2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
977 * wait for the pipe register state bit to turn off
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
984 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
989 enum pipe pipe
= crtc
->pipe
;
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1266 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1269 if (!intel_display_power_enabled(dev_priv
,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1273 reg
= PIPECONF(cpu_transcoder
);
1274 val
= I915_READ(reg
);
1275 cur_state
= !!(val
& PIPECONF_ENABLE
);
1278 WARN(cur_state
!= state
,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1283 static void assert_plane(struct drm_i915_private
*dev_priv
,
1284 enum plane plane
, bool state
)
1290 reg
= DSPCNTR(plane
);
1291 val
= I915_READ(reg
);
1292 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1293 WARN(cur_state
!= state
,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane
), state_string(state
), state_string(cur_state
));
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1301 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1304 struct drm_device
*dev
= dev_priv
->dev
;
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev
)->gen
>= 4) {
1311 reg
= DSPCNTR(pipe
);
1312 val
= I915_READ(reg
);
1313 WARN(val
& DISPLAY_PLANE_ENABLE
,
1314 "plane %c assertion failure, should be disabled but not\n",
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv
, i
) {
1322 val
= I915_READ(reg
);
1323 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1324 DISPPLANE_SEL_PIPE_SHIFT
;
1325 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i
), pipe_name(pipe
));
1331 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1334 struct drm_device
*dev
= dev_priv
->dev
;
1338 if (IS_VALLEYVIEW(dev
)) {
1339 for_each_sprite(pipe
, sprite
) {
1340 reg
= SPCNTR(pipe
, sprite
);
1341 val
= I915_READ(reg
);
1342 WARN(val
& SP_ENABLE
,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1346 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1348 val
= I915_READ(reg
);
1349 WARN(val
& SPRITE_ENABLE
,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe
), pipe_name(pipe
));
1352 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1353 reg
= DVSCNTR(pipe
);
1354 val
= I915_READ(reg
);
1355 WARN(val
& DVS_ENABLE
,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe
), pipe_name(pipe
));
1361 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1366 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1368 val
= I915_READ(PCH_DREF_CONTROL
);
1369 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1370 DREF_SUPERSPREAD_SOURCE_MASK
));
1371 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1374 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1381 reg
= PCH_TRANSCONF(pipe
);
1382 val
= I915_READ(reg
);
1383 enabled
= !!(val
& TRANS_ENABLE
);
1385 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1389 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1390 enum pipe pipe
, u32 port_sel
, u32 val
)
1392 if ((val
& DP_PORT_EN
) == 0)
1395 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1396 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1397 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1398 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1400 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1401 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1404 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1410 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1411 enum pipe pipe
, u32 val
)
1413 if ((val
& SDVO_ENABLE
) == 0)
1416 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1417 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1419 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1420 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1423 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1429 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1430 enum pipe pipe
, u32 val
)
1432 if ((val
& LVDS_PORT_EN
) == 0)
1435 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1436 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1439 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1445 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1446 enum pipe pipe
, u32 val
)
1448 if ((val
& ADPA_DAC_ENABLE
) == 0)
1450 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1451 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1454 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1460 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1461 enum pipe pipe
, int reg
, u32 port_sel
)
1463 u32 val
= I915_READ(reg
);
1464 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1465 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1466 reg
, pipe_name(pipe
));
1468 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1469 && (val
& DP_PIPEB_SELECT
),
1470 "IBX PCH dp port still using transcoder B\n");
1473 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1474 enum pipe pipe
, int reg
)
1476 u32 val
= I915_READ(reg
);
1477 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1478 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1479 reg
, pipe_name(pipe
));
1481 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1482 && (val
& SDVO_PIPE_B_SELECT
),
1483 "IBX PCH hdmi port still using transcoder B\n");
1486 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1492 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1493 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1494 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1497 val
= I915_READ(reg
);
1498 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1499 "PCH VGA enabled on transcoder %c, should be disabled\n",
1503 val
= I915_READ(reg
);
1504 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1505 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1508 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1509 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1510 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1513 static void intel_init_dpio(struct drm_device
*dev
)
1515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1517 if (!IS_VALLEYVIEW(dev
))
1521 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1522 * CHV x1 PHY (DP/HDMI D)
1523 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1525 if (IS_CHERRYVIEW(dev
)) {
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1527 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1529 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1533 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1535 struct drm_device
*dev
= crtc
->base
.dev
;
1536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1537 int reg
= DPLL(crtc
->pipe
);
1538 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1540 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1542 /* No really, not for ILK+ */
1543 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1545 /* PLL is protected by panel, make sure we can write it */
1546 if (IS_MOBILE(dev_priv
->dev
))
1547 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1549 I915_WRITE(reg
, dpll
);
1553 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1554 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1556 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1557 POSTING_READ(DPLL_MD(crtc
->pipe
));
1559 /* We do this three times for luck */
1560 I915_WRITE(reg
, dpll
);
1562 udelay(150); /* wait for warmup */
1563 I915_WRITE(reg
, dpll
);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg
, dpll
);
1568 udelay(150); /* wait for warmup */
1571 static void chv_enable_pll(struct intel_crtc
*crtc
)
1573 struct drm_device
*dev
= crtc
->base
.dev
;
1574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1575 int pipe
= crtc
->pipe
;
1576 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1579 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1581 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1583 mutex_lock(&dev_priv
->dpio_lock
);
1585 /* Enable back the 10bit clock to display controller */
1586 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1587 tmp
|= DPIO_DCLKP_EN
;
1588 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1591 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1596 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1598 /* Check PLL is locked */
1599 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1600 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1602 /* not sure when this should be written */
1603 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1604 POSTING_READ(DPLL_MD(pipe
));
1606 mutex_unlock(&dev_priv
->dpio_lock
);
1609 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1611 struct drm_device
*dev
= crtc
->base
.dev
;
1612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1613 int reg
= DPLL(crtc
->pipe
);
1614 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1616 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1618 /* No really, not for ILK+ */
1619 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1623 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1625 I915_WRITE(reg
, dpll
);
1627 /* Wait for the clocks to stabilize. */
1631 if (INTEL_INFO(dev
)->gen
>= 4) {
1632 I915_WRITE(DPLL_MD(crtc
->pipe
),
1633 crtc
->config
.dpll_hw_state
.dpll_md
);
1635 /* The pixel multiplier can only be updated once the
1636 * DPLL is enabled and the clocks are stable.
1638 * So write it again.
1640 I915_WRITE(reg
, dpll
);
1643 /* We do this three times for luck */
1644 I915_WRITE(reg
, dpll
);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg
, dpll
);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg
, dpll
);
1652 udelay(150); /* wait for warmup */
1656 * i9xx_disable_pll - disable a PLL
1657 * @dev_priv: i915 private structure
1658 * @pipe: pipe PLL to disable
1660 * Disable the PLL for @pipe, making sure the pipe is off first.
1662 * Note! This is for pre-ILK only.
1664 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1666 /* Don't disable pipe or pipe PLLs if needed */
1667 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1668 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv
, pipe
);
1674 I915_WRITE(DPLL(pipe
), 0);
1675 POSTING_READ(DPLL(pipe
));
1678 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1682 /* Make sure the pipe isn't still relying on us */
1683 assert_pipe_disabled(dev_priv
, pipe
);
1686 * Leave integrated clock source and reference clock enabled for pipe B.
1687 * The latter is needed for VGA hotplug / manual detection.
1690 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1691 I915_WRITE(DPLL(pipe
), val
);
1692 POSTING_READ(DPLL(pipe
));
1696 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1698 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1701 /* Make sure the pipe isn't still relying on us */
1702 assert_pipe_disabled(dev_priv
, pipe
);
1704 /* Set PLL en = 0 */
1705 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1707 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1708 I915_WRITE(DPLL(pipe
), val
);
1709 POSTING_READ(DPLL(pipe
));
1711 mutex_lock(&dev_priv
->dpio_lock
);
1713 /* Disable 10bit clock to display controller */
1714 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1715 val
&= ~DPIO_DCLKP_EN
;
1716 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1718 /* disable left/right clock distribution */
1719 if (pipe
!= PIPE_B
) {
1720 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1721 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1722 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1724 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1725 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1726 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1729 mutex_unlock(&dev_priv
->dpio_lock
);
1732 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1733 struct intel_digital_port
*dport
)
1738 switch (dport
->port
) {
1740 port_mask
= DPLL_PORTB_READY_MASK
;
1744 port_mask
= DPLL_PORTC_READY_MASK
;
1748 port_mask
= DPLL_PORTD_READY_MASK
;
1749 dpll_reg
= DPIO_PHY_STATUS
;
1755 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1756 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1757 port_name(dport
->port
), I915_READ(dpll_reg
));
1760 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1762 struct drm_device
*dev
= crtc
->base
.dev
;
1763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1764 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1766 if (WARN_ON(pll
== NULL
))
1769 WARN_ON(!pll
->refcount
);
1770 if (pll
->active
== 0) {
1771 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1773 assert_shared_dpll_disabled(dev_priv
, pll
);
1775 pll
->mode_set(dev_priv
, pll
);
1780 * intel_enable_shared_dpll - enable PCH PLL
1781 * @dev_priv: i915 private structure
1782 * @pipe: pipe PLL to enable
1784 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1785 * drives the transcoder clock.
1787 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1789 struct drm_device
*dev
= crtc
->base
.dev
;
1790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1791 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1793 if (WARN_ON(pll
== NULL
))
1796 if (WARN_ON(pll
->refcount
== 0))
1799 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1800 pll
->name
, pll
->active
, pll
->on
,
1801 crtc
->base
.base
.id
);
1803 if (pll
->active
++) {
1805 assert_shared_dpll_enabled(dev_priv
, pll
);
1810 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1812 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1813 pll
->enable(dev_priv
, pll
);
1817 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1819 struct drm_device
*dev
= crtc
->base
.dev
;
1820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1821 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1823 /* PCH only available on ILK+ */
1824 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1825 if (WARN_ON(pll
== NULL
))
1828 if (WARN_ON(pll
->refcount
== 0))
1831 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1832 pll
->name
, pll
->active
, pll
->on
,
1833 crtc
->base
.base
.id
);
1835 if (WARN_ON(pll
->active
== 0)) {
1836 assert_shared_dpll_disabled(dev_priv
, pll
);
1840 assert_shared_dpll_enabled(dev_priv
, pll
);
1845 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1846 pll
->disable(dev_priv
, pll
);
1849 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1852 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1855 struct drm_device
*dev
= dev_priv
->dev
;
1856 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1858 uint32_t reg
, val
, pipeconf_val
;
1860 /* PCH only available on ILK+ */
1861 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1863 /* Make sure PCH DPLL is enabled */
1864 assert_shared_dpll_enabled(dev_priv
,
1865 intel_crtc_to_shared_dpll(intel_crtc
));
1867 /* FDI must be feeding us bits for PCH ports */
1868 assert_fdi_tx_enabled(dev_priv
, pipe
);
1869 assert_fdi_rx_enabled(dev_priv
, pipe
);
1871 if (HAS_PCH_CPT(dev
)) {
1872 /* Workaround: Set the timing override bit before enabling the
1873 * pch transcoder. */
1874 reg
= TRANS_CHICKEN2(pipe
);
1875 val
= I915_READ(reg
);
1876 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1877 I915_WRITE(reg
, val
);
1880 reg
= PCH_TRANSCONF(pipe
);
1881 val
= I915_READ(reg
);
1882 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1884 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1886 * make the BPC in transcoder be consistent with
1887 * that in pipeconf reg.
1889 val
&= ~PIPECONF_BPC_MASK
;
1890 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1893 val
&= ~TRANS_INTERLACE_MASK
;
1894 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1895 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1896 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1897 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1899 val
|= TRANS_INTERLACED
;
1901 val
|= TRANS_PROGRESSIVE
;
1903 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1904 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1905 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1908 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1909 enum transcoder cpu_transcoder
)
1911 u32 val
, pipeconf_val
;
1913 /* PCH only available on ILK+ */
1914 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1916 /* FDI must be feeding us bits for PCH ports */
1917 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1918 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1920 /* Workaround: set timing override bit. */
1921 val
= I915_READ(_TRANSA_CHICKEN2
);
1922 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1923 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1926 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1928 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1929 PIPECONF_INTERLACED_ILK
)
1930 val
|= TRANS_INTERLACED
;
1932 val
|= TRANS_PROGRESSIVE
;
1934 I915_WRITE(LPT_TRANSCONF
, val
);
1935 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1936 DRM_ERROR("Failed to enable PCH transcoder\n");
1939 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1942 struct drm_device
*dev
= dev_priv
->dev
;
1945 /* FDI relies on the transcoder */
1946 assert_fdi_tx_disabled(dev_priv
, pipe
);
1947 assert_fdi_rx_disabled(dev_priv
, pipe
);
1949 /* Ports must be off as well */
1950 assert_pch_ports_disabled(dev_priv
, pipe
);
1952 reg
= PCH_TRANSCONF(pipe
);
1953 val
= I915_READ(reg
);
1954 val
&= ~TRANS_ENABLE
;
1955 I915_WRITE(reg
, val
);
1956 /* wait for PCH transcoder off, transcoder state */
1957 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1958 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1960 if (!HAS_PCH_IBX(dev
)) {
1961 /* Workaround: Clear the timing override chicken bit again. */
1962 reg
= TRANS_CHICKEN2(pipe
);
1963 val
= I915_READ(reg
);
1964 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1965 I915_WRITE(reg
, val
);
1969 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1973 val
= I915_READ(LPT_TRANSCONF
);
1974 val
&= ~TRANS_ENABLE
;
1975 I915_WRITE(LPT_TRANSCONF
, val
);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1978 DRM_ERROR("Failed to disable PCH transcoder\n");
1980 /* Workaround: clear timing override bit. */
1981 val
= I915_READ(_TRANSA_CHICKEN2
);
1982 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1983 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1987 * intel_enable_pipe - enable a pipe, asserting requirements
1988 * @crtc: crtc responsible for the pipe
1990 * Enable @crtc's pipe, making sure that various hardware specific requirements
1991 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1993 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1995 struct drm_device
*dev
= crtc
->base
.dev
;
1996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1997 enum pipe pipe
= crtc
->pipe
;
1998 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2000 enum pipe pch_transcoder
;
2004 assert_planes_disabled(dev_priv
, pipe
);
2005 assert_cursor_disabled(dev_priv
, pipe
);
2006 assert_sprites_disabled(dev_priv
, pipe
);
2008 if (HAS_PCH_LPT(dev_priv
->dev
))
2009 pch_transcoder
= TRANSCODER_A
;
2011 pch_transcoder
= pipe
;
2014 * A pipe without a PLL won't actually be able to drive bits from
2015 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2018 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2019 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2020 assert_dsi_pll_enabled(dev_priv
);
2022 assert_pll_enabled(dev_priv
, pipe
);
2024 if (crtc
->config
.has_pch_encoder
) {
2025 /* if driving the PCH, we need FDI enabled */
2026 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2027 assert_fdi_tx_pll_enabled(dev_priv
,
2028 (enum pipe
) cpu_transcoder
);
2030 /* FIXME: assert CPU port conditions for SNB+ */
2033 reg
= PIPECONF(cpu_transcoder
);
2034 val
= I915_READ(reg
);
2035 if (val
& PIPECONF_ENABLE
) {
2036 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2037 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2041 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2046 * intel_disable_pipe - disable a pipe, asserting requirements
2047 * @crtc: crtc whose pipes is to be disabled
2049 * Disable the pipe of @crtc, making sure that various hardware
2050 * specific requirements are met, if applicable, e.g. plane
2051 * disabled, panel fitter off, etc.
2053 * Will wait until the pipe has shut down before returning.
2055 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2057 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2058 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2059 enum pipe pipe
= crtc
->pipe
;
2064 * Make sure planes won't keep trying to pump pixels to us,
2065 * or we might hang the display.
2067 assert_planes_disabled(dev_priv
, pipe
);
2068 assert_cursor_disabled(dev_priv
, pipe
);
2069 assert_sprites_disabled(dev_priv
, pipe
);
2071 reg
= PIPECONF(cpu_transcoder
);
2072 val
= I915_READ(reg
);
2073 if ((val
& PIPECONF_ENABLE
) == 0)
2077 * Double wide has implications for planes
2078 * so best keep it disabled when not needed.
2080 if (crtc
->config
.double_wide
)
2081 val
&= ~PIPECONF_DOUBLE_WIDE
;
2083 /* Don't disable pipe or pipe PLLs if needed */
2084 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2085 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2086 val
&= ~PIPECONF_ENABLE
;
2088 I915_WRITE(reg
, val
);
2089 if ((val
& PIPECONF_ENABLE
) == 0)
2090 intel_wait_for_pipe_off(crtc
);
2094 * Plane regs are double buffered, going from enabled->disabled needs a
2095 * trigger in order to latch. The display address reg provides this.
2097 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2100 struct drm_device
*dev
= dev_priv
->dev
;
2101 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2103 I915_WRITE(reg
, I915_READ(reg
));
2108 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2109 * @plane: plane to be enabled
2110 * @crtc: crtc for the plane
2112 * Enable @plane on @crtc, making sure that the pipe is running first.
2114 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2115 struct drm_crtc
*crtc
)
2117 struct drm_device
*dev
= plane
->dev
;
2118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2119 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2121 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2122 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2124 if (intel_crtc
->primary_enabled
)
2127 intel_crtc
->primary_enabled
= true;
2129 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2133 * BDW signals flip done immediately if the plane
2134 * is disabled, even if the plane enable is already
2135 * armed to occur at the next vblank :(
2137 if (IS_BROADWELL(dev
))
2138 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2142 * intel_disable_primary_hw_plane - disable the primary hardware plane
2143 * @plane: plane to be disabled
2144 * @crtc: crtc for the plane
2146 * Disable @plane on @crtc, making sure that the pipe is running first.
2148 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2149 struct drm_crtc
*crtc
)
2151 struct drm_device
*dev
= plane
->dev
;
2152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2155 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2157 if (!intel_crtc
->primary_enabled
)
2160 intel_crtc
->primary_enabled
= false;
2162 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2166 static bool need_vtd_wa(struct drm_device
*dev
)
2168 #ifdef CONFIG_INTEL_IOMMU
2169 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2175 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2179 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2180 return ALIGN(height
, tile_height
);
2184 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2185 struct drm_i915_gem_object
*obj
,
2186 struct intel_engine_cs
*pipelined
)
2188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2194 switch (obj
->tiling_mode
) {
2195 case I915_TILING_NONE
:
2196 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2197 alignment
= 128 * 1024;
2198 else if (INTEL_INFO(dev
)->gen
>= 4)
2199 alignment
= 4 * 1024;
2201 alignment
= 64 * 1024;
2204 /* pin() will align the object as required by fence */
2208 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2214 /* Note that the w/a also requires 64 PTE of padding following the
2215 * bo. We currently fill all unused PTE with the shadow page and so
2216 * we should always have valid PTE following the scanout preventing
2219 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2220 alignment
= 256 * 1024;
2222 dev_priv
->mm
.interruptible
= false;
2223 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2225 goto err_interruptible
;
2227 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2228 * fence, whereas 965+ only requires a fence if using
2229 * framebuffer compression. For simplicity, we always install
2230 * a fence as the cost is not that onerous.
2232 ret
= i915_gem_object_get_fence(obj
);
2236 i915_gem_object_pin_fence(obj
);
2238 dev_priv
->mm
.interruptible
= true;
2242 i915_gem_object_unpin_from_display_plane(obj
);
2244 dev_priv
->mm
.interruptible
= true;
2248 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2250 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2252 i915_gem_object_unpin_fence(obj
);
2253 i915_gem_object_unpin_from_display_plane(obj
);
2256 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2257 * is assumed to be a power-of-two. */
2258 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2259 unsigned int tiling_mode
,
2263 if (tiling_mode
!= I915_TILING_NONE
) {
2264 unsigned int tile_rows
, tiles
;
2269 tiles
= *x
/ (512/cpp
);
2272 return tile_rows
* pitch
* 8 + tiles
* 4096;
2274 unsigned int offset
;
2276 offset
= *y
* pitch
+ *x
* cpp
;
2278 *x
= (offset
& 4095) / cpp
;
2279 return offset
& -4096;
2283 int intel_format_to_fourcc(int format
)
2286 case DISPPLANE_8BPP
:
2287 return DRM_FORMAT_C8
;
2288 case DISPPLANE_BGRX555
:
2289 return DRM_FORMAT_XRGB1555
;
2290 case DISPPLANE_BGRX565
:
2291 return DRM_FORMAT_RGB565
;
2293 case DISPPLANE_BGRX888
:
2294 return DRM_FORMAT_XRGB8888
;
2295 case DISPPLANE_RGBX888
:
2296 return DRM_FORMAT_XBGR8888
;
2297 case DISPPLANE_BGRX101010
:
2298 return DRM_FORMAT_XRGB2101010
;
2299 case DISPPLANE_RGBX101010
:
2300 return DRM_FORMAT_XBGR2101010
;
2304 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2305 struct intel_plane_config
*plane_config
)
2307 struct drm_device
*dev
= crtc
->base
.dev
;
2308 struct drm_i915_gem_object
*obj
= NULL
;
2309 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2310 u32 base
= plane_config
->base
;
2312 if (plane_config
->size
== 0)
2315 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2316 plane_config
->size
);
2320 if (plane_config
->tiled
) {
2321 obj
->tiling_mode
= I915_TILING_X
;
2322 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2325 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2326 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2327 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2328 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2330 mutex_lock(&dev
->struct_mutex
);
2332 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2334 DRM_DEBUG_KMS("intel fb init failed\n");
2338 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2339 mutex_unlock(&dev
->struct_mutex
);
2341 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2345 drm_gem_object_unreference(&obj
->base
);
2346 mutex_unlock(&dev
->struct_mutex
);
2350 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2351 struct intel_plane_config
*plane_config
)
2353 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2355 struct intel_crtc
*i
;
2356 struct drm_i915_gem_object
*obj
;
2358 if (!intel_crtc
->base
.primary
->fb
)
2361 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2364 kfree(intel_crtc
->base
.primary
->fb
);
2365 intel_crtc
->base
.primary
->fb
= NULL
;
2368 * Failed to alloc the obj, check to see if we should share
2369 * an fb with another CRTC instead
2371 for_each_crtc(dev
, c
) {
2372 i
= to_intel_crtc(c
);
2374 if (c
== &intel_crtc
->base
)
2380 obj
= intel_fb_obj(c
->primary
->fb
);
2384 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2385 drm_framebuffer_reference(c
->primary
->fb
);
2386 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2387 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2393 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2394 struct drm_framebuffer
*fb
,
2397 struct drm_device
*dev
= crtc
->dev
;
2398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2399 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2400 struct drm_i915_gem_object
*obj
;
2401 int plane
= intel_crtc
->plane
;
2402 unsigned long linear_offset
;
2404 u32 reg
= DSPCNTR(plane
);
2407 if (!intel_crtc
->primary_enabled
) {
2409 if (INTEL_INFO(dev
)->gen
>= 4)
2410 I915_WRITE(DSPSURF(plane
), 0);
2412 I915_WRITE(DSPADDR(plane
), 0);
2417 obj
= intel_fb_obj(fb
);
2418 if (WARN_ON(obj
== NULL
))
2421 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2423 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2425 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2427 if (INTEL_INFO(dev
)->gen
< 4) {
2428 if (intel_crtc
->pipe
== PIPE_B
)
2429 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2431 /* pipesrc and dspsize control the size that is scaled from,
2432 * which should always be the user's requested size.
2434 I915_WRITE(DSPSIZE(plane
),
2435 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2436 (intel_crtc
->config
.pipe_src_w
- 1));
2437 I915_WRITE(DSPPOS(plane
), 0);
2440 switch (fb
->pixel_format
) {
2442 dspcntr
|= DISPPLANE_8BPP
;
2444 case DRM_FORMAT_XRGB1555
:
2445 case DRM_FORMAT_ARGB1555
:
2446 dspcntr
|= DISPPLANE_BGRX555
;
2448 case DRM_FORMAT_RGB565
:
2449 dspcntr
|= DISPPLANE_BGRX565
;
2451 case DRM_FORMAT_XRGB8888
:
2452 case DRM_FORMAT_ARGB8888
:
2453 dspcntr
|= DISPPLANE_BGRX888
;
2455 case DRM_FORMAT_XBGR8888
:
2456 case DRM_FORMAT_ABGR8888
:
2457 dspcntr
|= DISPPLANE_RGBX888
;
2459 case DRM_FORMAT_XRGB2101010
:
2460 case DRM_FORMAT_ARGB2101010
:
2461 dspcntr
|= DISPPLANE_BGRX101010
;
2463 case DRM_FORMAT_XBGR2101010
:
2464 case DRM_FORMAT_ABGR2101010
:
2465 dspcntr
|= DISPPLANE_RGBX101010
;
2471 if (INTEL_INFO(dev
)->gen
>= 4 &&
2472 obj
->tiling_mode
!= I915_TILING_NONE
)
2473 dspcntr
|= DISPPLANE_TILED
;
2476 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2478 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2480 if (INTEL_INFO(dev
)->gen
>= 4) {
2481 intel_crtc
->dspaddr_offset
=
2482 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2485 linear_offset
-= intel_crtc
->dspaddr_offset
;
2487 intel_crtc
->dspaddr_offset
= linear_offset
;
2490 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2491 dspcntr
|= DISPPLANE_ROTATE_180
;
2493 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2494 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2496 /* Finding the last pixel of the last line of the display
2497 data and adding to linear_offset*/
2499 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2500 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2503 I915_WRITE(reg
, dspcntr
);
2505 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2506 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2508 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2509 if (INTEL_INFO(dev
)->gen
>= 4) {
2510 I915_WRITE(DSPSURF(plane
),
2511 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2512 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2513 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2515 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2519 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2520 struct drm_framebuffer
*fb
,
2523 struct drm_device
*dev
= crtc
->dev
;
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2525 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2526 struct drm_i915_gem_object
*obj
;
2527 int plane
= intel_crtc
->plane
;
2528 unsigned long linear_offset
;
2530 u32 reg
= DSPCNTR(plane
);
2533 if (!intel_crtc
->primary_enabled
) {
2535 I915_WRITE(DSPSURF(plane
), 0);
2540 obj
= intel_fb_obj(fb
);
2541 if (WARN_ON(obj
== NULL
))
2544 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2546 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2548 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2550 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2551 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2553 switch (fb
->pixel_format
) {
2555 dspcntr
|= DISPPLANE_8BPP
;
2557 case DRM_FORMAT_RGB565
:
2558 dspcntr
|= DISPPLANE_BGRX565
;
2560 case DRM_FORMAT_XRGB8888
:
2561 case DRM_FORMAT_ARGB8888
:
2562 dspcntr
|= DISPPLANE_BGRX888
;
2564 case DRM_FORMAT_XBGR8888
:
2565 case DRM_FORMAT_ABGR8888
:
2566 dspcntr
|= DISPPLANE_RGBX888
;
2568 case DRM_FORMAT_XRGB2101010
:
2569 case DRM_FORMAT_ARGB2101010
:
2570 dspcntr
|= DISPPLANE_BGRX101010
;
2572 case DRM_FORMAT_XBGR2101010
:
2573 case DRM_FORMAT_ABGR2101010
:
2574 dspcntr
|= DISPPLANE_RGBX101010
;
2580 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2581 dspcntr
|= DISPPLANE_TILED
;
2583 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2584 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2586 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2587 intel_crtc
->dspaddr_offset
=
2588 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2591 linear_offset
-= intel_crtc
->dspaddr_offset
;
2592 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2593 dspcntr
|= DISPPLANE_ROTATE_180
;
2595 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2596 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2597 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2599 /* Finding the last pixel of the last line of the display
2600 data and adding to linear_offset*/
2602 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2603 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2607 I915_WRITE(reg
, dspcntr
);
2609 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2610 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2612 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2613 I915_WRITE(DSPSURF(plane
),
2614 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2615 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2616 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2618 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2619 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2624 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2626 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2627 int x
, int y
, enum mode_set_atomic state
)
2629 struct drm_device
*dev
= crtc
->dev
;
2630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2632 if (dev_priv
->display
.disable_fbc
)
2633 dev_priv
->display
.disable_fbc(dev
);
2634 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2636 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2641 void intel_display_handle_reset(struct drm_device
*dev
)
2643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2644 struct drm_crtc
*crtc
;
2647 * Flips in the rings have been nuked by the reset,
2648 * so complete all pending flips so that user space
2649 * will get its events and not get stuck.
2651 * Also update the base address of all primary
2652 * planes to the the last fb to make sure we're
2653 * showing the correct fb after a reset.
2655 * Need to make two loops over the crtcs so that we
2656 * don't try to grab a crtc mutex before the
2657 * pending_flip_queue really got woken up.
2660 for_each_crtc(dev
, crtc
) {
2661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2662 enum plane plane
= intel_crtc
->plane
;
2664 intel_prepare_page_flip(dev
, plane
);
2665 intel_finish_page_flip_plane(dev
, plane
);
2668 for_each_crtc(dev
, crtc
) {
2669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2671 drm_modeset_lock(&crtc
->mutex
, NULL
);
2673 * FIXME: Once we have proper support for primary planes (and
2674 * disabling them without disabling the entire crtc) allow again
2675 * a NULL crtc->primary->fb.
2677 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2678 dev_priv
->display
.update_primary_plane(crtc
,
2682 drm_modeset_unlock(&crtc
->mutex
);
2687 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2689 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2690 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2691 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2694 /* Big Hammer, we also need to ensure that any pending
2695 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2696 * current scanout is retired before unpinning the old
2699 * This should only fail upon a hung GPU, in which case we
2700 * can safely continue.
2702 dev_priv
->mm
.interruptible
= false;
2703 ret
= i915_gem_object_finish_gpu(obj
);
2704 dev_priv
->mm
.interruptible
= was_interruptible
;
2709 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2711 struct drm_device
*dev
= crtc
->dev
;
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2714 unsigned long flags
;
2717 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2718 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2721 spin_lock_irqsave(&dev
->event_lock
, flags
);
2722 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2723 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2729 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2730 struct drm_framebuffer
*fb
)
2732 struct drm_device
*dev
= crtc
->dev
;
2733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2734 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2735 enum pipe pipe
= intel_crtc
->pipe
;
2736 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2737 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2738 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2741 if (intel_crtc_has_pending_flip(crtc
)) {
2742 DRM_ERROR("pipe is still busy with an old pageflip\n");
2748 DRM_ERROR("No FB bound\n");
2752 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2753 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2754 plane_name(intel_crtc
->plane
),
2755 INTEL_INFO(dev
)->num_pipes
);
2759 mutex_lock(&dev
->struct_mutex
);
2760 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2762 i915_gem_track_fb(old_obj
, obj
,
2763 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2764 mutex_unlock(&dev
->struct_mutex
);
2766 DRM_ERROR("pin & fence failed\n");
2771 * Update pipe size and adjust fitter if needed: the reason for this is
2772 * that in compute_mode_changes we check the native mode (not the pfit
2773 * mode) to see if we can flip rather than do a full mode set. In the
2774 * fastboot case, we'll flip, but if we don't update the pipesrc and
2775 * pfit state, we'll end up with a big fb scanned out into the wrong
2778 * To fix this properly, we need to hoist the checks up into
2779 * compute_mode_changes (or above), check the actual pfit state and
2780 * whether the platform allows pfit disable with pipe active, and only
2781 * then update the pipesrc and pfit state, even on the flip path.
2783 if (i915
.fastboot
) {
2784 const struct drm_display_mode
*adjusted_mode
=
2785 &intel_crtc
->config
.adjusted_mode
;
2787 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2788 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2789 (adjusted_mode
->crtc_vdisplay
- 1));
2790 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2791 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2792 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2793 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2794 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2795 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2797 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2798 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2801 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2803 if (intel_crtc
->active
)
2804 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2806 crtc
->primary
->fb
= fb
;
2811 if (intel_crtc
->active
&& old_fb
!= fb
)
2812 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2813 mutex_lock(&dev
->struct_mutex
);
2814 intel_unpin_fb_obj(old_obj
);
2815 mutex_unlock(&dev
->struct_mutex
);
2818 mutex_lock(&dev
->struct_mutex
);
2819 intel_update_fbc(dev
);
2820 mutex_unlock(&dev
->struct_mutex
);
2825 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2827 struct drm_device
*dev
= crtc
->dev
;
2828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2830 int pipe
= intel_crtc
->pipe
;
2833 /* enable normal train */
2834 reg
= FDI_TX_CTL(pipe
);
2835 temp
= I915_READ(reg
);
2836 if (IS_IVYBRIDGE(dev
)) {
2837 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2838 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2840 temp
&= ~FDI_LINK_TRAIN_NONE
;
2841 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2843 I915_WRITE(reg
, temp
);
2845 reg
= FDI_RX_CTL(pipe
);
2846 temp
= I915_READ(reg
);
2847 if (HAS_PCH_CPT(dev
)) {
2848 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2849 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2851 temp
&= ~FDI_LINK_TRAIN_NONE
;
2852 temp
|= FDI_LINK_TRAIN_NONE
;
2854 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2856 /* wait one idle pattern time */
2860 /* IVB wants error correction enabled */
2861 if (IS_IVYBRIDGE(dev
))
2862 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2863 FDI_FE_ERRC_ENABLE
);
2866 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2868 return crtc
->base
.enabled
&& crtc
->active
&&
2869 crtc
->config
.has_pch_encoder
;
2872 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2875 struct intel_crtc
*pipe_B_crtc
=
2876 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2877 struct intel_crtc
*pipe_C_crtc
=
2878 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2882 * When everything is off disable fdi C so that we could enable fdi B
2883 * with all lanes. Note that we don't care about enabled pipes without
2884 * an enabled pch encoder.
2886 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2887 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2888 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2889 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2891 temp
= I915_READ(SOUTH_CHICKEN1
);
2892 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2893 DRM_DEBUG_KMS("disabling fdi C rx\n");
2894 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2898 /* The FDI link training functions for ILK/Ibexpeak. */
2899 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2901 struct drm_device
*dev
= crtc
->dev
;
2902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2903 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2904 int pipe
= intel_crtc
->pipe
;
2905 u32 reg
, temp
, tries
;
2907 /* FDI needs bits from pipe first */
2908 assert_pipe_enabled(dev_priv
, pipe
);
2910 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2912 reg
= FDI_RX_IMR(pipe
);
2913 temp
= I915_READ(reg
);
2914 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2915 temp
&= ~FDI_RX_BIT_LOCK
;
2916 I915_WRITE(reg
, temp
);
2920 /* enable CPU FDI TX and PCH FDI RX */
2921 reg
= FDI_TX_CTL(pipe
);
2922 temp
= I915_READ(reg
);
2923 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2924 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2925 temp
&= ~FDI_LINK_TRAIN_NONE
;
2926 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2927 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2929 reg
= FDI_RX_CTL(pipe
);
2930 temp
= I915_READ(reg
);
2931 temp
&= ~FDI_LINK_TRAIN_NONE
;
2932 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2933 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2938 /* Ironlake workaround, enable clock pointer after FDI enable*/
2939 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2940 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2941 FDI_RX_PHASE_SYNC_POINTER_EN
);
2943 reg
= FDI_RX_IIR(pipe
);
2944 for (tries
= 0; tries
< 5; tries
++) {
2945 temp
= I915_READ(reg
);
2946 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2948 if ((temp
& FDI_RX_BIT_LOCK
)) {
2949 DRM_DEBUG_KMS("FDI train 1 done.\n");
2950 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2955 DRM_ERROR("FDI train 1 fail!\n");
2958 reg
= FDI_TX_CTL(pipe
);
2959 temp
= I915_READ(reg
);
2960 temp
&= ~FDI_LINK_TRAIN_NONE
;
2961 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2962 I915_WRITE(reg
, temp
);
2964 reg
= FDI_RX_CTL(pipe
);
2965 temp
= I915_READ(reg
);
2966 temp
&= ~FDI_LINK_TRAIN_NONE
;
2967 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2968 I915_WRITE(reg
, temp
);
2973 reg
= FDI_RX_IIR(pipe
);
2974 for (tries
= 0; tries
< 5; tries
++) {
2975 temp
= I915_READ(reg
);
2976 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2978 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2979 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2980 DRM_DEBUG_KMS("FDI train 2 done.\n");
2985 DRM_ERROR("FDI train 2 fail!\n");
2987 DRM_DEBUG_KMS("FDI train done\n");
2991 static const int snb_b_fdi_train_param
[] = {
2992 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2993 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2994 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2995 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2998 /* The FDI link training functions for SNB/Cougarpoint. */
2999 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3001 struct drm_device
*dev
= crtc
->dev
;
3002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3004 int pipe
= intel_crtc
->pipe
;
3005 u32 reg
, temp
, i
, retry
;
3007 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3009 reg
= FDI_RX_IMR(pipe
);
3010 temp
= I915_READ(reg
);
3011 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3012 temp
&= ~FDI_RX_BIT_LOCK
;
3013 I915_WRITE(reg
, temp
);
3018 /* enable CPU FDI TX and PCH FDI RX */
3019 reg
= FDI_TX_CTL(pipe
);
3020 temp
= I915_READ(reg
);
3021 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3022 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3023 temp
&= ~FDI_LINK_TRAIN_NONE
;
3024 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3025 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3027 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3028 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3030 I915_WRITE(FDI_RX_MISC(pipe
),
3031 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3033 reg
= FDI_RX_CTL(pipe
);
3034 temp
= I915_READ(reg
);
3035 if (HAS_PCH_CPT(dev
)) {
3036 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3037 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3039 temp
&= ~FDI_LINK_TRAIN_NONE
;
3040 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3042 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3047 for (i
= 0; i
< 4; i
++) {
3048 reg
= FDI_TX_CTL(pipe
);
3049 temp
= I915_READ(reg
);
3050 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3051 temp
|= snb_b_fdi_train_param
[i
];
3052 I915_WRITE(reg
, temp
);
3057 for (retry
= 0; retry
< 5; retry
++) {
3058 reg
= FDI_RX_IIR(pipe
);
3059 temp
= I915_READ(reg
);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3061 if (temp
& FDI_RX_BIT_LOCK
) {
3062 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3063 DRM_DEBUG_KMS("FDI train 1 done.\n");
3072 DRM_ERROR("FDI train 1 fail!\n");
3075 reg
= FDI_TX_CTL(pipe
);
3076 temp
= I915_READ(reg
);
3077 temp
&= ~FDI_LINK_TRAIN_NONE
;
3078 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3080 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3082 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3084 I915_WRITE(reg
, temp
);
3086 reg
= FDI_RX_CTL(pipe
);
3087 temp
= I915_READ(reg
);
3088 if (HAS_PCH_CPT(dev
)) {
3089 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3090 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3092 temp
&= ~FDI_LINK_TRAIN_NONE
;
3093 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3095 I915_WRITE(reg
, temp
);
3100 for (i
= 0; i
< 4; i
++) {
3101 reg
= FDI_TX_CTL(pipe
);
3102 temp
= I915_READ(reg
);
3103 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3104 temp
|= snb_b_fdi_train_param
[i
];
3105 I915_WRITE(reg
, temp
);
3110 for (retry
= 0; retry
< 5; retry
++) {
3111 reg
= FDI_RX_IIR(pipe
);
3112 temp
= I915_READ(reg
);
3113 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3114 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3115 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3116 DRM_DEBUG_KMS("FDI train 2 done.\n");
3125 DRM_ERROR("FDI train 2 fail!\n");
3127 DRM_DEBUG_KMS("FDI train done.\n");
3130 /* Manual link training for Ivy Bridge A0 parts */
3131 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3133 struct drm_device
*dev
= crtc
->dev
;
3134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3136 int pipe
= intel_crtc
->pipe
;
3137 u32 reg
, temp
, i
, j
;
3139 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3141 reg
= FDI_RX_IMR(pipe
);
3142 temp
= I915_READ(reg
);
3143 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3144 temp
&= ~FDI_RX_BIT_LOCK
;
3145 I915_WRITE(reg
, temp
);
3150 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3151 I915_READ(FDI_RX_IIR(pipe
)));
3153 /* Try each vswing and preemphasis setting twice before moving on */
3154 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3155 /* disable first in case we need to retry */
3156 reg
= FDI_TX_CTL(pipe
);
3157 temp
= I915_READ(reg
);
3158 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3159 temp
&= ~FDI_TX_ENABLE
;
3160 I915_WRITE(reg
, temp
);
3162 reg
= FDI_RX_CTL(pipe
);
3163 temp
= I915_READ(reg
);
3164 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3165 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3166 temp
&= ~FDI_RX_ENABLE
;
3167 I915_WRITE(reg
, temp
);
3169 /* enable CPU FDI TX and PCH FDI RX */
3170 reg
= FDI_TX_CTL(pipe
);
3171 temp
= I915_READ(reg
);
3172 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3173 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3174 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3175 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3176 temp
|= snb_b_fdi_train_param
[j
/2];
3177 temp
|= FDI_COMPOSITE_SYNC
;
3178 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3180 I915_WRITE(FDI_RX_MISC(pipe
),
3181 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3183 reg
= FDI_RX_CTL(pipe
);
3184 temp
= I915_READ(reg
);
3185 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3186 temp
|= FDI_COMPOSITE_SYNC
;
3187 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3190 udelay(1); /* should be 0.5us */
3192 for (i
= 0; i
< 4; i
++) {
3193 reg
= FDI_RX_IIR(pipe
);
3194 temp
= I915_READ(reg
);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3197 if (temp
& FDI_RX_BIT_LOCK
||
3198 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3199 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3200 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3204 udelay(1); /* should be 0.5us */
3207 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3212 reg
= FDI_TX_CTL(pipe
);
3213 temp
= I915_READ(reg
);
3214 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3215 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3216 I915_WRITE(reg
, temp
);
3218 reg
= FDI_RX_CTL(pipe
);
3219 temp
= I915_READ(reg
);
3220 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3221 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3222 I915_WRITE(reg
, temp
);
3225 udelay(2); /* should be 1.5us */
3227 for (i
= 0; i
< 4; i
++) {
3228 reg
= FDI_RX_IIR(pipe
);
3229 temp
= I915_READ(reg
);
3230 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3232 if (temp
& FDI_RX_SYMBOL_LOCK
||
3233 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3234 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3235 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3239 udelay(2); /* should be 1.5us */
3242 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3246 DRM_DEBUG_KMS("FDI train done.\n");
3249 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3251 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3253 int pipe
= intel_crtc
->pipe
;
3257 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3258 reg
= FDI_RX_CTL(pipe
);
3259 temp
= I915_READ(reg
);
3260 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3261 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3262 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3263 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3268 /* Switch from Rawclk to PCDclk */
3269 temp
= I915_READ(reg
);
3270 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3275 /* Enable CPU FDI TX PLL, always on for Ironlake */
3276 reg
= FDI_TX_CTL(pipe
);
3277 temp
= I915_READ(reg
);
3278 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3279 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3286 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3288 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3289 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3290 int pipe
= intel_crtc
->pipe
;
3293 /* Switch from PCDclk to Rawclk */
3294 reg
= FDI_RX_CTL(pipe
);
3295 temp
= I915_READ(reg
);
3296 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3298 /* Disable CPU FDI TX PLL */
3299 reg
= FDI_TX_CTL(pipe
);
3300 temp
= I915_READ(reg
);
3301 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3306 reg
= FDI_RX_CTL(pipe
);
3307 temp
= I915_READ(reg
);
3308 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3310 /* Wait for the clocks to turn off. */
3315 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3317 struct drm_device
*dev
= crtc
->dev
;
3318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3319 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3320 int pipe
= intel_crtc
->pipe
;
3323 /* disable CPU FDI tx and PCH FDI rx */
3324 reg
= FDI_TX_CTL(pipe
);
3325 temp
= I915_READ(reg
);
3326 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3329 reg
= FDI_RX_CTL(pipe
);
3330 temp
= I915_READ(reg
);
3331 temp
&= ~(0x7 << 16);
3332 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3333 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3338 /* Ironlake workaround, disable clock pointer after downing FDI */
3339 if (HAS_PCH_IBX(dev
))
3340 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3342 /* still set train pattern 1 */
3343 reg
= FDI_TX_CTL(pipe
);
3344 temp
= I915_READ(reg
);
3345 temp
&= ~FDI_LINK_TRAIN_NONE
;
3346 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3347 I915_WRITE(reg
, temp
);
3349 reg
= FDI_RX_CTL(pipe
);
3350 temp
= I915_READ(reg
);
3351 if (HAS_PCH_CPT(dev
)) {
3352 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3353 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3355 temp
&= ~FDI_LINK_TRAIN_NONE
;
3356 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3358 /* BPC in FDI rx is consistent with that in PIPECONF */
3359 temp
&= ~(0x07 << 16);
3360 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3361 I915_WRITE(reg
, temp
);
3367 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3369 struct intel_crtc
*crtc
;
3371 /* Note that we don't need to be called with mode_config.lock here
3372 * as our list of CRTC objects is static for the lifetime of the
3373 * device and so cannot disappear as we iterate. Similarly, we can
3374 * happily treat the predicates as racy, atomic checks as userspace
3375 * cannot claim and pin a new fb without at least acquring the
3376 * struct_mutex and so serialising with us.
3378 for_each_intel_crtc(dev
, crtc
) {
3379 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3382 if (crtc
->unpin_work
)
3383 intel_wait_for_vblank(dev
, crtc
->pipe
);
3391 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3393 struct drm_device
*dev
= crtc
->dev
;
3394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3396 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3397 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3398 !intel_crtc_has_pending_flip(crtc
),
3401 if (crtc
->primary
->fb
) {
3402 mutex_lock(&dev
->struct_mutex
);
3403 intel_finish_fb(crtc
->primary
->fb
);
3404 mutex_unlock(&dev
->struct_mutex
);
3408 /* Program iCLKIP clock to the desired frequency */
3409 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3411 struct drm_device
*dev
= crtc
->dev
;
3412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3413 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3414 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3417 mutex_lock(&dev_priv
->dpio_lock
);
3419 /* It is necessary to ungate the pixclk gate prior to programming
3420 * the divisors, and gate it back when it is done.
3422 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3424 /* Disable SSCCTL */
3425 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3426 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3430 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3431 if (clock
== 20000) {
3436 /* The iCLK virtual clock root frequency is in MHz,
3437 * but the adjusted_mode->crtc_clock in in KHz. To get the
3438 * divisors, it is necessary to divide one by another, so we
3439 * convert the virtual clock precision to KHz here for higher
3442 u32 iclk_virtual_root_freq
= 172800 * 1000;
3443 u32 iclk_pi_range
= 64;
3444 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3446 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3447 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3448 pi_value
= desired_divisor
% iclk_pi_range
;
3451 divsel
= msb_divisor_value
- 2;
3452 phaseinc
= pi_value
;
3455 /* This should not happen with any sane values */
3456 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3457 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3458 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3459 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3461 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3468 /* Program SSCDIVINTPHASE6 */
3469 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3470 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3471 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3472 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3473 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3474 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3475 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3476 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3478 /* Program SSCAUXDIV */
3479 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3480 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3481 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3482 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3484 /* Enable modulator and associated divider */
3485 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3486 temp
&= ~SBI_SSCCTL_DISABLE
;
3487 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3489 /* Wait for initialization time */
3492 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3494 mutex_unlock(&dev_priv
->dpio_lock
);
3497 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3498 enum pipe pch_transcoder
)
3500 struct drm_device
*dev
= crtc
->base
.dev
;
3501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3502 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3504 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3505 I915_READ(HTOTAL(cpu_transcoder
)));
3506 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3507 I915_READ(HBLANK(cpu_transcoder
)));
3508 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3509 I915_READ(HSYNC(cpu_transcoder
)));
3511 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3512 I915_READ(VTOTAL(cpu_transcoder
)));
3513 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3514 I915_READ(VBLANK(cpu_transcoder
)));
3515 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3516 I915_READ(VSYNC(cpu_transcoder
)));
3517 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3518 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3521 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3526 temp
= I915_READ(SOUTH_CHICKEN1
);
3527 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3530 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3531 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3533 temp
|= FDI_BC_BIFURCATION_SELECT
;
3534 DRM_DEBUG_KMS("enabling fdi C rx\n");
3535 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3536 POSTING_READ(SOUTH_CHICKEN1
);
3539 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3541 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3544 switch (intel_crtc
->pipe
) {
3548 if (intel_crtc
->config
.fdi_lanes
> 2)
3549 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3551 cpt_enable_fdi_bc_bifurcation(dev
);
3555 cpt_enable_fdi_bc_bifurcation(dev
);
3564 * Enable PCH resources required for PCH ports:
3566 * - FDI training & RX/TX
3567 * - update transcoder timings
3568 * - DP transcoding bits
3571 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3573 struct drm_device
*dev
= crtc
->dev
;
3574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3575 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3576 int pipe
= intel_crtc
->pipe
;
3579 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3581 if (IS_IVYBRIDGE(dev
))
3582 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3584 /* Write the TU size bits before fdi link training, so that error
3585 * detection works. */
3586 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3587 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3589 /* For PCH output, training FDI link */
3590 dev_priv
->display
.fdi_link_train(crtc
);
3592 /* We need to program the right clock selection before writing the pixel
3593 * mutliplier into the DPLL. */
3594 if (HAS_PCH_CPT(dev
)) {
3597 temp
= I915_READ(PCH_DPLL_SEL
);
3598 temp
|= TRANS_DPLL_ENABLE(pipe
);
3599 sel
= TRANS_DPLLB_SEL(pipe
);
3600 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3604 I915_WRITE(PCH_DPLL_SEL
, temp
);
3607 /* XXX: pch pll's can be enabled any time before we enable the PCH
3608 * transcoder, and we actually should do this to not upset any PCH
3609 * transcoder that already use the clock when we share it.
3611 * Note that enable_shared_dpll tries to do the right thing, but
3612 * get_shared_dpll unconditionally resets the pll - we need that to have
3613 * the right LVDS enable sequence. */
3614 intel_enable_shared_dpll(intel_crtc
);
3616 /* set transcoder timing, panel must allow it */
3617 assert_panel_unlocked(dev_priv
, pipe
);
3618 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3620 intel_fdi_normal_train(crtc
);
3622 /* For PCH DP, enable TRANS_DP_CTL */
3623 if (HAS_PCH_CPT(dev
) &&
3624 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3625 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3626 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3627 reg
= TRANS_DP_CTL(pipe
);
3628 temp
= I915_READ(reg
);
3629 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3630 TRANS_DP_SYNC_MASK
|
3632 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3633 TRANS_DP_ENH_FRAMING
);
3634 temp
|= bpc
<< 9; /* same format but at 11:9 */
3636 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3637 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3638 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3639 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3641 switch (intel_trans_dp_port_sel(crtc
)) {
3643 temp
|= TRANS_DP_PORT_SEL_B
;
3646 temp
|= TRANS_DP_PORT_SEL_C
;
3649 temp
|= TRANS_DP_PORT_SEL_D
;
3655 I915_WRITE(reg
, temp
);
3658 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3661 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3663 struct drm_device
*dev
= crtc
->dev
;
3664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3666 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3668 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3670 lpt_program_iclkip(crtc
);
3672 /* Set transcoder timing. */
3673 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3675 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3678 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3680 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3685 if (pll
->refcount
== 0) {
3686 WARN(1, "bad %s refcount\n", pll
->name
);
3690 if (--pll
->refcount
== 0) {
3692 WARN_ON(pll
->active
);
3695 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3698 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3700 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3701 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3702 enum intel_dpll_id i
;
3705 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3706 crtc
->base
.base
.id
, pll
->name
);
3707 intel_put_shared_dpll(crtc
);
3710 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3711 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3712 i
= (enum intel_dpll_id
) crtc
->pipe
;
3713 pll
= &dev_priv
->shared_dplls
[i
];
3715 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3716 crtc
->base
.base
.id
, pll
->name
);
3718 WARN_ON(pll
->refcount
);
3723 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3724 pll
= &dev_priv
->shared_dplls
[i
];
3726 /* Only want to check enabled timings first */
3727 if (pll
->refcount
== 0)
3730 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3731 sizeof(pll
->hw_state
)) == 0) {
3732 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3734 pll
->name
, pll
->refcount
, pll
->active
);
3740 /* Ok no matching timings, maybe there's a free one? */
3741 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3742 pll
= &dev_priv
->shared_dplls
[i
];
3743 if (pll
->refcount
== 0) {
3744 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3745 crtc
->base
.base
.id
, pll
->name
);
3753 if (pll
->refcount
== 0)
3754 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3756 crtc
->config
.shared_dpll
= i
;
3757 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3758 pipe_name(crtc
->pipe
));
3765 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3768 int dslreg
= PIPEDSL(pipe
);
3771 temp
= I915_READ(dslreg
);
3773 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3774 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3775 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3779 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3781 struct drm_device
*dev
= crtc
->base
.dev
;
3782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3783 int pipe
= crtc
->pipe
;
3785 if (crtc
->config
.pch_pfit
.enabled
) {
3786 /* Force use of hard-coded filter coefficients
3787 * as some pre-programmed values are broken,
3790 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3791 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3792 PF_PIPE_SEL_IVB(pipe
));
3794 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3795 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3796 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3800 static void intel_enable_planes(struct drm_crtc
*crtc
)
3802 struct drm_device
*dev
= crtc
->dev
;
3803 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3804 struct drm_plane
*plane
;
3805 struct intel_plane
*intel_plane
;
3807 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3808 intel_plane
= to_intel_plane(plane
);
3809 if (intel_plane
->pipe
== pipe
)
3810 intel_plane_restore(&intel_plane
->base
);
3814 static void intel_disable_planes(struct drm_crtc
*crtc
)
3816 struct drm_device
*dev
= crtc
->dev
;
3817 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3818 struct drm_plane
*plane
;
3819 struct intel_plane
*intel_plane
;
3821 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3822 intel_plane
= to_intel_plane(plane
);
3823 if (intel_plane
->pipe
== pipe
)
3824 intel_plane_disable(&intel_plane
->base
);
3828 void hsw_enable_ips(struct intel_crtc
*crtc
)
3830 struct drm_device
*dev
= crtc
->base
.dev
;
3831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3833 if (!crtc
->config
.ips_enabled
)
3836 /* We can only enable IPS after we enable a plane and wait for a vblank */
3837 intel_wait_for_vblank(dev
, crtc
->pipe
);
3839 assert_plane_enabled(dev_priv
, crtc
->plane
);
3840 if (IS_BROADWELL(dev
)) {
3841 mutex_lock(&dev_priv
->rps
.hw_lock
);
3842 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3843 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3844 /* Quoting Art Runyan: "its not safe to expect any particular
3845 * value in IPS_CTL bit 31 after enabling IPS through the
3846 * mailbox." Moreover, the mailbox may return a bogus state,
3847 * so we need to just enable it and continue on.
3850 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3851 /* The bit only becomes 1 in the next vblank, so this wait here
3852 * is essentially intel_wait_for_vblank. If we don't have this
3853 * and don't wait for vblanks until the end of crtc_enable, then
3854 * the HW state readout code will complain that the expected
3855 * IPS_CTL value is not the one we read. */
3856 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3857 DRM_ERROR("Timed out waiting for IPS enable\n");
3861 void hsw_disable_ips(struct intel_crtc
*crtc
)
3863 struct drm_device
*dev
= crtc
->base
.dev
;
3864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3866 if (!crtc
->config
.ips_enabled
)
3869 assert_plane_enabled(dev_priv
, crtc
->plane
);
3870 if (IS_BROADWELL(dev
)) {
3871 mutex_lock(&dev_priv
->rps
.hw_lock
);
3872 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3873 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3874 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3875 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3876 DRM_ERROR("Timed out waiting for IPS disable\n");
3878 I915_WRITE(IPS_CTL
, 0);
3879 POSTING_READ(IPS_CTL
);
3882 /* We need to wait for a vblank before we can disable the plane. */
3883 intel_wait_for_vblank(dev
, crtc
->pipe
);
3886 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3887 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3889 struct drm_device
*dev
= crtc
->dev
;
3890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3891 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3892 enum pipe pipe
= intel_crtc
->pipe
;
3893 int palreg
= PALETTE(pipe
);
3895 bool reenable_ips
= false;
3897 /* The clocks have to be on to load the palette. */
3898 if (!crtc
->enabled
|| !intel_crtc
->active
)
3901 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3902 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3903 assert_dsi_pll_enabled(dev_priv
);
3905 assert_pll_enabled(dev_priv
, pipe
);
3908 /* use legacy palette for Ironlake */
3909 if (!HAS_GMCH_DISPLAY(dev
))
3910 palreg
= LGC_PALETTE(pipe
);
3912 /* Workaround : Do not read or write the pipe palette/gamma data while
3913 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3915 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3916 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3917 GAMMA_MODE_MODE_SPLIT
)) {
3918 hsw_disable_ips(intel_crtc
);
3919 reenable_ips
= true;
3922 for (i
= 0; i
< 256; i
++) {
3923 I915_WRITE(palreg
+ 4 * i
,
3924 (intel_crtc
->lut_r
[i
] << 16) |
3925 (intel_crtc
->lut_g
[i
] << 8) |
3926 intel_crtc
->lut_b
[i
]);
3930 hsw_enable_ips(intel_crtc
);
3933 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3935 if (!enable
&& intel_crtc
->overlay
) {
3936 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3939 mutex_lock(&dev
->struct_mutex
);
3940 dev_priv
->mm
.interruptible
= false;
3941 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3942 dev_priv
->mm
.interruptible
= true;
3943 mutex_unlock(&dev
->struct_mutex
);
3946 /* Let userspace switch the overlay on again. In most cases userspace
3947 * has to recompute where to put it anyway.
3951 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3953 struct drm_device
*dev
= crtc
->dev
;
3954 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3955 int pipe
= intel_crtc
->pipe
;
3957 drm_vblank_on(dev
, pipe
);
3959 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
3960 intel_enable_planes(crtc
);
3961 intel_crtc_update_cursor(crtc
, true);
3962 intel_crtc_dpms_overlay(intel_crtc
, true);
3964 hsw_enable_ips(intel_crtc
);
3966 mutex_lock(&dev
->struct_mutex
);
3967 intel_update_fbc(dev
);
3968 mutex_unlock(&dev
->struct_mutex
);
3971 * FIXME: Once we grow proper nuclear flip support out of this we need
3972 * to compute the mask of flip planes precisely. For the time being
3973 * consider this a flip from a NULL plane.
3975 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3978 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3980 struct drm_device
*dev
= crtc
->dev
;
3981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3982 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3983 int pipe
= intel_crtc
->pipe
;
3984 int plane
= intel_crtc
->plane
;
3986 intel_crtc_wait_for_pending_flips(crtc
);
3988 if (dev_priv
->fbc
.plane
== plane
)
3989 intel_disable_fbc(dev
);
3991 hsw_disable_ips(intel_crtc
);
3993 intel_crtc_dpms_overlay(intel_crtc
, false);
3994 intel_crtc_update_cursor(crtc
, false);
3995 intel_disable_planes(crtc
);
3996 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
3999 * FIXME: Once we grow proper nuclear flip support out of this we need
4000 * to compute the mask of flip planes precisely. For the time being
4001 * consider this a flip to a NULL plane.
4003 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4005 drm_vblank_off(dev
, pipe
);
4008 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4010 struct drm_device
*dev
= crtc
->dev
;
4011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4013 struct intel_encoder
*encoder
;
4014 int pipe
= intel_crtc
->pipe
;
4016 WARN_ON(!crtc
->enabled
);
4018 if (intel_crtc
->active
)
4021 if (intel_crtc
->config
.has_pch_encoder
)
4022 intel_prepare_shared_dpll(intel_crtc
);
4024 if (intel_crtc
->config
.has_dp_encoder
)
4025 intel_dp_set_m_n(intel_crtc
);
4027 intel_set_pipe_timings(intel_crtc
);
4029 if (intel_crtc
->config
.has_pch_encoder
) {
4030 intel_cpu_transcoder_set_m_n(intel_crtc
,
4031 &intel_crtc
->config
.fdi_m_n
, NULL
);
4034 ironlake_set_pipeconf(crtc
);
4036 intel_crtc
->active
= true;
4038 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4039 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4041 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4042 if (encoder
->pre_enable
)
4043 encoder
->pre_enable(encoder
);
4045 if (intel_crtc
->config
.has_pch_encoder
) {
4046 /* Note: FDI PLL enabling _must_ be done before we enable the
4047 * cpu pipes, hence this is separate from all the other fdi/pch
4049 ironlake_fdi_pll_enable(intel_crtc
);
4051 assert_fdi_tx_disabled(dev_priv
, pipe
);
4052 assert_fdi_rx_disabled(dev_priv
, pipe
);
4055 ironlake_pfit_enable(intel_crtc
);
4058 * On ILK+ LUT must be loaded before the pipe is running but with
4061 intel_crtc_load_lut(crtc
);
4063 intel_update_watermarks(crtc
);
4064 intel_enable_pipe(intel_crtc
);
4066 if (intel_crtc
->config
.has_pch_encoder
)
4067 ironlake_pch_enable(crtc
);
4069 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4070 encoder
->enable(encoder
);
4072 if (HAS_PCH_CPT(dev
))
4073 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4075 intel_crtc_enable_planes(crtc
);
4078 /* IPS only exists on ULT machines and is tied to pipe A. */
4079 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4081 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4085 * This implements the workaround described in the "notes" section of the mode
4086 * set sequence documentation. When going from no pipes or single pipe to
4087 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4088 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4090 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4092 struct drm_device
*dev
= crtc
->base
.dev
;
4093 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4095 /* We want to get the other_active_crtc only if there's only 1 other
4097 for_each_intel_crtc(dev
, crtc_it
) {
4098 if (!crtc_it
->active
|| crtc_it
== crtc
)
4101 if (other_active_crtc
)
4104 other_active_crtc
= crtc_it
;
4106 if (!other_active_crtc
)
4109 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4110 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4113 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4115 struct drm_device
*dev
= crtc
->dev
;
4116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4118 struct intel_encoder
*encoder
;
4119 int pipe
= intel_crtc
->pipe
;
4121 WARN_ON(!crtc
->enabled
);
4123 if (intel_crtc
->active
)
4126 if (intel_crtc_to_shared_dpll(intel_crtc
))
4127 intel_enable_shared_dpll(intel_crtc
);
4129 if (intel_crtc
->config
.has_dp_encoder
)
4130 intel_dp_set_m_n(intel_crtc
);
4132 intel_set_pipe_timings(intel_crtc
);
4134 if (intel_crtc
->config
.has_pch_encoder
) {
4135 intel_cpu_transcoder_set_m_n(intel_crtc
,
4136 &intel_crtc
->config
.fdi_m_n
, NULL
);
4139 haswell_set_pipeconf(crtc
);
4141 intel_set_pipe_csc(crtc
);
4143 intel_crtc
->active
= true;
4145 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4146 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4147 if (encoder
->pre_enable
)
4148 encoder
->pre_enable(encoder
);
4150 if (intel_crtc
->config
.has_pch_encoder
) {
4151 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4152 dev_priv
->display
.fdi_link_train(crtc
);
4155 intel_ddi_enable_pipe_clock(intel_crtc
);
4157 ironlake_pfit_enable(intel_crtc
);
4160 * On ILK+ LUT must be loaded before the pipe is running but with
4163 intel_crtc_load_lut(crtc
);
4165 intel_ddi_set_pipe_settings(crtc
);
4166 intel_ddi_enable_transcoder_func(crtc
);
4168 intel_update_watermarks(crtc
);
4169 intel_enable_pipe(intel_crtc
);
4171 if (intel_crtc
->config
.has_pch_encoder
)
4172 lpt_pch_enable(crtc
);
4174 if (intel_crtc
->config
.dp_encoder_is_mst
)
4175 intel_ddi_set_vc_payload_alloc(crtc
, true);
4177 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4178 encoder
->enable(encoder
);
4179 intel_opregion_notify_encoder(encoder
, true);
4182 /* If we change the relative order between pipe/planes enabling, we need
4183 * to change the workaround. */
4184 haswell_mode_set_planes_workaround(intel_crtc
);
4185 intel_crtc_enable_planes(crtc
);
4188 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4190 struct drm_device
*dev
= crtc
->base
.dev
;
4191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4192 int pipe
= crtc
->pipe
;
4194 /* To avoid upsetting the power well on haswell only disable the pfit if
4195 * it's in use. The hw state code will make sure we get this right. */
4196 if (crtc
->config
.pch_pfit
.enabled
) {
4197 I915_WRITE(PF_CTL(pipe
), 0);
4198 I915_WRITE(PF_WIN_POS(pipe
), 0);
4199 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4203 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4205 struct drm_device
*dev
= crtc
->dev
;
4206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4207 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4208 struct intel_encoder
*encoder
;
4209 int pipe
= intel_crtc
->pipe
;
4212 if (!intel_crtc
->active
)
4215 intel_crtc_disable_planes(crtc
);
4217 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4218 encoder
->disable(encoder
);
4220 if (intel_crtc
->config
.has_pch_encoder
)
4221 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4223 intel_disable_pipe(intel_crtc
);
4225 if (intel_crtc
->config
.dp_encoder_is_mst
)
4226 intel_ddi_set_vc_payload_alloc(crtc
, false);
4228 ironlake_pfit_disable(intel_crtc
);
4230 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4231 if (encoder
->post_disable
)
4232 encoder
->post_disable(encoder
);
4234 if (intel_crtc
->config
.has_pch_encoder
) {
4235 ironlake_fdi_disable(crtc
);
4237 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4238 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4240 if (HAS_PCH_CPT(dev
)) {
4241 /* disable TRANS_DP_CTL */
4242 reg
= TRANS_DP_CTL(pipe
);
4243 temp
= I915_READ(reg
);
4244 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4245 TRANS_DP_PORT_SEL_MASK
);
4246 temp
|= TRANS_DP_PORT_SEL_NONE
;
4247 I915_WRITE(reg
, temp
);
4249 /* disable DPLL_SEL */
4250 temp
= I915_READ(PCH_DPLL_SEL
);
4251 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4252 I915_WRITE(PCH_DPLL_SEL
, temp
);
4255 /* disable PCH DPLL */
4256 intel_disable_shared_dpll(intel_crtc
);
4258 ironlake_fdi_pll_disable(intel_crtc
);
4261 intel_crtc
->active
= false;
4262 intel_update_watermarks(crtc
);
4264 mutex_lock(&dev
->struct_mutex
);
4265 intel_update_fbc(dev
);
4266 mutex_unlock(&dev
->struct_mutex
);
4269 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4271 struct drm_device
*dev
= crtc
->dev
;
4272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4273 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4274 struct intel_encoder
*encoder
;
4275 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4277 if (!intel_crtc
->active
)
4280 intel_crtc_disable_planes(crtc
);
4282 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4283 intel_opregion_notify_encoder(encoder
, false);
4284 encoder
->disable(encoder
);
4287 if (intel_crtc
->config
.has_pch_encoder
)
4288 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4289 intel_disable_pipe(intel_crtc
);
4291 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4293 ironlake_pfit_disable(intel_crtc
);
4295 intel_ddi_disable_pipe_clock(intel_crtc
);
4297 if (intel_crtc
->config
.has_pch_encoder
) {
4298 lpt_disable_pch_transcoder(dev_priv
);
4299 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4300 intel_ddi_fdi_disable(crtc
);
4303 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4304 if (encoder
->post_disable
)
4305 encoder
->post_disable(encoder
);
4307 intel_crtc
->active
= false;
4308 intel_update_watermarks(crtc
);
4310 mutex_lock(&dev
->struct_mutex
);
4311 intel_update_fbc(dev
);
4312 mutex_unlock(&dev
->struct_mutex
);
4314 if (intel_crtc_to_shared_dpll(intel_crtc
))
4315 intel_disable_shared_dpll(intel_crtc
);
4318 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4320 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4321 intel_put_shared_dpll(intel_crtc
);
4325 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4327 struct drm_device
*dev
= crtc
->base
.dev
;
4328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4329 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4331 if (!crtc
->config
.gmch_pfit
.control
)
4335 * The panel fitter should only be adjusted whilst the pipe is disabled,
4336 * according to register description and PRM.
4338 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4339 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4341 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4342 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4344 /* Border color in case we don't scale up to the full screen. Black by
4345 * default, change to something else for debugging. */
4346 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4349 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4353 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4355 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4357 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4359 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4362 return POWER_DOMAIN_PORT_OTHER
;
4366 #define for_each_power_domain(domain, mask) \
4367 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4368 if ((1 << (domain)) & (mask))
4370 enum intel_display_power_domain
4371 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4373 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4374 struct intel_digital_port
*intel_dig_port
;
4376 switch (intel_encoder
->type
) {
4377 case INTEL_OUTPUT_UNKNOWN
:
4378 /* Only DDI platforms should ever use this output type */
4379 WARN_ON_ONCE(!HAS_DDI(dev
));
4380 case INTEL_OUTPUT_DISPLAYPORT
:
4381 case INTEL_OUTPUT_HDMI
:
4382 case INTEL_OUTPUT_EDP
:
4383 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4384 return port_to_power_domain(intel_dig_port
->port
);
4385 case INTEL_OUTPUT_DP_MST
:
4386 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4387 return port_to_power_domain(intel_dig_port
->port
);
4388 case INTEL_OUTPUT_ANALOG
:
4389 return POWER_DOMAIN_PORT_CRT
;
4390 case INTEL_OUTPUT_DSI
:
4391 return POWER_DOMAIN_PORT_DSI
;
4393 return POWER_DOMAIN_PORT_OTHER
;
4397 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4399 struct drm_device
*dev
= crtc
->dev
;
4400 struct intel_encoder
*intel_encoder
;
4401 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4402 enum pipe pipe
= intel_crtc
->pipe
;
4404 enum transcoder transcoder
;
4406 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4408 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4409 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4410 if (intel_crtc
->config
.pch_pfit
.enabled
||
4411 intel_crtc
->config
.pch_pfit
.force_thru
)
4412 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4414 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4415 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4420 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4423 if (dev_priv
->power_domains
.init_power_on
== enable
)
4427 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4429 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4431 dev_priv
->power_domains
.init_power_on
= enable
;
4434 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4437 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4438 struct intel_crtc
*crtc
;
4441 * First get all needed power domains, then put all unneeded, to avoid
4442 * any unnecessary toggling of the power wells.
4444 for_each_intel_crtc(dev
, crtc
) {
4445 enum intel_display_power_domain domain
;
4447 if (!crtc
->base
.enabled
)
4450 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4452 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4453 intel_display_power_get(dev_priv
, domain
);
4456 for_each_intel_crtc(dev
, crtc
) {
4457 enum intel_display_power_domain domain
;
4459 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4460 intel_display_power_put(dev_priv
, domain
);
4462 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4465 intel_display_set_init_power(dev_priv
, false);
4468 /* returns HPLL frequency in kHz */
4469 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4471 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4473 /* Obtain SKU information */
4474 mutex_lock(&dev_priv
->dpio_lock
);
4475 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4476 CCK_FUSE_HPLL_FREQ_MASK
;
4477 mutex_unlock(&dev_priv
->dpio_lock
);
4479 return vco_freq
[hpll_freq
] * 1000;
4482 static void vlv_update_cdclk(struct drm_device
*dev
)
4484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4486 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4487 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4488 dev_priv
->vlv_cdclk_freq
);
4491 * Program the gmbus_freq based on the cdclk frequency.
4492 * BSpec erroneously claims we should aim for 4MHz, but
4493 * in fact 1MHz is the correct frequency.
4495 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4498 /* Adjust CDclk dividers to allow high res or save power if possible */
4499 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4504 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4506 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4508 else if (cdclk
== 266667)
4513 mutex_lock(&dev_priv
->rps
.hw_lock
);
4514 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4515 val
&= ~DSPFREQGUAR_MASK
;
4516 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4517 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4518 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4519 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4521 DRM_ERROR("timed out waiting for CDclk change\n");
4523 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4525 if (cdclk
== 400000) {
4528 vco
= valleyview_get_vco(dev_priv
);
4529 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4531 mutex_lock(&dev_priv
->dpio_lock
);
4532 /* adjust cdclk divider */
4533 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4534 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4536 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4538 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4539 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4541 DRM_ERROR("timed out waiting for CDclk change\n");
4542 mutex_unlock(&dev_priv
->dpio_lock
);
4545 mutex_lock(&dev_priv
->dpio_lock
);
4546 /* adjust self-refresh exit latency value */
4547 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4551 * For high bandwidth configs, we set a higher latency in the bunit
4552 * so that the core display fetch happens in time to avoid underruns.
4554 if (cdclk
== 400000)
4555 val
|= 4500 / 250; /* 4.5 usec */
4557 val
|= 3000 / 250; /* 3.0 usec */
4558 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4559 mutex_unlock(&dev_priv
->dpio_lock
);
4561 vlv_update_cdclk(dev
);
4564 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4569 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4590 mutex_lock(&dev_priv
->rps
.hw_lock
);
4591 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4592 val
&= ~DSPFREQGUAR_MASK_CHV
;
4593 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4594 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4595 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4596 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4598 DRM_ERROR("timed out waiting for CDclk change\n");
4600 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4602 vlv_update_cdclk(dev
);
4605 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4608 int vco
= valleyview_get_vco(dev_priv
);
4609 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4611 /* FIXME: Punit isn't quite ready yet */
4612 if (IS_CHERRYVIEW(dev_priv
->dev
))
4616 * Really only a few cases to deal with, as only 4 CDclks are supported:
4619 * 320/333MHz (depends on HPLL freq)
4621 * So we check to see whether we're above 90% of the lower bin and
4624 * We seem to get an unstable or solid color picture at 200MHz.
4625 * Not sure what's wrong. For now use 200MHz only when all pipes
4628 if (max_pixclk
> freq_320
*9/10)
4630 else if (max_pixclk
> 266667*9/10)
4632 else if (max_pixclk
> 0)
4638 /* compute the max pixel clock for new configuration */
4639 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4641 struct drm_device
*dev
= dev_priv
->dev
;
4642 struct intel_crtc
*intel_crtc
;
4645 for_each_intel_crtc(dev
, intel_crtc
) {
4646 if (intel_crtc
->new_enabled
)
4647 max_pixclk
= max(max_pixclk
,
4648 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4654 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4655 unsigned *prepare_pipes
)
4657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4658 struct intel_crtc
*intel_crtc
;
4659 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4661 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4662 dev_priv
->vlv_cdclk_freq
)
4665 /* disable/enable all currently active pipes while we change cdclk */
4666 for_each_intel_crtc(dev
, intel_crtc
)
4667 if (intel_crtc
->base
.enabled
)
4668 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4671 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4674 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4675 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4677 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4678 if (IS_CHERRYVIEW(dev
))
4679 cherryview_set_cdclk(dev
, req_cdclk
);
4681 valleyview_set_cdclk(dev
, req_cdclk
);
4684 modeset_update_crtc_power_domains(dev
);
4687 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4689 struct drm_device
*dev
= crtc
->dev
;
4690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4691 struct intel_encoder
*encoder
;
4692 int pipe
= intel_crtc
->pipe
;
4695 WARN_ON(!crtc
->enabled
);
4697 if (intel_crtc
->active
)
4700 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4703 if (IS_CHERRYVIEW(dev
))
4704 chv_prepare_pll(intel_crtc
);
4706 vlv_prepare_pll(intel_crtc
);
4709 if (intel_crtc
->config
.has_dp_encoder
)
4710 intel_dp_set_m_n(intel_crtc
);
4712 intel_set_pipe_timings(intel_crtc
);
4714 i9xx_set_pipeconf(intel_crtc
);
4716 intel_crtc
->active
= true;
4718 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4720 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4721 if (encoder
->pre_pll_enable
)
4722 encoder
->pre_pll_enable(encoder
);
4725 if (IS_CHERRYVIEW(dev
))
4726 chv_enable_pll(intel_crtc
);
4728 vlv_enable_pll(intel_crtc
);
4731 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4732 if (encoder
->pre_enable
)
4733 encoder
->pre_enable(encoder
);
4735 i9xx_pfit_enable(intel_crtc
);
4737 intel_crtc_load_lut(crtc
);
4739 intel_update_watermarks(crtc
);
4740 intel_enable_pipe(intel_crtc
);
4742 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4743 encoder
->enable(encoder
);
4745 intel_crtc_enable_planes(crtc
);
4747 /* Underruns don't raise interrupts, so check manually. */
4748 i9xx_check_fifo_underruns(dev
);
4751 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4753 struct drm_device
*dev
= crtc
->base
.dev
;
4754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4756 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4757 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4760 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4762 struct drm_device
*dev
= crtc
->dev
;
4763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4764 struct intel_encoder
*encoder
;
4765 int pipe
= intel_crtc
->pipe
;
4767 WARN_ON(!crtc
->enabled
);
4769 if (intel_crtc
->active
)
4772 i9xx_set_pll_dividers(intel_crtc
);
4774 if (intel_crtc
->config
.has_dp_encoder
)
4775 intel_dp_set_m_n(intel_crtc
);
4777 intel_set_pipe_timings(intel_crtc
);
4779 i9xx_set_pipeconf(intel_crtc
);
4781 intel_crtc
->active
= true;
4784 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4786 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4787 if (encoder
->pre_enable
)
4788 encoder
->pre_enable(encoder
);
4790 i9xx_enable_pll(intel_crtc
);
4792 i9xx_pfit_enable(intel_crtc
);
4794 intel_crtc_load_lut(crtc
);
4796 intel_update_watermarks(crtc
);
4797 intel_enable_pipe(intel_crtc
);
4799 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4800 encoder
->enable(encoder
);
4802 intel_crtc_enable_planes(crtc
);
4805 * Gen2 reports pipe underruns whenever all planes are disabled.
4806 * So don't enable underrun reporting before at least some planes
4808 * FIXME: Need to fix the logic to work when we turn off all planes
4809 * but leave the pipe running.
4812 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4814 /* Underruns don't raise interrupts, so check manually. */
4815 i9xx_check_fifo_underruns(dev
);
4818 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4820 struct drm_device
*dev
= crtc
->base
.dev
;
4821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4823 if (!crtc
->config
.gmch_pfit
.control
)
4826 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4828 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4829 I915_READ(PFIT_CONTROL
));
4830 I915_WRITE(PFIT_CONTROL
, 0);
4833 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4835 struct drm_device
*dev
= crtc
->dev
;
4836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4838 struct intel_encoder
*encoder
;
4839 int pipe
= intel_crtc
->pipe
;
4841 if (!intel_crtc
->active
)
4845 * Gen2 reports pipe underruns whenever all planes are disabled.
4846 * So diasble underrun reporting before all the planes get disabled.
4847 * FIXME: Need to fix the logic to work when we turn off all planes
4848 * but leave the pipe running.
4851 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4854 * Vblank time updates from the shadow to live plane control register
4855 * are blocked if the memory self-refresh mode is active at that
4856 * moment. So to make sure the plane gets truly disabled, disable
4857 * first the self-refresh mode. The self-refresh enable bit in turn
4858 * will be checked/applied by the HW only at the next frame start
4859 * event which is after the vblank start event, so we need to have a
4860 * wait-for-vblank between disabling the plane and the pipe.
4862 intel_set_memory_cxsr(dev_priv
, false);
4863 intel_crtc_disable_planes(crtc
);
4865 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4866 encoder
->disable(encoder
);
4869 * On gen2 planes are double buffered but the pipe isn't, so we must
4870 * wait for planes to fully turn off before disabling the pipe.
4871 * We also need to wait on all gmch platforms because of the
4872 * self-refresh mode constraint explained above.
4874 intel_wait_for_vblank(dev
, pipe
);
4876 intel_disable_pipe(intel_crtc
);
4878 i9xx_pfit_disable(intel_crtc
);
4880 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4881 if (encoder
->post_disable
)
4882 encoder
->post_disable(encoder
);
4884 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4885 if (IS_CHERRYVIEW(dev
))
4886 chv_disable_pll(dev_priv
, pipe
);
4887 else if (IS_VALLEYVIEW(dev
))
4888 vlv_disable_pll(dev_priv
, pipe
);
4890 i9xx_disable_pll(dev_priv
, pipe
);
4894 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4896 intel_crtc
->active
= false;
4897 intel_update_watermarks(crtc
);
4899 mutex_lock(&dev
->struct_mutex
);
4900 intel_update_fbc(dev
);
4901 mutex_unlock(&dev
->struct_mutex
);
4904 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4908 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4911 struct drm_device
*dev
= crtc
->dev
;
4912 struct drm_i915_master_private
*master_priv
;
4913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4914 int pipe
= intel_crtc
->pipe
;
4916 if (!dev
->primary
->master
)
4919 master_priv
= dev
->primary
->master
->driver_priv
;
4920 if (!master_priv
->sarea_priv
)
4925 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4926 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4929 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4930 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4933 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4938 /* Master function to enable/disable CRTC and corresponding power wells */
4939 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
4941 struct drm_device
*dev
= crtc
->dev
;
4942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4944 enum intel_display_power_domain domain
;
4945 unsigned long domains
;
4948 if (!intel_crtc
->active
) {
4949 domains
= get_crtc_power_domains(crtc
);
4950 for_each_power_domain(domain
, domains
)
4951 intel_display_power_get(dev_priv
, domain
);
4952 intel_crtc
->enabled_power_domains
= domains
;
4954 dev_priv
->display
.crtc_enable(crtc
);
4957 if (intel_crtc
->active
) {
4958 dev_priv
->display
.crtc_disable(crtc
);
4960 domains
= intel_crtc
->enabled_power_domains
;
4961 for_each_power_domain(domain
, domains
)
4962 intel_display_power_put(dev_priv
, domain
);
4963 intel_crtc
->enabled_power_domains
= 0;
4969 * Sets the power management mode of the pipe and plane.
4971 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4973 struct drm_device
*dev
= crtc
->dev
;
4974 struct intel_encoder
*intel_encoder
;
4975 bool enable
= false;
4977 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4978 enable
|= intel_encoder
->connectors_active
;
4980 intel_crtc_control(crtc
, enable
);
4982 intel_crtc_update_sarea(crtc
, enable
);
4985 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4987 struct drm_device
*dev
= crtc
->dev
;
4988 struct drm_connector
*connector
;
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
4991 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4993 /* crtc should still be enabled when we disable it. */
4994 WARN_ON(!crtc
->enabled
);
4996 dev_priv
->display
.crtc_disable(crtc
);
4997 intel_crtc_update_sarea(crtc
, false);
4998 dev_priv
->display
.off(crtc
);
5000 if (crtc
->primary
->fb
) {
5001 mutex_lock(&dev
->struct_mutex
);
5002 intel_unpin_fb_obj(old_obj
);
5003 i915_gem_track_fb(old_obj
, NULL
,
5004 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5005 mutex_unlock(&dev
->struct_mutex
);
5006 crtc
->primary
->fb
= NULL
;
5009 /* Update computed state. */
5010 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5011 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5014 if (connector
->encoder
->crtc
!= crtc
)
5017 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5018 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5022 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5024 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5026 drm_encoder_cleanup(encoder
);
5027 kfree(intel_encoder
);
5030 /* Simple dpms helper for encoders with just one connector, no cloning and only
5031 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5032 * state of the entire output pipe. */
5033 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5035 if (mode
== DRM_MODE_DPMS_ON
) {
5036 encoder
->connectors_active
= true;
5038 intel_crtc_update_dpms(encoder
->base
.crtc
);
5040 encoder
->connectors_active
= false;
5042 intel_crtc_update_dpms(encoder
->base
.crtc
);
5046 /* Cross check the actual hw state with our own modeset state tracking (and it's
5047 * internal consistency). */
5048 static void intel_connector_check_state(struct intel_connector
*connector
)
5050 if (connector
->get_hw_state(connector
)) {
5051 struct intel_encoder
*encoder
= connector
->encoder
;
5052 struct drm_crtc
*crtc
;
5053 bool encoder_enabled
;
5056 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5057 connector
->base
.base
.id
,
5058 connector
->base
.name
);
5060 /* there is no real hw state for MST connectors */
5061 if (connector
->mst_port
)
5064 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5065 "wrong connector dpms state\n");
5066 WARN(connector
->base
.encoder
!= &encoder
->base
,
5067 "active connector not linked to encoder\n");
5070 WARN(!encoder
->connectors_active
,
5071 "encoder->connectors_active not set\n");
5073 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5074 WARN(!encoder_enabled
, "encoder not enabled\n");
5075 if (WARN_ON(!encoder
->base
.crtc
))
5078 crtc
= encoder
->base
.crtc
;
5080 WARN(!crtc
->enabled
, "crtc not enabled\n");
5081 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5082 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5083 "encoder active on the wrong pipe\n");
5088 /* Even simpler default implementation, if there's really no special case to
5090 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5092 /* All the simple cases only support two dpms states. */
5093 if (mode
!= DRM_MODE_DPMS_ON
)
5094 mode
= DRM_MODE_DPMS_OFF
;
5096 if (mode
== connector
->dpms
)
5099 connector
->dpms
= mode
;
5101 /* Only need to change hw state when actually enabled */
5102 if (connector
->encoder
)
5103 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5105 intel_modeset_check_state(connector
->dev
);
5108 /* Simple connector->get_hw_state implementation for encoders that support only
5109 * one connector and no cloning and hence the encoder state determines the state
5110 * of the connector. */
5111 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5114 struct intel_encoder
*encoder
= connector
->encoder
;
5116 return encoder
->get_hw_state(encoder
, &pipe
);
5119 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5120 struct intel_crtc_config
*pipe_config
)
5122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5123 struct intel_crtc
*pipe_B_crtc
=
5124 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5126 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5127 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5128 if (pipe_config
->fdi_lanes
> 4) {
5129 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5130 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5134 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5135 if (pipe_config
->fdi_lanes
> 2) {
5136 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5137 pipe_config
->fdi_lanes
);
5144 if (INTEL_INFO(dev
)->num_pipes
== 2)
5147 /* Ivybridge 3 pipe is really complicated */
5152 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5153 pipe_config
->fdi_lanes
> 2) {
5154 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5155 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5160 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5161 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5162 if (pipe_config
->fdi_lanes
> 2) {
5163 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5164 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5168 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5178 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5179 struct intel_crtc_config
*pipe_config
)
5181 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5182 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5183 int lane
, link_bw
, fdi_dotclock
;
5184 bool setup_ok
, needs_recompute
= false;
5187 /* FDI is a binary signal running at ~2.7GHz, encoding
5188 * each output octet as 10 bits. The actual frequency
5189 * is stored as a divider into a 100MHz clock, and the
5190 * mode pixel clock is stored in units of 1KHz.
5191 * Hence the bw of each lane in terms of the mode signal
5194 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5196 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5198 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5199 pipe_config
->pipe_bpp
);
5201 pipe_config
->fdi_lanes
= lane
;
5203 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5204 link_bw
, &pipe_config
->fdi_m_n
);
5206 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5207 intel_crtc
->pipe
, pipe_config
);
5208 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5209 pipe_config
->pipe_bpp
-= 2*3;
5210 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5211 pipe_config
->pipe_bpp
);
5212 needs_recompute
= true;
5213 pipe_config
->bw_constrained
= true;
5218 if (needs_recompute
)
5221 return setup_ok
? 0 : -EINVAL
;
5224 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5225 struct intel_crtc_config
*pipe_config
)
5227 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5228 hsw_crtc_supports_ips(crtc
) &&
5229 pipe_config
->pipe_bpp
<= 24;
5232 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5233 struct intel_crtc_config
*pipe_config
)
5235 struct drm_device
*dev
= crtc
->base
.dev
;
5236 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5238 /* FIXME should check pixel clock limits on all platforms */
5239 if (INTEL_INFO(dev
)->gen
< 4) {
5240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5242 dev_priv
->display
.get_display_clock_speed(dev
);
5245 * Enable pixel doubling when the dot clock
5246 * is > 90% of the (display) core speed.
5248 * GDG double wide on either pipe,
5249 * otherwise pipe A only.
5251 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5252 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5254 pipe_config
->double_wide
= true;
5257 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5262 * Pipe horizontal size must be even in:
5264 * - LVDS dual channel mode
5265 * - Double wide pipe
5267 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5268 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5269 pipe_config
->pipe_src_w
&= ~1;
5271 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5272 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5274 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5275 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5278 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5279 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5280 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5281 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5283 pipe_config
->pipe_bpp
= 8*3;
5287 hsw_compute_ips_config(crtc
, pipe_config
);
5290 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5291 * old clock survives for now.
5293 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5294 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5296 if (pipe_config
->has_pch_encoder
)
5297 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5302 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5305 int vco
= valleyview_get_vco(dev_priv
);
5309 /* FIXME: Punit isn't quite ready yet */
5310 if (IS_CHERRYVIEW(dev
))
5313 mutex_lock(&dev_priv
->dpio_lock
);
5314 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5315 mutex_unlock(&dev_priv
->dpio_lock
);
5317 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5319 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5320 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5321 "cdclk change in progress\n");
5323 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5326 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5331 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5336 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5341 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5345 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5347 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5348 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5350 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5352 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5354 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5357 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5358 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5360 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5365 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5369 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5371 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5374 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5375 case GC_DISPLAY_CLOCK_333_MHZ
:
5378 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5384 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5389 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5392 /* Assume that the hardware is in the high speed state. This
5393 * should be the default.
5395 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5396 case GC_CLOCK_133_200
:
5397 case GC_CLOCK_100_200
:
5399 case GC_CLOCK_166_250
:
5401 case GC_CLOCK_100_133
:
5405 /* Shouldn't happen */
5409 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5415 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5417 while (*num
> DATA_LINK_M_N_MASK
||
5418 *den
> DATA_LINK_M_N_MASK
) {
5424 static void compute_m_n(unsigned int m
, unsigned int n
,
5425 uint32_t *ret_m
, uint32_t *ret_n
)
5427 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5428 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5429 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5433 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5434 int pixel_clock
, int link_clock
,
5435 struct intel_link_m_n
*m_n
)
5439 compute_m_n(bits_per_pixel
* pixel_clock
,
5440 link_clock
* nlanes
* 8,
5441 &m_n
->gmch_m
, &m_n
->gmch_n
);
5443 compute_m_n(pixel_clock
, link_clock
,
5444 &m_n
->link_m
, &m_n
->link_n
);
5447 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5449 if (i915
.panel_use_ssc
>= 0)
5450 return i915
.panel_use_ssc
!= 0;
5451 return dev_priv
->vbt
.lvds_use_ssc
5452 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5455 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5457 struct drm_device
*dev
= crtc
->dev
;
5458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5461 if (IS_VALLEYVIEW(dev
)) {
5463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5464 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5465 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5466 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5467 } else if (!IS_GEN2(dev
)) {
5476 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5478 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5481 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5483 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5486 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5487 intel_clock_t
*reduced_clock
)
5489 struct drm_device
*dev
= crtc
->base
.dev
;
5492 if (IS_PINEVIEW(dev
)) {
5493 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5495 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5497 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5499 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5502 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5504 crtc
->lowfreq_avail
= false;
5505 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5506 reduced_clock
&& i915
.powersave
) {
5507 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5508 crtc
->lowfreq_avail
= true;
5510 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5514 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5520 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5521 * and set it to a reasonable value instead.
5523 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5524 reg_val
&= 0xffffff00;
5525 reg_val
|= 0x00000030;
5526 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5528 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5529 reg_val
&= 0x8cffffff;
5530 reg_val
= 0x8c000000;
5531 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5533 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5534 reg_val
&= 0xffffff00;
5535 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5537 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5538 reg_val
&= 0x00ffffff;
5539 reg_val
|= 0xb0000000;
5540 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5543 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5544 struct intel_link_m_n
*m_n
)
5546 struct drm_device
*dev
= crtc
->base
.dev
;
5547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5548 int pipe
= crtc
->pipe
;
5550 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5551 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5552 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5553 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5556 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5557 struct intel_link_m_n
*m_n
,
5558 struct intel_link_m_n
*m2_n2
)
5560 struct drm_device
*dev
= crtc
->base
.dev
;
5561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5562 int pipe
= crtc
->pipe
;
5563 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5565 if (INTEL_INFO(dev
)->gen
>= 5) {
5566 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5567 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5568 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5569 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5570 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5571 * for gen < 8) and if DRRS is supported (to make sure the
5572 * registers are not unnecessarily accessed).
5574 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5575 crtc
->config
.has_drrs
) {
5576 I915_WRITE(PIPE_DATA_M2(transcoder
),
5577 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5578 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5579 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5580 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5583 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5584 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5585 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5586 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5590 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5592 if (crtc
->config
.has_pch_encoder
)
5593 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5595 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5596 &crtc
->config
.dp_m2_n2
);
5599 static void vlv_update_pll(struct intel_crtc
*crtc
)
5604 * Enable DPIO clock input. We should never disable the reference
5605 * clock for pipe B, since VGA hotplug / manual detection depends
5608 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5609 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5610 /* We should never disable this, set it here for state tracking */
5611 if (crtc
->pipe
== PIPE_B
)
5612 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5613 dpll
|= DPLL_VCO_ENABLE
;
5614 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5616 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5617 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5618 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5621 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5623 struct drm_device
*dev
= crtc
->base
.dev
;
5624 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5625 int pipe
= crtc
->pipe
;
5627 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5628 u32 coreclk
, reg_val
;
5630 mutex_lock(&dev_priv
->dpio_lock
);
5632 bestn
= crtc
->config
.dpll
.n
;
5633 bestm1
= crtc
->config
.dpll
.m1
;
5634 bestm2
= crtc
->config
.dpll
.m2
;
5635 bestp1
= crtc
->config
.dpll
.p1
;
5636 bestp2
= crtc
->config
.dpll
.p2
;
5638 /* See eDP HDMI DPIO driver vbios notes doc */
5640 /* PLL B needs special handling */
5642 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5644 /* Set up Tx target for periodic Rcomp update */
5645 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5647 /* Disable target IRef on PLL */
5648 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5649 reg_val
&= 0x00ffffff;
5650 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5652 /* Disable fast lock */
5653 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5655 /* Set idtafcrecal before PLL is enabled */
5656 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5657 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5658 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5659 mdiv
|= (1 << DPIO_K_SHIFT
);
5662 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5663 * but we don't support that).
5664 * Note: don't use the DAC post divider as it seems unstable.
5666 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5667 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5669 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5670 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5672 /* Set HBR and RBR LPF coefficients */
5673 if (crtc
->config
.port_clock
== 162000 ||
5674 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5675 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5676 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5679 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5682 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5683 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5684 /* Use SSC source */
5686 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5689 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5691 } else { /* HDMI or VGA */
5692 /* Use bend source */
5694 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5697 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5701 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5702 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5703 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5704 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5705 coreclk
|= 0x01000000;
5706 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5708 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5709 mutex_unlock(&dev_priv
->dpio_lock
);
5712 static void chv_update_pll(struct intel_crtc
*crtc
)
5714 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5715 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5717 if (crtc
->pipe
!= PIPE_A
)
5718 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5720 crtc
->config
.dpll_hw_state
.dpll_md
=
5721 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5724 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5726 struct drm_device
*dev
= crtc
->base
.dev
;
5727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5728 int pipe
= crtc
->pipe
;
5729 int dpll_reg
= DPLL(crtc
->pipe
);
5730 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5731 u32 loopfilter
, intcoeff
;
5732 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5735 bestn
= crtc
->config
.dpll
.n
;
5736 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5737 bestm1
= crtc
->config
.dpll
.m1
;
5738 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5739 bestp1
= crtc
->config
.dpll
.p1
;
5740 bestp2
= crtc
->config
.dpll
.p2
;
5743 * Enable Refclk and SSC
5745 I915_WRITE(dpll_reg
,
5746 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5748 mutex_lock(&dev_priv
->dpio_lock
);
5750 /* p1 and p2 divider */
5751 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5752 5 << DPIO_CHV_S1_DIV_SHIFT
|
5753 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5754 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5755 1 << DPIO_CHV_K_DIV_SHIFT
);
5757 /* Feedback post-divider - m2 */
5758 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5760 /* Feedback refclk divider - n and m1 */
5761 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5762 DPIO_CHV_M1_DIV_BY_2
|
5763 1 << DPIO_CHV_N_DIV_SHIFT
);
5765 /* M2 fraction division */
5766 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5768 /* M2 fraction division enable */
5769 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5770 DPIO_CHV_FRAC_DIV_EN
|
5771 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5774 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5775 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5776 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5777 if (refclk
== 100000)
5779 else if (refclk
== 38400)
5783 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5784 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5787 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5788 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5791 mutex_unlock(&dev_priv
->dpio_lock
);
5794 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5795 intel_clock_t
*reduced_clock
,
5798 struct drm_device
*dev
= crtc
->base
.dev
;
5799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5802 struct dpll
*clock
= &crtc
->config
.dpll
;
5804 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5806 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5807 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5809 dpll
= DPLL_VGA_MODE_DIS
;
5811 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5812 dpll
|= DPLLB_MODE_LVDS
;
5814 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5816 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5817 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5818 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5822 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5824 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5825 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5827 /* compute bitmask from p1 value */
5828 if (IS_PINEVIEW(dev
))
5829 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5831 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5832 if (IS_G4X(dev
) && reduced_clock
)
5833 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5835 switch (clock
->p2
) {
5837 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5840 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5843 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5846 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5849 if (INTEL_INFO(dev
)->gen
>= 4)
5850 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5852 if (crtc
->config
.sdvo_tv_clock
)
5853 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5854 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5855 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5856 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5858 dpll
|= PLL_REF_INPUT_DREFCLK
;
5860 dpll
|= DPLL_VCO_ENABLE
;
5861 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5863 if (INTEL_INFO(dev
)->gen
>= 4) {
5864 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5865 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5866 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5870 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5871 intel_clock_t
*reduced_clock
,
5874 struct drm_device
*dev
= crtc
->base
.dev
;
5875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5877 struct dpll
*clock
= &crtc
->config
.dpll
;
5879 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5881 dpll
= DPLL_VGA_MODE_DIS
;
5883 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5884 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5887 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5889 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5891 dpll
|= PLL_P2_DIVIDE_BY_4
;
5894 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5895 dpll
|= DPLL_DVO_2X_MODE
;
5897 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5898 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5899 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5901 dpll
|= PLL_REF_INPUT_DREFCLK
;
5903 dpll
|= DPLL_VCO_ENABLE
;
5904 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5907 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5909 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5911 enum pipe pipe
= intel_crtc
->pipe
;
5912 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5913 struct drm_display_mode
*adjusted_mode
=
5914 &intel_crtc
->config
.adjusted_mode
;
5915 uint32_t crtc_vtotal
, crtc_vblank_end
;
5918 /* We need to be careful not to changed the adjusted mode, for otherwise
5919 * the hw state checker will get angry at the mismatch. */
5920 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5921 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5923 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5924 /* the chip adds 2 halflines automatically */
5926 crtc_vblank_end
-= 1;
5928 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5929 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5931 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5932 adjusted_mode
->crtc_htotal
/ 2;
5934 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5937 if (INTEL_INFO(dev
)->gen
> 3)
5938 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5940 I915_WRITE(HTOTAL(cpu_transcoder
),
5941 (adjusted_mode
->crtc_hdisplay
- 1) |
5942 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5943 I915_WRITE(HBLANK(cpu_transcoder
),
5944 (adjusted_mode
->crtc_hblank_start
- 1) |
5945 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5946 I915_WRITE(HSYNC(cpu_transcoder
),
5947 (adjusted_mode
->crtc_hsync_start
- 1) |
5948 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5950 I915_WRITE(VTOTAL(cpu_transcoder
),
5951 (adjusted_mode
->crtc_vdisplay
- 1) |
5952 ((crtc_vtotal
- 1) << 16));
5953 I915_WRITE(VBLANK(cpu_transcoder
),
5954 (adjusted_mode
->crtc_vblank_start
- 1) |
5955 ((crtc_vblank_end
- 1) << 16));
5956 I915_WRITE(VSYNC(cpu_transcoder
),
5957 (adjusted_mode
->crtc_vsync_start
- 1) |
5958 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5960 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5961 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5962 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5964 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5965 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5966 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5968 /* pipesrc controls the size that is scaled from, which should
5969 * always be the user's requested size.
5971 I915_WRITE(PIPESRC(pipe
),
5972 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5973 (intel_crtc
->config
.pipe_src_h
- 1));
5976 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5977 struct intel_crtc_config
*pipe_config
)
5979 struct drm_device
*dev
= crtc
->base
.dev
;
5980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5981 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5984 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5985 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5986 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5987 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5988 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5989 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5990 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5991 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5992 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5994 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5995 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5996 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5997 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5998 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5999 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6000 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6001 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6002 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6004 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6005 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6006 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6007 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6010 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6011 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6012 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6014 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6015 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6018 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6019 struct intel_crtc_config
*pipe_config
)
6021 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6022 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6023 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6024 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6026 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6027 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6028 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6029 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6031 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6033 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6034 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6037 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6039 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6045 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6046 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6047 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6049 if (intel_crtc
->config
.double_wide
)
6050 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6052 /* only g4x and later have fancy bpc/dither controls */
6053 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6054 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6055 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6056 pipeconf
|= PIPECONF_DITHER_EN
|
6057 PIPECONF_DITHER_TYPE_SP
;
6059 switch (intel_crtc
->config
.pipe_bpp
) {
6061 pipeconf
|= PIPECONF_6BPC
;
6064 pipeconf
|= PIPECONF_8BPC
;
6067 pipeconf
|= PIPECONF_10BPC
;
6070 /* Case prevented by intel_choose_pipe_bpp_dither. */
6075 if (HAS_PIPE_CXSR(dev
)) {
6076 if (intel_crtc
->lowfreq_avail
) {
6077 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6078 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6080 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6084 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6085 if (INTEL_INFO(dev
)->gen
< 4 ||
6086 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6087 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6089 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6091 pipeconf
|= PIPECONF_PROGRESSIVE
;
6093 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6094 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6096 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6097 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6100 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6102 struct drm_framebuffer
*fb
)
6104 struct drm_device
*dev
= crtc
->dev
;
6105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6106 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6107 int refclk
, num_connectors
= 0;
6108 intel_clock_t clock
, reduced_clock
;
6109 bool ok
, has_reduced_clock
= false;
6110 bool is_lvds
= false, is_dsi
= false;
6111 struct intel_encoder
*encoder
;
6112 const intel_limit_t
*limit
;
6114 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6115 switch (encoder
->type
) {
6116 case INTEL_OUTPUT_LVDS
:
6119 case INTEL_OUTPUT_DSI
:
6130 if (!intel_crtc
->config
.clock_set
) {
6131 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6134 * Returns a set of divisors for the desired target clock with
6135 * the given refclk, or FALSE. The returned values represent
6136 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6139 limit
= intel_limit(crtc
, refclk
);
6140 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6141 intel_crtc
->config
.port_clock
,
6142 refclk
, NULL
, &clock
);
6144 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6148 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6150 * Ensure we match the reduced clock's P to the target
6151 * clock. If the clocks don't match, we can't switch
6152 * the display clock by using the FP0/FP1. In such case
6153 * we will disable the LVDS downclock feature.
6156 dev_priv
->display
.find_dpll(limit
, crtc
,
6157 dev_priv
->lvds_downclock
,
6161 /* Compat-code for transition, will disappear. */
6162 intel_crtc
->config
.dpll
.n
= clock
.n
;
6163 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6164 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6165 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6166 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6170 i8xx_update_pll(intel_crtc
,
6171 has_reduced_clock
? &reduced_clock
: NULL
,
6173 } else if (IS_CHERRYVIEW(dev
)) {
6174 chv_update_pll(intel_crtc
);
6175 } else if (IS_VALLEYVIEW(dev
)) {
6176 vlv_update_pll(intel_crtc
);
6178 i9xx_update_pll(intel_crtc
,
6179 has_reduced_clock
? &reduced_clock
: NULL
,
6186 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6187 struct intel_crtc_config
*pipe_config
)
6189 struct drm_device
*dev
= crtc
->base
.dev
;
6190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6193 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6196 tmp
= I915_READ(PFIT_CONTROL
);
6197 if (!(tmp
& PFIT_ENABLE
))
6200 /* Check whether the pfit is attached to our pipe. */
6201 if (INTEL_INFO(dev
)->gen
< 4) {
6202 if (crtc
->pipe
!= PIPE_B
)
6205 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6209 pipe_config
->gmch_pfit
.control
= tmp
;
6210 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6211 if (INTEL_INFO(dev
)->gen
< 5)
6212 pipe_config
->gmch_pfit
.lvds_border_bits
=
6213 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6216 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6217 struct intel_crtc_config
*pipe_config
)
6219 struct drm_device
*dev
= crtc
->base
.dev
;
6220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6221 int pipe
= pipe_config
->cpu_transcoder
;
6222 intel_clock_t clock
;
6224 int refclk
= 100000;
6226 /* In case of MIPI DPLL will not even be used */
6227 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6230 mutex_lock(&dev_priv
->dpio_lock
);
6231 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6232 mutex_unlock(&dev_priv
->dpio_lock
);
6234 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6235 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6236 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6237 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6238 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6240 vlv_clock(refclk
, &clock
);
6242 /* clock.dot is the fast clock */
6243 pipe_config
->port_clock
= clock
.dot
/ 5;
6246 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6247 struct intel_plane_config
*plane_config
)
6249 struct drm_device
*dev
= crtc
->base
.dev
;
6250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6251 u32 val
, base
, offset
;
6252 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6253 int fourcc
, pixel_format
;
6256 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6257 if (!crtc
->base
.primary
->fb
) {
6258 DRM_DEBUG_KMS("failed to alloc fb\n");
6262 val
= I915_READ(DSPCNTR(plane
));
6264 if (INTEL_INFO(dev
)->gen
>= 4)
6265 if (val
& DISPPLANE_TILED
)
6266 plane_config
->tiled
= true;
6268 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6269 fourcc
= intel_format_to_fourcc(pixel_format
);
6270 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6271 crtc
->base
.primary
->fb
->bits_per_pixel
=
6272 drm_format_plane_cpp(fourcc
, 0) * 8;
6274 if (INTEL_INFO(dev
)->gen
>= 4) {
6275 if (plane_config
->tiled
)
6276 offset
= I915_READ(DSPTILEOFF(plane
));
6278 offset
= I915_READ(DSPLINOFF(plane
));
6279 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6281 base
= I915_READ(DSPADDR(plane
));
6283 plane_config
->base
= base
;
6285 val
= I915_READ(PIPESRC(pipe
));
6286 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6287 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6289 val
= I915_READ(DSPSTRIDE(pipe
));
6290 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6292 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6293 plane_config
->tiled
);
6295 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6298 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6299 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6300 crtc
->base
.primary
->fb
->height
,
6301 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6302 crtc
->base
.primary
->fb
->pitches
[0],
6303 plane_config
->size
);
6307 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6308 struct intel_crtc_config
*pipe_config
)
6310 struct drm_device
*dev
= crtc
->base
.dev
;
6311 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6312 int pipe
= pipe_config
->cpu_transcoder
;
6313 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6314 intel_clock_t clock
;
6315 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6316 int refclk
= 100000;
6318 mutex_lock(&dev_priv
->dpio_lock
);
6319 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6320 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6321 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6322 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6323 mutex_unlock(&dev_priv
->dpio_lock
);
6325 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6326 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6327 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6328 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6329 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6331 chv_clock(refclk
, &clock
);
6333 /* clock.dot is the fast clock */
6334 pipe_config
->port_clock
= clock
.dot
/ 5;
6337 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6338 struct intel_crtc_config
*pipe_config
)
6340 struct drm_device
*dev
= crtc
->base
.dev
;
6341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6344 if (!intel_display_power_enabled(dev_priv
,
6345 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6348 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6349 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6351 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6352 if (!(tmp
& PIPECONF_ENABLE
))
6355 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6356 switch (tmp
& PIPECONF_BPC_MASK
) {
6358 pipe_config
->pipe_bpp
= 18;
6361 pipe_config
->pipe_bpp
= 24;
6363 case PIPECONF_10BPC
:
6364 pipe_config
->pipe_bpp
= 30;
6371 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6372 pipe_config
->limited_color_range
= true;
6374 if (INTEL_INFO(dev
)->gen
< 4)
6375 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6377 intel_get_pipe_timings(crtc
, pipe_config
);
6379 i9xx_get_pfit_config(crtc
, pipe_config
);
6381 if (INTEL_INFO(dev
)->gen
>= 4) {
6382 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6383 pipe_config
->pixel_multiplier
=
6384 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6385 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6386 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6387 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6388 tmp
= I915_READ(DPLL(crtc
->pipe
));
6389 pipe_config
->pixel_multiplier
=
6390 ((tmp
& SDVO_MULTIPLIER_MASK
)
6391 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6393 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6394 * port and will be fixed up in the encoder->get_config
6396 pipe_config
->pixel_multiplier
= 1;
6398 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6399 if (!IS_VALLEYVIEW(dev
)) {
6400 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6401 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6403 /* Mask out read-only status bits. */
6404 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6405 DPLL_PORTC_READY_MASK
|
6406 DPLL_PORTB_READY_MASK
);
6409 if (IS_CHERRYVIEW(dev
))
6410 chv_crtc_clock_get(crtc
, pipe_config
);
6411 else if (IS_VALLEYVIEW(dev
))
6412 vlv_crtc_clock_get(crtc
, pipe_config
);
6414 i9xx_crtc_clock_get(crtc
, pipe_config
);
6419 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6422 struct intel_encoder
*encoder
;
6424 bool has_lvds
= false;
6425 bool has_cpu_edp
= false;
6426 bool has_panel
= false;
6427 bool has_ck505
= false;
6428 bool can_ssc
= false;
6430 /* We need to take the global config into account */
6431 for_each_intel_encoder(dev
, encoder
) {
6432 switch (encoder
->type
) {
6433 case INTEL_OUTPUT_LVDS
:
6437 case INTEL_OUTPUT_EDP
:
6439 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6445 if (HAS_PCH_IBX(dev
)) {
6446 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6447 can_ssc
= has_ck505
;
6453 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6454 has_panel
, has_lvds
, has_ck505
);
6456 /* Ironlake: try to setup display ref clock before DPLL
6457 * enabling. This is only under driver's control after
6458 * PCH B stepping, previous chipset stepping should be
6459 * ignoring this setting.
6461 val
= I915_READ(PCH_DREF_CONTROL
);
6463 /* As we must carefully and slowly disable/enable each source in turn,
6464 * compute the final state we want first and check if we need to
6465 * make any changes at all.
6468 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6470 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6472 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6474 final
&= ~DREF_SSC_SOURCE_MASK
;
6475 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6476 final
&= ~DREF_SSC1_ENABLE
;
6479 final
|= DREF_SSC_SOURCE_ENABLE
;
6481 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6482 final
|= DREF_SSC1_ENABLE
;
6485 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6486 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6488 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6490 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6492 final
|= DREF_SSC_SOURCE_DISABLE
;
6493 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6499 /* Always enable nonspread source */
6500 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6503 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6505 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6508 val
&= ~DREF_SSC_SOURCE_MASK
;
6509 val
|= DREF_SSC_SOURCE_ENABLE
;
6511 /* SSC must be turned on before enabling the CPU output */
6512 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6513 DRM_DEBUG_KMS("Using SSC on panel\n");
6514 val
|= DREF_SSC1_ENABLE
;
6516 val
&= ~DREF_SSC1_ENABLE
;
6518 /* Get SSC going before enabling the outputs */
6519 I915_WRITE(PCH_DREF_CONTROL
, val
);
6520 POSTING_READ(PCH_DREF_CONTROL
);
6523 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6525 /* Enable CPU source on CPU attached eDP */
6527 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6528 DRM_DEBUG_KMS("Using SSC on eDP\n");
6529 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6531 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6533 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6535 I915_WRITE(PCH_DREF_CONTROL
, val
);
6536 POSTING_READ(PCH_DREF_CONTROL
);
6539 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6541 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6543 /* Turn off CPU output */
6544 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6546 I915_WRITE(PCH_DREF_CONTROL
, val
);
6547 POSTING_READ(PCH_DREF_CONTROL
);
6550 /* Turn off the SSC source */
6551 val
&= ~DREF_SSC_SOURCE_MASK
;
6552 val
|= DREF_SSC_SOURCE_DISABLE
;
6555 val
&= ~DREF_SSC1_ENABLE
;
6557 I915_WRITE(PCH_DREF_CONTROL
, val
);
6558 POSTING_READ(PCH_DREF_CONTROL
);
6562 BUG_ON(val
!= final
);
6565 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6569 tmp
= I915_READ(SOUTH_CHICKEN2
);
6570 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6571 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6573 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6574 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6575 DRM_ERROR("FDI mPHY reset assert timeout\n");
6577 tmp
= I915_READ(SOUTH_CHICKEN2
);
6578 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6579 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6581 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6582 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6583 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6586 /* WaMPhyProgramming:hsw */
6587 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6591 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6592 tmp
&= ~(0xFF << 24);
6593 tmp
|= (0x12 << 24);
6594 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6596 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6598 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6600 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6602 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6604 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6605 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6606 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6608 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6609 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6610 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6612 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6615 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6617 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6620 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6622 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6625 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6627 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6630 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6632 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6633 tmp
&= ~(0xFF << 16);
6634 tmp
|= (0x1C << 16);
6635 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6637 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6638 tmp
&= ~(0xFF << 16);
6639 tmp
|= (0x1C << 16);
6640 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6642 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6644 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6646 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6648 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6650 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6651 tmp
&= ~(0xF << 28);
6653 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6655 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6656 tmp
&= ~(0xF << 28);
6658 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6661 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6662 * Programming" based on the parameters passed:
6663 * - Sequence to enable CLKOUT_DP
6664 * - Sequence to enable CLKOUT_DP without spread
6665 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6667 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6673 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6675 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6676 with_fdi
, "LP PCH doesn't have FDI\n"))
6679 mutex_lock(&dev_priv
->dpio_lock
);
6681 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6682 tmp
&= ~SBI_SSCCTL_DISABLE
;
6683 tmp
|= SBI_SSCCTL_PATHALT
;
6684 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6689 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6690 tmp
&= ~SBI_SSCCTL_PATHALT
;
6691 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6694 lpt_reset_fdi_mphy(dev_priv
);
6695 lpt_program_fdi_mphy(dev_priv
);
6699 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6700 SBI_GEN0
: SBI_DBUFF0
;
6701 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6702 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6703 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6705 mutex_unlock(&dev_priv
->dpio_lock
);
6708 /* Sequence to disable CLKOUT_DP */
6709 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6714 mutex_lock(&dev_priv
->dpio_lock
);
6716 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6717 SBI_GEN0
: SBI_DBUFF0
;
6718 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6719 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6720 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6722 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6723 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6724 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6725 tmp
|= SBI_SSCCTL_PATHALT
;
6726 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6729 tmp
|= SBI_SSCCTL_DISABLE
;
6730 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6733 mutex_unlock(&dev_priv
->dpio_lock
);
6736 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6738 struct intel_encoder
*encoder
;
6739 bool has_vga
= false;
6741 for_each_intel_encoder(dev
, encoder
) {
6742 switch (encoder
->type
) {
6743 case INTEL_OUTPUT_ANALOG
:
6750 lpt_enable_clkout_dp(dev
, true, true);
6752 lpt_disable_clkout_dp(dev
);
6756 * Initialize reference clocks when the driver loads
6758 void intel_init_pch_refclk(struct drm_device
*dev
)
6760 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6761 ironlake_init_pch_refclk(dev
);
6762 else if (HAS_PCH_LPT(dev
))
6763 lpt_init_pch_refclk(dev
);
6766 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6768 struct drm_device
*dev
= crtc
->dev
;
6769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6770 struct intel_encoder
*encoder
;
6771 int num_connectors
= 0;
6772 bool is_lvds
= false;
6774 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6775 switch (encoder
->type
) {
6776 case INTEL_OUTPUT_LVDS
:
6783 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6784 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6785 dev_priv
->vbt
.lvds_ssc_freq
);
6786 return dev_priv
->vbt
.lvds_ssc_freq
;
6792 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6794 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6795 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6796 int pipe
= intel_crtc
->pipe
;
6801 switch (intel_crtc
->config
.pipe_bpp
) {
6803 val
|= PIPECONF_6BPC
;
6806 val
|= PIPECONF_8BPC
;
6809 val
|= PIPECONF_10BPC
;
6812 val
|= PIPECONF_12BPC
;
6815 /* Case prevented by intel_choose_pipe_bpp_dither. */
6819 if (intel_crtc
->config
.dither
)
6820 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6822 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6823 val
|= PIPECONF_INTERLACED_ILK
;
6825 val
|= PIPECONF_PROGRESSIVE
;
6827 if (intel_crtc
->config
.limited_color_range
)
6828 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6830 I915_WRITE(PIPECONF(pipe
), val
);
6831 POSTING_READ(PIPECONF(pipe
));
6835 * Set up the pipe CSC unit.
6837 * Currently only full range RGB to limited range RGB conversion
6838 * is supported, but eventually this should handle various
6839 * RGB<->YCbCr scenarios as well.
6841 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6843 struct drm_device
*dev
= crtc
->dev
;
6844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6845 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6846 int pipe
= intel_crtc
->pipe
;
6847 uint16_t coeff
= 0x7800; /* 1.0 */
6850 * TODO: Check what kind of values actually come out of the pipe
6851 * with these coeff/postoff values and adjust to get the best
6852 * accuracy. Perhaps we even need to take the bpc value into
6856 if (intel_crtc
->config
.limited_color_range
)
6857 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6860 * GY/GU and RY/RU should be the other way around according
6861 * to BSpec, but reality doesn't agree. Just set them up in
6862 * a way that results in the correct picture.
6864 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6865 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6867 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6868 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6870 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6871 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6873 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6874 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6875 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6877 if (INTEL_INFO(dev
)->gen
> 6) {
6878 uint16_t postoff
= 0;
6880 if (intel_crtc
->config
.limited_color_range
)
6881 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6883 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6884 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6885 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6887 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6889 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6891 if (intel_crtc
->config
.limited_color_range
)
6892 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6894 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6898 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6900 struct drm_device
*dev
= crtc
->dev
;
6901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6902 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6903 enum pipe pipe
= intel_crtc
->pipe
;
6904 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6909 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6910 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6912 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6913 val
|= PIPECONF_INTERLACED_ILK
;
6915 val
|= PIPECONF_PROGRESSIVE
;
6917 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6918 POSTING_READ(PIPECONF(cpu_transcoder
));
6920 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6921 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6923 if (IS_BROADWELL(dev
)) {
6926 switch (intel_crtc
->config
.pipe_bpp
) {
6928 val
|= PIPEMISC_DITHER_6_BPC
;
6931 val
|= PIPEMISC_DITHER_8_BPC
;
6934 val
|= PIPEMISC_DITHER_10_BPC
;
6937 val
|= PIPEMISC_DITHER_12_BPC
;
6940 /* Case prevented by pipe_config_set_bpp. */
6944 if (intel_crtc
->config
.dither
)
6945 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6947 I915_WRITE(PIPEMISC(pipe
), val
);
6951 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6952 intel_clock_t
*clock
,
6953 bool *has_reduced_clock
,
6954 intel_clock_t
*reduced_clock
)
6956 struct drm_device
*dev
= crtc
->dev
;
6957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6958 struct intel_encoder
*intel_encoder
;
6960 const intel_limit_t
*limit
;
6961 bool ret
, is_lvds
= false;
6963 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6964 switch (intel_encoder
->type
) {
6965 case INTEL_OUTPUT_LVDS
:
6971 refclk
= ironlake_get_refclk(crtc
);
6974 * Returns a set of divisors for the desired target clock with the given
6975 * refclk, or FALSE. The returned values represent the clock equation:
6976 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6978 limit
= intel_limit(crtc
, refclk
);
6979 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6980 to_intel_crtc(crtc
)->config
.port_clock
,
6981 refclk
, NULL
, clock
);
6985 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6987 * Ensure we match the reduced clock's P to the target clock.
6988 * If the clocks don't match, we can't switch the display clock
6989 * by using the FP0/FP1. In such case we will disable the LVDS
6990 * downclock feature.
6992 *has_reduced_clock
=
6993 dev_priv
->display
.find_dpll(limit
, crtc
,
6994 dev_priv
->lvds_downclock
,
7002 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7005 * Account for spread spectrum to avoid
7006 * oversubscribing the link. Max center spread
7007 * is 2.5%; use 5% for safety's sake.
7009 u32 bps
= target_clock
* bpp
* 21 / 20;
7010 return DIV_ROUND_UP(bps
, link_bw
* 8);
7013 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7015 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7018 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7020 intel_clock_t
*reduced_clock
, u32
*fp2
)
7022 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7023 struct drm_device
*dev
= crtc
->dev
;
7024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7025 struct intel_encoder
*intel_encoder
;
7027 int factor
, num_connectors
= 0;
7028 bool is_lvds
= false, is_sdvo
= false;
7030 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7031 switch (intel_encoder
->type
) {
7032 case INTEL_OUTPUT_LVDS
:
7035 case INTEL_OUTPUT_SDVO
:
7036 case INTEL_OUTPUT_HDMI
:
7044 /* Enable autotuning of the PLL clock (if permissible) */
7047 if ((intel_panel_use_ssc(dev_priv
) &&
7048 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7049 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7051 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7054 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7057 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7063 dpll
|= DPLLB_MODE_LVDS
;
7065 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7067 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7068 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7071 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7072 if (intel_crtc
->config
.has_dp_encoder
)
7073 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7075 /* compute bitmask from p1 value */
7076 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7078 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7080 switch (intel_crtc
->config
.dpll
.p2
) {
7082 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7085 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7088 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7091 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7095 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7096 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7098 dpll
|= PLL_REF_INPUT_DREFCLK
;
7100 return dpll
| DPLL_VCO_ENABLE
;
7103 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7105 struct drm_framebuffer
*fb
)
7107 struct drm_device
*dev
= crtc
->dev
;
7108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7109 int num_connectors
= 0;
7110 intel_clock_t clock
, reduced_clock
;
7111 u32 dpll
= 0, fp
= 0, fp2
= 0;
7112 bool ok
, has_reduced_clock
= false;
7113 bool is_lvds
= false;
7114 struct intel_encoder
*encoder
;
7115 struct intel_shared_dpll
*pll
;
7117 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7118 switch (encoder
->type
) {
7119 case INTEL_OUTPUT_LVDS
:
7127 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7128 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7130 ok
= ironlake_compute_clocks(crtc
, &clock
,
7131 &has_reduced_clock
, &reduced_clock
);
7132 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7133 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7136 /* Compat-code for transition, will disappear. */
7137 if (!intel_crtc
->config
.clock_set
) {
7138 intel_crtc
->config
.dpll
.n
= clock
.n
;
7139 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7140 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7141 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7142 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7145 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7146 if (intel_crtc
->config
.has_pch_encoder
) {
7147 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7148 if (has_reduced_clock
)
7149 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7151 dpll
= ironlake_compute_dpll(intel_crtc
,
7152 &fp
, &reduced_clock
,
7153 has_reduced_clock
? &fp2
: NULL
);
7155 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7156 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7157 if (has_reduced_clock
)
7158 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7160 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7162 pll
= intel_get_shared_dpll(intel_crtc
);
7164 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7165 pipe_name(intel_crtc
->pipe
));
7169 intel_put_shared_dpll(intel_crtc
);
7171 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7172 intel_crtc
->lowfreq_avail
= true;
7174 intel_crtc
->lowfreq_avail
= false;
7179 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7180 struct intel_link_m_n
*m_n
)
7182 struct drm_device
*dev
= crtc
->base
.dev
;
7183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7184 enum pipe pipe
= crtc
->pipe
;
7186 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7187 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7188 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7190 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7191 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7192 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7195 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7196 enum transcoder transcoder
,
7197 struct intel_link_m_n
*m_n
,
7198 struct intel_link_m_n
*m2_n2
)
7200 struct drm_device
*dev
= crtc
->base
.dev
;
7201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7202 enum pipe pipe
= crtc
->pipe
;
7204 if (INTEL_INFO(dev
)->gen
>= 5) {
7205 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7206 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7207 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7209 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7210 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7211 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7212 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7213 * gen < 8) and if DRRS is supported (to make sure the
7214 * registers are not unnecessarily read).
7216 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7217 crtc
->config
.has_drrs
) {
7218 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7219 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7220 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7222 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7223 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7224 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7227 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7228 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7229 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7231 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7232 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7233 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7237 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7238 struct intel_crtc_config
*pipe_config
)
7240 if (crtc
->config
.has_pch_encoder
)
7241 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7243 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7244 &pipe_config
->dp_m_n
,
7245 &pipe_config
->dp_m2_n2
);
7248 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7249 struct intel_crtc_config
*pipe_config
)
7251 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7252 &pipe_config
->fdi_m_n
, NULL
);
7255 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7256 struct intel_crtc_config
*pipe_config
)
7258 struct drm_device
*dev
= crtc
->base
.dev
;
7259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7262 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7264 if (tmp
& PF_ENABLE
) {
7265 pipe_config
->pch_pfit
.enabled
= true;
7266 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7267 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7269 /* We currently do not free assignements of panel fitters on
7270 * ivb/hsw (since we don't use the higher upscaling modes which
7271 * differentiates them) so just WARN about this case for now. */
7273 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7274 PF_PIPE_SEL_IVB(crtc
->pipe
));
7279 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7280 struct intel_plane_config
*plane_config
)
7282 struct drm_device
*dev
= crtc
->base
.dev
;
7283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7284 u32 val
, base
, offset
;
7285 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7286 int fourcc
, pixel_format
;
7289 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7290 if (!crtc
->base
.primary
->fb
) {
7291 DRM_DEBUG_KMS("failed to alloc fb\n");
7295 val
= I915_READ(DSPCNTR(plane
));
7297 if (INTEL_INFO(dev
)->gen
>= 4)
7298 if (val
& DISPPLANE_TILED
)
7299 plane_config
->tiled
= true;
7301 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7302 fourcc
= intel_format_to_fourcc(pixel_format
);
7303 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7304 crtc
->base
.primary
->fb
->bits_per_pixel
=
7305 drm_format_plane_cpp(fourcc
, 0) * 8;
7307 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7308 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7309 offset
= I915_READ(DSPOFFSET(plane
));
7311 if (plane_config
->tiled
)
7312 offset
= I915_READ(DSPTILEOFF(plane
));
7314 offset
= I915_READ(DSPLINOFF(plane
));
7316 plane_config
->base
= base
;
7318 val
= I915_READ(PIPESRC(pipe
));
7319 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7320 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7322 val
= I915_READ(DSPSTRIDE(pipe
));
7323 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7325 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7326 plane_config
->tiled
);
7328 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7331 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7332 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7333 crtc
->base
.primary
->fb
->height
,
7334 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7335 crtc
->base
.primary
->fb
->pitches
[0],
7336 plane_config
->size
);
7339 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7340 struct intel_crtc_config
*pipe_config
)
7342 struct drm_device
*dev
= crtc
->base
.dev
;
7343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7346 if (!intel_display_power_enabled(dev_priv
,
7347 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7350 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7351 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7353 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7354 if (!(tmp
& PIPECONF_ENABLE
))
7357 switch (tmp
& PIPECONF_BPC_MASK
) {
7359 pipe_config
->pipe_bpp
= 18;
7362 pipe_config
->pipe_bpp
= 24;
7364 case PIPECONF_10BPC
:
7365 pipe_config
->pipe_bpp
= 30;
7367 case PIPECONF_12BPC
:
7368 pipe_config
->pipe_bpp
= 36;
7374 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7375 pipe_config
->limited_color_range
= true;
7377 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7378 struct intel_shared_dpll
*pll
;
7380 pipe_config
->has_pch_encoder
= true;
7382 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7383 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7384 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7386 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7388 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7389 pipe_config
->shared_dpll
=
7390 (enum intel_dpll_id
) crtc
->pipe
;
7392 tmp
= I915_READ(PCH_DPLL_SEL
);
7393 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7394 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7396 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7399 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7401 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7402 &pipe_config
->dpll_hw_state
));
7404 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7405 pipe_config
->pixel_multiplier
=
7406 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7407 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7409 ironlake_pch_clock_get(crtc
, pipe_config
);
7411 pipe_config
->pixel_multiplier
= 1;
7414 intel_get_pipe_timings(crtc
, pipe_config
);
7416 ironlake_get_pfit_config(crtc
, pipe_config
);
7421 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7423 struct drm_device
*dev
= dev_priv
->dev
;
7424 struct intel_crtc
*crtc
;
7426 for_each_intel_crtc(dev
, crtc
)
7427 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7428 pipe_name(crtc
->pipe
));
7430 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7431 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7432 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7433 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7434 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7435 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7436 "CPU PWM1 enabled\n");
7437 if (IS_HASWELL(dev
))
7438 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7439 "CPU PWM2 enabled\n");
7440 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7441 "PCH PWM1 enabled\n");
7442 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7443 "Utility pin enabled\n");
7444 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7447 * In theory we can still leave IRQs enabled, as long as only the HPD
7448 * interrupts remain enabled. We used to check for that, but since it's
7449 * gen-specific and since we only disable LCPLL after we fully disable
7450 * the interrupts, the check below should be enough.
7452 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7455 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7457 struct drm_device
*dev
= dev_priv
->dev
;
7459 if (IS_HASWELL(dev
))
7460 return I915_READ(D_COMP_HSW
);
7462 return I915_READ(D_COMP_BDW
);
7465 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7467 struct drm_device
*dev
= dev_priv
->dev
;
7469 if (IS_HASWELL(dev
)) {
7470 mutex_lock(&dev_priv
->rps
.hw_lock
);
7471 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7473 DRM_ERROR("Failed to write to D_COMP\n");
7474 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7476 I915_WRITE(D_COMP_BDW
, val
);
7477 POSTING_READ(D_COMP_BDW
);
7482 * This function implements pieces of two sequences from BSpec:
7483 * - Sequence for display software to disable LCPLL
7484 * - Sequence for display software to allow package C8+
7485 * The steps implemented here are just the steps that actually touch the LCPLL
7486 * register. Callers should take care of disabling all the display engine
7487 * functions, doing the mode unset, fixing interrupts, etc.
7489 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7490 bool switch_to_fclk
, bool allow_power_down
)
7494 assert_can_disable_lcpll(dev_priv
);
7496 val
= I915_READ(LCPLL_CTL
);
7498 if (switch_to_fclk
) {
7499 val
|= LCPLL_CD_SOURCE_FCLK
;
7500 I915_WRITE(LCPLL_CTL
, val
);
7502 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7503 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7504 DRM_ERROR("Switching to FCLK failed\n");
7506 val
= I915_READ(LCPLL_CTL
);
7509 val
|= LCPLL_PLL_DISABLE
;
7510 I915_WRITE(LCPLL_CTL
, val
);
7511 POSTING_READ(LCPLL_CTL
);
7513 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7514 DRM_ERROR("LCPLL still locked\n");
7516 val
= hsw_read_dcomp(dev_priv
);
7517 val
|= D_COMP_COMP_DISABLE
;
7518 hsw_write_dcomp(dev_priv
, val
);
7521 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7523 DRM_ERROR("D_COMP RCOMP still in progress\n");
7525 if (allow_power_down
) {
7526 val
= I915_READ(LCPLL_CTL
);
7527 val
|= LCPLL_POWER_DOWN_ALLOW
;
7528 I915_WRITE(LCPLL_CTL
, val
);
7529 POSTING_READ(LCPLL_CTL
);
7534 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7537 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7540 unsigned long irqflags
;
7542 val
= I915_READ(LCPLL_CTL
);
7544 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7545 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7549 * Make sure we're not on PC8 state before disabling PC8, otherwise
7550 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7552 * The other problem is that hsw_restore_lcpll() is called as part of
7553 * the runtime PM resume sequence, so we can't just call
7554 * gen6_gt_force_wake_get() because that function calls
7555 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7556 * while we are on the resume sequence. So to solve this problem we have
7557 * to call special forcewake code that doesn't touch runtime PM and
7558 * doesn't enable the forcewake delayed work.
7560 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7561 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7562 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7563 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7565 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7566 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7567 I915_WRITE(LCPLL_CTL
, val
);
7568 POSTING_READ(LCPLL_CTL
);
7571 val
= hsw_read_dcomp(dev_priv
);
7572 val
|= D_COMP_COMP_FORCE
;
7573 val
&= ~D_COMP_COMP_DISABLE
;
7574 hsw_write_dcomp(dev_priv
, val
);
7576 val
= I915_READ(LCPLL_CTL
);
7577 val
&= ~LCPLL_PLL_DISABLE
;
7578 I915_WRITE(LCPLL_CTL
, val
);
7580 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7581 DRM_ERROR("LCPLL not locked yet\n");
7583 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7584 val
= I915_READ(LCPLL_CTL
);
7585 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7586 I915_WRITE(LCPLL_CTL
, val
);
7588 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7589 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7590 DRM_ERROR("Switching back to LCPLL failed\n");
7593 /* See the big comment above. */
7594 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7595 if (--dev_priv
->uncore
.forcewake_count
== 0)
7596 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7597 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7601 * Package states C8 and deeper are really deep PC states that can only be
7602 * reached when all the devices on the system allow it, so even if the graphics
7603 * device allows PC8+, it doesn't mean the system will actually get to these
7604 * states. Our driver only allows PC8+ when going into runtime PM.
7606 * The requirements for PC8+ are that all the outputs are disabled, the power
7607 * well is disabled and most interrupts are disabled, and these are also
7608 * requirements for runtime PM. When these conditions are met, we manually do
7609 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7610 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7613 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7614 * the state of some registers, so when we come back from PC8+ we need to
7615 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7616 * need to take care of the registers kept by RC6. Notice that this happens even
7617 * if we don't put the device in PCI D3 state (which is what currently happens
7618 * because of the runtime PM support).
7620 * For more, read "Display Sequences for Package C8" on the hardware
7623 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7625 struct drm_device
*dev
= dev_priv
->dev
;
7628 DRM_DEBUG_KMS("Enabling package C8+\n");
7630 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7631 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7632 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7633 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7636 lpt_disable_clkout_dp(dev
);
7637 hsw_disable_lcpll(dev_priv
, true, true);
7640 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7642 struct drm_device
*dev
= dev_priv
->dev
;
7645 DRM_DEBUG_KMS("Disabling package C8+\n");
7647 hsw_restore_lcpll(dev_priv
);
7648 lpt_init_pch_refclk(dev
);
7650 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7651 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7652 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7653 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7656 intel_prepare_ddi(dev
);
7659 static void snb_modeset_global_resources(struct drm_device
*dev
)
7661 modeset_update_crtc_power_domains(dev
);
7664 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7666 modeset_update_crtc_power_domains(dev
);
7669 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7671 struct drm_framebuffer
*fb
)
7673 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7675 if (!intel_ddi_pll_select(intel_crtc
))
7678 intel_crtc
->lowfreq_avail
= false;
7683 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7685 struct intel_crtc_config
*pipe_config
)
7687 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7689 switch (pipe_config
->ddi_pll_sel
) {
7690 case PORT_CLK_SEL_WRPLL1
:
7691 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7693 case PORT_CLK_SEL_WRPLL2
:
7694 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7699 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7700 struct intel_crtc_config
*pipe_config
)
7702 struct drm_device
*dev
= crtc
->base
.dev
;
7703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7704 struct intel_shared_dpll
*pll
;
7708 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7710 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7712 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7714 if (pipe_config
->shared_dpll
>= 0) {
7715 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7717 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7718 &pipe_config
->dpll_hw_state
));
7722 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7723 * DDI E. So just check whether this pipe is wired to DDI E and whether
7724 * the PCH transcoder is on.
7726 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7727 pipe_config
->has_pch_encoder
= true;
7729 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7730 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7731 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7733 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7737 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7738 struct intel_crtc_config
*pipe_config
)
7740 struct drm_device
*dev
= crtc
->base
.dev
;
7741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7742 enum intel_display_power_domain pfit_domain
;
7745 if (!intel_display_power_enabled(dev_priv
,
7746 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7749 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7750 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7752 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7753 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7754 enum pipe trans_edp_pipe
;
7755 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7757 WARN(1, "unknown pipe linked to edp transcoder\n");
7758 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7759 case TRANS_DDI_EDP_INPUT_A_ON
:
7760 trans_edp_pipe
= PIPE_A
;
7762 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7763 trans_edp_pipe
= PIPE_B
;
7765 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7766 trans_edp_pipe
= PIPE_C
;
7770 if (trans_edp_pipe
== crtc
->pipe
)
7771 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7774 if (!intel_display_power_enabled(dev_priv
,
7775 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7778 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7779 if (!(tmp
& PIPECONF_ENABLE
))
7782 haswell_get_ddi_port_state(crtc
, pipe_config
);
7784 intel_get_pipe_timings(crtc
, pipe_config
);
7786 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7787 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7788 ironlake_get_pfit_config(crtc
, pipe_config
);
7790 if (IS_HASWELL(dev
))
7791 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7792 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7794 pipe_config
->pixel_multiplier
= 1;
7802 } hdmi_audio_clock
[] = {
7803 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7804 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7805 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7806 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7807 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7808 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7809 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7810 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7811 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7812 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7815 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7816 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7820 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7821 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7825 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7826 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7830 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7831 hdmi_audio_clock
[i
].clock
,
7832 hdmi_audio_clock
[i
].config
);
7834 return hdmi_audio_clock
[i
].config
;
7837 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7838 int reg_eldv
, uint32_t bits_eldv
,
7839 int reg_elda
, uint32_t bits_elda
,
7842 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7843 uint8_t *eld
= connector
->eld
;
7846 i
= I915_READ(reg_eldv
);
7855 i
= I915_READ(reg_elda
);
7857 I915_WRITE(reg_elda
, i
);
7859 for (i
= 0; i
< eld
[2]; i
++)
7860 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7866 static void g4x_write_eld(struct drm_connector
*connector
,
7867 struct drm_crtc
*crtc
,
7868 struct drm_display_mode
*mode
)
7870 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7871 uint8_t *eld
= connector
->eld
;
7876 i
= I915_READ(G4X_AUD_VID_DID
);
7878 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7879 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7881 eldv
= G4X_ELDV_DEVCTG
;
7883 if (intel_eld_uptodate(connector
,
7884 G4X_AUD_CNTL_ST
, eldv
,
7885 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7886 G4X_HDMIW_HDMIEDID
))
7889 i
= I915_READ(G4X_AUD_CNTL_ST
);
7890 i
&= ~(eldv
| G4X_ELD_ADDR
);
7891 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7892 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7897 len
= min_t(uint8_t, eld
[2], len
);
7898 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7899 for (i
= 0; i
< len
; i
++)
7900 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7902 i
= I915_READ(G4X_AUD_CNTL_ST
);
7904 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7907 static void haswell_write_eld(struct drm_connector
*connector
,
7908 struct drm_crtc
*crtc
,
7909 struct drm_display_mode
*mode
)
7911 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7912 uint8_t *eld
= connector
->eld
;
7916 int pipe
= to_intel_crtc(crtc
)->pipe
;
7919 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7920 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7921 int aud_config
= HSW_AUD_CFG(pipe
);
7922 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7924 /* Audio output enable */
7925 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7926 tmp
= I915_READ(aud_cntrl_st2
);
7927 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7928 I915_WRITE(aud_cntrl_st2
, tmp
);
7929 POSTING_READ(aud_cntrl_st2
);
7931 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7933 /* Set ELD valid state */
7934 tmp
= I915_READ(aud_cntrl_st2
);
7935 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7936 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7937 I915_WRITE(aud_cntrl_st2
, tmp
);
7938 tmp
= I915_READ(aud_cntrl_st2
);
7939 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7941 /* Enable HDMI mode */
7942 tmp
= I915_READ(aud_config
);
7943 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7944 /* clear N_programing_enable and N_value_index */
7945 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7946 I915_WRITE(aud_config
, tmp
);
7948 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7950 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7952 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7953 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7954 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7955 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7957 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7960 if (intel_eld_uptodate(connector
,
7961 aud_cntrl_st2
, eldv
,
7962 aud_cntl_st
, IBX_ELD_ADDRESS
,
7966 i
= I915_READ(aud_cntrl_st2
);
7968 I915_WRITE(aud_cntrl_st2
, i
);
7973 i
= I915_READ(aud_cntl_st
);
7974 i
&= ~IBX_ELD_ADDRESS
;
7975 I915_WRITE(aud_cntl_st
, i
);
7976 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7977 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7979 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7980 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7981 for (i
= 0; i
< len
; i
++)
7982 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7984 i
= I915_READ(aud_cntrl_st2
);
7986 I915_WRITE(aud_cntrl_st2
, i
);
7990 static void ironlake_write_eld(struct drm_connector
*connector
,
7991 struct drm_crtc
*crtc
,
7992 struct drm_display_mode
*mode
)
7994 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7995 uint8_t *eld
= connector
->eld
;
8003 int pipe
= to_intel_crtc(crtc
)->pipe
;
8005 if (HAS_PCH_IBX(connector
->dev
)) {
8006 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8007 aud_config
= IBX_AUD_CFG(pipe
);
8008 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8009 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8010 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8011 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8012 aud_config
= VLV_AUD_CFG(pipe
);
8013 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8014 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8016 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8017 aud_config
= CPT_AUD_CFG(pipe
);
8018 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8019 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8022 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8024 if (IS_VALLEYVIEW(connector
->dev
)) {
8025 struct intel_encoder
*intel_encoder
;
8026 struct intel_digital_port
*intel_dig_port
;
8028 intel_encoder
= intel_attached_encoder(connector
);
8029 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8030 i
= intel_dig_port
->port
;
8032 i
= I915_READ(aud_cntl_st
);
8033 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8034 /* DIP_Port_Select, 0x1 = PortB */
8038 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8039 /* operate blindly on all ports */
8040 eldv
= IBX_ELD_VALIDB
;
8041 eldv
|= IBX_ELD_VALIDB
<< 4;
8042 eldv
|= IBX_ELD_VALIDB
<< 8;
8044 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8045 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8048 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8049 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8050 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8051 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8053 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8056 if (intel_eld_uptodate(connector
,
8057 aud_cntrl_st2
, eldv
,
8058 aud_cntl_st
, IBX_ELD_ADDRESS
,
8062 i
= I915_READ(aud_cntrl_st2
);
8064 I915_WRITE(aud_cntrl_st2
, i
);
8069 i
= I915_READ(aud_cntl_st
);
8070 i
&= ~IBX_ELD_ADDRESS
;
8071 I915_WRITE(aud_cntl_st
, i
);
8073 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8074 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8075 for (i
= 0; i
< len
; i
++)
8076 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8078 i
= I915_READ(aud_cntrl_st2
);
8080 I915_WRITE(aud_cntrl_st2
, i
);
8083 void intel_write_eld(struct drm_encoder
*encoder
,
8084 struct drm_display_mode
*mode
)
8086 struct drm_crtc
*crtc
= encoder
->crtc
;
8087 struct drm_connector
*connector
;
8088 struct drm_device
*dev
= encoder
->dev
;
8089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8091 connector
= drm_select_eld(encoder
, mode
);
8095 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8098 connector
->encoder
->base
.id
,
8099 connector
->encoder
->name
);
8101 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8103 if (dev_priv
->display
.write_eld
)
8104 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8107 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8109 struct drm_device
*dev
= crtc
->dev
;
8110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8111 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8112 uint32_t cntl
= 0, size
= 0;
8115 unsigned int width
= intel_crtc
->cursor_width
;
8116 unsigned int height
= intel_crtc
->cursor_height
;
8117 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8121 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8132 cntl
|= CURSOR_ENABLE
|
8133 CURSOR_GAMMA_ENABLE
|
8134 CURSOR_FORMAT_ARGB
|
8135 CURSOR_STRIDE(stride
);
8137 size
= (height
<< 12) | width
;
8140 if (intel_crtc
->cursor_cntl
!= 0 &&
8141 (intel_crtc
->cursor_base
!= base
||
8142 intel_crtc
->cursor_size
!= size
||
8143 intel_crtc
->cursor_cntl
!= cntl
)) {
8144 /* On these chipsets we can only modify the base/size/stride
8145 * whilst the cursor is disabled.
8147 I915_WRITE(_CURACNTR
, 0);
8148 POSTING_READ(_CURACNTR
);
8149 intel_crtc
->cursor_cntl
= 0;
8152 if (intel_crtc
->cursor_base
!= base
)
8153 I915_WRITE(_CURABASE
, base
);
8155 if (intel_crtc
->cursor_size
!= size
) {
8156 I915_WRITE(CURSIZE
, size
);
8157 intel_crtc
->cursor_size
= size
;
8160 if (intel_crtc
->cursor_cntl
!= cntl
) {
8161 I915_WRITE(_CURACNTR
, cntl
);
8162 POSTING_READ(_CURACNTR
);
8163 intel_crtc
->cursor_cntl
= cntl
;
8167 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8169 struct drm_device
*dev
= crtc
->dev
;
8170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8172 int pipe
= intel_crtc
->pipe
;
8177 cntl
= MCURSOR_GAMMA_ENABLE
;
8178 switch (intel_crtc
->cursor_width
) {
8180 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8183 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8186 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8192 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8194 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8195 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8197 if (intel_crtc
->cursor_cntl
!= cntl
) {
8198 I915_WRITE(CURCNTR(pipe
), cntl
);
8199 POSTING_READ(CURCNTR(pipe
));
8200 intel_crtc
->cursor_cntl
= cntl
;
8203 /* and commit changes on next vblank */
8204 I915_WRITE(CURBASE(pipe
), base
);
8205 POSTING_READ(CURBASE(pipe
));
8208 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8209 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8212 struct drm_device
*dev
= crtc
->dev
;
8213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8215 int pipe
= intel_crtc
->pipe
;
8216 int x
= crtc
->cursor_x
;
8217 int y
= crtc
->cursor_y
;
8218 u32 base
= 0, pos
= 0;
8221 base
= intel_crtc
->cursor_addr
;
8223 if (x
>= intel_crtc
->config
.pipe_src_w
)
8226 if (y
>= intel_crtc
->config
.pipe_src_h
)
8230 if (x
+ intel_crtc
->cursor_width
<= 0)
8233 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8236 pos
|= x
<< CURSOR_X_SHIFT
;
8239 if (y
+ intel_crtc
->cursor_height
<= 0)
8242 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8245 pos
|= y
<< CURSOR_Y_SHIFT
;
8247 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8250 I915_WRITE(CURPOS(pipe
), pos
);
8252 if (IS_845G(dev
) || IS_I865G(dev
))
8253 i845_update_cursor(crtc
, base
);
8255 i9xx_update_cursor(crtc
, base
);
8256 intel_crtc
->cursor_base
= base
;
8259 static bool cursor_size_ok(struct drm_device
*dev
,
8260 uint32_t width
, uint32_t height
)
8262 if (width
== 0 || height
== 0)
8266 * 845g/865g are special in that they are only limited by
8267 * the width of their cursors, the height is arbitrary up to
8268 * the precision of the register. Everything else requires
8269 * square cursors, limited to a few power-of-two sizes.
8271 if (IS_845G(dev
) || IS_I865G(dev
)) {
8272 if ((width
& 63) != 0)
8275 if (width
> (IS_845G(dev
) ? 64 : 512))
8281 switch (width
| height
) {
8297 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8299 * Note that the object's reference will be consumed if the update fails. If
8300 * the update succeeds, the reference of the old object (if any) will be
8303 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8304 struct drm_i915_gem_object
*obj
,
8305 uint32_t width
, uint32_t height
)
8307 struct drm_device
*dev
= crtc
->dev
;
8308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8309 enum pipe pipe
= intel_crtc
->pipe
;
8310 unsigned old_width
, stride
;
8314 /* if we want to turn off the cursor ignore width and height */
8316 DRM_DEBUG_KMS("cursor off\n");
8318 mutex_lock(&dev
->struct_mutex
);
8322 /* Check for which cursor types we support */
8323 if (!cursor_size_ok(dev
, width
, height
)) {
8324 DRM_DEBUG("Cursor dimension not supported\n");
8328 stride
= roundup_pow_of_two(width
) * 4;
8329 if (obj
->base
.size
< stride
* height
) {
8330 DRM_DEBUG_KMS("buffer is too small\n");
8335 /* we only need to pin inside GTT if cursor is non-phy */
8336 mutex_lock(&dev
->struct_mutex
);
8337 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8340 if (obj
->tiling_mode
) {
8341 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8346 /* Note that the w/a also requires 2 PTE of padding following
8347 * the bo. We currently fill all unused PTE with the shadow
8348 * page and so we should always have valid PTE following the
8349 * cursor preventing the VT-d warning.
8352 if (need_vtd_wa(dev
))
8353 alignment
= 64*1024;
8355 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8357 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8361 ret
= i915_gem_object_put_fence(obj
);
8363 DRM_DEBUG_KMS("failed to release fence for cursor");
8367 addr
= i915_gem_obj_ggtt_offset(obj
);
8369 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8370 ret
= i915_gem_object_attach_phys(obj
, align
);
8372 DRM_DEBUG_KMS("failed to attach phys object\n");
8375 addr
= obj
->phys_handle
->busaddr
;
8379 if (intel_crtc
->cursor_bo
) {
8380 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8381 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8384 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8385 INTEL_FRONTBUFFER_CURSOR(pipe
));
8386 mutex_unlock(&dev
->struct_mutex
);
8388 old_width
= intel_crtc
->cursor_width
;
8390 intel_crtc
->cursor_addr
= addr
;
8391 intel_crtc
->cursor_bo
= obj
;
8392 intel_crtc
->cursor_width
= width
;
8393 intel_crtc
->cursor_height
= height
;
8395 if (intel_crtc
->active
) {
8396 if (old_width
!= width
)
8397 intel_update_watermarks(crtc
);
8398 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8401 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8405 i915_gem_object_unpin_from_display_plane(obj
);
8407 mutex_unlock(&dev
->struct_mutex
);
8409 drm_gem_object_unreference_unlocked(&obj
->base
);
8413 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8414 u16
*blue
, uint32_t start
, uint32_t size
)
8416 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8417 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8419 for (i
= start
; i
< end
; i
++) {
8420 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8421 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8422 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8425 intel_crtc_load_lut(crtc
);
8428 /* VESA 640x480x72Hz mode to set on the pipe */
8429 static struct drm_display_mode load_detect_mode
= {
8430 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8431 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8434 struct drm_framebuffer
*
8435 __intel_framebuffer_create(struct drm_device
*dev
,
8436 struct drm_mode_fb_cmd2
*mode_cmd
,
8437 struct drm_i915_gem_object
*obj
)
8439 struct intel_framebuffer
*intel_fb
;
8442 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8444 drm_gem_object_unreference_unlocked(&obj
->base
);
8445 return ERR_PTR(-ENOMEM
);
8448 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8452 return &intel_fb
->base
;
8454 drm_gem_object_unreference_unlocked(&obj
->base
);
8457 return ERR_PTR(ret
);
8460 static struct drm_framebuffer
*
8461 intel_framebuffer_create(struct drm_device
*dev
,
8462 struct drm_mode_fb_cmd2
*mode_cmd
,
8463 struct drm_i915_gem_object
*obj
)
8465 struct drm_framebuffer
*fb
;
8468 ret
= i915_mutex_lock_interruptible(dev
);
8470 return ERR_PTR(ret
);
8471 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8472 mutex_unlock(&dev
->struct_mutex
);
8478 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8480 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8481 return ALIGN(pitch
, 64);
8485 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8487 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8488 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8491 static struct drm_framebuffer
*
8492 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8493 struct drm_display_mode
*mode
,
8496 struct drm_i915_gem_object
*obj
;
8497 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8499 obj
= i915_gem_alloc_object(dev
,
8500 intel_framebuffer_size_for_mode(mode
, bpp
));
8502 return ERR_PTR(-ENOMEM
);
8504 mode_cmd
.width
= mode
->hdisplay
;
8505 mode_cmd
.height
= mode
->vdisplay
;
8506 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8508 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8510 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8513 static struct drm_framebuffer
*
8514 mode_fits_in_fbdev(struct drm_device
*dev
,
8515 struct drm_display_mode
*mode
)
8517 #ifdef CONFIG_DRM_I915_FBDEV
8518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8519 struct drm_i915_gem_object
*obj
;
8520 struct drm_framebuffer
*fb
;
8522 if (!dev_priv
->fbdev
)
8525 if (!dev_priv
->fbdev
->fb
)
8528 obj
= dev_priv
->fbdev
->fb
->obj
;
8531 fb
= &dev_priv
->fbdev
->fb
->base
;
8532 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8533 fb
->bits_per_pixel
))
8536 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8545 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8546 struct drm_display_mode
*mode
,
8547 struct intel_load_detect_pipe
*old
,
8548 struct drm_modeset_acquire_ctx
*ctx
)
8550 struct intel_crtc
*intel_crtc
;
8551 struct intel_encoder
*intel_encoder
=
8552 intel_attached_encoder(connector
);
8553 struct drm_crtc
*possible_crtc
;
8554 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8555 struct drm_crtc
*crtc
= NULL
;
8556 struct drm_device
*dev
= encoder
->dev
;
8557 struct drm_framebuffer
*fb
;
8558 struct drm_mode_config
*config
= &dev
->mode_config
;
8561 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8562 connector
->base
.id
, connector
->name
,
8563 encoder
->base
.id
, encoder
->name
);
8566 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8571 * Algorithm gets a little messy:
8573 * - if the connector already has an assigned crtc, use it (but make
8574 * sure it's on first)
8576 * - try to find the first unused crtc that can drive this connector,
8577 * and use that if we find one
8580 /* See if we already have a CRTC for this connector */
8581 if (encoder
->crtc
) {
8582 crtc
= encoder
->crtc
;
8584 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8588 old
->dpms_mode
= connector
->dpms
;
8589 old
->load_detect_temp
= false;
8591 /* Make sure the crtc and connector are running */
8592 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8593 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8598 /* Find an unused one (if possible) */
8599 for_each_crtc(dev
, possible_crtc
) {
8601 if (!(encoder
->possible_crtcs
& (1 << i
)))
8603 if (possible_crtc
->enabled
)
8605 /* This can occur when applying the pipe A quirk on resume. */
8606 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8609 crtc
= possible_crtc
;
8614 * If we didn't find an unused CRTC, don't use any.
8617 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8621 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8624 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8625 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8627 intel_crtc
= to_intel_crtc(crtc
);
8628 intel_crtc
->new_enabled
= true;
8629 intel_crtc
->new_config
= &intel_crtc
->config
;
8630 old
->dpms_mode
= connector
->dpms
;
8631 old
->load_detect_temp
= true;
8632 old
->release_fb
= NULL
;
8635 mode
= &load_detect_mode
;
8637 /* We need a framebuffer large enough to accommodate all accesses
8638 * that the plane may generate whilst we perform load detection.
8639 * We can not rely on the fbcon either being present (we get called
8640 * during its initialisation to detect all boot displays, or it may
8641 * not even exist) or that it is large enough to satisfy the
8644 fb
= mode_fits_in_fbdev(dev
, mode
);
8646 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8647 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8648 old
->release_fb
= fb
;
8650 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8652 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8656 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8657 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8658 if (old
->release_fb
)
8659 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8663 /* let the connector get through one full cycle before testing */
8664 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8668 intel_crtc
->new_enabled
= crtc
->enabled
;
8669 if (intel_crtc
->new_enabled
)
8670 intel_crtc
->new_config
= &intel_crtc
->config
;
8672 intel_crtc
->new_config
= NULL
;
8674 if (ret
== -EDEADLK
) {
8675 drm_modeset_backoff(ctx
);
8682 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8683 struct intel_load_detect_pipe
*old
)
8685 struct intel_encoder
*intel_encoder
=
8686 intel_attached_encoder(connector
);
8687 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8688 struct drm_crtc
*crtc
= encoder
->crtc
;
8689 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8691 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8692 connector
->base
.id
, connector
->name
,
8693 encoder
->base
.id
, encoder
->name
);
8695 if (old
->load_detect_temp
) {
8696 to_intel_connector(connector
)->new_encoder
= NULL
;
8697 intel_encoder
->new_crtc
= NULL
;
8698 intel_crtc
->new_enabled
= false;
8699 intel_crtc
->new_config
= NULL
;
8700 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8702 if (old
->release_fb
) {
8703 drm_framebuffer_unregister_private(old
->release_fb
);
8704 drm_framebuffer_unreference(old
->release_fb
);
8710 /* Switch crtc and encoder back off if necessary */
8711 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8712 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8715 static int i9xx_pll_refclk(struct drm_device
*dev
,
8716 const struct intel_crtc_config
*pipe_config
)
8718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8719 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8721 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8722 return dev_priv
->vbt
.lvds_ssc_freq
;
8723 else if (HAS_PCH_SPLIT(dev
))
8725 else if (!IS_GEN2(dev
))
8731 /* Returns the clock of the currently programmed mode of the given pipe. */
8732 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8733 struct intel_crtc_config
*pipe_config
)
8735 struct drm_device
*dev
= crtc
->base
.dev
;
8736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8737 int pipe
= pipe_config
->cpu_transcoder
;
8738 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8740 intel_clock_t clock
;
8741 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8743 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8744 fp
= pipe_config
->dpll_hw_state
.fp0
;
8746 fp
= pipe_config
->dpll_hw_state
.fp1
;
8748 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8749 if (IS_PINEVIEW(dev
)) {
8750 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8751 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8753 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8754 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8757 if (!IS_GEN2(dev
)) {
8758 if (IS_PINEVIEW(dev
))
8759 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8760 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8762 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8763 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8765 switch (dpll
& DPLL_MODE_MASK
) {
8766 case DPLLB_MODE_DAC_SERIAL
:
8767 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8770 case DPLLB_MODE_LVDS
:
8771 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8775 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8776 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8780 if (IS_PINEVIEW(dev
))
8781 pineview_clock(refclk
, &clock
);
8783 i9xx_clock(refclk
, &clock
);
8785 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8786 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8789 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8790 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8792 if (lvds
& LVDS_CLKB_POWER_UP
)
8797 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8800 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8801 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8803 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8809 i9xx_clock(refclk
, &clock
);
8813 * This value includes pixel_multiplier. We will use
8814 * port_clock to compute adjusted_mode.crtc_clock in the
8815 * encoder's get_config() function.
8817 pipe_config
->port_clock
= clock
.dot
;
8820 int intel_dotclock_calculate(int link_freq
,
8821 const struct intel_link_m_n
*m_n
)
8824 * The calculation for the data clock is:
8825 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8826 * But we want to avoid losing precison if possible, so:
8827 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8829 * and the link clock is simpler:
8830 * link_clock = (m * link_clock) / n
8836 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8839 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8840 struct intel_crtc_config
*pipe_config
)
8842 struct drm_device
*dev
= crtc
->base
.dev
;
8844 /* read out port_clock from the DPLL */
8845 i9xx_crtc_clock_get(crtc
, pipe_config
);
8848 * This value does not include pixel_multiplier.
8849 * We will check that port_clock and adjusted_mode.crtc_clock
8850 * agree once we know their relationship in the encoder's
8851 * get_config() function.
8853 pipe_config
->adjusted_mode
.crtc_clock
=
8854 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8855 &pipe_config
->fdi_m_n
);
8858 /** Returns the currently programmed mode of the given pipe. */
8859 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8860 struct drm_crtc
*crtc
)
8862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8863 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8864 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8865 struct drm_display_mode
*mode
;
8866 struct intel_crtc_config pipe_config
;
8867 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8868 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8869 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8870 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8871 enum pipe pipe
= intel_crtc
->pipe
;
8873 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8878 * Construct a pipe_config sufficient for getting the clock info
8879 * back out of crtc_clock_get.
8881 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8882 * to use a real value here instead.
8884 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8885 pipe_config
.pixel_multiplier
= 1;
8886 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8887 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8888 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8889 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8891 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8892 mode
->hdisplay
= (htot
& 0xffff) + 1;
8893 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8894 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8895 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8896 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8897 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8898 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8899 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8901 drm_mode_set_name(mode
);
8906 static void intel_increase_pllclock(struct drm_device
*dev
,
8909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8910 int dpll_reg
= DPLL(pipe
);
8913 if (!HAS_GMCH_DISPLAY(dev
))
8916 if (!dev_priv
->lvds_downclock_avail
)
8919 dpll
= I915_READ(dpll_reg
);
8920 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8921 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8923 assert_panel_unlocked(dev_priv
, pipe
);
8925 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8926 I915_WRITE(dpll_reg
, dpll
);
8927 intel_wait_for_vblank(dev
, pipe
);
8929 dpll
= I915_READ(dpll_reg
);
8930 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8931 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8935 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8937 struct drm_device
*dev
= crtc
->dev
;
8938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8939 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8941 if (!HAS_GMCH_DISPLAY(dev
))
8944 if (!dev_priv
->lvds_downclock_avail
)
8948 * Since this is called by a timer, we should never get here in
8951 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8952 int pipe
= intel_crtc
->pipe
;
8953 int dpll_reg
= DPLL(pipe
);
8956 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8958 assert_panel_unlocked(dev_priv
, pipe
);
8960 dpll
= I915_READ(dpll_reg
);
8961 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8962 I915_WRITE(dpll_reg
, dpll
);
8963 intel_wait_for_vblank(dev
, pipe
);
8964 dpll
= I915_READ(dpll_reg
);
8965 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8966 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8971 void intel_mark_busy(struct drm_device
*dev
)
8973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8975 if (dev_priv
->mm
.busy
)
8978 intel_runtime_pm_get(dev_priv
);
8979 i915_update_gfx_val(dev_priv
);
8980 dev_priv
->mm
.busy
= true;
8983 void intel_mark_idle(struct drm_device
*dev
)
8985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8986 struct drm_crtc
*crtc
;
8988 if (!dev_priv
->mm
.busy
)
8991 dev_priv
->mm
.busy
= false;
8993 if (!i915
.powersave
)
8996 for_each_crtc(dev
, crtc
) {
8997 if (!crtc
->primary
->fb
)
9000 intel_decrease_pllclock(crtc
);
9003 if (INTEL_INFO(dev
)->gen
>= 6)
9004 gen6_rps_idle(dev
->dev_private
);
9007 intel_runtime_pm_put(dev_priv
);
9012 * intel_mark_fb_busy - mark given planes as busy
9014 * @frontbuffer_bits: bits for the affected planes
9015 * @ring: optional ring for asynchronous commands
9017 * This function gets called every time the screen contents change. It can be
9018 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9020 static void intel_mark_fb_busy(struct drm_device
*dev
,
9021 unsigned frontbuffer_bits
,
9022 struct intel_engine_cs
*ring
)
9024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9027 if (!i915
.powersave
)
9030 for_each_pipe(dev_priv
, pipe
) {
9031 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9034 intel_increase_pllclock(dev
, pipe
);
9035 if (ring
&& intel_fbc_enabled(dev
))
9036 ring
->fbc_dirty
= true;
9041 * intel_fb_obj_invalidate - invalidate frontbuffer object
9042 * @obj: GEM object to invalidate
9043 * @ring: set for asynchronous rendering
9045 * This function gets called every time rendering on the given object starts and
9046 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9047 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9048 * until the rendering completes or a flip on this frontbuffer plane is
9051 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9052 struct intel_engine_cs
*ring
)
9054 struct drm_device
*dev
= obj
->base
.dev
;
9055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9057 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9059 if (!obj
->frontbuffer_bits
)
9063 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9064 dev_priv
->fb_tracking
.busy_bits
9065 |= obj
->frontbuffer_bits
;
9066 dev_priv
->fb_tracking
.flip_bits
9067 &= ~obj
->frontbuffer_bits
;
9068 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9071 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9073 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9077 * intel_frontbuffer_flush - flush frontbuffer
9079 * @frontbuffer_bits: frontbuffer plane tracking bits
9081 * This function gets called every time rendering on the given planes has
9082 * completed and frontbuffer caching can be started again. Flushes will get
9083 * delayed if they're blocked by some oustanding asynchronous rendering.
9085 * Can be called without any locks held.
9087 void intel_frontbuffer_flush(struct drm_device
*dev
,
9088 unsigned frontbuffer_bits
)
9090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9092 /* Delay flushing when rings are still busy.*/
9093 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9094 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9095 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9097 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9099 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9102 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9106 * intel_fb_obj_flush - flush frontbuffer object
9107 * @obj: GEM object to flush
9108 * @retire: set when retiring asynchronous rendering
9110 * This function gets called every time rendering on the given object has
9111 * completed and frontbuffer caching can be started again. If @retire is true
9112 * then any delayed flushes will be unblocked.
9114 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9117 struct drm_device
*dev
= obj
->base
.dev
;
9118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9119 unsigned frontbuffer_bits
;
9121 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9123 if (!obj
->frontbuffer_bits
)
9126 frontbuffer_bits
= obj
->frontbuffer_bits
;
9129 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9130 /* Filter out new bits since rendering started. */
9131 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9133 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9134 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9137 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9141 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9143 * @frontbuffer_bits: frontbuffer plane tracking bits
9145 * This function gets called after scheduling a flip on @obj. The actual
9146 * frontbuffer flushing will be delayed until completion is signalled with
9147 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9148 * flush will be cancelled.
9150 * Can be called without any locks held.
9152 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9153 unsigned frontbuffer_bits
)
9155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9157 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9158 dev_priv
->fb_tracking
.flip_bits
9159 |= frontbuffer_bits
;
9160 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9164 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9166 * @frontbuffer_bits: frontbuffer plane tracking bits
9168 * This function gets called after the flip has been latched and will complete
9169 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9171 * Can be called without any locks held.
9173 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9174 unsigned frontbuffer_bits
)
9176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9178 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9179 /* Mask any cancelled flips. */
9180 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9181 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9182 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9184 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9187 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9190 struct drm_device
*dev
= crtc
->dev
;
9191 struct intel_unpin_work
*work
;
9192 unsigned long flags
;
9194 spin_lock_irqsave(&dev
->event_lock
, flags
);
9195 work
= intel_crtc
->unpin_work
;
9196 intel_crtc
->unpin_work
= NULL
;
9197 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9200 cancel_work_sync(&work
->work
);
9204 drm_crtc_cleanup(crtc
);
9209 static void intel_unpin_work_fn(struct work_struct
*__work
)
9211 struct intel_unpin_work
*work
=
9212 container_of(__work
, struct intel_unpin_work
, work
);
9213 struct drm_device
*dev
= work
->crtc
->dev
;
9214 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9216 mutex_lock(&dev
->struct_mutex
);
9217 intel_unpin_fb_obj(work
->old_fb_obj
);
9218 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9219 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9221 intel_update_fbc(dev
);
9222 mutex_unlock(&dev
->struct_mutex
);
9224 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9226 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9227 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9232 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9233 struct drm_crtc
*crtc
)
9235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9237 struct intel_unpin_work
*work
;
9238 unsigned long flags
;
9240 /* Ignore early vblank irqs */
9241 if (intel_crtc
== NULL
)
9244 spin_lock_irqsave(&dev
->event_lock
, flags
);
9245 work
= intel_crtc
->unpin_work
;
9247 /* Ensure we don't miss a work->pending update ... */
9250 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9251 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9255 /* and that the unpin work is consistent wrt ->pending. */
9258 intel_crtc
->unpin_work
= NULL
;
9261 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
9263 drm_crtc_vblank_put(crtc
);
9265 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9267 wake_up_all(&dev_priv
->pending_flip_queue
);
9269 queue_work(dev_priv
->wq
, &work
->work
);
9271 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
9274 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9277 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9279 do_intel_finish_page_flip(dev
, crtc
);
9282 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9285 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9287 do_intel_finish_page_flip(dev
, crtc
);
9290 /* Is 'a' after or equal to 'b'? */
9291 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9293 return !((a
- b
) & 0x80000000);
9296 static bool page_flip_finished(struct intel_crtc
*crtc
)
9298 struct drm_device
*dev
= crtc
->base
.dev
;
9299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9302 * The relevant registers doen't exist on pre-ctg.
9303 * As the flip done interrupt doesn't trigger for mmio
9304 * flips on gmch platforms, a flip count check isn't
9305 * really needed there. But since ctg has the registers,
9306 * include it in the check anyway.
9308 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9312 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9313 * used the same base address. In that case the mmio flip might
9314 * have completed, but the CS hasn't even executed the flip yet.
9316 * A flip count check isn't enough as the CS might have updated
9317 * the base address just after start of vblank, but before we
9318 * managed to process the interrupt. This means we'd complete the
9321 * Combining both checks should get us a good enough result. It may
9322 * still happen that the CS flip has been executed, but has not
9323 * yet actually completed. But in case the base address is the same
9324 * anyway, we don't really care.
9326 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9327 crtc
->unpin_work
->gtt_offset
&&
9328 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9329 crtc
->unpin_work
->flip_count
);
9332 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9335 struct intel_crtc
*intel_crtc
=
9336 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9337 unsigned long flags
;
9339 /* NB: An MMIO update of the plane base pointer will also
9340 * generate a page-flip completion irq, i.e. every modeset
9341 * is also accompanied by a spurious intel_prepare_page_flip().
9343 spin_lock_irqsave(&dev
->event_lock
, flags
);
9344 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9345 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9346 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9349 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9351 /* Ensure that the work item is consistent when activating it ... */
9353 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9354 /* and that it is marked active as soon as the irq could fire. */
9358 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9359 struct drm_crtc
*crtc
,
9360 struct drm_framebuffer
*fb
,
9361 struct drm_i915_gem_object
*obj
,
9362 struct intel_engine_cs
*ring
,
9365 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9369 ret
= intel_ring_begin(ring
, 6);
9373 /* Can't queue multiple flips, so wait for the previous
9374 * one to finish before executing the next.
9376 if (intel_crtc
->plane
)
9377 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9379 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9380 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9381 intel_ring_emit(ring
, MI_NOOP
);
9382 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9383 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9384 intel_ring_emit(ring
, fb
->pitches
[0]);
9385 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9386 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9388 intel_mark_page_flip_active(intel_crtc
);
9389 __intel_ring_advance(ring
);
9393 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9394 struct drm_crtc
*crtc
,
9395 struct drm_framebuffer
*fb
,
9396 struct drm_i915_gem_object
*obj
,
9397 struct intel_engine_cs
*ring
,
9400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9404 ret
= intel_ring_begin(ring
, 6);
9408 if (intel_crtc
->plane
)
9409 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9411 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9412 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9413 intel_ring_emit(ring
, MI_NOOP
);
9414 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9415 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9416 intel_ring_emit(ring
, fb
->pitches
[0]);
9417 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9418 intel_ring_emit(ring
, MI_NOOP
);
9420 intel_mark_page_flip_active(intel_crtc
);
9421 __intel_ring_advance(ring
);
9425 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9426 struct drm_crtc
*crtc
,
9427 struct drm_framebuffer
*fb
,
9428 struct drm_i915_gem_object
*obj
,
9429 struct intel_engine_cs
*ring
,
9432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9433 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9434 uint32_t pf
, pipesrc
;
9437 ret
= intel_ring_begin(ring
, 4);
9441 /* i965+ uses the linear or tiled offsets from the
9442 * Display Registers (which do not change across a page-flip)
9443 * so we need only reprogram the base address.
9445 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9446 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9447 intel_ring_emit(ring
, fb
->pitches
[0]);
9448 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9451 /* XXX Enabling the panel-fitter across page-flip is so far
9452 * untested on non-native modes, so ignore it for now.
9453 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9456 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9457 intel_ring_emit(ring
, pf
| pipesrc
);
9459 intel_mark_page_flip_active(intel_crtc
);
9460 __intel_ring_advance(ring
);
9464 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9465 struct drm_crtc
*crtc
,
9466 struct drm_framebuffer
*fb
,
9467 struct drm_i915_gem_object
*obj
,
9468 struct intel_engine_cs
*ring
,
9471 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9472 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9473 uint32_t pf
, pipesrc
;
9476 ret
= intel_ring_begin(ring
, 4);
9480 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9481 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9482 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9483 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9485 /* Contrary to the suggestions in the documentation,
9486 * "Enable Panel Fitter" does not seem to be required when page
9487 * flipping with a non-native mode, and worse causes a normal
9489 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9492 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9493 intel_ring_emit(ring
, pf
| pipesrc
);
9495 intel_mark_page_flip_active(intel_crtc
);
9496 __intel_ring_advance(ring
);
9500 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9501 struct drm_crtc
*crtc
,
9502 struct drm_framebuffer
*fb
,
9503 struct drm_i915_gem_object
*obj
,
9504 struct intel_engine_cs
*ring
,
9507 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9508 uint32_t plane_bit
= 0;
9511 switch (intel_crtc
->plane
) {
9513 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9516 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9519 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9522 WARN_ONCE(1, "unknown plane in flip command\n");
9527 if (ring
->id
== RCS
) {
9530 * On Gen 8, SRM is now taking an extra dword to accommodate
9531 * 48bits addresses, and we need a NOOP for the batch size to
9539 * BSpec MI_DISPLAY_FLIP for IVB:
9540 * "The full packet must be contained within the same cache line."
9542 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9543 * cacheline, if we ever start emitting more commands before
9544 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9545 * then do the cacheline alignment, and finally emit the
9548 ret
= intel_ring_cacheline_align(ring
);
9552 ret
= intel_ring_begin(ring
, len
);
9556 /* Unmask the flip-done completion message. Note that the bspec says that
9557 * we should do this for both the BCS and RCS, and that we must not unmask
9558 * more than one flip event at any time (or ensure that one flip message
9559 * can be sent by waiting for flip-done prior to queueing new flips).
9560 * Experimentation says that BCS works despite DERRMR masking all
9561 * flip-done completion events and that unmasking all planes at once
9562 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9563 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9565 if (ring
->id
== RCS
) {
9566 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9567 intel_ring_emit(ring
, DERRMR
);
9568 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9569 DERRMR_PIPEB_PRI_FLIP_DONE
|
9570 DERRMR_PIPEC_PRI_FLIP_DONE
));
9572 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9573 MI_SRM_LRM_GLOBAL_GTT
);
9575 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9576 MI_SRM_LRM_GLOBAL_GTT
);
9577 intel_ring_emit(ring
, DERRMR
);
9578 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9580 intel_ring_emit(ring
, 0);
9581 intel_ring_emit(ring
, MI_NOOP
);
9585 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9586 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9587 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9588 intel_ring_emit(ring
, (MI_NOOP
));
9590 intel_mark_page_flip_active(intel_crtc
);
9591 __intel_ring_advance(ring
);
9595 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9596 struct drm_i915_gem_object
*obj
)
9599 * This is not being used for older platforms, because
9600 * non-availability of flip done interrupt forces us to use
9601 * CS flips. Older platforms derive flip done using some clever
9602 * tricks involving the flip_pending status bits and vblank irqs.
9603 * So using MMIO flips there would disrupt this mechanism.
9609 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9612 if (i915
.use_mmio_flip
< 0)
9614 else if (i915
.use_mmio_flip
> 0)
9616 else if (i915
.enable_execlists
)
9619 return ring
!= obj
->ring
;
9622 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9624 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9626 struct intel_framebuffer
*intel_fb
=
9627 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9628 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9632 intel_mark_page_flip_active(intel_crtc
);
9634 reg
= DSPCNTR(intel_crtc
->plane
);
9635 dspcntr
= I915_READ(reg
);
9637 if (INTEL_INFO(dev
)->gen
>= 4) {
9638 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9639 dspcntr
|= DISPPLANE_TILED
;
9641 dspcntr
&= ~DISPPLANE_TILED
;
9643 I915_WRITE(reg
, dspcntr
);
9645 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9646 intel_crtc
->unpin_work
->gtt_offset
);
9647 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9650 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9652 struct intel_engine_cs
*ring
;
9655 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9657 if (!obj
->last_write_seqno
)
9662 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9663 obj
->last_write_seqno
))
9666 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9670 if (WARN_ON(!ring
->irq_get(ring
)))
9676 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9678 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9679 struct intel_crtc
*intel_crtc
;
9680 unsigned long irq_flags
;
9683 seqno
= ring
->get_seqno(ring
, false);
9685 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9686 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9687 struct intel_mmio_flip
*mmio_flip
;
9689 mmio_flip
= &intel_crtc
->mmio_flip
;
9690 if (mmio_flip
->seqno
== 0)
9693 if (ring
->id
!= mmio_flip
->ring_id
)
9696 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9697 intel_do_mmio_flip(intel_crtc
);
9698 mmio_flip
->seqno
= 0;
9699 ring
->irq_put(ring
);
9702 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9705 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9706 struct drm_crtc
*crtc
,
9707 struct drm_framebuffer
*fb
,
9708 struct drm_i915_gem_object
*obj
,
9709 struct intel_engine_cs
*ring
,
9712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9713 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9714 unsigned long irq_flags
;
9717 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9720 ret
= intel_postpone_flip(obj
);
9724 intel_do_mmio_flip(intel_crtc
);
9728 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9729 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9730 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9731 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9734 * Double check to catch cases where irq fired before
9735 * mmio flip data was ready
9737 intel_notify_mmio_flip(obj
->ring
);
9741 static int intel_default_queue_flip(struct drm_device
*dev
,
9742 struct drm_crtc
*crtc
,
9743 struct drm_framebuffer
*fb
,
9744 struct drm_i915_gem_object
*obj
,
9745 struct intel_engine_cs
*ring
,
9751 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9752 struct drm_framebuffer
*fb
,
9753 struct drm_pending_vblank_event
*event
,
9754 uint32_t page_flip_flags
)
9756 struct drm_device
*dev
= crtc
->dev
;
9757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9758 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9759 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9760 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9761 enum pipe pipe
= intel_crtc
->pipe
;
9762 struct intel_unpin_work
*work
;
9763 struct intel_engine_cs
*ring
;
9764 unsigned long flags
;
9767 //trigger software GT busyness calculation
9768 gen8_flip_interrupt(dev
);
9771 * drm_mode_page_flip_ioctl() should already catch this, but double
9772 * check to be safe. In the future we may enable pageflipping from
9773 * a disabled primary plane.
9775 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9778 /* Can't change pixel format via MI display flips. */
9779 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9783 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9784 * Note that pitch changes could also affect these register.
9786 if (INTEL_INFO(dev
)->gen
> 3 &&
9787 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9788 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9791 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9794 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9798 work
->event
= event
;
9800 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9801 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9803 ret
= drm_crtc_vblank_get(crtc
);
9807 /* We borrow the event spin lock for protecting unpin_work */
9808 spin_lock_irqsave(&dev
->event_lock
, flags
);
9809 if (intel_crtc
->unpin_work
) {
9810 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9812 drm_crtc_vblank_put(crtc
);
9814 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9817 intel_crtc
->unpin_work
= work
;
9818 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9820 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9821 flush_workqueue(dev_priv
->wq
);
9823 ret
= i915_mutex_lock_interruptible(dev
);
9827 /* Reference the objects for the scheduled work. */
9828 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9829 drm_gem_object_reference(&obj
->base
);
9831 crtc
->primary
->fb
= fb
;
9833 work
->pending_flip_obj
= obj
;
9835 work
->enable_stall_check
= true;
9837 atomic_inc(&intel_crtc
->unpin_work_count
);
9838 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9840 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9841 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9843 if (IS_VALLEYVIEW(dev
)) {
9844 ring
= &dev_priv
->ring
[BCS
];
9845 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9846 /* vlv: DISPLAY_FLIP fails to change tiling */
9848 } else if (IS_IVYBRIDGE(dev
)) {
9849 ring
= &dev_priv
->ring
[BCS
];
9850 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9852 if (ring
== NULL
|| ring
->id
!= RCS
)
9853 ring
= &dev_priv
->ring
[BCS
];
9855 ring
= &dev_priv
->ring
[RCS
];
9858 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9860 goto cleanup_pending
;
9863 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9865 if (use_mmio_flip(ring
, obj
))
9866 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9869 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9874 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9875 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9877 intel_disable_fbc(dev
);
9878 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9879 mutex_unlock(&dev
->struct_mutex
);
9881 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9886 intel_unpin_fb_obj(obj
);
9888 atomic_dec(&intel_crtc
->unpin_work_count
);
9889 crtc
->primary
->fb
= old_fb
;
9890 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9891 drm_gem_object_unreference(&obj
->base
);
9892 mutex_unlock(&dev
->struct_mutex
);
9895 spin_lock_irqsave(&dev
->event_lock
, flags
);
9896 intel_crtc
->unpin_work
= NULL
;
9897 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9899 drm_crtc_vblank_put(crtc
);
9905 intel_crtc_wait_for_pending_flips(crtc
);
9906 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9907 if (ret
== 0 && event
)
9908 drm_send_vblank_event(dev
, pipe
, event
);
9913 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9914 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9915 .load_lut
= intel_crtc_load_lut
,
9919 * intel_modeset_update_staged_output_state
9921 * Updates the staged output configuration state, e.g. after we've read out the
9924 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9926 struct intel_crtc
*crtc
;
9927 struct intel_encoder
*encoder
;
9928 struct intel_connector
*connector
;
9930 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9932 connector
->new_encoder
=
9933 to_intel_encoder(connector
->base
.encoder
);
9936 for_each_intel_encoder(dev
, encoder
) {
9938 to_intel_crtc(encoder
->base
.crtc
);
9941 for_each_intel_crtc(dev
, crtc
) {
9942 crtc
->new_enabled
= crtc
->base
.enabled
;
9944 if (crtc
->new_enabled
)
9945 crtc
->new_config
= &crtc
->config
;
9947 crtc
->new_config
= NULL
;
9952 * intel_modeset_commit_output_state
9954 * This function copies the stage display pipe configuration to the real one.
9956 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9958 struct intel_crtc
*crtc
;
9959 struct intel_encoder
*encoder
;
9960 struct intel_connector
*connector
;
9962 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9964 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9967 for_each_intel_encoder(dev
, encoder
) {
9968 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9971 for_each_intel_crtc(dev
, crtc
) {
9972 crtc
->base
.enabled
= crtc
->new_enabled
;
9977 connected_sink_compute_bpp(struct intel_connector
*connector
,
9978 struct intel_crtc_config
*pipe_config
)
9980 int bpp
= pipe_config
->pipe_bpp
;
9982 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9983 connector
->base
.base
.id
,
9984 connector
->base
.name
);
9986 /* Don't use an invalid EDID bpc value */
9987 if (connector
->base
.display_info
.bpc
&&
9988 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9989 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9990 bpp
, connector
->base
.display_info
.bpc
*3);
9991 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9994 /* Clamp bpp to 8 on screens without EDID 1.4 */
9995 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9996 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9998 pipe_config
->pipe_bpp
= 24;
10003 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10004 struct drm_framebuffer
*fb
,
10005 struct intel_crtc_config
*pipe_config
)
10007 struct drm_device
*dev
= crtc
->base
.dev
;
10008 struct intel_connector
*connector
;
10011 switch (fb
->pixel_format
) {
10012 case DRM_FORMAT_C8
:
10013 bpp
= 8*3; /* since we go through a colormap */
10015 case DRM_FORMAT_XRGB1555
:
10016 case DRM_FORMAT_ARGB1555
:
10017 /* checked in intel_framebuffer_init already */
10018 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10020 case DRM_FORMAT_RGB565
:
10021 bpp
= 6*3; /* min is 18bpp */
10023 case DRM_FORMAT_XBGR8888
:
10024 case DRM_FORMAT_ABGR8888
:
10025 /* checked in intel_framebuffer_init already */
10026 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10028 case DRM_FORMAT_XRGB8888
:
10029 case DRM_FORMAT_ARGB8888
:
10032 case DRM_FORMAT_XRGB2101010
:
10033 case DRM_FORMAT_ARGB2101010
:
10034 case DRM_FORMAT_XBGR2101010
:
10035 case DRM_FORMAT_ABGR2101010
:
10036 /* checked in intel_framebuffer_init already */
10037 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10041 /* TODO: gen4+ supports 16 bpc floating point, too. */
10043 DRM_DEBUG_KMS("unsupported depth\n");
10047 pipe_config
->pipe_bpp
= bpp
;
10049 /* Clamp display bpp to EDID value */
10050 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10052 if (!connector
->new_encoder
||
10053 connector
->new_encoder
->new_crtc
!= crtc
)
10056 connected_sink_compute_bpp(connector
, pipe_config
);
10062 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10064 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10065 "type: 0x%x flags: 0x%x\n",
10067 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10068 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10069 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10070 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10073 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10074 struct intel_crtc_config
*pipe_config
,
10075 const char *context
)
10077 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10078 context
, pipe_name(crtc
->pipe
));
10080 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10081 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10082 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10083 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10084 pipe_config
->has_pch_encoder
,
10085 pipe_config
->fdi_lanes
,
10086 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10087 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10088 pipe_config
->fdi_m_n
.tu
);
10089 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10090 pipe_config
->has_dp_encoder
,
10091 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10092 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10093 pipe_config
->dp_m_n
.tu
);
10095 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10096 pipe_config
->has_dp_encoder
,
10097 pipe_config
->dp_m2_n2
.gmch_m
,
10098 pipe_config
->dp_m2_n2
.gmch_n
,
10099 pipe_config
->dp_m2_n2
.link_m
,
10100 pipe_config
->dp_m2_n2
.link_n
,
10101 pipe_config
->dp_m2_n2
.tu
);
10103 DRM_DEBUG_KMS("requested mode:\n");
10104 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10105 DRM_DEBUG_KMS("adjusted mode:\n");
10106 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10107 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10108 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10109 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10110 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10111 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10112 pipe_config
->gmch_pfit
.control
,
10113 pipe_config
->gmch_pfit
.pgm_ratios
,
10114 pipe_config
->gmch_pfit
.lvds_border_bits
);
10115 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10116 pipe_config
->pch_pfit
.pos
,
10117 pipe_config
->pch_pfit
.size
,
10118 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10119 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10120 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10123 static bool encoders_cloneable(const struct intel_encoder
*a
,
10124 const struct intel_encoder
*b
)
10126 /* masks could be asymmetric, so check both ways */
10127 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10128 b
->cloneable
& (1 << a
->type
));
10131 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10132 struct intel_encoder
*encoder
)
10134 struct drm_device
*dev
= crtc
->base
.dev
;
10135 struct intel_encoder
*source_encoder
;
10137 for_each_intel_encoder(dev
, source_encoder
) {
10138 if (source_encoder
->new_crtc
!= crtc
)
10141 if (!encoders_cloneable(encoder
, source_encoder
))
10148 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10150 struct drm_device
*dev
= crtc
->base
.dev
;
10151 struct intel_encoder
*encoder
;
10153 for_each_intel_encoder(dev
, encoder
) {
10154 if (encoder
->new_crtc
!= crtc
)
10157 if (!check_single_encoder_cloning(crtc
, encoder
))
10164 static struct intel_crtc_config
*
10165 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10166 struct drm_framebuffer
*fb
,
10167 struct drm_display_mode
*mode
)
10169 struct drm_device
*dev
= crtc
->dev
;
10170 struct intel_encoder
*encoder
;
10171 struct intel_crtc_config
*pipe_config
;
10172 int plane_bpp
, ret
= -EINVAL
;
10175 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10176 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10177 return ERR_PTR(-EINVAL
);
10180 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10182 return ERR_PTR(-ENOMEM
);
10184 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10185 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10187 pipe_config
->cpu_transcoder
=
10188 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10189 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10192 * Sanitize sync polarity flags based on requested ones. If neither
10193 * positive or negative polarity is requested, treat this as meaning
10194 * negative polarity.
10196 if (!(pipe_config
->adjusted_mode
.flags
&
10197 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10198 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10200 if (!(pipe_config
->adjusted_mode
.flags
&
10201 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10202 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10204 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10205 * plane pixel format and any sink constraints into account. Returns the
10206 * source plane bpp so that dithering can be selected on mismatches
10207 * after encoders and crtc also have had their say. */
10208 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10214 * Determine the real pipe dimensions. Note that stereo modes can
10215 * increase the actual pipe size due to the frame doubling and
10216 * insertion of additional space for blanks between the frame. This
10217 * is stored in the crtc timings. We use the requested mode to do this
10218 * computation to clearly distinguish it from the adjusted mode, which
10219 * can be changed by the connectors in the below retry loop.
10221 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10222 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10223 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10226 /* Ensure the port clock defaults are reset when retrying. */
10227 pipe_config
->port_clock
= 0;
10228 pipe_config
->pixel_multiplier
= 1;
10230 /* Fill in default crtc timings, allow encoders to overwrite them. */
10231 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10233 /* Pass our mode to the connectors and the CRTC to give them a chance to
10234 * adjust it according to limitations or connector properties, and also
10235 * a chance to reject the mode entirely.
10237 for_each_intel_encoder(dev
, encoder
) {
10239 if (&encoder
->new_crtc
->base
!= crtc
)
10242 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10243 DRM_DEBUG_KMS("Encoder config failure\n");
10248 /* Set default port clock if not overwritten by the encoder. Needs to be
10249 * done afterwards in case the encoder adjusts the mode. */
10250 if (!pipe_config
->port_clock
)
10251 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10252 * pipe_config
->pixel_multiplier
;
10254 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10256 DRM_DEBUG_KMS("CRTC fixup failed\n");
10260 if (ret
== RETRY
) {
10261 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10266 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10268 goto encoder_retry
;
10271 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10272 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10273 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10275 return pipe_config
;
10277 kfree(pipe_config
);
10278 return ERR_PTR(ret
);
10281 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10282 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10284 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10285 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10287 struct intel_crtc
*intel_crtc
;
10288 struct drm_device
*dev
= crtc
->dev
;
10289 struct intel_encoder
*encoder
;
10290 struct intel_connector
*connector
;
10291 struct drm_crtc
*tmp_crtc
;
10293 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10295 /* Check which crtcs have changed outputs connected to them, these need
10296 * to be part of the prepare_pipes mask. We don't (yet) support global
10297 * modeset across multiple crtcs, so modeset_pipes will only have one
10298 * bit set at most. */
10299 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10301 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10304 if (connector
->base
.encoder
) {
10305 tmp_crtc
= connector
->base
.encoder
->crtc
;
10307 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10310 if (connector
->new_encoder
)
10312 1 << connector
->new_encoder
->new_crtc
->pipe
;
10315 for_each_intel_encoder(dev
, encoder
) {
10316 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10319 if (encoder
->base
.crtc
) {
10320 tmp_crtc
= encoder
->base
.crtc
;
10322 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10325 if (encoder
->new_crtc
)
10326 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10329 /* Check for pipes that will be enabled/disabled ... */
10330 for_each_intel_crtc(dev
, intel_crtc
) {
10331 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10334 if (!intel_crtc
->new_enabled
)
10335 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10337 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10341 /* set_mode is also used to update properties on life display pipes. */
10342 intel_crtc
= to_intel_crtc(crtc
);
10343 if (intel_crtc
->new_enabled
)
10344 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10347 * For simplicity do a full modeset on any pipe where the output routing
10348 * changed. We could be more clever, but that would require us to be
10349 * more careful with calling the relevant encoder->mode_set functions.
10351 if (*prepare_pipes
)
10352 *modeset_pipes
= *prepare_pipes
;
10354 /* ... and mask these out. */
10355 *modeset_pipes
&= ~(*disable_pipes
);
10356 *prepare_pipes
&= ~(*disable_pipes
);
10359 * HACK: We don't (yet) fully support global modesets. intel_set_config
10360 * obies this rule, but the modeset restore mode of
10361 * intel_modeset_setup_hw_state does not.
10363 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10364 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10366 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10367 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10370 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10372 struct drm_encoder
*encoder
;
10373 struct drm_device
*dev
= crtc
->dev
;
10375 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10376 if (encoder
->crtc
== crtc
)
10383 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10385 struct intel_encoder
*intel_encoder
;
10386 struct intel_crtc
*intel_crtc
;
10387 struct drm_connector
*connector
;
10389 for_each_intel_encoder(dev
, intel_encoder
) {
10390 if (!intel_encoder
->base
.crtc
)
10393 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10395 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10396 intel_encoder
->connectors_active
= false;
10399 intel_modeset_commit_output_state(dev
);
10401 /* Double check state. */
10402 for_each_intel_crtc(dev
, intel_crtc
) {
10403 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10404 WARN_ON(intel_crtc
->new_config
&&
10405 intel_crtc
->new_config
!= &intel_crtc
->config
);
10406 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10409 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10410 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10413 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10415 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10416 struct drm_property
*dpms_property
=
10417 dev
->mode_config
.dpms_property
;
10419 connector
->dpms
= DRM_MODE_DPMS_ON
;
10420 drm_object_property_set_value(&connector
->base
,
10424 intel_encoder
= to_intel_encoder(connector
->encoder
);
10425 intel_encoder
->connectors_active
= true;
10431 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10435 if (clock1
== clock2
)
10438 if (!clock1
|| !clock2
)
10441 diff
= abs(clock1
- clock2
);
10443 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10449 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10450 list_for_each_entry((intel_crtc), \
10451 &(dev)->mode_config.crtc_list, \
10453 if (mask & (1 <<(intel_crtc)->pipe))
10456 intel_pipe_config_compare(struct drm_device
*dev
,
10457 struct intel_crtc_config
*current_config
,
10458 struct intel_crtc_config
*pipe_config
)
10460 #define PIPE_CONF_CHECK_X(name) \
10461 if (current_config->name != pipe_config->name) { \
10462 DRM_ERROR("mismatch in " #name " " \
10463 "(expected 0x%08x, found 0x%08x)\n", \
10464 current_config->name, \
10465 pipe_config->name); \
10469 #define PIPE_CONF_CHECK_I(name) \
10470 if (current_config->name != pipe_config->name) { \
10471 DRM_ERROR("mismatch in " #name " " \
10472 "(expected %i, found %i)\n", \
10473 current_config->name, \
10474 pipe_config->name); \
10478 /* This is required for BDW+ where there is only one set of registers for
10479 * switching between high and low RR.
10480 * This macro can be used whenever a comparison has to be made between one
10481 * hw state and multiple sw state variables.
10483 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10484 if ((current_config->name != pipe_config->name) && \
10485 (current_config->alt_name != pipe_config->name)) { \
10486 DRM_ERROR("mismatch in " #name " " \
10487 "(expected %i or %i, found %i)\n", \
10488 current_config->name, \
10489 current_config->alt_name, \
10490 pipe_config->name); \
10494 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10495 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10496 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10497 "(expected %i, found %i)\n", \
10498 current_config->name & (mask), \
10499 pipe_config->name & (mask)); \
10503 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10504 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10505 DRM_ERROR("mismatch in " #name " " \
10506 "(expected %i, found %i)\n", \
10507 current_config->name, \
10508 pipe_config->name); \
10512 #define PIPE_CONF_QUIRK(quirk) \
10513 ((current_config->quirks | pipe_config->quirks) & (quirk))
10515 PIPE_CONF_CHECK_I(cpu_transcoder
);
10517 PIPE_CONF_CHECK_I(has_pch_encoder
);
10518 PIPE_CONF_CHECK_I(fdi_lanes
);
10519 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10520 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10521 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10522 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10523 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10525 PIPE_CONF_CHECK_I(has_dp_encoder
);
10527 if (INTEL_INFO(dev
)->gen
< 8) {
10528 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10529 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10530 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10531 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10532 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10534 if (current_config
->has_drrs
) {
10535 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10536 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10537 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10538 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10539 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10542 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10543 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10544 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10545 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10546 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10549 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10550 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10551 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10552 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10553 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10554 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10556 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10557 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10558 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10559 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10560 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10561 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10563 PIPE_CONF_CHECK_I(pixel_multiplier
);
10564 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10565 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10566 IS_VALLEYVIEW(dev
))
10567 PIPE_CONF_CHECK_I(limited_color_range
);
10569 PIPE_CONF_CHECK_I(has_audio
);
10571 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10572 DRM_MODE_FLAG_INTERLACE
);
10574 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10575 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10576 DRM_MODE_FLAG_PHSYNC
);
10577 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10578 DRM_MODE_FLAG_NHSYNC
);
10579 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10580 DRM_MODE_FLAG_PVSYNC
);
10581 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10582 DRM_MODE_FLAG_NVSYNC
);
10585 PIPE_CONF_CHECK_I(pipe_src_w
);
10586 PIPE_CONF_CHECK_I(pipe_src_h
);
10589 * FIXME: BIOS likes to set up a cloned config with lvds+external
10590 * screen. Since we don't yet re-compute the pipe config when moving
10591 * just the lvds port away to another pipe the sw tracking won't match.
10593 * Proper atomic modesets with recomputed global state will fix this.
10594 * Until then just don't check gmch state for inherited modes.
10596 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10597 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10598 /* pfit ratios are autocomputed by the hw on gen4+ */
10599 if (INTEL_INFO(dev
)->gen
< 4)
10600 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10601 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10604 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10605 if (current_config
->pch_pfit
.enabled
) {
10606 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10607 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10610 /* BDW+ don't expose a synchronous way to read the state */
10611 if (IS_HASWELL(dev
))
10612 PIPE_CONF_CHECK_I(ips_enabled
);
10614 PIPE_CONF_CHECK_I(double_wide
);
10616 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10618 PIPE_CONF_CHECK_I(shared_dpll
);
10619 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10620 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10621 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10622 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10623 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10625 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10626 PIPE_CONF_CHECK_I(pipe_bpp
);
10628 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10629 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10631 #undef PIPE_CONF_CHECK_X
10632 #undef PIPE_CONF_CHECK_I
10633 #undef PIPE_CONF_CHECK_I_ALT
10634 #undef PIPE_CONF_CHECK_FLAGS
10635 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10636 #undef PIPE_CONF_QUIRK
10642 check_connector_state(struct drm_device
*dev
)
10644 struct intel_connector
*connector
;
10646 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10648 /* This also checks the encoder/connector hw state with the
10649 * ->get_hw_state callbacks. */
10650 intel_connector_check_state(connector
);
10652 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10653 "connector's staged encoder doesn't match current encoder\n");
10658 check_encoder_state(struct drm_device
*dev
)
10660 struct intel_encoder
*encoder
;
10661 struct intel_connector
*connector
;
10663 for_each_intel_encoder(dev
, encoder
) {
10664 bool enabled
= false;
10665 bool active
= false;
10666 enum pipe pipe
, tracked_pipe
;
10668 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10669 encoder
->base
.base
.id
,
10670 encoder
->base
.name
);
10672 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10673 "encoder's stage crtc doesn't match current crtc\n");
10674 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10675 "encoder's active_connectors set, but no crtc\n");
10677 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10679 if (connector
->base
.encoder
!= &encoder
->base
)
10682 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10686 * for MST connectors if we unplug the connector is gone
10687 * away but the encoder is still connected to a crtc
10688 * until a modeset happens in response to the hotplug.
10690 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10693 WARN(!!encoder
->base
.crtc
!= enabled
,
10694 "encoder's enabled state mismatch "
10695 "(expected %i, found %i)\n",
10696 !!encoder
->base
.crtc
, enabled
);
10697 WARN(active
&& !encoder
->base
.crtc
,
10698 "active encoder with no crtc\n");
10700 WARN(encoder
->connectors_active
!= active
,
10701 "encoder's computed active state doesn't match tracked active state "
10702 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10704 active
= encoder
->get_hw_state(encoder
, &pipe
);
10705 WARN(active
!= encoder
->connectors_active
,
10706 "encoder's hw state doesn't match sw tracking "
10707 "(expected %i, found %i)\n",
10708 encoder
->connectors_active
, active
);
10710 if (!encoder
->base
.crtc
)
10713 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10714 WARN(active
&& pipe
!= tracked_pipe
,
10715 "active encoder's pipe doesn't match"
10716 "(expected %i, found %i)\n",
10717 tracked_pipe
, pipe
);
10723 check_crtc_state(struct drm_device
*dev
)
10725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10726 struct intel_crtc
*crtc
;
10727 struct intel_encoder
*encoder
;
10728 struct intel_crtc_config pipe_config
;
10730 for_each_intel_crtc(dev
, crtc
) {
10731 bool enabled
= false;
10732 bool active
= false;
10734 memset(&pipe_config
, 0, sizeof(pipe_config
));
10736 DRM_DEBUG_KMS("[CRTC:%d]\n",
10737 crtc
->base
.base
.id
);
10739 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10740 "active crtc, but not enabled in sw tracking\n");
10742 for_each_intel_encoder(dev
, encoder
) {
10743 if (encoder
->base
.crtc
!= &crtc
->base
)
10746 if (encoder
->connectors_active
)
10750 WARN(active
!= crtc
->active
,
10751 "crtc's computed active state doesn't match tracked active state "
10752 "(expected %i, found %i)\n", active
, crtc
->active
);
10753 WARN(enabled
!= crtc
->base
.enabled
,
10754 "crtc's computed enabled state doesn't match tracked enabled state "
10755 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10757 active
= dev_priv
->display
.get_pipe_config(crtc
,
10760 /* hw state is inconsistent with the pipe quirk */
10761 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10762 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10763 active
= crtc
->active
;
10765 for_each_intel_encoder(dev
, encoder
) {
10767 if (encoder
->base
.crtc
!= &crtc
->base
)
10769 if (encoder
->get_hw_state(encoder
, &pipe
))
10770 encoder
->get_config(encoder
, &pipe_config
);
10773 WARN(crtc
->active
!= active
,
10774 "crtc active state doesn't match with hw state "
10775 "(expected %i, found %i)\n", crtc
->active
, active
);
10778 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10779 WARN(1, "pipe state doesn't match!\n");
10780 intel_dump_pipe_config(crtc
, &pipe_config
,
10782 intel_dump_pipe_config(crtc
, &crtc
->config
,
10789 check_shared_dpll_state(struct drm_device
*dev
)
10791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10792 struct intel_crtc
*crtc
;
10793 struct intel_dpll_hw_state dpll_hw_state
;
10796 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10797 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10798 int enabled_crtcs
= 0, active_crtcs
= 0;
10801 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10803 DRM_DEBUG_KMS("%s\n", pll
->name
);
10805 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10807 WARN(pll
->active
> pll
->refcount
,
10808 "more active pll users than references: %i vs %i\n",
10809 pll
->active
, pll
->refcount
);
10810 WARN(pll
->active
&& !pll
->on
,
10811 "pll in active use but not on in sw tracking\n");
10812 WARN(pll
->on
&& !pll
->active
,
10813 "pll in on but not on in use in sw tracking\n");
10814 WARN(pll
->on
!= active
,
10815 "pll on state mismatch (expected %i, found %i)\n",
10818 for_each_intel_crtc(dev
, crtc
) {
10819 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10821 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10824 WARN(pll
->active
!= active_crtcs
,
10825 "pll active crtcs mismatch (expected %i, found %i)\n",
10826 pll
->active
, active_crtcs
);
10827 WARN(pll
->refcount
!= enabled_crtcs
,
10828 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10829 pll
->refcount
, enabled_crtcs
);
10831 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10832 sizeof(dpll_hw_state
)),
10833 "pll hw state mismatch\n");
10838 intel_modeset_check_state(struct drm_device
*dev
)
10840 check_connector_state(dev
);
10841 check_encoder_state(dev
);
10842 check_crtc_state(dev
);
10843 check_shared_dpll_state(dev
);
10846 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10850 * FDI already provided one idea for the dotclock.
10851 * Yell if the encoder disagrees.
10853 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10854 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10855 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10858 static void update_scanline_offset(struct intel_crtc
*crtc
)
10860 struct drm_device
*dev
= crtc
->base
.dev
;
10863 * The scanline counter increments at the leading edge of hsync.
10865 * On most platforms it starts counting from vtotal-1 on the
10866 * first active line. That means the scanline counter value is
10867 * always one less than what we would expect. Ie. just after
10868 * start of vblank, which also occurs at start of hsync (on the
10869 * last active line), the scanline counter will read vblank_start-1.
10871 * On gen2 the scanline counter starts counting from 1 instead
10872 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10873 * to keep the value positive), instead of adding one.
10875 * On HSW+ the behaviour of the scanline counter depends on the output
10876 * type. For DP ports it behaves like most other platforms, but on HDMI
10877 * there's an extra 1 line difference. So we need to add two instead of
10878 * one to the value.
10880 if (IS_GEN2(dev
)) {
10881 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10884 vtotal
= mode
->crtc_vtotal
;
10885 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10888 crtc
->scanline_offset
= vtotal
- 1;
10889 } else if (HAS_DDI(dev
) &&
10890 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10891 crtc
->scanline_offset
= 2;
10893 crtc
->scanline_offset
= 1;
10896 static int __intel_set_mode(struct drm_crtc
*crtc
,
10897 struct drm_display_mode
*mode
,
10898 int x
, int y
, struct drm_framebuffer
*fb
)
10900 struct drm_device
*dev
= crtc
->dev
;
10901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10902 struct drm_display_mode
*saved_mode
;
10903 struct intel_crtc_config
*pipe_config
= NULL
;
10904 struct intel_crtc
*intel_crtc
;
10905 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10908 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10912 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10913 &prepare_pipes
, &disable_pipes
);
10915 *saved_mode
= crtc
->mode
;
10917 /* Hack: Because we don't (yet) support global modeset on multiple
10918 * crtcs, we don't keep track of the new mode for more than one crtc.
10919 * Hence simply check whether any bit is set in modeset_pipes in all the
10920 * pieces of code that are not yet converted to deal with mutliple crtcs
10921 * changing their mode at the same time. */
10922 if (modeset_pipes
) {
10923 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10924 if (IS_ERR(pipe_config
)) {
10925 ret
= PTR_ERR(pipe_config
);
10926 pipe_config
= NULL
;
10930 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10932 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10936 * See if the config requires any additional preparation, e.g.
10937 * to adjust global state with pipes off. We need to do this
10938 * here so we can get the modeset_pipe updated config for the new
10939 * mode set on this crtc. For other crtcs we need to use the
10940 * adjusted_mode bits in the crtc directly.
10942 if (IS_VALLEYVIEW(dev
)) {
10943 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10945 /* may have added more to prepare_pipes than we should */
10946 prepare_pipes
&= ~disable_pipes
;
10949 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10950 intel_crtc_disable(&intel_crtc
->base
);
10952 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10953 if (intel_crtc
->base
.enabled
)
10954 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10957 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10958 * to set it here already despite that we pass it down the callchain.
10960 if (modeset_pipes
) {
10961 crtc
->mode
= *mode
;
10962 /* mode_set/enable/disable functions rely on a correct pipe
10964 to_intel_crtc(crtc
)->config
= *pipe_config
;
10965 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10968 * Calculate and store various constants which
10969 * are later needed by vblank and swap-completion
10970 * timestamping. They are derived from true hwmode.
10972 drm_calc_timestamping_constants(crtc
,
10973 &pipe_config
->adjusted_mode
);
10976 /* Only after disabling all output pipelines that will be changed can we
10977 * update the the output configuration. */
10978 intel_modeset_update_state(dev
, prepare_pipes
);
10980 if (dev_priv
->display
.modeset_global_resources
)
10981 dev_priv
->display
.modeset_global_resources(dev
);
10983 /* Set up the DPLL and any encoders state that needs to adjust or depend
10986 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10987 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10988 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10989 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10991 mutex_lock(&dev
->struct_mutex
);
10992 ret
= intel_pin_and_fence_fb_obj(dev
,
10996 DRM_ERROR("pin & fence failed\n");
10997 mutex_unlock(&dev
->struct_mutex
);
11001 intel_unpin_fb_obj(old_obj
);
11002 i915_gem_track_fb(old_obj
, obj
,
11003 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11004 mutex_unlock(&dev
->struct_mutex
);
11006 crtc
->primary
->fb
= fb
;
11010 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11016 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11017 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11018 update_scanline_offset(intel_crtc
);
11020 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11023 /* FIXME: add subpixel order */
11025 if (ret
&& crtc
->enabled
)
11026 crtc
->mode
= *saved_mode
;
11029 kfree(pipe_config
);
11034 static int intel_set_mode(struct drm_crtc
*crtc
,
11035 struct drm_display_mode
*mode
,
11036 int x
, int y
, struct drm_framebuffer
*fb
)
11040 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11043 intel_modeset_check_state(crtc
->dev
);
11048 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11050 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11053 #undef for_each_intel_crtc_masked
11055 static void intel_set_config_free(struct intel_set_config
*config
)
11060 kfree(config
->save_connector_encoders
);
11061 kfree(config
->save_encoder_crtcs
);
11062 kfree(config
->save_crtc_enabled
);
11066 static int intel_set_config_save_state(struct drm_device
*dev
,
11067 struct intel_set_config
*config
)
11069 struct drm_crtc
*crtc
;
11070 struct drm_encoder
*encoder
;
11071 struct drm_connector
*connector
;
11074 config
->save_crtc_enabled
=
11075 kcalloc(dev
->mode_config
.num_crtc
,
11076 sizeof(bool), GFP_KERNEL
);
11077 if (!config
->save_crtc_enabled
)
11080 config
->save_encoder_crtcs
=
11081 kcalloc(dev
->mode_config
.num_encoder
,
11082 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11083 if (!config
->save_encoder_crtcs
)
11086 config
->save_connector_encoders
=
11087 kcalloc(dev
->mode_config
.num_connector
,
11088 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11089 if (!config
->save_connector_encoders
)
11092 /* Copy data. Note that driver private data is not affected.
11093 * Should anything bad happen only the expected state is
11094 * restored, not the drivers personal bookkeeping.
11097 for_each_crtc(dev
, crtc
) {
11098 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11102 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11103 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11107 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11108 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11114 static void intel_set_config_restore_state(struct drm_device
*dev
,
11115 struct intel_set_config
*config
)
11117 struct intel_crtc
*crtc
;
11118 struct intel_encoder
*encoder
;
11119 struct intel_connector
*connector
;
11123 for_each_intel_crtc(dev
, crtc
) {
11124 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11126 if (crtc
->new_enabled
)
11127 crtc
->new_config
= &crtc
->config
;
11129 crtc
->new_config
= NULL
;
11133 for_each_intel_encoder(dev
, encoder
) {
11134 encoder
->new_crtc
=
11135 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11139 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11140 connector
->new_encoder
=
11141 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11146 is_crtc_connector_off(struct drm_mode_set
*set
)
11150 if (set
->num_connectors
== 0)
11153 if (WARN_ON(set
->connectors
== NULL
))
11156 for (i
= 0; i
< set
->num_connectors
; i
++)
11157 if (set
->connectors
[i
]->encoder
&&
11158 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11159 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11166 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11167 struct intel_set_config
*config
)
11170 /* We should be able to check here if the fb has the same properties
11171 * and then just flip_or_move it */
11172 if (is_crtc_connector_off(set
)) {
11173 config
->mode_changed
= true;
11174 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11176 * If we have no fb, we can only flip as long as the crtc is
11177 * active, otherwise we need a full mode set. The crtc may
11178 * be active if we've only disabled the primary plane, or
11179 * in fastboot situations.
11181 if (set
->crtc
->primary
->fb
== NULL
) {
11182 struct intel_crtc
*intel_crtc
=
11183 to_intel_crtc(set
->crtc
);
11185 if (intel_crtc
->active
) {
11186 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11187 config
->fb_changed
= true;
11189 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11190 config
->mode_changed
= true;
11192 } else if (set
->fb
== NULL
) {
11193 config
->mode_changed
= true;
11194 } else if (set
->fb
->pixel_format
!=
11195 set
->crtc
->primary
->fb
->pixel_format
) {
11196 config
->mode_changed
= true;
11198 config
->fb_changed
= true;
11202 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11203 config
->fb_changed
= true;
11205 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11206 DRM_DEBUG_KMS("modes are different, full mode set\n");
11207 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11208 drm_mode_debug_printmodeline(set
->mode
);
11209 config
->mode_changed
= true;
11212 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11213 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11217 intel_modeset_stage_output_state(struct drm_device
*dev
,
11218 struct drm_mode_set
*set
,
11219 struct intel_set_config
*config
)
11221 struct intel_connector
*connector
;
11222 struct intel_encoder
*encoder
;
11223 struct intel_crtc
*crtc
;
11226 /* The upper layers ensure that we either disable a crtc or have a list
11227 * of connectors. For paranoia, double-check this. */
11228 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11229 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11231 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11233 /* Otherwise traverse passed in connector list and get encoders
11235 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11236 if (set
->connectors
[ro
] == &connector
->base
) {
11237 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11242 /* If we disable the crtc, disable all its connectors. Also, if
11243 * the connector is on the changing crtc but not on the new
11244 * connector list, disable it. */
11245 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11246 connector
->base
.encoder
&&
11247 connector
->base
.encoder
->crtc
== set
->crtc
) {
11248 connector
->new_encoder
= NULL
;
11250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11251 connector
->base
.base
.id
,
11252 connector
->base
.name
);
11256 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11257 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11258 config
->mode_changed
= true;
11261 /* connector->new_encoder is now updated for all connectors. */
11263 /* Update crtc of enabled connectors. */
11264 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11266 struct drm_crtc
*new_crtc
;
11268 if (!connector
->new_encoder
)
11271 new_crtc
= connector
->new_encoder
->base
.crtc
;
11273 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11274 if (set
->connectors
[ro
] == &connector
->base
)
11275 new_crtc
= set
->crtc
;
11278 /* Make sure the new CRTC will work with the encoder */
11279 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11283 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11285 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11286 connector
->base
.base
.id
,
11287 connector
->base
.name
,
11288 new_crtc
->base
.id
);
11291 /* Check for any encoders that needs to be disabled. */
11292 for_each_intel_encoder(dev
, encoder
) {
11293 int num_connectors
= 0;
11294 list_for_each_entry(connector
,
11295 &dev
->mode_config
.connector_list
,
11297 if (connector
->new_encoder
== encoder
) {
11298 WARN_ON(!connector
->new_encoder
->new_crtc
);
11303 if (num_connectors
== 0)
11304 encoder
->new_crtc
= NULL
;
11305 else if (num_connectors
> 1)
11308 /* Only now check for crtc changes so we don't miss encoders
11309 * that will be disabled. */
11310 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11311 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11312 config
->mode_changed
= true;
11315 /* Now we've also updated encoder->new_crtc for all encoders. */
11316 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11318 if (connector
->new_encoder
)
11319 if (connector
->new_encoder
!= connector
->encoder
)
11320 connector
->encoder
= connector
->new_encoder
;
11322 for_each_intel_crtc(dev
, crtc
) {
11323 crtc
->new_enabled
= false;
11325 for_each_intel_encoder(dev
, encoder
) {
11326 if (encoder
->new_crtc
== crtc
) {
11327 crtc
->new_enabled
= true;
11332 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11333 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11334 crtc
->new_enabled
? "en" : "dis");
11335 config
->mode_changed
= true;
11338 if (crtc
->new_enabled
)
11339 crtc
->new_config
= &crtc
->config
;
11341 crtc
->new_config
= NULL
;
11347 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11349 struct drm_device
*dev
= crtc
->base
.dev
;
11350 struct intel_encoder
*encoder
;
11351 struct intel_connector
*connector
;
11353 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11354 pipe_name(crtc
->pipe
));
11356 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11357 if (connector
->new_encoder
&&
11358 connector
->new_encoder
->new_crtc
== crtc
)
11359 connector
->new_encoder
= NULL
;
11362 for_each_intel_encoder(dev
, encoder
) {
11363 if (encoder
->new_crtc
== crtc
)
11364 encoder
->new_crtc
= NULL
;
11367 crtc
->new_enabled
= false;
11368 crtc
->new_config
= NULL
;
11371 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11373 struct drm_device
*dev
;
11374 struct drm_mode_set save_set
;
11375 struct intel_set_config
*config
;
11379 BUG_ON(!set
->crtc
);
11380 BUG_ON(!set
->crtc
->helper_private
);
11382 /* Enforce sane interface api - has been abused by the fb helper. */
11383 BUG_ON(!set
->mode
&& set
->fb
);
11384 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11387 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11388 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11389 (int)set
->num_connectors
, set
->x
, set
->y
);
11391 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11394 dev
= set
->crtc
->dev
;
11397 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11401 ret
= intel_set_config_save_state(dev
, config
);
11405 save_set
.crtc
= set
->crtc
;
11406 save_set
.mode
= &set
->crtc
->mode
;
11407 save_set
.x
= set
->crtc
->x
;
11408 save_set
.y
= set
->crtc
->y
;
11409 save_set
.fb
= set
->crtc
->primary
->fb
;
11411 /* Compute whether we need a full modeset, only an fb base update or no
11412 * change at all. In the future we might also check whether only the
11413 * mode changed, e.g. for LVDS where we only change the panel fitter in
11415 intel_set_config_compute_mode_changes(set
, config
);
11417 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11421 if (config
->mode_changed
) {
11422 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11423 set
->x
, set
->y
, set
->fb
);
11424 } else if (config
->fb_changed
) {
11425 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11427 intel_crtc_wait_for_pending_flips(set
->crtc
);
11429 ret
= intel_pipe_set_base(set
->crtc
,
11430 set
->x
, set
->y
, set
->fb
);
11433 * We need to make sure the primary plane is re-enabled if it
11434 * has previously been turned off.
11436 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11437 WARN_ON(!intel_crtc
->active
);
11438 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11442 * In the fastboot case this may be our only check of the
11443 * state after boot. It would be better to only do it on
11444 * the first update, but we don't have a nice way of doing that
11445 * (and really, set_config isn't used much for high freq page
11446 * flipping, so increasing its cost here shouldn't be a big
11449 if (i915
.fastboot
&& ret
== 0)
11450 intel_modeset_check_state(set
->crtc
->dev
);
11454 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11455 set
->crtc
->base
.id
, ret
);
11457 intel_set_config_restore_state(dev
, config
);
11460 * HACK: if the pipe was on, but we didn't have a framebuffer,
11461 * force the pipe off to avoid oopsing in the modeset code
11462 * due to fb==NULL. This should only happen during boot since
11463 * we don't yet reconstruct the FB from the hardware state.
11465 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11466 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11468 /* Try to restore the config */
11469 if (config
->mode_changed
&&
11470 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11471 save_set
.x
, save_set
.y
, save_set
.fb
))
11472 DRM_ERROR("failed to restore config after modeset failure\n");
11476 intel_set_config_free(config
);
11480 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11481 .gamma_set
= intel_crtc_gamma_set
,
11482 .set_config
= intel_crtc_set_config
,
11483 .destroy
= intel_crtc_destroy
,
11484 .page_flip
= intel_crtc_page_flip
,
11487 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11488 struct intel_shared_dpll
*pll
,
11489 struct intel_dpll_hw_state
*hw_state
)
11493 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11496 val
= I915_READ(PCH_DPLL(pll
->id
));
11497 hw_state
->dpll
= val
;
11498 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11499 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11501 return val
& DPLL_VCO_ENABLE
;
11504 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11505 struct intel_shared_dpll
*pll
)
11507 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11508 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11511 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11512 struct intel_shared_dpll
*pll
)
11514 /* PCH refclock must be enabled first */
11515 ibx_assert_pch_refclk_enabled(dev_priv
);
11517 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11519 /* Wait for the clocks to stabilize. */
11520 POSTING_READ(PCH_DPLL(pll
->id
));
11523 /* The pixel multiplier can only be updated once the
11524 * DPLL is enabled and the clocks are stable.
11526 * So write it again.
11528 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11529 POSTING_READ(PCH_DPLL(pll
->id
));
11533 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11534 struct intel_shared_dpll
*pll
)
11536 struct drm_device
*dev
= dev_priv
->dev
;
11537 struct intel_crtc
*crtc
;
11539 /* Make sure no transcoder isn't still depending on us. */
11540 for_each_intel_crtc(dev
, crtc
) {
11541 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11542 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11545 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11546 POSTING_READ(PCH_DPLL(pll
->id
));
11550 static char *ibx_pch_dpll_names
[] = {
11555 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11560 dev_priv
->num_shared_dpll
= 2;
11562 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11563 dev_priv
->shared_dplls
[i
].id
= i
;
11564 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11565 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11566 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11567 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11568 dev_priv
->shared_dplls
[i
].get_hw_state
=
11569 ibx_pch_dpll_get_hw_state
;
11573 static void intel_shared_dpll_init(struct drm_device
*dev
)
11575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11578 intel_ddi_pll_init(dev
);
11579 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11580 ibx_pch_dpll_init(dev
);
11582 dev_priv
->num_shared_dpll
= 0;
11584 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11588 intel_primary_plane_disable(struct drm_plane
*plane
)
11590 struct drm_device
*dev
= plane
->dev
;
11591 struct intel_crtc
*intel_crtc
;
11596 BUG_ON(!plane
->crtc
);
11598 intel_crtc
= to_intel_crtc(plane
->crtc
);
11601 * Even though we checked plane->fb above, it's still possible that
11602 * the primary plane has been implicitly disabled because the crtc
11603 * coordinates given weren't visible, or because we detected
11604 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11605 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11606 * In either case, we need to unpin the FB and let the fb pointer get
11607 * updated, but otherwise we don't need to touch the hardware.
11609 if (!intel_crtc
->primary_enabled
)
11610 goto disable_unpin
;
11612 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11613 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11616 mutex_lock(&dev
->struct_mutex
);
11617 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11618 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11619 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11620 mutex_unlock(&dev
->struct_mutex
);
11627 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11628 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11629 unsigned int crtc_w
, unsigned int crtc_h
,
11630 uint32_t src_x
, uint32_t src_y
,
11631 uint32_t src_w
, uint32_t src_h
)
11633 struct drm_device
*dev
= crtc
->dev
;
11634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11635 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11636 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11637 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11638 struct drm_rect dest
= {
11639 /* integer pixels */
11642 .x2
= crtc_x
+ crtc_w
,
11643 .y2
= crtc_y
+ crtc_h
,
11645 struct drm_rect src
= {
11646 /* 16.16 fixed point */
11649 .x2
= src_x
+ src_w
,
11650 .y2
= src_y
+ src_h
,
11652 const struct drm_rect clip
= {
11653 /* integer pixels */
11654 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11655 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11658 int crtc_x
, crtc_y
;
11659 unsigned int crtc_w
, crtc_h
;
11660 uint32_t src_x
, src_y
, src_w
, src_h
;
11671 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11675 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11676 &src
, &dest
, &clip
,
11677 DRM_PLANE_HELPER_NO_SCALING
,
11678 DRM_PLANE_HELPER_NO_SCALING
,
11679 false, true, &visible
);
11685 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11686 * updating the fb pointer, and returning without touching the
11687 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11688 * turn on the display with all planes setup as desired.
11690 if (!crtc
->enabled
) {
11691 mutex_lock(&dev
->struct_mutex
);
11694 * If we already called setplane while the crtc was disabled,
11695 * we may have an fb pinned; unpin it.
11698 intel_unpin_fb_obj(old_obj
);
11700 i915_gem_track_fb(old_obj
, obj
,
11701 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11703 /* Pin and return without programming hardware */
11704 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11705 mutex_unlock(&dev
->struct_mutex
);
11710 intel_crtc_wait_for_pending_flips(crtc
);
11713 * If clipping results in a non-visible primary plane, we'll disable
11714 * the primary plane. Note that this is a bit different than what
11715 * happens if userspace explicitly disables the plane by passing fb=0
11716 * because plane->fb still gets set and pinned.
11719 mutex_lock(&dev
->struct_mutex
);
11722 * Try to pin the new fb first so that we can bail out if we
11725 if (plane
->fb
!= fb
) {
11726 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11728 mutex_unlock(&dev
->struct_mutex
);
11733 i915_gem_track_fb(old_obj
, obj
,
11734 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11736 if (intel_crtc
->primary_enabled
)
11737 intel_disable_primary_hw_plane(plane
, crtc
);
11740 if (plane
->fb
!= fb
)
11742 intel_unpin_fb_obj(old_obj
);
11744 mutex_unlock(&dev
->struct_mutex
);
11747 if (intel_crtc
&& intel_crtc
->active
&&
11748 intel_crtc
->primary_enabled
) {
11750 * FBC does not work on some platforms for rotated
11751 * planes, so disable it when rotation is not 0 and
11752 * update it when rotation is set back to 0.
11754 * FIXME: This is redundant with the fbc update done in
11755 * the primary plane enable function except that that
11756 * one is done too late. We eventually need to unify
11759 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11760 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11761 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11762 intel_disable_fbc(dev
);
11765 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11769 if (!intel_crtc
->primary_enabled
)
11770 intel_enable_primary_hw_plane(plane
, crtc
);
11773 intel_plane
->crtc_x
= orig
.crtc_x
;
11774 intel_plane
->crtc_y
= orig
.crtc_y
;
11775 intel_plane
->crtc_w
= orig
.crtc_w
;
11776 intel_plane
->crtc_h
= orig
.crtc_h
;
11777 intel_plane
->src_x
= orig
.src_x
;
11778 intel_plane
->src_y
= orig
.src_y
;
11779 intel_plane
->src_w
= orig
.src_w
;
11780 intel_plane
->src_h
= orig
.src_h
;
11781 intel_plane
->obj
= obj
;
11786 /* Common destruction function for both primary and cursor planes */
11787 static void intel_plane_destroy(struct drm_plane
*plane
)
11789 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11790 drm_plane_cleanup(plane
);
11791 kfree(intel_plane
);
11794 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11795 .update_plane
= intel_primary_plane_setplane
,
11796 .disable_plane
= intel_primary_plane_disable
,
11797 .destroy
= intel_plane_destroy
,
11798 .set_property
= intel_plane_set_property
11801 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11804 struct intel_plane
*primary
;
11805 const uint32_t *intel_primary_formats
;
11808 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11809 if (primary
== NULL
)
11812 primary
->can_scale
= false;
11813 primary
->max_downscale
= 1;
11814 primary
->pipe
= pipe
;
11815 primary
->plane
= pipe
;
11816 primary
->rotation
= BIT(DRM_ROTATE_0
);
11817 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11818 primary
->plane
= !pipe
;
11820 if (INTEL_INFO(dev
)->gen
<= 3) {
11821 intel_primary_formats
= intel_primary_formats_gen2
;
11822 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11824 intel_primary_formats
= intel_primary_formats_gen4
;
11825 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11828 drm_universal_plane_init(dev
, &primary
->base
, 0,
11829 &intel_primary_plane_funcs
,
11830 intel_primary_formats
, num_formats
,
11831 DRM_PLANE_TYPE_PRIMARY
);
11833 if (INTEL_INFO(dev
)->gen
>= 4) {
11834 if (!dev
->mode_config
.rotation_property
)
11835 dev
->mode_config
.rotation_property
=
11836 drm_mode_create_rotation_property(dev
,
11837 BIT(DRM_ROTATE_0
) |
11838 BIT(DRM_ROTATE_180
));
11839 if (dev
->mode_config
.rotation_property
)
11840 drm_object_attach_property(&primary
->base
.base
,
11841 dev
->mode_config
.rotation_property
,
11842 primary
->rotation
);
11845 return &primary
->base
;
11849 intel_cursor_plane_disable(struct drm_plane
*plane
)
11854 BUG_ON(!plane
->crtc
);
11856 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11860 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11861 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11862 unsigned int crtc_w
, unsigned int crtc_h
,
11863 uint32_t src_x
, uint32_t src_y
,
11864 uint32_t src_w
, uint32_t src_h
)
11866 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11867 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11868 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11869 struct drm_rect dest
= {
11870 /* integer pixels */
11873 .x2
= crtc_x
+ crtc_w
,
11874 .y2
= crtc_y
+ crtc_h
,
11876 struct drm_rect src
= {
11877 /* 16.16 fixed point */
11880 .x2
= src_x
+ src_w
,
11881 .y2
= src_y
+ src_h
,
11883 const struct drm_rect clip
= {
11884 /* integer pixels */
11885 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11886 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11891 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11892 &src
, &dest
, &clip
,
11893 DRM_PLANE_HELPER_NO_SCALING
,
11894 DRM_PLANE_HELPER_NO_SCALING
,
11895 true, true, &visible
);
11899 crtc
->cursor_x
= crtc_x
;
11900 crtc
->cursor_y
= crtc_y
;
11901 if (fb
!= crtc
->cursor
->fb
) {
11902 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11904 intel_crtc_update_cursor(crtc
, visible
);
11906 intel_frontbuffer_flip(crtc
->dev
,
11907 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
11912 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11913 .update_plane
= intel_cursor_plane_update
,
11914 .disable_plane
= intel_cursor_plane_disable
,
11915 .destroy
= intel_plane_destroy
,
11918 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11921 struct intel_plane
*cursor
;
11923 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11924 if (cursor
== NULL
)
11927 cursor
->can_scale
= false;
11928 cursor
->max_downscale
= 1;
11929 cursor
->pipe
= pipe
;
11930 cursor
->plane
= pipe
;
11932 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11933 &intel_cursor_plane_funcs
,
11934 intel_cursor_formats
,
11935 ARRAY_SIZE(intel_cursor_formats
),
11936 DRM_PLANE_TYPE_CURSOR
);
11937 return &cursor
->base
;
11940 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11943 struct intel_crtc
*intel_crtc
;
11944 struct drm_plane
*primary
= NULL
;
11945 struct drm_plane
*cursor
= NULL
;
11948 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11949 if (intel_crtc
== NULL
)
11952 primary
= intel_primary_plane_create(dev
, pipe
);
11956 cursor
= intel_cursor_plane_create(dev
, pipe
);
11960 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11961 cursor
, &intel_crtc_funcs
);
11965 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11966 for (i
= 0; i
< 256; i
++) {
11967 intel_crtc
->lut_r
[i
] = i
;
11968 intel_crtc
->lut_g
[i
] = i
;
11969 intel_crtc
->lut_b
[i
] = i
;
11973 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11974 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11976 intel_crtc
->pipe
= pipe
;
11977 intel_crtc
->plane
= pipe
;
11978 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11979 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11980 intel_crtc
->plane
= !pipe
;
11983 intel_crtc
->cursor_base
= ~0;
11984 intel_crtc
->cursor_cntl
= ~0;
11985 intel_crtc
->cursor_size
= ~0;
11987 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11988 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11989 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11990 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11992 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11994 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11999 drm_plane_cleanup(primary
);
12001 drm_plane_cleanup(cursor
);
12005 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12007 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12008 struct drm_device
*dev
= connector
->base
.dev
;
12010 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12013 return INVALID_PIPE
;
12015 return to_intel_crtc(encoder
->crtc
)->pipe
;
12018 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12019 struct drm_file
*file
)
12021 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12022 struct drm_crtc
*drmmode_crtc
;
12023 struct intel_crtc
*crtc
;
12025 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12028 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12030 if (!drmmode_crtc
) {
12031 DRM_ERROR("no such CRTC id\n");
12035 crtc
= to_intel_crtc(drmmode_crtc
);
12036 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12041 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12043 struct drm_device
*dev
= encoder
->base
.dev
;
12044 struct intel_encoder
*source_encoder
;
12045 int index_mask
= 0;
12048 for_each_intel_encoder(dev
, source_encoder
) {
12049 if (encoders_cloneable(encoder
, source_encoder
))
12050 index_mask
|= (1 << entry
);
12058 static bool has_edp_a(struct drm_device
*dev
)
12060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12062 if (!IS_MOBILE(dev
))
12065 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12068 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12074 const char *intel_output_name(int output
)
12076 static const char *names
[] = {
12077 [INTEL_OUTPUT_UNUSED
] = "Unused",
12078 [INTEL_OUTPUT_ANALOG
] = "Analog",
12079 [INTEL_OUTPUT_DVO
] = "DVO",
12080 [INTEL_OUTPUT_SDVO
] = "SDVO",
12081 [INTEL_OUTPUT_LVDS
] = "LVDS",
12082 [INTEL_OUTPUT_TVOUT
] = "TV",
12083 [INTEL_OUTPUT_HDMI
] = "HDMI",
12084 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12085 [INTEL_OUTPUT_EDP
] = "eDP",
12086 [INTEL_OUTPUT_DSI
] = "DSI",
12087 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12090 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12093 return names
[output
];
12096 static bool intel_crt_present(struct drm_device
*dev
)
12098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12103 if (IS_CHERRYVIEW(dev
))
12106 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12112 static void intel_setup_outputs(struct drm_device
*dev
)
12114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12115 struct intel_encoder
*encoder
;
12116 bool dpd_is_edp
= false;
12118 intel_lvds_init(dev
);
12120 if (intel_crt_present(dev
))
12121 intel_crt_init(dev
);
12123 if (HAS_DDI(dev
)) {
12126 /* Haswell uses DDI functions to detect digital outputs */
12127 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12128 /* DDI A only supports eDP */
12130 intel_ddi_init(dev
, PORT_A
);
12132 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12134 found
= I915_READ(SFUSE_STRAP
);
12136 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12137 intel_ddi_init(dev
, PORT_B
);
12138 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12139 intel_ddi_init(dev
, PORT_C
);
12140 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12141 intel_ddi_init(dev
, PORT_D
);
12142 } else if (HAS_PCH_SPLIT(dev
)) {
12144 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12146 if (has_edp_a(dev
))
12147 intel_dp_init(dev
, DP_A
, PORT_A
);
12149 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12150 /* PCH SDVOB multiplex with HDMIB */
12151 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12153 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12154 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12155 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12158 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12159 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12161 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12162 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12164 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12165 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12167 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12168 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12169 } else if (IS_VALLEYVIEW(dev
)) {
12170 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12171 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12173 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12174 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12177 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12178 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12180 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12181 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12184 if (IS_CHERRYVIEW(dev
)) {
12185 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12186 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12188 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12189 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12193 intel_dsi_init(dev
);
12194 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12195 bool found
= false;
12197 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12198 DRM_DEBUG_KMS("probing SDVOB\n");
12199 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12200 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12201 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12202 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12205 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12206 intel_dp_init(dev
, DP_B
, PORT_B
);
12209 /* Before G4X SDVOC doesn't have its own detect register */
12211 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12212 DRM_DEBUG_KMS("probing SDVOC\n");
12213 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12216 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12218 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12219 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12220 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12222 if (SUPPORTS_INTEGRATED_DP(dev
))
12223 intel_dp_init(dev
, DP_C
, PORT_C
);
12226 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12227 (I915_READ(DP_D
) & DP_DETECTED
))
12228 intel_dp_init(dev
, DP_D
, PORT_D
);
12229 } else if (IS_GEN2(dev
))
12230 intel_dvo_init(dev
);
12232 if (SUPPORTS_TV(dev
))
12233 intel_tv_init(dev
);
12235 intel_edp_psr_init(dev
);
12237 for_each_intel_encoder(dev
, encoder
) {
12238 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12239 encoder
->base
.possible_clones
=
12240 intel_encoder_clones(encoder
);
12243 intel_init_pch_refclk(dev
);
12245 drm_helper_move_panel_connectors_to_head(dev
);
12248 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12250 struct drm_device
*dev
= fb
->dev
;
12251 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12253 drm_framebuffer_cleanup(fb
);
12254 mutex_lock(&dev
->struct_mutex
);
12255 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12256 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12257 mutex_unlock(&dev
->struct_mutex
);
12261 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12262 struct drm_file
*file
,
12263 unsigned int *handle
)
12265 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12266 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12268 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12271 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12272 .destroy
= intel_user_framebuffer_destroy
,
12273 .create_handle
= intel_user_framebuffer_create_handle
,
12276 static int intel_framebuffer_init(struct drm_device
*dev
,
12277 struct intel_framebuffer
*intel_fb
,
12278 struct drm_mode_fb_cmd2
*mode_cmd
,
12279 struct drm_i915_gem_object
*obj
)
12281 int aligned_height
;
12285 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12287 if (obj
->tiling_mode
== I915_TILING_Y
) {
12288 DRM_DEBUG("hardware does not support tiling Y\n");
12292 if (mode_cmd
->pitches
[0] & 63) {
12293 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12294 mode_cmd
->pitches
[0]);
12298 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12299 pitch_limit
= 32*1024;
12300 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12301 if (obj
->tiling_mode
)
12302 pitch_limit
= 16*1024;
12304 pitch_limit
= 32*1024;
12305 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12306 if (obj
->tiling_mode
)
12307 pitch_limit
= 8*1024;
12309 pitch_limit
= 16*1024;
12311 /* XXX DSPC is limited to 4k tiled */
12312 pitch_limit
= 8*1024;
12314 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12315 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12316 obj
->tiling_mode
? "tiled" : "linear",
12317 mode_cmd
->pitches
[0], pitch_limit
);
12321 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12322 mode_cmd
->pitches
[0] != obj
->stride
) {
12323 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12324 mode_cmd
->pitches
[0], obj
->stride
);
12328 /* Reject formats not supported by any plane early. */
12329 switch (mode_cmd
->pixel_format
) {
12330 case DRM_FORMAT_C8
:
12331 case DRM_FORMAT_RGB565
:
12332 case DRM_FORMAT_XRGB8888
:
12333 case DRM_FORMAT_ARGB8888
:
12335 case DRM_FORMAT_XRGB1555
:
12336 case DRM_FORMAT_ARGB1555
:
12337 if (INTEL_INFO(dev
)->gen
> 3) {
12338 DRM_DEBUG("unsupported pixel format: %s\n",
12339 drm_get_format_name(mode_cmd
->pixel_format
));
12343 case DRM_FORMAT_XBGR8888
:
12344 case DRM_FORMAT_ABGR8888
:
12345 case DRM_FORMAT_XRGB2101010
:
12346 case DRM_FORMAT_ARGB2101010
:
12347 case DRM_FORMAT_XBGR2101010
:
12348 case DRM_FORMAT_ABGR2101010
:
12349 if (INTEL_INFO(dev
)->gen
< 4) {
12350 DRM_DEBUG("unsupported pixel format: %s\n",
12351 drm_get_format_name(mode_cmd
->pixel_format
));
12355 case DRM_FORMAT_YUYV
:
12356 case DRM_FORMAT_UYVY
:
12357 case DRM_FORMAT_YVYU
:
12358 case DRM_FORMAT_VYUY
:
12359 if (INTEL_INFO(dev
)->gen
< 5) {
12360 DRM_DEBUG("unsupported pixel format: %s\n",
12361 drm_get_format_name(mode_cmd
->pixel_format
));
12366 DRM_DEBUG("unsupported pixel format: %s\n",
12367 drm_get_format_name(mode_cmd
->pixel_format
));
12371 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12372 if (mode_cmd
->offsets
[0] != 0)
12375 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12377 /* FIXME drm helper for size checks (especially planar formats)? */
12378 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12381 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12382 intel_fb
->obj
= obj
;
12383 intel_fb
->obj
->framebuffer_references
++;
12385 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12387 DRM_ERROR("framebuffer init failed %d\n", ret
);
12394 static struct drm_framebuffer
*
12395 intel_user_framebuffer_create(struct drm_device
*dev
,
12396 struct drm_file
*filp
,
12397 struct drm_mode_fb_cmd2
*mode_cmd
)
12399 struct drm_i915_gem_object
*obj
;
12401 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12402 mode_cmd
->handles
[0]));
12403 if (&obj
->base
== NULL
)
12404 return ERR_PTR(-ENOENT
);
12406 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12409 #ifndef CONFIG_DRM_I915_FBDEV
12410 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12415 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12416 .fb_create
= intel_user_framebuffer_create
,
12417 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12420 /* Set up chip specific display functions */
12421 static void intel_init_display(struct drm_device
*dev
)
12423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12425 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12426 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12427 else if (IS_CHERRYVIEW(dev
))
12428 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12429 else if (IS_VALLEYVIEW(dev
))
12430 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12431 else if (IS_PINEVIEW(dev
))
12432 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12434 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12436 if (HAS_DDI(dev
)) {
12437 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12438 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12439 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12440 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12441 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12442 dev_priv
->display
.off
= ironlake_crtc_off
;
12443 dev_priv
->display
.update_primary_plane
=
12444 ironlake_update_primary_plane
;
12445 } else if (HAS_PCH_SPLIT(dev
)) {
12446 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12447 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12448 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12449 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12450 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12451 dev_priv
->display
.off
= ironlake_crtc_off
;
12452 dev_priv
->display
.update_primary_plane
=
12453 ironlake_update_primary_plane
;
12454 } else if (IS_VALLEYVIEW(dev
)) {
12455 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12456 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12457 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12458 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12459 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12460 dev_priv
->display
.off
= i9xx_crtc_off
;
12461 dev_priv
->display
.update_primary_plane
=
12462 i9xx_update_primary_plane
;
12464 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12465 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12466 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12467 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12468 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12469 dev_priv
->display
.off
= i9xx_crtc_off
;
12470 dev_priv
->display
.update_primary_plane
=
12471 i9xx_update_primary_plane
;
12474 /* Returns the core display clock speed */
12475 if (IS_VALLEYVIEW(dev
))
12476 dev_priv
->display
.get_display_clock_speed
=
12477 valleyview_get_display_clock_speed
;
12478 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12479 dev_priv
->display
.get_display_clock_speed
=
12480 i945_get_display_clock_speed
;
12481 else if (IS_I915G(dev
))
12482 dev_priv
->display
.get_display_clock_speed
=
12483 i915_get_display_clock_speed
;
12484 else if (IS_I945GM(dev
) || IS_845G(dev
))
12485 dev_priv
->display
.get_display_clock_speed
=
12486 i9xx_misc_get_display_clock_speed
;
12487 else if (IS_PINEVIEW(dev
))
12488 dev_priv
->display
.get_display_clock_speed
=
12489 pnv_get_display_clock_speed
;
12490 else if (IS_I915GM(dev
))
12491 dev_priv
->display
.get_display_clock_speed
=
12492 i915gm_get_display_clock_speed
;
12493 else if (IS_I865G(dev
))
12494 dev_priv
->display
.get_display_clock_speed
=
12495 i865_get_display_clock_speed
;
12496 else if (IS_I85X(dev
))
12497 dev_priv
->display
.get_display_clock_speed
=
12498 i855_get_display_clock_speed
;
12499 else /* 852, 830 */
12500 dev_priv
->display
.get_display_clock_speed
=
12501 i830_get_display_clock_speed
;
12504 dev_priv
->display
.write_eld
= g4x_write_eld
;
12505 } else if (IS_GEN5(dev
)) {
12506 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12507 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12508 } else if (IS_GEN6(dev
)) {
12509 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12510 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12511 dev_priv
->display
.modeset_global_resources
=
12512 snb_modeset_global_resources
;
12513 } else if (IS_IVYBRIDGE(dev
)) {
12514 /* FIXME: detect B0+ stepping and use auto training */
12515 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12516 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12517 dev_priv
->display
.modeset_global_resources
=
12518 ivb_modeset_global_resources
;
12519 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
12520 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12521 dev_priv
->display
.write_eld
= haswell_write_eld
;
12522 dev_priv
->display
.modeset_global_resources
=
12523 haswell_modeset_global_resources
;
12524 } else if (IS_VALLEYVIEW(dev
)) {
12525 dev_priv
->display
.modeset_global_resources
=
12526 valleyview_modeset_global_resources
;
12527 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12530 /* Default just returns -ENODEV to indicate unsupported */
12531 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12533 switch (INTEL_INFO(dev
)->gen
) {
12535 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12539 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12544 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12548 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12551 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12552 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12556 intel_panel_init_backlight_funcs(dev
);
12560 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12561 * resume, or other times. This quirk makes sure that's the case for
12562 * affected systems.
12564 static void quirk_pipea_force(struct drm_device
*dev
)
12566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12568 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12569 DRM_INFO("applying pipe a force quirk\n");
12572 static void quirk_pipeb_force(struct drm_device
*dev
)
12574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12576 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12577 DRM_INFO("applying pipe b force quirk\n");
12581 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12583 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12586 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12587 DRM_INFO("applying lvds SSC disable quirk\n");
12591 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12594 static void quirk_invert_brightness(struct drm_device
*dev
)
12596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12597 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12598 DRM_INFO("applying inverted panel brightness quirk\n");
12601 /* Some VBT's incorrectly indicate no backlight is present */
12602 static void quirk_backlight_present(struct drm_device
*dev
)
12604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12605 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12606 DRM_INFO("applying backlight present quirk\n");
12609 struct intel_quirk
{
12611 int subsystem_vendor
;
12612 int subsystem_device
;
12613 void (*hook
)(struct drm_device
*dev
);
12616 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12617 struct intel_dmi_quirk
{
12618 void (*hook
)(struct drm_device
*dev
);
12619 const struct dmi_system_id (*dmi_id_list
)[];
12622 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12624 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12628 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12630 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12632 .callback
= intel_dmi_reverse_brightness
,
12633 .ident
= "NCR Corporation",
12634 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12635 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12638 { } /* terminating entry */
12640 .hook
= quirk_invert_brightness
,
12644 static struct intel_quirk intel_quirks
[] = {
12645 /* HP Mini needs pipe A force quirk (LP: #322104) */
12646 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12648 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12649 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12651 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12652 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12654 /* 830 needs to leave pipe A & dpll A up */
12655 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12657 /* 830 needs to leave pipe B & dpll B up */
12658 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12660 /* Lenovo U160 cannot use SSC on LVDS */
12661 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12663 /* Sony Vaio Y cannot use SSC on LVDS */
12664 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12666 /* Acer Aspire 5734Z must invert backlight brightness */
12667 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12669 /* Acer/eMachines G725 */
12670 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12672 /* Acer/eMachines e725 */
12673 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12675 /* Acer/Packard Bell NCL20 */
12676 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12678 /* Acer Aspire 4736Z */
12679 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12681 /* Acer Aspire 5336 */
12682 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12684 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12685 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12687 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12688 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12690 /* HP Chromebook 14 (Celeron 2955U) */
12691 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12694 static void intel_init_quirks(struct drm_device
*dev
)
12696 struct pci_dev
*d
= dev
->pdev
;
12699 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12700 struct intel_quirk
*q
= &intel_quirks
[i
];
12702 if (d
->device
== q
->device
&&
12703 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12704 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12705 (d
->subsystem_device
== q
->subsystem_device
||
12706 q
->subsystem_device
== PCI_ANY_ID
))
12709 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12710 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12711 intel_dmi_quirks
[i
].hook(dev
);
12715 /* Disable the VGA plane that we never use */
12716 static void i915_disable_vga(struct drm_device
*dev
)
12718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12720 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12722 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12723 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12724 outb(SR01
, VGA_SR_INDEX
);
12725 sr1
= inb(VGA_SR_DATA
);
12726 outb(sr1
| 1<<5, VGA_SR_DATA
);
12727 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12731 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12732 * from S3 without preserving (some of?) the other bits.
12734 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12735 POSTING_READ(vga_reg
);
12738 void intel_modeset_init_hw(struct drm_device
*dev
)
12740 intel_prepare_ddi(dev
);
12742 if (IS_VALLEYVIEW(dev
))
12743 vlv_update_cdclk(dev
);
12745 intel_init_clock_gating(dev
);
12747 intel_enable_gt_powersave(dev
);
12750 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12752 intel_suspend_hw(dev
);
12755 void intel_modeset_init(struct drm_device
*dev
)
12757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12760 struct intel_crtc
*crtc
;
12762 drm_mode_config_init(dev
);
12764 dev
->mode_config
.min_width
= 0;
12765 dev
->mode_config
.min_height
= 0;
12767 dev
->mode_config
.preferred_depth
= 24;
12768 dev
->mode_config
.prefer_shadow
= 1;
12770 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12772 intel_init_quirks(dev
);
12774 intel_init_pm(dev
);
12776 if (INTEL_INFO(dev
)->num_pipes
== 0)
12779 intel_init_display(dev
);
12781 if (IS_GEN2(dev
)) {
12782 dev
->mode_config
.max_width
= 2048;
12783 dev
->mode_config
.max_height
= 2048;
12784 } else if (IS_GEN3(dev
)) {
12785 dev
->mode_config
.max_width
= 4096;
12786 dev
->mode_config
.max_height
= 4096;
12788 dev
->mode_config
.max_width
= 8192;
12789 dev
->mode_config
.max_height
= 8192;
12792 if (IS_845G(dev
) || IS_I865G(dev
)) {
12793 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12794 dev
->mode_config
.cursor_height
= 1023;
12795 } else if (IS_GEN2(dev
)) {
12796 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12797 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12799 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12800 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12803 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12805 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12806 INTEL_INFO(dev
)->num_pipes
,
12807 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12809 for_each_pipe(dev_priv
, pipe
) {
12810 intel_crtc_init(dev
, pipe
);
12811 for_each_sprite(pipe
, sprite
) {
12812 ret
= intel_plane_init(dev
, pipe
, sprite
);
12814 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12815 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12819 intel_init_dpio(dev
);
12821 intel_shared_dpll_init(dev
);
12823 /* save the BIOS value before clobbering it */
12824 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
12825 /* Just disable it once at startup */
12826 i915_disable_vga(dev
);
12827 intel_setup_outputs(dev
);
12829 /* Just in case the BIOS is doing something questionable. */
12830 intel_disable_fbc(dev
);
12832 drm_modeset_lock_all(dev
);
12833 intel_modeset_setup_hw_state(dev
, false);
12834 drm_modeset_unlock_all(dev
);
12836 for_each_intel_crtc(dev
, crtc
) {
12841 * Note that reserving the BIOS fb up front prevents us
12842 * from stuffing other stolen allocations like the ring
12843 * on top. This prevents some ugliness at boot time, and
12844 * can even allow for smooth boot transitions if the BIOS
12845 * fb is large enough for the active pipe configuration.
12847 if (dev_priv
->display
.get_plane_config
) {
12848 dev_priv
->display
.get_plane_config(crtc
,
12849 &crtc
->plane_config
);
12851 * If the fb is shared between multiple heads, we'll
12852 * just get the first one.
12854 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12859 static void intel_enable_pipe_a(struct drm_device
*dev
)
12861 struct intel_connector
*connector
;
12862 struct drm_connector
*crt
= NULL
;
12863 struct intel_load_detect_pipe load_detect_temp
;
12864 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12866 /* We can't just switch on the pipe A, we need to set things up with a
12867 * proper mode and output configuration. As a gross hack, enable pipe A
12868 * by enabling the load detect pipe once. */
12869 list_for_each_entry(connector
,
12870 &dev
->mode_config
.connector_list
,
12872 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12873 crt
= &connector
->base
;
12881 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12882 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12886 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12888 struct drm_device
*dev
= crtc
->base
.dev
;
12889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12892 if (INTEL_INFO(dev
)->num_pipes
== 1)
12895 reg
= DSPCNTR(!crtc
->plane
);
12896 val
= I915_READ(reg
);
12898 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12899 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12905 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12907 struct drm_device
*dev
= crtc
->base
.dev
;
12908 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12911 /* Clear any frame start delays used for debugging left by the BIOS */
12912 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12913 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12915 /* restore vblank interrupts to correct state */
12917 drm_vblank_on(dev
, crtc
->pipe
);
12919 drm_vblank_off(dev
, crtc
->pipe
);
12921 /* We need to sanitize the plane -> pipe mapping first because this will
12922 * disable the crtc (and hence change the state) if it is wrong. Note
12923 * that gen4+ has a fixed plane -> pipe mapping. */
12924 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12925 struct intel_connector
*connector
;
12928 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12929 crtc
->base
.base
.id
);
12931 /* Pipe has the wrong plane attached and the plane is active.
12932 * Temporarily change the plane mapping and disable everything
12934 plane
= crtc
->plane
;
12935 crtc
->plane
= !plane
;
12936 crtc
->primary_enabled
= true;
12937 dev_priv
->display
.crtc_disable(&crtc
->base
);
12938 crtc
->plane
= plane
;
12940 /* ... and break all links. */
12941 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12943 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12946 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12947 connector
->base
.encoder
= NULL
;
12949 /* multiple connectors may have the same encoder:
12950 * handle them and break crtc link separately */
12951 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12953 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12954 connector
->encoder
->base
.crtc
= NULL
;
12955 connector
->encoder
->connectors_active
= false;
12958 WARN_ON(crtc
->active
);
12959 crtc
->base
.enabled
= false;
12962 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12963 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12964 /* BIOS forgot to enable pipe A, this mostly happens after
12965 * resume. Force-enable the pipe to fix this, the update_dpms
12966 * call below we restore the pipe to the right state, but leave
12967 * the required bits on. */
12968 intel_enable_pipe_a(dev
);
12971 /* Adjust the state of the output pipe according to whether we
12972 * have active connectors/encoders. */
12973 intel_crtc_update_dpms(&crtc
->base
);
12975 if (crtc
->active
!= crtc
->base
.enabled
) {
12976 struct intel_encoder
*encoder
;
12978 /* This can happen either due to bugs in the get_hw_state
12979 * functions or because the pipe is force-enabled due to the
12981 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12982 crtc
->base
.base
.id
,
12983 crtc
->base
.enabled
? "enabled" : "disabled",
12984 crtc
->active
? "enabled" : "disabled");
12986 crtc
->base
.enabled
= crtc
->active
;
12988 /* Because we only establish the connector -> encoder ->
12989 * crtc links if something is active, this means the
12990 * crtc is now deactivated. Break the links. connector
12991 * -> encoder links are only establish when things are
12992 * actually up, hence no need to break them. */
12993 WARN_ON(crtc
->active
);
12995 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
12996 WARN_ON(encoder
->connectors_active
);
12997 encoder
->base
.crtc
= NULL
;
13001 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
13003 * We start out with underrun reporting disabled to avoid races.
13004 * For correct bookkeeping mark this on active crtcs.
13006 * Also on gmch platforms we dont have any hardware bits to
13007 * disable the underrun reporting. Which means we need to start
13008 * out with underrun reporting disabled also on inactive pipes,
13009 * since otherwise we'll complain about the garbage we read when
13010 * e.g. coming up after runtime pm.
13012 * No protection against concurrent access is required - at
13013 * worst a fifo underrun happens which also sets this to false.
13015 crtc
->cpu_fifo_underrun_disabled
= true;
13016 crtc
->pch_fifo_underrun_disabled
= true;
13018 update_scanline_offset(crtc
);
13022 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13024 struct intel_connector
*connector
;
13025 struct drm_device
*dev
= encoder
->base
.dev
;
13027 /* We need to check both for a crtc link (meaning that the
13028 * encoder is active and trying to read from a pipe) and the
13029 * pipe itself being active. */
13030 bool has_active_crtc
= encoder
->base
.crtc
&&
13031 to_intel_crtc(encoder
->base
.crtc
)->active
;
13033 if (encoder
->connectors_active
&& !has_active_crtc
) {
13034 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13035 encoder
->base
.base
.id
,
13036 encoder
->base
.name
);
13038 /* Connector is active, but has no active pipe. This is
13039 * fallout from our resume register restoring. Disable
13040 * the encoder manually again. */
13041 if (encoder
->base
.crtc
) {
13042 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13043 encoder
->base
.base
.id
,
13044 encoder
->base
.name
);
13045 encoder
->disable(encoder
);
13046 if (encoder
->post_disable
)
13047 encoder
->post_disable(encoder
);
13049 encoder
->base
.crtc
= NULL
;
13050 encoder
->connectors_active
= false;
13052 /* Inconsistent output/port/pipe state happens presumably due to
13053 * a bug in one of the get_hw_state functions. Or someplace else
13054 * in our code, like the register restore mess on resume. Clamp
13055 * things to off as a safer default. */
13056 list_for_each_entry(connector
,
13057 &dev
->mode_config
.connector_list
,
13059 if (connector
->encoder
!= encoder
)
13061 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13062 connector
->base
.encoder
= NULL
;
13065 /* Enabled encoders without active connectors will be fixed in
13066 * the crtc fixup. */
13069 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13072 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13074 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13075 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13076 i915_disable_vga(dev
);
13080 void i915_redisable_vga(struct drm_device
*dev
)
13082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13084 /* This function can be called both from intel_modeset_setup_hw_state or
13085 * at a very early point in our resume sequence, where the power well
13086 * structures are not yet restored. Since this function is at a very
13087 * paranoid "someone might have enabled VGA while we were not looking"
13088 * level, just check if the power well is enabled instead of trying to
13089 * follow the "don't touch the power well if we don't need it" policy
13090 * the rest of the driver uses. */
13091 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13094 i915_redisable_vga_power_on(dev
);
13097 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13099 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13104 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13107 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13111 struct intel_crtc
*crtc
;
13112 struct intel_encoder
*encoder
;
13113 struct intel_connector
*connector
;
13116 for_each_intel_crtc(dev
, crtc
) {
13117 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13119 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13121 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13124 crtc
->base
.enabled
= crtc
->active
;
13125 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13127 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13128 crtc
->base
.base
.id
,
13129 crtc
->active
? "enabled" : "disabled");
13132 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13133 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13135 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13137 for_each_intel_crtc(dev
, crtc
) {
13138 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13141 pll
->refcount
= pll
->active
;
13143 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13144 pll
->name
, pll
->refcount
, pll
->on
);
13147 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13150 for_each_intel_encoder(dev
, encoder
) {
13153 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13154 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13155 encoder
->base
.crtc
= &crtc
->base
;
13156 encoder
->get_config(encoder
, &crtc
->config
);
13158 encoder
->base
.crtc
= NULL
;
13161 encoder
->connectors_active
= false;
13162 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13163 encoder
->base
.base
.id
,
13164 encoder
->base
.name
,
13165 encoder
->base
.crtc
? "enabled" : "disabled",
13169 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13171 if (connector
->get_hw_state(connector
)) {
13172 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13173 connector
->encoder
->connectors_active
= true;
13174 connector
->base
.encoder
= &connector
->encoder
->base
;
13176 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13177 connector
->base
.encoder
= NULL
;
13179 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13180 connector
->base
.base
.id
,
13181 connector
->base
.name
,
13182 connector
->base
.encoder
? "enabled" : "disabled");
13186 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13187 * and i915 state tracking structures. */
13188 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13189 bool force_restore
)
13191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13193 struct intel_crtc
*crtc
;
13194 struct intel_encoder
*encoder
;
13197 intel_modeset_readout_hw_state(dev
);
13200 * Now that we have the config, copy it to each CRTC struct
13201 * Note that this could go away if we move to using crtc_config
13202 * checking everywhere.
13204 for_each_intel_crtc(dev
, crtc
) {
13205 if (crtc
->active
&& i915
.fastboot
) {
13206 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13207 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13208 crtc
->base
.base
.id
);
13209 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13213 /* HW state is read out, now we need to sanitize this mess. */
13214 for_each_intel_encoder(dev
, encoder
) {
13215 intel_sanitize_encoder(encoder
);
13218 for_each_pipe(dev_priv
, pipe
) {
13219 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13220 intel_sanitize_crtc(crtc
);
13221 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13224 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13225 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13227 if (!pll
->on
|| pll
->active
)
13230 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13232 pll
->disable(dev_priv
, pll
);
13236 if (HAS_PCH_SPLIT(dev
))
13237 ilk_wm_get_hw_state(dev
);
13239 if (force_restore
) {
13240 i915_redisable_vga(dev
);
13243 * We need to use raw interfaces for restoring state to avoid
13244 * checking (bogus) intermediate states.
13246 for_each_pipe(dev_priv
, pipe
) {
13247 struct drm_crtc
*crtc
=
13248 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13250 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13251 crtc
->primary
->fb
);
13254 intel_modeset_update_staged_output_state(dev
);
13257 intel_modeset_check_state(dev
);
13260 void intel_modeset_gem_init(struct drm_device
*dev
)
13262 struct drm_crtc
*c
;
13263 struct drm_i915_gem_object
*obj
;
13265 mutex_lock(&dev
->struct_mutex
);
13266 intel_init_gt_powersave(dev
);
13267 mutex_unlock(&dev
->struct_mutex
);
13269 intel_modeset_init_hw(dev
);
13271 intel_setup_overlay(dev
);
13274 * Make sure any fbs we allocated at startup are properly
13275 * pinned & fenced. When we do the allocation it's too early
13278 mutex_lock(&dev
->struct_mutex
);
13279 for_each_crtc(dev
, c
) {
13280 obj
= intel_fb_obj(c
->primary
->fb
);
13284 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13285 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13286 to_intel_crtc(c
)->pipe
);
13287 drm_framebuffer_unreference(c
->primary
->fb
);
13288 c
->primary
->fb
= NULL
;
13291 mutex_unlock(&dev
->struct_mutex
);
13294 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13296 struct drm_connector
*connector
= &intel_connector
->base
;
13298 intel_panel_destroy_backlight(connector
);
13299 drm_connector_unregister(connector
);
13302 void intel_modeset_cleanup(struct drm_device
*dev
)
13304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13305 struct drm_connector
*connector
;
13308 * Interrupts and polling as the first thing to avoid creating havoc.
13309 * Too much stuff here (turning of rps, connectors, ...) would
13310 * experience fancy races otherwise.
13312 drm_irq_uninstall(dev
);
13313 intel_hpd_cancel_work(dev_priv
);
13314 dev_priv
->pm
._irqs_disabled
= true;
13317 * Due to the hpd irq storm handling the hotplug work can re-arm the
13318 * poll handlers. Hence disable polling after hpd handling is shut down.
13320 drm_kms_helper_poll_fini(dev
);
13322 mutex_lock(&dev
->struct_mutex
);
13324 intel_unregister_dsm_handler();
13326 intel_disable_fbc(dev
);
13328 intel_disable_gt_powersave(dev
);
13330 ironlake_teardown_rc6(dev
);
13332 mutex_unlock(&dev
->struct_mutex
);
13334 /* flush any delayed tasks or pending work */
13335 flush_scheduled_work();
13337 /* destroy the backlight and sysfs files before encoders/connectors */
13338 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13339 struct intel_connector
*intel_connector
;
13341 intel_connector
= to_intel_connector(connector
);
13342 intel_connector
->unregister(intel_connector
);
13345 drm_mode_config_cleanup(dev
);
13347 intel_cleanup_overlay(dev
);
13349 mutex_lock(&dev
->struct_mutex
);
13350 intel_cleanup_gt_powersave(dev
);
13351 mutex_unlock(&dev
->struct_mutex
);
13355 * Return which encoder is currently attached for connector.
13357 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13359 return &intel_attached_encoder(connector
)->base
;
13362 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13363 struct intel_encoder
*encoder
)
13365 connector
->encoder
= encoder
;
13366 drm_mode_connector_attach_encoder(&connector
->base
,
13371 * set vga decode state - true == enable VGA decode
13373 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13376 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13379 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13380 DRM_ERROR("failed to read control word\n");
13384 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13388 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13390 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13392 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13393 DRM_ERROR("failed to write control word\n");
13400 struct intel_display_error_state
{
13402 u32 power_well_driver
;
13404 int num_transcoders
;
13406 struct intel_cursor_error_state
{
13411 } cursor
[I915_MAX_PIPES
];
13413 struct intel_pipe_error_state
{
13414 bool power_domain_on
;
13417 } pipe
[I915_MAX_PIPES
];
13419 struct intel_plane_error_state
{
13427 } plane
[I915_MAX_PIPES
];
13429 struct intel_transcoder_error_state
{
13430 bool power_domain_on
;
13431 enum transcoder cpu_transcoder
;
13444 struct intel_display_error_state
*
13445 intel_display_capture_error_state(struct drm_device
*dev
)
13447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13448 struct intel_display_error_state
*error
;
13449 int transcoders
[] = {
13457 if (INTEL_INFO(dev
)->num_pipes
== 0)
13460 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13464 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13465 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13467 for_each_pipe(dev_priv
, i
) {
13468 error
->pipe
[i
].power_domain_on
=
13469 intel_display_power_enabled_unlocked(dev_priv
,
13470 POWER_DOMAIN_PIPE(i
));
13471 if (!error
->pipe
[i
].power_domain_on
)
13474 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13475 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13476 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13478 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13479 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13480 if (INTEL_INFO(dev
)->gen
<= 3) {
13481 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13482 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13484 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13485 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13486 if (INTEL_INFO(dev
)->gen
>= 4) {
13487 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13488 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13491 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13493 if (HAS_GMCH_DISPLAY(dev
))
13494 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13497 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13498 if (HAS_DDI(dev_priv
->dev
))
13499 error
->num_transcoders
++; /* Account for eDP. */
13501 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13502 enum transcoder cpu_transcoder
= transcoders
[i
];
13504 error
->transcoder
[i
].power_domain_on
=
13505 intel_display_power_enabled_unlocked(dev_priv
,
13506 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13507 if (!error
->transcoder
[i
].power_domain_on
)
13510 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13512 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13513 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13514 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13515 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13516 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13517 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13518 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13524 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13527 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13528 struct drm_device
*dev
,
13529 struct intel_display_error_state
*error
)
13531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13537 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13538 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13539 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13540 error
->power_well_driver
);
13541 for_each_pipe(dev_priv
, i
) {
13542 err_printf(m
, "Pipe [%d]:\n", i
);
13543 err_printf(m
, " Power: %s\n",
13544 error
->pipe
[i
].power_domain_on
? "on" : "off");
13545 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13546 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13548 err_printf(m
, "Plane [%d]:\n", i
);
13549 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13550 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13551 if (INTEL_INFO(dev
)->gen
<= 3) {
13552 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13553 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13555 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13556 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13557 if (INTEL_INFO(dev
)->gen
>= 4) {
13558 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13559 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13562 err_printf(m
, "Cursor [%d]:\n", i
);
13563 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13564 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13565 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13568 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13569 err_printf(m
, "CPU transcoder: %c\n",
13570 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13571 err_printf(m
, " Power: %s\n",
13572 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13573 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13574 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13575 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13576 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13577 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13578 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13579 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13583 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13585 struct intel_crtc
*crtc
;
13587 for_each_intel_crtc(dev
, crtc
) {
13588 struct intel_unpin_work
*work
;
13589 unsigned long irqflags
;
13591 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13593 work
= crtc
->unpin_work
;
13595 if (work
&& work
->event
&&
13596 work
->event
->base
.file_priv
== file
) {
13597 kfree(work
->event
);
13598 work
->event
= NULL
;
13601 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);