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drm/i915: Allow pixel clock up to 95% of cdclk on CHV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(dev_priv, pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(dev_priv, pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196 {
2197 int tile_height;
2198 uint32_t bits_per_pixel;
2199
2200 switch (fb_format_modifier) {
2201 case DRM_FORMAT_MOD_NONE:
2202 tile_height = 1;
2203 break;
2204 case I915_FORMAT_MOD_X_TILED:
2205 tile_height = IS_GEN2(dev) ? 16 : 8;
2206 break;
2207 case I915_FORMAT_MOD_Y_TILED:
2208 tile_height = 32;
2209 break;
2210 case I915_FORMAT_MOD_Yf_TILED:
2211 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2212 switch (bits_per_pixel) {
2213 default:
2214 case 8:
2215 tile_height = 64;
2216 break;
2217 case 16:
2218 case 32:
2219 tile_height = 32;
2220 break;
2221 case 64:
2222 tile_height = 16;
2223 break;
2224 case 128:
2225 WARN_ONCE(1,
2226 "128-bit pixels are not supported for display!");
2227 tile_height = 16;
2228 break;
2229 }
2230 break;
2231 default:
2232 MISSING_CASE(fb_format_modifier);
2233 tile_height = 1;
2234 break;
2235 }
2236
2237 return ALIGN(height, tile_height);
2238 }
2239
2240 int
2241 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2242 struct drm_framebuffer *fb,
2243 struct intel_engine_cs *pipelined)
2244 {
2245 struct drm_device *dev = fb->dev;
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 u32 alignment;
2249 int ret;
2250
2251 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2252
2253 switch (fb->modifier[0]) {
2254 case DRM_FORMAT_MOD_NONE:
2255 if (INTEL_INFO(dev)->gen >= 9)
2256 alignment = 256 * 1024;
2257 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2258 alignment = 128 * 1024;
2259 else if (INTEL_INFO(dev)->gen >= 4)
2260 alignment = 4 * 1024;
2261 else
2262 alignment = 64 * 1024;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 if (INTEL_INFO(dev)->gen >= 9)
2266 alignment = 256 * 1024;
2267 else {
2268 /* pin() will align the object as required by fence */
2269 alignment = 0;
2270 }
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 case I915_FORMAT_MOD_Yf_TILED:
2274 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2275 "Y tiling bo slipped through, driver bug!\n"))
2276 return -EINVAL;
2277 alignment = 1 * 1024 * 1024;
2278 break;
2279 default:
2280 MISSING_CASE(fb->modifier[0]);
2281 return -EINVAL;
2282 }
2283
2284 /* Note that the w/a also requires 64 PTE of padding following the
2285 * bo. We currently fill all unused PTE with the shadow page and so
2286 * we should always have valid PTE following the scanout preventing
2287 * the VT-d warning.
2288 */
2289 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2290 alignment = 256 * 1024;
2291
2292 /*
2293 * Global gtt pte registers are special registers which actually forward
2294 * writes to a chunk of system memory. Which means that there is no risk
2295 * that the register values disappear as soon as we call
2296 * intel_runtime_pm_put(), so it is correct to wrap only the
2297 * pin/unpin/fence and not more.
2298 */
2299 intel_runtime_pm_get(dev_priv);
2300
2301 dev_priv->mm.interruptible = false;
2302 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2303 if (ret)
2304 goto err_interruptible;
2305
2306 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2307 * fence, whereas 965+ only requires a fence if using
2308 * framebuffer compression. For simplicity, we always install
2309 * a fence as the cost is not that onerous.
2310 */
2311 ret = i915_gem_object_get_fence(obj);
2312 if (ret)
2313 goto err_unpin;
2314
2315 i915_gem_object_pin_fence(obj);
2316
2317 dev_priv->mm.interruptible = true;
2318 intel_runtime_pm_put(dev_priv);
2319 return 0;
2320
2321 err_unpin:
2322 i915_gem_object_unpin_from_display_plane(obj);
2323 err_interruptible:
2324 dev_priv->mm.interruptible = true;
2325 intel_runtime_pm_put(dev_priv);
2326 return ret;
2327 }
2328
2329 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2330 {
2331 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2332
2333 i915_gem_object_unpin_fence(obj);
2334 i915_gem_object_unpin_from_display_plane(obj);
2335 }
2336
2337 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2338 * is assumed to be a power-of-two. */
2339 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2340 unsigned int tiling_mode,
2341 unsigned int cpp,
2342 unsigned int pitch)
2343 {
2344 if (tiling_mode != I915_TILING_NONE) {
2345 unsigned int tile_rows, tiles;
2346
2347 tile_rows = *y / 8;
2348 *y %= 8;
2349
2350 tiles = *x / (512/cpp);
2351 *x %= 512/cpp;
2352
2353 return tile_rows * pitch * 8 + tiles * 4096;
2354 } else {
2355 unsigned int offset;
2356
2357 offset = *y * pitch + *x * cpp;
2358 *y = 0;
2359 *x = (offset & 4095) / cpp;
2360 return offset & -4096;
2361 }
2362 }
2363
2364 static int i9xx_format_to_fourcc(int format)
2365 {
2366 switch (format) {
2367 case DISPPLANE_8BPP:
2368 return DRM_FORMAT_C8;
2369 case DISPPLANE_BGRX555:
2370 return DRM_FORMAT_XRGB1555;
2371 case DISPPLANE_BGRX565:
2372 return DRM_FORMAT_RGB565;
2373 default:
2374 case DISPPLANE_BGRX888:
2375 return DRM_FORMAT_XRGB8888;
2376 case DISPPLANE_RGBX888:
2377 return DRM_FORMAT_XBGR8888;
2378 case DISPPLANE_BGRX101010:
2379 return DRM_FORMAT_XRGB2101010;
2380 case DISPPLANE_RGBX101010:
2381 return DRM_FORMAT_XBGR2101010;
2382 }
2383 }
2384
2385 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2386 {
2387 switch (format) {
2388 case PLANE_CTL_FORMAT_RGB_565:
2389 return DRM_FORMAT_RGB565;
2390 default:
2391 case PLANE_CTL_FORMAT_XRGB_8888:
2392 if (rgb_order) {
2393 if (alpha)
2394 return DRM_FORMAT_ABGR8888;
2395 else
2396 return DRM_FORMAT_XBGR8888;
2397 } else {
2398 if (alpha)
2399 return DRM_FORMAT_ARGB8888;
2400 else
2401 return DRM_FORMAT_XRGB8888;
2402 }
2403 case PLANE_CTL_FORMAT_XRGB_2101010:
2404 if (rgb_order)
2405 return DRM_FORMAT_XBGR2101010;
2406 else
2407 return DRM_FORMAT_XRGB2101010;
2408 }
2409 }
2410
2411 static bool
2412 intel_alloc_plane_obj(struct intel_crtc *crtc,
2413 struct intel_initial_plane_config *plane_config)
2414 {
2415 struct drm_device *dev = crtc->base.dev;
2416 struct drm_i915_gem_object *obj = NULL;
2417 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2418 struct drm_framebuffer *fb = &plane_config->fb->base;
2419 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2420 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2421 PAGE_SIZE);
2422
2423 size_aligned -= base_aligned;
2424
2425 if (plane_config->size == 0)
2426 return false;
2427
2428 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2429 base_aligned,
2430 base_aligned,
2431 size_aligned);
2432 if (!obj)
2433 return false;
2434
2435 obj->tiling_mode = plane_config->tiling;
2436 if (obj->tiling_mode == I915_TILING_X)
2437 obj->stride = fb->pitches[0];
2438
2439 mode_cmd.pixel_format = fb->pixel_format;
2440 mode_cmd.width = fb->width;
2441 mode_cmd.height = fb->height;
2442 mode_cmd.pitches[0] = fb->pitches[0];
2443 mode_cmd.modifier[0] = fb->modifier[0];
2444 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2445
2446 mutex_lock(&dev->struct_mutex);
2447
2448 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2449 &mode_cmd, obj)) {
2450 DRM_DEBUG_KMS("intel fb init failed\n");
2451 goto out_unref_obj;
2452 }
2453
2454 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2455 mutex_unlock(&dev->struct_mutex);
2456
2457 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2458 return true;
2459
2460 out_unref_obj:
2461 drm_gem_object_unreference(&obj->base);
2462 mutex_unlock(&dev->struct_mutex);
2463 return false;
2464 }
2465
2466 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2467 static void
2468 update_state_fb(struct drm_plane *plane)
2469 {
2470 if (plane->fb == plane->state->fb)
2471 return;
2472
2473 if (plane->state->fb)
2474 drm_framebuffer_unreference(plane->state->fb);
2475 plane->state->fb = plane->fb;
2476 if (plane->state->fb)
2477 drm_framebuffer_reference(plane->state->fb);
2478 }
2479
2480 static void
2481 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2482 struct intel_initial_plane_config *plane_config)
2483 {
2484 struct drm_device *dev = intel_crtc->base.dev;
2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct drm_crtc *c;
2487 struct intel_crtc *i;
2488 struct drm_i915_gem_object *obj;
2489
2490 if (!plane_config->fb)
2491 return;
2492
2493 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2494 struct drm_plane *primary = intel_crtc->base.primary;
2495
2496 primary->fb = &plane_config->fb->base;
2497 primary->state->crtc = &intel_crtc->base;
2498 update_state_fb(primary);
2499
2500 return;
2501 }
2502
2503 kfree(plane_config->fb);
2504
2505 /*
2506 * Failed to alloc the obj, check to see if we should share
2507 * an fb with another CRTC instead
2508 */
2509 for_each_crtc(dev, c) {
2510 i = to_intel_crtc(c);
2511
2512 if (c == &intel_crtc->base)
2513 continue;
2514
2515 if (!i->active)
2516 continue;
2517
2518 obj = intel_fb_obj(c->primary->fb);
2519 if (obj == NULL)
2520 continue;
2521
2522 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2523 struct drm_plane *primary = intel_crtc->base.primary;
2524
2525 if (obj->tiling_mode != I915_TILING_NONE)
2526 dev_priv->preserve_bios_swizzle = true;
2527
2528 drm_framebuffer_reference(c->primary->fb);
2529 primary->fb = c->primary->fb;
2530 primary->state->crtc = &intel_crtc->base;
2531 update_state_fb(intel_crtc->base.primary);
2532 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2533 break;
2534 }
2535 }
2536
2537 }
2538
2539 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2540 struct drm_framebuffer *fb,
2541 int x, int y)
2542 {
2543 struct drm_device *dev = crtc->dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2546 struct drm_i915_gem_object *obj;
2547 int plane = intel_crtc->plane;
2548 unsigned long linear_offset;
2549 u32 dspcntr;
2550 u32 reg = DSPCNTR(plane);
2551 int pixel_size;
2552
2553 if (!intel_crtc->primary_enabled) {
2554 I915_WRITE(reg, 0);
2555 if (INTEL_INFO(dev)->gen >= 4)
2556 I915_WRITE(DSPSURF(plane), 0);
2557 else
2558 I915_WRITE(DSPADDR(plane), 0);
2559 POSTING_READ(reg);
2560 return;
2561 }
2562
2563 obj = intel_fb_obj(fb);
2564 if (WARN_ON(obj == NULL))
2565 return;
2566
2567 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2568
2569 dspcntr = DISPPLANE_GAMMA_ENABLE;
2570
2571 dspcntr |= DISPLAY_PLANE_ENABLE;
2572
2573 if (INTEL_INFO(dev)->gen < 4) {
2574 if (intel_crtc->pipe == PIPE_B)
2575 dspcntr |= DISPPLANE_SEL_PIPE_B;
2576
2577 /* pipesrc and dspsize control the size that is scaled from,
2578 * which should always be the user's requested size.
2579 */
2580 I915_WRITE(DSPSIZE(plane),
2581 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2582 (intel_crtc->config->pipe_src_w - 1));
2583 I915_WRITE(DSPPOS(plane), 0);
2584 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2585 I915_WRITE(PRIMSIZE(plane),
2586 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2587 (intel_crtc->config->pipe_src_w - 1));
2588 I915_WRITE(PRIMPOS(plane), 0);
2589 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2590 }
2591
2592 switch (fb->pixel_format) {
2593 case DRM_FORMAT_C8:
2594 dspcntr |= DISPPLANE_8BPP;
2595 break;
2596 case DRM_FORMAT_XRGB1555:
2597 case DRM_FORMAT_ARGB1555:
2598 dspcntr |= DISPPLANE_BGRX555;
2599 break;
2600 case DRM_FORMAT_RGB565:
2601 dspcntr |= DISPPLANE_BGRX565;
2602 break;
2603 case DRM_FORMAT_XRGB8888:
2604 case DRM_FORMAT_ARGB8888:
2605 dspcntr |= DISPPLANE_BGRX888;
2606 break;
2607 case DRM_FORMAT_XBGR8888:
2608 case DRM_FORMAT_ABGR8888:
2609 dspcntr |= DISPPLANE_RGBX888;
2610 break;
2611 case DRM_FORMAT_XRGB2101010:
2612 case DRM_FORMAT_ARGB2101010:
2613 dspcntr |= DISPPLANE_BGRX101010;
2614 break;
2615 case DRM_FORMAT_XBGR2101010:
2616 case DRM_FORMAT_ABGR2101010:
2617 dspcntr |= DISPPLANE_RGBX101010;
2618 break;
2619 default:
2620 BUG();
2621 }
2622
2623 if (INTEL_INFO(dev)->gen >= 4 &&
2624 obj->tiling_mode != I915_TILING_NONE)
2625 dspcntr |= DISPPLANE_TILED;
2626
2627 if (IS_G4X(dev))
2628 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2629
2630 linear_offset = y * fb->pitches[0] + x * pixel_size;
2631
2632 if (INTEL_INFO(dev)->gen >= 4) {
2633 intel_crtc->dspaddr_offset =
2634 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2635 pixel_size,
2636 fb->pitches[0]);
2637 linear_offset -= intel_crtc->dspaddr_offset;
2638 } else {
2639 intel_crtc->dspaddr_offset = linear_offset;
2640 }
2641
2642 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2643 dspcntr |= DISPPLANE_ROTATE_180;
2644
2645 x += (intel_crtc->config->pipe_src_w - 1);
2646 y += (intel_crtc->config->pipe_src_h - 1);
2647
2648 /* Finding the last pixel of the last line of the display
2649 data and adding to linear_offset*/
2650 linear_offset +=
2651 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2652 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2653 }
2654
2655 I915_WRITE(reg, dspcntr);
2656
2657 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2658 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2659 fb->pitches[0]);
2660 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2661 if (INTEL_INFO(dev)->gen >= 4) {
2662 I915_WRITE(DSPSURF(plane),
2663 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2664 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2665 I915_WRITE(DSPLINOFF(plane), linear_offset);
2666 } else
2667 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2668 POSTING_READ(reg);
2669 }
2670
2671 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2672 struct drm_framebuffer *fb,
2673 int x, int y)
2674 {
2675 struct drm_device *dev = crtc->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2678 struct drm_i915_gem_object *obj;
2679 int plane = intel_crtc->plane;
2680 unsigned long linear_offset;
2681 u32 dspcntr;
2682 u32 reg = DSPCNTR(plane);
2683 int pixel_size;
2684
2685 if (!intel_crtc->primary_enabled) {
2686 I915_WRITE(reg, 0);
2687 I915_WRITE(DSPSURF(plane), 0);
2688 POSTING_READ(reg);
2689 return;
2690 }
2691
2692 obj = intel_fb_obj(fb);
2693 if (WARN_ON(obj == NULL))
2694 return;
2695
2696 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2697
2698 dspcntr = DISPPLANE_GAMMA_ENABLE;
2699
2700 dspcntr |= DISPLAY_PLANE_ENABLE;
2701
2702 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2703 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2704
2705 switch (fb->pixel_format) {
2706 case DRM_FORMAT_C8:
2707 dspcntr |= DISPPLANE_8BPP;
2708 break;
2709 case DRM_FORMAT_RGB565:
2710 dspcntr |= DISPPLANE_BGRX565;
2711 break;
2712 case DRM_FORMAT_XRGB8888:
2713 case DRM_FORMAT_ARGB8888:
2714 dspcntr |= DISPPLANE_BGRX888;
2715 break;
2716 case DRM_FORMAT_XBGR8888:
2717 case DRM_FORMAT_ABGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
2721 case DRM_FORMAT_ARGB2101010:
2722 dspcntr |= DISPPLANE_BGRX101010;
2723 break;
2724 case DRM_FORMAT_XBGR2101010:
2725 case DRM_FORMAT_ABGR2101010:
2726 dspcntr |= DISPPLANE_RGBX101010;
2727 break;
2728 default:
2729 BUG();
2730 }
2731
2732 if (obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2734
2735 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739 intel_crtc->dspaddr_offset =
2740 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2741 pixel_size,
2742 fb->pitches[0]);
2743 linear_offset -= intel_crtc->dspaddr_offset;
2744 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2745 dspcntr |= DISPPLANE_ROTATE_180;
2746
2747 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2748 x += (intel_crtc->config->pipe_src_w - 1);
2749 y += (intel_crtc->config->pipe_src_h - 1);
2750
2751 /* Finding the last pixel of the last line of the display
2752 data and adding to linear_offset*/
2753 linear_offset +=
2754 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2755 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2756 }
2757 }
2758
2759 I915_WRITE(reg, dspcntr);
2760
2761 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2762 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2763 fb->pitches[0]);
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 I915_WRITE(DSPSURF(plane),
2766 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2767 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2768 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2769 } else {
2770 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2771 I915_WRITE(DSPLINOFF(plane), linear_offset);
2772 }
2773 POSTING_READ(reg);
2774 }
2775
2776 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2777 uint32_t pixel_format)
2778 {
2779 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2780
2781 /*
2782 * The stride is either expressed as a multiple of 64 bytes
2783 * chunks for linear buffers or in number of tiles for tiled
2784 * buffers.
2785 */
2786 switch (fb_modifier) {
2787 case DRM_FORMAT_MOD_NONE:
2788 return 64;
2789 case I915_FORMAT_MOD_X_TILED:
2790 if (INTEL_INFO(dev)->gen == 2)
2791 return 128;
2792 return 512;
2793 case I915_FORMAT_MOD_Y_TILED:
2794 /* No need to check for old gens and Y tiling since this is
2795 * about the display engine and those will be blocked before
2796 * we get here.
2797 */
2798 return 128;
2799 case I915_FORMAT_MOD_Yf_TILED:
2800 if (bits_per_pixel == 8)
2801 return 64;
2802 else
2803 return 128;
2804 default:
2805 MISSING_CASE(fb_modifier);
2806 return 64;
2807 }
2808 }
2809
2810 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2811 struct drm_framebuffer *fb,
2812 int x, int y)
2813 {
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 struct drm_i915_gem_object *obj;
2818 int pipe = intel_crtc->pipe;
2819 u32 plane_ctl, stride_div;
2820
2821 if (!intel_crtc->primary_enabled) {
2822 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2823 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2824 POSTING_READ(PLANE_CTL(pipe, 0));
2825 return;
2826 }
2827
2828 plane_ctl = PLANE_CTL_ENABLE |
2829 PLANE_CTL_PIPE_GAMMA_ENABLE |
2830 PLANE_CTL_PIPE_CSC_ENABLE;
2831
2832 switch (fb->pixel_format) {
2833 case DRM_FORMAT_RGB565:
2834 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2835 break;
2836 case DRM_FORMAT_XRGB8888:
2837 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2838 break;
2839 case DRM_FORMAT_ARGB8888:
2840 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2841 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2842 break;
2843 case DRM_FORMAT_XBGR8888:
2844 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2845 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2846 break;
2847 case DRM_FORMAT_ABGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2851 break;
2852 case DRM_FORMAT_XRGB2101010:
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2854 break;
2855 case DRM_FORMAT_XBGR2101010:
2856 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858 break;
2859 default:
2860 BUG();
2861 }
2862
2863 switch (fb->modifier[0]) {
2864 case DRM_FORMAT_MOD_NONE:
2865 break;
2866 case I915_FORMAT_MOD_X_TILED:
2867 plane_ctl |= PLANE_CTL_TILED_X;
2868 break;
2869 case I915_FORMAT_MOD_Y_TILED:
2870 plane_ctl |= PLANE_CTL_TILED_Y;
2871 break;
2872 case I915_FORMAT_MOD_Yf_TILED:
2873 plane_ctl |= PLANE_CTL_TILED_YF;
2874 break;
2875 default:
2876 MISSING_CASE(fb->modifier[0]);
2877 }
2878
2879 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2880 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2881 plane_ctl |= PLANE_CTL_ROTATE_180;
2882
2883 obj = intel_fb_obj(fb);
2884 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2885 fb->pixel_format);
2886
2887 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2888
2889 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2890 i915_gem_obj_ggtt_offset(obj),
2891 x, y, fb->width, fb->height,
2892 fb->pitches[0]);
2893
2894 I915_WRITE(PLANE_POS(pipe, 0), 0);
2895 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2896 I915_WRITE(PLANE_SIZE(pipe, 0),
2897 (intel_crtc->config->pipe_src_h - 1) << 16 |
2898 (intel_crtc->config->pipe_src_w - 1));
2899 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2900 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2901
2902 POSTING_READ(PLANE_SURF(pipe, 0));
2903 }
2904
2905 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2906 static int
2907 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2908 int x, int y, enum mode_set_atomic state)
2909 {
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912
2913 if (dev_priv->display.disable_fbc)
2914 dev_priv->display.disable_fbc(dev);
2915
2916 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2917
2918 return 0;
2919 }
2920
2921 static void intel_complete_page_flips(struct drm_device *dev)
2922 {
2923 struct drm_crtc *crtc;
2924
2925 for_each_crtc(dev, crtc) {
2926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2927 enum plane plane = intel_crtc->plane;
2928
2929 intel_prepare_page_flip(dev, plane);
2930 intel_finish_page_flip_plane(dev, plane);
2931 }
2932 }
2933
2934 static void intel_update_primary_planes(struct drm_device *dev)
2935 {
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 struct drm_crtc *crtc;
2938
2939 for_each_crtc(dev, crtc) {
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941
2942 drm_modeset_lock(&crtc->mutex, NULL);
2943 /*
2944 * FIXME: Once we have proper support for primary planes (and
2945 * disabling them without disabling the entire crtc) allow again
2946 * a NULL crtc->primary->fb.
2947 */
2948 if (intel_crtc->active && crtc->primary->fb)
2949 dev_priv->display.update_primary_plane(crtc,
2950 crtc->primary->fb,
2951 crtc->x,
2952 crtc->y);
2953 drm_modeset_unlock(&crtc->mutex);
2954 }
2955 }
2956
2957 void intel_prepare_reset(struct drm_device *dev)
2958 {
2959 struct drm_i915_private *dev_priv = to_i915(dev);
2960 struct intel_crtc *crtc;
2961
2962 /* no reset support for gen2 */
2963 if (IS_GEN2(dev))
2964 return;
2965
2966 /* reset doesn't touch the display */
2967 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2968 return;
2969
2970 drm_modeset_lock_all(dev);
2971
2972 /*
2973 * Disabling the crtcs gracefully seems nicer. Also the
2974 * g33 docs say we should at least disable all the planes.
2975 */
2976 for_each_intel_crtc(dev, crtc) {
2977 if (crtc->active)
2978 dev_priv->display.crtc_disable(&crtc->base);
2979 }
2980 }
2981
2982 void intel_finish_reset(struct drm_device *dev)
2983 {
2984 struct drm_i915_private *dev_priv = to_i915(dev);
2985
2986 /*
2987 * Flips in the rings will be nuked by the reset,
2988 * so complete all pending flips so that user space
2989 * will get its events and not get stuck.
2990 */
2991 intel_complete_page_flips(dev);
2992
2993 /* no reset support for gen2 */
2994 if (IS_GEN2(dev))
2995 return;
2996
2997 /* reset doesn't touch the display */
2998 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2999 /*
3000 * Flips in the rings have been nuked by the reset,
3001 * so update the base address of all primary
3002 * planes to the the last fb to make sure we're
3003 * showing the correct fb after a reset.
3004 */
3005 intel_update_primary_planes(dev);
3006 return;
3007 }
3008
3009 /*
3010 * The display has been reset as well,
3011 * so need a full re-initialization.
3012 */
3013 intel_runtime_pm_disable_interrupts(dev_priv);
3014 intel_runtime_pm_enable_interrupts(dev_priv);
3015
3016 intel_modeset_init_hw(dev);
3017
3018 spin_lock_irq(&dev_priv->irq_lock);
3019 if (dev_priv->display.hpd_irq_setup)
3020 dev_priv->display.hpd_irq_setup(dev);
3021 spin_unlock_irq(&dev_priv->irq_lock);
3022
3023 intel_modeset_setup_hw_state(dev, true);
3024
3025 intel_hpd_init(dev_priv);
3026
3027 drm_modeset_unlock_all(dev);
3028 }
3029
3030 static int
3031 intel_finish_fb(struct drm_framebuffer *old_fb)
3032 {
3033 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3034 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3035 bool was_interruptible = dev_priv->mm.interruptible;
3036 int ret;
3037
3038 /* Big Hammer, we also need to ensure that any pending
3039 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3040 * current scanout is retired before unpinning the old
3041 * framebuffer.
3042 *
3043 * This should only fail upon a hung GPU, in which case we
3044 * can safely continue.
3045 */
3046 dev_priv->mm.interruptible = false;
3047 ret = i915_gem_object_finish_gpu(obj);
3048 dev_priv->mm.interruptible = was_interruptible;
3049
3050 return ret;
3051 }
3052
3053 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3054 {
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058 bool pending;
3059
3060 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3061 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3062 return false;
3063
3064 spin_lock_irq(&dev->event_lock);
3065 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3066 spin_unlock_irq(&dev->event_lock);
3067
3068 return pending;
3069 }
3070
3071 static void intel_update_pipe_size(struct intel_crtc *crtc)
3072 {
3073 struct drm_device *dev = crtc->base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 const struct drm_display_mode *adjusted_mode;
3076
3077 if (!i915.fastboot)
3078 return;
3079
3080 /*
3081 * Update pipe size and adjust fitter if needed: the reason for this is
3082 * that in compute_mode_changes we check the native mode (not the pfit
3083 * mode) to see if we can flip rather than do a full mode set. In the
3084 * fastboot case, we'll flip, but if we don't update the pipesrc and
3085 * pfit state, we'll end up with a big fb scanned out into the wrong
3086 * sized surface.
3087 *
3088 * To fix this properly, we need to hoist the checks up into
3089 * compute_mode_changes (or above), check the actual pfit state and
3090 * whether the platform allows pfit disable with pipe active, and only
3091 * then update the pipesrc and pfit state, even on the flip path.
3092 */
3093
3094 adjusted_mode = &crtc->config->base.adjusted_mode;
3095
3096 I915_WRITE(PIPESRC(crtc->pipe),
3097 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3098 (adjusted_mode->crtc_vdisplay - 1));
3099 if (!crtc->config->pch_pfit.enabled &&
3100 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3101 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3102 I915_WRITE(PF_CTL(crtc->pipe), 0);
3103 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3104 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3105 }
3106 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3107 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3108 }
3109
3110 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3111 {
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
3114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3115 int pipe = intel_crtc->pipe;
3116 u32 reg, temp;
3117
3118 /* enable normal train */
3119 reg = FDI_TX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 if (IS_IVYBRIDGE(dev)) {
3122 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3123 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3124 } else {
3125 temp &= ~FDI_LINK_TRAIN_NONE;
3126 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3127 }
3128 I915_WRITE(reg, temp);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 if (HAS_PCH_CPT(dev)) {
3133 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3134 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3135 } else {
3136 temp &= ~FDI_LINK_TRAIN_NONE;
3137 temp |= FDI_LINK_TRAIN_NONE;
3138 }
3139 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3140
3141 /* wait one idle pattern time */
3142 POSTING_READ(reg);
3143 udelay(1000);
3144
3145 /* IVB wants error correction enabled */
3146 if (IS_IVYBRIDGE(dev))
3147 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3148 FDI_FE_ERRC_ENABLE);
3149 }
3150
3151 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3152 {
3153 return crtc->base.state->enable && crtc->active &&
3154 crtc->config->has_pch_encoder;
3155 }
3156
3157 static void ivb_modeset_global_resources(struct drm_device *dev)
3158 {
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160 struct intel_crtc *pipe_B_crtc =
3161 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3162 struct intel_crtc *pipe_C_crtc =
3163 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3164 uint32_t temp;
3165
3166 /*
3167 * When everything is off disable fdi C so that we could enable fdi B
3168 * with all lanes. Note that we don't care about enabled pipes without
3169 * an enabled pch encoder.
3170 */
3171 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3172 !pipe_has_enabled_pch(pipe_C_crtc)) {
3173 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3174 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3175
3176 temp = I915_READ(SOUTH_CHICKEN1);
3177 temp &= ~FDI_BC_BIFURCATION_SELECT;
3178 DRM_DEBUG_KMS("disabling fdi C rx\n");
3179 I915_WRITE(SOUTH_CHICKEN1, temp);
3180 }
3181 }
3182
3183 /* The FDI link training functions for ILK/Ibexpeak. */
3184 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3185 {
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 int pipe = intel_crtc->pipe;
3190 u32 reg, temp, tries;
3191
3192 /* FDI needs bits from pipe first */
3193 assert_pipe_enabled(dev_priv, pipe);
3194
3195 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3196 for train result */
3197 reg = FDI_RX_IMR(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~FDI_RX_SYMBOL_LOCK;
3200 temp &= ~FDI_RX_BIT_LOCK;
3201 I915_WRITE(reg, temp);
3202 I915_READ(reg);
3203 udelay(150);
3204
3205 /* enable CPU FDI TX and PCH FDI RX */
3206 reg = FDI_TX_CTL(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3209 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3210 temp &= ~FDI_LINK_TRAIN_NONE;
3211 temp |= FDI_LINK_TRAIN_PATTERN_1;
3212 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3213
3214 reg = FDI_RX_CTL(pipe);
3215 temp = I915_READ(reg);
3216 temp &= ~FDI_LINK_TRAIN_NONE;
3217 temp |= FDI_LINK_TRAIN_PATTERN_1;
3218 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3219
3220 POSTING_READ(reg);
3221 udelay(150);
3222
3223 /* Ironlake workaround, enable clock pointer after FDI enable*/
3224 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3225 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3226 FDI_RX_PHASE_SYNC_POINTER_EN);
3227
3228 reg = FDI_RX_IIR(pipe);
3229 for (tries = 0; tries < 5; tries++) {
3230 temp = I915_READ(reg);
3231 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3232
3233 if ((temp & FDI_RX_BIT_LOCK)) {
3234 DRM_DEBUG_KMS("FDI train 1 done.\n");
3235 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3236 break;
3237 }
3238 }
3239 if (tries == 5)
3240 DRM_ERROR("FDI train 1 fail!\n");
3241
3242 /* Train 2 */
3243 reg = FDI_TX_CTL(pipe);
3244 temp = I915_READ(reg);
3245 temp &= ~FDI_LINK_TRAIN_NONE;
3246 temp |= FDI_LINK_TRAIN_PATTERN_2;
3247 I915_WRITE(reg, temp);
3248
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 temp &= ~FDI_LINK_TRAIN_NONE;
3252 temp |= FDI_LINK_TRAIN_PATTERN_2;
3253 I915_WRITE(reg, temp);
3254
3255 POSTING_READ(reg);
3256 udelay(150);
3257
3258 reg = FDI_RX_IIR(pipe);
3259 for (tries = 0; tries < 5; tries++) {
3260 temp = I915_READ(reg);
3261 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3262
3263 if (temp & FDI_RX_SYMBOL_LOCK) {
3264 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3265 DRM_DEBUG_KMS("FDI train 2 done.\n");
3266 break;
3267 }
3268 }
3269 if (tries == 5)
3270 DRM_ERROR("FDI train 2 fail!\n");
3271
3272 DRM_DEBUG_KMS("FDI train done\n");
3273
3274 }
3275
3276 static const int snb_b_fdi_train_param[] = {
3277 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3278 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3279 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3280 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3281 };
3282
3283 /* The FDI link training functions for SNB/Cougarpoint. */
3284 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3285 {
3286 struct drm_device *dev = crtc->dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3289 int pipe = intel_crtc->pipe;
3290 u32 reg, temp, i, retry;
3291
3292 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3293 for train result */
3294 reg = FDI_RX_IMR(pipe);
3295 temp = I915_READ(reg);
3296 temp &= ~FDI_RX_SYMBOL_LOCK;
3297 temp &= ~FDI_RX_BIT_LOCK;
3298 I915_WRITE(reg, temp);
3299
3300 POSTING_READ(reg);
3301 udelay(150);
3302
3303 /* enable CPU FDI TX and PCH FDI RX */
3304 reg = FDI_TX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3307 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3308 temp &= ~FDI_LINK_TRAIN_NONE;
3309 temp |= FDI_LINK_TRAIN_PATTERN_1;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 /* SNB-B */
3312 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 if (HAS_PCH_CPT(dev)) {
3321 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3322 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3323 } else {
3324 temp &= ~FDI_LINK_TRAIN_NONE;
3325 temp |= FDI_LINK_TRAIN_PATTERN_1;
3326 }
3327 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3328
3329 POSTING_READ(reg);
3330 udelay(150);
3331
3332 for (i = 0; i < 4; i++) {
3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
3335 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3336 temp |= snb_b_fdi_train_param[i];
3337 I915_WRITE(reg, temp);
3338
3339 POSTING_READ(reg);
3340 udelay(500);
3341
3342 for (retry = 0; retry < 5; retry++) {
3343 reg = FDI_RX_IIR(pipe);
3344 temp = I915_READ(reg);
3345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3346 if (temp & FDI_RX_BIT_LOCK) {
3347 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3348 DRM_DEBUG_KMS("FDI train 1 done.\n");
3349 break;
3350 }
3351 udelay(50);
3352 }
3353 if (retry < 5)
3354 break;
3355 }
3356 if (i == 4)
3357 DRM_ERROR("FDI train 1 fail!\n");
3358
3359 /* Train 2 */
3360 reg = FDI_TX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_PATTERN_2;
3364 if (IS_GEN6(dev)) {
3365 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3366 /* SNB-B */
3367 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3368 }
3369 I915_WRITE(reg, temp);
3370
3371 reg = FDI_RX_CTL(pipe);
3372 temp = I915_READ(reg);
3373 if (HAS_PCH_CPT(dev)) {
3374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3376 } else {
3377 temp &= ~FDI_LINK_TRAIN_NONE;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2;
3379 }
3380 I915_WRITE(reg, temp);
3381
3382 POSTING_READ(reg);
3383 udelay(150);
3384
3385 for (i = 0; i < 4; i++) {
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
3388 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3389 temp |= snb_b_fdi_train_param[i];
3390 I915_WRITE(reg, temp);
3391
3392 POSTING_READ(reg);
3393 udelay(500);
3394
3395 for (retry = 0; retry < 5; retry++) {
3396 reg = FDI_RX_IIR(pipe);
3397 temp = I915_READ(reg);
3398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3399 if (temp & FDI_RX_SYMBOL_LOCK) {
3400 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3401 DRM_DEBUG_KMS("FDI train 2 done.\n");
3402 break;
3403 }
3404 udelay(50);
3405 }
3406 if (retry < 5)
3407 break;
3408 }
3409 if (i == 4)
3410 DRM_ERROR("FDI train 2 fail!\n");
3411
3412 DRM_DEBUG_KMS("FDI train done.\n");
3413 }
3414
3415 /* Manual link training for Ivy Bridge A0 parts */
3416 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3417 {
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 int pipe = intel_crtc->pipe;
3422 u32 reg, temp, i, j;
3423
3424 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3425 for train result */
3426 reg = FDI_RX_IMR(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_RX_SYMBOL_LOCK;
3429 temp &= ~FDI_RX_BIT_LOCK;
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(150);
3434
3435 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3436 I915_READ(FDI_RX_IIR(pipe)));
3437
3438 /* Try each vswing and preemphasis setting twice before moving on */
3439 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3440 /* disable first in case we need to retry */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3444 temp &= ~FDI_TX_ENABLE;
3445 I915_WRITE(reg, temp);
3446
3447 reg = FDI_RX_CTL(pipe);
3448 temp = I915_READ(reg);
3449 temp &= ~FDI_LINK_TRAIN_AUTO;
3450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451 temp &= ~FDI_RX_ENABLE;
3452 I915_WRITE(reg, temp);
3453
3454 /* enable CPU FDI TX and PCH FDI RX */
3455 reg = FDI_TX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3460 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3461 temp |= snb_b_fdi_train_param[j/2];
3462 temp |= FDI_COMPOSITE_SYNC;
3463 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3464
3465 I915_WRITE(FDI_RX_MISC(pipe),
3466 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3467
3468 reg = FDI_RX_CTL(pipe);
3469 temp = I915_READ(reg);
3470 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3471 temp |= FDI_COMPOSITE_SYNC;
3472 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3473
3474 POSTING_READ(reg);
3475 udelay(1); /* should be 0.5us */
3476
3477 for (i = 0; i < 4; i++) {
3478 reg = FDI_RX_IIR(pipe);
3479 temp = I915_READ(reg);
3480 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3481
3482 if (temp & FDI_RX_BIT_LOCK ||
3483 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3485 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3486 i);
3487 break;
3488 }
3489 udelay(1); /* should be 0.5us */
3490 }
3491 if (i == 4) {
3492 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3493 continue;
3494 }
3495
3496 /* Train 2 */
3497 reg = FDI_TX_CTL(pipe);
3498 temp = I915_READ(reg);
3499 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3500 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3501 I915_WRITE(reg, temp);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3506 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(2); /* should be 1.5us */
3511
3512 for (i = 0; i < 4; i++) {
3513 reg = FDI_RX_IIR(pipe);
3514 temp = I915_READ(reg);
3515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3516
3517 if (temp & FDI_RX_SYMBOL_LOCK ||
3518 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3521 i);
3522 goto train_done;
3523 }
3524 udelay(2); /* should be 1.5us */
3525 }
3526 if (i == 4)
3527 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3528 }
3529
3530 train_done:
3531 DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3535 {
3536 struct drm_device *dev = intel_crtc->base.dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 int pipe = intel_crtc->pipe;
3539 u32 reg, temp;
3540
3541
3542 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3543 reg = FDI_RX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3548 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3549
3550 POSTING_READ(reg);
3551 udelay(200);
3552
3553 /* Switch from Rawclk to PCDclk */
3554 temp = I915_READ(reg);
3555 I915_WRITE(reg, temp | FDI_PCDCLK);
3556
3557 POSTING_READ(reg);
3558 udelay(200);
3559
3560 /* Enable CPU FDI TX PLL, always on for Ironlake */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3564 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3565
3566 POSTING_READ(reg);
3567 udelay(100);
3568 }
3569 }
3570
3571 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3572 {
3573 struct drm_device *dev = intel_crtc->base.dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 int pipe = intel_crtc->pipe;
3576 u32 reg, temp;
3577
3578 /* Switch from PCDclk to Rawclk */
3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
3581 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3582
3583 /* Disable CPU FDI TX PLL */
3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
3586 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3587
3588 POSTING_READ(reg);
3589 udelay(100);
3590
3591 reg = FDI_RX_CTL(pipe);
3592 temp = I915_READ(reg);
3593 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3594
3595 /* Wait for the clocks to turn off. */
3596 POSTING_READ(reg);
3597 udelay(100);
3598 }
3599
3600 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3601 {
3602 struct drm_device *dev = crtc->dev;
3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3605 int pipe = intel_crtc->pipe;
3606 u32 reg, temp;
3607
3608 /* disable CPU FDI tx and PCH FDI rx */
3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3612 POSTING_READ(reg);
3613
3614 reg = FDI_RX_CTL(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~(0x7 << 16);
3617 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3618 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3619
3620 POSTING_READ(reg);
3621 udelay(100);
3622
3623 /* Ironlake workaround, disable clock pointer after downing FDI */
3624 if (HAS_PCH_IBX(dev))
3625 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3626
3627 /* still set train pattern 1 */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 temp &= ~FDI_LINK_TRAIN_NONE;
3631 temp |= FDI_LINK_TRAIN_PATTERN_1;
3632 I915_WRITE(reg, temp);
3633
3634 reg = FDI_RX_CTL(pipe);
3635 temp = I915_READ(reg);
3636 if (HAS_PCH_CPT(dev)) {
3637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3639 } else {
3640 temp &= ~FDI_LINK_TRAIN_NONE;
3641 temp |= FDI_LINK_TRAIN_PATTERN_1;
3642 }
3643 /* BPC in FDI rx is consistent with that in PIPECONF */
3644 temp &= ~(0x07 << 16);
3645 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3646 I915_WRITE(reg, temp);
3647
3648 POSTING_READ(reg);
3649 udelay(100);
3650 }
3651
3652 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3653 {
3654 struct intel_crtc *crtc;
3655
3656 /* Note that we don't need to be called with mode_config.lock here
3657 * as our list of CRTC objects is static for the lifetime of the
3658 * device and so cannot disappear as we iterate. Similarly, we can
3659 * happily treat the predicates as racy, atomic checks as userspace
3660 * cannot claim and pin a new fb without at least acquring the
3661 * struct_mutex and so serialising with us.
3662 */
3663 for_each_intel_crtc(dev, crtc) {
3664 if (atomic_read(&crtc->unpin_work_count) == 0)
3665 continue;
3666
3667 if (crtc->unpin_work)
3668 intel_wait_for_vblank(dev, crtc->pipe);
3669
3670 return true;
3671 }
3672
3673 return false;
3674 }
3675
3676 static void page_flip_completed(struct intel_crtc *intel_crtc)
3677 {
3678 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3679 struct intel_unpin_work *work = intel_crtc->unpin_work;
3680
3681 /* ensure that the unpin work is consistent wrt ->pending. */
3682 smp_rmb();
3683 intel_crtc->unpin_work = NULL;
3684
3685 if (work->event)
3686 drm_send_vblank_event(intel_crtc->base.dev,
3687 intel_crtc->pipe,
3688 work->event);
3689
3690 drm_crtc_vblank_put(&intel_crtc->base);
3691
3692 wake_up_all(&dev_priv->pending_flip_queue);
3693 queue_work(dev_priv->wq, &work->work);
3694
3695 trace_i915_flip_complete(intel_crtc->plane,
3696 work->pending_flip_obj);
3697 }
3698
3699 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3700 {
3701 struct drm_device *dev = crtc->dev;
3702 struct drm_i915_private *dev_priv = dev->dev_private;
3703
3704 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3705 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3706 !intel_crtc_has_pending_flip(crtc),
3707 60*HZ) == 0)) {
3708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3709
3710 spin_lock_irq(&dev->event_lock);
3711 if (intel_crtc->unpin_work) {
3712 WARN_ONCE(1, "Removing stuck page flip\n");
3713 page_flip_completed(intel_crtc);
3714 }
3715 spin_unlock_irq(&dev->event_lock);
3716 }
3717
3718 if (crtc->primary->fb) {
3719 mutex_lock(&dev->struct_mutex);
3720 intel_finish_fb(crtc->primary->fb);
3721 mutex_unlock(&dev->struct_mutex);
3722 }
3723 }
3724
3725 /* Program iCLKIP clock to the desired frequency */
3726 static void lpt_program_iclkip(struct drm_crtc *crtc)
3727 {
3728 struct drm_device *dev = crtc->dev;
3729 struct drm_i915_private *dev_priv = dev->dev_private;
3730 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3731 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3732 u32 temp;
3733
3734 mutex_lock(&dev_priv->dpio_lock);
3735
3736 /* It is necessary to ungate the pixclk gate prior to programming
3737 * the divisors, and gate it back when it is done.
3738 */
3739 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3740
3741 /* Disable SSCCTL */
3742 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3743 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3744 SBI_SSCCTL_DISABLE,
3745 SBI_ICLK);
3746
3747 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3748 if (clock == 20000) {
3749 auxdiv = 1;
3750 divsel = 0x41;
3751 phaseinc = 0x20;
3752 } else {
3753 /* The iCLK virtual clock root frequency is in MHz,
3754 * but the adjusted_mode->crtc_clock in in KHz. To get the
3755 * divisors, it is necessary to divide one by another, so we
3756 * convert the virtual clock precision to KHz here for higher
3757 * precision.
3758 */
3759 u32 iclk_virtual_root_freq = 172800 * 1000;
3760 u32 iclk_pi_range = 64;
3761 u32 desired_divisor, msb_divisor_value, pi_value;
3762
3763 desired_divisor = (iclk_virtual_root_freq / clock);
3764 msb_divisor_value = desired_divisor / iclk_pi_range;
3765 pi_value = desired_divisor % iclk_pi_range;
3766
3767 auxdiv = 0;
3768 divsel = msb_divisor_value - 2;
3769 phaseinc = pi_value;
3770 }
3771
3772 /* This should not happen with any sane values */
3773 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3774 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3775 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3776 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3777
3778 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3779 clock,
3780 auxdiv,
3781 divsel,
3782 phasedir,
3783 phaseinc);
3784
3785 /* Program SSCDIVINTPHASE6 */
3786 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3787 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3788 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3789 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3790 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3791 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3792 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3793 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3794
3795 /* Program SSCAUXDIV */
3796 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3797 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3798 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3799 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3800
3801 /* Enable modulator and associated divider */
3802 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3803 temp &= ~SBI_SSCCTL_DISABLE;
3804 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3805
3806 /* Wait for initialization time */
3807 udelay(24);
3808
3809 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3810
3811 mutex_unlock(&dev_priv->dpio_lock);
3812 }
3813
3814 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3815 enum pipe pch_transcoder)
3816 {
3817 struct drm_device *dev = crtc->base.dev;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3820
3821 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3822 I915_READ(HTOTAL(cpu_transcoder)));
3823 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3824 I915_READ(HBLANK(cpu_transcoder)));
3825 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3826 I915_READ(HSYNC(cpu_transcoder)));
3827
3828 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3829 I915_READ(VTOTAL(cpu_transcoder)));
3830 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3831 I915_READ(VBLANK(cpu_transcoder)));
3832 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3833 I915_READ(VSYNC(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3835 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3836 }
3837
3838 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3839 {
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841 uint32_t temp;
3842
3843 temp = I915_READ(SOUTH_CHICKEN1);
3844 if (temp & FDI_BC_BIFURCATION_SELECT)
3845 return;
3846
3847 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3848 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3849
3850 temp |= FDI_BC_BIFURCATION_SELECT;
3851 DRM_DEBUG_KMS("enabling fdi C rx\n");
3852 I915_WRITE(SOUTH_CHICKEN1, temp);
3853 POSTING_READ(SOUTH_CHICKEN1);
3854 }
3855
3856 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3857 {
3858 struct drm_device *dev = intel_crtc->base.dev;
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 switch (intel_crtc->pipe) {
3862 case PIPE_A:
3863 break;
3864 case PIPE_B:
3865 if (intel_crtc->config->fdi_lanes > 2)
3866 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3867 else
3868 cpt_enable_fdi_bc_bifurcation(dev);
3869
3870 break;
3871 case PIPE_C:
3872 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874 break;
3875 default:
3876 BUG();
3877 }
3878 }
3879
3880 /*
3881 * Enable PCH resources required for PCH ports:
3882 * - PCH PLLs
3883 * - FDI training & RX/TX
3884 * - update transcoder timings
3885 * - DP transcoding bits
3886 * - transcoder
3887 */
3888 static void ironlake_pch_enable(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 int pipe = intel_crtc->pipe;
3894 u32 reg, temp;
3895
3896 assert_pch_transcoder_disabled(dev_priv, pipe);
3897
3898 if (IS_IVYBRIDGE(dev))
3899 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3900
3901 /* Write the TU size bits before fdi link training, so that error
3902 * detection works. */
3903 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3904 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3905
3906 /* For PCH output, training FDI link */
3907 dev_priv->display.fdi_link_train(crtc);
3908
3909 /* We need to program the right clock selection before writing the pixel
3910 * mutliplier into the DPLL. */
3911 if (HAS_PCH_CPT(dev)) {
3912 u32 sel;
3913
3914 temp = I915_READ(PCH_DPLL_SEL);
3915 temp |= TRANS_DPLL_ENABLE(pipe);
3916 sel = TRANS_DPLLB_SEL(pipe);
3917 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3918 temp |= sel;
3919 else
3920 temp &= ~sel;
3921 I915_WRITE(PCH_DPLL_SEL, temp);
3922 }
3923
3924 /* XXX: pch pll's can be enabled any time before we enable the PCH
3925 * transcoder, and we actually should do this to not upset any PCH
3926 * transcoder that already use the clock when we share it.
3927 *
3928 * Note that enable_shared_dpll tries to do the right thing, but
3929 * get_shared_dpll unconditionally resets the pll - we need that to have
3930 * the right LVDS enable sequence. */
3931 intel_enable_shared_dpll(intel_crtc);
3932
3933 /* set transcoder timing, panel must allow it */
3934 assert_panel_unlocked(dev_priv, pipe);
3935 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3936
3937 intel_fdi_normal_train(crtc);
3938
3939 /* For PCH DP, enable TRANS_DP_CTL */
3940 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3941 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3942 reg = TRANS_DP_CTL(pipe);
3943 temp = I915_READ(reg);
3944 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3945 TRANS_DP_SYNC_MASK |
3946 TRANS_DP_BPC_MASK);
3947 temp |= (TRANS_DP_OUTPUT_ENABLE |
3948 TRANS_DP_ENH_FRAMING);
3949 temp |= bpc << 9; /* same format but at 11:9 */
3950
3951 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3952 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3953 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3954 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3955
3956 switch (intel_trans_dp_port_sel(crtc)) {
3957 case PCH_DP_B:
3958 temp |= TRANS_DP_PORT_SEL_B;
3959 break;
3960 case PCH_DP_C:
3961 temp |= TRANS_DP_PORT_SEL_C;
3962 break;
3963 case PCH_DP_D:
3964 temp |= TRANS_DP_PORT_SEL_D;
3965 break;
3966 default:
3967 BUG();
3968 }
3969
3970 I915_WRITE(reg, temp);
3971 }
3972
3973 ironlake_enable_pch_transcoder(dev_priv, pipe);
3974 }
3975
3976 static void lpt_pch_enable(struct drm_crtc *crtc)
3977 {
3978 struct drm_device *dev = crtc->dev;
3979 struct drm_i915_private *dev_priv = dev->dev_private;
3980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3981 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3982
3983 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3984
3985 lpt_program_iclkip(crtc);
3986
3987 /* Set transcoder timing. */
3988 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3989
3990 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3991 }
3992
3993 void intel_put_shared_dpll(struct intel_crtc *crtc)
3994 {
3995 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3996
3997 if (pll == NULL)
3998 return;
3999
4000 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4001 WARN(1, "bad %s crtc mask\n", pll->name);
4002 return;
4003 }
4004
4005 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4006 if (pll->config.crtc_mask == 0) {
4007 WARN_ON(pll->on);
4008 WARN_ON(pll->active);
4009 }
4010
4011 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4012 }
4013
4014 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4015 struct intel_crtc_state *crtc_state)
4016 {
4017 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4018 struct intel_shared_dpll *pll;
4019 enum intel_dpll_id i;
4020
4021 if (HAS_PCH_IBX(dev_priv->dev)) {
4022 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4023 i = (enum intel_dpll_id) crtc->pipe;
4024 pll = &dev_priv->shared_dplls[i];
4025
4026 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4027 crtc->base.base.id, pll->name);
4028
4029 WARN_ON(pll->new_config->crtc_mask);
4030
4031 goto found;
4032 }
4033
4034 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4035 pll = &dev_priv->shared_dplls[i];
4036
4037 /* Only want to check enabled timings first */
4038 if (pll->new_config->crtc_mask == 0)
4039 continue;
4040
4041 if (memcmp(&crtc_state->dpll_hw_state,
4042 &pll->new_config->hw_state,
4043 sizeof(pll->new_config->hw_state)) == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4045 crtc->base.base.id, pll->name,
4046 pll->new_config->crtc_mask,
4047 pll->active);
4048 goto found;
4049 }
4050 }
4051
4052 /* Ok no matching timings, maybe there's a free one? */
4053 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4054 pll = &dev_priv->shared_dplls[i];
4055 if (pll->new_config->crtc_mask == 0) {
4056 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4057 crtc->base.base.id, pll->name);
4058 goto found;
4059 }
4060 }
4061
4062 return NULL;
4063
4064 found:
4065 if (pll->new_config->crtc_mask == 0)
4066 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4067
4068 crtc_state->shared_dpll = i;
4069 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4070 pipe_name(crtc->pipe));
4071
4072 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4073
4074 return pll;
4075 }
4076
4077 /**
4078 * intel_shared_dpll_start_config - start a new PLL staged config
4079 * @dev_priv: DRM device
4080 * @clear_pipes: mask of pipes that will have their PLLs freed
4081 *
4082 * Starts a new PLL staged config, copying the current config but
4083 * releasing the references of pipes specified in clear_pipes.
4084 */
4085 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4086 unsigned clear_pipes)
4087 {
4088 struct intel_shared_dpll *pll;
4089 enum intel_dpll_id i;
4090
4091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4092 pll = &dev_priv->shared_dplls[i];
4093
4094 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4095 GFP_KERNEL);
4096 if (!pll->new_config)
4097 goto cleanup;
4098
4099 pll->new_config->crtc_mask &= ~clear_pipes;
4100 }
4101
4102 return 0;
4103
4104 cleanup:
4105 while (--i >= 0) {
4106 pll = &dev_priv->shared_dplls[i];
4107 kfree(pll->new_config);
4108 pll->new_config = NULL;
4109 }
4110
4111 return -ENOMEM;
4112 }
4113
4114 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4115 {
4116 struct intel_shared_dpll *pll;
4117 enum intel_dpll_id i;
4118
4119 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4120 pll = &dev_priv->shared_dplls[i];
4121
4122 WARN_ON(pll->new_config == &pll->config);
4123
4124 pll->config = *pll->new_config;
4125 kfree(pll->new_config);
4126 pll->new_config = NULL;
4127 }
4128 }
4129
4130 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4131 {
4132 struct intel_shared_dpll *pll;
4133 enum intel_dpll_id i;
4134
4135 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4136 pll = &dev_priv->shared_dplls[i];
4137
4138 WARN_ON(pll->new_config == &pll->config);
4139
4140 kfree(pll->new_config);
4141 pll->new_config = NULL;
4142 }
4143 }
4144
4145 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4146 {
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int dslreg = PIPEDSL(pipe);
4149 u32 temp;
4150
4151 temp = I915_READ(dslreg);
4152 udelay(500);
4153 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4154 if (wait_for(I915_READ(dslreg) != temp, 5))
4155 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4156 }
4157 }
4158
4159 static void skylake_pfit_enable(struct intel_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->base.dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 int pipe = crtc->pipe;
4164
4165 if (crtc->config->pch_pfit.enabled) {
4166 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4167 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4168 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4169 }
4170 }
4171
4172 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4173 {
4174 struct drm_device *dev = crtc->base.dev;
4175 struct drm_i915_private *dev_priv = dev->dev_private;
4176 int pipe = crtc->pipe;
4177
4178 if (crtc->config->pch_pfit.enabled) {
4179 /* Force use of hard-coded filter coefficients
4180 * as some pre-programmed values are broken,
4181 * e.g. x201.
4182 */
4183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4185 PF_PIPE_SEL_IVB(pipe));
4186 else
4187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4188 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4190 }
4191 }
4192
4193 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4194 {
4195 struct drm_device *dev = crtc->dev;
4196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4197 struct drm_plane *plane;
4198 struct intel_plane *intel_plane;
4199
4200 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4201 intel_plane = to_intel_plane(plane);
4202 if (intel_plane->pipe == pipe)
4203 intel_plane_restore(&intel_plane->base);
4204 }
4205 }
4206
4207 /*
4208 * Disable a plane internally without actually modifying the plane's state.
4209 * This will allow us to easily restore the plane later by just reprogramming
4210 * its state.
4211 */
4212 static void disable_plane_internal(struct drm_plane *plane)
4213 {
4214 struct intel_plane *intel_plane = to_intel_plane(plane);
4215 struct drm_plane_state *state =
4216 plane->funcs->atomic_duplicate_state(plane);
4217 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4218
4219 intel_state->visible = false;
4220 intel_plane->commit_plane(plane, intel_state);
4221
4222 intel_plane_destroy_state(plane, state);
4223 }
4224
4225 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4226 {
4227 struct drm_device *dev = crtc->dev;
4228 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4229 struct drm_plane *plane;
4230 struct intel_plane *intel_plane;
4231
4232 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4233 intel_plane = to_intel_plane(plane);
4234 if (plane->fb && intel_plane->pipe == pipe)
4235 disable_plane_internal(plane);
4236 }
4237 }
4238
4239 void hsw_enable_ips(struct intel_crtc *crtc)
4240 {
4241 struct drm_device *dev = crtc->base.dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244 if (!crtc->config->ips_enabled)
4245 return;
4246
4247 /* We can only enable IPS after we enable a plane and wait for a vblank */
4248 intel_wait_for_vblank(dev, crtc->pipe);
4249
4250 assert_plane_enabled(dev_priv, crtc->plane);
4251 if (IS_BROADWELL(dev)) {
4252 mutex_lock(&dev_priv->rps.hw_lock);
4253 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4254 mutex_unlock(&dev_priv->rps.hw_lock);
4255 /* Quoting Art Runyan: "its not safe to expect any particular
4256 * value in IPS_CTL bit 31 after enabling IPS through the
4257 * mailbox." Moreover, the mailbox may return a bogus state,
4258 * so we need to just enable it and continue on.
4259 */
4260 } else {
4261 I915_WRITE(IPS_CTL, IPS_ENABLE);
4262 /* The bit only becomes 1 in the next vblank, so this wait here
4263 * is essentially intel_wait_for_vblank. If we don't have this
4264 * and don't wait for vblanks until the end of crtc_enable, then
4265 * the HW state readout code will complain that the expected
4266 * IPS_CTL value is not the one we read. */
4267 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4268 DRM_ERROR("Timed out waiting for IPS enable\n");
4269 }
4270 }
4271
4272 void hsw_disable_ips(struct intel_crtc *crtc)
4273 {
4274 struct drm_device *dev = crtc->base.dev;
4275 struct drm_i915_private *dev_priv = dev->dev_private;
4276
4277 if (!crtc->config->ips_enabled)
4278 return;
4279
4280 assert_plane_enabled(dev_priv, crtc->plane);
4281 if (IS_BROADWELL(dev)) {
4282 mutex_lock(&dev_priv->rps.hw_lock);
4283 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4284 mutex_unlock(&dev_priv->rps.hw_lock);
4285 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4286 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4287 DRM_ERROR("Timed out waiting for IPS disable\n");
4288 } else {
4289 I915_WRITE(IPS_CTL, 0);
4290 POSTING_READ(IPS_CTL);
4291 }
4292
4293 /* We need to wait for a vblank before we can disable the plane. */
4294 intel_wait_for_vblank(dev, crtc->pipe);
4295 }
4296
4297 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4298 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4299 {
4300 struct drm_device *dev = crtc->dev;
4301 struct drm_i915_private *dev_priv = dev->dev_private;
4302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4303 enum pipe pipe = intel_crtc->pipe;
4304 int palreg = PALETTE(pipe);
4305 int i;
4306 bool reenable_ips = false;
4307
4308 /* The clocks have to be on to load the palette. */
4309 if (!crtc->state->enable || !intel_crtc->active)
4310 return;
4311
4312 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4313 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4314 assert_dsi_pll_enabled(dev_priv);
4315 else
4316 assert_pll_enabled(dev_priv, pipe);
4317 }
4318
4319 /* use legacy palette for Ironlake */
4320 if (!HAS_GMCH_DISPLAY(dev))
4321 palreg = LGC_PALETTE(pipe);
4322
4323 /* Workaround : Do not read or write the pipe palette/gamma data while
4324 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4325 */
4326 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4327 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4328 GAMMA_MODE_MODE_SPLIT)) {
4329 hsw_disable_ips(intel_crtc);
4330 reenable_ips = true;
4331 }
4332
4333 for (i = 0; i < 256; i++) {
4334 I915_WRITE(palreg + 4 * i,
4335 (intel_crtc->lut_r[i] << 16) |
4336 (intel_crtc->lut_g[i] << 8) |
4337 intel_crtc->lut_b[i]);
4338 }
4339
4340 if (reenable_ips)
4341 hsw_enable_ips(intel_crtc);
4342 }
4343
4344 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4345 {
4346 if (!enable && intel_crtc->overlay) {
4347 struct drm_device *dev = intel_crtc->base.dev;
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350 mutex_lock(&dev->struct_mutex);
4351 dev_priv->mm.interruptible = false;
4352 (void) intel_overlay_switch_off(intel_crtc->overlay);
4353 dev_priv->mm.interruptible = true;
4354 mutex_unlock(&dev->struct_mutex);
4355 }
4356
4357 /* Let userspace switch the overlay on again. In most cases userspace
4358 * has to recompute where to put it anyway.
4359 */
4360 }
4361
4362 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4363 {
4364 struct drm_device *dev = crtc->dev;
4365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366 int pipe = intel_crtc->pipe;
4367
4368 intel_enable_primary_hw_plane(crtc->primary, crtc);
4369 intel_enable_sprite_planes(crtc);
4370 intel_crtc_update_cursor(crtc, true);
4371 intel_crtc_dpms_overlay(intel_crtc, true);
4372
4373 hsw_enable_ips(intel_crtc);
4374
4375 mutex_lock(&dev->struct_mutex);
4376 intel_fbc_update(dev);
4377 mutex_unlock(&dev->struct_mutex);
4378
4379 /*
4380 * FIXME: Once we grow proper nuclear flip support out of this we need
4381 * to compute the mask of flip planes precisely. For the time being
4382 * consider this a flip from a NULL plane.
4383 */
4384 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4385 }
4386
4387 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4388 {
4389 struct drm_device *dev = crtc->dev;
4390 struct drm_i915_private *dev_priv = dev->dev_private;
4391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4392 int pipe = intel_crtc->pipe;
4393
4394 intel_crtc_wait_for_pending_flips(crtc);
4395
4396 if (dev_priv->fbc.crtc == intel_crtc)
4397 intel_fbc_disable(dev);
4398
4399 hsw_disable_ips(intel_crtc);
4400
4401 intel_crtc_dpms_overlay(intel_crtc, false);
4402 intel_crtc_update_cursor(crtc, false);
4403 intel_disable_sprite_planes(crtc);
4404 intel_disable_primary_hw_plane(crtc->primary, crtc);
4405
4406 /*
4407 * FIXME: Once we grow proper nuclear flip support out of this we need
4408 * to compute the mask of flip planes precisely. For the time being
4409 * consider this a flip to a NULL plane.
4410 */
4411 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4412 }
4413
4414 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4415 {
4416 struct drm_device *dev = crtc->dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4419 struct intel_encoder *encoder;
4420 int pipe = intel_crtc->pipe;
4421
4422 WARN_ON(!crtc->state->enable);
4423
4424 if (intel_crtc->active)
4425 return;
4426
4427 if (intel_crtc->config->has_pch_encoder)
4428 intel_prepare_shared_dpll(intel_crtc);
4429
4430 if (intel_crtc->config->has_dp_encoder)
4431 intel_dp_set_m_n(intel_crtc, M1_N1);
4432
4433 intel_set_pipe_timings(intel_crtc);
4434
4435 if (intel_crtc->config->has_pch_encoder) {
4436 intel_cpu_transcoder_set_m_n(intel_crtc,
4437 &intel_crtc->config->fdi_m_n, NULL);
4438 }
4439
4440 ironlake_set_pipeconf(crtc);
4441
4442 intel_crtc->active = true;
4443
4444 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4445 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4446
4447 for_each_encoder_on_crtc(dev, crtc, encoder)
4448 if (encoder->pre_enable)
4449 encoder->pre_enable(encoder);
4450
4451 if (intel_crtc->config->has_pch_encoder) {
4452 /* Note: FDI PLL enabling _must_ be done before we enable the
4453 * cpu pipes, hence this is separate from all the other fdi/pch
4454 * enabling. */
4455 ironlake_fdi_pll_enable(intel_crtc);
4456 } else {
4457 assert_fdi_tx_disabled(dev_priv, pipe);
4458 assert_fdi_rx_disabled(dev_priv, pipe);
4459 }
4460
4461 ironlake_pfit_enable(intel_crtc);
4462
4463 /*
4464 * On ILK+ LUT must be loaded before the pipe is running but with
4465 * clocks enabled
4466 */
4467 intel_crtc_load_lut(crtc);
4468
4469 intel_update_watermarks(crtc);
4470 intel_enable_pipe(intel_crtc);
4471
4472 if (intel_crtc->config->has_pch_encoder)
4473 ironlake_pch_enable(crtc);
4474
4475 assert_vblank_disabled(crtc);
4476 drm_crtc_vblank_on(crtc);
4477
4478 for_each_encoder_on_crtc(dev, crtc, encoder)
4479 encoder->enable(encoder);
4480
4481 if (HAS_PCH_CPT(dev))
4482 cpt_verify_modeset(dev, intel_crtc->pipe);
4483
4484 intel_crtc_enable_planes(crtc);
4485 }
4486
4487 /* IPS only exists on ULT machines and is tied to pipe A. */
4488 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4489 {
4490 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4491 }
4492
4493 /*
4494 * This implements the workaround described in the "notes" section of the mode
4495 * set sequence documentation. When going from no pipes or single pipe to
4496 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4497 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4498 */
4499 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4500 {
4501 struct drm_device *dev = crtc->base.dev;
4502 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4503
4504 /* We want to get the other_active_crtc only if there's only 1 other
4505 * active crtc. */
4506 for_each_intel_crtc(dev, crtc_it) {
4507 if (!crtc_it->active || crtc_it == crtc)
4508 continue;
4509
4510 if (other_active_crtc)
4511 return;
4512
4513 other_active_crtc = crtc_it;
4514 }
4515 if (!other_active_crtc)
4516 return;
4517
4518 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4519 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4520 }
4521
4522 static void haswell_crtc_enable(struct drm_crtc *crtc)
4523 {
4524 struct drm_device *dev = crtc->dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4527 struct intel_encoder *encoder;
4528 int pipe = intel_crtc->pipe;
4529
4530 WARN_ON(!crtc->state->enable);
4531
4532 if (intel_crtc->active)
4533 return;
4534
4535 if (intel_crtc_to_shared_dpll(intel_crtc))
4536 intel_enable_shared_dpll(intel_crtc);
4537
4538 if (intel_crtc->config->has_dp_encoder)
4539 intel_dp_set_m_n(intel_crtc, M1_N1);
4540
4541 intel_set_pipe_timings(intel_crtc);
4542
4543 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4544 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4545 intel_crtc->config->pixel_multiplier - 1);
4546 }
4547
4548 if (intel_crtc->config->has_pch_encoder) {
4549 intel_cpu_transcoder_set_m_n(intel_crtc,
4550 &intel_crtc->config->fdi_m_n, NULL);
4551 }
4552
4553 haswell_set_pipeconf(crtc);
4554
4555 intel_set_pipe_csc(crtc);
4556
4557 intel_crtc->active = true;
4558
4559 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->pre_enable)
4562 encoder->pre_enable(encoder);
4563
4564 if (intel_crtc->config->has_pch_encoder) {
4565 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4566 true);
4567 dev_priv->display.fdi_link_train(crtc);
4568 }
4569
4570 intel_ddi_enable_pipe_clock(intel_crtc);
4571
4572 if (IS_SKYLAKE(dev))
4573 skylake_pfit_enable(intel_crtc);
4574 else
4575 ironlake_pfit_enable(intel_crtc);
4576
4577 /*
4578 * On ILK+ LUT must be loaded before the pipe is running but with
4579 * clocks enabled
4580 */
4581 intel_crtc_load_lut(crtc);
4582
4583 intel_ddi_set_pipe_settings(crtc);
4584 intel_ddi_enable_transcoder_func(crtc);
4585
4586 intel_update_watermarks(crtc);
4587 intel_enable_pipe(intel_crtc);
4588
4589 if (intel_crtc->config->has_pch_encoder)
4590 lpt_pch_enable(crtc);
4591
4592 if (intel_crtc->config->dp_encoder_is_mst)
4593 intel_ddi_set_vc_payload_alloc(crtc, true);
4594
4595 assert_vblank_disabled(crtc);
4596 drm_crtc_vblank_on(crtc);
4597
4598 for_each_encoder_on_crtc(dev, crtc, encoder) {
4599 encoder->enable(encoder);
4600 intel_opregion_notify_encoder(encoder, true);
4601 }
4602
4603 /* If we change the relative order between pipe/planes enabling, we need
4604 * to change the workaround. */
4605 haswell_mode_set_planes_workaround(intel_crtc);
4606 intel_crtc_enable_planes(crtc);
4607 }
4608
4609 static void skylake_pfit_disable(struct intel_crtc *crtc)
4610 {
4611 struct drm_device *dev = crtc->base.dev;
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613 int pipe = crtc->pipe;
4614
4615 /* To avoid upsetting the power well on haswell only disable the pfit if
4616 * it's in use. The hw state code will make sure we get this right. */
4617 if (crtc->config->pch_pfit.enabled) {
4618 I915_WRITE(PS_CTL(pipe), 0);
4619 I915_WRITE(PS_WIN_POS(pipe), 0);
4620 I915_WRITE(PS_WIN_SZ(pipe), 0);
4621 }
4622 }
4623
4624 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4625 {
4626 struct drm_device *dev = crtc->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 int pipe = crtc->pipe;
4629
4630 /* To avoid upsetting the power well on haswell only disable the pfit if
4631 * it's in use. The hw state code will make sure we get this right. */
4632 if (crtc->config->pch_pfit.enabled) {
4633 I915_WRITE(PF_CTL(pipe), 0);
4634 I915_WRITE(PF_WIN_POS(pipe), 0);
4635 I915_WRITE(PF_WIN_SZ(pipe), 0);
4636 }
4637 }
4638
4639 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4640 {
4641 struct drm_device *dev = crtc->dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4644 struct intel_encoder *encoder;
4645 int pipe = intel_crtc->pipe;
4646 u32 reg, temp;
4647
4648 if (!intel_crtc->active)
4649 return;
4650
4651 intel_crtc_disable_planes(crtc);
4652
4653 for_each_encoder_on_crtc(dev, crtc, encoder)
4654 encoder->disable(encoder);
4655
4656 drm_crtc_vblank_off(crtc);
4657 assert_vblank_disabled(crtc);
4658
4659 if (intel_crtc->config->has_pch_encoder)
4660 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4661
4662 intel_disable_pipe(intel_crtc);
4663
4664 ironlake_pfit_disable(intel_crtc);
4665
4666 for_each_encoder_on_crtc(dev, crtc, encoder)
4667 if (encoder->post_disable)
4668 encoder->post_disable(encoder);
4669
4670 if (intel_crtc->config->has_pch_encoder) {
4671 ironlake_fdi_disable(crtc);
4672
4673 ironlake_disable_pch_transcoder(dev_priv, pipe);
4674
4675 if (HAS_PCH_CPT(dev)) {
4676 /* disable TRANS_DP_CTL */
4677 reg = TRANS_DP_CTL(pipe);
4678 temp = I915_READ(reg);
4679 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4680 TRANS_DP_PORT_SEL_MASK);
4681 temp |= TRANS_DP_PORT_SEL_NONE;
4682 I915_WRITE(reg, temp);
4683
4684 /* disable DPLL_SEL */
4685 temp = I915_READ(PCH_DPLL_SEL);
4686 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4687 I915_WRITE(PCH_DPLL_SEL, temp);
4688 }
4689
4690 /* disable PCH DPLL */
4691 intel_disable_shared_dpll(intel_crtc);
4692
4693 ironlake_fdi_pll_disable(intel_crtc);
4694 }
4695
4696 intel_crtc->active = false;
4697 intel_update_watermarks(crtc);
4698
4699 mutex_lock(&dev->struct_mutex);
4700 intel_fbc_update(dev);
4701 mutex_unlock(&dev->struct_mutex);
4702 }
4703
4704 static void haswell_crtc_disable(struct drm_crtc *crtc)
4705 {
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 struct intel_encoder *encoder;
4710 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4711
4712 if (!intel_crtc->active)
4713 return;
4714
4715 intel_crtc_disable_planes(crtc);
4716
4717 for_each_encoder_on_crtc(dev, crtc, encoder) {
4718 intel_opregion_notify_encoder(encoder, false);
4719 encoder->disable(encoder);
4720 }
4721
4722 drm_crtc_vblank_off(crtc);
4723 assert_vblank_disabled(crtc);
4724
4725 if (intel_crtc->config->has_pch_encoder)
4726 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4727 false);
4728 intel_disable_pipe(intel_crtc);
4729
4730 if (intel_crtc->config->dp_encoder_is_mst)
4731 intel_ddi_set_vc_payload_alloc(crtc, false);
4732
4733 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4734
4735 if (IS_SKYLAKE(dev))
4736 skylake_pfit_disable(intel_crtc);
4737 else
4738 ironlake_pfit_disable(intel_crtc);
4739
4740 intel_ddi_disable_pipe_clock(intel_crtc);
4741
4742 if (intel_crtc->config->has_pch_encoder) {
4743 lpt_disable_pch_transcoder(dev_priv);
4744 intel_ddi_fdi_disable(crtc);
4745 }
4746
4747 for_each_encoder_on_crtc(dev, crtc, encoder)
4748 if (encoder->post_disable)
4749 encoder->post_disable(encoder);
4750
4751 intel_crtc->active = false;
4752 intel_update_watermarks(crtc);
4753
4754 mutex_lock(&dev->struct_mutex);
4755 intel_fbc_update(dev);
4756 mutex_unlock(&dev->struct_mutex);
4757
4758 if (intel_crtc_to_shared_dpll(intel_crtc))
4759 intel_disable_shared_dpll(intel_crtc);
4760 }
4761
4762 static void ironlake_crtc_off(struct drm_crtc *crtc)
4763 {
4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4765 intel_put_shared_dpll(intel_crtc);
4766 }
4767
4768
4769 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4770 {
4771 struct drm_device *dev = crtc->base.dev;
4772 struct drm_i915_private *dev_priv = dev->dev_private;
4773 struct intel_crtc_state *pipe_config = crtc->config;
4774
4775 if (!pipe_config->gmch_pfit.control)
4776 return;
4777
4778 /*
4779 * The panel fitter should only be adjusted whilst the pipe is disabled,
4780 * according to register description and PRM.
4781 */
4782 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4783 assert_pipe_disabled(dev_priv, crtc->pipe);
4784
4785 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4786 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4787
4788 /* Border color in case we don't scale up to the full screen. Black by
4789 * default, change to something else for debugging. */
4790 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4791 }
4792
4793 static enum intel_display_power_domain port_to_power_domain(enum port port)
4794 {
4795 switch (port) {
4796 case PORT_A:
4797 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4798 case PORT_B:
4799 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4800 case PORT_C:
4801 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4802 case PORT_D:
4803 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4804 default:
4805 WARN_ON_ONCE(1);
4806 return POWER_DOMAIN_PORT_OTHER;
4807 }
4808 }
4809
4810 #define for_each_power_domain(domain, mask) \
4811 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4812 if ((1 << (domain)) & (mask))
4813
4814 enum intel_display_power_domain
4815 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4816 {
4817 struct drm_device *dev = intel_encoder->base.dev;
4818 struct intel_digital_port *intel_dig_port;
4819
4820 switch (intel_encoder->type) {
4821 case INTEL_OUTPUT_UNKNOWN:
4822 /* Only DDI platforms should ever use this output type */
4823 WARN_ON_ONCE(!HAS_DDI(dev));
4824 case INTEL_OUTPUT_DISPLAYPORT:
4825 case INTEL_OUTPUT_HDMI:
4826 case INTEL_OUTPUT_EDP:
4827 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4828 return port_to_power_domain(intel_dig_port->port);
4829 case INTEL_OUTPUT_DP_MST:
4830 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4831 return port_to_power_domain(intel_dig_port->port);
4832 case INTEL_OUTPUT_ANALOG:
4833 return POWER_DOMAIN_PORT_CRT;
4834 case INTEL_OUTPUT_DSI:
4835 return POWER_DOMAIN_PORT_DSI;
4836 default:
4837 return POWER_DOMAIN_PORT_OTHER;
4838 }
4839 }
4840
4841 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4842 {
4843 struct drm_device *dev = crtc->dev;
4844 struct intel_encoder *intel_encoder;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4846 enum pipe pipe = intel_crtc->pipe;
4847 unsigned long mask;
4848 enum transcoder transcoder;
4849
4850 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4851
4852 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4853 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4854 if (intel_crtc->config->pch_pfit.enabled ||
4855 intel_crtc->config->pch_pfit.force_thru)
4856 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4857
4858 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4859 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4860
4861 return mask;
4862 }
4863
4864 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4865 {
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4867 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4868 struct intel_crtc *crtc;
4869
4870 /*
4871 * First get all needed power domains, then put all unneeded, to avoid
4872 * any unnecessary toggling of the power wells.
4873 */
4874 for_each_intel_crtc(dev, crtc) {
4875 enum intel_display_power_domain domain;
4876
4877 if (!crtc->base.state->enable)
4878 continue;
4879
4880 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4881
4882 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4883 intel_display_power_get(dev_priv, domain);
4884 }
4885
4886 if (dev_priv->display.modeset_global_resources)
4887 dev_priv->display.modeset_global_resources(dev);
4888
4889 for_each_intel_crtc(dev, crtc) {
4890 enum intel_display_power_domain domain;
4891
4892 for_each_power_domain(domain, crtc->enabled_power_domains)
4893 intel_display_power_put(dev_priv, domain);
4894
4895 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4896 }
4897
4898 intel_display_set_init_power(dev_priv, false);
4899 }
4900
4901 /* returns HPLL frequency in kHz */
4902 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4903 {
4904 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4905
4906 /* Obtain SKU information */
4907 mutex_lock(&dev_priv->dpio_lock);
4908 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4909 CCK_FUSE_HPLL_FREQ_MASK;
4910 mutex_unlock(&dev_priv->dpio_lock);
4911
4912 return vco_freq[hpll_freq] * 1000;
4913 }
4914
4915 static void vlv_update_cdclk(struct drm_device *dev)
4916 {
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918
4919 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4920 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4921 dev_priv->vlv_cdclk_freq);
4922
4923 /*
4924 * Program the gmbus_freq based on the cdclk frequency.
4925 * BSpec erroneously claims we should aim for 4MHz, but
4926 * in fact 1MHz is the correct frequency.
4927 */
4928 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4929 }
4930
4931 /* Adjust CDclk dividers to allow high res or save power if possible */
4932 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4933 {
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935 u32 val, cmd;
4936
4937 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4938
4939 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4940 cmd = 2;
4941 else if (cdclk == 266667)
4942 cmd = 1;
4943 else
4944 cmd = 0;
4945
4946 mutex_lock(&dev_priv->rps.hw_lock);
4947 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4948 val &= ~DSPFREQGUAR_MASK;
4949 val |= (cmd << DSPFREQGUAR_SHIFT);
4950 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4951 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4952 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4953 50)) {
4954 DRM_ERROR("timed out waiting for CDclk change\n");
4955 }
4956 mutex_unlock(&dev_priv->rps.hw_lock);
4957
4958 if (cdclk == 400000) {
4959 u32 divider;
4960
4961 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4962
4963 mutex_lock(&dev_priv->dpio_lock);
4964 /* adjust cdclk divider */
4965 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4966 val &= ~DISPLAY_FREQUENCY_VALUES;
4967 val |= divider;
4968 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4969
4970 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4971 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4972 50))
4973 DRM_ERROR("timed out waiting for CDclk change\n");
4974 mutex_unlock(&dev_priv->dpio_lock);
4975 }
4976
4977 mutex_lock(&dev_priv->dpio_lock);
4978 /* adjust self-refresh exit latency value */
4979 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4980 val &= ~0x7f;
4981
4982 /*
4983 * For high bandwidth configs, we set a higher latency in the bunit
4984 * so that the core display fetch happens in time to avoid underruns.
4985 */
4986 if (cdclk == 400000)
4987 val |= 4500 / 250; /* 4.5 usec */
4988 else
4989 val |= 3000 / 250; /* 3.0 usec */
4990 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4991 mutex_unlock(&dev_priv->dpio_lock);
4992
4993 vlv_update_cdclk(dev);
4994 }
4995
4996 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4997 {
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 u32 val, cmd;
5000
5001 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5002
5003 switch (cdclk) {
5004 case 400000:
5005 cmd = 3;
5006 break;
5007 case 333333:
5008 case 320000:
5009 cmd = 2;
5010 break;
5011 case 266667:
5012 cmd = 1;
5013 break;
5014 case 200000:
5015 cmd = 0;
5016 break;
5017 default:
5018 MISSING_CASE(cdclk);
5019 return;
5020 }
5021
5022 mutex_lock(&dev_priv->rps.hw_lock);
5023 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5024 val &= ~DSPFREQGUAR_MASK_CHV;
5025 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5026 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5027 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5028 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5029 50)) {
5030 DRM_ERROR("timed out waiting for CDclk change\n");
5031 }
5032 mutex_unlock(&dev_priv->rps.hw_lock);
5033
5034 vlv_update_cdclk(dev);
5035 }
5036
5037 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5038 int max_pixclk)
5039 {
5040 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5041 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5042
5043 /* FIXME: Punit isn't quite ready yet */
5044 if (IS_CHERRYVIEW(dev_priv->dev))
5045 return 400000;
5046
5047 /*
5048 * Really only a few cases to deal with, as only 4 CDclks are supported:
5049 * 200MHz
5050 * 267MHz
5051 * 320/333MHz (depends on HPLL freq)
5052 * 400MHz (VLV only)
5053 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5054 * of the lower bin and adjust if needed.
5055 *
5056 * We seem to get an unstable or solid color picture at 200MHz.
5057 * Not sure what's wrong. For now use 200MHz only when all pipes
5058 * are off.
5059 */
5060 if (!IS_CHERRYVIEW(dev_priv) &&
5061 max_pixclk > freq_320*limit/100)
5062 return 400000;
5063 else if (max_pixclk > 266667*limit/100)
5064 return freq_320;
5065 else if (max_pixclk > 0)
5066 return 266667;
5067 else
5068 return 200000;
5069 }
5070
5071 /* compute the max pixel clock for new configuration */
5072 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5073 {
5074 struct drm_device *dev = dev_priv->dev;
5075 struct intel_crtc *intel_crtc;
5076 int max_pixclk = 0;
5077
5078 for_each_intel_crtc(dev, intel_crtc) {
5079 if (intel_crtc->new_enabled)
5080 max_pixclk = max(max_pixclk,
5081 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5082 }
5083
5084 return max_pixclk;
5085 }
5086
5087 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5088 unsigned *prepare_pipes)
5089 {
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 struct intel_crtc *intel_crtc;
5092 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5093
5094 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5095 dev_priv->vlv_cdclk_freq)
5096 return;
5097
5098 /* disable/enable all currently active pipes while we change cdclk */
5099 for_each_intel_crtc(dev, intel_crtc)
5100 if (intel_crtc->base.state->enable)
5101 *prepare_pipes |= (1 << intel_crtc->pipe);
5102 }
5103
5104 static void valleyview_modeset_global_resources(struct drm_device *dev)
5105 {
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5108 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5109
5110 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5111 /*
5112 * FIXME: We can end up here with all power domains off, yet
5113 * with a CDCLK frequency other than the minimum. To account
5114 * for this take the PIPE-A power domain, which covers the HW
5115 * blocks needed for the following programming. This can be
5116 * removed once it's guaranteed that we get here either with
5117 * the minimum CDCLK set, or the required power domains
5118 * enabled.
5119 */
5120 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5121
5122 if (IS_CHERRYVIEW(dev))
5123 cherryview_set_cdclk(dev, req_cdclk);
5124 else
5125 valleyview_set_cdclk(dev, req_cdclk);
5126
5127 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5128 }
5129 }
5130
5131 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5132 {
5133 struct drm_device *dev = crtc->dev;
5134 struct drm_i915_private *dev_priv = to_i915(dev);
5135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136 struct intel_encoder *encoder;
5137 int pipe = intel_crtc->pipe;
5138 bool is_dsi;
5139
5140 WARN_ON(!crtc->state->enable);
5141
5142 if (intel_crtc->active)
5143 return;
5144
5145 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5146
5147 if (!is_dsi) {
5148 if (IS_CHERRYVIEW(dev))
5149 chv_prepare_pll(intel_crtc, intel_crtc->config);
5150 else
5151 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5152 }
5153
5154 if (intel_crtc->config->has_dp_encoder)
5155 intel_dp_set_m_n(intel_crtc, M1_N1);
5156
5157 intel_set_pipe_timings(intel_crtc);
5158
5159 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5160 struct drm_i915_private *dev_priv = dev->dev_private;
5161
5162 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5163 I915_WRITE(CHV_CANVAS(pipe), 0);
5164 }
5165
5166 i9xx_set_pipeconf(intel_crtc);
5167
5168 intel_crtc->active = true;
5169
5170 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5171
5172 for_each_encoder_on_crtc(dev, crtc, encoder)
5173 if (encoder->pre_pll_enable)
5174 encoder->pre_pll_enable(encoder);
5175
5176 if (!is_dsi) {
5177 if (IS_CHERRYVIEW(dev))
5178 chv_enable_pll(intel_crtc, intel_crtc->config);
5179 else
5180 vlv_enable_pll(intel_crtc, intel_crtc->config);
5181 }
5182
5183 for_each_encoder_on_crtc(dev, crtc, encoder)
5184 if (encoder->pre_enable)
5185 encoder->pre_enable(encoder);
5186
5187 i9xx_pfit_enable(intel_crtc);
5188
5189 intel_crtc_load_lut(crtc);
5190
5191 intel_update_watermarks(crtc);
5192 intel_enable_pipe(intel_crtc);
5193
5194 assert_vblank_disabled(crtc);
5195 drm_crtc_vblank_on(crtc);
5196
5197 for_each_encoder_on_crtc(dev, crtc, encoder)
5198 encoder->enable(encoder);
5199
5200 intel_crtc_enable_planes(crtc);
5201
5202 /* Underruns don't raise interrupts, so check manually. */
5203 i9xx_check_fifo_underruns(dev_priv);
5204 }
5205
5206 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5207 {
5208 struct drm_device *dev = crtc->base.dev;
5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210
5211 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5212 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5213 }
5214
5215 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5216 {
5217 struct drm_device *dev = crtc->dev;
5218 struct drm_i915_private *dev_priv = to_i915(dev);
5219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5220 struct intel_encoder *encoder;
5221 int pipe = intel_crtc->pipe;
5222
5223 WARN_ON(!crtc->state->enable);
5224
5225 if (intel_crtc->active)
5226 return;
5227
5228 i9xx_set_pll_dividers(intel_crtc);
5229
5230 if (intel_crtc->config->has_dp_encoder)
5231 intel_dp_set_m_n(intel_crtc, M1_N1);
5232
5233 intel_set_pipe_timings(intel_crtc);
5234
5235 i9xx_set_pipeconf(intel_crtc);
5236
5237 intel_crtc->active = true;
5238
5239 if (!IS_GEN2(dev))
5240 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5241
5242 for_each_encoder_on_crtc(dev, crtc, encoder)
5243 if (encoder->pre_enable)
5244 encoder->pre_enable(encoder);
5245
5246 i9xx_enable_pll(intel_crtc);
5247
5248 i9xx_pfit_enable(intel_crtc);
5249
5250 intel_crtc_load_lut(crtc);
5251
5252 intel_update_watermarks(crtc);
5253 intel_enable_pipe(intel_crtc);
5254
5255 assert_vblank_disabled(crtc);
5256 drm_crtc_vblank_on(crtc);
5257
5258 for_each_encoder_on_crtc(dev, crtc, encoder)
5259 encoder->enable(encoder);
5260
5261 intel_crtc_enable_planes(crtc);
5262
5263 /*
5264 * Gen2 reports pipe underruns whenever all planes are disabled.
5265 * So don't enable underrun reporting before at least some planes
5266 * are enabled.
5267 * FIXME: Need to fix the logic to work when we turn off all planes
5268 * but leave the pipe running.
5269 */
5270 if (IS_GEN2(dev))
5271 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5272
5273 /* Underruns don't raise interrupts, so check manually. */
5274 i9xx_check_fifo_underruns(dev_priv);
5275 }
5276
5277 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5278 {
5279 struct drm_device *dev = crtc->base.dev;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281
5282 if (!crtc->config->gmch_pfit.control)
5283 return;
5284
5285 assert_pipe_disabled(dev_priv, crtc->pipe);
5286
5287 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5288 I915_READ(PFIT_CONTROL));
5289 I915_WRITE(PFIT_CONTROL, 0);
5290 }
5291
5292 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5293 {
5294 struct drm_device *dev = crtc->dev;
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5297 struct intel_encoder *encoder;
5298 int pipe = intel_crtc->pipe;
5299
5300 if (!intel_crtc->active)
5301 return;
5302
5303 /*
5304 * Gen2 reports pipe underruns whenever all planes are disabled.
5305 * So diasble underrun reporting before all the planes get disabled.
5306 * FIXME: Need to fix the logic to work when we turn off all planes
5307 * but leave the pipe running.
5308 */
5309 if (IS_GEN2(dev))
5310 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5311
5312 /*
5313 * Vblank time updates from the shadow to live plane control register
5314 * are blocked if the memory self-refresh mode is active at that
5315 * moment. So to make sure the plane gets truly disabled, disable
5316 * first the self-refresh mode. The self-refresh enable bit in turn
5317 * will be checked/applied by the HW only at the next frame start
5318 * event which is after the vblank start event, so we need to have a
5319 * wait-for-vblank between disabling the plane and the pipe.
5320 */
5321 intel_set_memory_cxsr(dev_priv, false);
5322 intel_crtc_disable_planes(crtc);
5323
5324 /*
5325 * On gen2 planes are double buffered but the pipe isn't, so we must
5326 * wait for planes to fully turn off before disabling the pipe.
5327 * We also need to wait on all gmch platforms because of the
5328 * self-refresh mode constraint explained above.
5329 */
5330 intel_wait_for_vblank(dev, pipe);
5331
5332 for_each_encoder_on_crtc(dev, crtc, encoder)
5333 encoder->disable(encoder);
5334
5335 drm_crtc_vblank_off(crtc);
5336 assert_vblank_disabled(crtc);
5337
5338 intel_disable_pipe(intel_crtc);
5339
5340 i9xx_pfit_disable(intel_crtc);
5341
5342 for_each_encoder_on_crtc(dev, crtc, encoder)
5343 if (encoder->post_disable)
5344 encoder->post_disable(encoder);
5345
5346 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5347 if (IS_CHERRYVIEW(dev))
5348 chv_disable_pll(dev_priv, pipe);
5349 else if (IS_VALLEYVIEW(dev))
5350 vlv_disable_pll(dev_priv, pipe);
5351 else
5352 i9xx_disable_pll(intel_crtc);
5353 }
5354
5355 if (!IS_GEN2(dev))
5356 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5357
5358 intel_crtc->active = false;
5359 intel_update_watermarks(crtc);
5360
5361 mutex_lock(&dev->struct_mutex);
5362 intel_fbc_update(dev);
5363 mutex_unlock(&dev->struct_mutex);
5364 }
5365
5366 static void i9xx_crtc_off(struct drm_crtc *crtc)
5367 {
5368 }
5369
5370 /* Master function to enable/disable CRTC and corresponding power wells */
5371 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5372 {
5373 struct drm_device *dev = crtc->dev;
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 enum intel_display_power_domain domain;
5377 unsigned long domains;
5378
5379 if (enable) {
5380 if (!intel_crtc->active) {
5381 domains = get_crtc_power_domains(crtc);
5382 for_each_power_domain(domain, domains)
5383 intel_display_power_get(dev_priv, domain);
5384 intel_crtc->enabled_power_domains = domains;
5385
5386 dev_priv->display.crtc_enable(crtc);
5387 }
5388 } else {
5389 if (intel_crtc->active) {
5390 dev_priv->display.crtc_disable(crtc);
5391
5392 domains = intel_crtc->enabled_power_domains;
5393 for_each_power_domain(domain, domains)
5394 intel_display_power_put(dev_priv, domain);
5395 intel_crtc->enabled_power_domains = 0;
5396 }
5397 }
5398 }
5399
5400 /**
5401 * Sets the power management mode of the pipe and plane.
5402 */
5403 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5404 {
5405 struct drm_device *dev = crtc->dev;
5406 struct intel_encoder *intel_encoder;
5407 bool enable = false;
5408
5409 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5410 enable |= intel_encoder->connectors_active;
5411
5412 intel_crtc_control(crtc, enable);
5413 }
5414
5415 static void intel_crtc_disable(struct drm_crtc *crtc)
5416 {
5417 struct drm_device *dev = crtc->dev;
5418 struct drm_connector *connector;
5419 struct drm_i915_private *dev_priv = dev->dev_private;
5420
5421 /* crtc should still be enabled when we disable it. */
5422 WARN_ON(!crtc->state->enable);
5423
5424 dev_priv->display.crtc_disable(crtc);
5425 dev_priv->display.off(crtc);
5426
5427 crtc->primary->funcs->disable_plane(crtc->primary);
5428
5429 /* Update computed state. */
5430 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5431 if (!connector->encoder || !connector->encoder->crtc)
5432 continue;
5433
5434 if (connector->encoder->crtc != crtc)
5435 continue;
5436
5437 connector->dpms = DRM_MODE_DPMS_OFF;
5438 to_intel_encoder(connector->encoder)->connectors_active = false;
5439 }
5440 }
5441
5442 void intel_encoder_destroy(struct drm_encoder *encoder)
5443 {
5444 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5445
5446 drm_encoder_cleanup(encoder);
5447 kfree(intel_encoder);
5448 }
5449
5450 /* Simple dpms helper for encoders with just one connector, no cloning and only
5451 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5452 * state of the entire output pipe. */
5453 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5454 {
5455 if (mode == DRM_MODE_DPMS_ON) {
5456 encoder->connectors_active = true;
5457
5458 intel_crtc_update_dpms(encoder->base.crtc);
5459 } else {
5460 encoder->connectors_active = false;
5461
5462 intel_crtc_update_dpms(encoder->base.crtc);
5463 }
5464 }
5465
5466 /* Cross check the actual hw state with our own modeset state tracking (and it's
5467 * internal consistency). */
5468 static void intel_connector_check_state(struct intel_connector *connector)
5469 {
5470 if (connector->get_hw_state(connector)) {
5471 struct intel_encoder *encoder = connector->encoder;
5472 struct drm_crtc *crtc;
5473 bool encoder_enabled;
5474 enum pipe pipe;
5475
5476 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5477 connector->base.base.id,
5478 connector->base.name);
5479
5480 /* there is no real hw state for MST connectors */
5481 if (connector->mst_port)
5482 return;
5483
5484 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5485 "wrong connector dpms state\n");
5486 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5487 "active connector not linked to encoder\n");
5488
5489 if (encoder) {
5490 I915_STATE_WARN(!encoder->connectors_active,
5491 "encoder->connectors_active not set\n");
5492
5493 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5494 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5495 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5496 return;
5497
5498 crtc = encoder->base.crtc;
5499
5500 I915_STATE_WARN(!crtc->state->enable,
5501 "crtc not enabled\n");
5502 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5503 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5504 "encoder active on the wrong pipe\n");
5505 }
5506 }
5507 }
5508
5509 /* Even simpler default implementation, if there's really no special case to
5510 * consider. */
5511 void intel_connector_dpms(struct drm_connector *connector, int mode)
5512 {
5513 /* All the simple cases only support two dpms states. */
5514 if (mode != DRM_MODE_DPMS_ON)
5515 mode = DRM_MODE_DPMS_OFF;
5516
5517 if (mode == connector->dpms)
5518 return;
5519
5520 connector->dpms = mode;
5521
5522 /* Only need to change hw state when actually enabled */
5523 if (connector->encoder)
5524 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5525
5526 intel_modeset_check_state(connector->dev);
5527 }
5528
5529 /* Simple connector->get_hw_state implementation for encoders that support only
5530 * one connector and no cloning and hence the encoder state determines the state
5531 * of the connector. */
5532 bool intel_connector_get_hw_state(struct intel_connector *connector)
5533 {
5534 enum pipe pipe = 0;
5535 struct intel_encoder *encoder = connector->encoder;
5536
5537 return encoder->get_hw_state(encoder, &pipe);
5538 }
5539
5540 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5541 struct intel_crtc_state *pipe_config)
5542 {
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5544 struct intel_crtc *pipe_B_crtc =
5545 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5546
5547 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5548 pipe_name(pipe), pipe_config->fdi_lanes);
5549 if (pipe_config->fdi_lanes > 4) {
5550 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5551 pipe_name(pipe), pipe_config->fdi_lanes);
5552 return false;
5553 }
5554
5555 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5556 if (pipe_config->fdi_lanes > 2) {
5557 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5558 pipe_config->fdi_lanes);
5559 return false;
5560 } else {
5561 return true;
5562 }
5563 }
5564
5565 if (INTEL_INFO(dev)->num_pipes == 2)
5566 return true;
5567
5568 /* Ivybridge 3 pipe is really complicated */
5569 switch (pipe) {
5570 case PIPE_A:
5571 return true;
5572 case PIPE_B:
5573 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5574 pipe_config->fdi_lanes > 2) {
5575 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5576 pipe_name(pipe), pipe_config->fdi_lanes);
5577 return false;
5578 }
5579 return true;
5580 case PIPE_C:
5581 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5582 pipe_B_crtc->config->fdi_lanes <= 2) {
5583 if (pipe_config->fdi_lanes > 2) {
5584 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5585 pipe_name(pipe), pipe_config->fdi_lanes);
5586 return false;
5587 }
5588 } else {
5589 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5590 return false;
5591 }
5592 return true;
5593 default:
5594 BUG();
5595 }
5596 }
5597
5598 #define RETRY 1
5599 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5600 struct intel_crtc_state *pipe_config)
5601 {
5602 struct drm_device *dev = intel_crtc->base.dev;
5603 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5604 int lane, link_bw, fdi_dotclock;
5605 bool setup_ok, needs_recompute = false;
5606
5607 retry:
5608 /* FDI is a binary signal running at ~2.7GHz, encoding
5609 * each output octet as 10 bits. The actual frequency
5610 * is stored as a divider into a 100MHz clock, and the
5611 * mode pixel clock is stored in units of 1KHz.
5612 * Hence the bw of each lane in terms of the mode signal
5613 * is:
5614 */
5615 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5616
5617 fdi_dotclock = adjusted_mode->crtc_clock;
5618
5619 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5620 pipe_config->pipe_bpp);
5621
5622 pipe_config->fdi_lanes = lane;
5623
5624 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5625 link_bw, &pipe_config->fdi_m_n);
5626
5627 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5628 intel_crtc->pipe, pipe_config);
5629 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5630 pipe_config->pipe_bpp -= 2*3;
5631 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5632 pipe_config->pipe_bpp);
5633 needs_recompute = true;
5634 pipe_config->bw_constrained = true;
5635
5636 goto retry;
5637 }
5638
5639 if (needs_recompute)
5640 return RETRY;
5641
5642 return setup_ok ? 0 : -EINVAL;
5643 }
5644
5645 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5646 struct intel_crtc_state *pipe_config)
5647 {
5648 pipe_config->ips_enabled = i915.enable_ips &&
5649 hsw_crtc_supports_ips(crtc) &&
5650 pipe_config->pipe_bpp <= 24;
5651 }
5652
5653 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5654 struct intel_crtc_state *pipe_config)
5655 {
5656 struct drm_device *dev = crtc->base.dev;
5657 struct drm_i915_private *dev_priv = dev->dev_private;
5658 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5659
5660 /* FIXME should check pixel clock limits on all platforms */
5661 if (INTEL_INFO(dev)->gen < 4) {
5662 int clock_limit =
5663 dev_priv->display.get_display_clock_speed(dev);
5664
5665 /*
5666 * Enable pixel doubling when the dot clock
5667 * is > 90% of the (display) core speed.
5668 *
5669 * GDG double wide on either pipe,
5670 * otherwise pipe A only.
5671 */
5672 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5673 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5674 clock_limit *= 2;
5675 pipe_config->double_wide = true;
5676 }
5677
5678 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5679 return -EINVAL;
5680 }
5681
5682 /*
5683 * Pipe horizontal size must be even in:
5684 * - DVO ganged mode
5685 * - LVDS dual channel mode
5686 * - Double wide pipe
5687 */
5688 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5689 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5690 pipe_config->pipe_src_w &= ~1;
5691
5692 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5693 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5694 */
5695 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5696 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5697 return -EINVAL;
5698
5699 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5700 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5701 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5702 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5703 * for lvds. */
5704 pipe_config->pipe_bpp = 8*3;
5705 }
5706
5707 if (HAS_IPS(dev))
5708 hsw_compute_ips_config(crtc, pipe_config);
5709
5710 if (pipe_config->has_pch_encoder)
5711 return ironlake_fdi_compute_config(crtc, pipe_config);
5712
5713 return 0;
5714 }
5715
5716 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5717 {
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719 u32 val;
5720 int divider;
5721
5722 /* FIXME: Punit isn't quite ready yet */
5723 if (IS_CHERRYVIEW(dev))
5724 return 400000;
5725
5726 if (dev_priv->hpll_freq == 0)
5727 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5728
5729 mutex_lock(&dev_priv->dpio_lock);
5730 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5731 mutex_unlock(&dev_priv->dpio_lock);
5732
5733 divider = val & DISPLAY_FREQUENCY_VALUES;
5734
5735 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5736 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5737 "cdclk change in progress\n");
5738
5739 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5740 }
5741
5742 static int i945_get_display_clock_speed(struct drm_device *dev)
5743 {
5744 return 400000;
5745 }
5746
5747 static int i915_get_display_clock_speed(struct drm_device *dev)
5748 {
5749 return 333000;
5750 }
5751
5752 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5753 {
5754 return 200000;
5755 }
5756
5757 static int pnv_get_display_clock_speed(struct drm_device *dev)
5758 {
5759 u16 gcfgc = 0;
5760
5761 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5762
5763 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5764 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5765 return 267000;
5766 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5767 return 333000;
5768 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5769 return 444000;
5770 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5771 return 200000;
5772 default:
5773 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5774 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5775 return 133000;
5776 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5777 return 167000;
5778 }
5779 }
5780
5781 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5782 {
5783 u16 gcfgc = 0;
5784
5785 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5786
5787 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5788 return 133000;
5789 else {
5790 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5791 case GC_DISPLAY_CLOCK_333_MHZ:
5792 return 333000;
5793 default:
5794 case GC_DISPLAY_CLOCK_190_200_MHZ:
5795 return 190000;
5796 }
5797 }
5798 }
5799
5800 static int i865_get_display_clock_speed(struct drm_device *dev)
5801 {
5802 return 266000;
5803 }
5804
5805 static int i855_get_display_clock_speed(struct drm_device *dev)
5806 {
5807 u16 hpllcc = 0;
5808 /* Assume that the hardware is in the high speed state. This
5809 * should be the default.
5810 */
5811 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5812 case GC_CLOCK_133_200:
5813 case GC_CLOCK_100_200:
5814 return 200000;
5815 case GC_CLOCK_166_250:
5816 return 250000;
5817 case GC_CLOCK_100_133:
5818 return 133000;
5819 }
5820
5821 /* Shouldn't happen */
5822 return 0;
5823 }
5824
5825 static int i830_get_display_clock_speed(struct drm_device *dev)
5826 {
5827 return 133000;
5828 }
5829
5830 static void
5831 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5832 {
5833 while (*num > DATA_LINK_M_N_MASK ||
5834 *den > DATA_LINK_M_N_MASK) {
5835 *num >>= 1;
5836 *den >>= 1;
5837 }
5838 }
5839
5840 static void compute_m_n(unsigned int m, unsigned int n,
5841 uint32_t *ret_m, uint32_t *ret_n)
5842 {
5843 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5844 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5845 intel_reduce_m_n_ratio(ret_m, ret_n);
5846 }
5847
5848 void
5849 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5850 int pixel_clock, int link_clock,
5851 struct intel_link_m_n *m_n)
5852 {
5853 m_n->tu = 64;
5854
5855 compute_m_n(bits_per_pixel * pixel_clock,
5856 link_clock * nlanes * 8,
5857 &m_n->gmch_m, &m_n->gmch_n);
5858
5859 compute_m_n(pixel_clock, link_clock,
5860 &m_n->link_m, &m_n->link_n);
5861 }
5862
5863 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5864 {
5865 if (i915.panel_use_ssc >= 0)
5866 return i915.panel_use_ssc != 0;
5867 return dev_priv->vbt.lvds_use_ssc
5868 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5869 }
5870
5871 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5872 {
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 int refclk;
5876
5877 if (IS_VALLEYVIEW(dev)) {
5878 refclk = 100000;
5879 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5880 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5881 refclk = dev_priv->vbt.lvds_ssc_freq;
5882 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5883 } else if (!IS_GEN2(dev)) {
5884 refclk = 96000;
5885 } else {
5886 refclk = 48000;
5887 }
5888
5889 return refclk;
5890 }
5891
5892 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5893 {
5894 return (1 << dpll->n) << 16 | dpll->m2;
5895 }
5896
5897 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5898 {
5899 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5900 }
5901
5902 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5903 struct intel_crtc_state *crtc_state,
5904 intel_clock_t *reduced_clock)
5905 {
5906 struct drm_device *dev = crtc->base.dev;
5907 u32 fp, fp2 = 0;
5908
5909 if (IS_PINEVIEW(dev)) {
5910 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5911 if (reduced_clock)
5912 fp2 = pnv_dpll_compute_fp(reduced_clock);
5913 } else {
5914 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5915 if (reduced_clock)
5916 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5917 }
5918
5919 crtc_state->dpll_hw_state.fp0 = fp;
5920
5921 crtc->lowfreq_avail = false;
5922 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5923 reduced_clock && i915.powersave) {
5924 crtc_state->dpll_hw_state.fp1 = fp2;
5925 crtc->lowfreq_avail = true;
5926 } else {
5927 crtc_state->dpll_hw_state.fp1 = fp;
5928 }
5929 }
5930
5931 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5932 pipe)
5933 {
5934 u32 reg_val;
5935
5936 /*
5937 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5938 * and set it to a reasonable value instead.
5939 */
5940 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5941 reg_val &= 0xffffff00;
5942 reg_val |= 0x00000030;
5943 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5944
5945 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5946 reg_val &= 0x8cffffff;
5947 reg_val = 0x8c000000;
5948 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5949
5950 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5951 reg_val &= 0xffffff00;
5952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5953
5954 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5955 reg_val &= 0x00ffffff;
5956 reg_val |= 0xb0000000;
5957 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5958 }
5959
5960 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5961 struct intel_link_m_n *m_n)
5962 {
5963 struct drm_device *dev = crtc->base.dev;
5964 struct drm_i915_private *dev_priv = dev->dev_private;
5965 int pipe = crtc->pipe;
5966
5967 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5968 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5969 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5970 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5971 }
5972
5973 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5974 struct intel_link_m_n *m_n,
5975 struct intel_link_m_n *m2_n2)
5976 {
5977 struct drm_device *dev = crtc->base.dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 int pipe = crtc->pipe;
5980 enum transcoder transcoder = crtc->config->cpu_transcoder;
5981
5982 if (INTEL_INFO(dev)->gen >= 5) {
5983 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5984 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5985 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5986 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5987 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5988 * for gen < 8) and if DRRS is supported (to make sure the
5989 * registers are not unnecessarily accessed).
5990 */
5991 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5992 crtc->config->has_drrs) {
5993 I915_WRITE(PIPE_DATA_M2(transcoder),
5994 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5995 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5996 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5997 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5998 }
5999 } else {
6000 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6001 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6002 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6003 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6004 }
6005 }
6006
6007 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6008 {
6009 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6010
6011 if (m_n == M1_N1) {
6012 dp_m_n = &crtc->config->dp_m_n;
6013 dp_m2_n2 = &crtc->config->dp_m2_n2;
6014 } else if (m_n == M2_N2) {
6015
6016 /*
6017 * M2_N2 registers are not supported. Hence m2_n2 divider value
6018 * needs to be programmed into M1_N1.
6019 */
6020 dp_m_n = &crtc->config->dp_m2_n2;
6021 } else {
6022 DRM_ERROR("Unsupported divider value\n");
6023 return;
6024 }
6025
6026 if (crtc->config->has_pch_encoder)
6027 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6028 else
6029 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6030 }
6031
6032 static void vlv_update_pll(struct intel_crtc *crtc,
6033 struct intel_crtc_state *pipe_config)
6034 {
6035 u32 dpll, dpll_md;
6036
6037 /*
6038 * Enable DPIO clock input. We should never disable the reference
6039 * clock for pipe B, since VGA hotplug / manual detection depends
6040 * on it.
6041 */
6042 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6043 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6044 /* We should never disable this, set it here for state tracking */
6045 if (crtc->pipe == PIPE_B)
6046 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6047 dpll |= DPLL_VCO_ENABLE;
6048 pipe_config->dpll_hw_state.dpll = dpll;
6049
6050 dpll_md = (pipe_config->pixel_multiplier - 1)
6051 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6052 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6053 }
6054
6055 static void vlv_prepare_pll(struct intel_crtc *crtc,
6056 const struct intel_crtc_state *pipe_config)
6057 {
6058 struct drm_device *dev = crtc->base.dev;
6059 struct drm_i915_private *dev_priv = dev->dev_private;
6060 int pipe = crtc->pipe;
6061 u32 mdiv;
6062 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6063 u32 coreclk, reg_val;
6064
6065 mutex_lock(&dev_priv->dpio_lock);
6066
6067 bestn = pipe_config->dpll.n;
6068 bestm1 = pipe_config->dpll.m1;
6069 bestm2 = pipe_config->dpll.m2;
6070 bestp1 = pipe_config->dpll.p1;
6071 bestp2 = pipe_config->dpll.p2;
6072
6073 /* See eDP HDMI DPIO driver vbios notes doc */
6074
6075 /* PLL B needs special handling */
6076 if (pipe == PIPE_B)
6077 vlv_pllb_recal_opamp(dev_priv, pipe);
6078
6079 /* Set up Tx target for periodic Rcomp update */
6080 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6081
6082 /* Disable target IRef on PLL */
6083 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6084 reg_val &= 0x00ffffff;
6085 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6086
6087 /* Disable fast lock */
6088 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6089
6090 /* Set idtafcrecal before PLL is enabled */
6091 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6092 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6093 mdiv |= ((bestn << DPIO_N_SHIFT));
6094 mdiv |= (1 << DPIO_K_SHIFT);
6095
6096 /*
6097 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6098 * but we don't support that).
6099 * Note: don't use the DAC post divider as it seems unstable.
6100 */
6101 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6102 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6103
6104 mdiv |= DPIO_ENABLE_CALIBRATION;
6105 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6106
6107 /* Set HBR and RBR LPF coefficients */
6108 if (pipe_config->port_clock == 162000 ||
6109 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6110 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6111 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6112 0x009f0003);
6113 else
6114 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6115 0x00d0000f);
6116
6117 if (pipe_config->has_dp_encoder) {
6118 /* Use SSC source */
6119 if (pipe == PIPE_A)
6120 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6121 0x0df40000);
6122 else
6123 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6124 0x0df70000);
6125 } else { /* HDMI or VGA */
6126 /* Use bend source */
6127 if (pipe == PIPE_A)
6128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6129 0x0df70000);
6130 else
6131 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6132 0x0df40000);
6133 }
6134
6135 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6136 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6137 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6138 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6139 coreclk |= 0x01000000;
6140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6141
6142 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6143 mutex_unlock(&dev_priv->dpio_lock);
6144 }
6145
6146 static void chv_update_pll(struct intel_crtc *crtc,
6147 struct intel_crtc_state *pipe_config)
6148 {
6149 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6150 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6151 DPLL_VCO_ENABLE;
6152 if (crtc->pipe != PIPE_A)
6153 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6154
6155 pipe_config->dpll_hw_state.dpll_md =
6156 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6157 }
6158
6159 static void chv_prepare_pll(struct intel_crtc *crtc,
6160 const struct intel_crtc_state *pipe_config)
6161 {
6162 struct drm_device *dev = crtc->base.dev;
6163 struct drm_i915_private *dev_priv = dev->dev_private;
6164 int pipe = crtc->pipe;
6165 int dpll_reg = DPLL(crtc->pipe);
6166 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6167 u32 loopfilter, intcoeff;
6168 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6169 int refclk;
6170
6171 bestn = pipe_config->dpll.n;
6172 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6173 bestm1 = pipe_config->dpll.m1;
6174 bestm2 = pipe_config->dpll.m2 >> 22;
6175 bestp1 = pipe_config->dpll.p1;
6176 bestp2 = pipe_config->dpll.p2;
6177
6178 /*
6179 * Enable Refclk and SSC
6180 */
6181 I915_WRITE(dpll_reg,
6182 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6183
6184 mutex_lock(&dev_priv->dpio_lock);
6185
6186 /* p1 and p2 divider */
6187 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6188 5 << DPIO_CHV_S1_DIV_SHIFT |
6189 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6190 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6191 1 << DPIO_CHV_K_DIV_SHIFT);
6192
6193 /* Feedback post-divider - m2 */
6194 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6195
6196 /* Feedback refclk divider - n and m1 */
6197 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6198 DPIO_CHV_M1_DIV_BY_2 |
6199 1 << DPIO_CHV_N_DIV_SHIFT);
6200
6201 /* M2 fraction division */
6202 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6203
6204 /* M2 fraction division enable */
6205 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6206 DPIO_CHV_FRAC_DIV_EN |
6207 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6208
6209 /* Loop filter */
6210 refclk = i9xx_get_refclk(crtc, 0);
6211 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6212 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6213 if (refclk == 100000)
6214 intcoeff = 11;
6215 else if (refclk == 38400)
6216 intcoeff = 10;
6217 else
6218 intcoeff = 9;
6219 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6220 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6221
6222 /* AFC Recal */
6223 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6224 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6225 DPIO_AFC_RECAL);
6226
6227 mutex_unlock(&dev_priv->dpio_lock);
6228 }
6229
6230 /**
6231 * vlv_force_pll_on - forcibly enable just the PLL
6232 * @dev_priv: i915 private structure
6233 * @pipe: pipe PLL to enable
6234 * @dpll: PLL configuration
6235 *
6236 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6237 * in cases where we need the PLL enabled even when @pipe is not going to
6238 * be enabled.
6239 */
6240 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6241 const struct dpll *dpll)
6242 {
6243 struct intel_crtc *crtc =
6244 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6245 struct intel_crtc_state pipe_config = {
6246 .pixel_multiplier = 1,
6247 .dpll = *dpll,
6248 };
6249
6250 if (IS_CHERRYVIEW(dev)) {
6251 chv_update_pll(crtc, &pipe_config);
6252 chv_prepare_pll(crtc, &pipe_config);
6253 chv_enable_pll(crtc, &pipe_config);
6254 } else {
6255 vlv_update_pll(crtc, &pipe_config);
6256 vlv_prepare_pll(crtc, &pipe_config);
6257 vlv_enable_pll(crtc, &pipe_config);
6258 }
6259 }
6260
6261 /**
6262 * vlv_force_pll_off - forcibly disable just the PLL
6263 * @dev_priv: i915 private structure
6264 * @pipe: pipe PLL to disable
6265 *
6266 * Disable the PLL for @pipe. To be used in cases where we need
6267 * the PLL enabled even when @pipe is not going to be enabled.
6268 */
6269 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6270 {
6271 if (IS_CHERRYVIEW(dev))
6272 chv_disable_pll(to_i915(dev), pipe);
6273 else
6274 vlv_disable_pll(to_i915(dev), pipe);
6275 }
6276
6277 static void i9xx_update_pll(struct intel_crtc *crtc,
6278 struct intel_crtc_state *crtc_state,
6279 intel_clock_t *reduced_clock,
6280 int num_connectors)
6281 {
6282 struct drm_device *dev = crtc->base.dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284 u32 dpll;
6285 bool is_sdvo;
6286 struct dpll *clock = &crtc_state->dpll;
6287
6288 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6289
6290 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6291 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6292
6293 dpll = DPLL_VGA_MODE_DIS;
6294
6295 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6296 dpll |= DPLLB_MODE_LVDS;
6297 else
6298 dpll |= DPLLB_MODE_DAC_SERIAL;
6299
6300 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6301 dpll |= (crtc_state->pixel_multiplier - 1)
6302 << SDVO_MULTIPLIER_SHIFT_HIRES;
6303 }
6304
6305 if (is_sdvo)
6306 dpll |= DPLL_SDVO_HIGH_SPEED;
6307
6308 if (crtc_state->has_dp_encoder)
6309 dpll |= DPLL_SDVO_HIGH_SPEED;
6310
6311 /* compute bitmask from p1 value */
6312 if (IS_PINEVIEW(dev))
6313 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6314 else {
6315 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6316 if (IS_G4X(dev) && reduced_clock)
6317 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6318 }
6319 switch (clock->p2) {
6320 case 5:
6321 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6322 break;
6323 case 7:
6324 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6325 break;
6326 case 10:
6327 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6328 break;
6329 case 14:
6330 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6331 break;
6332 }
6333 if (INTEL_INFO(dev)->gen >= 4)
6334 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6335
6336 if (crtc_state->sdvo_tv_clock)
6337 dpll |= PLL_REF_INPUT_TVCLKINBC;
6338 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6339 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6340 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6341 else
6342 dpll |= PLL_REF_INPUT_DREFCLK;
6343
6344 dpll |= DPLL_VCO_ENABLE;
6345 crtc_state->dpll_hw_state.dpll = dpll;
6346
6347 if (INTEL_INFO(dev)->gen >= 4) {
6348 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6349 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6350 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6351 }
6352 }
6353
6354 static void i8xx_update_pll(struct intel_crtc *crtc,
6355 struct intel_crtc_state *crtc_state,
6356 intel_clock_t *reduced_clock,
6357 int num_connectors)
6358 {
6359 struct drm_device *dev = crtc->base.dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 u32 dpll;
6362 struct dpll *clock = &crtc_state->dpll;
6363
6364 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6365
6366 dpll = DPLL_VGA_MODE_DIS;
6367
6368 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6369 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6370 } else {
6371 if (clock->p1 == 2)
6372 dpll |= PLL_P1_DIVIDE_BY_TWO;
6373 else
6374 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6375 if (clock->p2 == 4)
6376 dpll |= PLL_P2_DIVIDE_BY_4;
6377 }
6378
6379 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6380 dpll |= DPLL_DVO_2X_MODE;
6381
6382 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6383 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6384 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6385 else
6386 dpll |= PLL_REF_INPUT_DREFCLK;
6387
6388 dpll |= DPLL_VCO_ENABLE;
6389 crtc_state->dpll_hw_state.dpll = dpll;
6390 }
6391
6392 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6393 {
6394 struct drm_device *dev = intel_crtc->base.dev;
6395 struct drm_i915_private *dev_priv = dev->dev_private;
6396 enum pipe pipe = intel_crtc->pipe;
6397 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6398 struct drm_display_mode *adjusted_mode =
6399 &intel_crtc->config->base.adjusted_mode;
6400 uint32_t crtc_vtotal, crtc_vblank_end;
6401 int vsyncshift = 0;
6402
6403 /* We need to be careful not to changed the adjusted mode, for otherwise
6404 * the hw state checker will get angry at the mismatch. */
6405 crtc_vtotal = adjusted_mode->crtc_vtotal;
6406 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6407
6408 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6409 /* the chip adds 2 halflines automatically */
6410 crtc_vtotal -= 1;
6411 crtc_vblank_end -= 1;
6412
6413 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6414 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6415 else
6416 vsyncshift = adjusted_mode->crtc_hsync_start -
6417 adjusted_mode->crtc_htotal / 2;
6418 if (vsyncshift < 0)
6419 vsyncshift += adjusted_mode->crtc_htotal;
6420 }
6421
6422 if (INTEL_INFO(dev)->gen > 3)
6423 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6424
6425 I915_WRITE(HTOTAL(cpu_transcoder),
6426 (adjusted_mode->crtc_hdisplay - 1) |
6427 ((adjusted_mode->crtc_htotal - 1) << 16));
6428 I915_WRITE(HBLANK(cpu_transcoder),
6429 (adjusted_mode->crtc_hblank_start - 1) |
6430 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6431 I915_WRITE(HSYNC(cpu_transcoder),
6432 (adjusted_mode->crtc_hsync_start - 1) |
6433 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6434
6435 I915_WRITE(VTOTAL(cpu_transcoder),
6436 (adjusted_mode->crtc_vdisplay - 1) |
6437 ((crtc_vtotal - 1) << 16));
6438 I915_WRITE(VBLANK(cpu_transcoder),
6439 (adjusted_mode->crtc_vblank_start - 1) |
6440 ((crtc_vblank_end - 1) << 16));
6441 I915_WRITE(VSYNC(cpu_transcoder),
6442 (adjusted_mode->crtc_vsync_start - 1) |
6443 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6444
6445 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6446 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6447 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6448 * bits. */
6449 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6450 (pipe == PIPE_B || pipe == PIPE_C))
6451 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6452
6453 /* pipesrc controls the size that is scaled from, which should
6454 * always be the user's requested size.
6455 */
6456 I915_WRITE(PIPESRC(pipe),
6457 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6458 (intel_crtc->config->pipe_src_h - 1));
6459 }
6460
6461 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6462 struct intel_crtc_state *pipe_config)
6463 {
6464 struct drm_device *dev = crtc->base.dev;
6465 struct drm_i915_private *dev_priv = dev->dev_private;
6466 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6467 uint32_t tmp;
6468
6469 tmp = I915_READ(HTOTAL(cpu_transcoder));
6470 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6471 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6472 tmp = I915_READ(HBLANK(cpu_transcoder));
6473 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6474 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6475 tmp = I915_READ(HSYNC(cpu_transcoder));
6476 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6477 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6478
6479 tmp = I915_READ(VTOTAL(cpu_transcoder));
6480 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6481 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6482 tmp = I915_READ(VBLANK(cpu_transcoder));
6483 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6484 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6485 tmp = I915_READ(VSYNC(cpu_transcoder));
6486 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6487 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6488
6489 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6490 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6491 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6492 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6493 }
6494
6495 tmp = I915_READ(PIPESRC(crtc->pipe));
6496 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6497 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6498
6499 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6500 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6501 }
6502
6503 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6504 struct intel_crtc_state *pipe_config)
6505 {
6506 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6507 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6508 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6509 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6510
6511 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6512 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6513 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6514 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6515
6516 mode->flags = pipe_config->base.adjusted_mode.flags;
6517
6518 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6519 mode->flags |= pipe_config->base.adjusted_mode.flags;
6520 }
6521
6522 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6523 {
6524 struct drm_device *dev = intel_crtc->base.dev;
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 uint32_t pipeconf;
6527
6528 pipeconf = 0;
6529
6530 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6531 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6532 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6533
6534 if (intel_crtc->config->double_wide)
6535 pipeconf |= PIPECONF_DOUBLE_WIDE;
6536
6537 /* only g4x and later have fancy bpc/dither controls */
6538 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6539 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6540 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6541 pipeconf |= PIPECONF_DITHER_EN |
6542 PIPECONF_DITHER_TYPE_SP;
6543
6544 switch (intel_crtc->config->pipe_bpp) {
6545 case 18:
6546 pipeconf |= PIPECONF_6BPC;
6547 break;
6548 case 24:
6549 pipeconf |= PIPECONF_8BPC;
6550 break;
6551 case 30:
6552 pipeconf |= PIPECONF_10BPC;
6553 break;
6554 default:
6555 /* Case prevented by intel_choose_pipe_bpp_dither. */
6556 BUG();
6557 }
6558 }
6559
6560 if (HAS_PIPE_CXSR(dev)) {
6561 if (intel_crtc->lowfreq_avail) {
6562 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6563 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6564 } else {
6565 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6566 }
6567 }
6568
6569 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6570 if (INTEL_INFO(dev)->gen < 4 ||
6571 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6572 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6573 else
6574 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6575 } else
6576 pipeconf |= PIPECONF_PROGRESSIVE;
6577
6578 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6579 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6580
6581 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6582 POSTING_READ(PIPECONF(intel_crtc->pipe));
6583 }
6584
6585 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6586 struct intel_crtc_state *crtc_state)
6587 {
6588 struct drm_device *dev = crtc->base.dev;
6589 struct drm_i915_private *dev_priv = dev->dev_private;
6590 int refclk, num_connectors = 0;
6591 intel_clock_t clock, reduced_clock;
6592 bool ok, has_reduced_clock = false;
6593 bool is_lvds = false, is_dsi = false;
6594 struct intel_encoder *encoder;
6595 const intel_limit_t *limit;
6596
6597 for_each_intel_encoder(dev, encoder) {
6598 if (encoder->new_crtc != crtc)
6599 continue;
6600
6601 switch (encoder->type) {
6602 case INTEL_OUTPUT_LVDS:
6603 is_lvds = true;
6604 break;
6605 case INTEL_OUTPUT_DSI:
6606 is_dsi = true;
6607 break;
6608 default:
6609 break;
6610 }
6611
6612 num_connectors++;
6613 }
6614
6615 if (is_dsi)
6616 return 0;
6617
6618 if (!crtc_state->clock_set) {
6619 refclk = i9xx_get_refclk(crtc, num_connectors);
6620
6621 /*
6622 * Returns a set of divisors for the desired target clock with
6623 * the given refclk, or FALSE. The returned values represent
6624 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6625 * 2) / p1 / p2.
6626 */
6627 limit = intel_limit(crtc, refclk);
6628 ok = dev_priv->display.find_dpll(limit, crtc,
6629 crtc_state->port_clock,
6630 refclk, NULL, &clock);
6631 if (!ok) {
6632 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6633 return -EINVAL;
6634 }
6635
6636 if (is_lvds && dev_priv->lvds_downclock_avail) {
6637 /*
6638 * Ensure we match the reduced clock's P to the target
6639 * clock. If the clocks don't match, we can't switch
6640 * the display clock by using the FP0/FP1. In such case
6641 * we will disable the LVDS downclock feature.
6642 */
6643 has_reduced_clock =
6644 dev_priv->display.find_dpll(limit, crtc,
6645 dev_priv->lvds_downclock,
6646 refclk, &clock,
6647 &reduced_clock);
6648 }
6649 /* Compat-code for transition, will disappear. */
6650 crtc_state->dpll.n = clock.n;
6651 crtc_state->dpll.m1 = clock.m1;
6652 crtc_state->dpll.m2 = clock.m2;
6653 crtc_state->dpll.p1 = clock.p1;
6654 crtc_state->dpll.p2 = clock.p2;
6655 }
6656
6657 if (IS_GEN2(dev)) {
6658 i8xx_update_pll(crtc, crtc_state,
6659 has_reduced_clock ? &reduced_clock : NULL,
6660 num_connectors);
6661 } else if (IS_CHERRYVIEW(dev)) {
6662 chv_update_pll(crtc, crtc_state);
6663 } else if (IS_VALLEYVIEW(dev)) {
6664 vlv_update_pll(crtc, crtc_state);
6665 } else {
6666 i9xx_update_pll(crtc, crtc_state,
6667 has_reduced_clock ? &reduced_clock : NULL,
6668 num_connectors);
6669 }
6670
6671 return 0;
6672 }
6673
6674 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6675 struct intel_crtc_state *pipe_config)
6676 {
6677 struct drm_device *dev = crtc->base.dev;
6678 struct drm_i915_private *dev_priv = dev->dev_private;
6679 uint32_t tmp;
6680
6681 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6682 return;
6683
6684 tmp = I915_READ(PFIT_CONTROL);
6685 if (!(tmp & PFIT_ENABLE))
6686 return;
6687
6688 /* Check whether the pfit is attached to our pipe. */
6689 if (INTEL_INFO(dev)->gen < 4) {
6690 if (crtc->pipe != PIPE_B)
6691 return;
6692 } else {
6693 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6694 return;
6695 }
6696
6697 pipe_config->gmch_pfit.control = tmp;
6698 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6699 if (INTEL_INFO(dev)->gen < 5)
6700 pipe_config->gmch_pfit.lvds_border_bits =
6701 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6702 }
6703
6704 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6705 struct intel_crtc_state *pipe_config)
6706 {
6707 struct drm_device *dev = crtc->base.dev;
6708 struct drm_i915_private *dev_priv = dev->dev_private;
6709 int pipe = pipe_config->cpu_transcoder;
6710 intel_clock_t clock;
6711 u32 mdiv;
6712 int refclk = 100000;
6713
6714 /* In case of MIPI DPLL will not even be used */
6715 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6716 return;
6717
6718 mutex_lock(&dev_priv->dpio_lock);
6719 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6720 mutex_unlock(&dev_priv->dpio_lock);
6721
6722 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6723 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6724 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6725 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6726 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6727
6728 vlv_clock(refclk, &clock);
6729
6730 /* clock.dot is the fast clock */
6731 pipe_config->port_clock = clock.dot / 5;
6732 }
6733
6734 static void
6735 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6736 struct intel_initial_plane_config *plane_config)
6737 {
6738 struct drm_device *dev = crtc->base.dev;
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740 u32 val, base, offset;
6741 int pipe = crtc->pipe, plane = crtc->plane;
6742 int fourcc, pixel_format;
6743 int aligned_height;
6744 struct drm_framebuffer *fb;
6745 struct intel_framebuffer *intel_fb;
6746
6747 val = I915_READ(DSPCNTR(plane));
6748 if (!(val & DISPLAY_PLANE_ENABLE))
6749 return;
6750
6751 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6752 if (!intel_fb) {
6753 DRM_DEBUG_KMS("failed to alloc fb\n");
6754 return;
6755 }
6756
6757 fb = &intel_fb->base;
6758
6759 if (INTEL_INFO(dev)->gen >= 4) {
6760 if (val & DISPPLANE_TILED) {
6761 plane_config->tiling = I915_TILING_X;
6762 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6763 }
6764 }
6765
6766 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6767 fourcc = i9xx_format_to_fourcc(pixel_format);
6768 fb->pixel_format = fourcc;
6769 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6770
6771 if (INTEL_INFO(dev)->gen >= 4) {
6772 if (plane_config->tiling)
6773 offset = I915_READ(DSPTILEOFF(plane));
6774 else
6775 offset = I915_READ(DSPLINOFF(plane));
6776 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6777 } else {
6778 base = I915_READ(DSPADDR(plane));
6779 }
6780 plane_config->base = base;
6781
6782 val = I915_READ(PIPESRC(pipe));
6783 fb->width = ((val >> 16) & 0xfff) + 1;
6784 fb->height = ((val >> 0) & 0xfff) + 1;
6785
6786 val = I915_READ(DSPSTRIDE(pipe));
6787 fb->pitches[0] = val & 0xffffffc0;
6788
6789 aligned_height = intel_fb_align_height(dev, fb->height,
6790 fb->pixel_format,
6791 fb->modifier[0]);
6792
6793 plane_config->size = fb->pitches[0] * aligned_height;
6794
6795 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6796 pipe_name(pipe), plane, fb->width, fb->height,
6797 fb->bits_per_pixel, base, fb->pitches[0],
6798 plane_config->size);
6799
6800 plane_config->fb = intel_fb;
6801 }
6802
6803 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6804 struct intel_crtc_state *pipe_config)
6805 {
6806 struct drm_device *dev = crtc->base.dev;
6807 struct drm_i915_private *dev_priv = dev->dev_private;
6808 int pipe = pipe_config->cpu_transcoder;
6809 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6810 intel_clock_t clock;
6811 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6812 int refclk = 100000;
6813
6814 mutex_lock(&dev_priv->dpio_lock);
6815 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6816 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6817 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6818 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6819 mutex_unlock(&dev_priv->dpio_lock);
6820
6821 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6822 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6823 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6824 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6825 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6826
6827 chv_clock(refclk, &clock);
6828
6829 /* clock.dot is the fast clock */
6830 pipe_config->port_clock = clock.dot / 5;
6831 }
6832
6833 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6834 struct intel_crtc_state *pipe_config)
6835 {
6836 struct drm_device *dev = crtc->base.dev;
6837 struct drm_i915_private *dev_priv = dev->dev_private;
6838 uint32_t tmp;
6839
6840 if (!intel_display_power_is_enabled(dev_priv,
6841 POWER_DOMAIN_PIPE(crtc->pipe)))
6842 return false;
6843
6844 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6845 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6846
6847 tmp = I915_READ(PIPECONF(crtc->pipe));
6848 if (!(tmp & PIPECONF_ENABLE))
6849 return false;
6850
6851 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6852 switch (tmp & PIPECONF_BPC_MASK) {
6853 case PIPECONF_6BPC:
6854 pipe_config->pipe_bpp = 18;
6855 break;
6856 case PIPECONF_8BPC:
6857 pipe_config->pipe_bpp = 24;
6858 break;
6859 case PIPECONF_10BPC:
6860 pipe_config->pipe_bpp = 30;
6861 break;
6862 default:
6863 break;
6864 }
6865 }
6866
6867 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6868 pipe_config->limited_color_range = true;
6869
6870 if (INTEL_INFO(dev)->gen < 4)
6871 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6872
6873 intel_get_pipe_timings(crtc, pipe_config);
6874
6875 i9xx_get_pfit_config(crtc, pipe_config);
6876
6877 if (INTEL_INFO(dev)->gen >= 4) {
6878 tmp = I915_READ(DPLL_MD(crtc->pipe));
6879 pipe_config->pixel_multiplier =
6880 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6881 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6882 pipe_config->dpll_hw_state.dpll_md = tmp;
6883 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6884 tmp = I915_READ(DPLL(crtc->pipe));
6885 pipe_config->pixel_multiplier =
6886 ((tmp & SDVO_MULTIPLIER_MASK)
6887 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6888 } else {
6889 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6890 * port and will be fixed up in the encoder->get_config
6891 * function. */
6892 pipe_config->pixel_multiplier = 1;
6893 }
6894 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6895 if (!IS_VALLEYVIEW(dev)) {
6896 /*
6897 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6898 * on 830. Filter it out here so that we don't
6899 * report errors due to that.
6900 */
6901 if (IS_I830(dev))
6902 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6903
6904 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6905 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6906 } else {
6907 /* Mask out read-only status bits. */
6908 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6909 DPLL_PORTC_READY_MASK |
6910 DPLL_PORTB_READY_MASK);
6911 }
6912
6913 if (IS_CHERRYVIEW(dev))
6914 chv_crtc_clock_get(crtc, pipe_config);
6915 else if (IS_VALLEYVIEW(dev))
6916 vlv_crtc_clock_get(crtc, pipe_config);
6917 else
6918 i9xx_crtc_clock_get(crtc, pipe_config);
6919
6920 return true;
6921 }
6922
6923 static void ironlake_init_pch_refclk(struct drm_device *dev)
6924 {
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 struct intel_encoder *encoder;
6927 u32 val, final;
6928 bool has_lvds = false;
6929 bool has_cpu_edp = false;
6930 bool has_panel = false;
6931 bool has_ck505 = false;
6932 bool can_ssc = false;
6933
6934 /* We need to take the global config into account */
6935 for_each_intel_encoder(dev, encoder) {
6936 switch (encoder->type) {
6937 case INTEL_OUTPUT_LVDS:
6938 has_panel = true;
6939 has_lvds = true;
6940 break;
6941 case INTEL_OUTPUT_EDP:
6942 has_panel = true;
6943 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6944 has_cpu_edp = true;
6945 break;
6946 default:
6947 break;
6948 }
6949 }
6950
6951 if (HAS_PCH_IBX(dev)) {
6952 has_ck505 = dev_priv->vbt.display_clock_mode;
6953 can_ssc = has_ck505;
6954 } else {
6955 has_ck505 = false;
6956 can_ssc = true;
6957 }
6958
6959 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6960 has_panel, has_lvds, has_ck505);
6961
6962 /* Ironlake: try to setup display ref clock before DPLL
6963 * enabling. This is only under driver's control after
6964 * PCH B stepping, previous chipset stepping should be
6965 * ignoring this setting.
6966 */
6967 val = I915_READ(PCH_DREF_CONTROL);
6968
6969 /* As we must carefully and slowly disable/enable each source in turn,
6970 * compute the final state we want first and check if we need to
6971 * make any changes at all.
6972 */
6973 final = val;
6974 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6975 if (has_ck505)
6976 final |= DREF_NONSPREAD_CK505_ENABLE;
6977 else
6978 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6979
6980 final &= ~DREF_SSC_SOURCE_MASK;
6981 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6982 final &= ~DREF_SSC1_ENABLE;
6983
6984 if (has_panel) {
6985 final |= DREF_SSC_SOURCE_ENABLE;
6986
6987 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6988 final |= DREF_SSC1_ENABLE;
6989
6990 if (has_cpu_edp) {
6991 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6992 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6993 else
6994 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6995 } else
6996 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6997 } else {
6998 final |= DREF_SSC_SOURCE_DISABLE;
6999 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7000 }
7001
7002 if (final == val)
7003 return;
7004
7005 /* Always enable nonspread source */
7006 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7007
7008 if (has_ck505)
7009 val |= DREF_NONSPREAD_CK505_ENABLE;
7010 else
7011 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7012
7013 if (has_panel) {
7014 val &= ~DREF_SSC_SOURCE_MASK;
7015 val |= DREF_SSC_SOURCE_ENABLE;
7016
7017 /* SSC must be turned on before enabling the CPU output */
7018 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7019 DRM_DEBUG_KMS("Using SSC on panel\n");
7020 val |= DREF_SSC1_ENABLE;
7021 } else
7022 val &= ~DREF_SSC1_ENABLE;
7023
7024 /* Get SSC going before enabling the outputs */
7025 I915_WRITE(PCH_DREF_CONTROL, val);
7026 POSTING_READ(PCH_DREF_CONTROL);
7027 udelay(200);
7028
7029 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7030
7031 /* Enable CPU source on CPU attached eDP */
7032 if (has_cpu_edp) {
7033 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7034 DRM_DEBUG_KMS("Using SSC on eDP\n");
7035 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7036 } else
7037 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7038 } else
7039 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7040
7041 I915_WRITE(PCH_DREF_CONTROL, val);
7042 POSTING_READ(PCH_DREF_CONTROL);
7043 udelay(200);
7044 } else {
7045 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7046
7047 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7048
7049 /* Turn off CPU output */
7050 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7051
7052 I915_WRITE(PCH_DREF_CONTROL, val);
7053 POSTING_READ(PCH_DREF_CONTROL);
7054 udelay(200);
7055
7056 /* Turn off the SSC source */
7057 val &= ~DREF_SSC_SOURCE_MASK;
7058 val |= DREF_SSC_SOURCE_DISABLE;
7059
7060 /* Turn off SSC1 */
7061 val &= ~DREF_SSC1_ENABLE;
7062
7063 I915_WRITE(PCH_DREF_CONTROL, val);
7064 POSTING_READ(PCH_DREF_CONTROL);
7065 udelay(200);
7066 }
7067
7068 BUG_ON(val != final);
7069 }
7070
7071 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7072 {
7073 uint32_t tmp;
7074
7075 tmp = I915_READ(SOUTH_CHICKEN2);
7076 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7077 I915_WRITE(SOUTH_CHICKEN2, tmp);
7078
7079 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7080 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7081 DRM_ERROR("FDI mPHY reset assert timeout\n");
7082
7083 tmp = I915_READ(SOUTH_CHICKEN2);
7084 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7085 I915_WRITE(SOUTH_CHICKEN2, tmp);
7086
7087 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7088 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7089 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7090 }
7091
7092 /* WaMPhyProgramming:hsw */
7093 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7094 {
7095 uint32_t tmp;
7096
7097 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7098 tmp &= ~(0xFF << 24);
7099 tmp |= (0x12 << 24);
7100 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7101
7102 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7103 tmp |= (1 << 11);
7104 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7105
7106 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7107 tmp |= (1 << 11);
7108 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7109
7110 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7111 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7112 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7113
7114 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7115 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7116 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7117
7118 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7119 tmp &= ~(7 << 13);
7120 tmp |= (5 << 13);
7121 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7122
7123 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7124 tmp &= ~(7 << 13);
7125 tmp |= (5 << 13);
7126 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7127
7128 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7129 tmp &= ~0xFF;
7130 tmp |= 0x1C;
7131 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7132
7133 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7134 tmp &= ~0xFF;
7135 tmp |= 0x1C;
7136 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7137
7138 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7139 tmp &= ~(0xFF << 16);
7140 tmp |= (0x1C << 16);
7141 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7142
7143 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7144 tmp &= ~(0xFF << 16);
7145 tmp |= (0x1C << 16);
7146 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7147
7148 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7149 tmp |= (1 << 27);
7150 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7151
7152 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7153 tmp |= (1 << 27);
7154 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7155
7156 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7157 tmp &= ~(0xF << 28);
7158 tmp |= (4 << 28);
7159 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7160
7161 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7162 tmp &= ~(0xF << 28);
7163 tmp |= (4 << 28);
7164 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7165 }
7166
7167 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7168 * Programming" based on the parameters passed:
7169 * - Sequence to enable CLKOUT_DP
7170 * - Sequence to enable CLKOUT_DP without spread
7171 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7172 */
7173 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7174 bool with_fdi)
7175 {
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177 uint32_t reg, tmp;
7178
7179 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7180 with_spread = true;
7181 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7182 with_fdi, "LP PCH doesn't have FDI\n"))
7183 with_fdi = false;
7184
7185 mutex_lock(&dev_priv->dpio_lock);
7186
7187 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7188 tmp &= ~SBI_SSCCTL_DISABLE;
7189 tmp |= SBI_SSCCTL_PATHALT;
7190 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7191
7192 udelay(24);
7193
7194 if (with_spread) {
7195 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7196 tmp &= ~SBI_SSCCTL_PATHALT;
7197 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7198
7199 if (with_fdi) {
7200 lpt_reset_fdi_mphy(dev_priv);
7201 lpt_program_fdi_mphy(dev_priv);
7202 }
7203 }
7204
7205 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7206 SBI_GEN0 : SBI_DBUFF0;
7207 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7208 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7209 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7210
7211 mutex_unlock(&dev_priv->dpio_lock);
7212 }
7213
7214 /* Sequence to disable CLKOUT_DP */
7215 static void lpt_disable_clkout_dp(struct drm_device *dev)
7216 {
7217 struct drm_i915_private *dev_priv = dev->dev_private;
7218 uint32_t reg, tmp;
7219
7220 mutex_lock(&dev_priv->dpio_lock);
7221
7222 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7223 SBI_GEN0 : SBI_DBUFF0;
7224 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7225 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7226 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7227
7228 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7229 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7230 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7231 tmp |= SBI_SSCCTL_PATHALT;
7232 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7233 udelay(32);
7234 }
7235 tmp |= SBI_SSCCTL_DISABLE;
7236 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7237 }
7238
7239 mutex_unlock(&dev_priv->dpio_lock);
7240 }
7241
7242 static void lpt_init_pch_refclk(struct drm_device *dev)
7243 {
7244 struct intel_encoder *encoder;
7245 bool has_vga = false;
7246
7247 for_each_intel_encoder(dev, encoder) {
7248 switch (encoder->type) {
7249 case INTEL_OUTPUT_ANALOG:
7250 has_vga = true;
7251 break;
7252 default:
7253 break;
7254 }
7255 }
7256
7257 if (has_vga)
7258 lpt_enable_clkout_dp(dev, true, true);
7259 else
7260 lpt_disable_clkout_dp(dev);
7261 }
7262
7263 /*
7264 * Initialize reference clocks when the driver loads
7265 */
7266 void intel_init_pch_refclk(struct drm_device *dev)
7267 {
7268 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7269 ironlake_init_pch_refclk(dev);
7270 else if (HAS_PCH_LPT(dev))
7271 lpt_init_pch_refclk(dev);
7272 }
7273
7274 static int ironlake_get_refclk(struct drm_crtc *crtc)
7275 {
7276 struct drm_device *dev = crtc->dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 struct intel_encoder *encoder;
7279 int num_connectors = 0;
7280 bool is_lvds = false;
7281
7282 for_each_intel_encoder(dev, encoder) {
7283 if (encoder->new_crtc != to_intel_crtc(crtc))
7284 continue;
7285
7286 switch (encoder->type) {
7287 case INTEL_OUTPUT_LVDS:
7288 is_lvds = true;
7289 break;
7290 default:
7291 break;
7292 }
7293 num_connectors++;
7294 }
7295
7296 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7297 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7298 dev_priv->vbt.lvds_ssc_freq);
7299 return dev_priv->vbt.lvds_ssc_freq;
7300 }
7301
7302 return 120000;
7303 }
7304
7305 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7306 {
7307 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309 int pipe = intel_crtc->pipe;
7310 uint32_t val;
7311
7312 val = 0;
7313
7314 switch (intel_crtc->config->pipe_bpp) {
7315 case 18:
7316 val |= PIPECONF_6BPC;
7317 break;
7318 case 24:
7319 val |= PIPECONF_8BPC;
7320 break;
7321 case 30:
7322 val |= PIPECONF_10BPC;
7323 break;
7324 case 36:
7325 val |= PIPECONF_12BPC;
7326 break;
7327 default:
7328 /* Case prevented by intel_choose_pipe_bpp_dither. */
7329 BUG();
7330 }
7331
7332 if (intel_crtc->config->dither)
7333 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7334
7335 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7336 val |= PIPECONF_INTERLACED_ILK;
7337 else
7338 val |= PIPECONF_PROGRESSIVE;
7339
7340 if (intel_crtc->config->limited_color_range)
7341 val |= PIPECONF_COLOR_RANGE_SELECT;
7342
7343 I915_WRITE(PIPECONF(pipe), val);
7344 POSTING_READ(PIPECONF(pipe));
7345 }
7346
7347 /*
7348 * Set up the pipe CSC unit.
7349 *
7350 * Currently only full range RGB to limited range RGB conversion
7351 * is supported, but eventually this should handle various
7352 * RGB<->YCbCr scenarios as well.
7353 */
7354 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7355 {
7356 struct drm_device *dev = crtc->dev;
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359 int pipe = intel_crtc->pipe;
7360 uint16_t coeff = 0x7800; /* 1.0 */
7361
7362 /*
7363 * TODO: Check what kind of values actually come out of the pipe
7364 * with these coeff/postoff values and adjust to get the best
7365 * accuracy. Perhaps we even need to take the bpc value into
7366 * consideration.
7367 */
7368
7369 if (intel_crtc->config->limited_color_range)
7370 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7371
7372 /*
7373 * GY/GU and RY/RU should be the other way around according
7374 * to BSpec, but reality doesn't agree. Just set them up in
7375 * a way that results in the correct picture.
7376 */
7377 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7378 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7379
7380 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7381 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7382
7383 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7384 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7385
7386 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7387 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7388 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7389
7390 if (INTEL_INFO(dev)->gen > 6) {
7391 uint16_t postoff = 0;
7392
7393 if (intel_crtc->config->limited_color_range)
7394 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7395
7396 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7397 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7398 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7399
7400 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7401 } else {
7402 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7403
7404 if (intel_crtc->config->limited_color_range)
7405 mode |= CSC_BLACK_SCREEN_OFFSET;
7406
7407 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7408 }
7409 }
7410
7411 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7412 {
7413 struct drm_device *dev = crtc->dev;
7414 struct drm_i915_private *dev_priv = dev->dev_private;
7415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416 enum pipe pipe = intel_crtc->pipe;
7417 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7418 uint32_t val;
7419
7420 val = 0;
7421
7422 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7423 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7424
7425 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7426 val |= PIPECONF_INTERLACED_ILK;
7427 else
7428 val |= PIPECONF_PROGRESSIVE;
7429
7430 I915_WRITE(PIPECONF(cpu_transcoder), val);
7431 POSTING_READ(PIPECONF(cpu_transcoder));
7432
7433 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7434 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7435
7436 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7437 val = 0;
7438
7439 switch (intel_crtc->config->pipe_bpp) {
7440 case 18:
7441 val |= PIPEMISC_DITHER_6_BPC;
7442 break;
7443 case 24:
7444 val |= PIPEMISC_DITHER_8_BPC;
7445 break;
7446 case 30:
7447 val |= PIPEMISC_DITHER_10_BPC;
7448 break;
7449 case 36:
7450 val |= PIPEMISC_DITHER_12_BPC;
7451 break;
7452 default:
7453 /* Case prevented by pipe_config_set_bpp. */
7454 BUG();
7455 }
7456
7457 if (intel_crtc->config->dither)
7458 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7459
7460 I915_WRITE(PIPEMISC(pipe), val);
7461 }
7462 }
7463
7464 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7465 struct intel_crtc_state *crtc_state,
7466 intel_clock_t *clock,
7467 bool *has_reduced_clock,
7468 intel_clock_t *reduced_clock)
7469 {
7470 struct drm_device *dev = crtc->dev;
7471 struct drm_i915_private *dev_priv = dev->dev_private;
7472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7473 int refclk;
7474 const intel_limit_t *limit;
7475 bool ret, is_lvds = false;
7476
7477 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7478
7479 refclk = ironlake_get_refclk(crtc);
7480
7481 /*
7482 * Returns a set of divisors for the desired target clock with the given
7483 * refclk, or FALSE. The returned values represent the clock equation:
7484 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7485 */
7486 limit = intel_limit(intel_crtc, refclk);
7487 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7488 crtc_state->port_clock,
7489 refclk, NULL, clock);
7490 if (!ret)
7491 return false;
7492
7493 if (is_lvds && dev_priv->lvds_downclock_avail) {
7494 /*
7495 * Ensure we match the reduced clock's P to the target clock.
7496 * If the clocks don't match, we can't switch the display clock
7497 * by using the FP0/FP1. In such case we will disable the LVDS
7498 * downclock feature.
7499 */
7500 *has_reduced_clock =
7501 dev_priv->display.find_dpll(limit, intel_crtc,
7502 dev_priv->lvds_downclock,
7503 refclk, clock,
7504 reduced_clock);
7505 }
7506
7507 return true;
7508 }
7509
7510 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7511 {
7512 /*
7513 * Account for spread spectrum to avoid
7514 * oversubscribing the link. Max center spread
7515 * is 2.5%; use 5% for safety's sake.
7516 */
7517 u32 bps = target_clock * bpp * 21 / 20;
7518 return DIV_ROUND_UP(bps, link_bw * 8);
7519 }
7520
7521 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7522 {
7523 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7524 }
7525
7526 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7527 struct intel_crtc_state *crtc_state,
7528 u32 *fp,
7529 intel_clock_t *reduced_clock, u32 *fp2)
7530 {
7531 struct drm_crtc *crtc = &intel_crtc->base;
7532 struct drm_device *dev = crtc->dev;
7533 struct drm_i915_private *dev_priv = dev->dev_private;
7534 struct intel_encoder *intel_encoder;
7535 uint32_t dpll;
7536 int factor, num_connectors = 0;
7537 bool is_lvds = false, is_sdvo = false;
7538
7539 for_each_intel_encoder(dev, intel_encoder) {
7540 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7541 continue;
7542
7543 switch (intel_encoder->type) {
7544 case INTEL_OUTPUT_LVDS:
7545 is_lvds = true;
7546 break;
7547 case INTEL_OUTPUT_SDVO:
7548 case INTEL_OUTPUT_HDMI:
7549 is_sdvo = true;
7550 break;
7551 default:
7552 break;
7553 }
7554
7555 num_connectors++;
7556 }
7557
7558 /* Enable autotuning of the PLL clock (if permissible) */
7559 factor = 21;
7560 if (is_lvds) {
7561 if ((intel_panel_use_ssc(dev_priv) &&
7562 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7563 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7564 factor = 25;
7565 } else if (crtc_state->sdvo_tv_clock)
7566 factor = 20;
7567
7568 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7569 *fp |= FP_CB_TUNE;
7570
7571 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7572 *fp2 |= FP_CB_TUNE;
7573
7574 dpll = 0;
7575
7576 if (is_lvds)
7577 dpll |= DPLLB_MODE_LVDS;
7578 else
7579 dpll |= DPLLB_MODE_DAC_SERIAL;
7580
7581 dpll |= (crtc_state->pixel_multiplier - 1)
7582 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7583
7584 if (is_sdvo)
7585 dpll |= DPLL_SDVO_HIGH_SPEED;
7586 if (crtc_state->has_dp_encoder)
7587 dpll |= DPLL_SDVO_HIGH_SPEED;
7588
7589 /* compute bitmask from p1 value */
7590 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7591 /* also FPA1 */
7592 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7593
7594 switch (crtc_state->dpll.p2) {
7595 case 5:
7596 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7597 break;
7598 case 7:
7599 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7600 break;
7601 case 10:
7602 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7603 break;
7604 case 14:
7605 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7606 break;
7607 }
7608
7609 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7611 else
7612 dpll |= PLL_REF_INPUT_DREFCLK;
7613
7614 return dpll | DPLL_VCO_ENABLE;
7615 }
7616
7617 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7618 struct intel_crtc_state *crtc_state)
7619 {
7620 struct drm_device *dev = crtc->base.dev;
7621 intel_clock_t clock, reduced_clock;
7622 u32 dpll = 0, fp = 0, fp2 = 0;
7623 bool ok, has_reduced_clock = false;
7624 bool is_lvds = false;
7625 struct intel_shared_dpll *pll;
7626
7627 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7628
7629 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7630 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7631
7632 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7633 &has_reduced_clock, &reduced_clock);
7634 if (!ok && !crtc_state->clock_set) {
7635 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7636 return -EINVAL;
7637 }
7638 /* Compat-code for transition, will disappear. */
7639 if (!crtc_state->clock_set) {
7640 crtc_state->dpll.n = clock.n;
7641 crtc_state->dpll.m1 = clock.m1;
7642 crtc_state->dpll.m2 = clock.m2;
7643 crtc_state->dpll.p1 = clock.p1;
7644 crtc_state->dpll.p2 = clock.p2;
7645 }
7646
7647 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7648 if (crtc_state->has_pch_encoder) {
7649 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7650 if (has_reduced_clock)
7651 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7652
7653 dpll = ironlake_compute_dpll(crtc, crtc_state,
7654 &fp, &reduced_clock,
7655 has_reduced_clock ? &fp2 : NULL);
7656
7657 crtc_state->dpll_hw_state.dpll = dpll;
7658 crtc_state->dpll_hw_state.fp0 = fp;
7659 if (has_reduced_clock)
7660 crtc_state->dpll_hw_state.fp1 = fp2;
7661 else
7662 crtc_state->dpll_hw_state.fp1 = fp;
7663
7664 pll = intel_get_shared_dpll(crtc, crtc_state);
7665 if (pll == NULL) {
7666 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7667 pipe_name(crtc->pipe));
7668 return -EINVAL;
7669 }
7670 }
7671
7672 if (is_lvds && has_reduced_clock && i915.powersave)
7673 crtc->lowfreq_avail = true;
7674 else
7675 crtc->lowfreq_avail = false;
7676
7677 return 0;
7678 }
7679
7680 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7681 struct intel_link_m_n *m_n)
7682 {
7683 struct drm_device *dev = crtc->base.dev;
7684 struct drm_i915_private *dev_priv = dev->dev_private;
7685 enum pipe pipe = crtc->pipe;
7686
7687 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7688 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7689 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7690 & ~TU_SIZE_MASK;
7691 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7692 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7693 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7694 }
7695
7696 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7697 enum transcoder transcoder,
7698 struct intel_link_m_n *m_n,
7699 struct intel_link_m_n *m2_n2)
7700 {
7701 struct drm_device *dev = crtc->base.dev;
7702 struct drm_i915_private *dev_priv = dev->dev_private;
7703 enum pipe pipe = crtc->pipe;
7704
7705 if (INTEL_INFO(dev)->gen >= 5) {
7706 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7707 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7708 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7709 & ~TU_SIZE_MASK;
7710 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7711 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7712 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7713 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7714 * gen < 8) and if DRRS is supported (to make sure the
7715 * registers are not unnecessarily read).
7716 */
7717 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7718 crtc->config->has_drrs) {
7719 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7720 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7721 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7722 & ~TU_SIZE_MASK;
7723 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7724 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7725 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7726 }
7727 } else {
7728 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7729 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7730 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7731 & ~TU_SIZE_MASK;
7732 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7733 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7734 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7735 }
7736 }
7737
7738 void intel_dp_get_m_n(struct intel_crtc *crtc,
7739 struct intel_crtc_state *pipe_config)
7740 {
7741 if (pipe_config->has_pch_encoder)
7742 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7743 else
7744 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7745 &pipe_config->dp_m_n,
7746 &pipe_config->dp_m2_n2);
7747 }
7748
7749 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7750 struct intel_crtc_state *pipe_config)
7751 {
7752 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7753 &pipe_config->fdi_m_n, NULL);
7754 }
7755
7756 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7757 struct intel_crtc_state *pipe_config)
7758 {
7759 struct drm_device *dev = crtc->base.dev;
7760 struct drm_i915_private *dev_priv = dev->dev_private;
7761 uint32_t tmp;
7762
7763 tmp = I915_READ(PS_CTL(crtc->pipe));
7764
7765 if (tmp & PS_ENABLE) {
7766 pipe_config->pch_pfit.enabled = true;
7767 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7768 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7769 }
7770 }
7771
7772 static void
7773 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7774 struct intel_initial_plane_config *plane_config)
7775 {
7776 struct drm_device *dev = crtc->base.dev;
7777 struct drm_i915_private *dev_priv = dev->dev_private;
7778 u32 val, base, offset, stride_mult, tiling;
7779 int pipe = crtc->pipe;
7780 int fourcc, pixel_format;
7781 int aligned_height;
7782 struct drm_framebuffer *fb;
7783 struct intel_framebuffer *intel_fb;
7784
7785 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7786 if (!intel_fb) {
7787 DRM_DEBUG_KMS("failed to alloc fb\n");
7788 return;
7789 }
7790
7791 fb = &intel_fb->base;
7792
7793 val = I915_READ(PLANE_CTL(pipe, 0));
7794 if (!(val & PLANE_CTL_ENABLE))
7795 goto error;
7796
7797 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7798 fourcc = skl_format_to_fourcc(pixel_format,
7799 val & PLANE_CTL_ORDER_RGBX,
7800 val & PLANE_CTL_ALPHA_MASK);
7801 fb->pixel_format = fourcc;
7802 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7803
7804 tiling = val & PLANE_CTL_TILED_MASK;
7805 switch (tiling) {
7806 case PLANE_CTL_TILED_LINEAR:
7807 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7808 break;
7809 case PLANE_CTL_TILED_X:
7810 plane_config->tiling = I915_TILING_X;
7811 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7812 break;
7813 case PLANE_CTL_TILED_Y:
7814 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7815 break;
7816 case PLANE_CTL_TILED_YF:
7817 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7818 break;
7819 default:
7820 MISSING_CASE(tiling);
7821 goto error;
7822 }
7823
7824 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7825 plane_config->base = base;
7826
7827 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7828
7829 val = I915_READ(PLANE_SIZE(pipe, 0));
7830 fb->height = ((val >> 16) & 0xfff) + 1;
7831 fb->width = ((val >> 0) & 0x1fff) + 1;
7832
7833 val = I915_READ(PLANE_STRIDE(pipe, 0));
7834 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7835 fb->pixel_format);
7836 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7837
7838 aligned_height = intel_fb_align_height(dev, fb->height,
7839 fb->pixel_format,
7840 fb->modifier[0]);
7841
7842 plane_config->size = fb->pitches[0] * aligned_height;
7843
7844 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7845 pipe_name(pipe), fb->width, fb->height,
7846 fb->bits_per_pixel, base, fb->pitches[0],
7847 plane_config->size);
7848
7849 plane_config->fb = intel_fb;
7850 return;
7851
7852 error:
7853 kfree(fb);
7854 }
7855
7856 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7857 struct intel_crtc_state *pipe_config)
7858 {
7859 struct drm_device *dev = crtc->base.dev;
7860 struct drm_i915_private *dev_priv = dev->dev_private;
7861 uint32_t tmp;
7862
7863 tmp = I915_READ(PF_CTL(crtc->pipe));
7864
7865 if (tmp & PF_ENABLE) {
7866 pipe_config->pch_pfit.enabled = true;
7867 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7868 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7869
7870 /* We currently do not free assignements of panel fitters on
7871 * ivb/hsw (since we don't use the higher upscaling modes which
7872 * differentiates them) so just WARN about this case for now. */
7873 if (IS_GEN7(dev)) {
7874 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7875 PF_PIPE_SEL_IVB(crtc->pipe));
7876 }
7877 }
7878 }
7879
7880 static void
7881 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7882 struct intel_initial_plane_config *plane_config)
7883 {
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 u32 val, base, offset;
7887 int pipe = crtc->pipe;
7888 int fourcc, pixel_format;
7889 int aligned_height;
7890 struct drm_framebuffer *fb;
7891 struct intel_framebuffer *intel_fb;
7892
7893 val = I915_READ(DSPCNTR(pipe));
7894 if (!(val & DISPLAY_PLANE_ENABLE))
7895 return;
7896
7897 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7898 if (!intel_fb) {
7899 DRM_DEBUG_KMS("failed to alloc fb\n");
7900 return;
7901 }
7902
7903 fb = &intel_fb->base;
7904
7905 if (INTEL_INFO(dev)->gen >= 4) {
7906 if (val & DISPPLANE_TILED) {
7907 plane_config->tiling = I915_TILING_X;
7908 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7909 }
7910 }
7911
7912 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7913 fourcc = i9xx_format_to_fourcc(pixel_format);
7914 fb->pixel_format = fourcc;
7915 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7916
7917 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7918 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7919 offset = I915_READ(DSPOFFSET(pipe));
7920 } else {
7921 if (plane_config->tiling)
7922 offset = I915_READ(DSPTILEOFF(pipe));
7923 else
7924 offset = I915_READ(DSPLINOFF(pipe));
7925 }
7926 plane_config->base = base;
7927
7928 val = I915_READ(PIPESRC(pipe));
7929 fb->width = ((val >> 16) & 0xfff) + 1;
7930 fb->height = ((val >> 0) & 0xfff) + 1;
7931
7932 val = I915_READ(DSPSTRIDE(pipe));
7933 fb->pitches[0] = val & 0xffffffc0;
7934
7935 aligned_height = intel_fb_align_height(dev, fb->height,
7936 fb->pixel_format,
7937 fb->modifier[0]);
7938
7939 plane_config->size = fb->pitches[0] * aligned_height;
7940
7941 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7942 pipe_name(pipe), fb->width, fb->height,
7943 fb->bits_per_pixel, base, fb->pitches[0],
7944 plane_config->size);
7945
7946 plane_config->fb = intel_fb;
7947 }
7948
7949 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7950 struct intel_crtc_state *pipe_config)
7951 {
7952 struct drm_device *dev = crtc->base.dev;
7953 struct drm_i915_private *dev_priv = dev->dev_private;
7954 uint32_t tmp;
7955
7956 if (!intel_display_power_is_enabled(dev_priv,
7957 POWER_DOMAIN_PIPE(crtc->pipe)))
7958 return false;
7959
7960 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7961 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7962
7963 tmp = I915_READ(PIPECONF(crtc->pipe));
7964 if (!(tmp & PIPECONF_ENABLE))
7965 return false;
7966
7967 switch (tmp & PIPECONF_BPC_MASK) {
7968 case PIPECONF_6BPC:
7969 pipe_config->pipe_bpp = 18;
7970 break;
7971 case PIPECONF_8BPC:
7972 pipe_config->pipe_bpp = 24;
7973 break;
7974 case PIPECONF_10BPC:
7975 pipe_config->pipe_bpp = 30;
7976 break;
7977 case PIPECONF_12BPC:
7978 pipe_config->pipe_bpp = 36;
7979 break;
7980 default:
7981 break;
7982 }
7983
7984 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7985 pipe_config->limited_color_range = true;
7986
7987 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7988 struct intel_shared_dpll *pll;
7989
7990 pipe_config->has_pch_encoder = true;
7991
7992 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7993 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7994 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7995
7996 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7997
7998 if (HAS_PCH_IBX(dev_priv->dev)) {
7999 pipe_config->shared_dpll =
8000 (enum intel_dpll_id) crtc->pipe;
8001 } else {
8002 tmp = I915_READ(PCH_DPLL_SEL);
8003 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8004 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8005 else
8006 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8007 }
8008
8009 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8010
8011 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8012 &pipe_config->dpll_hw_state));
8013
8014 tmp = pipe_config->dpll_hw_state.dpll;
8015 pipe_config->pixel_multiplier =
8016 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8017 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8018
8019 ironlake_pch_clock_get(crtc, pipe_config);
8020 } else {
8021 pipe_config->pixel_multiplier = 1;
8022 }
8023
8024 intel_get_pipe_timings(crtc, pipe_config);
8025
8026 ironlake_get_pfit_config(crtc, pipe_config);
8027
8028 return true;
8029 }
8030
8031 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8032 {
8033 struct drm_device *dev = dev_priv->dev;
8034 struct intel_crtc *crtc;
8035
8036 for_each_intel_crtc(dev, crtc)
8037 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8038 pipe_name(crtc->pipe));
8039
8040 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8041 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8042 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8043 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8044 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8045 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8046 "CPU PWM1 enabled\n");
8047 if (IS_HASWELL(dev))
8048 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8049 "CPU PWM2 enabled\n");
8050 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8051 "PCH PWM1 enabled\n");
8052 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8053 "Utility pin enabled\n");
8054 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8055
8056 /*
8057 * In theory we can still leave IRQs enabled, as long as only the HPD
8058 * interrupts remain enabled. We used to check for that, but since it's
8059 * gen-specific and since we only disable LCPLL after we fully disable
8060 * the interrupts, the check below should be enough.
8061 */
8062 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8063 }
8064
8065 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8066 {
8067 struct drm_device *dev = dev_priv->dev;
8068
8069 if (IS_HASWELL(dev))
8070 return I915_READ(D_COMP_HSW);
8071 else
8072 return I915_READ(D_COMP_BDW);
8073 }
8074
8075 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8076 {
8077 struct drm_device *dev = dev_priv->dev;
8078
8079 if (IS_HASWELL(dev)) {
8080 mutex_lock(&dev_priv->rps.hw_lock);
8081 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8082 val))
8083 DRM_ERROR("Failed to write to D_COMP\n");
8084 mutex_unlock(&dev_priv->rps.hw_lock);
8085 } else {
8086 I915_WRITE(D_COMP_BDW, val);
8087 POSTING_READ(D_COMP_BDW);
8088 }
8089 }
8090
8091 /*
8092 * This function implements pieces of two sequences from BSpec:
8093 * - Sequence for display software to disable LCPLL
8094 * - Sequence for display software to allow package C8+
8095 * The steps implemented here are just the steps that actually touch the LCPLL
8096 * register. Callers should take care of disabling all the display engine
8097 * functions, doing the mode unset, fixing interrupts, etc.
8098 */
8099 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8100 bool switch_to_fclk, bool allow_power_down)
8101 {
8102 uint32_t val;
8103
8104 assert_can_disable_lcpll(dev_priv);
8105
8106 val = I915_READ(LCPLL_CTL);
8107
8108 if (switch_to_fclk) {
8109 val |= LCPLL_CD_SOURCE_FCLK;
8110 I915_WRITE(LCPLL_CTL, val);
8111
8112 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8113 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8114 DRM_ERROR("Switching to FCLK failed\n");
8115
8116 val = I915_READ(LCPLL_CTL);
8117 }
8118
8119 val |= LCPLL_PLL_DISABLE;
8120 I915_WRITE(LCPLL_CTL, val);
8121 POSTING_READ(LCPLL_CTL);
8122
8123 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8124 DRM_ERROR("LCPLL still locked\n");
8125
8126 val = hsw_read_dcomp(dev_priv);
8127 val |= D_COMP_COMP_DISABLE;
8128 hsw_write_dcomp(dev_priv, val);
8129 ndelay(100);
8130
8131 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8132 1))
8133 DRM_ERROR("D_COMP RCOMP still in progress\n");
8134
8135 if (allow_power_down) {
8136 val = I915_READ(LCPLL_CTL);
8137 val |= LCPLL_POWER_DOWN_ALLOW;
8138 I915_WRITE(LCPLL_CTL, val);
8139 POSTING_READ(LCPLL_CTL);
8140 }
8141 }
8142
8143 /*
8144 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8145 * source.
8146 */
8147 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8148 {
8149 uint32_t val;
8150
8151 val = I915_READ(LCPLL_CTL);
8152
8153 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8154 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8155 return;
8156
8157 /*
8158 * Make sure we're not on PC8 state before disabling PC8, otherwise
8159 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8160 */
8161 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8162
8163 if (val & LCPLL_POWER_DOWN_ALLOW) {
8164 val &= ~LCPLL_POWER_DOWN_ALLOW;
8165 I915_WRITE(LCPLL_CTL, val);
8166 POSTING_READ(LCPLL_CTL);
8167 }
8168
8169 val = hsw_read_dcomp(dev_priv);
8170 val |= D_COMP_COMP_FORCE;
8171 val &= ~D_COMP_COMP_DISABLE;
8172 hsw_write_dcomp(dev_priv, val);
8173
8174 val = I915_READ(LCPLL_CTL);
8175 val &= ~LCPLL_PLL_DISABLE;
8176 I915_WRITE(LCPLL_CTL, val);
8177
8178 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8179 DRM_ERROR("LCPLL not locked yet\n");
8180
8181 if (val & LCPLL_CD_SOURCE_FCLK) {
8182 val = I915_READ(LCPLL_CTL);
8183 val &= ~LCPLL_CD_SOURCE_FCLK;
8184 I915_WRITE(LCPLL_CTL, val);
8185
8186 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8187 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8188 DRM_ERROR("Switching back to LCPLL failed\n");
8189 }
8190
8191 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8192 }
8193
8194 /*
8195 * Package states C8 and deeper are really deep PC states that can only be
8196 * reached when all the devices on the system allow it, so even if the graphics
8197 * device allows PC8+, it doesn't mean the system will actually get to these
8198 * states. Our driver only allows PC8+ when going into runtime PM.
8199 *
8200 * The requirements for PC8+ are that all the outputs are disabled, the power
8201 * well is disabled and most interrupts are disabled, and these are also
8202 * requirements for runtime PM. When these conditions are met, we manually do
8203 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8204 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8205 * hang the machine.
8206 *
8207 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8208 * the state of some registers, so when we come back from PC8+ we need to
8209 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8210 * need to take care of the registers kept by RC6. Notice that this happens even
8211 * if we don't put the device in PCI D3 state (which is what currently happens
8212 * because of the runtime PM support).
8213 *
8214 * For more, read "Display Sequences for Package C8" on the hardware
8215 * documentation.
8216 */
8217 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8218 {
8219 struct drm_device *dev = dev_priv->dev;
8220 uint32_t val;
8221
8222 DRM_DEBUG_KMS("Enabling package C8+\n");
8223
8224 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8225 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8226 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8227 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8228 }
8229
8230 lpt_disable_clkout_dp(dev);
8231 hsw_disable_lcpll(dev_priv, true, true);
8232 }
8233
8234 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8235 {
8236 struct drm_device *dev = dev_priv->dev;
8237 uint32_t val;
8238
8239 DRM_DEBUG_KMS("Disabling package C8+\n");
8240
8241 hsw_restore_lcpll(dev_priv);
8242 lpt_init_pch_refclk(dev);
8243
8244 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8245 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8246 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8247 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8248 }
8249
8250 intel_prepare_ddi(dev);
8251 }
8252
8253 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8254 struct intel_crtc_state *crtc_state)
8255 {
8256 if (!intel_ddi_pll_select(crtc, crtc_state))
8257 return -EINVAL;
8258
8259 crtc->lowfreq_avail = false;
8260
8261 return 0;
8262 }
8263
8264 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8265 enum port port,
8266 struct intel_crtc_state *pipe_config)
8267 {
8268 u32 temp, dpll_ctl1;
8269
8270 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8271 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8272
8273 switch (pipe_config->ddi_pll_sel) {
8274 case SKL_DPLL0:
8275 /*
8276 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8277 * of the shared DPLL framework and thus needs to be read out
8278 * separately
8279 */
8280 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8281 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8282 break;
8283 case SKL_DPLL1:
8284 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8285 break;
8286 case SKL_DPLL2:
8287 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8288 break;
8289 case SKL_DPLL3:
8290 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8291 break;
8292 }
8293 }
8294
8295 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8296 enum port port,
8297 struct intel_crtc_state *pipe_config)
8298 {
8299 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8300
8301 switch (pipe_config->ddi_pll_sel) {
8302 case PORT_CLK_SEL_WRPLL1:
8303 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8304 break;
8305 case PORT_CLK_SEL_WRPLL2:
8306 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8307 break;
8308 }
8309 }
8310
8311 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8312 struct intel_crtc_state *pipe_config)
8313 {
8314 struct drm_device *dev = crtc->base.dev;
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8316 struct intel_shared_dpll *pll;
8317 enum port port;
8318 uint32_t tmp;
8319
8320 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8321
8322 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8323
8324 if (IS_SKYLAKE(dev))
8325 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8326 else
8327 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8328
8329 if (pipe_config->shared_dpll >= 0) {
8330 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8331
8332 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8333 &pipe_config->dpll_hw_state));
8334 }
8335
8336 /*
8337 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8338 * DDI E. So just check whether this pipe is wired to DDI E and whether
8339 * the PCH transcoder is on.
8340 */
8341 if (INTEL_INFO(dev)->gen < 9 &&
8342 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8343 pipe_config->has_pch_encoder = true;
8344
8345 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8346 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8347 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8348
8349 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8350 }
8351 }
8352
8353 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8354 struct intel_crtc_state *pipe_config)
8355 {
8356 struct drm_device *dev = crtc->base.dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 enum intel_display_power_domain pfit_domain;
8359 uint32_t tmp;
8360
8361 if (!intel_display_power_is_enabled(dev_priv,
8362 POWER_DOMAIN_PIPE(crtc->pipe)))
8363 return false;
8364
8365 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8366 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8367
8368 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8369 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8370 enum pipe trans_edp_pipe;
8371 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8372 default:
8373 WARN(1, "unknown pipe linked to edp transcoder\n");
8374 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8375 case TRANS_DDI_EDP_INPUT_A_ON:
8376 trans_edp_pipe = PIPE_A;
8377 break;
8378 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8379 trans_edp_pipe = PIPE_B;
8380 break;
8381 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8382 trans_edp_pipe = PIPE_C;
8383 break;
8384 }
8385
8386 if (trans_edp_pipe == crtc->pipe)
8387 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8388 }
8389
8390 if (!intel_display_power_is_enabled(dev_priv,
8391 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8392 return false;
8393
8394 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8395 if (!(tmp & PIPECONF_ENABLE))
8396 return false;
8397
8398 haswell_get_ddi_port_state(crtc, pipe_config);
8399
8400 intel_get_pipe_timings(crtc, pipe_config);
8401
8402 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8403 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8404 if (IS_SKYLAKE(dev))
8405 skylake_get_pfit_config(crtc, pipe_config);
8406 else
8407 ironlake_get_pfit_config(crtc, pipe_config);
8408 }
8409
8410 if (IS_HASWELL(dev))
8411 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8412 (I915_READ(IPS_CTL) & IPS_ENABLE);
8413
8414 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8415 pipe_config->pixel_multiplier =
8416 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8417 } else {
8418 pipe_config->pixel_multiplier = 1;
8419 }
8420
8421 return true;
8422 }
8423
8424 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8425 {
8426 struct drm_device *dev = crtc->dev;
8427 struct drm_i915_private *dev_priv = dev->dev_private;
8428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8429 uint32_t cntl = 0, size = 0;
8430
8431 if (base) {
8432 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8433 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8434 unsigned int stride = roundup_pow_of_two(width) * 4;
8435
8436 switch (stride) {
8437 default:
8438 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8439 width, stride);
8440 stride = 256;
8441 /* fallthrough */
8442 case 256:
8443 case 512:
8444 case 1024:
8445 case 2048:
8446 break;
8447 }
8448
8449 cntl |= CURSOR_ENABLE |
8450 CURSOR_GAMMA_ENABLE |
8451 CURSOR_FORMAT_ARGB |
8452 CURSOR_STRIDE(stride);
8453
8454 size = (height << 12) | width;
8455 }
8456
8457 if (intel_crtc->cursor_cntl != 0 &&
8458 (intel_crtc->cursor_base != base ||
8459 intel_crtc->cursor_size != size ||
8460 intel_crtc->cursor_cntl != cntl)) {
8461 /* On these chipsets we can only modify the base/size/stride
8462 * whilst the cursor is disabled.
8463 */
8464 I915_WRITE(_CURACNTR, 0);
8465 POSTING_READ(_CURACNTR);
8466 intel_crtc->cursor_cntl = 0;
8467 }
8468
8469 if (intel_crtc->cursor_base != base) {
8470 I915_WRITE(_CURABASE, base);
8471 intel_crtc->cursor_base = base;
8472 }
8473
8474 if (intel_crtc->cursor_size != size) {
8475 I915_WRITE(CURSIZE, size);
8476 intel_crtc->cursor_size = size;
8477 }
8478
8479 if (intel_crtc->cursor_cntl != cntl) {
8480 I915_WRITE(_CURACNTR, cntl);
8481 POSTING_READ(_CURACNTR);
8482 intel_crtc->cursor_cntl = cntl;
8483 }
8484 }
8485
8486 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8487 {
8488 struct drm_device *dev = crtc->dev;
8489 struct drm_i915_private *dev_priv = dev->dev_private;
8490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8491 int pipe = intel_crtc->pipe;
8492 uint32_t cntl;
8493
8494 cntl = 0;
8495 if (base) {
8496 cntl = MCURSOR_GAMMA_ENABLE;
8497 switch (intel_crtc->base.cursor->state->crtc_w) {
8498 case 64:
8499 cntl |= CURSOR_MODE_64_ARGB_AX;
8500 break;
8501 case 128:
8502 cntl |= CURSOR_MODE_128_ARGB_AX;
8503 break;
8504 case 256:
8505 cntl |= CURSOR_MODE_256_ARGB_AX;
8506 break;
8507 default:
8508 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8509 return;
8510 }
8511 cntl |= pipe << 28; /* Connect to correct pipe */
8512
8513 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8514 cntl |= CURSOR_PIPE_CSC_ENABLE;
8515 }
8516
8517 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8518 cntl |= CURSOR_ROTATE_180;
8519
8520 if (intel_crtc->cursor_cntl != cntl) {
8521 I915_WRITE(CURCNTR(pipe), cntl);
8522 POSTING_READ(CURCNTR(pipe));
8523 intel_crtc->cursor_cntl = cntl;
8524 }
8525
8526 /* and commit changes on next vblank */
8527 I915_WRITE(CURBASE(pipe), base);
8528 POSTING_READ(CURBASE(pipe));
8529
8530 intel_crtc->cursor_base = base;
8531 }
8532
8533 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8534 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8535 bool on)
8536 {
8537 struct drm_device *dev = crtc->dev;
8538 struct drm_i915_private *dev_priv = dev->dev_private;
8539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8540 int pipe = intel_crtc->pipe;
8541 int x = crtc->cursor_x;
8542 int y = crtc->cursor_y;
8543 u32 base = 0, pos = 0;
8544
8545 if (on)
8546 base = intel_crtc->cursor_addr;
8547
8548 if (x >= intel_crtc->config->pipe_src_w)
8549 base = 0;
8550
8551 if (y >= intel_crtc->config->pipe_src_h)
8552 base = 0;
8553
8554 if (x < 0) {
8555 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8556 base = 0;
8557
8558 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8559 x = -x;
8560 }
8561 pos |= x << CURSOR_X_SHIFT;
8562
8563 if (y < 0) {
8564 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8565 base = 0;
8566
8567 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8568 y = -y;
8569 }
8570 pos |= y << CURSOR_Y_SHIFT;
8571
8572 if (base == 0 && intel_crtc->cursor_base == 0)
8573 return;
8574
8575 I915_WRITE(CURPOS(pipe), pos);
8576
8577 /* ILK+ do this automagically */
8578 if (HAS_GMCH_DISPLAY(dev) &&
8579 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8580 base += (intel_crtc->base.cursor->state->crtc_h *
8581 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8582 }
8583
8584 if (IS_845G(dev) || IS_I865G(dev))
8585 i845_update_cursor(crtc, base);
8586 else
8587 i9xx_update_cursor(crtc, base);
8588 }
8589
8590 static bool cursor_size_ok(struct drm_device *dev,
8591 uint32_t width, uint32_t height)
8592 {
8593 if (width == 0 || height == 0)
8594 return false;
8595
8596 /*
8597 * 845g/865g are special in that they are only limited by
8598 * the width of their cursors, the height is arbitrary up to
8599 * the precision of the register. Everything else requires
8600 * square cursors, limited to a few power-of-two sizes.
8601 */
8602 if (IS_845G(dev) || IS_I865G(dev)) {
8603 if ((width & 63) != 0)
8604 return false;
8605
8606 if (width > (IS_845G(dev) ? 64 : 512))
8607 return false;
8608
8609 if (height > 1023)
8610 return false;
8611 } else {
8612 switch (width | height) {
8613 case 256:
8614 case 128:
8615 if (IS_GEN2(dev))
8616 return false;
8617 case 64:
8618 break;
8619 default:
8620 return false;
8621 }
8622 }
8623
8624 return true;
8625 }
8626
8627 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8628 u16 *blue, uint32_t start, uint32_t size)
8629 {
8630 int end = (start + size > 256) ? 256 : start + size, i;
8631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8632
8633 for (i = start; i < end; i++) {
8634 intel_crtc->lut_r[i] = red[i] >> 8;
8635 intel_crtc->lut_g[i] = green[i] >> 8;
8636 intel_crtc->lut_b[i] = blue[i] >> 8;
8637 }
8638
8639 intel_crtc_load_lut(crtc);
8640 }
8641
8642 /* VESA 640x480x72Hz mode to set on the pipe */
8643 static struct drm_display_mode load_detect_mode = {
8644 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8645 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8646 };
8647
8648 struct drm_framebuffer *
8649 __intel_framebuffer_create(struct drm_device *dev,
8650 struct drm_mode_fb_cmd2 *mode_cmd,
8651 struct drm_i915_gem_object *obj)
8652 {
8653 struct intel_framebuffer *intel_fb;
8654 int ret;
8655
8656 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8657 if (!intel_fb) {
8658 drm_gem_object_unreference(&obj->base);
8659 return ERR_PTR(-ENOMEM);
8660 }
8661
8662 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8663 if (ret)
8664 goto err;
8665
8666 return &intel_fb->base;
8667 err:
8668 drm_gem_object_unreference(&obj->base);
8669 kfree(intel_fb);
8670
8671 return ERR_PTR(ret);
8672 }
8673
8674 static struct drm_framebuffer *
8675 intel_framebuffer_create(struct drm_device *dev,
8676 struct drm_mode_fb_cmd2 *mode_cmd,
8677 struct drm_i915_gem_object *obj)
8678 {
8679 struct drm_framebuffer *fb;
8680 int ret;
8681
8682 ret = i915_mutex_lock_interruptible(dev);
8683 if (ret)
8684 return ERR_PTR(ret);
8685 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8686 mutex_unlock(&dev->struct_mutex);
8687
8688 return fb;
8689 }
8690
8691 static u32
8692 intel_framebuffer_pitch_for_width(int width, int bpp)
8693 {
8694 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8695 return ALIGN(pitch, 64);
8696 }
8697
8698 static u32
8699 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8700 {
8701 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8702 return PAGE_ALIGN(pitch * mode->vdisplay);
8703 }
8704
8705 static struct drm_framebuffer *
8706 intel_framebuffer_create_for_mode(struct drm_device *dev,
8707 struct drm_display_mode *mode,
8708 int depth, int bpp)
8709 {
8710 struct drm_i915_gem_object *obj;
8711 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8712
8713 obj = i915_gem_alloc_object(dev,
8714 intel_framebuffer_size_for_mode(mode, bpp));
8715 if (obj == NULL)
8716 return ERR_PTR(-ENOMEM);
8717
8718 mode_cmd.width = mode->hdisplay;
8719 mode_cmd.height = mode->vdisplay;
8720 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8721 bpp);
8722 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8723
8724 return intel_framebuffer_create(dev, &mode_cmd, obj);
8725 }
8726
8727 static struct drm_framebuffer *
8728 mode_fits_in_fbdev(struct drm_device *dev,
8729 struct drm_display_mode *mode)
8730 {
8731 #ifdef CONFIG_DRM_I915_FBDEV
8732 struct drm_i915_private *dev_priv = dev->dev_private;
8733 struct drm_i915_gem_object *obj;
8734 struct drm_framebuffer *fb;
8735
8736 if (!dev_priv->fbdev)
8737 return NULL;
8738
8739 if (!dev_priv->fbdev->fb)
8740 return NULL;
8741
8742 obj = dev_priv->fbdev->fb->obj;
8743 BUG_ON(!obj);
8744
8745 fb = &dev_priv->fbdev->fb->base;
8746 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8747 fb->bits_per_pixel))
8748 return NULL;
8749
8750 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8751 return NULL;
8752
8753 return fb;
8754 #else
8755 return NULL;
8756 #endif
8757 }
8758
8759 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8760 struct drm_display_mode *mode,
8761 struct intel_load_detect_pipe *old,
8762 struct drm_modeset_acquire_ctx *ctx)
8763 {
8764 struct intel_crtc *intel_crtc;
8765 struct intel_encoder *intel_encoder =
8766 intel_attached_encoder(connector);
8767 struct drm_crtc *possible_crtc;
8768 struct drm_encoder *encoder = &intel_encoder->base;
8769 struct drm_crtc *crtc = NULL;
8770 struct drm_device *dev = encoder->dev;
8771 struct drm_framebuffer *fb;
8772 struct drm_mode_config *config = &dev->mode_config;
8773 int ret, i = -1;
8774
8775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8776 connector->base.id, connector->name,
8777 encoder->base.id, encoder->name);
8778
8779 retry:
8780 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8781 if (ret)
8782 goto fail_unlock;
8783
8784 /*
8785 * Algorithm gets a little messy:
8786 *
8787 * - if the connector already has an assigned crtc, use it (but make
8788 * sure it's on first)
8789 *
8790 * - try to find the first unused crtc that can drive this connector,
8791 * and use that if we find one
8792 */
8793
8794 /* See if we already have a CRTC for this connector */
8795 if (encoder->crtc) {
8796 crtc = encoder->crtc;
8797
8798 ret = drm_modeset_lock(&crtc->mutex, ctx);
8799 if (ret)
8800 goto fail_unlock;
8801 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8802 if (ret)
8803 goto fail_unlock;
8804
8805 old->dpms_mode = connector->dpms;
8806 old->load_detect_temp = false;
8807
8808 /* Make sure the crtc and connector are running */
8809 if (connector->dpms != DRM_MODE_DPMS_ON)
8810 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8811
8812 return true;
8813 }
8814
8815 /* Find an unused one (if possible) */
8816 for_each_crtc(dev, possible_crtc) {
8817 i++;
8818 if (!(encoder->possible_crtcs & (1 << i)))
8819 continue;
8820 if (possible_crtc->state->enable)
8821 continue;
8822 /* This can occur when applying the pipe A quirk on resume. */
8823 if (to_intel_crtc(possible_crtc)->new_enabled)
8824 continue;
8825
8826 crtc = possible_crtc;
8827 break;
8828 }
8829
8830 /*
8831 * If we didn't find an unused CRTC, don't use any.
8832 */
8833 if (!crtc) {
8834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8835 goto fail_unlock;
8836 }
8837
8838 ret = drm_modeset_lock(&crtc->mutex, ctx);
8839 if (ret)
8840 goto fail_unlock;
8841 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8842 if (ret)
8843 goto fail_unlock;
8844 intel_encoder->new_crtc = to_intel_crtc(crtc);
8845 to_intel_connector(connector)->new_encoder = intel_encoder;
8846
8847 intel_crtc = to_intel_crtc(crtc);
8848 intel_crtc->new_enabled = true;
8849 intel_crtc->new_config = intel_crtc->config;
8850 old->dpms_mode = connector->dpms;
8851 old->load_detect_temp = true;
8852 old->release_fb = NULL;
8853
8854 if (!mode)
8855 mode = &load_detect_mode;
8856
8857 /* We need a framebuffer large enough to accommodate all accesses
8858 * that the plane may generate whilst we perform load detection.
8859 * We can not rely on the fbcon either being present (we get called
8860 * during its initialisation to detect all boot displays, or it may
8861 * not even exist) or that it is large enough to satisfy the
8862 * requested mode.
8863 */
8864 fb = mode_fits_in_fbdev(dev, mode);
8865 if (fb == NULL) {
8866 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8867 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8868 old->release_fb = fb;
8869 } else
8870 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8871 if (IS_ERR(fb)) {
8872 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8873 goto fail;
8874 }
8875
8876 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8877 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8878 if (old->release_fb)
8879 old->release_fb->funcs->destroy(old->release_fb);
8880 goto fail;
8881 }
8882 crtc->primary->crtc = crtc;
8883
8884 /* let the connector get through one full cycle before testing */
8885 intel_wait_for_vblank(dev, intel_crtc->pipe);
8886 return true;
8887
8888 fail:
8889 intel_crtc->new_enabled = crtc->state->enable;
8890 if (intel_crtc->new_enabled)
8891 intel_crtc->new_config = intel_crtc->config;
8892 else
8893 intel_crtc->new_config = NULL;
8894 fail_unlock:
8895 if (ret == -EDEADLK) {
8896 drm_modeset_backoff(ctx);
8897 goto retry;
8898 }
8899
8900 return false;
8901 }
8902
8903 void intel_release_load_detect_pipe(struct drm_connector *connector,
8904 struct intel_load_detect_pipe *old)
8905 {
8906 struct intel_encoder *intel_encoder =
8907 intel_attached_encoder(connector);
8908 struct drm_encoder *encoder = &intel_encoder->base;
8909 struct drm_crtc *crtc = encoder->crtc;
8910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8911
8912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8913 connector->base.id, connector->name,
8914 encoder->base.id, encoder->name);
8915
8916 if (old->load_detect_temp) {
8917 to_intel_connector(connector)->new_encoder = NULL;
8918 intel_encoder->new_crtc = NULL;
8919 intel_crtc->new_enabled = false;
8920 intel_crtc->new_config = NULL;
8921 intel_set_mode(crtc, NULL, 0, 0, NULL);
8922
8923 if (old->release_fb) {
8924 drm_framebuffer_unregister_private(old->release_fb);
8925 drm_framebuffer_unreference(old->release_fb);
8926 }
8927
8928 return;
8929 }
8930
8931 /* Switch crtc and encoder back off if necessary */
8932 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8933 connector->funcs->dpms(connector, old->dpms_mode);
8934 }
8935
8936 static int i9xx_pll_refclk(struct drm_device *dev,
8937 const struct intel_crtc_state *pipe_config)
8938 {
8939 struct drm_i915_private *dev_priv = dev->dev_private;
8940 u32 dpll = pipe_config->dpll_hw_state.dpll;
8941
8942 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8943 return dev_priv->vbt.lvds_ssc_freq;
8944 else if (HAS_PCH_SPLIT(dev))
8945 return 120000;
8946 else if (!IS_GEN2(dev))
8947 return 96000;
8948 else
8949 return 48000;
8950 }
8951
8952 /* Returns the clock of the currently programmed mode of the given pipe. */
8953 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8954 struct intel_crtc_state *pipe_config)
8955 {
8956 struct drm_device *dev = crtc->base.dev;
8957 struct drm_i915_private *dev_priv = dev->dev_private;
8958 int pipe = pipe_config->cpu_transcoder;
8959 u32 dpll = pipe_config->dpll_hw_state.dpll;
8960 u32 fp;
8961 intel_clock_t clock;
8962 int refclk = i9xx_pll_refclk(dev, pipe_config);
8963
8964 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8965 fp = pipe_config->dpll_hw_state.fp0;
8966 else
8967 fp = pipe_config->dpll_hw_state.fp1;
8968
8969 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8970 if (IS_PINEVIEW(dev)) {
8971 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8972 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8973 } else {
8974 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8975 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8976 }
8977
8978 if (!IS_GEN2(dev)) {
8979 if (IS_PINEVIEW(dev))
8980 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8981 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8982 else
8983 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8984 DPLL_FPA01_P1_POST_DIV_SHIFT);
8985
8986 switch (dpll & DPLL_MODE_MASK) {
8987 case DPLLB_MODE_DAC_SERIAL:
8988 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8989 5 : 10;
8990 break;
8991 case DPLLB_MODE_LVDS:
8992 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8993 7 : 14;
8994 break;
8995 default:
8996 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8997 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8998 return;
8999 }
9000
9001 if (IS_PINEVIEW(dev))
9002 pineview_clock(refclk, &clock);
9003 else
9004 i9xx_clock(refclk, &clock);
9005 } else {
9006 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9007 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9008
9009 if (is_lvds) {
9010 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9011 DPLL_FPA01_P1_POST_DIV_SHIFT);
9012
9013 if (lvds & LVDS_CLKB_POWER_UP)
9014 clock.p2 = 7;
9015 else
9016 clock.p2 = 14;
9017 } else {
9018 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9019 clock.p1 = 2;
9020 else {
9021 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9022 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9023 }
9024 if (dpll & PLL_P2_DIVIDE_BY_4)
9025 clock.p2 = 4;
9026 else
9027 clock.p2 = 2;
9028 }
9029
9030 i9xx_clock(refclk, &clock);
9031 }
9032
9033 /*
9034 * This value includes pixel_multiplier. We will use
9035 * port_clock to compute adjusted_mode.crtc_clock in the
9036 * encoder's get_config() function.
9037 */
9038 pipe_config->port_clock = clock.dot;
9039 }
9040
9041 int intel_dotclock_calculate(int link_freq,
9042 const struct intel_link_m_n *m_n)
9043 {
9044 /*
9045 * The calculation for the data clock is:
9046 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9047 * But we want to avoid losing precison if possible, so:
9048 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9049 *
9050 * and the link clock is simpler:
9051 * link_clock = (m * link_clock) / n
9052 */
9053
9054 if (!m_n->link_n)
9055 return 0;
9056
9057 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9058 }
9059
9060 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9061 struct intel_crtc_state *pipe_config)
9062 {
9063 struct drm_device *dev = crtc->base.dev;
9064
9065 /* read out port_clock from the DPLL */
9066 i9xx_crtc_clock_get(crtc, pipe_config);
9067
9068 /*
9069 * This value does not include pixel_multiplier.
9070 * We will check that port_clock and adjusted_mode.crtc_clock
9071 * agree once we know their relationship in the encoder's
9072 * get_config() function.
9073 */
9074 pipe_config->base.adjusted_mode.crtc_clock =
9075 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9076 &pipe_config->fdi_m_n);
9077 }
9078
9079 /** Returns the currently programmed mode of the given pipe. */
9080 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9081 struct drm_crtc *crtc)
9082 {
9083 struct drm_i915_private *dev_priv = dev->dev_private;
9084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9085 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9086 struct drm_display_mode *mode;
9087 struct intel_crtc_state pipe_config;
9088 int htot = I915_READ(HTOTAL(cpu_transcoder));
9089 int hsync = I915_READ(HSYNC(cpu_transcoder));
9090 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9091 int vsync = I915_READ(VSYNC(cpu_transcoder));
9092 enum pipe pipe = intel_crtc->pipe;
9093
9094 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9095 if (!mode)
9096 return NULL;
9097
9098 /*
9099 * Construct a pipe_config sufficient for getting the clock info
9100 * back out of crtc_clock_get.
9101 *
9102 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9103 * to use a real value here instead.
9104 */
9105 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9106 pipe_config.pixel_multiplier = 1;
9107 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9108 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9109 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9110 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9111
9112 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9113 mode->hdisplay = (htot & 0xffff) + 1;
9114 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9115 mode->hsync_start = (hsync & 0xffff) + 1;
9116 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9117 mode->vdisplay = (vtot & 0xffff) + 1;
9118 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9119 mode->vsync_start = (vsync & 0xffff) + 1;
9120 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9121
9122 drm_mode_set_name(mode);
9123
9124 return mode;
9125 }
9126
9127 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9128 {
9129 struct drm_device *dev = crtc->dev;
9130 struct drm_i915_private *dev_priv = dev->dev_private;
9131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9132
9133 if (!HAS_GMCH_DISPLAY(dev))
9134 return;
9135
9136 if (!dev_priv->lvds_downclock_avail)
9137 return;
9138
9139 /*
9140 * Since this is called by a timer, we should never get here in
9141 * the manual case.
9142 */
9143 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9144 int pipe = intel_crtc->pipe;
9145 int dpll_reg = DPLL(pipe);
9146 int dpll;
9147
9148 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9149
9150 assert_panel_unlocked(dev_priv, pipe);
9151
9152 dpll = I915_READ(dpll_reg);
9153 dpll |= DISPLAY_RATE_SELECT_FPA1;
9154 I915_WRITE(dpll_reg, dpll);
9155 intel_wait_for_vblank(dev, pipe);
9156 dpll = I915_READ(dpll_reg);
9157 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9158 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9159 }
9160
9161 }
9162
9163 void intel_mark_busy(struct drm_device *dev)
9164 {
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9166
9167 if (dev_priv->mm.busy)
9168 return;
9169
9170 intel_runtime_pm_get(dev_priv);
9171 i915_update_gfx_val(dev_priv);
9172 dev_priv->mm.busy = true;
9173 }
9174
9175 void intel_mark_idle(struct drm_device *dev)
9176 {
9177 struct drm_i915_private *dev_priv = dev->dev_private;
9178 struct drm_crtc *crtc;
9179
9180 if (!dev_priv->mm.busy)
9181 return;
9182
9183 dev_priv->mm.busy = false;
9184
9185 if (!i915.powersave)
9186 goto out;
9187
9188 for_each_crtc(dev, crtc) {
9189 if (!crtc->primary->fb)
9190 continue;
9191
9192 intel_decrease_pllclock(crtc);
9193 }
9194
9195 if (INTEL_INFO(dev)->gen >= 6)
9196 gen6_rps_idle(dev->dev_private);
9197
9198 out:
9199 intel_runtime_pm_put(dev_priv);
9200 }
9201
9202 static void intel_crtc_set_state(struct intel_crtc *crtc,
9203 struct intel_crtc_state *crtc_state)
9204 {
9205 kfree(crtc->config);
9206 crtc->config = crtc_state;
9207 crtc->base.state = &crtc_state->base;
9208 }
9209
9210 static void intel_crtc_destroy(struct drm_crtc *crtc)
9211 {
9212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9213 struct drm_device *dev = crtc->dev;
9214 struct intel_unpin_work *work;
9215
9216 spin_lock_irq(&dev->event_lock);
9217 work = intel_crtc->unpin_work;
9218 intel_crtc->unpin_work = NULL;
9219 spin_unlock_irq(&dev->event_lock);
9220
9221 if (work) {
9222 cancel_work_sync(&work->work);
9223 kfree(work);
9224 }
9225
9226 intel_crtc_set_state(intel_crtc, NULL);
9227 drm_crtc_cleanup(crtc);
9228
9229 kfree(intel_crtc);
9230 }
9231
9232 static void intel_unpin_work_fn(struct work_struct *__work)
9233 {
9234 struct intel_unpin_work *work =
9235 container_of(__work, struct intel_unpin_work, work);
9236 struct drm_device *dev = work->crtc->dev;
9237 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9238
9239 mutex_lock(&dev->struct_mutex);
9240 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9241 drm_gem_object_unreference(&work->pending_flip_obj->base);
9242 drm_framebuffer_unreference(work->old_fb);
9243
9244 intel_fbc_update(dev);
9245
9246 if (work->flip_queued_req)
9247 i915_gem_request_assign(&work->flip_queued_req, NULL);
9248 mutex_unlock(&dev->struct_mutex);
9249
9250 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9251
9252 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9253 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9254
9255 kfree(work);
9256 }
9257
9258 static void do_intel_finish_page_flip(struct drm_device *dev,
9259 struct drm_crtc *crtc)
9260 {
9261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9262 struct intel_unpin_work *work;
9263 unsigned long flags;
9264
9265 /* Ignore early vblank irqs */
9266 if (intel_crtc == NULL)
9267 return;
9268
9269 /*
9270 * This is called both by irq handlers and the reset code (to complete
9271 * lost pageflips) so needs the full irqsave spinlocks.
9272 */
9273 spin_lock_irqsave(&dev->event_lock, flags);
9274 work = intel_crtc->unpin_work;
9275
9276 /* Ensure we don't miss a work->pending update ... */
9277 smp_rmb();
9278
9279 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9280 spin_unlock_irqrestore(&dev->event_lock, flags);
9281 return;
9282 }
9283
9284 page_flip_completed(intel_crtc);
9285
9286 spin_unlock_irqrestore(&dev->event_lock, flags);
9287 }
9288
9289 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9290 {
9291 struct drm_i915_private *dev_priv = dev->dev_private;
9292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9293
9294 do_intel_finish_page_flip(dev, crtc);
9295 }
9296
9297 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9298 {
9299 struct drm_i915_private *dev_priv = dev->dev_private;
9300 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9301
9302 do_intel_finish_page_flip(dev, crtc);
9303 }
9304
9305 /* Is 'a' after or equal to 'b'? */
9306 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9307 {
9308 return !((a - b) & 0x80000000);
9309 }
9310
9311 static bool page_flip_finished(struct intel_crtc *crtc)
9312 {
9313 struct drm_device *dev = crtc->base.dev;
9314 struct drm_i915_private *dev_priv = dev->dev_private;
9315
9316 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9317 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9318 return true;
9319
9320 /*
9321 * The relevant registers doen't exist on pre-ctg.
9322 * As the flip done interrupt doesn't trigger for mmio
9323 * flips on gmch platforms, a flip count check isn't
9324 * really needed there. But since ctg has the registers,
9325 * include it in the check anyway.
9326 */
9327 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9328 return true;
9329
9330 /*
9331 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9332 * used the same base address. In that case the mmio flip might
9333 * have completed, but the CS hasn't even executed the flip yet.
9334 *
9335 * A flip count check isn't enough as the CS might have updated
9336 * the base address just after start of vblank, but before we
9337 * managed to process the interrupt. This means we'd complete the
9338 * CS flip too soon.
9339 *
9340 * Combining both checks should get us a good enough result. It may
9341 * still happen that the CS flip has been executed, but has not
9342 * yet actually completed. But in case the base address is the same
9343 * anyway, we don't really care.
9344 */
9345 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9346 crtc->unpin_work->gtt_offset &&
9347 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9348 crtc->unpin_work->flip_count);
9349 }
9350
9351 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9352 {
9353 struct drm_i915_private *dev_priv = dev->dev_private;
9354 struct intel_crtc *intel_crtc =
9355 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9356 unsigned long flags;
9357
9358
9359 /*
9360 * This is called both by irq handlers and the reset code (to complete
9361 * lost pageflips) so needs the full irqsave spinlocks.
9362 *
9363 * NB: An MMIO update of the plane base pointer will also
9364 * generate a page-flip completion irq, i.e. every modeset
9365 * is also accompanied by a spurious intel_prepare_page_flip().
9366 */
9367 spin_lock_irqsave(&dev->event_lock, flags);
9368 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9369 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9370 spin_unlock_irqrestore(&dev->event_lock, flags);
9371 }
9372
9373 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9374 {
9375 /* Ensure that the work item is consistent when activating it ... */
9376 smp_wmb();
9377 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9378 /* and that it is marked active as soon as the irq could fire. */
9379 smp_wmb();
9380 }
9381
9382 static int intel_gen2_queue_flip(struct drm_device *dev,
9383 struct drm_crtc *crtc,
9384 struct drm_framebuffer *fb,
9385 struct drm_i915_gem_object *obj,
9386 struct intel_engine_cs *ring,
9387 uint32_t flags)
9388 {
9389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9390 u32 flip_mask;
9391 int ret;
9392
9393 ret = intel_ring_begin(ring, 6);
9394 if (ret)
9395 return ret;
9396
9397 /* Can't queue multiple flips, so wait for the previous
9398 * one to finish before executing the next.
9399 */
9400 if (intel_crtc->plane)
9401 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9402 else
9403 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9404 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9405 intel_ring_emit(ring, MI_NOOP);
9406 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9407 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9408 intel_ring_emit(ring, fb->pitches[0]);
9409 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9410 intel_ring_emit(ring, 0); /* aux display base address, unused */
9411
9412 intel_mark_page_flip_active(intel_crtc);
9413 __intel_ring_advance(ring);
9414 return 0;
9415 }
9416
9417 static int intel_gen3_queue_flip(struct drm_device *dev,
9418 struct drm_crtc *crtc,
9419 struct drm_framebuffer *fb,
9420 struct drm_i915_gem_object *obj,
9421 struct intel_engine_cs *ring,
9422 uint32_t flags)
9423 {
9424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9425 u32 flip_mask;
9426 int ret;
9427
9428 ret = intel_ring_begin(ring, 6);
9429 if (ret)
9430 return ret;
9431
9432 if (intel_crtc->plane)
9433 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9434 else
9435 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9436 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9437 intel_ring_emit(ring, MI_NOOP);
9438 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9439 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9440 intel_ring_emit(ring, fb->pitches[0]);
9441 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9442 intel_ring_emit(ring, MI_NOOP);
9443
9444 intel_mark_page_flip_active(intel_crtc);
9445 __intel_ring_advance(ring);
9446 return 0;
9447 }
9448
9449 static int intel_gen4_queue_flip(struct drm_device *dev,
9450 struct drm_crtc *crtc,
9451 struct drm_framebuffer *fb,
9452 struct drm_i915_gem_object *obj,
9453 struct intel_engine_cs *ring,
9454 uint32_t flags)
9455 {
9456 struct drm_i915_private *dev_priv = dev->dev_private;
9457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9458 uint32_t pf, pipesrc;
9459 int ret;
9460
9461 ret = intel_ring_begin(ring, 4);
9462 if (ret)
9463 return ret;
9464
9465 /* i965+ uses the linear or tiled offsets from the
9466 * Display Registers (which do not change across a page-flip)
9467 * so we need only reprogram the base address.
9468 */
9469 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9470 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9471 intel_ring_emit(ring, fb->pitches[0]);
9472 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9473 obj->tiling_mode);
9474
9475 /* XXX Enabling the panel-fitter across page-flip is so far
9476 * untested on non-native modes, so ignore it for now.
9477 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9478 */
9479 pf = 0;
9480 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9481 intel_ring_emit(ring, pf | pipesrc);
9482
9483 intel_mark_page_flip_active(intel_crtc);
9484 __intel_ring_advance(ring);
9485 return 0;
9486 }
9487
9488 static int intel_gen6_queue_flip(struct drm_device *dev,
9489 struct drm_crtc *crtc,
9490 struct drm_framebuffer *fb,
9491 struct drm_i915_gem_object *obj,
9492 struct intel_engine_cs *ring,
9493 uint32_t flags)
9494 {
9495 struct drm_i915_private *dev_priv = dev->dev_private;
9496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9497 uint32_t pf, pipesrc;
9498 int ret;
9499
9500 ret = intel_ring_begin(ring, 4);
9501 if (ret)
9502 return ret;
9503
9504 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9505 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9506 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9507 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9508
9509 /* Contrary to the suggestions in the documentation,
9510 * "Enable Panel Fitter" does not seem to be required when page
9511 * flipping with a non-native mode, and worse causes a normal
9512 * modeset to fail.
9513 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9514 */
9515 pf = 0;
9516 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9517 intel_ring_emit(ring, pf | pipesrc);
9518
9519 intel_mark_page_flip_active(intel_crtc);
9520 __intel_ring_advance(ring);
9521 return 0;
9522 }
9523
9524 static int intel_gen7_queue_flip(struct drm_device *dev,
9525 struct drm_crtc *crtc,
9526 struct drm_framebuffer *fb,
9527 struct drm_i915_gem_object *obj,
9528 struct intel_engine_cs *ring,
9529 uint32_t flags)
9530 {
9531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9532 uint32_t plane_bit = 0;
9533 int len, ret;
9534
9535 switch (intel_crtc->plane) {
9536 case PLANE_A:
9537 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9538 break;
9539 case PLANE_B:
9540 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9541 break;
9542 case PLANE_C:
9543 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9544 break;
9545 default:
9546 WARN_ONCE(1, "unknown plane in flip command\n");
9547 return -ENODEV;
9548 }
9549
9550 len = 4;
9551 if (ring->id == RCS) {
9552 len += 6;
9553 /*
9554 * On Gen 8, SRM is now taking an extra dword to accommodate
9555 * 48bits addresses, and we need a NOOP for the batch size to
9556 * stay even.
9557 */
9558 if (IS_GEN8(dev))
9559 len += 2;
9560 }
9561
9562 /*
9563 * BSpec MI_DISPLAY_FLIP for IVB:
9564 * "The full packet must be contained within the same cache line."
9565 *
9566 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9567 * cacheline, if we ever start emitting more commands before
9568 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9569 * then do the cacheline alignment, and finally emit the
9570 * MI_DISPLAY_FLIP.
9571 */
9572 ret = intel_ring_cacheline_align(ring);
9573 if (ret)
9574 return ret;
9575
9576 ret = intel_ring_begin(ring, len);
9577 if (ret)
9578 return ret;
9579
9580 /* Unmask the flip-done completion message. Note that the bspec says that
9581 * we should do this for both the BCS and RCS, and that we must not unmask
9582 * more than one flip event at any time (or ensure that one flip message
9583 * can be sent by waiting for flip-done prior to queueing new flips).
9584 * Experimentation says that BCS works despite DERRMR masking all
9585 * flip-done completion events and that unmasking all planes at once
9586 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9587 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9588 */
9589 if (ring->id == RCS) {
9590 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9591 intel_ring_emit(ring, DERRMR);
9592 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9593 DERRMR_PIPEB_PRI_FLIP_DONE |
9594 DERRMR_PIPEC_PRI_FLIP_DONE));
9595 if (IS_GEN8(dev))
9596 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9597 MI_SRM_LRM_GLOBAL_GTT);
9598 else
9599 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9600 MI_SRM_LRM_GLOBAL_GTT);
9601 intel_ring_emit(ring, DERRMR);
9602 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9603 if (IS_GEN8(dev)) {
9604 intel_ring_emit(ring, 0);
9605 intel_ring_emit(ring, MI_NOOP);
9606 }
9607 }
9608
9609 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9610 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9611 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9612 intel_ring_emit(ring, (MI_NOOP));
9613
9614 intel_mark_page_flip_active(intel_crtc);
9615 __intel_ring_advance(ring);
9616 return 0;
9617 }
9618
9619 static bool use_mmio_flip(struct intel_engine_cs *ring,
9620 struct drm_i915_gem_object *obj)
9621 {
9622 /*
9623 * This is not being used for older platforms, because
9624 * non-availability of flip done interrupt forces us to use
9625 * CS flips. Older platforms derive flip done using some clever
9626 * tricks involving the flip_pending status bits and vblank irqs.
9627 * So using MMIO flips there would disrupt this mechanism.
9628 */
9629
9630 if (ring == NULL)
9631 return true;
9632
9633 if (INTEL_INFO(ring->dev)->gen < 5)
9634 return false;
9635
9636 if (i915.use_mmio_flip < 0)
9637 return false;
9638 else if (i915.use_mmio_flip > 0)
9639 return true;
9640 else if (i915.enable_execlists)
9641 return true;
9642 else
9643 return ring != i915_gem_request_get_ring(obj->last_read_req);
9644 }
9645
9646 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9647 {
9648 struct drm_device *dev = intel_crtc->base.dev;
9649 struct drm_i915_private *dev_priv = dev->dev_private;
9650 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9651 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9652 struct drm_i915_gem_object *obj = intel_fb->obj;
9653 const enum pipe pipe = intel_crtc->pipe;
9654 u32 ctl, stride;
9655
9656 ctl = I915_READ(PLANE_CTL(pipe, 0));
9657 ctl &= ~PLANE_CTL_TILED_MASK;
9658 if (obj->tiling_mode == I915_TILING_X)
9659 ctl |= PLANE_CTL_TILED_X;
9660
9661 /*
9662 * The stride is either expressed as a multiple of 64 bytes chunks for
9663 * linear buffers or in number of tiles for tiled buffers.
9664 */
9665 stride = fb->pitches[0] >> 6;
9666 if (obj->tiling_mode == I915_TILING_X)
9667 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9668
9669 /*
9670 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9671 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9672 */
9673 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9674 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9675
9676 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9677 POSTING_READ(PLANE_SURF(pipe, 0));
9678 }
9679
9680 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9681 {
9682 struct drm_device *dev = intel_crtc->base.dev;
9683 struct drm_i915_private *dev_priv = dev->dev_private;
9684 struct intel_framebuffer *intel_fb =
9685 to_intel_framebuffer(intel_crtc->base.primary->fb);
9686 struct drm_i915_gem_object *obj = intel_fb->obj;
9687 u32 dspcntr;
9688 u32 reg;
9689
9690 reg = DSPCNTR(intel_crtc->plane);
9691 dspcntr = I915_READ(reg);
9692
9693 if (obj->tiling_mode != I915_TILING_NONE)
9694 dspcntr |= DISPPLANE_TILED;
9695 else
9696 dspcntr &= ~DISPPLANE_TILED;
9697
9698 I915_WRITE(reg, dspcntr);
9699
9700 I915_WRITE(DSPSURF(intel_crtc->plane),
9701 intel_crtc->unpin_work->gtt_offset);
9702 POSTING_READ(DSPSURF(intel_crtc->plane));
9703
9704 }
9705
9706 /*
9707 * XXX: This is the temporary way to update the plane registers until we get
9708 * around to using the usual plane update functions for MMIO flips
9709 */
9710 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9711 {
9712 struct drm_device *dev = intel_crtc->base.dev;
9713 bool atomic_update;
9714 u32 start_vbl_count;
9715
9716 intel_mark_page_flip_active(intel_crtc);
9717
9718 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9719
9720 if (INTEL_INFO(dev)->gen >= 9)
9721 skl_do_mmio_flip(intel_crtc);
9722 else
9723 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9724 ilk_do_mmio_flip(intel_crtc);
9725
9726 if (atomic_update)
9727 intel_pipe_update_end(intel_crtc, start_vbl_count);
9728 }
9729
9730 static void intel_mmio_flip_work_func(struct work_struct *work)
9731 {
9732 struct intel_crtc *crtc =
9733 container_of(work, struct intel_crtc, mmio_flip.work);
9734 struct intel_mmio_flip *mmio_flip;
9735
9736 mmio_flip = &crtc->mmio_flip;
9737 if (mmio_flip->req)
9738 WARN_ON(__i915_wait_request(mmio_flip->req,
9739 crtc->reset_counter,
9740 false, NULL, NULL) != 0);
9741
9742 intel_do_mmio_flip(crtc);
9743 if (mmio_flip->req) {
9744 mutex_lock(&crtc->base.dev->struct_mutex);
9745 i915_gem_request_assign(&mmio_flip->req, NULL);
9746 mutex_unlock(&crtc->base.dev->struct_mutex);
9747 }
9748 }
9749
9750 static int intel_queue_mmio_flip(struct drm_device *dev,
9751 struct drm_crtc *crtc,
9752 struct drm_framebuffer *fb,
9753 struct drm_i915_gem_object *obj,
9754 struct intel_engine_cs *ring,
9755 uint32_t flags)
9756 {
9757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9758
9759 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9760 obj->last_write_req);
9761
9762 schedule_work(&intel_crtc->mmio_flip.work);
9763
9764 return 0;
9765 }
9766
9767 static int intel_default_queue_flip(struct drm_device *dev,
9768 struct drm_crtc *crtc,
9769 struct drm_framebuffer *fb,
9770 struct drm_i915_gem_object *obj,
9771 struct intel_engine_cs *ring,
9772 uint32_t flags)
9773 {
9774 return -ENODEV;
9775 }
9776
9777 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9778 struct drm_crtc *crtc)
9779 {
9780 struct drm_i915_private *dev_priv = dev->dev_private;
9781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9782 struct intel_unpin_work *work = intel_crtc->unpin_work;
9783 u32 addr;
9784
9785 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9786 return true;
9787
9788 if (!work->enable_stall_check)
9789 return false;
9790
9791 if (work->flip_ready_vblank == 0) {
9792 if (work->flip_queued_req &&
9793 !i915_gem_request_completed(work->flip_queued_req, true))
9794 return false;
9795
9796 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9797 }
9798
9799 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9800 return false;
9801
9802 /* Potential stall - if we see that the flip has happened,
9803 * assume a missed interrupt. */
9804 if (INTEL_INFO(dev)->gen >= 4)
9805 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9806 else
9807 addr = I915_READ(DSPADDR(intel_crtc->plane));
9808
9809 /* There is a potential issue here with a false positive after a flip
9810 * to the same address. We could address this by checking for a
9811 * non-incrementing frame counter.
9812 */
9813 return addr == work->gtt_offset;
9814 }
9815
9816 void intel_check_page_flip(struct drm_device *dev, int pipe)
9817 {
9818 struct drm_i915_private *dev_priv = dev->dev_private;
9819 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9821
9822 WARN_ON(!in_irq());
9823
9824 if (crtc == NULL)
9825 return;
9826
9827 spin_lock(&dev->event_lock);
9828 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9829 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9830 intel_crtc->unpin_work->flip_queued_vblank,
9831 drm_vblank_count(dev, pipe));
9832 page_flip_completed(intel_crtc);
9833 }
9834 spin_unlock(&dev->event_lock);
9835 }
9836
9837 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9838 struct drm_framebuffer *fb,
9839 struct drm_pending_vblank_event *event,
9840 uint32_t page_flip_flags)
9841 {
9842 struct drm_device *dev = crtc->dev;
9843 struct drm_i915_private *dev_priv = dev->dev_private;
9844 struct drm_framebuffer *old_fb = crtc->primary->fb;
9845 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9847 struct drm_plane *primary = crtc->primary;
9848 enum pipe pipe = intel_crtc->pipe;
9849 struct intel_unpin_work *work;
9850 struct intel_engine_cs *ring;
9851 int ret;
9852
9853 /*
9854 * drm_mode_page_flip_ioctl() should already catch this, but double
9855 * check to be safe. In the future we may enable pageflipping from
9856 * a disabled primary plane.
9857 */
9858 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9859 return -EBUSY;
9860
9861 /* Can't change pixel format via MI display flips. */
9862 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9863 return -EINVAL;
9864
9865 /*
9866 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9867 * Note that pitch changes could also affect these register.
9868 */
9869 if (INTEL_INFO(dev)->gen > 3 &&
9870 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9871 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9872 return -EINVAL;
9873
9874 if (i915_terminally_wedged(&dev_priv->gpu_error))
9875 goto out_hang;
9876
9877 work = kzalloc(sizeof(*work), GFP_KERNEL);
9878 if (work == NULL)
9879 return -ENOMEM;
9880
9881 work->event = event;
9882 work->crtc = crtc;
9883 work->old_fb = old_fb;
9884 INIT_WORK(&work->work, intel_unpin_work_fn);
9885
9886 ret = drm_crtc_vblank_get(crtc);
9887 if (ret)
9888 goto free_work;
9889
9890 /* We borrow the event spin lock for protecting unpin_work */
9891 spin_lock_irq(&dev->event_lock);
9892 if (intel_crtc->unpin_work) {
9893 /* Before declaring the flip queue wedged, check if
9894 * the hardware completed the operation behind our backs.
9895 */
9896 if (__intel_pageflip_stall_check(dev, crtc)) {
9897 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9898 page_flip_completed(intel_crtc);
9899 } else {
9900 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9901 spin_unlock_irq(&dev->event_lock);
9902
9903 drm_crtc_vblank_put(crtc);
9904 kfree(work);
9905 return -EBUSY;
9906 }
9907 }
9908 intel_crtc->unpin_work = work;
9909 spin_unlock_irq(&dev->event_lock);
9910
9911 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9912 flush_workqueue(dev_priv->wq);
9913
9914 ret = i915_mutex_lock_interruptible(dev);
9915 if (ret)
9916 goto cleanup;
9917
9918 /* Reference the objects for the scheduled work. */
9919 drm_framebuffer_reference(work->old_fb);
9920 drm_gem_object_reference(&obj->base);
9921
9922 crtc->primary->fb = fb;
9923 update_state_fb(crtc->primary);
9924
9925 work->pending_flip_obj = obj;
9926
9927 atomic_inc(&intel_crtc->unpin_work_count);
9928 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9929
9930 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9931 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9932
9933 if (IS_VALLEYVIEW(dev)) {
9934 ring = &dev_priv->ring[BCS];
9935 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9936 /* vlv: DISPLAY_FLIP fails to change tiling */
9937 ring = NULL;
9938 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9939 ring = &dev_priv->ring[BCS];
9940 } else if (INTEL_INFO(dev)->gen >= 7) {
9941 ring = i915_gem_request_get_ring(obj->last_read_req);
9942 if (ring == NULL || ring->id != RCS)
9943 ring = &dev_priv->ring[BCS];
9944 } else {
9945 ring = &dev_priv->ring[RCS];
9946 }
9947
9948 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9949 if (ret)
9950 goto cleanup_pending;
9951
9952 work->gtt_offset =
9953 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9954
9955 if (use_mmio_flip(ring, obj)) {
9956 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9957 page_flip_flags);
9958 if (ret)
9959 goto cleanup_unpin;
9960
9961 i915_gem_request_assign(&work->flip_queued_req,
9962 obj->last_write_req);
9963 } else {
9964 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9965 page_flip_flags);
9966 if (ret)
9967 goto cleanup_unpin;
9968
9969 i915_gem_request_assign(&work->flip_queued_req,
9970 intel_ring_get_request(ring));
9971 }
9972
9973 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9974 work->enable_stall_check = true;
9975
9976 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9977 INTEL_FRONTBUFFER_PRIMARY(pipe));
9978
9979 intel_fbc_disable(dev);
9980 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9981 mutex_unlock(&dev->struct_mutex);
9982
9983 trace_i915_flip_request(intel_crtc->plane, obj);
9984
9985 return 0;
9986
9987 cleanup_unpin:
9988 intel_unpin_fb_obj(obj);
9989 cleanup_pending:
9990 atomic_dec(&intel_crtc->unpin_work_count);
9991 crtc->primary->fb = old_fb;
9992 update_state_fb(crtc->primary);
9993 drm_framebuffer_unreference(work->old_fb);
9994 drm_gem_object_unreference(&obj->base);
9995 mutex_unlock(&dev->struct_mutex);
9996
9997 cleanup:
9998 spin_lock_irq(&dev->event_lock);
9999 intel_crtc->unpin_work = NULL;
10000 spin_unlock_irq(&dev->event_lock);
10001
10002 drm_crtc_vblank_put(crtc);
10003 free_work:
10004 kfree(work);
10005
10006 if (ret == -EIO) {
10007 out_hang:
10008 ret = intel_plane_restore(primary);
10009 if (ret == 0 && event) {
10010 spin_lock_irq(&dev->event_lock);
10011 drm_send_vblank_event(dev, pipe, event);
10012 spin_unlock_irq(&dev->event_lock);
10013 }
10014 }
10015 return ret;
10016 }
10017
10018 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10019 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10020 .load_lut = intel_crtc_load_lut,
10021 .atomic_begin = intel_begin_crtc_commit,
10022 .atomic_flush = intel_finish_crtc_commit,
10023 };
10024
10025 /**
10026 * intel_modeset_update_staged_output_state
10027 *
10028 * Updates the staged output configuration state, e.g. after we've read out the
10029 * current hw state.
10030 */
10031 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10032 {
10033 struct intel_crtc *crtc;
10034 struct intel_encoder *encoder;
10035 struct intel_connector *connector;
10036
10037 for_each_intel_connector(dev, connector) {
10038 connector->new_encoder =
10039 to_intel_encoder(connector->base.encoder);
10040 }
10041
10042 for_each_intel_encoder(dev, encoder) {
10043 encoder->new_crtc =
10044 to_intel_crtc(encoder->base.crtc);
10045 }
10046
10047 for_each_intel_crtc(dev, crtc) {
10048 crtc->new_enabled = crtc->base.state->enable;
10049
10050 if (crtc->new_enabled)
10051 crtc->new_config = crtc->config;
10052 else
10053 crtc->new_config = NULL;
10054 }
10055 }
10056
10057 /**
10058 * intel_modeset_commit_output_state
10059 *
10060 * This function copies the stage display pipe configuration to the real one.
10061 */
10062 static void intel_modeset_commit_output_state(struct drm_device *dev)
10063 {
10064 struct intel_crtc *crtc;
10065 struct intel_encoder *encoder;
10066 struct intel_connector *connector;
10067
10068 for_each_intel_connector(dev, connector) {
10069 connector->base.encoder = &connector->new_encoder->base;
10070 }
10071
10072 for_each_intel_encoder(dev, encoder) {
10073 encoder->base.crtc = &encoder->new_crtc->base;
10074 }
10075
10076 for_each_intel_crtc(dev, crtc) {
10077 crtc->base.state->enable = crtc->new_enabled;
10078 crtc->base.enabled = crtc->new_enabled;
10079 }
10080 }
10081
10082 static void
10083 connected_sink_compute_bpp(struct intel_connector *connector,
10084 struct intel_crtc_state *pipe_config)
10085 {
10086 int bpp = pipe_config->pipe_bpp;
10087
10088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10089 connector->base.base.id,
10090 connector->base.name);
10091
10092 /* Don't use an invalid EDID bpc value */
10093 if (connector->base.display_info.bpc &&
10094 connector->base.display_info.bpc * 3 < bpp) {
10095 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10096 bpp, connector->base.display_info.bpc*3);
10097 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10098 }
10099
10100 /* Clamp bpp to 8 on screens without EDID 1.4 */
10101 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10102 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10103 bpp);
10104 pipe_config->pipe_bpp = 24;
10105 }
10106 }
10107
10108 static int
10109 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10110 struct drm_framebuffer *fb,
10111 struct intel_crtc_state *pipe_config)
10112 {
10113 struct drm_device *dev = crtc->base.dev;
10114 struct intel_connector *connector;
10115 int bpp;
10116
10117 switch (fb->pixel_format) {
10118 case DRM_FORMAT_C8:
10119 bpp = 8*3; /* since we go through a colormap */
10120 break;
10121 case DRM_FORMAT_XRGB1555:
10122 case DRM_FORMAT_ARGB1555:
10123 /* checked in intel_framebuffer_init already */
10124 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10125 return -EINVAL;
10126 case DRM_FORMAT_RGB565:
10127 bpp = 6*3; /* min is 18bpp */
10128 break;
10129 case DRM_FORMAT_XBGR8888:
10130 case DRM_FORMAT_ABGR8888:
10131 /* checked in intel_framebuffer_init already */
10132 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10133 return -EINVAL;
10134 case DRM_FORMAT_XRGB8888:
10135 case DRM_FORMAT_ARGB8888:
10136 bpp = 8*3;
10137 break;
10138 case DRM_FORMAT_XRGB2101010:
10139 case DRM_FORMAT_ARGB2101010:
10140 case DRM_FORMAT_XBGR2101010:
10141 case DRM_FORMAT_ABGR2101010:
10142 /* checked in intel_framebuffer_init already */
10143 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10144 return -EINVAL;
10145 bpp = 10*3;
10146 break;
10147 /* TODO: gen4+ supports 16 bpc floating point, too. */
10148 default:
10149 DRM_DEBUG_KMS("unsupported depth\n");
10150 return -EINVAL;
10151 }
10152
10153 pipe_config->pipe_bpp = bpp;
10154
10155 /* Clamp display bpp to EDID value */
10156 for_each_intel_connector(dev, connector) {
10157 if (!connector->new_encoder ||
10158 connector->new_encoder->new_crtc != crtc)
10159 continue;
10160
10161 connected_sink_compute_bpp(connector, pipe_config);
10162 }
10163
10164 return bpp;
10165 }
10166
10167 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10168 {
10169 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10170 "type: 0x%x flags: 0x%x\n",
10171 mode->crtc_clock,
10172 mode->crtc_hdisplay, mode->crtc_hsync_start,
10173 mode->crtc_hsync_end, mode->crtc_htotal,
10174 mode->crtc_vdisplay, mode->crtc_vsync_start,
10175 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10176 }
10177
10178 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10179 struct intel_crtc_state *pipe_config,
10180 const char *context)
10181 {
10182 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10183 context, pipe_name(crtc->pipe));
10184
10185 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10186 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10187 pipe_config->pipe_bpp, pipe_config->dither);
10188 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10189 pipe_config->has_pch_encoder,
10190 pipe_config->fdi_lanes,
10191 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10192 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10193 pipe_config->fdi_m_n.tu);
10194 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10195 pipe_config->has_dp_encoder,
10196 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10197 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10198 pipe_config->dp_m_n.tu);
10199
10200 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10201 pipe_config->has_dp_encoder,
10202 pipe_config->dp_m2_n2.gmch_m,
10203 pipe_config->dp_m2_n2.gmch_n,
10204 pipe_config->dp_m2_n2.link_m,
10205 pipe_config->dp_m2_n2.link_n,
10206 pipe_config->dp_m2_n2.tu);
10207
10208 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10209 pipe_config->has_audio,
10210 pipe_config->has_infoframe);
10211
10212 DRM_DEBUG_KMS("requested mode:\n");
10213 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10214 DRM_DEBUG_KMS("adjusted mode:\n");
10215 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10216 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10217 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10218 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10219 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10220 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10221 pipe_config->gmch_pfit.control,
10222 pipe_config->gmch_pfit.pgm_ratios,
10223 pipe_config->gmch_pfit.lvds_border_bits);
10224 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10225 pipe_config->pch_pfit.pos,
10226 pipe_config->pch_pfit.size,
10227 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10228 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10229 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10230 }
10231
10232 static bool encoders_cloneable(const struct intel_encoder *a,
10233 const struct intel_encoder *b)
10234 {
10235 /* masks could be asymmetric, so check both ways */
10236 return a == b || (a->cloneable & (1 << b->type) &&
10237 b->cloneable & (1 << a->type));
10238 }
10239
10240 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10241 struct intel_encoder *encoder)
10242 {
10243 struct drm_device *dev = crtc->base.dev;
10244 struct intel_encoder *source_encoder;
10245
10246 for_each_intel_encoder(dev, source_encoder) {
10247 if (source_encoder->new_crtc != crtc)
10248 continue;
10249
10250 if (!encoders_cloneable(encoder, source_encoder))
10251 return false;
10252 }
10253
10254 return true;
10255 }
10256
10257 static bool check_encoder_cloning(struct intel_crtc *crtc)
10258 {
10259 struct drm_device *dev = crtc->base.dev;
10260 struct intel_encoder *encoder;
10261
10262 for_each_intel_encoder(dev, encoder) {
10263 if (encoder->new_crtc != crtc)
10264 continue;
10265
10266 if (!check_single_encoder_cloning(crtc, encoder))
10267 return false;
10268 }
10269
10270 return true;
10271 }
10272
10273 static bool check_digital_port_conflicts(struct drm_device *dev)
10274 {
10275 struct intel_connector *connector;
10276 unsigned int used_ports = 0;
10277
10278 /*
10279 * Walk the connector list instead of the encoder
10280 * list to detect the problem on ddi platforms
10281 * where there's just one encoder per digital port.
10282 */
10283 for_each_intel_connector(dev, connector) {
10284 struct intel_encoder *encoder = connector->new_encoder;
10285
10286 if (!encoder)
10287 continue;
10288
10289 WARN_ON(!encoder->new_crtc);
10290
10291 switch (encoder->type) {
10292 unsigned int port_mask;
10293 case INTEL_OUTPUT_UNKNOWN:
10294 if (WARN_ON(!HAS_DDI(dev)))
10295 break;
10296 case INTEL_OUTPUT_DISPLAYPORT:
10297 case INTEL_OUTPUT_HDMI:
10298 case INTEL_OUTPUT_EDP:
10299 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10300
10301 /* the same port mustn't appear more than once */
10302 if (used_ports & port_mask)
10303 return false;
10304
10305 used_ports |= port_mask;
10306 default:
10307 break;
10308 }
10309 }
10310
10311 return true;
10312 }
10313
10314 static struct intel_crtc_state *
10315 intel_modeset_pipe_config(struct drm_crtc *crtc,
10316 struct drm_framebuffer *fb,
10317 struct drm_display_mode *mode)
10318 {
10319 struct drm_device *dev = crtc->dev;
10320 struct intel_encoder *encoder;
10321 struct intel_crtc_state *pipe_config;
10322 int plane_bpp, ret = -EINVAL;
10323 bool retry = true;
10324
10325 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10326 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10327 return ERR_PTR(-EINVAL);
10328 }
10329
10330 if (!check_digital_port_conflicts(dev)) {
10331 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10332 return ERR_PTR(-EINVAL);
10333 }
10334
10335 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10336 if (!pipe_config)
10337 return ERR_PTR(-ENOMEM);
10338
10339 pipe_config->base.crtc = crtc;
10340 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10341 drm_mode_copy(&pipe_config->base.mode, mode);
10342
10343 pipe_config->cpu_transcoder =
10344 (enum transcoder) to_intel_crtc(crtc)->pipe;
10345 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10346
10347 /*
10348 * Sanitize sync polarity flags based on requested ones. If neither
10349 * positive or negative polarity is requested, treat this as meaning
10350 * negative polarity.
10351 */
10352 if (!(pipe_config->base.adjusted_mode.flags &
10353 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10354 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10355
10356 if (!(pipe_config->base.adjusted_mode.flags &
10357 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10358 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10359
10360 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10361 * plane pixel format and any sink constraints into account. Returns the
10362 * source plane bpp so that dithering can be selected on mismatches
10363 * after encoders and crtc also have had their say. */
10364 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10365 fb, pipe_config);
10366 if (plane_bpp < 0)
10367 goto fail;
10368
10369 /*
10370 * Determine the real pipe dimensions. Note that stereo modes can
10371 * increase the actual pipe size due to the frame doubling and
10372 * insertion of additional space for blanks between the frame. This
10373 * is stored in the crtc timings. We use the requested mode to do this
10374 * computation to clearly distinguish it from the adjusted mode, which
10375 * can be changed by the connectors in the below retry loop.
10376 */
10377 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10378 &pipe_config->pipe_src_w,
10379 &pipe_config->pipe_src_h);
10380
10381 encoder_retry:
10382 /* Ensure the port clock defaults are reset when retrying. */
10383 pipe_config->port_clock = 0;
10384 pipe_config->pixel_multiplier = 1;
10385
10386 /* Fill in default crtc timings, allow encoders to overwrite them. */
10387 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10388 CRTC_STEREO_DOUBLE);
10389
10390 /* Pass our mode to the connectors and the CRTC to give them a chance to
10391 * adjust it according to limitations or connector properties, and also
10392 * a chance to reject the mode entirely.
10393 */
10394 for_each_intel_encoder(dev, encoder) {
10395
10396 if (&encoder->new_crtc->base != crtc)
10397 continue;
10398
10399 if (!(encoder->compute_config(encoder, pipe_config))) {
10400 DRM_DEBUG_KMS("Encoder config failure\n");
10401 goto fail;
10402 }
10403 }
10404
10405 /* Set default port clock if not overwritten by the encoder. Needs to be
10406 * done afterwards in case the encoder adjusts the mode. */
10407 if (!pipe_config->port_clock)
10408 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10409 * pipe_config->pixel_multiplier;
10410
10411 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10412 if (ret < 0) {
10413 DRM_DEBUG_KMS("CRTC fixup failed\n");
10414 goto fail;
10415 }
10416
10417 if (ret == RETRY) {
10418 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10419 ret = -EINVAL;
10420 goto fail;
10421 }
10422
10423 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10424 retry = false;
10425 goto encoder_retry;
10426 }
10427
10428 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10429 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10430 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10431
10432 return pipe_config;
10433 fail:
10434 kfree(pipe_config);
10435 return ERR_PTR(ret);
10436 }
10437
10438 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10439 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10440 static void
10441 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10442 unsigned *prepare_pipes, unsigned *disable_pipes)
10443 {
10444 struct intel_crtc *intel_crtc;
10445 struct drm_device *dev = crtc->dev;
10446 struct intel_encoder *encoder;
10447 struct intel_connector *connector;
10448 struct drm_crtc *tmp_crtc;
10449
10450 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10451
10452 /* Check which crtcs have changed outputs connected to them, these need
10453 * to be part of the prepare_pipes mask. We don't (yet) support global
10454 * modeset across multiple crtcs, so modeset_pipes will only have one
10455 * bit set at most. */
10456 for_each_intel_connector(dev, connector) {
10457 if (connector->base.encoder == &connector->new_encoder->base)
10458 continue;
10459
10460 if (connector->base.encoder) {
10461 tmp_crtc = connector->base.encoder->crtc;
10462
10463 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10464 }
10465
10466 if (connector->new_encoder)
10467 *prepare_pipes |=
10468 1 << connector->new_encoder->new_crtc->pipe;
10469 }
10470
10471 for_each_intel_encoder(dev, encoder) {
10472 if (encoder->base.crtc == &encoder->new_crtc->base)
10473 continue;
10474
10475 if (encoder->base.crtc) {
10476 tmp_crtc = encoder->base.crtc;
10477
10478 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10479 }
10480
10481 if (encoder->new_crtc)
10482 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10483 }
10484
10485 /* Check for pipes that will be enabled/disabled ... */
10486 for_each_intel_crtc(dev, intel_crtc) {
10487 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10488 continue;
10489
10490 if (!intel_crtc->new_enabled)
10491 *disable_pipes |= 1 << intel_crtc->pipe;
10492 else
10493 *prepare_pipes |= 1 << intel_crtc->pipe;
10494 }
10495
10496
10497 /* set_mode is also used to update properties on life display pipes. */
10498 intel_crtc = to_intel_crtc(crtc);
10499 if (intel_crtc->new_enabled)
10500 *prepare_pipes |= 1 << intel_crtc->pipe;
10501
10502 /*
10503 * For simplicity do a full modeset on any pipe where the output routing
10504 * changed. We could be more clever, but that would require us to be
10505 * more careful with calling the relevant encoder->mode_set functions.
10506 */
10507 if (*prepare_pipes)
10508 *modeset_pipes = *prepare_pipes;
10509
10510 /* ... and mask these out. */
10511 *modeset_pipes &= ~(*disable_pipes);
10512 *prepare_pipes &= ~(*disable_pipes);
10513
10514 /*
10515 * HACK: We don't (yet) fully support global modesets. intel_set_config
10516 * obies this rule, but the modeset restore mode of
10517 * intel_modeset_setup_hw_state does not.
10518 */
10519 *modeset_pipes &= 1 << intel_crtc->pipe;
10520 *prepare_pipes &= 1 << intel_crtc->pipe;
10521
10522 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10523 *modeset_pipes, *prepare_pipes, *disable_pipes);
10524 }
10525
10526 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10527 {
10528 struct drm_encoder *encoder;
10529 struct drm_device *dev = crtc->dev;
10530
10531 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10532 if (encoder->crtc == crtc)
10533 return true;
10534
10535 return false;
10536 }
10537
10538 static void
10539 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10540 {
10541 struct drm_i915_private *dev_priv = dev->dev_private;
10542 struct intel_encoder *intel_encoder;
10543 struct intel_crtc *intel_crtc;
10544 struct drm_connector *connector;
10545
10546 intel_shared_dpll_commit(dev_priv);
10547
10548 for_each_intel_encoder(dev, intel_encoder) {
10549 if (!intel_encoder->base.crtc)
10550 continue;
10551
10552 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10553
10554 if (prepare_pipes & (1 << intel_crtc->pipe))
10555 intel_encoder->connectors_active = false;
10556 }
10557
10558 intel_modeset_commit_output_state(dev);
10559
10560 /* Double check state. */
10561 for_each_intel_crtc(dev, intel_crtc) {
10562 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10563 WARN_ON(intel_crtc->new_config &&
10564 intel_crtc->new_config != intel_crtc->config);
10565 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10566 }
10567
10568 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10569 if (!connector->encoder || !connector->encoder->crtc)
10570 continue;
10571
10572 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10573
10574 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10575 struct drm_property *dpms_property =
10576 dev->mode_config.dpms_property;
10577
10578 connector->dpms = DRM_MODE_DPMS_ON;
10579 drm_object_property_set_value(&connector->base,
10580 dpms_property,
10581 DRM_MODE_DPMS_ON);
10582
10583 intel_encoder = to_intel_encoder(connector->encoder);
10584 intel_encoder->connectors_active = true;
10585 }
10586 }
10587
10588 }
10589
10590 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10591 {
10592 int diff;
10593
10594 if (clock1 == clock2)
10595 return true;
10596
10597 if (!clock1 || !clock2)
10598 return false;
10599
10600 diff = abs(clock1 - clock2);
10601
10602 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10603 return true;
10604
10605 return false;
10606 }
10607
10608 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10609 list_for_each_entry((intel_crtc), \
10610 &(dev)->mode_config.crtc_list, \
10611 base.head) \
10612 if (mask & (1 <<(intel_crtc)->pipe))
10613
10614 static bool
10615 intel_pipe_config_compare(struct drm_device *dev,
10616 struct intel_crtc_state *current_config,
10617 struct intel_crtc_state *pipe_config)
10618 {
10619 #define PIPE_CONF_CHECK_X(name) \
10620 if (current_config->name != pipe_config->name) { \
10621 DRM_ERROR("mismatch in " #name " " \
10622 "(expected 0x%08x, found 0x%08x)\n", \
10623 current_config->name, \
10624 pipe_config->name); \
10625 return false; \
10626 }
10627
10628 #define PIPE_CONF_CHECK_I(name) \
10629 if (current_config->name != pipe_config->name) { \
10630 DRM_ERROR("mismatch in " #name " " \
10631 "(expected %i, found %i)\n", \
10632 current_config->name, \
10633 pipe_config->name); \
10634 return false; \
10635 }
10636
10637 /* This is required for BDW+ where there is only one set of registers for
10638 * switching between high and low RR.
10639 * This macro can be used whenever a comparison has to be made between one
10640 * hw state and multiple sw state variables.
10641 */
10642 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10643 if ((current_config->name != pipe_config->name) && \
10644 (current_config->alt_name != pipe_config->name)) { \
10645 DRM_ERROR("mismatch in " #name " " \
10646 "(expected %i or %i, found %i)\n", \
10647 current_config->name, \
10648 current_config->alt_name, \
10649 pipe_config->name); \
10650 return false; \
10651 }
10652
10653 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10654 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10655 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10656 "(expected %i, found %i)\n", \
10657 current_config->name & (mask), \
10658 pipe_config->name & (mask)); \
10659 return false; \
10660 }
10661
10662 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10663 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10664 DRM_ERROR("mismatch in " #name " " \
10665 "(expected %i, found %i)\n", \
10666 current_config->name, \
10667 pipe_config->name); \
10668 return false; \
10669 }
10670
10671 #define PIPE_CONF_QUIRK(quirk) \
10672 ((current_config->quirks | pipe_config->quirks) & (quirk))
10673
10674 PIPE_CONF_CHECK_I(cpu_transcoder);
10675
10676 PIPE_CONF_CHECK_I(has_pch_encoder);
10677 PIPE_CONF_CHECK_I(fdi_lanes);
10678 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10679 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10680 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10681 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10682 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10683
10684 PIPE_CONF_CHECK_I(has_dp_encoder);
10685
10686 if (INTEL_INFO(dev)->gen < 8) {
10687 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10688 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10689 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10690 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10691 PIPE_CONF_CHECK_I(dp_m_n.tu);
10692
10693 if (current_config->has_drrs) {
10694 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10695 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10696 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10697 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10698 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10699 }
10700 } else {
10701 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10702 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10703 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10704 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10705 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10706 }
10707
10708 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10709 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10710 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10711 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10712 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10713 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10714
10715 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10716 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10717 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10718 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10721
10722 PIPE_CONF_CHECK_I(pixel_multiplier);
10723 PIPE_CONF_CHECK_I(has_hdmi_sink);
10724 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10725 IS_VALLEYVIEW(dev))
10726 PIPE_CONF_CHECK_I(limited_color_range);
10727 PIPE_CONF_CHECK_I(has_infoframe);
10728
10729 PIPE_CONF_CHECK_I(has_audio);
10730
10731 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10732 DRM_MODE_FLAG_INTERLACE);
10733
10734 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10735 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10736 DRM_MODE_FLAG_PHSYNC);
10737 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10738 DRM_MODE_FLAG_NHSYNC);
10739 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10740 DRM_MODE_FLAG_PVSYNC);
10741 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10742 DRM_MODE_FLAG_NVSYNC);
10743 }
10744
10745 PIPE_CONF_CHECK_I(pipe_src_w);
10746 PIPE_CONF_CHECK_I(pipe_src_h);
10747
10748 /*
10749 * FIXME: BIOS likes to set up a cloned config with lvds+external
10750 * screen. Since we don't yet re-compute the pipe config when moving
10751 * just the lvds port away to another pipe the sw tracking won't match.
10752 *
10753 * Proper atomic modesets with recomputed global state will fix this.
10754 * Until then just don't check gmch state for inherited modes.
10755 */
10756 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10757 PIPE_CONF_CHECK_I(gmch_pfit.control);
10758 /* pfit ratios are autocomputed by the hw on gen4+ */
10759 if (INTEL_INFO(dev)->gen < 4)
10760 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10761 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10762 }
10763
10764 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10765 if (current_config->pch_pfit.enabled) {
10766 PIPE_CONF_CHECK_I(pch_pfit.pos);
10767 PIPE_CONF_CHECK_I(pch_pfit.size);
10768 }
10769
10770 /* BDW+ don't expose a synchronous way to read the state */
10771 if (IS_HASWELL(dev))
10772 PIPE_CONF_CHECK_I(ips_enabled);
10773
10774 PIPE_CONF_CHECK_I(double_wide);
10775
10776 PIPE_CONF_CHECK_X(ddi_pll_sel);
10777
10778 PIPE_CONF_CHECK_I(shared_dpll);
10779 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10780 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10781 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10782 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10783 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10784 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10785 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10786 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10787
10788 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10789 PIPE_CONF_CHECK_I(pipe_bpp);
10790
10791 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10792 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10793
10794 #undef PIPE_CONF_CHECK_X
10795 #undef PIPE_CONF_CHECK_I
10796 #undef PIPE_CONF_CHECK_I_ALT
10797 #undef PIPE_CONF_CHECK_FLAGS
10798 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10799 #undef PIPE_CONF_QUIRK
10800
10801 return true;
10802 }
10803
10804 static void check_wm_state(struct drm_device *dev)
10805 {
10806 struct drm_i915_private *dev_priv = dev->dev_private;
10807 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10808 struct intel_crtc *intel_crtc;
10809 int plane;
10810
10811 if (INTEL_INFO(dev)->gen < 9)
10812 return;
10813
10814 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10815 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10816
10817 for_each_intel_crtc(dev, intel_crtc) {
10818 struct skl_ddb_entry *hw_entry, *sw_entry;
10819 const enum pipe pipe = intel_crtc->pipe;
10820
10821 if (!intel_crtc->active)
10822 continue;
10823
10824 /* planes */
10825 for_each_plane(dev_priv, pipe, plane) {
10826 hw_entry = &hw_ddb.plane[pipe][plane];
10827 sw_entry = &sw_ddb->plane[pipe][plane];
10828
10829 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10830 continue;
10831
10832 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10833 "(expected (%u,%u), found (%u,%u))\n",
10834 pipe_name(pipe), plane + 1,
10835 sw_entry->start, sw_entry->end,
10836 hw_entry->start, hw_entry->end);
10837 }
10838
10839 /* cursor */
10840 hw_entry = &hw_ddb.cursor[pipe];
10841 sw_entry = &sw_ddb->cursor[pipe];
10842
10843 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10844 continue;
10845
10846 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10847 "(expected (%u,%u), found (%u,%u))\n",
10848 pipe_name(pipe),
10849 sw_entry->start, sw_entry->end,
10850 hw_entry->start, hw_entry->end);
10851 }
10852 }
10853
10854 static void
10855 check_connector_state(struct drm_device *dev)
10856 {
10857 struct intel_connector *connector;
10858
10859 for_each_intel_connector(dev, connector) {
10860 /* This also checks the encoder/connector hw state with the
10861 * ->get_hw_state callbacks. */
10862 intel_connector_check_state(connector);
10863
10864 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10865 "connector's staged encoder doesn't match current encoder\n");
10866 }
10867 }
10868
10869 static void
10870 check_encoder_state(struct drm_device *dev)
10871 {
10872 struct intel_encoder *encoder;
10873 struct intel_connector *connector;
10874
10875 for_each_intel_encoder(dev, encoder) {
10876 bool enabled = false;
10877 bool active = false;
10878 enum pipe pipe, tracked_pipe;
10879
10880 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10881 encoder->base.base.id,
10882 encoder->base.name);
10883
10884 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10885 "encoder's stage crtc doesn't match current crtc\n");
10886 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10887 "encoder's active_connectors set, but no crtc\n");
10888
10889 for_each_intel_connector(dev, connector) {
10890 if (connector->base.encoder != &encoder->base)
10891 continue;
10892 enabled = true;
10893 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10894 active = true;
10895 }
10896 /*
10897 * for MST connectors if we unplug the connector is gone
10898 * away but the encoder is still connected to a crtc
10899 * until a modeset happens in response to the hotplug.
10900 */
10901 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10902 continue;
10903
10904 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10905 "encoder's enabled state mismatch "
10906 "(expected %i, found %i)\n",
10907 !!encoder->base.crtc, enabled);
10908 I915_STATE_WARN(active && !encoder->base.crtc,
10909 "active encoder with no crtc\n");
10910
10911 I915_STATE_WARN(encoder->connectors_active != active,
10912 "encoder's computed active state doesn't match tracked active state "
10913 "(expected %i, found %i)\n", active, encoder->connectors_active);
10914
10915 active = encoder->get_hw_state(encoder, &pipe);
10916 I915_STATE_WARN(active != encoder->connectors_active,
10917 "encoder's hw state doesn't match sw tracking "
10918 "(expected %i, found %i)\n",
10919 encoder->connectors_active, active);
10920
10921 if (!encoder->base.crtc)
10922 continue;
10923
10924 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10925 I915_STATE_WARN(active && pipe != tracked_pipe,
10926 "active encoder's pipe doesn't match"
10927 "(expected %i, found %i)\n",
10928 tracked_pipe, pipe);
10929
10930 }
10931 }
10932
10933 static void
10934 check_crtc_state(struct drm_device *dev)
10935 {
10936 struct drm_i915_private *dev_priv = dev->dev_private;
10937 struct intel_crtc *crtc;
10938 struct intel_encoder *encoder;
10939 struct intel_crtc_state pipe_config;
10940
10941 for_each_intel_crtc(dev, crtc) {
10942 bool enabled = false;
10943 bool active = false;
10944
10945 memset(&pipe_config, 0, sizeof(pipe_config));
10946
10947 DRM_DEBUG_KMS("[CRTC:%d]\n",
10948 crtc->base.base.id);
10949
10950 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10951 "active crtc, but not enabled in sw tracking\n");
10952
10953 for_each_intel_encoder(dev, encoder) {
10954 if (encoder->base.crtc != &crtc->base)
10955 continue;
10956 enabled = true;
10957 if (encoder->connectors_active)
10958 active = true;
10959 }
10960
10961 I915_STATE_WARN(active != crtc->active,
10962 "crtc's computed active state doesn't match tracked active state "
10963 "(expected %i, found %i)\n", active, crtc->active);
10964 I915_STATE_WARN(enabled != crtc->base.state->enable,
10965 "crtc's computed enabled state doesn't match tracked enabled state "
10966 "(expected %i, found %i)\n", enabled,
10967 crtc->base.state->enable);
10968
10969 active = dev_priv->display.get_pipe_config(crtc,
10970 &pipe_config);
10971
10972 /* hw state is inconsistent with the pipe quirk */
10973 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10974 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10975 active = crtc->active;
10976
10977 for_each_intel_encoder(dev, encoder) {
10978 enum pipe pipe;
10979 if (encoder->base.crtc != &crtc->base)
10980 continue;
10981 if (encoder->get_hw_state(encoder, &pipe))
10982 encoder->get_config(encoder, &pipe_config);
10983 }
10984
10985 I915_STATE_WARN(crtc->active != active,
10986 "crtc active state doesn't match with hw state "
10987 "(expected %i, found %i)\n", crtc->active, active);
10988
10989 if (active &&
10990 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10991 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10992 intel_dump_pipe_config(crtc, &pipe_config,
10993 "[hw state]");
10994 intel_dump_pipe_config(crtc, crtc->config,
10995 "[sw state]");
10996 }
10997 }
10998 }
10999
11000 static void
11001 check_shared_dpll_state(struct drm_device *dev)
11002 {
11003 struct drm_i915_private *dev_priv = dev->dev_private;
11004 struct intel_crtc *crtc;
11005 struct intel_dpll_hw_state dpll_hw_state;
11006 int i;
11007
11008 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11009 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11010 int enabled_crtcs = 0, active_crtcs = 0;
11011 bool active;
11012
11013 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11014
11015 DRM_DEBUG_KMS("%s\n", pll->name);
11016
11017 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11018
11019 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11020 "more active pll users than references: %i vs %i\n",
11021 pll->active, hweight32(pll->config.crtc_mask));
11022 I915_STATE_WARN(pll->active && !pll->on,
11023 "pll in active use but not on in sw tracking\n");
11024 I915_STATE_WARN(pll->on && !pll->active,
11025 "pll in on but not on in use in sw tracking\n");
11026 I915_STATE_WARN(pll->on != active,
11027 "pll on state mismatch (expected %i, found %i)\n",
11028 pll->on, active);
11029
11030 for_each_intel_crtc(dev, crtc) {
11031 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11032 enabled_crtcs++;
11033 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11034 active_crtcs++;
11035 }
11036 I915_STATE_WARN(pll->active != active_crtcs,
11037 "pll active crtcs mismatch (expected %i, found %i)\n",
11038 pll->active, active_crtcs);
11039 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11040 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11041 hweight32(pll->config.crtc_mask), enabled_crtcs);
11042
11043 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11044 sizeof(dpll_hw_state)),
11045 "pll hw state mismatch\n");
11046 }
11047 }
11048
11049 void
11050 intel_modeset_check_state(struct drm_device *dev)
11051 {
11052 check_wm_state(dev);
11053 check_connector_state(dev);
11054 check_encoder_state(dev);
11055 check_crtc_state(dev);
11056 check_shared_dpll_state(dev);
11057 }
11058
11059 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11060 int dotclock)
11061 {
11062 /*
11063 * FDI already provided one idea for the dotclock.
11064 * Yell if the encoder disagrees.
11065 */
11066 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11067 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11068 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11069 }
11070
11071 static void update_scanline_offset(struct intel_crtc *crtc)
11072 {
11073 struct drm_device *dev = crtc->base.dev;
11074
11075 /*
11076 * The scanline counter increments at the leading edge of hsync.
11077 *
11078 * On most platforms it starts counting from vtotal-1 on the
11079 * first active line. That means the scanline counter value is
11080 * always one less than what we would expect. Ie. just after
11081 * start of vblank, which also occurs at start of hsync (on the
11082 * last active line), the scanline counter will read vblank_start-1.
11083 *
11084 * On gen2 the scanline counter starts counting from 1 instead
11085 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11086 * to keep the value positive), instead of adding one.
11087 *
11088 * On HSW+ the behaviour of the scanline counter depends on the output
11089 * type. For DP ports it behaves like most other platforms, but on HDMI
11090 * there's an extra 1 line difference. So we need to add two instead of
11091 * one to the value.
11092 */
11093 if (IS_GEN2(dev)) {
11094 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11095 int vtotal;
11096
11097 vtotal = mode->crtc_vtotal;
11098 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11099 vtotal /= 2;
11100
11101 crtc->scanline_offset = vtotal - 1;
11102 } else if (HAS_DDI(dev) &&
11103 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11104 crtc->scanline_offset = 2;
11105 } else
11106 crtc->scanline_offset = 1;
11107 }
11108
11109 static struct intel_crtc_state *
11110 intel_modeset_compute_config(struct drm_crtc *crtc,
11111 struct drm_display_mode *mode,
11112 struct drm_framebuffer *fb,
11113 unsigned *modeset_pipes,
11114 unsigned *prepare_pipes,
11115 unsigned *disable_pipes)
11116 {
11117 struct intel_crtc_state *pipe_config = NULL;
11118
11119 intel_modeset_affected_pipes(crtc, modeset_pipes,
11120 prepare_pipes, disable_pipes);
11121
11122 if ((*modeset_pipes) == 0)
11123 goto out;
11124
11125 /*
11126 * Note this needs changes when we start tracking multiple modes
11127 * and crtcs. At that point we'll need to compute the whole config
11128 * (i.e. one pipe_config for each crtc) rather than just the one
11129 * for this crtc.
11130 */
11131 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11132 if (IS_ERR(pipe_config)) {
11133 goto out;
11134 }
11135 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11136 "[modeset]");
11137
11138 out:
11139 return pipe_config;
11140 }
11141
11142 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11143 unsigned modeset_pipes,
11144 unsigned disable_pipes)
11145 {
11146 struct drm_i915_private *dev_priv = to_i915(dev);
11147 unsigned clear_pipes = modeset_pipes | disable_pipes;
11148 struct intel_crtc *intel_crtc;
11149 int ret = 0;
11150
11151 if (!dev_priv->display.crtc_compute_clock)
11152 return 0;
11153
11154 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11155 if (ret)
11156 goto done;
11157
11158 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11159 struct intel_crtc_state *state = intel_crtc->new_config;
11160 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11161 state);
11162 if (ret) {
11163 intel_shared_dpll_abort_config(dev_priv);
11164 goto done;
11165 }
11166 }
11167
11168 done:
11169 return ret;
11170 }
11171
11172 static int __intel_set_mode(struct drm_crtc *crtc,
11173 struct drm_display_mode *mode,
11174 int x, int y, struct drm_framebuffer *fb,
11175 struct intel_crtc_state *pipe_config,
11176 unsigned modeset_pipes,
11177 unsigned prepare_pipes,
11178 unsigned disable_pipes)
11179 {
11180 struct drm_device *dev = crtc->dev;
11181 struct drm_i915_private *dev_priv = dev->dev_private;
11182 struct drm_display_mode *saved_mode;
11183 struct intel_crtc *intel_crtc;
11184 int ret = 0;
11185
11186 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11187 if (!saved_mode)
11188 return -ENOMEM;
11189
11190 *saved_mode = crtc->mode;
11191
11192 if (modeset_pipes)
11193 to_intel_crtc(crtc)->new_config = pipe_config;
11194
11195 /*
11196 * See if the config requires any additional preparation, e.g.
11197 * to adjust global state with pipes off. We need to do this
11198 * here so we can get the modeset_pipe updated config for the new
11199 * mode set on this crtc. For other crtcs we need to use the
11200 * adjusted_mode bits in the crtc directly.
11201 */
11202 if (IS_VALLEYVIEW(dev)) {
11203 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11204
11205 /* may have added more to prepare_pipes than we should */
11206 prepare_pipes &= ~disable_pipes;
11207 }
11208
11209 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11210 if (ret)
11211 goto done;
11212
11213 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11214 intel_crtc_disable(&intel_crtc->base);
11215
11216 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11217 if (intel_crtc->base.state->enable)
11218 dev_priv->display.crtc_disable(&intel_crtc->base);
11219 }
11220
11221 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11222 * to set it here already despite that we pass it down the callchain.
11223 *
11224 * Note we'll need to fix this up when we start tracking multiple
11225 * pipes; here we assume a single modeset_pipe and only track the
11226 * single crtc and mode.
11227 */
11228 if (modeset_pipes) {
11229 crtc->mode = *mode;
11230 /* mode_set/enable/disable functions rely on a correct pipe
11231 * config. */
11232 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11233
11234 /*
11235 * Calculate and store various constants which
11236 * are later needed by vblank and swap-completion
11237 * timestamping. They are derived from true hwmode.
11238 */
11239 drm_calc_timestamping_constants(crtc,
11240 &pipe_config->base.adjusted_mode);
11241 }
11242
11243 /* Only after disabling all output pipelines that will be changed can we
11244 * update the the output configuration. */
11245 intel_modeset_update_state(dev, prepare_pipes);
11246
11247 modeset_update_crtc_power_domains(dev);
11248
11249 /* Set up the DPLL and any encoders state that needs to adjust or depend
11250 * on the DPLL.
11251 */
11252 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11253 struct drm_plane *primary = intel_crtc->base.primary;
11254 int vdisplay, hdisplay;
11255
11256 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11257 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11258 fb, 0, 0,
11259 hdisplay, vdisplay,
11260 x << 16, y << 16,
11261 hdisplay << 16, vdisplay << 16);
11262 }
11263
11264 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11265 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11266 update_scanline_offset(intel_crtc);
11267
11268 dev_priv->display.crtc_enable(&intel_crtc->base);
11269 }
11270
11271 /* FIXME: add subpixel order */
11272 done:
11273 if (ret && crtc->state->enable)
11274 crtc->mode = *saved_mode;
11275
11276 kfree(saved_mode);
11277 return ret;
11278 }
11279
11280 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11281 struct drm_display_mode *mode,
11282 int x, int y, struct drm_framebuffer *fb,
11283 struct intel_crtc_state *pipe_config,
11284 unsigned modeset_pipes,
11285 unsigned prepare_pipes,
11286 unsigned disable_pipes)
11287 {
11288 int ret;
11289
11290 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11291 prepare_pipes, disable_pipes);
11292
11293 if (ret == 0)
11294 intel_modeset_check_state(crtc->dev);
11295
11296 return ret;
11297 }
11298
11299 static int intel_set_mode(struct drm_crtc *crtc,
11300 struct drm_display_mode *mode,
11301 int x, int y, struct drm_framebuffer *fb)
11302 {
11303 struct intel_crtc_state *pipe_config;
11304 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11305
11306 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11307 &modeset_pipes,
11308 &prepare_pipes,
11309 &disable_pipes);
11310
11311 if (IS_ERR(pipe_config))
11312 return PTR_ERR(pipe_config);
11313
11314 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11315 modeset_pipes, prepare_pipes,
11316 disable_pipes);
11317 }
11318
11319 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11320 {
11321 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11322 }
11323
11324 #undef for_each_intel_crtc_masked
11325
11326 static void intel_set_config_free(struct intel_set_config *config)
11327 {
11328 if (!config)
11329 return;
11330
11331 kfree(config->save_connector_encoders);
11332 kfree(config->save_encoder_crtcs);
11333 kfree(config->save_crtc_enabled);
11334 kfree(config);
11335 }
11336
11337 static int intel_set_config_save_state(struct drm_device *dev,
11338 struct intel_set_config *config)
11339 {
11340 struct drm_crtc *crtc;
11341 struct drm_encoder *encoder;
11342 struct drm_connector *connector;
11343 int count;
11344
11345 config->save_crtc_enabled =
11346 kcalloc(dev->mode_config.num_crtc,
11347 sizeof(bool), GFP_KERNEL);
11348 if (!config->save_crtc_enabled)
11349 return -ENOMEM;
11350
11351 config->save_encoder_crtcs =
11352 kcalloc(dev->mode_config.num_encoder,
11353 sizeof(struct drm_crtc *), GFP_KERNEL);
11354 if (!config->save_encoder_crtcs)
11355 return -ENOMEM;
11356
11357 config->save_connector_encoders =
11358 kcalloc(dev->mode_config.num_connector,
11359 sizeof(struct drm_encoder *), GFP_KERNEL);
11360 if (!config->save_connector_encoders)
11361 return -ENOMEM;
11362
11363 /* Copy data. Note that driver private data is not affected.
11364 * Should anything bad happen only the expected state is
11365 * restored, not the drivers personal bookkeeping.
11366 */
11367 count = 0;
11368 for_each_crtc(dev, crtc) {
11369 config->save_crtc_enabled[count++] = crtc->state->enable;
11370 }
11371
11372 count = 0;
11373 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11374 config->save_encoder_crtcs[count++] = encoder->crtc;
11375 }
11376
11377 count = 0;
11378 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11379 config->save_connector_encoders[count++] = connector->encoder;
11380 }
11381
11382 return 0;
11383 }
11384
11385 static void intel_set_config_restore_state(struct drm_device *dev,
11386 struct intel_set_config *config)
11387 {
11388 struct intel_crtc *crtc;
11389 struct intel_encoder *encoder;
11390 struct intel_connector *connector;
11391 int count;
11392
11393 count = 0;
11394 for_each_intel_crtc(dev, crtc) {
11395 crtc->new_enabled = config->save_crtc_enabled[count++];
11396
11397 if (crtc->new_enabled)
11398 crtc->new_config = crtc->config;
11399 else
11400 crtc->new_config = NULL;
11401 }
11402
11403 count = 0;
11404 for_each_intel_encoder(dev, encoder) {
11405 encoder->new_crtc =
11406 to_intel_crtc(config->save_encoder_crtcs[count++]);
11407 }
11408
11409 count = 0;
11410 for_each_intel_connector(dev, connector) {
11411 connector->new_encoder =
11412 to_intel_encoder(config->save_connector_encoders[count++]);
11413 }
11414 }
11415
11416 static bool
11417 is_crtc_connector_off(struct drm_mode_set *set)
11418 {
11419 int i;
11420
11421 if (set->num_connectors == 0)
11422 return false;
11423
11424 if (WARN_ON(set->connectors == NULL))
11425 return false;
11426
11427 for (i = 0; i < set->num_connectors; i++)
11428 if (set->connectors[i]->encoder &&
11429 set->connectors[i]->encoder->crtc == set->crtc &&
11430 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11431 return true;
11432
11433 return false;
11434 }
11435
11436 static void
11437 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11438 struct intel_set_config *config)
11439 {
11440
11441 /* We should be able to check here if the fb has the same properties
11442 * and then just flip_or_move it */
11443 if (is_crtc_connector_off(set)) {
11444 config->mode_changed = true;
11445 } else if (set->crtc->primary->fb != set->fb) {
11446 /*
11447 * If we have no fb, we can only flip as long as the crtc is
11448 * active, otherwise we need a full mode set. The crtc may
11449 * be active if we've only disabled the primary plane, or
11450 * in fastboot situations.
11451 */
11452 if (set->crtc->primary->fb == NULL) {
11453 struct intel_crtc *intel_crtc =
11454 to_intel_crtc(set->crtc);
11455
11456 if (intel_crtc->active) {
11457 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11458 config->fb_changed = true;
11459 } else {
11460 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11461 config->mode_changed = true;
11462 }
11463 } else if (set->fb == NULL) {
11464 config->mode_changed = true;
11465 } else if (set->fb->pixel_format !=
11466 set->crtc->primary->fb->pixel_format) {
11467 config->mode_changed = true;
11468 } else {
11469 config->fb_changed = true;
11470 }
11471 }
11472
11473 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11474 config->fb_changed = true;
11475
11476 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11477 DRM_DEBUG_KMS("modes are different, full mode set\n");
11478 drm_mode_debug_printmodeline(&set->crtc->mode);
11479 drm_mode_debug_printmodeline(set->mode);
11480 config->mode_changed = true;
11481 }
11482
11483 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11484 set->crtc->base.id, config->mode_changed, config->fb_changed);
11485 }
11486
11487 static int
11488 intel_modeset_stage_output_state(struct drm_device *dev,
11489 struct drm_mode_set *set,
11490 struct intel_set_config *config)
11491 {
11492 struct intel_connector *connector;
11493 struct intel_encoder *encoder;
11494 struct intel_crtc *crtc;
11495 int ro;
11496
11497 /* The upper layers ensure that we either disable a crtc or have a list
11498 * of connectors. For paranoia, double-check this. */
11499 WARN_ON(!set->fb && (set->num_connectors != 0));
11500 WARN_ON(set->fb && (set->num_connectors == 0));
11501
11502 for_each_intel_connector(dev, connector) {
11503 /* Otherwise traverse passed in connector list and get encoders
11504 * for them. */
11505 for (ro = 0; ro < set->num_connectors; ro++) {
11506 if (set->connectors[ro] == &connector->base) {
11507 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11508 break;
11509 }
11510 }
11511
11512 /* If we disable the crtc, disable all its connectors. Also, if
11513 * the connector is on the changing crtc but not on the new
11514 * connector list, disable it. */
11515 if ((!set->fb || ro == set->num_connectors) &&
11516 connector->base.encoder &&
11517 connector->base.encoder->crtc == set->crtc) {
11518 connector->new_encoder = NULL;
11519
11520 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11521 connector->base.base.id,
11522 connector->base.name);
11523 }
11524
11525
11526 if (&connector->new_encoder->base != connector->base.encoder) {
11527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11528 connector->base.base.id,
11529 connector->base.name);
11530 config->mode_changed = true;
11531 }
11532 }
11533 /* connector->new_encoder is now updated for all connectors. */
11534
11535 /* Update crtc of enabled connectors. */
11536 for_each_intel_connector(dev, connector) {
11537 struct drm_crtc *new_crtc;
11538
11539 if (!connector->new_encoder)
11540 continue;
11541
11542 new_crtc = connector->new_encoder->base.crtc;
11543
11544 for (ro = 0; ro < set->num_connectors; ro++) {
11545 if (set->connectors[ro] == &connector->base)
11546 new_crtc = set->crtc;
11547 }
11548
11549 /* Make sure the new CRTC will work with the encoder */
11550 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11551 new_crtc)) {
11552 return -EINVAL;
11553 }
11554 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11555
11556 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11557 connector->base.base.id,
11558 connector->base.name,
11559 new_crtc->base.id);
11560 }
11561
11562 /* Check for any encoders that needs to be disabled. */
11563 for_each_intel_encoder(dev, encoder) {
11564 int num_connectors = 0;
11565 for_each_intel_connector(dev, connector) {
11566 if (connector->new_encoder == encoder) {
11567 WARN_ON(!connector->new_encoder->new_crtc);
11568 num_connectors++;
11569 }
11570 }
11571
11572 if (num_connectors == 0)
11573 encoder->new_crtc = NULL;
11574 else if (num_connectors > 1)
11575 return -EINVAL;
11576
11577 /* Only now check for crtc changes so we don't miss encoders
11578 * that will be disabled. */
11579 if (&encoder->new_crtc->base != encoder->base.crtc) {
11580 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11581 encoder->base.base.id,
11582 encoder->base.name);
11583 config->mode_changed = true;
11584 }
11585 }
11586 /* Now we've also updated encoder->new_crtc for all encoders. */
11587 for_each_intel_connector(dev, connector) {
11588 if (connector->new_encoder)
11589 if (connector->new_encoder != connector->encoder)
11590 connector->encoder = connector->new_encoder;
11591 }
11592 for_each_intel_crtc(dev, crtc) {
11593 crtc->new_enabled = false;
11594
11595 for_each_intel_encoder(dev, encoder) {
11596 if (encoder->new_crtc == crtc) {
11597 crtc->new_enabled = true;
11598 break;
11599 }
11600 }
11601
11602 if (crtc->new_enabled != crtc->base.state->enable) {
11603 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11604 crtc->base.base.id,
11605 crtc->new_enabled ? "en" : "dis");
11606 config->mode_changed = true;
11607 }
11608
11609 if (crtc->new_enabled)
11610 crtc->new_config = crtc->config;
11611 else
11612 crtc->new_config = NULL;
11613 }
11614
11615 return 0;
11616 }
11617
11618 static void disable_crtc_nofb(struct intel_crtc *crtc)
11619 {
11620 struct drm_device *dev = crtc->base.dev;
11621 struct intel_encoder *encoder;
11622 struct intel_connector *connector;
11623
11624 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11625 pipe_name(crtc->pipe));
11626
11627 for_each_intel_connector(dev, connector) {
11628 if (connector->new_encoder &&
11629 connector->new_encoder->new_crtc == crtc)
11630 connector->new_encoder = NULL;
11631 }
11632
11633 for_each_intel_encoder(dev, encoder) {
11634 if (encoder->new_crtc == crtc)
11635 encoder->new_crtc = NULL;
11636 }
11637
11638 crtc->new_enabled = false;
11639 crtc->new_config = NULL;
11640 }
11641
11642 static int intel_crtc_set_config(struct drm_mode_set *set)
11643 {
11644 struct drm_device *dev;
11645 struct drm_mode_set save_set;
11646 struct intel_set_config *config;
11647 struct intel_crtc_state *pipe_config;
11648 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11649 int ret;
11650
11651 BUG_ON(!set);
11652 BUG_ON(!set->crtc);
11653 BUG_ON(!set->crtc->helper_private);
11654
11655 /* Enforce sane interface api - has been abused by the fb helper. */
11656 BUG_ON(!set->mode && set->fb);
11657 BUG_ON(set->fb && set->num_connectors == 0);
11658
11659 if (set->fb) {
11660 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11661 set->crtc->base.id, set->fb->base.id,
11662 (int)set->num_connectors, set->x, set->y);
11663 } else {
11664 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11665 }
11666
11667 dev = set->crtc->dev;
11668
11669 ret = -ENOMEM;
11670 config = kzalloc(sizeof(*config), GFP_KERNEL);
11671 if (!config)
11672 goto out_config;
11673
11674 ret = intel_set_config_save_state(dev, config);
11675 if (ret)
11676 goto out_config;
11677
11678 save_set.crtc = set->crtc;
11679 save_set.mode = &set->crtc->mode;
11680 save_set.x = set->crtc->x;
11681 save_set.y = set->crtc->y;
11682 save_set.fb = set->crtc->primary->fb;
11683
11684 /* Compute whether we need a full modeset, only an fb base update or no
11685 * change at all. In the future we might also check whether only the
11686 * mode changed, e.g. for LVDS where we only change the panel fitter in
11687 * such cases. */
11688 intel_set_config_compute_mode_changes(set, config);
11689
11690 ret = intel_modeset_stage_output_state(dev, set, config);
11691 if (ret)
11692 goto fail;
11693
11694 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11695 set->fb,
11696 &modeset_pipes,
11697 &prepare_pipes,
11698 &disable_pipes);
11699 if (IS_ERR(pipe_config)) {
11700 ret = PTR_ERR(pipe_config);
11701 goto fail;
11702 } else if (pipe_config) {
11703 if (pipe_config->has_audio !=
11704 to_intel_crtc(set->crtc)->config->has_audio)
11705 config->mode_changed = true;
11706
11707 /*
11708 * Note we have an issue here with infoframes: current code
11709 * only updates them on the full mode set path per hw
11710 * requirements. So here we should be checking for any
11711 * required changes and forcing a mode set.
11712 */
11713 }
11714
11715 /* set_mode will free it in the mode_changed case */
11716 if (!config->mode_changed)
11717 kfree(pipe_config);
11718
11719 intel_update_pipe_size(to_intel_crtc(set->crtc));
11720
11721 if (config->mode_changed) {
11722 ret = intel_set_mode_pipes(set->crtc, set->mode,
11723 set->x, set->y, set->fb, pipe_config,
11724 modeset_pipes, prepare_pipes,
11725 disable_pipes);
11726 } else if (config->fb_changed) {
11727 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11728 struct drm_plane *primary = set->crtc->primary;
11729 int vdisplay, hdisplay;
11730
11731 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11732 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11733 0, 0, hdisplay, vdisplay,
11734 set->x << 16, set->y << 16,
11735 hdisplay << 16, vdisplay << 16);
11736
11737 /*
11738 * We need to make sure the primary plane is re-enabled if it
11739 * has previously been turned off.
11740 */
11741 if (!intel_crtc->primary_enabled && ret == 0) {
11742 WARN_ON(!intel_crtc->active);
11743 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11744 }
11745
11746 /*
11747 * In the fastboot case this may be our only check of the
11748 * state after boot. It would be better to only do it on
11749 * the first update, but we don't have a nice way of doing that
11750 * (and really, set_config isn't used much for high freq page
11751 * flipping, so increasing its cost here shouldn't be a big
11752 * deal).
11753 */
11754 if (i915.fastboot && ret == 0)
11755 intel_modeset_check_state(set->crtc->dev);
11756 }
11757
11758 if (ret) {
11759 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11760 set->crtc->base.id, ret);
11761 fail:
11762 intel_set_config_restore_state(dev, config);
11763
11764 /*
11765 * HACK: if the pipe was on, but we didn't have a framebuffer,
11766 * force the pipe off to avoid oopsing in the modeset code
11767 * due to fb==NULL. This should only happen during boot since
11768 * we don't yet reconstruct the FB from the hardware state.
11769 */
11770 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11771 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11772
11773 /* Try to restore the config */
11774 if (config->mode_changed &&
11775 intel_set_mode(save_set.crtc, save_set.mode,
11776 save_set.x, save_set.y, save_set.fb))
11777 DRM_ERROR("failed to restore config after modeset failure\n");
11778 }
11779
11780 out_config:
11781 intel_set_config_free(config);
11782 return ret;
11783 }
11784
11785 static const struct drm_crtc_funcs intel_crtc_funcs = {
11786 .gamma_set = intel_crtc_gamma_set,
11787 .set_config = intel_crtc_set_config,
11788 .destroy = intel_crtc_destroy,
11789 .page_flip = intel_crtc_page_flip,
11790 .atomic_duplicate_state = intel_crtc_duplicate_state,
11791 .atomic_destroy_state = intel_crtc_destroy_state,
11792 };
11793
11794 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11795 struct intel_shared_dpll *pll,
11796 struct intel_dpll_hw_state *hw_state)
11797 {
11798 uint32_t val;
11799
11800 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11801 return false;
11802
11803 val = I915_READ(PCH_DPLL(pll->id));
11804 hw_state->dpll = val;
11805 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11806 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11807
11808 return val & DPLL_VCO_ENABLE;
11809 }
11810
11811 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11812 struct intel_shared_dpll *pll)
11813 {
11814 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11815 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11816 }
11817
11818 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11819 struct intel_shared_dpll *pll)
11820 {
11821 /* PCH refclock must be enabled first */
11822 ibx_assert_pch_refclk_enabled(dev_priv);
11823
11824 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11825
11826 /* Wait for the clocks to stabilize. */
11827 POSTING_READ(PCH_DPLL(pll->id));
11828 udelay(150);
11829
11830 /* The pixel multiplier can only be updated once the
11831 * DPLL is enabled and the clocks are stable.
11832 *
11833 * So write it again.
11834 */
11835 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11836 POSTING_READ(PCH_DPLL(pll->id));
11837 udelay(200);
11838 }
11839
11840 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11841 struct intel_shared_dpll *pll)
11842 {
11843 struct drm_device *dev = dev_priv->dev;
11844 struct intel_crtc *crtc;
11845
11846 /* Make sure no transcoder isn't still depending on us. */
11847 for_each_intel_crtc(dev, crtc) {
11848 if (intel_crtc_to_shared_dpll(crtc) == pll)
11849 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11850 }
11851
11852 I915_WRITE(PCH_DPLL(pll->id), 0);
11853 POSTING_READ(PCH_DPLL(pll->id));
11854 udelay(200);
11855 }
11856
11857 static char *ibx_pch_dpll_names[] = {
11858 "PCH DPLL A",
11859 "PCH DPLL B",
11860 };
11861
11862 static void ibx_pch_dpll_init(struct drm_device *dev)
11863 {
11864 struct drm_i915_private *dev_priv = dev->dev_private;
11865 int i;
11866
11867 dev_priv->num_shared_dpll = 2;
11868
11869 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11870 dev_priv->shared_dplls[i].id = i;
11871 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11872 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11873 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11874 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11875 dev_priv->shared_dplls[i].get_hw_state =
11876 ibx_pch_dpll_get_hw_state;
11877 }
11878 }
11879
11880 static void intel_shared_dpll_init(struct drm_device *dev)
11881 {
11882 struct drm_i915_private *dev_priv = dev->dev_private;
11883
11884 if (HAS_DDI(dev))
11885 intel_ddi_pll_init(dev);
11886 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11887 ibx_pch_dpll_init(dev);
11888 else
11889 dev_priv->num_shared_dpll = 0;
11890
11891 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11892 }
11893
11894 /**
11895 * intel_prepare_plane_fb - Prepare fb for usage on plane
11896 * @plane: drm plane to prepare for
11897 * @fb: framebuffer to prepare for presentation
11898 *
11899 * Prepares a framebuffer for usage on a display plane. Generally this
11900 * involves pinning the underlying object and updating the frontbuffer tracking
11901 * bits. Some older platforms need special physical address handling for
11902 * cursor planes.
11903 *
11904 * Returns 0 on success, negative error code on failure.
11905 */
11906 int
11907 intel_prepare_plane_fb(struct drm_plane *plane,
11908 struct drm_framebuffer *fb,
11909 const struct drm_plane_state *new_state)
11910 {
11911 struct drm_device *dev = plane->dev;
11912 struct intel_plane *intel_plane = to_intel_plane(plane);
11913 enum pipe pipe = intel_plane->pipe;
11914 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11915 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11916 unsigned frontbuffer_bits = 0;
11917 int ret = 0;
11918
11919 if (!obj)
11920 return 0;
11921
11922 switch (plane->type) {
11923 case DRM_PLANE_TYPE_PRIMARY:
11924 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11925 break;
11926 case DRM_PLANE_TYPE_CURSOR:
11927 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11928 break;
11929 case DRM_PLANE_TYPE_OVERLAY:
11930 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11931 break;
11932 }
11933
11934 mutex_lock(&dev->struct_mutex);
11935
11936 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11937 INTEL_INFO(dev)->cursor_needs_physical) {
11938 int align = IS_I830(dev) ? 16 * 1024 : 256;
11939 ret = i915_gem_object_attach_phys(obj, align);
11940 if (ret)
11941 DRM_DEBUG_KMS("failed to attach phys object\n");
11942 } else {
11943 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11944 }
11945
11946 if (ret == 0)
11947 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11948
11949 mutex_unlock(&dev->struct_mutex);
11950
11951 return ret;
11952 }
11953
11954 /**
11955 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11956 * @plane: drm plane to clean up for
11957 * @fb: old framebuffer that was on plane
11958 *
11959 * Cleans up a framebuffer that has just been removed from a plane.
11960 */
11961 void
11962 intel_cleanup_plane_fb(struct drm_plane *plane,
11963 struct drm_framebuffer *fb,
11964 const struct drm_plane_state *old_state)
11965 {
11966 struct drm_device *dev = plane->dev;
11967 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11968
11969 if (WARN_ON(!obj))
11970 return;
11971
11972 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11973 !INTEL_INFO(dev)->cursor_needs_physical) {
11974 mutex_lock(&dev->struct_mutex);
11975 intel_unpin_fb_obj(obj);
11976 mutex_unlock(&dev->struct_mutex);
11977 }
11978 }
11979
11980 static int
11981 intel_check_primary_plane(struct drm_plane *plane,
11982 struct intel_plane_state *state)
11983 {
11984 struct drm_device *dev = plane->dev;
11985 struct drm_i915_private *dev_priv = dev->dev_private;
11986 struct drm_crtc *crtc = state->base.crtc;
11987 struct intel_crtc *intel_crtc;
11988 struct drm_framebuffer *fb = state->base.fb;
11989 struct drm_rect *dest = &state->dst;
11990 struct drm_rect *src = &state->src;
11991 const struct drm_rect *clip = &state->clip;
11992 int ret;
11993
11994 crtc = crtc ? crtc : plane->crtc;
11995 intel_crtc = to_intel_crtc(crtc);
11996
11997 ret = drm_plane_helper_check_update(plane, crtc, fb,
11998 src, dest, clip,
11999 DRM_PLANE_HELPER_NO_SCALING,
12000 DRM_PLANE_HELPER_NO_SCALING,
12001 false, true, &state->visible);
12002 if (ret)
12003 return ret;
12004
12005 if (intel_crtc->active) {
12006 intel_crtc->atomic.wait_for_flips = true;
12007
12008 /*
12009 * FBC does not work on some platforms for rotated
12010 * planes, so disable it when rotation is not 0 and
12011 * update it when rotation is set back to 0.
12012 *
12013 * FIXME: This is redundant with the fbc update done in
12014 * the primary plane enable function except that that
12015 * one is done too late. We eventually need to unify
12016 * this.
12017 */
12018 if (intel_crtc->primary_enabled &&
12019 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12020 dev_priv->fbc.crtc == intel_crtc &&
12021 state->base.rotation != BIT(DRM_ROTATE_0)) {
12022 intel_crtc->atomic.disable_fbc = true;
12023 }
12024
12025 if (state->visible) {
12026 /*
12027 * BDW signals flip done immediately if the plane
12028 * is disabled, even if the plane enable is already
12029 * armed to occur at the next vblank :(
12030 */
12031 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12032 intel_crtc->atomic.wait_vblank = true;
12033 }
12034
12035 intel_crtc->atomic.fb_bits |=
12036 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12037
12038 intel_crtc->atomic.update_fbc = true;
12039
12040 /* Update watermarks on tiling changes. */
12041 if (!plane->state->fb || !state->base.fb ||
12042 plane->state->fb->modifier[0] !=
12043 state->base.fb->modifier[0])
12044 intel_crtc->atomic.update_wm = true;
12045 }
12046
12047 return 0;
12048 }
12049
12050 static void
12051 intel_commit_primary_plane(struct drm_plane *plane,
12052 struct intel_plane_state *state)
12053 {
12054 struct drm_crtc *crtc = state->base.crtc;
12055 struct drm_framebuffer *fb = state->base.fb;
12056 struct drm_device *dev = plane->dev;
12057 struct drm_i915_private *dev_priv = dev->dev_private;
12058 struct intel_crtc *intel_crtc;
12059 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12060 struct intel_plane *intel_plane = to_intel_plane(plane);
12061 struct drm_rect *src = &state->src;
12062
12063 crtc = crtc ? crtc : plane->crtc;
12064 intel_crtc = to_intel_crtc(crtc);
12065
12066 plane->fb = fb;
12067 crtc->x = src->x1 >> 16;
12068 crtc->y = src->y1 >> 16;
12069
12070 intel_plane->obj = obj;
12071
12072 if (intel_crtc->active) {
12073 if (state->visible) {
12074 /* FIXME: kill this fastboot hack */
12075 intel_update_pipe_size(intel_crtc);
12076
12077 intel_crtc->primary_enabled = true;
12078
12079 dev_priv->display.update_primary_plane(crtc, plane->fb,
12080 crtc->x, crtc->y);
12081 } else {
12082 /*
12083 * If clipping results in a non-visible primary plane,
12084 * we'll disable the primary plane. Note that this is
12085 * a bit different than what happens if userspace
12086 * explicitly disables the plane by passing fb=0
12087 * because plane->fb still gets set and pinned.
12088 */
12089 intel_disable_primary_hw_plane(plane, crtc);
12090 }
12091 }
12092 }
12093
12094 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12095 {
12096 struct drm_device *dev = crtc->dev;
12097 struct drm_i915_private *dev_priv = dev->dev_private;
12098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12099 struct intel_plane *intel_plane;
12100 struct drm_plane *p;
12101 unsigned fb_bits = 0;
12102
12103 /* Track fb's for any planes being disabled */
12104 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12105 intel_plane = to_intel_plane(p);
12106
12107 if (intel_crtc->atomic.disabled_planes &
12108 (1 << drm_plane_index(p))) {
12109 switch (p->type) {
12110 case DRM_PLANE_TYPE_PRIMARY:
12111 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12112 break;
12113 case DRM_PLANE_TYPE_CURSOR:
12114 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12115 break;
12116 case DRM_PLANE_TYPE_OVERLAY:
12117 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12118 break;
12119 }
12120
12121 mutex_lock(&dev->struct_mutex);
12122 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12123 mutex_unlock(&dev->struct_mutex);
12124 }
12125 }
12126
12127 if (intel_crtc->atomic.wait_for_flips)
12128 intel_crtc_wait_for_pending_flips(crtc);
12129
12130 if (intel_crtc->atomic.disable_fbc)
12131 intel_fbc_disable(dev);
12132
12133 if (intel_crtc->atomic.pre_disable_primary)
12134 intel_pre_disable_primary(crtc);
12135
12136 if (intel_crtc->atomic.update_wm)
12137 intel_update_watermarks(crtc);
12138
12139 intel_runtime_pm_get(dev_priv);
12140
12141 /* Perform vblank evasion around commit operation */
12142 if (intel_crtc->active)
12143 intel_crtc->atomic.evade =
12144 intel_pipe_update_start(intel_crtc,
12145 &intel_crtc->atomic.start_vbl_count);
12146 }
12147
12148 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12149 {
12150 struct drm_device *dev = crtc->dev;
12151 struct drm_i915_private *dev_priv = dev->dev_private;
12152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12153 struct drm_plane *p;
12154
12155 if (intel_crtc->atomic.evade)
12156 intel_pipe_update_end(intel_crtc,
12157 intel_crtc->atomic.start_vbl_count);
12158
12159 intel_runtime_pm_put(dev_priv);
12160
12161 if (intel_crtc->atomic.wait_vblank)
12162 intel_wait_for_vblank(dev, intel_crtc->pipe);
12163
12164 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12165
12166 if (intel_crtc->atomic.update_fbc) {
12167 mutex_lock(&dev->struct_mutex);
12168 intel_fbc_update(dev);
12169 mutex_unlock(&dev->struct_mutex);
12170 }
12171
12172 if (intel_crtc->atomic.post_enable_primary)
12173 intel_post_enable_primary(crtc);
12174
12175 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12176 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12177 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12178 false, false);
12179
12180 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12181 }
12182
12183 /**
12184 * intel_plane_destroy - destroy a plane
12185 * @plane: plane to destroy
12186 *
12187 * Common destruction function for all types of planes (primary, cursor,
12188 * sprite).
12189 */
12190 void intel_plane_destroy(struct drm_plane *plane)
12191 {
12192 struct intel_plane *intel_plane = to_intel_plane(plane);
12193 drm_plane_cleanup(plane);
12194 kfree(intel_plane);
12195 }
12196
12197 const struct drm_plane_funcs intel_plane_funcs = {
12198 .update_plane = drm_plane_helper_update,
12199 .disable_plane = drm_plane_helper_disable,
12200 .destroy = intel_plane_destroy,
12201 .set_property = drm_atomic_helper_plane_set_property,
12202 .atomic_get_property = intel_plane_atomic_get_property,
12203 .atomic_set_property = intel_plane_atomic_set_property,
12204 .atomic_duplicate_state = intel_plane_duplicate_state,
12205 .atomic_destroy_state = intel_plane_destroy_state,
12206
12207 };
12208
12209 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12210 int pipe)
12211 {
12212 struct intel_plane *primary;
12213 struct intel_plane_state *state;
12214 const uint32_t *intel_primary_formats;
12215 int num_formats;
12216
12217 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12218 if (primary == NULL)
12219 return NULL;
12220
12221 state = intel_create_plane_state(&primary->base);
12222 if (!state) {
12223 kfree(primary);
12224 return NULL;
12225 }
12226 primary->base.state = &state->base;
12227
12228 primary->can_scale = false;
12229 primary->max_downscale = 1;
12230 primary->pipe = pipe;
12231 primary->plane = pipe;
12232 primary->check_plane = intel_check_primary_plane;
12233 primary->commit_plane = intel_commit_primary_plane;
12234 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12235 primary->plane = !pipe;
12236
12237 if (INTEL_INFO(dev)->gen <= 3) {
12238 intel_primary_formats = intel_primary_formats_gen2;
12239 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12240 } else {
12241 intel_primary_formats = intel_primary_formats_gen4;
12242 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12243 }
12244
12245 drm_universal_plane_init(dev, &primary->base, 0,
12246 &intel_plane_funcs,
12247 intel_primary_formats, num_formats,
12248 DRM_PLANE_TYPE_PRIMARY);
12249
12250 if (INTEL_INFO(dev)->gen >= 4) {
12251 if (!dev->mode_config.rotation_property)
12252 dev->mode_config.rotation_property =
12253 drm_mode_create_rotation_property(dev,
12254 BIT(DRM_ROTATE_0) |
12255 BIT(DRM_ROTATE_180));
12256 if (dev->mode_config.rotation_property)
12257 drm_object_attach_property(&primary->base.base,
12258 dev->mode_config.rotation_property,
12259 state->base.rotation);
12260 }
12261
12262 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12263
12264 return &primary->base;
12265 }
12266
12267 static int
12268 intel_check_cursor_plane(struct drm_plane *plane,
12269 struct intel_plane_state *state)
12270 {
12271 struct drm_crtc *crtc = state->base.crtc;
12272 struct drm_device *dev = plane->dev;
12273 struct drm_framebuffer *fb = state->base.fb;
12274 struct drm_rect *dest = &state->dst;
12275 struct drm_rect *src = &state->src;
12276 const struct drm_rect *clip = &state->clip;
12277 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12278 struct intel_crtc *intel_crtc;
12279 unsigned stride;
12280 int ret;
12281
12282 crtc = crtc ? crtc : plane->crtc;
12283 intel_crtc = to_intel_crtc(crtc);
12284
12285 ret = drm_plane_helper_check_update(plane, crtc, fb,
12286 src, dest, clip,
12287 DRM_PLANE_HELPER_NO_SCALING,
12288 DRM_PLANE_HELPER_NO_SCALING,
12289 true, true, &state->visible);
12290 if (ret)
12291 return ret;
12292
12293
12294 /* if we want to turn off the cursor ignore width and height */
12295 if (!obj)
12296 goto finish;
12297
12298 /* Check for which cursor types we support */
12299 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12300 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12301 state->base.crtc_w, state->base.crtc_h);
12302 return -EINVAL;
12303 }
12304
12305 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12306 if (obj->base.size < stride * state->base.crtc_h) {
12307 DRM_DEBUG_KMS("buffer is too small\n");
12308 return -ENOMEM;
12309 }
12310
12311 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12312 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12313 ret = -EINVAL;
12314 }
12315
12316 finish:
12317 if (intel_crtc->active) {
12318 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12319 intel_crtc->atomic.update_wm = true;
12320
12321 intel_crtc->atomic.fb_bits |=
12322 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12323 }
12324
12325 return ret;
12326 }
12327
12328 static void
12329 intel_commit_cursor_plane(struct drm_plane *plane,
12330 struct intel_plane_state *state)
12331 {
12332 struct drm_crtc *crtc = state->base.crtc;
12333 struct drm_device *dev = plane->dev;
12334 struct intel_crtc *intel_crtc;
12335 struct intel_plane *intel_plane = to_intel_plane(plane);
12336 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12337 uint32_t addr;
12338
12339 crtc = crtc ? crtc : plane->crtc;
12340 intel_crtc = to_intel_crtc(crtc);
12341
12342 plane->fb = state->base.fb;
12343 crtc->cursor_x = state->base.crtc_x;
12344 crtc->cursor_y = state->base.crtc_y;
12345
12346 intel_plane->obj = obj;
12347
12348 if (intel_crtc->cursor_bo == obj)
12349 goto update;
12350
12351 if (!obj)
12352 addr = 0;
12353 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12354 addr = i915_gem_obj_ggtt_offset(obj);
12355 else
12356 addr = obj->phys_handle->busaddr;
12357
12358 intel_crtc->cursor_addr = addr;
12359 intel_crtc->cursor_bo = obj;
12360 update:
12361
12362 if (intel_crtc->active)
12363 intel_crtc_update_cursor(crtc, state->visible);
12364 }
12365
12366 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12367 int pipe)
12368 {
12369 struct intel_plane *cursor;
12370 struct intel_plane_state *state;
12371
12372 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12373 if (cursor == NULL)
12374 return NULL;
12375
12376 state = intel_create_plane_state(&cursor->base);
12377 if (!state) {
12378 kfree(cursor);
12379 return NULL;
12380 }
12381 cursor->base.state = &state->base;
12382
12383 cursor->can_scale = false;
12384 cursor->max_downscale = 1;
12385 cursor->pipe = pipe;
12386 cursor->plane = pipe;
12387 cursor->check_plane = intel_check_cursor_plane;
12388 cursor->commit_plane = intel_commit_cursor_plane;
12389
12390 drm_universal_plane_init(dev, &cursor->base, 0,
12391 &intel_plane_funcs,
12392 intel_cursor_formats,
12393 ARRAY_SIZE(intel_cursor_formats),
12394 DRM_PLANE_TYPE_CURSOR);
12395
12396 if (INTEL_INFO(dev)->gen >= 4) {
12397 if (!dev->mode_config.rotation_property)
12398 dev->mode_config.rotation_property =
12399 drm_mode_create_rotation_property(dev,
12400 BIT(DRM_ROTATE_0) |
12401 BIT(DRM_ROTATE_180));
12402 if (dev->mode_config.rotation_property)
12403 drm_object_attach_property(&cursor->base.base,
12404 dev->mode_config.rotation_property,
12405 state->base.rotation);
12406 }
12407
12408 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12409
12410 return &cursor->base;
12411 }
12412
12413 static void intel_crtc_init(struct drm_device *dev, int pipe)
12414 {
12415 struct drm_i915_private *dev_priv = dev->dev_private;
12416 struct intel_crtc *intel_crtc;
12417 struct intel_crtc_state *crtc_state = NULL;
12418 struct drm_plane *primary = NULL;
12419 struct drm_plane *cursor = NULL;
12420 int i, ret;
12421
12422 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12423 if (intel_crtc == NULL)
12424 return;
12425
12426 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12427 if (!crtc_state)
12428 goto fail;
12429 intel_crtc_set_state(intel_crtc, crtc_state);
12430 crtc_state->base.crtc = &intel_crtc->base;
12431
12432 primary = intel_primary_plane_create(dev, pipe);
12433 if (!primary)
12434 goto fail;
12435
12436 cursor = intel_cursor_plane_create(dev, pipe);
12437 if (!cursor)
12438 goto fail;
12439
12440 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12441 cursor, &intel_crtc_funcs);
12442 if (ret)
12443 goto fail;
12444
12445 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12446 for (i = 0; i < 256; i++) {
12447 intel_crtc->lut_r[i] = i;
12448 intel_crtc->lut_g[i] = i;
12449 intel_crtc->lut_b[i] = i;
12450 }
12451
12452 /*
12453 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12454 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12455 */
12456 intel_crtc->pipe = pipe;
12457 intel_crtc->plane = pipe;
12458 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12459 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12460 intel_crtc->plane = !pipe;
12461 }
12462
12463 intel_crtc->cursor_base = ~0;
12464 intel_crtc->cursor_cntl = ~0;
12465 intel_crtc->cursor_size = ~0;
12466
12467 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12468 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12469 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12470 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12471
12472 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12473
12474 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12475
12476 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12477 return;
12478
12479 fail:
12480 if (primary)
12481 drm_plane_cleanup(primary);
12482 if (cursor)
12483 drm_plane_cleanup(cursor);
12484 kfree(crtc_state);
12485 kfree(intel_crtc);
12486 }
12487
12488 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12489 {
12490 struct drm_encoder *encoder = connector->base.encoder;
12491 struct drm_device *dev = connector->base.dev;
12492
12493 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12494
12495 if (!encoder || WARN_ON(!encoder->crtc))
12496 return INVALID_PIPE;
12497
12498 return to_intel_crtc(encoder->crtc)->pipe;
12499 }
12500
12501 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12502 struct drm_file *file)
12503 {
12504 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12505 struct drm_crtc *drmmode_crtc;
12506 struct intel_crtc *crtc;
12507
12508 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12509
12510 if (!drmmode_crtc) {
12511 DRM_ERROR("no such CRTC id\n");
12512 return -ENOENT;
12513 }
12514
12515 crtc = to_intel_crtc(drmmode_crtc);
12516 pipe_from_crtc_id->pipe = crtc->pipe;
12517
12518 return 0;
12519 }
12520
12521 static int intel_encoder_clones(struct intel_encoder *encoder)
12522 {
12523 struct drm_device *dev = encoder->base.dev;
12524 struct intel_encoder *source_encoder;
12525 int index_mask = 0;
12526 int entry = 0;
12527
12528 for_each_intel_encoder(dev, source_encoder) {
12529 if (encoders_cloneable(encoder, source_encoder))
12530 index_mask |= (1 << entry);
12531
12532 entry++;
12533 }
12534
12535 return index_mask;
12536 }
12537
12538 static bool has_edp_a(struct drm_device *dev)
12539 {
12540 struct drm_i915_private *dev_priv = dev->dev_private;
12541
12542 if (!IS_MOBILE(dev))
12543 return false;
12544
12545 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12546 return false;
12547
12548 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12549 return false;
12550
12551 return true;
12552 }
12553
12554 static bool intel_crt_present(struct drm_device *dev)
12555 {
12556 struct drm_i915_private *dev_priv = dev->dev_private;
12557
12558 if (INTEL_INFO(dev)->gen >= 9)
12559 return false;
12560
12561 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12562 return false;
12563
12564 if (IS_CHERRYVIEW(dev))
12565 return false;
12566
12567 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12568 return false;
12569
12570 return true;
12571 }
12572
12573 static void intel_setup_outputs(struct drm_device *dev)
12574 {
12575 struct drm_i915_private *dev_priv = dev->dev_private;
12576 struct intel_encoder *encoder;
12577 struct drm_connector *connector;
12578 bool dpd_is_edp = false;
12579
12580 intel_lvds_init(dev);
12581
12582 if (intel_crt_present(dev))
12583 intel_crt_init(dev);
12584
12585 if (HAS_DDI(dev)) {
12586 int found;
12587
12588 /*
12589 * Haswell uses DDI functions to detect digital outputs.
12590 * On SKL pre-D0 the strap isn't connected, so we assume
12591 * it's there.
12592 */
12593 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12594 /* WaIgnoreDDIAStrap: skl */
12595 if (found ||
12596 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12597 intel_ddi_init(dev, PORT_A);
12598
12599 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12600 * register */
12601 found = I915_READ(SFUSE_STRAP);
12602
12603 if (found & SFUSE_STRAP_DDIB_DETECTED)
12604 intel_ddi_init(dev, PORT_B);
12605 if (found & SFUSE_STRAP_DDIC_DETECTED)
12606 intel_ddi_init(dev, PORT_C);
12607 if (found & SFUSE_STRAP_DDID_DETECTED)
12608 intel_ddi_init(dev, PORT_D);
12609 } else if (HAS_PCH_SPLIT(dev)) {
12610 int found;
12611 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12612
12613 if (has_edp_a(dev))
12614 intel_dp_init(dev, DP_A, PORT_A);
12615
12616 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12617 /* PCH SDVOB multiplex with HDMIB */
12618 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12619 if (!found)
12620 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12621 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12622 intel_dp_init(dev, PCH_DP_B, PORT_B);
12623 }
12624
12625 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12626 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12627
12628 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12629 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12630
12631 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12632 intel_dp_init(dev, PCH_DP_C, PORT_C);
12633
12634 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12635 intel_dp_init(dev, PCH_DP_D, PORT_D);
12636 } else if (IS_VALLEYVIEW(dev)) {
12637 /*
12638 * The DP_DETECTED bit is the latched state of the DDC
12639 * SDA pin at boot. However since eDP doesn't require DDC
12640 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12641 * eDP ports may have been muxed to an alternate function.
12642 * Thus we can't rely on the DP_DETECTED bit alone to detect
12643 * eDP ports. Consult the VBT as well as DP_DETECTED to
12644 * detect eDP ports.
12645 */
12646 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12647 !intel_dp_is_edp(dev, PORT_B))
12648 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12649 PORT_B);
12650 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12651 intel_dp_is_edp(dev, PORT_B))
12652 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12653
12654 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12655 !intel_dp_is_edp(dev, PORT_C))
12656 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12657 PORT_C);
12658 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12659 intel_dp_is_edp(dev, PORT_C))
12660 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12661
12662 if (IS_CHERRYVIEW(dev)) {
12663 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12664 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12665 PORT_D);
12666 /* eDP not supported on port D, so don't check VBT */
12667 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12668 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12669 }
12670
12671 intel_dsi_init(dev);
12672 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12673 bool found = false;
12674
12675 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12676 DRM_DEBUG_KMS("probing SDVOB\n");
12677 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12678 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12679 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12680 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12681 }
12682
12683 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12684 intel_dp_init(dev, DP_B, PORT_B);
12685 }
12686
12687 /* Before G4X SDVOC doesn't have its own detect register */
12688
12689 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12690 DRM_DEBUG_KMS("probing SDVOC\n");
12691 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12692 }
12693
12694 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12695
12696 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12697 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12698 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12699 }
12700 if (SUPPORTS_INTEGRATED_DP(dev))
12701 intel_dp_init(dev, DP_C, PORT_C);
12702 }
12703
12704 if (SUPPORTS_INTEGRATED_DP(dev) &&
12705 (I915_READ(DP_D) & DP_DETECTED))
12706 intel_dp_init(dev, DP_D, PORT_D);
12707 } else if (IS_GEN2(dev))
12708 intel_dvo_init(dev);
12709
12710 if (SUPPORTS_TV(dev))
12711 intel_tv_init(dev);
12712
12713 /*
12714 * FIXME: We don't have full atomic support yet, but we want to be
12715 * able to enable/test plane updates via the atomic interface in the
12716 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12717 * will take some atomic codepaths to lookup properties during
12718 * drmModeGetConnector() that unconditionally dereference
12719 * connector->state.
12720 *
12721 * We create a dummy connector state here for each connector to ensure
12722 * the DRM core doesn't try to dereference a NULL connector->state.
12723 * The actual connector properties will never be updated or contain
12724 * useful information, but since we're doing this specifically for
12725 * testing/debug of the plane operations (and only when a specific
12726 * kernel module option is given), that shouldn't really matter.
12727 *
12728 * Once atomic support for crtc's + connectors lands, this loop should
12729 * be removed since we'll be setting up real connector state, which
12730 * will contain Intel-specific properties.
12731 */
12732 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12733 list_for_each_entry(connector,
12734 &dev->mode_config.connector_list,
12735 head) {
12736 if (!WARN_ON(connector->state)) {
12737 connector->state =
12738 kzalloc(sizeof(*connector->state),
12739 GFP_KERNEL);
12740 }
12741 }
12742 }
12743
12744 intel_psr_init(dev);
12745
12746 for_each_intel_encoder(dev, encoder) {
12747 encoder->base.possible_crtcs = encoder->crtc_mask;
12748 encoder->base.possible_clones =
12749 intel_encoder_clones(encoder);
12750 }
12751
12752 intel_init_pch_refclk(dev);
12753
12754 drm_helper_move_panel_connectors_to_head(dev);
12755 }
12756
12757 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12758 {
12759 struct drm_device *dev = fb->dev;
12760 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12761
12762 drm_framebuffer_cleanup(fb);
12763 mutex_lock(&dev->struct_mutex);
12764 WARN_ON(!intel_fb->obj->framebuffer_references--);
12765 drm_gem_object_unreference(&intel_fb->obj->base);
12766 mutex_unlock(&dev->struct_mutex);
12767 kfree(intel_fb);
12768 }
12769
12770 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12771 struct drm_file *file,
12772 unsigned int *handle)
12773 {
12774 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12775 struct drm_i915_gem_object *obj = intel_fb->obj;
12776
12777 return drm_gem_handle_create(file, &obj->base, handle);
12778 }
12779
12780 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12781 .destroy = intel_user_framebuffer_destroy,
12782 .create_handle = intel_user_framebuffer_create_handle,
12783 };
12784
12785 static
12786 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12787 uint32_t pixel_format)
12788 {
12789 u32 gen = INTEL_INFO(dev)->gen;
12790
12791 if (gen >= 9) {
12792 /* "The stride in bytes must not exceed the of the size of 8K
12793 * pixels and 32K bytes."
12794 */
12795 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12796 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12797 return 32*1024;
12798 } else if (gen >= 4) {
12799 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12800 return 16*1024;
12801 else
12802 return 32*1024;
12803 } else if (gen >= 3) {
12804 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12805 return 8*1024;
12806 else
12807 return 16*1024;
12808 } else {
12809 /* XXX DSPC is limited to 4k tiled */
12810 return 8*1024;
12811 }
12812 }
12813
12814 static int intel_framebuffer_init(struct drm_device *dev,
12815 struct intel_framebuffer *intel_fb,
12816 struct drm_mode_fb_cmd2 *mode_cmd,
12817 struct drm_i915_gem_object *obj)
12818 {
12819 int aligned_height;
12820 int ret;
12821 u32 pitch_limit, stride_alignment;
12822
12823 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12824
12825 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12826 /* Enforce that fb modifier and tiling mode match, but only for
12827 * X-tiled. This is needed for FBC. */
12828 if (!!(obj->tiling_mode == I915_TILING_X) !=
12829 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12830 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12831 return -EINVAL;
12832 }
12833 } else {
12834 if (obj->tiling_mode == I915_TILING_X)
12835 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12836 else if (obj->tiling_mode == I915_TILING_Y) {
12837 DRM_DEBUG("No Y tiling for legacy addfb\n");
12838 return -EINVAL;
12839 }
12840 }
12841
12842 /* Passed in modifier sanity checking. */
12843 switch (mode_cmd->modifier[0]) {
12844 case I915_FORMAT_MOD_Y_TILED:
12845 case I915_FORMAT_MOD_Yf_TILED:
12846 if (INTEL_INFO(dev)->gen < 9) {
12847 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12848 mode_cmd->modifier[0]);
12849 return -EINVAL;
12850 }
12851 case DRM_FORMAT_MOD_NONE:
12852 case I915_FORMAT_MOD_X_TILED:
12853 break;
12854 default:
12855 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12856 mode_cmd->modifier[0]);
12857 return -EINVAL;
12858 }
12859
12860 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12861 mode_cmd->pixel_format);
12862 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12863 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12864 mode_cmd->pitches[0], stride_alignment);
12865 return -EINVAL;
12866 }
12867
12868 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12869 mode_cmd->pixel_format);
12870 if (mode_cmd->pitches[0] > pitch_limit) {
12871 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12872 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12873 "tiled" : "linear",
12874 mode_cmd->pitches[0], pitch_limit);
12875 return -EINVAL;
12876 }
12877
12878 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12879 mode_cmd->pitches[0] != obj->stride) {
12880 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12881 mode_cmd->pitches[0], obj->stride);
12882 return -EINVAL;
12883 }
12884
12885 /* Reject formats not supported by any plane early. */
12886 switch (mode_cmd->pixel_format) {
12887 case DRM_FORMAT_C8:
12888 case DRM_FORMAT_RGB565:
12889 case DRM_FORMAT_XRGB8888:
12890 case DRM_FORMAT_ARGB8888:
12891 break;
12892 case DRM_FORMAT_XRGB1555:
12893 case DRM_FORMAT_ARGB1555:
12894 if (INTEL_INFO(dev)->gen > 3) {
12895 DRM_DEBUG("unsupported pixel format: %s\n",
12896 drm_get_format_name(mode_cmd->pixel_format));
12897 return -EINVAL;
12898 }
12899 break;
12900 case DRM_FORMAT_XBGR8888:
12901 case DRM_FORMAT_ABGR8888:
12902 case DRM_FORMAT_XRGB2101010:
12903 case DRM_FORMAT_ARGB2101010:
12904 case DRM_FORMAT_XBGR2101010:
12905 case DRM_FORMAT_ABGR2101010:
12906 if (INTEL_INFO(dev)->gen < 4) {
12907 DRM_DEBUG("unsupported pixel format: %s\n",
12908 drm_get_format_name(mode_cmd->pixel_format));
12909 return -EINVAL;
12910 }
12911 break;
12912 case DRM_FORMAT_YUYV:
12913 case DRM_FORMAT_UYVY:
12914 case DRM_FORMAT_YVYU:
12915 case DRM_FORMAT_VYUY:
12916 if (INTEL_INFO(dev)->gen < 5) {
12917 DRM_DEBUG("unsupported pixel format: %s\n",
12918 drm_get_format_name(mode_cmd->pixel_format));
12919 return -EINVAL;
12920 }
12921 break;
12922 default:
12923 DRM_DEBUG("unsupported pixel format: %s\n",
12924 drm_get_format_name(mode_cmd->pixel_format));
12925 return -EINVAL;
12926 }
12927
12928 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12929 if (mode_cmd->offsets[0] != 0)
12930 return -EINVAL;
12931
12932 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12933 mode_cmd->pixel_format,
12934 mode_cmd->modifier[0]);
12935 /* FIXME drm helper for size checks (especially planar formats)? */
12936 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12937 return -EINVAL;
12938
12939 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12940 intel_fb->obj = obj;
12941 intel_fb->obj->framebuffer_references++;
12942
12943 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12944 if (ret) {
12945 DRM_ERROR("framebuffer init failed %d\n", ret);
12946 return ret;
12947 }
12948
12949 return 0;
12950 }
12951
12952 static struct drm_framebuffer *
12953 intel_user_framebuffer_create(struct drm_device *dev,
12954 struct drm_file *filp,
12955 struct drm_mode_fb_cmd2 *mode_cmd)
12956 {
12957 struct drm_i915_gem_object *obj;
12958
12959 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12960 mode_cmd->handles[0]));
12961 if (&obj->base == NULL)
12962 return ERR_PTR(-ENOENT);
12963
12964 return intel_framebuffer_create(dev, mode_cmd, obj);
12965 }
12966
12967 #ifndef CONFIG_DRM_I915_FBDEV
12968 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12969 {
12970 }
12971 #endif
12972
12973 static const struct drm_mode_config_funcs intel_mode_funcs = {
12974 .fb_create = intel_user_framebuffer_create,
12975 .output_poll_changed = intel_fbdev_output_poll_changed,
12976 .atomic_check = intel_atomic_check,
12977 .atomic_commit = intel_atomic_commit,
12978 };
12979
12980 /* Set up chip specific display functions */
12981 static void intel_init_display(struct drm_device *dev)
12982 {
12983 struct drm_i915_private *dev_priv = dev->dev_private;
12984
12985 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12986 dev_priv->display.find_dpll = g4x_find_best_dpll;
12987 else if (IS_CHERRYVIEW(dev))
12988 dev_priv->display.find_dpll = chv_find_best_dpll;
12989 else if (IS_VALLEYVIEW(dev))
12990 dev_priv->display.find_dpll = vlv_find_best_dpll;
12991 else if (IS_PINEVIEW(dev))
12992 dev_priv->display.find_dpll = pnv_find_best_dpll;
12993 else
12994 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12995
12996 if (INTEL_INFO(dev)->gen >= 9) {
12997 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12998 dev_priv->display.get_initial_plane_config =
12999 skylake_get_initial_plane_config;
13000 dev_priv->display.crtc_compute_clock =
13001 haswell_crtc_compute_clock;
13002 dev_priv->display.crtc_enable = haswell_crtc_enable;
13003 dev_priv->display.crtc_disable = haswell_crtc_disable;
13004 dev_priv->display.off = ironlake_crtc_off;
13005 dev_priv->display.update_primary_plane =
13006 skylake_update_primary_plane;
13007 } else if (HAS_DDI(dev)) {
13008 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13009 dev_priv->display.get_initial_plane_config =
13010 ironlake_get_initial_plane_config;
13011 dev_priv->display.crtc_compute_clock =
13012 haswell_crtc_compute_clock;
13013 dev_priv->display.crtc_enable = haswell_crtc_enable;
13014 dev_priv->display.crtc_disable = haswell_crtc_disable;
13015 dev_priv->display.off = ironlake_crtc_off;
13016 dev_priv->display.update_primary_plane =
13017 ironlake_update_primary_plane;
13018 } else if (HAS_PCH_SPLIT(dev)) {
13019 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13020 dev_priv->display.get_initial_plane_config =
13021 ironlake_get_initial_plane_config;
13022 dev_priv->display.crtc_compute_clock =
13023 ironlake_crtc_compute_clock;
13024 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13025 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13026 dev_priv->display.off = ironlake_crtc_off;
13027 dev_priv->display.update_primary_plane =
13028 ironlake_update_primary_plane;
13029 } else if (IS_VALLEYVIEW(dev)) {
13030 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13031 dev_priv->display.get_initial_plane_config =
13032 i9xx_get_initial_plane_config;
13033 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13034 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13035 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13036 dev_priv->display.off = i9xx_crtc_off;
13037 dev_priv->display.update_primary_plane =
13038 i9xx_update_primary_plane;
13039 } else {
13040 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13041 dev_priv->display.get_initial_plane_config =
13042 i9xx_get_initial_plane_config;
13043 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13044 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13045 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13046 dev_priv->display.off = i9xx_crtc_off;
13047 dev_priv->display.update_primary_plane =
13048 i9xx_update_primary_plane;
13049 }
13050
13051 /* Returns the core display clock speed */
13052 if (IS_VALLEYVIEW(dev))
13053 dev_priv->display.get_display_clock_speed =
13054 valleyview_get_display_clock_speed;
13055 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13056 dev_priv->display.get_display_clock_speed =
13057 i945_get_display_clock_speed;
13058 else if (IS_I915G(dev))
13059 dev_priv->display.get_display_clock_speed =
13060 i915_get_display_clock_speed;
13061 else if (IS_I945GM(dev) || IS_845G(dev))
13062 dev_priv->display.get_display_clock_speed =
13063 i9xx_misc_get_display_clock_speed;
13064 else if (IS_PINEVIEW(dev))
13065 dev_priv->display.get_display_clock_speed =
13066 pnv_get_display_clock_speed;
13067 else if (IS_I915GM(dev))
13068 dev_priv->display.get_display_clock_speed =
13069 i915gm_get_display_clock_speed;
13070 else if (IS_I865G(dev))
13071 dev_priv->display.get_display_clock_speed =
13072 i865_get_display_clock_speed;
13073 else if (IS_I85X(dev))
13074 dev_priv->display.get_display_clock_speed =
13075 i855_get_display_clock_speed;
13076 else /* 852, 830 */
13077 dev_priv->display.get_display_clock_speed =
13078 i830_get_display_clock_speed;
13079
13080 if (IS_GEN5(dev)) {
13081 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13082 } else if (IS_GEN6(dev)) {
13083 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13084 } else if (IS_IVYBRIDGE(dev)) {
13085 /* FIXME: detect B0+ stepping and use auto training */
13086 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13087 dev_priv->display.modeset_global_resources =
13088 ivb_modeset_global_resources;
13089 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13090 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13091 } else if (IS_VALLEYVIEW(dev)) {
13092 dev_priv->display.modeset_global_resources =
13093 valleyview_modeset_global_resources;
13094 }
13095
13096 switch (INTEL_INFO(dev)->gen) {
13097 case 2:
13098 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13099 break;
13100
13101 case 3:
13102 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13103 break;
13104
13105 case 4:
13106 case 5:
13107 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13108 break;
13109
13110 case 6:
13111 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13112 break;
13113 case 7:
13114 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13115 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13116 break;
13117 case 9:
13118 /* Drop through - unsupported since execlist only. */
13119 default:
13120 /* Default just returns -ENODEV to indicate unsupported */
13121 dev_priv->display.queue_flip = intel_default_queue_flip;
13122 }
13123
13124 intel_panel_init_backlight_funcs(dev);
13125
13126 mutex_init(&dev_priv->pps_mutex);
13127 }
13128
13129 /*
13130 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13131 * resume, or other times. This quirk makes sure that's the case for
13132 * affected systems.
13133 */
13134 static void quirk_pipea_force(struct drm_device *dev)
13135 {
13136 struct drm_i915_private *dev_priv = dev->dev_private;
13137
13138 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13139 DRM_INFO("applying pipe a force quirk\n");
13140 }
13141
13142 static void quirk_pipeb_force(struct drm_device *dev)
13143 {
13144 struct drm_i915_private *dev_priv = dev->dev_private;
13145
13146 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13147 DRM_INFO("applying pipe b force quirk\n");
13148 }
13149
13150 /*
13151 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13152 */
13153 static void quirk_ssc_force_disable(struct drm_device *dev)
13154 {
13155 struct drm_i915_private *dev_priv = dev->dev_private;
13156 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13157 DRM_INFO("applying lvds SSC disable quirk\n");
13158 }
13159
13160 /*
13161 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13162 * brightness value
13163 */
13164 static void quirk_invert_brightness(struct drm_device *dev)
13165 {
13166 struct drm_i915_private *dev_priv = dev->dev_private;
13167 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13168 DRM_INFO("applying inverted panel brightness quirk\n");
13169 }
13170
13171 /* Some VBT's incorrectly indicate no backlight is present */
13172 static void quirk_backlight_present(struct drm_device *dev)
13173 {
13174 struct drm_i915_private *dev_priv = dev->dev_private;
13175 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13176 DRM_INFO("applying backlight present quirk\n");
13177 }
13178
13179 struct intel_quirk {
13180 int device;
13181 int subsystem_vendor;
13182 int subsystem_device;
13183 void (*hook)(struct drm_device *dev);
13184 };
13185
13186 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13187 struct intel_dmi_quirk {
13188 void (*hook)(struct drm_device *dev);
13189 const struct dmi_system_id (*dmi_id_list)[];
13190 };
13191
13192 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13193 {
13194 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13195 return 1;
13196 }
13197
13198 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13199 {
13200 .dmi_id_list = &(const struct dmi_system_id[]) {
13201 {
13202 .callback = intel_dmi_reverse_brightness,
13203 .ident = "NCR Corporation",
13204 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13205 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13206 },
13207 },
13208 { } /* terminating entry */
13209 },
13210 .hook = quirk_invert_brightness,
13211 },
13212 };
13213
13214 static struct intel_quirk intel_quirks[] = {
13215 /* HP Mini needs pipe A force quirk (LP: #322104) */
13216 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13217
13218 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13219 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13220
13221 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13222 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13223
13224 /* 830 needs to leave pipe A & dpll A up */
13225 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13226
13227 /* 830 needs to leave pipe B & dpll B up */
13228 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13229
13230 /* Lenovo U160 cannot use SSC on LVDS */
13231 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13232
13233 /* Sony Vaio Y cannot use SSC on LVDS */
13234 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13235
13236 /* Acer Aspire 5734Z must invert backlight brightness */
13237 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13238
13239 /* Acer/eMachines G725 */
13240 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13241
13242 /* Acer/eMachines e725 */
13243 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13244
13245 /* Acer/Packard Bell NCL20 */
13246 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13247
13248 /* Acer Aspire 4736Z */
13249 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13250
13251 /* Acer Aspire 5336 */
13252 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13253
13254 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13255 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13256
13257 /* Acer C720 Chromebook (Core i3 4005U) */
13258 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13259
13260 /* Apple Macbook 2,1 (Core 2 T7400) */
13261 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13262
13263 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13264 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13265
13266 /* HP Chromebook 14 (Celeron 2955U) */
13267 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13268
13269 /* Dell Chromebook 11 */
13270 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13271 };
13272
13273 static void intel_init_quirks(struct drm_device *dev)
13274 {
13275 struct pci_dev *d = dev->pdev;
13276 int i;
13277
13278 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13279 struct intel_quirk *q = &intel_quirks[i];
13280
13281 if (d->device == q->device &&
13282 (d->subsystem_vendor == q->subsystem_vendor ||
13283 q->subsystem_vendor == PCI_ANY_ID) &&
13284 (d->subsystem_device == q->subsystem_device ||
13285 q->subsystem_device == PCI_ANY_ID))
13286 q->hook(dev);
13287 }
13288 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13289 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13290 intel_dmi_quirks[i].hook(dev);
13291 }
13292 }
13293
13294 /* Disable the VGA plane that we never use */
13295 static void i915_disable_vga(struct drm_device *dev)
13296 {
13297 struct drm_i915_private *dev_priv = dev->dev_private;
13298 u8 sr1;
13299 u32 vga_reg = i915_vgacntrl_reg(dev);
13300
13301 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13302 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13303 outb(SR01, VGA_SR_INDEX);
13304 sr1 = inb(VGA_SR_DATA);
13305 outb(sr1 | 1<<5, VGA_SR_DATA);
13306 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13307 udelay(300);
13308
13309 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13310 POSTING_READ(vga_reg);
13311 }
13312
13313 void intel_modeset_init_hw(struct drm_device *dev)
13314 {
13315 intel_prepare_ddi(dev);
13316
13317 if (IS_VALLEYVIEW(dev))
13318 vlv_update_cdclk(dev);
13319
13320 intel_init_clock_gating(dev);
13321
13322 intel_enable_gt_powersave(dev);
13323 }
13324
13325 void intel_modeset_init(struct drm_device *dev)
13326 {
13327 struct drm_i915_private *dev_priv = dev->dev_private;
13328 int sprite, ret;
13329 enum pipe pipe;
13330 struct intel_crtc *crtc;
13331
13332 drm_mode_config_init(dev);
13333
13334 dev->mode_config.min_width = 0;
13335 dev->mode_config.min_height = 0;
13336
13337 dev->mode_config.preferred_depth = 24;
13338 dev->mode_config.prefer_shadow = 1;
13339
13340 dev->mode_config.allow_fb_modifiers = true;
13341
13342 dev->mode_config.funcs = &intel_mode_funcs;
13343
13344 intel_init_quirks(dev);
13345
13346 intel_init_pm(dev);
13347
13348 if (INTEL_INFO(dev)->num_pipes == 0)
13349 return;
13350
13351 intel_init_display(dev);
13352 intel_init_audio(dev);
13353
13354 if (IS_GEN2(dev)) {
13355 dev->mode_config.max_width = 2048;
13356 dev->mode_config.max_height = 2048;
13357 } else if (IS_GEN3(dev)) {
13358 dev->mode_config.max_width = 4096;
13359 dev->mode_config.max_height = 4096;
13360 } else {
13361 dev->mode_config.max_width = 8192;
13362 dev->mode_config.max_height = 8192;
13363 }
13364
13365 if (IS_845G(dev) || IS_I865G(dev)) {
13366 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13367 dev->mode_config.cursor_height = 1023;
13368 } else if (IS_GEN2(dev)) {
13369 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13370 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13371 } else {
13372 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13373 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13374 }
13375
13376 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13377
13378 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13379 INTEL_INFO(dev)->num_pipes,
13380 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13381
13382 for_each_pipe(dev_priv, pipe) {
13383 intel_crtc_init(dev, pipe);
13384 for_each_sprite(dev_priv, pipe, sprite) {
13385 ret = intel_plane_init(dev, pipe, sprite);
13386 if (ret)
13387 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13388 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13389 }
13390 }
13391
13392 intel_init_dpio(dev);
13393
13394 intel_shared_dpll_init(dev);
13395
13396 /* Just disable it once at startup */
13397 i915_disable_vga(dev);
13398 intel_setup_outputs(dev);
13399
13400 /* Just in case the BIOS is doing something questionable. */
13401 intel_fbc_disable(dev);
13402
13403 drm_modeset_lock_all(dev);
13404 intel_modeset_setup_hw_state(dev, false);
13405 drm_modeset_unlock_all(dev);
13406
13407 for_each_intel_crtc(dev, crtc) {
13408 if (!crtc->active)
13409 continue;
13410
13411 /*
13412 * Note that reserving the BIOS fb up front prevents us
13413 * from stuffing other stolen allocations like the ring
13414 * on top. This prevents some ugliness at boot time, and
13415 * can even allow for smooth boot transitions if the BIOS
13416 * fb is large enough for the active pipe configuration.
13417 */
13418 if (dev_priv->display.get_initial_plane_config) {
13419 dev_priv->display.get_initial_plane_config(crtc,
13420 &crtc->plane_config);
13421 /*
13422 * If the fb is shared between multiple heads, we'll
13423 * just get the first one.
13424 */
13425 intel_find_plane_obj(crtc, &crtc->plane_config);
13426 }
13427 }
13428 }
13429
13430 static void intel_enable_pipe_a(struct drm_device *dev)
13431 {
13432 struct intel_connector *connector;
13433 struct drm_connector *crt = NULL;
13434 struct intel_load_detect_pipe load_detect_temp;
13435 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13436
13437 /* We can't just switch on the pipe A, we need to set things up with a
13438 * proper mode and output configuration. As a gross hack, enable pipe A
13439 * by enabling the load detect pipe once. */
13440 for_each_intel_connector(dev, connector) {
13441 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13442 crt = &connector->base;
13443 break;
13444 }
13445 }
13446
13447 if (!crt)
13448 return;
13449
13450 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13451 intel_release_load_detect_pipe(crt, &load_detect_temp);
13452 }
13453
13454 static bool
13455 intel_check_plane_mapping(struct intel_crtc *crtc)
13456 {
13457 struct drm_device *dev = crtc->base.dev;
13458 struct drm_i915_private *dev_priv = dev->dev_private;
13459 u32 reg, val;
13460
13461 if (INTEL_INFO(dev)->num_pipes == 1)
13462 return true;
13463
13464 reg = DSPCNTR(!crtc->plane);
13465 val = I915_READ(reg);
13466
13467 if ((val & DISPLAY_PLANE_ENABLE) &&
13468 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13469 return false;
13470
13471 return true;
13472 }
13473
13474 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13475 {
13476 struct drm_device *dev = crtc->base.dev;
13477 struct drm_i915_private *dev_priv = dev->dev_private;
13478 u32 reg;
13479
13480 /* Clear any frame start delays used for debugging left by the BIOS */
13481 reg = PIPECONF(crtc->config->cpu_transcoder);
13482 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13483
13484 /* restore vblank interrupts to correct state */
13485 drm_crtc_vblank_reset(&crtc->base);
13486 if (crtc->active) {
13487 update_scanline_offset(crtc);
13488 drm_crtc_vblank_on(&crtc->base);
13489 }
13490
13491 /* We need to sanitize the plane -> pipe mapping first because this will
13492 * disable the crtc (and hence change the state) if it is wrong. Note
13493 * that gen4+ has a fixed plane -> pipe mapping. */
13494 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13495 struct intel_connector *connector;
13496 bool plane;
13497
13498 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13499 crtc->base.base.id);
13500
13501 /* Pipe has the wrong plane attached and the plane is active.
13502 * Temporarily change the plane mapping and disable everything
13503 * ... */
13504 plane = crtc->plane;
13505 crtc->plane = !plane;
13506 crtc->primary_enabled = true;
13507 dev_priv->display.crtc_disable(&crtc->base);
13508 crtc->plane = plane;
13509
13510 /* ... and break all links. */
13511 for_each_intel_connector(dev, connector) {
13512 if (connector->encoder->base.crtc != &crtc->base)
13513 continue;
13514
13515 connector->base.dpms = DRM_MODE_DPMS_OFF;
13516 connector->base.encoder = NULL;
13517 }
13518 /* multiple connectors may have the same encoder:
13519 * handle them and break crtc link separately */
13520 for_each_intel_connector(dev, connector)
13521 if (connector->encoder->base.crtc == &crtc->base) {
13522 connector->encoder->base.crtc = NULL;
13523 connector->encoder->connectors_active = false;
13524 }
13525
13526 WARN_ON(crtc->active);
13527 crtc->base.state->enable = false;
13528 crtc->base.enabled = false;
13529 }
13530
13531 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13532 crtc->pipe == PIPE_A && !crtc->active) {
13533 /* BIOS forgot to enable pipe A, this mostly happens after
13534 * resume. Force-enable the pipe to fix this, the update_dpms
13535 * call below we restore the pipe to the right state, but leave
13536 * the required bits on. */
13537 intel_enable_pipe_a(dev);
13538 }
13539
13540 /* Adjust the state of the output pipe according to whether we
13541 * have active connectors/encoders. */
13542 intel_crtc_update_dpms(&crtc->base);
13543
13544 if (crtc->active != crtc->base.state->enable) {
13545 struct intel_encoder *encoder;
13546
13547 /* This can happen either due to bugs in the get_hw_state
13548 * functions or because the pipe is force-enabled due to the
13549 * pipe A quirk. */
13550 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13551 crtc->base.base.id,
13552 crtc->base.state->enable ? "enabled" : "disabled",
13553 crtc->active ? "enabled" : "disabled");
13554
13555 crtc->base.state->enable = crtc->active;
13556 crtc->base.enabled = crtc->active;
13557
13558 /* Because we only establish the connector -> encoder ->
13559 * crtc links if something is active, this means the
13560 * crtc is now deactivated. Break the links. connector
13561 * -> encoder links are only establish when things are
13562 * actually up, hence no need to break them. */
13563 WARN_ON(crtc->active);
13564
13565 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13566 WARN_ON(encoder->connectors_active);
13567 encoder->base.crtc = NULL;
13568 }
13569 }
13570
13571 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13572 /*
13573 * We start out with underrun reporting disabled to avoid races.
13574 * For correct bookkeeping mark this on active crtcs.
13575 *
13576 * Also on gmch platforms we dont have any hardware bits to
13577 * disable the underrun reporting. Which means we need to start
13578 * out with underrun reporting disabled also on inactive pipes,
13579 * since otherwise we'll complain about the garbage we read when
13580 * e.g. coming up after runtime pm.
13581 *
13582 * No protection against concurrent access is required - at
13583 * worst a fifo underrun happens which also sets this to false.
13584 */
13585 crtc->cpu_fifo_underrun_disabled = true;
13586 crtc->pch_fifo_underrun_disabled = true;
13587 }
13588 }
13589
13590 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13591 {
13592 struct intel_connector *connector;
13593 struct drm_device *dev = encoder->base.dev;
13594
13595 /* We need to check both for a crtc link (meaning that the
13596 * encoder is active and trying to read from a pipe) and the
13597 * pipe itself being active. */
13598 bool has_active_crtc = encoder->base.crtc &&
13599 to_intel_crtc(encoder->base.crtc)->active;
13600
13601 if (encoder->connectors_active && !has_active_crtc) {
13602 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13603 encoder->base.base.id,
13604 encoder->base.name);
13605
13606 /* Connector is active, but has no active pipe. This is
13607 * fallout from our resume register restoring. Disable
13608 * the encoder manually again. */
13609 if (encoder->base.crtc) {
13610 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13611 encoder->base.base.id,
13612 encoder->base.name);
13613 encoder->disable(encoder);
13614 if (encoder->post_disable)
13615 encoder->post_disable(encoder);
13616 }
13617 encoder->base.crtc = NULL;
13618 encoder->connectors_active = false;
13619
13620 /* Inconsistent output/port/pipe state happens presumably due to
13621 * a bug in one of the get_hw_state functions. Or someplace else
13622 * in our code, like the register restore mess on resume. Clamp
13623 * things to off as a safer default. */
13624 for_each_intel_connector(dev, connector) {
13625 if (connector->encoder != encoder)
13626 continue;
13627 connector->base.dpms = DRM_MODE_DPMS_OFF;
13628 connector->base.encoder = NULL;
13629 }
13630 }
13631 /* Enabled encoders without active connectors will be fixed in
13632 * the crtc fixup. */
13633 }
13634
13635 void i915_redisable_vga_power_on(struct drm_device *dev)
13636 {
13637 struct drm_i915_private *dev_priv = dev->dev_private;
13638 u32 vga_reg = i915_vgacntrl_reg(dev);
13639
13640 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13641 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13642 i915_disable_vga(dev);
13643 }
13644 }
13645
13646 void i915_redisable_vga(struct drm_device *dev)
13647 {
13648 struct drm_i915_private *dev_priv = dev->dev_private;
13649
13650 /* This function can be called both from intel_modeset_setup_hw_state or
13651 * at a very early point in our resume sequence, where the power well
13652 * structures are not yet restored. Since this function is at a very
13653 * paranoid "someone might have enabled VGA while we were not looking"
13654 * level, just check if the power well is enabled instead of trying to
13655 * follow the "don't touch the power well if we don't need it" policy
13656 * the rest of the driver uses. */
13657 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13658 return;
13659
13660 i915_redisable_vga_power_on(dev);
13661 }
13662
13663 static bool primary_get_hw_state(struct intel_crtc *crtc)
13664 {
13665 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13666
13667 if (!crtc->active)
13668 return false;
13669
13670 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13671 }
13672
13673 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13674 {
13675 struct drm_i915_private *dev_priv = dev->dev_private;
13676 enum pipe pipe;
13677 struct intel_crtc *crtc;
13678 struct intel_encoder *encoder;
13679 struct intel_connector *connector;
13680 int i;
13681
13682 for_each_intel_crtc(dev, crtc) {
13683 memset(crtc->config, 0, sizeof(*crtc->config));
13684
13685 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13686
13687 crtc->active = dev_priv->display.get_pipe_config(crtc,
13688 crtc->config);
13689
13690 crtc->base.state->enable = crtc->active;
13691 crtc->base.enabled = crtc->active;
13692 crtc->primary_enabled = primary_get_hw_state(crtc);
13693
13694 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13695 crtc->base.base.id,
13696 crtc->active ? "enabled" : "disabled");
13697 }
13698
13699 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13700 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13701
13702 pll->on = pll->get_hw_state(dev_priv, pll,
13703 &pll->config.hw_state);
13704 pll->active = 0;
13705 pll->config.crtc_mask = 0;
13706 for_each_intel_crtc(dev, crtc) {
13707 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13708 pll->active++;
13709 pll->config.crtc_mask |= 1 << crtc->pipe;
13710 }
13711 }
13712
13713 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13714 pll->name, pll->config.crtc_mask, pll->on);
13715
13716 if (pll->config.crtc_mask)
13717 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13718 }
13719
13720 for_each_intel_encoder(dev, encoder) {
13721 pipe = 0;
13722
13723 if (encoder->get_hw_state(encoder, &pipe)) {
13724 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13725 encoder->base.crtc = &crtc->base;
13726 encoder->get_config(encoder, crtc->config);
13727 } else {
13728 encoder->base.crtc = NULL;
13729 }
13730
13731 encoder->connectors_active = false;
13732 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13733 encoder->base.base.id,
13734 encoder->base.name,
13735 encoder->base.crtc ? "enabled" : "disabled",
13736 pipe_name(pipe));
13737 }
13738
13739 for_each_intel_connector(dev, connector) {
13740 if (connector->get_hw_state(connector)) {
13741 connector->base.dpms = DRM_MODE_DPMS_ON;
13742 connector->encoder->connectors_active = true;
13743 connector->base.encoder = &connector->encoder->base;
13744 } else {
13745 connector->base.dpms = DRM_MODE_DPMS_OFF;
13746 connector->base.encoder = NULL;
13747 }
13748 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13749 connector->base.base.id,
13750 connector->base.name,
13751 connector->base.encoder ? "enabled" : "disabled");
13752 }
13753 }
13754
13755 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13756 * and i915 state tracking structures. */
13757 void intel_modeset_setup_hw_state(struct drm_device *dev,
13758 bool force_restore)
13759 {
13760 struct drm_i915_private *dev_priv = dev->dev_private;
13761 enum pipe pipe;
13762 struct intel_crtc *crtc;
13763 struct intel_encoder *encoder;
13764 int i;
13765
13766 intel_modeset_readout_hw_state(dev);
13767
13768 /*
13769 * Now that we have the config, copy it to each CRTC struct
13770 * Note that this could go away if we move to using crtc_config
13771 * checking everywhere.
13772 */
13773 for_each_intel_crtc(dev, crtc) {
13774 if (crtc->active && i915.fastboot) {
13775 intel_mode_from_pipe_config(&crtc->base.mode,
13776 crtc->config);
13777 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13778 crtc->base.base.id);
13779 drm_mode_debug_printmodeline(&crtc->base.mode);
13780 }
13781 }
13782
13783 /* HW state is read out, now we need to sanitize this mess. */
13784 for_each_intel_encoder(dev, encoder) {
13785 intel_sanitize_encoder(encoder);
13786 }
13787
13788 for_each_pipe(dev_priv, pipe) {
13789 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13790 intel_sanitize_crtc(crtc);
13791 intel_dump_pipe_config(crtc, crtc->config,
13792 "[setup_hw_state]");
13793 }
13794
13795 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13796 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13797
13798 if (!pll->on || pll->active)
13799 continue;
13800
13801 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13802
13803 pll->disable(dev_priv, pll);
13804 pll->on = false;
13805 }
13806
13807 if (IS_GEN9(dev))
13808 skl_wm_get_hw_state(dev);
13809 else if (HAS_PCH_SPLIT(dev))
13810 ilk_wm_get_hw_state(dev);
13811
13812 if (force_restore) {
13813 i915_redisable_vga(dev);
13814
13815 /*
13816 * We need to use raw interfaces for restoring state to avoid
13817 * checking (bogus) intermediate states.
13818 */
13819 for_each_pipe(dev_priv, pipe) {
13820 struct drm_crtc *crtc =
13821 dev_priv->pipe_to_crtc_mapping[pipe];
13822
13823 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13824 crtc->primary->fb);
13825 }
13826 } else {
13827 intel_modeset_update_staged_output_state(dev);
13828 }
13829
13830 intel_modeset_check_state(dev);
13831 }
13832
13833 void intel_modeset_gem_init(struct drm_device *dev)
13834 {
13835 struct drm_i915_private *dev_priv = dev->dev_private;
13836 struct drm_crtc *c;
13837 struct drm_i915_gem_object *obj;
13838
13839 mutex_lock(&dev->struct_mutex);
13840 intel_init_gt_powersave(dev);
13841 mutex_unlock(&dev->struct_mutex);
13842
13843 /*
13844 * There may be no VBT; and if the BIOS enabled SSC we can
13845 * just keep using it to avoid unnecessary flicker. Whereas if the
13846 * BIOS isn't using it, don't assume it will work even if the VBT
13847 * indicates as much.
13848 */
13849 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13850 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13851 DREF_SSC1_ENABLE);
13852
13853 intel_modeset_init_hw(dev);
13854
13855 intel_setup_overlay(dev);
13856
13857 /*
13858 * Make sure any fbs we allocated at startup are properly
13859 * pinned & fenced. When we do the allocation it's too early
13860 * for this.
13861 */
13862 mutex_lock(&dev->struct_mutex);
13863 for_each_crtc(dev, c) {
13864 obj = intel_fb_obj(c->primary->fb);
13865 if (obj == NULL)
13866 continue;
13867
13868 if (intel_pin_and_fence_fb_obj(c->primary,
13869 c->primary->fb,
13870 NULL)) {
13871 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13872 to_intel_crtc(c)->pipe);
13873 drm_framebuffer_unreference(c->primary->fb);
13874 c->primary->fb = NULL;
13875 update_state_fb(c->primary);
13876 }
13877 }
13878 mutex_unlock(&dev->struct_mutex);
13879
13880 intel_backlight_register(dev);
13881 }
13882
13883 void intel_connector_unregister(struct intel_connector *intel_connector)
13884 {
13885 struct drm_connector *connector = &intel_connector->base;
13886
13887 intel_panel_destroy_backlight(connector);
13888 drm_connector_unregister(connector);
13889 }
13890
13891 void intel_modeset_cleanup(struct drm_device *dev)
13892 {
13893 struct drm_i915_private *dev_priv = dev->dev_private;
13894 struct drm_connector *connector;
13895
13896 intel_disable_gt_powersave(dev);
13897
13898 intel_backlight_unregister(dev);
13899
13900 /*
13901 * Interrupts and polling as the first thing to avoid creating havoc.
13902 * Too much stuff here (turning of connectors, ...) would
13903 * experience fancy races otherwise.
13904 */
13905 intel_irq_uninstall(dev_priv);
13906
13907 /*
13908 * Due to the hpd irq storm handling the hotplug work can re-arm the
13909 * poll handlers. Hence disable polling after hpd handling is shut down.
13910 */
13911 drm_kms_helper_poll_fini(dev);
13912
13913 mutex_lock(&dev->struct_mutex);
13914
13915 intel_unregister_dsm_handler();
13916
13917 intel_fbc_disable(dev);
13918
13919 mutex_unlock(&dev->struct_mutex);
13920
13921 /* flush any delayed tasks or pending work */
13922 flush_scheduled_work();
13923
13924 /* destroy the backlight and sysfs files before encoders/connectors */
13925 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13926 struct intel_connector *intel_connector;
13927
13928 intel_connector = to_intel_connector(connector);
13929 intel_connector->unregister(intel_connector);
13930 }
13931
13932 drm_mode_config_cleanup(dev);
13933
13934 intel_cleanup_overlay(dev);
13935
13936 mutex_lock(&dev->struct_mutex);
13937 intel_cleanup_gt_powersave(dev);
13938 mutex_unlock(&dev->struct_mutex);
13939 }
13940
13941 /*
13942 * Return which encoder is currently attached for connector.
13943 */
13944 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13945 {
13946 return &intel_attached_encoder(connector)->base;
13947 }
13948
13949 void intel_connector_attach_encoder(struct intel_connector *connector,
13950 struct intel_encoder *encoder)
13951 {
13952 connector->encoder = encoder;
13953 drm_mode_connector_attach_encoder(&connector->base,
13954 &encoder->base);
13955 }
13956
13957 /*
13958 * set vga decode state - true == enable VGA decode
13959 */
13960 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13961 {
13962 struct drm_i915_private *dev_priv = dev->dev_private;
13963 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13964 u16 gmch_ctrl;
13965
13966 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13967 DRM_ERROR("failed to read control word\n");
13968 return -EIO;
13969 }
13970
13971 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13972 return 0;
13973
13974 if (state)
13975 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13976 else
13977 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13978
13979 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13980 DRM_ERROR("failed to write control word\n");
13981 return -EIO;
13982 }
13983
13984 return 0;
13985 }
13986
13987 struct intel_display_error_state {
13988
13989 u32 power_well_driver;
13990
13991 int num_transcoders;
13992
13993 struct intel_cursor_error_state {
13994 u32 control;
13995 u32 position;
13996 u32 base;
13997 u32 size;
13998 } cursor[I915_MAX_PIPES];
13999
14000 struct intel_pipe_error_state {
14001 bool power_domain_on;
14002 u32 source;
14003 u32 stat;
14004 } pipe[I915_MAX_PIPES];
14005
14006 struct intel_plane_error_state {
14007 u32 control;
14008 u32 stride;
14009 u32 size;
14010 u32 pos;
14011 u32 addr;
14012 u32 surface;
14013 u32 tile_offset;
14014 } plane[I915_MAX_PIPES];
14015
14016 struct intel_transcoder_error_state {
14017 bool power_domain_on;
14018 enum transcoder cpu_transcoder;
14019
14020 u32 conf;
14021
14022 u32 htotal;
14023 u32 hblank;
14024 u32 hsync;
14025 u32 vtotal;
14026 u32 vblank;
14027 u32 vsync;
14028 } transcoder[4];
14029 };
14030
14031 struct intel_display_error_state *
14032 intel_display_capture_error_state(struct drm_device *dev)
14033 {
14034 struct drm_i915_private *dev_priv = dev->dev_private;
14035 struct intel_display_error_state *error;
14036 int transcoders[] = {
14037 TRANSCODER_A,
14038 TRANSCODER_B,
14039 TRANSCODER_C,
14040 TRANSCODER_EDP,
14041 };
14042 int i;
14043
14044 if (INTEL_INFO(dev)->num_pipes == 0)
14045 return NULL;
14046
14047 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14048 if (error == NULL)
14049 return NULL;
14050
14051 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14052 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14053
14054 for_each_pipe(dev_priv, i) {
14055 error->pipe[i].power_domain_on =
14056 __intel_display_power_is_enabled(dev_priv,
14057 POWER_DOMAIN_PIPE(i));
14058 if (!error->pipe[i].power_domain_on)
14059 continue;
14060
14061 error->cursor[i].control = I915_READ(CURCNTR(i));
14062 error->cursor[i].position = I915_READ(CURPOS(i));
14063 error->cursor[i].base = I915_READ(CURBASE(i));
14064
14065 error->plane[i].control = I915_READ(DSPCNTR(i));
14066 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14067 if (INTEL_INFO(dev)->gen <= 3) {
14068 error->plane[i].size = I915_READ(DSPSIZE(i));
14069 error->plane[i].pos = I915_READ(DSPPOS(i));
14070 }
14071 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14072 error->plane[i].addr = I915_READ(DSPADDR(i));
14073 if (INTEL_INFO(dev)->gen >= 4) {
14074 error->plane[i].surface = I915_READ(DSPSURF(i));
14075 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14076 }
14077
14078 error->pipe[i].source = I915_READ(PIPESRC(i));
14079
14080 if (HAS_GMCH_DISPLAY(dev))
14081 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14082 }
14083
14084 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14085 if (HAS_DDI(dev_priv->dev))
14086 error->num_transcoders++; /* Account for eDP. */
14087
14088 for (i = 0; i < error->num_transcoders; i++) {
14089 enum transcoder cpu_transcoder = transcoders[i];
14090
14091 error->transcoder[i].power_domain_on =
14092 __intel_display_power_is_enabled(dev_priv,
14093 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14094 if (!error->transcoder[i].power_domain_on)
14095 continue;
14096
14097 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14098
14099 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14100 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14101 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14102 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14103 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14104 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14105 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14106 }
14107
14108 return error;
14109 }
14110
14111 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14112
14113 void
14114 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14115 struct drm_device *dev,
14116 struct intel_display_error_state *error)
14117 {
14118 struct drm_i915_private *dev_priv = dev->dev_private;
14119 int i;
14120
14121 if (!error)
14122 return;
14123
14124 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14125 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14126 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14127 error->power_well_driver);
14128 for_each_pipe(dev_priv, i) {
14129 err_printf(m, "Pipe [%d]:\n", i);
14130 err_printf(m, " Power: %s\n",
14131 error->pipe[i].power_domain_on ? "on" : "off");
14132 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14133 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14134
14135 err_printf(m, "Plane [%d]:\n", i);
14136 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14137 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14138 if (INTEL_INFO(dev)->gen <= 3) {
14139 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14140 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14141 }
14142 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14143 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14144 if (INTEL_INFO(dev)->gen >= 4) {
14145 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14146 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14147 }
14148
14149 err_printf(m, "Cursor [%d]:\n", i);
14150 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14151 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14152 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14153 }
14154
14155 for (i = 0; i < error->num_transcoders; i++) {
14156 err_printf(m, "CPU transcoder: %c\n",
14157 transcoder_name(error->transcoder[i].cpu_transcoder));
14158 err_printf(m, " Power: %s\n",
14159 error->transcoder[i].power_domain_on ? "on" : "off");
14160 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14161 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14162 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14163 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14164 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14165 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14166 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14167 }
14168 }
14169
14170 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14171 {
14172 struct intel_crtc *crtc;
14173
14174 for_each_intel_crtc(dev, crtc) {
14175 struct intel_unpin_work *work;
14176
14177 spin_lock_irq(&dev->event_lock);
14178
14179 work = crtc->unpin_work;
14180
14181 if (work && work->event &&
14182 work->event->base.file_priv == file) {
14183 kfree(work->event);
14184 work->event = NULL;
14185 }
14186
14187 spin_unlock_irq(&dev->event_lock);
14188 }
14189 }
Linux kernel - Deliverables
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