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drm/i915: Assert that runtime pm is active on user fw access
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_state *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_state *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
102 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
103
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105 {
106 if (!connector->mst_port)
107 return connector->encoder;
108 else
109 return &connector->mst_port->mst_encoders[pipe]->base;
110 }
111
112 typedef struct {
113 int min, max;
114 } intel_range_t;
115
116 typedef struct {
117 int dot_limit;
118 int p2_slow, p2_fast;
119 } intel_p2_t;
120
121 typedef struct intel_limit intel_limit_t;
122 struct intel_limit {
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_p2_t p2;
125 };
126
127 int
128 intel_pch_rawclk(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131
132 WARN_ON(!HAS_PCH_SPLIT(dev));
133
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 }
136
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
139 {
140 if (IS_GEN5(dev)) {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 } else
144 return 27;
145 }
146
147 static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
158 };
159
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
171 };
172
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
184 };
185
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
197 };
198
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
210 };
211
212
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
223 .p2_slow = 10,
224 .p2_fast = 10
225 },
226 };
227
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
239 };
240
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
252 },
253 };
254
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
266 },
267 };
268
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
282 };
283
284 static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
295 };
296
297 /* Ironlake / Sandybridge
298 *
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
301 */
302 static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 };
340
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
353 };
354
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
366 };
367
368 static const intel_limit_t intel_limits_vlv = {
369 /*
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
374 */
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 };
383
384 static const intel_limit_t intel_limits_chv = {
385 /*
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
390 */
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 };
399
400 static void vlv_clock(int refclk, intel_clock_t *clock)
401 {
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
405 return;
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408 }
409
410 /**
411 * Returns whether any output on the specified pipe is of the specified type
412 */
413 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
414 {
415 struct drm_device *dev = crtc->base.dev;
416 struct intel_encoder *encoder;
417
418 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
419 if (encoder->type == type)
420 return true;
421
422 return false;
423 }
424
425 /**
426 * Returns whether any output on the specified pipe will have the specified
427 * type after a staged modeset is complete, i.e., the same as
428 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 * encoder->crtc.
430 */
431 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
432 {
433 struct drm_device *dev = crtc->base.dev;
434 struct intel_encoder *encoder;
435
436 for_each_intel_encoder(dev, encoder)
437 if (encoder->new_crtc == crtc && encoder->type == type)
438 return true;
439
440 return false;
441 }
442
443 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
444 int refclk)
445 {
446 struct drm_device *dev = crtc->base.dev;
447 const intel_limit_t *limit;
448
449 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
450 if (intel_is_dual_link_lvds(dev)) {
451 if (refclk == 100000)
452 limit = &intel_limits_ironlake_dual_lvds_100m;
453 else
454 limit = &intel_limits_ironlake_dual_lvds;
455 } else {
456 if (refclk == 100000)
457 limit = &intel_limits_ironlake_single_lvds_100m;
458 else
459 limit = &intel_limits_ironlake_single_lvds;
460 }
461 } else
462 limit = &intel_limits_ironlake_dac;
463
464 return limit;
465 }
466
467 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
468 {
469 struct drm_device *dev = crtc->base.dev;
470 const intel_limit_t *limit;
471
472 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev))
474 limit = &intel_limits_g4x_dual_channel_lvds;
475 else
476 limit = &intel_limits_g4x_single_channel_lvds;
477 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
478 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
479 limit = &intel_limits_g4x_hdmi;
480 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
481 limit = &intel_limits_g4x_sdvo;
482 } else /* The option is for other outputs */
483 limit = &intel_limits_i9xx_sdvo;
484
485 return limit;
486 }
487
488 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
489 {
490 struct drm_device *dev = crtc->base.dev;
491 const intel_limit_t *limit;
492
493 if (HAS_PCH_SPLIT(dev))
494 limit = intel_ironlake_limit(crtc, refclk);
495 else if (IS_G4X(dev)) {
496 limit = intel_g4x_limit(crtc);
497 } else if (IS_PINEVIEW(dev)) {
498 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
499 limit = &intel_limits_pineview_lvds;
500 else
501 limit = &intel_limits_pineview_sdvo;
502 } else if (IS_CHERRYVIEW(dev)) {
503 limit = &intel_limits_chv;
504 } else if (IS_VALLEYVIEW(dev)) {
505 limit = &intel_limits_vlv;
506 } else if (!IS_GEN2(dev)) {
507 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
508 limit = &intel_limits_i9xx_lvds;
509 else
510 limit = &intel_limits_i9xx_sdvo;
511 } else {
512 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
513 limit = &intel_limits_i8xx_lvds;
514 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
515 limit = &intel_limits_i8xx_dvo;
516 else
517 limit = &intel_limits_i8xx_dac;
518 }
519 return limit;
520 }
521
522 /* m1 is reserved as 0 in Pineview, n is a ring counter */
523 static void pineview_clock(int refclk, intel_clock_t *clock)
524 {
525 clock->m = clock->m2 + 2;
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n == 0 || clock->p == 0))
528 return;
529 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
534 {
535 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
536 }
537
538 static void i9xx_clock(int refclk, intel_clock_t *clock)
539 {
540 clock->m = i9xx_dpll_compute_m(clock);
541 clock->p = clock->p1 * clock->p2;
542 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
543 return;
544 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
545 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
546 }
547
548 static void chv_clock(int refclk, intel_clock_t *clock)
549 {
550 clock->m = clock->m1 * clock->m2;
551 clock->p = clock->p1 * clock->p2;
552 if (WARN_ON(clock->n == 0 || clock->p == 0))
553 return;
554 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
555 clock->n << 22);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 }
558
559 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
560 /**
561 * Returns whether the given set of divisors are valid for a given refclk with
562 * the given connectors.
563 */
564
565 static bool intel_PLL_is_valid(struct drm_device *dev,
566 const intel_limit_t *limit,
567 const intel_clock_t *clock)
568 {
569 if (clock->n < limit->n.min || limit->n.max < clock->n)
570 INTELPllInvalid("n out of range\n");
571 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
572 INTELPllInvalid("p1 out of range\n");
573 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
574 INTELPllInvalid("m2 out of range\n");
575 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
576 INTELPllInvalid("m1 out of range\n");
577
578 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
579 if (clock->m1 <= clock->m2)
580 INTELPllInvalid("m1 <= m2\n");
581
582 if (!IS_VALLEYVIEW(dev)) {
583 if (clock->p < limit->p.min || limit->p.max < clock->p)
584 INTELPllInvalid("p out of range\n");
585 if (clock->m < limit->m.min || limit->m.max < clock->m)
586 INTELPllInvalid("m out of range\n");
587 }
588
589 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
590 INTELPllInvalid("vco out of range\n");
591 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
592 * connector, etc., rather than just a single range.
593 */
594 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
595 INTELPllInvalid("dot out of range\n");
596
597 return true;
598 }
599
600 static bool
601 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
602 int target, int refclk, intel_clock_t *match_clock,
603 intel_clock_t *best_clock)
604 {
605 struct drm_device *dev = crtc->base.dev;
606 intel_clock_t clock;
607 int err = target;
608
609 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
610 /*
611 * For LVDS just rely on its current settings for dual-channel.
612 * We haven't figured out how to reliably set up different
613 * single/dual channel state, if we even can.
614 */
615 if (intel_is_dual_link_lvds(dev))
616 clock.p2 = limit->p2.p2_fast;
617 else
618 clock.p2 = limit->p2.p2_slow;
619 } else {
620 if (target < limit->p2.dot_limit)
621 clock.p2 = limit->p2.p2_slow;
622 else
623 clock.p2 = limit->p2.p2_fast;
624 }
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
629 clock.m1++) {
630 for (clock.m2 = limit->m2.min;
631 clock.m2 <= limit->m2.max; clock.m2++) {
632 if (clock.m2 >= clock.m1)
633 break;
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 i9xx_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->base.dev;
667 intel_clock_t clock;
668 int err = target;
669
670 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
671 /*
672 * For LVDS just rely on its current settings for dual-channel.
673 * We haven't figured out how to reliably set up different
674 * single/dual channel state, if we even can.
675 */
676 if (intel_is_dual_link_lvds(dev))
677 clock.p2 = limit->p2.p2_fast;
678 else
679 clock.p2 = limit->p2.p2_slow;
680 } else {
681 if (target < limit->p2.dot_limit)
682 clock.p2 = limit->p2.p2_slow;
683 else
684 clock.p2 = limit->p2.p2_fast;
685 }
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 for (clock.n = limit->n.min;
694 clock.n <= limit->n.max; clock.n++) {
695 for (clock.p1 = limit->p1.min;
696 clock.p1 <= limit->p1.max; clock.p1++) {
697 int this_err;
698
699 pineview_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 static bool
721 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
722 int target, int refclk, intel_clock_t *match_clock,
723 intel_clock_t *best_clock)
724 {
725 struct drm_device *dev = crtc->base.dev;
726 intel_clock_t clock;
727 int max_n;
728 bool found;
729 /* approximately equals target * 0.00585 */
730 int err_most = (target >> 8) + (target >> 9);
731 found = false;
732
733 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
734 if (intel_is_dual_link_lvds(dev))
735 clock.p2 = limit->p2.p2_fast;
736 else
737 clock.p2 = limit->p2.p2_slow;
738 } else {
739 if (target < limit->p2.dot_limit)
740 clock.p2 = limit->p2.p2_slow;
741 else
742 clock.p2 = limit->p2.p2_fast;
743 }
744
745 memset(best_clock, 0, sizeof(*best_clock));
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_clock(refclk, &clock);
759 if (!intel_PLL_is_valid(dev, limit,
760 &clock))
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err_most) {
765 *best_clock = clock;
766 err_most = this_err;
767 max_n = clock.n;
768 found = true;
769 }
770 }
771 }
772 }
773 }
774 return found;
775 }
776
777 static bool
778 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
779 int target, int refclk, intel_clock_t *match_clock,
780 intel_clock_t *best_clock)
781 {
782 struct drm_device *dev = crtc->base.dev;
783 intel_clock_t clock;
784 unsigned int bestppm = 1000000;
785 /* min update 19.2 MHz */
786 int max_n = min(limit->n.max, refclk / 19200);
787 bool found = false;
788
789 target *= 5; /* fast clock */
790
791 memset(best_clock, 0, sizeof(*best_clock));
792
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
797 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
798 clock.p = clock.p1 * clock.p2;
799 /* based on hardware requirement, prefer bigger m1,m2 values */
800 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
801 unsigned int ppm, diff;
802
803 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
804 refclk * clock.m1);
805
806 vlv_clock(refclk, &clock);
807
808 if (!intel_PLL_is_valid(dev, limit,
809 &clock))
810 continue;
811
812 diff = abs(clock.dot - target);
813 ppm = div_u64(1000000ULL * diff, target);
814
815 if (ppm < 100 && clock.p > best_clock->p) {
816 bestppm = 0;
817 *best_clock = clock;
818 found = true;
819 }
820
821 if (bestppm >= 10 && ppm < bestppm - 10) {
822 bestppm = ppm;
823 *best_clock = clock;
824 found = true;
825 }
826 }
827 }
828 }
829 }
830
831 return found;
832 }
833
834 static bool
835 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
836 int target, int refclk, intel_clock_t *match_clock,
837 intel_clock_t *best_clock)
838 {
839 struct drm_device *dev = crtc->base.dev;
840 intel_clock_t clock;
841 uint64_t m2;
842 int found = false;
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 /*
847 * Based on hardware doc, the n always set to 1, and m1 always
848 * set to 2. If requires to support 200Mhz refclk, we need to
849 * revisit this because n may not 1 anymore.
850 */
851 clock.n = 1, clock.m1 = 2;
852 target *= 5; /* fast clock */
853
854 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
855 for (clock.p2 = limit->p2.p2_fast;
856 clock.p2 >= limit->p2.p2_slow;
857 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
858
859 clock.p = clock.p1 * clock.p2;
860
861 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
862 clock.n) << 22, refclk * clock.m1);
863
864 if (m2 > INT_MAX/clock.m1)
865 continue;
866
867 clock.m2 = m2;
868
869 chv_clock(refclk, &clock);
870
871 if (!intel_PLL_is_valid(dev, limit, &clock))
872 continue;
873
874 /* based on hardware requirement, prefer bigger p
875 */
876 if (clock.p > best_clock->p) {
877 *best_clock = clock;
878 found = true;
879 }
880 }
881 }
882
883 return found;
884 }
885
886 bool intel_crtc_active(struct drm_crtc *crtc)
887 {
888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
889
890 /* Be paranoid as we can arrive here with only partial
891 * state retrieved from the hardware during setup.
892 *
893 * We can ditch the adjusted_mode.crtc_clock check as soon
894 * as Haswell has gained clock readout/fastboot support.
895 *
896 * We can ditch the crtc->primary->fb check as soon as we can
897 * properly reconstruct framebuffers.
898 */
899 return intel_crtc->active && crtc->primary->fb &&
900 intel_crtc->config->base.adjusted_mode.crtc_clock;
901 }
902
903 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
908
909 return intel_crtc->config->cpu_transcoder;
910 }
911
912 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 u32 reg = PIPEDSL(pipe);
916 u32 line1, line2;
917 u32 line_mask;
918
919 if (IS_GEN2(dev))
920 line_mask = DSL_LINEMASK_GEN2;
921 else
922 line_mask = DSL_LINEMASK_GEN3;
923
924 line1 = I915_READ(reg) & line_mask;
925 mdelay(5);
926 line2 = I915_READ(reg) & line_mask;
927
928 return line1 == line2;
929 }
930
931 /*
932 * intel_wait_for_pipe_off - wait for pipe to turn off
933 * @crtc: crtc whose pipe to wait for
934 *
935 * After disabling a pipe, we can't wait for vblank in the usual way,
936 * spinning on the vblank interrupt status bit, since we won't actually
937 * see an interrupt when the pipe is disabled.
938 *
939 * On Gen4 and above:
940 * wait for the pipe register state bit to turn off
941 *
942 * Otherwise:
943 * wait for the display line value to settle (it usually
944 * ends up stopping at the start of the next frame).
945 *
946 */
947 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
948 {
949 struct drm_device *dev = crtc->base.dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
952 enum pipe pipe = crtc->pipe;
953
954 if (INTEL_INFO(dev)->gen >= 4) {
955 int reg = PIPECONF(cpu_transcoder);
956
957 /* Wait for the Pipe State to go off */
958 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
959 100))
960 WARN(1, "pipe_off wait timed out\n");
961 } else {
962 /* Wait for the display line to settle */
963 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
964 WARN(1, "pipe_off wait timed out\n");
965 }
966 }
967
968 /*
969 * ibx_digital_port_connected - is the specified port connected?
970 * @dev_priv: i915 private structure
971 * @port: the port to test
972 *
973 * Returns true if @port is connected, false otherwise.
974 */
975 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
976 struct intel_digital_port *port)
977 {
978 u32 bit;
979
980 if (HAS_PCH_IBX(dev_priv->dev)) {
981 switch (port->port) {
982 case PORT_B:
983 bit = SDE_PORTB_HOTPLUG;
984 break;
985 case PORT_C:
986 bit = SDE_PORTC_HOTPLUG;
987 break;
988 case PORT_D:
989 bit = SDE_PORTD_HOTPLUG;
990 break;
991 default:
992 return true;
993 }
994 } else {
995 switch (port->port) {
996 case PORT_B:
997 bit = SDE_PORTB_HOTPLUG_CPT;
998 break;
999 case PORT_C:
1000 bit = SDE_PORTC_HOTPLUG_CPT;
1001 break;
1002 case PORT_D:
1003 bit = SDE_PORTD_HOTPLUG_CPT;
1004 break;
1005 default:
1006 return true;
1007 }
1008 }
1009
1010 return I915_READ(SDEISR) & bit;
1011 }
1012
1013 static const char *state_string(bool enabled)
1014 {
1015 return enabled ? "on" : "off";
1016 }
1017
1018 /* Only for pre-ILK configs */
1019 void assert_pll(struct drm_i915_private *dev_priv,
1020 enum pipe pipe, bool state)
1021 {
1022 int reg;
1023 u32 val;
1024 bool cur_state;
1025
1026 reg = DPLL(pipe);
1027 val = I915_READ(reg);
1028 cur_state = !!(val & DPLL_VCO_ENABLE);
1029 I915_STATE_WARN(cur_state != state,
1030 "PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state), state_string(cur_state));
1032 }
1033
1034 /* XXX: the dsi pll is shared between MIPI DSI ports */
1035 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 mutex_lock(&dev_priv->dpio_lock);
1041 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1042 mutex_unlock(&dev_priv->dpio_lock);
1043
1044 cur_state = val & DSI_PLL_VCO_EN;
1045 I915_STATE_WARN(cur_state != state,
1046 "DSI PLL state assertion failure (expected %s, current %s)\n",
1047 state_string(state), state_string(cur_state));
1048 }
1049 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1050 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1051
1052 struct intel_shared_dpll *
1053 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1054 {
1055 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1056
1057 if (crtc->config->shared_dpll < 0)
1058 return NULL;
1059
1060 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1061 }
1062
1063 /* For ILK+ */
1064 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1065 struct intel_shared_dpll *pll,
1066 bool state)
1067 {
1068 bool cur_state;
1069 struct intel_dpll_hw_state hw_state;
1070
1071 if (WARN (!pll,
1072 "asserting DPLL %s with no DPLL\n", state_string(state)))
1073 return;
1074
1075 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1076 I915_STATE_WARN(cur_state != state,
1077 "%s assertion failure (expected %s, current %s)\n",
1078 pll->name, state_string(state), state_string(cur_state));
1079 }
1080
1081 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083 {
1084 int reg;
1085 u32 val;
1086 bool cur_state;
1087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1088 pipe);
1089
1090 if (HAS_DDI(dev_priv->dev)) {
1091 /* DDI does not have a specific FDI_TX register */
1092 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1095 } else {
1096 reg = FDI_TX_CTL(pipe);
1097 val = I915_READ(reg);
1098 cur_state = !!(val & FDI_TX_ENABLE);
1099 }
1100 I915_STATE_WARN(cur_state != state,
1101 "FDI TX state assertion failure (expected %s, current %s)\n",
1102 state_string(state), state_string(cur_state));
1103 }
1104 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1105 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1106
1107 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = FDI_RX_CTL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & FDI_RX_ENABLE);
1117 I915_STATE_WARN(cur_state != state,
1118 "FDI RX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1122 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1123
1124 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe)
1126 {
1127 int reg;
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv->dev))
1136 return;
1137
1138 reg = FDI_TX_CTL(pipe);
1139 val = I915_READ(reg);
1140 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 }
1142
1143 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, bool state)
1145 {
1146 int reg;
1147 u32 val;
1148 bool cur_state;
1149
1150 reg = FDI_RX_CTL(pipe);
1151 val = I915_READ(reg);
1152 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157
1158 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 struct drm_device *dev = dev_priv->dev;
1162 int pp_reg;
1163 u32 val;
1164 enum pipe panel_pipe = PIPE_A;
1165 bool locked = true;
1166
1167 if (WARN_ON(HAS_DDI(dev)))
1168 return;
1169
1170 if (HAS_PCH_SPLIT(dev)) {
1171 u32 port_sel;
1172
1173 pp_reg = PCH_PP_CONTROL;
1174 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1175
1176 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1177 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179 /* XXX: else fix for eDP */
1180 } else if (IS_VALLEYVIEW(dev)) {
1181 /* presumably write lock depends on pipe, not port select */
1182 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1183 panel_pipe = pipe;
1184 } else {
1185 pp_reg = PP_CONTROL;
1186 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1187 panel_pipe = PIPE_B;
1188 }
1189
1190 val = I915_READ(pp_reg);
1191 if (!(val & PANEL_POWER_ON) ||
1192 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 locked = false;
1194
1195 I915_STATE_WARN(panel_pipe == pipe && locked,
1196 "panel assertion failure, pipe %c regs locked\n",
1197 pipe_name(pipe));
1198 }
1199
1200 static void assert_cursor(struct drm_i915_private *dev_priv,
1201 enum pipe pipe, bool state)
1202 {
1203 struct drm_device *dev = dev_priv->dev;
1204 bool cur_state;
1205
1206 if (IS_845G(dev) || IS_I865G(dev))
1207 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1208 else
1209 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1210
1211 I915_STATE_WARN(cur_state != state,
1212 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1213 pipe_name(pipe), state_string(state), state_string(cur_state));
1214 }
1215 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1216 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1217
1218 void assert_pipe(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 int reg;
1222 u32 val;
1223 bool cur_state;
1224 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 pipe);
1226
1227 /* if we need the pipe quirk it must be always on */
1228 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1229 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1230 state = true;
1231
1232 if (!intel_display_power_is_enabled(dev_priv,
1233 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1234 cur_state = false;
1235 } else {
1236 reg = PIPECONF(cpu_transcoder);
1237 val = I915_READ(reg);
1238 cur_state = !!(val & PIPECONF_ENABLE);
1239 }
1240
1241 I915_STATE_WARN(cur_state != state,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 }
1245
1246 static void assert_plane(struct drm_i915_private *dev_priv,
1247 enum plane plane, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = DSPCNTR(plane);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "plane %c assertion failure (expected %s, current %s)\n",
1258 plane_name(plane), state_string(state), state_string(cur_state));
1259 }
1260
1261 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1262 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1263
1264 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe)
1266 {
1267 struct drm_device *dev = dev_priv->dev;
1268 int reg, i;
1269 u32 val;
1270 int cur_pipe;
1271
1272 /* Primary planes are fixed to pipes on gen4+ */
1273 if (INTEL_INFO(dev)->gen >= 4) {
1274 reg = DSPCNTR(pipe);
1275 val = I915_READ(reg);
1276 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1277 "plane %c assertion failure, should be disabled but not\n",
1278 plane_name(pipe));
1279 return;
1280 }
1281
1282 /* Need to check both planes against the pipe */
1283 for_each_pipe(dev_priv, i) {
1284 reg = DSPCNTR(i);
1285 val = I915_READ(reg);
1286 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287 DISPPLANE_SEL_PIPE_SHIFT;
1288 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i), pipe_name(pipe));
1291 }
1292 }
1293
1294 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = dev_priv->dev;
1298 int reg, sprite;
1299 u32 val;
1300
1301 if (INTEL_INFO(dev)->gen >= 9) {
1302 for_each_sprite(pipe, sprite) {
1303 val = I915_READ(PLANE_CTL(pipe, sprite));
1304 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1305 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1306 sprite, pipe_name(pipe));
1307 }
1308 } else if (IS_VALLEYVIEW(dev)) {
1309 for_each_sprite(pipe, sprite) {
1310 reg = SPCNTR(pipe, sprite);
1311 val = I915_READ(reg);
1312 I915_STATE_WARN(val & SP_ENABLE,
1313 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1314 sprite_name(pipe, sprite), pipe_name(pipe));
1315 }
1316 } else if (INTEL_INFO(dev)->gen >= 7) {
1317 reg = SPRCTL(pipe);
1318 val = I915_READ(reg);
1319 I915_STATE_WARN(val & SPRITE_ENABLE,
1320 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(pipe), pipe_name(pipe));
1322 } else if (INTEL_INFO(dev)->gen >= 5) {
1323 reg = DVSCNTR(pipe);
1324 val = I915_READ(reg);
1325 I915_STATE_WARN(val & DVS_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_vblank_disabled(struct drm_crtc *crtc)
1332 {
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1334 drm_crtc_vblank_put(crtc);
1335 }
1336
1337 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1338 {
1339 u32 val;
1340 bool enabled;
1341
1342 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1343
1344 val = I915_READ(PCH_DREF_CONTROL);
1345 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1346 DREF_SUPERSPREAD_SOURCE_MASK));
1347 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348 }
1349
1350 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1351 enum pipe pipe)
1352 {
1353 int reg;
1354 u32 val;
1355 bool enabled;
1356
1357 reg = PCH_TRANSCONF(pipe);
1358 val = I915_READ(reg);
1359 enabled = !!(val & TRANS_ENABLE);
1360 I915_STATE_WARN(enabled,
1361 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1362 pipe_name(pipe));
1363 }
1364
1365 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 port_sel, u32 val)
1367 {
1368 if ((val & DP_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1373 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1374 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1375 return false;
1376 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1377 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1378 return false;
1379 } else {
1380 if ((val & DP_PIPE_MASK) != (pipe << 30))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & SDVO_ENABLE) == 0)
1390 return false;
1391
1392 if (HAS_PCH_CPT(dev_priv->dev)) {
1393 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1394 return false;
1395 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1396 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1397 return false;
1398 } else {
1399 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1400 return false;
1401 }
1402 return true;
1403 }
1404
1405 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1406 enum pipe pipe, u32 val)
1407 {
1408 if ((val & LVDS_PORT_EN) == 0)
1409 return false;
1410
1411 if (HAS_PCH_CPT(dev_priv->dev)) {
1412 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1413 return false;
1414 } else {
1415 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1416 return false;
1417 }
1418 return true;
1419 }
1420
1421 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1422 enum pipe pipe, u32 val)
1423 {
1424 if ((val & ADPA_DAC_ENABLE) == 0)
1425 return false;
1426 if (HAS_PCH_CPT(dev_priv->dev)) {
1427 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1428 return false;
1429 } else {
1430 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg, u32 port_sel)
1438 {
1439 u32 val = I915_READ(reg);
1440 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1441 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1442 reg, pipe_name(pipe));
1443
1444 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1445 && (val & DP_PIPEB_SELECT),
1446 "IBX PCH dp port still using transcoder B\n");
1447 }
1448
1449 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, int reg)
1451 {
1452 u32 val = I915_READ(reg);
1453 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1454 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1455 reg, pipe_name(pipe));
1456
1457 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1458 && (val & SDVO_PIPE_B_SELECT),
1459 "IBX PCH hdmi port still using transcoder B\n");
1460 }
1461
1462 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe)
1464 {
1465 int reg;
1466 u32 val;
1467
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471
1472 reg = PCH_ADPA;
1473 val = I915_READ(reg);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 reg = PCH_LVDS;
1479 val = I915_READ(reg);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 pipe_name(pipe));
1483
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 }
1488
1489 static void intel_init_dpio(struct drm_device *dev)
1490 {
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492
1493 if (!IS_VALLEYVIEW(dev))
1494 return;
1495
1496 /*
1497 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1498 * CHV x1 PHY (DP/HDMI D)
1499 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1500 */
1501 if (IS_CHERRYVIEW(dev)) {
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1504 } else {
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1506 }
1507 }
1508
1509 static void vlv_enable_pll(struct intel_crtc *crtc,
1510 const struct intel_crtc_state *pipe_config)
1511 {
1512 struct drm_device *dev = crtc->base.dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 int reg = DPLL(crtc->pipe);
1515 u32 dpll = pipe_config->dpll_hw_state.dpll;
1516
1517 assert_pipe_disabled(dev_priv, crtc->pipe);
1518
1519 /* No really, not for ILK+ */
1520 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1521
1522 /* PLL is protected by panel, make sure we can write it */
1523 if (IS_MOBILE(dev_priv->dev))
1524 assert_panel_unlocked(dev_priv, crtc->pipe);
1525
1526 I915_WRITE(reg, dpll);
1527 POSTING_READ(reg);
1528 udelay(150);
1529
1530 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1531 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1532
1533 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1534 POSTING_READ(DPLL_MD(crtc->pipe));
1535
1536 /* We do this three times for luck */
1537 I915_WRITE(reg, dpll);
1538 POSTING_READ(reg);
1539 udelay(150); /* wait for warmup */
1540 I915_WRITE(reg, dpll);
1541 POSTING_READ(reg);
1542 udelay(150); /* wait for warmup */
1543 I915_WRITE(reg, dpll);
1544 POSTING_READ(reg);
1545 udelay(150); /* wait for warmup */
1546 }
1547
1548 static void chv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_state *pipe_config)
1550 {
1551 struct drm_device *dev = crtc->base.dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 int pipe = crtc->pipe;
1554 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1555 u32 tmp;
1556
1557 assert_pipe_disabled(dev_priv, crtc->pipe);
1558
1559 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1560
1561 mutex_lock(&dev_priv->dpio_lock);
1562
1563 /* Enable back the 10bit clock to display controller */
1564 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1565 tmp |= DPIO_DCLKP_EN;
1566 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1567
1568 /*
1569 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1570 */
1571 udelay(1);
1572
1573 /* Enable PLL */
1574 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1575
1576 /* Check PLL is locked */
1577 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1578 DRM_ERROR("PLL %d failed to lock\n", pipe);
1579
1580 /* not sure when this should be written */
1581 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1582 POSTING_READ(DPLL_MD(pipe));
1583
1584 mutex_unlock(&dev_priv->dpio_lock);
1585 }
1586
1587 static int intel_num_dvo_pipes(struct drm_device *dev)
1588 {
1589 struct intel_crtc *crtc;
1590 int count = 0;
1591
1592 for_each_intel_crtc(dev, crtc)
1593 count += crtc->active &&
1594 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1595
1596 return count;
1597 }
1598
1599 static void i9xx_enable_pll(struct intel_crtc *crtc)
1600 {
1601 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config->dpll_hw_state.dpll;
1605
1606 assert_pipe_disabled(dev_priv, crtc->pipe);
1607
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev) && !IS_I830(dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 /* Enable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1617 /*
1618 * It appears to be important that we don't enable this
1619 * for the current pipe before otherwise configuring the
1620 * PLL. No idea how this should be handled if multiple
1621 * DVO outputs are enabled simultaneosly.
1622 */
1623 dpll |= DPLL_DVO_2X_MODE;
1624 I915_WRITE(DPLL(!crtc->pipe),
1625 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1626 }
1627
1628 /* Wait for the clocks to stabilize. */
1629 POSTING_READ(reg);
1630 udelay(150);
1631
1632 if (INTEL_INFO(dev)->gen >= 4) {
1633 I915_WRITE(DPLL_MD(crtc->pipe),
1634 crtc->config->dpll_hw_state.dpll_md);
1635 } else {
1636 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable.
1638 *
1639 * So write it again.
1640 */
1641 I915_WRITE(reg, dpll);
1642 }
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 /**
1657 * i9xx_disable_pll - disable a PLL
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe PLL to disable
1660 *
1661 * Disable the PLL for @pipe, making sure the pipe is off first.
1662 *
1663 * Note! This is for pre-ILK only.
1664 */
1665 static void i9xx_disable_pll(struct intel_crtc *crtc)
1666 {
1667 struct drm_device *dev = crtc->base.dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 enum pipe pipe = crtc->pipe;
1670
1671 /* Disable DVO 2x clock on both PLLs if necessary */
1672 if (IS_I830(dev) &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1674 intel_num_dvo_pipes(dev) == 1) {
1675 I915_WRITE(DPLL(PIPE_B),
1676 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1677 I915_WRITE(DPLL(PIPE_A),
1678 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1679 }
1680
1681 /* Don't disable pipe or pipe PLLs if needed */
1682 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1683 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1684 return;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 I915_WRITE(DPLL(pipe), 0);
1690 POSTING_READ(DPLL(pipe));
1691 }
1692
1693 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695 u32 val = 0;
1696
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv, pipe);
1699
1700 /*
1701 * Leave integrated clock source and reference clock enabled for pipe B.
1702 * The latter is needed for VGA hotplug / manual detection.
1703 */
1704 if (pipe == PIPE_B)
1705 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
1708
1709 }
1710
1711 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 /* Set PLL en = 0 */
1720 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723 I915_WRITE(DPLL(pipe), val);
1724 POSTING_READ(DPLL(pipe));
1725
1726 mutex_lock(&dev_priv->dpio_lock);
1727
1728 /* Disable 10bit clock to display controller */
1729 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1730 val &= ~DPIO_DCLKP_EN;
1731 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1732
1733 /* disable left/right clock distribution */
1734 if (pipe != PIPE_B) {
1735 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1736 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1737 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1738 } else {
1739 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1740 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1741 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1742 }
1743
1744 mutex_unlock(&dev_priv->dpio_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport)
1749 {
1750 u32 port_mask;
1751 int dpll_reg;
1752
1753 switch (dport->port) {
1754 case PORT_B:
1755 port_mask = DPLL_PORTB_READY_MASK;
1756 dpll_reg = DPLL(0);
1757 break;
1758 case PORT_C:
1759 port_mask = DPLL_PORTC_READY_MASK;
1760 dpll_reg = DPLL(0);
1761 break;
1762 case PORT_D:
1763 port_mask = DPLL_PORTD_READY_MASK;
1764 dpll_reg = DPIO_PHY_STATUS;
1765 break;
1766 default:
1767 BUG();
1768 }
1769
1770 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1771 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1772 port_name(dport->port), I915_READ(dpll_reg));
1773 }
1774
1775 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1776 {
1777 struct drm_device *dev = crtc->base.dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1780
1781 if (WARN_ON(pll == NULL))
1782 return;
1783
1784 WARN_ON(!pll->config.crtc_mask);
1785 if (pll->active == 0) {
1786 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1787 WARN_ON(pll->on);
1788 assert_shared_dpll_disabled(dev_priv, pll);
1789
1790 pll->mode_set(dev_priv, pll);
1791 }
1792 }
1793
1794 /**
1795 * intel_enable_shared_dpll - enable PCH PLL
1796 * @dev_priv: i915 private structure
1797 * @pipe: pipe PLL to enable
1798 *
1799 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1800 * drives the transcoder clock.
1801 */
1802 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1803 {
1804 struct drm_device *dev = crtc->base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1807
1808 if (WARN_ON(pll == NULL))
1809 return;
1810
1811 if (WARN_ON(pll->config.crtc_mask == 0))
1812 return;
1813
1814 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
1816 crtc->base.base.id);
1817
1818 if (pll->active++) {
1819 WARN_ON(!pll->on);
1820 assert_shared_dpll_enabled(dev_priv, pll);
1821 return;
1822 }
1823 WARN_ON(pll->on);
1824
1825 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1826
1827 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1828 pll->enable(dev_priv, pll);
1829 pll->on = true;
1830 }
1831
1832 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1833 {
1834 struct drm_device *dev = crtc->base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1837
1838 /* PCH only available on ILK+ */
1839 BUG_ON(INTEL_INFO(dev)->gen < 5);
1840 if (WARN_ON(pll == NULL))
1841 return;
1842
1843 if (WARN_ON(pll->config.crtc_mask == 0))
1844 return;
1845
1846 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1847 pll->name, pll->active, pll->on,
1848 crtc->base.base.id);
1849
1850 if (WARN_ON(pll->active == 0)) {
1851 assert_shared_dpll_disabled(dev_priv, pll);
1852 return;
1853 }
1854
1855 assert_shared_dpll_enabled(dev_priv, pll);
1856 WARN_ON(!pll->on);
1857 if (--pll->active)
1858 return;
1859
1860 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1861 pll->disable(dev_priv, pll);
1862 pll->on = false;
1863
1864 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1865 }
1866
1867 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 enum pipe pipe)
1869 {
1870 struct drm_device *dev = dev_priv->dev;
1871 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1873 uint32_t reg, val, pipeconf_val;
1874
1875 /* PCH only available on ILK+ */
1876 BUG_ON(!HAS_PCH_SPLIT(dev));
1877
1878 /* Make sure PCH DPLL is enabled */
1879 assert_shared_dpll_enabled(dev_priv,
1880 intel_crtc_to_shared_dpll(intel_crtc));
1881
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv, pipe);
1884 assert_fdi_rx_enabled(dev_priv, pipe);
1885
1886 if (HAS_PCH_CPT(dev)) {
1887 /* Workaround: Set the timing override bit before enabling the
1888 * pch transcoder. */
1889 reg = TRANS_CHICKEN2(pipe);
1890 val = I915_READ(reg);
1891 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1892 I915_WRITE(reg, val);
1893 }
1894
1895 reg = PCH_TRANSCONF(pipe);
1896 val = I915_READ(reg);
1897 pipeconf_val = I915_READ(PIPECONF(pipe));
1898
1899 if (HAS_PCH_IBX(dev_priv->dev)) {
1900 /*
1901 * make the BPC in transcoder be consistent with
1902 * that in pipeconf reg.
1903 */
1904 val &= ~PIPECONF_BPC_MASK;
1905 val |= pipeconf_val & PIPECONF_BPC_MASK;
1906 }
1907
1908 val &= ~TRANS_INTERLACE_MASK;
1909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1910 if (HAS_PCH_IBX(dev_priv->dev) &&
1911 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1912 val |= TRANS_LEGACY_INTERLACED_ILK;
1913 else
1914 val |= TRANS_INTERLACED;
1915 else
1916 val |= TRANS_PROGRESSIVE;
1917
1918 I915_WRITE(reg, val | TRANS_ENABLE);
1919 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1920 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1921 }
1922
1923 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1924 enum transcoder cpu_transcoder)
1925 {
1926 u32 val, pipeconf_val;
1927
1928 /* PCH only available on ILK+ */
1929 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1930
1931 /* FDI must be feeding us bits for PCH ports */
1932 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1933 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1934
1935 /* Workaround: set timing override bit. */
1936 val = I915_READ(_TRANSA_CHICKEN2);
1937 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1938 I915_WRITE(_TRANSA_CHICKEN2, val);
1939
1940 val = TRANS_ENABLE;
1941 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1942
1943 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1944 PIPECONF_INTERLACED_ILK)
1945 val |= TRANS_INTERLACED;
1946 else
1947 val |= TRANS_PROGRESSIVE;
1948
1949 I915_WRITE(LPT_TRANSCONF, val);
1950 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1951 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 }
1953
1954 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 enum pipe pipe)
1956 {
1957 struct drm_device *dev = dev_priv->dev;
1958 uint32_t reg, val;
1959
1960 /* FDI relies on the transcoder */
1961 assert_fdi_tx_disabled(dev_priv, pipe);
1962 assert_fdi_rx_disabled(dev_priv, pipe);
1963
1964 /* Ports must be off as well */
1965 assert_pch_ports_disabled(dev_priv, pipe);
1966
1967 reg = PCH_TRANSCONF(pipe);
1968 val = I915_READ(reg);
1969 val &= ~TRANS_ENABLE;
1970 I915_WRITE(reg, val);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1973 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1974
1975 if (!HAS_PCH_IBX(dev)) {
1976 /* Workaround: Clear the timing override chicken bit again. */
1977 reg = TRANS_CHICKEN2(pipe);
1978 val = I915_READ(reg);
1979 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1980 I915_WRITE(reg, val);
1981 }
1982 }
1983
1984 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1985 {
1986 u32 val;
1987
1988 val = I915_READ(LPT_TRANSCONF);
1989 val &= ~TRANS_ENABLE;
1990 I915_WRITE(LPT_TRANSCONF, val);
1991 /* wait for PCH transcoder off, transcoder state */
1992 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1993 DRM_ERROR("Failed to disable PCH transcoder\n");
1994
1995 /* Workaround: clear timing override bit. */
1996 val = I915_READ(_TRANSA_CHICKEN2);
1997 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(_TRANSA_CHICKEN2, val);
1999 }
2000
2001 /**
2002 * intel_enable_pipe - enable a pipe, asserting requirements
2003 * @crtc: crtc responsible for the pipe
2004 *
2005 * Enable @crtc's pipe, making sure that various hardware specific requirements
2006 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2007 */
2008 static void intel_enable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_device *dev = crtc->base.dev;
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 enum pipe pipe = crtc->pipe;
2013 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2014 pipe);
2015 enum pipe pch_transcoder;
2016 int reg;
2017 u32 val;
2018
2019 assert_planes_disabled(dev_priv, pipe);
2020 assert_cursor_disabled(dev_priv, pipe);
2021 assert_sprites_disabled(dev_priv, pipe);
2022
2023 if (HAS_PCH_LPT(dev_priv->dev))
2024 pch_transcoder = TRANSCODER_A;
2025 else
2026 pch_transcoder = pipe;
2027
2028 /*
2029 * A pipe without a PLL won't actually be able to drive bits from
2030 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 * need the check.
2032 */
2033 if (!HAS_PCH_SPLIT(dev_priv->dev))
2034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2035 assert_dsi_pll_enabled(dev_priv);
2036 else
2037 assert_pll_enabled(dev_priv, pipe);
2038 else {
2039 if (crtc->config->has_pch_encoder) {
2040 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2042 assert_fdi_tx_pll_enabled(dev_priv,
2043 (enum pipe) cpu_transcoder);
2044 }
2045 /* FIXME: assert CPU port conditions for SNB+ */
2046 }
2047
2048 reg = PIPECONF(cpu_transcoder);
2049 val = I915_READ(reg);
2050 if (val & PIPECONF_ENABLE) {
2051 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2052 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2053 return;
2054 }
2055
2056 I915_WRITE(reg, val | PIPECONF_ENABLE);
2057 POSTING_READ(reg);
2058 }
2059
2060 /**
2061 * intel_disable_pipe - disable a pipe, asserting requirements
2062 * @crtc: crtc whose pipes is to be disabled
2063 *
2064 * Disable the pipe of @crtc, making sure that various hardware
2065 * specific requirements are met, if applicable, e.g. plane
2066 * disabled, panel fitter off, etc.
2067 *
2068 * Will wait until the pipe has shut down before returning.
2069 */
2070 static void intel_disable_pipe(struct intel_crtc *crtc)
2071 {
2072 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2073 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2074 enum pipe pipe = crtc->pipe;
2075 int reg;
2076 u32 val;
2077
2078 /*
2079 * Make sure planes won't keep trying to pump pixels to us,
2080 * or we might hang the display.
2081 */
2082 assert_planes_disabled(dev_priv, pipe);
2083 assert_cursor_disabled(dev_priv, pipe);
2084 assert_sprites_disabled(dev_priv, pipe);
2085
2086 reg = PIPECONF(cpu_transcoder);
2087 val = I915_READ(reg);
2088 if ((val & PIPECONF_ENABLE) == 0)
2089 return;
2090
2091 /*
2092 * Double wide has implications for planes
2093 * so best keep it disabled when not needed.
2094 */
2095 if (crtc->config->double_wide)
2096 val &= ~PIPECONF_DOUBLE_WIDE;
2097
2098 /* Don't disable pipe or pipe PLLs if needed */
2099 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2100 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2101 val &= ~PIPECONF_ENABLE;
2102
2103 I915_WRITE(reg, val);
2104 if ((val & PIPECONF_ENABLE) == 0)
2105 intel_wait_for_pipe_off(crtc);
2106 }
2107
2108 /*
2109 * Plane regs are double buffered, going from enabled->disabled needs a
2110 * trigger in order to latch. The display address reg provides this.
2111 */
2112 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2113 enum plane plane)
2114 {
2115 struct drm_device *dev = dev_priv->dev;
2116 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2117
2118 I915_WRITE(reg, I915_READ(reg));
2119 POSTING_READ(reg);
2120 }
2121
2122 /**
2123 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2124 * @plane: plane to be enabled
2125 * @crtc: crtc for the plane
2126 *
2127 * Enable @plane on @crtc, making sure that the pipe is running first.
2128 */
2129 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2130 struct drm_crtc *crtc)
2131 {
2132 struct drm_device *dev = plane->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135
2136 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2137 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2138
2139 if (intel_crtc->primary_enabled)
2140 return;
2141
2142 intel_crtc->primary_enabled = true;
2143
2144 dev_priv->display.update_primary_plane(crtc, plane->fb,
2145 crtc->x, crtc->y);
2146
2147 /*
2148 * BDW signals flip done immediately if the plane
2149 * is disabled, even if the plane enable is already
2150 * armed to occur at the next vblank :(
2151 */
2152 if (IS_BROADWELL(dev))
2153 intel_wait_for_vblank(dev, intel_crtc->pipe);
2154 }
2155
2156 /**
2157 * intel_disable_primary_hw_plane - disable the primary hardware plane
2158 * @plane: plane to be disabled
2159 * @crtc: crtc for the plane
2160 *
2161 * Disable @plane on @crtc, making sure that the pipe is running first.
2162 */
2163 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2164 struct drm_crtc *crtc)
2165 {
2166 struct drm_device *dev = plane->dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (WARN_ON(!intel_crtc->active))
2171 return;
2172
2173 if (!intel_crtc->primary_enabled)
2174 return;
2175
2176 intel_crtc->primary_enabled = false;
2177
2178 dev_priv->display.update_primary_plane(crtc, plane->fb,
2179 crtc->x, crtc->y);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186 return true;
2187 #endif
2188 return false;
2189 }
2190
2191 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2192 {
2193 int tile_height;
2194
2195 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2196 return ALIGN(height, tile_height);
2197 }
2198
2199 int
2200 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2201 struct drm_framebuffer *fb,
2202 struct intel_engine_cs *pipelined)
2203 {
2204 struct drm_device *dev = fb->dev;
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2207 u32 alignment;
2208 int ret;
2209
2210 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2211
2212 switch (obj->tiling_mode) {
2213 case I915_TILING_NONE:
2214 if (INTEL_INFO(dev)->gen >= 9)
2215 alignment = 256 * 1024;
2216 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2217 alignment = 128 * 1024;
2218 else if (INTEL_INFO(dev)->gen >= 4)
2219 alignment = 4 * 1024;
2220 else
2221 alignment = 64 * 1024;
2222 break;
2223 case I915_TILING_X:
2224 if (INTEL_INFO(dev)->gen >= 9)
2225 alignment = 256 * 1024;
2226 else {
2227 /* pin() will align the object as required by fence */
2228 alignment = 0;
2229 }
2230 break;
2231 case I915_TILING_Y:
2232 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2233 return -EINVAL;
2234 default:
2235 BUG();
2236 }
2237
2238 /* Note that the w/a also requires 64 PTE of padding following the
2239 * bo. We currently fill all unused PTE with the shadow page and so
2240 * we should always have valid PTE following the scanout preventing
2241 * the VT-d warning.
2242 */
2243 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2244 alignment = 256 * 1024;
2245
2246 /*
2247 * Global gtt pte registers are special registers which actually forward
2248 * writes to a chunk of system memory. Which means that there is no risk
2249 * that the register values disappear as soon as we call
2250 * intel_runtime_pm_put(), so it is correct to wrap only the
2251 * pin/unpin/fence and not more.
2252 */
2253 intel_runtime_pm_get(dev_priv);
2254
2255 dev_priv->mm.interruptible = false;
2256 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2257 if (ret)
2258 goto err_interruptible;
2259
2260 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2261 * fence, whereas 965+ only requires a fence if using
2262 * framebuffer compression. For simplicity, we always install
2263 * a fence as the cost is not that onerous.
2264 */
2265 ret = i915_gem_object_get_fence(obj);
2266 if (ret)
2267 goto err_unpin;
2268
2269 i915_gem_object_pin_fence(obj);
2270
2271 dev_priv->mm.interruptible = true;
2272 intel_runtime_pm_put(dev_priv);
2273 return 0;
2274
2275 err_unpin:
2276 i915_gem_object_unpin_from_display_plane(obj);
2277 err_interruptible:
2278 dev_priv->mm.interruptible = true;
2279 intel_runtime_pm_put(dev_priv);
2280 return ret;
2281 }
2282
2283 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2284 {
2285 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2286
2287 i915_gem_object_unpin_fence(obj);
2288 i915_gem_object_unpin_from_display_plane(obj);
2289 }
2290
2291 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2292 * is assumed to be a power-of-two. */
2293 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2294 unsigned int tiling_mode,
2295 unsigned int cpp,
2296 unsigned int pitch)
2297 {
2298 if (tiling_mode != I915_TILING_NONE) {
2299 unsigned int tile_rows, tiles;
2300
2301 tile_rows = *y / 8;
2302 *y %= 8;
2303
2304 tiles = *x / (512/cpp);
2305 *x %= 512/cpp;
2306
2307 return tile_rows * pitch * 8 + tiles * 4096;
2308 } else {
2309 unsigned int offset;
2310
2311 offset = *y * pitch + *x * cpp;
2312 *y = 0;
2313 *x = (offset & 4095) / cpp;
2314 return offset & -4096;
2315 }
2316 }
2317
2318 int intel_format_to_fourcc(int format)
2319 {
2320 switch (format) {
2321 case DISPPLANE_8BPP:
2322 return DRM_FORMAT_C8;
2323 case DISPPLANE_BGRX555:
2324 return DRM_FORMAT_XRGB1555;
2325 case DISPPLANE_BGRX565:
2326 return DRM_FORMAT_RGB565;
2327 default:
2328 case DISPPLANE_BGRX888:
2329 return DRM_FORMAT_XRGB8888;
2330 case DISPPLANE_RGBX888:
2331 return DRM_FORMAT_XBGR8888;
2332 case DISPPLANE_BGRX101010:
2333 return DRM_FORMAT_XRGB2101010;
2334 case DISPPLANE_RGBX101010:
2335 return DRM_FORMAT_XBGR2101010;
2336 }
2337 }
2338
2339 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2340 struct intel_plane_config *plane_config)
2341 {
2342 struct drm_device *dev = crtc->base.dev;
2343 struct drm_i915_gem_object *obj = NULL;
2344 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2345 u32 base = plane_config->base;
2346
2347 if (plane_config->size == 0)
2348 return false;
2349
2350 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2351 plane_config->size);
2352 if (!obj)
2353 return false;
2354
2355 if (plane_config->tiled) {
2356 obj->tiling_mode = I915_TILING_X;
2357 obj->stride = crtc->base.primary->fb->pitches[0];
2358 }
2359
2360 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2361 mode_cmd.width = crtc->base.primary->fb->width;
2362 mode_cmd.height = crtc->base.primary->fb->height;
2363 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2364
2365 mutex_lock(&dev->struct_mutex);
2366
2367 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2368 &mode_cmd, obj)) {
2369 DRM_DEBUG_KMS("intel fb init failed\n");
2370 goto out_unref_obj;
2371 }
2372
2373 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2374 mutex_unlock(&dev->struct_mutex);
2375
2376 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2377 return true;
2378
2379 out_unref_obj:
2380 drm_gem_object_unreference(&obj->base);
2381 mutex_unlock(&dev->struct_mutex);
2382 return false;
2383 }
2384
2385 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2386 struct intel_plane_config *plane_config)
2387 {
2388 struct drm_device *dev = intel_crtc->base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct drm_crtc *c;
2391 struct intel_crtc *i;
2392 struct drm_i915_gem_object *obj;
2393
2394 if (!intel_crtc->base.primary->fb)
2395 return;
2396
2397 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2398 return;
2399
2400 kfree(intel_crtc->base.primary->fb);
2401 intel_crtc->base.primary->fb = NULL;
2402
2403 /*
2404 * Failed to alloc the obj, check to see if we should share
2405 * an fb with another CRTC instead
2406 */
2407 for_each_crtc(dev, c) {
2408 i = to_intel_crtc(c);
2409
2410 if (c == &intel_crtc->base)
2411 continue;
2412
2413 if (!i->active)
2414 continue;
2415
2416 obj = intel_fb_obj(c->primary->fb);
2417 if (obj == NULL)
2418 continue;
2419
2420 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2421 if (obj->tiling_mode != I915_TILING_NONE)
2422 dev_priv->preserve_bios_swizzle = true;
2423
2424 drm_framebuffer_reference(c->primary->fb);
2425 intel_crtc->base.primary->fb = c->primary->fb;
2426 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2427 break;
2428 }
2429 }
2430 }
2431
2432 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2433 struct drm_framebuffer *fb,
2434 int x, int y)
2435 {
2436 struct drm_device *dev = crtc->dev;
2437 struct drm_i915_private *dev_priv = dev->dev_private;
2438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2439 struct drm_i915_gem_object *obj;
2440 int plane = intel_crtc->plane;
2441 unsigned long linear_offset;
2442 u32 dspcntr;
2443 u32 reg = DSPCNTR(plane);
2444 int pixel_size;
2445
2446 if (!intel_crtc->primary_enabled) {
2447 I915_WRITE(reg, 0);
2448 if (INTEL_INFO(dev)->gen >= 4)
2449 I915_WRITE(DSPSURF(plane), 0);
2450 else
2451 I915_WRITE(DSPADDR(plane), 0);
2452 POSTING_READ(reg);
2453 return;
2454 }
2455
2456 obj = intel_fb_obj(fb);
2457 if (WARN_ON(obj == NULL))
2458 return;
2459
2460 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2461
2462 dspcntr = DISPPLANE_GAMMA_ENABLE;
2463
2464 dspcntr |= DISPLAY_PLANE_ENABLE;
2465
2466 if (INTEL_INFO(dev)->gen < 4) {
2467 if (intel_crtc->pipe == PIPE_B)
2468 dspcntr |= DISPPLANE_SEL_PIPE_B;
2469
2470 /* pipesrc and dspsize control the size that is scaled from,
2471 * which should always be the user's requested size.
2472 */
2473 I915_WRITE(DSPSIZE(plane),
2474 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2475 (intel_crtc->config->pipe_src_w - 1));
2476 I915_WRITE(DSPPOS(plane), 0);
2477 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2478 I915_WRITE(PRIMSIZE(plane),
2479 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2480 (intel_crtc->config->pipe_src_w - 1));
2481 I915_WRITE(PRIMPOS(plane), 0);
2482 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2483 }
2484
2485 switch (fb->pixel_format) {
2486 case DRM_FORMAT_C8:
2487 dspcntr |= DISPPLANE_8BPP;
2488 break;
2489 case DRM_FORMAT_XRGB1555:
2490 case DRM_FORMAT_ARGB1555:
2491 dspcntr |= DISPPLANE_BGRX555;
2492 break;
2493 case DRM_FORMAT_RGB565:
2494 dspcntr |= DISPPLANE_BGRX565;
2495 break;
2496 case DRM_FORMAT_XRGB8888:
2497 case DRM_FORMAT_ARGB8888:
2498 dspcntr |= DISPPLANE_BGRX888;
2499 break;
2500 case DRM_FORMAT_XBGR8888:
2501 case DRM_FORMAT_ABGR8888:
2502 dspcntr |= DISPPLANE_RGBX888;
2503 break;
2504 case DRM_FORMAT_XRGB2101010:
2505 case DRM_FORMAT_ARGB2101010:
2506 dspcntr |= DISPPLANE_BGRX101010;
2507 break;
2508 case DRM_FORMAT_XBGR2101010:
2509 case DRM_FORMAT_ABGR2101010:
2510 dspcntr |= DISPPLANE_RGBX101010;
2511 break;
2512 default:
2513 BUG();
2514 }
2515
2516 if (INTEL_INFO(dev)->gen >= 4 &&
2517 obj->tiling_mode != I915_TILING_NONE)
2518 dspcntr |= DISPPLANE_TILED;
2519
2520 if (IS_G4X(dev))
2521 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2522
2523 linear_offset = y * fb->pitches[0] + x * pixel_size;
2524
2525 if (INTEL_INFO(dev)->gen >= 4) {
2526 intel_crtc->dspaddr_offset =
2527 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2528 pixel_size,
2529 fb->pitches[0]);
2530 linear_offset -= intel_crtc->dspaddr_offset;
2531 } else {
2532 intel_crtc->dspaddr_offset = linear_offset;
2533 }
2534
2535 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2536 dspcntr |= DISPPLANE_ROTATE_180;
2537
2538 x += (intel_crtc->config->pipe_src_w - 1);
2539 y += (intel_crtc->config->pipe_src_h - 1);
2540
2541 /* Finding the last pixel of the last line of the display
2542 data and adding to linear_offset*/
2543 linear_offset +=
2544 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2545 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2546 }
2547
2548 I915_WRITE(reg, dspcntr);
2549
2550 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2551 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2552 fb->pitches[0]);
2553 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2554 if (INTEL_INFO(dev)->gen >= 4) {
2555 I915_WRITE(DSPSURF(plane),
2556 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2558 I915_WRITE(DSPLINOFF(plane), linear_offset);
2559 } else
2560 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2561 POSTING_READ(reg);
2562 }
2563
2564 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2565 struct drm_framebuffer *fb,
2566 int x, int y)
2567 {
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2571 struct drm_i915_gem_object *obj;
2572 int plane = intel_crtc->plane;
2573 unsigned long linear_offset;
2574 u32 dspcntr;
2575 u32 reg = DSPCNTR(plane);
2576 int pixel_size;
2577
2578 if (!intel_crtc->primary_enabled) {
2579 I915_WRITE(reg, 0);
2580 I915_WRITE(DSPSURF(plane), 0);
2581 POSTING_READ(reg);
2582 return;
2583 }
2584
2585 obj = intel_fb_obj(fb);
2586 if (WARN_ON(obj == NULL))
2587 return;
2588
2589 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2590
2591 dspcntr = DISPPLANE_GAMMA_ENABLE;
2592
2593 dspcntr |= DISPLAY_PLANE_ENABLE;
2594
2595 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2596 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2597
2598 switch (fb->pixel_format) {
2599 case DRM_FORMAT_C8:
2600 dspcntr |= DISPPLANE_8BPP;
2601 break;
2602 case DRM_FORMAT_RGB565:
2603 dspcntr |= DISPPLANE_BGRX565;
2604 break;
2605 case DRM_FORMAT_XRGB8888:
2606 case DRM_FORMAT_ARGB8888:
2607 dspcntr |= DISPPLANE_BGRX888;
2608 break;
2609 case DRM_FORMAT_XBGR8888:
2610 case DRM_FORMAT_ABGR8888:
2611 dspcntr |= DISPPLANE_RGBX888;
2612 break;
2613 case DRM_FORMAT_XRGB2101010:
2614 case DRM_FORMAT_ARGB2101010:
2615 dspcntr |= DISPPLANE_BGRX101010;
2616 break;
2617 case DRM_FORMAT_XBGR2101010:
2618 case DRM_FORMAT_ABGR2101010:
2619 dspcntr |= DISPPLANE_RGBX101010;
2620 break;
2621 default:
2622 BUG();
2623 }
2624
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dspcntr |= DISPPLANE_TILED;
2627
2628 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2629 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2630
2631 linear_offset = y * fb->pitches[0] + x * pixel_size;
2632 intel_crtc->dspaddr_offset =
2633 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2634 pixel_size,
2635 fb->pitches[0]);
2636 linear_offset -= intel_crtc->dspaddr_offset;
2637 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2638 dspcntr |= DISPPLANE_ROTATE_180;
2639
2640 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2641 x += (intel_crtc->config->pipe_src_w - 1);
2642 y += (intel_crtc->config->pipe_src_h - 1);
2643
2644 /* Finding the last pixel of the last line of the display
2645 data and adding to linear_offset*/
2646 linear_offset +=
2647 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2648 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2649 }
2650 }
2651
2652 I915_WRITE(reg, dspcntr);
2653
2654 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2655 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2656 fb->pitches[0]);
2657 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2658 I915_WRITE(DSPSURF(plane),
2659 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2660 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2661 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2662 } else {
2663 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2664 I915_WRITE(DSPLINOFF(plane), linear_offset);
2665 }
2666 POSTING_READ(reg);
2667 }
2668
2669 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2670 struct drm_framebuffer *fb,
2671 int x, int y)
2672 {
2673 struct drm_device *dev = crtc->dev;
2674 struct drm_i915_private *dev_priv = dev->dev_private;
2675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2676 struct intel_framebuffer *intel_fb;
2677 struct drm_i915_gem_object *obj;
2678 int pipe = intel_crtc->pipe;
2679 u32 plane_ctl, stride;
2680
2681 if (!intel_crtc->primary_enabled) {
2682 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2683 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2684 POSTING_READ(PLANE_CTL(pipe, 0));
2685 return;
2686 }
2687
2688 plane_ctl = PLANE_CTL_ENABLE |
2689 PLANE_CTL_PIPE_GAMMA_ENABLE |
2690 PLANE_CTL_PIPE_CSC_ENABLE;
2691
2692 switch (fb->pixel_format) {
2693 case DRM_FORMAT_RGB565:
2694 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2695 break;
2696 case DRM_FORMAT_XRGB8888:
2697 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2698 break;
2699 case DRM_FORMAT_XBGR8888:
2700 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2702 break;
2703 case DRM_FORMAT_XRGB2101010:
2704 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2705 break;
2706 case DRM_FORMAT_XBGR2101010:
2707 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2708 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2709 break;
2710 default:
2711 BUG();
2712 }
2713
2714 intel_fb = to_intel_framebuffer(fb);
2715 obj = intel_fb->obj;
2716
2717 /*
2718 * The stride is either expressed as a multiple of 64 bytes chunks for
2719 * linear buffers or in number of tiles for tiled buffers.
2720 */
2721 switch (obj->tiling_mode) {
2722 case I915_TILING_NONE:
2723 stride = fb->pitches[0] >> 6;
2724 break;
2725 case I915_TILING_X:
2726 plane_ctl |= PLANE_CTL_TILED_X;
2727 stride = fb->pitches[0] >> 9;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2734 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2735 plane_ctl |= PLANE_CTL_ROTATE_180;
2736
2737 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2738
2739 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2740 i915_gem_obj_ggtt_offset(obj),
2741 x, y, fb->width, fb->height,
2742 fb->pitches[0]);
2743
2744 I915_WRITE(PLANE_POS(pipe, 0), 0);
2745 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2746 I915_WRITE(PLANE_SIZE(pipe, 0),
2747 (intel_crtc->config->pipe_src_h - 1) << 16 |
2748 (intel_crtc->config->pipe_src_w - 1));
2749 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2750 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2751
2752 POSTING_READ(PLANE_SURF(pipe, 0));
2753 }
2754
2755 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2756 static int
2757 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2758 int x, int y, enum mode_set_atomic state)
2759 {
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762
2763 if (dev_priv->display.disable_fbc)
2764 dev_priv->display.disable_fbc(dev);
2765
2766 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2767
2768 return 0;
2769 }
2770
2771 static void intel_complete_page_flips(struct drm_device *dev)
2772 {
2773 struct drm_crtc *crtc;
2774
2775 for_each_crtc(dev, crtc) {
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 enum plane plane = intel_crtc->plane;
2778
2779 intel_prepare_page_flip(dev, plane);
2780 intel_finish_page_flip_plane(dev, plane);
2781 }
2782 }
2783
2784 static void intel_update_primary_planes(struct drm_device *dev)
2785 {
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct drm_crtc *crtc;
2788
2789 for_each_crtc(dev, crtc) {
2790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2791
2792 drm_modeset_lock(&crtc->mutex, NULL);
2793 /*
2794 * FIXME: Once we have proper support for primary planes (and
2795 * disabling them without disabling the entire crtc) allow again
2796 * a NULL crtc->primary->fb.
2797 */
2798 if (intel_crtc->active && crtc->primary->fb)
2799 dev_priv->display.update_primary_plane(crtc,
2800 crtc->primary->fb,
2801 crtc->x,
2802 crtc->y);
2803 drm_modeset_unlock(&crtc->mutex);
2804 }
2805 }
2806
2807 void intel_prepare_reset(struct drm_device *dev)
2808 {
2809 struct drm_i915_private *dev_priv = to_i915(dev);
2810 struct intel_crtc *crtc;
2811
2812 /* no reset support for gen2 */
2813 if (IS_GEN2(dev))
2814 return;
2815
2816 /* reset doesn't touch the display */
2817 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2818 return;
2819
2820 drm_modeset_lock_all(dev);
2821
2822 /*
2823 * Disabling the crtcs gracefully seems nicer. Also the
2824 * g33 docs say we should at least disable all the planes.
2825 */
2826 for_each_intel_crtc(dev, crtc) {
2827 if (crtc->active)
2828 dev_priv->display.crtc_disable(&crtc->base);
2829 }
2830 }
2831
2832 void intel_finish_reset(struct drm_device *dev)
2833 {
2834 struct drm_i915_private *dev_priv = to_i915(dev);
2835
2836 /*
2837 * Flips in the rings will be nuked by the reset,
2838 * so complete all pending flips so that user space
2839 * will get its events and not get stuck.
2840 */
2841 intel_complete_page_flips(dev);
2842
2843 /* no reset support for gen2 */
2844 if (IS_GEN2(dev))
2845 return;
2846
2847 /* reset doesn't touch the display */
2848 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2849 /*
2850 * Flips in the rings have been nuked by the reset,
2851 * so update the base address of all primary
2852 * planes to the the last fb to make sure we're
2853 * showing the correct fb after a reset.
2854 */
2855 intel_update_primary_planes(dev);
2856 return;
2857 }
2858
2859 /*
2860 * The display has been reset as well,
2861 * so need a full re-initialization.
2862 */
2863 intel_runtime_pm_disable_interrupts(dev_priv);
2864 intel_runtime_pm_enable_interrupts(dev_priv);
2865
2866 intel_modeset_init_hw(dev);
2867
2868 spin_lock_irq(&dev_priv->irq_lock);
2869 if (dev_priv->display.hpd_irq_setup)
2870 dev_priv->display.hpd_irq_setup(dev);
2871 spin_unlock_irq(&dev_priv->irq_lock);
2872
2873 intel_modeset_setup_hw_state(dev, true);
2874
2875 intel_hpd_init(dev_priv);
2876
2877 drm_modeset_unlock_all(dev);
2878 }
2879
2880 static int
2881 intel_finish_fb(struct drm_framebuffer *old_fb)
2882 {
2883 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2884 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2885 bool was_interruptible = dev_priv->mm.interruptible;
2886 int ret;
2887
2888 /* Big Hammer, we also need to ensure that any pending
2889 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2890 * current scanout is retired before unpinning the old
2891 * framebuffer.
2892 *
2893 * This should only fail upon a hung GPU, in which case we
2894 * can safely continue.
2895 */
2896 dev_priv->mm.interruptible = false;
2897 ret = i915_gem_object_finish_gpu(obj);
2898 dev_priv->mm.interruptible = was_interruptible;
2899
2900 return ret;
2901 }
2902
2903 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2904 {
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2908 bool pending;
2909
2910 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2911 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2912 return false;
2913
2914 spin_lock_irq(&dev->event_lock);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irq(&dev->event_lock);
2917
2918 return pending;
2919 }
2920
2921 static void intel_update_pipe_size(struct intel_crtc *crtc)
2922 {
2923 struct drm_device *dev = crtc->base.dev;
2924 struct drm_i915_private *dev_priv = dev->dev_private;
2925 const struct drm_display_mode *adjusted_mode;
2926
2927 if (!i915.fastboot)
2928 return;
2929
2930 /*
2931 * Update pipe size and adjust fitter if needed: the reason for this is
2932 * that in compute_mode_changes we check the native mode (not the pfit
2933 * mode) to see if we can flip rather than do a full mode set. In the
2934 * fastboot case, we'll flip, but if we don't update the pipesrc and
2935 * pfit state, we'll end up with a big fb scanned out into the wrong
2936 * sized surface.
2937 *
2938 * To fix this properly, we need to hoist the checks up into
2939 * compute_mode_changes (or above), check the actual pfit state and
2940 * whether the platform allows pfit disable with pipe active, and only
2941 * then update the pipesrc and pfit state, even on the flip path.
2942 */
2943
2944 adjusted_mode = &crtc->config->base.adjusted_mode;
2945
2946 I915_WRITE(PIPESRC(crtc->pipe),
2947 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2948 (adjusted_mode->crtc_vdisplay - 1));
2949 if (!crtc->config->pch_pfit.enabled &&
2950 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2951 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952 I915_WRITE(PF_CTL(crtc->pipe), 0);
2953 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2954 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2955 }
2956 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
2957 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 int pipe = intel_crtc->pipe;
2966 u32 reg, temp;
2967
2968 /* enable normal train */
2969 reg = FDI_TX_CTL(pipe);
2970 temp = I915_READ(reg);
2971 if (IS_IVYBRIDGE(dev)) {
2972 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974 } else {
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977 }
2978 I915_WRITE(reg, temp);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_NONE;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991 /* wait one idle pattern time */
2992 POSTING_READ(reg);
2993 udelay(1000);
2994
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev))
2997 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998 FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003 return crtc->base.enabled && crtc->active &&
3004 crtc->config->has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *pipe_B_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012 struct intel_crtc *pipe_C_crtc =
3013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014 uint32_t temp;
3015
3016 /*
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3020 */
3021 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026 temp = I915_READ(SOUTH_CHICKEN1);
3027 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1, temp);
3030 }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
3040 u32 reg, temp, tries;
3041
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv, pipe);
3044
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 for train result */
3047 reg = FDI_RX_IMR(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_RX_SYMBOL_LOCK;
3050 temp &= ~FDI_RX_BIT_LOCK;
3051 I915_WRITE(reg, temp);
3052 I915_READ(reg);
3053 udelay(150);
3054
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg);
3058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1;
3062 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064 reg = FDI_RX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_1;
3068 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070 POSTING_READ(reg);
3071 udelay(150);
3072
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076 FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078 reg = FDI_RX_IIR(pipe);
3079 for (tries = 0; tries < 5; tries++) {
3080 temp = I915_READ(reg);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083 if ((temp & FDI_RX_BIT_LOCK)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086 break;
3087 }
3088 }
3089 if (tries == 5)
3090 DRM_ERROR("FDI train 1 fail!\n");
3091
3092 /* Train 2 */
3093 reg = FDI_TX_CTL(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_2;
3097 I915_WRITE(reg, temp);
3098
3099 reg = FDI_RX_CTL(pipe);
3100 temp = I915_READ(reg);
3101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
3103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
3106 udelay(150);
3107
3108 reg = FDI_RX_IIR(pipe);
3109 for (tries = 0; tries < 5; tries++) {
3110 temp = I915_READ(reg);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113 if (temp & FDI_RX_SYMBOL_LOCK) {
3114 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 break;
3117 }
3118 }
3119 if (tries == 5)
3120 DRM_ERROR("FDI train 2 fail!\n");
3121
3122 DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
3140 u32 reg, temp, i, retry;
3141
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 for train result */
3144 reg = FDI_RX_IMR(pipe);
3145 temp = I915_READ(reg);
3146 temp &= ~FDI_RX_SYMBOL_LOCK;
3147 temp &= ~FDI_RX_BIT_LOCK;
3148 I915_WRITE(reg, temp);
3149
3150 POSTING_READ(reg);
3151 udelay(150);
3152
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3158 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 /* SNB-B */
3162 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165 I915_WRITE(FDI_RX_MISC(pipe),
3166 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 if (HAS_PCH_CPT(dev)) {
3171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 } else {
3174 temp &= ~FDI_LINK_TRAIN_NONE;
3175 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 }
3177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179 POSTING_READ(reg);
3180 udelay(150);
3181
3182 for (i = 0; i < 4; i++) {
3183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[i];
3187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
3190 udelay(500);
3191
3192 for (retry = 0; retry < 5; retry++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196 if (temp & FDI_RX_BIT_LOCK) {
3197 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199 break;
3200 }
3201 udelay(50);
3202 }
3203 if (retry < 5)
3204 break;
3205 }
3206 if (i == 4)
3207 DRM_ERROR("FDI train 1 fail!\n");
3208
3209 /* Train 2 */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 if (IS_GEN6(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 }
3219 I915_WRITE(reg, temp);
3220
3221 reg = FDI_RX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 if (HAS_PCH_CPT(dev)) {
3224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 } else {
3227 temp &= ~FDI_LINK_TRAIN_NONE;
3228 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 }
3230 I915_WRITE(reg, temp);
3231
3232 POSTING_READ(reg);
3233 udelay(150);
3234
3235 for (i = 0; i < 4; i++) {
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239 temp |= snb_b_fdi_train_param[i];
3240 I915_WRITE(reg, temp);
3241
3242 POSTING_READ(reg);
3243 udelay(500);
3244
3245 for (retry = 0; retry < 5; retry++) {
3246 reg = FDI_RX_IIR(pipe);
3247 temp = I915_READ(reg);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 udelay(50);
3255 }
3256 if (retry < 5)
3257 break;
3258 }
3259 if (i == 4)
3260 DRM_ERROR("FDI train 2 fail!\n");
3261
3262 DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 u32 reg, temp, i, j;
3273
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 for train result */
3276 reg = FDI_RX_IMR(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_RX_SYMBOL_LOCK;
3279 temp &= ~FDI_RX_BIT_LOCK;
3280 I915_WRITE(reg, temp);
3281
3282 POSTING_READ(reg);
3283 udelay(150);
3284
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe)));
3287
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290 /* disable first in case we need to retry */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294 temp &= ~FDI_TX_ENABLE;
3295 I915_WRITE(reg, temp);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_AUTO;
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp &= ~FDI_RX_ENABLE;
3302 I915_WRITE(reg, temp);
3303
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 temp |= snb_b_fdi_train_param[j/2];
3312 temp |= FDI_COMPOSITE_SYNC;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321 temp |= FDI_COMPOSITE_SYNC;
3322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(1); /* should be 0.5us */
3326
3327 for (i = 0; i < 4; i++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332 if (temp & FDI_RX_BIT_LOCK ||
3333 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336 i);
3337 break;
3338 }
3339 udelay(1); /* should be 0.5us */
3340 }
3341 if (i == 4) {
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343 continue;
3344 }
3345
3346 /* Train 2 */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
3360 udelay(2); /* should be 1.5us */
3361
3362 for (i = 0; i < 4; i++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367 if (temp & FDI_RX_SYMBOL_LOCK ||
3368 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371 i);
3372 goto train_done;
3373 }
3374 udelay(2); /* should be 1.5us */
3375 }
3376 if (i == 4)
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378 }
3379
3380 train_done:
3381 DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386 struct drm_device *dev = intel_crtc->base.dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp;
3390
3391
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400 POSTING_READ(reg);
3401 udelay(200);
3402
3403 /* Switch from Rawclk to PCDclk */
3404 temp = I915_READ(reg);
3405 I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407 POSTING_READ(reg);
3408 udelay(200);
3409
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416 POSTING_READ(reg);
3417 udelay(100);
3418 }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423 struct drm_device *dev = intel_crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp;
3427
3428 /* Switch from PCDclk to Rawclk */
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433 /* Disable CPU FDI TX PLL */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438 POSTING_READ(reg);
3439 udelay(100);
3440
3441 reg = FDI_RX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445 /* Wait for the clocks to turn off. */
3446 POSTING_READ(reg);
3447 udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456 u32 reg, temp;
3457
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462 POSTING_READ(reg);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~(0x7 << 16);
3467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477 /* still set train pattern 1 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 if (HAS_PCH_CPT(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 } else {
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 }
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp &= ~(0x07 << 16);
3495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496 I915_WRITE(reg, temp);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504 struct intel_crtc *crtc;
3505
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3512 */
3513 for_each_intel_crtc(dev, crtc) {
3514 if (atomic_read(&crtc->unpin_work_count) == 0)
3515 continue;
3516
3517 if (crtc->unpin_work)
3518 intel_wait_for_vblank(dev, crtc->pipe);
3519
3520 return true;
3521 }
3522
3523 return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3532 smp_rmb();
3533 intel_crtc->unpin_work = NULL;
3534
3535 if (work->event)
3536 drm_send_vblank_event(intel_crtc->base.dev,
3537 intel_crtc->pipe,
3538 work->event);
3539
3540 drm_crtc_vblank_put(&intel_crtc->base);
3541
3542 wake_up_all(&dev_priv->pending_flip_queue);
3543 queue_work(dev_priv->wq, &work->work);
3544
3545 trace_i915_flip_complete(intel_crtc->plane,
3546 work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556 !intel_crtc_has_pending_flip(crtc),
3557 60*HZ) == 0)) {
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560 spin_lock_irq(&dev->event_lock);
3561 if (intel_crtc->unpin_work) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc);
3564 }
3565 spin_unlock_irq(&dev->event_lock);
3566 }
3567
3568 if (crtc->primary->fb) {
3569 mutex_lock(&dev->struct_mutex);
3570 intel_finish_fb(crtc->primary->fb);
3571 mutex_unlock(&dev->struct_mutex);
3572 }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3581 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp;
3583
3584 mutex_lock(&dev_priv->dpio_lock);
3585
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3588 */
3589 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594 SBI_SSCCTL_DISABLE,
3595 SBI_ICLK);
3596
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock == 20000) {
3599 auxdiv = 1;
3600 divsel = 0x41;
3601 phaseinc = 0x20;
3602 } else {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3607 * precision.
3608 */
3609 u32 iclk_virtual_root_freq = 172800 * 1000;
3610 u32 iclk_pi_range = 64;
3611 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613 desired_divisor = (iclk_virtual_root_freq / clock);
3614 msb_divisor_value = desired_divisor / iclk_pi_range;
3615 pi_value = desired_divisor % iclk_pi_range;
3616
3617 auxdiv = 0;
3618 divsel = msb_divisor_value - 2;
3619 phaseinc = pi_value;
3620 }
3621
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629 clock,
3630 auxdiv,
3631 divsel,
3632 phasedir,
3633 phaseinc);
3634
3635 /* Program SSCDIVINTPHASE6 */
3636 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645 /* Program SSCAUXDIV */
3646 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651 /* Enable modulator and associated divider */
3652 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653 temp &= ~SBI_SSCCTL_DISABLE;
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656 /* Wait for initialization time */
3657 udelay(24);
3658
3659 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661 mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665 enum pipe pch_transcoder)
3666 {
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3670
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674 I915_READ(HBLANK(cpu_transcoder)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676 I915_READ(HSYNC(cpu_transcoder)));
3677
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679 I915_READ(VTOTAL(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681 I915_READ(VBLANK(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683 I915_READ(VSYNC(cpu_transcoder)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 uint32_t temp;
3692
3693 temp = I915_READ(SOUTH_CHICKEN1);
3694 if (temp & FDI_BC_BIFURCATION_SELECT)
3695 return;
3696
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700 temp |= FDI_BC_BIFURCATION_SELECT;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1, temp);
3703 POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708 struct drm_device *dev = intel_crtc->base.dev;
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 switch (intel_crtc->pipe) {
3712 case PIPE_A:
3713 break;
3714 case PIPE_B:
3715 if (intel_crtc->config->fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else
3718 cpt_enable_fdi_bc_bifurcation(dev);
3719
3720 break;
3721 case PIPE_C:
3722 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724 break;
3725 default:
3726 BUG();
3727 }
3728 }
3729
3730 /*
3731 * Enable PCH resources required for PCH ports:
3732 * - PCH PLLs
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3736 * - transcoder
3737 */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748 if (IS_IVYBRIDGE(dev))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756 /* For PCH output, training FDI link */
3757 dev_priv->display.fdi_link_train(crtc);
3758
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev)) {
3762 u32 sel;
3763
3764 temp = I915_READ(PCH_DPLL_SEL);
3765 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe);
3767 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3768 temp |= sel;
3769 else
3770 temp &= ~sel;
3771 I915_WRITE(PCH_DPLL_SEL, temp);
3772 }
3773
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3777 *
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc);
3782
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv, pipe);
3785 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787 intel_fdi_normal_train(crtc);
3788
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795 TRANS_DP_SYNC_MASK |
3796 TRANS_DP_BPC_MASK);
3797 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798 TRANS_DP_ENH_FRAMING);
3799 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806 switch (intel_trans_dp_port_sel(crtc)) {
3807 case PCH_DP_B:
3808 temp |= TRANS_DP_PORT_SEL_B;
3809 break;
3810 case PCH_DP_C:
3811 temp |= TRANS_DP_PORT_SEL_C;
3812 break;
3813 case PCH_DP_D:
3814 temp |= TRANS_DP_PORT_SEL_D;
3815 break;
3816 default:
3817 BUG();
3818 }
3819
3820 I915_WRITE(reg, temp);
3821 }
3822
3823 ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3832
3833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835 lpt_program_iclkip(crtc);
3836
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847 if (pll == NULL)
3848 return;
3849
3850 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851 WARN(1, "bad %s crtc mask\n", pll->name);
3852 return;
3853 }
3854
3855 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856 if (pll->config.crtc_mask == 0) {
3857 WARN_ON(pll->on);
3858 WARN_ON(pll->active);
3859 }
3860
3861 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3865 struct intel_crtc_state *crtc_state)
3866 {
3867 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3868 struct intel_shared_dpll *pll;
3869 enum intel_dpll_id i;
3870
3871 if (HAS_PCH_IBX(dev_priv->dev)) {
3872 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3873 i = (enum intel_dpll_id) crtc->pipe;
3874 pll = &dev_priv->shared_dplls[i];
3875
3876 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3877 crtc->base.base.id, pll->name);
3878
3879 WARN_ON(pll->new_config->crtc_mask);
3880
3881 goto found;
3882 }
3883
3884 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3885 pll = &dev_priv->shared_dplls[i];
3886
3887 /* Only want to check enabled timings first */
3888 if (pll->new_config->crtc_mask == 0)
3889 continue;
3890
3891 if (memcmp(&crtc_state->dpll_hw_state,
3892 &pll->new_config->hw_state,
3893 sizeof(pll->new_config->hw_state)) == 0) {
3894 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3895 crtc->base.base.id, pll->name,
3896 pll->new_config->crtc_mask,
3897 pll->active);
3898 goto found;
3899 }
3900 }
3901
3902 /* Ok no matching timings, maybe there's a free one? */
3903 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3904 pll = &dev_priv->shared_dplls[i];
3905 if (pll->new_config->crtc_mask == 0) {
3906 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3907 crtc->base.base.id, pll->name);
3908 goto found;
3909 }
3910 }
3911
3912 return NULL;
3913
3914 found:
3915 if (pll->new_config->crtc_mask == 0)
3916 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3917
3918 crtc_state->shared_dpll = i;
3919 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3920 pipe_name(crtc->pipe));
3921
3922 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3923
3924 return pll;
3925 }
3926
3927 /**
3928 * intel_shared_dpll_start_config - start a new PLL staged config
3929 * @dev_priv: DRM device
3930 * @clear_pipes: mask of pipes that will have their PLLs freed
3931 *
3932 * Starts a new PLL staged config, copying the current config but
3933 * releasing the references of pipes specified in clear_pipes.
3934 */
3935 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3936 unsigned clear_pipes)
3937 {
3938 struct intel_shared_dpll *pll;
3939 enum intel_dpll_id i;
3940
3941 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3942 pll = &dev_priv->shared_dplls[i];
3943
3944 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3945 GFP_KERNEL);
3946 if (!pll->new_config)
3947 goto cleanup;
3948
3949 pll->new_config->crtc_mask &= ~clear_pipes;
3950 }
3951
3952 return 0;
3953
3954 cleanup:
3955 while (--i >= 0) {
3956 pll = &dev_priv->shared_dplls[i];
3957 kfree(pll->new_config);
3958 pll->new_config = NULL;
3959 }
3960
3961 return -ENOMEM;
3962 }
3963
3964 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3965 {
3966 struct intel_shared_dpll *pll;
3967 enum intel_dpll_id i;
3968
3969 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3970 pll = &dev_priv->shared_dplls[i];
3971
3972 WARN_ON(pll->new_config == &pll->config);
3973
3974 pll->config = *pll->new_config;
3975 kfree(pll->new_config);
3976 pll->new_config = NULL;
3977 }
3978 }
3979
3980 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3981 {
3982 struct intel_shared_dpll *pll;
3983 enum intel_dpll_id i;
3984
3985 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3986 pll = &dev_priv->shared_dplls[i];
3987
3988 WARN_ON(pll->new_config == &pll->config);
3989
3990 kfree(pll->new_config);
3991 pll->new_config = NULL;
3992 }
3993 }
3994
3995 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3996 {
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 int dslreg = PIPEDSL(pipe);
3999 u32 temp;
4000
4001 temp = I915_READ(dslreg);
4002 udelay(500);
4003 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4004 if (wait_for(I915_READ(dslreg) != temp, 5))
4005 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4006 }
4007 }
4008
4009 static void skylake_pfit_enable(struct intel_crtc *crtc)
4010 {
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 int pipe = crtc->pipe;
4014
4015 if (crtc->config->pch_pfit.enabled) {
4016 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4017 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4018 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4019 }
4020 }
4021
4022 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4023 {
4024 struct drm_device *dev = crtc->base.dev;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 int pipe = crtc->pipe;
4027
4028 if (crtc->config->pch_pfit.enabled) {
4029 /* Force use of hard-coded filter coefficients
4030 * as some pre-programmed values are broken,
4031 * e.g. x201.
4032 */
4033 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4034 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4035 PF_PIPE_SEL_IVB(pipe));
4036 else
4037 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4038 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4039 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4040 }
4041 }
4042
4043 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4044 {
4045 struct drm_device *dev = crtc->dev;
4046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4047 struct drm_plane *plane;
4048 struct intel_plane *intel_plane;
4049
4050 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4051 intel_plane = to_intel_plane(plane);
4052 if (intel_plane->pipe == pipe)
4053 intel_plane_restore(&intel_plane->base);
4054 }
4055 }
4056
4057 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4058 {
4059 struct drm_device *dev = crtc->dev;
4060 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4061 struct drm_plane *plane;
4062 struct intel_plane *intel_plane;
4063
4064 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4065 intel_plane = to_intel_plane(plane);
4066 if (intel_plane->pipe == pipe)
4067 plane->funcs->disable_plane(plane);
4068 }
4069 }
4070
4071 void hsw_enable_ips(struct intel_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->base.dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075
4076 if (!crtc->config->ips_enabled)
4077 return;
4078
4079 /* We can only enable IPS after we enable a plane and wait for a vblank */
4080 intel_wait_for_vblank(dev, crtc->pipe);
4081
4082 assert_plane_enabled(dev_priv, crtc->plane);
4083 if (IS_BROADWELL(dev)) {
4084 mutex_lock(&dev_priv->rps.hw_lock);
4085 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4086 mutex_unlock(&dev_priv->rps.hw_lock);
4087 /* Quoting Art Runyan: "its not safe to expect any particular
4088 * value in IPS_CTL bit 31 after enabling IPS through the
4089 * mailbox." Moreover, the mailbox may return a bogus state,
4090 * so we need to just enable it and continue on.
4091 */
4092 } else {
4093 I915_WRITE(IPS_CTL, IPS_ENABLE);
4094 /* The bit only becomes 1 in the next vblank, so this wait here
4095 * is essentially intel_wait_for_vblank. If we don't have this
4096 * and don't wait for vblanks until the end of crtc_enable, then
4097 * the HW state readout code will complain that the expected
4098 * IPS_CTL value is not the one we read. */
4099 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4100 DRM_ERROR("Timed out waiting for IPS enable\n");
4101 }
4102 }
4103
4104 void hsw_disable_ips(struct intel_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->base.dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108
4109 if (!crtc->config->ips_enabled)
4110 return;
4111
4112 assert_plane_enabled(dev_priv, crtc->plane);
4113 if (IS_BROADWELL(dev)) {
4114 mutex_lock(&dev_priv->rps.hw_lock);
4115 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4116 mutex_unlock(&dev_priv->rps.hw_lock);
4117 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4118 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4119 DRM_ERROR("Timed out waiting for IPS disable\n");
4120 } else {
4121 I915_WRITE(IPS_CTL, 0);
4122 POSTING_READ(IPS_CTL);
4123 }
4124
4125 /* We need to wait for a vblank before we can disable the plane. */
4126 intel_wait_for_vblank(dev, crtc->pipe);
4127 }
4128
4129 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4130 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4131 {
4132 struct drm_device *dev = crtc->dev;
4133 struct drm_i915_private *dev_priv = dev->dev_private;
4134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135 enum pipe pipe = intel_crtc->pipe;
4136 int palreg = PALETTE(pipe);
4137 int i;
4138 bool reenable_ips = false;
4139
4140 /* The clocks have to be on to load the palette. */
4141 if (!crtc->enabled || !intel_crtc->active)
4142 return;
4143
4144 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4145 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4146 assert_dsi_pll_enabled(dev_priv);
4147 else
4148 assert_pll_enabled(dev_priv, pipe);
4149 }
4150
4151 /* use legacy palette for Ironlake */
4152 if (!HAS_GMCH_DISPLAY(dev))
4153 palreg = LGC_PALETTE(pipe);
4154
4155 /* Workaround : Do not read or write the pipe palette/gamma data while
4156 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4157 */
4158 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4159 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4160 GAMMA_MODE_MODE_SPLIT)) {
4161 hsw_disable_ips(intel_crtc);
4162 reenable_ips = true;
4163 }
4164
4165 for (i = 0; i < 256; i++) {
4166 I915_WRITE(palreg + 4 * i,
4167 (intel_crtc->lut_r[i] << 16) |
4168 (intel_crtc->lut_g[i] << 8) |
4169 intel_crtc->lut_b[i]);
4170 }
4171
4172 if (reenable_ips)
4173 hsw_enable_ips(intel_crtc);
4174 }
4175
4176 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4177 {
4178 if (!enable && intel_crtc->overlay) {
4179 struct drm_device *dev = intel_crtc->base.dev;
4180 struct drm_i915_private *dev_priv = dev->dev_private;
4181
4182 mutex_lock(&dev->struct_mutex);
4183 dev_priv->mm.interruptible = false;
4184 (void) intel_overlay_switch_off(intel_crtc->overlay);
4185 dev_priv->mm.interruptible = true;
4186 mutex_unlock(&dev->struct_mutex);
4187 }
4188
4189 /* Let userspace switch the overlay on again. In most cases userspace
4190 * has to recompute where to put it anyway.
4191 */
4192 }
4193
4194 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4198 int pipe = intel_crtc->pipe;
4199
4200 intel_enable_primary_hw_plane(crtc->primary, crtc);
4201 intel_enable_sprite_planes(crtc);
4202 intel_crtc_update_cursor(crtc, true);
4203 intel_crtc_dpms_overlay(intel_crtc, true);
4204
4205 hsw_enable_ips(intel_crtc);
4206
4207 mutex_lock(&dev->struct_mutex);
4208 intel_fbc_update(dev);
4209 mutex_unlock(&dev->struct_mutex);
4210
4211 /*
4212 * FIXME: Once we grow proper nuclear flip support out of this we need
4213 * to compute the mask of flip planes precisely. For the time being
4214 * consider this a flip from a NULL plane.
4215 */
4216 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4217 }
4218
4219 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4220 {
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224 int pipe = intel_crtc->pipe;
4225 int plane = intel_crtc->plane;
4226
4227 intel_crtc_wait_for_pending_flips(crtc);
4228
4229 if (dev_priv->fbc.plane == plane)
4230 intel_fbc_disable(dev);
4231
4232 hsw_disable_ips(intel_crtc);
4233
4234 intel_crtc_dpms_overlay(intel_crtc, false);
4235 intel_crtc_update_cursor(crtc, false);
4236 intel_disable_sprite_planes(crtc);
4237 intel_disable_primary_hw_plane(crtc->primary, crtc);
4238
4239 /*
4240 * FIXME: Once we grow proper nuclear flip support out of this we need
4241 * to compute the mask of flip planes precisely. For the time being
4242 * consider this a flip to a NULL plane.
4243 */
4244 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4245 }
4246
4247 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4248 {
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 struct intel_encoder *encoder;
4253 int pipe = intel_crtc->pipe;
4254
4255 WARN_ON(!crtc->enabled);
4256
4257 if (intel_crtc->active)
4258 return;
4259
4260 if (intel_crtc->config->has_pch_encoder)
4261 intel_prepare_shared_dpll(intel_crtc);
4262
4263 if (intel_crtc->config->has_dp_encoder)
4264 intel_dp_set_m_n(intel_crtc);
4265
4266 intel_set_pipe_timings(intel_crtc);
4267
4268 if (intel_crtc->config->has_pch_encoder) {
4269 intel_cpu_transcoder_set_m_n(intel_crtc,
4270 &intel_crtc->config->fdi_m_n, NULL);
4271 }
4272
4273 ironlake_set_pipeconf(crtc);
4274
4275 intel_crtc->active = true;
4276
4277 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4278 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4279
4280 for_each_encoder_on_crtc(dev, crtc, encoder)
4281 if (encoder->pre_enable)
4282 encoder->pre_enable(encoder);
4283
4284 if (intel_crtc->config->has_pch_encoder) {
4285 /* Note: FDI PLL enabling _must_ be done before we enable the
4286 * cpu pipes, hence this is separate from all the other fdi/pch
4287 * enabling. */
4288 ironlake_fdi_pll_enable(intel_crtc);
4289 } else {
4290 assert_fdi_tx_disabled(dev_priv, pipe);
4291 assert_fdi_rx_disabled(dev_priv, pipe);
4292 }
4293
4294 ironlake_pfit_enable(intel_crtc);
4295
4296 /*
4297 * On ILK+ LUT must be loaded before the pipe is running but with
4298 * clocks enabled
4299 */
4300 intel_crtc_load_lut(crtc);
4301
4302 intel_update_watermarks(crtc);
4303 intel_enable_pipe(intel_crtc);
4304
4305 if (intel_crtc->config->has_pch_encoder)
4306 ironlake_pch_enable(crtc);
4307
4308 assert_vblank_disabled(crtc);
4309 drm_crtc_vblank_on(crtc);
4310
4311 for_each_encoder_on_crtc(dev, crtc, encoder)
4312 encoder->enable(encoder);
4313
4314 if (HAS_PCH_CPT(dev))
4315 cpt_verify_modeset(dev, intel_crtc->pipe);
4316
4317 intel_crtc_enable_planes(crtc);
4318 }
4319
4320 /* IPS only exists on ULT machines and is tied to pipe A. */
4321 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4322 {
4323 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4324 }
4325
4326 /*
4327 * This implements the workaround described in the "notes" section of the mode
4328 * set sequence documentation. When going from no pipes or single pipe to
4329 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4330 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4331 */
4332 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4333 {
4334 struct drm_device *dev = crtc->base.dev;
4335 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4336
4337 /* We want to get the other_active_crtc only if there's only 1 other
4338 * active crtc. */
4339 for_each_intel_crtc(dev, crtc_it) {
4340 if (!crtc_it->active || crtc_it == crtc)
4341 continue;
4342
4343 if (other_active_crtc)
4344 return;
4345
4346 other_active_crtc = crtc_it;
4347 }
4348 if (!other_active_crtc)
4349 return;
4350
4351 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4352 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4353 }
4354
4355 static void haswell_crtc_enable(struct drm_crtc *crtc)
4356 {
4357 struct drm_device *dev = crtc->dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360 struct intel_encoder *encoder;
4361 int pipe = intel_crtc->pipe;
4362
4363 WARN_ON(!crtc->enabled);
4364
4365 if (intel_crtc->active)
4366 return;
4367
4368 if (intel_crtc_to_shared_dpll(intel_crtc))
4369 intel_enable_shared_dpll(intel_crtc);
4370
4371 if (intel_crtc->config->has_dp_encoder)
4372 intel_dp_set_m_n(intel_crtc);
4373
4374 intel_set_pipe_timings(intel_crtc);
4375
4376 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4377 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4378 intel_crtc->config->pixel_multiplier - 1);
4379 }
4380
4381 if (intel_crtc->config->has_pch_encoder) {
4382 intel_cpu_transcoder_set_m_n(intel_crtc,
4383 &intel_crtc->config->fdi_m_n, NULL);
4384 }
4385
4386 haswell_set_pipeconf(crtc);
4387
4388 intel_set_pipe_csc(crtc);
4389
4390 intel_crtc->active = true;
4391
4392 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4393 for_each_encoder_on_crtc(dev, crtc, encoder)
4394 if (encoder->pre_enable)
4395 encoder->pre_enable(encoder);
4396
4397 if (intel_crtc->config->has_pch_encoder) {
4398 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4399 true);
4400 dev_priv->display.fdi_link_train(crtc);
4401 }
4402
4403 intel_ddi_enable_pipe_clock(intel_crtc);
4404
4405 if (IS_SKYLAKE(dev))
4406 skylake_pfit_enable(intel_crtc);
4407 else
4408 ironlake_pfit_enable(intel_crtc);
4409
4410 /*
4411 * On ILK+ LUT must be loaded before the pipe is running but with
4412 * clocks enabled
4413 */
4414 intel_crtc_load_lut(crtc);
4415
4416 intel_ddi_set_pipe_settings(crtc);
4417 intel_ddi_enable_transcoder_func(crtc);
4418
4419 intel_update_watermarks(crtc);
4420 intel_enable_pipe(intel_crtc);
4421
4422 if (intel_crtc->config->has_pch_encoder)
4423 lpt_pch_enable(crtc);
4424
4425 if (intel_crtc->config->dp_encoder_is_mst)
4426 intel_ddi_set_vc_payload_alloc(crtc, true);
4427
4428 assert_vblank_disabled(crtc);
4429 drm_crtc_vblank_on(crtc);
4430
4431 for_each_encoder_on_crtc(dev, crtc, encoder) {
4432 encoder->enable(encoder);
4433 intel_opregion_notify_encoder(encoder, true);
4434 }
4435
4436 /* If we change the relative order between pipe/planes enabling, we need
4437 * to change the workaround. */
4438 haswell_mode_set_planes_workaround(intel_crtc);
4439 intel_crtc_enable_planes(crtc);
4440 }
4441
4442 static void skylake_pfit_disable(struct intel_crtc *crtc)
4443 {
4444 struct drm_device *dev = crtc->base.dev;
4445 struct drm_i915_private *dev_priv = dev->dev_private;
4446 int pipe = crtc->pipe;
4447
4448 /* To avoid upsetting the power well on haswell only disable the pfit if
4449 * it's in use. The hw state code will make sure we get this right. */
4450 if (crtc->config->pch_pfit.enabled) {
4451 I915_WRITE(PS_CTL(pipe), 0);
4452 I915_WRITE(PS_WIN_POS(pipe), 0);
4453 I915_WRITE(PS_WIN_SZ(pipe), 0);
4454 }
4455 }
4456
4457 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4458 {
4459 struct drm_device *dev = crtc->base.dev;
4460 struct drm_i915_private *dev_priv = dev->dev_private;
4461 int pipe = crtc->pipe;
4462
4463 /* To avoid upsetting the power well on haswell only disable the pfit if
4464 * it's in use. The hw state code will make sure we get this right. */
4465 if (crtc->config->pch_pfit.enabled) {
4466 I915_WRITE(PF_CTL(pipe), 0);
4467 I915_WRITE(PF_WIN_POS(pipe), 0);
4468 I915_WRITE(PF_WIN_SZ(pipe), 0);
4469 }
4470 }
4471
4472 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4473 {
4474 struct drm_device *dev = crtc->dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4477 struct intel_encoder *encoder;
4478 int pipe = intel_crtc->pipe;
4479 u32 reg, temp;
4480
4481 if (!intel_crtc->active)
4482 return;
4483
4484 intel_crtc_disable_planes(crtc);
4485
4486 for_each_encoder_on_crtc(dev, crtc, encoder)
4487 encoder->disable(encoder);
4488
4489 drm_crtc_vblank_off(crtc);
4490 assert_vblank_disabled(crtc);
4491
4492 if (intel_crtc->config->has_pch_encoder)
4493 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4494
4495 intel_disable_pipe(intel_crtc);
4496
4497 ironlake_pfit_disable(intel_crtc);
4498
4499 for_each_encoder_on_crtc(dev, crtc, encoder)
4500 if (encoder->post_disable)
4501 encoder->post_disable(encoder);
4502
4503 if (intel_crtc->config->has_pch_encoder) {
4504 ironlake_fdi_disable(crtc);
4505
4506 ironlake_disable_pch_transcoder(dev_priv, pipe);
4507
4508 if (HAS_PCH_CPT(dev)) {
4509 /* disable TRANS_DP_CTL */
4510 reg = TRANS_DP_CTL(pipe);
4511 temp = I915_READ(reg);
4512 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4513 TRANS_DP_PORT_SEL_MASK);
4514 temp |= TRANS_DP_PORT_SEL_NONE;
4515 I915_WRITE(reg, temp);
4516
4517 /* disable DPLL_SEL */
4518 temp = I915_READ(PCH_DPLL_SEL);
4519 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4520 I915_WRITE(PCH_DPLL_SEL, temp);
4521 }
4522
4523 /* disable PCH DPLL */
4524 intel_disable_shared_dpll(intel_crtc);
4525
4526 ironlake_fdi_pll_disable(intel_crtc);
4527 }
4528
4529 intel_crtc->active = false;
4530 intel_update_watermarks(crtc);
4531
4532 mutex_lock(&dev->struct_mutex);
4533 intel_fbc_update(dev);
4534 mutex_unlock(&dev->struct_mutex);
4535 }
4536
4537 static void haswell_crtc_disable(struct drm_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4542 struct intel_encoder *encoder;
4543 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4544
4545 if (!intel_crtc->active)
4546 return;
4547
4548 intel_crtc_disable_planes(crtc);
4549
4550 for_each_encoder_on_crtc(dev, crtc, encoder) {
4551 intel_opregion_notify_encoder(encoder, false);
4552 encoder->disable(encoder);
4553 }
4554
4555 drm_crtc_vblank_off(crtc);
4556 assert_vblank_disabled(crtc);
4557
4558 if (intel_crtc->config->has_pch_encoder)
4559 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4560 false);
4561 intel_disable_pipe(intel_crtc);
4562
4563 if (intel_crtc->config->dp_encoder_is_mst)
4564 intel_ddi_set_vc_payload_alloc(crtc, false);
4565
4566 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4567
4568 if (IS_SKYLAKE(dev))
4569 skylake_pfit_disable(intel_crtc);
4570 else
4571 ironlake_pfit_disable(intel_crtc);
4572
4573 intel_ddi_disable_pipe_clock(intel_crtc);
4574
4575 if (intel_crtc->config->has_pch_encoder) {
4576 lpt_disable_pch_transcoder(dev_priv);
4577 intel_ddi_fdi_disable(crtc);
4578 }
4579
4580 for_each_encoder_on_crtc(dev, crtc, encoder)
4581 if (encoder->post_disable)
4582 encoder->post_disable(encoder);
4583
4584 intel_crtc->active = false;
4585 intel_update_watermarks(crtc);
4586
4587 mutex_lock(&dev->struct_mutex);
4588 intel_fbc_update(dev);
4589 mutex_unlock(&dev->struct_mutex);
4590
4591 if (intel_crtc_to_shared_dpll(intel_crtc))
4592 intel_disable_shared_dpll(intel_crtc);
4593 }
4594
4595 static void ironlake_crtc_off(struct drm_crtc *crtc)
4596 {
4597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598 intel_put_shared_dpll(intel_crtc);
4599 }
4600
4601
4602 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc_state *pipe_config = crtc->config;
4607
4608 if (!pipe_config->gmch_pfit.control)
4609 return;
4610
4611 /*
4612 * The panel fitter should only be adjusted whilst the pipe is disabled,
4613 * according to register description and PRM.
4614 */
4615 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4616 assert_pipe_disabled(dev_priv, crtc->pipe);
4617
4618 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4619 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4620
4621 /* Border color in case we don't scale up to the full screen. Black by
4622 * default, change to something else for debugging. */
4623 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4624 }
4625
4626 static enum intel_display_power_domain port_to_power_domain(enum port port)
4627 {
4628 switch (port) {
4629 case PORT_A:
4630 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4631 case PORT_B:
4632 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4633 case PORT_C:
4634 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4635 case PORT_D:
4636 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4637 default:
4638 WARN_ON_ONCE(1);
4639 return POWER_DOMAIN_PORT_OTHER;
4640 }
4641 }
4642
4643 #define for_each_power_domain(domain, mask) \
4644 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4645 if ((1 << (domain)) & (mask))
4646
4647 enum intel_display_power_domain
4648 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4649 {
4650 struct drm_device *dev = intel_encoder->base.dev;
4651 struct intel_digital_port *intel_dig_port;
4652
4653 switch (intel_encoder->type) {
4654 case INTEL_OUTPUT_UNKNOWN:
4655 /* Only DDI platforms should ever use this output type */
4656 WARN_ON_ONCE(!HAS_DDI(dev));
4657 case INTEL_OUTPUT_DISPLAYPORT:
4658 case INTEL_OUTPUT_HDMI:
4659 case INTEL_OUTPUT_EDP:
4660 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4661 return port_to_power_domain(intel_dig_port->port);
4662 case INTEL_OUTPUT_DP_MST:
4663 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4664 return port_to_power_domain(intel_dig_port->port);
4665 case INTEL_OUTPUT_ANALOG:
4666 return POWER_DOMAIN_PORT_CRT;
4667 case INTEL_OUTPUT_DSI:
4668 return POWER_DOMAIN_PORT_DSI;
4669 default:
4670 return POWER_DOMAIN_PORT_OTHER;
4671 }
4672 }
4673
4674 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4675 {
4676 struct drm_device *dev = crtc->dev;
4677 struct intel_encoder *intel_encoder;
4678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4679 enum pipe pipe = intel_crtc->pipe;
4680 unsigned long mask;
4681 enum transcoder transcoder;
4682
4683 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4684
4685 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4686 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4687 if (intel_crtc->config->pch_pfit.enabled ||
4688 intel_crtc->config->pch_pfit.force_thru)
4689 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4690
4691 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4692 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4693
4694 return mask;
4695 }
4696
4697 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4698 {
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4701 struct intel_crtc *crtc;
4702
4703 /*
4704 * First get all needed power domains, then put all unneeded, to avoid
4705 * any unnecessary toggling of the power wells.
4706 */
4707 for_each_intel_crtc(dev, crtc) {
4708 enum intel_display_power_domain domain;
4709
4710 if (!crtc->base.enabled)
4711 continue;
4712
4713 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4714
4715 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4716 intel_display_power_get(dev_priv, domain);
4717 }
4718
4719 if (dev_priv->display.modeset_global_resources)
4720 dev_priv->display.modeset_global_resources(dev);
4721
4722 for_each_intel_crtc(dev, crtc) {
4723 enum intel_display_power_domain domain;
4724
4725 for_each_power_domain(domain, crtc->enabled_power_domains)
4726 intel_display_power_put(dev_priv, domain);
4727
4728 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4729 }
4730
4731 intel_display_set_init_power(dev_priv, false);
4732 }
4733
4734 /* returns HPLL frequency in kHz */
4735 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4736 {
4737 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4738
4739 /* Obtain SKU information */
4740 mutex_lock(&dev_priv->dpio_lock);
4741 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4742 CCK_FUSE_HPLL_FREQ_MASK;
4743 mutex_unlock(&dev_priv->dpio_lock);
4744
4745 return vco_freq[hpll_freq] * 1000;
4746 }
4747
4748 static void vlv_update_cdclk(struct drm_device *dev)
4749 {
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4753 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4754 dev_priv->vlv_cdclk_freq);
4755
4756 /*
4757 * Program the gmbus_freq based on the cdclk frequency.
4758 * BSpec erroneously claims we should aim for 4MHz, but
4759 * in fact 1MHz is the correct frequency.
4760 */
4761 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4762 }
4763
4764 /* Adjust CDclk dividers to allow high res or save power if possible */
4765 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4766 {
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 u32 val, cmd;
4769
4770 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4771
4772 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4773 cmd = 2;
4774 else if (cdclk == 266667)
4775 cmd = 1;
4776 else
4777 cmd = 0;
4778
4779 mutex_lock(&dev_priv->rps.hw_lock);
4780 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4781 val &= ~DSPFREQGUAR_MASK;
4782 val |= (cmd << DSPFREQGUAR_SHIFT);
4783 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4784 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4785 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4786 50)) {
4787 DRM_ERROR("timed out waiting for CDclk change\n");
4788 }
4789 mutex_unlock(&dev_priv->rps.hw_lock);
4790
4791 if (cdclk == 400000) {
4792 u32 divider;
4793
4794 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4795
4796 mutex_lock(&dev_priv->dpio_lock);
4797 /* adjust cdclk divider */
4798 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4799 val &= ~DISPLAY_FREQUENCY_VALUES;
4800 val |= divider;
4801 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4802
4803 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4804 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4805 50))
4806 DRM_ERROR("timed out waiting for CDclk change\n");
4807 mutex_unlock(&dev_priv->dpio_lock);
4808 }
4809
4810 mutex_lock(&dev_priv->dpio_lock);
4811 /* adjust self-refresh exit latency value */
4812 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4813 val &= ~0x7f;
4814
4815 /*
4816 * For high bandwidth configs, we set a higher latency in the bunit
4817 * so that the core display fetch happens in time to avoid underruns.
4818 */
4819 if (cdclk == 400000)
4820 val |= 4500 / 250; /* 4.5 usec */
4821 else
4822 val |= 3000 / 250; /* 3.0 usec */
4823 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4824 mutex_unlock(&dev_priv->dpio_lock);
4825
4826 vlv_update_cdclk(dev);
4827 }
4828
4829 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4830 {
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 u32 val, cmd;
4833
4834 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4835
4836 switch (cdclk) {
4837 case 400000:
4838 cmd = 3;
4839 break;
4840 case 333333:
4841 case 320000:
4842 cmd = 2;
4843 break;
4844 case 266667:
4845 cmd = 1;
4846 break;
4847 case 200000:
4848 cmd = 0;
4849 break;
4850 default:
4851 MISSING_CASE(cdclk);
4852 return;
4853 }
4854
4855 mutex_lock(&dev_priv->rps.hw_lock);
4856 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4857 val &= ~DSPFREQGUAR_MASK_CHV;
4858 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4859 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4860 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4861 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4862 50)) {
4863 DRM_ERROR("timed out waiting for CDclk change\n");
4864 }
4865 mutex_unlock(&dev_priv->rps.hw_lock);
4866
4867 vlv_update_cdclk(dev);
4868 }
4869
4870 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4871 int max_pixclk)
4872 {
4873 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4874
4875 /* FIXME: Punit isn't quite ready yet */
4876 if (IS_CHERRYVIEW(dev_priv->dev))
4877 return 400000;
4878
4879 /*
4880 * Really only a few cases to deal with, as only 4 CDclks are supported:
4881 * 200MHz
4882 * 267MHz
4883 * 320/333MHz (depends on HPLL freq)
4884 * 400MHz
4885 * So we check to see whether we're above 90% of the lower bin and
4886 * adjust if needed.
4887 *
4888 * We seem to get an unstable or solid color picture at 200MHz.
4889 * Not sure what's wrong. For now use 200MHz only when all pipes
4890 * are off.
4891 */
4892 if (max_pixclk > freq_320*9/10)
4893 return 400000;
4894 else if (max_pixclk > 266667*9/10)
4895 return freq_320;
4896 else if (max_pixclk > 0)
4897 return 266667;
4898 else
4899 return 200000;
4900 }
4901
4902 /* compute the max pixel clock for new configuration */
4903 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4904 {
4905 struct drm_device *dev = dev_priv->dev;
4906 struct intel_crtc *intel_crtc;
4907 int max_pixclk = 0;
4908
4909 for_each_intel_crtc(dev, intel_crtc) {
4910 if (intel_crtc->new_enabled)
4911 max_pixclk = max(max_pixclk,
4912 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4913 }
4914
4915 return max_pixclk;
4916 }
4917
4918 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4919 unsigned *prepare_pipes)
4920 {
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922 struct intel_crtc *intel_crtc;
4923 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4924
4925 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4926 dev_priv->vlv_cdclk_freq)
4927 return;
4928
4929 /* disable/enable all currently active pipes while we change cdclk */
4930 for_each_intel_crtc(dev, intel_crtc)
4931 if (intel_crtc->base.enabled)
4932 *prepare_pipes |= (1 << intel_crtc->pipe);
4933 }
4934
4935 static void valleyview_modeset_global_resources(struct drm_device *dev)
4936 {
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4939 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4940
4941 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4942 /*
4943 * FIXME: We can end up here with all power domains off, yet
4944 * with a CDCLK frequency other than the minimum. To account
4945 * for this take the PIPE-A power domain, which covers the HW
4946 * blocks needed for the following programming. This can be
4947 * removed once it's guaranteed that we get here either with
4948 * the minimum CDCLK set, or the required power domains
4949 * enabled.
4950 */
4951 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4952
4953 if (IS_CHERRYVIEW(dev))
4954 cherryview_set_cdclk(dev, req_cdclk);
4955 else
4956 valleyview_set_cdclk(dev, req_cdclk);
4957
4958 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4959 }
4960 }
4961
4962 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4963 {
4964 struct drm_device *dev = crtc->dev;
4965 struct drm_i915_private *dev_priv = to_i915(dev);
4966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4967 struct intel_encoder *encoder;
4968 int pipe = intel_crtc->pipe;
4969 bool is_dsi;
4970
4971 WARN_ON(!crtc->enabled);
4972
4973 if (intel_crtc->active)
4974 return;
4975
4976 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4977
4978 if (!is_dsi) {
4979 if (IS_CHERRYVIEW(dev))
4980 chv_prepare_pll(intel_crtc, intel_crtc->config);
4981 else
4982 vlv_prepare_pll(intel_crtc, intel_crtc->config);
4983 }
4984
4985 if (intel_crtc->config->has_dp_encoder)
4986 intel_dp_set_m_n(intel_crtc);
4987
4988 intel_set_pipe_timings(intel_crtc);
4989
4990 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992
4993 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4994 I915_WRITE(CHV_CANVAS(pipe), 0);
4995 }
4996
4997 i9xx_set_pipeconf(intel_crtc);
4998
4999 intel_crtc->active = true;
5000
5001 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5002
5003 for_each_encoder_on_crtc(dev, crtc, encoder)
5004 if (encoder->pre_pll_enable)
5005 encoder->pre_pll_enable(encoder);
5006
5007 if (!is_dsi) {
5008 if (IS_CHERRYVIEW(dev))
5009 chv_enable_pll(intel_crtc, intel_crtc->config);
5010 else
5011 vlv_enable_pll(intel_crtc, intel_crtc->config);
5012 }
5013
5014 for_each_encoder_on_crtc(dev, crtc, encoder)
5015 if (encoder->pre_enable)
5016 encoder->pre_enable(encoder);
5017
5018 i9xx_pfit_enable(intel_crtc);
5019
5020 intel_crtc_load_lut(crtc);
5021
5022 intel_update_watermarks(crtc);
5023 intel_enable_pipe(intel_crtc);
5024
5025 assert_vblank_disabled(crtc);
5026 drm_crtc_vblank_on(crtc);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 encoder->enable(encoder);
5030
5031 intel_crtc_enable_planes(crtc);
5032
5033 /* Underruns don't raise interrupts, so check manually. */
5034 i9xx_check_fifo_underruns(dev_priv);
5035 }
5036
5037 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5038 {
5039 struct drm_device *dev = crtc->base.dev;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041
5042 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5043 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5044 }
5045
5046 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5047 {
5048 struct drm_device *dev = crtc->dev;
5049 struct drm_i915_private *dev_priv = to_i915(dev);
5050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5051 struct intel_encoder *encoder;
5052 int pipe = intel_crtc->pipe;
5053
5054 WARN_ON(!crtc->enabled);
5055
5056 if (intel_crtc->active)
5057 return;
5058
5059 i9xx_set_pll_dividers(intel_crtc);
5060
5061 if (intel_crtc->config->has_dp_encoder)
5062 intel_dp_set_m_n(intel_crtc);
5063
5064 intel_set_pipe_timings(intel_crtc);
5065
5066 i9xx_set_pipeconf(intel_crtc);
5067
5068 intel_crtc->active = true;
5069
5070 if (!IS_GEN2(dev))
5071 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5072
5073 for_each_encoder_on_crtc(dev, crtc, encoder)
5074 if (encoder->pre_enable)
5075 encoder->pre_enable(encoder);
5076
5077 i9xx_enable_pll(intel_crtc);
5078
5079 i9xx_pfit_enable(intel_crtc);
5080
5081 intel_crtc_load_lut(crtc);
5082
5083 intel_update_watermarks(crtc);
5084 intel_enable_pipe(intel_crtc);
5085
5086 assert_vblank_disabled(crtc);
5087 drm_crtc_vblank_on(crtc);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 encoder->enable(encoder);
5091
5092 intel_crtc_enable_planes(crtc);
5093
5094 /*
5095 * Gen2 reports pipe underruns whenever all planes are disabled.
5096 * So don't enable underrun reporting before at least some planes
5097 * are enabled.
5098 * FIXME: Need to fix the logic to work when we turn off all planes
5099 * but leave the pipe running.
5100 */
5101 if (IS_GEN2(dev))
5102 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5103
5104 /* Underruns don't raise interrupts, so check manually. */
5105 i9xx_check_fifo_underruns(dev_priv);
5106 }
5107
5108 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5109 {
5110 struct drm_device *dev = crtc->base.dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112
5113 if (!crtc->config->gmch_pfit.control)
5114 return;
5115
5116 assert_pipe_disabled(dev_priv, crtc->pipe);
5117
5118 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5119 I915_READ(PFIT_CONTROL));
5120 I915_WRITE(PFIT_CONTROL, 0);
5121 }
5122
5123 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5124 {
5125 struct drm_device *dev = crtc->dev;
5126 struct drm_i915_private *dev_priv = dev->dev_private;
5127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5128 struct intel_encoder *encoder;
5129 int pipe = intel_crtc->pipe;
5130
5131 if (!intel_crtc->active)
5132 return;
5133
5134 /*
5135 * Gen2 reports pipe underruns whenever all planes are disabled.
5136 * So diasble underrun reporting before all the planes get disabled.
5137 * FIXME: Need to fix the logic to work when we turn off all planes
5138 * but leave the pipe running.
5139 */
5140 if (IS_GEN2(dev))
5141 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143 /*
5144 * Vblank time updates from the shadow to live plane control register
5145 * are blocked if the memory self-refresh mode is active at that
5146 * moment. So to make sure the plane gets truly disabled, disable
5147 * first the self-refresh mode. The self-refresh enable bit in turn
5148 * will be checked/applied by the HW only at the next frame start
5149 * event which is after the vblank start event, so we need to have a
5150 * wait-for-vblank between disabling the plane and the pipe.
5151 */
5152 intel_set_memory_cxsr(dev_priv, false);
5153 intel_crtc_disable_planes(crtc);
5154
5155 /*
5156 * On gen2 planes are double buffered but the pipe isn't, so we must
5157 * wait for planes to fully turn off before disabling the pipe.
5158 * We also need to wait on all gmch platforms because of the
5159 * self-refresh mode constraint explained above.
5160 */
5161 intel_wait_for_vblank(dev, pipe);
5162
5163 for_each_encoder_on_crtc(dev, crtc, encoder)
5164 encoder->disable(encoder);
5165
5166 drm_crtc_vblank_off(crtc);
5167 assert_vblank_disabled(crtc);
5168
5169 intel_disable_pipe(intel_crtc);
5170
5171 i9xx_pfit_disable(intel_crtc);
5172
5173 for_each_encoder_on_crtc(dev, crtc, encoder)
5174 if (encoder->post_disable)
5175 encoder->post_disable(encoder);
5176
5177 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5178 if (IS_CHERRYVIEW(dev))
5179 chv_disable_pll(dev_priv, pipe);
5180 else if (IS_VALLEYVIEW(dev))
5181 vlv_disable_pll(dev_priv, pipe);
5182 else
5183 i9xx_disable_pll(intel_crtc);
5184 }
5185
5186 if (!IS_GEN2(dev))
5187 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5188
5189 intel_crtc->active = false;
5190 intel_update_watermarks(crtc);
5191
5192 mutex_lock(&dev->struct_mutex);
5193 intel_fbc_update(dev);
5194 mutex_unlock(&dev->struct_mutex);
5195 }
5196
5197 static void i9xx_crtc_off(struct drm_crtc *crtc)
5198 {
5199 }
5200
5201 /* Master function to enable/disable CRTC and corresponding power wells */
5202 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5203 {
5204 struct drm_device *dev = crtc->dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207 enum intel_display_power_domain domain;
5208 unsigned long domains;
5209
5210 if (enable) {
5211 if (!intel_crtc->active) {
5212 domains = get_crtc_power_domains(crtc);
5213 for_each_power_domain(domain, domains)
5214 intel_display_power_get(dev_priv, domain);
5215 intel_crtc->enabled_power_domains = domains;
5216
5217 dev_priv->display.crtc_enable(crtc);
5218 }
5219 } else {
5220 if (intel_crtc->active) {
5221 dev_priv->display.crtc_disable(crtc);
5222
5223 domains = intel_crtc->enabled_power_domains;
5224 for_each_power_domain(domain, domains)
5225 intel_display_power_put(dev_priv, domain);
5226 intel_crtc->enabled_power_domains = 0;
5227 }
5228 }
5229 }
5230
5231 /**
5232 * Sets the power management mode of the pipe and plane.
5233 */
5234 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5235 {
5236 struct drm_device *dev = crtc->dev;
5237 struct intel_encoder *intel_encoder;
5238 bool enable = false;
5239
5240 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5241 enable |= intel_encoder->connectors_active;
5242
5243 intel_crtc_control(crtc, enable);
5244 }
5245
5246 static void intel_crtc_disable(struct drm_crtc *crtc)
5247 {
5248 struct drm_device *dev = crtc->dev;
5249 struct drm_connector *connector;
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251
5252 /* crtc should still be enabled when we disable it. */
5253 WARN_ON(!crtc->enabled);
5254
5255 dev_priv->display.crtc_disable(crtc);
5256 dev_priv->display.off(crtc);
5257
5258 crtc->primary->funcs->disable_plane(crtc->primary);
5259
5260 /* Update computed state. */
5261 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5262 if (!connector->encoder || !connector->encoder->crtc)
5263 continue;
5264
5265 if (connector->encoder->crtc != crtc)
5266 continue;
5267
5268 connector->dpms = DRM_MODE_DPMS_OFF;
5269 to_intel_encoder(connector->encoder)->connectors_active = false;
5270 }
5271 }
5272
5273 void intel_encoder_destroy(struct drm_encoder *encoder)
5274 {
5275 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5276
5277 drm_encoder_cleanup(encoder);
5278 kfree(intel_encoder);
5279 }
5280
5281 /* Simple dpms helper for encoders with just one connector, no cloning and only
5282 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5283 * state of the entire output pipe. */
5284 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5285 {
5286 if (mode == DRM_MODE_DPMS_ON) {
5287 encoder->connectors_active = true;
5288
5289 intel_crtc_update_dpms(encoder->base.crtc);
5290 } else {
5291 encoder->connectors_active = false;
5292
5293 intel_crtc_update_dpms(encoder->base.crtc);
5294 }
5295 }
5296
5297 /* Cross check the actual hw state with our own modeset state tracking (and it's
5298 * internal consistency). */
5299 static void intel_connector_check_state(struct intel_connector *connector)
5300 {
5301 if (connector->get_hw_state(connector)) {
5302 struct intel_encoder *encoder = connector->encoder;
5303 struct drm_crtc *crtc;
5304 bool encoder_enabled;
5305 enum pipe pipe;
5306
5307 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5308 connector->base.base.id,
5309 connector->base.name);
5310
5311 /* there is no real hw state for MST connectors */
5312 if (connector->mst_port)
5313 return;
5314
5315 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5316 "wrong connector dpms state\n");
5317 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5318 "active connector not linked to encoder\n");
5319
5320 if (encoder) {
5321 I915_STATE_WARN(!encoder->connectors_active,
5322 "encoder->connectors_active not set\n");
5323
5324 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5325 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5326 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5327 return;
5328
5329 crtc = encoder->base.crtc;
5330
5331 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5332 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5333 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5334 "encoder active on the wrong pipe\n");
5335 }
5336 }
5337 }
5338
5339 /* Even simpler default implementation, if there's really no special case to
5340 * consider. */
5341 void intel_connector_dpms(struct drm_connector *connector, int mode)
5342 {
5343 /* All the simple cases only support two dpms states. */
5344 if (mode != DRM_MODE_DPMS_ON)
5345 mode = DRM_MODE_DPMS_OFF;
5346
5347 if (mode == connector->dpms)
5348 return;
5349
5350 connector->dpms = mode;
5351
5352 /* Only need to change hw state when actually enabled */
5353 if (connector->encoder)
5354 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5355
5356 intel_modeset_check_state(connector->dev);
5357 }
5358
5359 /* Simple connector->get_hw_state implementation for encoders that support only
5360 * one connector and no cloning and hence the encoder state determines the state
5361 * of the connector. */
5362 bool intel_connector_get_hw_state(struct intel_connector *connector)
5363 {
5364 enum pipe pipe = 0;
5365 struct intel_encoder *encoder = connector->encoder;
5366
5367 return encoder->get_hw_state(encoder, &pipe);
5368 }
5369
5370 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5371 struct intel_crtc_state *pipe_config)
5372 {
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct intel_crtc *pipe_B_crtc =
5375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5376
5377 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5378 pipe_name(pipe), pipe_config->fdi_lanes);
5379 if (pipe_config->fdi_lanes > 4) {
5380 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5381 pipe_name(pipe), pipe_config->fdi_lanes);
5382 return false;
5383 }
5384
5385 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5386 if (pipe_config->fdi_lanes > 2) {
5387 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5388 pipe_config->fdi_lanes);
5389 return false;
5390 } else {
5391 return true;
5392 }
5393 }
5394
5395 if (INTEL_INFO(dev)->num_pipes == 2)
5396 return true;
5397
5398 /* Ivybridge 3 pipe is really complicated */
5399 switch (pipe) {
5400 case PIPE_A:
5401 return true;
5402 case PIPE_B:
5403 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5404 pipe_config->fdi_lanes > 2) {
5405 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5406 pipe_name(pipe), pipe_config->fdi_lanes);
5407 return false;
5408 }
5409 return true;
5410 case PIPE_C:
5411 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5412 pipe_B_crtc->config->fdi_lanes <= 2) {
5413 if (pipe_config->fdi_lanes > 2) {
5414 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5415 pipe_name(pipe), pipe_config->fdi_lanes);
5416 return false;
5417 }
5418 } else {
5419 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5420 return false;
5421 }
5422 return true;
5423 default:
5424 BUG();
5425 }
5426 }
5427
5428 #define RETRY 1
5429 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5430 struct intel_crtc_state *pipe_config)
5431 {
5432 struct drm_device *dev = intel_crtc->base.dev;
5433 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5434 int lane, link_bw, fdi_dotclock;
5435 bool setup_ok, needs_recompute = false;
5436
5437 retry:
5438 /* FDI is a binary signal running at ~2.7GHz, encoding
5439 * each output octet as 10 bits. The actual frequency
5440 * is stored as a divider into a 100MHz clock, and the
5441 * mode pixel clock is stored in units of 1KHz.
5442 * Hence the bw of each lane in terms of the mode signal
5443 * is:
5444 */
5445 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5446
5447 fdi_dotclock = adjusted_mode->crtc_clock;
5448
5449 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5450 pipe_config->pipe_bpp);
5451
5452 pipe_config->fdi_lanes = lane;
5453
5454 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5455 link_bw, &pipe_config->fdi_m_n);
5456
5457 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5458 intel_crtc->pipe, pipe_config);
5459 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5460 pipe_config->pipe_bpp -= 2*3;
5461 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5462 pipe_config->pipe_bpp);
5463 needs_recompute = true;
5464 pipe_config->bw_constrained = true;
5465
5466 goto retry;
5467 }
5468
5469 if (needs_recompute)
5470 return RETRY;
5471
5472 return setup_ok ? 0 : -EINVAL;
5473 }
5474
5475 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5476 struct intel_crtc_state *pipe_config)
5477 {
5478 pipe_config->ips_enabled = i915.enable_ips &&
5479 hsw_crtc_supports_ips(crtc) &&
5480 pipe_config->pipe_bpp <= 24;
5481 }
5482
5483 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5484 struct intel_crtc_state *pipe_config)
5485 {
5486 struct drm_device *dev = crtc->base.dev;
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5489
5490 /* FIXME should check pixel clock limits on all platforms */
5491 if (INTEL_INFO(dev)->gen < 4) {
5492 int clock_limit =
5493 dev_priv->display.get_display_clock_speed(dev);
5494
5495 /*
5496 * Enable pixel doubling when the dot clock
5497 * is > 90% of the (display) core speed.
5498 *
5499 * GDG double wide on either pipe,
5500 * otherwise pipe A only.
5501 */
5502 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5503 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5504 clock_limit *= 2;
5505 pipe_config->double_wide = true;
5506 }
5507
5508 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5509 return -EINVAL;
5510 }
5511
5512 /*
5513 * Pipe horizontal size must be even in:
5514 * - DVO ganged mode
5515 * - LVDS dual channel mode
5516 * - Double wide pipe
5517 */
5518 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5519 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5520 pipe_config->pipe_src_w &= ~1;
5521
5522 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5523 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5524 */
5525 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5526 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5527 return -EINVAL;
5528
5529 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5530 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5531 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5532 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5533 * for lvds. */
5534 pipe_config->pipe_bpp = 8*3;
5535 }
5536
5537 if (HAS_IPS(dev))
5538 hsw_compute_ips_config(crtc, pipe_config);
5539
5540 if (pipe_config->has_pch_encoder)
5541 return ironlake_fdi_compute_config(crtc, pipe_config);
5542
5543 return 0;
5544 }
5545
5546 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5547 {
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 u32 val;
5550 int divider;
5551
5552 /* FIXME: Punit isn't quite ready yet */
5553 if (IS_CHERRYVIEW(dev))
5554 return 400000;
5555
5556 if (dev_priv->hpll_freq == 0)
5557 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5558
5559 mutex_lock(&dev_priv->dpio_lock);
5560 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5561 mutex_unlock(&dev_priv->dpio_lock);
5562
5563 divider = val & DISPLAY_FREQUENCY_VALUES;
5564
5565 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5566 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5567 "cdclk change in progress\n");
5568
5569 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5570 }
5571
5572 static int i945_get_display_clock_speed(struct drm_device *dev)
5573 {
5574 return 400000;
5575 }
5576
5577 static int i915_get_display_clock_speed(struct drm_device *dev)
5578 {
5579 return 333000;
5580 }
5581
5582 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5583 {
5584 return 200000;
5585 }
5586
5587 static int pnv_get_display_clock_speed(struct drm_device *dev)
5588 {
5589 u16 gcfgc = 0;
5590
5591 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5592
5593 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5594 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5595 return 267000;
5596 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5597 return 333000;
5598 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5599 return 444000;
5600 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5601 return 200000;
5602 default:
5603 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5604 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5605 return 133000;
5606 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5607 return 167000;
5608 }
5609 }
5610
5611 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5612 {
5613 u16 gcfgc = 0;
5614
5615 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5616
5617 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5618 return 133000;
5619 else {
5620 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5621 case GC_DISPLAY_CLOCK_333_MHZ:
5622 return 333000;
5623 default:
5624 case GC_DISPLAY_CLOCK_190_200_MHZ:
5625 return 190000;
5626 }
5627 }
5628 }
5629
5630 static int i865_get_display_clock_speed(struct drm_device *dev)
5631 {
5632 return 266000;
5633 }
5634
5635 static int i855_get_display_clock_speed(struct drm_device *dev)
5636 {
5637 u16 hpllcc = 0;
5638 /* Assume that the hardware is in the high speed state. This
5639 * should be the default.
5640 */
5641 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5642 case GC_CLOCK_133_200:
5643 case GC_CLOCK_100_200:
5644 return 200000;
5645 case GC_CLOCK_166_250:
5646 return 250000;
5647 case GC_CLOCK_100_133:
5648 return 133000;
5649 }
5650
5651 /* Shouldn't happen */
5652 return 0;
5653 }
5654
5655 static int i830_get_display_clock_speed(struct drm_device *dev)
5656 {
5657 return 133000;
5658 }
5659
5660 static void
5661 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5662 {
5663 while (*num > DATA_LINK_M_N_MASK ||
5664 *den > DATA_LINK_M_N_MASK) {
5665 *num >>= 1;
5666 *den >>= 1;
5667 }
5668 }
5669
5670 static void compute_m_n(unsigned int m, unsigned int n,
5671 uint32_t *ret_m, uint32_t *ret_n)
5672 {
5673 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5674 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5675 intel_reduce_m_n_ratio(ret_m, ret_n);
5676 }
5677
5678 void
5679 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5680 int pixel_clock, int link_clock,
5681 struct intel_link_m_n *m_n)
5682 {
5683 m_n->tu = 64;
5684
5685 compute_m_n(bits_per_pixel * pixel_clock,
5686 link_clock * nlanes * 8,
5687 &m_n->gmch_m, &m_n->gmch_n);
5688
5689 compute_m_n(pixel_clock, link_clock,
5690 &m_n->link_m, &m_n->link_n);
5691 }
5692
5693 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5694 {
5695 if (i915.panel_use_ssc >= 0)
5696 return i915.panel_use_ssc != 0;
5697 return dev_priv->vbt.lvds_use_ssc
5698 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5699 }
5700
5701 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5702 {
5703 struct drm_device *dev = crtc->base.dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
5705 int refclk;
5706
5707 if (IS_VALLEYVIEW(dev)) {
5708 refclk = 100000;
5709 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5710 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5711 refclk = dev_priv->vbt.lvds_ssc_freq;
5712 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5713 } else if (!IS_GEN2(dev)) {
5714 refclk = 96000;
5715 } else {
5716 refclk = 48000;
5717 }
5718
5719 return refclk;
5720 }
5721
5722 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5723 {
5724 return (1 << dpll->n) << 16 | dpll->m2;
5725 }
5726
5727 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5728 {
5729 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5730 }
5731
5732 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5733 struct intel_crtc_state *crtc_state,
5734 intel_clock_t *reduced_clock)
5735 {
5736 struct drm_device *dev = crtc->base.dev;
5737 u32 fp, fp2 = 0;
5738
5739 if (IS_PINEVIEW(dev)) {
5740 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5741 if (reduced_clock)
5742 fp2 = pnv_dpll_compute_fp(reduced_clock);
5743 } else {
5744 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5745 if (reduced_clock)
5746 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5747 }
5748
5749 crtc_state->dpll_hw_state.fp0 = fp;
5750
5751 crtc->lowfreq_avail = false;
5752 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5753 reduced_clock && i915.powersave) {
5754 crtc_state->dpll_hw_state.fp1 = fp2;
5755 crtc->lowfreq_avail = true;
5756 } else {
5757 crtc_state->dpll_hw_state.fp1 = fp;
5758 }
5759 }
5760
5761 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5762 pipe)
5763 {
5764 u32 reg_val;
5765
5766 /*
5767 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5768 * and set it to a reasonable value instead.
5769 */
5770 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5771 reg_val &= 0xffffff00;
5772 reg_val |= 0x00000030;
5773 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5774
5775 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5776 reg_val &= 0x8cffffff;
5777 reg_val = 0x8c000000;
5778 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5779
5780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5781 reg_val &= 0xffffff00;
5782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5783
5784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5785 reg_val &= 0x00ffffff;
5786 reg_val |= 0xb0000000;
5787 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5788 }
5789
5790 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5791 struct intel_link_m_n *m_n)
5792 {
5793 struct drm_device *dev = crtc->base.dev;
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 int pipe = crtc->pipe;
5796
5797 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5798 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5799 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5800 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5801 }
5802
5803 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5804 struct intel_link_m_n *m_n,
5805 struct intel_link_m_n *m2_n2)
5806 {
5807 struct drm_device *dev = crtc->base.dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 int pipe = crtc->pipe;
5810 enum transcoder transcoder = crtc->config->cpu_transcoder;
5811
5812 if (INTEL_INFO(dev)->gen >= 5) {
5813 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5814 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5815 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5816 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5817 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5818 * for gen < 8) and if DRRS is supported (to make sure the
5819 * registers are not unnecessarily accessed).
5820 */
5821 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5822 crtc->config->has_drrs) {
5823 I915_WRITE(PIPE_DATA_M2(transcoder),
5824 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5825 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5826 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5827 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5828 }
5829 } else {
5830 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5831 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5832 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5833 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5834 }
5835 }
5836
5837 void intel_dp_set_m_n(struct intel_crtc *crtc)
5838 {
5839 if (crtc->config->has_pch_encoder)
5840 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5841 else
5842 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5843 &crtc->config->dp_m2_n2);
5844 }
5845
5846 static void vlv_update_pll(struct intel_crtc *crtc,
5847 struct intel_crtc_state *pipe_config)
5848 {
5849 u32 dpll, dpll_md;
5850
5851 /*
5852 * Enable DPIO clock input. We should never disable the reference
5853 * clock for pipe B, since VGA hotplug / manual detection depends
5854 * on it.
5855 */
5856 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5857 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5858 /* We should never disable this, set it here for state tracking */
5859 if (crtc->pipe == PIPE_B)
5860 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5861 dpll |= DPLL_VCO_ENABLE;
5862 pipe_config->dpll_hw_state.dpll = dpll;
5863
5864 dpll_md = (pipe_config->pixel_multiplier - 1)
5865 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5866 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5867 }
5868
5869 static void vlv_prepare_pll(struct intel_crtc *crtc,
5870 const struct intel_crtc_state *pipe_config)
5871 {
5872 struct drm_device *dev = crtc->base.dev;
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874 int pipe = crtc->pipe;
5875 u32 mdiv;
5876 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5877 u32 coreclk, reg_val;
5878
5879 mutex_lock(&dev_priv->dpio_lock);
5880
5881 bestn = pipe_config->dpll.n;
5882 bestm1 = pipe_config->dpll.m1;
5883 bestm2 = pipe_config->dpll.m2;
5884 bestp1 = pipe_config->dpll.p1;
5885 bestp2 = pipe_config->dpll.p2;
5886
5887 /* See eDP HDMI DPIO driver vbios notes doc */
5888
5889 /* PLL B needs special handling */
5890 if (pipe == PIPE_B)
5891 vlv_pllb_recal_opamp(dev_priv, pipe);
5892
5893 /* Set up Tx target for periodic Rcomp update */
5894 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5895
5896 /* Disable target IRef on PLL */
5897 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5898 reg_val &= 0x00ffffff;
5899 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5900
5901 /* Disable fast lock */
5902 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5903
5904 /* Set idtafcrecal before PLL is enabled */
5905 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5906 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5907 mdiv |= ((bestn << DPIO_N_SHIFT));
5908 mdiv |= (1 << DPIO_K_SHIFT);
5909
5910 /*
5911 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5912 * but we don't support that).
5913 * Note: don't use the DAC post divider as it seems unstable.
5914 */
5915 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5916 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5917
5918 mdiv |= DPIO_ENABLE_CALIBRATION;
5919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5920
5921 /* Set HBR and RBR LPF coefficients */
5922 if (pipe_config->port_clock == 162000 ||
5923 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5924 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5925 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5926 0x009f0003);
5927 else
5928 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5929 0x00d0000f);
5930
5931 if (pipe_config->has_dp_encoder) {
5932 /* Use SSC source */
5933 if (pipe == PIPE_A)
5934 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5935 0x0df40000);
5936 else
5937 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5938 0x0df70000);
5939 } else { /* HDMI or VGA */
5940 /* Use bend source */
5941 if (pipe == PIPE_A)
5942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5943 0x0df70000);
5944 else
5945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5946 0x0df40000);
5947 }
5948
5949 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5950 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5951 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5953 coreclk |= 0x01000000;
5954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5955
5956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5957 mutex_unlock(&dev_priv->dpio_lock);
5958 }
5959
5960 static void chv_update_pll(struct intel_crtc *crtc,
5961 struct intel_crtc_state *pipe_config)
5962 {
5963 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5964 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5965 DPLL_VCO_ENABLE;
5966 if (crtc->pipe != PIPE_A)
5967 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5968
5969 pipe_config->dpll_hw_state.dpll_md =
5970 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5971 }
5972
5973 static void chv_prepare_pll(struct intel_crtc *crtc,
5974 const struct intel_crtc_state *pipe_config)
5975 {
5976 struct drm_device *dev = crtc->base.dev;
5977 struct drm_i915_private *dev_priv = dev->dev_private;
5978 int pipe = crtc->pipe;
5979 int dpll_reg = DPLL(crtc->pipe);
5980 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5981 u32 loopfilter, intcoeff;
5982 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5983 int refclk;
5984
5985 bestn = pipe_config->dpll.n;
5986 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5987 bestm1 = pipe_config->dpll.m1;
5988 bestm2 = pipe_config->dpll.m2 >> 22;
5989 bestp1 = pipe_config->dpll.p1;
5990 bestp2 = pipe_config->dpll.p2;
5991
5992 /*
5993 * Enable Refclk and SSC
5994 */
5995 I915_WRITE(dpll_reg,
5996 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5997
5998 mutex_lock(&dev_priv->dpio_lock);
5999
6000 /* p1 and p2 divider */
6001 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6002 5 << DPIO_CHV_S1_DIV_SHIFT |
6003 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6004 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6005 1 << DPIO_CHV_K_DIV_SHIFT);
6006
6007 /* Feedback post-divider - m2 */
6008 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6009
6010 /* Feedback refclk divider - n and m1 */
6011 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6012 DPIO_CHV_M1_DIV_BY_2 |
6013 1 << DPIO_CHV_N_DIV_SHIFT);
6014
6015 /* M2 fraction division */
6016 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6017
6018 /* M2 fraction division enable */
6019 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6020 DPIO_CHV_FRAC_DIV_EN |
6021 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6022
6023 /* Loop filter */
6024 refclk = i9xx_get_refclk(crtc, 0);
6025 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6026 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6027 if (refclk == 100000)
6028 intcoeff = 11;
6029 else if (refclk == 38400)
6030 intcoeff = 10;
6031 else
6032 intcoeff = 9;
6033 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6034 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6035
6036 /* AFC Recal */
6037 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6038 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6039 DPIO_AFC_RECAL);
6040
6041 mutex_unlock(&dev_priv->dpio_lock);
6042 }
6043
6044 /**
6045 * vlv_force_pll_on - forcibly enable just the PLL
6046 * @dev_priv: i915 private structure
6047 * @pipe: pipe PLL to enable
6048 * @dpll: PLL configuration
6049 *
6050 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6051 * in cases where we need the PLL enabled even when @pipe is not going to
6052 * be enabled.
6053 */
6054 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6055 const struct dpll *dpll)
6056 {
6057 struct intel_crtc *crtc =
6058 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6059 struct intel_crtc_state pipe_config = {
6060 .pixel_multiplier = 1,
6061 .dpll = *dpll,
6062 };
6063
6064 if (IS_CHERRYVIEW(dev)) {
6065 chv_update_pll(crtc, &pipe_config);
6066 chv_prepare_pll(crtc, &pipe_config);
6067 chv_enable_pll(crtc, &pipe_config);
6068 } else {
6069 vlv_update_pll(crtc, &pipe_config);
6070 vlv_prepare_pll(crtc, &pipe_config);
6071 vlv_enable_pll(crtc, &pipe_config);
6072 }
6073 }
6074
6075 /**
6076 * vlv_force_pll_off - forcibly disable just the PLL
6077 * @dev_priv: i915 private structure
6078 * @pipe: pipe PLL to disable
6079 *
6080 * Disable the PLL for @pipe. To be used in cases where we need
6081 * the PLL enabled even when @pipe is not going to be enabled.
6082 */
6083 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6084 {
6085 if (IS_CHERRYVIEW(dev))
6086 chv_disable_pll(to_i915(dev), pipe);
6087 else
6088 vlv_disable_pll(to_i915(dev), pipe);
6089 }
6090
6091 static void i9xx_update_pll(struct intel_crtc *crtc,
6092 struct intel_crtc_state *crtc_state,
6093 intel_clock_t *reduced_clock,
6094 int num_connectors)
6095 {
6096 struct drm_device *dev = crtc->base.dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 u32 dpll;
6099 bool is_sdvo;
6100 struct dpll *clock = &crtc_state->dpll;
6101
6102 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6103
6104 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6105 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6106
6107 dpll = DPLL_VGA_MODE_DIS;
6108
6109 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6110 dpll |= DPLLB_MODE_LVDS;
6111 else
6112 dpll |= DPLLB_MODE_DAC_SERIAL;
6113
6114 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6115 dpll |= (crtc_state->pixel_multiplier - 1)
6116 << SDVO_MULTIPLIER_SHIFT_HIRES;
6117 }
6118
6119 if (is_sdvo)
6120 dpll |= DPLL_SDVO_HIGH_SPEED;
6121
6122 if (crtc_state->has_dp_encoder)
6123 dpll |= DPLL_SDVO_HIGH_SPEED;
6124
6125 /* compute bitmask from p1 value */
6126 if (IS_PINEVIEW(dev))
6127 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6128 else {
6129 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6130 if (IS_G4X(dev) && reduced_clock)
6131 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6132 }
6133 switch (clock->p2) {
6134 case 5:
6135 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6136 break;
6137 case 7:
6138 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6139 break;
6140 case 10:
6141 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6142 break;
6143 case 14:
6144 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6145 break;
6146 }
6147 if (INTEL_INFO(dev)->gen >= 4)
6148 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6149
6150 if (crtc_state->sdvo_tv_clock)
6151 dpll |= PLL_REF_INPUT_TVCLKINBC;
6152 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6153 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6154 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6155 else
6156 dpll |= PLL_REF_INPUT_DREFCLK;
6157
6158 dpll |= DPLL_VCO_ENABLE;
6159 crtc_state->dpll_hw_state.dpll = dpll;
6160
6161 if (INTEL_INFO(dev)->gen >= 4) {
6162 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6163 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6164 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6165 }
6166 }
6167
6168 static void i8xx_update_pll(struct intel_crtc *crtc,
6169 struct intel_crtc_state *crtc_state,
6170 intel_clock_t *reduced_clock,
6171 int num_connectors)
6172 {
6173 struct drm_device *dev = crtc->base.dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 u32 dpll;
6176 struct dpll *clock = &crtc_state->dpll;
6177
6178 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6179
6180 dpll = DPLL_VGA_MODE_DIS;
6181
6182 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6183 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6184 } else {
6185 if (clock->p1 == 2)
6186 dpll |= PLL_P1_DIVIDE_BY_TWO;
6187 else
6188 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6189 if (clock->p2 == 4)
6190 dpll |= PLL_P2_DIVIDE_BY_4;
6191 }
6192
6193 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6194 dpll |= DPLL_DVO_2X_MODE;
6195
6196 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6197 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6198 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6199 else
6200 dpll |= PLL_REF_INPUT_DREFCLK;
6201
6202 dpll |= DPLL_VCO_ENABLE;
6203 crtc_state->dpll_hw_state.dpll = dpll;
6204 }
6205
6206 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6207 {
6208 struct drm_device *dev = intel_crtc->base.dev;
6209 struct drm_i915_private *dev_priv = dev->dev_private;
6210 enum pipe pipe = intel_crtc->pipe;
6211 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6212 struct drm_display_mode *adjusted_mode =
6213 &intel_crtc->config->base.adjusted_mode;
6214 uint32_t crtc_vtotal, crtc_vblank_end;
6215 int vsyncshift = 0;
6216
6217 /* We need to be careful not to changed the adjusted mode, for otherwise
6218 * the hw state checker will get angry at the mismatch. */
6219 crtc_vtotal = adjusted_mode->crtc_vtotal;
6220 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6221
6222 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6223 /* the chip adds 2 halflines automatically */
6224 crtc_vtotal -= 1;
6225 crtc_vblank_end -= 1;
6226
6227 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6228 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6229 else
6230 vsyncshift = adjusted_mode->crtc_hsync_start -
6231 adjusted_mode->crtc_htotal / 2;
6232 if (vsyncshift < 0)
6233 vsyncshift += adjusted_mode->crtc_htotal;
6234 }
6235
6236 if (INTEL_INFO(dev)->gen > 3)
6237 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6238
6239 I915_WRITE(HTOTAL(cpu_transcoder),
6240 (adjusted_mode->crtc_hdisplay - 1) |
6241 ((adjusted_mode->crtc_htotal - 1) << 16));
6242 I915_WRITE(HBLANK(cpu_transcoder),
6243 (adjusted_mode->crtc_hblank_start - 1) |
6244 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6245 I915_WRITE(HSYNC(cpu_transcoder),
6246 (adjusted_mode->crtc_hsync_start - 1) |
6247 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6248
6249 I915_WRITE(VTOTAL(cpu_transcoder),
6250 (adjusted_mode->crtc_vdisplay - 1) |
6251 ((crtc_vtotal - 1) << 16));
6252 I915_WRITE(VBLANK(cpu_transcoder),
6253 (adjusted_mode->crtc_vblank_start - 1) |
6254 ((crtc_vblank_end - 1) << 16));
6255 I915_WRITE(VSYNC(cpu_transcoder),
6256 (adjusted_mode->crtc_vsync_start - 1) |
6257 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6258
6259 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6260 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6261 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6262 * bits. */
6263 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6264 (pipe == PIPE_B || pipe == PIPE_C))
6265 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6266
6267 /* pipesrc controls the size that is scaled from, which should
6268 * always be the user's requested size.
6269 */
6270 I915_WRITE(PIPESRC(pipe),
6271 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6272 (intel_crtc->config->pipe_src_h - 1));
6273 }
6274
6275 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6276 struct intel_crtc_state *pipe_config)
6277 {
6278 struct drm_device *dev = crtc->base.dev;
6279 struct drm_i915_private *dev_priv = dev->dev_private;
6280 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6281 uint32_t tmp;
6282
6283 tmp = I915_READ(HTOTAL(cpu_transcoder));
6284 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6285 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6286 tmp = I915_READ(HBLANK(cpu_transcoder));
6287 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6288 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6289 tmp = I915_READ(HSYNC(cpu_transcoder));
6290 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6291 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6292
6293 tmp = I915_READ(VTOTAL(cpu_transcoder));
6294 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6295 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6296 tmp = I915_READ(VBLANK(cpu_transcoder));
6297 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6298 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6299 tmp = I915_READ(VSYNC(cpu_transcoder));
6300 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6301 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6302
6303 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6304 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6305 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6306 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6307 }
6308
6309 tmp = I915_READ(PIPESRC(crtc->pipe));
6310 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6311 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6312
6313 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6314 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6315 }
6316
6317 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6318 struct intel_crtc_state *pipe_config)
6319 {
6320 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6321 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6322 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6323 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6324
6325 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6326 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6327 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6328 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6329
6330 mode->flags = pipe_config->base.adjusted_mode.flags;
6331
6332 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6333 mode->flags |= pipe_config->base.adjusted_mode.flags;
6334 }
6335
6336 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6337 {
6338 struct drm_device *dev = intel_crtc->base.dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 uint32_t pipeconf;
6341
6342 pipeconf = 0;
6343
6344 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6345 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6346 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6347
6348 if (intel_crtc->config->double_wide)
6349 pipeconf |= PIPECONF_DOUBLE_WIDE;
6350
6351 /* only g4x and later have fancy bpc/dither controls */
6352 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6353 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6354 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6355 pipeconf |= PIPECONF_DITHER_EN |
6356 PIPECONF_DITHER_TYPE_SP;
6357
6358 switch (intel_crtc->config->pipe_bpp) {
6359 case 18:
6360 pipeconf |= PIPECONF_6BPC;
6361 break;
6362 case 24:
6363 pipeconf |= PIPECONF_8BPC;
6364 break;
6365 case 30:
6366 pipeconf |= PIPECONF_10BPC;
6367 break;
6368 default:
6369 /* Case prevented by intel_choose_pipe_bpp_dither. */
6370 BUG();
6371 }
6372 }
6373
6374 if (HAS_PIPE_CXSR(dev)) {
6375 if (intel_crtc->lowfreq_avail) {
6376 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6377 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6378 } else {
6379 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6380 }
6381 }
6382
6383 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6384 if (INTEL_INFO(dev)->gen < 4 ||
6385 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6386 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6387 else
6388 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6389 } else
6390 pipeconf |= PIPECONF_PROGRESSIVE;
6391
6392 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6393 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6394
6395 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6396 POSTING_READ(PIPECONF(intel_crtc->pipe));
6397 }
6398
6399 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6400 struct intel_crtc_state *crtc_state)
6401 {
6402 struct drm_device *dev = crtc->base.dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 int refclk, num_connectors = 0;
6405 intel_clock_t clock, reduced_clock;
6406 bool ok, has_reduced_clock = false;
6407 bool is_lvds = false, is_dsi = false;
6408 struct intel_encoder *encoder;
6409 const intel_limit_t *limit;
6410
6411 for_each_intel_encoder(dev, encoder) {
6412 if (encoder->new_crtc != crtc)
6413 continue;
6414
6415 switch (encoder->type) {
6416 case INTEL_OUTPUT_LVDS:
6417 is_lvds = true;
6418 break;
6419 case INTEL_OUTPUT_DSI:
6420 is_dsi = true;
6421 break;
6422 default:
6423 break;
6424 }
6425
6426 num_connectors++;
6427 }
6428
6429 if (is_dsi)
6430 return 0;
6431
6432 if (!crtc_state->clock_set) {
6433 refclk = i9xx_get_refclk(crtc, num_connectors);
6434
6435 /*
6436 * Returns a set of divisors for the desired target clock with
6437 * the given refclk, or FALSE. The returned values represent
6438 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6439 * 2) / p1 / p2.
6440 */
6441 limit = intel_limit(crtc, refclk);
6442 ok = dev_priv->display.find_dpll(limit, crtc,
6443 crtc_state->port_clock,
6444 refclk, NULL, &clock);
6445 if (!ok) {
6446 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6447 return -EINVAL;
6448 }
6449
6450 if (is_lvds && dev_priv->lvds_downclock_avail) {
6451 /*
6452 * Ensure we match the reduced clock's P to the target
6453 * clock. If the clocks don't match, we can't switch
6454 * the display clock by using the FP0/FP1. In such case
6455 * we will disable the LVDS downclock feature.
6456 */
6457 has_reduced_clock =
6458 dev_priv->display.find_dpll(limit, crtc,
6459 dev_priv->lvds_downclock,
6460 refclk, &clock,
6461 &reduced_clock);
6462 }
6463 /* Compat-code for transition, will disappear. */
6464 crtc_state->dpll.n = clock.n;
6465 crtc_state->dpll.m1 = clock.m1;
6466 crtc_state->dpll.m2 = clock.m2;
6467 crtc_state->dpll.p1 = clock.p1;
6468 crtc_state->dpll.p2 = clock.p2;
6469 }
6470
6471 if (IS_GEN2(dev)) {
6472 i8xx_update_pll(crtc, crtc_state,
6473 has_reduced_clock ? &reduced_clock : NULL,
6474 num_connectors);
6475 } else if (IS_CHERRYVIEW(dev)) {
6476 chv_update_pll(crtc, crtc_state);
6477 } else if (IS_VALLEYVIEW(dev)) {
6478 vlv_update_pll(crtc, crtc_state);
6479 } else {
6480 i9xx_update_pll(crtc, crtc_state,
6481 has_reduced_clock ? &reduced_clock : NULL,
6482 num_connectors);
6483 }
6484
6485 return 0;
6486 }
6487
6488 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6489 struct intel_crtc_state *pipe_config)
6490 {
6491 struct drm_device *dev = crtc->base.dev;
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 uint32_t tmp;
6494
6495 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6496 return;
6497
6498 tmp = I915_READ(PFIT_CONTROL);
6499 if (!(tmp & PFIT_ENABLE))
6500 return;
6501
6502 /* Check whether the pfit is attached to our pipe. */
6503 if (INTEL_INFO(dev)->gen < 4) {
6504 if (crtc->pipe != PIPE_B)
6505 return;
6506 } else {
6507 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6508 return;
6509 }
6510
6511 pipe_config->gmch_pfit.control = tmp;
6512 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6513 if (INTEL_INFO(dev)->gen < 5)
6514 pipe_config->gmch_pfit.lvds_border_bits =
6515 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6516 }
6517
6518 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6519 struct intel_crtc_state *pipe_config)
6520 {
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 int pipe = pipe_config->cpu_transcoder;
6524 intel_clock_t clock;
6525 u32 mdiv;
6526 int refclk = 100000;
6527
6528 /* In case of MIPI DPLL will not even be used */
6529 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6530 return;
6531
6532 mutex_lock(&dev_priv->dpio_lock);
6533 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6534 mutex_unlock(&dev_priv->dpio_lock);
6535
6536 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6537 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6538 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6539 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6540 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6541
6542 vlv_clock(refclk, &clock);
6543
6544 /* clock.dot is the fast clock */
6545 pipe_config->port_clock = clock.dot / 5;
6546 }
6547
6548 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6549 struct intel_plane_config *plane_config)
6550 {
6551 struct drm_device *dev = crtc->base.dev;
6552 struct drm_i915_private *dev_priv = dev->dev_private;
6553 u32 val, base, offset;
6554 int pipe = crtc->pipe, plane = crtc->plane;
6555 int fourcc, pixel_format;
6556 int aligned_height;
6557
6558 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6559 if (!crtc->base.primary->fb) {
6560 DRM_DEBUG_KMS("failed to alloc fb\n");
6561 return;
6562 }
6563
6564 val = I915_READ(DSPCNTR(plane));
6565
6566 if (INTEL_INFO(dev)->gen >= 4)
6567 if (val & DISPPLANE_TILED)
6568 plane_config->tiled = true;
6569
6570 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6571 fourcc = intel_format_to_fourcc(pixel_format);
6572 crtc->base.primary->fb->pixel_format = fourcc;
6573 crtc->base.primary->fb->bits_per_pixel =
6574 drm_format_plane_cpp(fourcc, 0) * 8;
6575
6576 if (INTEL_INFO(dev)->gen >= 4) {
6577 if (plane_config->tiled)
6578 offset = I915_READ(DSPTILEOFF(plane));
6579 else
6580 offset = I915_READ(DSPLINOFF(plane));
6581 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6582 } else {
6583 base = I915_READ(DSPADDR(plane));
6584 }
6585 plane_config->base = base;
6586
6587 val = I915_READ(PIPESRC(pipe));
6588 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6589 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6590
6591 val = I915_READ(DSPSTRIDE(pipe));
6592 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6593
6594 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6595 plane_config->tiled);
6596
6597 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6598 aligned_height);
6599
6600 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6601 pipe, plane, crtc->base.primary->fb->width,
6602 crtc->base.primary->fb->height,
6603 crtc->base.primary->fb->bits_per_pixel, base,
6604 crtc->base.primary->fb->pitches[0],
6605 plane_config->size);
6606
6607 }
6608
6609 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6610 struct intel_crtc_state *pipe_config)
6611 {
6612 struct drm_device *dev = crtc->base.dev;
6613 struct drm_i915_private *dev_priv = dev->dev_private;
6614 int pipe = pipe_config->cpu_transcoder;
6615 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6616 intel_clock_t clock;
6617 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6618 int refclk = 100000;
6619
6620 mutex_lock(&dev_priv->dpio_lock);
6621 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6622 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6623 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6624 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6625 mutex_unlock(&dev_priv->dpio_lock);
6626
6627 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6628 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6629 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6630 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6631 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6632
6633 chv_clock(refclk, &clock);
6634
6635 /* clock.dot is the fast clock */
6636 pipe_config->port_clock = clock.dot / 5;
6637 }
6638
6639 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6640 struct intel_crtc_state *pipe_config)
6641 {
6642 struct drm_device *dev = crtc->base.dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 uint32_t tmp;
6645
6646 if (!intel_display_power_is_enabled(dev_priv,
6647 POWER_DOMAIN_PIPE(crtc->pipe)))
6648 return false;
6649
6650 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6651 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6652
6653 tmp = I915_READ(PIPECONF(crtc->pipe));
6654 if (!(tmp & PIPECONF_ENABLE))
6655 return false;
6656
6657 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6658 switch (tmp & PIPECONF_BPC_MASK) {
6659 case PIPECONF_6BPC:
6660 pipe_config->pipe_bpp = 18;
6661 break;
6662 case PIPECONF_8BPC:
6663 pipe_config->pipe_bpp = 24;
6664 break;
6665 case PIPECONF_10BPC:
6666 pipe_config->pipe_bpp = 30;
6667 break;
6668 default:
6669 break;
6670 }
6671 }
6672
6673 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6674 pipe_config->limited_color_range = true;
6675
6676 if (INTEL_INFO(dev)->gen < 4)
6677 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6678
6679 intel_get_pipe_timings(crtc, pipe_config);
6680
6681 i9xx_get_pfit_config(crtc, pipe_config);
6682
6683 if (INTEL_INFO(dev)->gen >= 4) {
6684 tmp = I915_READ(DPLL_MD(crtc->pipe));
6685 pipe_config->pixel_multiplier =
6686 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6687 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6688 pipe_config->dpll_hw_state.dpll_md = tmp;
6689 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6690 tmp = I915_READ(DPLL(crtc->pipe));
6691 pipe_config->pixel_multiplier =
6692 ((tmp & SDVO_MULTIPLIER_MASK)
6693 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6694 } else {
6695 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6696 * port and will be fixed up in the encoder->get_config
6697 * function. */
6698 pipe_config->pixel_multiplier = 1;
6699 }
6700 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6701 if (!IS_VALLEYVIEW(dev)) {
6702 /*
6703 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6704 * on 830. Filter it out here so that we don't
6705 * report errors due to that.
6706 */
6707 if (IS_I830(dev))
6708 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6709
6710 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6711 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6712 } else {
6713 /* Mask out read-only status bits. */
6714 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6715 DPLL_PORTC_READY_MASK |
6716 DPLL_PORTB_READY_MASK);
6717 }
6718
6719 if (IS_CHERRYVIEW(dev))
6720 chv_crtc_clock_get(crtc, pipe_config);
6721 else if (IS_VALLEYVIEW(dev))
6722 vlv_crtc_clock_get(crtc, pipe_config);
6723 else
6724 i9xx_crtc_clock_get(crtc, pipe_config);
6725
6726 return true;
6727 }
6728
6729 static void ironlake_init_pch_refclk(struct drm_device *dev)
6730 {
6731 struct drm_i915_private *dev_priv = dev->dev_private;
6732 struct intel_encoder *encoder;
6733 u32 val, final;
6734 bool has_lvds = false;
6735 bool has_cpu_edp = false;
6736 bool has_panel = false;
6737 bool has_ck505 = false;
6738 bool can_ssc = false;
6739
6740 /* We need to take the global config into account */
6741 for_each_intel_encoder(dev, encoder) {
6742 switch (encoder->type) {
6743 case INTEL_OUTPUT_LVDS:
6744 has_panel = true;
6745 has_lvds = true;
6746 break;
6747 case INTEL_OUTPUT_EDP:
6748 has_panel = true;
6749 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6750 has_cpu_edp = true;
6751 break;
6752 default:
6753 break;
6754 }
6755 }
6756
6757 if (HAS_PCH_IBX(dev)) {
6758 has_ck505 = dev_priv->vbt.display_clock_mode;
6759 can_ssc = has_ck505;
6760 } else {
6761 has_ck505 = false;
6762 can_ssc = true;
6763 }
6764
6765 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6766 has_panel, has_lvds, has_ck505);
6767
6768 /* Ironlake: try to setup display ref clock before DPLL
6769 * enabling. This is only under driver's control after
6770 * PCH B stepping, previous chipset stepping should be
6771 * ignoring this setting.
6772 */
6773 val = I915_READ(PCH_DREF_CONTROL);
6774
6775 /* As we must carefully and slowly disable/enable each source in turn,
6776 * compute the final state we want first and check if we need to
6777 * make any changes at all.
6778 */
6779 final = val;
6780 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6781 if (has_ck505)
6782 final |= DREF_NONSPREAD_CK505_ENABLE;
6783 else
6784 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6785
6786 final &= ~DREF_SSC_SOURCE_MASK;
6787 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6788 final &= ~DREF_SSC1_ENABLE;
6789
6790 if (has_panel) {
6791 final |= DREF_SSC_SOURCE_ENABLE;
6792
6793 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6794 final |= DREF_SSC1_ENABLE;
6795
6796 if (has_cpu_edp) {
6797 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6798 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6799 else
6800 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6801 } else
6802 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6803 } else {
6804 final |= DREF_SSC_SOURCE_DISABLE;
6805 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6806 }
6807
6808 if (final == val)
6809 return;
6810
6811 /* Always enable nonspread source */
6812 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6813
6814 if (has_ck505)
6815 val |= DREF_NONSPREAD_CK505_ENABLE;
6816 else
6817 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6818
6819 if (has_panel) {
6820 val &= ~DREF_SSC_SOURCE_MASK;
6821 val |= DREF_SSC_SOURCE_ENABLE;
6822
6823 /* SSC must be turned on before enabling the CPU output */
6824 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6825 DRM_DEBUG_KMS("Using SSC on panel\n");
6826 val |= DREF_SSC1_ENABLE;
6827 } else
6828 val &= ~DREF_SSC1_ENABLE;
6829
6830 /* Get SSC going before enabling the outputs */
6831 I915_WRITE(PCH_DREF_CONTROL, val);
6832 POSTING_READ(PCH_DREF_CONTROL);
6833 udelay(200);
6834
6835 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6836
6837 /* Enable CPU source on CPU attached eDP */
6838 if (has_cpu_edp) {
6839 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6840 DRM_DEBUG_KMS("Using SSC on eDP\n");
6841 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6842 } else
6843 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6844 } else
6845 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6846
6847 I915_WRITE(PCH_DREF_CONTROL, val);
6848 POSTING_READ(PCH_DREF_CONTROL);
6849 udelay(200);
6850 } else {
6851 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6852
6853 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6854
6855 /* Turn off CPU output */
6856 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6857
6858 I915_WRITE(PCH_DREF_CONTROL, val);
6859 POSTING_READ(PCH_DREF_CONTROL);
6860 udelay(200);
6861
6862 /* Turn off the SSC source */
6863 val &= ~DREF_SSC_SOURCE_MASK;
6864 val |= DREF_SSC_SOURCE_DISABLE;
6865
6866 /* Turn off SSC1 */
6867 val &= ~DREF_SSC1_ENABLE;
6868
6869 I915_WRITE(PCH_DREF_CONTROL, val);
6870 POSTING_READ(PCH_DREF_CONTROL);
6871 udelay(200);
6872 }
6873
6874 BUG_ON(val != final);
6875 }
6876
6877 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6878 {
6879 uint32_t tmp;
6880
6881 tmp = I915_READ(SOUTH_CHICKEN2);
6882 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6883 I915_WRITE(SOUTH_CHICKEN2, tmp);
6884
6885 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6886 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6887 DRM_ERROR("FDI mPHY reset assert timeout\n");
6888
6889 tmp = I915_READ(SOUTH_CHICKEN2);
6890 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6891 I915_WRITE(SOUTH_CHICKEN2, tmp);
6892
6893 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6894 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6895 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6896 }
6897
6898 /* WaMPhyProgramming:hsw */
6899 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6900 {
6901 uint32_t tmp;
6902
6903 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6904 tmp &= ~(0xFF << 24);
6905 tmp |= (0x12 << 24);
6906 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6907
6908 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6909 tmp |= (1 << 11);
6910 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6911
6912 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6913 tmp |= (1 << 11);
6914 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6915
6916 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6917 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6918 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6919
6920 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6921 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6922 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6923
6924 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6925 tmp &= ~(7 << 13);
6926 tmp |= (5 << 13);
6927 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6928
6929 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6930 tmp &= ~(7 << 13);
6931 tmp |= (5 << 13);
6932 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6933
6934 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6935 tmp &= ~0xFF;
6936 tmp |= 0x1C;
6937 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6938
6939 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6940 tmp &= ~0xFF;
6941 tmp |= 0x1C;
6942 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6943
6944 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6945 tmp &= ~(0xFF << 16);
6946 tmp |= (0x1C << 16);
6947 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6948
6949 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6950 tmp &= ~(0xFF << 16);
6951 tmp |= (0x1C << 16);
6952 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6953
6954 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6955 tmp |= (1 << 27);
6956 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6957
6958 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6959 tmp |= (1 << 27);
6960 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6961
6962 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6963 tmp &= ~(0xF << 28);
6964 tmp |= (4 << 28);
6965 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6966
6967 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6968 tmp &= ~(0xF << 28);
6969 tmp |= (4 << 28);
6970 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6971 }
6972
6973 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6974 * Programming" based on the parameters passed:
6975 * - Sequence to enable CLKOUT_DP
6976 * - Sequence to enable CLKOUT_DP without spread
6977 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6978 */
6979 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6980 bool with_fdi)
6981 {
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983 uint32_t reg, tmp;
6984
6985 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6986 with_spread = true;
6987 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6988 with_fdi, "LP PCH doesn't have FDI\n"))
6989 with_fdi = false;
6990
6991 mutex_lock(&dev_priv->dpio_lock);
6992
6993 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6994 tmp &= ~SBI_SSCCTL_DISABLE;
6995 tmp |= SBI_SSCCTL_PATHALT;
6996 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6997
6998 udelay(24);
6999
7000 if (with_spread) {
7001 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7002 tmp &= ~SBI_SSCCTL_PATHALT;
7003 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7004
7005 if (with_fdi) {
7006 lpt_reset_fdi_mphy(dev_priv);
7007 lpt_program_fdi_mphy(dev_priv);
7008 }
7009 }
7010
7011 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7012 SBI_GEN0 : SBI_DBUFF0;
7013 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7014 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7015 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7016
7017 mutex_unlock(&dev_priv->dpio_lock);
7018 }
7019
7020 /* Sequence to disable CLKOUT_DP */
7021 static void lpt_disable_clkout_dp(struct drm_device *dev)
7022 {
7023 struct drm_i915_private *dev_priv = dev->dev_private;
7024 uint32_t reg, tmp;
7025
7026 mutex_lock(&dev_priv->dpio_lock);
7027
7028 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7029 SBI_GEN0 : SBI_DBUFF0;
7030 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7031 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7032 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7033
7034 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7035 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7036 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7037 tmp |= SBI_SSCCTL_PATHALT;
7038 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7039 udelay(32);
7040 }
7041 tmp |= SBI_SSCCTL_DISABLE;
7042 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7043 }
7044
7045 mutex_unlock(&dev_priv->dpio_lock);
7046 }
7047
7048 static void lpt_init_pch_refclk(struct drm_device *dev)
7049 {
7050 struct intel_encoder *encoder;
7051 bool has_vga = false;
7052
7053 for_each_intel_encoder(dev, encoder) {
7054 switch (encoder->type) {
7055 case INTEL_OUTPUT_ANALOG:
7056 has_vga = true;
7057 break;
7058 default:
7059 break;
7060 }
7061 }
7062
7063 if (has_vga)
7064 lpt_enable_clkout_dp(dev, true, true);
7065 else
7066 lpt_disable_clkout_dp(dev);
7067 }
7068
7069 /*
7070 * Initialize reference clocks when the driver loads
7071 */
7072 void intel_init_pch_refclk(struct drm_device *dev)
7073 {
7074 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7075 ironlake_init_pch_refclk(dev);
7076 else if (HAS_PCH_LPT(dev))
7077 lpt_init_pch_refclk(dev);
7078 }
7079
7080 static int ironlake_get_refclk(struct drm_crtc *crtc)
7081 {
7082 struct drm_device *dev = crtc->dev;
7083 struct drm_i915_private *dev_priv = dev->dev_private;
7084 struct intel_encoder *encoder;
7085 int num_connectors = 0;
7086 bool is_lvds = false;
7087
7088 for_each_intel_encoder(dev, encoder) {
7089 if (encoder->new_crtc != to_intel_crtc(crtc))
7090 continue;
7091
7092 switch (encoder->type) {
7093 case INTEL_OUTPUT_LVDS:
7094 is_lvds = true;
7095 break;
7096 default:
7097 break;
7098 }
7099 num_connectors++;
7100 }
7101
7102 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7103 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7104 dev_priv->vbt.lvds_ssc_freq);
7105 return dev_priv->vbt.lvds_ssc_freq;
7106 }
7107
7108 return 120000;
7109 }
7110
7111 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7112 {
7113 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7115 int pipe = intel_crtc->pipe;
7116 uint32_t val;
7117
7118 val = 0;
7119
7120 switch (intel_crtc->config->pipe_bpp) {
7121 case 18:
7122 val |= PIPECONF_6BPC;
7123 break;
7124 case 24:
7125 val |= PIPECONF_8BPC;
7126 break;
7127 case 30:
7128 val |= PIPECONF_10BPC;
7129 break;
7130 case 36:
7131 val |= PIPECONF_12BPC;
7132 break;
7133 default:
7134 /* Case prevented by intel_choose_pipe_bpp_dither. */
7135 BUG();
7136 }
7137
7138 if (intel_crtc->config->dither)
7139 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7140
7141 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7142 val |= PIPECONF_INTERLACED_ILK;
7143 else
7144 val |= PIPECONF_PROGRESSIVE;
7145
7146 if (intel_crtc->config->limited_color_range)
7147 val |= PIPECONF_COLOR_RANGE_SELECT;
7148
7149 I915_WRITE(PIPECONF(pipe), val);
7150 POSTING_READ(PIPECONF(pipe));
7151 }
7152
7153 /*
7154 * Set up the pipe CSC unit.
7155 *
7156 * Currently only full range RGB to limited range RGB conversion
7157 * is supported, but eventually this should handle various
7158 * RGB<->YCbCr scenarios as well.
7159 */
7160 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7161 {
7162 struct drm_device *dev = crtc->dev;
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7165 int pipe = intel_crtc->pipe;
7166 uint16_t coeff = 0x7800; /* 1.0 */
7167
7168 /*
7169 * TODO: Check what kind of values actually come out of the pipe
7170 * with these coeff/postoff values and adjust to get the best
7171 * accuracy. Perhaps we even need to take the bpc value into
7172 * consideration.
7173 */
7174
7175 if (intel_crtc->config->limited_color_range)
7176 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7177
7178 /*
7179 * GY/GU and RY/RU should be the other way around according
7180 * to BSpec, but reality doesn't agree. Just set them up in
7181 * a way that results in the correct picture.
7182 */
7183 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7184 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7185
7186 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7187 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7188
7189 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7190 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7191
7192 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7193 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7194 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7195
7196 if (INTEL_INFO(dev)->gen > 6) {
7197 uint16_t postoff = 0;
7198
7199 if (intel_crtc->config->limited_color_range)
7200 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7201
7202 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7203 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7204 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7205
7206 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7207 } else {
7208 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7209
7210 if (intel_crtc->config->limited_color_range)
7211 mode |= CSC_BLACK_SCREEN_OFFSET;
7212
7213 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7214 }
7215 }
7216
7217 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7218 {
7219 struct drm_device *dev = crtc->dev;
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7222 enum pipe pipe = intel_crtc->pipe;
7223 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7224 uint32_t val;
7225
7226 val = 0;
7227
7228 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7229 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7230
7231 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7232 val |= PIPECONF_INTERLACED_ILK;
7233 else
7234 val |= PIPECONF_PROGRESSIVE;
7235
7236 I915_WRITE(PIPECONF(cpu_transcoder), val);
7237 POSTING_READ(PIPECONF(cpu_transcoder));
7238
7239 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7240 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7241
7242 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7243 val = 0;
7244
7245 switch (intel_crtc->config->pipe_bpp) {
7246 case 18:
7247 val |= PIPEMISC_DITHER_6_BPC;
7248 break;
7249 case 24:
7250 val |= PIPEMISC_DITHER_8_BPC;
7251 break;
7252 case 30:
7253 val |= PIPEMISC_DITHER_10_BPC;
7254 break;
7255 case 36:
7256 val |= PIPEMISC_DITHER_12_BPC;
7257 break;
7258 default:
7259 /* Case prevented by pipe_config_set_bpp. */
7260 BUG();
7261 }
7262
7263 if (intel_crtc->config->dither)
7264 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7265
7266 I915_WRITE(PIPEMISC(pipe), val);
7267 }
7268 }
7269
7270 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7271 struct intel_crtc_state *crtc_state,
7272 intel_clock_t *clock,
7273 bool *has_reduced_clock,
7274 intel_clock_t *reduced_clock)
7275 {
7276 struct drm_device *dev = crtc->dev;
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7279 int refclk;
7280 const intel_limit_t *limit;
7281 bool ret, is_lvds = false;
7282
7283 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7284
7285 refclk = ironlake_get_refclk(crtc);
7286
7287 /*
7288 * Returns a set of divisors for the desired target clock with the given
7289 * refclk, or FALSE. The returned values represent the clock equation:
7290 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7291 */
7292 limit = intel_limit(intel_crtc, refclk);
7293 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7294 crtc_state->port_clock,
7295 refclk, NULL, clock);
7296 if (!ret)
7297 return false;
7298
7299 if (is_lvds && dev_priv->lvds_downclock_avail) {
7300 /*
7301 * Ensure we match the reduced clock's P to the target clock.
7302 * If the clocks don't match, we can't switch the display clock
7303 * by using the FP0/FP1. In such case we will disable the LVDS
7304 * downclock feature.
7305 */
7306 *has_reduced_clock =
7307 dev_priv->display.find_dpll(limit, intel_crtc,
7308 dev_priv->lvds_downclock,
7309 refclk, clock,
7310 reduced_clock);
7311 }
7312
7313 return true;
7314 }
7315
7316 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7317 {
7318 /*
7319 * Account for spread spectrum to avoid
7320 * oversubscribing the link. Max center spread
7321 * is 2.5%; use 5% for safety's sake.
7322 */
7323 u32 bps = target_clock * bpp * 21 / 20;
7324 return DIV_ROUND_UP(bps, link_bw * 8);
7325 }
7326
7327 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7328 {
7329 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7330 }
7331
7332 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7333 struct intel_crtc_state *crtc_state,
7334 u32 *fp,
7335 intel_clock_t *reduced_clock, u32 *fp2)
7336 {
7337 struct drm_crtc *crtc = &intel_crtc->base;
7338 struct drm_device *dev = crtc->dev;
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340 struct intel_encoder *intel_encoder;
7341 uint32_t dpll;
7342 int factor, num_connectors = 0;
7343 bool is_lvds = false, is_sdvo = false;
7344
7345 for_each_intel_encoder(dev, intel_encoder) {
7346 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7347 continue;
7348
7349 switch (intel_encoder->type) {
7350 case INTEL_OUTPUT_LVDS:
7351 is_lvds = true;
7352 break;
7353 case INTEL_OUTPUT_SDVO:
7354 case INTEL_OUTPUT_HDMI:
7355 is_sdvo = true;
7356 break;
7357 default:
7358 break;
7359 }
7360
7361 num_connectors++;
7362 }
7363
7364 /* Enable autotuning of the PLL clock (if permissible) */
7365 factor = 21;
7366 if (is_lvds) {
7367 if ((intel_panel_use_ssc(dev_priv) &&
7368 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7369 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7370 factor = 25;
7371 } else if (crtc_state->sdvo_tv_clock)
7372 factor = 20;
7373
7374 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7375 *fp |= FP_CB_TUNE;
7376
7377 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7378 *fp2 |= FP_CB_TUNE;
7379
7380 dpll = 0;
7381
7382 if (is_lvds)
7383 dpll |= DPLLB_MODE_LVDS;
7384 else
7385 dpll |= DPLLB_MODE_DAC_SERIAL;
7386
7387 dpll |= (crtc_state->pixel_multiplier - 1)
7388 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7389
7390 if (is_sdvo)
7391 dpll |= DPLL_SDVO_HIGH_SPEED;
7392 if (crtc_state->has_dp_encoder)
7393 dpll |= DPLL_SDVO_HIGH_SPEED;
7394
7395 /* compute bitmask from p1 value */
7396 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7397 /* also FPA1 */
7398 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7399
7400 switch (crtc_state->dpll.p2) {
7401 case 5:
7402 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7403 break;
7404 case 7:
7405 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7406 break;
7407 case 10:
7408 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7409 break;
7410 case 14:
7411 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7412 break;
7413 }
7414
7415 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7416 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7417 else
7418 dpll |= PLL_REF_INPUT_DREFCLK;
7419
7420 return dpll | DPLL_VCO_ENABLE;
7421 }
7422
7423 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7424 struct intel_crtc_state *crtc_state)
7425 {
7426 struct drm_device *dev = crtc->base.dev;
7427 intel_clock_t clock, reduced_clock;
7428 u32 dpll = 0, fp = 0, fp2 = 0;
7429 bool ok, has_reduced_clock = false;
7430 bool is_lvds = false;
7431 struct intel_shared_dpll *pll;
7432
7433 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7434
7435 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7436 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7437
7438 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7439 &has_reduced_clock, &reduced_clock);
7440 if (!ok && !crtc_state->clock_set) {
7441 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7442 return -EINVAL;
7443 }
7444 /* Compat-code for transition, will disappear. */
7445 if (!crtc_state->clock_set) {
7446 crtc_state->dpll.n = clock.n;
7447 crtc_state->dpll.m1 = clock.m1;
7448 crtc_state->dpll.m2 = clock.m2;
7449 crtc_state->dpll.p1 = clock.p1;
7450 crtc_state->dpll.p2 = clock.p2;
7451 }
7452
7453 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7454 if (crtc_state->has_pch_encoder) {
7455 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7456 if (has_reduced_clock)
7457 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7458
7459 dpll = ironlake_compute_dpll(crtc, crtc_state,
7460 &fp, &reduced_clock,
7461 has_reduced_clock ? &fp2 : NULL);
7462
7463 crtc_state->dpll_hw_state.dpll = dpll;
7464 crtc_state->dpll_hw_state.fp0 = fp;
7465 if (has_reduced_clock)
7466 crtc_state->dpll_hw_state.fp1 = fp2;
7467 else
7468 crtc_state->dpll_hw_state.fp1 = fp;
7469
7470 pll = intel_get_shared_dpll(crtc, crtc_state);
7471 if (pll == NULL) {
7472 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7473 pipe_name(crtc->pipe));
7474 return -EINVAL;
7475 }
7476 }
7477
7478 if (is_lvds && has_reduced_clock && i915.powersave)
7479 crtc->lowfreq_avail = true;
7480 else
7481 crtc->lowfreq_avail = false;
7482
7483 return 0;
7484 }
7485
7486 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7487 struct intel_link_m_n *m_n)
7488 {
7489 struct drm_device *dev = crtc->base.dev;
7490 struct drm_i915_private *dev_priv = dev->dev_private;
7491 enum pipe pipe = crtc->pipe;
7492
7493 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7494 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7495 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7496 & ~TU_SIZE_MASK;
7497 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7498 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7499 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7500 }
7501
7502 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7503 enum transcoder transcoder,
7504 struct intel_link_m_n *m_n,
7505 struct intel_link_m_n *m2_n2)
7506 {
7507 struct drm_device *dev = crtc->base.dev;
7508 struct drm_i915_private *dev_priv = dev->dev_private;
7509 enum pipe pipe = crtc->pipe;
7510
7511 if (INTEL_INFO(dev)->gen >= 5) {
7512 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7513 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7514 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7515 & ~TU_SIZE_MASK;
7516 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7517 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7518 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7519 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7520 * gen < 8) and if DRRS is supported (to make sure the
7521 * registers are not unnecessarily read).
7522 */
7523 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7524 crtc->config->has_drrs) {
7525 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7526 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7527 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7528 & ~TU_SIZE_MASK;
7529 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7530 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7531 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7532 }
7533 } else {
7534 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7535 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7536 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7537 & ~TU_SIZE_MASK;
7538 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7539 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7540 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7541 }
7542 }
7543
7544 void intel_dp_get_m_n(struct intel_crtc *crtc,
7545 struct intel_crtc_state *pipe_config)
7546 {
7547 if (pipe_config->has_pch_encoder)
7548 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7549 else
7550 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7551 &pipe_config->dp_m_n,
7552 &pipe_config->dp_m2_n2);
7553 }
7554
7555 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7556 struct intel_crtc_state *pipe_config)
7557 {
7558 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7559 &pipe_config->fdi_m_n, NULL);
7560 }
7561
7562 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7563 struct intel_crtc_state *pipe_config)
7564 {
7565 struct drm_device *dev = crtc->base.dev;
7566 struct drm_i915_private *dev_priv = dev->dev_private;
7567 uint32_t tmp;
7568
7569 tmp = I915_READ(PS_CTL(crtc->pipe));
7570
7571 if (tmp & PS_ENABLE) {
7572 pipe_config->pch_pfit.enabled = true;
7573 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7574 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7575 }
7576 }
7577
7578 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7579 struct intel_crtc_state *pipe_config)
7580 {
7581 struct drm_device *dev = crtc->base.dev;
7582 struct drm_i915_private *dev_priv = dev->dev_private;
7583 uint32_t tmp;
7584
7585 tmp = I915_READ(PF_CTL(crtc->pipe));
7586
7587 if (tmp & PF_ENABLE) {
7588 pipe_config->pch_pfit.enabled = true;
7589 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7590 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7591
7592 /* We currently do not free assignements of panel fitters on
7593 * ivb/hsw (since we don't use the higher upscaling modes which
7594 * differentiates them) so just WARN about this case for now. */
7595 if (IS_GEN7(dev)) {
7596 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7597 PF_PIPE_SEL_IVB(crtc->pipe));
7598 }
7599 }
7600 }
7601
7602 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7603 struct intel_plane_config *plane_config)
7604 {
7605 struct drm_device *dev = crtc->base.dev;
7606 struct drm_i915_private *dev_priv = dev->dev_private;
7607 u32 val, base, offset;
7608 int pipe = crtc->pipe, plane = crtc->plane;
7609 int fourcc, pixel_format;
7610 int aligned_height;
7611
7612 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7613 if (!crtc->base.primary->fb) {
7614 DRM_DEBUG_KMS("failed to alloc fb\n");
7615 return;
7616 }
7617
7618 val = I915_READ(DSPCNTR(plane));
7619
7620 if (INTEL_INFO(dev)->gen >= 4)
7621 if (val & DISPPLANE_TILED)
7622 plane_config->tiled = true;
7623
7624 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7625 fourcc = intel_format_to_fourcc(pixel_format);
7626 crtc->base.primary->fb->pixel_format = fourcc;
7627 crtc->base.primary->fb->bits_per_pixel =
7628 drm_format_plane_cpp(fourcc, 0) * 8;
7629
7630 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7631 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7632 offset = I915_READ(DSPOFFSET(plane));
7633 } else {
7634 if (plane_config->tiled)
7635 offset = I915_READ(DSPTILEOFF(plane));
7636 else
7637 offset = I915_READ(DSPLINOFF(plane));
7638 }
7639 plane_config->base = base;
7640
7641 val = I915_READ(PIPESRC(pipe));
7642 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7643 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7644
7645 val = I915_READ(DSPSTRIDE(pipe));
7646 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7647
7648 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7649 plane_config->tiled);
7650
7651 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7652 aligned_height);
7653
7654 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7655 pipe, plane, crtc->base.primary->fb->width,
7656 crtc->base.primary->fb->height,
7657 crtc->base.primary->fb->bits_per_pixel, base,
7658 crtc->base.primary->fb->pitches[0],
7659 plane_config->size);
7660 }
7661
7662 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7663 struct intel_crtc_state *pipe_config)
7664 {
7665 struct drm_device *dev = crtc->base.dev;
7666 struct drm_i915_private *dev_priv = dev->dev_private;
7667 uint32_t tmp;
7668
7669 if (!intel_display_power_is_enabled(dev_priv,
7670 POWER_DOMAIN_PIPE(crtc->pipe)))
7671 return false;
7672
7673 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7674 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7675
7676 tmp = I915_READ(PIPECONF(crtc->pipe));
7677 if (!(tmp & PIPECONF_ENABLE))
7678 return false;
7679
7680 switch (tmp & PIPECONF_BPC_MASK) {
7681 case PIPECONF_6BPC:
7682 pipe_config->pipe_bpp = 18;
7683 break;
7684 case PIPECONF_8BPC:
7685 pipe_config->pipe_bpp = 24;
7686 break;
7687 case PIPECONF_10BPC:
7688 pipe_config->pipe_bpp = 30;
7689 break;
7690 case PIPECONF_12BPC:
7691 pipe_config->pipe_bpp = 36;
7692 break;
7693 default:
7694 break;
7695 }
7696
7697 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7698 pipe_config->limited_color_range = true;
7699
7700 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7701 struct intel_shared_dpll *pll;
7702
7703 pipe_config->has_pch_encoder = true;
7704
7705 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7706 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7707 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7708
7709 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7710
7711 if (HAS_PCH_IBX(dev_priv->dev)) {
7712 pipe_config->shared_dpll =
7713 (enum intel_dpll_id) crtc->pipe;
7714 } else {
7715 tmp = I915_READ(PCH_DPLL_SEL);
7716 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7717 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7718 else
7719 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7720 }
7721
7722 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7723
7724 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7725 &pipe_config->dpll_hw_state));
7726
7727 tmp = pipe_config->dpll_hw_state.dpll;
7728 pipe_config->pixel_multiplier =
7729 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7730 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7731
7732 ironlake_pch_clock_get(crtc, pipe_config);
7733 } else {
7734 pipe_config->pixel_multiplier = 1;
7735 }
7736
7737 intel_get_pipe_timings(crtc, pipe_config);
7738
7739 ironlake_get_pfit_config(crtc, pipe_config);
7740
7741 return true;
7742 }
7743
7744 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7745 {
7746 struct drm_device *dev = dev_priv->dev;
7747 struct intel_crtc *crtc;
7748
7749 for_each_intel_crtc(dev, crtc)
7750 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7751 pipe_name(crtc->pipe));
7752
7753 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7754 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7755 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7756 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7757 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7758 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7759 "CPU PWM1 enabled\n");
7760 if (IS_HASWELL(dev))
7761 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7762 "CPU PWM2 enabled\n");
7763 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7764 "PCH PWM1 enabled\n");
7765 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7766 "Utility pin enabled\n");
7767 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7768
7769 /*
7770 * In theory we can still leave IRQs enabled, as long as only the HPD
7771 * interrupts remain enabled. We used to check for that, but since it's
7772 * gen-specific and since we only disable LCPLL after we fully disable
7773 * the interrupts, the check below should be enough.
7774 */
7775 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7776 }
7777
7778 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7779 {
7780 struct drm_device *dev = dev_priv->dev;
7781
7782 if (IS_HASWELL(dev))
7783 return I915_READ(D_COMP_HSW);
7784 else
7785 return I915_READ(D_COMP_BDW);
7786 }
7787
7788 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7789 {
7790 struct drm_device *dev = dev_priv->dev;
7791
7792 if (IS_HASWELL(dev)) {
7793 mutex_lock(&dev_priv->rps.hw_lock);
7794 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7795 val))
7796 DRM_ERROR("Failed to write to D_COMP\n");
7797 mutex_unlock(&dev_priv->rps.hw_lock);
7798 } else {
7799 I915_WRITE(D_COMP_BDW, val);
7800 POSTING_READ(D_COMP_BDW);
7801 }
7802 }
7803
7804 /*
7805 * This function implements pieces of two sequences from BSpec:
7806 * - Sequence for display software to disable LCPLL
7807 * - Sequence for display software to allow package C8+
7808 * The steps implemented here are just the steps that actually touch the LCPLL
7809 * register. Callers should take care of disabling all the display engine
7810 * functions, doing the mode unset, fixing interrupts, etc.
7811 */
7812 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7813 bool switch_to_fclk, bool allow_power_down)
7814 {
7815 uint32_t val;
7816
7817 assert_can_disable_lcpll(dev_priv);
7818
7819 val = I915_READ(LCPLL_CTL);
7820
7821 if (switch_to_fclk) {
7822 val |= LCPLL_CD_SOURCE_FCLK;
7823 I915_WRITE(LCPLL_CTL, val);
7824
7825 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7826 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7827 DRM_ERROR("Switching to FCLK failed\n");
7828
7829 val = I915_READ(LCPLL_CTL);
7830 }
7831
7832 val |= LCPLL_PLL_DISABLE;
7833 I915_WRITE(LCPLL_CTL, val);
7834 POSTING_READ(LCPLL_CTL);
7835
7836 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7837 DRM_ERROR("LCPLL still locked\n");
7838
7839 val = hsw_read_dcomp(dev_priv);
7840 val |= D_COMP_COMP_DISABLE;
7841 hsw_write_dcomp(dev_priv, val);
7842 ndelay(100);
7843
7844 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7845 1))
7846 DRM_ERROR("D_COMP RCOMP still in progress\n");
7847
7848 if (allow_power_down) {
7849 val = I915_READ(LCPLL_CTL);
7850 val |= LCPLL_POWER_DOWN_ALLOW;
7851 I915_WRITE(LCPLL_CTL, val);
7852 POSTING_READ(LCPLL_CTL);
7853 }
7854 }
7855
7856 /*
7857 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7858 * source.
7859 */
7860 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7861 {
7862 uint32_t val;
7863
7864 val = I915_READ(LCPLL_CTL);
7865
7866 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7867 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7868 return;
7869
7870 /*
7871 * Make sure we're not on PC8 state before disabling PC8, otherwise
7872 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7873 */
7874 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
7875
7876 if (val & LCPLL_POWER_DOWN_ALLOW) {
7877 val &= ~LCPLL_POWER_DOWN_ALLOW;
7878 I915_WRITE(LCPLL_CTL, val);
7879 POSTING_READ(LCPLL_CTL);
7880 }
7881
7882 val = hsw_read_dcomp(dev_priv);
7883 val |= D_COMP_COMP_FORCE;
7884 val &= ~D_COMP_COMP_DISABLE;
7885 hsw_write_dcomp(dev_priv, val);
7886
7887 val = I915_READ(LCPLL_CTL);
7888 val &= ~LCPLL_PLL_DISABLE;
7889 I915_WRITE(LCPLL_CTL, val);
7890
7891 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7892 DRM_ERROR("LCPLL not locked yet\n");
7893
7894 if (val & LCPLL_CD_SOURCE_FCLK) {
7895 val = I915_READ(LCPLL_CTL);
7896 val &= ~LCPLL_CD_SOURCE_FCLK;
7897 I915_WRITE(LCPLL_CTL, val);
7898
7899 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7900 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7901 DRM_ERROR("Switching back to LCPLL failed\n");
7902 }
7903
7904 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
7905 }
7906
7907 /*
7908 * Package states C8 and deeper are really deep PC states that can only be
7909 * reached when all the devices on the system allow it, so even if the graphics
7910 * device allows PC8+, it doesn't mean the system will actually get to these
7911 * states. Our driver only allows PC8+ when going into runtime PM.
7912 *
7913 * The requirements for PC8+ are that all the outputs are disabled, the power
7914 * well is disabled and most interrupts are disabled, and these are also
7915 * requirements for runtime PM. When these conditions are met, we manually do
7916 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7917 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7918 * hang the machine.
7919 *
7920 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7921 * the state of some registers, so when we come back from PC8+ we need to
7922 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7923 * need to take care of the registers kept by RC6. Notice that this happens even
7924 * if we don't put the device in PCI D3 state (which is what currently happens
7925 * because of the runtime PM support).
7926 *
7927 * For more, read "Display Sequences for Package C8" on the hardware
7928 * documentation.
7929 */
7930 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7931 {
7932 struct drm_device *dev = dev_priv->dev;
7933 uint32_t val;
7934
7935 DRM_DEBUG_KMS("Enabling package C8+\n");
7936
7937 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7938 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7939 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7940 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7941 }
7942
7943 lpt_disable_clkout_dp(dev);
7944 hsw_disable_lcpll(dev_priv, true, true);
7945 }
7946
7947 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7948 {
7949 struct drm_device *dev = dev_priv->dev;
7950 uint32_t val;
7951
7952 DRM_DEBUG_KMS("Disabling package C8+\n");
7953
7954 hsw_restore_lcpll(dev_priv);
7955 lpt_init_pch_refclk(dev);
7956
7957 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7958 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7959 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7960 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7961 }
7962
7963 intel_prepare_ddi(dev);
7964 }
7965
7966 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
7967 struct intel_crtc_state *crtc_state)
7968 {
7969 if (!intel_ddi_pll_select(crtc, crtc_state))
7970 return -EINVAL;
7971
7972 crtc->lowfreq_avail = false;
7973
7974 return 0;
7975 }
7976
7977 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7978 enum port port,
7979 struct intel_crtc_state *pipe_config)
7980 {
7981 u32 temp, dpll_ctl1;
7982
7983 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
7984 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
7985
7986 switch (pipe_config->ddi_pll_sel) {
7987 case SKL_DPLL0:
7988 /*
7989 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
7990 * of the shared DPLL framework and thus needs to be read out
7991 * separately
7992 */
7993 dpll_ctl1 = I915_READ(DPLL_CTRL1);
7994 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
7995 break;
7996 case SKL_DPLL1:
7997 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
7998 break;
7999 case SKL_DPLL2:
8000 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8001 break;
8002 case SKL_DPLL3:
8003 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8004 break;
8005 }
8006 }
8007
8008 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8009 enum port port,
8010 struct intel_crtc_state *pipe_config)
8011 {
8012 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8013
8014 switch (pipe_config->ddi_pll_sel) {
8015 case PORT_CLK_SEL_WRPLL1:
8016 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8017 break;
8018 case PORT_CLK_SEL_WRPLL2:
8019 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8020 break;
8021 }
8022 }
8023
8024 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8025 struct intel_crtc_state *pipe_config)
8026 {
8027 struct drm_device *dev = crtc->base.dev;
8028 struct drm_i915_private *dev_priv = dev->dev_private;
8029 struct intel_shared_dpll *pll;
8030 enum port port;
8031 uint32_t tmp;
8032
8033 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8034
8035 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8036
8037 if (IS_SKYLAKE(dev))
8038 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8039 else
8040 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8041
8042 if (pipe_config->shared_dpll >= 0) {
8043 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8044
8045 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8046 &pipe_config->dpll_hw_state));
8047 }
8048
8049 /*
8050 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8051 * DDI E. So just check whether this pipe is wired to DDI E and whether
8052 * the PCH transcoder is on.
8053 */
8054 if (INTEL_INFO(dev)->gen < 9 &&
8055 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8056 pipe_config->has_pch_encoder = true;
8057
8058 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8059 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8060 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8061
8062 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8063 }
8064 }
8065
8066 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8067 struct intel_crtc_state *pipe_config)
8068 {
8069 struct drm_device *dev = crtc->base.dev;
8070 struct drm_i915_private *dev_priv = dev->dev_private;
8071 enum intel_display_power_domain pfit_domain;
8072 uint32_t tmp;
8073
8074 if (!intel_display_power_is_enabled(dev_priv,
8075 POWER_DOMAIN_PIPE(crtc->pipe)))
8076 return false;
8077
8078 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8079 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8080
8081 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8082 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8083 enum pipe trans_edp_pipe;
8084 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8085 default:
8086 WARN(1, "unknown pipe linked to edp transcoder\n");
8087 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8088 case TRANS_DDI_EDP_INPUT_A_ON:
8089 trans_edp_pipe = PIPE_A;
8090 break;
8091 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8092 trans_edp_pipe = PIPE_B;
8093 break;
8094 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8095 trans_edp_pipe = PIPE_C;
8096 break;
8097 }
8098
8099 if (trans_edp_pipe == crtc->pipe)
8100 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8101 }
8102
8103 if (!intel_display_power_is_enabled(dev_priv,
8104 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8105 return false;
8106
8107 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8108 if (!(tmp & PIPECONF_ENABLE))
8109 return false;
8110
8111 haswell_get_ddi_port_state(crtc, pipe_config);
8112
8113 intel_get_pipe_timings(crtc, pipe_config);
8114
8115 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8116 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8117 if (IS_SKYLAKE(dev))
8118 skylake_get_pfit_config(crtc, pipe_config);
8119 else
8120 ironlake_get_pfit_config(crtc, pipe_config);
8121 }
8122
8123 if (IS_HASWELL(dev))
8124 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8125 (I915_READ(IPS_CTL) & IPS_ENABLE);
8126
8127 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8128 pipe_config->pixel_multiplier =
8129 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8130 } else {
8131 pipe_config->pixel_multiplier = 1;
8132 }
8133
8134 return true;
8135 }
8136
8137 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8138 {
8139 struct drm_device *dev = crtc->dev;
8140 struct drm_i915_private *dev_priv = dev->dev_private;
8141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8142 uint32_t cntl = 0, size = 0;
8143
8144 if (base) {
8145 unsigned int width = intel_crtc->cursor_width;
8146 unsigned int height = intel_crtc->cursor_height;
8147 unsigned int stride = roundup_pow_of_two(width) * 4;
8148
8149 switch (stride) {
8150 default:
8151 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8152 width, stride);
8153 stride = 256;
8154 /* fallthrough */
8155 case 256:
8156 case 512:
8157 case 1024:
8158 case 2048:
8159 break;
8160 }
8161
8162 cntl |= CURSOR_ENABLE |
8163 CURSOR_GAMMA_ENABLE |
8164 CURSOR_FORMAT_ARGB |
8165 CURSOR_STRIDE(stride);
8166
8167 size = (height << 12) | width;
8168 }
8169
8170 if (intel_crtc->cursor_cntl != 0 &&
8171 (intel_crtc->cursor_base != base ||
8172 intel_crtc->cursor_size != size ||
8173 intel_crtc->cursor_cntl != cntl)) {
8174 /* On these chipsets we can only modify the base/size/stride
8175 * whilst the cursor is disabled.
8176 */
8177 I915_WRITE(_CURACNTR, 0);
8178 POSTING_READ(_CURACNTR);
8179 intel_crtc->cursor_cntl = 0;
8180 }
8181
8182 if (intel_crtc->cursor_base != base) {
8183 I915_WRITE(_CURABASE, base);
8184 intel_crtc->cursor_base = base;
8185 }
8186
8187 if (intel_crtc->cursor_size != size) {
8188 I915_WRITE(CURSIZE, size);
8189 intel_crtc->cursor_size = size;
8190 }
8191
8192 if (intel_crtc->cursor_cntl != cntl) {
8193 I915_WRITE(_CURACNTR, cntl);
8194 POSTING_READ(_CURACNTR);
8195 intel_crtc->cursor_cntl = cntl;
8196 }
8197 }
8198
8199 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8200 {
8201 struct drm_device *dev = crtc->dev;
8202 struct drm_i915_private *dev_priv = dev->dev_private;
8203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8204 int pipe = intel_crtc->pipe;
8205 uint32_t cntl;
8206
8207 cntl = 0;
8208 if (base) {
8209 cntl = MCURSOR_GAMMA_ENABLE;
8210 switch (intel_crtc->cursor_width) {
8211 case 64:
8212 cntl |= CURSOR_MODE_64_ARGB_AX;
8213 break;
8214 case 128:
8215 cntl |= CURSOR_MODE_128_ARGB_AX;
8216 break;
8217 case 256:
8218 cntl |= CURSOR_MODE_256_ARGB_AX;
8219 break;
8220 default:
8221 MISSING_CASE(intel_crtc->cursor_width);
8222 return;
8223 }
8224 cntl |= pipe << 28; /* Connect to correct pipe */
8225
8226 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8227 cntl |= CURSOR_PIPE_CSC_ENABLE;
8228 }
8229
8230 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8231 cntl |= CURSOR_ROTATE_180;
8232
8233 if (intel_crtc->cursor_cntl != cntl) {
8234 I915_WRITE(CURCNTR(pipe), cntl);
8235 POSTING_READ(CURCNTR(pipe));
8236 intel_crtc->cursor_cntl = cntl;
8237 }
8238
8239 /* and commit changes on next vblank */
8240 I915_WRITE(CURBASE(pipe), base);
8241 POSTING_READ(CURBASE(pipe));
8242
8243 intel_crtc->cursor_base = base;
8244 }
8245
8246 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8247 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8248 bool on)
8249 {
8250 struct drm_device *dev = crtc->dev;
8251 struct drm_i915_private *dev_priv = dev->dev_private;
8252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8253 int pipe = intel_crtc->pipe;
8254 int x = crtc->cursor_x;
8255 int y = crtc->cursor_y;
8256 u32 base = 0, pos = 0;
8257
8258 if (on)
8259 base = intel_crtc->cursor_addr;
8260
8261 if (x >= intel_crtc->config->pipe_src_w)
8262 base = 0;
8263
8264 if (y >= intel_crtc->config->pipe_src_h)
8265 base = 0;
8266
8267 if (x < 0) {
8268 if (x + intel_crtc->cursor_width <= 0)
8269 base = 0;
8270
8271 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8272 x = -x;
8273 }
8274 pos |= x << CURSOR_X_SHIFT;
8275
8276 if (y < 0) {
8277 if (y + intel_crtc->cursor_height <= 0)
8278 base = 0;
8279
8280 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8281 y = -y;
8282 }
8283 pos |= y << CURSOR_Y_SHIFT;
8284
8285 if (base == 0 && intel_crtc->cursor_base == 0)
8286 return;
8287
8288 I915_WRITE(CURPOS(pipe), pos);
8289
8290 /* ILK+ do this automagically */
8291 if (HAS_GMCH_DISPLAY(dev) &&
8292 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8293 base += (intel_crtc->cursor_height *
8294 intel_crtc->cursor_width - 1) * 4;
8295 }
8296
8297 if (IS_845G(dev) || IS_I865G(dev))
8298 i845_update_cursor(crtc, base);
8299 else
8300 i9xx_update_cursor(crtc, base);
8301 }
8302
8303 static bool cursor_size_ok(struct drm_device *dev,
8304 uint32_t width, uint32_t height)
8305 {
8306 if (width == 0 || height == 0)
8307 return false;
8308
8309 /*
8310 * 845g/865g are special in that they are only limited by
8311 * the width of their cursors, the height is arbitrary up to
8312 * the precision of the register. Everything else requires
8313 * square cursors, limited to a few power-of-two sizes.
8314 */
8315 if (IS_845G(dev) || IS_I865G(dev)) {
8316 if ((width & 63) != 0)
8317 return false;
8318
8319 if (width > (IS_845G(dev) ? 64 : 512))
8320 return false;
8321
8322 if (height > 1023)
8323 return false;
8324 } else {
8325 switch (width | height) {
8326 case 256:
8327 case 128:
8328 if (IS_GEN2(dev))
8329 return false;
8330 case 64:
8331 break;
8332 default:
8333 return false;
8334 }
8335 }
8336
8337 return true;
8338 }
8339
8340 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8341 u16 *blue, uint32_t start, uint32_t size)
8342 {
8343 int end = (start + size > 256) ? 256 : start + size, i;
8344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8345
8346 for (i = start; i < end; i++) {
8347 intel_crtc->lut_r[i] = red[i] >> 8;
8348 intel_crtc->lut_g[i] = green[i] >> 8;
8349 intel_crtc->lut_b[i] = blue[i] >> 8;
8350 }
8351
8352 intel_crtc_load_lut(crtc);
8353 }
8354
8355 /* VESA 640x480x72Hz mode to set on the pipe */
8356 static struct drm_display_mode load_detect_mode = {
8357 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8358 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8359 };
8360
8361 struct drm_framebuffer *
8362 __intel_framebuffer_create(struct drm_device *dev,
8363 struct drm_mode_fb_cmd2 *mode_cmd,
8364 struct drm_i915_gem_object *obj)
8365 {
8366 struct intel_framebuffer *intel_fb;
8367 int ret;
8368
8369 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8370 if (!intel_fb) {
8371 drm_gem_object_unreference(&obj->base);
8372 return ERR_PTR(-ENOMEM);
8373 }
8374
8375 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8376 if (ret)
8377 goto err;
8378
8379 return &intel_fb->base;
8380 err:
8381 drm_gem_object_unreference(&obj->base);
8382 kfree(intel_fb);
8383
8384 return ERR_PTR(ret);
8385 }
8386
8387 static struct drm_framebuffer *
8388 intel_framebuffer_create(struct drm_device *dev,
8389 struct drm_mode_fb_cmd2 *mode_cmd,
8390 struct drm_i915_gem_object *obj)
8391 {
8392 struct drm_framebuffer *fb;
8393 int ret;
8394
8395 ret = i915_mutex_lock_interruptible(dev);
8396 if (ret)
8397 return ERR_PTR(ret);
8398 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8399 mutex_unlock(&dev->struct_mutex);
8400
8401 return fb;
8402 }
8403
8404 static u32
8405 intel_framebuffer_pitch_for_width(int width, int bpp)
8406 {
8407 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8408 return ALIGN(pitch, 64);
8409 }
8410
8411 static u32
8412 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8413 {
8414 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8415 return PAGE_ALIGN(pitch * mode->vdisplay);
8416 }
8417
8418 static struct drm_framebuffer *
8419 intel_framebuffer_create_for_mode(struct drm_device *dev,
8420 struct drm_display_mode *mode,
8421 int depth, int bpp)
8422 {
8423 struct drm_i915_gem_object *obj;
8424 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8425
8426 obj = i915_gem_alloc_object(dev,
8427 intel_framebuffer_size_for_mode(mode, bpp));
8428 if (obj == NULL)
8429 return ERR_PTR(-ENOMEM);
8430
8431 mode_cmd.width = mode->hdisplay;
8432 mode_cmd.height = mode->vdisplay;
8433 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8434 bpp);
8435 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8436
8437 return intel_framebuffer_create(dev, &mode_cmd, obj);
8438 }
8439
8440 static struct drm_framebuffer *
8441 mode_fits_in_fbdev(struct drm_device *dev,
8442 struct drm_display_mode *mode)
8443 {
8444 #ifdef CONFIG_DRM_I915_FBDEV
8445 struct drm_i915_private *dev_priv = dev->dev_private;
8446 struct drm_i915_gem_object *obj;
8447 struct drm_framebuffer *fb;
8448
8449 if (!dev_priv->fbdev)
8450 return NULL;
8451
8452 if (!dev_priv->fbdev->fb)
8453 return NULL;
8454
8455 obj = dev_priv->fbdev->fb->obj;
8456 BUG_ON(!obj);
8457
8458 fb = &dev_priv->fbdev->fb->base;
8459 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8460 fb->bits_per_pixel))
8461 return NULL;
8462
8463 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8464 return NULL;
8465
8466 return fb;
8467 #else
8468 return NULL;
8469 #endif
8470 }
8471
8472 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8473 struct drm_display_mode *mode,
8474 struct intel_load_detect_pipe *old,
8475 struct drm_modeset_acquire_ctx *ctx)
8476 {
8477 struct intel_crtc *intel_crtc;
8478 struct intel_encoder *intel_encoder =
8479 intel_attached_encoder(connector);
8480 struct drm_crtc *possible_crtc;
8481 struct drm_encoder *encoder = &intel_encoder->base;
8482 struct drm_crtc *crtc = NULL;
8483 struct drm_device *dev = encoder->dev;
8484 struct drm_framebuffer *fb;
8485 struct drm_mode_config *config = &dev->mode_config;
8486 int ret, i = -1;
8487
8488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8489 connector->base.id, connector->name,
8490 encoder->base.id, encoder->name);
8491
8492 retry:
8493 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8494 if (ret)
8495 goto fail_unlock;
8496
8497 /*
8498 * Algorithm gets a little messy:
8499 *
8500 * - if the connector already has an assigned crtc, use it (but make
8501 * sure it's on first)
8502 *
8503 * - try to find the first unused crtc that can drive this connector,
8504 * and use that if we find one
8505 */
8506
8507 /* See if we already have a CRTC for this connector */
8508 if (encoder->crtc) {
8509 crtc = encoder->crtc;
8510
8511 ret = drm_modeset_lock(&crtc->mutex, ctx);
8512 if (ret)
8513 goto fail_unlock;
8514 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8515 if (ret)
8516 goto fail_unlock;
8517
8518 old->dpms_mode = connector->dpms;
8519 old->load_detect_temp = false;
8520
8521 /* Make sure the crtc and connector are running */
8522 if (connector->dpms != DRM_MODE_DPMS_ON)
8523 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8524
8525 return true;
8526 }
8527
8528 /* Find an unused one (if possible) */
8529 for_each_crtc(dev, possible_crtc) {
8530 i++;
8531 if (!(encoder->possible_crtcs & (1 << i)))
8532 continue;
8533 if (possible_crtc->enabled)
8534 continue;
8535 /* This can occur when applying the pipe A quirk on resume. */
8536 if (to_intel_crtc(possible_crtc)->new_enabled)
8537 continue;
8538
8539 crtc = possible_crtc;
8540 break;
8541 }
8542
8543 /*
8544 * If we didn't find an unused CRTC, don't use any.
8545 */
8546 if (!crtc) {
8547 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8548 goto fail_unlock;
8549 }
8550
8551 ret = drm_modeset_lock(&crtc->mutex, ctx);
8552 if (ret)
8553 goto fail_unlock;
8554 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8555 if (ret)
8556 goto fail_unlock;
8557 intel_encoder->new_crtc = to_intel_crtc(crtc);
8558 to_intel_connector(connector)->new_encoder = intel_encoder;
8559
8560 intel_crtc = to_intel_crtc(crtc);
8561 intel_crtc->new_enabled = true;
8562 intel_crtc->new_config = intel_crtc->config;
8563 old->dpms_mode = connector->dpms;
8564 old->load_detect_temp = true;
8565 old->release_fb = NULL;
8566
8567 if (!mode)
8568 mode = &load_detect_mode;
8569
8570 /* We need a framebuffer large enough to accommodate all accesses
8571 * that the plane may generate whilst we perform load detection.
8572 * We can not rely on the fbcon either being present (we get called
8573 * during its initialisation to detect all boot displays, or it may
8574 * not even exist) or that it is large enough to satisfy the
8575 * requested mode.
8576 */
8577 fb = mode_fits_in_fbdev(dev, mode);
8578 if (fb == NULL) {
8579 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8580 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8581 old->release_fb = fb;
8582 } else
8583 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8584 if (IS_ERR(fb)) {
8585 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8586 goto fail;
8587 }
8588
8589 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8590 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8591 if (old->release_fb)
8592 old->release_fb->funcs->destroy(old->release_fb);
8593 goto fail;
8594 }
8595
8596 /* let the connector get through one full cycle before testing */
8597 intel_wait_for_vblank(dev, intel_crtc->pipe);
8598 return true;
8599
8600 fail:
8601 intel_crtc->new_enabled = crtc->enabled;
8602 if (intel_crtc->new_enabled)
8603 intel_crtc->new_config = intel_crtc->config;
8604 else
8605 intel_crtc->new_config = NULL;
8606 fail_unlock:
8607 if (ret == -EDEADLK) {
8608 drm_modeset_backoff(ctx);
8609 goto retry;
8610 }
8611
8612 return false;
8613 }
8614
8615 void intel_release_load_detect_pipe(struct drm_connector *connector,
8616 struct intel_load_detect_pipe *old)
8617 {
8618 struct intel_encoder *intel_encoder =
8619 intel_attached_encoder(connector);
8620 struct drm_encoder *encoder = &intel_encoder->base;
8621 struct drm_crtc *crtc = encoder->crtc;
8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623
8624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8625 connector->base.id, connector->name,
8626 encoder->base.id, encoder->name);
8627
8628 if (old->load_detect_temp) {
8629 to_intel_connector(connector)->new_encoder = NULL;
8630 intel_encoder->new_crtc = NULL;
8631 intel_crtc->new_enabled = false;
8632 intel_crtc->new_config = NULL;
8633 intel_set_mode(crtc, NULL, 0, 0, NULL);
8634
8635 if (old->release_fb) {
8636 drm_framebuffer_unregister_private(old->release_fb);
8637 drm_framebuffer_unreference(old->release_fb);
8638 }
8639
8640 return;
8641 }
8642
8643 /* Switch crtc and encoder back off if necessary */
8644 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8645 connector->funcs->dpms(connector, old->dpms_mode);
8646 }
8647
8648 static int i9xx_pll_refclk(struct drm_device *dev,
8649 const struct intel_crtc_state *pipe_config)
8650 {
8651 struct drm_i915_private *dev_priv = dev->dev_private;
8652 u32 dpll = pipe_config->dpll_hw_state.dpll;
8653
8654 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8655 return dev_priv->vbt.lvds_ssc_freq;
8656 else if (HAS_PCH_SPLIT(dev))
8657 return 120000;
8658 else if (!IS_GEN2(dev))
8659 return 96000;
8660 else
8661 return 48000;
8662 }
8663
8664 /* Returns the clock of the currently programmed mode of the given pipe. */
8665 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8666 struct intel_crtc_state *pipe_config)
8667 {
8668 struct drm_device *dev = crtc->base.dev;
8669 struct drm_i915_private *dev_priv = dev->dev_private;
8670 int pipe = pipe_config->cpu_transcoder;
8671 u32 dpll = pipe_config->dpll_hw_state.dpll;
8672 u32 fp;
8673 intel_clock_t clock;
8674 int refclk = i9xx_pll_refclk(dev, pipe_config);
8675
8676 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8677 fp = pipe_config->dpll_hw_state.fp0;
8678 else
8679 fp = pipe_config->dpll_hw_state.fp1;
8680
8681 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8682 if (IS_PINEVIEW(dev)) {
8683 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8684 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8685 } else {
8686 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8687 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8688 }
8689
8690 if (!IS_GEN2(dev)) {
8691 if (IS_PINEVIEW(dev))
8692 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8693 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8694 else
8695 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8696 DPLL_FPA01_P1_POST_DIV_SHIFT);
8697
8698 switch (dpll & DPLL_MODE_MASK) {
8699 case DPLLB_MODE_DAC_SERIAL:
8700 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8701 5 : 10;
8702 break;
8703 case DPLLB_MODE_LVDS:
8704 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8705 7 : 14;
8706 break;
8707 default:
8708 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8709 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8710 return;
8711 }
8712
8713 if (IS_PINEVIEW(dev))
8714 pineview_clock(refclk, &clock);
8715 else
8716 i9xx_clock(refclk, &clock);
8717 } else {
8718 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8719 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8720
8721 if (is_lvds) {
8722 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8723 DPLL_FPA01_P1_POST_DIV_SHIFT);
8724
8725 if (lvds & LVDS_CLKB_POWER_UP)
8726 clock.p2 = 7;
8727 else
8728 clock.p2 = 14;
8729 } else {
8730 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8731 clock.p1 = 2;
8732 else {
8733 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8734 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8735 }
8736 if (dpll & PLL_P2_DIVIDE_BY_4)
8737 clock.p2 = 4;
8738 else
8739 clock.p2 = 2;
8740 }
8741
8742 i9xx_clock(refclk, &clock);
8743 }
8744
8745 /*
8746 * This value includes pixel_multiplier. We will use
8747 * port_clock to compute adjusted_mode.crtc_clock in the
8748 * encoder's get_config() function.
8749 */
8750 pipe_config->port_clock = clock.dot;
8751 }
8752
8753 int intel_dotclock_calculate(int link_freq,
8754 const struct intel_link_m_n *m_n)
8755 {
8756 /*
8757 * The calculation for the data clock is:
8758 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8759 * But we want to avoid losing precison if possible, so:
8760 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8761 *
8762 * and the link clock is simpler:
8763 * link_clock = (m * link_clock) / n
8764 */
8765
8766 if (!m_n->link_n)
8767 return 0;
8768
8769 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8770 }
8771
8772 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8773 struct intel_crtc_state *pipe_config)
8774 {
8775 struct drm_device *dev = crtc->base.dev;
8776
8777 /* read out port_clock from the DPLL */
8778 i9xx_crtc_clock_get(crtc, pipe_config);
8779
8780 /*
8781 * This value does not include pixel_multiplier.
8782 * We will check that port_clock and adjusted_mode.crtc_clock
8783 * agree once we know their relationship in the encoder's
8784 * get_config() function.
8785 */
8786 pipe_config->base.adjusted_mode.crtc_clock =
8787 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8788 &pipe_config->fdi_m_n);
8789 }
8790
8791 /** Returns the currently programmed mode of the given pipe. */
8792 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8793 struct drm_crtc *crtc)
8794 {
8795 struct drm_i915_private *dev_priv = dev->dev_private;
8796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8797 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8798 struct drm_display_mode *mode;
8799 struct intel_crtc_state pipe_config;
8800 int htot = I915_READ(HTOTAL(cpu_transcoder));
8801 int hsync = I915_READ(HSYNC(cpu_transcoder));
8802 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8803 int vsync = I915_READ(VSYNC(cpu_transcoder));
8804 enum pipe pipe = intel_crtc->pipe;
8805
8806 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8807 if (!mode)
8808 return NULL;
8809
8810 /*
8811 * Construct a pipe_config sufficient for getting the clock info
8812 * back out of crtc_clock_get.
8813 *
8814 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8815 * to use a real value here instead.
8816 */
8817 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8818 pipe_config.pixel_multiplier = 1;
8819 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8820 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8821 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8822 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8823
8824 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8825 mode->hdisplay = (htot & 0xffff) + 1;
8826 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8827 mode->hsync_start = (hsync & 0xffff) + 1;
8828 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8829 mode->vdisplay = (vtot & 0xffff) + 1;
8830 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8831 mode->vsync_start = (vsync & 0xffff) + 1;
8832 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8833
8834 drm_mode_set_name(mode);
8835
8836 return mode;
8837 }
8838
8839 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8840 {
8841 struct drm_device *dev = crtc->dev;
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8844
8845 if (!HAS_GMCH_DISPLAY(dev))
8846 return;
8847
8848 if (!dev_priv->lvds_downclock_avail)
8849 return;
8850
8851 /*
8852 * Since this is called by a timer, we should never get here in
8853 * the manual case.
8854 */
8855 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8856 int pipe = intel_crtc->pipe;
8857 int dpll_reg = DPLL(pipe);
8858 int dpll;
8859
8860 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8861
8862 assert_panel_unlocked(dev_priv, pipe);
8863
8864 dpll = I915_READ(dpll_reg);
8865 dpll |= DISPLAY_RATE_SELECT_FPA1;
8866 I915_WRITE(dpll_reg, dpll);
8867 intel_wait_for_vblank(dev, pipe);
8868 dpll = I915_READ(dpll_reg);
8869 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8870 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8871 }
8872
8873 }
8874
8875 void intel_mark_busy(struct drm_device *dev)
8876 {
8877 struct drm_i915_private *dev_priv = dev->dev_private;
8878
8879 if (dev_priv->mm.busy)
8880 return;
8881
8882 intel_runtime_pm_get(dev_priv);
8883 i915_update_gfx_val(dev_priv);
8884 dev_priv->mm.busy = true;
8885 }
8886
8887 void intel_mark_idle(struct drm_device *dev)
8888 {
8889 struct drm_i915_private *dev_priv = dev->dev_private;
8890 struct drm_crtc *crtc;
8891
8892 if (!dev_priv->mm.busy)
8893 return;
8894
8895 dev_priv->mm.busy = false;
8896
8897 if (!i915.powersave)
8898 goto out;
8899
8900 for_each_crtc(dev, crtc) {
8901 if (!crtc->primary->fb)
8902 continue;
8903
8904 intel_decrease_pllclock(crtc);
8905 }
8906
8907 if (INTEL_INFO(dev)->gen >= 6)
8908 gen6_rps_idle(dev->dev_private);
8909
8910 out:
8911 intel_runtime_pm_put(dev_priv);
8912 }
8913
8914 static void intel_crtc_set_state(struct intel_crtc *crtc,
8915 struct intel_crtc_state *crtc_state)
8916 {
8917 kfree(crtc->config);
8918 crtc->config = crtc_state;
8919 crtc->base.state = &crtc_state->base;
8920 }
8921
8922 static void intel_crtc_destroy(struct drm_crtc *crtc)
8923 {
8924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8925 struct drm_device *dev = crtc->dev;
8926 struct intel_unpin_work *work;
8927
8928 spin_lock_irq(&dev->event_lock);
8929 work = intel_crtc->unpin_work;
8930 intel_crtc->unpin_work = NULL;
8931 spin_unlock_irq(&dev->event_lock);
8932
8933 if (work) {
8934 cancel_work_sync(&work->work);
8935 kfree(work);
8936 }
8937
8938 intel_crtc_set_state(intel_crtc, NULL);
8939 drm_crtc_cleanup(crtc);
8940
8941 kfree(intel_crtc);
8942 }
8943
8944 static void intel_unpin_work_fn(struct work_struct *__work)
8945 {
8946 struct intel_unpin_work *work =
8947 container_of(__work, struct intel_unpin_work, work);
8948 struct drm_device *dev = work->crtc->dev;
8949 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8950
8951 mutex_lock(&dev->struct_mutex);
8952 intel_unpin_fb_obj(work->old_fb_obj);
8953 drm_gem_object_unreference(&work->pending_flip_obj->base);
8954 drm_gem_object_unreference(&work->old_fb_obj->base);
8955
8956 intel_fbc_update(dev);
8957
8958 if (work->flip_queued_req)
8959 i915_gem_request_assign(&work->flip_queued_req, NULL);
8960 mutex_unlock(&dev->struct_mutex);
8961
8962 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
8963
8964 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8965 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8966
8967 kfree(work);
8968 }
8969
8970 static void do_intel_finish_page_flip(struct drm_device *dev,
8971 struct drm_crtc *crtc)
8972 {
8973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8974 struct intel_unpin_work *work;
8975 unsigned long flags;
8976
8977 /* Ignore early vblank irqs */
8978 if (intel_crtc == NULL)
8979 return;
8980
8981 /*
8982 * This is called both by irq handlers and the reset code (to complete
8983 * lost pageflips) so needs the full irqsave spinlocks.
8984 */
8985 spin_lock_irqsave(&dev->event_lock, flags);
8986 work = intel_crtc->unpin_work;
8987
8988 /* Ensure we don't miss a work->pending update ... */
8989 smp_rmb();
8990
8991 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8992 spin_unlock_irqrestore(&dev->event_lock, flags);
8993 return;
8994 }
8995
8996 page_flip_completed(intel_crtc);
8997
8998 spin_unlock_irqrestore(&dev->event_lock, flags);
8999 }
9000
9001 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9002 {
9003 struct drm_i915_private *dev_priv = dev->dev_private;
9004 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9005
9006 do_intel_finish_page_flip(dev, crtc);
9007 }
9008
9009 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9010 {
9011 struct drm_i915_private *dev_priv = dev->dev_private;
9012 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9013
9014 do_intel_finish_page_flip(dev, crtc);
9015 }
9016
9017 /* Is 'a' after or equal to 'b'? */
9018 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9019 {
9020 return !((a - b) & 0x80000000);
9021 }
9022
9023 static bool page_flip_finished(struct intel_crtc *crtc)
9024 {
9025 struct drm_device *dev = crtc->base.dev;
9026 struct drm_i915_private *dev_priv = dev->dev_private;
9027
9028 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9029 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9030 return true;
9031
9032 /*
9033 * The relevant registers doen't exist on pre-ctg.
9034 * As the flip done interrupt doesn't trigger for mmio
9035 * flips on gmch platforms, a flip count check isn't
9036 * really needed there. But since ctg has the registers,
9037 * include it in the check anyway.
9038 */
9039 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9040 return true;
9041
9042 /*
9043 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9044 * used the same base address. In that case the mmio flip might
9045 * have completed, but the CS hasn't even executed the flip yet.
9046 *
9047 * A flip count check isn't enough as the CS might have updated
9048 * the base address just after start of vblank, but before we
9049 * managed to process the interrupt. This means we'd complete the
9050 * CS flip too soon.
9051 *
9052 * Combining both checks should get us a good enough result. It may
9053 * still happen that the CS flip has been executed, but has not
9054 * yet actually completed. But in case the base address is the same
9055 * anyway, we don't really care.
9056 */
9057 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9058 crtc->unpin_work->gtt_offset &&
9059 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9060 crtc->unpin_work->flip_count);
9061 }
9062
9063 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9064 {
9065 struct drm_i915_private *dev_priv = dev->dev_private;
9066 struct intel_crtc *intel_crtc =
9067 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9068 unsigned long flags;
9069
9070
9071 /*
9072 * This is called both by irq handlers and the reset code (to complete
9073 * lost pageflips) so needs the full irqsave spinlocks.
9074 *
9075 * NB: An MMIO update of the plane base pointer will also
9076 * generate a page-flip completion irq, i.e. every modeset
9077 * is also accompanied by a spurious intel_prepare_page_flip().
9078 */
9079 spin_lock_irqsave(&dev->event_lock, flags);
9080 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9081 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9082 spin_unlock_irqrestore(&dev->event_lock, flags);
9083 }
9084
9085 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9086 {
9087 /* Ensure that the work item is consistent when activating it ... */
9088 smp_wmb();
9089 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9090 /* and that it is marked active as soon as the irq could fire. */
9091 smp_wmb();
9092 }
9093
9094 static int intel_gen2_queue_flip(struct drm_device *dev,
9095 struct drm_crtc *crtc,
9096 struct drm_framebuffer *fb,
9097 struct drm_i915_gem_object *obj,
9098 struct intel_engine_cs *ring,
9099 uint32_t flags)
9100 {
9101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9102 u32 flip_mask;
9103 int ret;
9104
9105 ret = intel_ring_begin(ring, 6);
9106 if (ret)
9107 return ret;
9108
9109 /* Can't queue multiple flips, so wait for the previous
9110 * one to finish before executing the next.
9111 */
9112 if (intel_crtc->plane)
9113 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9114 else
9115 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9116 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9117 intel_ring_emit(ring, MI_NOOP);
9118 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9119 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9120 intel_ring_emit(ring, fb->pitches[0]);
9121 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9122 intel_ring_emit(ring, 0); /* aux display base address, unused */
9123
9124 intel_mark_page_flip_active(intel_crtc);
9125 __intel_ring_advance(ring);
9126 return 0;
9127 }
9128
9129 static int intel_gen3_queue_flip(struct drm_device *dev,
9130 struct drm_crtc *crtc,
9131 struct drm_framebuffer *fb,
9132 struct drm_i915_gem_object *obj,
9133 struct intel_engine_cs *ring,
9134 uint32_t flags)
9135 {
9136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9137 u32 flip_mask;
9138 int ret;
9139
9140 ret = intel_ring_begin(ring, 6);
9141 if (ret)
9142 return ret;
9143
9144 if (intel_crtc->plane)
9145 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9146 else
9147 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9148 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9149 intel_ring_emit(ring, MI_NOOP);
9150 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9151 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9152 intel_ring_emit(ring, fb->pitches[0]);
9153 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9154 intel_ring_emit(ring, MI_NOOP);
9155
9156 intel_mark_page_flip_active(intel_crtc);
9157 __intel_ring_advance(ring);
9158 return 0;
9159 }
9160
9161 static int intel_gen4_queue_flip(struct drm_device *dev,
9162 struct drm_crtc *crtc,
9163 struct drm_framebuffer *fb,
9164 struct drm_i915_gem_object *obj,
9165 struct intel_engine_cs *ring,
9166 uint32_t flags)
9167 {
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9170 uint32_t pf, pipesrc;
9171 int ret;
9172
9173 ret = intel_ring_begin(ring, 4);
9174 if (ret)
9175 return ret;
9176
9177 /* i965+ uses the linear or tiled offsets from the
9178 * Display Registers (which do not change across a page-flip)
9179 * so we need only reprogram the base address.
9180 */
9181 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9182 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9183 intel_ring_emit(ring, fb->pitches[0]);
9184 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9185 obj->tiling_mode);
9186
9187 /* XXX Enabling the panel-fitter across page-flip is so far
9188 * untested on non-native modes, so ignore it for now.
9189 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9190 */
9191 pf = 0;
9192 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9193 intel_ring_emit(ring, pf | pipesrc);
9194
9195 intel_mark_page_flip_active(intel_crtc);
9196 __intel_ring_advance(ring);
9197 return 0;
9198 }
9199
9200 static int intel_gen6_queue_flip(struct drm_device *dev,
9201 struct drm_crtc *crtc,
9202 struct drm_framebuffer *fb,
9203 struct drm_i915_gem_object *obj,
9204 struct intel_engine_cs *ring,
9205 uint32_t flags)
9206 {
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9209 uint32_t pf, pipesrc;
9210 int ret;
9211
9212 ret = intel_ring_begin(ring, 4);
9213 if (ret)
9214 return ret;
9215
9216 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9217 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9218 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9219 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9220
9221 /* Contrary to the suggestions in the documentation,
9222 * "Enable Panel Fitter" does not seem to be required when page
9223 * flipping with a non-native mode, and worse causes a normal
9224 * modeset to fail.
9225 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9226 */
9227 pf = 0;
9228 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9229 intel_ring_emit(ring, pf | pipesrc);
9230
9231 intel_mark_page_flip_active(intel_crtc);
9232 __intel_ring_advance(ring);
9233 return 0;
9234 }
9235
9236 static int intel_gen7_queue_flip(struct drm_device *dev,
9237 struct drm_crtc *crtc,
9238 struct drm_framebuffer *fb,
9239 struct drm_i915_gem_object *obj,
9240 struct intel_engine_cs *ring,
9241 uint32_t flags)
9242 {
9243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9244 uint32_t plane_bit = 0;
9245 int len, ret;
9246
9247 switch (intel_crtc->plane) {
9248 case PLANE_A:
9249 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9250 break;
9251 case PLANE_B:
9252 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9253 break;
9254 case PLANE_C:
9255 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9256 break;
9257 default:
9258 WARN_ONCE(1, "unknown plane in flip command\n");
9259 return -ENODEV;
9260 }
9261
9262 len = 4;
9263 if (ring->id == RCS) {
9264 len += 6;
9265 /*
9266 * On Gen 8, SRM is now taking an extra dword to accommodate
9267 * 48bits addresses, and we need a NOOP for the batch size to
9268 * stay even.
9269 */
9270 if (IS_GEN8(dev))
9271 len += 2;
9272 }
9273
9274 /*
9275 * BSpec MI_DISPLAY_FLIP for IVB:
9276 * "The full packet must be contained within the same cache line."
9277 *
9278 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9279 * cacheline, if we ever start emitting more commands before
9280 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9281 * then do the cacheline alignment, and finally emit the
9282 * MI_DISPLAY_FLIP.
9283 */
9284 ret = intel_ring_cacheline_align(ring);
9285 if (ret)
9286 return ret;
9287
9288 ret = intel_ring_begin(ring, len);
9289 if (ret)
9290 return ret;
9291
9292 /* Unmask the flip-done completion message. Note that the bspec says that
9293 * we should do this for both the BCS and RCS, and that we must not unmask
9294 * more than one flip event at any time (or ensure that one flip message
9295 * can be sent by waiting for flip-done prior to queueing new flips).
9296 * Experimentation says that BCS works despite DERRMR masking all
9297 * flip-done completion events and that unmasking all planes at once
9298 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9299 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9300 */
9301 if (ring->id == RCS) {
9302 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9303 intel_ring_emit(ring, DERRMR);
9304 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9305 DERRMR_PIPEB_PRI_FLIP_DONE |
9306 DERRMR_PIPEC_PRI_FLIP_DONE));
9307 if (IS_GEN8(dev))
9308 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9309 MI_SRM_LRM_GLOBAL_GTT);
9310 else
9311 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9312 MI_SRM_LRM_GLOBAL_GTT);
9313 intel_ring_emit(ring, DERRMR);
9314 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9315 if (IS_GEN8(dev)) {
9316 intel_ring_emit(ring, 0);
9317 intel_ring_emit(ring, MI_NOOP);
9318 }
9319 }
9320
9321 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9322 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9323 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9324 intel_ring_emit(ring, (MI_NOOP));
9325
9326 intel_mark_page_flip_active(intel_crtc);
9327 __intel_ring_advance(ring);
9328 return 0;
9329 }
9330
9331 static bool use_mmio_flip(struct intel_engine_cs *ring,
9332 struct drm_i915_gem_object *obj)
9333 {
9334 /*
9335 * This is not being used for older platforms, because
9336 * non-availability of flip done interrupt forces us to use
9337 * CS flips. Older platforms derive flip done using some clever
9338 * tricks involving the flip_pending status bits and vblank irqs.
9339 * So using MMIO flips there would disrupt this mechanism.
9340 */
9341
9342 if (ring == NULL)
9343 return true;
9344
9345 if (INTEL_INFO(ring->dev)->gen < 5)
9346 return false;
9347
9348 if (i915.use_mmio_flip < 0)
9349 return false;
9350 else if (i915.use_mmio_flip > 0)
9351 return true;
9352 else if (i915.enable_execlists)
9353 return true;
9354 else
9355 return ring != i915_gem_request_get_ring(obj->last_read_req);
9356 }
9357
9358 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9359 {
9360 struct drm_device *dev = intel_crtc->base.dev;
9361 struct drm_i915_private *dev_priv = dev->dev_private;
9362 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9363 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9364 struct drm_i915_gem_object *obj = intel_fb->obj;
9365 const enum pipe pipe = intel_crtc->pipe;
9366 u32 ctl, stride;
9367
9368 ctl = I915_READ(PLANE_CTL(pipe, 0));
9369 ctl &= ~PLANE_CTL_TILED_MASK;
9370 if (obj->tiling_mode == I915_TILING_X)
9371 ctl |= PLANE_CTL_TILED_X;
9372
9373 /*
9374 * The stride is either expressed as a multiple of 64 bytes chunks for
9375 * linear buffers or in number of tiles for tiled buffers.
9376 */
9377 stride = fb->pitches[0] >> 6;
9378 if (obj->tiling_mode == I915_TILING_X)
9379 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9380
9381 /*
9382 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9383 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9384 */
9385 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9386 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9387
9388 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9389 POSTING_READ(PLANE_SURF(pipe, 0));
9390 }
9391
9392 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9393 {
9394 struct drm_device *dev = intel_crtc->base.dev;
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396 struct intel_framebuffer *intel_fb =
9397 to_intel_framebuffer(intel_crtc->base.primary->fb);
9398 struct drm_i915_gem_object *obj = intel_fb->obj;
9399 u32 dspcntr;
9400 u32 reg;
9401
9402 reg = DSPCNTR(intel_crtc->plane);
9403 dspcntr = I915_READ(reg);
9404
9405 if (obj->tiling_mode != I915_TILING_NONE)
9406 dspcntr |= DISPPLANE_TILED;
9407 else
9408 dspcntr &= ~DISPPLANE_TILED;
9409
9410 I915_WRITE(reg, dspcntr);
9411
9412 I915_WRITE(DSPSURF(intel_crtc->plane),
9413 intel_crtc->unpin_work->gtt_offset);
9414 POSTING_READ(DSPSURF(intel_crtc->plane));
9415
9416 }
9417
9418 /*
9419 * XXX: This is the temporary way to update the plane registers until we get
9420 * around to using the usual plane update functions for MMIO flips
9421 */
9422 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9423 {
9424 struct drm_device *dev = intel_crtc->base.dev;
9425 bool atomic_update;
9426 u32 start_vbl_count;
9427
9428 intel_mark_page_flip_active(intel_crtc);
9429
9430 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9431
9432 if (INTEL_INFO(dev)->gen >= 9)
9433 skl_do_mmio_flip(intel_crtc);
9434 else
9435 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9436 ilk_do_mmio_flip(intel_crtc);
9437
9438 if (atomic_update)
9439 intel_pipe_update_end(intel_crtc, start_vbl_count);
9440 }
9441
9442 static void intel_mmio_flip_work_func(struct work_struct *work)
9443 {
9444 struct intel_crtc *crtc =
9445 container_of(work, struct intel_crtc, mmio_flip.work);
9446 struct intel_mmio_flip *mmio_flip;
9447
9448 mmio_flip = &crtc->mmio_flip;
9449 if (mmio_flip->req)
9450 WARN_ON(__i915_wait_request(mmio_flip->req,
9451 crtc->reset_counter,
9452 false, NULL, NULL) != 0);
9453
9454 intel_do_mmio_flip(crtc);
9455 if (mmio_flip->req) {
9456 mutex_lock(&crtc->base.dev->struct_mutex);
9457 i915_gem_request_assign(&mmio_flip->req, NULL);
9458 mutex_unlock(&crtc->base.dev->struct_mutex);
9459 }
9460 }
9461
9462 static int intel_queue_mmio_flip(struct drm_device *dev,
9463 struct drm_crtc *crtc,
9464 struct drm_framebuffer *fb,
9465 struct drm_i915_gem_object *obj,
9466 struct intel_engine_cs *ring,
9467 uint32_t flags)
9468 {
9469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9470
9471 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9472 obj->last_write_req);
9473
9474 schedule_work(&intel_crtc->mmio_flip.work);
9475
9476 return 0;
9477 }
9478
9479 static int intel_gen9_queue_flip(struct drm_device *dev,
9480 struct drm_crtc *crtc,
9481 struct drm_framebuffer *fb,
9482 struct drm_i915_gem_object *obj,
9483 struct intel_engine_cs *ring,
9484 uint32_t flags)
9485 {
9486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9487 uint32_t plane = 0, stride;
9488 int ret;
9489
9490 switch(intel_crtc->pipe) {
9491 case PIPE_A:
9492 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9493 break;
9494 case PIPE_B:
9495 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9496 break;
9497 case PIPE_C:
9498 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9499 break;
9500 default:
9501 WARN_ONCE(1, "unknown plane in flip command\n");
9502 return -ENODEV;
9503 }
9504
9505 switch (obj->tiling_mode) {
9506 case I915_TILING_NONE:
9507 stride = fb->pitches[0] >> 6;
9508 break;
9509 case I915_TILING_X:
9510 stride = fb->pitches[0] >> 9;
9511 break;
9512 default:
9513 WARN_ONCE(1, "unknown tiling in flip command\n");
9514 return -ENODEV;
9515 }
9516
9517 ret = intel_ring_begin(ring, 10);
9518 if (ret)
9519 return ret;
9520
9521 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9522 intel_ring_emit(ring, DERRMR);
9523 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9524 DERRMR_PIPEB_PRI_FLIP_DONE |
9525 DERRMR_PIPEC_PRI_FLIP_DONE));
9526 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9527 MI_SRM_LRM_GLOBAL_GTT);
9528 intel_ring_emit(ring, DERRMR);
9529 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9530 intel_ring_emit(ring, 0);
9531
9532 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9533 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9534 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9535
9536 intel_mark_page_flip_active(intel_crtc);
9537 __intel_ring_advance(ring);
9538
9539 return 0;
9540 }
9541
9542 static int intel_default_queue_flip(struct drm_device *dev,
9543 struct drm_crtc *crtc,
9544 struct drm_framebuffer *fb,
9545 struct drm_i915_gem_object *obj,
9546 struct intel_engine_cs *ring,
9547 uint32_t flags)
9548 {
9549 return -ENODEV;
9550 }
9551
9552 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9553 struct drm_crtc *crtc)
9554 {
9555 struct drm_i915_private *dev_priv = dev->dev_private;
9556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9557 struct intel_unpin_work *work = intel_crtc->unpin_work;
9558 u32 addr;
9559
9560 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9561 return true;
9562
9563 if (!work->enable_stall_check)
9564 return false;
9565
9566 if (work->flip_ready_vblank == 0) {
9567 if (work->flip_queued_req &&
9568 !i915_gem_request_completed(work->flip_queued_req, true))
9569 return false;
9570
9571 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9572 }
9573
9574 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9575 return false;
9576
9577 /* Potential stall - if we see that the flip has happened,
9578 * assume a missed interrupt. */
9579 if (INTEL_INFO(dev)->gen >= 4)
9580 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9581 else
9582 addr = I915_READ(DSPADDR(intel_crtc->plane));
9583
9584 /* There is a potential issue here with a false positive after a flip
9585 * to the same address. We could address this by checking for a
9586 * non-incrementing frame counter.
9587 */
9588 return addr == work->gtt_offset;
9589 }
9590
9591 void intel_check_page_flip(struct drm_device *dev, int pipe)
9592 {
9593 struct drm_i915_private *dev_priv = dev->dev_private;
9594 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9596
9597 WARN_ON(!in_irq());
9598
9599 if (crtc == NULL)
9600 return;
9601
9602 spin_lock(&dev->event_lock);
9603 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9604 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9605 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9606 page_flip_completed(intel_crtc);
9607 }
9608 spin_unlock(&dev->event_lock);
9609 }
9610
9611 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9612 struct drm_framebuffer *fb,
9613 struct drm_pending_vblank_event *event,
9614 uint32_t page_flip_flags)
9615 {
9616 struct drm_device *dev = crtc->dev;
9617 struct drm_i915_private *dev_priv = dev->dev_private;
9618 struct drm_framebuffer *old_fb = crtc->primary->fb;
9619 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9621 struct drm_plane *primary = crtc->primary;
9622 enum pipe pipe = intel_crtc->pipe;
9623 struct intel_unpin_work *work;
9624 struct intel_engine_cs *ring;
9625 int ret;
9626
9627 /*
9628 * drm_mode_page_flip_ioctl() should already catch this, but double
9629 * check to be safe. In the future we may enable pageflipping from
9630 * a disabled primary plane.
9631 */
9632 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9633 return -EBUSY;
9634
9635 /* Can't change pixel format via MI display flips. */
9636 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9637 return -EINVAL;
9638
9639 /*
9640 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9641 * Note that pitch changes could also affect these register.
9642 */
9643 if (INTEL_INFO(dev)->gen > 3 &&
9644 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9645 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9646 return -EINVAL;
9647
9648 if (i915_terminally_wedged(&dev_priv->gpu_error))
9649 goto out_hang;
9650
9651 work = kzalloc(sizeof(*work), GFP_KERNEL);
9652 if (work == NULL)
9653 return -ENOMEM;
9654
9655 work->event = event;
9656 work->crtc = crtc;
9657 work->old_fb_obj = intel_fb_obj(old_fb);
9658 INIT_WORK(&work->work, intel_unpin_work_fn);
9659
9660 ret = drm_crtc_vblank_get(crtc);
9661 if (ret)
9662 goto free_work;
9663
9664 /* We borrow the event spin lock for protecting unpin_work */
9665 spin_lock_irq(&dev->event_lock);
9666 if (intel_crtc->unpin_work) {
9667 /* Before declaring the flip queue wedged, check if
9668 * the hardware completed the operation behind our backs.
9669 */
9670 if (__intel_pageflip_stall_check(dev, crtc)) {
9671 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9672 page_flip_completed(intel_crtc);
9673 } else {
9674 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9675 spin_unlock_irq(&dev->event_lock);
9676
9677 drm_crtc_vblank_put(crtc);
9678 kfree(work);
9679 return -EBUSY;
9680 }
9681 }
9682 intel_crtc->unpin_work = work;
9683 spin_unlock_irq(&dev->event_lock);
9684
9685 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9686 flush_workqueue(dev_priv->wq);
9687
9688 ret = i915_mutex_lock_interruptible(dev);
9689 if (ret)
9690 goto cleanup;
9691
9692 /* Reference the objects for the scheduled work. */
9693 drm_gem_object_reference(&work->old_fb_obj->base);
9694 drm_gem_object_reference(&obj->base);
9695
9696 crtc->primary->fb = fb;
9697
9698 work->pending_flip_obj = obj;
9699
9700 atomic_inc(&intel_crtc->unpin_work_count);
9701 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9702
9703 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9704 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9705
9706 if (IS_VALLEYVIEW(dev)) {
9707 ring = &dev_priv->ring[BCS];
9708 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9709 /* vlv: DISPLAY_FLIP fails to change tiling */
9710 ring = NULL;
9711 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9712 ring = &dev_priv->ring[BCS];
9713 } else if (INTEL_INFO(dev)->gen >= 7) {
9714 ring = i915_gem_request_get_ring(obj->last_read_req);
9715 if (ring == NULL || ring->id != RCS)
9716 ring = &dev_priv->ring[BCS];
9717 } else {
9718 ring = &dev_priv->ring[RCS];
9719 }
9720
9721 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9722 if (ret)
9723 goto cleanup_pending;
9724
9725 work->gtt_offset =
9726 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9727
9728 if (use_mmio_flip(ring, obj)) {
9729 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9730 page_flip_flags);
9731 if (ret)
9732 goto cleanup_unpin;
9733
9734 i915_gem_request_assign(&work->flip_queued_req,
9735 obj->last_write_req);
9736 } else {
9737 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9738 page_flip_flags);
9739 if (ret)
9740 goto cleanup_unpin;
9741
9742 i915_gem_request_assign(&work->flip_queued_req,
9743 intel_ring_get_request(ring));
9744 }
9745
9746 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9747 work->enable_stall_check = true;
9748
9749 i915_gem_track_fb(work->old_fb_obj, obj,
9750 INTEL_FRONTBUFFER_PRIMARY(pipe));
9751
9752 intel_fbc_disable(dev);
9753 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9754 mutex_unlock(&dev->struct_mutex);
9755
9756 trace_i915_flip_request(intel_crtc->plane, obj);
9757
9758 return 0;
9759
9760 cleanup_unpin:
9761 intel_unpin_fb_obj(obj);
9762 cleanup_pending:
9763 atomic_dec(&intel_crtc->unpin_work_count);
9764 crtc->primary->fb = old_fb;
9765 drm_gem_object_unreference(&work->old_fb_obj->base);
9766 drm_gem_object_unreference(&obj->base);
9767 mutex_unlock(&dev->struct_mutex);
9768
9769 cleanup:
9770 spin_lock_irq(&dev->event_lock);
9771 intel_crtc->unpin_work = NULL;
9772 spin_unlock_irq(&dev->event_lock);
9773
9774 drm_crtc_vblank_put(crtc);
9775 free_work:
9776 kfree(work);
9777
9778 if (ret == -EIO) {
9779 out_hang:
9780 ret = intel_plane_restore(primary);
9781 if (ret == 0 && event) {
9782 spin_lock_irq(&dev->event_lock);
9783 drm_send_vblank_event(dev, pipe, event);
9784 spin_unlock_irq(&dev->event_lock);
9785 }
9786 }
9787 return ret;
9788 }
9789
9790 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9791 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9792 .load_lut = intel_crtc_load_lut,
9793 .atomic_begin = intel_begin_crtc_commit,
9794 .atomic_flush = intel_finish_crtc_commit,
9795 };
9796
9797 /**
9798 * intel_modeset_update_staged_output_state
9799 *
9800 * Updates the staged output configuration state, e.g. after we've read out the
9801 * current hw state.
9802 */
9803 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9804 {
9805 struct intel_crtc *crtc;
9806 struct intel_encoder *encoder;
9807 struct intel_connector *connector;
9808
9809 list_for_each_entry(connector, &dev->mode_config.connector_list,
9810 base.head) {
9811 connector->new_encoder =
9812 to_intel_encoder(connector->base.encoder);
9813 }
9814
9815 for_each_intel_encoder(dev, encoder) {
9816 encoder->new_crtc =
9817 to_intel_crtc(encoder->base.crtc);
9818 }
9819
9820 for_each_intel_crtc(dev, crtc) {
9821 crtc->new_enabled = crtc->base.enabled;
9822
9823 if (crtc->new_enabled)
9824 crtc->new_config = crtc->config;
9825 else
9826 crtc->new_config = NULL;
9827 }
9828 }
9829
9830 /**
9831 * intel_modeset_commit_output_state
9832 *
9833 * This function copies the stage display pipe configuration to the real one.
9834 */
9835 static void intel_modeset_commit_output_state(struct drm_device *dev)
9836 {
9837 struct intel_crtc *crtc;
9838 struct intel_encoder *encoder;
9839 struct intel_connector *connector;
9840
9841 list_for_each_entry(connector, &dev->mode_config.connector_list,
9842 base.head) {
9843 connector->base.encoder = &connector->new_encoder->base;
9844 }
9845
9846 for_each_intel_encoder(dev, encoder) {
9847 encoder->base.crtc = &encoder->new_crtc->base;
9848 }
9849
9850 for_each_intel_crtc(dev, crtc) {
9851 crtc->base.enabled = crtc->new_enabled;
9852 }
9853 }
9854
9855 static void
9856 connected_sink_compute_bpp(struct intel_connector *connector,
9857 struct intel_crtc_state *pipe_config)
9858 {
9859 int bpp = pipe_config->pipe_bpp;
9860
9861 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9862 connector->base.base.id,
9863 connector->base.name);
9864
9865 /* Don't use an invalid EDID bpc value */
9866 if (connector->base.display_info.bpc &&
9867 connector->base.display_info.bpc * 3 < bpp) {
9868 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9869 bpp, connector->base.display_info.bpc*3);
9870 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9871 }
9872
9873 /* Clamp bpp to 8 on screens without EDID 1.4 */
9874 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9875 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9876 bpp);
9877 pipe_config->pipe_bpp = 24;
9878 }
9879 }
9880
9881 static int
9882 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9883 struct drm_framebuffer *fb,
9884 struct intel_crtc_state *pipe_config)
9885 {
9886 struct drm_device *dev = crtc->base.dev;
9887 struct intel_connector *connector;
9888 int bpp;
9889
9890 switch (fb->pixel_format) {
9891 case DRM_FORMAT_C8:
9892 bpp = 8*3; /* since we go through a colormap */
9893 break;
9894 case DRM_FORMAT_XRGB1555:
9895 case DRM_FORMAT_ARGB1555:
9896 /* checked in intel_framebuffer_init already */
9897 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9898 return -EINVAL;
9899 case DRM_FORMAT_RGB565:
9900 bpp = 6*3; /* min is 18bpp */
9901 break;
9902 case DRM_FORMAT_XBGR8888:
9903 case DRM_FORMAT_ABGR8888:
9904 /* checked in intel_framebuffer_init already */
9905 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9906 return -EINVAL;
9907 case DRM_FORMAT_XRGB8888:
9908 case DRM_FORMAT_ARGB8888:
9909 bpp = 8*3;
9910 break;
9911 case DRM_FORMAT_XRGB2101010:
9912 case DRM_FORMAT_ARGB2101010:
9913 case DRM_FORMAT_XBGR2101010:
9914 case DRM_FORMAT_ABGR2101010:
9915 /* checked in intel_framebuffer_init already */
9916 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9917 return -EINVAL;
9918 bpp = 10*3;
9919 break;
9920 /* TODO: gen4+ supports 16 bpc floating point, too. */
9921 default:
9922 DRM_DEBUG_KMS("unsupported depth\n");
9923 return -EINVAL;
9924 }
9925
9926 pipe_config->pipe_bpp = bpp;
9927
9928 /* Clamp display bpp to EDID value */
9929 list_for_each_entry(connector, &dev->mode_config.connector_list,
9930 base.head) {
9931 if (!connector->new_encoder ||
9932 connector->new_encoder->new_crtc != crtc)
9933 continue;
9934
9935 connected_sink_compute_bpp(connector, pipe_config);
9936 }
9937
9938 return bpp;
9939 }
9940
9941 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9942 {
9943 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9944 "type: 0x%x flags: 0x%x\n",
9945 mode->crtc_clock,
9946 mode->crtc_hdisplay, mode->crtc_hsync_start,
9947 mode->crtc_hsync_end, mode->crtc_htotal,
9948 mode->crtc_vdisplay, mode->crtc_vsync_start,
9949 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9950 }
9951
9952 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9953 struct intel_crtc_state *pipe_config,
9954 const char *context)
9955 {
9956 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9957 context, pipe_name(crtc->pipe));
9958
9959 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9960 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9961 pipe_config->pipe_bpp, pipe_config->dither);
9962 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9963 pipe_config->has_pch_encoder,
9964 pipe_config->fdi_lanes,
9965 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9966 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9967 pipe_config->fdi_m_n.tu);
9968 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9969 pipe_config->has_dp_encoder,
9970 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9971 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9972 pipe_config->dp_m_n.tu);
9973
9974 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9975 pipe_config->has_dp_encoder,
9976 pipe_config->dp_m2_n2.gmch_m,
9977 pipe_config->dp_m2_n2.gmch_n,
9978 pipe_config->dp_m2_n2.link_m,
9979 pipe_config->dp_m2_n2.link_n,
9980 pipe_config->dp_m2_n2.tu);
9981
9982 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
9983 pipe_config->has_audio,
9984 pipe_config->has_infoframe);
9985
9986 DRM_DEBUG_KMS("requested mode:\n");
9987 drm_mode_debug_printmodeline(&pipe_config->base.mode);
9988 DRM_DEBUG_KMS("adjusted mode:\n");
9989 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
9990 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
9991 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9992 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9993 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9994 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9995 pipe_config->gmch_pfit.control,
9996 pipe_config->gmch_pfit.pgm_ratios,
9997 pipe_config->gmch_pfit.lvds_border_bits);
9998 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9999 pipe_config->pch_pfit.pos,
10000 pipe_config->pch_pfit.size,
10001 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10002 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10003 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10004 }
10005
10006 static bool encoders_cloneable(const struct intel_encoder *a,
10007 const struct intel_encoder *b)
10008 {
10009 /* masks could be asymmetric, so check both ways */
10010 return a == b || (a->cloneable & (1 << b->type) &&
10011 b->cloneable & (1 << a->type));
10012 }
10013
10014 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10015 struct intel_encoder *encoder)
10016 {
10017 struct drm_device *dev = crtc->base.dev;
10018 struct intel_encoder *source_encoder;
10019
10020 for_each_intel_encoder(dev, source_encoder) {
10021 if (source_encoder->new_crtc != crtc)
10022 continue;
10023
10024 if (!encoders_cloneable(encoder, source_encoder))
10025 return false;
10026 }
10027
10028 return true;
10029 }
10030
10031 static bool check_encoder_cloning(struct intel_crtc *crtc)
10032 {
10033 struct drm_device *dev = crtc->base.dev;
10034 struct intel_encoder *encoder;
10035
10036 for_each_intel_encoder(dev, encoder) {
10037 if (encoder->new_crtc != crtc)
10038 continue;
10039
10040 if (!check_single_encoder_cloning(crtc, encoder))
10041 return false;
10042 }
10043
10044 return true;
10045 }
10046
10047 static bool check_digital_port_conflicts(struct drm_device *dev)
10048 {
10049 struct intel_connector *connector;
10050 unsigned int used_ports = 0;
10051
10052 /*
10053 * Walk the connector list instead of the encoder
10054 * list to detect the problem on ddi platforms
10055 * where there's just one encoder per digital port.
10056 */
10057 list_for_each_entry(connector,
10058 &dev->mode_config.connector_list, base.head) {
10059 struct intel_encoder *encoder = connector->new_encoder;
10060
10061 if (!encoder)
10062 continue;
10063
10064 WARN_ON(!encoder->new_crtc);
10065
10066 switch (encoder->type) {
10067 unsigned int port_mask;
10068 case INTEL_OUTPUT_UNKNOWN:
10069 if (WARN_ON(!HAS_DDI(dev)))
10070 break;
10071 case INTEL_OUTPUT_DISPLAYPORT:
10072 case INTEL_OUTPUT_HDMI:
10073 case INTEL_OUTPUT_EDP:
10074 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10075
10076 /* the same port mustn't appear more than once */
10077 if (used_ports & port_mask)
10078 return false;
10079
10080 used_ports |= port_mask;
10081 default:
10082 break;
10083 }
10084 }
10085
10086 return true;
10087 }
10088
10089 static struct intel_crtc_state *
10090 intel_modeset_pipe_config(struct drm_crtc *crtc,
10091 struct drm_framebuffer *fb,
10092 struct drm_display_mode *mode)
10093 {
10094 struct drm_device *dev = crtc->dev;
10095 struct intel_encoder *encoder;
10096 struct intel_crtc_state *pipe_config;
10097 int plane_bpp, ret = -EINVAL;
10098 bool retry = true;
10099
10100 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10101 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10102 return ERR_PTR(-EINVAL);
10103 }
10104
10105 if (!check_digital_port_conflicts(dev)) {
10106 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10107 return ERR_PTR(-EINVAL);
10108 }
10109
10110 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10111 if (!pipe_config)
10112 return ERR_PTR(-ENOMEM);
10113
10114 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10115 drm_mode_copy(&pipe_config->base.mode, mode);
10116
10117 pipe_config->cpu_transcoder =
10118 (enum transcoder) to_intel_crtc(crtc)->pipe;
10119 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10120
10121 /*
10122 * Sanitize sync polarity flags based on requested ones. If neither
10123 * positive or negative polarity is requested, treat this as meaning
10124 * negative polarity.
10125 */
10126 if (!(pipe_config->base.adjusted_mode.flags &
10127 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10128 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10129
10130 if (!(pipe_config->base.adjusted_mode.flags &
10131 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10132 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10133
10134 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10135 * plane pixel format and any sink constraints into account. Returns the
10136 * source plane bpp so that dithering can be selected on mismatches
10137 * after encoders and crtc also have had their say. */
10138 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10139 fb, pipe_config);
10140 if (plane_bpp < 0)
10141 goto fail;
10142
10143 /*
10144 * Determine the real pipe dimensions. Note that stereo modes can
10145 * increase the actual pipe size due to the frame doubling and
10146 * insertion of additional space for blanks between the frame. This
10147 * is stored in the crtc timings. We use the requested mode to do this
10148 * computation to clearly distinguish it from the adjusted mode, which
10149 * can be changed by the connectors in the below retry loop.
10150 */
10151 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10152 &pipe_config->pipe_src_w,
10153 &pipe_config->pipe_src_h);
10154
10155 encoder_retry:
10156 /* Ensure the port clock defaults are reset when retrying. */
10157 pipe_config->port_clock = 0;
10158 pipe_config->pixel_multiplier = 1;
10159
10160 /* Fill in default crtc timings, allow encoders to overwrite them. */
10161 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10162 CRTC_STEREO_DOUBLE);
10163
10164 /* Pass our mode to the connectors and the CRTC to give them a chance to
10165 * adjust it according to limitations or connector properties, and also
10166 * a chance to reject the mode entirely.
10167 */
10168 for_each_intel_encoder(dev, encoder) {
10169
10170 if (&encoder->new_crtc->base != crtc)
10171 continue;
10172
10173 if (!(encoder->compute_config(encoder, pipe_config))) {
10174 DRM_DEBUG_KMS("Encoder config failure\n");
10175 goto fail;
10176 }
10177 }
10178
10179 /* Set default port clock if not overwritten by the encoder. Needs to be
10180 * done afterwards in case the encoder adjusts the mode. */
10181 if (!pipe_config->port_clock)
10182 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10183 * pipe_config->pixel_multiplier;
10184
10185 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10186 if (ret < 0) {
10187 DRM_DEBUG_KMS("CRTC fixup failed\n");
10188 goto fail;
10189 }
10190
10191 if (ret == RETRY) {
10192 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10193 ret = -EINVAL;
10194 goto fail;
10195 }
10196
10197 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10198 retry = false;
10199 goto encoder_retry;
10200 }
10201
10202 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10203 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10204 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10205
10206 return pipe_config;
10207 fail:
10208 kfree(pipe_config);
10209 return ERR_PTR(ret);
10210 }
10211
10212 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10213 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10214 static void
10215 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10216 unsigned *prepare_pipes, unsigned *disable_pipes)
10217 {
10218 struct intel_crtc *intel_crtc;
10219 struct drm_device *dev = crtc->dev;
10220 struct intel_encoder *encoder;
10221 struct intel_connector *connector;
10222 struct drm_crtc *tmp_crtc;
10223
10224 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10225
10226 /* Check which crtcs have changed outputs connected to them, these need
10227 * to be part of the prepare_pipes mask. We don't (yet) support global
10228 * modeset across multiple crtcs, so modeset_pipes will only have one
10229 * bit set at most. */
10230 list_for_each_entry(connector, &dev->mode_config.connector_list,
10231 base.head) {
10232 if (connector->base.encoder == &connector->new_encoder->base)
10233 continue;
10234
10235 if (connector->base.encoder) {
10236 tmp_crtc = connector->base.encoder->crtc;
10237
10238 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10239 }
10240
10241 if (connector->new_encoder)
10242 *prepare_pipes |=
10243 1 << connector->new_encoder->new_crtc->pipe;
10244 }
10245
10246 for_each_intel_encoder(dev, encoder) {
10247 if (encoder->base.crtc == &encoder->new_crtc->base)
10248 continue;
10249
10250 if (encoder->base.crtc) {
10251 tmp_crtc = encoder->base.crtc;
10252
10253 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10254 }
10255
10256 if (encoder->new_crtc)
10257 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10258 }
10259
10260 /* Check for pipes that will be enabled/disabled ... */
10261 for_each_intel_crtc(dev, intel_crtc) {
10262 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10263 continue;
10264
10265 if (!intel_crtc->new_enabled)
10266 *disable_pipes |= 1 << intel_crtc->pipe;
10267 else
10268 *prepare_pipes |= 1 << intel_crtc->pipe;
10269 }
10270
10271
10272 /* set_mode is also used to update properties on life display pipes. */
10273 intel_crtc = to_intel_crtc(crtc);
10274 if (intel_crtc->new_enabled)
10275 *prepare_pipes |= 1 << intel_crtc->pipe;
10276
10277 /*
10278 * For simplicity do a full modeset on any pipe where the output routing
10279 * changed. We could be more clever, but that would require us to be
10280 * more careful with calling the relevant encoder->mode_set functions.
10281 */
10282 if (*prepare_pipes)
10283 *modeset_pipes = *prepare_pipes;
10284
10285 /* ... and mask these out. */
10286 *modeset_pipes &= ~(*disable_pipes);
10287 *prepare_pipes &= ~(*disable_pipes);
10288
10289 /*
10290 * HACK: We don't (yet) fully support global modesets. intel_set_config
10291 * obies this rule, but the modeset restore mode of
10292 * intel_modeset_setup_hw_state does not.
10293 */
10294 *modeset_pipes &= 1 << intel_crtc->pipe;
10295 *prepare_pipes &= 1 << intel_crtc->pipe;
10296
10297 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10298 *modeset_pipes, *prepare_pipes, *disable_pipes);
10299 }
10300
10301 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10302 {
10303 struct drm_encoder *encoder;
10304 struct drm_device *dev = crtc->dev;
10305
10306 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10307 if (encoder->crtc == crtc)
10308 return true;
10309
10310 return false;
10311 }
10312
10313 static void
10314 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10315 {
10316 struct drm_i915_private *dev_priv = dev->dev_private;
10317 struct intel_encoder *intel_encoder;
10318 struct intel_crtc *intel_crtc;
10319 struct drm_connector *connector;
10320
10321 intel_shared_dpll_commit(dev_priv);
10322
10323 for_each_intel_encoder(dev, intel_encoder) {
10324 if (!intel_encoder->base.crtc)
10325 continue;
10326
10327 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10328
10329 if (prepare_pipes & (1 << intel_crtc->pipe))
10330 intel_encoder->connectors_active = false;
10331 }
10332
10333 intel_modeset_commit_output_state(dev);
10334
10335 /* Double check state. */
10336 for_each_intel_crtc(dev, intel_crtc) {
10337 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10338 WARN_ON(intel_crtc->new_config &&
10339 intel_crtc->new_config != intel_crtc->config);
10340 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10341 }
10342
10343 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10344 if (!connector->encoder || !connector->encoder->crtc)
10345 continue;
10346
10347 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10348
10349 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10350 struct drm_property *dpms_property =
10351 dev->mode_config.dpms_property;
10352
10353 connector->dpms = DRM_MODE_DPMS_ON;
10354 drm_object_property_set_value(&connector->base,
10355 dpms_property,
10356 DRM_MODE_DPMS_ON);
10357
10358 intel_encoder = to_intel_encoder(connector->encoder);
10359 intel_encoder->connectors_active = true;
10360 }
10361 }
10362
10363 }
10364
10365 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10366 {
10367 int diff;
10368
10369 if (clock1 == clock2)
10370 return true;
10371
10372 if (!clock1 || !clock2)
10373 return false;
10374
10375 diff = abs(clock1 - clock2);
10376
10377 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10378 return true;
10379
10380 return false;
10381 }
10382
10383 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10384 list_for_each_entry((intel_crtc), \
10385 &(dev)->mode_config.crtc_list, \
10386 base.head) \
10387 if (mask & (1 <<(intel_crtc)->pipe))
10388
10389 static bool
10390 intel_pipe_config_compare(struct drm_device *dev,
10391 struct intel_crtc_state *current_config,
10392 struct intel_crtc_state *pipe_config)
10393 {
10394 #define PIPE_CONF_CHECK_X(name) \
10395 if (current_config->name != pipe_config->name) { \
10396 DRM_ERROR("mismatch in " #name " " \
10397 "(expected 0x%08x, found 0x%08x)\n", \
10398 current_config->name, \
10399 pipe_config->name); \
10400 return false; \
10401 }
10402
10403 #define PIPE_CONF_CHECK_I(name) \
10404 if (current_config->name != pipe_config->name) { \
10405 DRM_ERROR("mismatch in " #name " " \
10406 "(expected %i, found %i)\n", \
10407 current_config->name, \
10408 pipe_config->name); \
10409 return false; \
10410 }
10411
10412 /* This is required for BDW+ where there is only one set of registers for
10413 * switching between high and low RR.
10414 * This macro can be used whenever a comparison has to be made between one
10415 * hw state and multiple sw state variables.
10416 */
10417 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10418 if ((current_config->name != pipe_config->name) && \
10419 (current_config->alt_name != pipe_config->name)) { \
10420 DRM_ERROR("mismatch in " #name " " \
10421 "(expected %i or %i, found %i)\n", \
10422 current_config->name, \
10423 current_config->alt_name, \
10424 pipe_config->name); \
10425 return false; \
10426 }
10427
10428 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10429 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10430 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10431 "(expected %i, found %i)\n", \
10432 current_config->name & (mask), \
10433 pipe_config->name & (mask)); \
10434 return false; \
10435 }
10436
10437 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10438 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10439 DRM_ERROR("mismatch in " #name " " \
10440 "(expected %i, found %i)\n", \
10441 current_config->name, \
10442 pipe_config->name); \
10443 return false; \
10444 }
10445
10446 #define PIPE_CONF_QUIRK(quirk) \
10447 ((current_config->quirks | pipe_config->quirks) & (quirk))
10448
10449 PIPE_CONF_CHECK_I(cpu_transcoder);
10450
10451 PIPE_CONF_CHECK_I(has_pch_encoder);
10452 PIPE_CONF_CHECK_I(fdi_lanes);
10453 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10454 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10455 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10456 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10457 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10458
10459 PIPE_CONF_CHECK_I(has_dp_encoder);
10460
10461 if (INTEL_INFO(dev)->gen < 8) {
10462 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10463 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10464 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10465 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10466 PIPE_CONF_CHECK_I(dp_m_n.tu);
10467
10468 if (current_config->has_drrs) {
10469 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10470 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10471 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10472 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10473 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10474 }
10475 } else {
10476 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10477 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10478 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10479 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10480 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10481 }
10482
10483 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10484 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10485 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10486 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10487 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10488 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10489
10490 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10491 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10492 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10493 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10494 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10495 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10496
10497 PIPE_CONF_CHECK_I(pixel_multiplier);
10498 PIPE_CONF_CHECK_I(has_hdmi_sink);
10499 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10500 IS_VALLEYVIEW(dev))
10501 PIPE_CONF_CHECK_I(limited_color_range);
10502 PIPE_CONF_CHECK_I(has_infoframe);
10503
10504 PIPE_CONF_CHECK_I(has_audio);
10505
10506 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10507 DRM_MODE_FLAG_INTERLACE);
10508
10509 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10510 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10511 DRM_MODE_FLAG_PHSYNC);
10512 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10513 DRM_MODE_FLAG_NHSYNC);
10514 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10515 DRM_MODE_FLAG_PVSYNC);
10516 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10517 DRM_MODE_FLAG_NVSYNC);
10518 }
10519
10520 PIPE_CONF_CHECK_I(pipe_src_w);
10521 PIPE_CONF_CHECK_I(pipe_src_h);
10522
10523 /*
10524 * FIXME: BIOS likes to set up a cloned config with lvds+external
10525 * screen. Since we don't yet re-compute the pipe config when moving
10526 * just the lvds port away to another pipe the sw tracking won't match.
10527 *
10528 * Proper atomic modesets with recomputed global state will fix this.
10529 * Until then just don't check gmch state for inherited modes.
10530 */
10531 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10532 PIPE_CONF_CHECK_I(gmch_pfit.control);
10533 /* pfit ratios are autocomputed by the hw on gen4+ */
10534 if (INTEL_INFO(dev)->gen < 4)
10535 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10536 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10537 }
10538
10539 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10540 if (current_config->pch_pfit.enabled) {
10541 PIPE_CONF_CHECK_I(pch_pfit.pos);
10542 PIPE_CONF_CHECK_I(pch_pfit.size);
10543 }
10544
10545 /* BDW+ don't expose a synchronous way to read the state */
10546 if (IS_HASWELL(dev))
10547 PIPE_CONF_CHECK_I(ips_enabled);
10548
10549 PIPE_CONF_CHECK_I(double_wide);
10550
10551 PIPE_CONF_CHECK_X(ddi_pll_sel);
10552
10553 PIPE_CONF_CHECK_I(shared_dpll);
10554 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10555 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10556 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10557 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10558 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10559 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10560 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10561 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10562
10563 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10564 PIPE_CONF_CHECK_I(pipe_bpp);
10565
10566 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10567 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10568
10569 #undef PIPE_CONF_CHECK_X
10570 #undef PIPE_CONF_CHECK_I
10571 #undef PIPE_CONF_CHECK_I_ALT
10572 #undef PIPE_CONF_CHECK_FLAGS
10573 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10574 #undef PIPE_CONF_QUIRK
10575
10576 return true;
10577 }
10578
10579 static void check_wm_state(struct drm_device *dev)
10580 {
10581 struct drm_i915_private *dev_priv = dev->dev_private;
10582 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10583 struct intel_crtc *intel_crtc;
10584 int plane;
10585
10586 if (INTEL_INFO(dev)->gen < 9)
10587 return;
10588
10589 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10590 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10591
10592 for_each_intel_crtc(dev, intel_crtc) {
10593 struct skl_ddb_entry *hw_entry, *sw_entry;
10594 const enum pipe pipe = intel_crtc->pipe;
10595
10596 if (!intel_crtc->active)
10597 continue;
10598
10599 /* planes */
10600 for_each_plane(pipe, plane) {
10601 hw_entry = &hw_ddb.plane[pipe][plane];
10602 sw_entry = &sw_ddb->plane[pipe][plane];
10603
10604 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10605 continue;
10606
10607 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10608 "(expected (%u,%u), found (%u,%u))\n",
10609 pipe_name(pipe), plane + 1,
10610 sw_entry->start, sw_entry->end,
10611 hw_entry->start, hw_entry->end);
10612 }
10613
10614 /* cursor */
10615 hw_entry = &hw_ddb.cursor[pipe];
10616 sw_entry = &sw_ddb->cursor[pipe];
10617
10618 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10619 continue;
10620
10621 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10622 "(expected (%u,%u), found (%u,%u))\n",
10623 pipe_name(pipe),
10624 sw_entry->start, sw_entry->end,
10625 hw_entry->start, hw_entry->end);
10626 }
10627 }
10628
10629 static void
10630 check_connector_state(struct drm_device *dev)
10631 {
10632 struct intel_connector *connector;
10633
10634 list_for_each_entry(connector, &dev->mode_config.connector_list,
10635 base.head) {
10636 /* This also checks the encoder/connector hw state with the
10637 * ->get_hw_state callbacks. */
10638 intel_connector_check_state(connector);
10639
10640 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10641 "connector's staged encoder doesn't match current encoder\n");
10642 }
10643 }
10644
10645 static void
10646 check_encoder_state(struct drm_device *dev)
10647 {
10648 struct intel_encoder *encoder;
10649 struct intel_connector *connector;
10650
10651 for_each_intel_encoder(dev, encoder) {
10652 bool enabled = false;
10653 bool active = false;
10654 enum pipe pipe, tracked_pipe;
10655
10656 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10657 encoder->base.base.id,
10658 encoder->base.name);
10659
10660 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10661 "encoder's stage crtc doesn't match current crtc\n");
10662 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10663 "encoder's active_connectors set, but no crtc\n");
10664
10665 list_for_each_entry(connector, &dev->mode_config.connector_list,
10666 base.head) {
10667 if (connector->base.encoder != &encoder->base)
10668 continue;
10669 enabled = true;
10670 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10671 active = true;
10672 }
10673 /*
10674 * for MST connectors if we unplug the connector is gone
10675 * away but the encoder is still connected to a crtc
10676 * until a modeset happens in response to the hotplug.
10677 */
10678 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10679 continue;
10680
10681 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10682 "encoder's enabled state mismatch "
10683 "(expected %i, found %i)\n",
10684 !!encoder->base.crtc, enabled);
10685 I915_STATE_WARN(active && !encoder->base.crtc,
10686 "active encoder with no crtc\n");
10687
10688 I915_STATE_WARN(encoder->connectors_active != active,
10689 "encoder's computed active state doesn't match tracked active state "
10690 "(expected %i, found %i)\n", active, encoder->connectors_active);
10691
10692 active = encoder->get_hw_state(encoder, &pipe);
10693 I915_STATE_WARN(active != encoder->connectors_active,
10694 "encoder's hw state doesn't match sw tracking "
10695 "(expected %i, found %i)\n",
10696 encoder->connectors_active, active);
10697
10698 if (!encoder->base.crtc)
10699 continue;
10700
10701 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10702 I915_STATE_WARN(active && pipe != tracked_pipe,
10703 "active encoder's pipe doesn't match"
10704 "(expected %i, found %i)\n",
10705 tracked_pipe, pipe);
10706
10707 }
10708 }
10709
10710 static void
10711 check_crtc_state(struct drm_device *dev)
10712 {
10713 struct drm_i915_private *dev_priv = dev->dev_private;
10714 struct intel_crtc *crtc;
10715 struct intel_encoder *encoder;
10716 struct intel_crtc_state pipe_config;
10717
10718 for_each_intel_crtc(dev, crtc) {
10719 bool enabled = false;
10720 bool active = false;
10721
10722 memset(&pipe_config, 0, sizeof(pipe_config));
10723
10724 DRM_DEBUG_KMS("[CRTC:%d]\n",
10725 crtc->base.base.id);
10726
10727 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10728 "active crtc, but not enabled in sw tracking\n");
10729
10730 for_each_intel_encoder(dev, encoder) {
10731 if (encoder->base.crtc != &crtc->base)
10732 continue;
10733 enabled = true;
10734 if (encoder->connectors_active)
10735 active = true;
10736 }
10737
10738 I915_STATE_WARN(active != crtc->active,
10739 "crtc's computed active state doesn't match tracked active state "
10740 "(expected %i, found %i)\n", active, crtc->active);
10741 I915_STATE_WARN(enabled != crtc->base.enabled,
10742 "crtc's computed enabled state doesn't match tracked enabled state "
10743 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10744
10745 active = dev_priv->display.get_pipe_config(crtc,
10746 &pipe_config);
10747
10748 /* hw state is inconsistent with the pipe quirk */
10749 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10750 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10751 active = crtc->active;
10752
10753 for_each_intel_encoder(dev, encoder) {
10754 enum pipe pipe;
10755 if (encoder->base.crtc != &crtc->base)
10756 continue;
10757 if (encoder->get_hw_state(encoder, &pipe))
10758 encoder->get_config(encoder, &pipe_config);
10759 }
10760
10761 I915_STATE_WARN(crtc->active != active,
10762 "crtc active state doesn't match with hw state "
10763 "(expected %i, found %i)\n", crtc->active, active);
10764
10765 if (active &&
10766 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10767 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10768 intel_dump_pipe_config(crtc, &pipe_config,
10769 "[hw state]");
10770 intel_dump_pipe_config(crtc, crtc->config,
10771 "[sw state]");
10772 }
10773 }
10774 }
10775
10776 static void
10777 check_shared_dpll_state(struct drm_device *dev)
10778 {
10779 struct drm_i915_private *dev_priv = dev->dev_private;
10780 struct intel_crtc *crtc;
10781 struct intel_dpll_hw_state dpll_hw_state;
10782 int i;
10783
10784 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10785 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10786 int enabled_crtcs = 0, active_crtcs = 0;
10787 bool active;
10788
10789 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10790
10791 DRM_DEBUG_KMS("%s\n", pll->name);
10792
10793 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10794
10795 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10796 "more active pll users than references: %i vs %i\n",
10797 pll->active, hweight32(pll->config.crtc_mask));
10798 I915_STATE_WARN(pll->active && !pll->on,
10799 "pll in active use but not on in sw tracking\n");
10800 I915_STATE_WARN(pll->on && !pll->active,
10801 "pll in on but not on in use in sw tracking\n");
10802 I915_STATE_WARN(pll->on != active,
10803 "pll on state mismatch (expected %i, found %i)\n",
10804 pll->on, active);
10805
10806 for_each_intel_crtc(dev, crtc) {
10807 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10808 enabled_crtcs++;
10809 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10810 active_crtcs++;
10811 }
10812 I915_STATE_WARN(pll->active != active_crtcs,
10813 "pll active crtcs mismatch (expected %i, found %i)\n",
10814 pll->active, active_crtcs);
10815 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10816 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10817 hweight32(pll->config.crtc_mask), enabled_crtcs);
10818
10819 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10820 sizeof(dpll_hw_state)),
10821 "pll hw state mismatch\n");
10822 }
10823 }
10824
10825 void
10826 intel_modeset_check_state(struct drm_device *dev)
10827 {
10828 check_wm_state(dev);
10829 check_connector_state(dev);
10830 check_encoder_state(dev);
10831 check_crtc_state(dev);
10832 check_shared_dpll_state(dev);
10833 }
10834
10835 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10836 int dotclock)
10837 {
10838 /*
10839 * FDI already provided one idea for the dotclock.
10840 * Yell if the encoder disagrees.
10841 */
10842 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10843 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10844 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10845 }
10846
10847 static void update_scanline_offset(struct intel_crtc *crtc)
10848 {
10849 struct drm_device *dev = crtc->base.dev;
10850
10851 /*
10852 * The scanline counter increments at the leading edge of hsync.
10853 *
10854 * On most platforms it starts counting from vtotal-1 on the
10855 * first active line. That means the scanline counter value is
10856 * always one less than what we would expect. Ie. just after
10857 * start of vblank, which also occurs at start of hsync (on the
10858 * last active line), the scanline counter will read vblank_start-1.
10859 *
10860 * On gen2 the scanline counter starts counting from 1 instead
10861 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10862 * to keep the value positive), instead of adding one.
10863 *
10864 * On HSW+ the behaviour of the scanline counter depends on the output
10865 * type. For DP ports it behaves like most other platforms, but on HDMI
10866 * there's an extra 1 line difference. So we need to add two instead of
10867 * one to the value.
10868 */
10869 if (IS_GEN2(dev)) {
10870 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10871 int vtotal;
10872
10873 vtotal = mode->crtc_vtotal;
10874 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10875 vtotal /= 2;
10876
10877 crtc->scanline_offset = vtotal - 1;
10878 } else if (HAS_DDI(dev) &&
10879 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10880 crtc->scanline_offset = 2;
10881 } else
10882 crtc->scanline_offset = 1;
10883 }
10884
10885 static struct intel_crtc_state *
10886 intel_modeset_compute_config(struct drm_crtc *crtc,
10887 struct drm_display_mode *mode,
10888 struct drm_framebuffer *fb,
10889 unsigned *modeset_pipes,
10890 unsigned *prepare_pipes,
10891 unsigned *disable_pipes)
10892 {
10893 struct intel_crtc_state *pipe_config = NULL;
10894
10895 intel_modeset_affected_pipes(crtc, modeset_pipes,
10896 prepare_pipes, disable_pipes);
10897
10898 if ((*modeset_pipes) == 0)
10899 goto out;
10900
10901 /*
10902 * Note this needs changes when we start tracking multiple modes
10903 * and crtcs. At that point we'll need to compute the whole config
10904 * (i.e. one pipe_config for each crtc) rather than just the one
10905 * for this crtc.
10906 */
10907 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10908 if (IS_ERR(pipe_config)) {
10909 goto out;
10910 }
10911 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10912 "[modeset]");
10913
10914 out:
10915 return pipe_config;
10916 }
10917
10918 static int __intel_set_mode(struct drm_crtc *crtc,
10919 struct drm_display_mode *mode,
10920 int x, int y, struct drm_framebuffer *fb,
10921 struct intel_crtc_state *pipe_config,
10922 unsigned modeset_pipes,
10923 unsigned prepare_pipes,
10924 unsigned disable_pipes)
10925 {
10926 struct drm_device *dev = crtc->dev;
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 struct drm_display_mode *saved_mode;
10929 struct intel_crtc *intel_crtc;
10930 int ret = 0;
10931
10932 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10933 if (!saved_mode)
10934 return -ENOMEM;
10935
10936 *saved_mode = crtc->mode;
10937
10938 if (modeset_pipes)
10939 to_intel_crtc(crtc)->new_config = pipe_config;
10940
10941 /*
10942 * See if the config requires any additional preparation, e.g.
10943 * to adjust global state with pipes off. We need to do this
10944 * here so we can get the modeset_pipe updated config for the new
10945 * mode set on this crtc. For other crtcs we need to use the
10946 * adjusted_mode bits in the crtc directly.
10947 */
10948 if (IS_VALLEYVIEW(dev)) {
10949 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10950
10951 /* may have added more to prepare_pipes than we should */
10952 prepare_pipes &= ~disable_pipes;
10953 }
10954
10955 if (dev_priv->display.crtc_compute_clock) {
10956 unsigned clear_pipes = modeset_pipes | disable_pipes;
10957
10958 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10959 if (ret)
10960 goto done;
10961
10962 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10963 struct intel_crtc_state *state = intel_crtc->new_config;
10964 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10965 state);
10966 if (ret) {
10967 intel_shared_dpll_abort_config(dev_priv);
10968 goto done;
10969 }
10970 }
10971 }
10972
10973 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10974 intel_crtc_disable(&intel_crtc->base);
10975
10976 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10977 if (intel_crtc->base.enabled)
10978 dev_priv->display.crtc_disable(&intel_crtc->base);
10979 }
10980
10981 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10982 * to set it here already despite that we pass it down the callchain.
10983 *
10984 * Note we'll need to fix this up when we start tracking multiple
10985 * pipes; here we assume a single modeset_pipe and only track the
10986 * single crtc and mode.
10987 */
10988 if (modeset_pipes) {
10989 crtc->mode = *mode;
10990 /* mode_set/enable/disable functions rely on a correct pipe
10991 * config. */
10992 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
10993
10994 /*
10995 * Calculate and store various constants which
10996 * are later needed by vblank and swap-completion
10997 * timestamping. They are derived from true hwmode.
10998 */
10999 drm_calc_timestamping_constants(crtc,
11000 &pipe_config->base.adjusted_mode);
11001 }
11002
11003 /* Only after disabling all output pipelines that will be changed can we
11004 * update the the output configuration. */
11005 intel_modeset_update_state(dev, prepare_pipes);
11006
11007 modeset_update_crtc_power_domains(dev);
11008
11009 /* Set up the DPLL and any encoders state that needs to adjust or depend
11010 * on the DPLL.
11011 */
11012 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11013 struct drm_plane *primary = intel_crtc->base.primary;
11014 int vdisplay, hdisplay;
11015
11016 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11017 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11018 fb, 0, 0,
11019 hdisplay, vdisplay,
11020 x << 16, y << 16,
11021 hdisplay << 16, vdisplay << 16);
11022 }
11023
11024 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11025 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11026 update_scanline_offset(intel_crtc);
11027
11028 dev_priv->display.crtc_enable(&intel_crtc->base);
11029 }
11030
11031 /* FIXME: add subpixel order */
11032 done:
11033 if (ret && crtc->enabled)
11034 crtc->mode = *saved_mode;
11035
11036 kfree(saved_mode);
11037 return ret;
11038 }
11039
11040 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11041 struct drm_display_mode *mode,
11042 int x, int y, struct drm_framebuffer *fb,
11043 struct intel_crtc_state *pipe_config,
11044 unsigned modeset_pipes,
11045 unsigned prepare_pipes,
11046 unsigned disable_pipes)
11047 {
11048 int ret;
11049
11050 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11051 prepare_pipes, disable_pipes);
11052
11053 if (ret == 0)
11054 intel_modeset_check_state(crtc->dev);
11055
11056 return ret;
11057 }
11058
11059 static int intel_set_mode(struct drm_crtc *crtc,
11060 struct drm_display_mode *mode,
11061 int x, int y, struct drm_framebuffer *fb)
11062 {
11063 struct intel_crtc_state *pipe_config;
11064 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11065
11066 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11067 &modeset_pipes,
11068 &prepare_pipes,
11069 &disable_pipes);
11070
11071 if (IS_ERR(pipe_config))
11072 return PTR_ERR(pipe_config);
11073
11074 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11075 modeset_pipes, prepare_pipes,
11076 disable_pipes);
11077 }
11078
11079 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11080 {
11081 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11082 }
11083
11084 #undef for_each_intel_crtc_masked
11085
11086 static void intel_set_config_free(struct intel_set_config *config)
11087 {
11088 if (!config)
11089 return;
11090
11091 kfree(config->save_connector_encoders);
11092 kfree(config->save_encoder_crtcs);
11093 kfree(config->save_crtc_enabled);
11094 kfree(config);
11095 }
11096
11097 static int intel_set_config_save_state(struct drm_device *dev,
11098 struct intel_set_config *config)
11099 {
11100 struct drm_crtc *crtc;
11101 struct drm_encoder *encoder;
11102 struct drm_connector *connector;
11103 int count;
11104
11105 config->save_crtc_enabled =
11106 kcalloc(dev->mode_config.num_crtc,
11107 sizeof(bool), GFP_KERNEL);
11108 if (!config->save_crtc_enabled)
11109 return -ENOMEM;
11110
11111 config->save_encoder_crtcs =
11112 kcalloc(dev->mode_config.num_encoder,
11113 sizeof(struct drm_crtc *), GFP_KERNEL);
11114 if (!config->save_encoder_crtcs)
11115 return -ENOMEM;
11116
11117 config->save_connector_encoders =
11118 kcalloc(dev->mode_config.num_connector,
11119 sizeof(struct drm_encoder *), GFP_KERNEL);
11120 if (!config->save_connector_encoders)
11121 return -ENOMEM;
11122
11123 /* Copy data. Note that driver private data is not affected.
11124 * Should anything bad happen only the expected state is
11125 * restored, not the drivers personal bookkeeping.
11126 */
11127 count = 0;
11128 for_each_crtc(dev, crtc) {
11129 config->save_crtc_enabled[count++] = crtc->enabled;
11130 }
11131
11132 count = 0;
11133 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11134 config->save_encoder_crtcs[count++] = encoder->crtc;
11135 }
11136
11137 count = 0;
11138 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11139 config->save_connector_encoders[count++] = connector->encoder;
11140 }
11141
11142 return 0;
11143 }
11144
11145 static void intel_set_config_restore_state(struct drm_device *dev,
11146 struct intel_set_config *config)
11147 {
11148 struct intel_crtc *crtc;
11149 struct intel_encoder *encoder;
11150 struct intel_connector *connector;
11151 int count;
11152
11153 count = 0;
11154 for_each_intel_crtc(dev, crtc) {
11155 crtc->new_enabled = config->save_crtc_enabled[count++];
11156
11157 if (crtc->new_enabled)
11158 crtc->new_config = crtc->config;
11159 else
11160 crtc->new_config = NULL;
11161 }
11162
11163 count = 0;
11164 for_each_intel_encoder(dev, encoder) {
11165 encoder->new_crtc =
11166 to_intel_crtc(config->save_encoder_crtcs[count++]);
11167 }
11168
11169 count = 0;
11170 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11171 connector->new_encoder =
11172 to_intel_encoder(config->save_connector_encoders[count++]);
11173 }
11174 }
11175
11176 static bool
11177 is_crtc_connector_off(struct drm_mode_set *set)
11178 {
11179 int i;
11180
11181 if (set->num_connectors == 0)
11182 return false;
11183
11184 if (WARN_ON(set->connectors == NULL))
11185 return false;
11186
11187 for (i = 0; i < set->num_connectors; i++)
11188 if (set->connectors[i]->encoder &&
11189 set->connectors[i]->encoder->crtc == set->crtc &&
11190 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11191 return true;
11192
11193 return false;
11194 }
11195
11196 static void
11197 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11198 struct intel_set_config *config)
11199 {
11200
11201 /* We should be able to check here if the fb has the same properties
11202 * and then just flip_or_move it */
11203 if (is_crtc_connector_off(set)) {
11204 config->mode_changed = true;
11205 } else if (set->crtc->primary->fb != set->fb) {
11206 /*
11207 * If we have no fb, we can only flip as long as the crtc is
11208 * active, otherwise we need a full mode set. The crtc may
11209 * be active if we've only disabled the primary plane, or
11210 * in fastboot situations.
11211 */
11212 if (set->crtc->primary->fb == NULL) {
11213 struct intel_crtc *intel_crtc =
11214 to_intel_crtc(set->crtc);
11215
11216 if (intel_crtc->active) {
11217 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11218 config->fb_changed = true;
11219 } else {
11220 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11221 config->mode_changed = true;
11222 }
11223 } else if (set->fb == NULL) {
11224 config->mode_changed = true;
11225 } else if (set->fb->pixel_format !=
11226 set->crtc->primary->fb->pixel_format) {
11227 config->mode_changed = true;
11228 } else {
11229 config->fb_changed = true;
11230 }
11231 }
11232
11233 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11234 config->fb_changed = true;
11235
11236 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11237 DRM_DEBUG_KMS("modes are different, full mode set\n");
11238 drm_mode_debug_printmodeline(&set->crtc->mode);
11239 drm_mode_debug_printmodeline(set->mode);
11240 config->mode_changed = true;
11241 }
11242
11243 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11244 set->crtc->base.id, config->mode_changed, config->fb_changed);
11245 }
11246
11247 static int
11248 intel_modeset_stage_output_state(struct drm_device *dev,
11249 struct drm_mode_set *set,
11250 struct intel_set_config *config)
11251 {
11252 struct intel_connector *connector;
11253 struct intel_encoder *encoder;
11254 struct intel_crtc *crtc;
11255 int ro;
11256
11257 /* The upper layers ensure that we either disable a crtc or have a list
11258 * of connectors. For paranoia, double-check this. */
11259 WARN_ON(!set->fb && (set->num_connectors != 0));
11260 WARN_ON(set->fb && (set->num_connectors == 0));
11261
11262 list_for_each_entry(connector, &dev->mode_config.connector_list,
11263 base.head) {
11264 /* Otherwise traverse passed in connector list and get encoders
11265 * for them. */
11266 for (ro = 0; ro < set->num_connectors; ro++) {
11267 if (set->connectors[ro] == &connector->base) {
11268 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11269 break;
11270 }
11271 }
11272
11273 /* If we disable the crtc, disable all its connectors. Also, if
11274 * the connector is on the changing crtc but not on the new
11275 * connector list, disable it. */
11276 if ((!set->fb || ro == set->num_connectors) &&
11277 connector->base.encoder &&
11278 connector->base.encoder->crtc == set->crtc) {
11279 connector->new_encoder = NULL;
11280
11281 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11282 connector->base.base.id,
11283 connector->base.name);
11284 }
11285
11286
11287 if (&connector->new_encoder->base != connector->base.encoder) {
11288 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11289 config->mode_changed = true;
11290 }
11291 }
11292 /* connector->new_encoder is now updated for all connectors. */
11293
11294 /* Update crtc of enabled connectors. */
11295 list_for_each_entry(connector, &dev->mode_config.connector_list,
11296 base.head) {
11297 struct drm_crtc *new_crtc;
11298
11299 if (!connector->new_encoder)
11300 continue;
11301
11302 new_crtc = connector->new_encoder->base.crtc;
11303
11304 for (ro = 0; ro < set->num_connectors; ro++) {
11305 if (set->connectors[ro] == &connector->base)
11306 new_crtc = set->crtc;
11307 }
11308
11309 /* Make sure the new CRTC will work with the encoder */
11310 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11311 new_crtc)) {
11312 return -EINVAL;
11313 }
11314 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11315
11316 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11317 connector->base.base.id,
11318 connector->base.name,
11319 new_crtc->base.id);
11320 }
11321
11322 /* Check for any encoders that needs to be disabled. */
11323 for_each_intel_encoder(dev, encoder) {
11324 int num_connectors = 0;
11325 list_for_each_entry(connector,
11326 &dev->mode_config.connector_list,
11327 base.head) {
11328 if (connector->new_encoder == encoder) {
11329 WARN_ON(!connector->new_encoder->new_crtc);
11330 num_connectors++;
11331 }
11332 }
11333
11334 if (num_connectors == 0)
11335 encoder->new_crtc = NULL;
11336 else if (num_connectors > 1)
11337 return -EINVAL;
11338
11339 /* Only now check for crtc changes so we don't miss encoders
11340 * that will be disabled. */
11341 if (&encoder->new_crtc->base != encoder->base.crtc) {
11342 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11343 config->mode_changed = true;
11344 }
11345 }
11346 /* Now we've also updated encoder->new_crtc for all encoders. */
11347 list_for_each_entry(connector, &dev->mode_config.connector_list,
11348 base.head) {
11349 if (connector->new_encoder)
11350 if (connector->new_encoder != connector->encoder)
11351 connector->encoder = connector->new_encoder;
11352 }
11353 for_each_intel_crtc(dev, crtc) {
11354 crtc->new_enabled = false;
11355
11356 for_each_intel_encoder(dev, encoder) {
11357 if (encoder->new_crtc == crtc) {
11358 crtc->new_enabled = true;
11359 break;
11360 }
11361 }
11362
11363 if (crtc->new_enabled != crtc->base.enabled) {
11364 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11365 crtc->new_enabled ? "en" : "dis");
11366 config->mode_changed = true;
11367 }
11368
11369 if (crtc->new_enabled)
11370 crtc->new_config = crtc->config;
11371 else
11372 crtc->new_config = NULL;
11373 }
11374
11375 return 0;
11376 }
11377
11378 static void disable_crtc_nofb(struct intel_crtc *crtc)
11379 {
11380 struct drm_device *dev = crtc->base.dev;
11381 struct intel_encoder *encoder;
11382 struct intel_connector *connector;
11383
11384 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11385 pipe_name(crtc->pipe));
11386
11387 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11388 if (connector->new_encoder &&
11389 connector->new_encoder->new_crtc == crtc)
11390 connector->new_encoder = NULL;
11391 }
11392
11393 for_each_intel_encoder(dev, encoder) {
11394 if (encoder->new_crtc == crtc)
11395 encoder->new_crtc = NULL;
11396 }
11397
11398 crtc->new_enabled = false;
11399 crtc->new_config = NULL;
11400 }
11401
11402 static int intel_crtc_set_config(struct drm_mode_set *set)
11403 {
11404 struct drm_device *dev;
11405 struct drm_mode_set save_set;
11406 struct intel_set_config *config;
11407 struct intel_crtc_state *pipe_config;
11408 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11409 int ret;
11410
11411 BUG_ON(!set);
11412 BUG_ON(!set->crtc);
11413 BUG_ON(!set->crtc->helper_private);
11414
11415 /* Enforce sane interface api - has been abused by the fb helper. */
11416 BUG_ON(!set->mode && set->fb);
11417 BUG_ON(set->fb && set->num_connectors == 0);
11418
11419 if (set->fb) {
11420 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11421 set->crtc->base.id, set->fb->base.id,
11422 (int)set->num_connectors, set->x, set->y);
11423 } else {
11424 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11425 }
11426
11427 dev = set->crtc->dev;
11428
11429 ret = -ENOMEM;
11430 config = kzalloc(sizeof(*config), GFP_KERNEL);
11431 if (!config)
11432 goto out_config;
11433
11434 ret = intel_set_config_save_state(dev, config);
11435 if (ret)
11436 goto out_config;
11437
11438 save_set.crtc = set->crtc;
11439 save_set.mode = &set->crtc->mode;
11440 save_set.x = set->crtc->x;
11441 save_set.y = set->crtc->y;
11442 save_set.fb = set->crtc->primary->fb;
11443
11444 /* Compute whether we need a full modeset, only an fb base update or no
11445 * change at all. In the future we might also check whether only the
11446 * mode changed, e.g. for LVDS where we only change the panel fitter in
11447 * such cases. */
11448 intel_set_config_compute_mode_changes(set, config);
11449
11450 ret = intel_modeset_stage_output_state(dev, set, config);
11451 if (ret)
11452 goto fail;
11453
11454 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11455 set->fb,
11456 &modeset_pipes,
11457 &prepare_pipes,
11458 &disable_pipes);
11459 if (IS_ERR(pipe_config)) {
11460 ret = PTR_ERR(pipe_config);
11461 goto fail;
11462 } else if (pipe_config) {
11463 if (pipe_config->has_audio !=
11464 to_intel_crtc(set->crtc)->config->has_audio)
11465 config->mode_changed = true;
11466
11467 /*
11468 * Note we have an issue here with infoframes: current code
11469 * only updates them on the full mode set path per hw
11470 * requirements. So here we should be checking for any
11471 * required changes and forcing a mode set.
11472 */
11473 }
11474
11475 /* set_mode will free it in the mode_changed case */
11476 if (!config->mode_changed)
11477 kfree(pipe_config);
11478
11479 intel_update_pipe_size(to_intel_crtc(set->crtc));
11480
11481 if (config->mode_changed) {
11482 ret = intel_set_mode_pipes(set->crtc, set->mode,
11483 set->x, set->y, set->fb, pipe_config,
11484 modeset_pipes, prepare_pipes,
11485 disable_pipes);
11486 } else if (config->fb_changed) {
11487 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11488 struct drm_plane *primary = set->crtc->primary;
11489 int vdisplay, hdisplay;
11490
11491 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11492 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11493 0, 0, hdisplay, vdisplay,
11494 set->x << 16, set->y << 16,
11495 hdisplay << 16, vdisplay << 16);
11496
11497 /*
11498 * We need to make sure the primary plane is re-enabled if it
11499 * has previously been turned off.
11500 */
11501 if (!intel_crtc->primary_enabled && ret == 0) {
11502 WARN_ON(!intel_crtc->active);
11503 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11504 }
11505
11506 /*
11507 * In the fastboot case this may be our only check of the
11508 * state after boot. It would be better to only do it on
11509 * the first update, but we don't have a nice way of doing that
11510 * (and really, set_config isn't used much for high freq page
11511 * flipping, so increasing its cost here shouldn't be a big
11512 * deal).
11513 */
11514 if (i915.fastboot && ret == 0)
11515 intel_modeset_check_state(set->crtc->dev);
11516 }
11517
11518 if (ret) {
11519 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11520 set->crtc->base.id, ret);
11521 fail:
11522 intel_set_config_restore_state(dev, config);
11523
11524 /*
11525 * HACK: if the pipe was on, but we didn't have a framebuffer,
11526 * force the pipe off to avoid oopsing in the modeset code
11527 * due to fb==NULL. This should only happen during boot since
11528 * we don't yet reconstruct the FB from the hardware state.
11529 */
11530 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11531 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11532
11533 /* Try to restore the config */
11534 if (config->mode_changed &&
11535 intel_set_mode(save_set.crtc, save_set.mode,
11536 save_set.x, save_set.y, save_set.fb))
11537 DRM_ERROR("failed to restore config after modeset failure\n");
11538 }
11539
11540 out_config:
11541 intel_set_config_free(config);
11542 return ret;
11543 }
11544
11545 static const struct drm_crtc_funcs intel_crtc_funcs = {
11546 .gamma_set = intel_crtc_gamma_set,
11547 .set_config = intel_crtc_set_config,
11548 .destroy = intel_crtc_destroy,
11549 .page_flip = intel_crtc_page_flip,
11550 };
11551
11552 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11553 struct intel_shared_dpll *pll,
11554 struct intel_dpll_hw_state *hw_state)
11555 {
11556 uint32_t val;
11557
11558 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11559 return false;
11560
11561 val = I915_READ(PCH_DPLL(pll->id));
11562 hw_state->dpll = val;
11563 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11564 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11565
11566 return val & DPLL_VCO_ENABLE;
11567 }
11568
11569 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11570 struct intel_shared_dpll *pll)
11571 {
11572 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11573 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11574 }
11575
11576 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11577 struct intel_shared_dpll *pll)
11578 {
11579 /* PCH refclock must be enabled first */
11580 ibx_assert_pch_refclk_enabled(dev_priv);
11581
11582 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11583
11584 /* Wait for the clocks to stabilize. */
11585 POSTING_READ(PCH_DPLL(pll->id));
11586 udelay(150);
11587
11588 /* The pixel multiplier can only be updated once the
11589 * DPLL is enabled and the clocks are stable.
11590 *
11591 * So write it again.
11592 */
11593 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11594 POSTING_READ(PCH_DPLL(pll->id));
11595 udelay(200);
11596 }
11597
11598 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11599 struct intel_shared_dpll *pll)
11600 {
11601 struct drm_device *dev = dev_priv->dev;
11602 struct intel_crtc *crtc;
11603
11604 /* Make sure no transcoder isn't still depending on us. */
11605 for_each_intel_crtc(dev, crtc) {
11606 if (intel_crtc_to_shared_dpll(crtc) == pll)
11607 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11608 }
11609
11610 I915_WRITE(PCH_DPLL(pll->id), 0);
11611 POSTING_READ(PCH_DPLL(pll->id));
11612 udelay(200);
11613 }
11614
11615 static char *ibx_pch_dpll_names[] = {
11616 "PCH DPLL A",
11617 "PCH DPLL B",
11618 };
11619
11620 static void ibx_pch_dpll_init(struct drm_device *dev)
11621 {
11622 struct drm_i915_private *dev_priv = dev->dev_private;
11623 int i;
11624
11625 dev_priv->num_shared_dpll = 2;
11626
11627 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11628 dev_priv->shared_dplls[i].id = i;
11629 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11630 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11631 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11632 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11633 dev_priv->shared_dplls[i].get_hw_state =
11634 ibx_pch_dpll_get_hw_state;
11635 }
11636 }
11637
11638 static void intel_shared_dpll_init(struct drm_device *dev)
11639 {
11640 struct drm_i915_private *dev_priv = dev->dev_private;
11641
11642 if (HAS_DDI(dev))
11643 intel_ddi_pll_init(dev);
11644 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11645 ibx_pch_dpll_init(dev);
11646 else
11647 dev_priv->num_shared_dpll = 0;
11648
11649 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11650 }
11651
11652 /**
11653 * intel_prepare_plane_fb - Prepare fb for usage on plane
11654 * @plane: drm plane to prepare for
11655 * @fb: framebuffer to prepare for presentation
11656 *
11657 * Prepares a framebuffer for usage on a display plane. Generally this
11658 * involves pinning the underlying object and updating the frontbuffer tracking
11659 * bits. Some older platforms need special physical address handling for
11660 * cursor planes.
11661 *
11662 * Returns 0 on success, negative error code on failure.
11663 */
11664 int
11665 intel_prepare_plane_fb(struct drm_plane *plane,
11666 struct drm_framebuffer *fb)
11667 {
11668 struct drm_device *dev = plane->dev;
11669 struct intel_plane *intel_plane = to_intel_plane(plane);
11670 enum pipe pipe = intel_plane->pipe;
11671 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11672 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11673 unsigned frontbuffer_bits = 0;
11674 int ret = 0;
11675
11676 if (!obj)
11677 return 0;
11678
11679 switch (plane->type) {
11680 case DRM_PLANE_TYPE_PRIMARY:
11681 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11682 break;
11683 case DRM_PLANE_TYPE_CURSOR:
11684 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11685 break;
11686 case DRM_PLANE_TYPE_OVERLAY:
11687 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11688 break;
11689 }
11690
11691 mutex_lock(&dev->struct_mutex);
11692
11693 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11694 INTEL_INFO(dev)->cursor_needs_physical) {
11695 int align = IS_I830(dev) ? 16 * 1024 : 256;
11696 ret = i915_gem_object_attach_phys(obj, align);
11697 if (ret)
11698 DRM_DEBUG_KMS("failed to attach phys object\n");
11699 } else {
11700 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11701 }
11702
11703 if (ret == 0)
11704 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11705
11706 mutex_unlock(&dev->struct_mutex);
11707
11708 return ret;
11709 }
11710
11711 /**
11712 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11713 * @plane: drm plane to clean up for
11714 * @fb: old framebuffer that was on plane
11715 *
11716 * Cleans up a framebuffer that has just been removed from a plane.
11717 */
11718 void
11719 intel_cleanup_plane_fb(struct drm_plane *plane,
11720 struct drm_framebuffer *fb)
11721 {
11722 struct drm_device *dev = plane->dev;
11723 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11724
11725 if (WARN_ON(!obj))
11726 return;
11727
11728 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11729 !INTEL_INFO(dev)->cursor_needs_physical) {
11730 mutex_lock(&dev->struct_mutex);
11731 intel_unpin_fb_obj(obj);
11732 mutex_unlock(&dev->struct_mutex);
11733 }
11734 }
11735
11736 static int
11737 intel_check_primary_plane(struct drm_plane *plane,
11738 struct intel_plane_state *state)
11739 {
11740 struct drm_device *dev = plane->dev;
11741 struct drm_i915_private *dev_priv = dev->dev_private;
11742 struct drm_crtc *crtc = state->base.crtc;
11743 struct intel_crtc *intel_crtc;
11744 struct intel_plane *intel_plane = to_intel_plane(plane);
11745 struct drm_framebuffer *fb = state->base.fb;
11746 struct drm_rect *dest = &state->dst;
11747 struct drm_rect *src = &state->src;
11748 const struct drm_rect *clip = &state->clip;
11749 int ret;
11750
11751 crtc = crtc ? crtc : plane->crtc;
11752 intel_crtc = to_intel_crtc(crtc);
11753
11754 ret = drm_plane_helper_check_update(plane, crtc, fb,
11755 src, dest, clip,
11756 DRM_PLANE_HELPER_NO_SCALING,
11757 DRM_PLANE_HELPER_NO_SCALING,
11758 false, true, &state->visible);
11759 if (ret)
11760 return ret;
11761
11762 if (intel_crtc->active) {
11763 intel_crtc->atomic.wait_for_flips = true;
11764
11765 /*
11766 * FBC does not work on some platforms for rotated
11767 * planes, so disable it when rotation is not 0 and
11768 * update it when rotation is set back to 0.
11769 *
11770 * FIXME: This is redundant with the fbc update done in
11771 * the primary plane enable function except that that
11772 * one is done too late. We eventually need to unify
11773 * this.
11774 */
11775 if (intel_crtc->primary_enabled &&
11776 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11777 dev_priv->fbc.plane == intel_crtc->plane &&
11778 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11779 intel_crtc->atomic.disable_fbc = true;
11780 }
11781
11782 if (state->visible) {
11783 /*
11784 * BDW signals flip done immediately if the plane
11785 * is disabled, even if the plane enable is already
11786 * armed to occur at the next vblank :(
11787 */
11788 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11789 intel_crtc->atomic.wait_vblank = true;
11790 }
11791
11792 intel_crtc->atomic.fb_bits |=
11793 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11794
11795 intel_crtc->atomic.update_fbc = true;
11796 }
11797
11798 return 0;
11799 }
11800
11801 static void
11802 intel_commit_primary_plane(struct drm_plane *plane,
11803 struct intel_plane_state *state)
11804 {
11805 struct drm_crtc *crtc = state->base.crtc;
11806 struct drm_framebuffer *fb = state->base.fb;
11807 struct drm_device *dev = plane->dev;
11808 struct drm_i915_private *dev_priv = dev->dev_private;
11809 struct intel_crtc *intel_crtc;
11810 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11811 struct intel_plane *intel_plane = to_intel_plane(plane);
11812 struct drm_rect *src = &state->src;
11813
11814 crtc = crtc ? crtc : plane->crtc;
11815 intel_crtc = to_intel_crtc(crtc);
11816
11817 plane->fb = fb;
11818 crtc->x = src->x1 >> 16;
11819 crtc->y = src->y1 >> 16;
11820
11821 intel_plane->obj = obj;
11822
11823 if (intel_crtc->active) {
11824 if (state->visible) {
11825 /* FIXME: kill this fastboot hack */
11826 intel_update_pipe_size(intel_crtc);
11827
11828 intel_crtc->primary_enabled = true;
11829
11830 dev_priv->display.update_primary_plane(crtc, plane->fb,
11831 crtc->x, crtc->y);
11832 } else {
11833 /*
11834 * If clipping results in a non-visible primary plane,
11835 * we'll disable the primary plane. Note that this is
11836 * a bit different than what happens if userspace
11837 * explicitly disables the plane by passing fb=0
11838 * because plane->fb still gets set and pinned.
11839 */
11840 intel_disable_primary_hw_plane(plane, crtc);
11841 }
11842 }
11843 }
11844
11845 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11846 {
11847 struct drm_device *dev = crtc->dev;
11848 struct drm_i915_private *dev_priv = dev->dev_private;
11849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11850 struct intel_plane *intel_plane;
11851 struct drm_plane *p;
11852 unsigned fb_bits = 0;
11853
11854 /* Track fb's for any planes being disabled */
11855 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11856 intel_plane = to_intel_plane(p);
11857
11858 if (intel_crtc->atomic.disabled_planes &
11859 (1 << drm_plane_index(p))) {
11860 switch (p->type) {
11861 case DRM_PLANE_TYPE_PRIMARY:
11862 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11863 break;
11864 case DRM_PLANE_TYPE_CURSOR:
11865 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11866 break;
11867 case DRM_PLANE_TYPE_OVERLAY:
11868 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11869 break;
11870 }
11871
11872 mutex_lock(&dev->struct_mutex);
11873 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
11874 mutex_unlock(&dev->struct_mutex);
11875 }
11876 }
11877
11878 if (intel_crtc->atomic.wait_for_flips)
11879 intel_crtc_wait_for_pending_flips(crtc);
11880
11881 if (intel_crtc->atomic.disable_fbc)
11882 intel_fbc_disable(dev);
11883
11884 if (intel_crtc->atomic.pre_disable_primary)
11885 intel_pre_disable_primary(crtc);
11886
11887 if (intel_crtc->atomic.update_wm)
11888 intel_update_watermarks(crtc);
11889
11890 intel_runtime_pm_get(dev_priv);
11891
11892 /* Perform vblank evasion around commit operation */
11893 if (intel_crtc->active)
11894 intel_crtc->atomic.evade =
11895 intel_pipe_update_start(intel_crtc,
11896 &intel_crtc->atomic.start_vbl_count);
11897 }
11898
11899 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
11900 {
11901 struct drm_device *dev = crtc->dev;
11902 struct drm_i915_private *dev_priv = dev->dev_private;
11903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11904 struct drm_plane *p;
11905
11906 if (intel_crtc->atomic.evade)
11907 intel_pipe_update_end(intel_crtc,
11908 intel_crtc->atomic.start_vbl_count);
11909
11910 intel_runtime_pm_put(dev_priv);
11911
11912 if (intel_crtc->atomic.wait_vblank)
11913 intel_wait_for_vblank(dev, intel_crtc->pipe);
11914
11915 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
11916
11917 if (intel_crtc->atomic.update_fbc) {
11918 mutex_lock(&dev->struct_mutex);
11919 intel_fbc_update(dev);
11920 mutex_unlock(&dev->struct_mutex);
11921 }
11922
11923 if (intel_crtc->atomic.post_enable_primary)
11924 intel_post_enable_primary(crtc);
11925
11926 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
11927 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
11928 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
11929 false, false);
11930
11931 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
11932 }
11933
11934 /**
11935 * intel_plane_destroy - destroy a plane
11936 * @plane: plane to destroy
11937 *
11938 * Common destruction function for all types of planes (primary, cursor,
11939 * sprite).
11940 */
11941 void intel_plane_destroy(struct drm_plane *plane)
11942 {
11943 struct intel_plane *intel_plane = to_intel_plane(plane);
11944 drm_plane_cleanup(plane);
11945 kfree(intel_plane);
11946 }
11947
11948 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11949 .update_plane = drm_plane_helper_update,
11950 .disable_plane = drm_plane_helper_disable,
11951 .destroy = intel_plane_destroy,
11952 .set_property = intel_plane_set_property,
11953 .atomic_duplicate_state = intel_plane_duplicate_state,
11954 .atomic_destroy_state = intel_plane_destroy_state,
11955
11956 };
11957
11958 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11959 int pipe)
11960 {
11961 struct intel_plane *primary;
11962 const uint32_t *intel_primary_formats;
11963 int num_formats;
11964
11965 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11966 if (primary == NULL)
11967 return NULL;
11968
11969 primary->base.state = intel_plane_duplicate_state(&primary->base);
11970 if (primary->base.state == NULL) {
11971 kfree(primary);
11972 return NULL;
11973 }
11974
11975 primary->can_scale = false;
11976 primary->max_downscale = 1;
11977 primary->pipe = pipe;
11978 primary->plane = pipe;
11979 primary->rotation = BIT(DRM_ROTATE_0);
11980 primary->check_plane = intel_check_primary_plane;
11981 primary->commit_plane = intel_commit_primary_plane;
11982 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11983 primary->plane = !pipe;
11984
11985 if (INTEL_INFO(dev)->gen <= 3) {
11986 intel_primary_formats = intel_primary_formats_gen2;
11987 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11988 } else {
11989 intel_primary_formats = intel_primary_formats_gen4;
11990 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11991 }
11992
11993 drm_universal_plane_init(dev, &primary->base, 0,
11994 &intel_primary_plane_funcs,
11995 intel_primary_formats, num_formats,
11996 DRM_PLANE_TYPE_PRIMARY);
11997
11998 if (INTEL_INFO(dev)->gen >= 4) {
11999 if (!dev->mode_config.rotation_property)
12000 dev->mode_config.rotation_property =
12001 drm_mode_create_rotation_property(dev,
12002 BIT(DRM_ROTATE_0) |
12003 BIT(DRM_ROTATE_180));
12004 if (dev->mode_config.rotation_property)
12005 drm_object_attach_property(&primary->base.base,
12006 dev->mode_config.rotation_property,
12007 primary->rotation);
12008 }
12009
12010 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12011
12012 return &primary->base;
12013 }
12014
12015 static int
12016 intel_check_cursor_plane(struct drm_plane *plane,
12017 struct intel_plane_state *state)
12018 {
12019 struct drm_crtc *crtc = state->base.crtc;
12020 struct drm_device *dev = plane->dev;
12021 struct drm_framebuffer *fb = state->base.fb;
12022 struct drm_rect *dest = &state->dst;
12023 struct drm_rect *src = &state->src;
12024 const struct drm_rect *clip = &state->clip;
12025 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12026 struct intel_crtc *intel_crtc;
12027 unsigned stride;
12028 int ret;
12029
12030 crtc = crtc ? crtc : plane->crtc;
12031 intel_crtc = to_intel_crtc(crtc);
12032
12033 ret = drm_plane_helper_check_update(plane, crtc, fb,
12034 src, dest, clip,
12035 DRM_PLANE_HELPER_NO_SCALING,
12036 DRM_PLANE_HELPER_NO_SCALING,
12037 true, true, &state->visible);
12038 if (ret)
12039 return ret;
12040
12041
12042 /* if we want to turn off the cursor ignore width and height */
12043 if (!obj)
12044 goto finish;
12045
12046 /* Check for which cursor types we support */
12047 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12048 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12049 state->base.crtc_w, state->base.crtc_h);
12050 return -EINVAL;
12051 }
12052
12053 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12054 if (obj->base.size < stride * state->base.crtc_h) {
12055 DRM_DEBUG_KMS("buffer is too small\n");
12056 return -ENOMEM;
12057 }
12058
12059 if (fb == crtc->cursor->fb)
12060 return 0;
12061
12062 /* we only need to pin inside GTT if cursor is non-phy */
12063 mutex_lock(&dev->struct_mutex);
12064 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12065 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12066 ret = -EINVAL;
12067 }
12068 mutex_unlock(&dev->struct_mutex);
12069
12070 finish:
12071 if (intel_crtc->active) {
12072 if (intel_crtc->cursor_width != state->base.crtc_w)
12073 intel_crtc->atomic.update_wm = true;
12074
12075 intel_crtc->atomic.fb_bits |=
12076 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12077 }
12078
12079 return ret;
12080 }
12081
12082 static void
12083 intel_commit_cursor_plane(struct drm_plane *plane,
12084 struct intel_plane_state *state)
12085 {
12086 struct drm_crtc *crtc = state->base.crtc;
12087 struct drm_device *dev = plane->dev;
12088 struct intel_crtc *intel_crtc;
12089 struct intel_plane *intel_plane = to_intel_plane(plane);
12090 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12091 uint32_t addr;
12092
12093 crtc = crtc ? crtc : plane->crtc;
12094 intel_crtc = to_intel_crtc(crtc);
12095
12096 plane->fb = state->base.fb;
12097 crtc->cursor_x = state->base.crtc_x;
12098 crtc->cursor_y = state->base.crtc_y;
12099
12100 intel_plane->obj = obj;
12101
12102 if (intel_crtc->cursor_bo == obj)
12103 goto update;
12104
12105 if (!obj)
12106 addr = 0;
12107 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12108 addr = i915_gem_obj_ggtt_offset(obj);
12109 else
12110 addr = obj->phys_handle->busaddr;
12111
12112 intel_crtc->cursor_addr = addr;
12113 intel_crtc->cursor_bo = obj;
12114 update:
12115 intel_crtc->cursor_width = state->base.crtc_w;
12116 intel_crtc->cursor_height = state->base.crtc_h;
12117
12118 if (intel_crtc->active)
12119 intel_crtc_update_cursor(crtc, state->visible);
12120 }
12121
12122 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12123 .update_plane = drm_plane_helper_update,
12124 .disable_plane = drm_plane_helper_disable,
12125 .destroy = intel_plane_destroy,
12126 .set_property = intel_plane_set_property,
12127 .atomic_duplicate_state = intel_plane_duplicate_state,
12128 .atomic_destroy_state = intel_plane_destroy_state,
12129 };
12130
12131 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12132 int pipe)
12133 {
12134 struct intel_plane *cursor;
12135
12136 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12137 if (cursor == NULL)
12138 return NULL;
12139
12140 cursor->base.state = intel_plane_duplicate_state(&cursor->base);
12141 if (cursor->base.state == NULL) {
12142 kfree(cursor);
12143 return NULL;
12144 }
12145
12146 cursor->can_scale = false;
12147 cursor->max_downscale = 1;
12148 cursor->pipe = pipe;
12149 cursor->plane = pipe;
12150 cursor->rotation = BIT(DRM_ROTATE_0);
12151 cursor->check_plane = intel_check_cursor_plane;
12152 cursor->commit_plane = intel_commit_cursor_plane;
12153
12154 drm_universal_plane_init(dev, &cursor->base, 0,
12155 &intel_cursor_plane_funcs,
12156 intel_cursor_formats,
12157 ARRAY_SIZE(intel_cursor_formats),
12158 DRM_PLANE_TYPE_CURSOR);
12159
12160 if (INTEL_INFO(dev)->gen >= 4) {
12161 if (!dev->mode_config.rotation_property)
12162 dev->mode_config.rotation_property =
12163 drm_mode_create_rotation_property(dev,
12164 BIT(DRM_ROTATE_0) |
12165 BIT(DRM_ROTATE_180));
12166 if (dev->mode_config.rotation_property)
12167 drm_object_attach_property(&cursor->base.base,
12168 dev->mode_config.rotation_property,
12169 cursor->rotation);
12170 }
12171
12172 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12173
12174 return &cursor->base;
12175 }
12176
12177 static void intel_crtc_init(struct drm_device *dev, int pipe)
12178 {
12179 struct drm_i915_private *dev_priv = dev->dev_private;
12180 struct intel_crtc *intel_crtc;
12181 struct intel_crtc_state *crtc_state = NULL;
12182 struct drm_plane *primary = NULL;
12183 struct drm_plane *cursor = NULL;
12184 int i, ret;
12185
12186 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12187 if (intel_crtc == NULL)
12188 return;
12189
12190 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12191 if (!crtc_state)
12192 goto fail;
12193 intel_crtc_set_state(intel_crtc, crtc_state);
12194
12195 primary = intel_primary_plane_create(dev, pipe);
12196 if (!primary)
12197 goto fail;
12198
12199 cursor = intel_cursor_plane_create(dev, pipe);
12200 if (!cursor)
12201 goto fail;
12202
12203 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12204 cursor, &intel_crtc_funcs);
12205 if (ret)
12206 goto fail;
12207
12208 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12209 for (i = 0; i < 256; i++) {
12210 intel_crtc->lut_r[i] = i;
12211 intel_crtc->lut_g[i] = i;
12212 intel_crtc->lut_b[i] = i;
12213 }
12214
12215 /*
12216 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12217 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12218 */
12219 intel_crtc->pipe = pipe;
12220 intel_crtc->plane = pipe;
12221 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12222 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12223 intel_crtc->plane = !pipe;
12224 }
12225
12226 intel_crtc->cursor_base = ~0;
12227 intel_crtc->cursor_cntl = ~0;
12228 intel_crtc->cursor_size = ~0;
12229
12230 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12231 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12232 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12233 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12234
12235 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12236
12237 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12238
12239 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12240 return;
12241
12242 fail:
12243 if (primary)
12244 drm_plane_cleanup(primary);
12245 if (cursor)
12246 drm_plane_cleanup(cursor);
12247 kfree(crtc_state);
12248 kfree(intel_crtc);
12249 }
12250
12251 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12252 {
12253 struct drm_encoder *encoder = connector->base.encoder;
12254 struct drm_device *dev = connector->base.dev;
12255
12256 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12257
12258 if (!encoder || WARN_ON(!encoder->crtc))
12259 return INVALID_PIPE;
12260
12261 return to_intel_crtc(encoder->crtc)->pipe;
12262 }
12263
12264 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12265 struct drm_file *file)
12266 {
12267 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12268 struct drm_crtc *drmmode_crtc;
12269 struct intel_crtc *crtc;
12270
12271 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12272 return -ENODEV;
12273
12274 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12275
12276 if (!drmmode_crtc) {
12277 DRM_ERROR("no such CRTC id\n");
12278 return -ENOENT;
12279 }
12280
12281 crtc = to_intel_crtc(drmmode_crtc);
12282 pipe_from_crtc_id->pipe = crtc->pipe;
12283
12284 return 0;
12285 }
12286
12287 static int intel_encoder_clones(struct intel_encoder *encoder)
12288 {
12289 struct drm_device *dev = encoder->base.dev;
12290 struct intel_encoder *source_encoder;
12291 int index_mask = 0;
12292 int entry = 0;
12293
12294 for_each_intel_encoder(dev, source_encoder) {
12295 if (encoders_cloneable(encoder, source_encoder))
12296 index_mask |= (1 << entry);
12297
12298 entry++;
12299 }
12300
12301 return index_mask;
12302 }
12303
12304 static bool has_edp_a(struct drm_device *dev)
12305 {
12306 struct drm_i915_private *dev_priv = dev->dev_private;
12307
12308 if (!IS_MOBILE(dev))
12309 return false;
12310
12311 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12312 return false;
12313
12314 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12315 return false;
12316
12317 return true;
12318 }
12319
12320 static bool intel_crt_present(struct drm_device *dev)
12321 {
12322 struct drm_i915_private *dev_priv = dev->dev_private;
12323
12324 if (INTEL_INFO(dev)->gen >= 9)
12325 return false;
12326
12327 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12328 return false;
12329
12330 if (IS_CHERRYVIEW(dev))
12331 return false;
12332
12333 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12334 return false;
12335
12336 return true;
12337 }
12338
12339 static void intel_setup_outputs(struct drm_device *dev)
12340 {
12341 struct drm_i915_private *dev_priv = dev->dev_private;
12342 struct intel_encoder *encoder;
12343 bool dpd_is_edp = false;
12344
12345 intel_lvds_init(dev);
12346
12347 if (intel_crt_present(dev))
12348 intel_crt_init(dev);
12349
12350 if (HAS_DDI(dev)) {
12351 int found;
12352
12353 /* Haswell uses DDI functions to detect digital outputs */
12354 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12355 /* DDI A only supports eDP */
12356 if (found)
12357 intel_ddi_init(dev, PORT_A);
12358
12359 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12360 * register */
12361 found = I915_READ(SFUSE_STRAP);
12362
12363 if (found & SFUSE_STRAP_DDIB_DETECTED)
12364 intel_ddi_init(dev, PORT_B);
12365 if (found & SFUSE_STRAP_DDIC_DETECTED)
12366 intel_ddi_init(dev, PORT_C);
12367 if (found & SFUSE_STRAP_DDID_DETECTED)
12368 intel_ddi_init(dev, PORT_D);
12369 } else if (HAS_PCH_SPLIT(dev)) {
12370 int found;
12371 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12372
12373 if (has_edp_a(dev))
12374 intel_dp_init(dev, DP_A, PORT_A);
12375
12376 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12377 /* PCH SDVOB multiplex with HDMIB */
12378 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12379 if (!found)
12380 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12381 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12382 intel_dp_init(dev, PCH_DP_B, PORT_B);
12383 }
12384
12385 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12386 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12387
12388 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12389 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12390
12391 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12392 intel_dp_init(dev, PCH_DP_C, PORT_C);
12393
12394 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12395 intel_dp_init(dev, PCH_DP_D, PORT_D);
12396 } else if (IS_VALLEYVIEW(dev)) {
12397 /*
12398 * The DP_DETECTED bit is the latched state of the DDC
12399 * SDA pin at boot. However since eDP doesn't require DDC
12400 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12401 * eDP ports may have been muxed to an alternate function.
12402 * Thus we can't rely on the DP_DETECTED bit alone to detect
12403 * eDP ports. Consult the VBT as well as DP_DETECTED to
12404 * detect eDP ports.
12405 */
12406 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12407 !intel_dp_is_edp(dev, PORT_B))
12408 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12409 PORT_B);
12410 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12411 intel_dp_is_edp(dev, PORT_B))
12412 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12413
12414 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12415 !intel_dp_is_edp(dev, PORT_C))
12416 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12417 PORT_C);
12418 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12419 intel_dp_is_edp(dev, PORT_C))
12420 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12421
12422 if (IS_CHERRYVIEW(dev)) {
12423 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12424 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12425 PORT_D);
12426 /* eDP not supported on port D, so don't check VBT */
12427 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12428 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12429 }
12430
12431 intel_dsi_init(dev);
12432 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12433 bool found = false;
12434
12435 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12436 DRM_DEBUG_KMS("probing SDVOB\n");
12437 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12438 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12439 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12440 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12441 }
12442
12443 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12444 intel_dp_init(dev, DP_B, PORT_B);
12445 }
12446
12447 /* Before G4X SDVOC doesn't have its own detect register */
12448
12449 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12450 DRM_DEBUG_KMS("probing SDVOC\n");
12451 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12452 }
12453
12454 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12455
12456 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12457 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12458 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12459 }
12460 if (SUPPORTS_INTEGRATED_DP(dev))
12461 intel_dp_init(dev, DP_C, PORT_C);
12462 }
12463
12464 if (SUPPORTS_INTEGRATED_DP(dev) &&
12465 (I915_READ(DP_D) & DP_DETECTED))
12466 intel_dp_init(dev, DP_D, PORT_D);
12467 } else if (IS_GEN2(dev))
12468 intel_dvo_init(dev);
12469
12470 if (SUPPORTS_TV(dev))
12471 intel_tv_init(dev);
12472
12473 intel_psr_init(dev);
12474
12475 for_each_intel_encoder(dev, encoder) {
12476 encoder->base.possible_crtcs = encoder->crtc_mask;
12477 encoder->base.possible_clones =
12478 intel_encoder_clones(encoder);
12479 }
12480
12481 intel_init_pch_refclk(dev);
12482
12483 drm_helper_move_panel_connectors_to_head(dev);
12484 }
12485
12486 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12487 {
12488 struct drm_device *dev = fb->dev;
12489 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12490
12491 drm_framebuffer_cleanup(fb);
12492 mutex_lock(&dev->struct_mutex);
12493 WARN_ON(!intel_fb->obj->framebuffer_references--);
12494 drm_gem_object_unreference(&intel_fb->obj->base);
12495 mutex_unlock(&dev->struct_mutex);
12496 kfree(intel_fb);
12497 }
12498
12499 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12500 struct drm_file *file,
12501 unsigned int *handle)
12502 {
12503 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12504 struct drm_i915_gem_object *obj = intel_fb->obj;
12505
12506 return drm_gem_handle_create(file, &obj->base, handle);
12507 }
12508
12509 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12510 .destroy = intel_user_framebuffer_destroy,
12511 .create_handle = intel_user_framebuffer_create_handle,
12512 };
12513
12514 static int intel_framebuffer_init(struct drm_device *dev,
12515 struct intel_framebuffer *intel_fb,
12516 struct drm_mode_fb_cmd2 *mode_cmd,
12517 struct drm_i915_gem_object *obj)
12518 {
12519 int aligned_height;
12520 int pitch_limit;
12521 int ret;
12522
12523 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12524
12525 if (obj->tiling_mode == I915_TILING_Y) {
12526 DRM_DEBUG("hardware does not support tiling Y\n");
12527 return -EINVAL;
12528 }
12529
12530 if (mode_cmd->pitches[0] & 63) {
12531 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12532 mode_cmd->pitches[0]);
12533 return -EINVAL;
12534 }
12535
12536 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12537 pitch_limit = 32*1024;
12538 } else if (INTEL_INFO(dev)->gen >= 4) {
12539 if (obj->tiling_mode)
12540 pitch_limit = 16*1024;
12541 else
12542 pitch_limit = 32*1024;
12543 } else if (INTEL_INFO(dev)->gen >= 3) {
12544 if (obj->tiling_mode)
12545 pitch_limit = 8*1024;
12546 else
12547 pitch_limit = 16*1024;
12548 } else
12549 /* XXX DSPC is limited to 4k tiled */
12550 pitch_limit = 8*1024;
12551
12552 if (mode_cmd->pitches[0] > pitch_limit) {
12553 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12554 obj->tiling_mode ? "tiled" : "linear",
12555 mode_cmd->pitches[0], pitch_limit);
12556 return -EINVAL;
12557 }
12558
12559 if (obj->tiling_mode != I915_TILING_NONE &&
12560 mode_cmd->pitches[0] != obj->stride) {
12561 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12562 mode_cmd->pitches[0], obj->stride);
12563 return -EINVAL;
12564 }
12565
12566 /* Reject formats not supported by any plane early. */
12567 switch (mode_cmd->pixel_format) {
12568 case DRM_FORMAT_C8:
12569 case DRM_FORMAT_RGB565:
12570 case DRM_FORMAT_XRGB8888:
12571 case DRM_FORMAT_ARGB8888:
12572 break;
12573 case DRM_FORMAT_XRGB1555:
12574 case DRM_FORMAT_ARGB1555:
12575 if (INTEL_INFO(dev)->gen > 3) {
12576 DRM_DEBUG("unsupported pixel format: %s\n",
12577 drm_get_format_name(mode_cmd->pixel_format));
12578 return -EINVAL;
12579 }
12580 break;
12581 case DRM_FORMAT_XBGR8888:
12582 case DRM_FORMAT_ABGR8888:
12583 case DRM_FORMAT_XRGB2101010:
12584 case DRM_FORMAT_ARGB2101010:
12585 case DRM_FORMAT_XBGR2101010:
12586 case DRM_FORMAT_ABGR2101010:
12587 if (INTEL_INFO(dev)->gen < 4) {
12588 DRM_DEBUG("unsupported pixel format: %s\n",
12589 drm_get_format_name(mode_cmd->pixel_format));
12590 return -EINVAL;
12591 }
12592 break;
12593 case DRM_FORMAT_YUYV:
12594 case DRM_FORMAT_UYVY:
12595 case DRM_FORMAT_YVYU:
12596 case DRM_FORMAT_VYUY:
12597 if (INTEL_INFO(dev)->gen < 5) {
12598 DRM_DEBUG("unsupported pixel format: %s\n",
12599 drm_get_format_name(mode_cmd->pixel_format));
12600 return -EINVAL;
12601 }
12602 break;
12603 default:
12604 DRM_DEBUG("unsupported pixel format: %s\n",
12605 drm_get_format_name(mode_cmd->pixel_format));
12606 return -EINVAL;
12607 }
12608
12609 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12610 if (mode_cmd->offsets[0] != 0)
12611 return -EINVAL;
12612
12613 aligned_height = intel_align_height(dev, mode_cmd->height,
12614 obj->tiling_mode);
12615 /* FIXME drm helper for size checks (especially planar formats)? */
12616 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12617 return -EINVAL;
12618
12619 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12620 intel_fb->obj = obj;
12621 intel_fb->obj->framebuffer_references++;
12622
12623 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12624 if (ret) {
12625 DRM_ERROR("framebuffer init failed %d\n", ret);
12626 return ret;
12627 }
12628
12629 return 0;
12630 }
12631
12632 static struct drm_framebuffer *
12633 intel_user_framebuffer_create(struct drm_device *dev,
12634 struct drm_file *filp,
12635 struct drm_mode_fb_cmd2 *mode_cmd)
12636 {
12637 struct drm_i915_gem_object *obj;
12638
12639 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12640 mode_cmd->handles[0]));
12641 if (&obj->base == NULL)
12642 return ERR_PTR(-ENOENT);
12643
12644 return intel_framebuffer_create(dev, mode_cmd, obj);
12645 }
12646
12647 #ifndef CONFIG_DRM_I915_FBDEV
12648 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12649 {
12650 }
12651 #endif
12652
12653 static const struct drm_mode_config_funcs intel_mode_funcs = {
12654 .fb_create = intel_user_framebuffer_create,
12655 .output_poll_changed = intel_fbdev_output_poll_changed,
12656 };
12657
12658 /* Set up chip specific display functions */
12659 static void intel_init_display(struct drm_device *dev)
12660 {
12661 struct drm_i915_private *dev_priv = dev->dev_private;
12662
12663 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12664 dev_priv->display.find_dpll = g4x_find_best_dpll;
12665 else if (IS_CHERRYVIEW(dev))
12666 dev_priv->display.find_dpll = chv_find_best_dpll;
12667 else if (IS_VALLEYVIEW(dev))
12668 dev_priv->display.find_dpll = vlv_find_best_dpll;
12669 else if (IS_PINEVIEW(dev))
12670 dev_priv->display.find_dpll = pnv_find_best_dpll;
12671 else
12672 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12673
12674 if (HAS_DDI(dev)) {
12675 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12676 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12677 dev_priv->display.crtc_compute_clock =
12678 haswell_crtc_compute_clock;
12679 dev_priv->display.crtc_enable = haswell_crtc_enable;
12680 dev_priv->display.crtc_disable = haswell_crtc_disable;
12681 dev_priv->display.off = ironlake_crtc_off;
12682 if (INTEL_INFO(dev)->gen >= 9)
12683 dev_priv->display.update_primary_plane =
12684 skylake_update_primary_plane;
12685 else
12686 dev_priv->display.update_primary_plane =
12687 ironlake_update_primary_plane;
12688 } else if (HAS_PCH_SPLIT(dev)) {
12689 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12690 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12691 dev_priv->display.crtc_compute_clock =
12692 ironlake_crtc_compute_clock;
12693 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12694 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12695 dev_priv->display.off = ironlake_crtc_off;
12696 dev_priv->display.update_primary_plane =
12697 ironlake_update_primary_plane;
12698 } else if (IS_VALLEYVIEW(dev)) {
12699 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12700 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12701 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12702 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12703 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12704 dev_priv->display.off = i9xx_crtc_off;
12705 dev_priv->display.update_primary_plane =
12706 i9xx_update_primary_plane;
12707 } else {
12708 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12709 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12710 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12711 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12712 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12713 dev_priv->display.off = i9xx_crtc_off;
12714 dev_priv->display.update_primary_plane =
12715 i9xx_update_primary_plane;
12716 }
12717
12718 /* Returns the core display clock speed */
12719 if (IS_VALLEYVIEW(dev))
12720 dev_priv->display.get_display_clock_speed =
12721 valleyview_get_display_clock_speed;
12722 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12723 dev_priv->display.get_display_clock_speed =
12724 i945_get_display_clock_speed;
12725 else if (IS_I915G(dev))
12726 dev_priv->display.get_display_clock_speed =
12727 i915_get_display_clock_speed;
12728 else if (IS_I945GM(dev) || IS_845G(dev))
12729 dev_priv->display.get_display_clock_speed =
12730 i9xx_misc_get_display_clock_speed;
12731 else if (IS_PINEVIEW(dev))
12732 dev_priv->display.get_display_clock_speed =
12733 pnv_get_display_clock_speed;
12734 else if (IS_I915GM(dev))
12735 dev_priv->display.get_display_clock_speed =
12736 i915gm_get_display_clock_speed;
12737 else if (IS_I865G(dev))
12738 dev_priv->display.get_display_clock_speed =
12739 i865_get_display_clock_speed;
12740 else if (IS_I85X(dev))
12741 dev_priv->display.get_display_clock_speed =
12742 i855_get_display_clock_speed;
12743 else /* 852, 830 */
12744 dev_priv->display.get_display_clock_speed =
12745 i830_get_display_clock_speed;
12746
12747 if (IS_GEN5(dev)) {
12748 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12749 } else if (IS_GEN6(dev)) {
12750 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12751 } else if (IS_IVYBRIDGE(dev)) {
12752 /* FIXME: detect B0+ stepping and use auto training */
12753 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12754 dev_priv->display.modeset_global_resources =
12755 ivb_modeset_global_resources;
12756 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12757 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12758 } else if (IS_VALLEYVIEW(dev)) {
12759 dev_priv->display.modeset_global_resources =
12760 valleyview_modeset_global_resources;
12761 }
12762
12763 /* Default just returns -ENODEV to indicate unsupported */
12764 dev_priv->display.queue_flip = intel_default_queue_flip;
12765
12766 switch (INTEL_INFO(dev)->gen) {
12767 case 2:
12768 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12769 break;
12770
12771 case 3:
12772 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12773 break;
12774
12775 case 4:
12776 case 5:
12777 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12778 break;
12779
12780 case 6:
12781 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12782 break;
12783 case 7:
12784 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12785 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12786 break;
12787 case 9:
12788 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12789 break;
12790 }
12791
12792 intel_panel_init_backlight_funcs(dev);
12793
12794 mutex_init(&dev_priv->pps_mutex);
12795 }
12796
12797 /*
12798 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12799 * resume, or other times. This quirk makes sure that's the case for
12800 * affected systems.
12801 */
12802 static void quirk_pipea_force(struct drm_device *dev)
12803 {
12804 struct drm_i915_private *dev_priv = dev->dev_private;
12805
12806 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12807 DRM_INFO("applying pipe a force quirk\n");
12808 }
12809
12810 static void quirk_pipeb_force(struct drm_device *dev)
12811 {
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12813
12814 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12815 DRM_INFO("applying pipe b force quirk\n");
12816 }
12817
12818 /*
12819 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12820 */
12821 static void quirk_ssc_force_disable(struct drm_device *dev)
12822 {
12823 struct drm_i915_private *dev_priv = dev->dev_private;
12824 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12825 DRM_INFO("applying lvds SSC disable quirk\n");
12826 }
12827
12828 /*
12829 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12830 * brightness value
12831 */
12832 static void quirk_invert_brightness(struct drm_device *dev)
12833 {
12834 struct drm_i915_private *dev_priv = dev->dev_private;
12835 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12836 DRM_INFO("applying inverted panel brightness quirk\n");
12837 }
12838
12839 /* Some VBT's incorrectly indicate no backlight is present */
12840 static void quirk_backlight_present(struct drm_device *dev)
12841 {
12842 struct drm_i915_private *dev_priv = dev->dev_private;
12843 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12844 DRM_INFO("applying backlight present quirk\n");
12845 }
12846
12847 struct intel_quirk {
12848 int device;
12849 int subsystem_vendor;
12850 int subsystem_device;
12851 void (*hook)(struct drm_device *dev);
12852 };
12853
12854 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12855 struct intel_dmi_quirk {
12856 void (*hook)(struct drm_device *dev);
12857 const struct dmi_system_id (*dmi_id_list)[];
12858 };
12859
12860 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12861 {
12862 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12863 return 1;
12864 }
12865
12866 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12867 {
12868 .dmi_id_list = &(const struct dmi_system_id[]) {
12869 {
12870 .callback = intel_dmi_reverse_brightness,
12871 .ident = "NCR Corporation",
12872 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12873 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12874 },
12875 },
12876 { } /* terminating entry */
12877 },
12878 .hook = quirk_invert_brightness,
12879 },
12880 };
12881
12882 static struct intel_quirk intel_quirks[] = {
12883 /* HP Mini needs pipe A force quirk (LP: #322104) */
12884 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12885
12886 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12887 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12888
12889 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12890 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12891
12892 /* 830 needs to leave pipe A & dpll A up */
12893 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12894
12895 /* 830 needs to leave pipe B & dpll B up */
12896 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12897
12898 /* Lenovo U160 cannot use SSC on LVDS */
12899 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12900
12901 /* Sony Vaio Y cannot use SSC on LVDS */
12902 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12903
12904 /* Acer Aspire 5734Z must invert backlight brightness */
12905 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12906
12907 /* Acer/eMachines G725 */
12908 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12909
12910 /* Acer/eMachines e725 */
12911 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12912
12913 /* Acer/Packard Bell NCL20 */
12914 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12915
12916 /* Acer Aspire 4736Z */
12917 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12918
12919 /* Acer Aspire 5336 */
12920 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12921
12922 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12923 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12924
12925 /* Acer C720 Chromebook (Core i3 4005U) */
12926 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12927
12928 /* Apple Macbook 2,1 (Core 2 T7400) */
12929 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12930
12931 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12932 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12933
12934 /* HP Chromebook 14 (Celeron 2955U) */
12935 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12936 };
12937
12938 static void intel_init_quirks(struct drm_device *dev)
12939 {
12940 struct pci_dev *d = dev->pdev;
12941 int i;
12942
12943 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12944 struct intel_quirk *q = &intel_quirks[i];
12945
12946 if (d->device == q->device &&
12947 (d->subsystem_vendor == q->subsystem_vendor ||
12948 q->subsystem_vendor == PCI_ANY_ID) &&
12949 (d->subsystem_device == q->subsystem_device ||
12950 q->subsystem_device == PCI_ANY_ID))
12951 q->hook(dev);
12952 }
12953 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12954 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12955 intel_dmi_quirks[i].hook(dev);
12956 }
12957 }
12958
12959 /* Disable the VGA plane that we never use */
12960 static void i915_disable_vga(struct drm_device *dev)
12961 {
12962 struct drm_i915_private *dev_priv = dev->dev_private;
12963 u8 sr1;
12964 u32 vga_reg = i915_vgacntrl_reg(dev);
12965
12966 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12967 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12968 outb(SR01, VGA_SR_INDEX);
12969 sr1 = inb(VGA_SR_DATA);
12970 outb(sr1 | 1<<5, VGA_SR_DATA);
12971 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12972 udelay(300);
12973
12974 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12975 POSTING_READ(vga_reg);
12976 }
12977
12978 void intel_modeset_init_hw(struct drm_device *dev)
12979 {
12980 intel_prepare_ddi(dev);
12981
12982 if (IS_VALLEYVIEW(dev))
12983 vlv_update_cdclk(dev);
12984
12985 intel_init_clock_gating(dev);
12986
12987 intel_enable_gt_powersave(dev);
12988 }
12989
12990 void intel_modeset_init(struct drm_device *dev)
12991 {
12992 struct drm_i915_private *dev_priv = dev->dev_private;
12993 int sprite, ret;
12994 enum pipe pipe;
12995 struct intel_crtc *crtc;
12996
12997 drm_mode_config_init(dev);
12998
12999 dev->mode_config.min_width = 0;
13000 dev->mode_config.min_height = 0;
13001
13002 dev->mode_config.preferred_depth = 24;
13003 dev->mode_config.prefer_shadow = 1;
13004
13005 dev->mode_config.funcs = &intel_mode_funcs;
13006
13007 intel_init_quirks(dev);
13008
13009 intel_init_pm(dev);
13010
13011 if (INTEL_INFO(dev)->num_pipes == 0)
13012 return;
13013
13014 intel_init_display(dev);
13015 intel_init_audio(dev);
13016
13017 if (IS_GEN2(dev)) {
13018 dev->mode_config.max_width = 2048;
13019 dev->mode_config.max_height = 2048;
13020 } else if (IS_GEN3(dev)) {
13021 dev->mode_config.max_width = 4096;
13022 dev->mode_config.max_height = 4096;
13023 } else {
13024 dev->mode_config.max_width = 8192;
13025 dev->mode_config.max_height = 8192;
13026 }
13027
13028 if (IS_845G(dev) || IS_I865G(dev)) {
13029 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13030 dev->mode_config.cursor_height = 1023;
13031 } else if (IS_GEN2(dev)) {
13032 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13033 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13034 } else {
13035 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13036 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13037 }
13038
13039 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13040
13041 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13042 INTEL_INFO(dev)->num_pipes,
13043 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13044
13045 for_each_pipe(dev_priv, pipe) {
13046 intel_crtc_init(dev, pipe);
13047 for_each_sprite(pipe, sprite) {
13048 ret = intel_plane_init(dev, pipe, sprite);
13049 if (ret)
13050 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13051 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13052 }
13053 }
13054
13055 intel_init_dpio(dev);
13056
13057 intel_shared_dpll_init(dev);
13058
13059 /* Just disable it once at startup */
13060 i915_disable_vga(dev);
13061 intel_setup_outputs(dev);
13062
13063 /* Just in case the BIOS is doing something questionable. */
13064 intel_fbc_disable(dev);
13065
13066 drm_modeset_lock_all(dev);
13067 intel_modeset_setup_hw_state(dev, false);
13068 drm_modeset_unlock_all(dev);
13069
13070 for_each_intel_crtc(dev, crtc) {
13071 if (!crtc->active)
13072 continue;
13073
13074 /*
13075 * Note that reserving the BIOS fb up front prevents us
13076 * from stuffing other stolen allocations like the ring
13077 * on top. This prevents some ugliness at boot time, and
13078 * can even allow for smooth boot transitions if the BIOS
13079 * fb is large enough for the active pipe configuration.
13080 */
13081 if (dev_priv->display.get_plane_config) {
13082 dev_priv->display.get_plane_config(crtc,
13083 &crtc->plane_config);
13084 /*
13085 * If the fb is shared between multiple heads, we'll
13086 * just get the first one.
13087 */
13088 intel_find_plane_obj(crtc, &crtc->plane_config);
13089 }
13090 }
13091 }
13092
13093 static void intel_enable_pipe_a(struct drm_device *dev)
13094 {
13095 struct intel_connector *connector;
13096 struct drm_connector *crt = NULL;
13097 struct intel_load_detect_pipe load_detect_temp;
13098 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13099
13100 /* We can't just switch on the pipe A, we need to set things up with a
13101 * proper mode and output configuration. As a gross hack, enable pipe A
13102 * by enabling the load detect pipe once. */
13103 list_for_each_entry(connector,
13104 &dev->mode_config.connector_list,
13105 base.head) {
13106 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13107 crt = &connector->base;
13108 break;
13109 }
13110 }
13111
13112 if (!crt)
13113 return;
13114
13115 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13116 intel_release_load_detect_pipe(crt, &load_detect_temp);
13117 }
13118
13119 static bool
13120 intel_check_plane_mapping(struct intel_crtc *crtc)
13121 {
13122 struct drm_device *dev = crtc->base.dev;
13123 struct drm_i915_private *dev_priv = dev->dev_private;
13124 u32 reg, val;
13125
13126 if (INTEL_INFO(dev)->num_pipes == 1)
13127 return true;
13128
13129 reg = DSPCNTR(!crtc->plane);
13130 val = I915_READ(reg);
13131
13132 if ((val & DISPLAY_PLANE_ENABLE) &&
13133 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13134 return false;
13135
13136 return true;
13137 }
13138
13139 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13140 {
13141 struct drm_device *dev = crtc->base.dev;
13142 struct drm_i915_private *dev_priv = dev->dev_private;
13143 u32 reg;
13144
13145 /* Clear any frame start delays used for debugging left by the BIOS */
13146 reg = PIPECONF(crtc->config->cpu_transcoder);
13147 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13148
13149 /* restore vblank interrupts to correct state */
13150 if (crtc->active) {
13151 update_scanline_offset(crtc);
13152 drm_vblank_on(dev, crtc->pipe);
13153 } else
13154 drm_vblank_off(dev, crtc->pipe);
13155
13156 /* We need to sanitize the plane -> pipe mapping first because this will
13157 * disable the crtc (and hence change the state) if it is wrong. Note
13158 * that gen4+ has a fixed plane -> pipe mapping. */
13159 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13160 struct intel_connector *connector;
13161 bool plane;
13162
13163 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13164 crtc->base.base.id);
13165
13166 /* Pipe has the wrong plane attached and the plane is active.
13167 * Temporarily change the plane mapping and disable everything
13168 * ... */
13169 plane = crtc->plane;
13170 crtc->plane = !plane;
13171 crtc->primary_enabled = true;
13172 dev_priv->display.crtc_disable(&crtc->base);
13173 crtc->plane = plane;
13174
13175 /* ... and break all links. */
13176 list_for_each_entry(connector, &dev->mode_config.connector_list,
13177 base.head) {
13178 if (connector->encoder->base.crtc != &crtc->base)
13179 continue;
13180
13181 connector->base.dpms = DRM_MODE_DPMS_OFF;
13182 connector->base.encoder = NULL;
13183 }
13184 /* multiple connectors may have the same encoder:
13185 * handle them and break crtc link separately */
13186 list_for_each_entry(connector, &dev->mode_config.connector_list,
13187 base.head)
13188 if (connector->encoder->base.crtc == &crtc->base) {
13189 connector->encoder->base.crtc = NULL;
13190 connector->encoder->connectors_active = false;
13191 }
13192
13193 WARN_ON(crtc->active);
13194 crtc->base.enabled = false;
13195 }
13196
13197 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13198 crtc->pipe == PIPE_A && !crtc->active) {
13199 /* BIOS forgot to enable pipe A, this mostly happens after
13200 * resume. Force-enable the pipe to fix this, the update_dpms
13201 * call below we restore the pipe to the right state, but leave
13202 * the required bits on. */
13203 intel_enable_pipe_a(dev);
13204 }
13205
13206 /* Adjust the state of the output pipe according to whether we
13207 * have active connectors/encoders. */
13208 intel_crtc_update_dpms(&crtc->base);
13209
13210 if (crtc->active != crtc->base.enabled) {
13211 struct intel_encoder *encoder;
13212
13213 /* This can happen either due to bugs in the get_hw_state
13214 * functions or because the pipe is force-enabled due to the
13215 * pipe A quirk. */
13216 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13217 crtc->base.base.id,
13218 crtc->base.enabled ? "enabled" : "disabled",
13219 crtc->active ? "enabled" : "disabled");
13220
13221 crtc->base.enabled = crtc->active;
13222
13223 /* Because we only establish the connector -> encoder ->
13224 * crtc links if something is active, this means the
13225 * crtc is now deactivated. Break the links. connector
13226 * -> encoder links are only establish when things are
13227 * actually up, hence no need to break them. */
13228 WARN_ON(crtc->active);
13229
13230 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13231 WARN_ON(encoder->connectors_active);
13232 encoder->base.crtc = NULL;
13233 }
13234 }
13235
13236 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13237 /*
13238 * We start out with underrun reporting disabled to avoid races.
13239 * For correct bookkeeping mark this on active crtcs.
13240 *
13241 * Also on gmch platforms we dont have any hardware bits to
13242 * disable the underrun reporting. Which means we need to start
13243 * out with underrun reporting disabled also on inactive pipes,
13244 * since otherwise we'll complain about the garbage we read when
13245 * e.g. coming up after runtime pm.
13246 *
13247 * No protection against concurrent access is required - at
13248 * worst a fifo underrun happens which also sets this to false.
13249 */
13250 crtc->cpu_fifo_underrun_disabled = true;
13251 crtc->pch_fifo_underrun_disabled = true;
13252 }
13253 }
13254
13255 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13256 {
13257 struct intel_connector *connector;
13258 struct drm_device *dev = encoder->base.dev;
13259
13260 /* We need to check both for a crtc link (meaning that the
13261 * encoder is active and trying to read from a pipe) and the
13262 * pipe itself being active. */
13263 bool has_active_crtc = encoder->base.crtc &&
13264 to_intel_crtc(encoder->base.crtc)->active;
13265
13266 if (encoder->connectors_active && !has_active_crtc) {
13267 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13268 encoder->base.base.id,
13269 encoder->base.name);
13270
13271 /* Connector is active, but has no active pipe. This is
13272 * fallout from our resume register restoring. Disable
13273 * the encoder manually again. */
13274 if (encoder->base.crtc) {
13275 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13276 encoder->base.base.id,
13277 encoder->base.name);
13278 encoder->disable(encoder);
13279 if (encoder->post_disable)
13280 encoder->post_disable(encoder);
13281 }
13282 encoder->base.crtc = NULL;
13283 encoder->connectors_active = false;
13284
13285 /* Inconsistent output/port/pipe state happens presumably due to
13286 * a bug in one of the get_hw_state functions. Or someplace else
13287 * in our code, like the register restore mess on resume. Clamp
13288 * things to off as a safer default. */
13289 list_for_each_entry(connector,
13290 &dev->mode_config.connector_list,
13291 base.head) {
13292 if (connector->encoder != encoder)
13293 continue;
13294 connector->base.dpms = DRM_MODE_DPMS_OFF;
13295 connector->base.encoder = NULL;
13296 }
13297 }
13298 /* Enabled encoders without active connectors will be fixed in
13299 * the crtc fixup. */
13300 }
13301
13302 void i915_redisable_vga_power_on(struct drm_device *dev)
13303 {
13304 struct drm_i915_private *dev_priv = dev->dev_private;
13305 u32 vga_reg = i915_vgacntrl_reg(dev);
13306
13307 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13308 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13309 i915_disable_vga(dev);
13310 }
13311 }
13312
13313 void i915_redisable_vga(struct drm_device *dev)
13314 {
13315 struct drm_i915_private *dev_priv = dev->dev_private;
13316
13317 /* This function can be called both from intel_modeset_setup_hw_state or
13318 * at a very early point in our resume sequence, where the power well
13319 * structures are not yet restored. Since this function is at a very
13320 * paranoid "someone might have enabled VGA while we were not looking"
13321 * level, just check if the power well is enabled instead of trying to
13322 * follow the "don't touch the power well if we don't need it" policy
13323 * the rest of the driver uses. */
13324 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13325 return;
13326
13327 i915_redisable_vga_power_on(dev);
13328 }
13329
13330 static bool primary_get_hw_state(struct intel_crtc *crtc)
13331 {
13332 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13333
13334 if (!crtc->active)
13335 return false;
13336
13337 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13338 }
13339
13340 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13341 {
13342 struct drm_i915_private *dev_priv = dev->dev_private;
13343 enum pipe pipe;
13344 struct intel_crtc *crtc;
13345 struct intel_encoder *encoder;
13346 struct intel_connector *connector;
13347 int i;
13348
13349 for_each_intel_crtc(dev, crtc) {
13350 memset(crtc->config, 0, sizeof(*crtc->config));
13351
13352 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13353
13354 crtc->active = dev_priv->display.get_pipe_config(crtc,
13355 crtc->config);
13356
13357 crtc->base.enabled = crtc->active;
13358 crtc->primary_enabled = primary_get_hw_state(crtc);
13359
13360 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13361 crtc->base.base.id,
13362 crtc->active ? "enabled" : "disabled");
13363 }
13364
13365 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13366 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13367
13368 pll->on = pll->get_hw_state(dev_priv, pll,
13369 &pll->config.hw_state);
13370 pll->active = 0;
13371 pll->config.crtc_mask = 0;
13372 for_each_intel_crtc(dev, crtc) {
13373 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13374 pll->active++;
13375 pll->config.crtc_mask |= 1 << crtc->pipe;
13376 }
13377 }
13378
13379 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13380 pll->name, pll->config.crtc_mask, pll->on);
13381
13382 if (pll->config.crtc_mask)
13383 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13384 }
13385
13386 for_each_intel_encoder(dev, encoder) {
13387 pipe = 0;
13388
13389 if (encoder->get_hw_state(encoder, &pipe)) {
13390 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13391 encoder->base.crtc = &crtc->base;
13392 encoder->get_config(encoder, crtc->config);
13393 } else {
13394 encoder->base.crtc = NULL;
13395 }
13396
13397 encoder->connectors_active = false;
13398 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13399 encoder->base.base.id,
13400 encoder->base.name,
13401 encoder->base.crtc ? "enabled" : "disabled",
13402 pipe_name(pipe));
13403 }
13404
13405 list_for_each_entry(connector, &dev->mode_config.connector_list,
13406 base.head) {
13407 if (connector->get_hw_state(connector)) {
13408 connector->base.dpms = DRM_MODE_DPMS_ON;
13409 connector->encoder->connectors_active = true;
13410 connector->base.encoder = &connector->encoder->base;
13411 } else {
13412 connector->base.dpms = DRM_MODE_DPMS_OFF;
13413 connector->base.encoder = NULL;
13414 }
13415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13416 connector->base.base.id,
13417 connector->base.name,
13418 connector->base.encoder ? "enabled" : "disabled");
13419 }
13420 }
13421
13422 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13423 * and i915 state tracking structures. */
13424 void intel_modeset_setup_hw_state(struct drm_device *dev,
13425 bool force_restore)
13426 {
13427 struct drm_i915_private *dev_priv = dev->dev_private;
13428 enum pipe pipe;
13429 struct intel_crtc *crtc;
13430 struct intel_encoder *encoder;
13431 int i;
13432
13433 intel_modeset_readout_hw_state(dev);
13434
13435 /*
13436 * Now that we have the config, copy it to each CRTC struct
13437 * Note that this could go away if we move to using crtc_config
13438 * checking everywhere.
13439 */
13440 for_each_intel_crtc(dev, crtc) {
13441 if (crtc->active && i915.fastboot) {
13442 intel_mode_from_pipe_config(&crtc->base.mode,
13443 crtc->config);
13444 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13445 crtc->base.base.id);
13446 drm_mode_debug_printmodeline(&crtc->base.mode);
13447 }
13448 }
13449
13450 /* HW state is read out, now we need to sanitize this mess. */
13451 for_each_intel_encoder(dev, encoder) {
13452 intel_sanitize_encoder(encoder);
13453 }
13454
13455 for_each_pipe(dev_priv, pipe) {
13456 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13457 intel_sanitize_crtc(crtc);
13458 intel_dump_pipe_config(crtc, crtc->config,
13459 "[setup_hw_state]");
13460 }
13461
13462 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13463 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13464
13465 if (!pll->on || pll->active)
13466 continue;
13467
13468 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13469
13470 pll->disable(dev_priv, pll);
13471 pll->on = false;
13472 }
13473
13474 if (IS_GEN9(dev))
13475 skl_wm_get_hw_state(dev);
13476 else if (HAS_PCH_SPLIT(dev))
13477 ilk_wm_get_hw_state(dev);
13478
13479 if (force_restore) {
13480 i915_redisable_vga(dev);
13481
13482 /*
13483 * We need to use raw interfaces for restoring state to avoid
13484 * checking (bogus) intermediate states.
13485 */
13486 for_each_pipe(dev_priv, pipe) {
13487 struct drm_crtc *crtc =
13488 dev_priv->pipe_to_crtc_mapping[pipe];
13489
13490 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13491 crtc->primary->fb);
13492 }
13493 } else {
13494 intel_modeset_update_staged_output_state(dev);
13495 }
13496
13497 intel_modeset_check_state(dev);
13498 }
13499
13500 void intel_modeset_gem_init(struct drm_device *dev)
13501 {
13502 struct drm_i915_private *dev_priv = dev->dev_private;
13503 struct drm_crtc *c;
13504 struct drm_i915_gem_object *obj;
13505
13506 mutex_lock(&dev->struct_mutex);
13507 intel_init_gt_powersave(dev);
13508 mutex_unlock(&dev->struct_mutex);
13509
13510 /*
13511 * There may be no VBT; and if the BIOS enabled SSC we can
13512 * just keep using it to avoid unnecessary flicker. Whereas if the
13513 * BIOS isn't using it, don't assume it will work even if the VBT
13514 * indicates as much.
13515 */
13516 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13517 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13518 DREF_SSC1_ENABLE);
13519
13520 intel_modeset_init_hw(dev);
13521
13522 intel_setup_overlay(dev);
13523
13524 /*
13525 * Make sure any fbs we allocated at startup are properly
13526 * pinned & fenced. When we do the allocation it's too early
13527 * for this.
13528 */
13529 mutex_lock(&dev->struct_mutex);
13530 for_each_crtc(dev, c) {
13531 obj = intel_fb_obj(c->primary->fb);
13532 if (obj == NULL)
13533 continue;
13534
13535 if (intel_pin_and_fence_fb_obj(c->primary,
13536 c->primary->fb,
13537 NULL)) {
13538 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13539 to_intel_crtc(c)->pipe);
13540 drm_framebuffer_unreference(c->primary->fb);
13541 c->primary->fb = NULL;
13542 }
13543 }
13544 mutex_unlock(&dev->struct_mutex);
13545
13546 intel_backlight_register(dev);
13547 }
13548
13549 void intel_connector_unregister(struct intel_connector *intel_connector)
13550 {
13551 struct drm_connector *connector = &intel_connector->base;
13552
13553 intel_panel_destroy_backlight(connector);
13554 drm_connector_unregister(connector);
13555 }
13556
13557 void intel_modeset_cleanup(struct drm_device *dev)
13558 {
13559 struct drm_i915_private *dev_priv = dev->dev_private;
13560 struct drm_connector *connector;
13561
13562 intel_disable_gt_powersave(dev);
13563
13564 intel_backlight_unregister(dev);
13565
13566 /*
13567 * Interrupts and polling as the first thing to avoid creating havoc.
13568 * Too much stuff here (turning of connectors, ...) would
13569 * experience fancy races otherwise.
13570 */
13571 intel_irq_uninstall(dev_priv);
13572
13573 /*
13574 * Due to the hpd irq storm handling the hotplug work can re-arm the
13575 * poll handlers. Hence disable polling after hpd handling is shut down.
13576 */
13577 drm_kms_helper_poll_fini(dev);
13578
13579 mutex_lock(&dev->struct_mutex);
13580
13581 intel_unregister_dsm_handler();
13582
13583 intel_fbc_disable(dev);
13584
13585 ironlake_teardown_rc6(dev);
13586
13587 mutex_unlock(&dev->struct_mutex);
13588
13589 /* flush any delayed tasks or pending work */
13590 flush_scheduled_work();
13591
13592 /* destroy the backlight and sysfs files before encoders/connectors */
13593 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13594 struct intel_connector *intel_connector;
13595
13596 intel_connector = to_intel_connector(connector);
13597 intel_connector->unregister(intel_connector);
13598 }
13599
13600 drm_mode_config_cleanup(dev);
13601
13602 intel_cleanup_overlay(dev);
13603
13604 mutex_lock(&dev->struct_mutex);
13605 intel_cleanup_gt_powersave(dev);
13606 mutex_unlock(&dev->struct_mutex);
13607 }
13608
13609 /*
13610 * Return which encoder is currently attached for connector.
13611 */
13612 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13613 {
13614 return &intel_attached_encoder(connector)->base;
13615 }
13616
13617 void intel_connector_attach_encoder(struct intel_connector *connector,
13618 struct intel_encoder *encoder)
13619 {
13620 connector->encoder = encoder;
13621 drm_mode_connector_attach_encoder(&connector->base,
13622 &encoder->base);
13623 }
13624
13625 /*
13626 * set vga decode state - true == enable VGA decode
13627 */
13628 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13629 {
13630 struct drm_i915_private *dev_priv = dev->dev_private;
13631 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13632 u16 gmch_ctrl;
13633
13634 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13635 DRM_ERROR("failed to read control word\n");
13636 return -EIO;
13637 }
13638
13639 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13640 return 0;
13641
13642 if (state)
13643 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13644 else
13645 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13646
13647 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13648 DRM_ERROR("failed to write control word\n");
13649 return -EIO;
13650 }
13651
13652 return 0;
13653 }
13654
13655 struct intel_display_error_state {
13656
13657 u32 power_well_driver;
13658
13659 int num_transcoders;
13660
13661 struct intel_cursor_error_state {
13662 u32 control;
13663 u32 position;
13664 u32 base;
13665 u32 size;
13666 } cursor[I915_MAX_PIPES];
13667
13668 struct intel_pipe_error_state {
13669 bool power_domain_on;
13670 u32 source;
13671 u32 stat;
13672 } pipe[I915_MAX_PIPES];
13673
13674 struct intel_plane_error_state {
13675 u32 control;
13676 u32 stride;
13677 u32 size;
13678 u32 pos;
13679 u32 addr;
13680 u32 surface;
13681 u32 tile_offset;
13682 } plane[I915_MAX_PIPES];
13683
13684 struct intel_transcoder_error_state {
13685 bool power_domain_on;
13686 enum transcoder cpu_transcoder;
13687
13688 u32 conf;
13689
13690 u32 htotal;
13691 u32 hblank;
13692 u32 hsync;
13693 u32 vtotal;
13694 u32 vblank;
13695 u32 vsync;
13696 } transcoder[4];
13697 };
13698
13699 struct intel_display_error_state *
13700 intel_display_capture_error_state(struct drm_device *dev)
13701 {
13702 struct drm_i915_private *dev_priv = dev->dev_private;
13703 struct intel_display_error_state *error;
13704 int transcoders[] = {
13705 TRANSCODER_A,
13706 TRANSCODER_B,
13707 TRANSCODER_C,
13708 TRANSCODER_EDP,
13709 };
13710 int i;
13711
13712 if (INTEL_INFO(dev)->num_pipes == 0)
13713 return NULL;
13714
13715 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13716 if (error == NULL)
13717 return NULL;
13718
13719 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13720 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13721
13722 for_each_pipe(dev_priv, i) {
13723 error->pipe[i].power_domain_on =
13724 __intel_display_power_is_enabled(dev_priv,
13725 POWER_DOMAIN_PIPE(i));
13726 if (!error->pipe[i].power_domain_on)
13727 continue;
13728
13729 error->cursor[i].control = I915_READ(CURCNTR(i));
13730 error->cursor[i].position = I915_READ(CURPOS(i));
13731 error->cursor[i].base = I915_READ(CURBASE(i));
13732
13733 error->plane[i].control = I915_READ(DSPCNTR(i));
13734 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13735 if (INTEL_INFO(dev)->gen <= 3) {
13736 error->plane[i].size = I915_READ(DSPSIZE(i));
13737 error->plane[i].pos = I915_READ(DSPPOS(i));
13738 }
13739 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13740 error->plane[i].addr = I915_READ(DSPADDR(i));
13741 if (INTEL_INFO(dev)->gen >= 4) {
13742 error->plane[i].surface = I915_READ(DSPSURF(i));
13743 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13744 }
13745
13746 error->pipe[i].source = I915_READ(PIPESRC(i));
13747
13748 if (HAS_GMCH_DISPLAY(dev))
13749 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13750 }
13751
13752 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13753 if (HAS_DDI(dev_priv->dev))
13754 error->num_transcoders++; /* Account for eDP. */
13755
13756 for (i = 0; i < error->num_transcoders; i++) {
13757 enum transcoder cpu_transcoder = transcoders[i];
13758
13759 error->transcoder[i].power_domain_on =
13760 __intel_display_power_is_enabled(dev_priv,
13761 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13762 if (!error->transcoder[i].power_domain_on)
13763 continue;
13764
13765 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13766
13767 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13768 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13769 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13770 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13771 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13772 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13773 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13774 }
13775
13776 return error;
13777 }
13778
13779 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13780
13781 void
13782 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13783 struct drm_device *dev,
13784 struct intel_display_error_state *error)
13785 {
13786 struct drm_i915_private *dev_priv = dev->dev_private;
13787 int i;
13788
13789 if (!error)
13790 return;
13791
13792 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13793 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13794 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13795 error->power_well_driver);
13796 for_each_pipe(dev_priv, i) {
13797 err_printf(m, "Pipe [%d]:\n", i);
13798 err_printf(m, " Power: %s\n",
13799 error->pipe[i].power_domain_on ? "on" : "off");
13800 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13801 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13802
13803 err_printf(m, "Plane [%d]:\n", i);
13804 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13805 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13806 if (INTEL_INFO(dev)->gen <= 3) {
13807 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13808 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13809 }
13810 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13811 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13812 if (INTEL_INFO(dev)->gen >= 4) {
13813 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13814 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13815 }
13816
13817 err_printf(m, "Cursor [%d]:\n", i);
13818 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13819 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13820 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13821 }
13822
13823 for (i = 0; i < error->num_transcoders; i++) {
13824 err_printf(m, "CPU transcoder: %c\n",
13825 transcoder_name(error->transcoder[i].cpu_transcoder));
13826 err_printf(m, " Power: %s\n",
13827 error->transcoder[i].power_domain_on ? "on" : "off");
13828 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13829 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13830 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13831 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13832 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13833 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13834 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13835 }
13836 }
13837
13838 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13839 {
13840 struct intel_crtc *crtc;
13841
13842 for_each_intel_crtc(dev, crtc) {
13843 struct intel_unpin_work *work;
13844
13845 spin_lock_irq(&dev->event_lock);
13846
13847 work = crtc->unpin_work;
13848
13849 if (work && work->event &&
13850 work->event->base.file_priv == file) {
13851 kfree(work->event);
13852 work->event = NULL;
13853 }
13854
13855 spin_unlock_irq(&dev->event_lock);
13856 }
13857 }
Linux kernel - Deliverables
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