2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
977 * wait for the pipe register state bit to turn off
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
984 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
989 enum pipe pipe
= crtc
->pipe
;
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1266 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1269 if (!intel_display_power_enabled(dev_priv
,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1273 reg
= PIPECONF(cpu_transcoder
);
1274 val
= I915_READ(reg
);
1275 cur_state
= !!(val
& PIPECONF_ENABLE
);
1278 WARN(cur_state
!= state
,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1283 static void assert_plane(struct drm_i915_private
*dev_priv
,
1284 enum plane plane
, bool state
)
1290 reg
= DSPCNTR(plane
);
1291 val
= I915_READ(reg
);
1292 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1293 WARN(cur_state
!= state
,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane
), state_string(state
), state_string(cur_state
));
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1301 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1304 struct drm_device
*dev
= dev_priv
->dev
;
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev
)->gen
>= 4) {
1311 reg
= DSPCNTR(pipe
);
1312 val
= I915_READ(reg
);
1313 WARN(val
& DISPLAY_PLANE_ENABLE
,
1314 "plane %c assertion failure, should be disabled but not\n",
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv
, i
) {
1322 val
= I915_READ(reg
);
1323 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1324 DISPPLANE_SEL_PIPE_SHIFT
;
1325 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i
), pipe_name(pipe
));
1331 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1334 struct drm_device
*dev
= dev_priv
->dev
;
1338 if (IS_VALLEYVIEW(dev
)) {
1339 for_each_sprite(pipe
, sprite
) {
1340 reg
= SPCNTR(pipe
, sprite
);
1341 val
= I915_READ(reg
);
1342 WARN(val
& SP_ENABLE
,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1346 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1348 val
= I915_READ(reg
);
1349 WARN(val
& SPRITE_ENABLE
,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe
), pipe_name(pipe
));
1352 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1353 reg
= DVSCNTR(pipe
);
1354 val
= I915_READ(reg
);
1355 WARN(val
& DVS_ENABLE
,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe
), pipe_name(pipe
));
1361 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1363 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1364 drm_crtc_vblank_put(crtc
);
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1374 val
= I915_READ(PCH_DREF_CONTROL
);
1375 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1376 DREF_SUPERSPREAD_SOURCE_MASK
));
1377 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1387 reg
= PCH_TRANSCONF(pipe
);
1388 val
= I915_READ(reg
);
1389 enabled
= !!(val
& TRANS_ENABLE
);
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1395 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1396 enum pipe pipe
, u32 port_sel
, u32 val
)
1398 if ((val
& DP_PORT_EN
) == 0)
1401 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1402 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1403 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1404 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1406 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1407 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1410 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1416 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1417 enum pipe pipe
, u32 val
)
1419 if ((val
& SDVO_ENABLE
) == 0)
1422 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1423 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1425 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1426 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1429 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1435 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1436 enum pipe pipe
, u32 val
)
1438 if ((val
& LVDS_PORT_EN
) == 0)
1441 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1442 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1445 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1451 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, u32 val
)
1454 if ((val
& ADPA_DAC_ENABLE
) == 0)
1456 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1457 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1460 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1466 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1467 enum pipe pipe
, int reg
, u32 port_sel
)
1469 u32 val
= I915_READ(reg
);
1470 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg
, pipe_name(pipe
));
1474 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1475 && (val
& DP_PIPEB_SELECT
),
1476 "IBX PCH dp port still using transcoder B\n");
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1480 enum pipe pipe
, int reg
)
1482 u32 val
= I915_READ(reg
);
1483 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg
, pipe_name(pipe
));
1487 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1488 && (val
& SDVO_PIPE_B_SELECT
),
1489 "IBX PCH hdmi port still using transcoder B\n");
1492 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1498 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1499 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1500 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1503 val
= I915_READ(reg
);
1504 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1509 val
= I915_READ(reg
);
1510 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1514 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1515 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1516 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1519 static void intel_init_dpio(struct drm_device
*dev
)
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 if (!IS_VALLEYVIEW(dev
))
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1531 if (IS_CHERRYVIEW(dev
)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1539 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1541 struct drm_device
*dev
= crtc
->base
.dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 int reg
= DPLL(crtc
->pipe
);
1544 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1546 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv
->dev
))
1553 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1555 I915_WRITE(reg
, dpll
);
1559 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1562 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1563 POSTING_READ(DPLL_MD(crtc
->pipe
));
1565 /* We do this three times for luck */
1566 I915_WRITE(reg
, dpll
);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg
, dpll
);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg
, dpll
);
1574 udelay(150); /* wait for warmup */
1577 static void chv_enable_pll(struct intel_crtc
*crtc
)
1579 struct drm_device
*dev
= crtc
->base
.dev
;
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 int pipe
= crtc
->pipe
;
1582 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1585 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1589 mutex_lock(&dev_priv
->dpio_lock
);
1591 /* Enable back the 10bit clock to display controller */
1592 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1593 tmp
|= DPIO_DCLKP_EN
;
1594 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1602 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1610 POSTING_READ(DPLL_MD(pipe
));
1612 mutex_unlock(&dev_priv
->dpio_lock
);
1615 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1617 struct drm_device
*dev
= crtc
->base
.dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 int reg
= DPLL(crtc
->pipe
);
1620 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1622 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1624 /* No really, not for ILK+ */
1625 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1627 /* PLL is protected by panel, make sure we can write it */
1628 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1629 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1631 I915_WRITE(reg
, dpll
);
1633 /* Wait for the clocks to stabilize. */
1637 if (INTEL_INFO(dev
)->gen
>= 4) {
1638 I915_WRITE(DPLL_MD(crtc
->pipe
),
1639 crtc
->config
.dpll_hw_state
.dpll_md
);
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1644 * So write it again.
1646 I915_WRITE(reg
, dpll
);
1649 /* We do this three times for luck */
1650 I915_WRITE(reg
, dpll
);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg
, dpll
);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg
, dpll
);
1658 udelay(150); /* wait for warmup */
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1668 * Note! This is for pre-ILK only.
1670 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1672 /* Don't disable pipe or pipe PLLs if needed */
1673 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1674 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1677 /* Make sure the pipe isn't still relying on us */
1678 assert_pipe_disabled(dev_priv
, pipe
);
1680 I915_WRITE(DPLL(pipe
), 0);
1681 POSTING_READ(DPLL(pipe
));
1684 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1688 /* Make sure the pipe isn't still relying on us */
1689 assert_pipe_disabled(dev_priv
, pipe
);
1692 * Leave integrated clock source and reference clock enabled for pipe B.
1693 * The latter is needed for VGA hotplug / manual detection.
1696 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1697 I915_WRITE(DPLL(pipe
), val
);
1698 POSTING_READ(DPLL(pipe
));
1702 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1704 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1707 /* Make sure the pipe isn't still relying on us */
1708 assert_pipe_disabled(dev_priv
, pipe
);
1710 /* Set PLL en = 0 */
1711 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1713 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1714 I915_WRITE(DPLL(pipe
), val
);
1715 POSTING_READ(DPLL(pipe
));
1717 mutex_lock(&dev_priv
->dpio_lock
);
1719 /* Disable 10bit clock to display controller */
1720 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1721 val
&= ~DPIO_DCLKP_EN
;
1722 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1724 /* disable left/right clock distribution */
1725 if (pipe
!= PIPE_B
) {
1726 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1727 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1728 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1730 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1731 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1732 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1735 mutex_unlock(&dev_priv
->dpio_lock
);
1738 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1739 struct intel_digital_port
*dport
)
1744 switch (dport
->port
) {
1746 port_mask
= DPLL_PORTB_READY_MASK
;
1750 port_mask
= DPLL_PORTC_READY_MASK
;
1754 port_mask
= DPLL_PORTD_READY_MASK
;
1755 dpll_reg
= DPIO_PHY_STATUS
;
1761 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1762 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1763 port_name(dport
->port
), I915_READ(dpll_reg
));
1766 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1768 struct drm_device
*dev
= crtc
->base
.dev
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1772 if (WARN_ON(pll
== NULL
))
1775 WARN_ON(!pll
->refcount
);
1776 if (pll
->active
== 0) {
1777 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1779 assert_shared_dpll_disabled(dev_priv
, pll
);
1781 pll
->mode_set(dev_priv
, pll
);
1786 * intel_enable_shared_dpll - enable PCH PLL
1787 * @dev_priv: i915 private structure
1788 * @pipe: pipe PLL to enable
1790 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1791 * drives the transcoder clock.
1793 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1795 struct drm_device
*dev
= crtc
->base
.dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1799 if (WARN_ON(pll
== NULL
))
1802 if (WARN_ON(pll
->refcount
== 0))
1805 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1806 pll
->name
, pll
->active
, pll
->on
,
1807 crtc
->base
.base
.id
);
1809 if (pll
->active
++) {
1811 assert_shared_dpll_enabled(dev_priv
, pll
);
1816 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1818 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1819 pll
->enable(dev_priv
, pll
);
1823 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1825 struct drm_device
*dev
= crtc
->base
.dev
;
1826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1827 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1829 /* PCH only available on ILK+ */
1830 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1831 if (WARN_ON(pll
== NULL
))
1834 if (WARN_ON(pll
->refcount
== 0))
1837 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1838 pll
->name
, pll
->active
, pll
->on
,
1839 crtc
->base
.base
.id
);
1841 if (WARN_ON(pll
->active
== 0)) {
1842 assert_shared_dpll_disabled(dev_priv
, pll
);
1846 assert_shared_dpll_enabled(dev_priv
, pll
);
1851 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1852 pll
->disable(dev_priv
, pll
);
1855 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1858 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1861 struct drm_device
*dev
= dev_priv
->dev
;
1862 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1863 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1864 uint32_t reg
, val
, pipeconf_val
;
1866 /* PCH only available on ILK+ */
1867 BUG_ON(!HAS_PCH_SPLIT(dev
));
1869 /* Make sure PCH DPLL is enabled */
1870 assert_shared_dpll_enabled(dev_priv
,
1871 intel_crtc_to_shared_dpll(intel_crtc
));
1873 /* FDI must be feeding us bits for PCH ports */
1874 assert_fdi_tx_enabled(dev_priv
, pipe
);
1875 assert_fdi_rx_enabled(dev_priv
, pipe
);
1877 if (HAS_PCH_CPT(dev
)) {
1878 /* Workaround: Set the timing override bit before enabling the
1879 * pch transcoder. */
1880 reg
= TRANS_CHICKEN2(pipe
);
1881 val
= I915_READ(reg
);
1882 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1883 I915_WRITE(reg
, val
);
1886 reg
= PCH_TRANSCONF(pipe
);
1887 val
= I915_READ(reg
);
1888 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1890 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1892 * make the BPC in transcoder be consistent with
1893 * that in pipeconf reg.
1895 val
&= ~PIPECONF_BPC_MASK
;
1896 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1899 val
&= ~TRANS_INTERLACE_MASK
;
1900 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1901 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1902 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1903 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1905 val
|= TRANS_INTERLACED
;
1907 val
|= TRANS_PROGRESSIVE
;
1909 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1910 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1911 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1914 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1915 enum transcoder cpu_transcoder
)
1917 u32 val
, pipeconf_val
;
1919 /* PCH only available on ILK+ */
1920 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1922 /* FDI must be feeding us bits for PCH ports */
1923 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1924 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1926 /* Workaround: set timing override bit. */
1927 val
= I915_READ(_TRANSA_CHICKEN2
);
1928 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1929 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1932 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1934 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1935 PIPECONF_INTERLACED_ILK
)
1936 val
|= TRANS_INTERLACED
;
1938 val
|= TRANS_PROGRESSIVE
;
1940 I915_WRITE(LPT_TRANSCONF
, val
);
1941 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1942 DRM_ERROR("Failed to enable PCH transcoder\n");
1945 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1948 struct drm_device
*dev
= dev_priv
->dev
;
1951 /* FDI relies on the transcoder */
1952 assert_fdi_tx_disabled(dev_priv
, pipe
);
1953 assert_fdi_rx_disabled(dev_priv
, pipe
);
1955 /* Ports must be off as well */
1956 assert_pch_ports_disabled(dev_priv
, pipe
);
1958 reg
= PCH_TRANSCONF(pipe
);
1959 val
= I915_READ(reg
);
1960 val
&= ~TRANS_ENABLE
;
1961 I915_WRITE(reg
, val
);
1962 /* wait for PCH transcoder off, transcoder state */
1963 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1964 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1966 if (!HAS_PCH_IBX(dev
)) {
1967 /* Workaround: Clear the timing override chicken bit again. */
1968 reg
= TRANS_CHICKEN2(pipe
);
1969 val
= I915_READ(reg
);
1970 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1971 I915_WRITE(reg
, val
);
1975 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1979 val
= I915_READ(LPT_TRANSCONF
);
1980 val
&= ~TRANS_ENABLE
;
1981 I915_WRITE(LPT_TRANSCONF
, val
);
1982 /* wait for PCH transcoder off, transcoder state */
1983 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1984 DRM_ERROR("Failed to disable PCH transcoder\n");
1986 /* Workaround: clear timing override bit. */
1987 val
= I915_READ(_TRANSA_CHICKEN2
);
1988 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1989 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1993 * intel_enable_pipe - enable a pipe, asserting requirements
1994 * @crtc: crtc responsible for the pipe
1996 * Enable @crtc's pipe, making sure that various hardware specific requirements
1997 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1999 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2001 struct drm_device
*dev
= crtc
->base
.dev
;
2002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2003 enum pipe pipe
= crtc
->pipe
;
2004 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2006 enum pipe pch_transcoder
;
2010 assert_planes_disabled(dev_priv
, pipe
);
2011 assert_cursor_disabled(dev_priv
, pipe
);
2012 assert_sprites_disabled(dev_priv
, pipe
);
2014 if (HAS_PCH_LPT(dev_priv
->dev
))
2015 pch_transcoder
= TRANSCODER_A
;
2017 pch_transcoder
= pipe
;
2020 * A pipe without a PLL won't actually be able to drive bits from
2021 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2024 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2025 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2026 assert_dsi_pll_enabled(dev_priv
);
2028 assert_pll_enabled(dev_priv
, pipe
);
2030 if (crtc
->config
.has_pch_encoder
) {
2031 /* if driving the PCH, we need FDI enabled */
2032 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2033 assert_fdi_tx_pll_enabled(dev_priv
,
2034 (enum pipe
) cpu_transcoder
);
2036 /* FIXME: assert CPU port conditions for SNB+ */
2039 reg
= PIPECONF(cpu_transcoder
);
2040 val
= I915_READ(reg
);
2041 if (val
& PIPECONF_ENABLE
) {
2042 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2043 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2047 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2052 * intel_disable_pipe - disable a pipe, asserting requirements
2053 * @crtc: crtc whose pipes is to be disabled
2055 * Disable the pipe of @crtc, making sure that various hardware
2056 * specific requirements are met, if applicable, e.g. plane
2057 * disabled, panel fitter off, etc.
2059 * Will wait until the pipe has shut down before returning.
2061 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2063 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2064 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2065 enum pipe pipe
= crtc
->pipe
;
2070 * Make sure planes won't keep trying to pump pixels to us,
2071 * or we might hang the display.
2073 assert_planes_disabled(dev_priv
, pipe
);
2074 assert_cursor_disabled(dev_priv
, pipe
);
2075 assert_sprites_disabled(dev_priv
, pipe
);
2077 reg
= PIPECONF(cpu_transcoder
);
2078 val
= I915_READ(reg
);
2079 if ((val
& PIPECONF_ENABLE
) == 0)
2083 * Double wide has implications for planes
2084 * so best keep it disabled when not needed.
2086 if (crtc
->config
.double_wide
)
2087 val
&= ~PIPECONF_DOUBLE_WIDE
;
2089 /* Don't disable pipe or pipe PLLs if needed */
2090 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2091 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2092 val
&= ~PIPECONF_ENABLE
;
2094 I915_WRITE(reg
, val
);
2095 if ((val
& PIPECONF_ENABLE
) == 0)
2096 intel_wait_for_pipe_off(crtc
);
2100 * Plane regs are double buffered, going from enabled->disabled needs a
2101 * trigger in order to latch. The display address reg provides this.
2103 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2106 struct drm_device
*dev
= dev_priv
->dev
;
2107 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2109 I915_WRITE(reg
, I915_READ(reg
));
2114 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2115 * @plane: plane to be enabled
2116 * @crtc: crtc for the plane
2118 * Enable @plane on @crtc, making sure that the pipe is running first.
2120 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2121 struct drm_crtc
*crtc
)
2123 struct drm_device
*dev
= plane
->dev
;
2124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2130 if (intel_crtc
->primary_enabled
)
2133 intel_crtc
->primary_enabled
= true;
2135 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2139 * BDW signals flip done immediately if the plane
2140 * is disabled, even if the plane enable is already
2141 * armed to occur at the next vblank :(
2143 if (IS_BROADWELL(dev
))
2144 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2148 * intel_disable_primary_hw_plane - disable the primary hardware plane
2149 * @plane: plane to be disabled
2150 * @crtc: crtc for the plane
2152 * Disable @plane on @crtc, making sure that the pipe is running first.
2154 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2155 struct drm_crtc
*crtc
)
2157 struct drm_device
*dev
= plane
->dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2161 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2163 if (!intel_crtc
->primary_enabled
)
2166 intel_crtc
->primary_enabled
= false;
2168 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2172 static bool need_vtd_wa(struct drm_device
*dev
)
2174 #ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2181 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2185 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2186 return ALIGN(height
, tile_height
);
2190 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2191 struct drm_i915_gem_object
*obj
,
2192 struct intel_engine_cs
*pipelined
)
2194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2198 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2200 switch (obj
->tiling_mode
) {
2201 case I915_TILING_NONE
:
2202 if (INTEL_INFO(dev
)->gen
>= 9)
2203 alignment
= 256 * 1024;
2204 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2205 alignment
= 128 * 1024;
2206 else if (INTEL_INFO(dev
)->gen
>= 4)
2207 alignment
= 4 * 1024;
2209 alignment
= 64 * 1024;
2212 if (INTEL_INFO(dev
)->gen
>= 9)
2213 alignment
= 256 * 1024;
2215 /* pin() will align the object as required by fence */
2220 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2226 /* Note that the w/a also requires 64 PTE of padding following the
2227 * bo. We currently fill all unused PTE with the shadow page and so
2228 * we should always have valid PTE following the scanout preventing
2231 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2232 alignment
= 256 * 1024;
2235 * Global gtt pte registers are special registers which actually forward
2236 * writes to a chunk of system memory. Which means that there is no risk
2237 * that the register values disappear as soon as we call
2238 * intel_runtime_pm_put(), so it is correct to wrap only the
2239 * pin/unpin/fence and not more.
2241 intel_runtime_pm_get(dev_priv
);
2243 dev_priv
->mm
.interruptible
= false;
2244 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2246 goto err_interruptible
;
2248 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2249 * fence, whereas 965+ only requires a fence if using
2250 * framebuffer compression. For simplicity, we always install
2251 * a fence as the cost is not that onerous.
2253 ret
= i915_gem_object_get_fence(obj
);
2257 i915_gem_object_pin_fence(obj
);
2259 dev_priv
->mm
.interruptible
= true;
2260 intel_runtime_pm_put(dev_priv
);
2264 i915_gem_object_unpin_from_display_plane(obj
);
2266 dev_priv
->mm
.interruptible
= true;
2267 intel_runtime_pm_put(dev_priv
);
2271 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2273 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2275 i915_gem_object_unpin_fence(obj
);
2276 i915_gem_object_unpin_from_display_plane(obj
);
2279 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2280 * is assumed to be a power-of-two. */
2281 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2282 unsigned int tiling_mode
,
2286 if (tiling_mode
!= I915_TILING_NONE
) {
2287 unsigned int tile_rows
, tiles
;
2292 tiles
= *x
/ (512/cpp
);
2295 return tile_rows
* pitch
* 8 + tiles
* 4096;
2297 unsigned int offset
;
2299 offset
= *y
* pitch
+ *x
* cpp
;
2301 *x
= (offset
& 4095) / cpp
;
2302 return offset
& -4096;
2306 int intel_format_to_fourcc(int format
)
2309 case DISPPLANE_8BPP
:
2310 return DRM_FORMAT_C8
;
2311 case DISPPLANE_BGRX555
:
2312 return DRM_FORMAT_XRGB1555
;
2313 case DISPPLANE_BGRX565
:
2314 return DRM_FORMAT_RGB565
;
2316 case DISPPLANE_BGRX888
:
2317 return DRM_FORMAT_XRGB8888
;
2318 case DISPPLANE_RGBX888
:
2319 return DRM_FORMAT_XBGR8888
;
2320 case DISPPLANE_BGRX101010
:
2321 return DRM_FORMAT_XRGB2101010
;
2322 case DISPPLANE_RGBX101010
:
2323 return DRM_FORMAT_XBGR2101010
;
2327 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2328 struct intel_plane_config
*plane_config
)
2330 struct drm_device
*dev
= crtc
->base
.dev
;
2331 struct drm_i915_gem_object
*obj
= NULL
;
2332 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2333 u32 base
= plane_config
->base
;
2335 if (plane_config
->size
== 0)
2338 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2339 plane_config
->size
);
2343 if (plane_config
->tiled
) {
2344 obj
->tiling_mode
= I915_TILING_X
;
2345 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2348 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2349 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2350 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2351 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2353 mutex_lock(&dev
->struct_mutex
);
2355 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2357 DRM_DEBUG_KMS("intel fb init failed\n");
2361 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2362 mutex_unlock(&dev
->struct_mutex
);
2364 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2368 drm_gem_object_unreference(&obj
->base
);
2369 mutex_unlock(&dev
->struct_mutex
);
2373 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2374 struct intel_plane_config
*plane_config
)
2376 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2378 struct intel_crtc
*i
;
2379 struct drm_i915_gem_object
*obj
;
2381 if (!intel_crtc
->base
.primary
->fb
)
2384 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2387 kfree(intel_crtc
->base
.primary
->fb
);
2388 intel_crtc
->base
.primary
->fb
= NULL
;
2391 * Failed to alloc the obj, check to see if we should share
2392 * an fb with another CRTC instead
2394 for_each_crtc(dev
, c
) {
2395 i
= to_intel_crtc(c
);
2397 if (c
== &intel_crtc
->base
)
2403 obj
= intel_fb_obj(c
->primary
->fb
);
2407 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2408 drm_framebuffer_reference(c
->primary
->fb
);
2409 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2410 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2416 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2417 struct drm_framebuffer
*fb
,
2420 struct drm_device
*dev
= crtc
->dev
;
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2423 struct drm_i915_gem_object
*obj
;
2424 int plane
= intel_crtc
->plane
;
2425 unsigned long linear_offset
;
2427 u32 reg
= DSPCNTR(plane
);
2430 if (!intel_crtc
->primary_enabled
) {
2432 if (INTEL_INFO(dev
)->gen
>= 4)
2433 I915_WRITE(DSPSURF(plane
), 0);
2435 I915_WRITE(DSPADDR(plane
), 0);
2440 obj
= intel_fb_obj(fb
);
2441 if (WARN_ON(obj
== NULL
))
2444 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2446 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2448 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2450 if (INTEL_INFO(dev
)->gen
< 4) {
2451 if (intel_crtc
->pipe
== PIPE_B
)
2452 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2454 /* pipesrc and dspsize control the size that is scaled from,
2455 * which should always be the user's requested size.
2457 I915_WRITE(DSPSIZE(plane
),
2458 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2459 (intel_crtc
->config
.pipe_src_w
- 1));
2460 I915_WRITE(DSPPOS(plane
), 0);
2463 switch (fb
->pixel_format
) {
2465 dspcntr
|= DISPPLANE_8BPP
;
2467 case DRM_FORMAT_XRGB1555
:
2468 case DRM_FORMAT_ARGB1555
:
2469 dspcntr
|= DISPPLANE_BGRX555
;
2471 case DRM_FORMAT_RGB565
:
2472 dspcntr
|= DISPPLANE_BGRX565
;
2474 case DRM_FORMAT_XRGB8888
:
2475 case DRM_FORMAT_ARGB8888
:
2476 dspcntr
|= DISPPLANE_BGRX888
;
2478 case DRM_FORMAT_XBGR8888
:
2479 case DRM_FORMAT_ABGR8888
:
2480 dspcntr
|= DISPPLANE_RGBX888
;
2482 case DRM_FORMAT_XRGB2101010
:
2483 case DRM_FORMAT_ARGB2101010
:
2484 dspcntr
|= DISPPLANE_BGRX101010
;
2486 case DRM_FORMAT_XBGR2101010
:
2487 case DRM_FORMAT_ABGR2101010
:
2488 dspcntr
|= DISPPLANE_RGBX101010
;
2494 if (INTEL_INFO(dev
)->gen
>= 4 &&
2495 obj
->tiling_mode
!= I915_TILING_NONE
)
2496 dspcntr
|= DISPPLANE_TILED
;
2499 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2501 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2503 if (INTEL_INFO(dev
)->gen
>= 4) {
2504 intel_crtc
->dspaddr_offset
=
2505 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2508 linear_offset
-= intel_crtc
->dspaddr_offset
;
2510 intel_crtc
->dspaddr_offset
= linear_offset
;
2513 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2514 dspcntr
|= DISPPLANE_ROTATE_180
;
2516 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2517 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2519 /* Finding the last pixel of the last line of the display
2520 data and adding to linear_offset*/
2522 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2523 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2526 I915_WRITE(reg
, dspcntr
);
2528 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2529 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2531 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2532 if (INTEL_INFO(dev
)->gen
>= 4) {
2533 I915_WRITE(DSPSURF(plane
),
2534 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2535 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2536 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2538 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2542 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2543 struct drm_framebuffer
*fb
,
2546 struct drm_device
*dev
= crtc
->dev
;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2549 struct drm_i915_gem_object
*obj
;
2550 int plane
= intel_crtc
->plane
;
2551 unsigned long linear_offset
;
2553 u32 reg
= DSPCNTR(plane
);
2556 if (!intel_crtc
->primary_enabled
) {
2558 I915_WRITE(DSPSURF(plane
), 0);
2563 obj
= intel_fb_obj(fb
);
2564 if (WARN_ON(obj
== NULL
))
2567 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2569 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2571 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2573 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2574 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2576 switch (fb
->pixel_format
) {
2578 dspcntr
|= DISPPLANE_8BPP
;
2580 case DRM_FORMAT_RGB565
:
2581 dspcntr
|= DISPPLANE_BGRX565
;
2583 case DRM_FORMAT_XRGB8888
:
2584 case DRM_FORMAT_ARGB8888
:
2585 dspcntr
|= DISPPLANE_BGRX888
;
2587 case DRM_FORMAT_XBGR8888
:
2588 case DRM_FORMAT_ABGR8888
:
2589 dspcntr
|= DISPPLANE_RGBX888
;
2591 case DRM_FORMAT_XRGB2101010
:
2592 case DRM_FORMAT_ARGB2101010
:
2593 dspcntr
|= DISPPLANE_BGRX101010
;
2595 case DRM_FORMAT_XBGR2101010
:
2596 case DRM_FORMAT_ABGR2101010
:
2597 dspcntr
|= DISPPLANE_RGBX101010
;
2603 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2604 dspcntr
|= DISPPLANE_TILED
;
2606 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2607 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2609 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2610 intel_crtc
->dspaddr_offset
=
2611 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2614 linear_offset
-= intel_crtc
->dspaddr_offset
;
2615 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2616 dspcntr
|= DISPPLANE_ROTATE_180
;
2618 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2619 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2620 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2622 /* Finding the last pixel of the last line of the display
2623 data and adding to linear_offset*/
2625 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2626 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2630 I915_WRITE(reg
, dspcntr
);
2632 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2633 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2635 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2636 I915_WRITE(DSPSURF(plane
),
2637 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2638 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2639 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2641 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2642 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2647 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2648 struct drm_framebuffer
*fb
,
2651 struct drm_device
*dev
= crtc
->dev
;
2652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2653 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2654 struct intel_framebuffer
*intel_fb
;
2655 struct drm_i915_gem_object
*obj
;
2656 int pipe
= intel_crtc
->pipe
;
2657 u32 plane_ctl
, stride
;
2659 if (!intel_crtc
->primary_enabled
) {
2660 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2661 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2662 POSTING_READ(PLANE_CTL(pipe
, 0));
2666 plane_ctl
= PLANE_CTL_ENABLE
|
2667 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2668 PLANE_CTL_PIPE_CSC_ENABLE
;
2670 switch (fb
->pixel_format
) {
2671 case DRM_FORMAT_RGB565
:
2672 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2674 case DRM_FORMAT_XRGB8888
:
2675 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2677 case DRM_FORMAT_XBGR8888
:
2678 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2679 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2681 case DRM_FORMAT_XRGB2101010
:
2682 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2684 case DRM_FORMAT_XBGR2101010
:
2685 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2686 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2692 intel_fb
= to_intel_framebuffer(fb
);
2693 obj
= intel_fb
->obj
;
2696 * The stride is either expressed as a multiple of 64 bytes chunks for
2697 * linear buffers or in number of tiles for tiled buffers.
2699 switch (obj
->tiling_mode
) {
2700 case I915_TILING_NONE
:
2701 stride
= fb
->pitches
[0] >> 6;
2704 plane_ctl
|= PLANE_CTL_TILED_X
;
2705 stride
= fb
->pitches
[0] >> 9;
2711 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2713 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2715 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2716 i915_gem_obj_ggtt_offset(obj
),
2717 x
, y
, fb
->width
, fb
->height
,
2720 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2721 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2722 I915_WRITE(PLANE_SIZE(pipe
, 0),
2723 (intel_crtc
->config
.pipe_src_h
- 1) << 16 |
2724 (intel_crtc
->config
.pipe_src_w
- 1));
2725 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2726 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2728 POSTING_READ(PLANE_SURF(pipe
, 0));
2731 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2733 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2734 int x
, int y
, enum mode_set_atomic state
)
2736 struct drm_device
*dev
= crtc
->dev
;
2737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 if (dev_priv
->display
.disable_fbc
)
2740 dev_priv
->display
.disable_fbc(dev
);
2741 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2743 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2748 void intel_display_handle_reset(struct drm_device
*dev
)
2750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2751 struct drm_crtc
*crtc
;
2754 * Flips in the rings have been nuked by the reset,
2755 * so complete all pending flips so that user space
2756 * will get its events and not get stuck.
2758 * Also update the base address of all primary
2759 * planes to the the last fb to make sure we're
2760 * showing the correct fb after a reset.
2762 * Need to make two loops over the crtcs so that we
2763 * don't try to grab a crtc mutex before the
2764 * pending_flip_queue really got woken up.
2767 for_each_crtc(dev
, crtc
) {
2768 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2769 enum plane plane
= intel_crtc
->plane
;
2771 intel_prepare_page_flip(dev
, plane
);
2772 intel_finish_page_flip_plane(dev
, plane
);
2775 for_each_crtc(dev
, crtc
) {
2776 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2778 drm_modeset_lock(&crtc
->mutex
, NULL
);
2780 * FIXME: Once we have proper support for primary planes (and
2781 * disabling them without disabling the entire crtc) allow again
2782 * a NULL crtc->primary->fb.
2784 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2785 dev_priv
->display
.update_primary_plane(crtc
,
2789 drm_modeset_unlock(&crtc
->mutex
);
2794 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2796 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2797 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2798 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2801 /* Big Hammer, we also need to ensure that any pending
2802 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2803 * current scanout is retired before unpinning the old
2806 * This should only fail upon a hung GPU, in which case we
2807 * can safely continue.
2809 dev_priv
->mm
.interruptible
= false;
2810 ret
= i915_gem_object_finish_gpu(obj
);
2811 dev_priv
->mm
.interruptible
= was_interruptible
;
2816 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2818 struct drm_device
*dev
= crtc
->dev
;
2819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2821 unsigned long flags
;
2824 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2825 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2828 spin_lock_irqsave(&dev
->event_lock
, flags
);
2829 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2830 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2836 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2837 struct drm_framebuffer
*fb
)
2839 struct drm_device
*dev
= crtc
->dev
;
2840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2841 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2842 enum pipe pipe
= intel_crtc
->pipe
;
2843 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2844 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2845 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2848 if (intel_crtc_has_pending_flip(crtc
)) {
2849 DRM_ERROR("pipe is still busy with an old pageflip\n");
2855 DRM_ERROR("No FB bound\n");
2859 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2860 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2861 plane_name(intel_crtc
->plane
),
2862 INTEL_INFO(dev
)->num_pipes
);
2866 mutex_lock(&dev
->struct_mutex
);
2867 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2869 i915_gem_track_fb(old_obj
, obj
,
2870 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2871 mutex_unlock(&dev
->struct_mutex
);
2873 DRM_ERROR("pin & fence failed\n");
2878 * Update pipe size and adjust fitter if needed: the reason for this is
2879 * that in compute_mode_changes we check the native mode (not the pfit
2880 * mode) to see if we can flip rather than do a full mode set. In the
2881 * fastboot case, we'll flip, but if we don't update the pipesrc and
2882 * pfit state, we'll end up with a big fb scanned out into the wrong
2885 * To fix this properly, we need to hoist the checks up into
2886 * compute_mode_changes (or above), check the actual pfit state and
2887 * whether the platform allows pfit disable with pipe active, and only
2888 * then update the pipesrc and pfit state, even on the flip path.
2890 if (i915
.fastboot
) {
2891 const struct drm_display_mode
*adjusted_mode
=
2892 &intel_crtc
->config
.adjusted_mode
;
2894 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2895 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2896 (adjusted_mode
->crtc_vdisplay
- 1));
2897 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2898 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2899 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2900 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2901 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2902 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2904 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2905 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2908 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2910 if (intel_crtc
->active
)
2911 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2913 crtc
->primary
->fb
= fb
;
2918 if (intel_crtc
->active
&& old_fb
!= fb
)
2919 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2920 mutex_lock(&dev
->struct_mutex
);
2921 intel_unpin_fb_obj(old_obj
);
2922 mutex_unlock(&dev
->struct_mutex
);
2925 mutex_lock(&dev
->struct_mutex
);
2926 intel_update_fbc(dev
);
2927 mutex_unlock(&dev
->struct_mutex
);
2932 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2934 struct drm_device
*dev
= crtc
->dev
;
2935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2936 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2937 int pipe
= intel_crtc
->pipe
;
2940 /* enable normal train */
2941 reg
= FDI_TX_CTL(pipe
);
2942 temp
= I915_READ(reg
);
2943 if (IS_IVYBRIDGE(dev
)) {
2944 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2945 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2947 temp
&= ~FDI_LINK_TRAIN_NONE
;
2948 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2950 I915_WRITE(reg
, temp
);
2952 reg
= FDI_RX_CTL(pipe
);
2953 temp
= I915_READ(reg
);
2954 if (HAS_PCH_CPT(dev
)) {
2955 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2956 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2958 temp
&= ~FDI_LINK_TRAIN_NONE
;
2959 temp
|= FDI_LINK_TRAIN_NONE
;
2961 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2963 /* wait one idle pattern time */
2967 /* IVB wants error correction enabled */
2968 if (IS_IVYBRIDGE(dev
))
2969 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2970 FDI_FE_ERRC_ENABLE
);
2973 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2975 return crtc
->base
.enabled
&& crtc
->active
&&
2976 crtc
->config
.has_pch_encoder
;
2979 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2982 struct intel_crtc
*pipe_B_crtc
=
2983 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2984 struct intel_crtc
*pipe_C_crtc
=
2985 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2989 * When everything is off disable fdi C so that we could enable fdi B
2990 * with all lanes. Note that we don't care about enabled pipes without
2991 * an enabled pch encoder.
2993 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2994 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2995 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2996 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2998 temp
= I915_READ(SOUTH_CHICKEN1
);
2999 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3000 DRM_DEBUG_KMS("disabling fdi C rx\n");
3001 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3005 /* The FDI link training functions for ILK/Ibexpeak. */
3006 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3008 struct drm_device
*dev
= crtc
->dev
;
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3011 int pipe
= intel_crtc
->pipe
;
3012 u32 reg
, temp
, tries
;
3014 /* FDI needs bits from pipe first */
3015 assert_pipe_enabled(dev_priv
, pipe
);
3017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3019 reg
= FDI_RX_IMR(pipe
);
3020 temp
= I915_READ(reg
);
3021 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3022 temp
&= ~FDI_RX_BIT_LOCK
;
3023 I915_WRITE(reg
, temp
);
3027 /* enable CPU FDI TX and PCH FDI RX */
3028 reg
= FDI_TX_CTL(pipe
);
3029 temp
= I915_READ(reg
);
3030 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3031 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3032 temp
&= ~FDI_LINK_TRAIN_NONE
;
3033 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3034 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3036 reg
= FDI_RX_CTL(pipe
);
3037 temp
= I915_READ(reg
);
3038 temp
&= ~FDI_LINK_TRAIN_NONE
;
3039 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3040 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3045 /* Ironlake workaround, enable clock pointer after FDI enable*/
3046 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3047 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3048 FDI_RX_PHASE_SYNC_POINTER_EN
);
3050 reg
= FDI_RX_IIR(pipe
);
3051 for (tries
= 0; tries
< 5; tries
++) {
3052 temp
= I915_READ(reg
);
3053 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3055 if ((temp
& FDI_RX_BIT_LOCK
)) {
3056 DRM_DEBUG_KMS("FDI train 1 done.\n");
3057 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3062 DRM_ERROR("FDI train 1 fail!\n");
3065 reg
= FDI_TX_CTL(pipe
);
3066 temp
= I915_READ(reg
);
3067 temp
&= ~FDI_LINK_TRAIN_NONE
;
3068 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3069 I915_WRITE(reg
, temp
);
3071 reg
= FDI_RX_CTL(pipe
);
3072 temp
= I915_READ(reg
);
3073 temp
&= ~FDI_LINK_TRAIN_NONE
;
3074 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3075 I915_WRITE(reg
, temp
);
3080 reg
= FDI_RX_IIR(pipe
);
3081 for (tries
= 0; tries
< 5; tries
++) {
3082 temp
= I915_READ(reg
);
3083 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3085 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3086 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3087 DRM_DEBUG_KMS("FDI train 2 done.\n");
3092 DRM_ERROR("FDI train 2 fail!\n");
3094 DRM_DEBUG_KMS("FDI train done\n");
3098 static const int snb_b_fdi_train_param
[] = {
3099 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3100 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3101 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3102 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3105 /* The FDI link training functions for SNB/Cougarpoint. */
3106 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3108 struct drm_device
*dev
= crtc
->dev
;
3109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3110 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3111 int pipe
= intel_crtc
->pipe
;
3112 u32 reg
, temp
, i
, retry
;
3114 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3116 reg
= FDI_RX_IMR(pipe
);
3117 temp
= I915_READ(reg
);
3118 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3119 temp
&= ~FDI_RX_BIT_LOCK
;
3120 I915_WRITE(reg
, temp
);
3125 /* enable CPU FDI TX and PCH FDI RX */
3126 reg
= FDI_TX_CTL(pipe
);
3127 temp
= I915_READ(reg
);
3128 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3129 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3130 temp
&= ~FDI_LINK_TRAIN_NONE
;
3131 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3132 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3134 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3135 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3137 I915_WRITE(FDI_RX_MISC(pipe
),
3138 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3140 reg
= FDI_RX_CTL(pipe
);
3141 temp
= I915_READ(reg
);
3142 if (HAS_PCH_CPT(dev
)) {
3143 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3144 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3146 temp
&= ~FDI_LINK_TRAIN_NONE
;
3147 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3149 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3154 for (i
= 0; i
< 4; i
++) {
3155 reg
= FDI_TX_CTL(pipe
);
3156 temp
= I915_READ(reg
);
3157 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3158 temp
|= snb_b_fdi_train_param
[i
];
3159 I915_WRITE(reg
, temp
);
3164 for (retry
= 0; retry
< 5; retry
++) {
3165 reg
= FDI_RX_IIR(pipe
);
3166 temp
= I915_READ(reg
);
3167 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3168 if (temp
& FDI_RX_BIT_LOCK
) {
3169 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3170 DRM_DEBUG_KMS("FDI train 1 done.\n");
3179 DRM_ERROR("FDI train 1 fail!\n");
3182 reg
= FDI_TX_CTL(pipe
);
3183 temp
= I915_READ(reg
);
3184 temp
&= ~FDI_LINK_TRAIN_NONE
;
3185 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3187 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3189 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3191 I915_WRITE(reg
, temp
);
3193 reg
= FDI_RX_CTL(pipe
);
3194 temp
= I915_READ(reg
);
3195 if (HAS_PCH_CPT(dev
)) {
3196 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3197 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3199 temp
&= ~FDI_LINK_TRAIN_NONE
;
3200 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3202 I915_WRITE(reg
, temp
);
3207 for (i
= 0; i
< 4; i
++) {
3208 reg
= FDI_TX_CTL(pipe
);
3209 temp
= I915_READ(reg
);
3210 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3211 temp
|= snb_b_fdi_train_param
[i
];
3212 I915_WRITE(reg
, temp
);
3217 for (retry
= 0; retry
< 5; retry
++) {
3218 reg
= FDI_RX_IIR(pipe
);
3219 temp
= I915_READ(reg
);
3220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3221 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3222 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3223 DRM_DEBUG_KMS("FDI train 2 done.\n");
3232 DRM_ERROR("FDI train 2 fail!\n");
3234 DRM_DEBUG_KMS("FDI train done.\n");
3237 /* Manual link training for Ivy Bridge A0 parts */
3238 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3240 struct drm_device
*dev
= crtc
->dev
;
3241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3243 int pipe
= intel_crtc
->pipe
;
3244 u32 reg
, temp
, i
, j
;
3246 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3248 reg
= FDI_RX_IMR(pipe
);
3249 temp
= I915_READ(reg
);
3250 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3251 temp
&= ~FDI_RX_BIT_LOCK
;
3252 I915_WRITE(reg
, temp
);
3257 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3258 I915_READ(FDI_RX_IIR(pipe
)));
3260 /* Try each vswing and preemphasis setting twice before moving on */
3261 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3262 /* disable first in case we need to retry */
3263 reg
= FDI_TX_CTL(pipe
);
3264 temp
= I915_READ(reg
);
3265 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3266 temp
&= ~FDI_TX_ENABLE
;
3267 I915_WRITE(reg
, temp
);
3269 reg
= FDI_RX_CTL(pipe
);
3270 temp
= I915_READ(reg
);
3271 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3272 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3273 temp
&= ~FDI_RX_ENABLE
;
3274 I915_WRITE(reg
, temp
);
3276 /* enable CPU FDI TX and PCH FDI RX */
3277 reg
= FDI_TX_CTL(pipe
);
3278 temp
= I915_READ(reg
);
3279 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3280 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3281 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3282 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3283 temp
|= snb_b_fdi_train_param
[j
/2];
3284 temp
|= FDI_COMPOSITE_SYNC
;
3285 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3287 I915_WRITE(FDI_RX_MISC(pipe
),
3288 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3290 reg
= FDI_RX_CTL(pipe
);
3291 temp
= I915_READ(reg
);
3292 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3293 temp
|= FDI_COMPOSITE_SYNC
;
3294 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3297 udelay(1); /* should be 0.5us */
3299 for (i
= 0; i
< 4; i
++) {
3300 reg
= FDI_RX_IIR(pipe
);
3301 temp
= I915_READ(reg
);
3302 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3304 if (temp
& FDI_RX_BIT_LOCK
||
3305 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3306 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3307 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3311 udelay(1); /* should be 0.5us */
3314 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3319 reg
= FDI_TX_CTL(pipe
);
3320 temp
= I915_READ(reg
);
3321 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3322 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3323 I915_WRITE(reg
, temp
);
3325 reg
= FDI_RX_CTL(pipe
);
3326 temp
= I915_READ(reg
);
3327 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3328 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3329 I915_WRITE(reg
, temp
);
3332 udelay(2); /* should be 1.5us */
3334 for (i
= 0; i
< 4; i
++) {
3335 reg
= FDI_RX_IIR(pipe
);
3336 temp
= I915_READ(reg
);
3337 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3339 if (temp
& FDI_RX_SYMBOL_LOCK
||
3340 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3341 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3342 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3346 udelay(2); /* should be 1.5us */
3349 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3353 DRM_DEBUG_KMS("FDI train done.\n");
3356 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3358 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3360 int pipe
= intel_crtc
->pipe
;
3364 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3365 reg
= FDI_RX_CTL(pipe
);
3366 temp
= I915_READ(reg
);
3367 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3368 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3369 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3370 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3375 /* Switch from Rawclk to PCDclk */
3376 temp
= I915_READ(reg
);
3377 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3382 /* Enable CPU FDI TX PLL, always on for Ironlake */
3383 reg
= FDI_TX_CTL(pipe
);
3384 temp
= I915_READ(reg
);
3385 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3386 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3393 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3395 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3397 int pipe
= intel_crtc
->pipe
;
3400 /* Switch from PCDclk to Rawclk */
3401 reg
= FDI_RX_CTL(pipe
);
3402 temp
= I915_READ(reg
);
3403 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3405 /* Disable CPU FDI TX PLL */
3406 reg
= FDI_TX_CTL(pipe
);
3407 temp
= I915_READ(reg
);
3408 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3413 reg
= FDI_RX_CTL(pipe
);
3414 temp
= I915_READ(reg
);
3415 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3417 /* Wait for the clocks to turn off. */
3422 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3424 struct drm_device
*dev
= crtc
->dev
;
3425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3427 int pipe
= intel_crtc
->pipe
;
3430 /* disable CPU FDI tx and PCH FDI rx */
3431 reg
= FDI_TX_CTL(pipe
);
3432 temp
= I915_READ(reg
);
3433 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3436 reg
= FDI_RX_CTL(pipe
);
3437 temp
= I915_READ(reg
);
3438 temp
&= ~(0x7 << 16);
3439 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3440 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3445 /* Ironlake workaround, disable clock pointer after downing FDI */
3446 if (HAS_PCH_IBX(dev
))
3447 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3449 /* still set train pattern 1 */
3450 reg
= FDI_TX_CTL(pipe
);
3451 temp
= I915_READ(reg
);
3452 temp
&= ~FDI_LINK_TRAIN_NONE
;
3453 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3454 I915_WRITE(reg
, temp
);
3456 reg
= FDI_RX_CTL(pipe
);
3457 temp
= I915_READ(reg
);
3458 if (HAS_PCH_CPT(dev
)) {
3459 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3460 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3462 temp
&= ~FDI_LINK_TRAIN_NONE
;
3463 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3465 /* BPC in FDI rx is consistent with that in PIPECONF */
3466 temp
&= ~(0x07 << 16);
3467 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3468 I915_WRITE(reg
, temp
);
3474 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3476 struct intel_crtc
*crtc
;
3478 /* Note that we don't need to be called with mode_config.lock here
3479 * as our list of CRTC objects is static for the lifetime of the
3480 * device and so cannot disappear as we iterate. Similarly, we can
3481 * happily treat the predicates as racy, atomic checks as userspace
3482 * cannot claim and pin a new fb without at least acquring the
3483 * struct_mutex and so serialising with us.
3485 for_each_intel_crtc(dev
, crtc
) {
3486 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3489 if (crtc
->unpin_work
)
3490 intel_wait_for_vblank(dev
, crtc
->pipe
);
3498 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3500 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3501 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3503 /* ensure that the unpin work is consistent wrt ->pending. */
3505 intel_crtc
->unpin_work
= NULL
;
3508 drm_send_vblank_event(intel_crtc
->base
.dev
,
3512 drm_crtc_vblank_put(&intel_crtc
->base
);
3514 wake_up_all(&dev_priv
->pending_flip_queue
);
3515 queue_work(dev_priv
->wq
, &work
->work
);
3517 trace_i915_flip_complete(intel_crtc
->plane
,
3518 work
->pending_flip_obj
);
3521 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3523 struct drm_device
*dev
= crtc
->dev
;
3524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3526 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3527 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3528 !intel_crtc_has_pending_flip(crtc
),
3530 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3531 unsigned long flags
;
3533 spin_lock_irqsave(&dev
->event_lock
, flags
);
3534 if (intel_crtc
->unpin_work
) {
3535 WARN_ONCE(1, "Removing stuck page flip\n");
3536 page_flip_completed(intel_crtc
);
3538 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
3541 if (crtc
->primary
->fb
) {
3542 mutex_lock(&dev
->struct_mutex
);
3543 intel_finish_fb(crtc
->primary
->fb
);
3544 mutex_unlock(&dev
->struct_mutex
);
3548 /* Program iCLKIP clock to the desired frequency */
3549 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3551 struct drm_device
*dev
= crtc
->dev
;
3552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3553 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3554 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3557 mutex_lock(&dev_priv
->dpio_lock
);
3559 /* It is necessary to ungate the pixclk gate prior to programming
3560 * the divisors, and gate it back when it is done.
3562 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3564 /* Disable SSCCTL */
3565 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3566 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3570 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3571 if (clock
== 20000) {
3576 /* The iCLK virtual clock root frequency is in MHz,
3577 * but the adjusted_mode->crtc_clock in in KHz. To get the
3578 * divisors, it is necessary to divide one by another, so we
3579 * convert the virtual clock precision to KHz here for higher
3582 u32 iclk_virtual_root_freq
= 172800 * 1000;
3583 u32 iclk_pi_range
= 64;
3584 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3586 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3587 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3588 pi_value
= desired_divisor
% iclk_pi_range
;
3591 divsel
= msb_divisor_value
- 2;
3592 phaseinc
= pi_value
;
3595 /* This should not happen with any sane values */
3596 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3597 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3598 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3599 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3601 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3608 /* Program SSCDIVINTPHASE6 */
3609 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3610 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3611 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3612 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3613 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3614 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3615 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3616 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3618 /* Program SSCAUXDIV */
3619 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3620 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3621 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3622 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3624 /* Enable modulator and associated divider */
3625 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3626 temp
&= ~SBI_SSCCTL_DISABLE
;
3627 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3629 /* Wait for initialization time */
3632 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3634 mutex_unlock(&dev_priv
->dpio_lock
);
3637 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3638 enum pipe pch_transcoder
)
3640 struct drm_device
*dev
= crtc
->base
.dev
;
3641 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3642 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3644 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3645 I915_READ(HTOTAL(cpu_transcoder
)));
3646 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3647 I915_READ(HBLANK(cpu_transcoder
)));
3648 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3649 I915_READ(HSYNC(cpu_transcoder
)));
3651 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3652 I915_READ(VTOTAL(cpu_transcoder
)));
3653 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3654 I915_READ(VBLANK(cpu_transcoder
)));
3655 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3656 I915_READ(VSYNC(cpu_transcoder
)));
3657 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3658 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3661 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3663 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3666 temp
= I915_READ(SOUTH_CHICKEN1
);
3667 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3670 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3671 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3673 temp
|= FDI_BC_BIFURCATION_SELECT
;
3674 DRM_DEBUG_KMS("enabling fdi C rx\n");
3675 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3676 POSTING_READ(SOUTH_CHICKEN1
);
3679 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3681 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3684 switch (intel_crtc
->pipe
) {
3688 if (intel_crtc
->config
.fdi_lanes
> 2)
3689 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3691 cpt_enable_fdi_bc_bifurcation(dev
);
3695 cpt_enable_fdi_bc_bifurcation(dev
);
3704 * Enable PCH resources required for PCH ports:
3706 * - FDI training & RX/TX
3707 * - update transcoder timings
3708 * - DP transcoding bits
3711 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3713 struct drm_device
*dev
= crtc
->dev
;
3714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3715 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3716 int pipe
= intel_crtc
->pipe
;
3719 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3721 if (IS_IVYBRIDGE(dev
))
3722 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3724 /* Write the TU size bits before fdi link training, so that error
3725 * detection works. */
3726 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3727 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3729 /* For PCH output, training FDI link */
3730 dev_priv
->display
.fdi_link_train(crtc
);
3732 /* We need to program the right clock selection before writing the pixel
3733 * mutliplier into the DPLL. */
3734 if (HAS_PCH_CPT(dev
)) {
3737 temp
= I915_READ(PCH_DPLL_SEL
);
3738 temp
|= TRANS_DPLL_ENABLE(pipe
);
3739 sel
= TRANS_DPLLB_SEL(pipe
);
3740 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3744 I915_WRITE(PCH_DPLL_SEL
, temp
);
3747 /* XXX: pch pll's can be enabled any time before we enable the PCH
3748 * transcoder, and we actually should do this to not upset any PCH
3749 * transcoder that already use the clock when we share it.
3751 * Note that enable_shared_dpll tries to do the right thing, but
3752 * get_shared_dpll unconditionally resets the pll - we need that to have
3753 * the right LVDS enable sequence. */
3754 intel_enable_shared_dpll(intel_crtc
);
3756 /* set transcoder timing, panel must allow it */
3757 assert_panel_unlocked(dev_priv
, pipe
);
3758 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3760 intel_fdi_normal_train(crtc
);
3762 /* For PCH DP, enable TRANS_DP_CTL */
3763 if (HAS_PCH_CPT(dev
) &&
3764 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3765 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3766 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3767 reg
= TRANS_DP_CTL(pipe
);
3768 temp
= I915_READ(reg
);
3769 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3770 TRANS_DP_SYNC_MASK
|
3772 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3773 TRANS_DP_ENH_FRAMING
);
3774 temp
|= bpc
<< 9; /* same format but at 11:9 */
3776 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3777 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3778 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3779 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3781 switch (intel_trans_dp_port_sel(crtc
)) {
3783 temp
|= TRANS_DP_PORT_SEL_B
;
3786 temp
|= TRANS_DP_PORT_SEL_C
;
3789 temp
|= TRANS_DP_PORT_SEL_D
;
3795 I915_WRITE(reg
, temp
);
3798 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3801 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3803 struct drm_device
*dev
= crtc
->dev
;
3804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3805 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3806 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3808 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3810 lpt_program_iclkip(crtc
);
3812 /* Set transcoder timing. */
3813 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3815 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3818 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3820 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3825 if (pll
->refcount
== 0) {
3826 WARN(1, "bad %s refcount\n", pll
->name
);
3830 if (--pll
->refcount
== 0) {
3832 WARN_ON(pll
->active
);
3835 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3838 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3840 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3841 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3842 enum intel_dpll_id i
;
3845 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3846 crtc
->base
.base
.id
, pll
->name
);
3847 intel_put_shared_dpll(crtc
);
3850 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3851 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3852 i
= (enum intel_dpll_id
) crtc
->pipe
;
3853 pll
= &dev_priv
->shared_dplls
[i
];
3855 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3856 crtc
->base
.base
.id
, pll
->name
);
3858 WARN_ON(pll
->refcount
);
3863 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3864 pll
= &dev_priv
->shared_dplls
[i
];
3866 /* Only want to check enabled timings first */
3867 if (pll
->refcount
== 0)
3870 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3871 sizeof(pll
->hw_state
)) == 0) {
3872 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3874 pll
->name
, pll
->refcount
, pll
->active
);
3880 /* Ok no matching timings, maybe there's a free one? */
3881 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3882 pll
= &dev_priv
->shared_dplls
[i
];
3883 if (pll
->refcount
== 0) {
3884 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3885 crtc
->base
.base
.id
, pll
->name
);
3893 if (pll
->refcount
== 0)
3894 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3896 crtc
->config
.shared_dpll
= i
;
3897 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3898 pipe_name(crtc
->pipe
));
3905 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3908 int dslreg
= PIPEDSL(pipe
);
3911 temp
= I915_READ(dslreg
);
3913 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3914 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3915 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3919 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3921 struct drm_device
*dev
= crtc
->base
.dev
;
3922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3923 int pipe
= crtc
->pipe
;
3925 if (crtc
->config
.pch_pfit
.enabled
) {
3926 /* Force use of hard-coded filter coefficients
3927 * as some pre-programmed values are broken,
3930 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3931 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3932 PF_PIPE_SEL_IVB(pipe
));
3934 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3935 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3936 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3940 static void intel_enable_planes(struct drm_crtc
*crtc
)
3942 struct drm_device
*dev
= crtc
->dev
;
3943 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3944 struct drm_plane
*plane
;
3945 struct intel_plane
*intel_plane
;
3947 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3948 intel_plane
= to_intel_plane(plane
);
3949 if (intel_plane
->pipe
== pipe
)
3950 intel_plane_restore(&intel_plane
->base
);
3954 static void intel_disable_planes(struct drm_crtc
*crtc
)
3956 struct drm_device
*dev
= crtc
->dev
;
3957 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3958 struct drm_plane
*plane
;
3959 struct intel_plane
*intel_plane
;
3961 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3962 intel_plane
= to_intel_plane(plane
);
3963 if (intel_plane
->pipe
== pipe
)
3964 intel_plane_disable(&intel_plane
->base
);
3968 void hsw_enable_ips(struct intel_crtc
*crtc
)
3970 struct drm_device
*dev
= crtc
->base
.dev
;
3971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3973 if (!crtc
->config
.ips_enabled
)
3976 /* We can only enable IPS after we enable a plane and wait for a vblank */
3977 intel_wait_for_vblank(dev
, crtc
->pipe
);
3979 assert_plane_enabled(dev_priv
, crtc
->plane
);
3980 if (IS_BROADWELL(dev
)) {
3981 mutex_lock(&dev_priv
->rps
.hw_lock
);
3982 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3983 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3984 /* Quoting Art Runyan: "its not safe to expect any particular
3985 * value in IPS_CTL bit 31 after enabling IPS through the
3986 * mailbox." Moreover, the mailbox may return a bogus state,
3987 * so we need to just enable it and continue on.
3990 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3991 /* The bit only becomes 1 in the next vblank, so this wait here
3992 * is essentially intel_wait_for_vblank. If we don't have this
3993 * and don't wait for vblanks until the end of crtc_enable, then
3994 * the HW state readout code will complain that the expected
3995 * IPS_CTL value is not the one we read. */
3996 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3997 DRM_ERROR("Timed out waiting for IPS enable\n");
4001 void hsw_disable_ips(struct intel_crtc
*crtc
)
4003 struct drm_device
*dev
= crtc
->base
.dev
;
4004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4006 if (!crtc
->config
.ips_enabled
)
4009 assert_plane_enabled(dev_priv
, crtc
->plane
);
4010 if (IS_BROADWELL(dev
)) {
4011 mutex_lock(&dev_priv
->rps
.hw_lock
);
4012 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4013 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4014 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4015 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4016 DRM_ERROR("Timed out waiting for IPS disable\n");
4018 I915_WRITE(IPS_CTL
, 0);
4019 POSTING_READ(IPS_CTL
);
4022 /* We need to wait for a vblank before we can disable the plane. */
4023 intel_wait_for_vblank(dev
, crtc
->pipe
);
4026 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4027 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4029 struct drm_device
*dev
= crtc
->dev
;
4030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4031 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4032 enum pipe pipe
= intel_crtc
->pipe
;
4033 int palreg
= PALETTE(pipe
);
4035 bool reenable_ips
= false;
4037 /* The clocks have to be on to load the palette. */
4038 if (!crtc
->enabled
|| !intel_crtc
->active
)
4041 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4042 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
4043 assert_dsi_pll_enabled(dev_priv
);
4045 assert_pll_enabled(dev_priv
, pipe
);
4048 /* use legacy palette for Ironlake */
4049 if (!HAS_GMCH_DISPLAY(dev
))
4050 palreg
= LGC_PALETTE(pipe
);
4052 /* Workaround : Do not read or write the pipe palette/gamma data while
4053 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4055 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
4056 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4057 GAMMA_MODE_MODE_SPLIT
)) {
4058 hsw_disable_ips(intel_crtc
);
4059 reenable_ips
= true;
4062 for (i
= 0; i
< 256; i
++) {
4063 I915_WRITE(palreg
+ 4 * i
,
4064 (intel_crtc
->lut_r
[i
] << 16) |
4065 (intel_crtc
->lut_g
[i
] << 8) |
4066 intel_crtc
->lut_b
[i
]);
4070 hsw_enable_ips(intel_crtc
);
4073 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4075 if (!enable
&& intel_crtc
->overlay
) {
4076 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4079 mutex_lock(&dev
->struct_mutex
);
4080 dev_priv
->mm
.interruptible
= false;
4081 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4082 dev_priv
->mm
.interruptible
= true;
4083 mutex_unlock(&dev
->struct_mutex
);
4086 /* Let userspace switch the overlay on again. In most cases userspace
4087 * has to recompute where to put it anyway.
4091 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4093 struct drm_device
*dev
= crtc
->dev
;
4094 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4095 int pipe
= intel_crtc
->pipe
;
4097 assert_vblank_disabled(crtc
);
4099 drm_vblank_on(dev
, pipe
);
4101 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4102 intel_enable_planes(crtc
);
4103 intel_crtc_update_cursor(crtc
, true);
4104 intel_crtc_dpms_overlay(intel_crtc
, true);
4106 hsw_enable_ips(intel_crtc
);
4108 mutex_lock(&dev
->struct_mutex
);
4109 intel_update_fbc(dev
);
4110 mutex_unlock(&dev
->struct_mutex
);
4113 * FIXME: Once we grow proper nuclear flip support out of this we need
4114 * to compute the mask of flip planes precisely. For the time being
4115 * consider this a flip from a NULL plane.
4117 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4120 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4122 struct drm_device
*dev
= crtc
->dev
;
4123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4125 int pipe
= intel_crtc
->pipe
;
4126 int plane
= intel_crtc
->plane
;
4128 intel_crtc_wait_for_pending_flips(crtc
);
4130 if (dev_priv
->fbc
.plane
== plane
)
4131 intel_disable_fbc(dev
);
4133 hsw_disable_ips(intel_crtc
);
4135 intel_crtc_dpms_overlay(intel_crtc
, false);
4136 intel_crtc_update_cursor(crtc
, false);
4137 intel_disable_planes(crtc
);
4138 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4141 * FIXME: Once we grow proper nuclear flip support out of this we need
4142 * to compute the mask of flip planes precisely. For the time being
4143 * consider this a flip to a NULL plane.
4145 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4147 drm_vblank_off(dev
, pipe
);
4149 assert_vblank_disabled(crtc
);
4152 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4154 struct drm_device
*dev
= crtc
->dev
;
4155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4156 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4157 struct intel_encoder
*encoder
;
4158 int pipe
= intel_crtc
->pipe
;
4160 WARN_ON(!crtc
->enabled
);
4162 if (intel_crtc
->active
)
4165 if (intel_crtc
->config
.has_pch_encoder
)
4166 intel_prepare_shared_dpll(intel_crtc
);
4168 if (intel_crtc
->config
.has_dp_encoder
)
4169 intel_dp_set_m_n(intel_crtc
);
4171 intel_set_pipe_timings(intel_crtc
);
4173 if (intel_crtc
->config
.has_pch_encoder
) {
4174 intel_cpu_transcoder_set_m_n(intel_crtc
,
4175 &intel_crtc
->config
.fdi_m_n
, NULL
);
4178 ironlake_set_pipeconf(crtc
);
4180 intel_crtc
->active
= true;
4182 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4183 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4185 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4186 if (encoder
->pre_enable
)
4187 encoder
->pre_enable(encoder
);
4189 if (intel_crtc
->config
.has_pch_encoder
) {
4190 /* Note: FDI PLL enabling _must_ be done before we enable the
4191 * cpu pipes, hence this is separate from all the other fdi/pch
4193 ironlake_fdi_pll_enable(intel_crtc
);
4195 assert_fdi_tx_disabled(dev_priv
, pipe
);
4196 assert_fdi_rx_disabled(dev_priv
, pipe
);
4199 ironlake_pfit_enable(intel_crtc
);
4202 * On ILK+ LUT must be loaded before the pipe is running but with
4205 intel_crtc_load_lut(crtc
);
4207 intel_update_watermarks(crtc
);
4208 intel_enable_pipe(intel_crtc
);
4210 if (intel_crtc
->config
.has_pch_encoder
)
4211 ironlake_pch_enable(crtc
);
4213 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4214 encoder
->enable(encoder
);
4216 if (HAS_PCH_CPT(dev
))
4217 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4219 intel_crtc_enable_planes(crtc
);
4222 /* IPS only exists on ULT machines and is tied to pipe A. */
4223 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4225 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4229 * This implements the workaround described in the "notes" section of the mode
4230 * set sequence documentation. When going from no pipes or single pipe to
4231 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4232 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4234 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4236 struct drm_device
*dev
= crtc
->base
.dev
;
4237 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4239 /* We want to get the other_active_crtc only if there's only 1 other
4241 for_each_intel_crtc(dev
, crtc_it
) {
4242 if (!crtc_it
->active
|| crtc_it
== crtc
)
4245 if (other_active_crtc
)
4248 other_active_crtc
= crtc_it
;
4250 if (!other_active_crtc
)
4253 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4254 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4257 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4259 struct drm_device
*dev
= crtc
->dev
;
4260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4261 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4262 struct intel_encoder
*encoder
;
4263 int pipe
= intel_crtc
->pipe
;
4265 WARN_ON(!crtc
->enabled
);
4267 if (intel_crtc
->active
)
4270 if (intel_crtc_to_shared_dpll(intel_crtc
))
4271 intel_enable_shared_dpll(intel_crtc
);
4273 if (intel_crtc
->config
.has_dp_encoder
)
4274 intel_dp_set_m_n(intel_crtc
);
4276 intel_set_pipe_timings(intel_crtc
);
4278 if (intel_crtc
->config
.has_pch_encoder
) {
4279 intel_cpu_transcoder_set_m_n(intel_crtc
,
4280 &intel_crtc
->config
.fdi_m_n
, NULL
);
4283 haswell_set_pipeconf(crtc
);
4285 intel_set_pipe_csc(crtc
);
4287 intel_crtc
->active
= true;
4289 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4290 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4291 if (encoder
->pre_enable
)
4292 encoder
->pre_enable(encoder
);
4294 if (intel_crtc
->config
.has_pch_encoder
) {
4295 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4296 dev_priv
->display
.fdi_link_train(crtc
);
4299 intel_ddi_enable_pipe_clock(intel_crtc
);
4301 ironlake_pfit_enable(intel_crtc
);
4304 * On ILK+ LUT must be loaded before the pipe is running but with
4307 intel_crtc_load_lut(crtc
);
4309 intel_ddi_set_pipe_settings(crtc
);
4310 intel_ddi_enable_transcoder_func(crtc
);
4312 intel_update_watermarks(crtc
);
4313 intel_enable_pipe(intel_crtc
);
4315 if (intel_crtc
->config
.has_pch_encoder
)
4316 lpt_pch_enable(crtc
);
4318 if (intel_crtc
->config
.dp_encoder_is_mst
)
4319 intel_ddi_set_vc_payload_alloc(crtc
, true);
4321 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4322 encoder
->enable(encoder
);
4323 intel_opregion_notify_encoder(encoder
, true);
4326 /* If we change the relative order between pipe/planes enabling, we need
4327 * to change the workaround. */
4328 haswell_mode_set_planes_workaround(intel_crtc
);
4329 intel_crtc_enable_planes(crtc
);
4332 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4334 struct drm_device
*dev
= crtc
->base
.dev
;
4335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4336 int pipe
= crtc
->pipe
;
4338 /* To avoid upsetting the power well on haswell only disable the pfit if
4339 * it's in use. The hw state code will make sure we get this right. */
4340 if (crtc
->config
.pch_pfit
.enabled
) {
4341 I915_WRITE(PF_CTL(pipe
), 0);
4342 I915_WRITE(PF_WIN_POS(pipe
), 0);
4343 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4347 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4349 struct drm_device
*dev
= crtc
->dev
;
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4352 struct intel_encoder
*encoder
;
4353 int pipe
= intel_crtc
->pipe
;
4356 if (!intel_crtc
->active
)
4359 intel_crtc_disable_planes(crtc
);
4361 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4362 encoder
->disable(encoder
);
4364 if (intel_crtc
->config
.has_pch_encoder
)
4365 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4367 intel_disable_pipe(intel_crtc
);
4369 ironlake_pfit_disable(intel_crtc
);
4371 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4372 if (encoder
->post_disable
)
4373 encoder
->post_disable(encoder
);
4375 if (intel_crtc
->config
.has_pch_encoder
) {
4376 ironlake_fdi_disable(crtc
);
4378 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4379 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4381 if (HAS_PCH_CPT(dev
)) {
4382 /* disable TRANS_DP_CTL */
4383 reg
= TRANS_DP_CTL(pipe
);
4384 temp
= I915_READ(reg
);
4385 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4386 TRANS_DP_PORT_SEL_MASK
);
4387 temp
|= TRANS_DP_PORT_SEL_NONE
;
4388 I915_WRITE(reg
, temp
);
4390 /* disable DPLL_SEL */
4391 temp
= I915_READ(PCH_DPLL_SEL
);
4392 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4393 I915_WRITE(PCH_DPLL_SEL
, temp
);
4396 /* disable PCH DPLL */
4397 intel_disable_shared_dpll(intel_crtc
);
4399 ironlake_fdi_pll_disable(intel_crtc
);
4402 intel_crtc
->active
= false;
4403 intel_update_watermarks(crtc
);
4405 mutex_lock(&dev
->struct_mutex
);
4406 intel_update_fbc(dev
);
4407 mutex_unlock(&dev
->struct_mutex
);
4410 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4412 struct drm_device
*dev
= crtc
->dev
;
4413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4415 struct intel_encoder
*encoder
;
4416 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4418 if (!intel_crtc
->active
)
4421 intel_crtc_disable_planes(crtc
);
4423 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4424 intel_opregion_notify_encoder(encoder
, false);
4425 encoder
->disable(encoder
);
4428 if (intel_crtc
->config
.has_pch_encoder
)
4429 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4430 intel_disable_pipe(intel_crtc
);
4432 if (intel_crtc
->config
.dp_encoder_is_mst
)
4433 intel_ddi_set_vc_payload_alloc(crtc
, false);
4435 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4437 ironlake_pfit_disable(intel_crtc
);
4439 intel_ddi_disable_pipe_clock(intel_crtc
);
4441 if (intel_crtc
->config
.has_pch_encoder
) {
4442 lpt_disable_pch_transcoder(dev_priv
);
4443 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4444 intel_ddi_fdi_disable(crtc
);
4447 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4448 if (encoder
->post_disable
)
4449 encoder
->post_disable(encoder
);
4451 intel_crtc
->active
= false;
4452 intel_update_watermarks(crtc
);
4454 mutex_lock(&dev
->struct_mutex
);
4455 intel_update_fbc(dev
);
4456 mutex_unlock(&dev
->struct_mutex
);
4458 if (intel_crtc_to_shared_dpll(intel_crtc
))
4459 intel_disable_shared_dpll(intel_crtc
);
4462 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4465 intel_put_shared_dpll(intel_crtc
);
4469 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4471 struct drm_device
*dev
= crtc
->base
.dev
;
4472 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4473 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4475 if (!crtc
->config
.gmch_pfit
.control
)
4479 * The panel fitter should only be adjusted whilst the pipe is disabled,
4480 * according to register description and PRM.
4482 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4483 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4485 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4486 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4488 /* Border color in case we don't scale up to the full screen. Black by
4489 * default, change to something else for debugging. */
4490 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4493 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4497 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4499 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4501 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4503 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4506 return POWER_DOMAIN_PORT_OTHER
;
4510 #define for_each_power_domain(domain, mask) \
4511 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4512 if ((1 << (domain)) & (mask))
4514 enum intel_display_power_domain
4515 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4517 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4518 struct intel_digital_port
*intel_dig_port
;
4520 switch (intel_encoder
->type
) {
4521 case INTEL_OUTPUT_UNKNOWN
:
4522 /* Only DDI platforms should ever use this output type */
4523 WARN_ON_ONCE(!HAS_DDI(dev
));
4524 case INTEL_OUTPUT_DISPLAYPORT
:
4525 case INTEL_OUTPUT_HDMI
:
4526 case INTEL_OUTPUT_EDP
:
4527 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4528 return port_to_power_domain(intel_dig_port
->port
);
4529 case INTEL_OUTPUT_DP_MST
:
4530 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4531 return port_to_power_domain(intel_dig_port
->port
);
4532 case INTEL_OUTPUT_ANALOG
:
4533 return POWER_DOMAIN_PORT_CRT
;
4534 case INTEL_OUTPUT_DSI
:
4535 return POWER_DOMAIN_PORT_DSI
;
4537 return POWER_DOMAIN_PORT_OTHER
;
4541 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4543 struct drm_device
*dev
= crtc
->dev
;
4544 struct intel_encoder
*intel_encoder
;
4545 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4546 enum pipe pipe
= intel_crtc
->pipe
;
4548 enum transcoder transcoder
;
4550 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4552 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4553 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4554 if (intel_crtc
->config
.pch_pfit
.enabled
||
4555 intel_crtc
->config
.pch_pfit
.force_thru
)
4556 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4558 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4559 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4564 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4567 if (dev_priv
->power_domains
.init_power_on
== enable
)
4571 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4573 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4575 dev_priv
->power_domains
.init_power_on
= enable
;
4578 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4581 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4582 struct intel_crtc
*crtc
;
4585 * First get all needed power domains, then put all unneeded, to avoid
4586 * any unnecessary toggling of the power wells.
4588 for_each_intel_crtc(dev
, crtc
) {
4589 enum intel_display_power_domain domain
;
4591 if (!crtc
->base
.enabled
)
4594 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4596 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4597 intel_display_power_get(dev_priv
, domain
);
4600 for_each_intel_crtc(dev
, crtc
) {
4601 enum intel_display_power_domain domain
;
4603 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4604 intel_display_power_put(dev_priv
, domain
);
4606 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4609 intel_display_set_init_power(dev_priv
, false);
4612 /* returns HPLL frequency in kHz */
4613 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4615 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4617 /* Obtain SKU information */
4618 mutex_lock(&dev_priv
->dpio_lock
);
4619 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4620 CCK_FUSE_HPLL_FREQ_MASK
;
4621 mutex_unlock(&dev_priv
->dpio_lock
);
4623 return vco_freq
[hpll_freq
] * 1000;
4626 static void vlv_update_cdclk(struct drm_device
*dev
)
4628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4630 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4631 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4632 dev_priv
->vlv_cdclk_freq
);
4635 * Program the gmbus_freq based on the cdclk frequency.
4636 * BSpec erroneously claims we should aim for 4MHz, but
4637 * in fact 1MHz is the correct frequency.
4639 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4642 /* Adjust CDclk dividers to allow high res or save power if possible */
4643 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4648 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4650 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4652 else if (cdclk
== 266667)
4657 mutex_lock(&dev_priv
->rps
.hw_lock
);
4658 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4659 val
&= ~DSPFREQGUAR_MASK
;
4660 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4661 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4662 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4663 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4665 DRM_ERROR("timed out waiting for CDclk change\n");
4667 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4669 if (cdclk
== 400000) {
4672 vco
= valleyview_get_vco(dev_priv
);
4673 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4675 mutex_lock(&dev_priv
->dpio_lock
);
4676 /* adjust cdclk divider */
4677 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4678 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4680 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4682 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4683 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4685 DRM_ERROR("timed out waiting for CDclk change\n");
4686 mutex_unlock(&dev_priv
->dpio_lock
);
4689 mutex_lock(&dev_priv
->dpio_lock
);
4690 /* adjust self-refresh exit latency value */
4691 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4695 * For high bandwidth configs, we set a higher latency in the bunit
4696 * so that the core display fetch happens in time to avoid underruns.
4698 if (cdclk
== 400000)
4699 val
|= 4500 / 250; /* 4.5 usec */
4701 val
|= 3000 / 250; /* 3.0 usec */
4702 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4703 mutex_unlock(&dev_priv
->dpio_lock
);
4705 vlv_update_cdclk(dev
);
4708 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4713 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4734 mutex_lock(&dev_priv
->rps
.hw_lock
);
4735 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4736 val
&= ~DSPFREQGUAR_MASK_CHV
;
4737 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4738 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4739 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4740 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4742 DRM_ERROR("timed out waiting for CDclk change\n");
4744 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4746 vlv_update_cdclk(dev
);
4749 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4752 int vco
= valleyview_get_vco(dev_priv
);
4753 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4755 /* FIXME: Punit isn't quite ready yet */
4756 if (IS_CHERRYVIEW(dev_priv
->dev
))
4760 * Really only a few cases to deal with, as only 4 CDclks are supported:
4763 * 320/333MHz (depends on HPLL freq)
4765 * So we check to see whether we're above 90% of the lower bin and
4768 * We seem to get an unstable or solid color picture at 200MHz.
4769 * Not sure what's wrong. For now use 200MHz only when all pipes
4772 if (max_pixclk
> freq_320
*9/10)
4774 else if (max_pixclk
> 266667*9/10)
4776 else if (max_pixclk
> 0)
4782 /* compute the max pixel clock for new configuration */
4783 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4785 struct drm_device
*dev
= dev_priv
->dev
;
4786 struct intel_crtc
*intel_crtc
;
4789 for_each_intel_crtc(dev
, intel_crtc
) {
4790 if (intel_crtc
->new_enabled
)
4791 max_pixclk
= max(max_pixclk
,
4792 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4798 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4799 unsigned *prepare_pipes
)
4801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4802 struct intel_crtc
*intel_crtc
;
4803 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4805 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4806 dev_priv
->vlv_cdclk_freq
)
4809 /* disable/enable all currently active pipes while we change cdclk */
4810 for_each_intel_crtc(dev
, intel_crtc
)
4811 if (intel_crtc
->base
.enabled
)
4812 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4815 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4818 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4819 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4821 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4822 if (IS_CHERRYVIEW(dev
))
4823 cherryview_set_cdclk(dev
, req_cdclk
);
4825 valleyview_set_cdclk(dev
, req_cdclk
);
4828 modeset_update_crtc_power_domains(dev
);
4831 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4833 struct drm_device
*dev
= crtc
->dev
;
4834 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4835 struct intel_encoder
*encoder
;
4836 int pipe
= intel_crtc
->pipe
;
4839 WARN_ON(!crtc
->enabled
);
4841 if (intel_crtc
->active
)
4844 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4847 if (IS_CHERRYVIEW(dev
))
4848 chv_prepare_pll(intel_crtc
);
4850 vlv_prepare_pll(intel_crtc
);
4853 if (intel_crtc
->config
.has_dp_encoder
)
4854 intel_dp_set_m_n(intel_crtc
);
4856 intel_set_pipe_timings(intel_crtc
);
4858 i9xx_set_pipeconf(intel_crtc
);
4860 intel_crtc
->active
= true;
4862 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4864 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4865 if (encoder
->pre_pll_enable
)
4866 encoder
->pre_pll_enable(encoder
);
4869 if (IS_CHERRYVIEW(dev
))
4870 chv_enable_pll(intel_crtc
);
4872 vlv_enable_pll(intel_crtc
);
4875 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4876 if (encoder
->pre_enable
)
4877 encoder
->pre_enable(encoder
);
4879 i9xx_pfit_enable(intel_crtc
);
4881 intel_crtc_load_lut(crtc
);
4883 intel_update_watermarks(crtc
);
4884 intel_enable_pipe(intel_crtc
);
4886 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4887 encoder
->enable(encoder
);
4889 intel_crtc_enable_planes(crtc
);
4891 /* Underruns don't raise interrupts, so check manually. */
4892 i9xx_check_fifo_underruns(dev
);
4895 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4897 struct drm_device
*dev
= crtc
->base
.dev
;
4898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4900 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4901 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4904 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4906 struct drm_device
*dev
= crtc
->dev
;
4907 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4908 struct intel_encoder
*encoder
;
4909 int pipe
= intel_crtc
->pipe
;
4911 WARN_ON(!crtc
->enabled
);
4913 if (intel_crtc
->active
)
4916 i9xx_set_pll_dividers(intel_crtc
);
4918 if (intel_crtc
->config
.has_dp_encoder
)
4919 intel_dp_set_m_n(intel_crtc
);
4921 intel_set_pipe_timings(intel_crtc
);
4923 i9xx_set_pipeconf(intel_crtc
);
4925 intel_crtc
->active
= true;
4928 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4930 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4931 if (encoder
->pre_enable
)
4932 encoder
->pre_enable(encoder
);
4934 i9xx_enable_pll(intel_crtc
);
4936 i9xx_pfit_enable(intel_crtc
);
4938 intel_crtc_load_lut(crtc
);
4940 intel_update_watermarks(crtc
);
4941 intel_enable_pipe(intel_crtc
);
4943 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4944 encoder
->enable(encoder
);
4946 intel_crtc_enable_planes(crtc
);
4949 * Gen2 reports pipe underruns whenever all planes are disabled.
4950 * So don't enable underrun reporting before at least some planes
4952 * FIXME: Need to fix the logic to work when we turn off all planes
4953 * but leave the pipe running.
4956 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4958 /* Underruns don't raise interrupts, so check manually. */
4959 i9xx_check_fifo_underruns(dev
);
4962 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4964 struct drm_device
*dev
= crtc
->base
.dev
;
4965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4967 if (!crtc
->config
.gmch_pfit
.control
)
4970 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4972 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4973 I915_READ(PFIT_CONTROL
));
4974 I915_WRITE(PFIT_CONTROL
, 0);
4977 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4979 struct drm_device
*dev
= crtc
->dev
;
4980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4982 struct intel_encoder
*encoder
;
4983 int pipe
= intel_crtc
->pipe
;
4985 if (!intel_crtc
->active
)
4989 * Gen2 reports pipe underruns whenever all planes are disabled.
4990 * So diasble underrun reporting before all the planes get disabled.
4991 * FIXME: Need to fix the logic to work when we turn off all planes
4992 * but leave the pipe running.
4995 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4998 * Vblank time updates from the shadow to live plane control register
4999 * are blocked if the memory self-refresh mode is active at that
5000 * moment. So to make sure the plane gets truly disabled, disable
5001 * first the self-refresh mode. The self-refresh enable bit in turn
5002 * will be checked/applied by the HW only at the next frame start
5003 * event which is after the vblank start event, so we need to have a
5004 * wait-for-vblank between disabling the plane and the pipe.
5006 intel_set_memory_cxsr(dev_priv
, false);
5007 intel_crtc_disable_planes(crtc
);
5009 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5010 encoder
->disable(encoder
);
5013 * On gen2 planes are double buffered but the pipe isn't, so we must
5014 * wait for planes to fully turn off before disabling the pipe.
5015 * We also need to wait on all gmch platforms because of the
5016 * self-refresh mode constraint explained above.
5018 intel_wait_for_vblank(dev
, pipe
);
5020 intel_disable_pipe(intel_crtc
);
5022 i9xx_pfit_disable(intel_crtc
);
5024 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5025 if (encoder
->post_disable
)
5026 encoder
->post_disable(encoder
);
5028 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
5029 if (IS_CHERRYVIEW(dev
))
5030 chv_disable_pll(dev_priv
, pipe
);
5031 else if (IS_VALLEYVIEW(dev
))
5032 vlv_disable_pll(dev_priv
, pipe
);
5034 i9xx_disable_pll(dev_priv
, pipe
);
5038 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
5040 intel_crtc
->active
= false;
5041 intel_update_watermarks(crtc
);
5043 mutex_lock(&dev
->struct_mutex
);
5044 intel_update_fbc(dev
);
5045 mutex_unlock(&dev
->struct_mutex
);
5048 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5052 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
5055 struct drm_device
*dev
= crtc
->dev
;
5056 struct drm_i915_master_private
*master_priv
;
5057 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5058 int pipe
= intel_crtc
->pipe
;
5060 if (!dev
->primary
->master
)
5063 master_priv
= dev
->primary
->master
->driver_priv
;
5064 if (!master_priv
->sarea_priv
)
5069 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5070 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5073 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5074 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5077 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
5082 /* Master function to enable/disable CRTC and corresponding power wells */
5083 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5085 struct drm_device
*dev
= crtc
->dev
;
5086 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5087 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5088 enum intel_display_power_domain domain
;
5089 unsigned long domains
;
5092 if (!intel_crtc
->active
) {
5093 domains
= get_crtc_power_domains(crtc
);
5094 for_each_power_domain(domain
, domains
)
5095 intel_display_power_get(dev_priv
, domain
);
5096 intel_crtc
->enabled_power_domains
= domains
;
5098 dev_priv
->display
.crtc_enable(crtc
);
5101 if (intel_crtc
->active
) {
5102 dev_priv
->display
.crtc_disable(crtc
);
5104 domains
= intel_crtc
->enabled_power_domains
;
5105 for_each_power_domain(domain
, domains
)
5106 intel_display_power_put(dev_priv
, domain
);
5107 intel_crtc
->enabled_power_domains
= 0;
5113 * Sets the power management mode of the pipe and plane.
5115 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5117 struct drm_device
*dev
= crtc
->dev
;
5118 struct intel_encoder
*intel_encoder
;
5119 bool enable
= false;
5121 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5122 enable
|= intel_encoder
->connectors_active
;
5124 intel_crtc_control(crtc
, enable
);
5126 intel_crtc_update_sarea(crtc
, enable
);
5129 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5131 struct drm_device
*dev
= crtc
->dev
;
5132 struct drm_connector
*connector
;
5133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5134 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5135 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5137 /* crtc should still be enabled when we disable it. */
5138 WARN_ON(!crtc
->enabled
);
5140 dev_priv
->display
.crtc_disable(crtc
);
5141 intel_crtc_update_sarea(crtc
, false);
5142 dev_priv
->display
.off(crtc
);
5144 if (crtc
->primary
->fb
) {
5145 mutex_lock(&dev
->struct_mutex
);
5146 intel_unpin_fb_obj(old_obj
);
5147 i915_gem_track_fb(old_obj
, NULL
,
5148 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5149 mutex_unlock(&dev
->struct_mutex
);
5150 crtc
->primary
->fb
= NULL
;
5153 /* Update computed state. */
5154 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5155 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5158 if (connector
->encoder
->crtc
!= crtc
)
5161 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5162 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5166 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5168 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5170 drm_encoder_cleanup(encoder
);
5171 kfree(intel_encoder
);
5174 /* Simple dpms helper for encoders with just one connector, no cloning and only
5175 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5176 * state of the entire output pipe. */
5177 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5179 if (mode
== DRM_MODE_DPMS_ON
) {
5180 encoder
->connectors_active
= true;
5182 intel_crtc_update_dpms(encoder
->base
.crtc
);
5184 encoder
->connectors_active
= false;
5186 intel_crtc_update_dpms(encoder
->base
.crtc
);
5190 /* Cross check the actual hw state with our own modeset state tracking (and it's
5191 * internal consistency). */
5192 static void intel_connector_check_state(struct intel_connector
*connector
)
5194 if (connector
->get_hw_state(connector
)) {
5195 struct intel_encoder
*encoder
= connector
->encoder
;
5196 struct drm_crtc
*crtc
;
5197 bool encoder_enabled
;
5200 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5201 connector
->base
.base
.id
,
5202 connector
->base
.name
);
5204 /* there is no real hw state for MST connectors */
5205 if (connector
->mst_port
)
5208 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5209 "wrong connector dpms state\n");
5210 WARN(connector
->base
.encoder
!= &encoder
->base
,
5211 "active connector not linked to encoder\n");
5214 WARN(!encoder
->connectors_active
,
5215 "encoder->connectors_active not set\n");
5217 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5218 WARN(!encoder_enabled
, "encoder not enabled\n");
5219 if (WARN_ON(!encoder
->base
.crtc
))
5222 crtc
= encoder
->base
.crtc
;
5224 WARN(!crtc
->enabled
, "crtc not enabled\n");
5225 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5226 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5227 "encoder active on the wrong pipe\n");
5232 /* Even simpler default implementation, if there's really no special case to
5234 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5236 /* All the simple cases only support two dpms states. */
5237 if (mode
!= DRM_MODE_DPMS_ON
)
5238 mode
= DRM_MODE_DPMS_OFF
;
5240 if (mode
== connector
->dpms
)
5243 connector
->dpms
= mode
;
5245 /* Only need to change hw state when actually enabled */
5246 if (connector
->encoder
)
5247 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5249 intel_modeset_check_state(connector
->dev
);
5252 /* Simple connector->get_hw_state implementation for encoders that support only
5253 * one connector and no cloning and hence the encoder state determines the state
5254 * of the connector. */
5255 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5258 struct intel_encoder
*encoder
= connector
->encoder
;
5260 return encoder
->get_hw_state(encoder
, &pipe
);
5263 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5264 struct intel_crtc_config
*pipe_config
)
5266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5267 struct intel_crtc
*pipe_B_crtc
=
5268 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5270 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5271 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5272 if (pipe_config
->fdi_lanes
> 4) {
5273 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5274 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5278 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5279 if (pipe_config
->fdi_lanes
> 2) {
5280 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5281 pipe_config
->fdi_lanes
);
5288 if (INTEL_INFO(dev
)->num_pipes
== 2)
5291 /* Ivybridge 3 pipe is really complicated */
5296 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5297 pipe_config
->fdi_lanes
> 2) {
5298 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5299 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5304 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5305 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5306 if (pipe_config
->fdi_lanes
> 2) {
5307 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5308 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5312 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5322 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5323 struct intel_crtc_config
*pipe_config
)
5325 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5326 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5327 int lane
, link_bw
, fdi_dotclock
;
5328 bool setup_ok
, needs_recompute
= false;
5331 /* FDI is a binary signal running at ~2.7GHz, encoding
5332 * each output octet as 10 bits. The actual frequency
5333 * is stored as a divider into a 100MHz clock, and the
5334 * mode pixel clock is stored in units of 1KHz.
5335 * Hence the bw of each lane in terms of the mode signal
5338 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5340 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5342 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5343 pipe_config
->pipe_bpp
);
5345 pipe_config
->fdi_lanes
= lane
;
5347 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5348 link_bw
, &pipe_config
->fdi_m_n
);
5350 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5351 intel_crtc
->pipe
, pipe_config
);
5352 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5353 pipe_config
->pipe_bpp
-= 2*3;
5354 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5355 pipe_config
->pipe_bpp
);
5356 needs_recompute
= true;
5357 pipe_config
->bw_constrained
= true;
5362 if (needs_recompute
)
5365 return setup_ok
? 0 : -EINVAL
;
5368 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5369 struct intel_crtc_config
*pipe_config
)
5371 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5372 hsw_crtc_supports_ips(crtc
) &&
5373 pipe_config
->pipe_bpp
<= 24;
5376 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5377 struct intel_crtc_config
*pipe_config
)
5379 struct drm_device
*dev
= crtc
->base
.dev
;
5380 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5382 /* FIXME should check pixel clock limits on all platforms */
5383 if (INTEL_INFO(dev
)->gen
< 4) {
5384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5386 dev_priv
->display
.get_display_clock_speed(dev
);
5389 * Enable pixel doubling when the dot clock
5390 * is > 90% of the (display) core speed.
5392 * GDG double wide on either pipe,
5393 * otherwise pipe A only.
5395 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5396 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5398 pipe_config
->double_wide
= true;
5401 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5406 * Pipe horizontal size must be even in:
5408 * - LVDS dual channel mode
5409 * - Double wide pipe
5411 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5412 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5413 pipe_config
->pipe_src_w
&= ~1;
5415 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5416 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5418 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5419 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5422 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5423 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5424 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5425 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5427 pipe_config
->pipe_bpp
= 8*3;
5431 hsw_compute_ips_config(crtc
, pipe_config
);
5434 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5435 * old clock survives for now.
5437 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5438 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5440 if (pipe_config
->has_pch_encoder
)
5441 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5446 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5449 int vco
= valleyview_get_vco(dev_priv
);
5453 /* FIXME: Punit isn't quite ready yet */
5454 if (IS_CHERRYVIEW(dev
))
5457 mutex_lock(&dev_priv
->dpio_lock
);
5458 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5459 mutex_unlock(&dev_priv
->dpio_lock
);
5461 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5463 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5464 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5465 "cdclk change in progress\n");
5467 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5470 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5475 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5480 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5485 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5489 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5491 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5492 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5494 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5496 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5498 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5501 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5502 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5504 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5509 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5513 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5515 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5518 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5519 case GC_DISPLAY_CLOCK_333_MHZ
:
5522 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5528 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5533 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5536 /* Assume that the hardware is in the high speed state. This
5537 * should be the default.
5539 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5540 case GC_CLOCK_133_200
:
5541 case GC_CLOCK_100_200
:
5543 case GC_CLOCK_166_250
:
5545 case GC_CLOCK_100_133
:
5549 /* Shouldn't happen */
5553 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5559 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5561 while (*num
> DATA_LINK_M_N_MASK
||
5562 *den
> DATA_LINK_M_N_MASK
) {
5568 static void compute_m_n(unsigned int m
, unsigned int n
,
5569 uint32_t *ret_m
, uint32_t *ret_n
)
5571 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5572 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5573 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5577 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5578 int pixel_clock
, int link_clock
,
5579 struct intel_link_m_n
*m_n
)
5583 compute_m_n(bits_per_pixel
* pixel_clock
,
5584 link_clock
* nlanes
* 8,
5585 &m_n
->gmch_m
, &m_n
->gmch_n
);
5587 compute_m_n(pixel_clock
, link_clock
,
5588 &m_n
->link_m
, &m_n
->link_n
);
5591 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5593 if (i915
.panel_use_ssc
>= 0)
5594 return i915
.panel_use_ssc
!= 0;
5595 return dev_priv
->vbt
.lvds_use_ssc
5596 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5599 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5601 struct drm_device
*dev
= crtc
->dev
;
5602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5605 if (IS_VALLEYVIEW(dev
)) {
5607 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5608 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5609 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5610 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5611 } else if (!IS_GEN2(dev
)) {
5620 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5622 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5625 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5627 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5630 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5631 intel_clock_t
*reduced_clock
)
5633 struct drm_device
*dev
= crtc
->base
.dev
;
5636 if (IS_PINEVIEW(dev
)) {
5637 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5639 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5641 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5643 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5646 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5648 crtc
->lowfreq_avail
= false;
5649 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5650 reduced_clock
&& i915
.powersave
) {
5651 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5652 crtc
->lowfreq_avail
= true;
5654 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5658 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5664 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5665 * and set it to a reasonable value instead.
5667 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5668 reg_val
&= 0xffffff00;
5669 reg_val
|= 0x00000030;
5670 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5672 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5673 reg_val
&= 0x8cffffff;
5674 reg_val
= 0x8c000000;
5675 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5677 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5678 reg_val
&= 0xffffff00;
5679 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5681 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5682 reg_val
&= 0x00ffffff;
5683 reg_val
|= 0xb0000000;
5684 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5687 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5688 struct intel_link_m_n
*m_n
)
5690 struct drm_device
*dev
= crtc
->base
.dev
;
5691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5692 int pipe
= crtc
->pipe
;
5694 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5695 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5696 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5697 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5700 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5701 struct intel_link_m_n
*m_n
,
5702 struct intel_link_m_n
*m2_n2
)
5704 struct drm_device
*dev
= crtc
->base
.dev
;
5705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5706 int pipe
= crtc
->pipe
;
5707 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5709 if (INTEL_INFO(dev
)->gen
>= 5) {
5710 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5711 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5712 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5713 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5714 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5715 * for gen < 8) and if DRRS is supported (to make sure the
5716 * registers are not unnecessarily accessed).
5718 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5719 crtc
->config
.has_drrs
) {
5720 I915_WRITE(PIPE_DATA_M2(transcoder
),
5721 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5722 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5723 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5724 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5727 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5728 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5729 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5730 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5734 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5736 if (crtc
->config
.has_pch_encoder
)
5737 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5739 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5740 &crtc
->config
.dp_m2_n2
);
5743 static void vlv_update_pll(struct intel_crtc
*crtc
)
5748 * Enable DPIO clock input. We should never disable the reference
5749 * clock for pipe B, since VGA hotplug / manual detection depends
5752 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5753 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5754 /* We should never disable this, set it here for state tracking */
5755 if (crtc
->pipe
== PIPE_B
)
5756 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5757 dpll
|= DPLL_VCO_ENABLE
;
5758 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5760 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5761 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5762 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5765 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5767 struct drm_device
*dev
= crtc
->base
.dev
;
5768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5769 int pipe
= crtc
->pipe
;
5771 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5772 u32 coreclk
, reg_val
;
5774 mutex_lock(&dev_priv
->dpio_lock
);
5776 bestn
= crtc
->config
.dpll
.n
;
5777 bestm1
= crtc
->config
.dpll
.m1
;
5778 bestm2
= crtc
->config
.dpll
.m2
;
5779 bestp1
= crtc
->config
.dpll
.p1
;
5780 bestp2
= crtc
->config
.dpll
.p2
;
5782 /* See eDP HDMI DPIO driver vbios notes doc */
5784 /* PLL B needs special handling */
5786 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5788 /* Set up Tx target for periodic Rcomp update */
5789 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5791 /* Disable target IRef on PLL */
5792 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5793 reg_val
&= 0x00ffffff;
5794 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5796 /* Disable fast lock */
5797 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5799 /* Set idtafcrecal before PLL is enabled */
5800 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5801 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5802 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5803 mdiv
|= (1 << DPIO_K_SHIFT
);
5806 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5807 * but we don't support that).
5808 * Note: don't use the DAC post divider as it seems unstable.
5810 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5811 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5813 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5814 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5816 /* Set HBR and RBR LPF coefficients */
5817 if (crtc
->config
.port_clock
== 162000 ||
5818 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5819 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5820 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5823 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5826 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5827 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5828 /* Use SSC source */
5830 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5833 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5835 } else { /* HDMI or VGA */
5836 /* Use bend source */
5838 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5841 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5845 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5846 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5847 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5848 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5849 coreclk
|= 0x01000000;
5850 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5852 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5853 mutex_unlock(&dev_priv
->dpio_lock
);
5856 static void chv_update_pll(struct intel_crtc
*crtc
)
5858 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5859 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5861 if (crtc
->pipe
!= PIPE_A
)
5862 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5864 crtc
->config
.dpll_hw_state
.dpll_md
=
5865 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5868 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5870 struct drm_device
*dev
= crtc
->base
.dev
;
5871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5872 int pipe
= crtc
->pipe
;
5873 int dpll_reg
= DPLL(crtc
->pipe
);
5874 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5875 u32 loopfilter
, intcoeff
;
5876 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5879 bestn
= crtc
->config
.dpll
.n
;
5880 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5881 bestm1
= crtc
->config
.dpll
.m1
;
5882 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5883 bestp1
= crtc
->config
.dpll
.p1
;
5884 bestp2
= crtc
->config
.dpll
.p2
;
5887 * Enable Refclk and SSC
5889 I915_WRITE(dpll_reg
,
5890 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5892 mutex_lock(&dev_priv
->dpio_lock
);
5894 /* p1 and p2 divider */
5895 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5896 5 << DPIO_CHV_S1_DIV_SHIFT
|
5897 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5898 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5899 1 << DPIO_CHV_K_DIV_SHIFT
);
5901 /* Feedback post-divider - m2 */
5902 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5904 /* Feedback refclk divider - n and m1 */
5905 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5906 DPIO_CHV_M1_DIV_BY_2
|
5907 1 << DPIO_CHV_N_DIV_SHIFT
);
5909 /* M2 fraction division */
5910 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5912 /* M2 fraction division enable */
5913 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5914 DPIO_CHV_FRAC_DIV_EN
|
5915 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5918 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5919 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5920 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5921 if (refclk
== 100000)
5923 else if (refclk
== 38400)
5927 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5928 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5931 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5932 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5935 mutex_unlock(&dev_priv
->dpio_lock
);
5938 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5939 intel_clock_t
*reduced_clock
,
5942 struct drm_device
*dev
= crtc
->base
.dev
;
5943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5946 struct dpll
*clock
= &crtc
->config
.dpll
;
5948 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5950 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5951 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5953 dpll
= DPLL_VGA_MODE_DIS
;
5955 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5956 dpll
|= DPLLB_MODE_LVDS
;
5958 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5960 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5961 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5962 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5966 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5968 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5969 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5971 /* compute bitmask from p1 value */
5972 if (IS_PINEVIEW(dev
))
5973 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5975 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5976 if (IS_G4X(dev
) && reduced_clock
)
5977 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5979 switch (clock
->p2
) {
5981 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5984 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5987 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5990 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5993 if (INTEL_INFO(dev
)->gen
>= 4)
5994 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5996 if (crtc
->config
.sdvo_tv_clock
)
5997 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5998 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5999 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6000 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6002 dpll
|= PLL_REF_INPUT_DREFCLK
;
6004 dpll
|= DPLL_VCO_ENABLE
;
6005 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6007 if (INTEL_INFO(dev
)->gen
>= 4) {
6008 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
6009 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6010 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
6014 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6015 intel_clock_t
*reduced_clock
,
6018 struct drm_device
*dev
= crtc
->base
.dev
;
6019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6021 struct dpll
*clock
= &crtc
->config
.dpll
;
6023 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6025 dpll
= DPLL_VGA_MODE_DIS
;
6027 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
6028 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6031 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6033 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6035 dpll
|= PLL_P2_DIVIDE_BY_4
;
6038 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
6039 dpll
|= DPLL_DVO_2X_MODE
;
6041 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
6042 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6043 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6045 dpll
|= PLL_REF_INPUT_DREFCLK
;
6047 dpll
|= DPLL_VCO_ENABLE
;
6048 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6051 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6053 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6055 enum pipe pipe
= intel_crtc
->pipe
;
6056 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6057 struct drm_display_mode
*adjusted_mode
=
6058 &intel_crtc
->config
.adjusted_mode
;
6059 uint32_t crtc_vtotal
, crtc_vblank_end
;
6062 /* We need to be careful not to changed the adjusted mode, for otherwise
6063 * the hw state checker will get angry at the mismatch. */
6064 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6065 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6067 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6068 /* the chip adds 2 halflines automatically */
6070 crtc_vblank_end
-= 1;
6072 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6073 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6075 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6076 adjusted_mode
->crtc_htotal
/ 2;
6078 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6081 if (INTEL_INFO(dev
)->gen
> 3)
6082 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6084 I915_WRITE(HTOTAL(cpu_transcoder
),
6085 (adjusted_mode
->crtc_hdisplay
- 1) |
6086 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6087 I915_WRITE(HBLANK(cpu_transcoder
),
6088 (adjusted_mode
->crtc_hblank_start
- 1) |
6089 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6090 I915_WRITE(HSYNC(cpu_transcoder
),
6091 (adjusted_mode
->crtc_hsync_start
- 1) |
6092 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6094 I915_WRITE(VTOTAL(cpu_transcoder
),
6095 (adjusted_mode
->crtc_vdisplay
- 1) |
6096 ((crtc_vtotal
- 1) << 16));
6097 I915_WRITE(VBLANK(cpu_transcoder
),
6098 (adjusted_mode
->crtc_vblank_start
- 1) |
6099 ((crtc_vblank_end
- 1) << 16));
6100 I915_WRITE(VSYNC(cpu_transcoder
),
6101 (adjusted_mode
->crtc_vsync_start
- 1) |
6102 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6104 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6105 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6106 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6108 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6109 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6110 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6112 /* pipesrc controls the size that is scaled from, which should
6113 * always be the user's requested size.
6115 I915_WRITE(PIPESRC(pipe
),
6116 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6117 (intel_crtc
->config
.pipe_src_h
- 1));
6120 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6121 struct intel_crtc_config
*pipe_config
)
6123 struct drm_device
*dev
= crtc
->base
.dev
;
6124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6125 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6128 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6129 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6130 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6131 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6132 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6133 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6134 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6135 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6136 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6138 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6139 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6140 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6141 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6142 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6143 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6144 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6145 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6146 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6148 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6149 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6150 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6151 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6154 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6155 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6156 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6158 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6159 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6162 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6163 struct intel_crtc_config
*pipe_config
)
6165 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6166 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6167 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6168 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6170 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6171 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6172 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6173 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6175 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6177 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6178 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6181 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6183 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6189 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6190 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6191 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6193 if (intel_crtc
->config
.double_wide
)
6194 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6196 /* only g4x and later have fancy bpc/dither controls */
6197 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6198 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6199 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6200 pipeconf
|= PIPECONF_DITHER_EN
|
6201 PIPECONF_DITHER_TYPE_SP
;
6203 switch (intel_crtc
->config
.pipe_bpp
) {
6205 pipeconf
|= PIPECONF_6BPC
;
6208 pipeconf
|= PIPECONF_8BPC
;
6211 pipeconf
|= PIPECONF_10BPC
;
6214 /* Case prevented by intel_choose_pipe_bpp_dither. */
6219 if (HAS_PIPE_CXSR(dev
)) {
6220 if (intel_crtc
->lowfreq_avail
) {
6221 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6222 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6224 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6228 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6229 if (INTEL_INFO(dev
)->gen
< 4 ||
6230 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6231 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6233 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6235 pipeconf
|= PIPECONF_PROGRESSIVE
;
6237 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6238 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6240 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6241 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6244 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6246 struct drm_framebuffer
*fb
)
6248 struct drm_device
*dev
= crtc
->dev
;
6249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6250 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6251 int refclk
, num_connectors
= 0;
6252 intel_clock_t clock
, reduced_clock
;
6253 bool ok
, has_reduced_clock
= false;
6254 bool is_lvds
= false, is_dsi
= false;
6255 struct intel_encoder
*encoder
;
6256 const intel_limit_t
*limit
;
6258 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6259 switch (encoder
->type
) {
6260 case INTEL_OUTPUT_LVDS
:
6263 case INTEL_OUTPUT_DSI
:
6274 if (!intel_crtc
->config
.clock_set
) {
6275 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6278 * Returns a set of divisors for the desired target clock with
6279 * the given refclk, or FALSE. The returned values represent
6280 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6283 limit
= intel_limit(crtc
, refclk
);
6284 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6285 intel_crtc
->config
.port_clock
,
6286 refclk
, NULL
, &clock
);
6288 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6292 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6294 * Ensure we match the reduced clock's P to the target
6295 * clock. If the clocks don't match, we can't switch
6296 * the display clock by using the FP0/FP1. In such case
6297 * we will disable the LVDS downclock feature.
6300 dev_priv
->display
.find_dpll(limit
, crtc
,
6301 dev_priv
->lvds_downclock
,
6305 /* Compat-code for transition, will disappear. */
6306 intel_crtc
->config
.dpll
.n
= clock
.n
;
6307 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6308 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6309 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6310 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6314 i8xx_update_pll(intel_crtc
,
6315 has_reduced_clock
? &reduced_clock
: NULL
,
6317 } else if (IS_CHERRYVIEW(dev
)) {
6318 chv_update_pll(intel_crtc
);
6319 } else if (IS_VALLEYVIEW(dev
)) {
6320 vlv_update_pll(intel_crtc
);
6322 i9xx_update_pll(intel_crtc
,
6323 has_reduced_clock
? &reduced_clock
: NULL
,
6330 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6331 struct intel_crtc_config
*pipe_config
)
6333 struct drm_device
*dev
= crtc
->base
.dev
;
6334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6337 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6340 tmp
= I915_READ(PFIT_CONTROL
);
6341 if (!(tmp
& PFIT_ENABLE
))
6344 /* Check whether the pfit is attached to our pipe. */
6345 if (INTEL_INFO(dev
)->gen
< 4) {
6346 if (crtc
->pipe
!= PIPE_B
)
6349 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6353 pipe_config
->gmch_pfit
.control
= tmp
;
6354 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6355 if (INTEL_INFO(dev
)->gen
< 5)
6356 pipe_config
->gmch_pfit
.lvds_border_bits
=
6357 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6360 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6361 struct intel_crtc_config
*pipe_config
)
6363 struct drm_device
*dev
= crtc
->base
.dev
;
6364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6365 int pipe
= pipe_config
->cpu_transcoder
;
6366 intel_clock_t clock
;
6368 int refclk
= 100000;
6370 /* In case of MIPI DPLL will not even be used */
6371 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6374 mutex_lock(&dev_priv
->dpio_lock
);
6375 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6376 mutex_unlock(&dev_priv
->dpio_lock
);
6378 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6379 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6380 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6381 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6382 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6384 vlv_clock(refclk
, &clock
);
6386 /* clock.dot is the fast clock */
6387 pipe_config
->port_clock
= clock
.dot
/ 5;
6390 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6391 struct intel_plane_config
*plane_config
)
6393 struct drm_device
*dev
= crtc
->base
.dev
;
6394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6395 u32 val
, base
, offset
;
6396 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6397 int fourcc
, pixel_format
;
6400 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6401 if (!crtc
->base
.primary
->fb
) {
6402 DRM_DEBUG_KMS("failed to alloc fb\n");
6406 val
= I915_READ(DSPCNTR(plane
));
6408 if (INTEL_INFO(dev
)->gen
>= 4)
6409 if (val
& DISPPLANE_TILED
)
6410 plane_config
->tiled
= true;
6412 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6413 fourcc
= intel_format_to_fourcc(pixel_format
);
6414 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6415 crtc
->base
.primary
->fb
->bits_per_pixel
=
6416 drm_format_plane_cpp(fourcc
, 0) * 8;
6418 if (INTEL_INFO(dev
)->gen
>= 4) {
6419 if (plane_config
->tiled
)
6420 offset
= I915_READ(DSPTILEOFF(plane
));
6422 offset
= I915_READ(DSPLINOFF(plane
));
6423 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6425 base
= I915_READ(DSPADDR(plane
));
6427 plane_config
->base
= base
;
6429 val
= I915_READ(PIPESRC(pipe
));
6430 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6431 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6433 val
= I915_READ(DSPSTRIDE(pipe
));
6434 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6436 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6437 plane_config
->tiled
);
6439 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6442 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6443 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6444 crtc
->base
.primary
->fb
->height
,
6445 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6446 crtc
->base
.primary
->fb
->pitches
[0],
6447 plane_config
->size
);
6451 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6452 struct intel_crtc_config
*pipe_config
)
6454 struct drm_device
*dev
= crtc
->base
.dev
;
6455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6456 int pipe
= pipe_config
->cpu_transcoder
;
6457 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6458 intel_clock_t clock
;
6459 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6460 int refclk
= 100000;
6462 mutex_lock(&dev_priv
->dpio_lock
);
6463 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6464 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6465 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6466 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6467 mutex_unlock(&dev_priv
->dpio_lock
);
6469 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6470 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6471 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6472 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6473 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6475 chv_clock(refclk
, &clock
);
6477 /* clock.dot is the fast clock */
6478 pipe_config
->port_clock
= clock
.dot
/ 5;
6481 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6482 struct intel_crtc_config
*pipe_config
)
6484 struct drm_device
*dev
= crtc
->base
.dev
;
6485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6488 if (!intel_display_power_enabled(dev_priv
,
6489 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6492 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6493 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6495 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6496 if (!(tmp
& PIPECONF_ENABLE
))
6499 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6500 switch (tmp
& PIPECONF_BPC_MASK
) {
6502 pipe_config
->pipe_bpp
= 18;
6505 pipe_config
->pipe_bpp
= 24;
6507 case PIPECONF_10BPC
:
6508 pipe_config
->pipe_bpp
= 30;
6515 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6516 pipe_config
->limited_color_range
= true;
6518 if (INTEL_INFO(dev
)->gen
< 4)
6519 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6521 intel_get_pipe_timings(crtc
, pipe_config
);
6523 i9xx_get_pfit_config(crtc
, pipe_config
);
6525 if (INTEL_INFO(dev
)->gen
>= 4) {
6526 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6527 pipe_config
->pixel_multiplier
=
6528 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6529 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6530 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6531 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6532 tmp
= I915_READ(DPLL(crtc
->pipe
));
6533 pipe_config
->pixel_multiplier
=
6534 ((tmp
& SDVO_MULTIPLIER_MASK
)
6535 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6537 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6538 * port and will be fixed up in the encoder->get_config
6540 pipe_config
->pixel_multiplier
= 1;
6542 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6543 if (!IS_VALLEYVIEW(dev
)) {
6544 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6545 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6547 /* Mask out read-only status bits. */
6548 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6549 DPLL_PORTC_READY_MASK
|
6550 DPLL_PORTB_READY_MASK
);
6553 if (IS_CHERRYVIEW(dev
))
6554 chv_crtc_clock_get(crtc
, pipe_config
);
6555 else if (IS_VALLEYVIEW(dev
))
6556 vlv_crtc_clock_get(crtc
, pipe_config
);
6558 i9xx_crtc_clock_get(crtc
, pipe_config
);
6563 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6566 struct intel_encoder
*encoder
;
6568 bool has_lvds
= false;
6569 bool has_cpu_edp
= false;
6570 bool has_panel
= false;
6571 bool has_ck505
= false;
6572 bool can_ssc
= false;
6574 /* We need to take the global config into account */
6575 for_each_intel_encoder(dev
, encoder
) {
6576 switch (encoder
->type
) {
6577 case INTEL_OUTPUT_LVDS
:
6581 case INTEL_OUTPUT_EDP
:
6583 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6589 if (HAS_PCH_IBX(dev
)) {
6590 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6591 can_ssc
= has_ck505
;
6597 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6598 has_panel
, has_lvds
, has_ck505
);
6600 /* Ironlake: try to setup display ref clock before DPLL
6601 * enabling. This is only under driver's control after
6602 * PCH B stepping, previous chipset stepping should be
6603 * ignoring this setting.
6605 val
= I915_READ(PCH_DREF_CONTROL
);
6607 /* As we must carefully and slowly disable/enable each source in turn,
6608 * compute the final state we want first and check if we need to
6609 * make any changes at all.
6612 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6614 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6616 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6618 final
&= ~DREF_SSC_SOURCE_MASK
;
6619 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6620 final
&= ~DREF_SSC1_ENABLE
;
6623 final
|= DREF_SSC_SOURCE_ENABLE
;
6625 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6626 final
|= DREF_SSC1_ENABLE
;
6629 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6630 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6632 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6634 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6636 final
|= DREF_SSC_SOURCE_DISABLE
;
6637 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6643 /* Always enable nonspread source */
6644 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6647 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6649 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6652 val
&= ~DREF_SSC_SOURCE_MASK
;
6653 val
|= DREF_SSC_SOURCE_ENABLE
;
6655 /* SSC must be turned on before enabling the CPU output */
6656 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6657 DRM_DEBUG_KMS("Using SSC on panel\n");
6658 val
|= DREF_SSC1_ENABLE
;
6660 val
&= ~DREF_SSC1_ENABLE
;
6662 /* Get SSC going before enabling the outputs */
6663 I915_WRITE(PCH_DREF_CONTROL
, val
);
6664 POSTING_READ(PCH_DREF_CONTROL
);
6667 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6669 /* Enable CPU source on CPU attached eDP */
6671 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6672 DRM_DEBUG_KMS("Using SSC on eDP\n");
6673 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6675 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6677 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6679 I915_WRITE(PCH_DREF_CONTROL
, val
);
6680 POSTING_READ(PCH_DREF_CONTROL
);
6683 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6685 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6687 /* Turn off CPU output */
6688 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6690 I915_WRITE(PCH_DREF_CONTROL
, val
);
6691 POSTING_READ(PCH_DREF_CONTROL
);
6694 /* Turn off the SSC source */
6695 val
&= ~DREF_SSC_SOURCE_MASK
;
6696 val
|= DREF_SSC_SOURCE_DISABLE
;
6699 val
&= ~DREF_SSC1_ENABLE
;
6701 I915_WRITE(PCH_DREF_CONTROL
, val
);
6702 POSTING_READ(PCH_DREF_CONTROL
);
6706 BUG_ON(val
!= final
);
6709 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6713 tmp
= I915_READ(SOUTH_CHICKEN2
);
6714 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6715 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6717 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6718 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6719 DRM_ERROR("FDI mPHY reset assert timeout\n");
6721 tmp
= I915_READ(SOUTH_CHICKEN2
);
6722 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6723 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6725 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6726 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6727 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6730 /* WaMPhyProgramming:hsw */
6731 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6735 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6736 tmp
&= ~(0xFF << 24);
6737 tmp
|= (0x12 << 24);
6738 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6740 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6742 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6744 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6746 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6748 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6749 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6750 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6752 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6753 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6754 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6756 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6759 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6761 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6764 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6766 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6769 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6771 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6774 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6776 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6777 tmp
&= ~(0xFF << 16);
6778 tmp
|= (0x1C << 16);
6779 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6781 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6782 tmp
&= ~(0xFF << 16);
6783 tmp
|= (0x1C << 16);
6784 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6786 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6788 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6790 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6792 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6794 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6795 tmp
&= ~(0xF << 28);
6797 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6799 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6800 tmp
&= ~(0xF << 28);
6802 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6805 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6806 * Programming" based on the parameters passed:
6807 * - Sequence to enable CLKOUT_DP
6808 * - Sequence to enable CLKOUT_DP without spread
6809 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6811 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6817 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6819 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6820 with_fdi
, "LP PCH doesn't have FDI\n"))
6823 mutex_lock(&dev_priv
->dpio_lock
);
6825 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6826 tmp
&= ~SBI_SSCCTL_DISABLE
;
6827 tmp
|= SBI_SSCCTL_PATHALT
;
6828 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6833 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6834 tmp
&= ~SBI_SSCCTL_PATHALT
;
6835 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6838 lpt_reset_fdi_mphy(dev_priv
);
6839 lpt_program_fdi_mphy(dev_priv
);
6843 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6844 SBI_GEN0
: SBI_DBUFF0
;
6845 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6846 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6847 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6849 mutex_unlock(&dev_priv
->dpio_lock
);
6852 /* Sequence to disable CLKOUT_DP */
6853 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6858 mutex_lock(&dev_priv
->dpio_lock
);
6860 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6861 SBI_GEN0
: SBI_DBUFF0
;
6862 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6863 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6864 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6866 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6867 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6868 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6869 tmp
|= SBI_SSCCTL_PATHALT
;
6870 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6873 tmp
|= SBI_SSCCTL_DISABLE
;
6874 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6877 mutex_unlock(&dev_priv
->dpio_lock
);
6880 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6882 struct intel_encoder
*encoder
;
6883 bool has_vga
= false;
6885 for_each_intel_encoder(dev
, encoder
) {
6886 switch (encoder
->type
) {
6887 case INTEL_OUTPUT_ANALOG
:
6894 lpt_enable_clkout_dp(dev
, true, true);
6896 lpt_disable_clkout_dp(dev
);
6900 * Initialize reference clocks when the driver loads
6902 void intel_init_pch_refclk(struct drm_device
*dev
)
6904 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6905 ironlake_init_pch_refclk(dev
);
6906 else if (HAS_PCH_LPT(dev
))
6907 lpt_init_pch_refclk(dev
);
6910 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6912 struct drm_device
*dev
= crtc
->dev
;
6913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6914 struct intel_encoder
*encoder
;
6915 int num_connectors
= 0;
6916 bool is_lvds
= false;
6918 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6919 switch (encoder
->type
) {
6920 case INTEL_OUTPUT_LVDS
:
6927 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6928 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6929 dev_priv
->vbt
.lvds_ssc_freq
);
6930 return dev_priv
->vbt
.lvds_ssc_freq
;
6936 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6938 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6939 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6940 int pipe
= intel_crtc
->pipe
;
6945 switch (intel_crtc
->config
.pipe_bpp
) {
6947 val
|= PIPECONF_6BPC
;
6950 val
|= PIPECONF_8BPC
;
6953 val
|= PIPECONF_10BPC
;
6956 val
|= PIPECONF_12BPC
;
6959 /* Case prevented by intel_choose_pipe_bpp_dither. */
6963 if (intel_crtc
->config
.dither
)
6964 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6966 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6967 val
|= PIPECONF_INTERLACED_ILK
;
6969 val
|= PIPECONF_PROGRESSIVE
;
6971 if (intel_crtc
->config
.limited_color_range
)
6972 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6974 I915_WRITE(PIPECONF(pipe
), val
);
6975 POSTING_READ(PIPECONF(pipe
));
6979 * Set up the pipe CSC unit.
6981 * Currently only full range RGB to limited range RGB conversion
6982 * is supported, but eventually this should handle various
6983 * RGB<->YCbCr scenarios as well.
6985 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6987 struct drm_device
*dev
= crtc
->dev
;
6988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6989 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6990 int pipe
= intel_crtc
->pipe
;
6991 uint16_t coeff
= 0x7800; /* 1.0 */
6994 * TODO: Check what kind of values actually come out of the pipe
6995 * with these coeff/postoff values and adjust to get the best
6996 * accuracy. Perhaps we even need to take the bpc value into
7000 if (intel_crtc
->config
.limited_color_range
)
7001 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7004 * GY/GU and RY/RU should be the other way around according
7005 * to BSpec, but reality doesn't agree. Just set them up in
7006 * a way that results in the correct picture.
7008 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7009 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7011 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7012 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7014 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7015 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7017 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7018 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7019 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7021 if (INTEL_INFO(dev
)->gen
> 6) {
7022 uint16_t postoff
= 0;
7024 if (intel_crtc
->config
.limited_color_range
)
7025 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7027 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7028 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7029 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7031 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7033 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7035 if (intel_crtc
->config
.limited_color_range
)
7036 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7038 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7042 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7044 struct drm_device
*dev
= crtc
->dev
;
7045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7046 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7047 enum pipe pipe
= intel_crtc
->pipe
;
7048 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7053 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
7054 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7056 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7057 val
|= PIPECONF_INTERLACED_ILK
;
7059 val
|= PIPECONF_PROGRESSIVE
;
7061 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7062 POSTING_READ(PIPECONF(cpu_transcoder
));
7064 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7065 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7067 if (IS_BROADWELL(dev
)) {
7070 switch (intel_crtc
->config
.pipe_bpp
) {
7072 val
|= PIPEMISC_DITHER_6_BPC
;
7075 val
|= PIPEMISC_DITHER_8_BPC
;
7078 val
|= PIPEMISC_DITHER_10_BPC
;
7081 val
|= PIPEMISC_DITHER_12_BPC
;
7084 /* Case prevented by pipe_config_set_bpp. */
7088 if (intel_crtc
->config
.dither
)
7089 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7091 I915_WRITE(PIPEMISC(pipe
), val
);
7095 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7096 intel_clock_t
*clock
,
7097 bool *has_reduced_clock
,
7098 intel_clock_t
*reduced_clock
)
7100 struct drm_device
*dev
= crtc
->dev
;
7101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7102 struct intel_encoder
*intel_encoder
;
7104 const intel_limit_t
*limit
;
7105 bool ret
, is_lvds
= false;
7107 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7108 switch (intel_encoder
->type
) {
7109 case INTEL_OUTPUT_LVDS
:
7115 refclk
= ironlake_get_refclk(crtc
);
7118 * Returns a set of divisors for the desired target clock with the given
7119 * refclk, or FALSE. The returned values represent the clock equation:
7120 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7122 limit
= intel_limit(crtc
, refclk
);
7123 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
7124 to_intel_crtc(crtc
)->config
.port_clock
,
7125 refclk
, NULL
, clock
);
7129 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7131 * Ensure we match the reduced clock's P to the target clock.
7132 * If the clocks don't match, we can't switch the display clock
7133 * by using the FP0/FP1. In such case we will disable the LVDS
7134 * downclock feature.
7136 *has_reduced_clock
=
7137 dev_priv
->display
.find_dpll(limit
, crtc
,
7138 dev_priv
->lvds_downclock
,
7146 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7149 * Account for spread spectrum to avoid
7150 * oversubscribing the link. Max center spread
7151 * is 2.5%; use 5% for safety's sake.
7153 u32 bps
= target_clock
* bpp
* 21 / 20;
7154 return DIV_ROUND_UP(bps
, link_bw
* 8);
7157 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7159 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7162 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7164 intel_clock_t
*reduced_clock
, u32
*fp2
)
7166 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7167 struct drm_device
*dev
= crtc
->dev
;
7168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7169 struct intel_encoder
*intel_encoder
;
7171 int factor
, num_connectors
= 0;
7172 bool is_lvds
= false, is_sdvo
= false;
7174 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7175 switch (intel_encoder
->type
) {
7176 case INTEL_OUTPUT_LVDS
:
7179 case INTEL_OUTPUT_SDVO
:
7180 case INTEL_OUTPUT_HDMI
:
7188 /* Enable autotuning of the PLL clock (if permissible) */
7191 if ((intel_panel_use_ssc(dev_priv
) &&
7192 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7193 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7195 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7198 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7201 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7207 dpll
|= DPLLB_MODE_LVDS
;
7209 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7211 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7212 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7215 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7216 if (intel_crtc
->config
.has_dp_encoder
)
7217 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7219 /* compute bitmask from p1 value */
7220 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7222 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7224 switch (intel_crtc
->config
.dpll
.p2
) {
7226 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7229 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7232 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7235 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7239 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7240 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7242 dpll
|= PLL_REF_INPUT_DREFCLK
;
7244 return dpll
| DPLL_VCO_ENABLE
;
7247 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7249 struct drm_framebuffer
*fb
)
7251 struct drm_device
*dev
= crtc
->dev
;
7252 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7253 int num_connectors
= 0;
7254 intel_clock_t clock
, reduced_clock
;
7255 u32 dpll
= 0, fp
= 0, fp2
= 0;
7256 bool ok
, has_reduced_clock
= false;
7257 bool is_lvds
= false;
7258 struct intel_encoder
*encoder
;
7259 struct intel_shared_dpll
*pll
;
7261 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7262 switch (encoder
->type
) {
7263 case INTEL_OUTPUT_LVDS
:
7271 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7272 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7274 ok
= ironlake_compute_clocks(crtc
, &clock
,
7275 &has_reduced_clock
, &reduced_clock
);
7276 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7277 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7280 /* Compat-code for transition, will disappear. */
7281 if (!intel_crtc
->config
.clock_set
) {
7282 intel_crtc
->config
.dpll
.n
= clock
.n
;
7283 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7284 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7285 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7286 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7289 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7290 if (intel_crtc
->config
.has_pch_encoder
) {
7291 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7292 if (has_reduced_clock
)
7293 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7295 dpll
= ironlake_compute_dpll(intel_crtc
,
7296 &fp
, &reduced_clock
,
7297 has_reduced_clock
? &fp2
: NULL
);
7299 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7300 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7301 if (has_reduced_clock
)
7302 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7304 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7306 pll
= intel_get_shared_dpll(intel_crtc
);
7308 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7309 pipe_name(intel_crtc
->pipe
));
7313 intel_put_shared_dpll(intel_crtc
);
7315 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7316 intel_crtc
->lowfreq_avail
= true;
7318 intel_crtc
->lowfreq_avail
= false;
7323 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7324 struct intel_link_m_n
*m_n
)
7326 struct drm_device
*dev
= crtc
->base
.dev
;
7327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7328 enum pipe pipe
= crtc
->pipe
;
7330 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7331 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7332 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7334 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7335 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7336 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7339 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7340 enum transcoder transcoder
,
7341 struct intel_link_m_n
*m_n
,
7342 struct intel_link_m_n
*m2_n2
)
7344 struct drm_device
*dev
= crtc
->base
.dev
;
7345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7346 enum pipe pipe
= crtc
->pipe
;
7348 if (INTEL_INFO(dev
)->gen
>= 5) {
7349 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7350 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7351 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7353 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7354 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7355 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7356 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7357 * gen < 8) and if DRRS is supported (to make sure the
7358 * registers are not unnecessarily read).
7360 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7361 crtc
->config
.has_drrs
) {
7362 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7363 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7364 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7366 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7367 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7368 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7371 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7372 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7373 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7375 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7376 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7377 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7381 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7382 struct intel_crtc_config
*pipe_config
)
7384 if (crtc
->config
.has_pch_encoder
)
7385 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7387 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7388 &pipe_config
->dp_m_n
,
7389 &pipe_config
->dp_m2_n2
);
7392 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7393 struct intel_crtc_config
*pipe_config
)
7395 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7396 &pipe_config
->fdi_m_n
, NULL
);
7399 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7400 struct intel_crtc_config
*pipe_config
)
7402 struct drm_device
*dev
= crtc
->base
.dev
;
7403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7406 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7408 if (tmp
& PF_ENABLE
) {
7409 pipe_config
->pch_pfit
.enabled
= true;
7410 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7411 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7413 /* We currently do not free assignements of panel fitters on
7414 * ivb/hsw (since we don't use the higher upscaling modes which
7415 * differentiates them) so just WARN about this case for now. */
7417 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7418 PF_PIPE_SEL_IVB(crtc
->pipe
));
7423 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7424 struct intel_plane_config
*plane_config
)
7426 struct drm_device
*dev
= crtc
->base
.dev
;
7427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7428 u32 val
, base
, offset
;
7429 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7430 int fourcc
, pixel_format
;
7433 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7434 if (!crtc
->base
.primary
->fb
) {
7435 DRM_DEBUG_KMS("failed to alloc fb\n");
7439 val
= I915_READ(DSPCNTR(plane
));
7441 if (INTEL_INFO(dev
)->gen
>= 4)
7442 if (val
& DISPPLANE_TILED
)
7443 plane_config
->tiled
= true;
7445 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7446 fourcc
= intel_format_to_fourcc(pixel_format
);
7447 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7448 crtc
->base
.primary
->fb
->bits_per_pixel
=
7449 drm_format_plane_cpp(fourcc
, 0) * 8;
7451 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7452 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7453 offset
= I915_READ(DSPOFFSET(plane
));
7455 if (plane_config
->tiled
)
7456 offset
= I915_READ(DSPTILEOFF(plane
));
7458 offset
= I915_READ(DSPLINOFF(plane
));
7460 plane_config
->base
= base
;
7462 val
= I915_READ(PIPESRC(pipe
));
7463 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7464 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7466 val
= I915_READ(DSPSTRIDE(pipe
));
7467 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7469 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7470 plane_config
->tiled
);
7472 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7475 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7476 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7477 crtc
->base
.primary
->fb
->height
,
7478 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7479 crtc
->base
.primary
->fb
->pitches
[0],
7480 plane_config
->size
);
7483 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7484 struct intel_crtc_config
*pipe_config
)
7486 struct drm_device
*dev
= crtc
->base
.dev
;
7487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7490 if (!intel_display_power_enabled(dev_priv
,
7491 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7494 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7495 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7497 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7498 if (!(tmp
& PIPECONF_ENABLE
))
7501 switch (tmp
& PIPECONF_BPC_MASK
) {
7503 pipe_config
->pipe_bpp
= 18;
7506 pipe_config
->pipe_bpp
= 24;
7508 case PIPECONF_10BPC
:
7509 pipe_config
->pipe_bpp
= 30;
7511 case PIPECONF_12BPC
:
7512 pipe_config
->pipe_bpp
= 36;
7518 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7519 pipe_config
->limited_color_range
= true;
7521 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7522 struct intel_shared_dpll
*pll
;
7524 pipe_config
->has_pch_encoder
= true;
7526 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7527 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7528 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7530 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7532 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7533 pipe_config
->shared_dpll
=
7534 (enum intel_dpll_id
) crtc
->pipe
;
7536 tmp
= I915_READ(PCH_DPLL_SEL
);
7537 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7538 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7540 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7543 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7545 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7546 &pipe_config
->dpll_hw_state
));
7548 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7549 pipe_config
->pixel_multiplier
=
7550 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7551 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7553 ironlake_pch_clock_get(crtc
, pipe_config
);
7555 pipe_config
->pixel_multiplier
= 1;
7558 intel_get_pipe_timings(crtc
, pipe_config
);
7560 ironlake_get_pfit_config(crtc
, pipe_config
);
7565 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7567 struct drm_device
*dev
= dev_priv
->dev
;
7568 struct intel_crtc
*crtc
;
7570 for_each_intel_crtc(dev
, crtc
)
7571 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7572 pipe_name(crtc
->pipe
));
7574 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7575 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7576 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7577 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7578 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7579 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7580 "CPU PWM1 enabled\n");
7581 if (IS_HASWELL(dev
))
7582 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7583 "CPU PWM2 enabled\n");
7584 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7585 "PCH PWM1 enabled\n");
7586 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7587 "Utility pin enabled\n");
7588 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7591 * In theory we can still leave IRQs enabled, as long as only the HPD
7592 * interrupts remain enabled. We used to check for that, but since it's
7593 * gen-specific and since we only disable LCPLL after we fully disable
7594 * the interrupts, the check below should be enough.
7596 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7599 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7601 struct drm_device
*dev
= dev_priv
->dev
;
7603 if (IS_HASWELL(dev
))
7604 return I915_READ(D_COMP_HSW
);
7606 return I915_READ(D_COMP_BDW
);
7609 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7611 struct drm_device
*dev
= dev_priv
->dev
;
7613 if (IS_HASWELL(dev
)) {
7614 mutex_lock(&dev_priv
->rps
.hw_lock
);
7615 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7617 DRM_ERROR("Failed to write to D_COMP\n");
7618 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7620 I915_WRITE(D_COMP_BDW
, val
);
7621 POSTING_READ(D_COMP_BDW
);
7626 * This function implements pieces of two sequences from BSpec:
7627 * - Sequence for display software to disable LCPLL
7628 * - Sequence for display software to allow package C8+
7629 * The steps implemented here are just the steps that actually touch the LCPLL
7630 * register. Callers should take care of disabling all the display engine
7631 * functions, doing the mode unset, fixing interrupts, etc.
7633 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7634 bool switch_to_fclk
, bool allow_power_down
)
7638 assert_can_disable_lcpll(dev_priv
);
7640 val
= I915_READ(LCPLL_CTL
);
7642 if (switch_to_fclk
) {
7643 val
|= LCPLL_CD_SOURCE_FCLK
;
7644 I915_WRITE(LCPLL_CTL
, val
);
7646 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7647 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7648 DRM_ERROR("Switching to FCLK failed\n");
7650 val
= I915_READ(LCPLL_CTL
);
7653 val
|= LCPLL_PLL_DISABLE
;
7654 I915_WRITE(LCPLL_CTL
, val
);
7655 POSTING_READ(LCPLL_CTL
);
7657 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7658 DRM_ERROR("LCPLL still locked\n");
7660 val
= hsw_read_dcomp(dev_priv
);
7661 val
|= D_COMP_COMP_DISABLE
;
7662 hsw_write_dcomp(dev_priv
, val
);
7665 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7667 DRM_ERROR("D_COMP RCOMP still in progress\n");
7669 if (allow_power_down
) {
7670 val
= I915_READ(LCPLL_CTL
);
7671 val
|= LCPLL_POWER_DOWN_ALLOW
;
7672 I915_WRITE(LCPLL_CTL
, val
);
7673 POSTING_READ(LCPLL_CTL
);
7678 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7681 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7684 unsigned long irqflags
;
7686 val
= I915_READ(LCPLL_CTL
);
7688 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7689 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7693 * Make sure we're not on PC8 state before disabling PC8, otherwise
7694 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7696 * The other problem is that hsw_restore_lcpll() is called as part of
7697 * the runtime PM resume sequence, so we can't just call
7698 * gen6_gt_force_wake_get() because that function calls
7699 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7700 * while we are on the resume sequence. So to solve this problem we have
7701 * to call special forcewake code that doesn't touch runtime PM and
7702 * doesn't enable the forcewake delayed work.
7704 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7705 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7706 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7707 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7709 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7710 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7711 I915_WRITE(LCPLL_CTL
, val
);
7712 POSTING_READ(LCPLL_CTL
);
7715 val
= hsw_read_dcomp(dev_priv
);
7716 val
|= D_COMP_COMP_FORCE
;
7717 val
&= ~D_COMP_COMP_DISABLE
;
7718 hsw_write_dcomp(dev_priv
, val
);
7720 val
= I915_READ(LCPLL_CTL
);
7721 val
&= ~LCPLL_PLL_DISABLE
;
7722 I915_WRITE(LCPLL_CTL
, val
);
7724 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7725 DRM_ERROR("LCPLL not locked yet\n");
7727 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7728 val
= I915_READ(LCPLL_CTL
);
7729 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7730 I915_WRITE(LCPLL_CTL
, val
);
7732 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7733 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7734 DRM_ERROR("Switching back to LCPLL failed\n");
7737 /* See the big comment above. */
7738 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7739 if (--dev_priv
->uncore
.forcewake_count
== 0)
7740 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7741 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7745 * Package states C8 and deeper are really deep PC states that can only be
7746 * reached when all the devices on the system allow it, so even if the graphics
7747 * device allows PC8+, it doesn't mean the system will actually get to these
7748 * states. Our driver only allows PC8+ when going into runtime PM.
7750 * The requirements for PC8+ are that all the outputs are disabled, the power
7751 * well is disabled and most interrupts are disabled, and these are also
7752 * requirements for runtime PM. When these conditions are met, we manually do
7753 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7754 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7757 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7758 * the state of some registers, so when we come back from PC8+ we need to
7759 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7760 * need to take care of the registers kept by RC6. Notice that this happens even
7761 * if we don't put the device in PCI D3 state (which is what currently happens
7762 * because of the runtime PM support).
7764 * For more, read "Display Sequences for Package C8" on the hardware
7767 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7769 struct drm_device
*dev
= dev_priv
->dev
;
7772 DRM_DEBUG_KMS("Enabling package C8+\n");
7774 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7775 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7776 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7777 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7780 lpt_disable_clkout_dp(dev
);
7781 hsw_disable_lcpll(dev_priv
, true, true);
7784 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7786 struct drm_device
*dev
= dev_priv
->dev
;
7789 DRM_DEBUG_KMS("Disabling package C8+\n");
7791 hsw_restore_lcpll(dev_priv
);
7792 lpt_init_pch_refclk(dev
);
7794 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7795 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7796 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7797 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7800 intel_prepare_ddi(dev
);
7803 static void snb_modeset_global_resources(struct drm_device
*dev
)
7805 modeset_update_crtc_power_domains(dev
);
7808 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7810 modeset_update_crtc_power_domains(dev
);
7813 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7815 struct drm_framebuffer
*fb
)
7817 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7819 if (!intel_ddi_pll_select(intel_crtc
))
7822 intel_crtc
->lowfreq_avail
= false;
7827 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7829 struct intel_crtc_config
*pipe_config
)
7831 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7833 switch (pipe_config
->ddi_pll_sel
) {
7834 case PORT_CLK_SEL_WRPLL1
:
7835 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7837 case PORT_CLK_SEL_WRPLL2
:
7838 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7843 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7844 struct intel_crtc_config
*pipe_config
)
7846 struct drm_device
*dev
= crtc
->base
.dev
;
7847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7848 struct intel_shared_dpll
*pll
;
7852 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7854 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7856 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7858 if (pipe_config
->shared_dpll
>= 0) {
7859 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7861 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7862 &pipe_config
->dpll_hw_state
));
7866 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7867 * DDI E. So just check whether this pipe is wired to DDI E and whether
7868 * the PCH transcoder is on.
7870 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7871 pipe_config
->has_pch_encoder
= true;
7873 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7874 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7875 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7877 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7881 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7882 struct intel_crtc_config
*pipe_config
)
7884 struct drm_device
*dev
= crtc
->base
.dev
;
7885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7886 enum intel_display_power_domain pfit_domain
;
7889 if (!intel_display_power_enabled(dev_priv
,
7890 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7893 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7894 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7896 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7897 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7898 enum pipe trans_edp_pipe
;
7899 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7901 WARN(1, "unknown pipe linked to edp transcoder\n");
7902 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7903 case TRANS_DDI_EDP_INPUT_A_ON
:
7904 trans_edp_pipe
= PIPE_A
;
7906 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7907 trans_edp_pipe
= PIPE_B
;
7909 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7910 trans_edp_pipe
= PIPE_C
;
7914 if (trans_edp_pipe
== crtc
->pipe
)
7915 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7918 if (!intel_display_power_enabled(dev_priv
,
7919 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7922 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7923 if (!(tmp
& PIPECONF_ENABLE
))
7926 haswell_get_ddi_port_state(crtc
, pipe_config
);
7928 intel_get_pipe_timings(crtc
, pipe_config
);
7930 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7931 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7932 ironlake_get_pfit_config(crtc
, pipe_config
);
7934 if (IS_HASWELL(dev
))
7935 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7936 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7938 pipe_config
->pixel_multiplier
= 1;
7946 } hdmi_audio_clock
[] = {
7947 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7948 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7949 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7950 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7951 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7952 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7953 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7954 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7955 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7956 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7959 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7960 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7964 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7965 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7969 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7970 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7974 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7975 hdmi_audio_clock
[i
].clock
,
7976 hdmi_audio_clock
[i
].config
);
7978 return hdmi_audio_clock
[i
].config
;
7981 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7982 int reg_eldv
, uint32_t bits_eldv
,
7983 int reg_elda
, uint32_t bits_elda
,
7986 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7987 uint8_t *eld
= connector
->eld
;
7990 i
= I915_READ(reg_eldv
);
7999 i
= I915_READ(reg_elda
);
8001 I915_WRITE(reg_elda
, i
);
8003 for (i
= 0; i
< eld
[2]; i
++)
8004 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
8010 static void g4x_write_eld(struct drm_connector
*connector
,
8011 struct drm_crtc
*crtc
,
8012 struct drm_display_mode
*mode
)
8014 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8015 uint8_t *eld
= connector
->eld
;
8020 i
= I915_READ(G4X_AUD_VID_DID
);
8022 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
8023 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
8025 eldv
= G4X_ELDV_DEVCTG
;
8027 if (intel_eld_uptodate(connector
,
8028 G4X_AUD_CNTL_ST
, eldv
,
8029 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
8030 G4X_HDMIW_HDMIEDID
))
8033 i
= I915_READ(G4X_AUD_CNTL_ST
);
8034 i
&= ~(eldv
| G4X_ELD_ADDR
);
8035 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
8036 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
8041 len
= min_t(uint8_t, eld
[2], len
);
8042 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8043 for (i
= 0; i
< len
; i
++)
8044 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
8046 i
= I915_READ(G4X_AUD_CNTL_ST
);
8048 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
8051 static void haswell_write_eld(struct drm_connector
*connector
,
8052 struct drm_crtc
*crtc
,
8053 struct drm_display_mode
*mode
)
8055 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8056 uint8_t *eld
= connector
->eld
;
8060 int pipe
= to_intel_crtc(crtc
)->pipe
;
8063 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
8064 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
8065 int aud_config
= HSW_AUD_CFG(pipe
);
8066 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
8068 /* Audio output enable */
8069 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8070 tmp
= I915_READ(aud_cntrl_st2
);
8071 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
8072 I915_WRITE(aud_cntrl_st2
, tmp
);
8073 POSTING_READ(aud_cntrl_st2
);
8075 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
8077 /* Set ELD valid state */
8078 tmp
= I915_READ(aud_cntrl_st2
);
8079 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
8080 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
8081 I915_WRITE(aud_cntrl_st2
, tmp
);
8082 tmp
= I915_READ(aud_cntrl_st2
);
8083 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
8085 /* Enable HDMI mode */
8086 tmp
= I915_READ(aud_config
);
8087 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
8088 /* clear N_programing_enable and N_value_index */
8089 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
8090 I915_WRITE(aud_config
, tmp
);
8092 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8094 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
8096 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8097 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8098 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8099 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8101 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8104 if (intel_eld_uptodate(connector
,
8105 aud_cntrl_st2
, eldv
,
8106 aud_cntl_st
, IBX_ELD_ADDRESS
,
8110 i
= I915_READ(aud_cntrl_st2
);
8112 I915_WRITE(aud_cntrl_st2
, i
);
8117 i
= I915_READ(aud_cntl_st
);
8118 i
&= ~IBX_ELD_ADDRESS
;
8119 I915_WRITE(aud_cntl_st
, i
);
8120 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
8121 DRM_DEBUG_DRIVER("port num:%d\n", i
);
8123 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8124 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8125 for (i
= 0; i
< len
; i
++)
8126 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8128 i
= I915_READ(aud_cntrl_st2
);
8130 I915_WRITE(aud_cntrl_st2
, i
);
8134 static void ironlake_write_eld(struct drm_connector
*connector
,
8135 struct drm_crtc
*crtc
,
8136 struct drm_display_mode
*mode
)
8138 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8139 uint8_t *eld
= connector
->eld
;
8147 int pipe
= to_intel_crtc(crtc
)->pipe
;
8149 if (HAS_PCH_IBX(connector
->dev
)) {
8150 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8151 aud_config
= IBX_AUD_CFG(pipe
);
8152 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8153 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8154 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8155 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8156 aud_config
= VLV_AUD_CFG(pipe
);
8157 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8158 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8160 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8161 aud_config
= CPT_AUD_CFG(pipe
);
8162 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8163 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8166 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8168 if (IS_VALLEYVIEW(connector
->dev
)) {
8169 struct intel_encoder
*intel_encoder
;
8170 struct intel_digital_port
*intel_dig_port
;
8172 intel_encoder
= intel_attached_encoder(connector
);
8173 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8174 i
= intel_dig_port
->port
;
8176 i
= I915_READ(aud_cntl_st
);
8177 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8178 /* DIP_Port_Select, 0x1 = PortB */
8182 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8183 /* operate blindly on all ports */
8184 eldv
= IBX_ELD_VALIDB
;
8185 eldv
|= IBX_ELD_VALIDB
<< 4;
8186 eldv
|= IBX_ELD_VALIDB
<< 8;
8188 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8189 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8192 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8193 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8194 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8195 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8197 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8200 if (intel_eld_uptodate(connector
,
8201 aud_cntrl_st2
, eldv
,
8202 aud_cntl_st
, IBX_ELD_ADDRESS
,
8206 i
= I915_READ(aud_cntrl_st2
);
8208 I915_WRITE(aud_cntrl_st2
, i
);
8213 i
= I915_READ(aud_cntl_st
);
8214 i
&= ~IBX_ELD_ADDRESS
;
8215 I915_WRITE(aud_cntl_st
, i
);
8217 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8218 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8219 for (i
= 0; i
< len
; i
++)
8220 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8222 i
= I915_READ(aud_cntrl_st2
);
8224 I915_WRITE(aud_cntrl_st2
, i
);
8227 void intel_write_eld(struct drm_encoder
*encoder
,
8228 struct drm_display_mode
*mode
)
8230 struct drm_crtc
*crtc
= encoder
->crtc
;
8231 struct drm_connector
*connector
;
8232 struct drm_device
*dev
= encoder
->dev
;
8233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8235 connector
= drm_select_eld(encoder
, mode
);
8239 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8242 connector
->encoder
->base
.id
,
8243 connector
->encoder
->name
);
8245 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8247 if (dev_priv
->display
.write_eld
)
8248 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8251 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8253 struct drm_device
*dev
= crtc
->dev
;
8254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8255 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8256 uint32_t cntl
= 0, size
= 0;
8259 unsigned int width
= intel_crtc
->cursor_width
;
8260 unsigned int height
= intel_crtc
->cursor_height
;
8261 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8265 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8276 cntl
|= CURSOR_ENABLE
|
8277 CURSOR_GAMMA_ENABLE
|
8278 CURSOR_FORMAT_ARGB
|
8279 CURSOR_STRIDE(stride
);
8281 size
= (height
<< 12) | width
;
8284 if (intel_crtc
->cursor_cntl
!= 0 &&
8285 (intel_crtc
->cursor_base
!= base
||
8286 intel_crtc
->cursor_size
!= size
||
8287 intel_crtc
->cursor_cntl
!= cntl
)) {
8288 /* On these chipsets we can only modify the base/size/stride
8289 * whilst the cursor is disabled.
8291 I915_WRITE(_CURACNTR
, 0);
8292 POSTING_READ(_CURACNTR
);
8293 intel_crtc
->cursor_cntl
= 0;
8296 if (intel_crtc
->cursor_base
!= base
)
8297 I915_WRITE(_CURABASE
, base
);
8299 if (intel_crtc
->cursor_size
!= size
) {
8300 I915_WRITE(CURSIZE
, size
);
8301 intel_crtc
->cursor_size
= size
;
8304 if (intel_crtc
->cursor_cntl
!= cntl
) {
8305 I915_WRITE(_CURACNTR
, cntl
);
8306 POSTING_READ(_CURACNTR
);
8307 intel_crtc
->cursor_cntl
= cntl
;
8311 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8313 struct drm_device
*dev
= crtc
->dev
;
8314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8315 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8316 int pipe
= intel_crtc
->pipe
;
8321 cntl
= MCURSOR_GAMMA_ENABLE
;
8322 switch (intel_crtc
->cursor_width
) {
8324 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8327 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8330 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8336 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8338 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8339 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8341 if (intel_crtc
->cursor_cntl
!= cntl
) {
8342 I915_WRITE(CURCNTR(pipe
), cntl
);
8343 POSTING_READ(CURCNTR(pipe
));
8344 intel_crtc
->cursor_cntl
= cntl
;
8347 /* and commit changes on next vblank */
8348 I915_WRITE(CURBASE(pipe
), base
);
8349 POSTING_READ(CURBASE(pipe
));
8352 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8353 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8356 struct drm_device
*dev
= crtc
->dev
;
8357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8359 int pipe
= intel_crtc
->pipe
;
8360 int x
= crtc
->cursor_x
;
8361 int y
= crtc
->cursor_y
;
8362 u32 base
= 0, pos
= 0;
8365 base
= intel_crtc
->cursor_addr
;
8367 if (x
>= intel_crtc
->config
.pipe_src_w
)
8370 if (y
>= intel_crtc
->config
.pipe_src_h
)
8374 if (x
+ intel_crtc
->cursor_width
<= 0)
8377 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8380 pos
|= x
<< CURSOR_X_SHIFT
;
8383 if (y
+ intel_crtc
->cursor_height
<= 0)
8386 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8389 pos
|= y
<< CURSOR_Y_SHIFT
;
8391 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8394 I915_WRITE(CURPOS(pipe
), pos
);
8396 if (IS_845G(dev
) || IS_I865G(dev
))
8397 i845_update_cursor(crtc
, base
);
8399 i9xx_update_cursor(crtc
, base
);
8400 intel_crtc
->cursor_base
= base
;
8403 static bool cursor_size_ok(struct drm_device
*dev
,
8404 uint32_t width
, uint32_t height
)
8406 if (width
== 0 || height
== 0)
8410 * 845g/865g are special in that they are only limited by
8411 * the width of their cursors, the height is arbitrary up to
8412 * the precision of the register. Everything else requires
8413 * square cursors, limited to a few power-of-two sizes.
8415 if (IS_845G(dev
) || IS_I865G(dev
)) {
8416 if ((width
& 63) != 0)
8419 if (width
> (IS_845G(dev
) ? 64 : 512))
8425 switch (width
| height
) {
8441 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8443 * Note that the object's reference will be consumed if the update fails. If
8444 * the update succeeds, the reference of the old object (if any) will be
8447 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8448 struct drm_i915_gem_object
*obj
,
8449 uint32_t width
, uint32_t height
)
8451 struct drm_device
*dev
= crtc
->dev
;
8452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8453 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8454 enum pipe pipe
= intel_crtc
->pipe
;
8455 unsigned old_width
, stride
;
8459 /* if we want to turn off the cursor ignore width and height */
8461 DRM_DEBUG_KMS("cursor off\n");
8463 mutex_lock(&dev
->struct_mutex
);
8467 /* Check for which cursor types we support */
8468 if (!cursor_size_ok(dev
, width
, height
)) {
8469 DRM_DEBUG("Cursor dimension not supported\n");
8473 stride
= roundup_pow_of_two(width
) * 4;
8474 if (obj
->base
.size
< stride
* height
) {
8475 DRM_DEBUG_KMS("buffer is too small\n");
8480 /* we only need to pin inside GTT if cursor is non-phy */
8481 mutex_lock(&dev
->struct_mutex
);
8482 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8485 if (obj
->tiling_mode
) {
8486 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8492 * Global gtt pte registers are special registers which actually
8493 * forward writes to a chunk of system memory. Which means that
8494 * there is no risk that the register values disappear as soon
8495 * as we call intel_runtime_pm_put(), so it is correct to wrap
8496 * only the pin/unpin/fence and not more.
8498 intel_runtime_pm_get(dev_priv
);
8500 /* Note that the w/a also requires 2 PTE of padding following
8501 * the bo. We currently fill all unused PTE with the shadow
8502 * page and so we should always have valid PTE following the
8503 * cursor preventing the VT-d warning.
8506 if (need_vtd_wa(dev
))
8507 alignment
= 64*1024;
8509 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8511 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8512 intel_runtime_pm_put(dev_priv
);
8516 ret
= i915_gem_object_put_fence(obj
);
8518 DRM_DEBUG_KMS("failed to release fence for cursor");
8519 intel_runtime_pm_put(dev_priv
);
8523 addr
= i915_gem_obj_ggtt_offset(obj
);
8525 intel_runtime_pm_put(dev_priv
);
8527 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8528 ret
= i915_gem_object_attach_phys(obj
, align
);
8530 DRM_DEBUG_KMS("failed to attach phys object\n");
8533 addr
= obj
->phys_handle
->busaddr
;
8537 if (intel_crtc
->cursor_bo
) {
8538 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8539 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8542 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8543 INTEL_FRONTBUFFER_CURSOR(pipe
));
8544 mutex_unlock(&dev
->struct_mutex
);
8546 old_width
= intel_crtc
->cursor_width
;
8548 intel_crtc
->cursor_addr
= addr
;
8549 intel_crtc
->cursor_bo
= obj
;
8550 intel_crtc
->cursor_width
= width
;
8551 intel_crtc
->cursor_height
= height
;
8553 if (intel_crtc
->active
) {
8554 if (old_width
!= width
)
8555 intel_update_watermarks(crtc
);
8556 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8559 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8563 i915_gem_object_unpin_from_display_plane(obj
);
8565 mutex_unlock(&dev
->struct_mutex
);
8567 drm_gem_object_unreference_unlocked(&obj
->base
);
8571 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8572 u16
*blue
, uint32_t start
, uint32_t size
)
8574 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8575 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8577 for (i
= start
; i
< end
; i
++) {
8578 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8579 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8580 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8583 intel_crtc_load_lut(crtc
);
8586 /* VESA 640x480x72Hz mode to set on the pipe */
8587 static struct drm_display_mode load_detect_mode
= {
8588 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8589 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8592 struct drm_framebuffer
*
8593 __intel_framebuffer_create(struct drm_device
*dev
,
8594 struct drm_mode_fb_cmd2
*mode_cmd
,
8595 struct drm_i915_gem_object
*obj
)
8597 struct intel_framebuffer
*intel_fb
;
8600 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8602 drm_gem_object_unreference_unlocked(&obj
->base
);
8603 return ERR_PTR(-ENOMEM
);
8606 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8610 return &intel_fb
->base
;
8612 drm_gem_object_unreference_unlocked(&obj
->base
);
8615 return ERR_PTR(ret
);
8618 static struct drm_framebuffer
*
8619 intel_framebuffer_create(struct drm_device
*dev
,
8620 struct drm_mode_fb_cmd2
*mode_cmd
,
8621 struct drm_i915_gem_object
*obj
)
8623 struct drm_framebuffer
*fb
;
8626 ret
= i915_mutex_lock_interruptible(dev
);
8628 return ERR_PTR(ret
);
8629 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8630 mutex_unlock(&dev
->struct_mutex
);
8636 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8638 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8639 return ALIGN(pitch
, 64);
8643 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8645 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8646 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8649 static struct drm_framebuffer
*
8650 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8651 struct drm_display_mode
*mode
,
8654 struct drm_i915_gem_object
*obj
;
8655 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8657 obj
= i915_gem_alloc_object(dev
,
8658 intel_framebuffer_size_for_mode(mode
, bpp
));
8660 return ERR_PTR(-ENOMEM
);
8662 mode_cmd
.width
= mode
->hdisplay
;
8663 mode_cmd
.height
= mode
->vdisplay
;
8664 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8666 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8668 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8671 static struct drm_framebuffer
*
8672 mode_fits_in_fbdev(struct drm_device
*dev
,
8673 struct drm_display_mode
*mode
)
8675 #ifdef CONFIG_DRM_I915_FBDEV
8676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8677 struct drm_i915_gem_object
*obj
;
8678 struct drm_framebuffer
*fb
;
8680 if (!dev_priv
->fbdev
)
8683 if (!dev_priv
->fbdev
->fb
)
8686 obj
= dev_priv
->fbdev
->fb
->obj
;
8689 fb
= &dev_priv
->fbdev
->fb
->base
;
8690 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8691 fb
->bits_per_pixel
))
8694 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8703 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8704 struct drm_display_mode
*mode
,
8705 struct intel_load_detect_pipe
*old
,
8706 struct drm_modeset_acquire_ctx
*ctx
)
8708 struct intel_crtc
*intel_crtc
;
8709 struct intel_encoder
*intel_encoder
=
8710 intel_attached_encoder(connector
);
8711 struct drm_crtc
*possible_crtc
;
8712 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8713 struct drm_crtc
*crtc
= NULL
;
8714 struct drm_device
*dev
= encoder
->dev
;
8715 struct drm_framebuffer
*fb
;
8716 struct drm_mode_config
*config
= &dev
->mode_config
;
8719 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8720 connector
->base
.id
, connector
->name
,
8721 encoder
->base
.id
, encoder
->name
);
8724 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8729 * Algorithm gets a little messy:
8731 * - if the connector already has an assigned crtc, use it (but make
8732 * sure it's on first)
8734 * - try to find the first unused crtc that can drive this connector,
8735 * and use that if we find one
8738 /* See if we already have a CRTC for this connector */
8739 if (encoder
->crtc
) {
8740 crtc
= encoder
->crtc
;
8742 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8746 old
->dpms_mode
= connector
->dpms
;
8747 old
->load_detect_temp
= false;
8749 /* Make sure the crtc and connector are running */
8750 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8751 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8756 /* Find an unused one (if possible) */
8757 for_each_crtc(dev
, possible_crtc
) {
8759 if (!(encoder
->possible_crtcs
& (1 << i
)))
8761 if (possible_crtc
->enabled
)
8763 /* This can occur when applying the pipe A quirk on resume. */
8764 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8767 crtc
= possible_crtc
;
8772 * If we didn't find an unused CRTC, don't use any.
8775 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8779 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8782 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8783 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8785 intel_crtc
= to_intel_crtc(crtc
);
8786 intel_crtc
->new_enabled
= true;
8787 intel_crtc
->new_config
= &intel_crtc
->config
;
8788 old
->dpms_mode
= connector
->dpms
;
8789 old
->load_detect_temp
= true;
8790 old
->release_fb
= NULL
;
8793 mode
= &load_detect_mode
;
8795 /* We need a framebuffer large enough to accommodate all accesses
8796 * that the plane may generate whilst we perform load detection.
8797 * We can not rely on the fbcon either being present (we get called
8798 * during its initialisation to detect all boot displays, or it may
8799 * not even exist) or that it is large enough to satisfy the
8802 fb
= mode_fits_in_fbdev(dev
, mode
);
8804 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8805 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8806 old
->release_fb
= fb
;
8808 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8810 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8814 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8815 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8816 if (old
->release_fb
)
8817 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8821 /* let the connector get through one full cycle before testing */
8822 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8826 intel_crtc
->new_enabled
= crtc
->enabled
;
8827 if (intel_crtc
->new_enabled
)
8828 intel_crtc
->new_config
= &intel_crtc
->config
;
8830 intel_crtc
->new_config
= NULL
;
8832 if (ret
== -EDEADLK
) {
8833 drm_modeset_backoff(ctx
);
8840 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8841 struct intel_load_detect_pipe
*old
)
8843 struct intel_encoder
*intel_encoder
=
8844 intel_attached_encoder(connector
);
8845 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8846 struct drm_crtc
*crtc
= encoder
->crtc
;
8847 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8850 connector
->base
.id
, connector
->name
,
8851 encoder
->base
.id
, encoder
->name
);
8853 if (old
->load_detect_temp
) {
8854 to_intel_connector(connector
)->new_encoder
= NULL
;
8855 intel_encoder
->new_crtc
= NULL
;
8856 intel_crtc
->new_enabled
= false;
8857 intel_crtc
->new_config
= NULL
;
8858 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8860 if (old
->release_fb
) {
8861 drm_framebuffer_unregister_private(old
->release_fb
);
8862 drm_framebuffer_unreference(old
->release_fb
);
8868 /* Switch crtc and encoder back off if necessary */
8869 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8870 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8873 static int i9xx_pll_refclk(struct drm_device
*dev
,
8874 const struct intel_crtc_config
*pipe_config
)
8876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8877 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8879 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8880 return dev_priv
->vbt
.lvds_ssc_freq
;
8881 else if (HAS_PCH_SPLIT(dev
))
8883 else if (!IS_GEN2(dev
))
8889 /* Returns the clock of the currently programmed mode of the given pipe. */
8890 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8891 struct intel_crtc_config
*pipe_config
)
8893 struct drm_device
*dev
= crtc
->base
.dev
;
8894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8895 int pipe
= pipe_config
->cpu_transcoder
;
8896 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8898 intel_clock_t clock
;
8899 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8901 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8902 fp
= pipe_config
->dpll_hw_state
.fp0
;
8904 fp
= pipe_config
->dpll_hw_state
.fp1
;
8906 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8907 if (IS_PINEVIEW(dev
)) {
8908 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8909 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8911 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8912 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8915 if (!IS_GEN2(dev
)) {
8916 if (IS_PINEVIEW(dev
))
8917 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8918 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8920 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8921 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8923 switch (dpll
& DPLL_MODE_MASK
) {
8924 case DPLLB_MODE_DAC_SERIAL
:
8925 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8928 case DPLLB_MODE_LVDS
:
8929 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8933 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8934 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8938 if (IS_PINEVIEW(dev
))
8939 pineview_clock(refclk
, &clock
);
8941 i9xx_clock(refclk
, &clock
);
8943 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8944 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8947 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8948 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8950 if (lvds
& LVDS_CLKB_POWER_UP
)
8955 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8958 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8959 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8961 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8967 i9xx_clock(refclk
, &clock
);
8971 * This value includes pixel_multiplier. We will use
8972 * port_clock to compute adjusted_mode.crtc_clock in the
8973 * encoder's get_config() function.
8975 pipe_config
->port_clock
= clock
.dot
;
8978 int intel_dotclock_calculate(int link_freq
,
8979 const struct intel_link_m_n
*m_n
)
8982 * The calculation for the data clock is:
8983 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8984 * But we want to avoid losing precison if possible, so:
8985 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8987 * and the link clock is simpler:
8988 * link_clock = (m * link_clock) / n
8994 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8997 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8998 struct intel_crtc_config
*pipe_config
)
9000 struct drm_device
*dev
= crtc
->base
.dev
;
9002 /* read out port_clock from the DPLL */
9003 i9xx_crtc_clock_get(crtc
, pipe_config
);
9006 * This value does not include pixel_multiplier.
9007 * We will check that port_clock and adjusted_mode.crtc_clock
9008 * agree once we know their relationship in the encoder's
9009 * get_config() function.
9011 pipe_config
->adjusted_mode
.crtc_clock
=
9012 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
9013 &pipe_config
->fdi_m_n
);
9016 /** Returns the currently programmed mode of the given pipe. */
9017 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
9018 struct drm_crtc
*crtc
)
9020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9021 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9022 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
9023 struct drm_display_mode
*mode
;
9024 struct intel_crtc_config pipe_config
;
9025 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
9026 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
9027 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
9028 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
9029 enum pipe pipe
= intel_crtc
->pipe
;
9031 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
9036 * Construct a pipe_config sufficient for getting the clock info
9037 * back out of crtc_clock_get.
9039 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9040 * to use a real value here instead.
9042 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
9043 pipe_config
.pixel_multiplier
= 1;
9044 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
9045 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
9046 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
9047 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
9049 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
9050 mode
->hdisplay
= (htot
& 0xffff) + 1;
9051 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
9052 mode
->hsync_start
= (hsync
& 0xffff) + 1;
9053 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9054 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9055 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9056 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9057 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9059 drm_mode_set_name(mode
);
9064 static void intel_increase_pllclock(struct drm_device
*dev
,
9067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9068 int dpll_reg
= DPLL(pipe
);
9071 if (!HAS_GMCH_DISPLAY(dev
))
9074 if (!dev_priv
->lvds_downclock_avail
)
9077 dpll
= I915_READ(dpll_reg
);
9078 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
9079 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9081 assert_panel_unlocked(dev_priv
, pipe
);
9083 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
9084 I915_WRITE(dpll_reg
, dpll
);
9085 intel_wait_for_vblank(dev
, pipe
);
9087 dpll
= I915_READ(dpll_reg
);
9088 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
9089 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9093 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9095 struct drm_device
*dev
= crtc
->dev
;
9096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9097 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9099 if (!HAS_GMCH_DISPLAY(dev
))
9102 if (!dev_priv
->lvds_downclock_avail
)
9106 * Since this is called by a timer, we should never get here in
9109 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9110 int pipe
= intel_crtc
->pipe
;
9111 int dpll_reg
= DPLL(pipe
);
9114 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9116 assert_panel_unlocked(dev_priv
, pipe
);
9118 dpll
= I915_READ(dpll_reg
);
9119 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9120 I915_WRITE(dpll_reg
, dpll
);
9121 intel_wait_for_vblank(dev
, pipe
);
9122 dpll
= I915_READ(dpll_reg
);
9123 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9124 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9129 void intel_mark_busy(struct drm_device
*dev
)
9131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9133 if (dev_priv
->mm
.busy
)
9136 intel_runtime_pm_get(dev_priv
);
9137 i915_update_gfx_val(dev_priv
);
9138 dev_priv
->mm
.busy
= true;
9141 void intel_mark_idle(struct drm_device
*dev
)
9143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9144 struct drm_crtc
*crtc
;
9146 if (!dev_priv
->mm
.busy
)
9149 dev_priv
->mm
.busy
= false;
9151 if (!i915
.powersave
)
9154 for_each_crtc(dev
, crtc
) {
9155 if (!crtc
->primary
->fb
)
9158 intel_decrease_pllclock(crtc
);
9161 if (INTEL_INFO(dev
)->gen
>= 6)
9162 gen6_rps_idle(dev
->dev_private
);
9165 intel_runtime_pm_put(dev_priv
);
9170 * intel_mark_fb_busy - mark given planes as busy
9172 * @frontbuffer_bits: bits for the affected planes
9173 * @ring: optional ring for asynchronous commands
9175 * This function gets called every time the screen contents change. It can be
9176 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9178 static void intel_mark_fb_busy(struct drm_device
*dev
,
9179 unsigned frontbuffer_bits
,
9180 struct intel_engine_cs
*ring
)
9182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9185 if (!i915
.powersave
)
9188 for_each_pipe(dev_priv
, pipe
) {
9189 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9192 intel_increase_pllclock(dev
, pipe
);
9193 if (ring
&& intel_fbc_enabled(dev
))
9194 ring
->fbc_dirty
= true;
9199 * intel_fb_obj_invalidate - invalidate frontbuffer object
9200 * @obj: GEM object to invalidate
9201 * @ring: set for asynchronous rendering
9203 * This function gets called every time rendering on the given object starts and
9204 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9205 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9206 * until the rendering completes or a flip on this frontbuffer plane is
9209 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9210 struct intel_engine_cs
*ring
)
9212 struct drm_device
*dev
= obj
->base
.dev
;
9213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9215 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9217 if (!obj
->frontbuffer_bits
)
9221 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9222 dev_priv
->fb_tracking
.busy_bits
9223 |= obj
->frontbuffer_bits
;
9224 dev_priv
->fb_tracking
.flip_bits
9225 &= ~obj
->frontbuffer_bits
;
9226 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9229 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9231 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9235 * intel_frontbuffer_flush - flush frontbuffer
9237 * @frontbuffer_bits: frontbuffer plane tracking bits
9239 * This function gets called every time rendering on the given planes has
9240 * completed and frontbuffer caching can be started again. Flushes will get
9241 * delayed if they're blocked by some oustanding asynchronous rendering.
9243 * Can be called without any locks held.
9245 void intel_frontbuffer_flush(struct drm_device
*dev
,
9246 unsigned frontbuffer_bits
)
9248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9250 /* Delay flushing when rings are still busy.*/
9251 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9252 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9253 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9255 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9257 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9260 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9261 * needs to be reworked into a proper frontbuffer tracking scheme like
9264 if (IS_BROADWELL(dev
))
9265 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9269 * intel_fb_obj_flush - flush frontbuffer object
9270 * @obj: GEM object to flush
9271 * @retire: set when retiring asynchronous rendering
9273 * This function gets called every time rendering on the given object has
9274 * completed and frontbuffer caching can be started again. If @retire is true
9275 * then any delayed flushes will be unblocked.
9277 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9280 struct drm_device
*dev
= obj
->base
.dev
;
9281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9282 unsigned frontbuffer_bits
;
9284 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9286 if (!obj
->frontbuffer_bits
)
9289 frontbuffer_bits
= obj
->frontbuffer_bits
;
9292 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9293 /* Filter out new bits since rendering started. */
9294 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9296 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9297 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9300 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9304 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9306 * @frontbuffer_bits: frontbuffer plane tracking bits
9308 * This function gets called after scheduling a flip on @obj. The actual
9309 * frontbuffer flushing will be delayed until completion is signalled with
9310 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9311 * flush will be cancelled.
9313 * Can be called without any locks held.
9315 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9316 unsigned frontbuffer_bits
)
9318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9320 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9321 dev_priv
->fb_tracking
.flip_bits
9322 |= frontbuffer_bits
;
9323 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9327 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9329 * @frontbuffer_bits: frontbuffer plane tracking bits
9331 * This function gets called after the flip has been latched and will complete
9332 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9334 * Can be called without any locks held.
9336 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9337 unsigned frontbuffer_bits
)
9339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9341 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9342 /* Mask any cancelled flips. */
9343 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9344 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9345 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9347 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9350 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9352 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9353 struct drm_device
*dev
= crtc
->dev
;
9354 struct intel_unpin_work
*work
;
9355 unsigned long flags
;
9357 spin_lock_irqsave(&dev
->event_lock
, flags
);
9358 work
= intel_crtc
->unpin_work
;
9359 intel_crtc
->unpin_work
= NULL
;
9360 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9363 cancel_work_sync(&work
->work
);
9367 drm_crtc_cleanup(crtc
);
9372 static void intel_unpin_work_fn(struct work_struct
*__work
)
9374 struct intel_unpin_work
*work
=
9375 container_of(__work
, struct intel_unpin_work
, work
);
9376 struct drm_device
*dev
= work
->crtc
->dev
;
9377 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9379 mutex_lock(&dev
->struct_mutex
);
9380 intel_unpin_fb_obj(work
->old_fb_obj
);
9381 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9382 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9384 intel_update_fbc(dev
);
9385 mutex_unlock(&dev
->struct_mutex
);
9387 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9389 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9390 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9395 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9396 struct drm_crtc
*crtc
)
9398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9399 struct intel_unpin_work
*work
;
9400 unsigned long flags
;
9402 /* Ignore early vblank irqs */
9403 if (intel_crtc
== NULL
)
9406 spin_lock_irqsave(&dev
->event_lock
, flags
);
9407 work
= intel_crtc
->unpin_work
;
9409 /* Ensure we don't miss a work->pending update ... */
9412 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9413 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9417 page_flip_completed(intel_crtc
);
9419 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9422 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9425 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9427 do_intel_finish_page_flip(dev
, crtc
);
9430 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9433 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9435 do_intel_finish_page_flip(dev
, crtc
);
9438 /* Is 'a' after or equal to 'b'? */
9439 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9441 return !((a
- b
) & 0x80000000);
9444 static bool page_flip_finished(struct intel_crtc
*crtc
)
9446 struct drm_device
*dev
= crtc
->base
.dev
;
9447 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9450 * The relevant registers doen't exist on pre-ctg.
9451 * As the flip done interrupt doesn't trigger for mmio
9452 * flips on gmch platforms, a flip count check isn't
9453 * really needed there. But since ctg has the registers,
9454 * include it in the check anyway.
9456 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9460 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9461 * used the same base address. In that case the mmio flip might
9462 * have completed, but the CS hasn't even executed the flip yet.
9464 * A flip count check isn't enough as the CS might have updated
9465 * the base address just after start of vblank, but before we
9466 * managed to process the interrupt. This means we'd complete the
9469 * Combining both checks should get us a good enough result. It may
9470 * still happen that the CS flip has been executed, but has not
9471 * yet actually completed. But in case the base address is the same
9472 * anyway, we don't really care.
9474 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9475 crtc
->unpin_work
->gtt_offset
&&
9476 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9477 crtc
->unpin_work
->flip_count
);
9480 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9483 struct intel_crtc
*intel_crtc
=
9484 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9485 unsigned long flags
;
9487 /* NB: An MMIO update of the plane base pointer will also
9488 * generate a page-flip completion irq, i.e. every modeset
9489 * is also accompanied by a spurious intel_prepare_page_flip().
9491 spin_lock_irqsave(&dev
->event_lock
, flags
);
9492 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9493 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9494 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9497 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9499 /* Ensure that the work item is consistent when activating it ... */
9501 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9502 /* and that it is marked active as soon as the irq could fire. */
9506 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9507 struct drm_crtc
*crtc
,
9508 struct drm_framebuffer
*fb
,
9509 struct drm_i915_gem_object
*obj
,
9510 struct intel_engine_cs
*ring
,
9513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9517 ret
= intel_ring_begin(ring
, 6);
9521 /* Can't queue multiple flips, so wait for the previous
9522 * one to finish before executing the next.
9524 if (intel_crtc
->plane
)
9525 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9527 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9528 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9529 intel_ring_emit(ring
, MI_NOOP
);
9530 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9531 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9532 intel_ring_emit(ring
, fb
->pitches
[0]);
9533 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9534 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9536 intel_mark_page_flip_active(intel_crtc
);
9537 __intel_ring_advance(ring
);
9541 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9542 struct drm_crtc
*crtc
,
9543 struct drm_framebuffer
*fb
,
9544 struct drm_i915_gem_object
*obj
,
9545 struct intel_engine_cs
*ring
,
9548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9552 ret
= intel_ring_begin(ring
, 6);
9556 if (intel_crtc
->plane
)
9557 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9559 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9560 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9561 intel_ring_emit(ring
, MI_NOOP
);
9562 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9563 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9564 intel_ring_emit(ring
, fb
->pitches
[0]);
9565 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9566 intel_ring_emit(ring
, MI_NOOP
);
9568 intel_mark_page_flip_active(intel_crtc
);
9569 __intel_ring_advance(ring
);
9573 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9574 struct drm_crtc
*crtc
,
9575 struct drm_framebuffer
*fb
,
9576 struct drm_i915_gem_object
*obj
,
9577 struct intel_engine_cs
*ring
,
9580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9581 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9582 uint32_t pf
, pipesrc
;
9585 ret
= intel_ring_begin(ring
, 4);
9589 /* i965+ uses the linear or tiled offsets from the
9590 * Display Registers (which do not change across a page-flip)
9591 * so we need only reprogram the base address.
9593 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9594 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9595 intel_ring_emit(ring
, fb
->pitches
[0]);
9596 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9599 /* XXX Enabling the panel-fitter across page-flip is so far
9600 * untested on non-native modes, so ignore it for now.
9601 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9604 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9605 intel_ring_emit(ring
, pf
| pipesrc
);
9607 intel_mark_page_flip_active(intel_crtc
);
9608 __intel_ring_advance(ring
);
9612 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9613 struct drm_crtc
*crtc
,
9614 struct drm_framebuffer
*fb
,
9615 struct drm_i915_gem_object
*obj
,
9616 struct intel_engine_cs
*ring
,
9619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9620 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9621 uint32_t pf
, pipesrc
;
9624 ret
= intel_ring_begin(ring
, 4);
9628 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9629 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9630 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9631 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9633 /* Contrary to the suggestions in the documentation,
9634 * "Enable Panel Fitter" does not seem to be required when page
9635 * flipping with a non-native mode, and worse causes a normal
9637 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9640 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9641 intel_ring_emit(ring
, pf
| pipesrc
);
9643 intel_mark_page_flip_active(intel_crtc
);
9644 __intel_ring_advance(ring
);
9648 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9649 struct drm_crtc
*crtc
,
9650 struct drm_framebuffer
*fb
,
9651 struct drm_i915_gem_object
*obj
,
9652 struct intel_engine_cs
*ring
,
9655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9656 uint32_t plane_bit
= 0;
9659 switch (intel_crtc
->plane
) {
9661 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9664 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9667 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9670 WARN_ONCE(1, "unknown plane in flip command\n");
9675 if (ring
->id
== RCS
) {
9678 * On Gen 8, SRM is now taking an extra dword to accommodate
9679 * 48bits addresses, and we need a NOOP for the batch size to
9687 * BSpec MI_DISPLAY_FLIP for IVB:
9688 * "The full packet must be contained within the same cache line."
9690 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9691 * cacheline, if we ever start emitting more commands before
9692 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9693 * then do the cacheline alignment, and finally emit the
9696 ret
= intel_ring_cacheline_align(ring
);
9700 ret
= intel_ring_begin(ring
, len
);
9704 /* Unmask the flip-done completion message. Note that the bspec says that
9705 * we should do this for both the BCS and RCS, and that we must not unmask
9706 * more than one flip event at any time (or ensure that one flip message
9707 * can be sent by waiting for flip-done prior to queueing new flips).
9708 * Experimentation says that BCS works despite DERRMR masking all
9709 * flip-done completion events and that unmasking all planes at once
9710 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9711 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9713 if (ring
->id
== RCS
) {
9714 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9715 intel_ring_emit(ring
, DERRMR
);
9716 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9717 DERRMR_PIPEB_PRI_FLIP_DONE
|
9718 DERRMR_PIPEC_PRI_FLIP_DONE
));
9720 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9721 MI_SRM_LRM_GLOBAL_GTT
);
9723 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9724 MI_SRM_LRM_GLOBAL_GTT
);
9725 intel_ring_emit(ring
, DERRMR
);
9726 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9728 intel_ring_emit(ring
, 0);
9729 intel_ring_emit(ring
, MI_NOOP
);
9733 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9734 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9735 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9736 intel_ring_emit(ring
, (MI_NOOP
));
9738 intel_mark_page_flip_active(intel_crtc
);
9739 __intel_ring_advance(ring
);
9743 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9744 struct drm_i915_gem_object
*obj
)
9747 * This is not being used for older platforms, because
9748 * non-availability of flip done interrupt forces us to use
9749 * CS flips. Older platforms derive flip done using some clever
9750 * tricks involving the flip_pending status bits and vblank irqs.
9751 * So using MMIO flips there would disrupt this mechanism.
9757 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9760 if (i915
.use_mmio_flip
< 0)
9762 else if (i915
.use_mmio_flip
> 0)
9764 else if (i915
.enable_execlists
)
9767 return ring
!= obj
->ring
;
9770 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9772 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9774 struct intel_framebuffer
*intel_fb
=
9775 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9776 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9780 intel_mark_page_flip_active(intel_crtc
);
9782 reg
= DSPCNTR(intel_crtc
->plane
);
9783 dspcntr
= I915_READ(reg
);
9785 if (INTEL_INFO(dev
)->gen
>= 4) {
9786 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9787 dspcntr
|= DISPPLANE_TILED
;
9789 dspcntr
&= ~DISPPLANE_TILED
;
9791 I915_WRITE(reg
, dspcntr
);
9793 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9794 intel_crtc
->unpin_work
->gtt_offset
);
9795 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9798 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9800 struct intel_engine_cs
*ring
;
9803 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9805 if (!obj
->last_write_seqno
)
9810 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9811 obj
->last_write_seqno
))
9814 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9818 if (WARN_ON(!ring
->irq_get(ring
)))
9824 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9826 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9827 struct intel_crtc
*intel_crtc
;
9828 unsigned long irq_flags
;
9831 seqno
= ring
->get_seqno(ring
, false);
9833 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9834 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9835 struct intel_mmio_flip
*mmio_flip
;
9837 mmio_flip
= &intel_crtc
->mmio_flip
;
9838 if (mmio_flip
->seqno
== 0)
9841 if (ring
->id
!= mmio_flip
->ring_id
)
9844 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9845 intel_do_mmio_flip(intel_crtc
);
9846 mmio_flip
->seqno
= 0;
9847 ring
->irq_put(ring
);
9850 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9853 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9854 struct drm_crtc
*crtc
,
9855 struct drm_framebuffer
*fb
,
9856 struct drm_i915_gem_object
*obj
,
9857 struct intel_engine_cs
*ring
,
9860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9861 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9862 unsigned long irq_flags
;
9865 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9868 ret
= intel_postpone_flip(obj
);
9872 intel_do_mmio_flip(intel_crtc
);
9876 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9877 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9878 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9879 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9882 * Double check to catch cases where irq fired before
9883 * mmio flip data was ready
9885 intel_notify_mmio_flip(obj
->ring
);
9889 static int intel_default_queue_flip(struct drm_device
*dev
,
9890 struct drm_crtc
*crtc
,
9891 struct drm_framebuffer
*fb
,
9892 struct drm_i915_gem_object
*obj
,
9893 struct intel_engine_cs
*ring
,
9899 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9900 struct drm_crtc
*crtc
)
9902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9903 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9904 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9907 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9910 if (!work
->enable_stall_check
)
9913 if (work
->flip_ready_vblank
== 0) {
9914 if (work
->flip_queued_ring
&&
9915 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9916 work
->flip_queued_seqno
))
9919 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9922 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9925 /* Potential stall - if we see that the flip has happened,
9926 * assume a missed interrupt. */
9927 if (INTEL_INFO(dev
)->gen
>= 4)
9928 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9930 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9932 /* There is a potential issue here with a false positive after a flip
9933 * to the same address. We could address this by checking for a
9934 * non-incrementing frame counter.
9936 return addr
== work
->gtt_offset
;
9939 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9942 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9944 unsigned long flags
;
9949 spin_lock_irqsave(&dev
->event_lock
, flags
);
9950 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9951 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9952 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9953 page_flip_completed(intel_crtc
);
9955 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9958 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9959 struct drm_framebuffer
*fb
,
9960 struct drm_pending_vblank_event
*event
,
9961 uint32_t page_flip_flags
)
9963 struct drm_device
*dev
= crtc
->dev
;
9964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9965 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9966 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9968 enum pipe pipe
= intel_crtc
->pipe
;
9969 struct intel_unpin_work
*work
;
9970 struct intel_engine_cs
*ring
;
9971 unsigned long flags
;
9974 //trigger software GT busyness calculation
9975 gen8_flip_interrupt(dev
);
9978 * drm_mode_page_flip_ioctl() should already catch this, but double
9979 * check to be safe. In the future we may enable pageflipping from
9980 * a disabled primary plane.
9982 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9985 /* Can't change pixel format via MI display flips. */
9986 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9990 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9991 * Note that pitch changes could also affect these register.
9993 if (INTEL_INFO(dev
)->gen
> 3 &&
9994 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9995 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9998 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10001 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10005 work
->event
= event
;
10007 work
->old_fb_obj
= intel_fb_obj(old_fb
);
10008 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10010 ret
= drm_crtc_vblank_get(crtc
);
10014 /* We borrow the event spin lock for protecting unpin_work */
10015 spin_lock_irqsave(&dev
->event_lock
, flags
);
10016 if (intel_crtc
->unpin_work
) {
10017 /* Before declaring the flip queue wedged, check if
10018 * the hardware completed the operation behind our backs.
10020 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10021 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10022 page_flip_completed(intel_crtc
);
10024 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10025 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10027 drm_crtc_vblank_put(crtc
);
10032 intel_crtc
->unpin_work
= work
;
10033 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10035 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10036 flush_workqueue(dev_priv
->wq
);
10038 ret
= i915_mutex_lock_interruptible(dev
);
10042 /* Reference the objects for the scheduled work. */
10043 drm_gem_object_reference(&work
->old_fb_obj
->base
);
10044 drm_gem_object_reference(&obj
->base
);
10046 crtc
->primary
->fb
= fb
;
10048 work
->pending_flip_obj
= obj
;
10050 atomic_inc(&intel_crtc
->unpin_work_count
);
10051 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10053 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10054 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10056 if (IS_VALLEYVIEW(dev
)) {
10057 ring
= &dev_priv
->ring
[BCS
];
10058 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
10059 /* vlv: DISPLAY_FLIP fails to change tiling */
10061 } else if (IS_IVYBRIDGE(dev
)) {
10062 ring
= &dev_priv
->ring
[BCS
];
10063 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10065 if (ring
== NULL
|| ring
->id
!= RCS
)
10066 ring
= &dev_priv
->ring
[BCS
];
10068 ring
= &dev_priv
->ring
[RCS
];
10071 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
10073 goto cleanup_pending
;
10076 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
10078 if (use_mmio_flip(ring
, obj
)) {
10079 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10082 goto cleanup_unpin
;
10084 work
->flip_queued_seqno
= obj
->last_write_seqno
;
10085 work
->flip_queued_ring
= obj
->ring
;
10087 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10090 goto cleanup_unpin
;
10092 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
10093 work
->flip_queued_ring
= ring
;
10096 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
10097 work
->enable_stall_check
= true;
10099 i915_gem_track_fb(work
->old_fb_obj
, obj
,
10100 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10102 intel_disable_fbc(dev
);
10103 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10104 mutex_unlock(&dev
->struct_mutex
);
10106 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10111 intel_unpin_fb_obj(obj
);
10113 atomic_dec(&intel_crtc
->unpin_work_count
);
10114 crtc
->primary
->fb
= old_fb
;
10115 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
10116 drm_gem_object_unreference(&obj
->base
);
10117 mutex_unlock(&dev
->struct_mutex
);
10120 spin_lock_irqsave(&dev
->event_lock
, flags
);
10121 intel_crtc
->unpin_work
= NULL
;
10122 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10124 drm_crtc_vblank_put(crtc
);
10130 intel_crtc_wait_for_pending_flips(crtc
);
10131 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
10132 if (ret
== 0 && event
)
10133 drm_send_vblank_event(dev
, pipe
, event
);
10138 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10139 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10140 .load_lut
= intel_crtc_load_lut
,
10144 * intel_modeset_update_staged_output_state
10146 * Updates the staged output configuration state, e.g. after we've read out the
10147 * current hw state.
10149 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10151 struct intel_crtc
*crtc
;
10152 struct intel_encoder
*encoder
;
10153 struct intel_connector
*connector
;
10155 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10157 connector
->new_encoder
=
10158 to_intel_encoder(connector
->base
.encoder
);
10161 for_each_intel_encoder(dev
, encoder
) {
10162 encoder
->new_crtc
=
10163 to_intel_crtc(encoder
->base
.crtc
);
10166 for_each_intel_crtc(dev
, crtc
) {
10167 crtc
->new_enabled
= crtc
->base
.enabled
;
10169 if (crtc
->new_enabled
)
10170 crtc
->new_config
= &crtc
->config
;
10172 crtc
->new_config
= NULL
;
10177 * intel_modeset_commit_output_state
10179 * This function copies the stage display pipe configuration to the real one.
10181 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10183 struct intel_crtc
*crtc
;
10184 struct intel_encoder
*encoder
;
10185 struct intel_connector
*connector
;
10187 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10189 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10192 for_each_intel_encoder(dev
, encoder
) {
10193 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10196 for_each_intel_crtc(dev
, crtc
) {
10197 crtc
->base
.enabled
= crtc
->new_enabled
;
10202 connected_sink_compute_bpp(struct intel_connector
*connector
,
10203 struct intel_crtc_config
*pipe_config
)
10205 int bpp
= pipe_config
->pipe_bpp
;
10207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10208 connector
->base
.base
.id
,
10209 connector
->base
.name
);
10211 /* Don't use an invalid EDID bpc value */
10212 if (connector
->base
.display_info
.bpc
&&
10213 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10214 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10215 bpp
, connector
->base
.display_info
.bpc
*3);
10216 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10219 /* Clamp bpp to 8 on screens without EDID 1.4 */
10220 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10221 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10223 pipe_config
->pipe_bpp
= 24;
10228 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10229 struct drm_framebuffer
*fb
,
10230 struct intel_crtc_config
*pipe_config
)
10232 struct drm_device
*dev
= crtc
->base
.dev
;
10233 struct intel_connector
*connector
;
10236 switch (fb
->pixel_format
) {
10237 case DRM_FORMAT_C8
:
10238 bpp
= 8*3; /* since we go through a colormap */
10240 case DRM_FORMAT_XRGB1555
:
10241 case DRM_FORMAT_ARGB1555
:
10242 /* checked in intel_framebuffer_init already */
10243 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10245 case DRM_FORMAT_RGB565
:
10246 bpp
= 6*3; /* min is 18bpp */
10248 case DRM_FORMAT_XBGR8888
:
10249 case DRM_FORMAT_ABGR8888
:
10250 /* checked in intel_framebuffer_init already */
10251 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10253 case DRM_FORMAT_XRGB8888
:
10254 case DRM_FORMAT_ARGB8888
:
10257 case DRM_FORMAT_XRGB2101010
:
10258 case DRM_FORMAT_ARGB2101010
:
10259 case DRM_FORMAT_XBGR2101010
:
10260 case DRM_FORMAT_ABGR2101010
:
10261 /* checked in intel_framebuffer_init already */
10262 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10266 /* TODO: gen4+ supports 16 bpc floating point, too. */
10268 DRM_DEBUG_KMS("unsupported depth\n");
10272 pipe_config
->pipe_bpp
= bpp
;
10274 /* Clamp display bpp to EDID value */
10275 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10277 if (!connector
->new_encoder
||
10278 connector
->new_encoder
->new_crtc
!= crtc
)
10281 connected_sink_compute_bpp(connector
, pipe_config
);
10287 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10289 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10290 "type: 0x%x flags: 0x%x\n",
10292 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10293 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10294 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10295 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10298 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10299 struct intel_crtc_config
*pipe_config
,
10300 const char *context
)
10302 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10303 context
, pipe_name(crtc
->pipe
));
10305 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10306 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10307 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10308 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10309 pipe_config
->has_pch_encoder
,
10310 pipe_config
->fdi_lanes
,
10311 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10312 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10313 pipe_config
->fdi_m_n
.tu
);
10314 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10315 pipe_config
->has_dp_encoder
,
10316 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10317 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10318 pipe_config
->dp_m_n
.tu
);
10320 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10321 pipe_config
->has_dp_encoder
,
10322 pipe_config
->dp_m2_n2
.gmch_m
,
10323 pipe_config
->dp_m2_n2
.gmch_n
,
10324 pipe_config
->dp_m2_n2
.link_m
,
10325 pipe_config
->dp_m2_n2
.link_n
,
10326 pipe_config
->dp_m2_n2
.tu
);
10328 DRM_DEBUG_KMS("requested mode:\n");
10329 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10330 DRM_DEBUG_KMS("adjusted mode:\n");
10331 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10332 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10333 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10334 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10335 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10336 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10337 pipe_config
->gmch_pfit
.control
,
10338 pipe_config
->gmch_pfit
.pgm_ratios
,
10339 pipe_config
->gmch_pfit
.lvds_border_bits
);
10340 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10341 pipe_config
->pch_pfit
.pos
,
10342 pipe_config
->pch_pfit
.size
,
10343 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10344 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10345 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10348 static bool encoders_cloneable(const struct intel_encoder
*a
,
10349 const struct intel_encoder
*b
)
10351 /* masks could be asymmetric, so check both ways */
10352 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10353 b
->cloneable
& (1 << a
->type
));
10356 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10357 struct intel_encoder
*encoder
)
10359 struct drm_device
*dev
= crtc
->base
.dev
;
10360 struct intel_encoder
*source_encoder
;
10362 for_each_intel_encoder(dev
, source_encoder
) {
10363 if (source_encoder
->new_crtc
!= crtc
)
10366 if (!encoders_cloneable(encoder
, source_encoder
))
10373 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10375 struct drm_device
*dev
= crtc
->base
.dev
;
10376 struct intel_encoder
*encoder
;
10378 for_each_intel_encoder(dev
, encoder
) {
10379 if (encoder
->new_crtc
!= crtc
)
10382 if (!check_single_encoder_cloning(crtc
, encoder
))
10389 static struct intel_crtc_config
*
10390 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10391 struct drm_framebuffer
*fb
,
10392 struct drm_display_mode
*mode
)
10394 struct drm_device
*dev
= crtc
->dev
;
10395 struct intel_encoder
*encoder
;
10396 struct intel_crtc_config
*pipe_config
;
10397 int plane_bpp
, ret
= -EINVAL
;
10400 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10401 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10402 return ERR_PTR(-EINVAL
);
10405 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10407 return ERR_PTR(-ENOMEM
);
10409 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10410 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10412 pipe_config
->cpu_transcoder
=
10413 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10414 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10417 * Sanitize sync polarity flags based on requested ones. If neither
10418 * positive or negative polarity is requested, treat this as meaning
10419 * negative polarity.
10421 if (!(pipe_config
->adjusted_mode
.flags
&
10422 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10423 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10425 if (!(pipe_config
->adjusted_mode
.flags
&
10426 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10427 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10429 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10430 * plane pixel format and any sink constraints into account. Returns the
10431 * source plane bpp so that dithering can be selected on mismatches
10432 * after encoders and crtc also have had their say. */
10433 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10439 * Determine the real pipe dimensions. Note that stereo modes can
10440 * increase the actual pipe size due to the frame doubling and
10441 * insertion of additional space for blanks between the frame. This
10442 * is stored in the crtc timings. We use the requested mode to do this
10443 * computation to clearly distinguish it from the adjusted mode, which
10444 * can be changed by the connectors in the below retry loop.
10446 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10447 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10448 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10451 /* Ensure the port clock defaults are reset when retrying. */
10452 pipe_config
->port_clock
= 0;
10453 pipe_config
->pixel_multiplier
= 1;
10455 /* Fill in default crtc timings, allow encoders to overwrite them. */
10456 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10458 /* Pass our mode to the connectors and the CRTC to give them a chance to
10459 * adjust it according to limitations or connector properties, and also
10460 * a chance to reject the mode entirely.
10462 for_each_intel_encoder(dev
, encoder
) {
10464 if (&encoder
->new_crtc
->base
!= crtc
)
10467 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10468 DRM_DEBUG_KMS("Encoder config failure\n");
10473 /* Set default port clock if not overwritten by the encoder. Needs to be
10474 * done afterwards in case the encoder adjusts the mode. */
10475 if (!pipe_config
->port_clock
)
10476 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10477 * pipe_config
->pixel_multiplier
;
10479 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10481 DRM_DEBUG_KMS("CRTC fixup failed\n");
10485 if (ret
== RETRY
) {
10486 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10491 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10493 goto encoder_retry
;
10496 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10497 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10498 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10500 return pipe_config
;
10502 kfree(pipe_config
);
10503 return ERR_PTR(ret
);
10506 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10507 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10509 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10510 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10512 struct intel_crtc
*intel_crtc
;
10513 struct drm_device
*dev
= crtc
->dev
;
10514 struct intel_encoder
*encoder
;
10515 struct intel_connector
*connector
;
10516 struct drm_crtc
*tmp_crtc
;
10518 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10520 /* Check which crtcs have changed outputs connected to them, these need
10521 * to be part of the prepare_pipes mask. We don't (yet) support global
10522 * modeset across multiple crtcs, so modeset_pipes will only have one
10523 * bit set at most. */
10524 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10526 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10529 if (connector
->base
.encoder
) {
10530 tmp_crtc
= connector
->base
.encoder
->crtc
;
10532 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10535 if (connector
->new_encoder
)
10537 1 << connector
->new_encoder
->new_crtc
->pipe
;
10540 for_each_intel_encoder(dev
, encoder
) {
10541 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10544 if (encoder
->base
.crtc
) {
10545 tmp_crtc
= encoder
->base
.crtc
;
10547 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10550 if (encoder
->new_crtc
)
10551 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10554 /* Check for pipes that will be enabled/disabled ... */
10555 for_each_intel_crtc(dev
, intel_crtc
) {
10556 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10559 if (!intel_crtc
->new_enabled
)
10560 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10562 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10566 /* set_mode is also used to update properties on life display pipes. */
10567 intel_crtc
= to_intel_crtc(crtc
);
10568 if (intel_crtc
->new_enabled
)
10569 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10572 * For simplicity do a full modeset on any pipe where the output routing
10573 * changed. We could be more clever, but that would require us to be
10574 * more careful with calling the relevant encoder->mode_set functions.
10576 if (*prepare_pipes
)
10577 *modeset_pipes
= *prepare_pipes
;
10579 /* ... and mask these out. */
10580 *modeset_pipes
&= ~(*disable_pipes
);
10581 *prepare_pipes
&= ~(*disable_pipes
);
10584 * HACK: We don't (yet) fully support global modesets. intel_set_config
10585 * obies this rule, but the modeset restore mode of
10586 * intel_modeset_setup_hw_state does not.
10588 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10589 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10591 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10592 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10595 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10597 struct drm_encoder
*encoder
;
10598 struct drm_device
*dev
= crtc
->dev
;
10600 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10601 if (encoder
->crtc
== crtc
)
10608 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10610 struct intel_encoder
*intel_encoder
;
10611 struct intel_crtc
*intel_crtc
;
10612 struct drm_connector
*connector
;
10614 for_each_intel_encoder(dev
, intel_encoder
) {
10615 if (!intel_encoder
->base
.crtc
)
10618 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10620 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10621 intel_encoder
->connectors_active
= false;
10624 intel_modeset_commit_output_state(dev
);
10626 /* Double check state. */
10627 for_each_intel_crtc(dev
, intel_crtc
) {
10628 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10629 WARN_ON(intel_crtc
->new_config
&&
10630 intel_crtc
->new_config
!= &intel_crtc
->config
);
10631 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10634 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10635 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10638 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10640 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10641 struct drm_property
*dpms_property
=
10642 dev
->mode_config
.dpms_property
;
10644 connector
->dpms
= DRM_MODE_DPMS_ON
;
10645 drm_object_property_set_value(&connector
->base
,
10649 intel_encoder
= to_intel_encoder(connector
->encoder
);
10650 intel_encoder
->connectors_active
= true;
10656 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10660 if (clock1
== clock2
)
10663 if (!clock1
|| !clock2
)
10666 diff
= abs(clock1
- clock2
);
10668 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10674 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10675 list_for_each_entry((intel_crtc), \
10676 &(dev)->mode_config.crtc_list, \
10678 if (mask & (1 <<(intel_crtc)->pipe))
10681 intel_pipe_config_compare(struct drm_device
*dev
,
10682 struct intel_crtc_config
*current_config
,
10683 struct intel_crtc_config
*pipe_config
)
10685 #define PIPE_CONF_CHECK_X(name) \
10686 if (current_config->name != pipe_config->name) { \
10687 DRM_ERROR("mismatch in " #name " " \
10688 "(expected 0x%08x, found 0x%08x)\n", \
10689 current_config->name, \
10690 pipe_config->name); \
10694 #define PIPE_CONF_CHECK_I(name) \
10695 if (current_config->name != pipe_config->name) { \
10696 DRM_ERROR("mismatch in " #name " " \
10697 "(expected %i, found %i)\n", \
10698 current_config->name, \
10699 pipe_config->name); \
10703 /* This is required for BDW+ where there is only one set of registers for
10704 * switching between high and low RR.
10705 * This macro can be used whenever a comparison has to be made between one
10706 * hw state and multiple sw state variables.
10708 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10709 if ((current_config->name != pipe_config->name) && \
10710 (current_config->alt_name != pipe_config->name)) { \
10711 DRM_ERROR("mismatch in " #name " " \
10712 "(expected %i or %i, found %i)\n", \
10713 current_config->name, \
10714 current_config->alt_name, \
10715 pipe_config->name); \
10719 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10720 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10721 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10722 "(expected %i, found %i)\n", \
10723 current_config->name & (mask), \
10724 pipe_config->name & (mask)); \
10728 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10729 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10730 DRM_ERROR("mismatch in " #name " " \
10731 "(expected %i, found %i)\n", \
10732 current_config->name, \
10733 pipe_config->name); \
10737 #define PIPE_CONF_QUIRK(quirk) \
10738 ((current_config->quirks | pipe_config->quirks) & (quirk))
10740 PIPE_CONF_CHECK_I(cpu_transcoder
);
10742 PIPE_CONF_CHECK_I(has_pch_encoder
);
10743 PIPE_CONF_CHECK_I(fdi_lanes
);
10744 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10745 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10746 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10747 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10748 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10750 PIPE_CONF_CHECK_I(has_dp_encoder
);
10752 if (INTEL_INFO(dev
)->gen
< 8) {
10753 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10754 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10755 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10756 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10757 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10759 if (current_config
->has_drrs
) {
10760 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10761 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10762 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10763 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10764 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10767 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10768 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10769 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10770 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10771 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10774 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10775 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10776 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10777 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10778 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10779 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10781 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10782 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10783 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10784 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10785 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10786 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10788 PIPE_CONF_CHECK_I(pixel_multiplier
);
10789 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10790 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10791 IS_VALLEYVIEW(dev
))
10792 PIPE_CONF_CHECK_I(limited_color_range
);
10794 PIPE_CONF_CHECK_I(has_audio
);
10796 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10797 DRM_MODE_FLAG_INTERLACE
);
10799 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10800 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10801 DRM_MODE_FLAG_PHSYNC
);
10802 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10803 DRM_MODE_FLAG_NHSYNC
);
10804 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10805 DRM_MODE_FLAG_PVSYNC
);
10806 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10807 DRM_MODE_FLAG_NVSYNC
);
10810 PIPE_CONF_CHECK_I(pipe_src_w
);
10811 PIPE_CONF_CHECK_I(pipe_src_h
);
10814 * FIXME: BIOS likes to set up a cloned config with lvds+external
10815 * screen. Since we don't yet re-compute the pipe config when moving
10816 * just the lvds port away to another pipe the sw tracking won't match.
10818 * Proper atomic modesets with recomputed global state will fix this.
10819 * Until then just don't check gmch state for inherited modes.
10821 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10822 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10823 /* pfit ratios are autocomputed by the hw on gen4+ */
10824 if (INTEL_INFO(dev
)->gen
< 4)
10825 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10826 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10829 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10830 if (current_config
->pch_pfit
.enabled
) {
10831 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10832 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10835 /* BDW+ don't expose a synchronous way to read the state */
10836 if (IS_HASWELL(dev
))
10837 PIPE_CONF_CHECK_I(ips_enabled
);
10839 PIPE_CONF_CHECK_I(double_wide
);
10841 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10843 PIPE_CONF_CHECK_I(shared_dpll
);
10844 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10845 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10846 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10847 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10848 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10850 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10851 PIPE_CONF_CHECK_I(pipe_bpp
);
10853 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10854 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10856 #undef PIPE_CONF_CHECK_X
10857 #undef PIPE_CONF_CHECK_I
10858 #undef PIPE_CONF_CHECK_I_ALT
10859 #undef PIPE_CONF_CHECK_FLAGS
10860 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10861 #undef PIPE_CONF_QUIRK
10867 check_connector_state(struct drm_device
*dev
)
10869 struct intel_connector
*connector
;
10871 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10873 /* This also checks the encoder/connector hw state with the
10874 * ->get_hw_state callbacks. */
10875 intel_connector_check_state(connector
);
10877 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10878 "connector's staged encoder doesn't match current encoder\n");
10883 check_encoder_state(struct drm_device
*dev
)
10885 struct intel_encoder
*encoder
;
10886 struct intel_connector
*connector
;
10888 for_each_intel_encoder(dev
, encoder
) {
10889 bool enabled
= false;
10890 bool active
= false;
10891 enum pipe pipe
, tracked_pipe
;
10893 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10894 encoder
->base
.base
.id
,
10895 encoder
->base
.name
);
10897 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10898 "encoder's stage crtc doesn't match current crtc\n");
10899 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10900 "encoder's active_connectors set, but no crtc\n");
10902 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10904 if (connector
->base
.encoder
!= &encoder
->base
)
10907 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10911 * for MST connectors if we unplug the connector is gone
10912 * away but the encoder is still connected to a crtc
10913 * until a modeset happens in response to the hotplug.
10915 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10918 WARN(!!encoder
->base
.crtc
!= enabled
,
10919 "encoder's enabled state mismatch "
10920 "(expected %i, found %i)\n",
10921 !!encoder
->base
.crtc
, enabled
);
10922 WARN(active
&& !encoder
->base
.crtc
,
10923 "active encoder with no crtc\n");
10925 WARN(encoder
->connectors_active
!= active
,
10926 "encoder's computed active state doesn't match tracked active state "
10927 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10929 active
= encoder
->get_hw_state(encoder
, &pipe
);
10930 WARN(active
!= encoder
->connectors_active
,
10931 "encoder's hw state doesn't match sw tracking "
10932 "(expected %i, found %i)\n",
10933 encoder
->connectors_active
, active
);
10935 if (!encoder
->base
.crtc
)
10938 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10939 WARN(active
&& pipe
!= tracked_pipe
,
10940 "active encoder's pipe doesn't match"
10941 "(expected %i, found %i)\n",
10942 tracked_pipe
, pipe
);
10948 check_crtc_state(struct drm_device
*dev
)
10950 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10951 struct intel_crtc
*crtc
;
10952 struct intel_encoder
*encoder
;
10953 struct intel_crtc_config pipe_config
;
10955 for_each_intel_crtc(dev
, crtc
) {
10956 bool enabled
= false;
10957 bool active
= false;
10959 memset(&pipe_config
, 0, sizeof(pipe_config
));
10961 DRM_DEBUG_KMS("[CRTC:%d]\n",
10962 crtc
->base
.base
.id
);
10964 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10965 "active crtc, but not enabled in sw tracking\n");
10967 for_each_intel_encoder(dev
, encoder
) {
10968 if (encoder
->base
.crtc
!= &crtc
->base
)
10971 if (encoder
->connectors_active
)
10975 WARN(active
!= crtc
->active
,
10976 "crtc's computed active state doesn't match tracked active state "
10977 "(expected %i, found %i)\n", active
, crtc
->active
);
10978 WARN(enabled
!= crtc
->base
.enabled
,
10979 "crtc's computed enabled state doesn't match tracked enabled state "
10980 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10982 active
= dev_priv
->display
.get_pipe_config(crtc
,
10985 /* hw state is inconsistent with the pipe quirk */
10986 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10987 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10988 active
= crtc
->active
;
10990 for_each_intel_encoder(dev
, encoder
) {
10992 if (encoder
->base
.crtc
!= &crtc
->base
)
10994 if (encoder
->get_hw_state(encoder
, &pipe
))
10995 encoder
->get_config(encoder
, &pipe_config
);
10998 WARN(crtc
->active
!= active
,
10999 "crtc active state doesn't match with hw state "
11000 "(expected %i, found %i)\n", crtc
->active
, active
);
11003 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
11004 WARN(1, "pipe state doesn't match!\n");
11005 intel_dump_pipe_config(crtc
, &pipe_config
,
11007 intel_dump_pipe_config(crtc
, &crtc
->config
,
11014 check_shared_dpll_state(struct drm_device
*dev
)
11016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11017 struct intel_crtc
*crtc
;
11018 struct intel_dpll_hw_state dpll_hw_state
;
11021 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11022 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11023 int enabled_crtcs
= 0, active_crtcs
= 0;
11026 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11028 DRM_DEBUG_KMS("%s\n", pll
->name
);
11030 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11032 WARN(pll
->active
> pll
->refcount
,
11033 "more active pll users than references: %i vs %i\n",
11034 pll
->active
, pll
->refcount
);
11035 WARN(pll
->active
&& !pll
->on
,
11036 "pll in active use but not on in sw tracking\n");
11037 WARN(pll
->on
&& !pll
->active
,
11038 "pll in on but not on in use in sw tracking\n");
11039 WARN(pll
->on
!= active
,
11040 "pll on state mismatch (expected %i, found %i)\n",
11043 for_each_intel_crtc(dev
, crtc
) {
11044 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11046 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11049 WARN(pll
->active
!= active_crtcs
,
11050 "pll active crtcs mismatch (expected %i, found %i)\n",
11051 pll
->active
, active_crtcs
);
11052 WARN(pll
->refcount
!= enabled_crtcs
,
11053 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11054 pll
->refcount
, enabled_crtcs
);
11056 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
11057 sizeof(dpll_hw_state
)),
11058 "pll hw state mismatch\n");
11063 intel_modeset_check_state(struct drm_device
*dev
)
11065 check_connector_state(dev
);
11066 check_encoder_state(dev
);
11067 check_crtc_state(dev
);
11068 check_shared_dpll_state(dev
);
11071 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
11075 * FDI already provided one idea for the dotclock.
11076 * Yell if the encoder disagrees.
11078 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
11079 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11080 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
11083 static void update_scanline_offset(struct intel_crtc
*crtc
)
11085 struct drm_device
*dev
= crtc
->base
.dev
;
11088 * The scanline counter increments at the leading edge of hsync.
11090 * On most platforms it starts counting from vtotal-1 on the
11091 * first active line. That means the scanline counter value is
11092 * always one less than what we would expect. Ie. just after
11093 * start of vblank, which also occurs at start of hsync (on the
11094 * last active line), the scanline counter will read vblank_start-1.
11096 * On gen2 the scanline counter starts counting from 1 instead
11097 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11098 * to keep the value positive), instead of adding one.
11100 * On HSW+ the behaviour of the scanline counter depends on the output
11101 * type. For DP ports it behaves like most other platforms, but on HDMI
11102 * there's an extra 1 line difference. So we need to add two instead of
11103 * one to the value.
11105 if (IS_GEN2(dev
)) {
11106 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
11109 vtotal
= mode
->crtc_vtotal
;
11110 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11113 crtc
->scanline_offset
= vtotal
- 1;
11114 } else if (HAS_DDI(dev
) &&
11115 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
11116 crtc
->scanline_offset
= 2;
11118 crtc
->scanline_offset
= 1;
11121 static int __intel_set_mode(struct drm_crtc
*crtc
,
11122 struct drm_display_mode
*mode
,
11123 int x
, int y
, struct drm_framebuffer
*fb
)
11125 struct drm_device
*dev
= crtc
->dev
;
11126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11127 struct drm_display_mode
*saved_mode
;
11128 struct intel_crtc_config
*pipe_config
= NULL
;
11129 struct intel_crtc
*intel_crtc
;
11130 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
11133 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11137 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
11138 &prepare_pipes
, &disable_pipes
);
11140 *saved_mode
= crtc
->mode
;
11142 /* Hack: Because we don't (yet) support global modeset on multiple
11143 * crtcs, we don't keep track of the new mode for more than one crtc.
11144 * Hence simply check whether any bit is set in modeset_pipes in all the
11145 * pieces of code that are not yet converted to deal with mutliple crtcs
11146 * changing their mode at the same time. */
11147 if (modeset_pipes
) {
11148 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11149 if (IS_ERR(pipe_config
)) {
11150 ret
= PTR_ERR(pipe_config
);
11151 pipe_config
= NULL
;
11155 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11157 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11161 * See if the config requires any additional preparation, e.g.
11162 * to adjust global state with pipes off. We need to do this
11163 * here so we can get the modeset_pipe updated config for the new
11164 * mode set on this crtc. For other crtcs we need to use the
11165 * adjusted_mode bits in the crtc directly.
11167 if (IS_VALLEYVIEW(dev
)) {
11168 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11170 /* may have added more to prepare_pipes than we should */
11171 prepare_pipes
&= ~disable_pipes
;
11174 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11175 intel_crtc_disable(&intel_crtc
->base
);
11177 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11178 if (intel_crtc
->base
.enabled
)
11179 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11182 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11183 * to set it here already despite that we pass it down the callchain.
11185 if (modeset_pipes
) {
11186 crtc
->mode
= *mode
;
11187 /* mode_set/enable/disable functions rely on a correct pipe
11189 to_intel_crtc(crtc
)->config
= *pipe_config
;
11190 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
11193 * Calculate and store various constants which
11194 * are later needed by vblank and swap-completion
11195 * timestamping. They are derived from true hwmode.
11197 drm_calc_timestamping_constants(crtc
,
11198 &pipe_config
->adjusted_mode
);
11201 /* Only after disabling all output pipelines that will be changed can we
11202 * update the the output configuration. */
11203 intel_modeset_update_state(dev
, prepare_pipes
);
11205 if (dev_priv
->display
.modeset_global_resources
)
11206 dev_priv
->display
.modeset_global_resources(dev
);
11208 /* Set up the DPLL and any encoders state that needs to adjust or depend
11211 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11212 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11213 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
11214 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11216 mutex_lock(&dev
->struct_mutex
);
11217 ret
= intel_pin_and_fence_fb_obj(dev
,
11221 DRM_ERROR("pin & fence failed\n");
11222 mutex_unlock(&dev
->struct_mutex
);
11226 intel_unpin_fb_obj(old_obj
);
11227 i915_gem_track_fb(old_obj
, obj
,
11228 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11229 mutex_unlock(&dev
->struct_mutex
);
11231 crtc
->primary
->fb
= fb
;
11235 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11241 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11242 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11243 update_scanline_offset(intel_crtc
);
11245 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11248 /* FIXME: add subpixel order */
11250 if (ret
&& crtc
->enabled
)
11251 crtc
->mode
= *saved_mode
;
11254 kfree(pipe_config
);
11259 static int intel_set_mode(struct drm_crtc
*crtc
,
11260 struct drm_display_mode
*mode
,
11261 int x
, int y
, struct drm_framebuffer
*fb
)
11265 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11268 intel_modeset_check_state(crtc
->dev
);
11273 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11275 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11278 #undef for_each_intel_crtc_masked
11280 static void intel_set_config_free(struct intel_set_config
*config
)
11285 kfree(config
->save_connector_encoders
);
11286 kfree(config
->save_encoder_crtcs
);
11287 kfree(config
->save_crtc_enabled
);
11291 static int intel_set_config_save_state(struct drm_device
*dev
,
11292 struct intel_set_config
*config
)
11294 struct drm_crtc
*crtc
;
11295 struct drm_encoder
*encoder
;
11296 struct drm_connector
*connector
;
11299 config
->save_crtc_enabled
=
11300 kcalloc(dev
->mode_config
.num_crtc
,
11301 sizeof(bool), GFP_KERNEL
);
11302 if (!config
->save_crtc_enabled
)
11305 config
->save_encoder_crtcs
=
11306 kcalloc(dev
->mode_config
.num_encoder
,
11307 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11308 if (!config
->save_encoder_crtcs
)
11311 config
->save_connector_encoders
=
11312 kcalloc(dev
->mode_config
.num_connector
,
11313 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11314 if (!config
->save_connector_encoders
)
11317 /* Copy data. Note that driver private data is not affected.
11318 * Should anything bad happen only the expected state is
11319 * restored, not the drivers personal bookkeeping.
11322 for_each_crtc(dev
, crtc
) {
11323 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11327 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11328 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11332 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11333 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11339 static void intel_set_config_restore_state(struct drm_device
*dev
,
11340 struct intel_set_config
*config
)
11342 struct intel_crtc
*crtc
;
11343 struct intel_encoder
*encoder
;
11344 struct intel_connector
*connector
;
11348 for_each_intel_crtc(dev
, crtc
) {
11349 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11351 if (crtc
->new_enabled
)
11352 crtc
->new_config
= &crtc
->config
;
11354 crtc
->new_config
= NULL
;
11358 for_each_intel_encoder(dev
, encoder
) {
11359 encoder
->new_crtc
=
11360 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11364 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11365 connector
->new_encoder
=
11366 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11371 is_crtc_connector_off(struct drm_mode_set
*set
)
11375 if (set
->num_connectors
== 0)
11378 if (WARN_ON(set
->connectors
== NULL
))
11381 for (i
= 0; i
< set
->num_connectors
; i
++)
11382 if (set
->connectors
[i
]->encoder
&&
11383 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11384 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11391 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11392 struct intel_set_config
*config
)
11395 /* We should be able to check here if the fb has the same properties
11396 * and then just flip_or_move it */
11397 if (is_crtc_connector_off(set
)) {
11398 config
->mode_changed
= true;
11399 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11401 * If we have no fb, we can only flip as long as the crtc is
11402 * active, otherwise we need a full mode set. The crtc may
11403 * be active if we've only disabled the primary plane, or
11404 * in fastboot situations.
11406 if (set
->crtc
->primary
->fb
== NULL
) {
11407 struct intel_crtc
*intel_crtc
=
11408 to_intel_crtc(set
->crtc
);
11410 if (intel_crtc
->active
) {
11411 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11412 config
->fb_changed
= true;
11414 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11415 config
->mode_changed
= true;
11417 } else if (set
->fb
== NULL
) {
11418 config
->mode_changed
= true;
11419 } else if (set
->fb
->pixel_format
!=
11420 set
->crtc
->primary
->fb
->pixel_format
) {
11421 config
->mode_changed
= true;
11423 config
->fb_changed
= true;
11427 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11428 config
->fb_changed
= true;
11430 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11431 DRM_DEBUG_KMS("modes are different, full mode set\n");
11432 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11433 drm_mode_debug_printmodeline(set
->mode
);
11434 config
->mode_changed
= true;
11437 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11438 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11442 intel_modeset_stage_output_state(struct drm_device
*dev
,
11443 struct drm_mode_set
*set
,
11444 struct intel_set_config
*config
)
11446 struct intel_connector
*connector
;
11447 struct intel_encoder
*encoder
;
11448 struct intel_crtc
*crtc
;
11451 /* The upper layers ensure that we either disable a crtc or have a list
11452 * of connectors. For paranoia, double-check this. */
11453 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11454 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11456 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11458 /* Otherwise traverse passed in connector list and get encoders
11460 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11461 if (set
->connectors
[ro
] == &connector
->base
) {
11462 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11467 /* If we disable the crtc, disable all its connectors. Also, if
11468 * the connector is on the changing crtc but not on the new
11469 * connector list, disable it. */
11470 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11471 connector
->base
.encoder
&&
11472 connector
->base
.encoder
->crtc
== set
->crtc
) {
11473 connector
->new_encoder
= NULL
;
11475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11476 connector
->base
.base
.id
,
11477 connector
->base
.name
);
11481 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11482 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11483 config
->mode_changed
= true;
11486 /* connector->new_encoder is now updated for all connectors. */
11488 /* Update crtc of enabled connectors. */
11489 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11491 struct drm_crtc
*new_crtc
;
11493 if (!connector
->new_encoder
)
11496 new_crtc
= connector
->new_encoder
->base
.crtc
;
11498 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11499 if (set
->connectors
[ro
] == &connector
->base
)
11500 new_crtc
= set
->crtc
;
11503 /* Make sure the new CRTC will work with the encoder */
11504 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11508 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11510 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11511 connector
->base
.base
.id
,
11512 connector
->base
.name
,
11513 new_crtc
->base
.id
);
11516 /* Check for any encoders that needs to be disabled. */
11517 for_each_intel_encoder(dev
, encoder
) {
11518 int num_connectors
= 0;
11519 list_for_each_entry(connector
,
11520 &dev
->mode_config
.connector_list
,
11522 if (connector
->new_encoder
== encoder
) {
11523 WARN_ON(!connector
->new_encoder
->new_crtc
);
11528 if (num_connectors
== 0)
11529 encoder
->new_crtc
= NULL
;
11530 else if (num_connectors
> 1)
11533 /* Only now check for crtc changes so we don't miss encoders
11534 * that will be disabled. */
11535 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11536 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11537 config
->mode_changed
= true;
11540 /* Now we've also updated encoder->new_crtc for all encoders. */
11541 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11543 if (connector
->new_encoder
)
11544 if (connector
->new_encoder
!= connector
->encoder
)
11545 connector
->encoder
= connector
->new_encoder
;
11547 for_each_intel_crtc(dev
, crtc
) {
11548 crtc
->new_enabled
= false;
11550 for_each_intel_encoder(dev
, encoder
) {
11551 if (encoder
->new_crtc
== crtc
) {
11552 crtc
->new_enabled
= true;
11557 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11558 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11559 crtc
->new_enabled
? "en" : "dis");
11560 config
->mode_changed
= true;
11563 if (crtc
->new_enabled
)
11564 crtc
->new_config
= &crtc
->config
;
11566 crtc
->new_config
= NULL
;
11572 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11574 struct drm_device
*dev
= crtc
->base
.dev
;
11575 struct intel_encoder
*encoder
;
11576 struct intel_connector
*connector
;
11578 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11579 pipe_name(crtc
->pipe
));
11581 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11582 if (connector
->new_encoder
&&
11583 connector
->new_encoder
->new_crtc
== crtc
)
11584 connector
->new_encoder
= NULL
;
11587 for_each_intel_encoder(dev
, encoder
) {
11588 if (encoder
->new_crtc
== crtc
)
11589 encoder
->new_crtc
= NULL
;
11592 crtc
->new_enabled
= false;
11593 crtc
->new_config
= NULL
;
11596 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11598 struct drm_device
*dev
;
11599 struct drm_mode_set save_set
;
11600 struct intel_set_config
*config
;
11604 BUG_ON(!set
->crtc
);
11605 BUG_ON(!set
->crtc
->helper_private
);
11607 /* Enforce sane interface api - has been abused by the fb helper. */
11608 BUG_ON(!set
->mode
&& set
->fb
);
11609 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11612 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11613 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11614 (int)set
->num_connectors
, set
->x
, set
->y
);
11616 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11619 dev
= set
->crtc
->dev
;
11622 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11626 ret
= intel_set_config_save_state(dev
, config
);
11630 save_set
.crtc
= set
->crtc
;
11631 save_set
.mode
= &set
->crtc
->mode
;
11632 save_set
.x
= set
->crtc
->x
;
11633 save_set
.y
= set
->crtc
->y
;
11634 save_set
.fb
= set
->crtc
->primary
->fb
;
11636 /* Compute whether we need a full modeset, only an fb base update or no
11637 * change at all. In the future we might also check whether only the
11638 * mode changed, e.g. for LVDS where we only change the panel fitter in
11640 intel_set_config_compute_mode_changes(set
, config
);
11642 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11646 if (config
->mode_changed
) {
11647 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11648 set
->x
, set
->y
, set
->fb
);
11649 } else if (config
->fb_changed
) {
11650 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11652 intel_crtc_wait_for_pending_flips(set
->crtc
);
11654 ret
= intel_pipe_set_base(set
->crtc
,
11655 set
->x
, set
->y
, set
->fb
);
11658 * We need to make sure the primary plane is re-enabled if it
11659 * has previously been turned off.
11661 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11662 WARN_ON(!intel_crtc
->active
);
11663 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11667 * In the fastboot case this may be our only check of the
11668 * state after boot. It would be better to only do it on
11669 * the first update, but we don't have a nice way of doing that
11670 * (and really, set_config isn't used much for high freq page
11671 * flipping, so increasing its cost here shouldn't be a big
11674 if (i915
.fastboot
&& ret
== 0)
11675 intel_modeset_check_state(set
->crtc
->dev
);
11679 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11680 set
->crtc
->base
.id
, ret
);
11682 intel_set_config_restore_state(dev
, config
);
11685 * HACK: if the pipe was on, but we didn't have a framebuffer,
11686 * force the pipe off to avoid oopsing in the modeset code
11687 * due to fb==NULL. This should only happen during boot since
11688 * we don't yet reconstruct the FB from the hardware state.
11690 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11691 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11693 /* Try to restore the config */
11694 if (config
->mode_changed
&&
11695 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11696 save_set
.x
, save_set
.y
, save_set
.fb
))
11697 DRM_ERROR("failed to restore config after modeset failure\n");
11701 intel_set_config_free(config
);
11705 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11706 .gamma_set
= intel_crtc_gamma_set
,
11707 .set_config
= intel_crtc_set_config
,
11708 .destroy
= intel_crtc_destroy
,
11709 .page_flip
= intel_crtc_page_flip
,
11712 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11713 struct intel_shared_dpll
*pll
,
11714 struct intel_dpll_hw_state
*hw_state
)
11718 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11721 val
= I915_READ(PCH_DPLL(pll
->id
));
11722 hw_state
->dpll
= val
;
11723 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11724 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11726 return val
& DPLL_VCO_ENABLE
;
11729 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11730 struct intel_shared_dpll
*pll
)
11732 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11733 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11736 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11737 struct intel_shared_dpll
*pll
)
11739 /* PCH refclock must be enabled first */
11740 ibx_assert_pch_refclk_enabled(dev_priv
);
11742 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11744 /* Wait for the clocks to stabilize. */
11745 POSTING_READ(PCH_DPLL(pll
->id
));
11748 /* The pixel multiplier can only be updated once the
11749 * DPLL is enabled and the clocks are stable.
11751 * So write it again.
11753 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11754 POSTING_READ(PCH_DPLL(pll
->id
));
11758 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11759 struct intel_shared_dpll
*pll
)
11761 struct drm_device
*dev
= dev_priv
->dev
;
11762 struct intel_crtc
*crtc
;
11764 /* Make sure no transcoder isn't still depending on us. */
11765 for_each_intel_crtc(dev
, crtc
) {
11766 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11767 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11770 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11771 POSTING_READ(PCH_DPLL(pll
->id
));
11775 static char *ibx_pch_dpll_names
[] = {
11780 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11785 dev_priv
->num_shared_dpll
= 2;
11787 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11788 dev_priv
->shared_dplls
[i
].id
= i
;
11789 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11790 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11791 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11792 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11793 dev_priv
->shared_dplls
[i
].get_hw_state
=
11794 ibx_pch_dpll_get_hw_state
;
11798 static void intel_shared_dpll_init(struct drm_device
*dev
)
11800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11803 intel_ddi_pll_init(dev
);
11804 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11805 ibx_pch_dpll_init(dev
);
11807 dev_priv
->num_shared_dpll
= 0;
11809 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11813 intel_primary_plane_disable(struct drm_plane
*plane
)
11815 struct drm_device
*dev
= plane
->dev
;
11816 struct intel_crtc
*intel_crtc
;
11821 BUG_ON(!plane
->crtc
);
11823 intel_crtc
= to_intel_crtc(plane
->crtc
);
11826 * Even though we checked plane->fb above, it's still possible that
11827 * the primary plane has been implicitly disabled because the crtc
11828 * coordinates given weren't visible, or because we detected
11829 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11830 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11831 * In either case, we need to unpin the FB and let the fb pointer get
11832 * updated, but otherwise we don't need to touch the hardware.
11834 if (!intel_crtc
->primary_enabled
)
11835 goto disable_unpin
;
11837 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11838 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11841 mutex_lock(&dev
->struct_mutex
);
11842 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11843 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11844 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11845 mutex_unlock(&dev
->struct_mutex
);
11852 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11853 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11854 unsigned int crtc_w
, unsigned int crtc_h
,
11855 uint32_t src_x
, uint32_t src_y
,
11856 uint32_t src_w
, uint32_t src_h
)
11858 struct drm_device
*dev
= crtc
->dev
;
11859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11860 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11861 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11862 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11863 struct drm_rect dest
= {
11864 /* integer pixels */
11867 .x2
= crtc_x
+ crtc_w
,
11868 .y2
= crtc_y
+ crtc_h
,
11870 struct drm_rect src
= {
11871 /* 16.16 fixed point */
11874 .x2
= src_x
+ src_w
,
11875 .y2
= src_y
+ src_h
,
11877 const struct drm_rect clip
= {
11878 /* integer pixels */
11879 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11880 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11883 int crtc_x
, crtc_y
;
11884 unsigned int crtc_w
, crtc_h
;
11885 uint32_t src_x
, src_y
, src_w
, src_h
;
11896 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11900 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11901 &src
, &dest
, &clip
,
11902 DRM_PLANE_HELPER_NO_SCALING
,
11903 DRM_PLANE_HELPER_NO_SCALING
,
11904 false, true, &visible
);
11910 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11911 * updating the fb pointer, and returning without touching the
11912 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11913 * turn on the display with all planes setup as desired.
11915 if (!crtc
->enabled
) {
11916 mutex_lock(&dev
->struct_mutex
);
11919 * If we already called setplane while the crtc was disabled,
11920 * we may have an fb pinned; unpin it.
11923 intel_unpin_fb_obj(old_obj
);
11925 i915_gem_track_fb(old_obj
, obj
,
11926 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11928 /* Pin and return without programming hardware */
11929 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11930 mutex_unlock(&dev
->struct_mutex
);
11935 intel_crtc_wait_for_pending_flips(crtc
);
11938 * If clipping results in a non-visible primary plane, we'll disable
11939 * the primary plane. Note that this is a bit different than what
11940 * happens if userspace explicitly disables the plane by passing fb=0
11941 * because plane->fb still gets set and pinned.
11944 mutex_lock(&dev
->struct_mutex
);
11947 * Try to pin the new fb first so that we can bail out if we
11950 if (plane
->fb
!= fb
) {
11951 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11953 mutex_unlock(&dev
->struct_mutex
);
11958 i915_gem_track_fb(old_obj
, obj
,
11959 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11961 if (intel_crtc
->primary_enabled
)
11962 intel_disable_primary_hw_plane(plane
, crtc
);
11965 if (plane
->fb
!= fb
)
11967 intel_unpin_fb_obj(old_obj
);
11969 mutex_unlock(&dev
->struct_mutex
);
11972 if (intel_crtc
&& intel_crtc
->active
&&
11973 intel_crtc
->primary_enabled
) {
11975 * FBC does not work on some platforms for rotated
11976 * planes, so disable it when rotation is not 0 and
11977 * update it when rotation is set back to 0.
11979 * FIXME: This is redundant with the fbc update done in
11980 * the primary plane enable function except that that
11981 * one is done too late. We eventually need to unify
11984 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11985 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11986 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11987 intel_disable_fbc(dev
);
11990 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11994 if (!intel_crtc
->primary_enabled
)
11995 intel_enable_primary_hw_plane(plane
, crtc
);
11998 intel_plane
->crtc_x
= orig
.crtc_x
;
11999 intel_plane
->crtc_y
= orig
.crtc_y
;
12000 intel_plane
->crtc_w
= orig
.crtc_w
;
12001 intel_plane
->crtc_h
= orig
.crtc_h
;
12002 intel_plane
->src_x
= orig
.src_x
;
12003 intel_plane
->src_y
= orig
.src_y
;
12004 intel_plane
->src_w
= orig
.src_w
;
12005 intel_plane
->src_h
= orig
.src_h
;
12006 intel_plane
->obj
= obj
;
12011 /* Common destruction function for both primary and cursor planes */
12012 static void intel_plane_destroy(struct drm_plane
*plane
)
12014 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12015 drm_plane_cleanup(plane
);
12016 kfree(intel_plane
);
12019 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
12020 .update_plane
= intel_primary_plane_setplane
,
12021 .disable_plane
= intel_primary_plane_disable
,
12022 .destroy
= intel_plane_destroy
,
12023 .set_property
= intel_plane_set_property
12026 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12029 struct intel_plane
*primary
;
12030 const uint32_t *intel_primary_formats
;
12033 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12034 if (primary
== NULL
)
12037 primary
->can_scale
= false;
12038 primary
->max_downscale
= 1;
12039 primary
->pipe
= pipe
;
12040 primary
->plane
= pipe
;
12041 primary
->rotation
= BIT(DRM_ROTATE_0
);
12042 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12043 primary
->plane
= !pipe
;
12045 if (INTEL_INFO(dev
)->gen
<= 3) {
12046 intel_primary_formats
= intel_primary_formats_gen2
;
12047 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12049 intel_primary_formats
= intel_primary_formats_gen4
;
12050 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12053 drm_universal_plane_init(dev
, &primary
->base
, 0,
12054 &intel_primary_plane_funcs
,
12055 intel_primary_formats
, num_formats
,
12056 DRM_PLANE_TYPE_PRIMARY
);
12058 if (INTEL_INFO(dev
)->gen
>= 4) {
12059 if (!dev
->mode_config
.rotation_property
)
12060 dev
->mode_config
.rotation_property
=
12061 drm_mode_create_rotation_property(dev
,
12062 BIT(DRM_ROTATE_0
) |
12063 BIT(DRM_ROTATE_180
));
12064 if (dev
->mode_config
.rotation_property
)
12065 drm_object_attach_property(&primary
->base
.base
,
12066 dev
->mode_config
.rotation_property
,
12067 primary
->rotation
);
12070 return &primary
->base
;
12074 intel_cursor_plane_disable(struct drm_plane
*plane
)
12079 BUG_ON(!plane
->crtc
);
12081 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
12085 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
12086 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
12087 unsigned int crtc_w
, unsigned int crtc_h
,
12088 uint32_t src_x
, uint32_t src_y
,
12089 uint32_t src_w
, uint32_t src_h
)
12091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12092 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12093 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12094 struct drm_rect dest
= {
12095 /* integer pixels */
12098 .x2
= crtc_x
+ crtc_w
,
12099 .y2
= crtc_y
+ crtc_h
,
12101 struct drm_rect src
= {
12102 /* 16.16 fixed point */
12105 .x2
= src_x
+ src_w
,
12106 .y2
= src_y
+ src_h
,
12108 const struct drm_rect clip
= {
12109 /* integer pixels */
12110 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
12111 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
12116 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12117 &src
, &dest
, &clip
,
12118 DRM_PLANE_HELPER_NO_SCALING
,
12119 DRM_PLANE_HELPER_NO_SCALING
,
12120 true, true, &visible
);
12124 crtc
->cursor_x
= crtc_x
;
12125 crtc
->cursor_y
= crtc_y
;
12126 if (fb
!= crtc
->cursor
->fb
) {
12127 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
12129 intel_crtc_update_cursor(crtc
, visible
);
12131 intel_frontbuffer_flip(crtc
->dev
,
12132 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
12137 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12138 .update_plane
= intel_cursor_plane_update
,
12139 .disable_plane
= intel_cursor_plane_disable
,
12140 .destroy
= intel_plane_destroy
,
12143 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12146 struct intel_plane
*cursor
;
12148 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12149 if (cursor
== NULL
)
12152 cursor
->can_scale
= false;
12153 cursor
->max_downscale
= 1;
12154 cursor
->pipe
= pipe
;
12155 cursor
->plane
= pipe
;
12157 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12158 &intel_cursor_plane_funcs
,
12159 intel_cursor_formats
,
12160 ARRAY_SIZE(intel_cursor_formats
),
12161 DRM_PLANE_TYPE_CURSOR
);
12162 return &cursor
->base
;
12165 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12168 struct intel_crtc
*intel_crtc
;
12169 struct drm_plane
*primary
= NULL
;
12170 struct drm_plane
*cursor
= NULL
;
12173 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12174 if (intel_crtc
== NULL
)
12177 primary
= intel_primary_plane_create(dev
, pipe
);
12181 cursor
= intel_cursor_plane_create(dev
, pipe
);
12185 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12186 cursor
, &intel_crtc_funcs
);
12190 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12191 for (i
= 0; i
< 256; i
++) {
12192 intel_crtc
->lut_r
[i
] = i
;
12193 intel_crtc
->lut_g
[i
] = i
;
12194 intel_crtc
->lut_b
[i
] = i
;
12198 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12199 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12201 intel_crtc
->pipe
= pipe
;
12202 intel_crtc
->plane
= pipe
;
12203 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12204 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12205 intel_crtc
->plane
= !pipe
;
12208 intel_crtc
->cursor_base
= ~0;
12209 intel_crtc
->cursor_cntl
= ~0;
12210 intel_crtc
->cursor_size
= ~0;
12212 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12213 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12214 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12215 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12217 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12219 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12224 drm_plane_cleanup(primary
);
12226 drm_plane_cleanup(cursor
);
12230 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12232 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12233 struct drm_device
*dev
= connector
->base
.dev
;
12235 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12238 return INVALID_PIPE
;
12240 return to_intel_crtc(encoder
->crtc
)->pipe
;
12243 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12244 struct drm_file
*file
)
12246 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12247 struct drm_crtc
*drmmode_crtc
;
12248 struct intel_crtc
*crtc
;
12250 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12253 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12255 if (!drmmode_crtc
) {
12256 DRM_ERROR("no such CRTC id\n");
12260 crtc
= to_intel_crtc(drmmode_crtc
);
12261 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12266 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12268 struct drm_device
*dev
= encoder
->base
.dev
;
12269 struct intel_encoder
*source_encoder
;
12270 int index_mask
= 0;
12273 for_each_intel_encoder(dev
, source_encoder
) {
12274 if (encoders_cloneable(encoder
, source_encoder
))
12275 index_mask
|= (1 << entry
);
12283 static bool has_edp_a(struct drm_device
*dev
)
12285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12287 if (!IS_MOBILE(dev
))
12290 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12293 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12299 const char *intel_output_name(int output
)
12301 static const char *names
[] = {
12302 [INTEL_OUTPUT_UNUSED
] = "Unused",
12303 [INTEL_OUTPUT_ANALOG
] = "Analog",
12304 [INTEL_OUTPUT_DVO
] = "DVO",
12305 [INTEL_OUTPUT_SDVO
] = "SDVO",
12306 [INTEL_OUTPUT_LVDS
] = "LVDS",
12307 [INTEL_OUTPUT_TVOUT
] = "TV",
12308 [INTEL_OUTPUT_HDMI
] = "HDMI",
12309 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12310 [INTEL_OUTPUT_EDP
] = "eDP",
12311 [INTEL_OUTPUT_DSI
] = "DSI",
12312 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12315 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12318 return names
[output
];
12321 static bool intel_crt_present(struct drm_device
*dev
)
12323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12328 if (IS_CHERRYVIEW(dev
))
12331 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12337 static void intel_setup_outputs(struct drm_device
*dev
)
12339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12340 struct intel_encoder
*encoder
;
12341 bool dpd_is_edp
= false;
12343 intel_lvds_init(dev
);
12345 if (intel_crt_present(dev
))
12346 intel_crt_init(dev
);
12348 if (HAS_DDI(dev
)) {
12351 /* Haswell uses DDI functions to detect digital outputs */
12352 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12353 /* DDI A only supports eDP */
12355 intel_ddi_init(dev
, PORT_A
);
12357 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12359 found
= I915_READ(SFUSE_STRAP
);
12361 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12362 intel_ddi_init(dev
, PORT_B
);
12363 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12364 intel_ddi_init(dev
, PORT_C
);
12365 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12366 intel_ddi_init(dev
, PORT_D
);
12367 } else if (HAS_PCH_SPLIT(dev
)) {
12369 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12371 if (has_edp_a(dev
))
12372 intel_dp_init(dev
, DP_A
, PORT_A
);
12374 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12375 /* PCH SDVOB multiplex with HDMIB */
12376 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12378 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12379 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12380 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12383 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12384 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12386 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12387 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12389 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12390 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12392 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12393 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12394 } else if (IS_VALLEYVIEW(dev
)) {
12395 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12396 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12398 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12399 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12402 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12403 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12405 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12406 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12409 if (IS_CHERRYVIEW(dev
)) {
12410 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12411 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12413 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12414 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12418 intel_dsi_init(dev
);
12419 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12420 bool found
= false;
12422 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12423 DRM_DEBUG_KMS("probing SDVOB\n");
12424 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12425 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12426 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12427 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12430 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12431 intel_dp_init(dev
, DP_B
, PORT_B
);
12434 /* Before G4X SDVOC doesn't have its own detect register */
12436 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12437 DRM_DEBUG_KMS("probing SDVOC\n");
12438 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12441 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12443 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12444 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12445 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12447 if (SUPPORTS_INTEGRATED_DP(dev
))
12448 intel_dp_init(dev
, DP_C
, PORT_C
);
12451 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12452 (I915_READ(DP_D
) & DP_DETECTED
))
12453 intel_dp_init(dev
, DP_D
, PORT_D
);
12454 } else if (IS_GEN2(dev
))
12455 intel_dvo_init(dev
);
12457 if (SUPPORTS_TV(dev
))
12458 intel_tv_init(dev
);
12460 intel_edp_psr_init(dev
);
12462 for_each_intel_encoder(dev
, encoder
) {
12463 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12464 encoder
->base
.possible_clones
=
12465 intel_encoder_clones(encoder
);
12468 intel_init_pch_refclk(dev
);
12470 drm_helper_move_panel_connectors_to_head(dev
);
12473 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12475 struct drm_device
*dev
= fb
->dev
;
12476 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12478 drm_framebuffer_cleanup(fb
);
12479 mutex_lock(&dev
->struct_mutex
);
12480 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12481 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12482 mutex_unlock(&dev
->struct_mutex
);
12486 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12487 struct drm_file
*file
,
12488 unsigned int *handle
)
12490 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12491 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12493 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12496 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12497 .destroy
= intel_user_framebuffer_destroy
,
12498 .create_handle
= intel_user_framebuffer_create_handle
,
12501 static int intel_framebuffer_init(struct drm_device
*dev
,
12502 struct intel_framebuffer
*intel_fb
,
12503 struct drm_mode_fb_cmd2
*mode_cmd
,
12504 struct drm_i915_gem_object
*obj
)
12506 int aligned_height
;
12510 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12512 if (obj
->tiling_mode
== I915_TILING_Y
) {
12513 DRM_DEBUG("hardware does not support tiling Y\n");
12517 if (mode_cmd
->pitches
[0] & 63) {
12518 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12519 mode_cmd
->pitches
[0]);
12523 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12524 pitch_limit
= 32*1024;
12525 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12526 if (obj
->tiling_mode
)
12527 pitch_limit
= 16*1024;
12529 pitch_limit
= 32*1024;
12530 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12531 if (obj
->tiling_mode
)
12532 pitch_limit
= 8*1024;
12534 pitch_limit
= 16*1024;
12536 /* XXX DSPC is limited to 4k tiled */
12537 pitch_limit
= 8*1024;
12539 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12540 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12541 obj
->tiling_mode
? "tiled" : "linear",
12542 mode_cmd
->pitches
[0], pitch_limit
);
12546 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12547 mode_cmd
->pitches
[0] != obj
->stride
) {
12548 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12549 mode_cmd
->pitches
[0], obj
->stride
);
12553 /* Reject formats not supported by any plane early. */
12554 switch (mode_cmd
->pixel_format
) {
12555 case DRM_FORMAT_C8
:
12556 case DRM_FORMAT_RGB565
:
12557 case DRM_FORMAT_XRGB8888
:
12558 case DRM_FORMAT_ARGB8888
:
12560 case DRM_FORMAT_XRGB1555
:
12561 case DRM_FORMAT_ARGB1555
:
12562 if (INTEL_INFO(dev
)->gen
> 3) {
12563 DRM_DEBUG("unsupported pixel format: %s\n",
12564 drm_get_format_name(mode_cmd
->pixel_format
));
12568 case DRM_FORMAT_XBGR8888
:
12569 case DRM_FORMAT_ABGR8888
:
12570 case DRM_FORMAT_XRGB2101010
:
12571 case DRM_FORMAT_ARGB2101010
:
12572 case DRM_FORMAT_XBGR2101010
:
12573 case DRM_FORMAT_ABGR2101010
:
12574 if (INTEL_INFO(dev
)->gen
< 4) {
12575 DRM_DEBUG("unsupported pixel format: %s\n",
12576 drm_get_format_name(mode_cmd
->pixel_format
));
12580 case DRM_FORMAT_YUYV
:
12581 case DRM_FORMAT_UYVY
:
12582 case DRM_FORMAT_YVYU
:
12583 case DRM_FORMAT_VYUY
:
12584 if (INTEL_INFO(dev
)->gen
< 5) {
12585 DRM_DEBUG("unsupported pixel format: %s\n",
12586 drm_get_format_name(mode_cmd
->pixel_format
));
12591 DRM_DEBUG("unsupported pixel format: %s\n",
12592 drm_get_format_name(mode_cmd
->pixel_format
));
12596 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12597 if (mode_cmd
->offsets
[0] != 0)
12600 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12602 /* FIXME drm helper for size checks (especially planar formats)? */
12603 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12606 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12607 intel_fb
->obj
= obj
;
12608 intel_fb
->obj
->framebuffer_references
++;
12610 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12612 DRM_ERROR("framebuffer init failed %d\n", ret
);
12619 static struct drm_framebuffer
*
12620 intel_user_framebuffer_create(struct drm_device
*dev
,
12621 struct drm_file
*filp
,
12622 struct drm_mode_fb_cmd2
*mode_cmd
)
12624 struct drm_i915_gem_object
*obj
;
12626 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12627 mode_cmd
->handles
[0]));
12628 if (&obj
->base
== NULL
)
12629 return ERR_PTR(-ENOENT
);
12631 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12634 #ifndef CONFIG_DRM_I915_FBDEV
12635 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12640 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12641 .fb_create
= intel_user_framebuffer_create
,
12642 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12645 /* Set up chip specific display functions */
12646 static void intel_init_display(struct drm_device
*dev
)
12648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12650 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12651 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12652 else if (IS_CHERRYVIEW(dev
))
12653 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12654 else if (IS_VALLEYVIEW(dev
))
12655 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12656 else if (IS_PINEVIEW(dev
))
12657 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12659 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12661 if (HAS_DDI(dev
)) {
12662 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12663 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12664 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12665 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12666 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12667 dev_priv
->display
.off
= ironlake_crtc_off
;
12668 if (INTEL_INFO(dev
)->gen
>= 9)
12669 dev_priv
->display
.update_primary_plane
=
12670 skylake_update_primary_plane
;
12672 dev_priv
->display
.update_primary_plane
=
12673 ironlake_update_primary_plane
;
12674 } else if (HAS_PCH_SPLIT(dev
)) {
12675 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12676 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12677 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12678 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12679 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12680 dev_priv
->display
.off
= ironlake_crtc_off
;
12681 dev_priv
->display
.update_primary_plane
=
12682 ironlake_update_primary_plane
;
12683 } else if (IS_VALLEYVIEW(dev
)) {
12684 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12685 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12686 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12687 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12688 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12689 dev_priv
->display
.off
= i9xx_crtc_off
;
12690 dev_priv
->display
.update_primary_plane
=
12691 i9xx_update_primary_plane
;
12693 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12694 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12695 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12696 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12697 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12698 dev_priv
->display
.off
= i9xx_crtc_off
;
12699 dev_priv
->display
.update_primary_plane
=
12700 i9xx_update_primary_plane
;
12703 /* Returns the core display clock speed */
12704 if (IS_VALLEYVIEW(dev
))
12705 dev_priv
->display
.get_display_clock_speed
=
12706 valleyview_get_display_clock_speed
;
12707 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12708 dev_priv
->display
.get_display_clock_speed
=
12709 i945_get_display_clock_speed
;
12710 else if (IS_I915G(dev
))
12711 dev_priv
->display
.get_display_clock_speed
=
12712 i915_get_display_clock_speed
;
12713 else if (IS_I945GM(dev
) || IS_845G(dev
))
12714 dev_priv
->display
.get_display_clock_speed
=
12715 i9xx_misc_get_display_clock_speed
;
12716 else if (IS_PINEVIEW(dev
))
12717 dev_priv
->display
.get_display_clock_speed
=
12718 pnv_get_display_clock_speed
;
12719 else if (IS_I915GM(dev
))
12720 dev_priv
->display
.get_display_clock_speed
=
12721 i915gm_get_display_clock_speed
;
12722 else if (IS_I865G(dev
))
12723 dev_priv
->display
.get_display_clock_speed
=
12724 i865_get_display_clock_speed
;
12725 else if (IS_I85X(dev
))
12726 dev_priv
->display
.get_display_clock_speed
=
12727 i855_get_display_clock_speed
;
12728 else /* 852, 830 */
12729 dev_priv
->display
.get_display_clock_speed
=
12730 i830_get_display_clock_speed
;
12733 dev_priv
->display
.write_eld
= g4x_write_eld
;
12734 } else if (IS_GEN5(dev
)) {
12735 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12736 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12737 } else if (IS_GEN6(dev
)) {
12738 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12739 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12740 dev_priv
->display
.modeset_global_resources
=
12741 snb_modeset_global_resources
;
12742 } else if (IS_IVYBRIDGE(dev
)) {
12743 /* FIXME: detect B0+ stepping and use auto training */
12744 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12745 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12746 dev_priv
->display
.modeset_global_resources
=
12747 ivb_modeset_global_resources
;
12748 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12749 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12750 dev_priv
->display
.write_eld
= haswell_write_eld
;
12751 dev_priv
->display
.modeset_global_resources
=
12752 haswell_modeset_global_resources
;
12753 } else if (IS_VALLEYVIEW(dev
)) {
12754 dev_priv
->display
.modeset_global_resources
=
12755 valleyview_modeset_global_resources
;
12756 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12759 /* Default just returns -ENODEV to indicate unsupported */
12760 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12762 switch (INTEL_INFO(dev
)->gen
) {
12764 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12768 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12773 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12777 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12780 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12781 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12785 intel_panel_init_backlight_funcs(dev
);
12787 mutex_init(&dev_priv
->pps_mutex
);
12791 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12792 * resume, or other times. This quirk makes sure that's the case for
12793 * affected systems.
12795 static void quirk_pipea_force(struct drm_device
*dev
)
12797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12799 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12800 DRM_INFO("applying pipe a force quirk\n");
12803 static void quirk_pipeb_force(struct drm_device
*dev
)
12805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12807 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12808 DRM_INFO("applying pipe b force quirk\n");
12812 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12814 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12817 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12818 DRM_INFO("applying lvds SSC disable quirk\n");
12822 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12825 static void quirk_invert_brightness(struct drm_device
*dev
)
12827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12828 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12829 DRM_INFO("applying inverted panel brightness quirk\n");
12832 /* Some VBT's incorrectly indicate no backlight is present */
12833 static void quirk_backlight_present(struct drm_device
*dev
)
12835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12836 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12837 DRM_INFO("applying backlight present quirk\n");
12840 struct intel_quirk
{
12842 int subsystem_vendor
;
12843 int subsystem_device
;
12844 void (*hook
)(struct drm_device
*dev
);
12847 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12848 struct intel_dmi_quirk
{
12849 void (*hook
)(struct drm_device
*dev
);
12850 const struct dmi_system_id (*dmi_id_list
)[];
12853 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12855 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12859 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12861 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12863 .callback
= intel_dmi_reverse_brightness
,
12864 .ident
= "NCR Corporation",
12865 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12866 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12869 { } /* terminating entry */
12871 .hook
= quirk_invert_brightness
,
12875 static struct intel_quirk intel_quirks
[] = {
12876 /* HP Mini needs pipe A force quirk (LP: #322104) */
12877 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12879 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12880 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12882 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12883 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12885 /* 830 needs to leave pipe A & dpll A up */
12886 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12888 /* 830 needs to leave pipe B & dpll B up */
12889 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12891 /* Lenovo U160 cannot use SSC on LVDS */
12892 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12894 /* Sony Vaio Y cannot use SSC on LVDS */
12895 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12897 /* Acer Aspire 5734Z must invert backlight brightness */
12898 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12900 /* Acer/eMachines G725 */
12901 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12903 /* Acer/eMachines e725 */
12904 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12906 /* Acer/Packard Bell NCL20 */
12907 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12909 /* Acer Aspire 4736Z */
12910 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12912 /* Acer Aspire 5336 */
12913 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12915 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12916 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12918 /* Acer C720 Chromebook (Core i3 4005U) */
12919 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12921 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12922 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12924 /* HP Chromebook 14 (Celeron 2955U) */
12925 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12928 static void intel_init_quirks(struct drm_device
*dev
)
12930 struct pci_dev
*d
= dev
->pdev
;
12933 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12934 struct intel_quirk
*q
= &intel_quirks
[i
];
12936 if (d
->device
== q
->device
&&
12937 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12938 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12939 (d
->subsystem_device
== q
->subsystem_device
||
12940 q
->subsystem_device
== PCI_ANY_ID
))
12943 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12944 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12945 intel_dmi_quirks
[i
].hook(dev
);
12949 /* Disable the VGA plane that we never use */
12950 static void i915_disable_vga(struct drm_device
*dev
)
12952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12954 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12956 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12957 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12958 outb(SR01
, VGA_SR_INDEX
);
12959 sr1
= inb(VGA_SR_DATA
);
12960 outb(sr1
| 1<<5, VGA_SR_DATA
);
12961 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12965 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12966 * from S3 without preserving (some of?) the other bits.
12968 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12969 POSTING_READ(vga_reg
);
12972 void intel_modeset_init_hw(struct drm_device
*dev
)
12974 intel_prepare_ddi(dev
);
12976 if (IS_VALLEYVIEW(dev
))
12977 vlv_update_cdclk(dev
);
12979 intel_init_clock_gating(dev
);
12981 intel_enable_gt_powersave(dev
);
12984 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12986 intel_suspend_hw(dev
);
12989 void intel_modeset_init(struct drm_device
*dev
)
12991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12994 struct intel_crtc
*crtc
;
12996 drm_mode_config_init(dev
);
12998 dev
->mode_config
.min_width
= 0;
12999 dev
->mode_config
.min_height
= 0;
13001 dev
->mode_config
.preferred_depth
= 24;
13002 dev
->mode_config
.prefer_shadow
= 1;
13004 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13006 intel_init_quirks(dev
);
13008 intel_init_pm(dev
);
13010 if (INTEL_INFO(dev
)->num_pipes
== 0)
13013 intel_init_display(dev
);
13015 if (IS_GEN2(dev
)) {
13016 dev
->mode_config
.max_width
= 2048;
13017 dev
->mode_config
.max_height
= 2048;
13018 } else if (IS_GEN3(dev
)) {
13019 dev
->mode_config
.max_width
= 4096;
13020 dev
->mode_config
.max_height
= 4096;
13022 dev
->mode_config
.max_width
= 8192;
13023 dev
->mode_config
.max_height
= 8192;
13026 if (IS_845G(dev
) || IS_I865G(dev
)) {
13027 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13028 dev
->mode_config
.cursor_height
= 1023;
13029 } else if (IS_GEN2(dev
)) {
13030 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13031 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13033 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13034 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13037 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13039 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13040 INTEL_INFO(dev
)->num_pipes
,
13041 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13043 for_each_pipe(dev_priv
, pipe
) {
13044 intel_crtc_init(dev
, pipe
);
13045 for_each_sprite(pipe
, sprite
) {
13046 ret
= intel_plane_init(dev
, pipe
, sprite
);
13048 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13049 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13053 intel_init_dpio(dev
);
13055 intel_shared_dpll_init(dev
);
13057 /* save the BIOS value before clobbering it */
13058 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
13059 /* Just disable it once at startup */
13060 i915_disable_vga(dev
);
13061 intel_setup_outputs(dev
);
13063 /* Just in case the BIOS is doing something questionable. */
13064 intel_disable_fbc(dev
);
13066 drm_modeset_lock_all(dev
);
13067 intel_modeset_setup_hw_state(dev
, false);
13068 drm_modeset_unlock_all(dev
);
13070 for_each_intel_crtc(dev
, crtc
) {
13075 * Note that reserving the BIOS fb up front prevents us
13076 * from stuffing other stolen allocations like the ring
13077 * on top. This prevents some ugliness at boot time, and
13078 * can even allow for smooth boot transitions if the BIOS
13079 * fb is large enough for the active pipe configuration.
13081 if (dev_priv
->display
.get_plane_config
) {
13082 dev_priv
->display
.get_plane_config(crtc
,
13083 &crtc
->plane_config
);
13085 * If the fb is shared between multiple heads, we'll
13086 * just get the first one.
13088 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13093 static void intel_enable_pipe_a(struct drm_device
*dev
)
13095 struct intel_connector
*connector
;
13096 struct drm_connector
*crt
= NULL
;
13097 struct intel_load_detect_pipe load_detect_temp
;
13098 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13100 /* We can't just switch on the pipe A, we need to set things up with a
13101 * proper mode and output configuration. As a gross hack, enable pipe A
13102 * by enabling the load detect pipe once. */
13103 list_for_each_entry(connector
,
13104 &dev
->mode_config
.connector_list
,
13106 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13107 crt
= &connector
->base
;
13115 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13116 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13120 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13122 struct drm_device
*dev
= crtc
->base
.dev
;
13123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13126 if (INTEL_INFO(dev
)->num_pipes
== 1)
13129 reg
= DSPCNTR(!crtc
->plane
);
13130 val
= I915_READ(reg
);
13132 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13133 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13139 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13141 struct drm_device
*dev
= crtc
->base
.dev
;
13142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13145 /* Clear any frame start delays used for debugging left by the BIOS */
13146 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
13147 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13149 /* restore vblank interrupts to correct state */
13150 if (crtc
->active
) {
13151 update_scanline_offset(crtc
);
13152 drm_vblank_on(dev
, crtc
->pipe
);
13154 drm_vblank_off(dev
, crtc
->pipe
);
13156 /* We need to sanitize the plane -> pipe mapping first because this will
13157 * disable the crtc (and hence change the state) if it is wrong. Note
13158 * that gen4+ has a fixed plane -> pipe mapping. */
13159 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13160 struct intel_connector
*connector
;
13163 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13164 crtc
->base
.base
.id
);
13166 /* Pipe has the wrong plane attached and the plane is active.
13167 * Temporarily change the plane mapping and disable everything
13169 plane
= crtc
->plane
;
13170 crtc
->plane
= !plane
;
13171 crtc
->primary_enabled
= true;
13172 dev_priv
->display
.crtc_disable(&crtc
->base
);
13173 crtc
->plane
= plane
;
13175 /* ... and break all links. */
13176 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13178 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13181 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13182 connector
->base
.encoder
= NULL
;
13184 /* multiple connectors may have the same encoder:
13185 * handle them and break crtc link separately */
13186 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13188 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13189 connector
->encoder
->base
.crtc
= NULL
;
13190 connector
->encoder
->connectors_active
= false;
13193 WARN_ON(crtc
->active
);
13194 crtc
->base
.enabled
= false;
13197 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13198 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13199 /* BIOS forgot to enable pipe A, this mostly happens after
13200 * resume. Force-enable the pipe to fix this, the update_dpms
13201 * call below we restore the pipe to the right state, but leave
13202 * the required bits on. */
13203 intel_enable_pipe_a(dev
);
13206 /* Adjust the state of the output pipe according to whether we
13207 * have active connectors/encoders. */
13208 intel_crtc_update_dpms(&crtc
->base
);
13210 if (crtc
->active
!= crtc
->base
.enabled
) {
13211 struct intel_encoder
*encoder
;
13213 /* This can happen either due to bugs in the get_hw_state
13214 * functions or because the pipe is force-enabled due to the
13216 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13217 crtc
->base
.base
.id
,
13218 crtc
->base
.enabled
? "enabled" : "disabled",
13219 crtc
->active
? "enabled" : "disabled");
13221 crtc
->base
.enabled
= crtc
->active
;
13223 /* Because we only establish the connector -> encoder ->
13224 * crtc links if something is active, this means the
13225 * crtc is now deactivated. Break the links. connector
13226 * -> encoder links are only establish when things are
13227 * actually up, hence no need to break them. */
13228 WARN_ON(crtc
->active
);
13230 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13231 WARN_ON(encoder
->connectors_active
);
13232 encoder
->base
.crtc
= NULL
;
13236 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13238 * We start out with underrun reporting disabled to avoid races.
13239 * For correct bookkeeping mark this on active crtcs.
13241 * Also on gmch platforms we dont have any hardware bits to
13242 * disable the underrun reporting. Which means we need to start
13243 * out with underrun reporting disabled also on inactive pipes,
13244 * since otherwise we'll complain about the garbage we read when
13245 * e.g. coming up after runtime pm.
13247 * No protection against concurrent access is required - at
13248 * worst a fifo underrun happens which also sets this to false.
13250 crtc
->cpu_fifo_underrun_disabled
= true;
13251 crtc
->pch_fifo_underrun_disabled
= true;
13255 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13257 struct intel_connector
*connector
;
13258 struct drm_device
*dev
= encoder
->base
.dev
;
13260 /* We need to check both for a crtc link (meaning that the
13261 * encoder is active and trying to read from a pipe) and the
13262 * pipe itself being active. */
13263 bool has_active_crtc
= encoder
->base
.crtc
&&
13264 to_intel_crtc(encoder
->base
.crtc
)->active
;
13266 if (encoder
->connectors_active
&& !has_active_crtc
) {
13267 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13268 encoder
->base
.base
.id
,
13269 encoder
->base
.name
);
13271 /* Connector is active, but has no active pipe. This is
13272 * fallout from our resume register restoring. Disable
13273 * the encoder manually again. */
13274 if (encoder
->base
.crtc
) {
13275 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13276 encoder
->base
.base
.id
,
13277 encoder
->base
.name
);
13278 encoder
->disable(encoder
);
13279 if (encoder
->post_disable
)
13280 encoder
->post_disable(encoder
);
13282 encoder
->base
.crtc
= NULL
;
13283 encoder
->connectors_active
= false;
13285 /* Inconsistent output/port/pipe state happens presumably due to
13286 * a bug in one of the get_hw_state functions. Or someplace else
13287 * in our code, like the register restore mess on resume. Clamp
13288 * things to off as a safer default. */
13289 list_for_each_entry(connector
,
13290 &dev
->mode_config
.connector_list
,
13292 if (connector
->encoder
!= encoder
)
13294 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13295 connector
->base
.encoder
= NULL
;
13298 /* Enabled encoders without active connectors will be fixed in
13299 * the crtc fixup. */
13302 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13305 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13307 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13308 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13309 i915_disable_vga(dev
);
13313 void i915_redisable_vga(struct drm_device
*dev
)
13315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13317 /* This function can be called both from intel_modeset_setup_hw_state or
13318 * at a very early point in our resume sequence, where the power well
13319 * structures are not yet restored. Since this function is at a very
13320 * paranoid "someone might have enabled VGA while we were not looking"
13321 * level, just check if the power well is enabled instead of trying to
13322 * follow the "don't touch the power well if we don't need it" policy
13323 * the rest of the driver uses. */
13324 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13327 i915_redisable_vga_power_on(dev
);
13330 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13332 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13337 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13340 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13344 struct intel_crtc
*crtc
;
13345 struct intel_encoder
*encoder
;
13346 struct intel_connector
*connector
;
13349 for_each_intel_crtc(dev
, crtc
) {
13350 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13352 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13354 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13357 crtc
->base
.enabled
= crtc
->active
;
13358 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13360 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13361 crtc
->base
.base
.id
,
13362 crtc
->active
? "enabled" : "disabled");
13365 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13366 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13368 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13370 for_each_intel_crtc(dev
, crtc
) {
13371 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13374 pll
->refcount
= pll
->active
;
13376 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13377 pll
->name
, pll
->refcount
, pll
->on
);
13380 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13383 for_each_intel_encoder(dev
, encoder
) {
13386 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13387 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13388 encoder
->base
.crtc
= &crtc
->base
;
13389 encoder
->get_config(encoder
, &crtc
->config
);
13391 encoder
->base
.crtc
= NULL
;
13394 encoder
->connectors_active
= false;
13395 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13396 encoder
->base
.base
.id
,
13397 encoder
->base
.name
,
13398 encoder
->base
.crtc
? "enabled" : "disabled",
13402 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13404 if (connector
->get_hw_state(connector
)) {
13405 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13406 connector
->encoder
->connectors_active
= true;
13407 connector
->base
.encoder
= &connector
->encoder
->base
;
13409 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13410 connector
->base
.encoder
= NULL
;
13412 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13413 connector
->base
.base
.id
,
13414 connector
->base
.name
,
13415 connector
->base
.encoder
? "enabled" : "disabled");
13419 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13420 * and i915 state tracking structures. */
13421 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13422 bool force_restore
)
13424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13426 struct intel_crtc
*crtc
;
13427 struct intel_encoder
*encoder
;
13430 intel_modeset_readout_hw_state(dev
);
13433 * Now that we have the config, copy it to each CRTC struct
13434 * Note that this could go away if we move to using crtc_config
13435 * checking everywhere.
13437 for_each_intel_crtc(dev
, crtc
) {
13438 if (crtc
->active
&& i915
.fastboot
) {
13439 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13440 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13441 crtc
->base
.base
.id
);
13442 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13446 /* HW state is read out, now we need to sanitize this mess. */
13447 for_each_intel_encoder(dev
, encoder
) {
13448 intel_sanitize_encoder(encoder
);
13451 for_each_pipe(dev_priv
, pipe
) {
13452 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13453 intel_sanitize_crtc(crtc
);
13454 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13457 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13458 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13460 if (!pll
->on
|| pll
->active
)
13463 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13465 pll
->disable(dev_priv
, pll
);
13469 if (HAS_PCH_SPLIT(dev
))
13470 ilk_wm_get_hw_state(dev
);
13472 if (force_restore
) {
13473 i915_redisable_vga(dev
);
13476 * We need to use raw interfaces for restoring state to avoid
13477 * checking (bogus) intermediate states.
13479 for_each_pipe(dev_priv
, pipe
) {
13480 struct drm_crtc
*crtc
=
13481 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13483 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13484 crtc
->primary
->fb
);
13487 intel_modeset_update_staged_output_state(dev
);
13490 intel_modeset_check_state(dev
);
13493 void intel_modeset_gem_init(struct drm_device
*dev
)
13495 struct drm_crtc
*c
;
13496 struct drm_i915_gem_object
*obj
;
13498 mutex_lock(&dev
->struct_mutex
);
13499 intel_init_gt_powersave(dev
);
13500 mutex_unlock(&dev
->struct_mutex
);
13502 intel_modeset_init_hw(dev
);
13504 intel_setup_overlay(dev
);
13507 * Make sure any fbs we allocated at startup are properly
13508 * pinned & fenced. When we do the allocation it's too early
13511 mutex_lock(&dev
->struct_mutex
);
13512 for_each_crtc(dev
, c
) {
13513 obj
= intel_fb_obj(c
->primary
->fb
);
13517 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13518 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13519 to_intel_crtc(c
)->pipe
);
13520 drm_framebuffer_unreference(c
->primary
->fb
);
13521 c
->primary
->fb
= NULL
;
13524 mutex_unlock(&dev
->struct_mutex
);
13527 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13529 struct drm_connector
*connector
= &intel_connector
->base
;
13531 intel_panel_destroy_backlight(connector
);
13532 drm_connector_unregister(connector
);
13535 void intel_modeset_cleanup(struct drm_device
*dev
)
13537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13538 struct drm_connector
*connector
;
13541 * Interrupts and polling as the first thing to avoid creating havoc.
13542 * Too much stuff here (turning of rps, connectors, ...) would
13543 * experience fancy races otherwise.
13545 drm_irq_uninstall(dev
);
13546 intel_hpd_cancel_work(dev_priv
);
13547 dev_priv
->pm
._irqs_disabled
= true;
13550 * Due to the hpd irq storm handling the hotplug work can re-arm the
13551 * poll handlers. Hence disable polling after hpd handling is shut down.
13553 drm_kms_helper_poll_fini(dev
);
13555 mutex_lock(&dev
->struct_mutex
);
13557 intel_unregister_dsm_handler();
13559 intel_disable_fbc(dev
);
13561 intel_disable_gt_powersave(dev
);
13563 ironlake_teardown_rc6(dev
);
13565 mutex_unlock(&dev
->struct_mutex
);
13567 /* flush any delayed tasks or pending work */
13568 flush_scheduled_work();
13570 /* destroy the backlight and sysfs files before encoders/connectors */
13571 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13572 struct intel_connector
*intel_connector
;
13574 intel_connector
= to_intel_connector(connector
);
13575 intel_connector
->unregister(intel_connector
);
13578 drm_mode_config_cleanup(dev
);
13580 intel_cleanup_overlay(dev
);
13582 mutex_lock(&dev
->struct_mutex
);
13583 intel_cleanup_gt_powersave(dev
);
13584 mutex_unlock(&dev
->struct_mutex
);
13588 * Return which encoder is currently attached for connector.
13590 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13592 return &intel_attached_encoder(connector
)->base
;
13595 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13596 struct intel_encoder
*encoder
)
13598 connector
->encoder
= encoder
;
13599 drm_mode_connector_attach_encoder(&connector
->base
,
13604 * set vga decode state - true == enable VGA decode
13606 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13609 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13612 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13613 DRM_ERROR("failed to read control word\n");
13617 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13621 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13623 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13625 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13626 DRM_ERROR("failed to write control word\n");
13633 struct intel_display_error_state
{
13635 u32 power_well_driver
;
13637 int num_transcoders
;
13639 struct intel_cursor_error_state
{
13644 } cursor
[I915_MAX_PIPES
];
13646 struct intel_pipe_error_state
{
13647 bool power_domain_on
;
13650 } pipe
[I915_MAX_PIPES
];
13652 struct intel_plane_error_state
{
13660 } plane
[I915_MAX_PIPES
];
13662 struct intel_transcoder_error_state
{
13663 bool power_domain_on
;
13664 enum transcoder cpu_transcoder
;
13677 struct intel_display_error_state
*
13678 intel_display_capture_error_state(struct drm_device
*dev
)
13680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13681 struct intel_display_error_state
*error
;
13682 int transcoders
[] = {
13690 if (INTEL_INFO(dev
)->num_pipes
== 0)
13693 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13697 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13698 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13700 for_each_pipe(dev_priv
, i
) {
13701 error
->pipe
[i
].power_domain_on
=
13702 intel_display_power_enabled_unlocked(dev_priv
,
13703 POWER_DOMAIN_PIPE(i
));
13704 if (!error
->pipe
[i
].power_domain_on
)
13707 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13708 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13709 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13711 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13712 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13713 if (INTEL_INFO(dev
)->gen
<= 3) {
13714 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13715 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13717 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13718 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13719 if (INTEL_INFO(dev
)->gen
>= 4) {
13720 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13721 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13724 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13726 if (HAS_GMCH_DISPLAY(dev
))
13727 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13730 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13731 if (HAS_DDI(dev_priv
->dev
))
13732 error
->num_transcoders
++; /* Account for eDP. */
13734 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13735 enum transcoder cpu_transcoder
= transcoders
[i
];
13737 error
->transcoder
[i
].power_domain_on
=
13738 intel_display_power_enabled_unlocked(dev_priv
,
13739 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13740 if (!error
->transcoder
[i
].power_domain_on
)
13743 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13745 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13746 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13747 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13748 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13749 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13750 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13751 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13757 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13760 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13761 struct drm_device
*dev
,
13762 struct intel_display_error_state
*error
)
13764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13770 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13771 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13772 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13773 error
->power_well_driver
);
13774 for_each_pipe(dev_priv
, i
) {
13775 err_printf(m
, "Pipe [%d]:\n", i
);
13776 err_printf(m
, " Power: %s\n",
13777 error
->pipe
[i
].power_domain_on
? "on" : "off");
13778 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13779 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13781 err_printf(m
, "Plane [%d]:\n", i
);
13782 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13783 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13784 if (INTEL_INFO(dev
)->gen
<= 3) {
13785 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13786 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13788 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13789 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13790 if (INTEL_INFO(dev
)->gen
>= 4) {
13791 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13792 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13795 err_printf(m
, "Cursor [%d]:\n", i
);
13796 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13797 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13798 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13801 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13802 err_printf(m
, "CPU transcoder: %c\n",
13803 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13804 err_printf(m
, " Power: %s\n",
13805 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13806 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13807 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13808 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13809 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13810 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13811 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13812 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13816 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13818 struct intel_crtc
*crtc
;
13820 for_each_intel_crtc(dev
, crtc
) {
13821 struct intel_unpin_work
*work
;
13822 unsigned long irqflags
;
13824 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13826 work
= crtc
->unpin_work
;
13828 if (work
&& work
->event
&&
13829 work
->event
->base
.file_priv
== file
) {
13830 kfree(work
->event
);
13831 work
->event
= NULL
;
13834 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);