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drm/i915/skl: Adjust assert_sprites_disabled()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267 state = true;
1268
1269 if (!intel_display_power_enabled(dev_priv,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271 cur_state = false;
1272 } else {
1273 reg = PIPECONF(cpu_transcoder);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & PIPECONF_ENABLE);
1276 }
1277
1278 WARN(cur_state != state,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, bool state)
1285 {
1286 int reg;
1287 u32 val;
1288 bool cur_state;
1289
1290 reg = DSPCNTR(plane);
1291 val = I915_READ(reg);
1292 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293 WARN(cur_state != state,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe)
1303 {
1304 struct drm_device *dev = dev_priv->dev;
1305 int reg, i;
1306 u32 val;
1307 int cur_pipe;
1308
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev)->gen >= 4) {
1311 reg = DSPCNTR(pipe);
1312 val = I915_READ(reg);
1313 WARN(val & DISPLAY_PLANE_ENABLE,
1314 "plane %c assertion failure, should be disabled but not\n",
1315 plane_name(pipe));
1316 return;
1317 }
1318
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv, i) {
1321 reg = DSPCNTR(i);
1322 val = I915_READ(reg);
1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324 DISPPLANE_SEL_PIPE_SHIFT;
1325 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int reg, sprite;
1336 u32 val;
1337
1338 if (INTEL_INFO(dev)->gen >= 9) {
1339 for_each_sprite(pipe, sprite) {
1340 val = I915_READ(PLANE_CTL(pipe, sprite));
1341 WARN(val & PLANE_CTL_ENABLE,
1342 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1343 sprite, pipe_name(pipe));
1344 }
1345 } else if (IS_VALLEYVIEW(dev)) {
1346 for_each_sprite(pipe, sprite) {
1347 reg = SPCNTR(pipe, sprite);
1348 val = I915_READ(reg);
1349 WARN(val & SP_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 sprite_name(pipe, sprite), pipe_name(pipe));
1352 }
1353 } else if (INTEL_INFO(dev)->gen >= 7) {
1354 reg = SPRCTL(pipe);
1355 val = I915_READ(reg);
1356 WARN(val & SPRITE_ENABLE,
1357 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1358 plane_name(pipe), pipe_name(pipe));
1359 } else if (INTEL_INFO(dev)->gen >= 5) {
1360 reg = DVSCNTR(pipe);
1361 val = I915_READ(reg);
1362 WARN(val & DVS_ENABLE,
1363 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(pipe), pipe_name(pipe));
1365 }
1366 }
1367
1368 static void assert_vblank_disabled(struct drm_crtc *crtc)
1369 {
1370 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1371 drm_crtc_vblank_put(crtc);
1372 }
1373
1374 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1375 {
1376 u32 val;
1377 bool enabled;
1378
1379 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1380
1381 val = I915_READ(PCH_DREF_CONTROL);
1382 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1383 DREF_SUPERSPREAD_SOURCE_MASK));
1384 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1385 }
1386
1387 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe)
1389 {
1390 int reg;
1391 u32 val;
1392 bool enabled;
1393
1394 reg = PCH_TRANSCONF(pipe);
1395 val = I915_READ(reg);
1396 enabled = !!(val & TRANS_ENABLE);
1397 WARN(enabled,
1398 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1399 pipe_name(pipe));
1400 }
1401
1402 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe, u32 port_sel, u32 val)
1404 {
1405 if ((val & DP_PORT_EN) == 0)
1406 return false;
1407
1408 if (HAS_PCH_CPT(dev_priv->dev)) {
1409 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1410 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1411 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1412 return false;
1413 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1414 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1415 return false;
1416 } else {
1417 if ((val & DP_PIPE_MASK) != (pipe << 30))
1418 return false;
1419 }
1420 return true;
1421 }
1422
1423 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1424 enum pipe pipe, u32 val)
1425 {
1426 if ((val & SDVO_ENABLE) == 0)
1427 return false;
1428
1429 if (HAS_PCH_CPT(dev_priv->dev)) {
1430 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1431 return false;
1432 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1433 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1434 return false;
1435 } else {
1436 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, u32 val)
1444 {
1445 if ((val & LVDS_PORT_EN) == 0)
1446 return false;
1447
1448 if (HAS_PCH_CPT(dev_priv->dev)) {
1449 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1450 return false;
1451 } else {
1452 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1453 return false;
1454 }
1455 return true;
1456 }
1457
1458 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe, u32 val)
1460 {
1461 if ((val & ADPA_DAC_ENABLE) == 0)
1462 return false;
1463 if (HAS_PCH_CPT(dev_priv->dev)) {
1464 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1465 return false;
1466 } else {
1467 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1468 return false;
1469 }
1470 return true;
1471 }
1472
1473 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg, u32 port_sel)
1475 {
1476 u32 val = I915_READ(reg);
1477 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1478 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1479 reg, pipe_name(pipe));
1480
1481 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1482 && (val & DP_PIPEB_SELECT),
1483 "IBX PCH dp port still using transcoder B\n");
1484 }
1485
1486 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, int reg)
1488 {
1489 u32 val = I915_READ(reg);
1490 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1491 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1492 reg, pipe_name(pipe));
1493
1494 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1495 && (val & SDVO_PIPE_B_SELECT),
1496 "IBX PCH hdmi port still using transcoder B\n");
1497 }
1498
1499 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1500 enum pipe pipe)
1501 {
1502 int reg;
1503 u32 val;
1504
1505 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1506 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1507 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1508
1509 reg = PCH_ADPA;
1510 val = I915_READ(reg);
1511 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1512 "PCH VGA enabled on transcoder %c, should be disabled\n",
1513 pipe_name(pipe));
1514
1515 reg = PCH_LVDS;
1516 val = I915_READ(reg);
1517 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1518 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1519 pipe_name(pipe));
1520
1521 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1522 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1523 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1524 }
1525
1526 static void intel_init_dpio(struct drm_device *dev)
1527 {
1528 struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530 if (!IS_VALLEYVIEW(dev))
1531 return;
1532
1533 /*
1534 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1535 * CHV x1 PHY (DP/HDMI D)
1536 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1537 */
1538 if (IS_CHERRYVIEW(dev)) {
1539 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1540 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1541 } else {
1542 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1543 }
1544 }
1545
1546 static void vlv_enable_pll(struct intel_crtc *crtc)
1547 {
1548 struct drm_device *dev = crtc->base.dev;
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 int reg = DPLL(crtc->pipe);
1551 u32 dpll = crtc->config.dpll_hw_state.dpll;
1552
1553 assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555 /* No really, not for ILK+ */
1556 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1557
1558 /* PLL is protected by panel, make sure we can write it */
1559 if (IS_MOBILE(dev_priv->dev))
1560 assert_panel_unlocked(dev_priv, crtc->pipe);
1561
1562 I915_WRITE(reg, dpll);
1563 POSTING_READ(reg);
1564 udelay(150);
1565
1566 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1567 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1568
1569 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1570 POSTING_READ(DPLL_MD(crtc->pipe));
1571
1572 /* We do this three times for luck */
1573 I915_WRITE(reg, dpll);
1574 POSTING_READ(reg);
1575 udelay(150); /* wait for warmup */
1576 I915_WRITE(reg, dpll);
1577 POSTING_READ(reg);
1578 udelay(150); /* wait for warmup */
1579 I915_WRITE(reg, dpll);
1580 POSTING_READ(reg);
1581 udelay(150); /* wait for warmup */
1582 }
1583
1584 static void chv_enable_pll(struct intel_crtc *crtc)
1585 {
1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int pipe = crtc->pipe;
1589 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1590 u32 tmp;
1591
1592 assert_pipe_disabled(dev_priv, crtc->pipe);
1593
1594 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1595
1596 mutex_lock(&dev_priv->dpio_lock);
1597
1598 /* Enable back the 10bit clock to display controller */
1599 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1600 tmp |= DPIO_DCLKP_EN;
1601 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1602
1603 /*
1604 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1605 */
1606 udelay(1);
1607
1608 /* Enable PLL */
1609 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1610
1611 /* Check PLL is locked */
1612 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1613 DRM_ERROR("PLL %d failed to lock\n", pipe);
1614
1615 /* not sure when this should be written */
1616 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1617 POSTING_READ(DPLL_MD(pipe));
1618
1619 mutex_unlock(&dev_priv->dpio_lock);
1620 }
1621
1622 static void i9xx_enable_pll(struct intel_crtc *crtc)
1623 {
1624 struct drm_device *dev = crtc->base.dev;
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 int reg = DPLL(crtc->pipe);
1627 u32 dpll = crtc->config.dpll_hw_state.dpll;
1628
1629 assert_pipe_disabled(dev_priv, crtc->pipe);
1630
1631 /* No really, not for ILK+ */
1632 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1633
1634 /* PLL is protected by panel, make sure we can write it */
1635 if (IS_MOBILE(dev) && !IS_I830(dev))
1636 assert_panel_unlocked(dev_priv, crtc->pipe);
1637
1638 I915_WRITE(reg, dpll);
1639
1640 /* Wait for the clocks to stabilize. */
1641 POSTING_READ(reg);
1642 udelay(150);
1643
1644 if (INTEL_INFO(dev)->gen >= 4) {
1645 I915_WRITE(DPLL_MD(crtc->pipe),
1646 crtc->config.dpll_hw_state.dpll_md);
1647 } else {
1648 /* The pixel multiplier can only be updated once the
1649 * DPLL is enabled and the clocks are stable.
1650 *
1651 * So write it again.
1652 */
1653 I915_WRITE(reg, dpll);
1654 }
1655
1656 /* We do this three times for luck */
1657 I915_WRITE(reg, dpll);
1658 POSTING_READ(reg);
1659 udelay(150); /* wait for warmup */
1660 I915_WRITE(reg, dpll);
1661 POSTING_READ(reg);
1662 udelay(150); /* wait for warmup */
1663 I915_WRITE(reg, dpll);
1664 POSTING_READ(reg);
1665 udelay(150); /* wait for warmup */
1666 }
1667
1668 /**
1669 * i9xx_disable_pll - disable a PLL
1670 * @dev_priv: i915 private structure
1671 * @pipe: pipe PLL to disable
1672 *
1673 * Disable the PLL for @pipe, making sure the pipe is off first.
1674 *
1675 * Note! This is for pre-ILK only.
1676 */
1677 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1678 {
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
1698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
1702 if (pipe == PIPE_B)
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712 u32 val;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
1742 mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1747 {
1748 u32 port_mask;
1749 int dpll_reg;
1750
1751 switch (dport->port) {
1752 case PORT_B:
1753 port_mask = DPLL_PORTB_READY_MASK;
1754 dpll_reg = DPLL(0);
1755 break;
1756 case PORT_C:
1757 port_mask = DPLL_PORTC_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1763 break;
1764 default:
1765 BUG();
1766 }
1767
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779 if (WARN_ON(pll == NULL))
1780 return;
1781
1782 WARN_ON(!pll->refcount);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790 }
1791
1792 /**
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->refcount == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (pll->active++) {
1817 WARN_ON(!pll->on);
1818 assert_shared_dpll_enabled(dev_priv, pll);
1819 return;
1820 }
1821 WARN_ON(pll->on);
1822
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1827 pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
1841 if (WARN_ON(pll->refcount == 0))
1842 return;
1843
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1847
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850 return;
1851 }
1852
1853 assert_shared_dpll_enabled(dev_priv, pll);
1854 WARN_ON(!pll->on);
1855 if (--pll->active)
1856 return;
1857
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1860 pll->on = false;
1861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1872
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1891 }
1892
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904 }
1905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
1913 else
1914 val |= TRANS_PROGRESSIVE;
1915
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1923 {
1924 u32 val, pipeconf_val;
1925
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938 val = TRANS_ENABLE;
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1944 else
1945 val |= TRANS_PROGRESSIVE;
1946
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
1954 {
1955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
1957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984 u32 val;
1985
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2002 *
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005 */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
2013 enum pipe pch_transcoder;
2014 int reg;
2015 u32 val;
2016
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2020
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
2026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
2036 else {
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051 return;
2052 }
2053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2055 POSTING_READ(reg);
2056 }
2057
2058 /**
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2061 *
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
2118 }
2119
2120 /**
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2124 *
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2126 */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2129 {
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137 if (intel_crtc->primary_enabled)
2138 return;
2139
2140 intel_crtc->primary_enabled = true;
2141
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
2144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2158 *
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2160 */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2163 {
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (!intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = false;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184 #endif
2185 return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2198 struct drm_i915_gem_object *obj,
2199 struct intel_engine_cs *pipelined)
2200 {
2201 struct drm_i915_private *dev_priv = dev->dev_private;
2202 u32 alignment;
2203 int ret;
2204
2205 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2206
2207 switch (obj->tiling_mode) {
2208 case I915_TILING_NONE:
2209 if (INTEL_INFO(dev)->gen >= 9)
2210 alignment = 256 * 1024;
2211 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2212 alignment = 128 * 1024;
2213 else if (INTEL_INFO(dev)->gen >= 4)
2214 alignment = 4 * 1024;
2215 else
2216 alignment = 64 * 1024;
2217 break;
2218 case I915_TILING_X:
2219 if (INTEL_INFO(dev)->gen >= 9)
2220 alignment = 256 * 1024;
2221 else {
2222 /* pin() will align the object as required by fence */
2223 alignment = 0;
2224 }
2225 break;
2226 case I915_TILING_Y:
2227 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2228 return -EINVAL;
2229 default:
2230 BUG();
2231 }
2232
2233 /* Note that the w/a also requires 64 PTE of padding following the
2234 * bo. We currently fill all unused PTE with the shadow page and so
2235 * we should always have valid PTE following the scanout preventing
2236 * the VT-d warning.
2237 */
2238 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2239 alignment = 256 * 1024;
2240
2241 /*
2242 * Global gtt pte registers are special registers which actually forward
2243 * writes to a chunk of system memory. Which means that there is no risk
2244 * that the register values disappear as soon as we call
2245 * intel_runtime_pm_put(), so it is correct to wrap only the
2246 * pin/unpin/fence and not more.
2247 */
2248 intel_runtime_pm_get(dev_priv);
2249
2250 dev_priv->mm.interruptible = false;
2251 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2252 if (ret)
2253 goto err_interruptible;
2254
2255 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2256 * fence, whereas 965+ only requires a fence if using
2257 * framebuffer compression. For simplicity, we always install
2258 * a fence as the cost is not that onerous.
2259 */
2260 ret = i915_gem_object_get_fence(obj);
2261 if (ret)
2262 goto err_unpin;
2263
2264 i915_gem_object_pin_fence(obj);
2265
2266 dev_priv->mm.interruptible = true;
2267 intel_runtime_pm_put(dev_priv);
2268 return 0;
2269
2270 err_unpin:
2271 i915_gem_object_unpin_from_display_plane(obj);
2272 err_interruptible:
2273 dev_priv->mm.interruptible = true;
2274 intel_runtime_pm_put(dev_priv);
2275 return ret;
2276 }
2277
2278 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2279 {
2280 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2281
2282 i915_gem_object_unpin_fence(obj);
2283 i915_gem_object_unpin_from_display_plane(obj);
2284 }
2285
2286 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2287 * is assumed to be a power-of-two. */
2288 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2289 unsigned int tiling_mode,
2290 unsigned int cpp,
2291 unsigned int pitch)
2292 {
2293 if (tiling_mode != I915_TILING_NONE) {
2294 unsigned int tile_rows, tiles;
2295
2296 tile_rows = *y / 8;
2297 *y %= 8;
2298
2299 tiles = *x / (512/cpp);
2300 *x %= 512/cpp;
2301
2302 return tile_rows * pitch * 8 + tiles * 4096;
2303 } else {
2304 unsigned int offset;
2305
2306 offset = *y * pitch + *x * cpp;
2307 *y = 0;
2308 *x = (offset & 4095) / cpp;
2309 return offset & -4096;
2310 }
2311 }
2312
2313 int intel_format_to_fourcc(int format)
2314 {
2315 switch (format) {
2316 case DISPPLANE_8BPP:
2317 return DRM_FORMAT_C8;
2318 case DISPPLANE_BGRX555:
2319 return DRM_FORMAT_XRGB1555;
2320 case DISPPLANE_BGRX565:
2321 return DRM_FORMAT_RGB565;
2322 default:
2323 case DISPPLANE_BGRX888:
2324 return DRM_FORMAT_XRGB8888;
2325 case DISPPLANE_RGBX888:
2326 return DRM_FORMAT_XBGR8888;
2327 case DISPPLANE_BGRX101010:
2328 return DRM_FORMAT_XRGB2101010;
2329 case DISPPLANE_RGBX101010:
2330 return DRM_FORMAT_XBGR2101010;
2331 }
2332 }
2333
2334 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2335 struct intel_plane_config *plane_config)
2336 {
2337 struct drm_device *dev = crtc->base.dev;
2338 struct drm_i915_gem_object *obj = NULL;
2339 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2340 u32 base = plane_config->base;
2341
2342 if (plane_config->size == 0)
2343 return false;
2344
2345 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2346 plane_config->size);
2347 if (!obj)
2348 return false;
2349
2350 if (plane_config->tiled) {
2351 obj->tiling_mode = I915_TILING_X;
2352 obj->stride = crtc->base.primary->fb->pitches[0];
2353 }
2354
2355 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2356 mode_cmd.width = crtc->base.primary->fb->width;
2357 mode_cmd.height = crtc->base.primary->fb->height;
2358 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2359
2360 mutex_lock(&dev->struct_mutex);
2361
2362 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2363 &mode_cmd, obj)) {
2364 DRM_DEBUG_KMS("intel fb init failed\n");
2365 goto out_unref_obj;
2366 }
2367
2368 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2369 mutex_unlock(&dev->struct_mutex);
2370
2371 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2372 return true;
2373
2374 out_unref_obj:
2375 drm_gem_object_unreference(&obj->base);
2376 mutex_unlock(&dev->struct_mutex);
2377 return false;
2378 }
2379
2380 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2381 struct intel_plane_config *plane_config)
2382 {
2383 struct drm_device *dev = intel_crtc->base.dev;
2384 struct drm_crtc *c;
2385 struct intel_crtc *i;
2386 struct drm_i915_gem_object *obj;
2387
2388 if (!intel_crtc->base.primary->fb)
2389 return;
2390
2391 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2392 return;
2393
2394 kfree(intel_crtc->base.primary->fb);
2395 intel_crtc->base.primary->fb = NULL;
2396
2397 /*
2398 * Failed to alloc the obj, check to see if we should share
2399 * an fb with another CRTC instead
2400 */
2401 for_each_crtc(dev, c) {
2402 i = to_intel_crtc(c);
2403
2404 if (c == &intel_crtc->base)
2405 continue;
2406
2407 if (!i->active)
2408 continue;
2409
2410 obj = intel_fb_obj(c->primary->fb);
2411 if (obj == NULL)
2412 continue;
2413
2414 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2415 drm_framebuffer_reference(c->primary->fb);
2416 intel_crtc->base.primary->fb = c->primary->fb;
2417 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2418 break;
2419 }
2420 }
2421 }
2422
2423 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2424 struct drm_framebuffer *fb,
2425 int x, int y)
2426 {
2427 struct drm_device *dev = crtc->dev;
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2430 struct drm_i915_gem_object *obj;
2431 int plane = intel_crtc->plane;
2432 unsigned long linear_offset;
2433 u32 dspcntr;
2434 u32 reg = DSPCNTR(plane);
2435 int pixel_size;
2436
2437 if (!intel_crtc->primary_enabled) {
2438 I915_WRITE(reg, 0);
2439 if (INTEL_INFO(dev)->gen >= 4)
2440 I915_WRITE(DSPSURF(plane), 0);
2441 else
2442 I915_WRITE(DSPADDR(plane), 0);
2443 POSTING_READ(reg);
2444 return;
2445 }
2446
2447 obj = intel_fb_obj(fb);
2448 if (WARN_ON(obj == NULL))
2449 return;
2450
2451 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2452
2453 dspcntr = DISPPLANE_GAMMA_ENABLE;
2454
2455 dspcntr |= DISPLAY_PLANE_ENABLE;
2456
2457 if (INTEL_INFO(dev)->gen < 4) {
2458 if (intel_crtc->pipe == PIPE_B)
2459 dspcntr |= DISPPLANE_SEL_PIPE_B;
2460
2461 /* pipesrc and dspsize control the size that is scaled from,
2462 * which should always be the user's requested size.
2463 */
2464 I915_WRITE(DSPSIZE(plane),
2465 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2466 (intel_crtc->config.pipe_src_w - 1));
2467 I915_WRITE(DSPPOS(plane), 0);
2468 }
2469
2470 switch (fb->pixel_format) {
2471 case DRM_FORMAT_C8:
2472 dspcntr |= DISPPLANE_8BPP;
2473 break;
2474 case DRM_FORMAT_XRGB1555:
2475 case DRM_FORMAT_ARGB1555:
2476 dspcntr |= DISPPLANE_BGRX555;
2477 break;
2478 case DRM_FORMAT_RGB565:
2479 dspcntr |= DISPPLANE_BGRX565;
2480 break;
2481 case DRM_FORMAT_XRGB8888:
2482 case DRM_FORMAT_ARGB8888:
2483 dspcntr |= DISPPLANE_BGRX888;
2484 break;
2485 case DRM_FORMAT_XBGR8888:
2486 case DRM_FORMAT_ABGR8888:
2487 dspcntr |= DISPPLANE_RGBX888;
2488 break;
2489 case DRM_FORMAT_XRGB2101010:
2490 case DRM_FORMAT_ARGB2101010:
2491 dspcntr |= DISPPLANE_BGRX101010;
2492 break;
2493 case DRM_FORMAT_XBGR2101010:
2494 case DRM_FORMAT_ABGR2101010:
2495 dspcntr |= DISPPLANE_RGBX101010;
2496 break;
2497 default:
2498 BUG();
2499 }
2500
2501 if (INTEL_INFO(dev)->gen >= 4 &&
2502 obj->tiling_mode != I915_TILING_NONE)
2503 dspcntr |= DISPPLANE_TILED;
2504
2505 if (IS_G4X(dev))
2506 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2507
2508 linear_offset = y * fb->pitches[0] + x * pixel_size;
2509
2510 if (INTEL_INFO(dev)->gen >= 4) {
2511 intel_crtc->dspaddr_offset =
2512 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2513 pixel_size,
2514 fb->pitches[0]);
2515 linear_offset -= intel_crtc->dspaddr_offset;
2516 } else {
2517 intel_crtc->dspaddr_offset = linear_offset;
2518 }
2519
2520 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2521 dspcntr |= DISPPLANE_ROTATE_180;
2522
2523 x += (intel_crtc->config.pipe_src_w - 1);
2524 y += (intel_crtc->config.pipe_src_h - 1);
2525
2526 /* Finding the last pixel of the last line of the display
2527 data and adding to linear_offset*/
2528 linear_offset +=
2529 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2530 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2531 }
2532
2533 I915_WRITE(reg, dspcntr);
2534
2535 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2536 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2537 fb->pitches[0]);
2538 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2539 if (INTEL_INFO(dev)->gen >= 4) {
2540 I915_WRITE(DSPSURF(plane),
2541 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2542 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2543 I915_WRITE(DSPLINOFF(plane), linear_offset);
2544 } else
2545 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2546 POSTING_READ(reg);
2547 }
2548
2549 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2550 struct drm_framebuffer *fb,
2551 int x, int y)
2552 {
2553 struct drm_device *dev = crtc->dev;
2554 struct drm_i915_private *dev_priv = dev->dev_private;
2555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2556 struct drm_i915_gem_object *obj;
2557 int plane = intel_crtc->plane;
2558 unsigned long linear_offset;
2559 u32 dspcntr;
2560 u32 reg = DSPCNTR(plane);
2561 int pixel_size;
2562
2563 if (!intel_crtc->primary_enabled) {
2564 I915_WRITE(reg, 0);
2565 I915_WRITE(DSPSURF(plane), 0);
2566 POSTING_READ(reg);
2567 return;
2568 }
2569
2570 obj = intel_fb_obj(fb);
2571 if (WARN_ON(obj == NULL))
2572 return;
2573
2574 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2575
2576 dspcntr = DISPPLANE_GAMMA_ENABLE;
2577
2578 dspcntr |= DISPLAY_PLANE_ENABLE;
2579
2580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2581 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2582
2583 switch (fb->pixel_format) {
2584 case DRM_FORMAT_C8:
2585 dspcntr |= DISPPLANE_8BPP;
2586 break;
2587 case DRM_FORMAT_RGB565:
2588 dspcntr |= DISPPLANE_BGRX565;
2589 break;
2590 case DRM_FORMAT_XRGB8888:
2591 case DRM_FORMAT_ARGB8888:
2592 dspcntr |= DISPPLANE_BGRX888;
2593 break;
2594 case DRM_FORMAT_XBGR8888:
2595 case DRM_FORMAT_ABGR8888:
2596 dspcntr |= DISPPLANE_RGBX888;
2597 break;
2598 case DRM_FORMAT_XRGB2101010:
2599 case DRM_FORMAT_ARGB2101010:
2600 dspcntr |= DISPPLANE_BGRX101010;
2601 break;
2602 case DRM_FORMAT_XBGR2101010:
2603 case DRM_FORMAT_ABGR2101010:
2604 dspcntr |= DISPPLANE_RGBX101010;
2605 break;
2606 default:
2607 BUG();
2608 }
2609
2610 if (obj->tiling_mode != I915_TILING_NONE)
2611 dspcntr |= DISPPLANE_TILED;
2612
2613 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2614 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2615
2616 linear_offset = y * fb->pitches[0] + x * pixel_size;
2617 intel_crtc->dspaddr_offset =
2618 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2619 pixel_size,
2620 fb->pitches[0]);
2621 linear_offset -= intel_crtc->dspaddr_offset;
2622 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2623 dspcntr |= DISPPLANE_ROTATE_180;
2624
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2626 x += (intel_crtc->config.pipe_src_w - 1);
2627 y += (intel_crtc->config.pipe_src_h - 1);
2628
2629 /* Finding the last pixel of the last line of the display
2630 data and adding to linear_offset*/
2631 linear_offset +=
2632 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2633 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2634 }
2635 }
2636
2637 I915_WRITE(reg, dspcntr);
2638
2639 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2640 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2641 fb->pitches[0]);
2642 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2643 I915_WRITE(DSPSURF(plane),
2644 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2645 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2646 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2647 } else {
2648 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2649 I915_WRITE(DSPLINOFF(plane), linear_offset);
2650 }
2651 POSTING_READ(reg);
2652 }
2653
2654 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2655 struct drm_framebuffer *fb,
2656 int x, int y)
2657 {
2658 struct drm_device *dev = crtc->dev;
2659 struct drm_i915_private *dev_priv = dev->dev_private;
2660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661 struct intel_framebuffer *intel_fb;
2662 struct drm_i915_gem_object *obj;
2663 int pipe = intel_crtc->pipe;
2664 u32 plane_ctl, stride;
2665
2666 if (!intel_crtc->primary_enabled) {
2667 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2668 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2669 POSTING_READ(PLANE_CTL(pipe, 0));
2670 return;
2671 }
2672
2673 plane_ctl = PLANE_CTL_ENABLE |
2674 PLANE_CTL_PIPE_GAMMA_ENABLE |
2675 PLANE_CTL_PIPE_CSC_ENABLE;
2676
2677 switch (fb->pixel_format) {
2678 case DRM_FORMAT_RGB565:
2679 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2680 break;
2681 case DRM_FORMAT_XRGB8888:
2682 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2683 break;
2684 case DRM_FORMAT_XBGR8888:
2685 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2686 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2687 break;
2688 case DRM_FORMAT_XRGB2101010:
2689 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2690 break;
2691 case DRM_FORMAT_XBGR2101010:
2692 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2693 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2694 break;
2695 default:
2696 BUG();
2697 }
2698
2699 intel_fb = to_intel_framebuffer(fb);
2700 obj = intel_fb->obj;
2701
2702 /*
2703 * The stride is either expressed as a multiple of 64 bytes chunks for
2704 * linear buffers or in number of tiles for tiled buffers.
2705 */
2706 switch (obj->tiling_mode) {
2707 case I915_TILING_NONE:
2708 stride = fb->pitches[0] >> 6;
2709 break;
2710 case I915_TILING_X:
2711 plane_ctl |= PLANE_CTL_TILED_X;
2712 stride = fb->pitches[0] >> 9;
2713 break;
2714 default:
2715 BUG();
2716 }
2717
2718 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2719
2720 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2721
2722 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2723 i915_gem_obj_ggtt_offset(obj),
2724 x, y, fb->width, fb->height,
2725 fb->pitches[0]);
2726
2727 I915_WRITE(PLANE_POS(pipe, 0), 0);
2728 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2729 I915_WRITE(PLANE_SIZE(pipe, 0),
2730 (intel_crtc->config.pipe_src_h - 1) << 16 |
2731 (intel_crtc->config.pipe_src_w - 1));
2732 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2733 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2734
2735 POSTING_READ(PLANE_SURF(pipe, 0));
2736 }
2737
2738 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2739 static int
2740 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2741 int x, int y, enum mode_set_atomic state)
2742 {
2743 struct drm_device *dev = crtc->dev;
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745
2746 if (dev_priv->display.disable_fbc)
2747 dev_priv->display.disable_fbc(dev);
2748 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2749
2750 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2751
2752 return 0;
2753 }
2754
2755 void intel_display_handle_reset(struct drm_device *dev)
2756 {
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct drm_crtc *crtc;
2759
2760 /*
2761 * Flips in the rings have been nuked by the reset,
2762 * so complete all pending flips so that user space
2763 * will get its events and not get stuck.
2764 *
2765 * Also update the base address of all primary
2766 * planes to the the last fb to make sure we're
2767 * showing the correct fb after a reset.
2768 *
2769 * Need to make two loops over the crtcs so that we
2770 * don't try to grab a crtc mutex before the
2771 * pending_flip_queue really got woken up.
2772 */
2773
2774 for_each_crtc(dev, crtc) {
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 enum plane plane = intel_crtc->plane;
2777
2778 intel_prepare_page_flip(dev, plane);
2779 intel_finish_page_flip_plane(dev, plane);
2780 }
2781
2782 for_each_crtc(dev, crtc) {
2783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2784
2785 drm_modeset_lock(&crtc->mutex, NULL);
2786 /*
2787 * FIXME: Once we have proper support for primary planes (and
2788 * disabling them without disabling the entire crtc) allow again
2789 * a NULL crtc->primary->fb.
2790 */
2791 if (intel_crtc->active && crtc->primary->fb)
2792 dev_priv->display.update_primary_plane(crtc,
2793 crtc->primary->fb,
2794 crtc->x,
2795 crtc->y);
2796 drm_modeset_unlock(&crtc->mutex);
2797 }
2798 }
2799
2800 static int
2801 intel_finish_fb(struct drm_framebuffer *old_fb)
2802 {
2803 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2804 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2805 bool was_interruptible = dev_priv->mm.interruptible;
2806 int ret;
2807
2808 /* Big Hammer, we also need to ensure that any pending
2809 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2810 * current scanout is retired before unpinning the old
2811 * framebuffer.
2812 *
2813 * This should only fail upon a hung GPU, in which case we
2814 * can safely continue.
2815 */
2816 dev_priv->mm.interruptible = false;
2817 ret = i915_gem_object_finish_gpu(obj);
2818 dev_priv->mm.interruptible = was_interruptible;
2819
2820 return ret;
2821 }
2822
2823 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2824 {
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828 unsigned long flags;
2829 bool pending;
2830
2831 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2832 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2833 return false;
2834
2835 spin_lock_irqsave(&dev->event_lock, flags);
2836 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2837 spin_unlock_irqrestore(&dev->event_lock, flags);
2838
2839 return pending;
2840 }
2841
2842 static int
2843 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2844 struct drm_framebuffer *fb)
2845 {
2846 struct drm_device *dev = crtc->dev;
2847 struct drm_i915_private *dev_priv = dev->dev_private;
2848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2849 enum pipe pipe = intel_crtc->pipe;
2850 struct drm_framebuffer *old_fb = crtc->primary->fb;
2851 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2852 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2853 int ret;
2854
2855 if (intel_crtc_has_pending_flip(crtc)) {
2856 DRM_ERROR("pipe is still busy with an old pageflip\n");
2857 return -EBUSY;
2858 }
2859
2860 /* no fb bound */
2861 if (!fb) {
2862 DRM_ERROR("No FB bound\n");
2863 return 0;
2864 }
2865
2866 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2867 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2868 plane_name(intel_crtc->plane),
2869 INTEL_INFO(dev)->num_pipes);
2870 return -EINVAL;
2871 }
2872
2873 mutex_lock(&dev->struct_mutex);
2874 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2875 if (ret == 0)
2876 i915_gem_track_fb(old_obj, obj,
2877 INTEL_FRONTBUFFER_PRIMARY(pipe));
2878 mutex_unlock(&dev->struct_mutex);
2879 if (ret != 0) {
2880 DRM_ERROR("pin & fence failed\n");
2881 return ret;
2882 }
2883
2884 /*
2885 * Update pipe size and adjust fitter if needed: the reason for this is
2886 * that in compute_mode_changes we check the native mode (not the pfit
2887 * mode) to see if we can flip rather than do a full mode set. In the
2888 * fastboot case, we'll flip, but if we don't update the pipesrc and
2889 * pfit state, we'll end up with a big fb scanned out into the wrong
2890 * sized surface.
2891 *
2892 * To fix this properly, we need to hoist the checks up into
2893 * compute_mode_changes (or above), check the actual pfit state and
2894 * whether the platform allows pfit disable with pipe active, and only
2895 * then update the pipesrc and pfit state, even on the flip path.
2896 */
2897 if (i915.fastboot) {
2898 const struct drm_display_mode *adjusted_mode =
2899 &intel_crtc->config.adjusted_mode;
2900
2901 I915_WRITE(PIPESRC(intel_crtc->pipe),
2902 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2903 (adjusted_mode->crtc_vdisplay - 1));
2904 if (!intel_crtc->config.pch_pfit.enabled &&
2905 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2906 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2907 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2908 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2909 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2910 }
2911 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2912 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2913 }
2914
2915 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2916
2917 if (intel_crtc->active)
2918 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2919
2920 crtc->primary->fb = fb;
2921 crtc->x = x;
2922 crtc->y = y;
2923
2924 if (old_fb) {
2925 if (intel_crtc->active && old_fb != fb)
2926 intel_wait_for_vblank(dev, intel_crtc->pipe);
2927 mutex_lock(&dev->struct_mutex);
2928 intel_unpin_fb_obj(old_obj);
2929 mutex_unlock(&dev->struct_mutex);
2930 }
2931
2932 mutex_lock(&dev->struct_mutex);
2933 intel_update_fbc(dev);
2934 mutex_unlock(&dev->struct_mutex);
2935
2936 return 0;
2937 }
2938
2939 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2940 {
2941 struct drm_device *dev = crtc->dev;
2942 struct drm_i915_private *dev_priv = dev->dev_private;
2943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2944 int pipe = intel_crtc->pipe;
2945 u32 reg, temp;
2946
2947 /* enable normal train */
2948 reg = FDI_TX_CTL(pipe);
2949 temp = I915_READ(reg);
2950 if (IS_IVYBRIDGE(dev)) {
2951 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2952 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2953 } else {
2954 temp &= ~FDI_LINK_TRAIN_NONE;
2955 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2956 }
2957 I915_WRITE(reg, temp);
2958
2959 reg = FDI_RX_CTL(pipe);
2960 temp = I915_READ(reg);
2961 if (HAS_PCH_CPT(dev)) {
2962 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2963 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2964 } else {
2965 temp &= ~FDI_LINK_TRAIN_NONE;
2966 temp |= FDI_LINK_TRAIN_NONE;
2967 }
2968 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2969
2970 /* wait one idle pattern time */
2971 POSTING_READ(reg);
2972 udelay(1000);
2973
2974 /* IVB wants error correction enabled */
2975 if (IS_IVYBRIDGE(dev))
2976 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2977 FDI_FE_ERRC_ENABLE);
2978 }
2979
2980 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2981 {
2982 return crtc->base.enabled && crtc->active &&
2983 crtc->config.has_pch_encoder;
2984 }
2985
2986 static void ivb_modeset_global_resources(struct drm_device *dev)
2987 {
2988 struct drm_i915_private *dev_priv = dev->dev_private;
2989 struct intel_crtc *pipe_B_crtc =
2990 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2991 struct intel_crtc *pipe_C_crtc =
2992 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2993 uint32_t temp;
2994
2995 /*
2996 * When everything is off disable fdi C so that we could enable fdi B
2997 * with all lanes. Note that we don't care about enabled pipes without
2998 * an enabled pch encoder.
2999 */
3000 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3001 !pipe_has_enabled_pch(pipe_C_crtc)) {
3002 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3003 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3004
3005 temp = I915_READ(SOUTH_CHICKEN1);
3006 temp &= ~FDI_BC_BIFURCATION_SELECT;
3007 DRM_DEBUG_KMS("disabling fdi C rx\n");
3008 I915_WRITE(SOUTH_CHICKEN1, temp);
3009 }
3010 }
3011
3012 /* The FDI link training functions for ILK/Ibexpeak. */
3013 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3014 {
3015 struct drm_device *dev = crtc->dev;
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3018 int pipe = intel_crtc->pipe;
3019 u32 reg, temp, tries;
3020
3021 /* FDI needs bits from pipe first */
3022 assert_pipe_enabled(dev_priv, pipe);
3023
3024 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3025 for train result */
3026 reg = FDI_RX_IMR(pipe);
3027 temp = I915_READ(reg);
3028 temp &= ~FDI_RX_SYMBOL_LOCK;
3029 temp &= ~FDI_RX_BIT_LOCK;
3030 I915_WRITE(reg, temp);
3031 I915_READ(reg);
3032 udelay(150);
3033
3034 /* enable CPU FDI TX and PCH FDI RX */
3035 reg = FDI_TX_CTL(pipe);
3036 temp = I915_READ(reg);
3037 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3038 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_1;
3041 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3042
3043 reg = FDI_RX_CTL(pipe);
3044 temp = I915_READ(reg);
3045 temp &= ~FDI_LINK_TRAIN_NONE;
3046 temp |= FDI_LINK_TRAIN_PATTERN_1;
3047 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3048
3049 POSTING_READ(reg);
3050 udelay(150);
3051
3052 /* Ironlake workaround, enable clock pointer after FDI enable*/
3053 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3054 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3055 FDI_RX_PHASE_SYNC_POINTER_EN);
3056
3057 reg = FDI_RX_IIR(pipe);
3058 for (tries = 0; tries < 5; tries++) {
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061
3062 if ((temp & FDI_RX_BIT_LOCK)) {
3063 DRM_DEBUG_KMS("FDI train 1 done.\n");
3064 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3065 break;
3066 }
3067 }
3068 if (tries == 5)
3069 DRM_ERROR("FDI train 1 fail!\n");
3070
3071 /* Train 2 */
3072 reg = FDI_TX_CTL(pipe);
3073 temp = I915_READ(reg);
3074 temp &= ~FDI_LINK_TRAIN_NONE;
3075 temp |= FDI_LINK_TRAIN_PATTERN_2;
3076 I915_WRITE(reg, temp);
3077
3078 reg = FDI_RX_CTL(pipe);
3079 temp = I915_READ(reg);
3080 temp &= ~FDI_LINK_TRAIN_NONE;
3081 temp |= FDI_LINK_TRAIN_PATTERN_2;
3082 I915_WRITE(reg, temp);
3083
3084 POSTING_READ(reg);
3085 udelay(150);
3086
3087 reg = FDI_RX_IIR(pipe);
3088 for (tries = 0; tries < 5; tries++) {
3089 temp = I915_READ(reg);
3090 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3091
3092 if (temp & FDI_RX_SYMBOL_LOCK) {
3093 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3094 DRM_DEBUG_KMS("FDI train 2 done.\n");
3095 break;
3096 }
3097 }
3098 if (tries == 5)
3099 DRM_ERROR("FDI train 2 fail!\n");
3100
3101 DRM_DEBUG_KMS("FDI train done\n");
3102
3103 }
3104
3105 static const int snb_b_fdi_train_param[] = {
3106 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3107 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3108 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3109 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3110 };
3111
3112 /* The FDI link training functions for SNB/Cougarpoint. */
3113 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3114 {
3115 struct drm_device *dev = crtc->dev;
3116 struct drm_i915_private *dev_priv = dev->dev_private;
3117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3118 int pipe = intel_crtc->pipe;
3119 u32 reg, temp, i, retry;
3120
3121 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3122 for train result */
3123 reg = FDI_RX_IMR(pipe);
3124 temp = I915_READ(reg);
3125 temp &= ~FDI_RX_SYMBOL_LOCK;
3126 temp &= ~FDI_RX_BIT_LOCK;
3127 I915_WRITE(reg, temp);
3128
3129 POSTING_READ(reg);
3130 udelay(150);
3131
3132 /* enable CPU FDI TX and PCH FDI RX */
3133 reg = FDI_TX_CTL(pipe);
3134 temp = I915_READ(reg);
3135 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3136 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3137 temp &= ~FDI_LINK_TRAIN_NONE;
3138 temp |= FDI_LINK_TRAIN_PATTERN_1;
3139 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3140 /* SNB-B */
3141 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3142 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3143
3144 I915_WRITE(FDI_RX_MISC(pipe),
3145 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3146
3147 reg = FDI_RX_CTL(pipe);
3148 temp = I915_READ(reg);
3149 if (HAS_PCH_CPT(dev)) {
3150 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3151 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3152 } else {
3153 temp &= ~FDI_LINK_TRAIN_NONE;
3154 temp |= FDI_LINK_TRAIN_PATTERN_1;
3155 }
3156 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3157
3158 POSTING_READ(reg);
3159 udelay(150);
3160
3161 for (i = 0; i < 4; i++) {
3162 reg = FDI_TX_CTL(pipe);
3163 temp = I915_READ(reg);
3164 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3165 temp |= snb_b_fdi_train_param[i];
3166 I915_WRITE(reg, temp);
3167
3168 POSTING_READ(reg);
3169 udelay(500);
3170
3171 for (retry = 0; retry < 5; retry++) {
3172 reg = FDI_RX_IIR(pipe);
3173 temp = I915_READ(reg);
3174 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3175 if (temp & FDI_RX_BIT_LOCK) {
3176 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3177 DRM_DEBUG_KMS("FDI train 1 done.\n");
3178 break;
3179 }
3180 udelay(50);
3181 }
3182 if (retry < 5)
3183 break;
3184 }
3185 if (i == 4)
3186 DRM_ERROR("FDI train 1 fail!\n");
3187
3188 /* Train 2 */
3189 reg = FDI_TX_CTL(pipe);
3190 temp = I915_READ(reg);
3191 temp &= ~FDI_LINK_TRAIN_NONE;
3192 temp |= FDI_LINK_TRAIN_PATTERN_2;
3193 if (IS_GEN6(dev)) {
3194 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3195 /* SNB-B */
3196 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3197 }
3198 I915_WRITE(reg, temp);
3199
3200 reg = FDI_RX_CTL(pipe);
3201 temp = I915_READ(reg);
3202 if (HAS_PCH_CPT(dev)) {
3203 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3204 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3205 } else {
3206 temp &= ~FDI_LINK_TRAIN_NONE;
3207 temp |= FDI_LINK_TRAIN_PATTERN_2;
3208 }
3209 I915_WRITE(reg, temp);
3210
3211 POSTING_READ(reg);
3212 udelay(150);
3213
3214 for (i = 0; i < 4; i++) {
3215 reg = FDI_TX_CTL(pipe);
3216 temp = I915_READ(reg);
3217 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3218 temp |= snb_b_fdi_train_param[i];
3219 I915_WRITE(reg, temp);
3220
3221 POSTING_READ(reg);
3222 udelay(500);
3223
3224 for (retry = 0; retry < 5; retry++) {
3225 reg = FDI_RX_IIR(pipe);
3226 temp = I915_READ(reg);
3227 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3228 if (temp & FDI_RX_SYMBOL_LOCK) {
3229 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3230 DRM_DEBUG_KMS("FDI train 2 done.\n");
3231 break;
3232 }
3233 udelay(50);
3234 }
3235 if (retry < 5)
3236 break;
3237 }
3238 if (i == 4)
3239 DRM_ERROR("FDI train 2 fail!\n");
3240
3241 DRM_DEBUG_KMS("FDI train done.\n");
3242 }
3243
3244 /* Manual link training for Ivy Bridge A0 parts */
3245 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3246 {
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250 int pipe = intel_crtc->pipe;
3251 u32 reg, temp, i, j;
3252
3253 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3254 for train result */
3255 reg = FDI_RX_IMR(pipe);
3256 temp = I915_READ(reg);
3257 temp &= ~FDI_RX_SYMBOL_LOCK;
3258 temp &= ~FDI_RX_BIT_LOCK;
3259 I915_WRITE(reg, temp);
3260
3261 POSTING_READ(reg);
3262 udelay(150);
3263
3264 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3265 I915_READ(FDI_RX_IIR(pipe)));
3266
3267 /* Try each vswing and preemphasis setting twice before moving on */
3268 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3269 /* disable first in case we need to retry */
3270 reg = FDI_TX_CTL(pipe);
3271 temp = I915_READ(reg);
3272 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3273 temp &= ~FDI_TX_ENABLE;
3274 I915_WRITE(reg, temp);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_LINK_TRAIN_AUTO;
3279 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3280 temp &= ~FDI_RX_ENABLE;
3281 I915_WRITE(reg, temp);
3282
3283 /* enable CPU FDI TX and PCH FDI RX */
3284 reg = FDI_TX_CTL(pipe);
3285 temp = I915_READ(reg);
3286 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3287 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3288 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3289 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3290 temp |= snb_b_fdi_train_param[j/2];
3291 temp |= FDI_COMPOSITE_SYNC;
3292 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3293
3294 I915_WRITE(FDI_RX_MISC(pipe),
3295 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3300 temp |= FDI_COMPOSITE_SYNC;
3301 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3302
3303 POSTING_READ(reg);
3304 udelay(1); /* should be 0.5us */
3305
3306 for (i = 0; i < 4; i++) {
3307 reg = FDI_RX_IIR(pipe);
3308 temp = I915_READ(reg);
3309 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3310
3311 if (temp & FDI_RX_BIT_LOCK ||
3312 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3313 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3314 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3315 i);
3316 break;
3317 }
3318 udelay(1); /* should be 0.5us */
3319 }
3320 if (i == 4) {
3321 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3322 continue;
3323 }
3324
3325 /* Train 2 */
3326 reg = FDI_TX_CTL(pipe);
3327 temp = I915_READ(reg);
3328 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3329 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3330 I915_WRITE(reg, temp);
3331
3332 reg = FDI_RX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3335 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3336 I915_WRITE(reg, temp);
3337
3338 POSTING_READ(reg);
3339 udelay(2); /* should be 1.5us */
3340
3341 for (i = 0; i < 4; i++) {
3342 reg = FDI_RX_IIR(pipe);
3343 temp = I915_READ(reg);
3344 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3345
3346 if (temp & FDI_RX_SYMBOL_LOCK ||
3347 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3348 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3349 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3350 i);
3351 goto train_done;
3352 }
3353 udelay(2); /* should be 1.5us */
3354 }
3355 if (i == 4)
3356 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3357 }
3358
3359 train_done:
3360 DRM_DEBUG_KMS("FDI train done.\n");
3361 }
3362
3363 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3364 {
3365 struct drm_device *dev = intel_crtc->base.dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int pipe = intel_crtc->pipe;
3368 u32 reg, temp;
3369
3370
3371 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3372 reg = FDI_RX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3375 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3376 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3377 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3378
3379 POSTING_READ(reg);
3380 udelay(200);
3381
3382 /* Switch from Rawclk to PCDclk */
3383 temp = I915_READ(reg);
3384 I915_WRITE(reg, temp | FDI_PCDCLK);
3385
3386 POSTING_READ(reg);
3387 udelay(200);
3388
3389 /* Enable CPU FDI TX PLL, always on for Ironlake */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3393 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3394
3395 POSTING_READ(reg);
3396 udelay(100);
3397 }
3398 }
3399
3400 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3401 {
3402 struct drm_device *dev = intel_crtc->base.dev;
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404 int pipe = intel_crtc->pipe;
3405 u32 reg, temp;
3406
3407 /* Switch from PCDclk to Rawclk */
3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3411
3412 /* Disable CPU FDI TX PLL */
3413 reg = FDI_TX_CTL(pipe);
3414 temp = I915_READ(reg);
3415 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3416
3417 POSTING_READ(reg);
3418 udelay(100);
3419
3420 reg = FDI_RX_CTL(pipe);
3421 temp = I915_READ(reg);
3422 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3423
3424 /* Wait for the clocks to turn off. */
3425 POSTING_READ(reg);
3426 udelay(100);
3427 }
3428
3429 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3430 {
3431 struct drm_device *dev = crtc->dev;
3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3434 int pipe = intel_crtc->pipe;
3435 u32 reg, temp;
3436
3437 /* disable CPU FDI tx and PCH FDI rx */
3438 reg = FDI_TX_CTL(pipe);
3439 temp = I915_READ(reg);
3440 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3441 POSTING_READ(reg);
3442
3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~(0x7 << 16);
3446 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3447 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3448
3449 POSTING_READ(reg);
3450 udelay(100);
3451
3452 /* Ironlake workaround, disable clock pointer after downing FDI */
3453 if (HAS_PCH_IBX(dev))
3454 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3455
3456 /* still set train pattern 1 */
3457 reg = FDI_TX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_1;
3461 I915_WRITE(reg, temp);
3462
3463 reg = FDI_RX_CTL(pipe);
3464 temp = I915_READ(reg);
3465 if (HAS_PCH_CPT(dev)) {
3466 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3467 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3468 } else {
3469 temp &= ~FDI_LINK_TRAIN_NONE;
3470 temp |= FDI_LINK_TRAIN_PATTERN_1;
3471 }
3472 /* BPC in FDI rx is consistent with that in PIPECONF */
3473 temp &= ~(0x07 << 16);
3474 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(100);
3479 }
3480
3481 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3482 {
3483 struct intel_crtc *crtc;
3484
3485 /* Note that we don't need to be called with mode_config.lock here
3486 * as our list of CRTC objects is static for the lifetime of the
3487 * device and so cannot disappear as we iterate. Similarly, we can
3488 * happily treat the predicates as racy, atomic checks as userspace
3489 * cannot claim and pin a new fb without at least acquring the
3490 * struct_mutex and so serialising with us.
3491 */
3492 for_each_intel_crtc(dev, crtc) {
3493 if (atomic_read(&crtc->unpin_work_count) == 0)
3494 continue;
3495
3496 if (crtc->unpin_work)
3497 intel_wait_for_vblank(dev, crtc->pipe);
3498
3499 return true;
3500 }
3501
3502 return false;
3503 }
3504
3505 static void page_flip_completed(struct intel_crtc *intel_crtc)
3506 {
3507 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3508 struct intel_unpin_work *work = intel_crtc->unpin_work;
3509
3510 /* ensure that the unpin work is consistent wrt ->pending. */
3511 smp_rmb();
3512 intel_crtc->unpin_work = NULL;
3513
3514 if (work->event)
3515 drm_send_vblank_event(intel_crtc->base.dev,
3516 intel_crtc->pipe,
3517 work->event);
3518
3519 drm_crtc_vblank_put(&intel_crtc->base);
3520
3521 wake_up_all(&dev_priv->pending_flip_queue);
3522 queue_work(dev_priv->wq, &work->work);
3523
3524 trace_i915_flip_complete(intel_crtc->plane,
3525 work->pending_flip_obj);
3526 }
3527
3528 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3529 {
3530 struct drm_device *dev = crtc->dev;
3531 struct drm_i915_private *dev_priv = dev->dev_private;
3532
3533 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3534 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3535 !intel_crtc_has_pending_flip(crtc),
3536 60*HZ) == 0)) {
3537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3538 unsigned long flags;
3539
3540 spin_lock_irqsave(&dev->event_lock, flags);
3541 if (intel_crtc->unpin_work) {
3542 WARN_ONCE(1, "Removing stuck page flip\n");
3543 page_flip_completed(intel_crtc);
3544 }
3545 spin_unlock_irqrestore(&dev->event_lock, flags);
3546 }
3547
3548 if (crtc->primary->fb) {
3549 mutex_lock(&dev->struct_mutex);
3550 intel_finish_fb(crtc->primary->fb);
3551 mutex_unlock(&dev->struct_mutex);
3552 }
3553 }
3554
3555 /* Program iCLKIP clock to the desired frequency */
3556 static void lpt_program_iclkip(struct drm_crtc *crtc)
3557 {
3558 struct drm_device *dev = crtc->dev;
3559 struct drm_i915_private *dev_priv = dev->dev_private;
3560 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3561 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3562 u32 temp;
3563
3564 mutex_lock(&dev_priv->dpio_lock);
3565
3566 /* It is necessary to ungate the pixclk gate prior to programming
3567 * the divisors, and gate it back when it is done.
3568 */
3569 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3570
3571 /* Disable SSCCTL */
3572 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3573 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3574 SBI_SSCCTL_DISABLE,
3575 SBI_ICLK);
3576
3577 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3578 if (clock == 20000) {
3579 auxdiv = 1;
3580 divsel = 0x41;
3581 phaseinc = 0x20;
3582 } else {
3583 /* The iCLK virtual clock root frequency is in MHz,
3584 * but the adjusted_mode->crtc_clock in in KHz. To get the
3585 * divisors, it is necessary to divide one by another, so we
3586 * convert the virtual clock precision to KHz here for higher
3587 * precision.
3588 */
3589 u32 iclk_virtual_root_freq = 172800 * 1000;
3590 u32 iclk_pi_range = 64;
3591 u32 desired_divisor, msb_divisor_value, pi_value;
3592
3593 desired_divisor = (iclk_virtual_root_freq / clock);
3594 msb_divisor_value = desired_divisor / iclk_pi_range;
3595 pi_value = desired_divisor % iclk_pi_range;
3596
3597 auxdiv = 0;
3598 divsel = msb_divisor_value - 2;
3599 phaseinc = pi_value;
3600 }
3601
3602 /* This should not happen with any sane values */
3603 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3604 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3605 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3606 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3607
3608 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3609 clock,
3610 auxdiv,
3611 divsel,
3612 phasedir,
3613 phaseinc);
3614
3615 /* Program SSCDIVINTPHASE6 */
3616 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3617 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3618 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3619 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3620 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3621 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3622 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3623 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3624
3625 /* Program SSCAUXDIV */
3626 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3627 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3628 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3629 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3630
3631 /* Enable modulator and associated divider */
3632 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3633 temp &= ~SBI_SSCCTL_DISABLE;
3634 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3635
3636 /* Wait for initialization time */
3637 udelay(24);
3638
3639 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3640
3641 mutex_unlock(&dev_priv->dpio_lock);
3642 }
3643
3644 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3645 enum pipe pch_transcoder)
3646 {
3647 struct drm_device *dev = crtc->base.dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3650
3651 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3652 I915_READ(HTOTAL(cpu_transcoder)));
3653 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3654 I915_READ(HBLANK(cpu_transcoder)));
3655 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3656 I915_READ(HSYNC(cpu_transcoder)));
3657
3658 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3659 I915_READ(VTOTAL(cpu_transcoder)));
3660 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3661 I915_READ(VBLANK(cpu_transcoder)));
3662 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3663 I915_READ(VSYNC(cpu_transcoder)));
3664 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3665 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3666 }
3667
3668 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3669 {
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 uint32_t temp;
3672
3673 temp = I915_READ(SOUTH_CHICKEN1);
3674 if (temp & FDI_BC_BIFURCATION_SELECT)
3675 return;
3676
3677 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3678 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3679
3680 temp |= FDI_BC_BIFURCATION_SELECT;
3681 DRM_DEBUG_KMS("enabling fdi C rx\n");
3682 I915_WRITE(SOUTH_CHICKEN1, temp);
3683 POSTING_READ(SOUTH_CHICKEN1);
3684 }
3685
3686 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3687 {
3688 struct drm_device *dev = intel_crtc->base.dev;
3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690
3691 switch (intel_crtc->pipe) {
3692 case PIPE_A:
3693 break;
3694 case PIPE_B:
3695 if (intel_crtc->config.fdi_lanes > 2)
3696 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3697 else
3698 cpt_enable_fdi_bc_bifurcation(dev);
3699
3700 break;
3701 case PIPE_C:
3702 cpt_enable_fdi_bc_bifurcation(dev);
3703
3704 break;
3705 default:
3706 BUG();
3707 }
3708 }
3709
3710 /*
3711 * Enable PCH resources required for PCH ports:
3712 * - PCH PLLs
3713 * - FDI training & RX/TX
3714 * - update transcoder timings
3715 * - DP transcoding bits
3716 * - transcoder
3717 */
3718 static void ironlake_pch_enable(struct drm_crtc *crtc)
3719 {
3720 struct drm_device *dev = crtc->dev;
3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3723 int pipe = intel_crtc->pipe;
3724 u32 reg, temp;
3725
3726 assert_pch_transcoder_disabled(dev_priv, pipe);
3727
3728 if (IS_IVYBRIDGE(dev))
3729 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3730
3731 /* Write the TU size bits before fdi link training, so that error
3732 * detection works. */
3733 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3734 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3735
3736 /* For PCH output, training FDI link */
3737 dev_priv->display.fdi_link_train(crtc);
3738
3739 /* We need to program the right clock selection before writing the pixel
3740 * mutliplier into the DPLL. */
3741 if (HAS_PCH_CPT(dev)) {
3742 u32 sel;
3743
3744 temp = I915_READ(PCH_DPLL_SEL);
3745 temp |= TRANS_DPLL_ENABLE(pipe);
3746 sel = TRANS_DPLLB_SEL(pipe);
3747 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3748 temp |= sel;
3749 else
3750 temp &= ~sel;
3751 I915_WRITE(PCH_DPLL_SEL, temp);
3752 }
3753
3754 /* XXX: pch pll's can be enabled any time before we enable the PCH
3755 * transcoder, and we actually should do this to not upset any PCH
3756 * transcoder that already use the clock when we share it.
3757 *
3758 * Note that enable_shared_dpll tries to do the right thing, but
3759 * get_shared_dpll unconditionally resets the pll - we need that to have
3760 * the right LVDS enable sequence. */
3761 intel_enable_shared_dpll(intel_crtc);
3762
3763 /* set transcoder timing, panel must allow it */
3764 assert_panel_unlocked(dev_priv, pipe);
3765 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3766
3767 intel_fdi_normal_train(crtc);
3768
3769 /* For PCH DP, enable TRANS_DP_CTL */
3770 if (HAS_PCH_CPT(dev) &&
3771 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3772 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3773 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3774 reg = TRANS_DP_CTL(pipe);
3775 temp = I915_READ(reg);
3776 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3777 TRANS_DP_SYNC_MASK |
3778 TRANS_DP_BPC_MASK);
3779 temp |= (TRANS_DP_OUTPUT_ENABLE |
3780 TRANS_DP_ENH_FRAMING);
3781 temp |= bpc << 9; /* same format but at 11:9 */
3782
3783 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3784 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3785 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3786 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3787
3788 switch (intel_trans_dp_port_sel(crtc)) {
3789 case PCH_DP_B:
3790 temp |= TRANS_DP_PORT_SEL_B;
3791 break;
3792 case PCH_DP_C:
3793 temp |= TRANS_DP_PORT_SEL_C;
3794 break;
3795 case PCH_DP_D:
3796 temp |= TRANS_DP_PORT_SEL_D;
3797 break;
3798 default:
3799 BUG();
3800 }
3801
3802 I915_WRITE(reg, temp);
3803 }
3804
3805 ironlake_enable_pch_transcoder(dev_priv, pipe);
3806 }
3807
3808 static void lpt_pch_enable(struct drm_crtc *crtc)
3809 {
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3814
3815 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3816
3817 lpt_program_iclkip(crtc);
3818
3819 /* Set transcoder timing. */
3820 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3821
3822 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3823 }
3824
3825 void intel_put_shared_dpll(struct intel_crtc *crtc)
3826 {
3827 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3828
3829 if (pll == NULL)
3830 return;
3831
3832 if (pll->refcount == 0) {
3833 WARN(1, "bad %s refcount\n", pll->name);
3834 return;
3835 }
3836
3837 if (--pll->refcount == 0) {
3838 WARN_ON(pll->on);
3839 WARN_ON(pll->active);
3840 }
3841
3842 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3843 }
3844
3845 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3846 {
3847 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3848 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3849 enum intel_dpll_id i;
3850
3851 if (pll) {
3852 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3853 crtc->base.base.id, pll->name);
3854 intel_put_shared_dpll(crtc);
3855 }
3856
3857 if (HAS_PCH_IBX(dev_priv->dev)) {
3858 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3859 i = (enum intel_dpll_id) crtc->pipe;
3860 pll = &dev_priv->shared_dplls[i];
3861
3862 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3863 crtc->base.base.id, pll->name);
3864
3865 WARN_ON(pll->refcount);
3866
3867 goto found;
3868 }
3869
3870 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3871 pll = &dev_priv->shared_dplls[i];
3872
3873 /* Only want to check enabled timings first */
3874 if (pll->refcount == 0)
3875 continue;
3876
3877 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3878 sizeof(pll->hw_state)) == 0) {
3879 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3880 crtc->base.base.id,
3881 pll->name, pll->refcount, pll->active);
3882
3883 goto found;
3884 }
3885 }
3886
3887 /* Ok no matching timings, maybe there's a free one? */
3888 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3889 pll = &dev_priv->shared_dplls[i];
3890 if (pll->refcount == 0) {
3891 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3892 crtc->base.base.id, pll->name);
3893 goto found;
3894 }
3895 }
3896
3897 return NULL;
3898
3899 found:
3900 if (pll->refcount == 0)
3901 pll->hw_state = crtc->config.dpll_hw_state;
3902
3903 crtc->config.shared_dpll = i;
3904 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3905 pipe_name(crtc->pipe));
3906
3907 pll->refcount++;
3908
3909 return pll;
3910 }
3911
3912 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3913 {
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 int dslreg = PIPEDSL(pipe);
3916 u32 temp;
3917
3918 temp = I915_READ(dslreg);
3919 udelay(500);
3920 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3921 if (wait_for(I915_READ(dslreg) != temp, 5))
3922 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3923 }
3924 }
3925
3926 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3927 {
3928 struct drm_device *dev = crtc->base.dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 int pipe = crtc->pipe;
3931
3932 if (crtc->config.pch_pfit.enabled) {
3933 /* Force use of hard-coded filter coefficients
3934 * as some pre-programmed values are broken,
3935 * e.g. x201.
3936 */
3937 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3938 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3939 PF_PIPE_SEL_IVB(pipe));
3940 else
3941 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3942 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3943 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3944 }
3945 }
3946
3947 static void intel_enable_planes(struct drm_crtc *crtc)
3948 {
3949 struct drm_device *dev = crtc->dev;
3950 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3951 struct drm_plane *plane;
3952 struct intel_plane *intel_plane;
3953
3954 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3955 intel_plane = to_intel_plane(plane);
3956 if (intel_plane->pipe == pipe)
3957 intel_plane_restore(&intel_plane->base);
3958 }
3959 }
3960
3961 static void intel_disable_planes(struct drm_crtc *crtc)
3962 {
3963 struct drm_device *dev = crtc->dev;
3964 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3965 struct drm_plane *plane;
3966 struct intel_plane *intel_plane;
3967
3968 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3969 intel_plane = to_intel_plane(plane);
3970 if (intel_plane->pipe == pipe)
3971 intel_plane_disable(&intel_plane->base);
3972 }
3973 }
3974
3975 void hsw_enable_ips(struct intel_crtc *crtc)
3976 {
3977 struct drm_device *dev = crtc->base.dev;
3978 struct drm_i915_private *dev_priv = dev->dev_private;
3979
3980 if (!crtc->config.ips_enabled)
3981 return;
3982
3983 /* We can only enable IPS after we enable a plane and wait for a vblank */
3984 intel_wait_for_vblank(dev, crtc->pipe);
3985
3986 assert_plane_enabled(dev_priv, crtc->plane);
3987 if (IS_BROADWELL(dev)) {
3988 mutex_lock(&dev_priv->rps.hw_lock);
3989 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3990 mutex_unlock(&dev_priv->rps.hw_lock);
3991 /* Quoting Art Runyan: "its not safe to expect any particular
3992 * value in IPS_CTL bit 31 after enabling IPS through the
3993 * mailbox." Moreover, the mailbox may return a bogus state,
3994 * so we need to just enable it and continue on.
3995 */
3996 } else {
3997 I915_WRITE(IPS_CTL, IPS_ENABLE);
3998 /* The bit only becomes 1 in the next vblank, so this wait here
3999 * is essentially intel_wait_for_vblank. If we don't have this
4000 * and don't wait for vblanks until the end of crtc_enable, then
4001 * the HW state readout code will complain that the expected
4002 * IPS_CTL value is not the one we read. */
4003 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4004 DRM_ERROR("Timed out waiting for IPS enable\n");
4005 }
4006 }
4007
4008 void hsw_disable_ips(struct intel_crtc *crtc)
4009 {
4010 struct drm_device *dev = crtc->base.dev;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012
4013 if (!crtc->config.ips_enabled)
4014 return;
4015
4016 assert_plane_enabled(dev_priv, crtc->plane);
4017 if (IS_BROADWELL(dev)) {
4018 mutex_lock(&dev_priv->rps.hw_lock);
4019 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4020 mutex_unlock(&dev_priv->rps.hw_lock);
4021 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4022 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4023 DRM_ERROR("Timed out waiting for IPS disable\n");
4024 } else {
4025 I915_WRITE(IPS_CTL, 0);
4026 POSTING_READ(IPS_CTL);
4027 }
4028
4029 /* We need to wait for a vblank before we can disable the plane. */
4030 intel_wait_for_vblank(dev, crtc->pipe);
4031 }
4032
4033 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4034 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4035 {
4036 struct drm_device *dev = crtc->dev;
4037 struct drm_i915_private *dev_priv = dev->dev_private;
4038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039 enum pipe pipe = intel_crtc->pipe;
4040 int palreg = PALETTE(pipe);
4041 int i;
4042 bool reenable_ips = false;
4043
4044 /* The clocks have to be on to load the palette. */
4045 if (!crtc->enabled || !intel_crtc->active)
4046 return;
4047
4048 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4049 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4050 assert_dsi_pll_enabled(dev_priv);
4051 else
4052 assert_pll_enabled(dev_priv, pipe);
4053 }
4054
4055 /* use legacy palette for Ironlake */
4056 if (!HAS_GMCH_DISPLAY(dev))
4057 palreg = LGC_PALETTE(pipe);
4058
4059 /* Workaround : Do not read or write the pipe palette/gamma data while
4060 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4061 */
4062 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4063 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4064 GAMMA_MODE_MODE_SPLIT)) {
4065 hsw_disable_ips(intel_crtc);
4066 reenable_ips = true;
4067 }
4068
4069 for (i = 0; i < 256; i++) {
4070 I915_WRITE(palreg + 4 * i,
4071 (intel_crtc->lut_r[i] << 16) |
4072 (intel_crtc->lut_g[i] << 8) |
4073 intel_crtc->lut_b[i]);
4074 }
4075
4076 if (reenable_ips)
4077 hsw_enable_ips(intel_crtc);
4078 }
4079
4080 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4081 {
4082 if (!enable && intel_crtc->overlay) {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085
4086 mutex_lock(&dev->struct_mutex);
4087 dev_priv->mm.interruptible = false;
4088 (void) intel_overlay_switch_off(intel_crtc->overlay);
4089 dev_priv->mm.interruptible = true;
4090 mutex_unlock(&dev->struct_mutex);
4091 }
4092
4093 /* Let userspace switch the overlay on again. In most cases userspace
4094 * has to recompute where to put it anyway.
4095 */
4096 }
4097
4098 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4099 {
4100 struct drm_device *dev = crtc->dev;
4101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102 int pipe = intel_crtc->pipe;
4103
4104 assert_vblank_disabled(crtc);
4105
4106 drm_vblank_on(dev, pipe);
4107
4108 intel_enable_primary_hw_plane(crtc->primary, crtc);
4109 intel_enable_planes(crtc);
4110 intel_crtc_update_cursor(crtc, true);
4111 intel_crtc_dpms_overlay(intel_crtc, true);
4112
4113 hsw_enable_ips(intel_crtc);
4114
4115 mutex_lock(&dev->struct_mutex);
4116 intel_update_fbc(dev);
4117 mutex_unlock(&dev->struct_mutex);
4118
4119 /*
4120 * FIXME: Once we grow proper nuclear flip support out of this we need
4121 * to compute the mask of flip planes precisely. For the time being
4122 * consider this a flip from a NULL plane.
4123 */
4124 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4125 }
4126
4127 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4128 {
4129 struct drm_device *dev = crtc->dev;
4130 struct drm_i915_private *dev_priv = dev->dev_private;
4131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4132 int pipe = intel_crtc->pipe;
4133 int plane = intel_crtc->plane;
4134
4135 intel_crtc_wait_for_pending_flips(crtc);
4136
4137 if (dev_priv->fbc.plane == plane)
4138 intel_disable_fbc(dev);
4139
4140 hsw_disable_ips(intel_crtc);
4141
4142 intel_crtc_dpms_overlay(intel_crtc, false);
4143 intel_crtc_update_cursor(crtc, false);
4144 intel_disable_planes(crtc);
4145 intel_disable_primary_hw_plane(crtc->primary, crtc);
4146
4147 /*
4148 * FIXME: Once we grow proper nuclear flip support out of this we need
4149 * to compute the mask of flip planes precisely. For the time being
4150 * consider this a flip to a NULL plane.
4151 */
4152 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4153
4154 drm_vblank_off(dev, pipe);
4155
4156 assert_vblank_disabled(crtc);
4157 }
4158
4159 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 struct intel_encoder *encoder;
4165 int pipe = intel_crtc->pipe;
4166
4167 WARN_ON(!crtc->enabled);
4168
4169 if (intel_crtc->active)
4170 return;
4171
4172 if (intel_crtc->config.has_pch_encoder)
4173 intel_prepare_shared_dpll(intel_crtc);
4174
4175 if (intel_crtc->config.has_dp_encoder)
4176 intel_dp_set_m_n(intel_crtc);
4177
4178 intel_set_pipe_timings(intel_crtc);
4179
4180 if (intel_crtc->config.has_pch_encoder) {
4181 intel_cpu_transcoder_set_m_n(intel_crtc,
4182 &intel_crtc->config.fdi_m_n, NULL);
4183 }
4184
4185 ironlake_set_pipeconf(crtc);
4186
4187 intel_crtc->active = true;
4188
4189 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4190 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4191
4192 for_each_encoder_on_crtc(dev, crtc, encoder)
4193 if (encoder->pre_enable)
4194 encoder->pre_enable(encoder);
4195
4196 if (intel_crtc->config.has_pch_encoder) {
4197 /* Note: FDI PLL enabling _must_ be done before we enable the
4198 * cpu pipes, hence this is separate from all the other fdi/pch
4199 * enabling. */
4200 ironlake_fdi_pll_enable(intel_crtc);
4201 } else {
4202 assert_fdi_tx_disabled(dev_priv, pipe);
4203 assert_fdi_rx_disabled(dev_priv, pipe);
4204 }
4205
4206 ironlake_pfit_enable(intel_crtc);
4207
4208 /*
4209 * On ILK+ LUT must be loaded before the pipe is running but with
4210 * clocks enabled
4211 */
4212 intel_crtc_load_lut(crtc);
4213
4214 intel_update_watermarks(crtc);
4215 intel_enable_pipe(intel_crtc);
4216
4217 if (intel_crtc->config.has_pch_encoder)
4218 ironlake_pch_enable(crtc);
4219
4220 for_each_encoder_on_crtc(dev, crtc, encoder)
4221 encoder->enable(encoder);
4222
4223 if (HAS_PCH_CPT(dev))
4224 cpt_verify_modeset(dev, intel_crtc->pipe);
4225
4226 intel_crtc_enable_planes(crtc);
4227 }
4228
4229 /* IPS only exists on ULT machines and is tied to pipe A. */
4230 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4231 {
4232 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4233 }
4234
4235 /*
4236 * This implements the workaround described in the "notes" section of the mode
4237 * set sequence documentation. When going from no pipes or single pipe to
4238 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4239 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4240 */
4241 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4242 {
4243 struct drm_device *dev = crtc->base.dev;
4244 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4245
4246 /* We want to get the other_active_crtc only if there's only 1 other
4247 * active crtc. */
4248 for_each_intel_crtc(dev, crtc_it) {
4249 if (!crtc_it->active || crtc_it == crtc)
4250 continue;
4251
4252 if (other_active_crtc)
4253 return;
4254
4255 other_active_crtc = crtc_it;
4256 }
4257 if (!other_active_crtc)
4258 return;
4259
4260 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4261 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4262 }
4263
4264 static void haswell_crtc_enable(struct drm_crtc *crtc)
4265 {
4266 struct drm_device *dev = crtc->dev;
4267 struct drm_i915_private *dev_priv = dev->dev_private;
4268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4269 struct intel_encoder *encoder;
4270 int pipe = intel_crtc->pipe;
4271
4272 WARN_ON(!crtc->enabled);
4273
4274 if (intel_crtc->active)
4275 return;
4276
4277 if (intel_crtc_to_shared_dpll(intel_crtc))
4278 intel_enable_shared_dpll(intel_crtc);
4279
4280 if (intel_crtc->config.has_dp_encoder)
4281 intel_dp_set_m_n(intel_crtc);
4282
4283 intel_set_pipe_timings(intel_crtc);
4284
4285 if (intel_crtc->config.has_pch_encoder) {
4286 intel_cpu_transcoder_set_m_n(intel_crtc,
4287 &intel_crtc->config.fdi_m_n, NULL);
4288 }
4289
4290 haswell_set_pipeconf(crtc);
4291
4292 intel_set_pipe_csc(crtc);
4293
4294 intel_crtc->active = true;
4295
4296 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4297 for_each_encoder_on_crtc(dev, crtc, encoder)
4298 if (encoder->pre_enable)
4299 encoder->pre_enable(encoder);
4300
4301 if (intel_crtc->config.has_pch_encoder) {
4302 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4303 dev_priv->display.fdi_link_train(crtc);
4304 }
4305
4306 intel_ddi_enable_pipe_clock(intel_crtc);
4307
4308 ironlake_pfit_enable(intel_crtc);
4309
4310 /*
4311 * On ILK+ LUT must be loaded before the pipe is running but with
4312 * clocks enabled
4313 */
4314 intel_crtc_load_lut(crtc);
4315
4316 intel_ddi_set_pipe_settings(crtc);
4317 intel_ddi_enable_transcoder_func(crtc);
4318
4319 intel_update_watermarks(crtc);
4320 intel_enable_pipe(intel_crtc);
4321
4322 if (intel_crtc->config.has_pch_encoder)
4323 lpt_pch_enable(crtc);
4324
4325 if (intel_crtc->config.dp_encoder_is_mst)
4326 intel_ddi_set_vc_payload_alloc(crtc, true);
4327
4328 for_each_encoder_on_crtc(dev, crtc, encoder) {
4329 encoder->enable(encoder);
4330 intel_opregion_notify_encoder(encoder, true);
4331 }
4332
4333 /* If we change the relative order between pipe/planes enabling, we need
4334 * to change the workaround. */
4335 haswell_mode_set_planes_workaround(intel_crtc);
4336 intel_crtc_enable_planes(crtc);
4337 }
4338
4339 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4340 {
4341 struct drm_device *dev = crtc->base.dev;
4342 struct drm_i915_private *dev_priv = dev->dev_private;
4343 int pipe = crtc->pipe;
4344
4345 /* To avoid upsetting the power well on haswell only disable the pfit if
4346 * it's in use. The hw state code will make sure we get this right. */
4347 if (crtc->config.pch_pfit.enabled) {
4348 I915_WRITE(PF_CTL(pipe), 0);
4349 I915_WRITE(PF_WIN_POS(pipe), 0);
4350 I915_WRITE(PF_WIN_SZ(pipe), 0);
4351 }
4352 }
4353
4354 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4355 {
4356 struct drm_device *dev = crtc->dev;
4357 struct drm_i915_private *dev_priv = dev->dev_private;
4358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4359 struct intel_encoder *encoder;
4360 int pipe = intel_crtc->pipe;
4361 u32 reg, temp;
4362
4363 if (!intel_crtc->active)
4364 return;
4365
4366 intel_crtc_disable_planes(crtc);
4367
4368 for_each_encoder_on_crtc(dev, crtc, encoder)
4369 encoder->disable(encoder);
4370
4371 if (intel_crtc->config.has_pch_encoder)
4372 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4373
4374 intel_disable_pipe(intel_crtc);
4375
4376 ironlake_pfit_disable(intel_crtc);
4377
4378 for_each_encoder_on_crtc(dev, crtc, encoder)
4379 if (encoder->post_disable)
4380 encoder->post_disable(encoder);
4381
4382 if (intel_crtc->config.has_pch_encoder) {
4383 ironlake_fdi_disable(crtc);
4384
4385 ironlake_disable_pch_transcoder(dev_priv, pipe);
4386 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4387
4388 if (HAS_PCH_CPT(dev)) {
4389 /* disable TRANS_DP_CTL */
4390 reg = TRANS_DP_CTL(pipe);
4391 temp = I915_READ(reg);
4392 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4393 TRANS_DP_PORT_SEL_MASK);
4394 temp |= TRANS_DP_PORT_SEL_NONE;
4395 I915_WRITE(reg, temp);
4396
4397 /* disable DPLL_SEL */
4398 temp = I915_READ(PCH_DPLL_SEL);
4399 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4400 I915_WRITE(PCH_DPLL_SEL, temp);
4401 }
4402
4403 /* disable PCH DPLL */
4404 intel_disable_shared_dpll(intel_crtc);
4405
4406 ironlake_fdi_pll_disable(intel_crtc);
4407 }
4408
4409 intel_crtc->active = false;
4410 intel_update_watermarks(crtc);
4411
4412 mutex_lock(&dev->struct_mutex);
4413 intel_update_fbc(dev);
4414 mutex_unlock(&dev->struct_mutex);
4415 }
4416
4417 static void haswell_crtc_disable(struct drm_crtc *crtc)
4418 {
4419 struct drm_device *dev = crtc->dev;
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4422 struct intel_encoder *encoder;
4423 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4424
4425 if (!intel_crtc->active)
4426 return;
4427
4428 intel_crtc_disable_planes(crtc);
4429
4430 for_each_encoder_on_crtc(dev, crtc, encoder) {
4431 intel_opregion_notify_encoder(encoder, false);
4432 encoder->disable(encoder);
4433 }
4434
4435 if (intel_crtc->config.has_pch_encoder)
4436 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4437 intel_disable_pipe(intel_crtc);
4438
4439 if (intel_crtc->config.dp_encoder_is_mst)
4440 intel_ddi_set_vc_payload_alloc(crtc, false);
4441
4442 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4443
4444 ironlake_pfit_disable(intel_crtc);
4445
4446 intel_ddi_disable_pipe_clock(intel_crtc);
4447
4448 if (intel_crtc->config.has_pch_encoder) {
4449 lpt_disable_pch_transcoder(dev_priv);
4450 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4451 intel_ddi_fdi_disable(crtc);
4452 }
4453
4454 for_each_encoder_on_crtc(dev, crtc, encoder)
4455 if (encoder->post_disable)
4456 encoder->post_disable(encoder);
4457
4458 intel_crtc->active = false;
4459 intel_update_watermarks(crtc);
4460
4461 mutex_lock(&dev->struct_mutex);
4462 intel_update_fbc(dev);
4463 mutex_unlock(&dev->struct_mutex);
4464
4465 if (intel_crtc_to_shared_dpll(intel_crtc))
4466 intel_disable_shared_dpll(intel_crtc);
4467 }
4468
4469 static void ironlake_crtc_off(struct drm_crtc *crtc)
4470 {
4471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4472 intel_put_shared_dpll(intel_crtc);
4473 }
4474
4475
4476 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4477 {
4478 struct drm_device *dev = crtc->base.dev;
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480 struct intel_crtc_config *pipe_config = &crtc->config;
4481
4482 if (!crtc->config.gmch_pfit.control)
4483 return;
4484
4485 /*
4486 * The panel fitter should only be adjusted whilst the pipe is disabled,
4487 * according to register description and PRM.
4488 */
4489 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4490 assert_pipe_disabled(dev_priv, crtc->pipe);
4491
4492 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4493 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4494
4495 /* Border color in case we don't scale up to the full screen. Black by
4496 * default, change to something else for debugging. */
4497 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4498 }
4499
4500 static enum intel_display_power_domain port_to_power_domain(enum port port)
4501 {
4502 switch (port) {
4503 case PORT_A:
4504 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4505 case PORT_B:
4506 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4507 case PORT_C:
4508 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4509 case PORT_D:
4510 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4511 default:
4512 WARN_ON_ONCE(1);
4513 return POWER_DOMAIN_PORT_OTHER;
4514 }
4515 }
4516
4517 #define for_each_power_domain(domain, mask) \
4518 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4519 if ((1 << (domain)) & (mask))
4520
4521 enum intel_display_power_domain
4522 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4523 {
4524 struct drm_device *dev = intel_encoder->base.dev;
4525 struct intel_digital_port *intel_dig_port;
4526
4527 switch (intel_encoder->type) {
4528 case INTEL_OUTPUT_UNKNOWN:
4529 /* Only DDI platforms should ever use this output type */
4530 WARN_ON_ONCE(!HAS_DDI(dev));
4531 case INTEL_OUTPUT_DISPLAYPORT:
4532 case INTEL_OUTPUT_HDMI:
4533 case INTEL_OUTPUT_EDP:
4534 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4535 return port_to_power_domain(intel_dig_port->port);
4536 case INTEL_OUTPUT_DP_MST:
4537 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4538 return port_to_power_domain(intel_dig_port->port);
4539 case INTEL_OUTPUT_ANALOG:
4540 return POWER_DOMAIN_PORT_CRT;
4541 case INTEL_OUTPUT_DSI:
4542 return POWER_DOMAIN_PORT_DSI;
4543 default:
4544 return POWER_DOMAIN_PORT_OTHER;
4545 }
4546 }
4547
4548 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4549 {
4550 struct drm_device *dev = crtc->dev;
4551 struct intel_encoder *intel_encoder;
4552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4553 enum pipe pipe = intel_crtc->pipe;
4554 unsigned long mask;
4555 enum transcoder transcoder;
4556
4557 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4558
4559 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4560 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4561 if (intel_crtc->config.pch_pfit.enabled ||
4562 intel_crtc->config.pch_pfit.force_thru)
4563 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4564
4565 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4566 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4567
4568 return mask;
4569 }
4570
4571 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4572 bool enable)
4573 {
4574 if (dev_priv->power_domains.init_power_on == enable)
4575 return;
4576
4577 if (enable)
4578 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4579 else
4580 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4581
4582 dev_priv->power_domains.init_power_on = enable;
4583 }
4584
4585 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4586 {
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4589 struct intel_crtc *crtc;
4590
4591 /*
4592 * First get all needed power domains, then put all unneeded, to avoid
4593 * any unnecessary toggling of the power wells.
4594 */
4595 for_each_intel_crtc(dev, crtc) {
4596 enum intel_display_power_domain domain;
4597
4598 if (!crtc->base.enabled)
4599 continue;
4600
4601 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4602
4603 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4604 intel_display_power_get(dev_priv, domain);
4605 }
4606
4607 for_each_intel_crtc(dev, crtc) {
4608 enum intel_display_power_domain domain;
4609
4610 for_each_power_domain(domain, crtc->enabled_power_domains)
4611 intel_display_power_put(dev_priv, domain);
4612
4613 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4614 }
4615
4616 intel_display_set_init_power(dev_priv, false);
4617 }
4618
4619 /* returns HPLL frequency in kHz */
4620 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4621 {
4622 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4623
4624 /* Obtain SKU information */
4625 mutex_lock(&dev_priv->dpio_lock);
4626 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4627 CCK_FUSE_HPLL_FREQ_MASK;
4628 mutex_unlock(&dev_priv->dpio_lock);
4629
4630 return vco_freq[hpll_freq] * 1000;
4631 }
4632
4633 static void vlv_update_cdclk(struct drm_device *dev)
4634 {
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636
4637 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4638 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4639 dev_priv->vlv_cdclk_freq);
4640
4641 /*
4642 * Program the gmbus_freq based on the cdclk frequency.
4643 * BSpec erroneously claims we should aim for 4MHz, but
4644 * in fact 1MHz is the correct frequency.
4645 */
4646 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4647 }
4648
4649 /* Adjust CDclk dividers to allow high res or save power if possible */
4650 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4651 {
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 u32 val, cmd;
4654
4655 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4656
4657 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4658 cmd = 2;
4659 else if (cdclk == 266667)
4660 cmd = 1;
4661 else
4662 cmd = 0;
4663
4664 mutex_lock(&dev_priv->rps.hw_lock);
4665 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4666 val &= ~DSPFREQGUAR_MASK;
4667 val |= (cmd << DSPFREQGUAR_SHIFT);
4668 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4669 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4670 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4671 50)) {
4672 DRM_ERROR("timed out waiting for CDclk change\n");
4673 }
4674 mutex_unlock(&dev_priv->rps.hw_lock);
4675
4676 if (cdclk == 400000) {
4677 u32 divider, vco;
4678
4679 vco = valleyview_get_vco(dev_priv);
4680 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4681
4682 mutex_lock(&dev_priv->dpio_lock);
4683 /* adjust cdclk divider */
4684 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4685 val &= ~DISPLAY_FREQUENCY_VALUES;
4686 val |= divider;
4687 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4688
4689 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4690 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4691 50))
4692 DRM_ERROR("timed out waiting for CDclk change\n");
4693 mutex_unlock(&dev_priv->dpio_lock);
4694 }
4695
4696 mutex_lock(&dev_priv->dpio_lock);
4697 /* adjust self-refresh exit latency value */
4698 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4699 val &= ~0x7f;
4700
4701 /*
4702 * For high bandwidth configs, we set a higher latency in the bunit
4703 * so that the core display fetch happens in time to avoid underruns.
4704 */
4705 if (cdclk == 400000)
4706 val |= 4500 / 250; /* 4.5 usec */
4707 else
4708 val |= 3000 / 250; /* 3.0 usec */
4709 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4710 mutex_unlock(&dev_priv->dpio_lock);
4711
4712 vlv_update_cdclk(dev);
4713 }
4714
4715 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4716 {
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 u32 val, cmd;
4719
4720 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4721
4722 switch (cdclk) {
4723 case 400000:
4724 cmd = 3;
4725 break;
4726 case 333333:
4727 case 320000:
4728 cmd = 2;
4729 break;
4730 case 266667:
4731 cmd = 1;
4732 break;
4733 case 200000:
4734 cmd = 0;
4735 break;
4736 default:
4737 WARN_ON(1);
4738 return;
4739 }
4740
4741 mutex_lock(&dev_priv->rps.hw_lock);
4742 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4743 val &= ~DSPFREQGUAR_MASK_CHV;
4744 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4745 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4746 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4747 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4748 50)) {
4749 DRM_ERROR("timed out waiting for CDclk change\n");
4750 }
4751 mutex_unlock(&dev_priv->rps.hw_lock);
4752
4753 vlv_update_cdclk(dev);
4754 }
4755
4756 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4757 int max_pixclk)
4758 {
4759 int vco = valleyview_get_vco(dev_priv);
4760 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4761
4762 /* FIXME: Punit isn't quite ready yet */
4763 if (IS_CHERRYVIEW(dev_priv->dev))
4764 return 400000;
4765
4766 /*
4767 * Really only a few cases to deal with, as only 4 CDclks are supported:
4768 * 200MHz
4769 * 267MHz
4770 * 320/333MHz (depends on HPLL freq)
4771 * 400MHz
4772 * So we check to see whether we're above 90% of the lower bin and
4773 * adjust if needed.
4774 *
4775 * We seem to get an unstable or solid color picture at 200MHz.
4776 * Not sure what's wrong. For now use 200MHz only when all pipes
4777 * are off.
4778 */
4779 if (max_pixclk > freq_320*9/10)
4780 return 400000;
4781 else if (max_pixclk > 266667*9/10)
4782 return freq_320;
4783 else if (max_pixclk > 0)
4784 return 266667;
4785 else
4786 return 200000;
4787 }
4788
4789 /* compute the max pixel clock for new configuration */
4790 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4791 {
4792 struct drm_device *dev = dev_priv->dev;
4793 struct intel_crtc *intel_crtc;
4794 int max_pixclk = 0;
4795
4796 for_each_intel_crtc(dev, intel_crtc) {
4797 if (intel_crtc->new_enabled)
4798 max_pixclk = max(max_pixclk,
4799 intel_crtc->new_config->adjusted_mode.crtc_clock);
4800 }
4801
4802 return max_pixclk;
4803 }
4804
4805 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4806 unsigned *prepare_pipes)
4807 {
4808 struct drm_i915_private *dev_priv = dev->dev_private;
4809 struct intel_crtc *intel_crtc;
4810 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4811
4812 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4813 dev_priv->vlv_cdclk_freq)
4814 return;
4815
4816 /* disable/enable all currently active pipes while we change cdclk */
4817 for_each_intel_crtc(dev, intel_crtc)
4818 if (intel_crtc->base.enabled)
4819 *prepare_pipes |= (1 << intel_crtc->pipe);
4820 }
4821
4822 static void valleyview_modeset_global_resources(struct drm_device *dev)
4823 {
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4826 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4827
4828 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4829 if (IS_CHERRYVIEW(dev))
4830 cherryview_set_cdclk(dev, req_cdclk);
4831 else
4832 valleyview_set_cdclk(dev, req_cdclk);
4833 }
4834
4835 modeset_update_crtc_power_domains(dev);
4836 }
4837
4838 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4839 {
4840 struct drm_device *dev = crtc->dev;
4841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4842 struct intel_encoder *encoder;
4843 int pipe = intel_crtc->pipe;
4844 bool is_dsi;
4845
4846 WARN_ON(!crtc->enabled);
4847
4848 if (intel_crtc->active)
4849 return;
4850
4851 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4852
4853 if (!is_dsi) {
4854 if (IS_CHERRYVIEW(dev))
4855 chv_prepare_pll(intel_crtc);
4856 else
4857 vlv_prepare_pll(intel_crtc);
4858 }
4859
4860 if (intel_crtc->config.has_dp_encoder)
4861 intel_dp_set_m_n(intel_crtc);
4862
4863 intel_set_pipe_timings(intel_crtc);
4864
4865 i9xx_set_pipeconf(intel_crtc);
4866
4867 intel_crtc->active = true;
4868
4869 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4870
4871 for_each_encoder_on_crtc(dev, crtc, encoder)
4872 if (encoder->pre_pll_enable)
4873 encoder->pre_pll_enable(encoder);
4874
4875 if (!is_dsi) {
4876 if (IS_CHERRYVIEW(dev))
4877 chv_enable_pll(intel_crtc);
4878 else
4879 vlv_enable_pll(intel_crtc);
4880 }
4881
4882 for_each_encoder_on_crtc(dev, crtc, encoder)
4883 if (encoder->pre_enable)
4884 encoder->pre_enable(encoder);
4885
4886 i9xx_pfit_enable(intel_crtc);
4887
4888 intel_crtc_load_lut(crtc);
4889
4890 intel_update_watermarks(crtc);
4891 intel_enable_pipe(intel_crtc);
4892
4893 for_each_encoder_on_crtc(dev, crtc, encoder)
4894 encoder->enable(encoder);
4895
4896 intel_crtc_enable_planes(crtc);
4897
4898 /* Underruns don't raise interrupts, so check manually. */
4899 i9xx_check_fifo_underruns(dev);
4900 }
4901
4902 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4903 {
4904 struct drm_device *dev = crtc->base.dev;
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906
4907 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4908 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4909 }
4910
4911 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4912 {
4913 struct drm_device *dev = crtc->dev;
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915 struct intel_encoder *encoder;
4916 int pipe = intel_crtc->pipe;
4917
4918 WARN_ON(!crtc->enabled);
4919
4920 if (intel_crtc->active)
4921 return;
4922
4923 i9xx_set_pll_dividers(intel_crtc);
4924
4925 if (intel_crtc->config.has_dp_encoder)
4926 intel_dp_set_m_n(intel_crtc);
4927
4928 intel_set_pipe_timings(intel_crtc);
4929
4930 i9xx_set_pipeconf(intel_crtc);
4931
4932 intel_crtc->active = true;
4933
4934 if (!IS_GEN2(dev))
4935 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4936
4937 for_each_encoder_on_crtc(dev, crtc, encoder)
4938 if (encoder->pre_enable)
4939 encoder->pre_enable(encoder);
4940
4941 i9xx_enable_pll(intel_crtc);
4942
4943 i9xx_pfit_enable(intel_crtc);
4944
4945 intel_crtc_load_lut(crtc);
4946
4947 intel_update_watermarks(crtc);
4948 intel_enable_pipe(intel_crtc);
4949
4950 for_each_encoder_on_crtc(dev, crtc, encoder)
4951 encoder->enable(encoder);
4952
4953 intel_crtc_enable_planes(crtc);
4954
4955 /*
4956 * Gen2 reports pipe underruns whenever all planes are disabled.
4957 * So don't enable underrun reporting before at least some planes
4958 * are enabled.
4959 * FIXME: Need to fix the logic to work when we turn off all planes
4960 * but leave the pipe running.
4961 */
4962 if (IS_GEN2(dev))
4963 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4964
4965 /* Underruns don't raise interrupts, so check manually. */
4966 i9xx_check_fifo_underruns(dev);
4967 }
4968
4969 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4970 {
4971 struct drm_device *dev = crtc->base.dev;
4972 struct drm_i915_private *dev_priv = dev->dev_private;
4973
4974 if (!crtc->config.gmch_pfit.control)
4975 return;
4976
4977 assert_pipe_disabled(dev_priv, crtc->pipe);
4978
4979 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4980 I915_READ(PFIT_CONTROL));
4981 I915_WRITE(PFIT_CONTROL, 0);
4982 }
4983
4984 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4985 {
4986 struct drm_device *dev = crtc->dev;
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4989 struct intel_encoder *encoder;
4990 int pipe = intel_crtc->pipe;
4991
4992 if (!intel_crtc->active)
4993 return;
4994
4995 /*
4996 * Gen2 reports pipe underruns whenever all planes are disabled.
4997 * So diasble underrun reporting before all the planes get disabled.
4998 * FIXME: Need to fix the logic to work when we turn off all planes
4999 * but leave the pipe running.
5000 */
5001 if (IS_GEN2(dev))
5002 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5003
5004 /*
5005 * Vblank time updates from the shadow to live plane control register
5006 * are blocked if the memory self-refresh mode is active at that
5007 * moment. So to make sure the plane gets truly disabled, disable
5008 * first the self-refresh mode. The self-refresh enable bit in turn
5009 * will be checked/applied by the HW only at the next frame start
5010 * event which is after the vblank start event, so we need to have a
5011 * wait-for-vblank between disabling the plane and the pipe.
5012 */
5013 intel_set_memory_cxsr(dev_priv, false);
5014 intel_crtc_disable_planes(crtc);
5015
5016 for_each_encoder_on_crtc(dev, crtc, encoder)
5017 encoder->disable(encoder);
5018
5019 /*
5020 * On gen2 planes are double buffered but the pipe isn't, so we must
5021 * wait for planes to fully turn off before disabling the pipe.
5022 * We also need to wait on all gmch platforms because of the
5023 * self-refresh mode constraint explained above.
5024 */
5025 intel_wait_for_vblank(dev, pipe);
5026
5027 intel_disable_pipe(intel_crtc);
5028
5029 i9xx_pfit_disable(intel_crtc);
5030
5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 if (encoder->post_disable)
5033 encoder->post_disable(encoder);
5034
5035 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
5036 if (IS_CHERRYVIEW(dev))
5037 chv_disable_pll(dev_priv, pipe);
5038 else if (IS_VALLEYVIEW(dev))
5039 vlv_disable_pll(dev_priv, pipe);
5040 else
5041 i9xx_disable_pll(dev_priv, pipe);
5042 }
5043
5044 if (!IS_GEN2(dev))
5045 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5046
5047 intel_crtc->active = false;
5048 intel_update_watermarks(crtc);
5049
5050 mutex_lock(&dev->struct_mutex);
5051 intel_update_fbc(dev);
5052 mutex_unlock(&dev->struct_mutex);
5053 }
5054
5055 static void i9xx_crtc_off(struct drm_crtc *crtc)
5056 {
5057 }
5058
5059 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5060 bool enabled)
5061 {
5062 struct drm_device *dev = crtc->dev;
5063 struct drm_i915_master_private *master_priv;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 int pipe = intel_crtc->pipe;
5066
5067 if (!dev->primary->master)
5068 return;
5069
5070 master_priv = dev->primary->master->driver_priv;
5071 if (!master_priv->sarea_priv)
5072 return;
5073
5074 switch (pipe) {
5075 case 0:
5076 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5077 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5078 break;
5079 case 1:
5080 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5081 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5082 break;
5083 default:
5084 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5085 break;
5086 }
5087 }
5088
5089 /* Master function to enable/disable CRTC and corresponding power wells */
5090 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5091 {
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095 enum intel_display_power_domain domain;
5096 unsigned long domains;
5097
5098 if (enable) {
5099 if (!intel_crtc->active) {
5100 domains = get_crtc_power_domains(crtc);
5101 for_each_power_domain(domain, domains)
5102 intel_display_power_get(dev_priv, domain);
5103 intel_crtc->enabled_power_domains = domains;
5104
5105 dev_priv->display.crtc_enable(crtc);
5106 }
5107 } else {
5108 if (intel_crtc->active) {
5109 dev_priv->display.crtc_disable(crtc);
5110
5111 domains = intel_crtc->enabled_power_domains;
5112 for_each_power_domain(domain, domains)
5113 intel_display_power_put(dev_priv, domain);
5114 intel_crtc->enabled_power_domains = 0;
5115 }
5116 }
5117 }
5118
5119 /**
5120 * Sets the power management mode of the pipe and plane.
5121 */
5122 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5123 {
5124 struct drm_device *dev = crtc->dev;
5125 struct intel_encoder *intel_encoder;
5126 bool enable = false;
5127
5128 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5129 enable |= intel_encoder->connectors_active;
5130
5131 intel_crtc_control(crtc, enable);
5132
5133 intel_crtc_update_sarea(crtc, enable);
5134 }
5135
5136 static void intel_crtc_disable(struct drm_crtc *crtc)
5137 {
5138 struct drm_device *dev = crtc->dev;
5139 struct drm_connector *connector;
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5142 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5143
5144 /* crtc should still be enabled when we disable it. */
5145 WARN_ON(!crtc->enabled);
5146
5147 dev_priv->display.crtc_disable(crtc);
5148 intel_crtc_update_sarea(crtc, false);
5149 dev_priv->display.off(crtc);
5150
5151 if (crtc->primary->fb) {
5152 mutex_lock(&dev->struct_mutex);
5153 intel_unpin_fb_obj(old_obj);
5154 i915_gem_track_fb(old_obj, NULL,
5155 INTEL_FRONTBUFFER_PRIMARY(pipe));
5156 mutex_unlock(&dev->struct_mutex);
5157 crtc->primary->fb = NULL;
5158 }
5159
5160 /* Update computed state. */
5161 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5162 if (!connector->encoder || !connector->encoder->crtc)
5163 continue;
5164
5165 if (connector->encoder->crtc != crtc)
5166 continue;
5167
5168 connector->dpms = DRM_MODE_DPMS_OFF;
5169 to_intel_encoder(connector->encoder)->connectors_active = false;
5170 }
5171 }
5172
5173 void intel_encoder_destroy(struct drm_encoder *encoder)
5174 {
5175 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5176
5177 drm_encoder_cleanup(encoder);
5178 kfree(intel_encoder);
5179 }
5180
5181 /* Simple dpms helper for encoders with just one connector, no cloning and only
5182 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5183 * state of the entire output pipe. */
5184 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5185 {
5186 if (mode == DRM_MODE_DPMS_ON) {
5187 encoder->connectors_active = true;
5188
5189 intel_crtc_update_dpms(encoder->base.crtc);
5190 } else {
5191 encoder->connectors_active = false;
5192
5193 intel_crtc_update_dpms(encoder->base.crtc);
5194 }
5195 }
5196
5197 /* Cross check the actual hw state with our own modeset state tracking (and it's
5198 * internal consistency). */
5199 static void intel_connector_check_state(struct intel_connector *connector)
5200 {
5201 if (connector->get_hw_state(connector)) {
5202 struct intel_encoder *encoder = connector->encoder;
5203 struct drm_crtc *crtc;
5204 bool encoder_enabled;
5205 enum pipe pipe;
5206
5207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5208 connector->base.base.id,
5209 connector->base.name);
5210
5211 /* there is no real hw state for MST connectors */
5212 if (connector->mst_port)
5213 return;
5214
5215 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5216 "wrong connector dpms state\n");
5217 WARN(connector->base.encoder != &encoder->base,
5218 "active connector not linked to encoder\n");
5219
5220 if (encoder) {
5221 WARN(!encoder->connectors_active,
5222 "encoder->connectors_active not set\n");
5223
5224 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5225 WARN(!encoder_enabled, "encoder not enabled\n");
5226 if (WARN_ON(!encoder->base.crtc))
5227 return;
5228
5229 crtc = encoder->base.crtc;
5230
5231 WARN(!crtc->enabled, "crtc not enabled\n");
5232 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5233 WARN(pipe != to_intel_crtc(crtc)->pipe,
5234 "encoder active on the wrong pipe\n");
5235 }
5236 }
5237 }
5238
5239 /* Even simpler default implementation, if there's really no special case to
5240 * consider. */
5241 void intel_connector_dpms(struct drm_connector *connector, int mode)
5242 {
5243 /* All the simple cases only support two dpms states. */
5244 if (mode != DRM_MODE_DPMS_ON)
5245 mode = DRM_MODE_DPMS_OFF;
5246
5247 if (mode == connector->dpms)
5248 return;
5249
5250 connector->dpms = mode;
5251
5252 /* Only need to change hw state when actually enabled */
5253 if (connector->encoder)
5254 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5255
5256 intel_modeset_check_state(connector->dev);
5257 }
5258
5259 /* Simple connector->get_hw_state implementation for encoders that support only
5260 * one connector and no cloning and hence the encoder state determines the state
5261 * of the connector. */
5262 bool intel_connector_get_hw_state(struct intel_connector *connector)
5263 {
5264 enum pipe pipe = 0;
5265 struct intel_encoder *encoder = connector->encoder;
5266
5267 return encoder->get_hw_state(encoder, &pipe);
5268 }
5269
5270 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5271 struct intel_crtc_config *pipe_config)
5272 {
5273 struct drm_i915_private *dev_priv = dev->dev_private;
5274 struct intel_crtc *pipe_B_crtc =
5275 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5276
5277 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5278 pipe_name(pipe), pipe_config->fdi_lanes);
5279 if (pipe_config->fdi_lanes > 4) {
5280 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5281 pipe_name(pipe), pipe_config->fdi_lanes);
5282 return false;
5283 }
5284
5285 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5286 if (pipe_config->fdi_lanes > 2) {
5287 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5288 pipe_config->fdi_lanes);
5289 return false;
5290 } else {
5291 return true;
5292 }
5293 }
5294
5295 if (INTEL_INFO(dev)->num_pipes == 2)
5296 return true;
5297
5298 /* Ivybridge 3 pipe is really complicated */
5299 switch (pipe) {
5300 case PIPE_A:
5301 return true;
5302 case PIPE_B:
5303 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5304 pipe_config->fdi_lanes > 2) {
5305 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5306 pipe_name(pipe), pipe_config->fdi_lanes);
5307 return false;
5308 }
5309 return true;
5310 case PIPE_C:
5311 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5312 pipe_B_crtc->config.fdi_lanes <= 2) {
5313 if (pipe_config->fdi_lanes > 2) {
5314 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5315 pipe_name(pipe), pipe_config->fdi_lanes);
5316 return false;
5317 }
5318 } else {
5319 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5320 return false;
5321 }
5322 return true;
5323 default:
5324 BUG();
5325 }
5326 }
5327
5328 #define RETRY 1
5329 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5330 struct intel_crtc_config *pipe_config)
5331 {
5332 struct drm_device *dev = intel_crtc->base.dev;
5333 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5334 int lane, link_bw, fdi_dotclock;
5335 bool setup_ok, needs_recompute = false;
5336
5337 retry:
5338 /* FDI is a binary signal running at ~2.7GHz, encoding
5339 * each output octet as 10 bits. The actual frequency
5340 * is stored as a divider into a 100MHz clock, and the
5341 * mode pixel clock is stored in units of 1KHz.
5342 * Hence the bw of each lane in terms of the mode signal
5343 * is:
5344 */
5345 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5346
5347 fdi_dotclock = adjusted_mode->crtc_clock;
5348
5349 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5350 pipe_config->pipe_bpp);
5351
5352 pipe_config->fdi_lanes = lane;
5353
5354 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5355 link_bw, &pipe_config->fdi_m_n);
5356
5357 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5358 intel_crtc->pipe, pipe_config);
5359 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5360 pipe_config->pipe_bpp -= 2*3;
5361 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5362 pipe_config->pipe_bpp);
5363 needs_recompute = true;
5364 pipe_config->bw_constrained = true;
5365
5366 goto retry;
5367 }
5368
5369 if (needs_recompute)
5370 return RETRY;
5371
5372 return setup_ok ? 0 : -EINVAL;
5373 }
5374
5375 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5376 struct intel_crtc_config *pipe_config)
5377 {
5378 pipe_config->ips_enabled = i915.enable_ips &&
5379 hsw_crtc_supports_ips(crtc) &&
5380 pipe_config->pipe_bpp <= 24;
5381 }
5382
5383 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5384 struct intel_crtc_config *pipe_config)
5385 {
5386 struct drm_device *dev = crtc->base.dev;
5387 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5388
5389 /* FIXME should check pixel clock limits on all platforms */
5390 if (INTEL_INFO(dev)->gen < 4) {
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 int clock_limit =
5393 dev_priv->display.get_display_clock_speed(dev);
5394
5395 /*
5396 * Enable pixel doubling when the dot clock
5397 * is > 90% of the (display) core speed.
5398 *
5399 * GDG double wide on either pipe,
5400 * otherwise pipe A only.
5401 */
5402 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5403 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5404 clock_limit *= 2;
5405 pipe_config->double_wide = true;
5406 }
5407
5408 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5409 return -EINVAL;
5410 }
5411
5412 /*
5413 * Pipe horizontal size must be even in:
5414 * - DVO ganged mode
5415 * - LVDS dual channel mode
5416 * - Double wide pipe
5417 */
5418 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5419 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5420 pipe_config->pipe_src_w &= ~1;
5421
5422 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5423 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5424 */
5425 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5426 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5427 return -EINVAL;
5428
5429 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5430 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5431 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5432 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5433 * for lvds. */
5434 pipe_config->pipe_bpp = 8*3;
5435 }
5436
5437 if (HAS_IPS(dev))
5438 hsw_compute_ips_config(crtc, pipe_config);
5439
5440 /*
5441 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5442 * old clock survives for now.
5443 */
5444 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5445 pipe_config->shared_dpll = crtc->config.shared_dpll;
5446
5447 if (pipe_config->has_pch_encoder)
5448 return ironlake_fdi_compute_config(crtc, pipe_config);
5449
5450 return 0;
5451 }
5452
5453 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5454 {
5455 struct drm_i915_private *dev_priv = dev->dev_private;
5456 int vco = valleyview_get_vco(dev_priv);
5457 u32 val;
5458 int divider;
5459
5460 /* FIXME: Punit isn't quite ready yet */
5461 if (IS_CHERRYVIEW(dev))
5462 return 400000;
5463
5464 mutex_lock(&dev_priv->dpio_lock);
5465 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5466 mutex_unlock(&dev_priv->dpio_lock);
5467
5468 divider = val & DISPLAY_FREQUENCY_VALUES;
5469
5470 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5471 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5472 "cdclk change in progress\n");
5473
5474 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5475 }
5476
5477 static int i945_get_display_clock_speed(struct drm_device *dev)
5478 {
5479 return 400000;
5480 }
5481
5482 static int i915_get_display_clock_speed(struct drm_device *dev)
5483 {
5484 return 333000;
5485 }
5486
5487 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5488 {
5489 return 200000;
5490 }
5491
5492 static int pnv_get_display_clock_speed(struct drm_device *dev)
5493 {
5494 u16 gcfgc = 0;
5495
5496 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5497
5498 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5499 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5500 return 267000;
5501 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5502 return 333000;
5503 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5504 return 444000;
5505 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5506 return 200000;
5507 default:
5508 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5509 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5510 return 133000;
5511 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5512 return 167000;
5513 }
5514 }
5515
5516 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5517 {
5518 u16 gcfgc = 0;
5519
5520 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5521
5522 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5523 return 133000;
5524 else {
5525 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5526 case GC_DISPLAY_CLOCK_333_MHZ:
5527 return 333000;
5528 default:
5529 case GC_DISPLAY_CLOCK_190_200_MHZ:
5530 return 190000;
5531 }
5532 }
5533 }
5534
5535 static int i865_get_display_clock_speed(struct drm_device *dev)
5536 {
5537 return 266000;
5538 }
5539
5540 static int i855_get_display_clock_speed(struct drm_device *dev)
5541 {
5542 u16 hpllcc = 0;
5543 /* Assume that the hardware is in the high speed state. This
5544 * should be the default.
5545 */
5546 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5547 case GC_CLOCK_133_200:
5548 case GC_CLOCK_100_200:
5549 return 200000;
5550 case GC_CLOCK_166_250:
5551 return 250000;
5552 case GC_CLOCK_100_133:
5553 return 133000;
5554 }
5555
5556 /* Shouldn't happen */
5557 return 0;
5558 }
5559
5560 static int i830_get_display_clock_speed(struct drm_device *dev)
5561 {
5562 return 133000;
5563 }
5564
5565 static void
5566 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5567 {
5568 while (*num > DATA_LINK_M_N_MASK ||
5569 *den > DATA_LINK_M_N_MASK) {
5570 *num >>= 1;
5571 *den >>= 1;
5572 }
5573 }
5574
5575 static void compute_m_n(unsigned int m, unsigned int n,
5576 uint32_t *ret_m, uint32_t *ret_n)
5577 {
5578 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5579 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5580 intel_reduce_m_n_ratio(ret_m, ret_n);
5581 }
5582
5583 void
5584 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5585 int pixel_clock, int link_clock,
5586 struct intel_link_m_n *m_n)
5587 {
5588 m_n->tu = 64;
5589
5590 compute_m_n(bits_per_pixel * pixel_clock,
5591 link_clock * nlanes * 8,
5592 &m_n->gmch_m, &m_n->gmch_n);
5593
5594 compute_m_n(pixel_clock, link_clock,
5595 &m_n->link_m, &m_n->link_n);
5596 }
5597
5598 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5599 {
5600 if (i915.panel_use_ssc >= 0)
5601 return i915.panel_use_ssc != 0;
5602 return dev_priv->vbt.lvds_use_ssc
5603 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5604 }
5605
5606 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5607 {
5608 struct drm_device *dev = crtc->dev;
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 int refclk;
5611
5612 if (IS_VALLEYVIEW(dev)) {
5613 refclk = 100000;
5614 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5615 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5616 refclk = dev_priv->vbt.lvds_ssc_freq;
5617 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5618 } else if (!IS_GEN2(dev)) {
5619 refclk = 96000;
5620 } else {
5621 refclk = 48000;
5622 }
5623
5624 return refclk;
5625 }
5626
5627 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5628 {
5629 return (1 << dpll->n) << 16 | dpll->m2;
5630 }
5631
5632 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5633 {
5634 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5635 }
5636
5637 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5638 intel_clock_t *reduced_clock)
5639 {
5640 struct drm_device *dev = crtc->base.dev;
5641 u32 fp, fp2 = 0;
5642
5643 if (IS_PINEVIEW(dev)) {
5644 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5645 if (reduced_clock)
5646 fp2 = pnv_dpll_compute_fp(reduced_clock);
5647 } else {
5648 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5649 if (reduced_clock)
5650 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5651 }
5652
5653 crtc->config.dpll_hw_state.fp0 = fp;
5654
5655 crtc->lowfreq_avail = false;
5656 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5657 reduced_clock && i915.powersave) {
5658 crtc->config.dpll_hw_state.fp1 = fp2;
5659 crtc->lowfreq_avail = true;
5660 } else {
5661 crtc->config.dpll_hw_state.fp1 = fp;
5662 }
5663 }
5664
5665 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5666 pipe)
5667 {
5668 u32 reg_val;
5669
5670 /*
5671 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5672 * and set it to a reasonable value instead.
5673 */
5674 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5675 reg_val &= 0xffffff00;
5676 reg_val |= 0x00000030;
5677 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5678
5679 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5680 reg_val &= 0x8cffffff;
5681 reg_val = 0x8c000000;
5682 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5683
5684 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5685 reg_val &= 0xffffff00;
5686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5687
5688 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5689 reg_val &= 0x00ffffff;
5690 reg_val |= 0xb0000000;
5691 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5692 }
5693
5694 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5695 struct intel_link_m_n *m_n)
5696 {
5697 struct drm_device *dev = crtc->base.dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
5699 int pipe = crtc->pipe;
5700
5701 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5702 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5703 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5704 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5705 }
5706
5707 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5708 struct intel_link_m_n *m_n,
5709 struct intel_link_m_n *m2_n2)
5710 {
5711 struct drm_device *dev = crtc->base.dev;
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 int pipe = crtc->pipe;
5714 enum transcoder transcoder = crtc->config.cpu_transcoder;
5715
5716 if (INTEL_INFO(dev)->gen >= 5) {
5717 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5718 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5719 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5720 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5721 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5722 * for gen < 8) and if DRRS is supported (to make sure the
5723 * registers are not unnecessarily accessed).
5724 */
5725 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5726 crtc->config.has_drrs) {
5727 I915_WRITE(PIPE_DATA_M2(transcoder),
5728 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5729 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5730 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5731 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5732 }
5733 } else {
5734 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5735 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5736 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5737 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5738 }
5739 }
5740
5741 void intel_dp_set_m_n(struct intel_crtc *crtc)
5742 {
5743 if (crtc->config.has_pch_encoder)
5744 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5745 else
5746 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5747 &crtc->config.dp_m2_n2);
5748 }
5749
5750 static void vlv_update_pll(struct intel_crtc *crtc)
5751 {
5752 u32 dpll, dpll_md;
5753
5754 /*
5755 * Enable DPIO clock input. We should never disable the reference
5756 * clock for pipe B, since VGA hotplug / manual detection depends
5757 * on it.
5758 */
5759 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5760 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5761 /* We should never disable this, set it here for state tracking */
5762 if (crtc->pipe == PIPE_B)
5763 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5764 dpll |= DPLL_VCO_ENABLE;
5765 crtc->config.dpll_hw_state.dpll = dpll;
5766
5767 dpll_md = (crtc->config.pixel_multiplier - 1)
5768 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5769 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5770 }
5771
5772 static void vlv_prepare_pll(struct intel_crtc *crtc)
5773 {
5774 struct drm_device *dev = crtc->base.dev;
5775 struct drm_i915_private *dev_priv = dev->dev_private;
5776 int pipe = crtc->pipe;
5777 u32 mdiv;
5778 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5779 u32 coreclk, reg_val;
5780
5781 mutex_lock(&dev_priv->dpio_lock);
5782
5783 bestn = crtc->config.dpll.n;
5784 bestm1 = crtc->config.dpll.m1;
5785 bestm2 = crtc->config.dpll.m2;
5786 bestp1 = crtc->config.dpll.p1;
5787 bestp2 = crtc->config.dpll.p2;
5788
5789 /* See eDP HDMI DPIO driver vbios notes doc */
5790
5791 /* PLL B needs special handling */
5792 if (pipe == PIPE_B)
5793 vlv_pllb_recal_opamp(dev_priv, pipe);
5794
5795 /* Set up Tx target for periodic Rcomp update */
5796 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5797
5798 /* Disable target IRef on PLL */
5799 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5800 reg_val &= 0x00ffffff;
5801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5802
5803 /* Disable fast lock */
5804 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5805
5806 /* Set idtafcrecal before PLL is enabled */
5807 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5808 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5809 mdiv |= ((bestn << DPIO_N_SHIFT));
5810 mdiv |= (1 << DPIO_K_SHIFT);
5811
5812 /*
5813 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5814 * but we don't support that).
5815 * Note: don't use the DAC post divider as it seems unstable.
5816 */
5817 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5818 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5819
5820 mdiv |= DPIO_ENABLE_CALIBRATION;
5821 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5822
5823 /* Set HBR and RBR LPF coefficients */
5824 if (crtc->config.port_clock == 162000 ||
5825 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5826 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5827 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5828 0x009f0003);
5829 else
5830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5831 0x00d0000f);
5832
5833 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5834 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5835 /* Use SSC source */
5836 if (pipe == PIPE_A)
5837 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5838 0x0df40000);
5839 else
5840 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5841 0x0df70000);
5842 } else { /* HDMI or VGA */
5843 /* Use bend source */
5844 if (pipe == PIPE_A)
5845 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5846 0x0df70000);
5847 else
5848 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5849 0x0df40000);
5850 }
5851
5852 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5853 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5854 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5855 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5856 coreclk |= 0x01000000;
5857 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5858
5859 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5860 mutex_unlock(&dev_priv->dpio_lock);
5861 }
5862
5863 static void chv_update_pll(struct intel_crtc *crtc)
5864 {
5865 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5866 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5867 DPLL_VCO_ENABLE;
5868 if (crtc->pipe != PIPE_A)
5869 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5870
5871 crtc->config.dpll_hw_state.dpll_md =
5872 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5873 }
5874
5875 static void chv_prepare_pll(struct intel_crtc *crtc)
5876 {
5877 struct drm_device *dev = crtc->base.dev;
5878 struct drm_i915_private *dev_priv = dev->dev_private;
5879 int pipe = crtc->pipe;
5880 int dpll_reg = DPLL(crtc->pipe);
5881 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5882 u32 loopfilter, intcoeff;
5883 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5884 int refclk;
5885
5886 bestn = crtc->config.dpll.n;
5887 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5888 bestm1 = crtc->config.dpll.m1;
5889 bestm2 = crtc->config.dpll.m2 >> 22;
5890 bestp1 = crtc->config.dpll.p1;
5891 bestp2 = crtc->config.dpll.p2;
5892
5893 /*
5894 * Enable Refclk and SSC
5895 */
5896 I915_WRITE(dpll_reg,
5897 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5898
5899 mutex_lock(&dev_priv->dpio_lock);
5900
5901 /* p1 and p2 divider */
5902 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5903 5 << DPIO_CHV_S1_DIV_SHIFT |
5904 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5905 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5906 1 << DPIO_CHV_K_DIV_SHIFT);
5907
5908 /* Feedback post-divider - m2 */
5909 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5910
5911 /* Feedback refclk divider - n and m1 */
5912 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5913 DPIO_CHV_M1_DIV_BY_2 |
5914 1 << DPIO_CHV_N_DIV_SHIFT);
5915
5916 /* M2 fraction division */
5917 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5918
5919 /* M2 fraction division enable */
5920 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5921 DPIO_CHV_FRAC_DIV_EN |
5922 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5923
5924 /* Loop filter */
5925 refclk = i9xx_get_refclk(&crtc->base, 0);
5926 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5927 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5928 if (refclk == 100000)
5929 intcoeff = 11;
5930 else if (refclk == 38400)
5931 intcoeff = 10;
5932 else
5933 intcoeff = 9;
5934 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5935 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5936
5937 /* AFC Recal */
5938 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5939 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5940 DPIO_AFC_RECAL);
5941
5942 mutex_unlock(&dev_priv->dpio_lock);
5943 }
5944
5945 static void i9xx_update_pll(struct intel_crtc *crtc,
5946 intel_clock_t *reduced_clock,
5947 int num_connectors)
5948 {
5949 struct drm_device *dev = crtc->base.dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 u32 dpll;
5952 bool is_sdvo;
5953 struct dpll *clock = &crtc->config.dpll;
5954
5955 i9xx_update_pll_dividers(crtc, reduced_clock);
5956
5957 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5958 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5959
5960 dpll = DPLL_VGA_MODE_DIS;
5961
5962 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5963 dpll |= DPLLB_MODE_LVDS;
5964 else
5965 dpll |= DPLLB_MODE_DAC_SERIAL;
5966
5967 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5968 dpll |= (crtc->config.pixel_multiplier - 1)
5969 << SDVO_MULTIPLIER_SHIFT_HIRES;
5970 }
5971
5972 if (is_sdvo)
5973 dpll |= DPLL_SDVO_HIGH_SPEED;
5974
5975 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5976 dpll |= DPLL_SDVO_HIGH_SPEED;
5977
5978 /* compute bitmask from p1 value */
5979 if (IS_PINEVIEW(dev))
5980 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5981 else {
5982 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5983 if (IS_G4X(dev) && reduced_clock)
5984 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5985 }
5986 switch (clock->p2) {
5987 case 5:
5988 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5989 break;
5990 case 7:
5991 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5992 break;
5993 case 10:
5994 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5995 break;
5996 case 14:
5997 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5998 break;
5999 }
6000 if (INTEL_INFO(dev)->gen >= 4)
6001 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6002
6003 if (crtc->config.sdvo_tv_clock)
6004 dpll |= PLL_REF_INPUT_TVCLKINBC;
6005 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
6006 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6007 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6008 else
6009 dpll |= PLL_REF_INPUT_DREFCLK;
6010
6011 dpll |= DPLL_VCO_ENABLE;
6012 crtc->config.dpll_hw_state.dpll = dpll;
6013
6014 if (INTEL_INFO(dev)->gen >= 4) {
6015 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6016 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6017 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6018 }
6019 }
6020
6021 static void i8xx_update_pll(struct intel_crtc *crtc,
6022 intel_clock_t *reduced_clock,
6023 int num_connectors)
6024 {
6025 struct drm_device *dev = crtc->base.dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
6027 u32 dpll;
6028 struct dpll *clock = &crtc->config.dpll;
6029
6030 i9xx_update_pll_dividers(crtc, reduced_clock);
6031
6032 dpll = DPLL_VGA_MODE_DIS;
6033
6034 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
6035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6036 } else {
6037 if (clock->p1 == 2)
6038 dpll |= PLL_P1_DIVIDE_BY_TWO;
6039 else
6040 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6041 if (clock->p2 == 4)
6042 dpll |= PLL_P2_DIVIDE_BY_4;
6043 }
6044
6045 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
6046 dpll |= DPLL_DVO_2X_MODE;
6047
6048 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
6049 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6050 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6051 else
6052 dpll |= PLL_REF_INPUT_DREFCLK;
6053
6054 dpll |= DPLL_VCO_ENABLE;
6055 crtc->config.dpll_hw_state.dpll = dpll;
6056 }
6057
6058 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6059 {
6060 struct drm_device *dev = intel_crtc->base.dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 enum pipe pipe = intel_crtc->pipe;
6063 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6064 struct drm_display_mode *adjusted_mode =
6065 &intel_crtc->config.adjusted_mode;
6066 uint32_t crtc_vtotal, crtc_vblank_end;
6067 int vsyncshift = 0;
6068
6069 /* We need to be careful not to changed the adjusted mode, for otherwise
6070 * the hw state checker will get angry at the mismatch. */
6071 crtc_vtotal = adjusted_mode->crtc_vtotal;
6072 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6073
6074 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6075 /* the chip adds 2 halflines automatically */
6076 crtc_vtotal -= 1;
6077 crtc_vblank_end -= 1;
6078
6079 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6080 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6081 else
6082 vsyncshift = adjusted_mode->crtc_hsync_start -
6083 adjusted_mode->crtc_htotal / 2;
6084 if (vsyncshift < 0)
6085 vsyncshift += adjusted_mode->crtc_htotal;
6086 }
6087
6088 if (INTEL_INFO(dev)->gen > 3)
6089 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6090
6091 I915_WRITE(HTOTAL(cpu_transcoder),
6092 (adjusted_mode->crtc_hdisplay - 1) |
6093 ((adjusted_mode->crtc_htotal - 1) << 16));
6094 I915_WRITE(HBLANK(cpu_transcoder),
6095 (adjusted_mode->crtc_hblank_start - 1) |
6096 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6097 I915_WRITE(HSYNC(cpu_transcoder),
6098 (adjusted_mode->crtc_hsync_start - 1) |
6099 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6100
6101 I915_WRITE(VTOTAL(cpu_transcoder),
6102 (adjusted_mode->crtc_vdisplay - 1) |
6103 ((crtc_vtotal - 1) << 16));
6104 I915_WRITE(VBLANK(cpu_transcoder),
6105 (adjusted_mode->crtc_vblank_start - 1) |
6106 ((crtc_vblank_end - 1) << 16));
6107 I915_WRITE(VSYNC(cpu_transcoder),
6108 (adjusted_mode->crtc_vsync_start - 1) |
6109 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6110
6111 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6112 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6113 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6114 * bits. */
6115 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6116 (pipe == PIPE_B || pipe == PIPE_C))
6117 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6118
6119 /* pipesrc controls the size that is scaled from, which should
6120 * always be the user's requested size.
6121 */
6122 I915_WRITE(PIPESRC(pipe),
6123 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6124 (intel_crtc->config.pipe_src_h - 1));
6125 }
6126
6127 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6128 struct intel_crtc_config *pipe_config)
6129 {
6130 struct drm_device *dev = crtc->base.dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6133 uint32_t tmp;
6134
6135 tmp = I915_READ(HTOTAL(cpu_transcoder));
6136 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6137 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6138 tmp = I915_READ(HBLANK(cpu_transcoder));
6139 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6140 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6141 tmp = I915_READ(HSYNC(cpu_transcoder));
6142 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6143 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6144
6145 tmp = I915_READ(VTOTAL(cpu_transcoder));
6146 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6147 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6148 tmp = I915_READ(VBLANK(cpu_transcoder));
6149 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6150 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6151 tmp = I915_READ(VSYNC(cpu_transcoder));
6152 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6153 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6154
6155 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6156 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6157 pipe_config->adjusted_mode.crtc_vtotal += 1;
6158 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6159 }
6160
6161 tmp = I915_READ(PIPESRC(crtc->pipe));
6162 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6163 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6164
6165 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6166 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6167 }
6168
6169 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6170 struct intel_crtc_config *pipe_config)
6171 {
6172 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6173 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6174 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6175 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6176
6177 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6178 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6179 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6180 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6181
6182 mode->flags = pipe_config->adjusted_mode.flags;
6183
6184 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6185 mode->flags |= pipe_config->adjusted_mode.flags;
6186 }
6187
6188 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6189 {
6190 struct drm_device *dev = intel_crtc->base.dev;
6191 struct drm_i915_private *dev_priv = dev->dev_private;
6192 uint32_t pipeconf;
6193
6194 pipeconf = 0;
6195
6196 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6197 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6198 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6199
6200 if (intel_crtc->config.double_wide)
6201 pipeconf |= PIPECONF_DOUBLE_WIDE;
6202
6203 /* only g4x and later have fancy bpc/dither controls */
6204 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6205 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6206 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6207 pipeconf |= PIPECONF_DITHER_EN |
6208 PIPECONF_DITHER_TYPE_SP;
6209
6210 switch (intel_crtc->config.pipe_bpp) {
6211 case 18:
6212 pipeconf |= PIPECONF_6BPC;
6213 break;
6214 case 24:
6215 pipeconf |= PIPECONF_8BPC;
6216 break;
6217 case 30:
6218 pipeconf |= PIPECONF_10BPC;
6219 break;
6220 default:
6221 /* Case prevented by intel_choose_pipe_bpp_dither. */
6222 BUG();
6223 }
6224 }
6225
6226 if (HAS_PIPE_CXSR(dev)) {
6227 if (intel_crtc->lowfreq_avail) {
6228 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6229 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6230 } else {
6231 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6232 }
6233 }
6234
6235 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6236 if (INTEL_INFO(dev)->gen < 4 ||
6237 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6238 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6239 else
6240 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6241 } else
6242 pipeconf |= PIPECONF_PROGRESSIVE;
6243
6244 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6245 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6246
6247 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6248 POSTING_READ(PIPECONF(intel_crtc->pipe));
6249 }
6250
6251 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6252 int x, int y,
6253 struct drm_framebuffer *fb)
6254 {
6255 struct drm_device *dev = crtc->dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6258 int refclk, num_connectors = 0;
6259 intel_clock_t clock, reduced_clock;
6260 bool ok, has_reduced_clock = false;
6261 bool is_lvds = false, is_dsi = false;
6262 struct intel_encoder *encoder;
6263 const intel_limit_t *limit;
6264
6265 for_each_encoder_on_crtc(dev, crtc, encoder) {
6266 switch (encoder->type) {
6267 case INTEL_OUTPUT_LVDS:
6268 is_lvds = true;
6269 break;
6270 case INTEL_OUTPUT_DSI:
6271 is_dsi = true;
6272 break;
6273 }
6274
6275 num_connectors++;
6276 }
6277
6278 if (is_dsi)
6279 return 0;
6280
6281 if (!intel_crtc->config.clock_set) {
6282 refclk = i9xx_get_refclk(crtc, num_connectors);
6283
6284 /*
6285 * Returns a set of divisors for the desired target clock with
6286 * the given refclk, or FALSE. The returned values represent
6287 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6288 * 2) / p1 / p2.
6289 */
6290 limit = intel_limit(crtc, refclk);
6291 ok = dev_priv->display.find_dpll(limit, crtc,
6292 intel_crtc->config.port_clock,
6293 refclk, NULL, &clock);
6294 if (!ok) {
6295 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6296 return -EINVAL;
6297 }
6298
6299 if (is_lvds && dev_priv->lvds_downclock_avail) {
6300 /*
6301 * Ensure we match the reduced clock's P to the target
6302 * clock. If the clocks don't match, we can't switch
6303 * the display clock by using the FP0/FP1. In such case
6304 * we will disable the LVDS downclock feature.
6305 */
6306 has_reduced_clock =
6307 dev_priv->display.find_dpll(limit, crtc,
6308 dev_priv->lvds_downclock,
6309 refclk, &clock,
6310 &reduced_clock);
6311 }
6312 /* Compat-code for transition, will disappear. */
6313 intel_crtc->config.dpll.n = clock.n;
6314 intel_crtc->config.dpll.m1 = clock.m1;
6315 intel_crtc->config.dpll.m2 = clock.m2;
6316 intel_crtc->config.dpll.p1 = clock.p1;
6317 intel_crtc->config.dpll.p2 = clock.p2;
6318 }
6319
6320 if (IS_GEN2(dev)) {
6321 i8xx_update_pll(intel_crtc,
6322 has_reduced_clock ? &reduced_clock : NULL,
6323 num_connectors);
6324 } else if (IS_CHERRYVIEW(dev)) {
6325 chv_update_pll(intel_crtc);
6326 } else if (IS_VALLEYVIEW(dev)) {
6327 vlv_update_pll(intel_crtc);
6328 } else {
6329 i9xx_update_pll(intel_crtc,
6330 has_reduced_clock ? &reduced_clock : NULL,
6331 num_connectors);
6332 }
6333
6334 return 0;
6335 }
6336
6337 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6338 struct intel_crtc_config *pipe_config)
6339 {
6340 struct drm_device *dev = crtc->base.dev;
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 uint32_t tmp;
6343
6344 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6345 return;
6346
6347 tmp = I915_READ(PFIT_CONTROL);
6348 if (!(tmp & PFIT_ENABLE))
6349 return;
6350
6351 /* Check whether the pfit is attached to our pipe. */
6352 if (INTEL_INFO(dev)->gen < 4) {
6353 if (crtc->pipe != PIPE_B)
6354 return;
6355 } else {
6356 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6357 return;
6358 }
6359
6360 pipe_config->gmch_pfit.control = tmp;
6361 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6362 if (INTEL_INFO(dev)->gen < 5)
6363 pipe_config->gmch_pfit.lvds_border_bits =
6364 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6365 }
6366
6367 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6368 struct intel_crtc_config *pipe_config)
6369 {
6370 struct drm_device *dev = crtc->base.dev;
6371 struct drm_i915_private *dev_priv = dev->dev_private;
6372 int pipe = pipe_config->cpu_transcoder;
6373 intel_clock_t clock;
6374 u32 mdiv;
6375 int refclk = 100000;
6376
6377 /* In case of MIPI DPLL will not even be used */
6378 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6379 return;
6380
6381 mutex_lock(&dev_priv->dpio_lock);
6382 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6383 mutex_unlock(&dev_priv->dpio_lock);
6384
6385 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6386 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6387 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6388 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6389 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6390
6391 vlv_clock(refclk, &clock);
6392
6393 /* clock.dot is the fast clock */
6394 pipe_config->port_clock = clock.dot / 5;
6395 }
6396
6397 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6398 struct intel_plane_config *plane_config)
6399 {
6400 struct drm_device *dev = crtc->base.dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 u32 val, base, offset;
6403 int pipe = crtc->pipe, plane = crtc->plane;
6404 int fourcc, pixel_format;
6405 int aligned_height;
6406
6407 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6408 if (!crtc->base.primary->fb) {
6409 DRM_DEBUG_KMS("failed to alloc fb\n");
6410 return;
6411 }
6412
6413 val = I915_READ(DSPCNTR(plane));
6414
6415 if (INTEL_INFO(dev)->gen >= 4)
6416 if (val & DISPPLANE_TILED)
6417 plane_config->tiled = true;
6418
6419 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6420 fourcc = intel_format_to_fourcc(pixel_format);
6421 crtc->base.primary->fb->pixel_format = fourcc;
6422 crtc->base.primary->fb->bits_per_pixel =
6423 drm_format_plane_cpp(fourcc, 0) * 8;
6424
6425 if (INTEL_INFO(dev)->gen >= 4) {
6426 if (plane_config->tiled)
6427 offset = I915_READ(DSPTILEOFF(plane));
6428 else
6429 offset = I915_READ(DSPLINOFF(plane));
6430 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6431 } else {
6432 base = I915_READ(DSPADDR(plane));
6433 }
6434 plane_config->base = base;
6435
6436 val = I915_READ(PIPESRC(pipe));
6437 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6438 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6439
6440 val = I915_READ(DSPSTRIDE(pipe));
6441 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6442
6443 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6444 plane_config->tiled);
6445
6446 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6447 aligned_height);
6448
6449 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6450 pipe, plane, crtc->base.primary->fb->width,
6451 crtc->base.primary->fb->height,
6452 crtc->base.primary->fb->bits_per_pixel, base,
6453 crtc->base.primary->fb->pitches[0],
6454 plane_config->size);
6455
6456 }
6457
6458 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6459 struct intel_crtc_config *pipe_config)
6460 {
6461 struct drm_device *dev = crtc->base.dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 int pipe = pipe_config->cpu_transcoder;
6464 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6465 intel_clock_t clock;
6466 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6467 int refclk = 100000;
6468
6469 mutex_lock(&dev_priv->dpio_lock);
6470 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6471 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6472 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6473 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6474 mutex_unlock(&dev_priv->dpio_lock);
6475
6476 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6477 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6478 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6479 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6480 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6481
6482 chv_clock(refclk, &clock);
6483
6484 /* clock.dot is the fast clock */
6485 pipe_config->port_clock = clock.dot / 5;
6486 }
6487
6488 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6489 struct intel_crtc_config *pipe_config)
6490 {
6491 struct drm_device *dev = crtc->base.dev;
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 uint32_t tmp;
6494
6495 if (!intel_display_power_enabled(dev_priv,
6496 POWER_DOMAIN_PIPE(crtc->pipe)))
6497 return false;
6498
6499 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6500 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6501
6502 tmp = I915_READ(PIPECONF(crtc->pipe));
6503 if (!(tmp & PIPECONF_ENABLE))
6504 return false;
6505
6506 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6507 switch (tmp & PIPECONF_BPC_MASK) {
6508 case PIPECONF_6BPC:
6509 pipe_config->pipe_bpp = 18;
6510 break;
6511 case PIPECONF_8BPC:
6512 pipe_config->pipe_bpp = 24;
6513 break;
6514 case PIPECONF_10BPC:
6515 pipe_config->pipe_bpp = 30;
6516 break;
6517 default:
6518 break;
6519 }
6520 }
6521
6522 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6523 pipe_config->limited_color_range = true;
6524
6525 if (INTEL_INFO(dev)->gen < 4)
6526 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6527
6528 intel_get_pipe_timings(crtc, pipe_config);
6529
6530 i9xx_get_pfit_config(crtc, pipe_config);
6531
6532 if (INTEL_INFO(dev)->gen >= 4) {
6533 tmp = I915_READ(DPLL_MD(crtc->pipe));
6534 pipe_config->pixel_multiplier =
6535 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6536 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6537 pipe_config->dpll_hw_state.dpll_md = tmp;
6538 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6539 tmp = I915_READ(DPLL(crtc->pipe));
6540 pipe_config->pixel_multiplier =
6541 ((tmp & SDVO_MULTIPLIER_MASK)
6542 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6543 } else {
6544 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6545 * port and will be fixed up in the encoder->get_config
6546 * function. */
6547 pipe_config->pixel_multiplier = 1;
6548 }
6549 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6550 if (!IS_VALLEYVIEW(dev)) {
6551 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6552 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6553 } else {
6554 /* Mask out read-only status bits. */
6555 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6556 DPLL_PORTC_READY_MASK |
6557 DPLL_PORTB_READY_MASK);
6558 }
6559
6560 if (IS_CHERRYVIEW(dev))
6561 chv_crtc_clock_get(crtc, pipe_config);
6562 else if (IS_VALLEYVIEW(dev))
6563 vlv_crtc_clock_get(crtc, pipe_config);
6564 else
6565 i9xx_crtc_clock_get(crtc, pipe_config);
6566
6567 return true;
6568 }
6569
6570 static void ironlake_init_pch_refclk(struct drm_device *dev)
6571 {
6572 struct drm_i915_private *dev_priv = dev->dev_private;
6573 struct intel_encoder *encoder;
6574 u32 val, final;
6575 bool has_lvds = false;
6576 bool has_cpu_edp = false;
6577 bool has_panel = false;
6578 bool has_ck505 = false;
6579 bool can_ssc = false;
6580
6581 /* We need to take the global config into account */
6582 for_each_intel_encoder(dev, encoder) {
6583 switch (encoder->type) {
6584 case INTEL_OUTPUT_LVDS:
6585 has_panel = true;
6586 has_lvds = true;
6587 break;
6588 case INTEL_OUTPUT_EDP:
6589 has_panel = true;
6590 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6591 has_cpu_edp = true;
6592 break;
6593 }
6594 }
6595
6596 if (HAS_PCH_IBX(dev)) {
6597 has_ck505 = dev_priv->vbt.display_clock_mode;
6598 can_ssc = has_ck505;
6599 } else {
6600 has_ck505 = false;
6601 can_ssc = true;
6602 }
6603
6604 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6605 has_panel, has_lvds, has_ck505);
6606
6607 /* Ironlake: try to setup display ref clock before DPLL
6608 * enabling. This is only under driver's control after
6609 * PCH B stepping, previous chipset stepping should be
6610 * ignoring this setting.
6611 */
6612 val = I915_READ(PCH_DREF_CONTROL);
6613
6614 /* As we must carefully and slowly disable/enable each source in turn,
6615 * compute the final state we want first and check if we need to
6616 * make any changes at all.
6617 */
6618 final = val;
6619 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6620 if (has_ck505)
6621 final |= DREF_NONSPREAD_CK505_ENABLE;
6622 else
6623 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6624
6625 final &= ~DREF_SSC_SOURCE_MASK;
6626 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6627 final &= ~DREF_SSC1_ENABLE;
6628
6629 if (has_panel) {
6630 final |= DREF_SSC_SOURCE_ENABLE;
6631
6632 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6633 final |= DREF_SSC1_ENABLE;
6634
6635 if (has_cpu_edp) {
6636 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6637 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6638 else
6639 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6640 } else
6641 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6642 } else {
6643 final |= DREF_SSC_SOURCE_DISABLE;
6644 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6645 }
6646
6647 if (final == val)
6648 return;
6649
6650 /* Always enable nonspread source */
6651 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6652
6653 if (has_ck505)
6654 val |= DREF_NONSPREAD_CK505_ENABLE;
6655 else
6656 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6657
6658 if (has_panel) {
6659 val &= ~DREF_SSC_SOURCE_MASK;
6660 val |= DREF_SSC_SOURCE_ENABLE;
6661
6662 /* SSC must be turned on before enabling the CPU output */
6663 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6664 DRM_DEBUG_KMS("Using SSC on panel\n");
6665 val |= DREF_SSC1_ENABLE;
6666 } else
6667 val &= ~DREF_SSC1_ENABLE;
6668
6669 /* Get SSC going before enabling the outputs */
6670 I915_WRITE(PCH_DREF_CONTROL, val);
6671 POSTING_READ(PCH_DREF_CONTROL);
6672 udelay(200);
6673
6674 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6675
6676 /* Enable CPU source on CPU attached eDP */
6677 if (has_cpu_edp) {
6678 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6679 DRM_DEBUG_KMS("Using SSC on eDP\n");
6680 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6681 } else
6682 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6683 } else
6684 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6685
6686 I915_WRITE(PCH_DREF_CONTROL, val);
6687 POSTING_READ(PCH_DREF_CONTROL);
6688 udelay(200);
6689 } else {
6690 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6691
6692 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6693
6694 /* Turn off CPU output */
6695 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6696
6697 I915_WRITE(PCH_DREF_CONTROL, val);
6698 POSTING_READ(PCH_DREF_CONTROL);
6699 udelay(200);
6700
6701 /* Turn off the SSC source */
6702 val &= ~DREF_SSC_SOURCE_MASK;
6703 val |= DREF_SSC_SOURCE_DISABLE;
6704
6705 /* Turn off SSC1 */
6706 val &= ~DREF_SSC1_ENABLE;
6707
6708 I915_WRITE(PCH_DREF_CONTROL, val);
6709 POSTING_READ(PCH_DREF_CONTROL);
6710 udelay(200);
6711 }
6712
6713 BUG_ON(val != final);
6714 }
6715
6716 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6717 {
6718 uint32_t tmp;
6719
6720 tmp = I915_READ(SOUTH_CHICKEN2);
6721 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6722 I915_WRITE(SOUTH_CHICKEN2, tmp);
6723
6724 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6725 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6726 DRM_ERROR("FDI mPHY reset assert timeout\n");
6727
6728 tmp = I915_READ(SOUTH_CHICKEN2);
6729 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6730 I915_WRITE(SOUTH_CHICKEN2, tmp);
6731
6732 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6733 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6734 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6735 }
6736
6737 /* WaMPhyProgramming:hsw */
6738 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6739 {
6740 uint32_t tmp;
6741
6742 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6743 tmp &= ~(0xFF << 24);
6744 tmp |= (0x12 << 24);
6745 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6746
6747 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6748 tmp |= (1 << 11);
6749 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6750
6751 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6752 tmp |= (1 << 11);
6753 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6754
6755 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6756 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6757 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6758
6759 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6760 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6761 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6762
6763 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6764 tmp &= ~(7 << 13);
6765 tmp |= (5 << 13);
6766 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6767
6768 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6769 tmp &= ~(7 << 13);
6770 tmp |= (5 << 13);
6771 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6772
6773 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6774 tmp &= ~0xFF;
6775 tmp |= 0x1C;
6776 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6777
6778 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6779 tmp &= ~0xFF;
6780 tmp |= 0x1C;
6781 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6782
6783 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6784 tmp &= ~(0xFF << 16);
6785 tmp |= (0x1C << 16);
6786 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6787
6788 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6789 tmp &= ~(0xFF << 16);
6790 tmp |= (0x1C << 16);
6791 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6792
6793 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6794 tmp |= (1 << 27);
6795 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6796
6797 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6798 tmp |= (1 << 27);
6799 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6800
6801 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6802 tmp &= ~(0xF << 28);
6803 tmp |= (4 << 28);
6804 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6805
6806 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6807 tmp &= ~(0xF << 28);
6808 tmp |= (4 << 28);
6809 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6810 }
6811
6812 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6813 * Programming" based on the parameters passed:
6814 * - Sequence to enable CLKOUT_DP
6815 * - Sequence to enable CLKOUT_DP without spread
6816 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6817 */
6818 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6819 bool with_fdi)
6820 {
6821 struct drm_i915_private *dev_priv = dev->dev_private;
6822 uint32_t reg, tmp;
6823
6824 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6825 with_spread = true;
6826 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6827 with_fdi, "LP PCH doesn't have FDI\n"))
6828 with_fdi = false;
6829
6830 mutex_lock(&dev_priv->dpio_lock);
6831
6832 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6833 tmp &= ~SBI_SSCCTL_DISABLE;
6834 tmp |= SBI_SSCCTL_PATHALT;
6835 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6836
6837 udelay(24);
6838
6839 if (with_spread) {
6840 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6841 tmp &= ~SBI_SSCCTL_PATHALT;
6842 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6843
6844 if (with_fdi) {
6845 lpt_reset_fdi_mphy(dev_priv);
6846 lpt_program_fdi_mphy(dev_priv);
6847 }
6848 }
6849
6850 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6851 SBI_GEN0 : SBI_DBUFF0;
6852 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6853 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6854 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6855
6856 mutex_unlock(&dev_priv->dpio_lock);
6857 }
6858
6859 /* Sequence to disable CLKOUT_DP */
6860 static void lpt_disable_clkout_dp(struct drm_device *dev)
6861 {
6862 struct drm_i915_private *dev_priv = dev->dev_private;
6863 uint32_t reg, tmp;
6864
6865 mutex_lock(&dev_priv->dpio_lock);
6866
6867 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6868 SBI_GEN0 : SBI_DBUFF0;
6869 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6870 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6871 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6872
6873 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6874 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6875 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6876 tmp |= SBI_SSCCTL_PATHALT;
6877 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6878 udelay(32);
6879 }
6880 tmp |= SBI_SSCCTL_DISABLE;
6881 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6882 }
6883
6884 mutex_unlock(&dev_priv->dpio_lock);
6885 }
6886
6887 static void lpt_init_pch_refclk(struct drm_device *dev)
6888 {
6889 struct intel_encoder *encoder;
6890 bool has_vga = false;
6891
6892 for_each_intel_encoder(dev, encoder) {
6893 switch (encoder->type) {
6894 case INTEL_OUTPUT_ANALOG:
6895 has_vga = true;
6896 break;
6897 }
6898 }
6899
6900 if (has_vga)
6901 lpt_enable_clkout_dp(dev, true, true);
6902 else
6903 lpt_disable_clkout_dp(dev);
6904 }
6905
6906 /*
6907 * Initialize reference clocks when the driver loads
6908 */
6909 void intel_init_pch_refclk(struct drm_device *dev)
6910 {
6911 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6912 ironlake_init_pch_refclk(dev);
6913 else if (HAS_PCH_LPT(dev))
6914 lpt_init_pch_refclk(dev);
6915 }
6916
6917 static int ironlake_get_refclk(struct drm_crtc *crtc)
6918 {
6919 struct drm_device *dev = crtc->dev;
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 struct intel_encoder *encoder;
6922 int num_connectors = 0;
6923 bool is_lvds = false;
6924
6925 for_each_encoder_on_crtc(dev, crtc, encoder) {
6926 switch (encoder->type) {
6927 case INTEL_OUTPUT_LVDS:
6928 is_lvds = true;
6929 break;
6930 }
6931 num_connectors++;
6932 }
6933
6934 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6935 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6936 dev_priv->vbt.lvds_ssc_freq);
6937 return dev_priv->vbt.lvds_ssc_freq;
6938 }
6939
6940 return 120000;
6941 }
6942
6943 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6944 {
6945 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6947 int pipe = intel_crtc->pipe;
6948 uint32_t val;
6949
6950 val = 0;
6951
6952 switch (intel_crtc->config.pipe_bpp) {
6953 case 18:
6954 val |= PIPECONF_6BPC;
6955 break;
6956 case 24:
6957 val |= PIPECONF_8BPC;
6958 break;
6959 case 30:
6960 val |= PIPECONF_10BPC;
6961 break;
6962 case 36:
6963 val |= PIPECONF_12BPC;
6964 break;
6965 default:
6966 /* Case prevented by intel_choose_pipe_bpp_dither. */
6967 BUG();
6968 }
6969
6970 if (intel_crtc->config.dither)
6971 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6972
6973 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6974 val |= PIPECONF_INTERLACED_ILK;
6975 else
6976 val |= PIPECONF_PROGRESSIVE;
6977
6978 if (intel_crtc->config.limited_color_range)
6979 val |= PIPECONF_COLOR_RANGE_SELECT;
6980
6981 I915_WRITE(PIPECONF(pipe), val);
6982 POSTING_READ(PIPECONF(pipe));
6983 }
6984
6985 /*
6986 * Set up the pipe CSC unit.
6987 *
6988 * Currently only full range RGB to limited range RGB conversion
6989 * is supported, but eventually this should handle various
6990 * RGB<->YCbCr scenarios as well.
6991 */
6992 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6993 {
6994 struct drm_device *dev = crtc->dev;
6995 struct drm_i915_private *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 int pipe = intel_crtc->pipe;
6998 uint16_t coeff = 0x7800; /* 1.0 */
6999
7000 /*
7001 * TODO: Check what kind of values actually come out of the pipe
7002 * with these coeff/postoff values and adjust to get the best
7003 * accuracy. Perhaps we even need to take the bpc value into
7004 * consideration.
7005 */
7006
7007 if (intel_crtc->config.limited_color_range)
7008 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7009
7010 /*
7011 * GY/GU and RY/RU should be the other way around according
7012 * to BSpec, but reality doesn't agree. Just set them up in
7013 * a way that results in the correct picture.
7014 */
7015 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7016 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7017
7018 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7019 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7020
7021 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7022 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7023
7024 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7025 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7026 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7027
7028 if (INTEL_INFO(dev)->gen > 6) {
7029 uint16_t postoff = 0;
7030
7031 if (intel_crtc->config.limited_color_range)
7032 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7033
7034 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7035 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7036 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7037
7038 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7039 } else {
7040 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7041
7042 if (intel_crtc->config.limited_color_range)
7043 mode |= CSC_BLACK_SCREEN_OFFSET;
7044
7045 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7046 }
7047 }
7048
7049 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7050 {
7051 struct drm_device *dev = crtc->dev;
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054 enum pipe pipe = intel_crtc->pipe;
7055 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7056 uint32_t val;
7057
7058 val = 0;
7059
7060 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7061 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7062
7063 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7064 val |= PIPECONF_INTERLACED_ILK;
7065 else
7066 val |= PIPECONF_PROGRESSIVE;
7067
7068 I915_WRITE(PIPECONF(cpu_transcoder), val);
7069 POSTING_READ(PIPECONF(cpu_transcoder));
7070
7071 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7072 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7073
7074 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7075 val = 0;
7076
7077 switch (intel_crtc->config.pipe_bpp) {
7078 case 18:
7079 val |= PIPEMISC_DITHER_6_BPC;
7080 break;
7081 case 24:
7082 val |= PIPEMISC_DITHER_8_BPC;
7083 break;
7084 case 30:
7085 val |= PIPEMISC_DITHER_10_BPC;
7086 break;
7087 case 36:
7088 val |= PIPEMISC_DITHER_12_BPC;
7089 break;
7090 default:
7091 /* Case prevented by pipe_config_set_bpp. */
7092 BUG();
7093 }
7094
7095 if (intel_crtc->config.dither)
7096 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7097
7098 I915_WRITE(PIPEMISC(pipe), val);
7099 }
7100 }
7101
7102 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7103 intel_clock_t *clock,
7104 bool *has_reduced_clock,
7105 intel_clock_t *reduced_clock)
7106 {
7107 struct drm_device *dev = crtc->dev;
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 struct intel_encoder *intel_encoder;
7110 int refclk;
7111 const intel_limit_t *limit;
7112 bool ret, is_lvds = false;
7113
7114 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7115 switch (intel_encoder->type) {
7116 case INTEL_OUTPUT_LVDS:
7117 is_lvds = true;
7118 break;
7119 }
7120 }
7121
7122 refclk = ironlake_get_refclk(crtc);
7123
7124 /*
7125 * Returns a set of divisors for the desired target clock with the given
7126 * refclk, or FALSE. The returned values represent the clock equation:
7127 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7128 */
7129 limit = intel_limit(crtc, refclk);
7130 ret = dev_priv->display.find_dpll(limit, crtc,
7131 to_intel_crtc(crtc)->config.port_clock,
7132 refclk, NULL, clock);
7133 if (!ret)
7134 return false;
7135
7136 if (is_lvds && dev_priv->lvds_downclock_avail) {
7137 /*
7138 * Ensure we match the reduced clock's P to the target clock.
7139 * If the clocks don't match, we can't switch the display clock
7140 * by using the FP0/FP1. In such case we will disable the LVDS
7141 * downclock feature.
7142 */
7143 *has_reduced_clock =
7144 dev_priv->display.find_dpll(limit, crtc,
7145 dev_priv->lvds_downclock,
7146 refclk, clock,
7147 reduced_clock);
7148 }
7149
7150 return true;
7151 }
7152
7153 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7154 {
7155 /*
7156 * Account for spread spectrum to avoid
7157 * oversubscribing the link. Max center spread
7158 * is 2.5%; use 5% for safety's sake.
7159 */
7160 u32 bps = target_clock * bpp * 21 / 20;
7161 return DIV_ROUND_UP(bps, link_bw * 8);
7162 }
7163
7164 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7165 {
7166 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7167 }
7168
7169 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7170 u32 *fp,
7171 intel_clock_t *reduced_clock, u32 *fp2)
7172 {
7173 struct drm_crtc *crtc = &intel_crtc->base;
7174 struct drm_device *dev = crtc->dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 struct intel_encoder *intel_encoder;
7177 uint32_t dpll;
7178 int factor, num_connectors = 0;
7179 bool is_lvds = false, is_sdvo = false;
7180
7181 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7182 switch (intel_encoder->type) {
7183 case INTEL_OUTPUT_LVDS:
7184 is_lvds = true;
7185 break;
7186 case INTEL_OUTPUT_SDVO:
7187 case INTEL_OUTPUT_HDMI:
7188 is_sdvo = true;
7189 break;
7190 }
7191
7192 num_connectors++;
7193 }
7194
7195 /* Enable autotuning of the PLL clock (if permissible) */
7196 factor = 21;
7197 if (is_lvds) {
7198 if ((intel_panel_use_ssc(dev_priv) &&
7199 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7200 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7201 factor = 25;
7202 } else if (intel_crtc->config.sdvo_tv_clock)
7203 factor = 20;
7204
7205 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7206 *fp |= FP_CB_TUNE;
7207
7208 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7209 *fp2 |= FP_CB_TUNE;
7210
7211 dpll = 0;
7212
7213 if (is_lvds)
7214 dpll |= DPLLB_MODE_LVDS;
7215 else
7216 dpll |= DPLLB_MODE_DAC_SERIAL;
7217
7218 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7219 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7220
7221 if (is_sdvo)
7222 dpll |= DPLL_SDVO_HIGH_SPEED;
7223 if (intel_crtc->config.has_dp_encoder)
7224 dpll |= DPLL_SDVO_HIGH_SPEED;
7225
7226 /* compute bitmask from p1 value */
7227 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7228 /* also FPA1 */
7229 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7230
7231 switch (intel_crtc->config.dpll.p2) {
7232 case 5:
7233 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7234 break;
7235 case 7:
7236 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7237 break;
7238 case 10:
7239 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7240 break;
7241 case 14:
7242 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7243 break;
7244 }
7245
7246 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7248 else
7249 dpll |= PLL_REF_INPUT_DREFCLK;
7250
7251 return dpll | DPLL_VCO_ENABLE;
7252 }
7253
7254 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7255 int x, int y,
7256 struct drm_framebuffer *fb)
7257 {
7258 struct drm_device *dev = crtc->dev;
7259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7260 int num_connectors = 0;
7261 intel_clock_t clock, reduced_clock;
7262 u32 dpll = 0, fp = 0, fp2 = 0;
7263 bool ok, has_reduced_clock = false;
7264 bool is_lvds = false;
7265 struct intel_encoder *encoder;
7266 struct intel_shared_dpll *pll;
7267
7268 for_each_encoder_on_crtc(dev, crtc, encoder) {
7269 switch (encoder->type) {
7270 case INTEL_OUTPUT_LVDS:
7271 is_lvds = true;
7272 break;
7273 }
7274
7275 num_connectors++;
7276 }
7277
7278 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7279 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7280
7281 ok = ironlake_compute_clocks(crtc, &clock,
7282 &has_reduced_clock, &reduced_clock);
7283 if (!ok && !intel_crtc->config.clock_set) {
7284 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7285 return -EINVAL;
7286 }
7287 /* Compat-code for transition, will disappear. */
7288 if (!intel_crtc->config.clock_set) {
7289 intel_crtc->config.dpll.n = clock.n;
7290 intel_crtc->config.dpll.m1 = clock.m1;
7291 intel_crtc->config.dpll.m2 = clock.m2;
7292 intel_crtc->config.dpll.p1 = clock.p1;
7293 intel_crtc->config.dpll.p2 = clock.p2;
7294 }
7295
7296 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7297 if (intel_crtc->config.has_pch_encoder) {
7298 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7299 if (has_reduced_clock)
7300 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7301
7302 dpll = ironlake_compute_dpll(intel_crtc,
7303 &fp, &reduced_clock,
7304 has_reduced_clock ? &fp2 : NULL);
7305
7306 intel_crtc->config.dpll_hw_state.dpll = dpll;
7307 intel_crtc->config.dpll_hw_state.fp0 = fp;
7308 if (has_reduced_clock)
7309 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7310 else
7311 intel_crtc->config.dpll_hw_state.fp1 = fp;
7312
7313 pll = intel_get_shared_dpll(intel_crtc);
7314 if (pll == NULL) {
7315 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7316 pipe_name(intel_crtc->pipe));
7317 return -EINVAL;
7318 }
7319 } else
7320 intel_put_shared_dpll(intel_crtc);
7321
7322 if (is_lvds && has_reduced_clock && i915.powersave)
7323 intel_crtc->lowfreq_avail = true;
7324 else
7325 intel_crtc->lowfreq_avail = false;
7326
7327 return 0;
7328 }
7329
7330 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7331 struct intel_link_m_n *m_n)
7332 {
7333 struct drm_device *dev = crtc->base.dev;
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 enum pipe pipe = crtc->pipe;
7336
7337 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7338 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7339 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7340 & ~TU_SIZE_MASK;
7341 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7342 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7343 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7344 }
7345
7346 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7347 enum transcoder transcoder,
7348 struct intel_link_m_n *m_n,
7349 struct intel_link_m_n *m2_n2)
7350 {
7351 struct drm_device *dev = crtc->base.dev;
7352 struct drm_i915_private *dev_priv = dev->dev_private;
7353 enum pipe pipe = crtc->pipe;
7354
7355 if (INTEL_INFO(dev)->gen >= 5) {
7356 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7357 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7358 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7359 & ~TU_SIZE_MASK;
7360 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7361 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7362 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7363 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7364 * gen < 8) and if DRRS is supported (to make sure the
7365 * registers are not unnecessarily read).
7366 */
7367 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7368 crtc->config.has_drrs) {
7369 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7370 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7371 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7372 & ~TU_SIZE_MASK;
7373 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7374 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7375 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7376 }
7377 } else {
7378 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7379 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7380 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7381 & ~TU_SIZE_MASK;
7382 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7383 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7384 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7385 }
7386 }
7387
7388 void intel_dp_get_m_n(struct intel_crtc *crtc,
7389 struct intel_crtc_config *pipe_config)
7390 {
7391 if (crtc->config.has_pch_encoder)
7392 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7393 else
7394 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7395 &pipe_config->dp_m_n,
7396 &pipe_config->dp_m2_n2);
7397 }
7398
7399 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7400 struct intel_crtc_config *pipe_config)
7401 {
7402 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7403 &pipe_config->fdi_m_n, NULL);
7404 }
7405
7406 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7407 struct intel_crtc_config *pipe_config)
7408 {
7409 struct drm_device *dev = crtc->base.dev;
7410 struct drm_i915_private *dev_priv = dev->dev_private;
7411 uint32_t tmp;
7412
7413 tmp = I915_READ(PF_CTL(crtc->pipe));
7414
7415 if (tmp & PF_ENABLE) {
7416 pipe_config->pch_pfit.enabled = true;
7417 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7418 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7419
7420 /* We currently do not free assignements of panel fitters on
7421 * ivb/hsw (since we don't use the higher upscaling modes which
7422 * differentiates them) so just WARN about this case for now. */
7423 if (IS_GEN7(dev)) {
7424 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7425 PF_PIPE_SEL_IVB(crtc->pipe));
7426 }
7427 }
7428 }
7429
7430 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7431 struct intel_plane_config *plane_config)
7432 {
7433 struct drm_device *dev = crtc->base.dev;
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435 u32 val, base, offset;
7436 int pipe = crtc->pipe, plane = crtc->plane;
7437 int fourcc, pixel_format;
7438 int aligned_height;
7439
7440 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7441 if (!crtc->base.primary->fb) {
7442 DRM_DEBUG_KMS("failed to alloc fb\n");
7443 return;
7444 }
7445
7446 val = I915_READ(DSPCNTR(plane));
7447
7448 if (INTEL_INFO(dev)->gen >= 4)
7449 if (val & DISPPLANE_TILED)
7450 plane_config->tiled = true;
7451
7452 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7453 fourcc = intel_format_to_fourcc(pixel_format);
7454 crtc->base.primary->fb->pixel_format = fourcc;
7455 crtc->base.primary->fb->bits_per_pixel =
7456 drm_format_plane_cpp(fourcc, 0) * 8;
7457
7458 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7459 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7460 offset = I915_READ(DSPOFFSET(plane));
7461 } else {
7462 if (plane_config->tiled)
7463 offset = I915_READ(DSPTILEOFF(plane));
7464 else
7465 offset = I915_READ(DSPLINOFF(plane));
7466 }
7467 plane_config->base = base;
7468
7469 val = I915_READ(PIPESRC(pipe));
7470 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7471 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7472
7473 val = I915_READ(DSPSTRIDE(pipe));
7474 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7475
7476 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7477 plane_config->tiled);
7478
7479 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7480 aligned_height);
7481
7482 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7483 pipe, plane, crtc->base.primary->fb->width,
7484 crtc->base.primary->fb->height,
7485 crtc->base.primary->fb->bits_per_pixel, base,
7486 crtc->base.primary->fb->pitches[0],
7487 plane_config->size);
7488 }
7489
7490 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7491 struct intel_crtc_config *pipe_config)
7492 {
7493 struct drm_device *dev = crtc->base.dev;
7494 struct drm_i915_private *dev_priv = dev->dev_private;
7495 uint32_t tmp;
7496
7497 if (!intel_display_power_enabled(dev_priv,
7498 POWER_DOMAIN_PIPE(crtc->pipe)))
7499 return false;
7500
7501 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7502 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7503
7504 tmp = I915_READ(PIPECONF(crtc->pipe));
7505 if (!(tmp & PIPECONF_ENABLE))
7506 return false;
7507
7508 switch (tmp & PIPECONF_BPC_MASK) {
7509 case PIPECONF_6BPC:
7510 pipe_config->pipe_bpp = 18;
7511 break;
7512 case PIPECONF_8BPC:
7513 pipe_config->pipe_bpp = 24;
7514 break;
7515 case PIPECONF_10BPC:
7516 pipe_config->pipe_bpp = 30;
7517 break;
7518 case PIPECONF_12BPC:
7519 pipe_config->pipe_bpp = 36;
7520 break;
7521 default:
7522 break;
7523 }
7524
7525 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7526 pipe_config->limited_color_range = true;
7527
7528 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7529 struct intel_shared_dpll *pll;
7530
7531 pipe_config->has_pch_encoder = true;
7532
7533 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7534 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7535 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7536
7537 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7538
7539 if (HAS_PCH_IBX(dev_priv->dev)) {
7540 pipe_config->shared_dpll =
7541 (enum intel_dpll_id) crtc->pipe;
7542 } else {
7543 tmp = I915_READ(PCH_DPLL_SEL);
7544 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7545 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7546 else
7547 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7548 }
7549
7550 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7551
7552 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7553 &pipe_config->dpll_hw_state));
7554
7555 tmp = pipe_config->dpll_hw_state.dpll;
7556 pipe_config->pixel_multiplier =
7557 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7558 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7559
7560 ironlake_pch_clock_get(crtc, pipe_config);
7561 } else {
7562 pipe_config->pixel_multiplier = 1;
7563 }
7564
7565 intel_get_pipe_timings(crtc, pipe_config);
7566
7567 ironlake_get_pfit_config(crtc, pipe_config);
7568
7569 return true;
7570 }
7571
7572 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7573 {
7574 struct drm_device *dev = dev_priv->dev;
7575 struct intel_crtc *crtc;
7576
7577 for_each_intel_crtc(dev, crtc)
7578 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7579 pipe_name(crtc->pipe));
7580
7581 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7582 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7583 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7584 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7585 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7586 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7587 "CPU PWM1 enabled\n");
7588 if (IS_HASWELL(dev))
7589 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7590 "CPU PWM2 enabled\n");
7591 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7592 "PCH PWM1 enabled\n");
7593 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7594 "Utility pin enabled\n");
7595 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7596
7597 /*
7598 * In theory we can still leave IRQs enabled, as long as only the HPD
7599 * interrupts remain enabled. We used to check for that, but since it's
7600 * gen-specific and since we only disable LCPLL after we fully disable
7601 * the interrupts, the check below should be enough.
7602 */
7603 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7604 }
7605
7606 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7607 {
7608 struct drm_device *dev = dev_priv->dev;
7609
7610 if (IS_HASWELL(dev))
7611 return I915_READ(D_COMP_HSW);
7612 else
7613 return I915_READ(D_COMP_BDW);
7614 }
7615
7616 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7617 {
7618 struct drm_device *dev = dev_priv->dev;
7619
7620 if (IS_HASWELL(dev)) {
7621 mutex_lock(&dev_priv->rps.hw_lock);
7622 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7623 val))
7624 DRM_ERROR("Failed to write to D_COMP\n");
7625 mutex_unlock(&dev_priv->rps.hw_lock);
7626 } else {
7627 I915_WRITE(D_COMP_BDW, val);
7628 POSTING_READ(D_COMP_BDW);
7629 }
7630 }
7631
7632 /*
7633 * This function implements pieces of two sequences from BSpec:
7634 * - Sequence for display software to disable LCPLL
7635 * - Sequence for display software to allow package C8+
7636 * The steps implemented here are just the steps that actually touch the LCPLL
7637 * register. Callers should take care of disabling all the display engine
7638 * functions, doing the mode unset, fixing interrupts, etc.
7639 */
7640 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7641 bool switch_to_fclk, bool allow_power_down)
7642 {
7643 uint32_t val;
7644
7645 assert_can_disable_lcpll(dev_priv);
7646
7647 val = I915_READ(LCPLL_CTL);
7648
7649 if (switch_to_fclk) {
7650 val |= LCPLL_CD_SOURCE_FCLK;
7651 I915_WRITE(LCPLL_CTL, val);
7652
7653 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7654 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7655 DRM_ERROR("Switching to FCLK failed\n");
7656
7657 val = I915_READ(LCPLL_CTL);
7658 }
7659
7660 val |= LCPLL_PLL_DISABLE;
7661 I915_WRITE(LCPLL_CTL, val);
7662 POSTING_READ(LCPLL_CTL);
7663
7664 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7665 DRM_ERROR("LCPLL still locked\n");
7666
7667 val = hsw_read_dcomp(dev_priv);
7668 val |= D_COMP_COMP_DISABLE;
7669 hsw_write_dcomp(dev_priv, val);
7670 ndelay(100);
7671
7672 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7673 1))
7674 DRM_ERROR("D_COMP RCOMP still in progress\n");
7675
7676 if (allow_power_down) {
7677 val = I915_READ(LCPLL_CTL);
7678 val |= LCPLL_POWER_DOWN_ALLOW;
7679 I915_WRITE(LCPLL_CTL, val);
7680 POSTING_READ(LCPLL_CTL);
7681 }
7682 }
7683
7684 /*
7685 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7686 * source.
7687 */
7688 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7689 {
7690 uint32_t val;
7691 unsigned long irqflags;
7692
7693 val = I915_READ(LCPLL_CTL);
7694
7695 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7696 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7697 return;
7698
7699 /*
7700 * Make sure we're not on PC8 state before disabling PC8, otherwise
7701 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7702 *
7703 * The other problem is that hsw_restore_lcpll() is called as part of
7704 * the runtime PM resume sequence, so we can't just call
7705 * gen6_gt_force_wake_get() because that function calls
7706 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7707 * while we are on the resume sequence. So to solve this problem we have
7708 * to call special forcewake code that doesn't touch runtime PM and
7709 * doesn't enable the forcewake delayed work.
7710 */
7711 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7712 if (dev_priv->uncore.forcewake_count++ == 0)
7713 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7714 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7715
7716 if (val & LCPLL_POWER_DOWN_ALLOW) {
7717 val &= ~LCPLL_POWER_DOWN_ALLOW;
7718 I915_WRITE(LCPLL_CTL, val);
7719 POSTING_READ(LCPLL_CTL);
7720 }
7721
7722 val = hsw_read_dcomp(dev_priv);
7723 val |= D_COMP_COMP_FORCE;
7724 val &= ~D_COMP_COMP_DISABLE;
7725 hsw_write_dcomp(dev_priv, val);
7726
7727 val = I915_READ(LCPLL_CTL);
7728 val &= ~LCPLL_PLL_DISABLE;
7729 I915_WRITE(LCPLL_CTL, val);
7730
7731 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7732 DRM_ERROR("LCPLL not locked yet\n");
7733
7734 if (val & LCPLL_CD_SOURCE_FCLK) {
7735 val = I915_READ(LCPLL_CTL);
7736 val &= ~LCPLL_CD_SOURCE_FCLK;
7737 I915_WRITE(LCPLL_CTL, val);
7738
7739 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7740 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7741 DRM_ERROR("Switching back to LCPLL failed\n");
7742 }
7743
7744 /* See the big comment above. */
7745 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7746 if (--dev_priv->uncore.forcewake_count == 0)
7747 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7748 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7749 }
7750
7751 /*
7752 * Package states C8 and deeper are really deep PC states that can only be
7753 * reached when all the devices on the system allow it, so even if the graphics
7754 * device allows PC8+, it doesn't mean the system will actually get to these
7755 * states. Our driver only allows PC8+ when going into runtime PM.
7756 *
7757 * The requirements for PC8+ are that all the outputs are disabled, the power
7758 * well is disabled and most interrupts are disabled, and these are also
7759 * requirements for runtime PM. When these conditions are met, we manually do
7760 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7761 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7762 * hang the machine.
7763 *
7764 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7765 * the state of some registers, so when we come back from PC8+ we need to
7766 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7767 * need to take care of the registers kept by RC6. Notice that this happens even
7768 * if we don't put the device in PCI D3 state (which is what currently happens
7769 * because of the runtime PM support).
7770 *
7771 * For more, read "Display Sequences for Package C8" on the hardware
7772 * documentation.
7773 */
7774 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7775 {
7776 struct drm_device *dev = dev_priv->dev;
7777 uint32_t val;
7778
7779 DRM_DEBUG_KMS("Enabling package C8+\n");
7780
7781 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7782 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7783 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7784 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7785 }
7786
7787 lpt_disable_clkout_dp(dev);
7788 hsw_disable_lcpll(dev_priv, true, true);
7789 }
7790
7791 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7792 {
7793 struct drm_device *dev = dev_priv->dev;
7794 uint32_t val;
7795
7796 DRM_DEBUG_KMS("Disabling package C8+\n");
7797
7798 hsw_restore_lcpll(dev_priv);
7799 lpt_init_pch_refclk(dev);
7800
7801 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7802 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7803 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7804 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7805 }
7806
7807 intel_prepare_ddi(dev);
7808 }
7809
7810 static void snb_modeset_global_resources(struct drm_device *dev)
7811 {
7812 modeset_update_crtc_power_domains(dev);
7813 }
7814
7815 static void haswell_modeset_global_resources(struct drm_device *dev)
7816 {
7817 modeset_update_crtc_power_domains(dev);
7818 }
7819
7820 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7821 int x, int y,
7822 struct drm_framebuffer *fb)
7823 {
7824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7825
7826 if (!intel_ddi_pll_select(intel_crtc))
7827 return -EINVAL;
7828
7829 intel_crtc->lowfreq_avail = false;
7830
7831 return 0;
7832 }
7833
7834 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7835 enum port port,
7836 struct intel_crtc_config *pipe_config)
7837 {
7838 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7839
7840 switch (pipe_config->ddi_pll_sel) {
7841 case PORT_CLK_SEL_WRPLL1:
7842 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7843 break;
7844 case PORT_CLK_SEL_WRPLL2:
7845 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7846 break;
7847 }
7848 }
7849
7850 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7851 struct intel_crtc_config *pipe_config)
7852 {
7853 struct drm_device *dev = crtc->base.dev;
7854 struct drm_i915_private *dev_priv = dev->dev_private;
7855 struct intel_shared_dpll *pll;
7856 enum port port;
7857 uint32_t tmp;
7858
7859 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7860
7861 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7862
7863 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7864
7865 if (pipe_config->shared_dpll >= 0) {
7866 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7867
7868 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7869 &pipe_config->dpll_hw_state));
7870 }
7871
7872 /*
7873 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7874 * DDI E. So just check whether this pipe is wired to DDI E and whether
7875 * the PCH transcoder is on.
7876 */
7877 if (INTEL_INFO(dev)->gen < 9 &&
7878 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7879 pipe_config->has_pch_encoder = true;
7880
7881 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7882 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7883 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7884
7885 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7886 }
7887 }
7888
7889 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7890 struct intel_crtc_config *pipe_config)
7891 {
7892 struct drm_device *dev = crtc->base.dev;
7893 struct drm_i915_private *dev_priv = dev->dev_private;
7894 enum intel_display_power_domain pfit_domain;
7895 uint32_t tmp;
7896
7897 if (!intel_display_power_enabled(dev_priv,
7898 POWER_DOMAIN_PIPE(crtc->pipe)))
7899 return false;
7900
7901 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7902 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7903
7904 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7905 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7906 enum pipe trans_edp_pipe;
7907 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7908 default:
7909 WARN(1, "unknown pipe linked to edp transcoder\n");
7910 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7911 case TRANS_DDI_EDP_INPUT_A_ON:
7912 trans_edp_pipe = PIPE_A;
7913 break;
7914 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7915 trans_edp_pipe = PIPE_B;
7916 break;
7917 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7918 trans_edp_pipe = PIPE_C;
7919 break;
7920 }
7921
7922 if (trans_edp_pipe == crtc->pipe)
7923 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7924 }
7925
7926 if (!intel_display_power_enabled(dev_priv,
7927 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7928 return false;
7929
7930 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7931 if (!(tmp & PIPECONF_ENABLE))
7932 return false;
7933
7934 haswell_get_ddi_port_state(crtc, pipe_config);
7935
7936 intel_get_pipe_timings(crtc, pipe_config);
7937
7938 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7939 if (intel_display_power_enabled(dev_priv, pfit_domain))
7940 ironlake_get_pfit_config(crtc, pipe_config);
7941
7942 if (IS_HASWELL(dev))
7943 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7944 (I915_READ(IPS_CTL) & IPS_ENABLE);
7945
7946 pipe_config->pixel_multiplier = 1;
7947
7948 return true;
7949 }
7950
7951 static struct {
7952 int clock;
7953 u32 config;
7954 } hdmi_audio_clock[] = {
7955 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7956 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7957 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7958 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7959 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7960 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7961 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7962 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7963 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7964 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7965 };
7966
7967 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7968 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7969 {
7970 int i;
7971
7972 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7973 if (mode->clock == hdmi_audio_clock[i].clock)
7974 break;
7975 }
7976
7977 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7978 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7979 i = 1;
7980 }
7981
7982 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7983 hdmi_audio_clock[i].clock,
7984 hdmi_audio_clock[i].config);
7985
7986 return hdmi_audio_clock[i].config;
7987 }
7988
7989 static bool intel_eld_uptodate(struct drm_connector *connector,
7990 int reg_eldv, uint32_t bits_eldv,
7991 int reg_elda, uint32_t bits_elda,
7992 int reg_edid)
7993 {
7994 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7995 uint8_t *eld = connector->eld;
7996 uint32_t i;
7997
7998 i = I915_READ(reg_eldv);
7999 i &= bits_eldv;
8000
8001 if (!eld[0])
8002 return !i;
8003
8004 if (!i)
8005 return false;
8006
8007 i = I915_READ(reg_elda);
8008 i &= ~bits_elda;
8009 I915_WRITE(reg_elda, i);
8010
8011 for (i = 0; i < eld[2]; i++)
8012 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8013 return false;
8014
8015 return true;
8016 }
8017
8018 static void g4x_write_eld(struct drm_connector *connector,
8019 struct drm_crtc *crtc,
8020 struct drm_display_mode *mode)
8021 {
8022 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8023 uint8_t *eld = connector->eld;
8024 uint32_t eldv;
8025 uint32_t len;
8026 uint32_t i;
8027
8028 i = I915_READ(G4X_AUD_VID_DID);
8029
8030 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8031 eldv = G4X_ELDV_DEVCL_DEVBLC;
8032 else
8033 eldv = G4X_ELDV_DEVCTG;
8034
8035 if (intel_eld_uptodate(connector,
8036 G4X_AUD_CNTL_ST, eldv,
8037 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8038 G4X_HDMIW_HDMIEDID))
8039 return;
8040
8041 i = I915_READ(G4X_AUD_CNTL_ST);
8042 i &= ~(eldv | G4X_ELD_ADDR);
8043 len = (i >> 9) & 0x1f; /* ELD buffer size */
8044 I915_WRITE(G4X_AUD_CNTL_ST, i);
8045
8046 if (!eld[0])
8047 return;
8048
8049 len = min_t(uint8_t, eld[2], len);
8050 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8051 for (i = 0; i < len; i++)
8052 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8053
8054 i = I915_READ(G4X_AUD_CNTL_ST);
8055 i |= eldv;
8056 I915_WRITE(G4X_AUD_CNTL_ST, i);
8057 }
8058
8059 static void haswell_write_eld(struct drm_connector *connector,
8060 struct drm_crtc *crtc,
8061 struct drm_display_mode *mode)
8062 {
8063 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8064 uint8_t *eld = connector->eld;
8065 uint32_t eldv;
8066 uint32_t i;
8067 int len;
8068 int pipe = to_intel_crtc(crtc)->pipe;
8069 int tmp;
8070
8071 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8072 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8073 int aud_config = HSW_AUD_CFG(pipe);
8074 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8075
8076 /* Audio output enable */
8077 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8078 tmp = I915_READ(aud_cntrl_st2);
8079 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8080 I915_WRITE(aud_cntrl_st2, tmp);
8081 POSTING_READ(aud_cntrl_st2);
8082
8083 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8084
8085 /* Set ELD valid state */
8086 tmp = I915_READ(aud_cntrl_st2);
8087 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8088 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8089 I915_WRITE(aud_cntrl_st2, tmp);
8090 tmp = I915_READ(aud_cntrl_st2);
8091 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8092
8093 /* Enable HDMI mode */
8094 tmp = I915_READ(aud_config);
8095 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8096 /* clear N_programing_enable and N_value_index */
8097 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8098 I915_WRITE(aud_config, tmp);
8099
8100 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8101
8102 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8103
8104 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8105 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8106 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8107 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8108 } else {
8109 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8110 }
8111
8112 if (intel_eld_uptodate(connector,
8113 aud_cntrl_st2, eldv,
8114 aud_cntl_st, IBX_ELD_ADDRESS,
8115 hdmiw_hdmiedid))
8116 return;
8117
8118 i = I915_READ(aud_cntrl_st2);
8119 i &= ~eldv;
8120 I915_WRITE(aud_cntrl_st2, i);
8121
8122 if (!eld[0])
8123 return;
8124
8125 i = I915_READ(aud_cntl_st);
8126 i &= ~IBX_ELD_ADDRESS;
8127 I915_WRITE(aud_cntl_st, i);
8128 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8129 DRM_DEBUG_DRIVER("port num:%d\n", i);
8130
8131 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8132 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8133 for (i = 0; i < len; i++)
8134 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8135
8136 i = I915_READ(aud_cntrl_st2);
8137 i |= eldv;
8138 I915_WRITE(aud_cntrl_st2, i);
8139
8140 }
8141
8142 static void ironlake_write_eld(struct drm_connector *connector,
8143 struct drm_crtc *crtc,
8144 struct drm_display_mode *mode)
8145 {
8146 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8147 uint8_t *eld = connector->eld;
8148 uint32_t eldv;
8149 uint32_t i;
8150 int len;
8151 int hdmiw_hdmiedid;
8152 int aud_config;
8153 int aud_cntl_st;
8154 int aud_cntrl_st2;
8155 int pipe = to_intel_crtc(crtc)->pipe;
8156
8157 if (HAS_PCH_IBX(connector->dev)) {
8158 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8159 aud_config = IBX_AUD_CFG(pipe);
8160 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8161 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8162 } else if (IS_VALLEYVIEW(connector->dev)) {
8163 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8164 aud_config = VLV_AUD_CFG(pipe);
8165 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8166 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8167 } else {
8168 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8169 aud_config = CPT_AUD_CFG(pipe);
8170 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8171 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8172 }
8173
8174 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8175
8176 if (IS_VALLEYVIEW(connector->dev)) {
8177 struct intel_encoder *intel_encoder;
8178 struct intel_digital_port *intel_dig_port;
8179
8180 intel_encoder = intel_attached_encoder(connector);
8181 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8182 i = intel_dig_port->port;
8183 } else {
8184 i = I915_READ(aud_cntl_st);
8185 i = (i >> 29) & DIP_PORT_SEL_MASK;
8186 /* DIP_Port_Select, 0x1 = PortB */
8187 }
8188
8189 if (!i) {
8190 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8191 /* operate blindly on all ports */
8192 eldv = IBX_ELD_VALIDB;
8193 eldv |= IBX_ELD_VALIDB << 4;
8194 eldv |= IBX_ELD_VALIDB << 8;
8195 } else {
8196 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8197 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8198 }
8199
8200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8201 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8202 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8203 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8204 } else {
8205 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8206 }
8207
8208 if (intel_eld_uptodate(connector,
8209 aud_cntrl_st2, eldv,
8210 aud_cntl_st, IBX_ELD_ADDRESS,
8211 hdmiw_hdmiedid))
8212 return;
8213
8214 i = I915_READ(aud_cntrl_st2);
8215 i &= ~eldv;
8216 I915_WRITE(aud_cntrl_st2, i);
8217
8218 if (!eld[0])
8219 return;
8220
8221 i = I915_READ(aud_cntl_st);
8222 i &= ~IBX_ELD_ADDRESS;
8223 I915_WRITE(aud_cntl_st, i);
8224
8225 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8226 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8227 for (i = 0; i < len; i++)
8228 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8229
8230 i = I915_READ(aud_cntrl_st2);
8231 i |= eldv;
8232 I915_WRITE(aud_cntrl_st2, i);
8233 }
8234
8235 void intel_write_eld(struct drm_encoder *encoder,
8236 struct drm_display_mode *mode)
8237 {
8238 struct drm_crtc *crtc = encoder->crtc;
8239 struct drm_connector *connector;
8240 struct drm_device *dev = encoder->dev;
8241 struct drm_i915_private *dev_priv = dev->dev_private;
8242
8243 connector = drm_select_eld(encoder, mode);
8244 if (!connector)
8245 return;
8246
8247 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8248 connector->base.id,
8249 connector->name,
8250 connector->encoder->base.id,
8251 connector->encoder->name);
8252
8253 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8254
8255 if (dev_priv->display.write_eld)
8256 dev_priv->display.write_eld(connector, crtc, mode);
8257 }
8258
8259 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8260 {
8261 struct drm_device *dev = crtc->dev;
8262 struct drm_i915_private *dev_priv = dev->dev_private;
8263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8264 uint32_t cntl = 0, size = 0;
8265
8266 if (base) {
8267 unsigned int width = intel_crtc->cursor_width;
8268 unsigned int height = intel_crtc->cursor_height;
8269 unsigned int stride = roundup_pow_of_two(width) * 4;
8270
8271 switch (stride) {
8272 default:
8273 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8274 width, stride);
8275 stride = 256;
8276 /* fallthrough */
8277 case 256:
8278 case 512:
8279 case 1024:
8280 case 2048:
8281 break;
8282 }
8283
8284 cntl |= CURSOR_ENABLE |
8285 CURSOR_GAMMA_ENABLE |
8286 CURSOR_FORMAT_ARGB |
8287 CURSOR_STRIDE(stride);
8288
8289 size = (height << 12) | width;
8290 }
8291
8292 if (intel_crtc->cursor_cntl != 0 &&
8293 (intel_crtc->cursor_base != base ||
8294 intel_crtc->cursor_size != size ||
8295 intel_crtc->cursor_cntl != cntl)) {
8296 /* On these chipsets we can only modify the base/size/stride
8297 * whilst the cursor is disabled.
8298 */
8299 I915_WRITE(_CURACNTR, 0);
8300 POSTING_READ(_CURACNTR);
8301 intel_crtc->cursor_cntl = 0;
8302 }
8303
8304 if (intel_crtc->cursor_base != base)
8305 I915_WRITE(_CURABASE, base);
8306
8307 if (intel_crtc->cursor_size != size) {
8308 I915_WRITE(CURSIZE, size);
8309 intel_crtc->cursor_size = size;
8310 }
8311
8312 if (intel_crtc->cursor_cntl != cntl) {
8313 I915_WRITE(_CURACNTR, cntl);
8314 POSTING_READ(_CURACNTR);
8315 intel_crtc->cursor_cntl = cntl;
8316 }
8317 }
8318
8319 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8320 {
8321 struct drm_device *dev = crtc->dev;
8322 struct drm_i915_private *dev_priv = dev->dev_private;
8323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8324 int pipe = intel_crtc->pipe;
8325 uint32_t cntl;
8326
8327 cntl = 0;
8328 if (base) {
8329 cntl = MCURSOR_GAMMA_ENABLE;
8330 switch (intel_crtc->cursor_width) {
8331 case 64:
8332 cntl |= CURSOR_MODE_64_ARGB_AX;
8333 break;
8334 case 128:
8335 cntl |= CURSOR_MODE_128_ARGB_AX;
8336 break;
8337 case 256:
8338 cntl |= CURSOR_MODE_256_ARGB_AX;
8339 break;
8340 default:
8341 WARN_ON(1);
8342 return;
8343 }
8344 cntl |= pipe << 28; /* Connect to correct pipe */
8345 }
8346 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8347 cntl |= CURSOR_PIPE_CSC_ENABLE;
8348
8349 if (intel_crtc->cursor_cntl != cntl) {
8350 I915_WRITE(CURCNTR(pipe), cntl);
8351 POSTING_READ(CURCNTR(pipe));
8352 intel_crtc->cursor_cntl = cntl;
8353 }
8354
8355 /* and commit changes on next vblank */
8356 I915_WRITE(CURBASE(pipe), base);
8357 POSTING_READ(CURBASE(pipe));
8358 }
8359
8360 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8361 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8362 bool on)
8363 {
8364 struct drm_device *dev = crtc->dev;
8365 struct drm_i915_private *dev_priv = dev->dev_private;
8366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8367 int pipe = intel_crtc->pipe;
8368 int x = crtc->cursor_x;
8369 int y = crtc->cursor_y;
8370 u32 base = 0, pos = 0;
8371
8372 if (on)
8373 base = intel_crtc->cursor_addr;
8374
8375 if (x >= intel_crtc->config.pipe_src_w)
8376 base = 0;
8377
8378 if (y >= intel_crtc->config.pipe_src_h)
8379 base = 0;
8380
8381 if (x < 0) {
8382 if (x + intel_crtc->cursor_width <= 0)
8383 base = 0;
8384
8385 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8386 x = -x;
8387 }
8388 pos |= x << CURSOR_X_SHIFT;
8389
8390 if (y < 0) {
8391 if (y + intel_crtc->cursor_height <= 0)
8392 base = 0;
8393
8394 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8395 y = -y;
8396 }
8397 pos |= y << CURSOR_Y_SHIFT;
8398
8399 if (base == 0 && intel_crtc->cursor_base == 0)
8400 return;
8401
8402 I915_WRITE(CURPOS(pipe), pos);
8403
8404 if (IS_845G(dev) || IS_I865G(dev))
8405 i845_update_cursor(crtc, base);
8406 else
8407 i9xx_update_cursor(crtc, base);
8408 intel_crtc->cursor_base = base;
8409 }
8410
8411 static bool cursor_size_ok(struct drm_device *dev,
8412 uint32_t width, uint32_t height)
8413 {
8414 if (width == 0 || height == 0)
8415 return false;
8416
8417 /*
8418 * 845g/865g are special in that they are only limited by
8419 * the width of their cursors, the height is arbitrary up to
8420 * the precision of the register. Everything else requires
8421 * square cursors, limited to a few power-of-two sizes.
8422 */
8423 if (IS_845G(dev) || IS_I865G(dev)) {
8424 if ((width & 63) != 0)
8425 return false;
8426
8427 if (width > (IS_845G(dev) ? 64 : 512))
8428 return false;
8429
8430 if (height > 1023)
8431 return false;
8432 } else {
8433 switch (width | height) {
8434 case 256:
8435 case 128:
8436 if (IS_GEN2(dev))
8437 return false;
8438 case 64:
8439 break;
8440 default:
8441 return false;
8442 }
8443 }
8444
8445 return true;
8446 }
8447
8448 /*
8449 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8450 *
8451 * Note that the object's reference will be consumed if the update fails. If
8452 * the update succeeds, the reference of the old object (if any) will be
8453 * consumed.
8454 */
8455 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8456 struct drm_i915_gem_object *obj,
8457 uint32_t width, uint32_t height)
8458 {
8459 struct drm_device *dev = crtc->dev;
8460 struct drm_i915_private *dev_priv = dev->dev_private;
8461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8462 enum pipe pipe = intel_crtc->pipe;
8463 unsigned old_width, stride;
8464 uint32_t addr;
8465 int ret;
8466
8467 /* if we want to turn off the cursor ignore width and height */
8468 if (!obj) {
8469 DRM_DEBUG_KMS("cursor off\n");
8470 addr = 0;
8471 mutex_lock(&dev->struct_mutex);
8472 goto finish;
8473 }
8474
8475 /* Check for which cursor types we support */
8476 if (!cursor_size_ok(dev, width, height)) {
8477 DRM_DEBUG("Cursor dimension not supported\n");
8478 return -EINVAL;
8479 }
8480
8481 stride = roundup_pow_of_two(width) * 4;
8482 if (obj->base.size < stride * height) {
8483 DRM_DEBUG_KMS("buffer is too small\n");
8484 ret = -ENOMEM;
8485 goto fail;
8486 }
8487
8488 /* we only need to pin inside GTT if cursor is non-phy */
8489 mutex_lock(&dev->struct_mutex);
8490 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8491 unsigned alignment;
8492
8493 if (obj->tiling_mode) {
8494 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8495 ret = -EINVAL;
8496 goto fail_locked;
8497 }
8498
8499 /*
8500 * Global gtt pte registers are special registers which actually
8501 * forward writes to a chunk of system memory. Which means that
8502 * there is no risk that the register values disappear as soon
8503 * as we call intel_runtime_pm_put(), so it is correct to wrap
8504 * only the pin/unpin/fence and not more.
8505 */
8506 intel_runtime_pm_get(dev_priv);
8507
8508 /* Note that the w/a also requires 2 PTE of padding following
8509 * the bo. We currently fill all unused PTE with the shadow
8510 * page and so we should always have valid PTE following the
8511 * cursor preventing the VT-d warning.
8512 */
8513 alignment = 0;
8514 if (need_vtd_wa(dev))
8515 alignment = 64*1024;
8516
8517 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8518 if (ret) {
8519 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8520 intel_runtime_pm_put(dev_priv);
8521 goto fail_locked;
8522 }
8523
8524 ret = i915_gem_object_put_fence(obj);
8525 if (ret) {
8526 DRM_DEBUG_KMS("failed to release fence for cursor");
8527 intel_runtime_pm_put(dev_priv);
8528 goto fail_unpin;
8529 }
8530
8531 addr = i915_gem_obj_ggtt_offset(obj);
8532
8533 intel_runtime_pm_put(dev_priv);
8534 } else {
8535 int align = IS_I830(dev) ? 16 * 1024 : 256;
8536 ret = i915_gem_object_attach_phys(obj, align);
8537 if (ret) {
8538 DRM_DEBUG_KMS("failed to attach phys object\n");
8539 goto fail_locked;
8540 }
8541 addr = obj->phys_handle->busaddr;
8542 }
8543
8544 finish:
8545 if (intel_crtc->cursor_bo) {
8546 if (!INTEL_INFO(dev)->cursor_needs_physical)
8547 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8548 }
8549
8550 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8551 INTEL_FRONTBUFFER_CURSOR(pipe));
8552 mutex_unlock(&dev->struct_mutex);
8553
8554 old_width = intel_crtc->cursor_width;
8555
8556 intel_crtc->cursor_addr = addr;
8557 intel_crtc->cursor_bo = obj;
8558 intel_crtc->cursor_width = width;
8559 intel_crtc->cursor_height = height;
8560
8561 if (intel_crtc->active) {
8562 if (old_width != width)
8563 intel_update_watermarks(crtc);
8564 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8565 }
8566
8567 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8568
8569 return 0;
8570 fail_unpin:
8571 i915_gem_object_unpin_from_display_plane(obj);
8572 fail_locked:
8573 mutex_unlock(&dev->struct_mutex);
8574 fail:
8575 drm_gem_object_unreference_unlocked(&obj->base);
8576 return ret;
8577 }
8578
8579 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8580 u16 *blue, uint32_t start, uint32_t size)
8581 {
8582 int end = (start + size > 256) ? 256 : start + size, i;
8583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8584
8585 for (i = start; i < end; i++) {
8586 intel_crtc->lut_r[i] = red[i] >> 8;
8587 intel_crtc->lut_g[i] = green[i] >> 8;
8588 intel_crtc->lut_b[i] = blue[i] >> 8;
8589 }
8590
8591 intel_crtc_load_lut(crtc);
8592 }
8593
8594 /* VESA 640x480x72Hz mode to set on the pipe */
8595 static struct drm_display_mode load_detect_mode = {
8596 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8597 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8598 };
8599
8600 struct drm_framebuffer *
8601 __intel_framebuffer_create(struct drm_device *dev,
8602 struct drm_mode_fb_cmd2 *mode_cmd,
8603 struct drm_i915_gem_object *obj)
8604 {
8605 struct intel_framebuffer *intel_fb;
8606 int ret;
8607
8608 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8609 if (!intel_fb) {
8610 drm_gem_object_unreference_unlocked(&obj->base);
8611 return ERR_PTR(-ENOMEM);
8612 }
8613
8614 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8615 if (ret)
8616 goto err;
8617
8618 return &intel_fb->base;
8619 err:
8620 drm_gem_object_unreference_unlocked(&obj->base);
8621 kfree(intel_fb);
8622
8623 return ERR_PTR(ret);
8624 }
8625
8626 static struct drm_framebuffer *
8627 intel_framebuffer_create(struct drm_device *dev,
8628 struct drm_mode_fb_cmd2 *mode_cmd,
8629 struct drm_i915_gem_object *obj)
8630 {
8631 struct drm_framebuffer *fb;
8632 int ret;
8633
8634 ret = i915_mutex_lock_interruptible(dev);
8635 if (ret)
8636 return ERR_PTR(ret);
8637 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8638 mutex_unlock(&dev->struct_mutex);
8639
8640 return fb;
8641 }
8642
8643 static u32
8644 intel_framebuffer_pitch_for_width(int width, int bpp)
8645 {
8646 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8647 return ALIGN(pitch, 64);
8648 }
8649
8650 static u32
8651 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8652 {
8653 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8654 return PAGE_ALIGN(pitch * mode->vdisplay);
8655 }
8656
8657 static struct drm_framebuffer *
8658 intel_framebuffer_create_for_mode(struct drm_device *dev,
8659 struct drm_display_mode *mode,
8660 int depth, int bpp)
8661 {
8662 struct drm_i915_gem_object *obj;
8663 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8664
8665 obj = i915_gem_alloc_object(dev,
8666 intel_framebuffer_size_for_mode(mode, bpp));
8667 if (obj == NULL)
8668 return ERR_PTR(-ENOMEM);
8669
8670 mode_cmd.width = mode->hdisplay;
8671 mode_cmd.height = mode->vdisplay;
8672 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8673 bpp);
8674 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8675
8676 return intel_framebuffer_create(dev, &mode_cmd, obj);
8677 }
8678
8679 static struct drm_framebuffer *
8680 mode_fits_in_fbdev(struct drm_device *dev,
8681 struct drm_display_mode *mode)
8682 {
8683 #ifdef CONFIG_DRM_I915_FBDEV
8684 struct drm_i915_private *dev_priv = dev->dev_private;
8685 struct drm_i915_gem_object *obj;
8686 struct drm_framebuffer *fb;
8687
8688 if (!dev_priv->fbdev)
8689 return NULL;
8690
8691 if (!dev_priv->fbdev->fb)
8692 return NULL;
8693
8694 obj = dev_priv->fbdev->fb->obj;
8695 BUG_ON(!obj);
8696
8697 fb = &dev_priv->fbdev->fb->base;
8698 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8699 fb->bits_per_pixel))
8700 return NULL;
8701
8702 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8703 return NULL;
8704
8705 return fb;
8706 #else
8707 return NULL;
8708 #endif
8709 }
8710
8711 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8712 struct drm_display_mode *mode,
8713 struct intel_load_detect_pipe *old,
8714 struct drm_modeset_acquire_ctx *ctx)
8715 {
8716 struct intel_crtc *intel_crtc;
8717 struct intel_encoder *intel_encoder =
8718 intel_attached_encoder(connector);
8719 struct drm_crtc *possible_crtc;
8720 struct drm_encoder *encoder = &intel_encoder->base;
8721 struct drm_crtc *crtc = NULL;
8722 struct drm_device *dev = encoder->dev;
8723 struct drm_framebuffer *fb;
8724 struct drm_mode_config *config = &dev->mode_config;
8725 int ret, i = -1;
8726
8727 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8728 connector->base.id, connector->name,
8729 encoder->base.id, encoder->name);
8730
8731 retry:
8732 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8733 if (ret)
8734 goto fail_unlock;
8735
8736 /*
8737 * Algorithm gets a little messy:
8738 *
8739 * - if the connector already has an assigned crtc, use it (but make
8740 * sure it's on first)
8741 *
8742 * - try to find the first unused crtc that can drive this connector,
8743 * and use that if we find one
8744 */
8745
8746 /* See if we already have a CRTC for this connector */
8747 if (encoder->crtc) {
8748 crtc = encoder->crtc;
8749
8750 ret = drm_modeset_lock(&crtc->mutex, ctx);
8751 if (ret)
8752 goto fail_unlock;
8753
8754 old->dpms_mode = connector->dpms;
8755 old->load_detect_temp = false;
8756
8757 /* Make sure the crtc and connector are running */
8758 if (connector->dpms != DRM_MODE_DPMS_ON)
8759 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8760
8761 return true;
8762 }
8763
8764 /* Find an unused one (if possible) */
8765 for_each_crtc(dev, possible_crtc) {
8766 i++;
8767 if (!(encoder->possible_crtcs & (1 << i)))
8768 continue;
8769 if (possible_crtc->enabled)
8770 continue;
8771 /* This can occur when applying the pipe A quirk on resume. */
8772 if (to_intel_crtc(possible_crtc)->new_enabled)
8773 continue;
8774
8775 crtc = possible_crtc;
8776 break;
8777 }
8778
8779 /*
8780 * If we didn't find an unused CRTC, don't use any.
8781 */
8782 if (!crtc) {
8783 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8784 goto fail_unlock;
8785 }
8786
8787 ret = drm_modeset_lock(&crtc->mutex, ctx);
8788 if (ret)
8789 goto fail_unlock;
8790 intel_encoder->new_crtc = to_intel_crtc(crtc);
8791 to_intel_connector(connector)->new_encoder = intel_encoder;
8792
8793 intel_crtc = to_intel_crtc(crtc);
8794 intel_crtc->new_enabled = true;
8795 intel_crtc->new_config = &intel_crtc->config;
8796 old->dpms_mode = connector->dpms;
8797 old->load_detect_temp = true;
8798 old->release_fb = NULL;
8799
8800 if (!mode)
8801 mode = &load_detect_mode;
8802
8803 /* We need a framebuffer large enough to accommodate all accesses
8804 * that the plane may generate whilst we perform load detection.
8805 * We can not rely on the fbcon either being present (we get called
8806 * during its initialisation to detect all boot displays, or it may
8807 * not even exist) or that it is large enough to satisfy the
8808 * requested mode.
8809 */
8810 fb = mode_fits_in_fbdev(dev, mode);
8811 if (fb == NULL) {
8812 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8813 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8814 old->release_fb = fb;
8815 } else
8816 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8817 if (IS_ERR(fb)) {
8818 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8819 goto fail;
8820 }
8821
8822 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8823 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8824 if (old->release_fb)
8825 old->release_fb->funcs->destroy(old->release_fb);
8826 goto fail;
8827 }
8828
8829 /* let the connector get through one full cycle before testing */
8830 intel_wait_for_vblank(dev, intel_crtc->pipe);
8831 return true;
8832
8833 fail:
8834 intel_crtc->new_enabled = crtc->enabled;
8835 if (intel_crtc->new_enabled)
8836 intel_crtc->new_config = &intel_crtc->config;
8837 else
8838 intel_crtc->new_config = NULL;
8839 fail_unlock:
8840 if (ret == -EDEADLK) {
8841 drm_modeset_backoff(ctx);
8842 goto retry;
8843 }
8844
8845 return false;
8846 }
8847
8848 void intel_release_load_detect_pipe(struct drm_connector *connector,
8849 struct intel_load_detect_pipe *old)
8850 {
8851 struct intel_encoder *intel_encoder =
8852 intel_attached_encoder(connector);
8853 struct drm_encoder *encoder = &intel_encoder->base;
8854 struct drm_crtc *crtc = encoder->crtc;
8855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8856
8857 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8858 connector->base.id, connector->name,
8859 encoder->base.id, encoder->name);
8860
8861 if (old->load_detect_temp) {
8862 to_intel_connector(connector)->new_encoder = NULL;
8863 intel_encoder->new_crtc = NULL;
8864 intel_crtc->new_enabled = false;
8865 intel_crtc->new_config = NULL;
8866 intel_set_mode(crtc, NULL, 0, 0, NULL);
8867
8868 if (old->release_fb) {
8869 drm_framebuffer_unregister_private(old->release_fb);
8870 drm_framebuffer_unreference(old->release_fb);
8871 }
8872
8873 return;
8874 }
8875
8876 /* Switch crtc and encoder back off if necessary */
8877 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8878 connector->funcs->dpms(connector, old->dpms_mode);
8879 }
8880
8881 static int i9xx_pll_refclk(struct drm_device *dev,
8882 const struct intel_crtc_config *pipe_config)
8883 {
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 u32 dpll = pipe_config->dpll_hw_state.dpll;
8886
8887 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8888 return dev_priv->vbt.lvds_ssc_freq;
8889 else if (HAS_PCH_SPLIT(dev))
8890 return 120000;
8891 else if (!IS_GEN2(dev))
8892 return 96000;
8893 else
8894 return 48000;
8895 }
8896
8897 /* Returns the clock of the currently programmed mode of the given pipe. */
8898 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8899 struct intel_crtc_config *pipe_config)
8900 {
8901 struct drm_device *dev = crtc->base.dev;
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903 int pipe = pipe_config->cpu_transcoder;
8904 u32 dpll = pipe_config->dpll_hw_state.dpll;
8905 u32 fp;
8906 intel_clock_t clock;
8907 int refclk = i9xx_pll_refclk(dev, pipe_config);
8908
8909 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8910 fp = pipe_config->dpll_hw_state.fp0;
8911 else
8912 fp = pipe_config->dpll_hw_state.fp1;
8913
8914 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8915 if (IS_PINEVIEW(dev)) {
8916 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8917 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8918 } else {
8919 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8920 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8921 }
8922
8923 if (!IS_GEN2(dev)) {
8924 if (IS_PINEVIEW(dev))
8925 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8926 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8927 else
8928 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8929 DPLL_FPA01_P1_POST_DIV_SHIFT);
8930
8931 switch (dpll & DPLL_MODE_MASK) {
8932 case DPLLB_MODE_DAC_SERIAL:
8933 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8934 5 : 10;
8935 break;
8936 case DPLLB_MODE_LVDS:
8937 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8938 7 : 14;
8939 break;
8940 default:
8941 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8942 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8943 return;
8944 }
8945
8946 if (IS_PINEVIEW(dev))
8947 pineview_clock(refclk, &clock);
8948 else
8949 i9xx_clock(refclk, &clock);
8950 } else {
8951 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8952 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8953
8954 if (is_lvds) {
8955 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8956 DPLL_FPA01_P1_POST_DIV_SHIFT);
8957
8958 if (lvds & LVDS_CLKB_POWER_UP)
8959 clock.p2 = 7;
8960 else
8961 clock.p2 = 14;
8962 } else {
8963 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8964 clock.p1 = 2;
8965 else {
8966 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8967 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8968 }
8969 if (dpll & PLL_P2_DIVIDE_BY_4)
8970 clock.p2 = 4;
8971 else
8972 clock.p2 = 2;
8973 }
8974
8975 i9xx_clock(refclk, &clock);
8976 }
8977
8978 /*
8979 * This value includes pixel_multiplier. We will use
8980 * port_clock to compute adjusted_mode.crtc_clock in the
8981 * encoder's get_config() function.
8982 */
8983 pipe_config->port_clock = clock.dot;
8984 }
8985
8986 int intel_dotclock_calculate(int link_freq,
8987 const struct intel_link_m_n *m_n)
8988 {
8989 /*
8990 * The calculation for the data clock is:
8991 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8992 * But we want to avoid losing precison if possible, so:
8993 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8994 *
8995 * and the link clock is simpler:
8996 * link_clock = (m * link_clock) / n
8997 */
8998
8999 if (!m_n->link_n)
9000 return 0;
9001
9002 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9003 }
9004
9005 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9006 struct intel_crtc_config *pipe_config)
9007 {
9008 struct drm_device *dev = crtc->base.dev;
9009
9010 /* read out port_clock from the DPLL */
9011 i9xx_crtc_clock_get(crtc, pipe_config);
9012
9013 /*
9014 * This value does not include pixel_multiplier.
9015 * We will check that port_clock and adjusted_mode.crtc_clock
9016 * agree once we know their relationship in the encoder's
9017 * get_config() function.
9018 */
9019 pipe_config->adjusted_mode.crtc_clock =
9020 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9021 &pipe_config->fdi_m_n);
9022 }
9023
9024 /** Returns the currently programmed mode of the given pipe. */
9025 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9026 struct drm_crtc *crtc)
9027 {
9028 struct drm_i915_private *dev_priv = dev->dev_private;
9029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9030 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
9031 struct drm_display_mode *mode;
9032 struct intel_crtc_config pipe_config;
9033 int htot = I915_READ(HTOTAL(cpu_transcoder));
9034 int hsync = I915_READ(HSYNC(cpu_transcoder));
9035 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9036 int vsync = I915_READ(VSYNC(cpu_transcoder));
9037 enum pipe pipe = intel_crtc->pipe;
9038
9039 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9040 if (!mode)
9041 return NULL;
9042
9043 /*
9044 * Construct a pipe_config sufficient for getting the clock info
9045 * back out of crtc_clock_get.
9046 *
9047 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9048 * to use a real value here instead.
9049 */
9050 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9051 pipe_config.pixel_multiplier = 1;
9052 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9053 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9054 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9055 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9056
9057 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9058 mode->hdisplay = (htot & 0xffff) + 1;
9059 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9060 mode->hsync_start = (hsync & 0xffff) + 1;
9061 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9062 mode->vdisplay = (vtot & 0xffff) + 1;
9063 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9064 mode->vsync_start = (vsync & 0xffff) + 1;
9065 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9066
9067 drm_mode_set_name(mode);
9068
9069 return mode;
9070 }
9071
9072 static void intel_increase_pllclock(struct drm_device *dev,
9073 enum pipe pipe)
9074 {
9075 struct drm_i915_private *dev_priv = dev->dev_private;
9076 int dpll_reg = DPLL(pipe);
9077 int dpll;
9078
9079 if (!HAS_GMCH_DISPLAY(dev))
9080 return;
9081
9082 if (!dev_priv->lvds_downclock_avail)
9083 return;
9084
9085 dpll = I915_READ(dpll_reg);
9086 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9087 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9088
9089 assert_panel_unlocked(dev_priv, pipe);
9090
9091 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9092 I915_WRITE(dpll_reg, dpll);
9093 intel_wait_for_vblank(dev, pipe);
9094
9095 dpll = I915_READ(dpll_reg);
9096 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9097 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9098 }
9099 }
9100
9101 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9102 {
9103 struct drm_device *dev = crtc->dev;
9104 struct drm_i915_private *dev_priv = dev->dev_private;
9105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9106
9107 if (!HAS_GMCH_DISPLAY(dev))
9108 return;
9109
9110 if (!dev_priv->lvds_downclock_avail)
9111 return;
9112
9113 /*
9114 * Since this is called by a timer, we should never get here in
9115 * the manual case.
9116 */
9117 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9118 int pipe = intel_crtc->pipe;
9119 int dpll_reg = DPLL(pipe);
9120 int dpll;
9121
9122 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9123
9124 assert_panel_unlocked(dev_priv, pipe);
9125
9126 dpll = I915_READ(dpll_reg);
9127 dpll |= DISPLAY_RATE_SELECT_FPA1;
9128 I915_WRITE(dpll_reg, dpll);
9129 intel_wait_for_vblank(dev, pipe);
9130 dpll = I915_READ(dpll_reg);
9131 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9132 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9133 }
9134
9135 }
9136
9137 void intel_mark_busy(struct drm_device *dev)
9138 {
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140
9141 if (dev_priv->mm.busy)
9142 return;
9143
9144 intel_runtime_pm_get(dev_priv);
9145 i915_update_gfx_val(dev_priv);
9146 dev_priv->mm.busy = true;
9147 }
9148
9149 void intel_mark_idle(struct drm_device *dev)
9150 {
9151 struct drm_i915_private *dev_priv = dev->dev_private;
9152 struct drm_crtc *crtc;
9153
9154 if (!dev_priv->mm.busy)
9155 return;
9156
9157 dev_priv->mm.busy = false;
9158
9159 if (!i915.powersave)
9160 goto out;
9161
9162 for_each_crtc(dev, crtc) {
9163 if (!crtc->primary->fb)
9164 continue;
9165
9166 intel_decrease_pllclock(crtc);
9167 }
9168
9169 if (INTEL_INFO(dev)->gen >= 6)
9170 gen6_rps_idle(dev->dev_private);
9171
9172 out:
9173 intel_runtime_pm_put(dev_priv);
9174 }
9175
9176
9177 /**
9178 * intel_mark_fb_busy - mark given planes as busy
9179 * @dev: DRM device
9180 * @frontbuffer_bits: bits for the affected planes
9181 * @ring: optional ring for asynchronous commands
9182 *
9183 * This function gets called every time the screen contents change. It can be
9184 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9185 */
9186 static void intel_mark_fb_busy(struct drm_device *dev,
9187 unsigned frontbuffer_bits,
9188 struct intel_engine_cs *ring)
9189 {
9190 struct drm_i915_private *dev_priv = dev->dev_private;
9191 enum pipe pipe;
9192
9193 if (!i915.powersave)
9194 return;
9195
9196 for_each_pipe(dev_priv, pipe) {
9197 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9198 continue;
9199
9200 intel_increase_pllclock(dev, pipe);
9201 if (ring && intel_fbc_enabled(dev))
9202 ring->fbc_dirty = true;
9203 }
9204 }
9205
9206 /**
9207 * intel_fb_obj_invalidate - invalidate frontbuffer object
9208 * @obj: GEM object to invalidate
9209 * @ring: set for asynchronous rendering
9210 *
9211 * This function gets called every time rendering on the given object starts and
9212 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9213 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9214 * until the rendering completes or a flip on this frontbuffer plane is
9215 * scheduled.
9216 */
9217 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9218 struct intel_engine_cs *ring)
9219 {
9220 struct drm_device *dev = obj->base.dev;
9221 struct drm_i915_private *dev_priv = dev->dev_private;
9222
9223 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9224
9225 if (!obj->frontbuffer_bits)
9226 return;
9227
9228 if (ring) {
9229 mutex_lock(&dev_priv->fb_tracking.lock);
9230 dev_priv->fb_tracking.busy_bits
9231 |= obj->frontbuffer_bits;
9232 dev_priv->fb_tracking.flip_bits
9233 &= ~obj->frontbuffer_bits;
9234 mutex_unlock(&dev_priv->fb_tracking.lock);
9235 }
9236
9237 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9238
9239 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9240 }
9241
9242 /**
9243 * intel_frontbuffer_flush - flush frontbuffer
9244 * @dev: DRM device
9245 * @frontbuffer_bits: frontbuffer plane tracking bits
9246 *
9247 * This function gets called every time rendering on the given planes has
9248 * completed and frontbuffer caching can be started again. Flushes will get
9249 * delayed if they're blocked by some oustanding asynchronous rendering.
9250 *
9251 * Can be called without any locks held.
9252 */
9253 void intel_frontbuffer_flush(struct drm_device *dev,
9254 unsigned frontbuffer_bits)
9255 {
9256 struct drm_i915_private *dev_priv = dev->dev_private;
9257
9258 /* Delay flushing when rings are still busy.*/
9259 mutex_lock(&dev_priv->fb_tracking.lock);
9260 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9261 mutex_unlock(&dev_priv->fb_tracking.lock);
9262
9263 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9264
9265 intel_edp_psr_flush(dev, frontbuffer_bits);
9266
9267 /*
9268 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9269 * needs to be reworked into a proper frontbuffer tracking scheme like
9270 * psr employs.
9271 */
9272 if (IS_BROADWELL(dev))
9273 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9274 }
9275
9276 /**
9277 * intel_fb_obj_flush - flush frontbuffer object
9278 * @obj: GEM object to flush
9279 * @retire: set when retiring asynchronous rendering
9280 *
9281 * This function gets called every time rendering on the given object has
9282 * completed and frontbuffer caching can be started again. If @retire is true
9283 * then any delayed flushes will be unblocked.
9284 */
9285 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9286 bool retire)
9287 {
9288 struct drm_device *dev = obj->base.dev;
9289 struct drm_i915_private *dev_priv = dev->dev_private;
9290 unsigned frontbuffer_bits;
9291
9292 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9293
9294 if (!obj->frontbuffer_bits)
9295 return;
9296
9297 frontbuffer_bits = obj->frontbuffer_bits;
9298
9299 if (retire) {
9300 mutex_lock(&dev_priv->fb_tracking.lock);
9301 /* Filter out new bits since rendering started. */
9302 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9303
9304 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9305 mutex_unlock(&dev_priv->fb_tracking.lock);
9306 }
9307
9308 intel_frontbuffer_flush(dev, frontbuffer_bits);
9309 }
9310
9311 /**
9312 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9313 * @dev: DRM device
9314 * @frontbuffer_bits: frontbuffer plane tracking bits
9315 *
9316 * This function gets called after scheduling a flip on @obj. The actual
9317 * frontbuffer flushing will be delayed until completion is signalled with
9318 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9319 * flush will be cancelled.
9320 *
9321 * Can be called without any locks held.
9322 */
9323 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9324 unsigned frontbuffer_bits)
9325 {
9326 struct drm_i915_private *dev_priv = dev->dev_private;
9327
9328 mutex_lock(&dev_priv->fb_tracking.lock);
9329 dev_priv->fb_tracking.flip_bits
9330 |= frontbuffer_bits;
9331 mutex_unlock(&dev_priv->fb_tracking.lock);
9332 }
9333
9334 /**
9335 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9336 * @dev: DRM device
9337 * @frontbuffer_bits: frontbuffer plane tracking bits
9338 *
9339 * This function gets called after the flip has been latched and will complete
9340 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9341 *
9342 * Can be called without any locks held.
9343 */
9344 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9345 unsigned frontbuffer_bits)
9346 {
9347 struct drm_i915_private *dev_priv = dev->dev_private;
9348
9349 mutex_lock(&dev_priv->fb_tracking.lock);
9350 /* Mask any cancelled flips. */
9351 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9352 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9353 mutex_unlock(&dev_priv->fb_tracking.lock);
9354
9355 intel_frontbuffer_flush(dev, frontbuffer_bits);
9356 }
9357
9358 static void intel_crtc_destroy(struct drm_crtc *crtc)
9359 {
9360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9361 struct drm_device *dev = crtc->dev;
9362 struct intel_unpin_work *work;
9363 unsigned long flags;
9364
9365 spin_lock_irqsave(&dev->event_lock, flags);
9366 work = intel_crtc->unpin_work;
9367 intel_crtc->unpin_work = NULL;
9368 spin_unlock_irqrestore(&dev->event_lock, flags);
9369
9370 if (work) {
9371 cancel_work_sync(&work->work);
9372 kfree(work);
9373 }
9374
9375 drm_crtc_cleanup(crtc);
9376
9377 kfree(intel_crtc);
9378 }
9379
9380 static void intel_unpin_work_fn(struct work_struct *__work)
9381 {
9382 struct intel_unpin_work *work =
9383 container_of(__work, struct intel_unpin_work, work);
9384 struct drm_device *dev = work->crtc->dev;
9385 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9386
9387 mutex_lock(&dev->struct_mutex);
9388 intel_unpin_fb_obj(work->old_fb_obj);
9389 drm_gem_object_unreference(&work->pending_flip_obj->base);
9390 drm_gem_object_unreference(&work->old_fb_obj->base);
9391
9392 intel_update_fbc(dev);
9393 mutex_unlock(&dev->struct_mutex);
9394
9395 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9396
9397 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9398 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9399
9400 kfree(work);
9401 }
9402
9403 static void do_intel_finish_page_flip(struct drm_device *dev,
9404 struct drm_crtc *crtc)
9405 {
9406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9407 struct intel_unpin_work *work;
9408 unsigned long flags;
9409
9410 /* Ignore early vblank irqs */
9411 if (intel_crtc == NULL)
9412 return;
9413
9414 spin_lock_irqsave(&dev->event_lock, flags);
9415 work = intel_crtc->unpin_work;
9416
9417 /* Ensure we don't miss a work->pending update ... */
9418 smp_rmb();
9419
9420 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9421 spin_unlock_irqrestore(&dev->event_lock, flags);
9422 return;
9423 }
9424
9425 page_flip_completed(intel_crtc);
9426
9427 spin_unlock_irqrestore(&dev->event_lock, flags);
9428 }
9429
9430 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9431 {
9432 struct drm_i915_private *dev_priv = dev->dev_private;
9433 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9434
9435 do_intel_finish_page_flip(dev, crtc);
9436 }
9437
9438 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9439 {
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9442
9443 do_intel_finish_page_flip(dev, crtc);
9444 }
9445
9446 /* Is 'a' after or equal to 'b'? */
9447 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9448 {
9449 return !((a - b) & 0x80000000);
9450 }
9451
9452 static bool page_flip_finished(struct intel_crtc *crtc)
9453 {
9454 struct drm_device *dev = crtc->base.dev;
9455 struct drm_i915_private *dev_priv = dev->dev_private;
9456
9457 /*
9458 * The relevant registers doen't exist on pre-ctg.
9459 * As the flip done interrupt doesn't trigger for mmio
9460 * flips on gmch platforms, a flip count check isn't
9461 * really needed there. But since ctg has the registers,
9462 * include it in the check anyway.
9463 */
9464 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9465 return true;
9466
9467 /*
9468 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9469 * used the same base address. In that case the mmio flip might
9470 * have completed, but the CS hasn't even executed the flip yet.
9471 *
9472 * A flip count check isn't enough as the CS might have updated
9473 * the base address just after start of vblank, but before we
9474 * managed to process the interrupt. This means we'd complete the
9475 * CS flip too soon.
9476 *
9477 * Combining both checks should get us a good enough result. It may
9478 * still happen that the CS flip has been executed, but has not
9479 * yet actually completed. But in case the base address is the same
9480 * anyway, we don't really care.
9481 */
9482 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9483 crtc->unpin_work->gtt_offset &&
9484 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9485 crtc->unpin_work->flip_count);
9486 }
9487
9488 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9489 {
9490 struct drm_i915_private *dev_priv = dev->dev_private;
9491 struct intel_crtc *intel_crtc =
9492 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9493 unsigned long flags;
9494
9495 /* NB: An MMIO update of the plane base pointer will also
9496 * generate a page-flip completion irq, i.e. every modeset
9497 * is also accompanied by a spurious intel_prepare_page_flip().
9498 */
9499 spin_lock_irqsave(&dev->event_lock, flags);
9500 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9501 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9502 spin_unlock_irqrestore(&dev->event_lock, flags);
9503 }
9504
9505 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9506 {
9507 /* Ensure that the work item is consistent when activating it ... */
9508 smp_wmb();
9509 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9510 /* and that it is marked active as soon as the irq could fire. */
9511 smp_wmb();
9512 }
9513
9514 static int intel_gen2_queue_flip(struct drm_device *dev,
9515 struct drm_crtc *crtc,
9516 struct drm_framebuffer *fb,
9517 struct drm_i915_gem_object *obj,
9518 struct intel_engine_cs *ring,
9519 uint32_t flags)
9520 {
9521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9522 u32 flip_mask;
9523 int ret;
9524
9525 ret = intel_ring_begin(ring, 6);
9526 if (ret)
9527 return ret;
9528
9529 /* Can't queue multiple flips, so wait for the previous
9530 * one to finish before executing the next.
9531 */
9532 if (intel_crtc->plane)
9533 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9534 else
9535 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9536 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9537 intel_ring_emit(ring, MI_NOOP);
9538 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9539 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9540 intel_ring_emit(ring, fb->pitches[0]);
9541 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9542 intel_ring_emit(ring, 0); /* aux display base address, unused */
9543
9544 intel_mark_page_flip_active(intel_crtc);
9545 __intel_ring_advance(ring);
9546 return 0;
9547 }
9548
9549 static int intel_gen3_queue_flip(struct drm_device *dev,
9550 struct drm_crtc *crtc,
9551 struct drm_framebuffer *fb,
9552 struct drm_i915_gem_object *obj,
9553 struct intel_engine_cs *ring,
9554 uint32_t flags)
9555 {
9556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9557 u32 flip_mask;
9558 int ret;
9559
9560 ret = intel_ring_begin(ring, 6);
9561 if (ret)
9562 return ret;
9563
9564 if (intel_crtc->plane)
9565 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9566 else
9567 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9568 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9569 intel_ring_emit(ring, MI_NOOP);
9570 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9571 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9572 intel_ring_emit(ring, fb->pitches[0]);
9573 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9574 intel_ring_emit(ring, MI_NOOP);
9575
9576 intel_mark_page_flip_active(intel_crtc);
9577 __intel_ring_advance(ring);
9578 return 0;
9579 }
9580
9581 static int intel_gen4_queue_flip(struct drm_device *dev,
9582 struct drm_crtc *crtc,
9583 struct drm_framebuffer *fb,
9584 struct drm_i915_gem_object *obj,
9585 struct intel_engine_cs *ring,
9586 uint32_t flags)
9587 {
9588 struct drm_i915_private *dev_priv = dev->dev_private;
9589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9590 uint32_t pf, pipesrc;
9591 int ret;
9592
9593 ret = intel_ring_begin(ring, 4);
9594 if (ret)
9595 return ret;
9596
9597 /* i965+ uses the linear or tiled offsets from the
9598 * Display Registers (which do not change across a page-flip)
9599 * so we need only reprogram the base address.
9600 */
9601 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9602 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9603 intel_ring_emit(ring, fb->pitches[0]);
9604 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9605 obj->tiling_mode);
9606
9607 /* XXX Enabling the panel-fitter across page-flip is so far
9608 * untested on non-native modes, so ignore it for now.
9609 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9610 */
9611 pf = 0;
9612 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9613 intel_ring_emit(ring, pf | pipesrc);
9614
9615 intel_mark_page_flip_active(intel_crtc);
9616 __intel_ring_advance(ring);
9617 return 0;
9618 }
9619
9620 static int intel_gen6_queue_flip(struct drm_device *dev,
9621 struct drm_crtc *crtc,
9622 struct drm_framebuffer *fb,
9623 struct drm_i915_gem_object *obj,
9624 struct intel_engine_cs *ring,
9625 uint32_t flags)
9626 {
9627 struct drm_i915_private *dev_priv = dev->dev_private;
9628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9629 uint32_t pf, pipesrc;
9630 int ret;
9631
9632 ret = intel_ring_begin(ring, 4);
9633 if (ret)
9634 return ret;
9635
9636 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9637 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9638 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9639 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9640
9641 /* Contrary to the suggestions in the documentation,
9642 * "Enable Panel Fitter" does not seem to be required when page
9643 * flipping with a non-native mode, and worse causes a normal
9644 * modeset to fail.
9645 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9646 */
9647 pf = 0;
9648 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9649 intel_ring_emit(ring, pf | pipesrc);
9650
9651 intel_mark_page_flip_active(intel_crtc);
9652 __intel_ring_advance(ring);
9653 return 0;
9654 }
9655
9656 static int intel_gen7_queue_flip(struct drm_device *dev,
9657 struct drm_crtc *crtc,
9658 struct drm_framebuffer *fb,
9659 struct drm_i915_gem_object *obj,
9660 struct intel_engine_cs *ring,
9661 uint32_t flags)
9662 {
9663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9664 uint32_t plane_bit = 0;
9665 int len, ret;
9666
9667 switch (intel_crtc->plane) {
9668 case PLANE_A:
9669 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9670 break;
9671 case PLANE_B:
9672 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9673 break;
9674 case PLANE_C:
9675 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9676 break;
9677 default:
9678 WARN_ONCE(1, "unknown plane in flip command\n");
9679 return -ENODEV;
9680 }
9681
9682 len = 4;
9683 if (ring->id == RCS) {
9684 len += 6;
9685 /*
9686 * On Gen 8, SRM is now taking an extra dword to accommodate
9687 * 48bits addresses, and we need a NOOP for the batch size to
9688 * stay even.
9689 */
9690 if (IS_GEN8(dev))
9691 len += 2;
9692 }
9693
9694 /*
9695 * BSpec MI_DISPLAY_FLIP for IVB:
9696 * "The full packet must be contained within the same cache line."
9697 *
9698 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9699 * cacheline, if we ever start emitting more commands before
9700 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9701 * then do the cacheline alignment, and finally emit the
9702 * MI_DISPLAY_FLIP.
9703 */
9704 ret = intel_ring_cacheline_align(ring);
9705 if (ret)
9706 return ret;
9707
9708 ret = intel_ring_begin(ring, len);
9709 if (ret)
9710 return ret;
9711
9712 /* Unmask the flip-done completion message. Note that the bspec says that
9713 * we should do this for both the BCS and RCS, and that we must not unmask
9714 * more than one flip event at any time (or ensure that one flip message
9715 * can be sent by waiting for flip-done prior to queueing new flips).
9716 * Experimentation says that BCS works despite DERRMR masking all
9717 * flip-done completion events and that unmasking all planes at once
9718 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9719 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9720 */
9721 if (ring->id == RCS) {
9722 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9723 intel_ring_emit(ring, DERRMR);
9724 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9725 DERRMR_PIPEB_PRI_FLIP_DONE |
9726 DERRMR_PIPEC_PRI_FLIP_DONE));
9727 if (IS_GEN8(dev))
9728 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9729 MI_SRM_LRM_GLOBAL_GTT);
9730 else
9731 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9732 MI_SRM_LRM_GLOBAL_GTT);
9733 intel_ring_emit(ring, DERRMR);
9734 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9735 if (IS_GEN8(dev)) {
9736 intel_ring_emit(ring, 0);
9737 intel_ring_emit(ring, MI_NOOP);
9738 }
9739 }
9740
9741 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9742 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9743 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9744 intel_ring_emit(ring, (MI_NOOP));
9745
9746 intel_mark_page_flip_active(intel_crtc);
9747 __intel_ring_advance(ring);
9748 return 0;
9749 }
9750
9751 static bool use_mmio_flip(struct intel_engine_cs *ring,
9752 struct drm_i915_gem_object *obj)
9753 {
9754 /*
9755 * This is not being used for older platforms, because
9756 * non-availability of flip done interrupt forces us to use
9757 * CS flips. Older platforms derive flip done using some clever
9758 * tricks involving the flip_pending status bits and vblank irqs.
9759 * So using MMIO flips there would disrupt this mechanism.
9760 */
9761
9762 if (ring == NULL)
9763 return true;
9764
9765 if (INTEL_INFO(ring->dev)->gen < 5)
9766 return false;
9767
9768 if (i915.use_mmio_flip < 0)
9769 return false;
9770 else if (i915.use_mmio_flip > 0)
9771 return true;
9772 else if (i915.enable_execlists)
9773 return true;
9774 else
9775 return ring != obj->ring;
9776 }
9777
9778 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9779 {
9780 struct drm_device *dev = intel_crtc->base.dev;
9781 struct drm_i915_private *dev_priv = dev->dev_private;
9782 struct intel_framebuffer *intel_fb =
9783 to_intel_framebuffer(intel_crtc->base.primary->fb);
9784 struct drm_i915_gem_object *obj = intel_fb->obj;
9785 u32 dspcntr;
9786 u32 reg;
9787
9788 intel_mark_page_flip_active(intel_crtc);
9789
9790 reg = DSPCNTR(intel_crtc->plane);
9791 dspcntr = I915_READ(reg);
9792
9793 if (INTEL_INFO(dev)->gen >= 4) {
9794 if (obj->tiling_mode != I915_TILING_NONE)
9795 dspcntr |= DISPPLANE_TILED;
9796 else
9797 dspcntr &= ~DISPPLANE_TILED;
9798 }
9799 I915_WRITE(reg, dspcntr);
9800
9801 I915_WRITE(DSPSURF(intel_crtc->plane),
9802 intel_crtc->unpin_work->gtt_offset);
9803 POSTING_READ(DSPSURF(intel_crtc->plane));
9804 }
9805
9806 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9807 {
9808 struct intel_engine_cs *ring;
9809 int ret;
9810
9811 lockdep_assert_held(&obj->base.dev->struct_mutex);
9812
9813 if (!obj->last_write_seqno)
9814 return 0;
9815
9816 ring = obj->ring;
9817
9818 if (i915_seqno_passed(ring->get_seqno(ring, true),
9819 obj->last_write_seqno))
9820 return 0;
9821
9822 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9823 if (ret)
9824 return ret;
9825
9826 if (WARN_ON(!ring->irq_get(ring)))
9827 return 0;
9828
9829 return 1;
9830 }
9831
9832 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9833 {
9834 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9835 struct intel_crtc *intel_crtc;
9836 unsigned long irq_flags;
9837 u32 seqno;
9838
9839 seqno = ring->get_seqno(ring, false);
9840
9841 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9842 for_each_intel_crtc(ring->dev, intel_crtc) {
9843 struct intel_mmio_flip *mmio_flip;
9844
9845 mmio_flip = &intel_crtc->mmio_flip;
9846 if (mmio_flip->seqno == 0)
9847 continue;
9848
9849 if (ring->id != mmio_flip->ring_id)
9850 continue;
9851
9852 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9853 intel_do_mmio_flip(intel_crtc);
9854 mmio_flip->seqno = 0;
9855 ring->irq_put(ring);
9856 }
9857 }
9858 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9859 }
9860
9861 static int intel_queue_mmio_flip(struct drm_device *dev,
9862 struct drm_crtc *crtc,
9863 struct drm_framebuffer *fb,
9864 struct drm_i915_gem_object *obj,
9865 struct intel_engine_cs *ring,
9866 uint32_t flags)
9867 {
9868 struct drm_i915_private *dev_priv = dev->dev_private;
9869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9870 unsigned long irq_flags;
9871 int ret;
9872
9873 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9874 return -EBUSY;
9875
9876 ret = intel_postpone_flip(obj);
9877 if (ret < 0)
9878 return ret;
9879 if (ret == 0) {
9880 intel_do_mmio_flip(intel_crtc);
9881 return 0;
9882 }
9883
9884 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9885 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9886 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9887 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9888
9889 /*
9890 * Double check to catch cases where irq fired before
9891 * mmio flip data was ready
9892 */
9893 intel_notify_mmio_flip(obj->ring);
9894 return 0;
9895 }
9896
9897 static int intel_default_queue_flip(struct drm_device *dev,
9898 struct drm_crtc *crtc,
9899 struct drm_framebuffer *fb,
9900 struct drm_i915_gem_object *obj,
9901 struct intel_engine_cs *ring,
9902 uint32_t flags)
9903 {
9904 return -ENODEV;
9905 }
9906
9907 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9908 struct drm_crtc *crtc)
9909 {
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9912 struct intel_unpin_work *work = intel_crtc->unpin_work;
9913 u32 addr;
9914
9915 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9916 return true;
9917
9918 if (!work->enable_stall_check)
9919 return false;
9920
9921 if (work->flip_ready_vblank == 0) {
9922 if (work->flip_queued_ring &&
9923 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9924 work->flip_queued_seqno))
9925 return false;
9926
9927 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9928 }
9929
9930 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9931 return false;
9932
9933 /* Potential stall - if we see that the flip has happened,
9934 * assume a missed interrupt. */
9935 if (INTEL_INFO(dev)->gen >= 4)
9936 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9937 else
9938 addr = I915_READ(DSPADDR(intel_crtc->plane));
9939
9940 /* There is a potential issue here with a false positive after a flip
9941 * to the same address. We could address this by checking for a
9942 * non-incrementing frame counter.
9943 */
9944 return addr == work->gtt_offset;
9945 }
9946
9947 void intel_check_page_flip(struct drm_device *dev, int pipe)
9948 {
9949 struct drm_i915_private *dev_priv = dev->dev_private;
9950 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9952 unsigned long flags;
9953
9954 if (crtc == NULL)
9955 return;
9956
9957 spin_lock_irqsave(&dev->event_lock, flags);
9958 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9959 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9960 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9961 page_flip_completed(intel_crtc);
9962 }
9963 spin_unlock_irqrestore(&dev->event_lock, flags);
9964 }
9965
9966 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9967 struct drm_framebuffer *fb,
9968 struct drm_pending_vblank_event *event,
9969 uint32_t page_flip_flags)
9970 {
9971 struct drm_device *dev = crtc->dev;
9972 struct drm_i915_private *dev_priv = dev->dev_private;
9973 struct drm_framebuffer *old_fb = crtc->primary->fb;
9974 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9976 enum pipe pipe = intel_crtc->pipe;
9977 struct intel_unpin_work *work;
9978 struct intel_engine_cs *ring;
9979 unsigned long flags;
9980 int ret;
9981
9982 //trigger software GT busyness calculation
9983 gen8_flip_interrupt(dev);
9984
9985 /*
9986 * drm_mode_page_flip_ioctl() should already catch this, but double
9987 * check to be safe. In the future we may enable pageflipping from
9988 * a disabled primary plane.
9989 */
9990 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9991 return -EBUSY;
9992
9993 /* Can't change pixel format via MI display flips. */
9994 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9995 return -EINVAL;
9996
9997 /*
9998 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9999 * Note that pitch changes could also affect these register.
10000 */
10001 if (INTEL_INFO(dev)->gen > 3 &&
10002 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10003 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10004 return -EINVAL;
10005
10006 if (i915_terminally_wedged(&dev_priv->gpu_error))
10007 goto out_hang;
10008
10009 work = kzalloc(sizeof(*work), GFP_KERNEL);
10010 if (work == NULL)
10011 return -ENOMEM;
10012
10013 work->event = event;
10014 work->crtc = crtc;
10015 work->old_fb_obj = intel_fb_obj(old_fb);
10016 INIT_WORK(&work->work, intel_unpin_work_fn);
10017
10018 ret = drm_crtc_vblank_get(crtc);
10019 if (ret)
10020 goto free_work;
10021
10022 /* We borrow the event spin lock for protecting unpin_work */
10023 spin_lock_irqsave(&dev->event_lock, flags);
10024 if (intel_crtc->unpin_work) {
10025 /* Before declaring the flip queue wedged, check if
10026 * the hardware completed the operation behind our backs.
10027 */
10028 if (__intel_pageflip_stall_check(dev, crtc)) {
10029 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10030 page_flip_completed(intel_crtc);
10031 } else {
10032 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10033 spin_unlock_irqrestore(&dev->event_lock, flags);
10034
10035 drm_crtc_vblank_put(crtc);
10036 kfree(work);
10037 return -EBUSY;
10038 }
10039 }
10040 intel_crtc->unpin_work = work;
10041 spin_unlock_irqrestore(&dev->event_lock, flags);
10042
10043 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10044 flush_workqueue(dev_priv->wq);
10045
10046 ret = i915_mutex_lock_interruptible(dev);
10047 if (ret)
10048 goto cleanup;
10049
10050 /* Reference the objects for the scheduled work. */
10051 drm_gem_object_reference(&work->old_fb_obj->base);
10052 drm_gem_object_reference(&obj->base);
10053
10054 crtc->primary->fb = fb;
10055
10056 work->pending_flip_obj = obj;
10057
10058 atomic_inc(&intel_crtc->unpin_work_count);
10059 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10060
10061 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10062 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10063
10064 if (IS_VALLEYVIEW(dev)) {
10065 ring = &dev_priv->ring[BCS];
10066 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10067 /* vlv: DISPLAY_FLIP fails to change tiling */
10068 ring = NULL;
10069 } else if (IS_IVYBRIDGE(dev)) {
10070 ring = &dev_priv->ring[BCS];
10071 } else if (INTEL_INFO(dev)->gen >= 7) {
10072 ring = obj->ring;
10073 if (ring == NULL || ring->id != RCS)
10074 ring = &dev_priv->ring[BCS];
10075 } else {
10076 ring = &dev_priv->ring[RCS];
10077 }
10078
10079 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10080 if (ret)
10081 goto cleanup_pending;
10082
10083 work->gtt_offset =
10084 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10085
10086 if (use_mmio_flip(ring, obj)) {
10087 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10088 page_flip_flags);
10089 if (ret)
10090 goto cleanup_unpin;
10091
10092 work->flip_queued_seqno = obj->last_write_seqno;
10093 work->flip_queued_ring = obj->ring;
10094 } else {
10095 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10096 page_flip_flags);
10097 if (ret)
10098 goto cleanup_unpin;
10099
10100 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10101 work->flip_queued_ring = ring;
10102 }
10103
10104 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10105 work->enable_stall_check = true;
10106
10107 i915_gem_track_fb(work->old_fb_obj, obj,
10108 INTEL_FRONTBUFFER_PRIMARY(pipe));
10109
10110 intel_disable_fbc(dev);
10111 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10112 mutex_unlock(&dev->struct_mutex);
10113
10114 trace_i915_flip_request(intel_crtc->plane, obj);
10115
10116 return 0;
10117
10118 cleanup_unpin:
10119 intel_unpin_fb_obj(obj);
10120 cleanup_pending:
10121 atomic_dec(&intel_crtc->unpin_work_count);
10122 crtc->primary->fb = old_fb;
10123 drm_gem_object_unreference(&work->old_fb_obj->base);
10124 drm_gem_object_unreference(&obj->base);
10125 mutex_unlock(&dev->struct_mutex);
10126
10127 cleanup:
10128 spin_lock_irqsave(&dev->event_lock, flags);
10129 intel_crtc->unpin_work = NULL;
10130 spin_unlock_irqrestore(&dev->event_lock, flags);
10131
10132 drm_crtc_vblank_put(crtc);
10133 free_work:
10134 kfree(work);
10135
10136 if (ret == -EIO) {
10137 out_hang:
10138 intel_crtc_wait_for_pending_flips(crtc);
10139 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10140 if (ret == 0 && event)
10141 drm_send_vblank_event(dev, pipe, event);
10142 }
10143 return ret;
10144 }
10145
10146 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10147 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10148 .load_lut = intel_crtc_load_lut,
10149 };
10150
10151 /**
10152 * intel_modeset_update_staged_output_state
10153 *
10154 * Updates the staged output configuration state, e.g. after we've read out the
10155 * current hw state.
10156 */
10157 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10158 {
10159 struct intel_crtc *crtc;
10160 struct intel_encoder *encoder;
10161 struct intel_connector *connector;
10162
10163 list_for_each_entry(connector, &dev->mode_config.connector_list,
10164 base.head) {
10165 connector->new_encoder =
10166 to_intel_encoder(connector->base.encoder);
10167 }
10168
10169 for_each_intel_encoder(dev, encoder) {
10170 encoder->new_crtc =
10171 to_intel_crtc(encoder->base.crtc);
10172 }
10173
10174 for_each_intel_crtc(dev, crtc) {
10175 crtc->new_enabled = crtc->base.enabled;
10176
10177 if (crtc->new_enabled)
10178 crtc->new_config = &crtc->config;
10179 else
10180 crtc->new_config = NULL;
10181 }
10182 }
10183
10184 /**
10185 * intel_modeset_commit_output_state
10186 *
10187 * This function copies the stage display pipe configuration to the real one.
10188 */
10189 static void intel_modeset_commit_output_state(struct drm_device *dev)
10190 {
10191 struct intel_crtc *crtc;
10192 struct intel_encoder *encoder;
10193 struct intel_connector *connector;
10194
10195 list_for_each_entry(connector, &dev->mode_config.connector_list,
10196 base.head) {
10197 connector->base.encoder = &connector->new_encoder->base;
10198 }
10199
10200 for_each_intel_encoder(dev, encoder) {
10201 encoder->base.crtc = &encoder->new_crtc->base;
10202 }
10203
10204 for_each_intel_crtc(dev, crtc) {
10205 crtc->base.enabled = crtc->new_enabled;
10206 }
10207 }
10208
10209 static void
10210 connected_sink_compute_bpp(struct intel_connector *connector,
10211 struct intel_crtc_config *pipe_config)
10212 {
10213 int bpp = pipe_config->pipe_bpp;
10214
10215 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10216 connector->base.base.id,
10217 connector->base.name);
10218
10219 /* Don't use an invalid EDID bpc value */
10220 if (connector->base.display_info.bpc &&
10221 connector->base.display_info.bpc * 3 < bpp) {
10222 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10223 bpp, connector->base.display_info.bpc*3);
10224 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10225 }
10226
10227 /* Clamp bpp to 8 on screens without EDID 1.4 */
10228 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10229 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10230 bpp);
10231 pipe_config->pipe_bpp = 24;
10232 }
10233 }
10234
10235 static int
10236 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10237 struct drm_framebuffer *fb,
10238 struct intel_crtc_config *pipe_config)
10239 {
10240 struct drm_device *dev = crtc->base.dev;
10241 struct intel_connector *connector;
10242 int bpp;
10243
10244 switch (fb->pixel_format) {
10245 case DRM_FORMAT_C8:
10246 bpp = 8*3; /* since we go through a colormap */
10247 break;
10248 case DRM_FORMAT_XRGB1555:
10249 case DRM_FORMAT_ARGB1555:
10250 /* checked in intel_framebuffer_init already */
10251 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10252 return -EINVAL;
10253 case DRM_FORMAT_RGB565:
10254 bpp = 6*3; /* min is 18bpp */
10255 break;
10256 case DRM_FORMAT_XBGR8888:
10257 case DRM_FORMAT_ABGR8888:
10258 /* checked in intel_framebuffer_init already */
10259 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10260 return -EINVAL;
10261 case DRM_FORMAT_XRGB8888:
10262 case DRM_FORMAT_ARGB8888:
10263 bpp = 8*3;
10264 break;
10265 case DRM_FORMAT_XRGB2101010:
10266 case DRM_FORMAT_ARGB2101010:
10267 case DRM_FORMAT_XBGR2101010:
10268 case DRM_FORMAT_ABGR2101010:
10269 /* checked in intel_framebuffer_init already */
10270 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10271 return -EINVAL;
10272 bpp = 10*3;
10273 break;
10274 /* TODO: gen4+ supports 16 bpc floating point, too. */
10275 default:
10276 DRM_DEBUG_KMS("unsupported depth\n");
10277 return -EINVAL;
10278 }
10279
10280 pipe_config->pipe_bpp = bpp;
10281
10282 /* Clamp display bpp to EDID value */
10283 list_for_each_entry(connector, &dev->mode_config.connector_list,
10284 base.head) {
10285 if (!connector->new_encoder ||
10286 connector->new_encoder->new_crtc != crtc)
10287 continue;
10288
10289 connected_sink_compute_bpp(connector, pipe_config);
10290 }
10291
10292 return bpp;
10293 }
10294
10295 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10296 {
10297 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10298 "type: 0x%x flags: 0x%x\n",
10299 mode->crtc_clock,
10300 mode->crtc_hdisplay, mode->crtc_hsync_start,
10301 mode->crtc_hsync_end, mode->crtc_htotal,
10302 mode->crtc_vdisplay, mode->crtc_vsync_start,
10303 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10304 }
10305
10306 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10307 struct intel_crtc_config *pipe_config,
10308 const char *context)
10309 {
10310 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10311 context, pipe_name(crtc->pipe));
10312
10313 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10314 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10315 pipe_config->pipe_bpp, pipe_config->dither);
10316 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10317 pipe_config->has_pch_encoder,
10318 pipe_config->fdi_lanes,
10319 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10320 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10321 pipe_config->fdi_m_n.tu);
10322 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10323 pipe_config->has_dp_encoder,
10324 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10325 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10326 pipe_config->dp_m_n.tu);
10327
10328 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10329 pipe_config->has_dp_encoder,
10330 pipe_config->dp_m2_n2.gmch_m,
10331 pipe_config->dp_m2_n2.gmch_n,
10332 pipe_config->dp_m2_n2.link_m,
10333 pipe_config->dp_m2_n2.link_n,
10334 pipe_config->dp_m2_n2.tu);
10335
10336 DRM_DEBUG_KMS("requested mode:\n");
10337 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10338 DRM_DEBUG_KMS("adjusted mode:\n");
10339 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10340 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10341 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10342 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10343 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10344 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10345 pipe_config->gmch_pfit.control,
10346 pipe_config->gmch_pfit.pgm_ratios,
10347 pipe_config->gmch_pfit.lvds_border_bits);
10348 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10349 pipe_config->pch_pfit.pos,
10350 pipe_config->pch_pfit.size,
10351 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10352 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10353 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10354 }
10355
10356 static bool encoders_cloneable(const struct intel_encoder *a,
10357 const struct intel_encoder *b)
10358 {
10359 /* masks could be asymmetric, so check both ways */
10360 return a == b || (a->cloneable & (1 << b->type) &&
10361 b->cloneable & (1 << a->type));
10362 }
10363
10364 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10365 struct intel_encoder *encoder)
10366 {
10367 struct drm_device *dev = crtc->base.dev;
10368 struct intel_encoder *source_encoder;
10369
10370 for_each_intel_encoder(dev, source_encoder) {
10371 if (source_encoder->new_crtc != crtc)
10372 continue;
10373
10374 if (!encoders_cloneable(encoder, source_encoder))
10375 return false;
10376 }
10377
10378 return true;
10379 }
10380
10381 static bool check_encoder_cloning(struct intel_crtc *crtc)
10382 {
10383 struct drm_device *dev = crtc->base.dev;
10384 struct intel_encoder *encoder;
10385
10386 for_each_intel_encoder(dev, encoder) {
10387 if (encoder->new_crtc != crtc)
10388 continue;
10389
10390 if (!check_single_encoder_cloning(crtc, encoder))
10391 return false;
10392 }
10393
10394 return true;
10395 }
10396
10397 static struct intel_crtc_config *
10398 intel_modeset_pipe_config(struct drm_crtc *crtc,
10399 struct drm_framebuffer *fb,
10400 struct drm_display_mode *mode)
10401 {
10402 struct drm_device *dev = crtc->dev;
10403 struct intel_encoder *encoder;
10404 struct intel_crtc_config *pipe_config;
10405 int plane_bpp, ret = -EINVAL;
10406 bool retry = true;
10407
10408 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10409 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10410 return ERR_PTR(-EINVAL);
10411 }
10412
10413 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10414 if (!pipe_config)
10415 return ERR_PTR(-ENOMEM);
10416
10417 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10418 drm_mode_copy(&pipe_config->requested_mode, mode);
10419
10420 pipe_config->cpu_transcoder =
10421 (enum transcoder) to_intel_crtc(crtc)->pipe;
10422 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10423
10424 /*
10425 * Sanitize sync polarity flags based on requested ones. If neither
10426 * positive or negative polarity is requested, treat this as meaning
10427 * negative polarity.
10428 */
10429 if (!(pipe_config->adjusted_mode.flags &
10430 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10431 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10432
10433 if (!(pipe_config->adjusted_mode.flags &
10434 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10435 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10436
10437 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10438 * plane pixel format and any sink constraints into account. Returns the
10439 * source plane bpp so that dithering can be selected on mismatches
10440 * after encoders and crtc also have had their say. */
10441 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10442 fb, pipe_config);
10443 if (plane_bpp < 0)
10444 goto fail;
10445
10446 /*
10447 * Determine the real pipe dimensions. Note that stereo modes can
10448 * increase the actual pipe size due to the frame doubling and
10449 * insertion of additional space for blanks between the frame. This
10450 * is stored in the crtc timings. We use the requested mode to do this
10451 * computation to clearly distinguish it from the adjusted mode, which
10452 * can be changed by the connectors in the below retry loop.
10453 */
10454 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10455 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10456 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10457
10458 encoder_retry:
10459 /* Ensure the port clock defaults are reset when retrying. */
10460 pipe_config->port_clock = 0;
10461 pipe_config->pixel_multiplier = 1;
10462
10463 /* Fill in default crtc timings, allow encoders to overwrite them. */
10464 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10465
10466 /* Pass our mode to the connectors and the CRTC to give them a chance to
10467 * adjust it according to limitations or connector properties, and also
10468 * a chance to reject the mode entirely.
10469 */
10470 for_each_intel_encoder(dev, encoder) {
10471
10472 if (&encoder->new_crtc->base != crtc)
10473 continue;
10474
10475 if (!(encoder->compute_config(encoder, pipe_config))) {
10476 DRM_DEBUG_KMS("Encoder config failure\n");
10477 goto fail;
10478 }
10479 }
10480
10481 /* Set default port clock if not overwritten by the encoder. Needs to be
10482 * done afterwards in case the encoder adjusts the mode. */
10483 if (!pipe_config->port_clock)
10484 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10485 * pipe_config->pixel_multiplier;
10486
10487 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10488 if (ret < 0) {
10489 DRM_DEBUG_KMS("CRTC fixup failed\n");
10490 goto fail;
10491 }
10492
10493 if (ret == RETRY) {
10494 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10495 ret = -EINVAL;
10496 goto fail;
10497 }
10498
10499 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10500 retry = false;
10501 goto encoder_retry;
10502 }
10503
10504 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10505 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10506 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10507
10508 return pipe_config;
10509 fail:
10510 kfree(pipe_config);
10511 return ERR_PTR(ret);
10512 }
10513
10514 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10515 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10516 static void
10517 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10518 unsigned *prepare_pipes, unsigned *disable_pipes)
10519 {
10520 struct intel_crtc *intel_crtc;
10521 struct drm_device *dev = crtc->dev;
10522 struct intel_encoder *encoder;
10523 struct intel_connector *connector;
10524 struct drm_crtc *tmp_crtc;
10525
10526 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10527
10528 /* Check which crtcs have changed outputs connected to them, these need
10529 * to be part of the prepare_pipes mask. We don't (yet) support global
10530 * modeset across multiple crtcs, so modeset_pipes will only have one
10531 * bit set at most. */
10532 list_for_each_entry(connector, &dev->mode_config.connector_list,
10533 base.head) {
10534 if (connector->base.encoder == &connector->new_encoder->base)
10535 continue;
10536
10537 if (connector->base.encoder) {
10538 tmp_crtc = connector->base.encoder->crtc;
10539
10540 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10541 }
10542
10543 if (connector->new_encoder)
10544 *prepare_pipes |=
10545 1 << connector->new_encoder->new_crtc->pipe;
10546 }
10547
10548 for_each_intel_encoder(dev, encoder) {
10549 if (encoder->base.crtc == &encoder->new_crtc->base)
10550 continue;
10551
10552 if (encoder->base.crtc) {
10553 tmp_crtc = encoder->base.crtc;
10554
10555 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10556 }
10557
10558 if (encoder->new_crtc)
10559 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10560 }
10561
10562 /* Check for pipes that will be enabled/disabled ... */
10563 for_each_intel_crtc(dev, intel_crtc) {
10564 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10565 continue;
10566
10567 if (!intel_crtc->new_enabled)
10568 *disable_pipes |= 1 << intel_crtc->pipe;
10569 else
10570 *prepare_pipes |= 1 << intel_crtc->pipe;
10571 }
10572
10573
10574 /* set_mode is also used to update properties on life display pipes. */
10575 intel_crtc = to_intel_crtc(crtc);
10576 if (intel_crtc->new_enabled)
10577 *prepare_pipes |= 1 << intel_crtc->pipe;
10578
10579 /*
10580 * For simplicity do a full modeset on any pipe where the output routing
10581 * changed. We could be more clever, but that would require us to be
10582 * more careful with calling the relevant encoder->mode_set functions.
10583 */
10584 if (*prepare_pipes)
10585 *modeset_pipes = *prepare_pipes;
10586
10587 /* ... and mask these out. */
10588 *modeset_pipes &= ~(*disable_pipes);
10589 *prepare_pipes &= ~(*disable_pipes);
10590
10591 /*
10592 * HACK: We don't (yet) fully support global modesets. intel_set_config
10593 * obies this rule, but the modeset restore mode of
10594 * intel_modeset_setup_hw_state does not.
10595 */
10596 *modeset_pipes &= 1 << intel_crtc->pipe;
10597 *prepare_pipes &= 1 << intel_crtc->pipe;
10598
10599 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10600 *modeset_pipes, *prepare_pipes, *disable_pipes);
10601 }
10602
10603 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10604 {
10605 struct drm_encoder *encoder;
10606 struct drm_device *dev = crtc->dev;
10607
10608 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10609 if (encoder->crtc == crtc)
10610 return true;
10611
10612 return false;
10613 }
10614
10615 static void
10616 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10617 {
10618 struct intel_encoder *intel_encoder;
10619 struct intel_crtc *intel_crtc;
10620 struct drm_connector *connector;
10621
10622 for_each_intel_encoder(dev, intel_encoder) {
10623 if (!intel_encoder->base.crtc)
10624 continue;
10625
10626 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10627
10628 if (prepare_pipes & (1 << intel_crtc->pipe))
10629 intel_encoder->connectors_active = false;
10630 }
10631
10632 intel_modeset_commit_output_state(dev);
10633
10634 /* Double check state. */
10635 for_each_intel_crtc(dev, intel_crtc) {
10636 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10637 WARN_ON(intel_crtc->new_config &&
10638 intel_crtc->new_config != &intel_crtc->config);
10639 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10640 }
10641
10642 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10643 if (!connector->encoder || !connector->encoder->crtc)
10644 continue;
10645
10646 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10647
10648 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10649 struct drm_property *dpms_property =
10650 dev->mode_config.dpms_property;
10651
10652 connector->dpms = DRM_MODE_DPMS_ON;
10653 drm_object_property_set_value(&connector->base,
10654 dpms_property,
10655 DRM_MODE_DPMS_ON);
10656
10657 intel_encoder = to_intel_encoder(connector->encoder);
10658 intel_encoder->connectors_active = true;
10659 }
10660 }
10661
10662 }
10663
10664 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10665 {
10666 int diff;
10667
10668 if (clock1 == clock2)
10669 return true;
10670
10671 if (!clock1 || !clock2)
10672 return false;
10673
10674 diff = abs(clock1 - clock2);
10675
10676 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10677 return true;
10678
10679 return false;
10680 }
10681
10682 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10683 list_for_each_entry((intel_crtc), \
10684 &(dev)->mode_config.crtc_list, \
10685 base.head) \
10686 if (mask & (1 <<(intel_crtc)->pipe))
10687
10688 static bool
10689 intel_pipe_config_compare(struct drm_device *dev,
10690 struct intel_crtc_config *current_config,
10691 struct intel_crtc_config *pipe_config)
10692 {
10693 #define PIPE_CONF_CHECK_X(name) \
10694 if (current_config->name != pipe_config->name) { \
10695 DRM_ERROR("mismatch in " #name " " \
10696 "(expected 0x%08x, found 0x%08x)\n", \
10697 current_config->name, \
10698 pipe_config->name); \
10699 return false; \
10700 }
10701
10702 #define PIPE_CONF_CHECK_I(name) \
10703 if (current_config->name != pipe_config->name) { \
10704 DRM_ERROR("mismatch in " #name " " \
10705 "(expected %i, found %i)\n", \
10706 current_config->name, \
10707 pipe_config->name); \
10708 return false; \
10709 }
10710
10711 /* This is required for BDW+ where there is only one set of registers for
10712 * switching between high and low RR.
10713 * This macro can be used whenever a comparison has to be made between one
10714 * hw state and multiple sw state variables.
10715 */
10716 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10717 if ((current_config->name != pipe_config->name) && \
10718 (current_config->alt_name != pipe_config->name)) { \
10719 DRM_ERROR("mismatch in " #name " " \
10720 "(expected %i or %i, found %i)\n", \
10721 current_config->name, \
10722 current_config->alt_name, \
10723 pipe_config->name); \
10724 return false; \
10725 }
10726
10727 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10728 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10729 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10730 "(expected %i, found %i)\n", \
10731 current_config->name & (mask), \
10732 pipe_config->name & (mask)); \
10733 return false; \
10734 }
10735
10736 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10737 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10738 DRM_ERROR("mismatch in " #name " " \
10739 "(expected %i, found %i)\n", \
10740 current_config->name, \
10741 pipe_config->name); \
10742 return false; \
10743 }
10744
10745 #define PIPE_CONF_QUIRK(quirk) \
10746 ((current_config->quirks | pipe_config->quirks) & (quirk))
10747
10748 PIPE_CONF_CHECK_I(cpu_transcoder);
10749
10750 PIPE_CONF_CHECK_I(has_pch_encoder);
10751 PIPE_CONF_CHECK_I(fdi_lanes);
10752 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10753 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10754 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10755 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10756 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10757
10758 PIPE_CONF_CHECK_I(has_dp_encoder);
10759
10760 if (INTEL_INFO(dev)->gen < 8) {
10761 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10762 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10763 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10764 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10765 PIPE_CONF_CHECK_I(dp_m_n.tu);
10766
10767 if (current_config->has_drrs) {
10768 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10769 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10770 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10771 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10772 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10773 }
10774 } else {
10775 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10776 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10777 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10778 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10779 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10780 }
10781
10782 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10783 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10784 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10785 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10786 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10787 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10788
10789 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10790 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10791 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10792 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10793 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10794 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10795
10796 PIPE_CONF_CHECK_I(pixel_multiplier);
10797 PIPE_CONF_CHECK_I(has_hdmi_sink);
10798 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10799 IS_VALLEYVIEW(dev))
10800 PIPE_CONF_CHECK_I(limited_color_range);
10801
10802 PIPE_CONF_CHECK_I(has_audio);
10803
10804 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10805 DRM_MODE_FLAG_INTERLACE);
10806
10807 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10808 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10809 DRM_MODE_FLAG_PHSYNC);
10810 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10811 DRM_MODE_FLAG_NHSYNC);
10812 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10813 DRM_MODE_FLAG_PVSYNC);
10814 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10815 DRM_MODE_FLAG_NVSYNC);
10816 }
10817
10818 PIPE_CONF_CHECK_I(pipe_src_w);
10819 PIPE_CONF_CHECK_I(pipe_src_h);
10820
10821 /*
10822 * FIXME: BIOS likes to set up a cloned config with lvds+external
10823 * screen. Since we don't yet re-compute the pipe config when moving
10824 * just the lvds port away to another pipe the sw tracking won't match.
10825 *
10826 * Proper atomic modesets with recomputed global state will fix this.
10827 * Until then just don't check gmch state for inherited modes.
10828 */
10829 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10830 PIPE_CONF_CHECK_I(gmch_pfit.control);
10831 /* pfit ratios are autocomputed by the hw on gen4+ */
10832 if (INTEL_INFO(dev)->gen < 4)
10833 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10834 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10835 }
10836
10837 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10838 if (current_config->pch_pfit.enabled) {
10839 PIPE_CONF_CHECK_I(pch_pfit.pos);
10840 PIPE_CONF_CHECK_I(pch_pfit.size);
10841 }
10842
10843 /* BDW+ don't expose a synchronous way to read the state */
10844 if (IS_HASWELL(dev))
10845 PIPE_CONF_CHECK_I(ips_enabled);
10846
10847 PIPE_CONF_CHECK_I(double_wide);
10848
10849 PIPE_CONF_CHECK_X(ddi_pll_sel);
10850
10851 PIPE_CONF_CHECK_I(shared_dpll);
10852 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10853 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10854 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10855 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10856 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10857
10858 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10859 PIPE_CONF_CHECK_I(pipe_bpp);
10860
10861 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10862 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10863
10864 #undef PIPE_CONF_CHECK_X
10865 #undef PIPE_CONF_CHECK_I
10866 #undef PIPE_CONF_CHECK_I_ALT
10867 #undef PIPE_CONF_CHECK_FLAGS
10868 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10869 #undef PIPE_CONF_QUIRK
10870
10871 return true;
10872 }
10873
10874 static void
10875 check_connector_state(struct drm_device *dev)
10876 {
10877 struct intel_connector *connector;
10878
10879 list_for_each_entry(connector, &dev->mode_config.connector_list,
10880 base.head) {
10881 /* This also checks the encoder/connector hw state with the
10882 * ->get_hw_state callbacks. */
10883 intel_connector_check_state(connector);
10884
10885 WARN(&connector->new_encoder->base != connector->base.encoder,
10886 "connector's staged encoder doesn't match current encoder\n");
10887 }
10888 }
10889
10890 static void
10891 check_encoder_state(struct drm_device *dev)
10892 {
10893 struct intel_encoder *encoder;
10894 struct intel_connector *connector;
10895
10896 for_each_intel_encoder(dev, encoder) {
10897 bool enabled = false;
10898 bool active = false;
10899 enum pipe pipe, tracked_pipe;
10900
10901 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10902 encoder->base.base.id,
10903 encoder->base.name);
10904
10905 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10906 "encoder's stage crtc doesn't match current crtc\n");
10907 WARN(encoder->connectors_active && !encoder->base.crtc,
10908 "encoder's active_connectors set, but no crtc\n");
10909
10910 list_for_each_entry(connector, &dev->mode_config.connector_list,
10911 base.head) {
10912 if (connector->base.encoder != &encoder->base)
10913 continue;
10914 enabled = true;
10915 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10916 active = true;
10917 }
10918 /*
10919 * for MST connectors if we unplug the connector is gone
10920 * away but the encoder is still connected to a crtc
10921 * until a modeset happens in response to the hotplug.
10922 */
10923 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10924 continue;
10925
10926 WARN(!!encoder->base.crtc != enabled,
10927 "encoder's enabled state mismatch "
10928 "(expected %i, found %i)\n",
10929 !!encoder->base.crtc, enabled);
10930 WARN(active && !encoder->base.crtc,
10931 "active encoder with no crtc\n");
10932
10933 WARN(encoder->connectors_active != active,
10934 "encoder's computed active state doesn't match tracked active state "
10935 "(expected %i, found %i)\n", active, encoder->connectors_active);
10936
10937 active = encoder->get_hw_state(encoder, &pipe);
10938 WARN(active != encoder->connectors_active,
10939 "encoder's hw state doesn't match sw tracking "
10940 "(expected %i, found %i)\n",
10941 encoder->connectors_active, active);
10942
10943 if (!encoder->base.crtc)
10944 continue;
10945
10946 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10947 WARN(active && pipe != tracked_pipe,
10948 "active encoder's pipe doesn't match"
10949 "(expected %i, found %i)\n",
10950 tracked_pipe, pipe);
10951
10952 }
10953 }
10954
10955 static void
10956 check_crtc_state(struct drm_device *dev)
10957 {
10958 struct drm_i915_private *dev_priv = dev->dev_private;
10959 struct intel_crtc *crtc;
10960 struct intel_encoder *encoder;
10961 struct intel_crtc_config pipe_config;
10962
10963 for_each_intel_crtc(dev, crtc) {
10964 bool enabled = false;
10965 bool active = false;
10966
10967 memset(&pipe_config, 0, sizeof(pipe_config));
10968
10969 DRM_DEBUG_KMS("[CRTC:%d]\n",
10970 crtc->base.base.id);
10971
10972 WARN(crtc->active && !crtc->base.enabled,
10973 "active crtc, but not enabled in sw tracking\n");
10974
10975 for_each_intel_encoder(dev, encoder) {
10976 if (encoder->base.crtc != &crtc->base)
10977 continue;
10978 enabled = true;
10979 if (encoder->connectors_active)
10980 active = true;
10981 }
10982
10983 WARN(active != crtc->active,
10984 "crtc's computed active state doesn't match tracked active state "
10985 "(expected %i, found %i)\n", active, crtc->active);
10986 WARN(enabled != crtc->base.enabled,
10987 "crtc's computed enabled state doesn't match tracked enabled state "
10988 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10989
10990 active = dev_priv->display.get_pipe_config(crtc,
10991 &pipe_config);
10992
10993 /* hw state is inconsistent with the pipe quirk */
10994 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10995 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10996 active = crtc->active;
10997
10998 for_each_intel_encoder(dev, encoder) {
10999 enum pipe pipe;
11000 if (encoder->base.crtc != &crtc->base)
11001 continue;
11002 if (encoder->get_hw_state(encoder, &pipe))
11003 encoder->get_config(encoder, &pipe_config);
11004 }
11005
11006 WARN(crtc->active != active,
11007 "crtc active state doesn't match with hw state "
11008 "(expected %i, found %i)\n", crtc->active, active);
11009
11010 if (active &&
11011 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
11012 WARN(1, "pipe state doesn't match!\n");
11013 intel_dump_pipe_config(crtc, &pipe_config,
11014 "[hw state]");
11015 intel_dump_pipe_config(crtc, &crtc->config,
11016 "[sw state]");
11017 }
11018 }
11019 }
11020
11021 static void
11022 check_shared_dpll_state(struct drm_device *dev)
11023 {
11024 struct drm_i915_private *dev_priv = dev->dev_private;
11025 struct intel_crtc *crtc;
11026 struct intel_dpll_hw_state dpll_hw_state;
11027 int i;
11028
11029 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11030 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11031 int enabled_crtcs = 0, active_crtcs = 0;
11032 bool active;
11033
11034 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11035
11036 DRM_DEBUG_KMS("%s\n", pll->name);
11037
11038 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11039
11040 WARN(pll->active > pll->refcount,
11041 "more active pll users than references: %i vs %i\n",
11042 pll->active, pll->refcount);
11043 WARN(pll->active && !pll->on,
11044 "pll in active use but not on in sw tracking\n");
11045 WARN(pll->on && !pll->active,
11046 "pll in on but not on in use in sw tracking\n");
11047 WARN(pll->on != active,
11048 "pll on state mismatch (expected %i, found %i)\n",
11049 pll->on, active);
11050
11051 for_each_intel_crtc(dev, crtc) {
11052 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11053 enabled_crtcs++;
11054 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11055 active_crtcs++;
11056 }
11057 WARN(pll->active != active_crtcs,
11058 "pll active crtcs mismatch (expected %i, found %i)\n",
11059 pll->active, active_crtcs);
11060 WARN(pll->refcount != enabled_crtcs,
11061 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11062 pll->refcount, enabled_crtcs);
11063
11064 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11065 sizeof(dpll_hw_state)),
11066 "pll hw state mismatch\n");
11067 }
11068 }
11069
11070 void
11071 intel_modeset_check_state(struct drm_device *dev)
11072 {
11073 check_connector_state(dev);
11074 check_encoder_state(dev);
11075 check_crtc_state(dev);
11076 check_shared_dpll_state(dev);
11077 }
11078
11079 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11080 int dotclock)
11081 {
11082 /*
11083 * FDI already provided one idea for the dotclock.
11084 * Yell if the encoder disagrees.
11085 */
11086 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11087 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11088 pipe_config->adjusted_mode.crtc_clock, dotclock);
11089 }
11090
11091 static void update_scanline_offset(struct intel_crtc *crtc)
11092 {
11093 struct drm_device *dev = crtc->base.dev;
11094
11095 /*
11096 * The scanline counter increments at the leading edge of hsync.
11097 *
11098 * On most platforms it starts counting from vtotal-1 on the
11099 * first active line. That means the scanline counter value is
11100 * always one less than what we would expect. Ie. just after
11101 * start of vblank, which also occurs at start of hsync (on the
11102 * last active line), the scanline counter will read vblank_start-1.
11103 *
11104 * On gen2 the scanline counter starts counting from 1 instead
11105 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11106 * to keep the value positive), instead of adding one.
11107 *
11108 * On HSW+ the behaviour of the scanline counter depends on the output
11109 * type. For DP ports it behaves like most other platforms, but on HDMI
11110 * there's an extra 1 line difference. So we need to add two instead of
11111 * one to the value.
11112 */
11113 if (IS_GEN2(dev)) {
11114 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11115 int vtotal;
11116
11117 vtotal = mode->crtc_vtotal;
11118 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11119 vtotal /= 2;
11120
11121 crtc->scanline_offset = vtotal - 1;
11122 } else if (HAS_DDI(dev) &&
11123 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11124 crtc->scanline_offset = 2;
11125 } else
11126 crtc->scanline_offset = 1;
11127 }
11128
11129 static int __intel_set_mode(struct drm_crtc *crtc,
11130 struct drm_display_mode *mode,
11131 int x, int y, struct drm_framebuffer *fb)
11132 {
11133 struct drm_device *dev = crtc->dev;
11134 struct drm_i915_private *dev_priv = dev->dev_private;
11135 struct drm_display_mode *saved_mode;
11136 struct intel_crtc_config *pipe_config = NULL;
11137 struct intel_crtc *intel_crtc;
11138 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11139 int ret = 0;
11140
11141 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11142 if (!saved_mode)
11143 return -ENOMEM;
11144
11145 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11146 &prepare_pipes, &disable_pipes);
11147
11148 *saved_mode = crtc->mode;
11149
11150 /* Hack: Because we don't (yet) support global modeset on multiple
11151 * crtcs, we don't keep track of the new mode for more than one crtc.
11152 * Hence simply check whether any bit is set in modeset_pipes in all the
11153 * pieces of code that are not yet converted to deal with mutliple crtcs
11154 * changing their mode at the same time. */
11155 if (modeset_pipes) {
11156 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11157 if (IS_ERR(pipe_config)) {
11158 ret = PTR_ERR(pipe_config);
11159 pipe_config = NULL;
11160
11161 goto out;
11162 }
11163 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11164 "[modeset]");
11165 to_intel_crtc(crtc)->new_config = pipe_config;
11166 }
11167
11168 /*
11169 * See if the config requires any additional preparation, e.g.
11170 * to adjust global state with pipes off. We need to do this
11171 * here so we can get the modeset_pipe updated config for the new
11172 * mode set on this crtc. For other crtcs we need to use the
11173 * adjusted_mode bits in the crtc directly.
11174 */
11175 if (IS_VALLEYVIEW(dev)) {
11176 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11177
11178 /* may have added more to prepare_pipes than we should */
11179 prepare_pipes &= ~disable_pipes;
11180 }
11181
11182 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11183 intel_crtc_disable(&intel_crtc->base);
11184
11185 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11186 if (intel_crtc->base.enabled)
11187 dev_priv->display.crtc_disable(&intel_crtc->base);
11188 }
11189
11190 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11191 * to set it here already despite that we pass it down the callchain.
11192 */
11193 if (modeset_pipes) {
11194 crtc->mode = *mode;
11195 /* mode_set/enable/disable functions rely on a correct pipe
11196 * config. */
11197 to_intel_crtc(crtc)->config = *pipe_config;
11198 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11199
11200 /*
11201 * Calculate and store various constants which
11202 * are later needed by vblank and swap-completion
11203 * timestamping. They are derived from true hwmode.
11204 */
11205 drm_calc_timestamping_constants(crtc,
11206 &pipe_config->adjusted_mode);
11207 }
11208
11209 /* Only after disabling all output pipelines that will be changed can we
11210 * update the the output configuration. */
11211 intel_modeset_update_state(dev, prepare_pipes);
11212
11213 if (dev_priv->display.modeset_global_resources)
11214 dev_priv->display.modeset_global_resources(dev);
11215
11216 /* Set up the DPLL and any encoders state that needs to adjust or depend
11217 * on the DPLL.
11218 */
11219 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11220 struct drm_framebuffer *old_fb = crtc->primary->fb;
11221 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11222 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11223
11224 mutex_lock(&dev->struct_mutex);
11225 ret = intel_pin_and_fence_fb_obj(dev,
11226 obj,
11227 NULL);
11228 if (ret != 0) {
11229 DRM_ERROR("pin & fence failed\n");
11230 mutex_unlock(&dev->struct_mutex);
11231 goto done;
11232 }
11233 if (old_fb)
11234 intel_unpin_fb_obj(old_obj);
11235 i915_gem_track_fb(old_obj, obj,
11236 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11237 mutex_unlock(&dev->struct_mutex);
11238
11239 crtc->primary->fb = fb;
11240 crtc->x = x;
11241 crtc->y = y;
11242
11243 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11244 x, y, fb);
11245 if (ret)
11246 goto done;
11247 }
11248
11249 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11250 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11251 update_scanline_offset(intel_crtc);
11252
11253 dev_priv->display.crtc_enable(&intel_crtc->base);
11254 }
11255
11256 /* FIXME: add subpixel order */
11257 done:
11258 if (ret && crtc->enabled)
11259 crtc->mode = *saved_mode;
11260
11261 out:
11262 kfree(pipe_config);
11263 kfree(saved_mode);
11264 return ret;
11265 }
11266
11267 static int intel_set_mode(struct drm_crtc *crtc,
11268 struct drm_display_mode *mode,
11269 int x, int y, struct drm_framebuffer *fb)
11270 {
11271 int ret;
11272
11273 ret = __intel_set_mode(crtc, mode, x, y, fb);
11274
11275 if (ret == 0)
11276 intel_modeset_check_state(crtc->dev);
11277
11278 return ret;
11279 }
11280
11281 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11282 {
11283 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11284 }
11285
11286 #undef for_each_intel_crtc_masked
11287
11288 static void intel_set_config_free(struct intel_set_config *config)
11289 {
11290 if (!config)
11291 return;
11292
11293 kfree(config->save_connector_encoders);
11294 kfree(config->save_encoder_crtcs);
11295 kfree(config->save_crtc_enabled);
11296 kfree(config);
11297 }
11298
11299 static int intel_set_config_save_state(struct drm_device *dev,
11300 struct intel_set_config *config)
11301 {
11302 struct drm_crtc *crtc;
11303 struct drm_encoder *encoder;
11304 struct drm_connector *connector;
11305 int count;
11306
11307 config->save_crtc_enabled =
11308 kcalloc(dev->mode_config.num_crtc,
11309 sizeof(bool), GFP_KERNEL);
11310 if (!config->save_crtc_enabled)
11311 return -ENOMEM;
11312
11313 config->save_encoder_crtcs =
11314 kcalloc(dev->mode_config.num_encoder,
11315 sizeof(struct drm_crtc *), GFP_KERNEL);
11316 if (!config->save_encoder_crtcs)
11317 return -ENOMEM;
11318
11319 config->save_connector_encoders =
11320 kcalloc(dev->mode_config.num_connector,
11321 sizeof(struct drm_encoder *), GFP_KERNEL);
11322 if (!config->save_connector_encoders)
11323 return -ENOMEM;
11324
11325 /* Copy data. Note that driver private data is not affected.
11326 * Should anything bad happen only the expected state is
11327 * restored, not the drivers personal bookkeeping.
11328 */
11329 count = 0;
11330 for_each_crtc(dev, crtc) {
11331 config->save_crtc_enabled[count++] = crtc->enabled;
11332 }
11333
11334 count = 0;
11335 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11336 config->save_encoder_crtcs[count++] = encoder->crtc;
11337 }
11338
11339 count = 0;
11340 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11341 config->save_connector_encoders[count++] = connector->encoder;
11342 }
11343
11344 return 0;
11345 }
11346
11347 static void intel_set_config_restore_state(struct drm_device *dev,
11348 struct intel_set_config *config)
11349 {
11350 struct intel_crtc *crtc;
11351 struct intel_encoder *encoder;
11352 struct intel_connector *connector;
11353 int count;
11354
11355 count = 0;
11356 for_each_intel_crtc(dev, crtc) {
11357 crtc->new_enabled = config->save_crtc_enabled[count++];
11358
11359 if (crtc->new_enabled)
11360 crtc->new_config = &crtc->config;
11361 else
11362 crtc->new_config = NULL;
11363 }
11364
11365 count = 0;
11366 for_each_intel_encoder(dev, encoder) {
11367 encoder->new_crtc =
11368 to_intel_crtc(config->save_encoder_crtcs[count++]);
11369 }
11370
11371 count = 0;
11372 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11373 connector->new_encoder =
11374 to_intel_encoder(config->save_connector_encoders[count++]);
11375 }
11376 }
11377
11378 static bool
11379 is_crtc_connector_off(struct drm_mode_set *set)
11380 {
11381 int i;
11382
11383 if (set->num_connectors == 0)
11384 return false;
11385
11386 if (WARN_ON(set->connectors == NULL))
11387 return false;
11388
11389 for (i = 0; i < set->num_connectors; i++)
11390 if (set->connectors[i]->encoder &&
11391 set->connectors[i]->encoder->crtc == set->crtc &&
11392 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11393 return true;
11394
11395 return false;
11396 }
11397
11398 static void
11399 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11400 struct intel_set_config *config)
11401 {
11402
11403 /* We should be able to check here if the fb has the same properties
11404 * and then just flip_or_move it */
11405 if (is_crtc_connector_off(set)) {
11406 config->mode_changed = true;
11407 } else if (set->crtc->primary->fb != set->fb) {
11408 /*
11409 * If we have no fb, we can only flip as long as the crtc is
11410 * active, otherwise we need a full mode set. The crtc may
11411 * be active if we've only disabled the primary plane, or
11412 * in fastboot situations.
11413 */
11414 if (set->crtc->primary->fb == NULL) {
11415 struct intel_crtc *intel_crtc =
11416 to_intel_crtc(set->crtc);
11417
11418 if (intel_crtc->active) {
11419 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11420 config->fb_changed = true;
11421 } else {
11422 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11423 config->mode_changed = true;
11424 }
11425 } else if (set->fb == NULL) {
11426 config->mode_changed = true;
11427 } else if (set->fb->pixel_format !=
11428 set->crtc->primary->fb->pixel_format) {
11429 config->mode_changed = true;
11430 } else {
11431 config->fb_changed = true;
11432 }
11433 }
11434
11435 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11436 config->fb_changed = true;
11437
11438 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11439 DRM_DEBUG_KMS("modes are different, full mode set\n");
11440 drm_mode_debug_printmodeline(&set->crtc->mode);
11441 drm_mode_debug_printmodeline(set->mode);
11442 config->mode_changed = true;
11443 }
11444
11445 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11446 set->crtc->base.id, config->mode_changed, config->fb_changed);
11447 }
11448
11449 static int
11450 intel_modeset_stage_output_state(struct drm_device *dev,
11451 struct drm_mode_set *set,
11452 struct intel_set_config *config)
11453 {
11454 struct intel_connector *connector;
11455 struct intel_encoder *encoder;
11456 struct intel_crtc *crtc;
11457 int ro;
11458
11459 /* The upper layers ensure that we either disable a crtc or have a list
11460 * of connectors. For paranoia, double-check this. */
11461 WARN_ON(!set->fb && (set->num_connectors != 0));
11462 WARN_ON(set->fb && (set->num_connectors == 0));
11463
11464 list_for_each_entry(connector, &dev->mode_config.connector_list,
11465 base.head) {
11466 /* Otherwise traverse passed in connector list and get encoders
11467 * for them. */
11468 for (ro = 0; ro < set->num_connectors; ro++) {
11469 if (set->connectors[ro] == &connector->base) {
11470 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11471 break;
11472 }
11473 }
11474
11475 /* If we disable the crtc, disable all its connectors. Also, if
11476 * the connector is on the changing crtc but not on the new
11477 * connector list, disable it. */
11478 if ((!set->fb || ro == set->num_connectors) &&
11479 connector->base.encoder &&
11480 connector->base.encoder->crtc == set->crtc) {
11481 connector->new_encoder = NULL;
11482
11483 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11484 connector->base.base.id,
11485 connector->base.name);
11486 }
11487
11488
11489 if (&connector->new_encoder->base != connector->base.encoder) {
11490 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11491 config->mode_changed = true;
11492 }
11493 }
11494 /* connector->new_encoder is now updated for all connectors. */
11495
11496 /* Update crtc of enabled connectors. */
11497 list_for_each_entry(connector, &dev->mode_config.connector_list,
11498 base.head) {
11499 struct drm_crtc *new_crtc;
11500
11501 if (!connector->new_encoder)
11502 continue;
11503
11504 new_crtc = connector->new_encoder->base.crtc;
11505
11506 for (ro = 0; ro < set->num_connectors; ro++) {
11507 if (set->connectors[ro] == &connector->base)
11508 new_crtc = set->crtc;
11509 }
11510
11511 /* Make sure the new CRTC will work with the encoder */
11512 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11513 new_crtc)) {
11514 return -EINVAL;
11515 }
11516 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11517
11518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11519 connector->base.base.id,
11520 connector->base.name,
11521 new_crtc->base.id);
11522 }
11523
11524 /* Check for any encoders that needs to be disabled. */
11525 for_each_intel_encoder(dev, encoder) {
11526 int num_connectors = 0;
11527 list_for_each_entry(connector,
11528 &dev->mode_config.connector_list,
11529 base.head) {
11530 if (connector->new_encoder == encoder) {
11531 WARN_ON(!connector->new_encoder->new_crtc);
11532 num_connectors++;
11533 }
11534 }
11535
11536 if (num_connectors == 0)
11537 encoder->new_crtc = NULL;
11538 else if (num_connectors > 1)
11539 return -EINVAL;
11540
11541 /* Only now check for crtc changes so we don't miss encoders
11542 * that will be disabled. */
11543 if (&encoder->new_crtc->base != encoder->base.crtc) {
11544 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11545 config->mode_changed = true;
11546 }
11547 }
11548 /* Now we've also updated encoder->new_crtc for all encoders. */
11549 list_for_each_entry(connector, &dev->mode_config.connector_list,
11550 base.head) {
11551 if (connector->new_encoder)
11552 if (connector->new_encoder != connector->encoder)
11553 connector->encoder = connector->new_encoder;
11554 }
11555 for_each_intel_crtc(dev, crtc) {
11556 crtc->new_enabled = false;
11557
11558 for_each_intel_encoder(dev, encoder) {
11559 if (encoder->new_crtc == crtc) {
11560 crtc->new_enabled = true;
11561 break;
11562 }
11563 }
11564
11565 if (crtc->new_enabled != crtc->base.enabled) {
11566 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11567 crtc->new_enabled ? "en" : "dis");
11568 config->mode_changed = true;
11569 }
11570
11571 if (crtc->new_enabled)
11572 crtc->new_config = &crtc->config;
11573 else
11574 crtc->new_config = NULL;
11575 }
11576
11577 return 0;
11578 }
11579
11580 static void disable_crtc_nofb(struct intel_crtc *crtc)
11581 {
11582 struct drm_device *dev = crtc->base.dev;
11583 struct intel_encoder *encoder;
11584 struct intel_connector *connector;
11585
11586 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11587 pipe_name(crtc->pipe));
11588
11589 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11590 if (connector->new_encoder &&
11591 connector->new_encoder->new_crtc == crtc)
11592 connector->new_encoder = NULL;
11593 }
11594
11595 for_each_intel_encoder(dev, encoder) {
11596 if (encoder->new_crtc == crtc)
11597 encoder->new_crtc = NULL;
11598 }
11599
11600 crtc->new_enabled = false;
11601 crtc->new_config = NULL;
11602 }
11603
11604 static int intel_crtc_set_config(struct drm_mode_set *set)
11605 {
11606 struct drm_device *dev;
11607 struct drm_mode_set save_set;
11608 struct intel_set_config *config;
11609 int ret;
11610
11611 BUG_ON(!set);
11612 BUG_ON(!set->crtc);
11613 BUG_ON(!set->crtc->helper_private);
11614
11615 /* Enforce sane interface api - has been abused by the fb helper. */
11616 BUG_ON(!set->mode && set->fb);
11617 BUG_ON(set->fb && set->num_connectors == 0);
11618
11619 if (set->fb) {
11620 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11621 set->crtc->base.id, set->fb->base.id,
11622 (int)set->num_connectors, set->x, set->y);
11623 } else {
11624 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11625 }
11626
11627 dev = set->crtc->dev;
11628
11629 ret = -ENOMEM;
11630 config = kzalloc(sizeof(*config), GFP_KERNEL);
11631 if (!config)
11632 goto out_config;
11633
11634 ret = intel_set_config_save_state(dev, config);
11635 if (ret)
11636 goto out_config;
11637
11638 save_set.crtc = set->crtc;
11639 save_set.mode = &set->crtc->mode;
11640 save_set.x = set->crtc->x;
11641 save_set.y = set->crtc->y;
11642 save_set.fb = set->crtc->primary->fb;
11643
11644 /* Compute whether we need a full modeset, only an fb base update or no
11645 * change at all. In the future we might also check whether only the
11646 * mode changed, e.g. for LVDS where we only change the panel fitter in
11647 * such cases. */
11648 intel_set_config_compute_mode_changes(set, config);
11649
11650 ret = intel_modeset_stage_output_state(dev, set, config);
11651 if (ret)
11652 goto fail;
11653
11654 if (config->mode_changed) {
11655 ret = intel_set_mode(set->crtc, set->mode,
11656 set->x, set->y, set->fb);
11657 } else if (config->fb_changed) {
11658 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11659
11660 intel_crtc_wait_for_pending_flips(set->crtc);
11661
11662 ret = intel_pipe_set_base(set->crtc,
11663 set->x, set->y, set->fb);
11664
11665 /*
11666 * We need to make sure the primary plane is re-enabled if it
11667 * has previously been turned off.
11668 */
11669 if (!intel_crtc->primary_enabled && ret == 0) {
11670 WARN_ON(!intel_crtc->active);
11671 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11672 }
11673
11674 /*
11675 * In the fastboot case this may be our only check of the
11676 * state after boot. It would be better to only do it on
11677 * the first update, but we don't have a nice way of doing that
11678 * (and really, set_config isn't used much for high freq page
11679 * flipping, so increasing its cost here shouldn't be a big
11680 * deal).
11681 */
11682 if (i915.fastboot && ret == 0)
11683 intel_modeset_check_state(set->crtc->dev);
11684 }
11685
11686 if (ret) {
11687 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11688 set->crtc->base.id, ret);
11689 fail:
11690 intel_set_config_restore_state(dev, config);
11691
11692 /*
11693 * HACK: if the pipe was on, but we didn't have a framebuffer,
11694 * force the pipe off to avoid oopsing in the modeset code
11695 * due to fb==NULL. This should only happen during boot since
11696 * we don't yet reconstruct the FB from the hardware state.
11697 */
11698 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11699 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11700
11701 /* Try to restore the config */
11702 if (config->mode_changed &&
11703 intel_set_mode(save_set.crtc, save_set.mode,
11704 save_set.x, save_set.y, save_set.fb))
11705 DRM_ERROR("failed to restore config after modeset failure\n");
11706 }
11707
11708 out_config:
11709 intel_set_config_free(config);
11710 return ret;
11711 }
11712
11713 static const struct drm_crtc_funcs intel_crtc_funcs = {
11714 .gamma_set = intel_crtc_gamma_set,
11715 .set_config = intel_crtc_set_config,
11716 .destroy = intel_crtc_destroy,
11717 .page_flip = intel_crtc_page_flip,
11718 };
11719
11720 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11721 struct intel_shared_dpll *pll,
11722 struct intel_dpll_hw_state *hw_state)
11723 {
11724 uint32_t val;
11725
11726 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11727 return false;
11728
11729 val = I915_READ(PCH_DPLL(pll->id));
11730 hw_state->dpll = val;
11731 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11732 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11733
11734 return val & DPLL_VCO_ENABLE;
11735 }
11736
11737 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11738 struct intel_shared_dpll *pll)
11739 {
11740 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11741 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11742 }
11743
11744 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11745 struct intel_shared_dpll *pll)
11746 {
11747 /* PCH refclock must be enabled first */
11748 ibx_assert_pch_refclk_enabled(dev_priv);
11749
11750 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11751
11752 /* Wait for the clocks to stabilize. */
11753 POSTING_READ(PCH_DPLL(pll->id));
11754 udelay(150);
11755
11756 /* The pixel multiplier can only be updated once the
11757 * DPLL is enabled and the clocks are stable.
11758 *
11759 * So write it again.
11760 */
11761 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11762 POSTING_READ(PCH_DPLL(pll->id));
11763 udelay(200);
11764 }
11765
11766 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11767 struct intel_shared_dpll *pll)
11768 {
11769 struct drm_device *dev = dev_priv->dev;
11770 struct intel_crtc *crtc;
11771
11772 /* Make sure no transcoder isn't still depending on us. */
11773 for_each_intel_crtc(dev, crtc) {
11774 if (intel_crtc_to_shared_dpll(crtc) == pll)
11775 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11776 }
11777
11778 I915_WRITE(PCH_DPLL(pll->id), 0);
11779 POSTING_READ(PCH_DPLL(pll->id));
11780 udelay(200);
11781 }
11782
11783 static char *ibx_pch_dpll_names[] = {
11784 "PCH DPLL A",
11785 "PCH DPLL B",
11786 };
11787
11788 static void ibx_pch_dpll_init(struct drm_device *dev)
11789 {
11790 struct drm_i915_private *dev_priv = dev->dev_private;
11791 int i;
11792
11793 dev_priv->num_shared_dpll = 2;
11794
11795 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11796 dev_priv->shared_dplls[i].id = i;
11797 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11798 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11799 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11800 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11801 dev_priv->shared_dplls[i].get_hw_state =
11802 ibx_pch_dpll_get_hw_state;
11803 }
11804 }
11805
11806 static void intel_shared_dpll_init(struct drm_device *dev)
11807 {
11808 struct drm_i915_private *dev_priv = dev->dev_private;
11809
11810 if (HAS_DDI(dev))
11811 intel_ddi_pll_init(dev);
11812 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11813 ibx_pch_dpll_init(dev);
11814 else
11815 dev_priv->num_shared_dpll = 0;
11816
11817 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11818 }
11819
11820 static int
11821 intel_primary_plane_disable(struct drm_plane *plane)
11822 {
11823 struct drm_device *dev = plane->dev;
11824 struct intel_crtc *intel_crtc;
11825
11826 if (!plane->fb)
11827 return 0;
11828
11829 BUG_ON(!plane->crtc);
11830
11831 intel_crtc = to_intel_crtc(plane->crtc);
11832
11833 /*
11834 * Even though we checked plane->fb above, it's still possible that
11835 * the primary plane has been implicitly disabled because the crtc
11836 * coordinates given weren't visible, or because we detected
11837 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11838 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11839 * In either case, we need to unpin the FB and let the fb pointer get
11840 * updated, but otherwise we don't need to touch the hardware.
11841 */
11842 if (!intel_crtc->primary_enabled)
11843 goto disable_unpin;
11844
11845 intel_crtc_wait_for_pending_flips(plane->crtc);
11846 intel_disable_primary_hw_plane(plane, plane->crtc);
11847
11848 disable_unpin:
11849 mutex_lock(&dev->struct_mutex);
11850 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11851 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11852 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11853 mutex_unlock(&dev->struct_mutex);
11854 plane->fb = NULL;
11855
11856 return 0;
11857 }
11858
11859 static int
11860 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11861 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11862 unsigned int crtc_w, unsigned int crtc_h,
11863 uint32_t src_x, uint32_t src_y,
11864 uint32_t src_w, uint32_t src_h)
11865 {
11866 struct drm_device *dev = crtc->dev;
11867 struct drm_i915_private *dev_priv = dev->dev_private;
11868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11869 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11870 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11871 struct drm_rect dest = {
11872 /* integer pixels */
11873 .x1 = crtc_x,
11874 .y1 = crtc_y,
11875 .x2 = crtc_x + crtc_w,
11876 .y2 = crtc_y + crtc_h,
11877 };
11878 struct drm_rect src = {
11879 /* 16.16 fixed point */
11880 .x1 = src_x,
11881 .y1 = src_y,
11882 .x2 = src_x + src_w,
11883 .y2 = src_y + src_h,
11884 };
11885 const struct drm_rect clip = {
11886 /* integer pixels */
11887 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11888 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11889 };
11890 const struct {
11891 int crtc_x, crtc_y;
11892 unsigned int crtc_w, crtc_h;
11893 uint32_t src_x, src_y, src_w, src_h;
11894 } orig = {
11895 .crtc_x = crtc_x,
11896 .crtc_y = crtc_y,
11897 .crtc_w = crtc_w,
11898 .crtc_h = crtc_h,
11899 .src_x = src_x,
11900 .src_y = src_y,
11901 .src_w = src_w,
11902 .src_h = src_h,
11903 };
11904 struct intel_plane *intel_plane = to_intel_plane(plane);
11905 bool visible;
11906 int ret;
11907
11908 ret = drm_plane_helper_check_update(plane, crtc, fb,
11909 &src, &dest, &clip,
11910 DRM_PLANE_HELPER_NO_SCALING,
11911 DRM_PLANE_HELPER_NO_SCALING,
11912 false, true, &visible);
11913
11914 if (ret)
11915 return ret;
11916
11917 /*
11918 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11919 * updating the fb pointer, and returning without touching the
11920 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11921 * turn on the display with all planes setup as desired.
11922 */
11923 if (!crtc->enabled) {
11924 mutex_lock(&dev->struct_mutex);
11925
11926 /*
11927 * If we already called setplane while the crtc was disabled,
11928 * we may have an fb pinned; unpin it.
11929 */
11930 if (plane->fb)
11931 intel_unpin_fb_obj(old_obj);
11932
11933 i915_gem_track_fb(old_obj, obj,
11934 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11935
11936 /* Pin and return without programming hardware */
11937 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11938 mutex_unlock(&dev->struct_mutex);
11939
11940 return ret;
11941 }
11942
11943 intel_crtc_wait_for_pending_flips(crtc);
11944
11945 /*
11946 * If clipping results in a non-visible primary plane, we'll disable
11947 * the primary plane. Note that this is a bit different than what
11948 * happens if userspace explicitly disables the plane by passing fb=0
11949 * because plane->fb still gets set and pinned.
11950 */
11951 if (!visible) {
11952 mutex_lock(&dev->struct_mutex);
11953
11954 /*
11955 * Try to pin the new fb first so that we can bail out if we
11956 * fail.
11957 */
11958 if (plane->fb != fb) {
11959 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11960 if (ret) {
11961 mutex_unlock(&dev->struct_mutex);
11962 return ret;
11963 }
11964 }
11965
11966 i915_gem_track_fb(old_obj, obj,
11967 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11968
11969 if (intel_crtc->primary_enabled)
11970 intel_disable_primary_hw_plane(plane, crtc);
11971
11972
11973 if (plane->fb != fb)
11974 if (plane->fb)
11975 intel_unpin_fb_obj(old_obj);
11976
11977 mutex_unlock(&dev->struct_mutex);
11978
11979 } else {
11980 if (intel_crtc && intel_crtc->active &&
11981 intel_crtc->primary_enabled) {
11982 /*
11983 * FBC does not work on some platforms for rotated
11984 * planes, so disable it when rotation is not 0 and
11985 * update it when rotation is set back to 0.
11986 *
11987 * FIXME: This is redundant with the fbc update done in
11988 * the primary plane enable function except that that
11989 * one is done too late. We eventually need to unify
11990 * this.
11991 */
11992 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11993 dev_priv->fbc.plane == intel_crtc->plane &&
11994 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11995 intel_disable_fbc(dev);
11996 }
11997 }
11998 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11999 if (ret)
12000 return ret;
12001
12002 if (!intel_crtc->primary_enabled)
12003 intel_enable_primary_hw_plane(plane, crtc);
12004 }
12005
12006 intel_plane->crtc_x = orig.crtc_x;
12007 intel_plane->crtc_y = orig.crtc_y;
12008 intel_plane->crtc_w = orig.crtc_w;
12009 intel_plane->crtc_h = orig.crtc_h;
12010 intel_plane->src_x = orig.src_x;
12011 intel_plane->src_y = orig.src_y;
12012 intel_plane->src_w = orig.src_w;
12013 intel_plane->src_h = orig.src_h;
12014 intel_plane->obj = obj;
12015
12016 return 0;
12017 }
12018
12019 /* Common destruction function for both primary and cursor planes */
12020 static void intel_plane_destroy(struct drm_plane *plane)
12021 {
12022 struct intel_plane *intel_plane = to_intel_plane(plane);
12023 drm_plane_cleanup(plane);
12024 kfree(intel_plane);
12025 }
12026
12027 static const struct drm_plane_funcs intel_primary_plane_funcs = {
12028 .update_plane = intel_primary_plane_setplane,
12029 .disable_plane = intel_primary_plane_disable,
12030 .destroy = intel_plane_destroy,
12031 .set_property = intel_plane_set_property
12032 };
12033
12034 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12035 int pipe)
12036 {
12037 struct intel_plane *primary;
12038 const uint32_t *intel_primary_formats;
12039 int num_formats;
12040
12041 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12042 if (primary == NULL)
12043 return NULL;
12044
12045 primary->can_scale = false;
12046 primary->max_downscale = 1;
12047 primary->pipe = pipe;
12048 primary->plane = pipe;
12049 primary->rotation = BIT(DRM_ROTATE_0);
12050 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12051 primary->plane = !pipe;
12052
12053 if (INTEL_INFO(dev)->gen <= 3) {
12054 intel_primary_formats = intel_primary_formats_gen2;
12055 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12056 } else {
12057 intel_primary_formats = intel_primary_formats_gen4;
12058 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12059 }
12060
12061 drm_universal_plane_init(dev, &primary->base, 0,
12062 &intel_primary_plane_funcs,
12063 intel_primary_formats, num_formats,
12064 DRM_PLANE_TYPE_PRIMARY);
12065
12066 if (INTEL_INFO(dev)->gen >= 4) {
12067 if (!dev->mode_config.rotation_property)
12068 dev->mode_config.rotation_property =
12069 drm_mode_create_rotation_property(dev,
12070 BIT(DRM_ROTATE_0) |
12071 BIT(DRM_ROTATE_180));
12072 if (dev->mode_config.rotation_property)
12073 drm_object_attach_property(&primary->base.base,
12074 dev->mode_config.rotation_property,
12075 primary->rotation);
12076 }
12077
12078 return &primary->base;
12079 }
12080
12081 static int
12082 intel_cursor_plane_disable(struct drm_plane *plane)
12083 {
12084 if (!plane->fb)
12085 return 0;
12086
12087 BUG_ON(!plane->crtc);
12088
12089 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12090 }
12091
12092 static int
12093 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12094 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12095 unsigned int crtc_w, unsigned int crtc_h,
12096 uint32_t src_x, uint32_t src_y,
12097 uint32_t src_w, uint32_t src_h)
12098 {
12099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12100 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12101 struct drm_i915_gem_object *obj = intel_fb->obj;
12102 struct drm_rect dest = {
12103 /* integer pixels */
12104 .x1 = crtc_x,
12105 .y1 = crtc_y,
12106 .x2 = crtc_x + crtc_w,
12107 .y2 = crtc_y + crtc_h,
12108 };
12109 struct drm_rect src = {
12110 /* 16.16 fixed point */
12111 .x1 = src_x,
12112 .y1 = src_y,
12113 .x2 = src_x + src_w,
12114 .y2 = src_y + src_h,
12115 };
12116 const struct drm_rect clip = {
12117 /* integer pixels */
12118 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12119 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12120 };
12121 bool visible;
12122 int ret;
12123
12124 ret = drm_plane_helper_check_update(plane, crtc, fb,
12125 &src, &dest, &clip,
12126 DRM_PLANE_HELPER_NO_SCALING,
12127 DRM_PLANE_HELPER_NO_SCALING,
12128 true, true, &visible);
12129 if (ret)
12130 return ret;
12131
12132 crtc->cursor_x = crtc_x;
12133 crtc->cursor_y = crtc_y;
12134 if (fb != crtc->cursor->fb) {
12135 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12136 } else {
12137 intel_crtc_update_cursor(crtc, visible);
12138
12139 intel_frontbuffer_flip(crtc->dev,
12140 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12141
12142 return 0;
12143 }
12144 }
12145 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12146 .update_plane = intel_cursor_plane_update,
12147 .disable_plane = intel_cursor_plane_disable,
12148 .destroy = intel_plane_destroy,
12149 };
12150
12151 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12152 int pipe)
12153 {
12154 struct intel_plane *cursor;
12155
12156 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12157 if (cursor == NULL)
12158 return NULL;
12159
12160 cursor->can_scale = false;
12161 cursor->max_downscale = 1;
12162 cursor->pipe = pipe;
12163 cursor->plane = pipe;
12164
12165 drm_universal_plane_init(dev, &cursor->base, 0,
12166 &intel_cursor_plane_funcs,
12167 intel_cursor_formats,
12168 ARRAY_SIZE(intel_cursor_formats),
12169 DRM_PLANE_TYPE_CURSOR);
12170 return &cursor->base;
12171 }
12172
12173 static void intel_crtc_init(struct drm_device *dev, int pipe)
12174 {
12175 struct drm_i915_private *dev_priv = dev->dev_private;
12176 struct intel_crtc *intel_crtc;
12177 struct drm_plane *primary = NULL;
12178 struct drm_plane *cursor = NULL;
12179 int i, ret;
12180
12181 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12182 if (intel_crtc == NULL)
12183 return;
12184
12185 primary = intel_primary_plane_create(dev, pipe);
12186 if (!primary)
12187 goto fail;
12188
12189 cursor = intel_cursor_plane_create(dev, pipe);
12190 if (!cursor)
12191 goto fail;
12192
12193 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12194 cursor, &intel_crtc_funcs);
12195 if (ret)
12196 goto fail;
12197
12198 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12199 for (i = 0; i < 256; i++) {
12200 intel_crtc->lut_r[i] = i;
12201 intel_crtc->lut_g[i] = i;
12202 intel_crtc->lut_b[i] = i;
12203 }
12204
12205 /*
12206 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12207 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12208 */
12209 intel_crtc->pipe = pipe;
12210 intel_crtc->plane = pipe;
12211 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12212 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12213 intel_crtc->plane = !pipe;
12214 }
12215
12216 intel_crtc->cursor_base = ~0;
12217 intel_crtc->cursor_cntl = ~0;
12218 intel_crtc->cursor_size = ~0;
12219
12220 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12221 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12222 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12223 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12224
12225 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12226
12227 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12228 return;
12229
12230 fail:
12231 if (primary)
12232 drm_plane_cleanup(primary);
12233 if (cursor)
12234 drm_plane_cleanup(cursor);
12235 kfree(intel_crtc);
12236 }
12237
12238 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12239 {
12240 struct drm_encoder *encoder = connector->base.encoder;
12241 struct drm_device *dev = connector->base.dev;
12242
12243 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12244
12245 if (!encoder)
12246 return INVALID_PIPE;
12247
12248 return to_intel_crtc(encoder->crtc)->pipe;
12249 }
12250
12251 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12252 struct drm_file *file)
12253 {
12254 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12255 struct drm_crtc *drmmode_crtc;
12256 struct intel_crtc *crtc;
12257
12258 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12259 return -ENODEV;
12260
12261 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12262
12263 if (!drmmode_crtc) {
12264 DRM_ERROR("no such CRTC id\n");
12265 return -ENOENT;
12266 }
12267
12268 crtc = to_intel_crtc(drmmode_crtc);
12269 pipe_from_crtc_id->pipe = crtc->pipe;
12270
12271 return 0;
12272 }
12273
12274 static int intel_encoder_clones(struct intel_encoder *encoder)
12275 {
12276 struct drm_device *dev = encoder->base.dev;
12277 struct intel_encoder *source_encoder;
12278 int index_mask = 0;
12279 int entry = 0;
12280
12281 for_each_intel_encoder(dev, source_encoder) {
12282 if (encoders_cloneable(encoder, source_encoder))
12283 index_mask |= (1 << entry);
12284
12285 entry++;
12286 }
12287
12288 return index_mask;
12289 }
12290
12291 static bool has_edp_a(struct drm_device *dev)
12292 {
12293 struct drm_i915_private *dev_priv = dev->dev_private;
12294
12295 if (!IS_MOBILE(dev))
12296 return false;
12297
12298 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12299 return false;
12300
12301 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12302 return false;
12303
12304 return true;
12305 }
12306
12307 const char *intel_output_name(int output)
12308 {
12309 static const char *names[] = {
12310 [INTEL_OUTPUT_UNUSED] = "Unused",
12311 [INTEL_OUTPUT_ANALOG] = "Analog",
12312 [INTEL_OUTPUT_DVO] = "DVO",
12313 [INTEL_OUTPUT_SDVO] = "SDVO",
12314 [INTEL_OUTPUT_LVDS] = "LVDS",
12315 [INTEL_OUTPUT_TVOUT] = "TV",
12316 [INTEL_OUTPUT_HDMI] = "HDMI",
12317 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12318 [INTEL_OUTPUT_EDP] = "eDP",
12319 [INTEL_OUTPUT_DSI] = "DSI",
12320 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12321 };
12322
12323 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12324 return "Invalid";
12325
12326 return names[output];
12327 }
12328
12329 static bool intel_crt_present(struct drm_device *dev)
12330 {
12331 struct drm_i915_private *dev_priv = dev->dev_private;
12332
12333 if (INTEL_INFO(dev)->gen >= 9)
12334 return false;
12335
12336 if (IS_ULT(dev))
12337 return false;
12338
12339 if (IS_CHERRYVIEW(dev))
12340 return false;
12341
12342 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12343 return false;
12344
12345 return true;
12346 }
12347
12348 static void intel_setup_outputs(struct drm_device *dev)
12349 {
12350 struct drm_i915_private *dev_priv = dev->dev_private;
12351 struct intel_encoder *encoder;
12352 bool dpd_is_edp = false;
12353
12354 intel_lvds_init(dev);
12355
12356 if (intel_crt_present(dev))
12357 intel_crt_init(dev);
12358
12359 if (HAS_DDI(dev)) {
12360 int found;
12361
12362 /* Haswell uses DDI functions to detect digital outputs */
12363 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12364 /* DDI A only supports eDP */
12365 if (found)
12366 intel_ddi_init(dev, PORT_A);
12367
12368 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12369 * register */
12370 found = I915_READ(SFUSE_STRAP);
12371
12372 if (found & SFUSE_STRAP_DDIB_DETECTED)
12373 intel_ddi_init(dev, PORT_B);
12374 if (found & SFUSE_STRAP_DDIC_DETECTED)
12375 intel_ddi_init(dev, PORT_C);
12376 if (found & SFUSE_STRAP_DDID_DETECTED)
12377 intel_ddi_init(dev, PORT_D);
12378 } else if (HAS_PCH_SPLIT(dev)) {
12379 int found;
12380 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12381
12382 if (has_edp_a(dev))
12383 intel_dp_init(dev, DP_A, PORT_A);
12384
12385 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12386 /* PCH SDVOB multiplex with HDMIB */
12387 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12388 if (!found)
12389 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12390 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12391 intel_dp_init(dev, PCH_DP_B, PORT_B);
12392 }
12393
12394 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12395 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12396
12397 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12398 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12399
12400 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12401 intel_dp_init(dev, PCH_DP_C, PORT_C);
12402
12403 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12404 intel_dp_init(dev, PCH_DP_D, PORT_D);
12405 } else if (IS_VALLEYVIEW(dev)) {
12406 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12407 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12408 PORT_B);
12409 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12410 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12411 }
12412
12413 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12414 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12415 PORT_C);
12416 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12417 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12418 }
12419
12420 if (IS_CHERRYVIEW(dev)) {
12421 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12422 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12423 PORT_D);
12424 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12425 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12426 }
12427 }
12428
12429 intel_dsi_init(dev);
12430 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12431 bool found = false;
12432
12433 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12434 DRM_DEBUG_KMS("probing SDVOB\n");
12435 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12436 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12437 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12438 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12439 }
12440
12441 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12442 intel_dp_init(dev, DP_B, PORT_B);
12443 }
12444
12445 /* Before G4X SDVOC doesn't have its own detect register */
12446
12447 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12448 DRM_DEBUG_KMS("probing SDVOC\n");
12449 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12450 }
12451
12452 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12453
12454 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12455 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12456 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12457 }
12458 if (SUPPORTS_INTEGRATED_DP(dev))
12459 intel_dp_init(dev, DP_C, PORT_C);
12460 }
12461
12462 if (SUPPORTS_INTEGRATED_DP(dev) &&
12463 (I915_READ(DP_D) & DP_DETECTED))
12464 intel_dp_init(dev, DP_D, PORT_D);
12465 } else if (IS_GEN2(dev))
12466 intel_dvo_init(dev);
12467
12468 if (SUPPORTS_TV(dev))
12469 intel_tv_init(dev);
12470
12471 intel_edp_psr_init(dev);
12472
12473 for_each_intel_encoder(dev, encoder) {
12474 encoder->base.possible_crtcs = encoder->crtc_mask;
12475 encoder->base.possible_clones =
12476 intel_encoder_clones(encoder);
12477 }
12478
12479 intel_init_pch_refclk(dev);
12480
12481 drm_helper_move_panel_connectors_to_head(dev);
12482 }
12483
12484 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12485 {
12486 struct drm_device *dev = fb->dev;
12487 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12488
12489 drm_framebuffer_cleanup(fb);
12490 mutex_lock(&dev->struct_mutex);
12491 WARN_ON(!intel_fb->obj->framebuffer_references--);
12492 drm_gem_object_unreference(&intel_fb->obj->base);
12493 mutex_unlock(&dev->struct_mutex);
12494 kfree(intel_fb);
12495 }
12496
12497 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12498 struct drm_file *file,
12499 unsigned int *handle)
12500 {
12501 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12502 struct drm_i915_gem_object *obj = intel_fb->obj;
12503
12504 return drm_gem_handle_create(file, &obj->base, handle);
12505 }
12506
12507 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12508 .destroy = intel_user_framebuffer_destroy,
12509 .create_handle = intel_user_framebuffer_create_handle,
12510 };
12511
12512 static int intel_framebuffer_init(struct drm_device *dev,
12513 struct intel_framebuffer *intel_fb,
12514 struct drm_mode_fb_cmd2 *mode_cmd,
12515 struct drm_i915_gem_object *obj)
12516 {
12517 int aligned_height;
12518 int pitch_limit;
12519 int ret;
12520
12521 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12522
12523 if (obj->tiling_mode == I915_TILING_Y) {
12524 DRM_DEBUG("hardware does not support tiling Y\n");
12525 return -EINVAL;
12526 }
12527
12528 if (mode_cmd->pitches[0] & 63) {
12529 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12530 mode_cmd->pitches[0]);
12531 return -EINVAL;
12532 }
12533
12534 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12535 pitch_limit = 32*1024;
12536 } else if (INTEL_INFO(dev)->gen >= 4) {
12537 if (obj->tiling_mode)
12538 pitch_limit = 16*1024;
12539 else
12540 pitch_limit = 32*1024;
12541 } else if (INTEL_INFO(dev)->gen >= 3) {
12542 if (obj->tiling_mode)
12543 pitch_limit = 8*1024;
12544 else
12545 pitch_limit = 16*1024;
12546 } else
12547 /* XXX DSPC is limited to 4k tiled */
12548 pitch_limit = 8*1024;
12549
12550 if (mode_cmd->pitches[0] > pitch_limit) {
12551 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12552 obj->tiling_mode ? "tiled" : "linear",
12553 mode_cmd->pitches[0], pitch_limit);
12554 return -EINVAL;
12555 }
12556
12557 if (obj->tiling_mode != I915_TILING_NONE &&
12558 mode_cmd->pitches[0] != obj->stride) {
12559 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12560 mode_cmd->pitches[0], obj->stride);
12561 return -EINVAL;
12562 }
12563
12564 /* Reject formats not supported by any plane early. */
12565 switch (mode_cmd->pixel_format) {
12566 case DRM_FORMAT_C8:
12567 case DRM_FORMAT_RGB565:
12568 case DRM_FORMAT_XRGB8888:
12569 case DRM_FORMAT_ARGB8888:
12570 break;
12571 case DRM_FORMAT_XRGB1555:
12572 case DRM_FORMAT_ARGB1555:
12573 if (INTEL_INFO(dev)->gen > 3) {
12574 DRM_DEBUG("unsupported pixel format: %s\n",
12575 drm_get_format_name(mode_cmd->pixel_format));
12576 return -EINVAL;
12577 }
12578 break;
12579 case DRM_FORMAT_XBGR8888:
12580 case DRM_FORMAT_ABGR8888:
12581 case DRM_FORMAT_XRGB2101010:
12582 case DRM_FORMAT_ARGB2101010:
12583 case DRM_FORMAT_XBGR2101010:
12584 case DRM_FORMAT_ABGR2101010:
12585 if (INTEL_INFO(dev)->gen < 4) {
12586 DRM_DEBUG("unsupported pixel format: %s\n",
12587 drm_get_format_name(mode_cmd->pixel_format));
12588 return -EINVAL;
12589 }
12590 break;
12591 case DRM_FORMAT_YUYV:
12592 case DRM_FORMAT_UYVY:
12593 case DRM_FORMAT_YVYU:
12594 case DRM_FORMAT_VYUY:
12595 if (INTEL_INFO(dev)->gen < 5) {
12596 DRM_DEBUG("unsupported pixel format: %s\n",
12597 drm_get_format_name(mode_cmd->pixel_format));
12598 return -EINVAL;
12599 }
12600 break;
12601 default:
12602 DRM_DEBUG("unsupported pixel format: %s\n",
12603 drm_get_format_name(mode_cmd->pixel_format));
12604 return -EINVAL;
12605 }
12606
12607 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12608 if (mode_cmd->offsets[0] != 0)
12609 return -EINVAL;
12610
12611 aligned_height = intel_align_height(dev, mode_cmd->height,
12612 obj->tiling_mode);
12613 /* FIXME drm helper for size checks (especially planar formats)? */
12614 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12615 return -EINVAL;
12616
12617 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12618 intel_fb->obj = obj;
12619 intel_fb->obj->framebuffer_references++;
12620
12621 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12622 if (ret) {
12623 DRM_ERROR("framebuffer init failed %d\n", ret);
12624 return ret;
12625 }
12626
12627 return 0;
12628 }
12629
12630 static struct drm_framebuffer *
12631 intel_user_framebuffer_create(struct drm_device *dev,
12632 struct drm_file *filp,
12633 struct drm_mode_fb_cmd2 *mode_cmd)
12634 {
12635 struct drm_i915_gem_object *obj;
12636
12637 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12638 mode_cmd->handles[0]));
12639 if (&obj->base == NULL)
12640 return ERR_PTR(-ENOENT);
12641
12642 return intel_framebuffer_create(dev, mode_cmd, obj);
12643 }
12644
12645 #ifndef CONFIG_DRM_I915_FBDEV
12646 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12647 {
12648 }
12649 #endif
12650
12651 static const struct drm_mode_config_funcs intel_mode_funcs = {
12652 .fb_create = intel_user_framebuffer_create,
12653 .output_poll_changed = intel_fbdev_output_poll_changed,
12654 };
12655
12656 /* Set up chip specific display functions */
12657 static void intel_init_display(struct drm_device *dev)
12658 {
12659 struct drm_i915_private *dev_priv = dev->dev_private;
12660
12661 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12662 dev_priv->display.find_dpll = g4x_find_best_dpll;
12663 else if (IS_CHERRYVIEW(dev))
12664 dev_priv->display.find_dpll = chv_find_best_dpll;
12665 else if (IS_VALLEYVIEW(dev))
12666 dev_priv->display.find_dpll = vlv_find_best_dpll;
12667 else if (IS_PINEVIEW(dev))
12668 dev_priv->display.find_dpll = pnv_find_best_dpll;
12669 else
12670 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12671
12672 if (HAS_DDI(dev)) {
12673 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12674 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12675 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12676 dev_priv->display.crtc_enable = haswell_crtc_enable;
12677 dev_priv->display.crtc_disable = haswell_crtc_disable;
12678 dev_priv->display.off = ironlake_crtc_off;
12679 if (INTEL_INFO(dev)->gen >= 9)
12680 dev_priv->display.update_primary_plane =
12681 skylake_update_primary_plane;
12682 else
12683 dev_priv->display.update_primary_plane =
12684 ironlake_update_primary_plane;
12685 } else if (HAS_PCH_SPLIT(dev)) {
12686 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12687 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12688 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12689 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12690 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12691 dev_priv->display.off = ironlake_crtc_off;
12692 dev_priv->display.update_primary_plane =
12693 ironlake_update_primary_plane;
12694 } else if (IS_VALLEYVIEW(dev)) {
12695 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12696 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12697 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12698 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12699 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12700 dev_priv->display.off = i9xx_crtc_off;
12701 dev_priv->display.update_primary_plane =
12702 i9xx_update_primary_plane;
12703 } else {
12704 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12705 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12706 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12707 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12708 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12709 dev_priv->display.off = i9xx_crtc_off;
12710 dev_priv->display.update_primary_plane =
12711 i9xx_update_primary_plane;
12712 }
12713
12714 /* Returns the core display clock speed */
12715 if (IS_VALLEYVIEW(dev))
12716 dev_priv->display.get_display_clock_speed =
12717 valleyview_get_display_clock_speed;
12718 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12719 dev_priv->display.get_display_clock_speed =
12720 i945_get_display_clock_speed;
12721 else if (IS_I915G(dev))
12722 dev_priv->display.get_display_clock_speed =
12723 i915_get_display_clock_speed;
12724 else if (IS_I945GM(dev) || IS_845G(dev))
12725 dev_priv->display.get_display_clock_speed =
12726 i9xx_misc_get_display_clock_speed;
12727 else if (IS_PINEVIEW(dev))
12728 dev_priv->display.get_display_clock_speed =
12729 pnv_get_display_clock_speed;
12730 else if (IS_I915GM(dev))
12731 dev_priv->display.get_display_clock_speed =
12732 i915gm_get_display_clock_speed;
12733 else if (IS_I865G(dev))
12734 dev_priv->display.get_display_clock_speed =
12735 i865_get_display_clock_speed;
12736 else if (IS_I85X(dev))
12737 dev_priv->display.get_display_clock_speed =
12738 i855_get_display_clock_speed;
12739 else /* 852, 830 */
12740 dev_priv->display.get_display_clock_speed =
12741 i830_get_display_clock_speed;
12742
12743 if (IS_G4X(dev)) {
12744 dev_priv->display.write_eld = g4x_write_eld;
12745 } else if (IS_GEN5(dev)) {
12746 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12747 dev_priv->display.write_eld = ironlake_write_eld;
12748 } else if (IS_GEN6(dev)) {
12749 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12750 dev_priv->display.write_eld = ironlake_write_eld;
12751 dev_priv->display.modeset_global_resources =
12752 snb_modeset_global_resources;
12753 } else if (IS_IVYBRIDGE(dev)) {
12754 /* FIXME: detect B0+ stepping and use auto training */
12755 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12756 dev_priv->display.write_eld = ironlake_write_eld;
12757 dev_priv->display.modeset_global_resources =
12758 ivb_modeset_global_resources;
12759 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12760 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12761 dev_priv->display.write_eld = haswell_write_eld;
12762 dev_priv->display.modeset_global_resources =
12763 haswell_modeset_global_resources;
12764 } else if (IS_VALLEYVIEW(dev)) {
12765 dev_priv->display.modeset_global_resources =
12766 valleyview_modeset_global_resources;
12767 dev_priv->display.write_eld = ironlake_write_eld;
12768 } else if (INTEL_INFO(dev)->gen >= 9) {
12769 dev_priv->display.write_eld = haswell_write_eld;
12770 dev_priv->display.modeset_global_resources =
12771 haswell_modeset_global_resources;
12772 }
12773
12774 /* Default just returns -ENODEV to indicate unsupported */
12775 dev_priv->display.queue_flip = intel_default_queue_flip;
12776
12777 switch (INTEL_INFO(dev)->gen) {
12778 case 2:
12779 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12780 break;
12781
12782 case 3:
12783 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12784 break;
12785
12786 case 4:
12787 case 5:
12788 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12789 break;
12790
12791 case 6:
12792 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12793 break;
12794 case 7:
12795 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12796 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12797 break;
12798 }
12799
12800 intel_panel_init_backlight_funcs(dev);
12801
12802 mutex_init(&dev_priv->pps_mutex);
12803 }
12804
12805 /*
12806 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12807 * resume, or other times. This quirk makes sure that's the case for
12808 * affected systems.
12809 */
12810 static void quirk_pipea_force(struct drm_device *dev)
12811 {
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12813
12814 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12815 DRM_INFO("applying pipe a force quirk\n");
12816 }
12817
12818 static void quirk_pipeb_force(struct drm_device *dev)
12819 {
12820 struct drm_i915_private *dev_priv = dev->dev_private;
12821
12822 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12823 DRM_INFO("applying pipe b force quirk\n");
12824 }
12825
12826 /*
12827 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12828 */
12829 static void quirk_ssc_force_disable(struct drm_device *dev)
12830 {
12831 struct drm_i915_private *dev_priv = dev->dev_private;
12832 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12833 DRM_INFO("applying lvds SSC disable quirk\n");
12834 }
12835
12836 /*
12837 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12838 * brightness value
12839 */
12840 static void quirk_invert_brightness(struct drm_device *dev)
12841 {
12842 struct drm_i915_private *dev_priv = dev->dev_private;
12843 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12844 DRM_INFO("applying inverted panel brightness quirk\n");
12845 }
12846
12847 /* Some VBT's incorrectly indicate no backlight is present */
12848 static void quirk_backlight_present(struct drm_device *dev)
12849 {
12850 struct drm_i915_private *dev_priv = dev->dev_private;
12851 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12852 DRM_INFO("applying backlight present quirk\n");
12853 }
12854
12855 struct intel_quirk {
12856 int device;
12857 int subsystem_vendor;
12858 int subsystem_device;
12859 void (*hook)(struct drm_device *dev);
12860 };
12861
12862 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12863 struct intel_dmi_quirk {
12864 void (*hook)(struct drm_device *dev);
12865 const struct dmi_system_id (*dmi_id_list)[];
12866 };
12867
12868 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12869 {
12870 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12871 return 1;
12872 }
12873
12874 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12875 {
12876 .dmi_id_list = &(const struct dmi_system_id[]) {
12877 {
12878 .callback = intel_dmi_reverse_brightness,
12879 .ident = "NCR Corporation",
12880 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12881 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12882 },
12883 },
12884 { } /* terminating entry */
12885 },
12886 .hook = quirk_invert_brightness,
12887 },
12888 };
12889
12890 static struct intel_quirk intel_quirks[] = {
12891 /* HP Mini needs pipe A force quirk (LP: #322104) */
12892 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12893
12894 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12895 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12896
12897 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12898 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12899
12900 /* 830 needs to leave pipe A & dpll A up */
12901 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12902
12903 /* 830 needs to leave pipe B & dpll B up */
12904 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12905
12906 /* Lenovo U160 cannot use SSC on LVDS */
12907 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12908
12909 /* Sony Vaio Y cannot use SSC on LVDS */
12910 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12911
12912 /* Acer Aspire 5734Z must invert backlight brightness */
12913 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12914
12915 /* Acer/eMachines G725 */
12916 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12917
12918 /* Acer/eMachines e725 */
12919 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12920
12921 /* Acer/Packard Bell NCL20 */
12922 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12923
12924 /* Acer Aspire 4736Z */
12925 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12926
12927 /* Acer Aspire 5336 */
12928 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12929
12930 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12931 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12932
12933 /* Acer C720 Chromebook (Core i3 4005U) */
12934 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12935
12936 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12937 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12938
12939 /* HP Chromebook 14 (Celeron 2955U) */
12940 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12941 };
12942
12943 static void intel_init_quirks(struct drm_device *dev)
12944 {
12945 struct pci_dev *d = dev->pdev;
12946 int i;
12947
12948 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12949 struct intel_quirk *q = &intel_quirks[i];
12950
12951 if (d->device == q->device &&
12952 (d->subsystem_vendor == q->subsystem_vendor ||
12953 q->subsystem_vendor == PCI_ANY_ID) &&
12954 (d->subsystem_device == q->subsystem_device ||
12955 q->subsystem_device == PCI_ANY_ID))
12956 q->hook(dev);
12957 }
12958 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12959 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12960 intel_dmi_quirks[i].hook(dev);
12961 }
12962 }
12963
12964 /* Disable the VGA plane that we never use */
12965 static void i915_disable_vga(struct drm_device *dev)
12966 {
12967 struct drm_i915_private *dev_priv = dev->dev_private;
12968 u8 sr1;
12969 u32 vga_reg = i915_vgacntrl_reg(dev);
12970
12971 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12972 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12973 outb(SR01, VGA_SR_INDEX);
12974 sr1 = inb(VGA_SR_DATA);
12975 outb(sr1 | 1<<5, VGA_SR_DATA);
12976 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12977 udelay(300);
12978
12979 /*
12980 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12981 * from S3 without preserving (some of?) the other bits.
12982 */
12983 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12984 POSTING_READ(vga_reg);
12985 }
12986
12987 void intel_modeset_init_hw(struct drm_device *dev)
12988 {
12989 intel_prepare_ddi(dev);
12990
12991 if (IS_VALLEYVIEW(dev))
12992 vlv_update_cdclk(dev);
12993
12994 intel_init_clock_gating(dev);
12995
12996 intel_enable_gt_powersave(dev);
12997 }
12998
12999 void intel_modeset_suspend_hw(struct drm_device *dev)
13000 {
13001 intel_suspend_hw(dev);
13002 }
13003
13004 void intel_modeset_init(struct drm_device *dev)
13005 {
13006 struct drm_i915_private *dev_priv = dev->dev_private;
13007 int sprite, ret;
13008 enum pipe pipe;
13009 struct intel_crtc *crtc;
13010
13011 drm_mode_config_init(dev);
13012
13013 dev->mode_config.min_width = 0;
13014 dev->mode_config.min_height = 0;
13015
13016 dev->mode_config.preferred_depth = 24;
13017 dev->mode_config.prefer_shadow = 1;
13018
13019 dev->mode_config.funcs = &intel_mode_funcs;
13020
13021 intel_init_quirks(dev);
13022
13023 intel_init_pm(dev);
13024
13025 if (INTEL_INFO(dev)->num_pipes == 0)
13026 return;
13027
13028 intel_init_display(dev);
13029
13030 if (IS_GEN2(dev)) {
13031 dev->mode_config.max_width = 2048;
13032 dev->mode_config.max_height = 2048;
13033 } else if (IS_GEN3(dev)) {
13034 dev->mode_config.max_width = 4096;
13035 dev->mode_config.max_height = 4096;
13036 } else {
13037 dev->mode_config.max_width = 8192;
13038 dev->mode_config.max_height = 8192;
13039 }
13040
13041 if (IS_845G(dev) || IS_I865G(dev)) {
13042 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13043 dev->mode_config.cursor_height = 1023;
13044 } else if (IS_GEN2(dev)) {
13045 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13046 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13047 } else {
13048 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13049 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13050 }
13051
13052 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13053
13054 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13055 INTEL_INFO(dev)->num_pipes,
13056 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13057
13058 for_each_pipe(dev_priv, pipe) {
13059 intel_crtc_init(dev, pipe);
13060 for_each_sprite(pipe, sprite) {
13061 ret = intel_plane_init(dev, pipe, sprite);
13062 if (ret)
13063 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13064 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13065 }
13066 }
13067
13068 intel_init_dpio(dev);
13069
13070 intel_shared_dpll_init(dev);
13071
13072 /* save the BIOS value before clobbering it */
13073 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13074 /* Just disable it once at startup */
13075 i915_disable_vga(dev);
13076 intel_setup_outputs(dev);
13077
13078 /* Just in case the BIOS is doing something questionable. */
13079 intel_disable_fbc(dev);
13080
13081 drm_modeset_lock_all(dev);
13082 intel_modeset_setup_hw_state(dev, false);
13083 drm_modeset_unlock_all(dev);
13084
13085 for_each_intel_crtc(dev, crtc) {
13086 if (!crtc->active)
13087 continue;
13088
13089 /*
13090 * Note that reserving the BIOS fb up front prevents us
13091 * from stuffing other stolen allocations like the ring
13092 * on top. This prevents some ugliness at boot time, and
13093 * can even allow for smooth boot transitions if the BIOS
13094 * fb is large enough for the active pipe configuration.
13095 */
13096 if (dev_priv->display.get_plane_config) {
13097 dev_priv->display.get_plane_config(crtc,
13098 &crtc->plane_config);
13099 /*
13100 * If the fb is shared between multiple heads, we'll
13101 * just get the first one.
13102 */
13103 intel_find_plane_obj(crtc, &crtc->plane_config);
13104 }
13105 }
13106 }
13107
13108 static void intel_enable_pipe_a(struct drm_device *dev)
13109 {
13110 struct intel_connector *connector;
13111 struct drm_connector *crt = NULL;
13112 struct intel_load_detect_pipe load_detect_temp;
13113 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13114
13115 /* We can't just switch on the pipe A, we need to set things up with a
13116 * proper mode and output configuration. As a gross hack, enable pipe A
13117 * by enabling the load detect pipe once. */
13118 list_for_each_entry(connector,
13119 &dev->mode_config.connector_list,
13120 base.head) {
13121 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13122 crt = &connector->base;
13123 break;
13124 }
13125 }
13126
13127 if (!crt)
13128 return;
13129
13130 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13131 intel_release_load_detect_pipe(crt, &load_detect_temp);
13132 }
13133
13134 static bool
13135 intel_check_plane_mapping(struct intel_crtc *crtc)
13136 {
13137 struct drm_device *dev = crtc->base.dev;
13138 struct drm_i915_private *dev_priv = dev->dev_private;
13139 u32 reg, val;
13140
13141 if (INTEL_INFO(dev)->num_pipes == 1)
13142 return true;
13143
13144 reg = DSPCNTR(!crtc->plane);
13145 val = I915_READ(reg);
13146
13147 if ((val & DISPLAY_PLANE_ENABLE) &&
13148 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13149 return false;
13150
13151 return true;
13152 }
13153
13154 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13155 {
13156 struct drm_device *dev = crtc->base.dev;
13157 struct drm_i915_private *dev_priv = dev->dev_private;
13158 u32 reg;
13159
13160 /* Clear any frame start delays used for debugging left by the BIOS */
13161 reg = PIPECONF(crtc->config.cpu_transcoder);
13162 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13163
13164 /* restore vblank interrupts to correct state */
13165 if (crtc->active) {
13166 update_scanline_offset(crtc);
13167 drm_vblank_on(dev, crtc->pipe);
13168 } else
13169 drm_vblank_off(dev, crtc->pipe);
13170
13171 /* We need to sanitize the plane -> pipe mapping first because this will
13172 * disable the crtc (and hence change the state) if it is wrong. Note
13173 * that gen4+ has a fixed plane -> pipe mapping. */
13174 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13175 struct intel_connector *connector;
13176 bool plane;
13177
13178 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13179 crtc->base.base.id);
13180
13181 /* Pipe has the wrong plane attached and the plane is active.
13182 * Temporarily change the plane mapping and disable everything
13183 * ... */
13184 plane = crtc->plane;
13185 crtc->plane = !plane;
13186 crtc->primary_enabled = true;
13187 dev_priv->display.crtc_disable(&crtc->base);
13188 crtc->plane = plane;
13189
13190 /* ... and break all links. */
13191 list_for_each_entry(connector, &dev->mode_config.connector_list,
13192 base.head) {
13193 if (connector->encoder->base.crtc != &crtc->base)
13194 continue;
13195
13196 connector->base.dpms = DRM_MODE_DPMS_OFF;
13197 connector->base.encoder = NULL;
13198 }
13199 /* multiple connectors may have the same encoder:
13200 * handle them and break crtc link separately */
13201 list_for_each_entry(connector, &dev->mode_config.connector_list,
13202 base.head)
13203 if (connector->encoder->base.crtc == &crtc->base) {
13204 connector->encoder->base.crtc = NULL;
13205 connector->encoder->connectors_active = false;
13206 }
13207
13208 WARN_ON(crtc->active);
13209 crtc->base.enabled = false;
13210 }
13211
13212 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13213 crtc->pipe == PIPE_A && !crtc->active) {
13214 /* BIOS forgot to enable pipe A, this mostly happens after
13215 * resume. Force-enable the pipe to fix this, the update_dpms
13216 * call below we restore the pipe to the right state, but leave
13217 * the required bits on. */
13218 intel_enable_pipe_a(dev);
13219 }
13220
13221 /* Adjust the state of the output pipe according to whether we
13222 * have active connectors/encoders. */
13223 intel_crtc_update_dpms(&crtc->base);
13224
13225 if (crtc->active != crtc->base.enabled) {
13226 struct intel_encoder *encoder;
13227
13228 /* This can happen either due to bugs in the get_hw_state
13229 * functions or because the pipe is force-enabled due to the
13230 * pipe A quirk. */
13231 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13232 crtc->base.base.id,
13233 crtc->base.enabled ? "enabled" : "disabled",
13234 crtc->active ? "enabled" : "disabled");
13235
13236 crtc->base.enabled = crtc->active;
13237
13238 /* Because we only establish the connector -> encoder ->
13239 * crtc links if something is active, this means the
13240 * crtc is now deactivated. Break the links. connector
13241 * -> encoder links are only establish when things are
13242 * actually up, hence no need to break them. */
13243 WARN_ON(crtc->active);
13244
13245 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13246 WARN_ON(encoder->connectors_active);
13247 encoder->base.crtc = NULL;
13248 }
13249 }
13250
13251 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13252 /*
13253 * We start out with underrun reporting disabled to avoid races.
13254 * For correct bookkeeping mark this on active crtcs.
13255 *
13256 * Also on gmch platforms we dont have any hardware bits to
13257 * disable the underrun reporting. Which means we need to start
13258 * out with underrun reporting disabled also on inactive pipes,
13259 * since otherwise we'll complain about the garbage we read when
13260 * e.g. coming up after runtime pm.
13261 *
13262 * No protection against concurrent access is required - at
13263 * worst a fifo underrun happens which also sets this to false.
13264 */
13265 crtc->cpu_fifo_underrun_disabled = true;
13266 crtc->pch_fifo_underrun_disabled = true;
13267 }
13268 }
13269
13270 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13271 {
13272 struct intel_connector *connector;
13273 struct drm_device *dev = encoder->base.dev;
13274
13275 /* We need to check both for a crtc link (meaning that the
13276 * encoder is active and trying to read from a pipe) and the
13277 * pipe itself being active. */
13278 bool has_active_crtc = encoder->base.crtc &&
13279 to_intel_crtc(encoder->base.crtc)->active;
13280
13281 if (encoder->connectors_active && !has_active_crtc) {
13282 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13283 encoder->base.base.id,
13284 encoder->base.name);
13285
13286 /* Connector is active, but has no active pipe. This is
13287 * fallout from our resume register restoring. Disable
13288 * the encoder manually again. */
13289 if (encoder->base.crtc) {
13290 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13291 encoder->base.base.id,
13292 encoder->base.name);
13293 encoder->disable(encoder);
13294 if (encoder->post_disable)
13295 encoder->post_disable(encoder);
13296 }
13297 encoder->base.crtc = NULL;
13298 encoder->connectors_active = false;
13299
13300 /* Inconsistent output/port/pipe state happens presumably due to
13301 * a bug in one of the get_hw_state functions. Or someplace else
13302 * in our code, like the register restore mess on resume. Clamp
13303 * things to off as a safer default. */
13304 list_for_each_entry(connector,
13305 &dev->mode_config.connector_list,
13306 base.head) {
13307 if (connector->encoder != encoder)
13308 continue;
13309 connector->base.dpms = DRM_MODE_DPMS_OFF;
13310 connector->base.encoder = NULL;
13311 }
13312 }
13313 /* Enabled encoders without active connectors will be fixed in
13314 * the crtc fixup. */
13315 }
13316
13317 void i915_redisable_vga_power_on(struct drm_device *dev)
13318 {
13319 struct drm_i915_private *dev_priv = dev->dev_private;
13320 u32 vga_reg = i915_vgacntrl_reg(dev);
13321
13322 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13323 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13324 i915_disable_vga(dev);
13325 }
13326 }
13327
13328 void i915_redisable_vga(struct drm_device *dev)
13329 {
13330 struct drm_i915_private *dev_priv = dev->dev_private;
13331
13332 /* This function can be called both from intel_modeset_setup_hw_state or
13333 * at a very early point in our resume sequence, where the power well
13334 * structures are not yet restored. Since this function is at a very
13335 * paranoid "someone might have enabled VGA while we were not looking"
13336 * level, just check if the power well is enabled instead of trying to
13337 * follow the "don't touch the power well if we don't need it" policy
13338 * the rest of the driver uses. */
13339 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13340 return;
13341
13342 i915_redisable_vga_power_on(dev);
13343 }
13344
13345 static bool primary_get_hw_state(struct intel_crtc *crtc)
13346 {
13347 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13348
13349 if (!crtc->active)
13350 return false;
13351
13352 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13353 }
13354
13355 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13356 {
13357 struct drm_i915_private *dev_priv = dev->dev_private;
13358 enum pipe pipe;
13359 struct intel_crtc *crtc;
13360 struct intel_encoder *encoder;
13361 struct intel_connector *connector;
13362 int i;
13363
13364 for_each_intel_crtc(dev, crtc) {
13365 memset(&crtc->config, 0, sizeof(crtc->config));
13366
13367 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13368
13369 crtc->active = dev_priv->display.get_pipe_config(crtc,
13370 &crtc->config);
13371
13372 crtc->base.enabled = crtc->active;
13373 crtc->primary_enabled = primary_get_hw_state(crtc);
13374
13375 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13376 crtc->base.base.id,
13377 crtc->active ? "enabled" : "disabled");
13378 }
13379
13380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13381 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13382
13383 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13384 pll->active = 0;
13385 for_each_intel_crtc(dev, crtc) {
13386 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13387 pll->active++;
13388 }
13389 pll->refcount = pll->active;
13390
13391 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13392 pll->name, pll->refcount, pll->on);
13393
13394 if (pll->refcount)
13395 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13396 }
13397
13398 for_each_intel_encoder(dev, encoder) {
13399 pipe = 0;
13400
13401 if (encoder->get_hw_state(encoder, &pipe)) {
13402 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13403 encoder->base.crtc = &crtc->base;
13404 encoder->get_config(encoder, &crtc->config);
13405 } else {
13406 encoder->base.crtc = NULL;
13407 }
13408
13409 encoder->connectors_active = false;
13410 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13411 encoder->base.base.id,
13412 encoder->base.name,
13413 encoder->base.crtc ? "enabled" : "disabled",
13414 pipe_name(pipe));
13415 }
13416
13417 list_for_each_entry(connector, &dev->mode_config.connector_list,
13418 base.head) {
13419 if (connector->get_hw_state(connector)) {
13420 connector->base.dpms = DRM_MODE_DPMS_ON;
13421 connector->encoder->connectors_active = true;
13422 connector->base.encoder = &connector->encoder->base;
13423 } else {
13424 connector->base.dpms = DRM_MODE_DPMS_OFF;
13425 connector->base.encoder = NULL;
13426 }
13427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13428 connector->base.base.id,
13429 connector->base.name,
13430 connector->base.encoder ? "enabled" : "disabled");
13431 }
13432 }
13433
13434 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13435 * and i915 state tracking structures. */
13436 void intel_modeset_setup_hw_state(struct drm_device *dev,
13437 bool force_restore)
13438 {
13439 struct drm_i915_private *dev_priv = dev->dev_private;
13440 enum pipe pipe;
13441 struct intel_crtc *crtc;
13442 struct intel_encoder *encoder;
13443 int i;
13444
13445 intel_modeset_readout_hw_state(dev);
13446
13447 /*
13448 * Now that we have the config, copy it to each CRTC struct
13449 * Note that this could go away if we move to using crtc_config
13450 * checking everywhere.
13451 */
13452 for_each_intel_crtc(dev, crtc) {
13453 if (crtc->active && i915.fastboot) {
13454 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13455 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13456 crtc->base.base.id);
13457 drm_mode_debug_printmodeline(&crtc->base.mode);
13458 }
13459 }
13460
13461 /* HW state is read out, now we need to sanitize this mess. */
13462 for_each_intel_encoder(dev, encoder) {
13463 intel_sanitize_encoder(encoder);
13464 }
13465
13466 for_each_pipe(dev_priv, pipe) {
13467 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13468 intel_sanitize_crtc(crtc);
13469 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13470 }
13471
13472 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13473 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13474
13475 if (!pll->on || pll->active)
13476 continue;
13477
13478 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13479
13480 pll->disable(dev_priv, pll);
13481 pll->on = false;
13482 }
13483
13484 if (HAS_PCH_SPLIT(dev))
13485 ilk_wm_get_hw_state(dev);
13486
13487 if (force_restore) {
13488 i915_redisable_vga(dev);
13489
13490 /*
13491 * We need to use raw interfaces for restoring state to avoid
13492 * checking (bogus) intermediate states.
13493 */
13494 for_each_pipe(dev_priv, pipe) {
13495 struct drm_crtc *crtc =
13496 dev_priv->pipe_to_crtc_mapping[pipe];
13497
13498 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13499 crtc->primary->fb);
13500 }
13501 } else {
13502 intel_modeset_update_staged_output_state(dev);
13503 }
13504
13505 intel_modeset_check_state(dev);
13506 }
13507
13508 void intel_modeset_gem_init(struct drm_device *dev)
13509 {
13510 struct drm_crtc *c;
13511 struct drm_i915_gem_object *obj;
13512
13513 mutex_lock(&dev->struct_mutex);
13514 intel_init_gt_powersave(dev);
13515 mutex_unlock(&dev->struct_mutex);
13516
13517 intel_modeset_init_hw(dev);
13518
13519 intel_setup_overlay(dev);
13520
13521 /*
13522 * Make sure any fbs we allocated at startup are properly
13523 * pinned & fenced. When we do the allocation it's too early
13524 * for this.
13525 */
13526 mutex_lock(&dev->struct_mutex);
13527 for_each_crtc(dev, c) {
13528 obj = intel_fb_obj(c->primary->fb);
13529 if (obj == NULL)
13530 continue;
13531
13532 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13533 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13534 to_intel_crtc(c)->pipe);
13535 drm_framebuffer_unreference(c->primary->fb);
13536 c->primary->fb = NULL;
13537 }
13538 }
13539 mutex_unlock(&dev->struct_mutex);
13540 }
13541
13542 void intel_connector_unregister(struct intel_connector *intel_connector)
13543 {
13544 struct drm_connector *connector = &intel_connector->base;
13545
13546 intel_panel_destroy_backlight(connector);
13547 drm_connector_unregister(connector);
13548 }
13549
13550 void intel_modeset_cleanup(struct drm_device *dev)
13551 {
13552 struct drm_i915_private *dev_priv = dev->dev_private;
13553 struct drm_connector *connector;
13554
13555 /*
13556 * Interrupts and polling as the first thing to avoid creating havoc.
13557 * Too much stuff here (turning of rps, connectors, ...) would
13558 * experience fancy races otherwise.
13559 */
13560 drm_irq_uninstall(dev);
13561 intel_hpd_cancel_work(dev_priv);
13562 dev_priv->pm._irqs_disabled = true;
13563
13564 /*
13565 * Due to the hpd irq storm handling the hotplug work can re-arm the
13566 * poll handlers. Hence disable polling after hpd handling is shut down.
13567 */
13568 drm_kms_helper_poll_fini(dev);
13569
13570 mutex_lock(&dev->struct_mutex);
13571
13572 intel_unregister_dsm_handler();
13573
13574 intel_disable_fbc(dev);
13575
13576 intel_disable_gt_powersave(dev);
13577
13578 ironlake_teardown_rc6(dev);
13579
13580 mutex_unlock(&dev->struct_mutex);
13581
13582 /* flush any delayed tasks or pending work */
13583 flush_scheduled_work();
13584
13585 /* destroy the backlight and sysfs files before encoders/connectors */
13586 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13587 struct intel_connector *intel_connector;
13588
13589 intel_connector = to_intel_connector(connector);
13590 intel_connector->unregister(intel_connector);
13591 }
13592
13593 drm_mode_config_cleanup(dev);
13594
13595 intel_cleanup_overlay(dev);
13596
13597 mutex_lock(&dev->struct_mutex);
13598 intel_cleanup_gt_powersave(dev);
13599 mutex_unlock(&dev->struct_mutex);
13600 }
13601
13602 /*
13603 * Return which encoder is currently attached for connector.
13604 */
13605 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13606 {
13607 return &intel_attached_encoder(connector)->base;
13608 }
13609
13610 void intel_connector_attach_encoder(struct intel_connector *connector,
13611 struct intel_encoder *encoder)
13612 {
13613 connector->encoder = encoder;
13614 drm_mode_connector_attach_encoder(&connector->base,
13615 &encoder->base);
13616 }
13617
13618 /*
13619 * set vga decode state - true == enable VGA decode
13620 */
13621 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13622 {
13623 struct drm_i915_private *dev_priv = dev->dev_private;
13624 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13625 u16 gmch_ctrl;
13626
13627 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13628 DRM_ERROR("failed to read control word\n");
13629 return -EIO;
13630 }
13631
13632 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13633 return 0;
13634
13635 if (state)
13636 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13637 else
13638 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13639
13640 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13641 DRM_ERROR("failed to write control word\n");
13642 return -EIO;
13643 }
13644
13645 return 0;
13646 }
13647
13648 struct intel_display_error_state {
13649
13650 u32 power_well_driver;
13651
13652 int num_transcoders;
13653
13654 struct intel_cursor_error_state {
13655 u32 control;
13656 u32 position;
13657 u32 base;
13658 u32 size;
13659 } cursor[I915_MAX_PIPES];
13660
13661 struct intel_pipe_error_state {
13662 bool power_domain_on;
13663 u32 source;
13664 u32 stat;
13665 } pipe[I915_MAX_PIPES];
13666
13667 struct intel_plane_error_state {
13668 u32 control;
13669 u32 stride;
13670 u32 size;
13671 u32 pos;
13672 u32 addr;
13673 u32 surface;
13674 u32 tile_offset;
13675 } plane[I915_MAX_PIPES];
13676
13677 struct intel_transcoder_error_state {
13678 bool power_domain_on;
13679 enum transcoder cpu_transcoder;
13680
13681 u32 conf;
13682
13683 u32 htotal;
13684 u32 hblank;
13685 u32 hsync;
13686 u32 vtotal;
13687 u32 vblank;
13688 u32 vsync;
13689 } transcoder[4];
13690 };
13691
13692 struct intel_display_error_state *
13693 intel_display_capture_error_state(struct drm_device *dev)
13694 {
13695 struct drm_i915_private *dev_priv = dev->dev_private;
13696 struct intel_display_error_state *error;
13697 int transcoders[] = {
13698 TRANSCODER_A,
13699 TRANSCODER_B,
13700 TRANSCODER_C,
13701 TRANSCODER_EDP,
13702 };
13703 int i;
13704
13705 if (INTEL_INFO(dev)->num_pipes == 0)
13706 return NULL;
13707
13708 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13709 if (error == NULL)
13710 return NULL;
13711
13712 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13713 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13714
13715 for_each_pipe(dev_priv, i) {
13716 error->pipe[i].power_domain_on =
13717 intel_display_power_enabled_unlocked(dev_priv,
13718 POWER_DOMAIN_PIPE(i));
13719 if (!error->pipe[i].power_domain_on)
13720 continue;
13721
13722 error->cursor[i].control = I915_READ(CURCNTR(i));
13723 error->cursor[i].position = I915_READ(CURPOS(i));
13724 error->cursor[i].base = I915_READ(CURBASE(i));
13725
13726 error->plane[i].control = I915_READ(DSPCNTR(i));
13727 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13728 if (INTEL_INFO(dev)->gen <= 3) {
13729 error->plane[i].size = I915_READ(DSPSIZE(i));
13730 error->plane[i].pos = I915_READ(DSPPOS(i));
13731 }
13732 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13733 error->plane[i].addr = I915_READ(DSPADDR(i));
13734 if (INTEL_INFO(dev)->gen >= 4) {
13735 error->plane[i].surface = I915_READ(DSPSURF(i));
13736 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13737 }
13738
13739 error->pipe[i].source = I915_READ(PIPESRC(i));
13740
13741 if (HAS_GMCH_DISPLAY(dev))
13742 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13743 }
13744
13745 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13746 if (HAS_DDI(dev_priv->dev))
13747 error->num_transcoders++; /* Account for eDP. */
13748
13749 for (i = 0; i < error->num_transcoders; i++) {
13750 enum transcoder cpu_transcoder = transcoders[i];
13751
13752 error->transcoder[i].power_domain_on =
13753 intel_display_power_enabled_unlocked(dev_priv,
13754 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13755 if (!error->transcoder[i].power_domain_on)
13756 continue;
13757
13758 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13759
13760 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13761 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13762 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13763 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13764 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13765 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13766 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13767 }
13768
13769 return error;
13770 }
13771
13772 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13773
13774 void
13775 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13776 struct drm_device *dev,
13777 struct intel_display_error_state *error)
13778 {
13779 struct drm_i915_private *dev_priv = dev->dev_private;
13780 int i;
13781
13782 if (!error)
13783 return;
13784
13785 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13786 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13787 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13788 error->power_well_driver);
13789 for_each_pipe(dev_priv, i) {
13790 err_printf(m, "Pipe [%d]:\n", i);
13791 err_printf(m, " Power: %s\n",
13792 error->pipe[i].power_domain_on ? "on" : "off");
13793 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13794 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13795
13796 err_printf(m, "Plane [%d]:\n", i);
13797 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13798 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13799 if (INTEL_INFO(dev)->gen <= 3) {
13800 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13801 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13802 }
13803 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13804 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13805 if (INTEL_INFO(dev)->gen >= 4) {
13806 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13807 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13808 }
13809
13810 err_printf(m, "Cursor [%d]:\n", i);
13811 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13812 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13813 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13814 }
13815
13816 for (i = 0; i < error->num_transcoders; i++) {
13817 err_printf(m, "CPU transcoder: %c\n",
13818 transcoder_name(error->transcoder[i].cpu_transcoder));
13819 err_printf(m, " Power: %s\n",
13820 error->transcoder[i].power_domain_on ? "on" : "off");
13821 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13822 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13823 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13824 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13825 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13826 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13827 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13828 }
13829 }
13830
13831 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13832 {
13833 struct intel_crtc *crtc;
13834
13835 for_each_intel_crtc(dev, crtc) {
13836 struct intel_unpin_work *work;
13837 unsigned long irqflags;
13838
13839 spin_lock_irqsave(&dev->event_lock, irqflags);
13840
13841 work = crtc->unpin_work;
13842
13843 if (work && work->event &&
13844 work->event->base.file_priv == file) {
13845 kfree(work->event);
13846 work->event = NULL;
13847 }
13848
13849 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13850 }
13851 }
Linux kernel - Deliverables
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