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drm/i915: extract modeset config save/restore code
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385 {
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1409 pipe_name(pipe));
1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe));
1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434 */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518 out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525 unsigned long flags;
1526 u32 value = 0;
1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552 }
1553
1554 /**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1566 int reg;
1567 u32 val;
1568
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
1598
1599 pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606 int reg;
1607 u32 val;
1608
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
1616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623 return;
1624 }
1625
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636 reg = pll->pll_reg;
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
1642
1643 pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648 {
1649 int reg;
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1680 }
1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699 {
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
1735 {
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778 {
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806 enum plane plane)
1807 {
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822 {
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849 {
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1865 {
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1870 }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875 {
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1881 }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 alignment;
1923 int ret;
1924
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948 if (ret)
1949 goto err_interruptible;
1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
1956 ret = i915_gem_object_get_fence(obj);
1957 if (ret)
1958 goto err_unpin;
1959
1960 i915_gem_object_pin_fence(obj);
1961
1962 dev_priv->mm.interruptible = true;
1963 return 0;
1964
1965 err_unpin:
1966 i915_gem_object_unpin(obj);
1967 err_interruptible:
1968 dev_priv->mm.interruptible = true;
1969 return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983 {
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
1996 {
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2004 u32 dspcntr;
2005 u32 reg;
2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039 return -EINVAL;
2040 }
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
2048 I915_WRITE(reg, dspcntr);
2049
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
2059 intel_crtc->dspaddr_offset = linear_offset;
2060 }
2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072 POSTING_READ(reg);
2073
2074 return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079 {
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 case 2:
2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
2147
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2155 POSTING_READ(reg);
2156
2157 return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2171
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
2205 {
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 int ret;
2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
2214 DRM_ERROR("No FB bound\n");
2215 return 0;
2216 }
2217
2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
2222 return -EINVAL;
2223 }
2224
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2228 NULL);
2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2232 return ret;
2233 }
2234
2235 if (old_fb)
2236 intel_finish_fb(old_fb);
2237
2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239 if (ret) {
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2243 return ret;
2244 }
2245
2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249 }
2250
2251 intel_update_fbc(dev);
2252 mutex_unlock(&dev->struct_mutex);
2253
2254 if (!dev->primary->master)
2255 return 0;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return 0;
2260
2261 if (intel_crtc->pipe) {
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
2305 POSTING_READ(DP_A);
2306 udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 if (IS_IVYBRIDGE(dev)) {
2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326 }
2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2371
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
2384 udelay(150);
2385
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
2402 udelay(150);
2403
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
2410
2411 reg = FDI_RX_IIR(pipe);
2412 for (tries = 0; tries < 5; tries++) {
2413 temp = I915_READ(reg);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419 break;
2420 }
2421 }
2422 if (tries == 5)
2423 DRM_ERROR("FDI train 1 fail!\n");
2424
2425 /* Train 2 */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 I915_WRITE(reg, temp);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
2439 udelay(150);
2440
2441 reg = FDI_RX_IIR(pipe);
2442 for (tries = 0; tries < 5; tries++) {
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
2451 }
2452 if (tries == 5)
2453 DRM_ERROR("FDI train 2 fail!\n");
2454
2455 DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 u32 reg, temp, i, retry;
2474
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
2484 udelay(150);
2485
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
2510 udelay(150);
2511
2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
2515 for (i = 0; i < 4; i++) {
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(500);
2524
2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
2535 }
2536 if (retry < 5)
2537 break;
2538 }
2539 if (i == 4)
2540 DRM_ERROR("FDI train 1 fail!\n");
2541
2542 /* Train 2 */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
2552 I915_WRITE(reg, temp);
2553
2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
2588 }
2589 if (retry < 5)
2590 break;
2591 }
2592 if (i == 4)
2593 DRM_ERROR("FDI train 2 fail!\n");
2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 temp |= FDI_COMPOSITE_SYNC;
2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 temp |= FDI_COMPOSITE_SYNC;
2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2713 {
2714 struct drm_device *dev = intel_crtc->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int pipe = intel_crtc->pipe;
2717 u32 reg, temp;
2718
2719 /* Write the TU size bits so error detection works */
2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2722
2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
2739 udelay(200);
2740
2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749
2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
2753 }
2754 }
2755
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757 {
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783 }
2784
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786 {
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795 }
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797 {
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
2827 }
2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852 }
2853
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->dev;
2857
2858 if (crtc->fb == NULL)
2859 return;
2860
2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
2864 }
2865
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 {
2868 struct drm_device *dev = crtc->dev;
2869 struct intel_encoder *intel_encoder;
2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2876
2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888 intel_encoder->type);
2889 return false;
2890 }
2891 }
2892
2893 switch (intel_encoder->type) {
2894 case INTEL_OUTPUT_EDP:
2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993 }
2994
2995 /*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3004 {
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
3009 u32 reg, temp;
3010
3011 assert_transcoder_disabled(dev_priv, pipe);
3012
3013 /* For PCH output, training FDI link */
3014 dev_priv->display.fdi_link_train(crtc);
3015
3016 intel_enable_pch_pll(intel_crtc);
3017
3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
3022 u32 sel;
3023
3024 temp = I915_READ(PCH_DPLL_SEL);
3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
3039 }
3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
3044 I915_WRITE(PCH_DPLL_SEL, temp);
3045 }
3046
3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3052
3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3057
3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
3060
3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
3073 temp |= bpc << 9; /* same format but at 11:9 */
3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
3082 temp |= TRANS_DP_PORT_SEL_B;
3083 break;
3084 case PCH_DP_C:
3085 temp |= TRANS_DP_PORT_SEL_C;
3086 break;
3087 case PCH_DP_D:
3088 temp |= TRANS_DP_PORT_SEL_D;
3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092 temp |= TRANS_DP_PORT_SEL_B;
3093 break;
3094 }
3095
3096 I915_WRITE(reg, temp);
3097 }
3098
3099 intel_enable_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103 {
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116 }
3117
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119 {
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171 found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3177
3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3185 pll->on = false;
3186 return pll;
3187 }
3188
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190 {
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205 }
3206
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208 {
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 struct intel_encoder *encoder;
3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
3218 WARN_ON(!crtc->enabled);
3219
3220 /* XXX: For compatability with the crtc helper code, call the encoder's
3221 * enable function unconditionally for now. */
3222 if (intel_crtc->active)
3223 goto encoders;
3224
3225 intel_crtc->active = true;
3226 intel_update_watermarks(dev);
3227
3228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3229 temp = I915_READ(PCH_LVDS);
3230 if ((temp & LVDS_PORT_EN) == 0)
3231 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3232 }
3233
3234 is_pch_port = intel_crtc_driving_pch(crtc);
3235
3236 if (is_pch_port)
3237 ironlake_fdi_pll_enable(intel_crtc);
3238 else
3239 ironlake_fdi_disable(crtc);
3240
3241 /* Enable panel fitting for LVDS */
3242 if (dev_priv->pch_pf_size &&
3243 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3246 * e.g. x201.
3247 */
3248 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3249 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3250 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3251 }
3252
3253 /*
3254 * On ILK+ LUT must be loaded before the pipe is running but with
3255 * clocks enabled
3256 */
3257 intel_crtc_load_lut(crtc);
3258
3259 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3260 intel_enable_plane(dev_priv, plane, pipe);
3261
3262 if (is_pch_port)
3263 ironlake_pch_enable(crtc);
3264
3265 mutex_lock(&dev->struct_mutex);
3266 intel_update_fbc(dev);
3267 mutex_unlock(&dev->struct_mutex);
3268
3269 intel_crtc_update_cursor(crtc, true);
3270
3271 encoders:
3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->enable(encoder);
3274
3275 if (HAS_PCH_CPT(dev))
3276 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3277 }
3278
3279 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3280 {
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 struct intel_encoder *encoder;
3285 int pipe = intel_crtc->pipe;
3286 int plane = intel_crtc->plane;
3287 u32 reg, temp;
3288
3289 /* XXX: For compatability with the crtc helper code, call the encoder's
3290 * disable function unconditionally for now. */
3291 for_each_encoder_on_crtc(dev, crtc, encoder)
3292 encoder->disable(encoder);
3293
3294 if (!intel_crtc->active)
3295 return;
3296
3297 intel_crtc_wait_for_pending_flips(crtc);
3298 drm_vblank_off(dev, pipe);
3299 intel_crtc_update_cursor(crtc, false);
3300
3301 intel_disable_plane(dev_priv, plane, pipe);
3302
3303 if (dev_priv->cfb_plane == plane)
3304 intel_disable_fbc(dev);
3305
3306 intel_disable_pipe(dev_priv, pipe);
3307
3308 /* Disable PF */
3309 I915_WRITE(PF_CTL(pipe), 0);
3310 I915_WRITE(PF_WIN_SZ(pipe), 0);
3311
3312 ironlake_fdi_disable(crtc);
3313
3314 /* This is a horrible layering violation; we should be doing this in
3315 * the connector/encoder ->prepare instead, but we don't always have
3316 * enough information there about the config to know whether it will
3317 * actually be necessary or just cause undesired flicker.
3318 */
3319 intel_disable_pch_ports(dev_priv, pipe);
3320
3321 intel_disable_transcoder(dev_priv, pipe);
3322
3323 if (HAS_PCH_CPT(dev)) {
3324 /* disable TRANS_DP_CTL */
3325 reg = TRANS_DP_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3328 temp |= TRANS_DP_PORT_SEL_NONE;
3329 I915_WRITE(reg, temp);
3330
3331 /* disable DPLL_SEL */
3332 temp = I915_READ(PCH_DPLL_SEL);
3333 switch (pipe) {
3334 case 0:
3335 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3336 break;
3337 case 1:
3338 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3339 break;
3340 case 2:
3341 /* C shares PLL A or B */
3342 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3343 break;
3344 default:
3345 BUG(); /* wtf */
3346 }
3347 I915_WRITE(PCH_DPLL_SEL, temp);
3348 }
3349
3350 /* disable PCH DPLL */
3351 intel_disable_pch_pll(intel_crtc);
3352
3353 ironlake_fdi_pll_disable(intel_crtc);
3354
3355 intel_crtc->active = false;
3356 intel_update_watermarks(dev);
3357
3358 mutex_lock(&dev->struct_mutex);
3359 intel_update_fbc(dev);
3360 mutex_unlock(&dev->struct_mutex);
3361 }
3362
3363 static void ironlake_crtc_off(struct drm_crtc *crtc)
3364 {
3365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3366 intel_put_pch_pll(intel_crtc);
3367 }
3368
3369 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3370 {
3371 if (!enable && intel_crtc->overlay) {
3372 struct drm_device *dev = intel_crtc->base.dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374
3375 mutex_lock(&dev->struct_mutex);
3376 dev_priv->mm.interruptible = false;
3377 (void) intel_overlay_switch_off(intel_crtc->overlay);
3378 dev_priv->mm.interruptible = true;
3379 mutex_unlock(&dev->struct_mutex);
3380 }
3381
3382 /* Let userspace switch the overlay on again. In most cases userspace
3383 * has to recompute where to put it anyway.
3384 */
3385 }
3386
3387 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3388 {
3389 struct drm_device *dev = crtc->dev;
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 struct intel_encoder *encoder;
3393 int pipe = intel_crtc->pipe;
3394 int plane = intel_crtc->plane;
3395
3396 WARN_ON(!crtc->enabled);
3397
3398 /* XXX: For compatability with the crtc helper code, call the encoder's
3399 * enable function unconditionally for now. */
3400 if (intel_crtc->active)
3401 goto encoders;
3402
3403 intel_crtc->active = true;
3404 intel_update_watermarks(dev);
3405
3406 intel_enable_pll(dev_priv, pipe);
3407 intel_enable_pipe(dev_priv, pipe, false);
3408 intel_enable_plane(dev_priv, plane, pipe);
3409
3410 intel_crtc_load_lut(crtc);
3411 intel_update_fbc(dev);
3412
3413 /* Give the overlay scaler a chance to enable if it's on this pipe */
3414 intel_crtc_dpms_overlay(intel_crtc, true);
3415 intel_crtc_update_cursor(crtc, true);
3416
3417 encoders:
3418 for_each_encoder_on_crtc(dev, crtc, encoder)
3419 encoder->enable(encoder);
3420 }
3421
3422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3423 {
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427 struct intel_encoder *encoder;
3428 int pipe = intel_crtc->pipe;
3429 int plane = intel_crtc->plane;
3430
3431 /* XXX: For compatability with the crtc helper code, call the encoder's
3432 * disable function unconditionally for now. */
3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->disable(encoder);
3435
3436 if (!intel_crtc->active)
3437 return;
3438
3439 /* Give the overlay scaler a chance to disable if it's on this pipe */
3440 intel_crtc_wait_for_pending_flips(crtc);
3441 drm_vblank_off(dev, pipe);
3442 intel_crtc_dpms_overlay(intel_crtc, false);
3443 intel_crtc_update_cursor(crtc, false);
3444
3445 if (dev_priv->cfb_plane == plane)
3446 intel_disable_fbc(dev);
3447
3448 intel_disable_plane(dev_priv, plane, pipe);
3449 intel_disable_pipe(dev_priv, pipe);
3450 intel_disable_pll(dev_priv, pipe);
3451
3452 intel_crtc->active = false;
3453 intel_update_fbc(dev);
3454 intel_update_watermarks(dev);
3455 }
3456
3457 static void i9xx_crtc_off(struct drm_crtc *crtc)
3458 {
3459 }
3460
3461 /**
3462 * Sets the power management mode of the pipe and plane.
3463 */
3464 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3465 {
3466 struct drm_device *dev = crtc->dev;
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct drm_i915_master_private *master_priv;
3469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3470 struct intel_encoder *intel_encoder;
3471 int pipe = intel_crtc->pipe;
3472 bool enabled, enable = false;
3473
3474 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3475 enable |= intel_encoder->connectors_active;
3476
3477 if (enable)
3478 dev_priv->display.crtc_enable(crtc);
3479 else
3480 dev_priv->display.crtc_disable(crtc);
3481
3482 if (!dev->primary->master)
3483 return;
3484
3485 master_priv = dev->primary->master->driver_priv;
3486 if (!master_priv->sarea_priv)
3487 return;
3488
3489 enabled = crtc->enabled && enable;
3490
3491 switch (pipe) {
3492 case 0:
3493 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3494 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3495 break;
3496 case 1:
3497 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3498 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3499 break;
3500 default:
3501 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3502 break;
3503 }
3504 }
3505
3506 static void intel_crtc_disable(struct drm_crtc *crtc)
3507 {
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510
3511 /* crtc->disable is only called when we have no encoders, hence this
3512 * will disable the pipe. */
3513 intel_crtc_update_dpms(crtc);
3514 dev_priv->display.off(crtc);
3515
3516 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3517 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3518
3519 if (crtc->fb) {
3520 mutex_lock(&dev->struct_mutex);
3521 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3522 mutex_unlock(&dev->struct_mutex);
3523 }
3524 }
3525
3526 void intel_encoder_disable(struct drm_encoder *encoder)
3527 {
3528 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3529
3530 intel_encoder->disable(intel_encoder);
3531 }
3532
3533 void intel_encoder_destroy(struct drm_encoder *encoder)
3534 {
3535 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3536
3537 drm_encoder_cleanup(encoder);
3538 kfree(intel_encoder);
3539 }
3540
3541 /* Simple dpms helper for encodres with just one connector, no cloning and only
3542 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3543 * state of the entire output pipe. */
3544 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3545 {
3546 if (mode == DRM_MODE_DPMS_ON) {
3547 encoder->connectors_active = true;
3548
3549 intel_crtc_update_dpms(encoder->base.crtc);
3550 } else {
3551 encoder->connectors_active = false;
3552
3553 intel_crtc_update_dpms(encoder->base.crtc);
3554 }
3555 }
3556
3557 /* Cross check the actual hw state with our own modeset state tracking (and it's
3558 * internal consistency). */
3559 void intel_connector_check_state(struct intel_connector *connector)
3560 {
3561 if (connector->get_hw_state(connector)) {
3562 struct intel_encoder *encoder = connector->encoder;
3563 struct drm_crtc *crtc;
3564 bool encoder_enabled;
3565 enum pipe pipe;
3566
3567 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3568 connector->base.base.id,
3569 drm_get_connector_name(&connector->base));
3570
3571 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3572 "wrong connector dpms state\n");
3573 WARN(connector->base.encoder != &encoder->base,
3574 "active connector not linked to encoder\n");
3575 WARN(!encoder->connectors_active,
3576 "encoder->connectors_active not set\n");
3577
3578 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3579 WARN(!encoder_enabled, "encoder not enabled\n");
3580 if (WARN_ON(!encoder->base.crtc))
3581 return;
3582
3583 crtc = encoder->base.crtc;
3584
3585 WARN(!crtc->enabled, "crtc not enabled\n");
3586 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3587 WARN(pipe != to_intel_crtc(crtc)->pipe,
3588 "encoder active on the wrong pipe\n");
3589 }
3590 }
3591
3592 /* Even simpler default implementation, if there's really no special case to
3593 * consider. */
3594 void intel_connector_dpms(struct drm_connector *connector, int mode)
3595 {
3596 struct intel_encoder *encoder = intel_attached_encoder(connector);
3597
3598 /* All the simple cases only support two dpms states. */
3599 if (mode != DRM_MODE_DPMS_ON)
3600 mode = DRM_MODE_DPMS_OFF;
3601
3602 if (mode == connector->dpms)
3603 return;
3604
3605 connector->dpms = mode;
3606
3607 /* Only need to change hw state when actually enabled */
3608 if (encoder->base.crtc)
3609 intel_encoder_dpms(encoder, mode);
3610 else
3611 encoder->connectors_active = false;
3612
3613 intel_connector_check_state(to_intel_connector(connector));
3614 }
3615
3616 /* Simple connector->get_hw_state implementation for encoders that support only
3617 * one connector and no cloning and hence the encoder state determines the state
3618 * of the connector. */
3619 bool intel_connector_get_hw_state(struct intel_connector *connector)
3620 {
3621 enum pipe pipe = 0;
3622 struct intel_encoder *encoder = connector->encoder;
3623
3624 return encoder->get_hw_state(encoder, &pipe);
3625 }
3626
3627 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3628 const struct drm_display_mode *mode,
3629 struct drm_display_mode *adjusted_mode)
3630 {
3631 struct drm_device *dev = crtc->dev;
3632
3633 if (HAS_PCH_SPLIT(dev)) {
3634 /* FDI link clock is fixed at 2.7G */
3635 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3636 return false;
3637 }
3638
3639 /* All interlaced capable intel hw wants timings in frames. Note though
3640 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3641 * timings, so we need to be careful not to clobber these.*/
3642 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3643 drm_mode_set_crtcinfo(adjusted_mode, 0);
3644
3645 return true;
3646 }
3647
3648 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3649 {
3650 return 400000; /* FIXME */
3651 }
3652
3653 static int i945_get_display_clock_speed(struct drm_device *dev)
3654 {
3655 return 400000;
3656 }
3657
3658 static int i915_get_display_clock_speed(struct drm_device *dev)
3659 {
3660 return 333000;
3661 }
3662
3663 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3664 {
3665 return 200000;
3666 }
3667
3668 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3669 {
3670 u16 gcfgc = 0;
3671
3672 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3673
3674 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3675 return 133000;
3676 else {
3677 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3678 case GC_DISPLAY_CLOCK_333_MHZ:
3679 return 333000;
3680 default:
3681 case GC_DISPLAY_CLOCK_190_200_MHZ:
3682 return 190000;
3683 }
3684 }
3685 }
3686
3687 static int i865_get_display_clock_speed(struct drm_device *dev)
3688 {
3689 return 266000;
3690 }
3691
3692 static int i855_get_display_clock_speed(struct drm_device *dev)
3693 {
3694 u16 hpllcc = 0;
3695 /* Assume that the hardware is in the high speed state. This
3696 * should be the default.
3697 */
3698 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3699 case GC_CLOCK_133_200:
3700 case GC_CLOCK_100_200:
3701 return 200000;
3702 case GC_CLOCK_166_250:
3703 return 250000;
3704 case GC_CLOCK_100_133:
3705 return 133000;
3706 }
3707
3708 /* Shouldn't happen */
3709 return 0;
3710 }
3711
3712 static int i830_get_display_clock_speed(struct drm_device *dev)
3713 {
3714 return 133000;
3715 }
3716
3717 struct fdi_m_n {
3718 u32 tu;
3719 u32 gmch_m;
3720 u32 gmch_n;
3721 u32 link_m;
3722 u32 link_n;
3723 };
3724
3725 static void
3726 fdi_reduce_ratio(u32 *num, u32 *den)
3727 {
3728 while (*num > 0xffffff || *den > 0xffffff) {
3729 *num >>= 1;
3730 *den >>= 1;
3731 }
3732 }
3733
3734 static void
3735 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3736 int link_clock, struct fdi_m_n *m_n)
3737 {
3738 m_n->tu = 64; /* default size */
3739
3740 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3741 m_n->gmch_m = bits_per_pixel * pixel_clock;
3742 m_n->gmch_n = link_clock * nlanes * 8;
3743 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3744
3745 m_n->link_m = pixel_clock;
3746 m_n->link_n = link_clock;
3747 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3748 }
3749
3750 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3751 {
3752 if (i915_panel_use_ssc >= 0)
3753 return i915_panel_use_ssc != 0;
3754 return dev_priv->lvds_use_ssc
3755 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3756 }
3757
3758 /**
3759 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3760 * @crtc: CRTC structure
3761 * @mode: requested mode
3762 *
3763 * A pipe may be connected to one or more outputs. Based on the depth of the
3764 * attached framebuffer, choose a good color depth to use on the pipe.
3765 *
3766 * If possible, match the pipe depth to the fb depth. In some cases, this
3767 * isn't ideal, because the connected output supports a lesser or restricted
3768 * set of depths. Resolve that here:
3769 * LVDS typically supports only 6bpc, so clamp down in that case
3770 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3771 * Displays may support a restricted set as well, check EDID and clamp as
3772 * appropriate.
3773 * DP may want to dither down to 6bpc to fit larger modes
3774 *
3775 * RETURNS:
3776 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3777 * true if they don't match).
3778 */
3779 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3780 unsigned int *pipe_bpp,
3781 struct drm_display_mode *mode)
3782 {
3783 struct drm_device *dev = crtc->dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 struct drm_connector *connector;
3786 struct intel_encoder *intel_encoder;
3787 unsigned int display_bpc = UINT_MAX, bpc;
3788
3789 /* Walk the encoders & connectors on this crtc, get min bpc */
3790 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3791
3792 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3793 unsigned int lvds_bpc;
3794
3795 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3796 LVDS_A3_POWER_UP)
3797 lvds_bpc = 8;
3798 else
3799 lvds_bpc = 6;
3800
3801 if (lvds_bpc < display_bpc) {
3802 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3803 display_bpc = lvds_bpc;
3804 }
3805 continue;
3806 }
3807
3808 /* Not one of the known troublemakers, check the EDID */
3809 list_for_each_entry(connector, &dev->mode_config.connector_list,
3810 head) {
3811 if (connector->encoder != &intel_encoder->base)
3812 continue;
3813
3814 /* Don't use an invalid EDID bpc value */
3815 if (connector->display_info.bpc &&
3816 connector->display_info.bpc < display_bpc) {
3817 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3818 display_bpc = connector->display_info.bpc;
3819 }
3820 }
3821
3822 /*
3823 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3824 * through, clamp it down. (Note: >12bpc will be caught below.)
3825 */
3826 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3827 if (display_bpc > 8 && display_bpc < 12) {
3828 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3829 display_bpc = 12;
3830 } else {
3831 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3832 display_bpc = 8;
3833 }
3834 }
3835 }
3836
3837 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3838 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3839 display_bpc = 6;
3840 }
3841
3842 /*
3843 * We could just drive the pipe at the highest bpc all the time and
3844 * enable dithering as needed, but that costs bandwidth. So choose
3845 * the minimum value that expresses the full color range of the fb but
3846 * also stays within the max display bpc discovered above.
3847 */
3848
3849 switch (crtc->fb->depth) {
3850 case 8:
3851 bpc = 8; /* since we go through a colormap */
3852 break;
3853 case 15:
3854 case 16:
3855 bpc = 6; /* min is 18bpp */
3856 break;
3857 case 24:
3858 bpc = 8;
3859 break;
3860 case 30:
3861 bpc = 10;
3862 break;
3863 case 48:
3864 bpc = 12;
3865 break;
3866 default:
3867 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3868 bpc = min((unsigned int)8, display_bpc);
3869 break;
3870 }
3871
3872 display_bpc = min(display_bpc, bpc);
3873
3874 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3875 bpc, display_bpc);
3876
3877 *pipe_bpp = display_bpc * 3;
3878
3879 return display_bpc != bpc;
3880 }
3881
3882 static int vlv_get_refclk(struct drm_crtc *crtc)
3883 {
3884 struct drm_device *dev = crtc->dev;
3885 struct drm_i915_private *dev_priv = dev->dev_private;
3886 int refclk = 27000; /* for DP & HDMI */
3887
3888 return 100000; /* only one validated so far */
3889
3890 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3891 refclk = 96000;
3892 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3893 if (intel_panel_use_ssc(dev_priv))
3894 refclk = 100000;
3895 else
3896 refclk = 96000;
3897 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3898 refclk = 100000;
3899 }
3900
3901 return refclk;
3902 }
3903
3904 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3905 {
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 int refclk;
3909
3910 if (IS_VALLEYVIEW(dev)) {
3911 refclk = vlv_get_refclk(crtc);
3912 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3913 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3914 refclk = dev_priv->lvds_ssc_freq * 1000;
3915 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3916 refclk / 1000);
3917 } else if (!IS_GEN2(dev)) {
3918 refclk = 96000;
3919 } else {
3920 refclk = 48000;
3921 }
3922
3923 return refclk;
3924 }
3925
3926 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3927 intel_clock_t *clock)
3928 {
3929 /* SDVO TV has fixed PLL values depend on its clock range,
3930 this mirrors vbios setting. */
3931 if (adjusted_mode->clock >= 100000
3932 && adjusted_mode->clock < 140500) {
3933 clock->p1 = 2;
3934 clock->p2 = 10;
3935 clock->n = 3;
3936 clock->m1 = 16;
3937 clock->m2 = 8;
3938 } else if (adjusted_mode->clock >= 140500
3939 && adjusted_mode->clock <= 200000) {
3940 clock->p1 = 1;
3941 clock->p2 = 10;
3942 clock->n = 6;
3943 clock->m1 = 12;
3944 clock->m2 = 8;
3945 }
3946 }
3947
3948 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3949 intel_clock_t *clock,
3950 intel_clock_t *reduced_clock)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955 int pipe = intel_crtc->pipe;
3956 u32 fp, fp2 = 0;
3957
3958 if (IS_PINEVIEW(dev)) {
3959 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3960 if (reduced_clock)
3961 fp2 = (1 << reduced_clock->n) << 16 |
3962 reduced_clock->m1 << 8 | reduced_clock->m2;
3963 } else {
3964 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3965 if (reduced_clock)
3966 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3967 reduced_clock->m2;
3968 }
3969
3970 I915_WRITE(FP0(pipe), fp);
3971
3972 intel_crtc->lowfreq_avail = false;
3973 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3974 reduced_clock && i915_powersave) {
3975 I915_WRITE(FP1(pipe), fp2);
3976 intel_crtc->lowfreq_avail = true;
3977 } else {
3978 I915_WRITE(FP1(pipe), fp);
3979 }
3980 }
3981
3982 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3983 struct drm_display_mode *adjusted_mode)
3984 {
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
3989 u32 temp;
3990
3991 temp = I915_READ(LVDS);
3992 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3993 if (pipe == 1) {
3994 temp |= LVDS_PIPEB_SELECT;
3995 } else {
3996 temp &= ~LVDS_PIPEB_SELECT;
3997 }
3998 /* set the corresponsding LVDS_BORDER bit */
3999 temp |= dev_priv->lvds_border_bits;
4000 /* Set the B0-B3 data pairs corresponding to whether we're going to
4001 * set the DPLLs for dual-channel mode or not.
4002 */
4003 if (clock->p2 == 7)
4004 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4005 else
4006 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4007
4008 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4009 * appropriately here, but we need to look more thoroughly into how
4010 * panels behave in the two modes.
4011 */
4012 /* set the dithering flag on LVDS as needed */
4013 if (INTEL_INFO(dev)->gen >= 4) {
4014 if (dev_priv->lvds_dither)
4015 temp |= LVDS_ENABLE_DITHER;
4016 else
4017 temp &= ~LVDS_ENABLE_DITHER;
4018 }
4019 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4020 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4021 temp |= LVDS_HSYNC_POLARITY;
4022 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4023 temp |= LVDS_VSYNC_POLARITY;
4024 I915_WRITE(LVDS, temp);
4025 }
4026
4027 static void vlv_update_pll(struct drm_crtc *crtc,
4028 struct drm_display_mode *mode,
4029 struct drm_display_mode *adjusted_mode,
4030 intel_clock_t *clock, intel_clock_t *reduced_clock,
4031 int refclk, int num_connectors)
4032 {
4033 struct drm_device *dev = crtc->dev;
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4036 int pipe = intel_crtc->pipe;
4037 u32 dpll, mdiv, pdiv;
4038 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4039 bool is_hdmi;
4040
4041 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4042
4043 bestn = clock->n;
4044 bestm1 = clock->m1;
4045 bestm2 = clock->m2;
4046 bestp1 = clock->p1;
4047 bestp2 = clock->p2;
4048
4049 /* Enable DPIO clock input */
4050 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4051 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4052 I915_WRITE(DPLL(pipe), dpll);
4053 POSTING_READ(DPLL(pipe));
4054
4055 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4056 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4057 mdiv |= ((bestn << DPIO_N_SHIFT));
4058 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4059 mdiv |= (1 << DPIO_K_SHIFT);
4060 mdiv |= DPIO_ENABLE_CALIBRATION;
4061 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4062
4063 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4064
4065 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4066 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4067 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4068 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4069
4070 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4071
4072 dpll |= DPLL_VCO_ENABLE;
4073 I915_WRITE(DPLL(pipe), dpll);
4074 POSTING_READ(DPLL(pipe));
4075 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4076 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4077
4078 if (is_hdmi) {
4079 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4080
4081 if (temp > 1)
4082 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4083 else
4084 temp = 0;
4085
4086 I915_WRITE(DPLL_MD(pipe), temp);
4087 POSTING_READ(DPLL_MD(pipe));
4088 }
4089
4090 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4091 }
4092
4093 static void i9xx_update_pll(struct drm_crtc *crtc,
4094 struct drm_display_mode *mode,
4095 struct drm_display_mode *adjusted_mode,
4096 intel_clock_t *clock, intel_clock_t *reduced_clock,
4097 int num_connectors)
4098 {
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4102 int pipe = intel_crtc->pipe;
4103 u32 dpll;
4104 bool is_sdvo;
4105
4106 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4107 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4108
4109 dpll = DPLL_VGA_MODE_DIS;
4110
4111 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4112 dpll |= DPLLB_MODE_LVDS;
4113 else
4114 dpll |= DPLLB_MODE_DAC_SERIAL;
4115 if (is_sdvo) {
4116 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4117 if (pixel_multiplier > 1) {
4118 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4119 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4120 }
4121 dpll |= DPLL_DVO_HIGH_SPEED;
4122 }
4123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4124 dpll |= DPLL_DVO_HIGH_SPEED;
4125
4126 /* compute bitmask from p1 value */
4127 if (IS_PINEVIEW(dev))
4128 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4129 else {
4130 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4131 if (IS_G4X(dev) && reduced_clock)
4132 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4133 }
4134 switch (clock->p2) {
4135 case 5:
4136 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4137 break;
4138 case 7:
4139 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4140 break;
4141 case 10:
4142 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4143 break;
4144 case 14:
4145 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4146 break;
4147 }
4148 if (INTEL_INFO(dev)->gen >= 4)
4149 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4150
4151 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4152 dpll |= PLL_REF_INPUT_TVCLKINBC;
4153 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4154 /* XXX: just matching BIOS for now */
4155 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4156 dpll |= 3;
4157 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4158 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4159 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4160 else
4161 dpll |= PLL_REF_INPUT_DREFCLK;
4162
4163 dpll |= DPLL_VCO_ENABLE;
4164 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4165 POSTING_READ(DPLL(pipe));
4166 udelay(150);
4167
4168 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4169 * This is an exception to the general rule that mode_set doesn't turn
4170 * things on.
4171 */
4172 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4173 intel_update_lvds(crtc, clock, adjusted_mode);
4174
4175 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4176 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4177
4178 I915_WRITE(DPLL(pipe), dpll);
4179
4180 /* Wait for the clocks to stabilize. */
4181 POSTING_READ(DPLL(pipe));
4182 udelay(150);
4183
4184 if (INTEL_INFO(dev)->gen >= 4) {
4185 u32 temp = 0;
4186 if (is_sdvo) {
4187 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4188 if (temp > 1)
4189 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4190 else
4191 temp = 0;
4192 }
4193 I915_WRITE(DPLL_MD(pipe), temp);
4194 } else {
4195 /* The pixel multiplier can only be updated once the
4196 * DPLL is enabled and the clocks are stable.
4197 *
4198 * So write it again.
4199 */
4200 I915_WRITE(DPLL(pipe), dpll);
4201 }
4202 }
4203
4204 static void i8xx_update_pll(struct drm_crtc *crtc,
4205 struct drm_display_mode *adjusted_mode,
4206 intel_clock_t *clock,
4207 int num_connectors)
4208 {
4209 struct drm_device *dev = crtc->dev;
4210 struct drm_i915_private *dev_priv = dev->dev_private;
4211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4212 int pipe = intel_crtc->pipe;
4213 u32 dpll;
4214
4215 dpll = DPLL_VGA_MODE_DIS;
4216
4217 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4218 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4219 } else {
4220 if (clock->p1 == 2)
4221 dpll |= PLL_P1_DIVIDE_BY_TWO;
4222 else
4223 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4224 if (clock->p2 == 4)
4225 dpll |= PLL_P2_DIVIDE_BY_4;
4226 }
4227
4228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4229 /* XXX: just matching BIOS for now */
4230 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4231 dpll |= 3;
4232 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4233 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4234 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4235 else
4236 dpll |= PLL_REF_INPUT_DREFCLK;
4237
4238 dpll |= DPLL_VCO_ENABLE;
4239 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4240 POSTING_READ(DPLL(pipe));
4241 udelay(150);
4242
4243 I915_WRITE(DPLL(pipe), dpll);
4244
4245 /* Wait for the clocks to stabilize. */
4246 POSTING_READ(DPLL(pipe));
4247 udelay(150);
4248
4249 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4250 * This is an exception to the general rule that mode_set doesn't turn
4251 * things on.
4252 */
4253 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4254 intel_update_lvds(crtc, clock, adjusted_mode);
4255
4256 /* The pixel multiplier can only be updated once the
4257 * DPLL is enabled and the clocks are stable.
4258 *
4259 * So write it again.
4260 */
4261 I915_WRITE(DPLL(pipe), dpll);
4262 }
4263
4264 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4265 struct drm_display_mode *mode,
4266 struct drm_display_mode *adjusted_mode,
4267 int x, int y,
4268 struct drm_framebuffer *old_fb)
4269 {
4270 struct drm_device *dev = crtc->dev;
4271 struct drm_i915_private *dev_priv = dev->dev_private;
4272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4273 int pipe = intel_crtc->pipe;
4274 int plane = intel_crtc->plane;
4275 int refclk, num_connectors = 0;
4276 intel_clock_t clock, reduced_clock;
4277 u32 dspcntr, pipeconf, vsyncshift;
4278 bool ok, has_reduced_clock = false, is_sdvo = false;
4279 bool is_lvds = false, is_tv = false, is_dp = false;
4280 struct intel_encoder *encoder;
4281 const intel_limit_t *limit;
4282 int ret;
4283
4284 for_each_encoder_on_crtc(dev, crtc, encoder) {
4285 switch (encoder->type) {
4286 case INTEL_OUTPUT_LVDS:
4287 is_lvds = true;
4288 break;
4289 case INTEL_OUTPUT_SDVO:
4290 case INTEL_OUTPUT_HDMI:
4291 is_sdvo = true;
4292 if (encoder->needs_tv_clock)
4293 is_tv = true;
4294 break;
4295 case INTEL_OUTPUT_TVOUT:
4296 is_tv = true;
4297 break;
4298 case INTEL_OUTPUT_DISPLAYPORT:
4299 is_dp = true;
4300 break;
4301 }
4302
4303 num_connectors++;
4304 }
4305
4306 refclk = i9xx_get_refclk(crtc, num_connectors);
4307
4308 /*
4309 * Returns a set of divisors for the desired target clock with the given
4310 * refclk, or FALSE. The returned values represent the clock equation:
4311 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4312 */
4313 limit = intel_limit(crtc, refclk);
4314 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4315 &clock);
4316 if (!ok) {
4317 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4318 return -EINVAL;
4319 }
4320
4321 /* Ensure that the cursor is valid for the new mode before changing... */
4322 intel_crtc_update_cursor(crtc, true);
4323
4324 if (is_lvds && dev_priv->lvds_downclock_avail) {
4325 /*
4326 * Ensure we match the reduced clock's P to the target clock.
4327 * If the clocks don't match, we can't switch the display clock
4328 * by using the FP0/FP1. In such case we will disable the LVDS
4329 * downclock feature.
4330 */
4331 has_reduced_clock = limit->find_pll(limit, crtc,
4332 dev_priv->lvds_downclock,
4333 refclk,
4334 &clock,
4335 &reduced_clock);
4336 }
4337
4338 if (is_sdvo && is_tv)
4339 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4340
4341 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4342 &reduced_clock : NULL);
4343
4344 if (IS_GEN2(dev))
4345 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4346 else if (IS_VALLEYVIEW(dev))
4347 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4348 refclk, num_connectors);
4349 else
4350 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4351 has_reduced_clock ? &reduced_clock : NULL,
4352 num_connectors);
4353
4354 /* setup pipeconf */
4355 pipeconf = I915_READ(PIPECONF(pipe));
4356
4357 /* Set up the display plane register */
4358 dspcntr = DISPPLANE_GAMMA_ENABLE;
4359
4360 if (pipe == 0)
4361 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4362 else
4363 dspcntr |= DISPPLANE_SEL_PIPE_B;
4364
4365 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4366 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4367 * core speed.
4368 *
4369 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4370 * pipe == 0 check?
4371 */
4372 if (mode->clock >
4373 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4374 pipeconf |= PIPECONF_DOUBLE_WIDE;
4375 else
4376 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4377 }
4378
4379 /* default to 8bpc */
4380 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4381 if (is_dp) {
4382 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4383 pipeconf |= PIPECONF_BPP_6 |
4384 PIPECONF_DITHER_EN |
4385 PIPECONF_DITHER_TYPE_SP;
4386 }
4387 }
4388
4389 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4390 drm_mode_debug_printmodeline(mode);
4391
4392 if (HAS_PIPE_CXSR(dev)) {
4393 if (intel_crtc->lowfreq_avail) {
4394 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4395 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4396 } else {
4397 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4398 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4399 }
4400 }
4401
4402 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4403 if (!IS_GEN2(dev) &&
4404 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4405 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4406 /* the chip adds 2 halflines automatically */
4407 adjusted_mode->crtc_vtotal -= 1;
4408 adjusted_mode->crtc_vblank_end -= 1;
4409 vsyncshift = adjusted_mode->crtc_hsync_start
4410 - adjusted_mode->crtc_htotal/2;
4411 } else {
4412 pipeconf |= PIPECONF_PROGRESSIVE;
4413 vsyncshift = 0;
4414 }
4415
4416 if (!IS_GEN3(dev))
4417 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4418
4419 I915_WRITE(HTOTAL(pipe),
4420 (adjusted_mode->crtc_hdisplay - 1) |
4421 ((adjusted_mode->crtc_htotal - 1) << 16));
4422 I915_WRITE(HBLANK(pipe),
4423 (adjusted_mode->crtc_hblank_start - 1) |
4424 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4425 I915_WRITE(HSYNC(pipe),
4426 (adjusted_mode->crtc_hsync_start - 1) |
4427 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4428
4429 I915_WRITE(VTOTAL(pipe),
4430 (adjusted_mode->crtc_vdisplay - 1) |
4431 ((adjusted_mode->crtc_vtotal - 1) << 16));
4432 I915_WRITE(VBLANK(pipe),
4433 (adjusted_mode->crtc_vblank_start - 1) |
4434 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4435 I915_WRITE(VSYNC(pipe),
4436 (adjusted_mode->crtc_vsync_start - 1) |
4437 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4438
4439 /* pipesrc and dspsize control the size that is scaled from,
4440 * which should always be the user's requested size.
4441 */
4442 I915_WRITE(DSPSIZE(plane),
4443 ((mode->vdisplay - 1) << 16) |
4444 (mode->hdisplay - 1));
4445 I915_WRITE(DSPPOS(plane), 0);
4446 I915_WRITE(PIPESRC(pipe),
4447 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4448
4449 I915_WRITE(PIPECONF(pipe), pipeconf);
4450 POSTING_READ(PIPECONF(pipe));
4451 intel_enable_pipe(dev_priv, pipe, false);
4452
4453 intel_wait_for_vblank(dev, pipe);
4454
4455 I915_WRITE(DSPCNTR(plane), dspcntr);
4456 POSTING_READ(DSPCNTR(plane));
4457
4458 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4459
4460 intel_update_watermarks(dev);
4461
4462 return ret;
4463 }
4464
4465 /*
4466 * Initialize reference clocks when the driver loads
4467 */
4468 void ironlake_init_pch_refclk(struct drm_device *dev)
4469 {
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 struct drm_mode_config *mode_config = &dev->mode_config;
4472 struct intel_encoder *encoder;
4473 u32 temp;
4474 bool has_lvds = false;
4475 bool has_cpu_edp = false;
4476 bool has_pch_edp = false;
4477 bool has_panel = false;
4478 bool has_ck505 = false;
4479 bool can_ssc = false;
4480
4481 /* We need to take the global config into account */
4482 list_for_each_entry(encoder, &mode_config->encoder_list,
4483 base.head) {
4484 switch (encoder->type) {
4485 case INTEL_OUTPUT_LVDS:
4486 has_panel = true;
4487 has_lvds = true;
4488 break;
4489 case INTEL_OUTPUT_EDP:
4490 has_panel = true;
4491 if (intel_encoder_is_pch_edp(&encoder->base))
4492 has_pch_edp = true;
4493 else
4494 has_cpu_edp = true;
4495 break;
4496 }
4497 }
4498
4499 if (HAS_PCH_IBX(dev)) {
4500 has_ck505 = dev_priv->display_clock_mode;
4501 can_ssc = has_ck505;
4502 } else {
4503 has_ck505 = false;
4504 can_ssc = true;
4505 }
4506
4507 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4508 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4509 has_ck505);
4510
4511 /* Ironlake: try to setup display ref clock before DPLL
4512 * enabling. This is only under driver's control after
4513 * PCH B stepping, previous chipset stepping should be
4514 * ignoring this setting.
4515 */
4516 temp = I915_READ(PCH_DREF_CONTROL);
4517 /* Always enable nonspread source */
4518 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4519
4520 if (has_ck505)
4521 temp |= DREF_NONSPREAD_CK505_ENABLE;
4522 else
4523 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4524
4525 if (has_panel) {
4526 temp &= ~DREF_SSC_SOURCE_MASK;
4527 temp |= DREF_SSC_SOURCE_ENABLE;
4528
4529 /* SSC must be turned on before enabling the CPU output */
4530 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4531 DRM_DEBUG_KMS("Using SSC on panel\n");
4532 temp |= DREF_SSC1_ENABLE;
4533 } else
4534 temp &= ~DREF_SSC1_ENABLE;
4535
4536 /* Get SSC going before enabling the outputs */
4537 I915_WRITE(PCH_DREF_CONTROL, temp);
4538 POSTING_READ(PCH_DREF_CONTROL);
4539 udelay(200);
4540
4541 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4542
4543 /* Enable CPU source on CPU attached eDP */
4544 if (has_cpu_edp) {
4545 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4546 DRM_DEBUG_KMS("Using SSC on eDP\n");
4547 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4548 }
4549 else
4550 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4551 } else
4552 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4553
4554 I915_WRITE(PCH_DREF_CONTROL, temp);
4555 POSTING_READ(PCH_DREF_CONTROL);
4556 udelay(200);
4557 } else {
4558 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4559
4560 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4561
4562 /* Turn off CPU output */
4563 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4564
4565 I915_WRITE(PCH_DREF_CONTROL, temp);
4566 POSTING_READ(PCH_DREF_CONTROL);
4567 udelay(200);
4568
4569 /* Turn off the SSC source */
4570 temp &= ~DREF_SSC_SOURCE_MASK;
4571 temp |= DREF_SSC_SOURCE_DISABLE;
4572
4573 /* Turn off SSC1 */
4574 temp &= ~ DREF_SSC1_ENABLE;
4575
4576 I915_WRITE(PCH_DREF_CONTROL, temp);
4577 POSTING_READ(PCH_DREF_CONTROL);
4578 udelay(200);
4579 }
4580 }
4581
4582 static int ironlake_get_refclk(struct drm_crtc *crtc)
4583 {
4584 struct drm_device *dev = crtc->dev;
4585 struct drm_i915_private *dev_priv = dev->dev_private;
4586 struct intel_encoder *encoder;
4587 struct intel_encoder *edp_encoder = NULL;
4588 int num_connectors = 0;
4589 bool is_lvds = false;
4590
4591 for_each_encoder_on_crtc(dev, crtc, encoder) {
4592 switch (encoder->type) {
4593 case INTEL_OUTPUT_LVDS:
4594 is_lvds = true;
4595 break;
4596 case INTEL_OUTPUT_EDP:
4597 edp_encoder = encoder;
4598 break;
4599 }
4600 num_connectors++;
4601 }
4602
4603 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4604 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4605 dev_priv->lvds_ssc_freq);
4606 return dev_priv->lvds_ssc_freq * 1000;
4607 }
4608
4609 return 120000;
4610 }
4611
4612 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4613 struct drm_display_mode *mode,
4614 struct drm_display_mode *adjusted_mode,
4615 int x, int y,
4616 struct drm_framebuffer *old_fb)
4617 {
4618 struct drm_device *dev = crtc->dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4621 int pipe = intel_crtc->pipe;
4622 int plane = intel_crtc->plane;
4623 int refclk, num_connectors = 0;
4624 intel_clock_t clock, reduced_clock;
4625 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4626 bool ok, has_reduced_clock = false, is_sdvo = false;
4627 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4628 struct intel_encoder *encoder, *edp_encoder = NULL;
4629 const intel_limit_t *limit;
4630 int ret;
4631 struct fdi_m_n m_n = {0};
4632 u32 temp;
4633 int target_clock, pixel_multiplier, lane, link_bw, factor;
4634 unsigned int pipe_bpp;
4635 bool dither;
4636 bool is_cpu_edp = false, is_pch_edp = false;
4637
4638 for_each_encoder_on_crtc(dev, crtc, encoder) {
4639 switch (encoder->type) {
4640 case INTEL_OUTPUT_LVDS:
4641 is_lvds = true;
4642 break;
4643 case INTEL_OUTPUT_SDVO:
4644 case INTEL_OUTPUT_HDMI:
4645 is_sdvo = true;
4646 if (encoder->needs_tv_clock)
4647 is_tv = true;
4648 break;
4649 case INTEL_OUTPUT_TVOUT:
4650 is_tv = true;
4651 break;
4652 case INTEL_OUTPUT_ANALOG:
4653 is_crt = true;
4654 break;
4655 case INTEL_OUTPUT_DISPLAYPORT:
4656 is_dp = true;
4657 break;
4658 case INTEL_OUTPUT_EDP:
4659 is_dp = true;
4660 if (intel_encoder_is_pch_edp(&encoder->base))
4661 is_pch_edp = true;
4662 else
4663 is_cpu_edp = true;
4664 edp_encoder = encoder;
4665 break;
4666 }
4667
4668 num_connectors++;
4669 }
4670
4671 refclk = ironlake_get_refclk(crtc);
4672
4673 /*
4674 * Returns a set of divisors for the desired target clock with the given
4675 * refclk, or FALSE. The returned values represent the clock equation:
4676 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4677 */
4678 limit = intel_limit(crtc, refclk);
4679 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4680 &clock);
4681 if (!ok) {
4682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4683 return -EINVAL;
4684 }
4685
4686 /* Ensure that the cursor is valid for the new mode before changing... */
4687 intel_crtc_update_cursor(crtc, true);
4688
4689 if (is_lvds && dev_priv->lvds_downclock_avail) {
4690 /*
4691 * Ensure we match the reduced clock's P to the target clock.
4692 * If the clocks don't match, we can't switch the display clock
4693 * by using the FP0/FP1. In such case we will disable the LVDS
4694 * downclock feature.
4695 */
4696 has_reduced_clock = limit->find_pll(limit, crtc,
4697 dev_priv->lvds_downclock,
4698 refclk,
4699 &clock,
4700 &reduced_clock);
4701 }
4702
4703 if (is_sdvo && is_tv)
4704 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4705
4706
4707 /* FDI link */
4708 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4709 lane = 0;
4710 /* CPU eDP doesn't require FDI link, so just set DP M/N
4711 according to current link config */
4712 if (is_cpu_edp) {
4713 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4714 } else {
4715 /* FDI is a binary signal running at ~2.7GHz, encoding
4716 * each output octet as 10 bits. The actual frequency
4717 * is stored as a divider into a 100MHz clock, and the
4718 * mode pixel clock is stored in units of 1KHz.
4719 * Hence the bw of each lane in terms of the mode signal
4720 * is:
4721 */
4722 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4723 }
4724
4725 /* [e]DP over FDI requires target mode clock instead of link clock. */
4726 if (edp_encoder)
4727 target_clock = intel_edp_target_clock(edp_encoder, mode);
4728 else if (is_dp)
4729 target_clock = mode->clock;
4730 else
4731 target_clock = adjusted_mode->clock;
4732
4733 /* determine panel color depth */
4734 temp = I915_READ(PIPECONF(pipe));
4735 temp &= ~PIPE_BPC_MASK;
4736 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4737 switch (pipe_bpp) {
4738 case 18:
4739 temp |= PIPE_6BPC;
4740 break;
4741 case 24:
4742 temp |= PIPE_8BPC;
4743 break;
4744 case 30:
4745 temp |= PIPE_10BPC;
4746 break;
4747 case 36:
4748 temp |= PIPE_12BPC;
4749 break;
4750 default:
4751 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4752 pipe_bpp);
4753 temp |= PIPE_8BPC;
4754 pipe_bpp = 24;
4755 break;
4756 }
4757
4758 intel_crtc->bpp = pipe_bpp;
4759 I915_WRITE(PIPECONF(pipe), temp);
4760
4761 if (!lane) {
4762 /*
4763 * Account for spread spectrum to avoid
4764 * oversubscribing the link. Max center spread
4765 * is 2.5%; use 5% for safety's sake.
4766 */
4767 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4768 lane = bps / (link_bw * 8) + 1;
4769 }
4770
4771 intel_crtc->fdi_lanes = lane;
4772
4773 if (pixel_multiplier > 1)
4774 link_bw *= pixel_multiplier;
4775 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4776 &m_n);
4777
4778 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4779 if (has_reduced_clock)
4780 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4781 reduced_clock.m2;
4782
4783 /* Enable autotuning of the PLL clock (if permissible) */
4784 factor = 21;
4785 if (is_lvds) {
4786 if ((intel_panel_use_ssc(dev_priv) &&
4787 dev_priv->lvds_ssc_freq == 100) ||
4788 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4789 factor = 25;
4790 } else if (is_sdvo && is_tv)
4791 factor = 20;
4792
4793 if (clock.m < factor * clock.n)
4794 fp |= FP_CB_TUNE;
4795
4796 dpll = 0;
4797
4798 if (is_lvds)
4799 dpll |= DPLLB_MODE_LVDS;
4800 else
4801 dpll |= DPLLB_MODE_DAC_SERIAL;
4802 if (is_sdvo) {
4803 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4804 if (pixel_multiplier > 1) {
4805 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4806 }
4807 dpll |= DPLL_DVO_HIGH_SPEED;
4808 }
4809 if (is_dp && !is_cpu_edp)
4810 dpll |= DPLL_DVO_HIGH_SPEED;
4811
4812 /* compute bitmask from p1 value */
4813 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4814 /* also FPA1 */
4815 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4816
4817 switch (clock.p2) {
4818 case 5:
4819 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4820 break;
4821 case 7:
4822 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4823 break;
4824 case 10:
4825 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4826 break;
4827 case 14:
4828 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4829 break;
4830 }
4831
4832 if (is_sdvo && is_tv)
4833 dpll |= PLL_REF_INPUT_TVCLKINBC;
4834 else if (is_tv)
4835 /* XXX: just matching BIOS for now */
4836 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4837 dpll |= 3;
4838 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4839 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4840 else
4841 dpll |= PLL_REF_INPUT_DREFCLK;
4842
4843 /* setup pipeconf */
4844 pipeconf = I915_READ(PIPECONF(pipe));
4845
4846 /* Set up the display plane register */
4847 dspcntr = DISPPLANE_GAMMA_ENABLE;
4848
4849 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4850 drm_mode_debug_printmodeline(mode);
4851
4852 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4853 * pre-Haswell/LPT generation */
4854 if (HAS_PCH_LPT(dev)) {
4855 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4856 pipe);
4857 } else if (!is_cpu_edp) {
4858 struct intel_pch_pll *pll;
4859
4860 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4861 if (pll == NULL) {
4862 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4863 pipe);
4864 return -EINVAL;
4865 }
4866 } else
4867 intel_put_pch_pll(intel_crtc);
4868
4869 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4870 * This is an exception to the general rule that mode_set doesn't turn
4871 * things on.
4872 */
4873 if (is_lvds) {
4874 temp = I915_READ(PCH_LVDS);
4875 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4876 if (HAS_PCH_CPT(dev)) {
4877 temp &= ~PORT_TRANS_SEL_MASK;
4878 temp |= PORT_TRANS_SEL_CPT(pipe);
4879 } else {
4880 if (pipe == 1)
4881 temp |= LVDS_PIPEB_SELECT;
4882 else
4883 temp &= ~LVDS_PIPEB_SELECT;
4884 }
4885
4886 /* set the corresponsding LVDS_BORDER bit */
4887 temp |= dev_priv->lvds_border_bits;
4888 /* Set the B0-B3 data pairs corresponding to whether we're going to
4889 * set the DPLLs for dual-channel mode or not.
4890 */
4891 if (clock.p2 == 7)
4892 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4893 else
4894 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4895
4896 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4897 * appropriately here, but we need to look more thoroughly into how
4898 * panels behave in the two modes.
4899 */
4900 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4901 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4902 temp |= LVDS_HSYNC_POLARITY;
4903 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4904 temp |= LVDS_VSYNC_POLARITY;
4905 I915_WRITE(PCH_LVDS, temp);
4906 }
4907
4908 pipeconf &= ~PIPECONF_DITHER_EN;
4909 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4910 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4911 pipeconf |= PIPECONF_DITHER_EN;
4912 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4913 }
4914 if (is_dp && !is_cpu_edp) {
4915 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4916 } else {
4917 /* For non-DP output, clear any trans DP clock recovery setting.*/
4918 I915_WRITE(TRANSDATA_M1(pipe), 0);
4919 I915_WRITE(TRANSDATA_N1(pipe), 0);
4920 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4921 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4922 }
4923
4924 if (intel_crtc->pch_pll) {
4925 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4926
4927 /* Wait for the clocks to stabilize. */
4928 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4929 udelay(150);
4930
4931 /* The pixel multiplier can only be updated once the
4932 * DPLL is enabled and the clocks are stable.
4933 *
4934 * So write it again.
4935 */
4936 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4937 }
4938
4939 intel_crtc->lowfreq_avail = false;
4940 if (intel_crtc->pch_pll) {
4941 if (is_lvds && has_reduced_clock && i915_powersave) {
4942 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4943 intel_crtc->lowfreq_avail = true;
4944 } else {
4945 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4946 }
4947 }
4948
4949 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4950 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4951 pipeconf |= PIPECONF_INTERLACED_ILK;
4952 /* the chip adds 2 halflines automatically */
4953 adjusted_mode->crtc_vtotal -= 1;
4954 adjusted_mode->crtc_vblank_end -= 1;
4955 I915_WRITE(VSYNCSHIFT(pipe),
4956 adjusted_mode->crtc_hsync_start
4957 - adjusted_mode->crtc_htotal/2);
4958 } else {
4959 pipeconf |= PIPECONF_PROGRESSIVE;
4960 I915_WRITE(VSYNCSHIFT(pipe), 0);
4961 }
4962
4963 I915_WRITE(HTOTAL(pipe),
4964 (adjusted_mode->crtc_hdisplay - 1) |
4965 ((adjusted_mode->crtc_htotal - 1) << 16));
4966 I915_WRITE(HBLANK(pipe),
4967 (adjusted_mode->crtc_hblank_start - 1) |
4968 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4969 I915_WRITE(HSYNC(pipe),
4970 (adjusted_mode->crtc_hsync_start - 1) |
4971 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4972
4973 I915_WRITE(VTOTAL(pipe),
4974 (adjusted_mode->crtc_vdisplay - 1) |
4975 ((adjusted_mode->crtc_vtotal - 1) << 16));
4976 I915_WRITE(VBLANK(pipe),
4977 (adjusted_mode->crtc_vblank_start - 1) |
4978 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4979 I915_WRITE(VSYNC(pipe),
4980 (adjusted_mode->crtc_vsync_start - 1) |
4981 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4982
4983 /* pipesrc controls the size that is scaled from, which should
4984 * always be the user's requested size.
4985 */
4986 I915_WRITE(PIPESRC(pipe),
4987 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4988
4989 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4990 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4991 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4992 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4993
4994 if (is_cpu_edp)
4995 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4996
4997 I915_WRITE(PIPECONF(pipe), pipeconf);
4998 POSTING_READ(PIPECONF(pipe));
4999
5000 intel_wait_for_vblank(dev, pipe);
5001
5002 I915_WRITE(DSPCNTR(plane), dspcntr);
5003 POSTING_READ(DSPCNTR(plane));
5004
5005 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5006
5007 intel_update_watermarks(dev);
5008
5009 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5010
5011 return ret;
5012 }
5013
5014 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5015 struct drm_display_mode *mode,
5016 struct drm_display_mode *adjusted_mode,
5017 int x, int y,
5018 struct drm_framebuffer *old_fb)
5019 {
5020 struct drm_device *dev = crtc->dev;
5021 struct drm_i915_private *dev_priv = dev->dev_private;
5022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5023 int pipe = intel_crtc->pipe;
5024 int ret;
5025
5026 drm_vblank_pre_modeset(dev, pipe);
5027
5028 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5029 x, y, old_fb);
5030 drm_vblank_post_modeset(dev, pipe);
5031
5032 return ret;
5033 }
5034
5035 static bool intel_eld_uptodate(struct drm_connector *connector,
5036 int reg_eldv, uint32_t bits_eldv,
5037 int reg_elda, uint32_t bits_elda,
5038 int reg_edid)
5039 {
5040 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5041 uint8_t *eld = connector->eld;
5042 uint32_t i;
5043
5044 i = I915_READ(reg_eldv);
5045 i &= bits_eldv;
5046
5047 if (!eld[0])
5048 return !i;
5049
5050 if (!i)
5051 return false;
5052
5053 i = I915_READ(reg_elda);
5054 i &= ~bits_elda;
5055 I915_WRITE(reg_elda, i);
5056
5057 for (i = 0; i < eld[2]; i++)
5058 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5059 return false;
5060
5061 return true;
5062 }
5063
5064 static void g4x_write_eld(struct drm_connector *connector,
5065 struct drm_crtc *crtc)
5066 {
5067 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5068 uint8_t *eld = connector->eld;
5069 uint32_t eldv;
5070 uint32_t len;
5071 uint32_t i;
5072
5073 i = I915_READ(G4X_AUD_VID_DID);
5074
5075 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5076 eldv = G4X_ELDV_DEVCL_DEVBLC;
5077 else
5078 eldv = G4X_ELDV_DEVCTG;
5079
5080 if (intel_eld_uptodate(connector,
5081 G4X_AUD_CNTL_ST, eldv,
5082 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5083 G4X_HDMIW_HDMIEDID))
5084 return;
5085
5086 i = I915_READ(G4X_AUD_CNTL_ST);
5087 i &= ~(eldv | G4X_ELD_ADDR);
5088 len = (i >> 9) & 0x1f; /* ELD buffer size */
5089 I915_WRITE(G4X_AUD_CNTL_ST, i);
5090
5091 if (!eld[0])
5092 return;
5093
5094 len = min_t(uint8_t, eld[2], len);
5095 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5096 for (i = 0; i < len; i++)
5097 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5098
5099 i = I915_READ(G4X_AUD_CNTL_ST);
5100 i |= eldv;
5101 I915_WRITE(G4X_AUD_CNTL_ST, i);
5102 }
5103
5104 static void haswell_write_eld(struct drm_connector *connector,
5105 struct drm_crtc *crtc)
5106 {
5107 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5108 uint8_t *eld = connector->eld;
5109 struct drm_device *dev = crtc->dev;
5110 uint32_t eldv;
5111 uint32_t i;
5112 int len;
5113 int pipe = to_intel_crtc(crtc)->pipe;
5114 int tmp;
5115
5116 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5117 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5118 int aud_config = HSW_AUD_CFG(pipe);
5119 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5120
5121
5122 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5123
5124 /* Audio output enable */
5125 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5126 tmp = I915_READ(aud_cntrl_st2);
5127 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5128 I915_WRITE(aud_cntrl_st2, tmp);
5129
5130 /* Wait for 1 vertical blank */
5131 intel_wait_for_vblank(dev, pipe);
5132
5133 /* Set ELD valid state */
5134 tmp = I915_READ(aud_cntrl_st2);
5135 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5136 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5137 I915_WRITE(aud_cntrl_st2, tmp);
5138 tmp = I915_READ(aud_cntrl_st2);
5139 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5140
5141 /* Enable HDMI mode */
5142 tmp = I915_READ(aud_config);
5143 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5144 /* clear N_programing_enable and N_value_index */
5145 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5146 I915_WRITE(aud_config, tmp);
5147
5148 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5149
5150 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5151
5152 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5153 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5154 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5155 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5156 } else
5157 I915_WRITE(aud_config, 0);
5158
5159 if (intel_eld_uptodate(connector,
5160 aud_cntrl_st2, eldv,
5161 aud_cntl_st, IBX_ELD_ADDRESS,
5162 hdmiw_hdmiedid))
5163 return;
5164
5165 i = I915_READ(aud_cntrl_st2);
5166 i &= ~eldv;
5167 I915_WRITE(aud_cntrl_st2, i);
5168
5169 if (!eld[0])
5170 return;
5171
5172 i = I915_READ(aud_cntl_st);
5173 i &= ~IBX_ELD_ADDRESS;
5174 I915_WRITE(aud_cntl_st, i);
5175 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5176 DRM_DEBUG_DRIVER("port num:%d\n", i);
5177
5178 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5179 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5180 for (i = 0; i < len; i++)
5181 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5182
5183 i = I915_READ(aud_cntrl_st2);
5184 i |= eldv;
5185 I915_WRITE(aud_cntrl_st2, i);
5186
5187 }
5188
5189 static void ironlake_write_eld(struct drm_connector *connector,
5190 struct drm_crtc *crtc)
5191 {
5192 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5193 uint8_t *eld = connector->eld;
5194 uint32_t eldv;
5195 uint32_t i;
5196 int len;
5197 int hdmiw_hdmiedid;
5198 int aud_config;
5199 int aud_cntl_st;
5200 int aud_cntrl_st2;
5201 int pipe = to_intel_crtc(crtc)->pipe;
5202
5203 if (HAS_PCH_IBX(connector->dev)) {
5204 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5205 aud_config = IBX_AUD_CFG(pipe);
5206 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5207 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5208 } else {
5209 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5210 aud_config = CPT_AUD_CFG(pipe);
5211 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5212 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5213 }
5214
5215 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5216
5217 i = I915_READ(aud_cntl_st);
5218 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5219 if (!i) {
5220 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5221 /* operate blindly on all ports */
5222 eldv = IBX_ELD_VALIDB;
5223 eldv |= IBX_ELD_VALIDB << 4;
5224 eldv |= IBX_ELD_VALIDB << 8;
5225 } else {
5226 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5227 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5228 }
5229
5230 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5231 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5232 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5233 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5234 } else
5235 I915_WRITE(aud_config, 0);
5236
5237 if (intel_eld_uptodate(connector,
5238 aud_cntrl_st2, eldv,
5239 aud_cntl_st, IBX_ELD_ADDRESS,
5240 hdmiw_hdmiedid))
5241 return;
5242
5243 i = I915_READ(aud_cntrl_st2);
5244 i &= ~eldv;
5245 I915_WRITE(aud_cntrl_st2, i);
5246
5247 if (!eld[0])
5248 return;
5249
5250 i = I915_READ(aud_cntl_st);
5251 i &= ~IBX_ELD_ADDRESS;
5252 I915_WRITE(aud_cntl_st, i);
5253
5254 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5255 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5256 for (i = 0; i < len; i++)
5257 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5258
5259 i = I915_READ(aud_cntrl_st2);
5260 i |= eldv;
5261 I915_WRITE(aud_cntrl_st2, i);
5262 }
5263
5264 void intel_write_eld(struct drm_encoder *encoder,
5265 struct drm_display_mode *mode)
5266 {
5267 struct drm_crtc *crtc = encoder->crtc;
5268 struct drm_connector *connector;
5269 struct drm_device *dev = encoder->dev;
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272 connector = drm_select_eld(encoder, mode);
5273 if (!connector)
5274 return;
5275
5276 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5277 connector->base.id,
5278 drm_get_connector_name(connector),
5279 connector->encoder->base.id,
5280 drm_get_encoder_name(connector->encoder));
5281
5282 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5283
5284 if (dev_priv->display.write_eld)
5285 dev_priv->display.write_eld(connector, crtc);
5286 }
5287
5288 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5289 void intel_crtc_load_lut(struct drm_crtc *crtc)
5290 {
5291 struct drm_device *dev = crtc->dev;
5292 struct drm_i915_private *dev_priv = dev->dev_private;
5293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5294 int palreg = PALETTE(intel_crtc->pipe);
5295 int i;
5296
5297 /* The clocks have to be on to load the palette. */
5298 if (!crtc->enabled || !intel_crtc->active)
5299 return;
5300
5301 /* use legacy palette for Ironlake */
5302 if (HAS_PCH_SPLIT(dev))
5303 palreg = LGC_PALETTE(intel_crtc->pipe);
5304
5305 for (i = 0; i < 256; i++) {
5306 I915_WRITE(palreg + 4 * i,
5307 (intel_crtc->lut_r[i] << 16) |
5308 (intel_crtc->lut_g[i] << 8) |
5309 intel_crtc->lut_b[i]);
5310 }
5311 }
5312
5313 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5314 {
5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 bool visible = base != 0;
5319 u32 cntl;
5320
5321 if (intel_crtc->cursor_visible == visible)
5322 return;
5323
5324 cntl = I915_READ(_CURACNTR);
5325 if (visible) {
5326 /* On these chipsets we can only modify the base whilst
5327 * the cursor is disabled.
5328 */
5329 I915_WRITE(_CURABASE, base);
5330
5331 cntl &= ~(CURSOR_FORMAT_MASK);
5332 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5333 cntl |= CURSOR_ENABLE |
5334 CURSOR_GAMMA_ENABLE |
5335 CURSOR_FORMAT_ARGB;
5336 } else
5337 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5338 I915_WRITE(_CURACNTR, cntl);
5339
5340 intel_crtc->cursor_visible = visible;
5341 }
5342
5343 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5344 {
5345 struct drm_device *dev = crtc->dev;
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 int pipe = intel_crtc->pipe;
5349 bool visible = base != 0;
5350
5351 if (intel_crtc->cursor_visible != visible) {
5352 uint32_t cntl = I915_READ(CURCNTR(pipe));
5353 if (base) {
5354 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5355 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5356 cntl |= pipe << 28; /* Connect to correct pipe */
5357 } else {
5358 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5359 cntl |= CURSOR_MODE_DISABLE;
5360 }
5361 I915_WRITE(CURCNTR(pipe), cntl);
5362
5363 intel_crtc->cursor_visible = visible;
5364 }
5365 /* and commit changes on next vblank */
5366 I915_WRITE(CURBASE(pipe), base);
5367 }
5368
5369 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5370 {
5371 struct drm_device *dev = crtc->dev;
5372 struct drm_i915_private *dev_priv = dev->dev_private;
5373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5374 int pipe = intel_crtc->pipe;
5375 bool visible = base != 0;
5376
5377 if (intel_crtc->cursor_visible != visible) {
5378 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5379 if (base) {
5380 cntl &= ~CURSOR_MODE;
5381 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5382 } else {
5383 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5384 cntl |= CURSOR_MODE_DISABLE;
5385 }
5386 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5387
5388 intel_crtc->cursor_visible = visible;
5389 }
5390 /* and commit changes on next vblank */
5391 I915_WRITE(CURBASE_IVB(pipe), base);
5392 }
5393
5394 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5395 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5396 bool on)
5397 {
5398 struct drm_device *dev = crtc->dev;
5399 struct drm_i915_private *dev_priv = dev->dev_private;
5400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5401 int pipe = intel_crtc->pipe;
5402 int x = intel_crtc->cursor_x;
5403 int y = intel_crtc->cursor_y;
5404 u32 base, pos;
5405 bool visible;
5406
5407 pos = 0;
5408
5409 if (on && crtc->enabled && crtc->fb) {
5410 base = intel_crtc->cursor_addr;
5411 if (x > (int) crtc->fb->width)
5412 base = 0;
5413
5414 if (y > (int) crtc->fb->height)
5415 base = 0;
5416 } else
5417 base = 0;
5418
5419 if (x < 0) {
5420 if (x + intel_crtc->cursor_width < 0)
5421 base = 0;
5422
5423 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5424 x = -x;
5425 }
5426 pos |= x << CURSOR_X_SHIFT;
5427
5428 if (y < 0) {
5429 if (y + intel_crtc->cursor_height < 0)
5430 base = 0;
5431
5432 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5433 y = -y;
5434 }
5435 pos |= y << CURSOR_Y_SHIFT;
5436
5437 visible = base != 0;
5438 if (!visible && !intel_crtc->cursor_visible)
5439 return;
5440
5441 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5442 I915_WRITE(CURPOS_IVB(pipe), pos);
5443 ivb_update_cursor(crtc, base);
5444 } else {
5445 I915_WRITE(CURPOS(pipe), pos);
5446 if (IS_845G(dev) || IS_I865G(dev))
5447 i845_update_cursor(crtc, base);
5448 else
5449 i9xx_update_cursor(crtc, base);
5450 }
5451 }
5452
5453 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5454 struct drm_file *file,
5455 uint32_t handle,
5456 uint32_t width, uint32_t height)
5457 {
5458 struct drm_device *dev = crtc->dev;
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5461 struct drm_i915_gem_object *obj;
5462 uint32_t addr;
5463 int ret;
5464
5465 DRM_DEBUG_KMS("\n");
5466
5467 /* if we want to turn off the cursor ignore width and height */
5468 if (!handle) {
5469 DRM_DEBUG_KMS("cursor off\n");
5470 addr = 0;
5471 obj = NULL;
5472 mutex_lock(&dev->struct_mutex);
5473 goto finish;
5474 }
5475
5476 /* Currently we only support 64x64 cursors */
5477 if (width != 64 || height != 64) {
5478 DRM_ERROR("we currently only support 64x64 cursors\n");
5479 return -EINVAL;
5480 }
5481
5482 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5483 if (&obj->base == NULL)
5484 return -ENOENT;
5485
5486 if (obj->base.size < width * height * 4) {
5487 DRM_ERROR("buffer is to small\n");
5488 ret = -ENOMEM;
5489 goto fail;
5490 }
5491
5492 /* we only need to pin inside GTT if cursor is non-phy */
5493 mutex_lock(&dev->struct_mutex);
5494 if (!dev_priv->info->cursor_needs_physical) {
5495 if (obj->tiling_mode) {
5496 DRM_ERROR("cursor cannot be tiled\n");
5497 ret = -EINVAL;
5498 goto fail_locked;
5499 }
5500
5501 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5502 if (ret) {
5503 DRM_ERROR("failed to move cursor bo into the GTT\n");
5504 goto fail_locked;
5505 }
5506
5507 ret = i915_gem_object_put_fence(obj);
5508 if (ret) {
5509 DRM_ERROR("failed to release fence for cursor");
5510 goto fail_unpin;
5511 }
5512
5513 addr = obj->gtt_offset;
5514 } else {
5515 int align = IS_I830(dev) ? 16 * 1024 : 256;
5516 ret = i915_gem_attach_phys_object(dev, obj,
5517 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5518 align);
5519 if (ret) {
5520 DRM_ERROR("failed to attach phys object\n");
5521 goto fail_locked;
5522 }
5523 addr = obj->phys_obj->handle->busaddr;
5524 }
5525
5526 if (IS_GEN2(dev))
5527 I915_WRITE(CURSIZE, (height << 12) | width);
5528
5529 finish:
5530 if (intel_crtc->cursor_bo) {
5531 if (dev_priv->info->cursor_needs_physical) {
5532 if (intel_crtc->cursor_bo != obj)
5533 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5534 } else
5535 i915_gem_object_unpin(intel_crtc->cursor_bo);
5536 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5537 }
5538
5539 mutex_unlock(&dev->struct_mutex);
5540
5541 intel_crtc->cursor_addr = addr;
5542 intel_crtc->cursor_bo = obj;
5543 intel_crtc->cursor_width = width;
5544 intel_crtc->cursor_height = height;
5545
5546 intel_crtc_update_cursor(crtc, true);
5547
5548 return 0;
5549 fail_unpin:
5550 i915_gem_object_unpin(obj);
5551 fail_locked:
5552 mutex_unlock(&dev->struct_mutex);
5553 fail:
5554 drm_gem_object_unreference_unlocked(&obj->base);
5555 return ret;
5556 }
5557
5558 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5559 {
5560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5561
5562 intel_crtc->cursor_x = x;
5563 intel_crtc->cursor_y = y;
5564
5565 intel_crtc_update_cursor(crtc, true);
5566
5567 return 0;
5568 }
5569
5570 /** Sets the color ramps on behalf of RandR */
5571 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5572 u16 blue, int regno)
5573 {
5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575
5576 intel_crtc->lut_r[regno] = red >> 8;
5577 intel_crtc->lut_g[regno] = green >> 8;
5578 intel_crtc->lut_b[regno] = blue >> 8;
5579 }
5580
5581 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5582 u16 *blue, int regno)
5583 {
5584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5585
5586 *red = intel_crtc->lut_r[regno] << 8;
5587 *green = intel_crtc->lut_g[regno] << 8;
5588 *blue = intel_crtc->lut_b[regno] << 8;
5589 }
5590
5591 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5592 u16 *blue, uint32_t start, uint32_t size)
5593 {
5594 int end = (start + size > 256) ? 256 : start + size, i;
5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596
5597 for (i = start; i < end; i++) {
5598 intel_crtc->lut_r[i] = red[i] >> 8;
5599 intel_crtc->lut_g[i] = green[i] >> 8;
5600 intel_crtc->lut_b[i] = blue[i] >> 8;
5601 }
5602
5603 intel_crtc_load_lut(crtc);
5604 }
5605
5606 /**
5607 * Get a pipe with a simple mode set on it for doing load-based monitor
5608 * detection.
5609 *
5610 * It will be up to the load-detect code to adjust the pipe as appropriate for
5611 * its requirements. The pipe will be connected to no other encoders.
5612 *
5613 * Currently this code will only succeed if there is a pipe with no encoders
5614 * configured for it. In the future, it could choose to temporarily disable
5615 * some outputs to free up a pipe for its use.
5616 *
5617 * \return crtc, or NULL if no pipes are available.
5618 */
5619
5620 /* VESA 640x480x72Hz mode to set on the pipe */
5621 static struct drm_display_mode load_detect_mode = {
5622 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5623 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5624 };
5625
5626 static struct drm_framebuffer *
5627 intel_framebuffer_create(struct drm_device *dev,
5628 struct drm_mode_fb_cmd2 *mode_cmd,
5629 struct drm_i915_gem_object *obj)
5630 {
5631 struct intel_framebuffer *intel_fb;
5632 int ret;
5633
5634 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5635 if (!intel_fb) {
5636 drm_gem_object_unreference_unlocked(&obj->base);
5637 return ERR_PTR(-ENOMEM);
5638 }
5639
5640 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5641 if (ret) {
5642 drm_gem_object_unreference_unlocked(&obj->base);
5643 kfree(intel_fb);
5644 return ERR_PTR(ret);
5645 }
5646
5647 return &intel_fb->base;
5648 }
5649
5650 static u32
5651 intel_framebuffer_pitch_for_width(int width, int bpp)
5652 {
5653 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5654 return ALIGN(pitch, 64);
5655 }
5656
5657 static u32
5658 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5659 {
5660 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5661 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5662 }
5663
5664 static struct drm_framebuffer *
5665 intel_framebuffer_create_for_mode(struct drm_device *dev,
5666 struct drm_display_mode *mode,
5667 int depth, int bpp)
5668 {
5669 struct drm_i915_gem_object *obj;
5670 struct drm_mode_fb_cmd2 mode_cmd;
5671
5672 obj = i915_gem_alloc_object(dev,
5673 intel_framebuffer_size_for_mode(mode, bpp));
5674 if (obj == NULL)
5675 return ERR_PTR(-ENOMEM);
5676
5677 mode_cmd.width = mode->hdisplay;
5678 mode_cmd.height = mode->vdisplay;
5679 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5680 bpp);
5681 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5682
5683 return intel_framebuffer_create(dev, &mode_cmd, obj);
5684 }
5685
5686 static struct drm_framebuffer *
5687 mode_fits_in_fbdev(struct drm_device *dev,
5688 struct drm_display_mode *mode)
5689 {
5690 struct drm_i915_private *dev_priv = dev->dev_private;
5691 struct drm_i915_gem_object *obj;
5692 struct drm_framebuffer *fb;
5693
5694 if (dev_priv->fbdev == NULL)
5695 return NULL;
5696
5697 obj = dev_priv->fbdev->ifb.obj;
5698 if (obj == NULL)
5699 return NULL;
5700
5701 fb = &dev_priv->fbdev->ifb.base;
5702 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5703 fb->bits_per_pixel))
5704 return NULL;
5705
5706 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5707 return NULL;
5708
5709 return fb;
5710 }
5711
5712 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5713 struct drm_display_mode *mode,
5714 struct intel_load_detect_pipe *old)
5715 {
5716 struct intel_crtc *intel_crtc;
5717 struct intel_encoder *intel_encoder =
5718 intel_attached_encoder(connector);
5719 struct drm_crtc *possible_crtc;
5720 struct drm_encoder *encoder = &intel_encoder->base;
5721 struct drm_crtc *crtc = NULL;
5722 struct drm_device *dev = encoder->dev;
5723 struct drm_framebuffer *old_fb;
5724 int i = -1;
5725
5726 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5727 connector->base.id, drm_get_connector_name(connector),
5728 encoder->base.id, drm_get_encoder_name(encoder));
5729
5730 /*
5731 * Algorithm gets a little messy:
5732 *
5733 * - if the connector already has an assigned crtc, use it (but make
5734 * sure it's on first)
5735 *
5736 * - try to find the first unused crtc that can drive this connector,
5737 * and use that if we find one
5738 */
5739
5740 /* See if we already have a CRTC for this connector */
5741 if (encoder->crtc) {
5742 crtc = encoder->crtc;
5743
5744 old->dpms_mode = connector->dpms;
5745 old->load_detect_temp = false;
5746
5747 /* Make sure the crtc and connector are running */
5748 if (connector->dpms != DRM_MODE_DPMS_ON)
5749 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5750
5751 return true;
5752 }
5753
5754 /* Find an unused one (if possible) */
5755 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5756 i++;
5757 if (!(encoder->possible_crtcs & (1 << i)))
5758 continue;
5759 if (!possible_crtc->enabled) {
5760 crtc = possible_crtc;
5761 break;
5762 }
5763 }
5764
5765 /*
5766 * If we didn't find an unused CRTC, don't use any.
5767 */
5768 if (!crtc) {
5769 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5770 return false;
5771 }
5772
5773 encoder->crtc = crtc;
5774 connector->encoder = encoder;
5775
5776 intel_crtc = to_intel_crtc(crtc);
5777 old->dpms_mode = connector->dpms;
5778 old->load_detect_temp = true;
5779 old->release_fb = NULL;
5780
5781 if (!mode)
5782 mode = &load_detect_mode;
5783
5784 old_fb = crtc->fb;
5785
5786 /* We need a framebuffer large enough to accommodate all accesses
5787 * that the plane may generate whilst we perform load detection.
5788 * We can not rely on the fbcon either being present (we get called
5789 * during its initialisation to detect all boot displays, or it may
5790 * not even exist) or that it is large enough to satisfy the
5791 * requested mode.
5792 */
5793 crtc->fb = mode_fits_in_fbdev(dev, mode);
5794 if (crtc->fb == NULL) {
5795 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5796 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5797 old->release_fb = crtc->fb;
5798 } else
5799 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5800 if (IS_ERR(crtc->fb)) {
5801 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5802 goto fail;
5803 }
5804
5805 if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
5806 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5807 if (old->release_fb)
5808 old->release_fb->funcs->destroy(old->release_fb);
5809 goto fail;
5810 }
5811
5812 /* let the connector get through one full cycle before testing */
5813 intel_wait_for_vblank(dev, intel_crtc->pipe);
5814
5815 return true;
5816 fail:
5817 connector->encoder = NULL;
5818 encoder->crtc = NULL;
5819 crtc->fb = old_fb;
5820 return false;
5821 }
5822
5823 void intel_release_load_detect_pipe(struct drm_connector *connector,
5824 struct intel_load_detect_pipe *old)
5825 {
5826 struct intel_encoder *intel_encoder =
5827 intel_attached_encoder(connector);
5828 struct drm_encoder *encoder = &intel_encoder->base;
5829 struct drm_device *dev = encoder->dev;
5830
5831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5832 connector->base.id, drm_get_connector_name(connector),
5833 encoder->base.id, drm_get_encoder_name(encoder));
5834
5835 if (old->load_detect_temp) {
5836 connector->encoder = NULL;
5837 encoder->crtc = NULL;
5838 drm_helper_disable_unused_functions(dev);
5839
5840 if (old->release_fb)
5841 old->release_fb->funcs->destroy(old->release_fb);
5842
5843 return;
5844 }
5845
5846 /* Switch crtc and encoder back off if necessary */
5847 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5848 connector->funcs->dpms(connector, old->dpms_mode);
5849 }
5850
5851 /* Returns the clock of the currently programmed mode of the given pipe. */
5852 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5853 {
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856 int pipe = intel_crtc->pipe;
5857 u32 dpll = I915_READ(DPLL(pipe));
5858 u32 fp;
5859 intel_clock_t clock;
5860
5861 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5862 fp = I915_READ(FP0(pipe));
5863 else
5864 fp = I915_READ(FP1(pipe));
5865
5866 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5867 if (IS_PINEVIEW(dev)) {
5868 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5869 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5870 } else {
5871 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5872 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5873 }
5874
5875 if (!IS_GEN2(dev)) {
5876 if (IS_PINEVIEW(dev))
5877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5878 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5879 else
5880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5881 DPLL_FPA01_P1_POST_DIV_SHIFT);
5882
5883 switch (dpll & DPLL_MODE_MASK) {
5884 case DPLLB_MODE_DAC_SERIAL:
5885 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5886 5 : 10;
5887 break;
5888 case DPLLB_MODE_LVDS:
5889 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5890 7 : 14;
5891 break;
5892 default:
5893 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5894 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5895 return 0;
5896 }
5897
5898 /* XXX: Handle the 100Mhz refclk */
5899 intel_clock(dev, 96000, &clock);
5900 } else {
5901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5902
5903 if (is_lvds) {
5904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5905 DPLL_FPA01_P1_POST_DIV_SHIFT);
5906 clock.p2 = 14;
5907
5908 if ((dpll & PLL_REF_INPUT_MASK) ==
5909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5910 /* XXX: might not be 66MHz */
5911 intel_clock(dev, 66000, &clock);
5912 } else
5913 intel_clock(dev, 48000, &clock);
5914 } else {
5915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5916 clock.p1 = 2;
5917 else {
5918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5920 }
5921 if (dpll & PLL_P2_DIVIDE_BY_4)
5922 clock.p2 = 4;
5923 else
5924 clock.p2 = 2;
5925
5926 intel_clock(dev, 48000, &clock);
5927 }
5928 }
5929
5930 /* XXX: It would be nice to validate the clocks, but we can't reuse
5931 * i830PllIsValid() because it relies on the xf86_config connector
5932 * configuration being accurate, which it isn't necessarily.
5933 */
5934
5935 return clock.dot;
5936 }
5937
5938 /** Returns the currently programmed mode of the given pipe. */
5939 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5940 struct drm_crtc *crtc)
5941 {
5942 struct drm_i915_private *dev_priv = dev->dev_private;
5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944 int pipe = intel_crtc->pipe;
5945 struct drm_display_mode *mode;
5946 int htot = I915_READ(HTOTAL(pipe));
5947 int hsync = I915_READ(HSYNC(pipe));
5948 int vtot = I915_READ(VTOTAL(pipe));
5949 int vsync = I915_READ(VSYNC(pipe));
5950
5951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5952 if (!mode)
5953 return NULL;
5954
5955 mode->clock = intel_crtc_clock_get(dev, crtc);
5956 mode->hdisplay = (htot & 0xffff) + 1;
5957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5958 mode->hsync_start = (hsync & 0xffff) + 1;
5959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5960 mode->vdisplay = (vtot & 0xffff) + 1;
5961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5962 mode->vsync_start = (vsync & 0xffff) + 1;
5963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5964
5965 drm_mode_set_name(mode);
5966
5967 return mode;
5968 }
5969
5970 static void intel_increase_pllclock(struct drm_crtc *crtc)
5971 {
5972 struct drm_device *dev = crtc->dev;
5973 drm_i915_private_t *dev_priv = dev->dev_private;
5974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5975 int pipe = intel_crtc->pipe;
5976 int dpll_reg = DPLL(pipe);
5977 int dpll;
5978
5979 if (HAS_PCH_SPLIT(dev))
5980 return;
5981
5982 if (!dev_priv->lvds_downclock_avail)
5983 return;
5984
5985 dpll = I915_READ(dpll_reg);
5986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5988
5989 assert_panel_unlocked(dev_priv, pipe);
5990
5991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5992 I915_WRITE(dpll_reg, dpll);
5993 intel_wait_for_vblank(dev, pipe);
5994
5995 dpll = I915_READ(dpll_reg);
5996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5998 }
5999 }
6000
6001 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6002 {
6003 struct drm_device *dev = crtc->dev;
6004 drm_i915_private_t *dev_priv = dev->dev_private;
6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6006
6007 if (HAS_PCH_SPLIT(dev))
6008 return;
6009
6010 if (!dev_priv->lvds_downclock_avail)
6011 return;
6012
6013 /*
6014 * Since this is called by a timer, we should never get here in
6015 * the manual case.
6016 */
6017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6018 int pipe = intel_crtc->pipe;
6019 int dpll_reg = DPLL(pipe);
6020 int dpll;
6021
6022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6023
6024 assert_panel_unlocked(dev_priv, pipe);
6025
6026 dpll = I915_READ(dpll_reg);
6027 dpll |= DISPLAY_RATE_SELECT_FPA1;
6028 I915_WRITE(dpll_reg, dpll);
6029 intel_wait_for_vblank(dev, pipe);
6030 dpll = I915_READ(dpll_reg);
6031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6033 }
6034
6035 }
6036
6037 void intel_mark_busy(struct drm_device *dev)
6038 {
6039 i915_update_gfx_val(dev->dev_private);
6040 }
6041
6042 void intel_mark_idle(struct drm_device *dev)
6043 {
6044 }
6045
6046 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6047 {
6048 struct drm_device *dev = obj->base.dev;
6049 struct drm_crtc *crtc;
6050
6051 if (!i915_powersave)
6052 return;
6053
6054 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6055 if (!crtc->fb)
6056 continue;
6057
6058 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6059 intel_increase_pllclock(crtc);
6060 }
6061 }
6062
6063 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6064 {
6065 struct drm_device *dev = obj->base.dev;
6066 struct drm_crtc *crtc;
6067
6068 if (!i915_powersave)
6069 return;
6070
6071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6072 if (!crtc->fb)
6073 continue;
6074
6075 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6076 intel_decrease_pllclock(crtc);
6077 }
6078 }
6079
6080 static void intel_crtc_destroy(struct drm_crtc *crtc)
6081 {
6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083 struct drm_device *dev = crtc->dev;
6084 struct intel_unpin_work *work;
6085 unsigned long flags;
6086
6087 spin_lock_irqsave(&dev->event_lock, flags);
6088 work = intel_crtc->unpin_work;
6089 intel_crtc->unpin_work = NULL;
6090 spin_unlock_irqrestore(&dev->event_lock, flags);
6091
6092 if (work) {
6093 cancel_work_sync(&work->work);
6094 kfree(work);
6095 }
6096
6097 drm_crtc_cleanup(crtc);
6098
6099 kfree(intel_crtc);
6100 }
6101
6102 static void intel_unpin_work_fn(struct work_struct *__work)
6103 {
6104 struct intel_unpin_work *work =
6105 container_of(__work, struct intel_unpin_work, work);
6106
6107 mutex_lock(&work->dev->struct_mutex);
6108 intel_unpin_fb_obj(work->old_fb_obj);
6109 drm_gem_object_unreference(&work->pending_flip_obj->base);
6110 drm_gem_object_unreference(&work->old_fb_obj->base);
6111
6112 intel_update_fbc(work->dev);
6113 mutex_unlock(&work->dev->struct_mutex);
6114 kfree(work);
6115 }
6116
6117 static void do_intel_finish_page_flip(struct drm_device *dev,
6118 struct drm_crtc *crtc)
6119 {
6120 drm_i915_private_t *dev_priv = dev->dev_private;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 struct intel_unpin_work *work;
6123 struct drm_i915_gem_object *obj;
6124 struct drm_pending_vblank_event *e;
6125 struct timeval tnow, tvbl;
6126 unsigned long flags;
6127
6128 /* Ignore early vblank irqs */
6129 if (intel_crtc == NULL)
6130 return;
6131
6132 do_gettimeofday(&tnow);
6133
6134 spin_lock_irqsave(&dev->event_lock, flags);
6135 work = intel_crtc->unpin_work;
6136 if (work == NULL || !work->pending) {
6137 spin_unlock_irqrestore(&dev->event_lock, flags);
6138 return;
6139 }
6140
6141 intel_crtc->unpin_work = NULL;
6142
6143 if (work->event) {
6144 e = work->event;
6145 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6146
6147 /* Called before vblank count and timestamps have
6148 * been updated for the vblank interval of flip
6149 * completion? Need to increment vblank count and
6150 * add one videorefresh duration to returned timestamp
6151 * to account for this. We assume this happened if we
6152 * get called over 0.9 frame durations after the last
6153 * timestamped vblank.
6154 *
6155 * This calculation can not be used with vrefresh rates
6156 * below 5Hz (10Hz to be on the safe side) without
6157 * promoting to 64 integers.
6158 */
6159 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6160 9 * crtc->framedur_ns) {
6161 e->event.sequence++;
6162 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6163 crtc->framedur_ns);
6164 }
6165
6166 e->event.tv_sec = tvbl.tv_sec;
6167 e->event.tv_usec = tvbl.tv_usec;
6168
6169 list_add_tail(&e->base.link,
6170 &e->base.file_priv->event_list);
6171 wake_up_interruptible(&e->base.file_priv->event_wait);
6172 }
6173
6174 drm_vblank_put(dev, intel_crtc->pipe);
6175
6176 spin_unlock_irqrestore(&dev->event_lock, flags);
6177
6178 obj = work->old_fb_obj;
6179
6180 atomic_clear_mask(1 << intel_crtc->plane,
6181 &obj->pending_flip.counter);
6182 if (atomic_read(&obj->pending_flip) == 0)
6183 wake_up(&dev_priv->pending_flip_queue);
6184
6185 schedule_work(&work->work);
6186
6187 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6188 }
6189
6190 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6191 {
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6193 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6194
6195 do_intel_finish_page_flip(dev, crtc);
6196 }
6197
6198 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6199 {
6200 drm_i915_private_t *dev_priv = dev->dev_private;
6201 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6202
6203 do_intel_finish_page_flip(dev, crtc);
6204 }
6205
6206 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6207 {
6208 drm_i915_private_t *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc =
6210 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6211 unsigned long flags;
6212
6213 spin_lock_irqsave(&dev->event_lock, flags);
6214 if (intel_crtc->unpin_work) {
6215 if ((++intel_crtc->unpin_work->pending) > 1)
6216 DRM_ERROR("Prepared flip multiple times\n");
6217 } else {
6218 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6219 }
6220 spin_unlock_irqrestore(&dev->event_lock, flags);
6221 }
6222
6223 static int intel_gen2_queue_flip(struct drm_device *dev,
6224 struct drm_crtc *crtc,
6225 struct drm_framebuffer *fb,
6226 struct drm_i915_gem_object *obj)
6227 {
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6230 u32 flip_mask;
6231 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6232 int ret;
6233
6234 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6235 if (ret)
6236 goto err;
6237
6238 ret = intel_ring_begin(ring, 6);
6239 if (ret)
6240 goto err_unpin;
6241
6242 /* Can't queue multiple flips, so wait for the previous
6243 * one to finish before executing the next.
6244 */
6245 if (intel_crtc->plane)
6246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6247 else
6248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250 intel_ring_emit(ring, MI_NOOP);
6251 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253 intel_ring_emit(ring, fb->pitches[0]);
6254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6255 intel_ring_emit(ring, 0); /* aux display base address, unused */
6256 intel_ring_advance(ring);
6257 return 0;
6258
6259 err_unpin:
6260 intel_unpin_fb_obj(obj);
6261 err:
6262 return ret;
6263 }
6264
6265 static int intel_gen3_queue_flip(struct drm_device *dev,
6266 struct drm_crtc *crtc,
6267 struct drm_framebuffer *fb,
6268 struct drm_i915_gem_object *obj)
6269 {
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 u32 flip_mask;
6273 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6274 int ret;
6275
6276 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6277 if (ret)
6278 goto err;
6279
6280 ret = intel_ring_begin(ring, 6);
6281 if (ret)
6282 goto err_unpin;
6283
6284 if (intel_crtc->plane)
6285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6286 else
6287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6289 intel_ring_emit(ring, MI_NOOP);
6290 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292 intel_ring_emit(ring, fb->pitches[0]);
6293 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6294 intel_ring_emit(ring, MI_NOOP);
6295
6296 intel_ring_advance(ring);
6297 return 0;
6298
6299 err_unpin:
6300 intel_unpin_fb_obj(obj);
6301 err:
6302 return ret;
6303 }
6304
6305 static int intel_gen4_queue_flip(struct drm_device *dev,
6306 struct drm_crtc *crtc,
6307 struct drm_framebuffer *fb,
6308 struct drm_i915_gem_object *obj)
6309 {
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 uint32_t pf, pipesrc;
6313 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6314 int ret;
6315
6316 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6317 if (ret)
6318 goto err;
6319
6320 ret = intel_ring_begin(ring, 4);
6321 if (ret)
6322 goto err_unpin;
6323
6324 /* i965+ uses the linear or tiled offsets from the
6325 * Display Registers (which do not change across a page-flip)
6326 * so we need only reprogram the base address.
6327 */
6328 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6330 intel_ring_emit(ring, fb->pitches[0]);
6331 intel_ring_emit(ring,
6332 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6333 obj->tiling_mode);
6334
6335 /* XXX Enabling the panel-fitter across page-flip is so far
6336 * untested on non-native modes, so ignore it for now.
6337 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6338 */
6339 pf = 0;
6340 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6341 intel_ring_emit(ring, pf | pipesrc);
6342 intel_ring_advance(ring);
6343 return 0;
6344
6345 err_unpin:
6346 intel_unpin_fb_obj(obj);
6347 err:
6348 return ret;
6349 }
6350
6351 static int intel_gen6_queue_flip(struct drm_device *dev,
6352 struct drm_crtc *crtc,
6353 struct drm_framebuffer *fb,
6354 struct drm_i915_gem_object *obj)
6355 {
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6358 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6359 uint32_t pf, pipesrc;
6360 int ret;
6361
6362 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6363 if (ret)
6364 goto err;
6365
6366 ret = intel_ring_begin(ring, 4);
6367 if (ret)
6368 goto err_unpin;
6369
6370 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6371 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6372 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6373 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6374
6375 /* Contrary to the suggestions in the documentation,
6376 * "Enable Panel Fitter" does not seem to be required when page
6377 * flipping with a non-native mode, and worse causes a normal
6378 * modeset to fail.
6379 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6380 */
6381 pf = 0;
6382 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6383 intel_ring_emit(ring, pf | pipesrc);
6384 intel_ring_advance(ring);
6385 return 0;
6386
6387 err_unpin:
6388 intel_unpin_fb_obj(obj);
6389 err:
6390 return ret;
6391 }
6392
6393 /*
6394 * On gen7 we currently use the blit ring because (in early silicon at least)
6395 * the render ring doesn't give us interrpts for page flip completion, which
6396 * means clients will hang after the first flip is queued. Fortunately the
6397 * blit ring generates interrupts properly, so use it instead.
6398 */
6399 static int intel_gen7_queue_flip(struct drm_device *dev,
6400 struct drm_crtc *crtc,
6401 struct drm_framebuffer *fb,
6402 struct drm_i915_gem_object *obj)
6403 {
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6407 uint32_t plane_bit = 0;
6408 int ret;
6409
6410 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6411 if (ret)
6412 goto err;
6413
6414 switch(intel_crtc->plane) {
6415 case PLANE_A:
6416 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6417 break;
6418 case PLANE_B:
6419 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6420 break;
6421 case PLANE_C:
6422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6423 break;
6424 default:
6425 WARN_ONCE(1, "unknown plane in flip command\n");
6426 ret = -ENODEV;
6427 goto err_unpin;
6428 }
6429
6430 ret = intel_ring_begin(ring, 4);
6431 if (ret)
6432 goto err_unpin;
6433
6434 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6435 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6436 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6437 intel_ring_emit(ring, (MI_NOOP));
6438 intel_ring_advance(ring);
6439 return 0;
6440
6441 err_unpin:
6442 intel_unpin_fb_obj(obj);
6443 err:
6444 return ret;
6445 }
6446
6447 static int intel_default_queue_flip(struct drm_device *dev,
6448 struct drm_crtc *crtc,
6449 struct drm_framebuffer *fb,
6450 struct drm_i915_gem_object *obj)
6451 {
6452 return -ENODEV;
6453 }
6454
6455 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6456 struct drm_framebuffer *fb,
6457 struct drm_pending_vblank_event *event)
6458 {
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_framebuffer *intel_fb;
6462 struct drm_i915_gem_object *obj;
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 struct intel_unpin_work *work;
6465 unsigned long flags;
6466 int ret;
6467
6468 /* Can't change pixel format via MI display flips. */
6469 if (fb->pixel_format != crtc->fb->pixel_format)
6470 return -EINVAL;
6471
6472 /*
6473 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6474 * Note that pitch changes could also affect these register.
6475 */
6476 if (INTEL_INFO(dev)->gen > 3 &&
6477 (fb->offsets[0] != crtc->fb->offsets[0] ||
6478 fb->pitches[0] != crtc->fb->pitches[0]))
6479 return -EINVAL;
6480
6481 work = kzalloc(sizeof *work, GFP_KERNEL);
6482 if (work == NULL)
6483 return -ENOMEM;
6484
6485 work->event = event;
6486 work->dev = crtc->dev;
6487 intel_fb = to_intel_framebuffer(crtc->fb);
6488 work->old_fb_obj = intel_fb->obj;
6489 INIT_WORK(&work->work, intel_unpin_work_fn);
6490
6491 ret = drm_vblank_get(dev, intel_crtc->pipe);
6492 if (ret)
6493 goto free_work;
6494
6495 /* We borrow the event spin lock for protecting unpin_work */
6496 spin_lock_irqsave(&dev->event_lock, flags);
6497 if (intel_crtc->unpin_work) {
6498 spin_unlock_irqrestore(&dev->event_lock, flags);
6499 kfree(work);
6500 drm_vblank_put(dev, intel_crtc->pipe);
6501
6502 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6503 return -EBUSY;
6504 }
6505 intel_crtc->unpin_work = work;
6506 spin_unlock_irqrestore(&dev->event_lock, flags);
6507
6508 intel_fb = to_intel_framebuffer(fb);
6509 obj = intel_fb->obj;
6510
6511 ret = i915_mutex_lock_interruptible(dev);
6512 if (ret)
6513 goto cleanup;
6514
6515 /* Reference the objects for the scheduled work. */
6516 drm_gem_object_reference(&work->old_fb_obj->base);
6517 drm_gem_object_reference(&obj->base);
6518
6519 crtc->fb = fb;
6520
6521 work->pending_flip_obj = obj;
6522
6523 work->enable_stall_check = true;
6524
6525 /* Block clients from rendering to the new back buffer until
6526 * the flip occurs and the object is no longer visible.
6527 */
6528 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6529
6530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6531 if (ret)
6532 goto cleanup_pending;
6533
6534 intel_disable_fbc(dev);
6535 intel_mark_fb_busy(obj);
6536 mutex_unlock(&dev->struct_mutex);
6537
6538 trace_i915_flip_request(intel_crtc->plane, obj);
6539
6540 return 0;
6541
6542 cleanup_pending:
6543 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6544 drm_gem_object_unreference(&work->old_fb_obj->base);
6545 drm_gem_object_unreference(&obj->base);
6546 mutex_unlock(&dev->struct_mutex);
6547
6548 cleanup:
6549 spin_lock_irqsave(&dev->event_lock, flags);
6550 intel_crtc->unpin_work = NULL;
6551 spin_unlock_irqrestore(&dev->event_lock, flags);
6552
6553 drm_vblank_put(dev, intel_crtc->pipe);
6554 free_work:
6555 kfree(work);
6556
6557 return ret;
6558 }
6559
6560 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6561 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6562 .load_lut = intel_crtc_load_lut,
6563 .disable = intel_crtc_disable,
6564 };
6565
6566 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6567 struct drm_crtc *crtc)
6568 {
6569 struct drm_device *dev;
6570 struct drm_crtc *tmp;
6571 int crtc_mask = 1;
6572
6573 WARN(!crtc, "checking null crtc?\n");
6574
6575 dev = crtc->dev;
6576
6577 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6578 if (tmp == crtc)
6579 break;
6580 crtc_mask <<= 1;
6581 }
6582
6583 if (encoder->possible_crtcs & crtc_mask)
6584 return true;
6585 return false;
6586 }
6587
6588 static int
6589 intel_crtc_helper_disable(struct drm_crtc *crtc)
6590 {
6591 struct drm_device *dev = crtc->dev;
6592 struct drm_connector *connector;
6593 struct drm_encoder *encoder;
6594
6595 /* Decouple all encoders and their attached connectors from this crtc */
6596 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6597 if (encoder->crtc != crtc)
6598 continue;
6599
6600 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6601 if (connector->encoder != encoder)
6602 continue;
6603
6604 connector->encoder = NULL;
6605 }
6606 }
6607
6608 drm_helper_disable_unused_functions(dev);
6609 return 0;
6610 }
6611
6612 static void
6613 intel_crtc_prepare_encoders(struct drm_device *dev)
6614 {
6615 struct intel_encoder *encoder;
6616
6617 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6618 /* Disable unused encoders */
6619 if (encoder->base.crtc == NULL)
6620 encoder->disable(encoder);
6621 }
6622 }
6623
6624 bool intel_set_mode(struct drm_crtc *crtc,
6625 struct drm_display_mode *mode,
6626 int x, int y, struct drm_framebuffer *old_fb)
6627 {
6628 struct drm_device *dev = crtc->dev;
6629 drm_i915_private_t *dev_priv = dev->dev_private;
6630 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
6631 struct drm_encoder_helper_funcs *encoder_funcs;
6632 int saved_x, saved_y;
6633 struct drm_encoder *encoder;
6634 bool ret = true;
6635
6636 crtc->enabled = drm_helper_crtc_in_use(crtc);
6637 if (!crtc->enabled)
6638 return true;
6639
6640 adjusted_mode = drm_mode_duplicate(dev, mode);
6641 if (!adjusted_mode)
6642 return false;
6643
6644 saved_hwmode = crtc->hwmode;
6645 saved_mode = crtc->mode;
6646 saved_x = crtc->x;
6647 saved_y = crtc->y;
6648
6649 /* Update crtc values up front so the driver can rely on them for mode
6650 * setting.
6651 */
6652 crtc->mode = *mode;
6653 crtc->x = x;
6654 crtc->y = y;
6655
6656 /* Pass our mode to the connectors and the CRTC to give them a chance to
6657 * adjust it according to limitations or connector properties, and also
6658 * a chance to reject the mode entirely.
6659 */
6660 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6661
6662 if (encoder->crtc != crtc)
6663 continue;
6664 encoder_funcs = encoder->helper_private;
6665 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6666 adjusted_mode))) {
6667 DRM_DEBUG_KMS("Encoder fixup failed\n");
6668 goto done;
6669 }
6670 }
6671
6672 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6673 DRM_DEBUG_KMS("CRTC fixup failed\n");
6674 goto done;
6675 }
6676 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6677
6678 intel_crtc_prepare_encoders(dev);
6679
6680 dev_priv->display.crtc_disable(crtc);
6681
6682 /* Set up the DPLL and any encoders state that needs to adjust or depend
6683 * on the DPLL.
6684 */
6685 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
6686 if (!ret)
6687 goto done;
6688
6689 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6690
6691 if (encoder->crtc != crtc)
6692 continue;
6693
6694 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6695 encoder->base.id, drm_get_encoder_name(encoder),
6696 mode->base.id, mode->name);
6697 encoder_funcs = encoder->helper_private;
6698 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6699 }
6700
6701 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
6702 dev_priv->display.crtc_enable(crtc);
6703
6704 /* Store real post-adjustment hardware mode. */
6705 crtc->hwmode = *adjusted_mode;
6706
6707 /* Calculate and store various constants which
6708 * are later needed by vblank and swap-completion
6709 * timestamping. They are derived from true hwmode.
6710 */
6711 drm_calc_timestamping_constants(crtc);
6712
6713 /* FIXME: add subpixel order */
6714 done:
6715 drm_mode_destroy(dev, adjusted_mode);
6716 if (!ret) {
6717 crtc->hwmode = saved_hwmode;
6718 crtc->mode = saved_mode;
6719 crtc->x = saved_x;
6720 crtc->y = saved_y;
6721 }
6722
6723 return ret;
6724 }
6725
6726 static void intel_set_config_free(struct intel_set_config *config)
6727 {
6728 if (!config)
6729 return;
6730
6731 kfree(config->save_connectors);
6732 kfree(config->save_encoders);
6733 kfree(config->save_crtcs);
6734 kfree(config);
6735 }
6736
6737 static int intel_set_config_save_state(struct drm_device *dev,
6738 struct intel_set_config *config)
6739 {
6740 struct drm_crtc *crtc;
6741 struct drm_encoder *encoder;
6742 struct drm_connector *connector;
6743 int count;
6744
6745 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6746 * connector data. */
6747 config->save_crtcs = kzalloc(dev->mode_config.num_crtc *
6748 sizeof(struct drm_crtc), GFP_KERNEL);
6749 if (!config->save_crtcs)
6750 return -ENOMEM;
6751
6752 config->save_encoders = kzalloc(dev->mode_config.num_encoder *
6753 sizeof(struct drm_encoder), GFP_KERNEL);
6754 if (!config->save_encoders)
6755 return -ENOMEM;
6756
6757 config->save_connectors = kzalloc(dev->mode_config.num_connector *
6758 sizeof(struct drm_connector), GFP_KERNEL);
6759 if (!config->save_connectors)
6760 return -ENOMEM;
6761
6762 /* Copy data. Note that driver private data is not affected.
6763 * Should anything bad happen only the expected state is
6764 * restored, not the drivers personal bookkeeping.
6765 */
6766 count = 0;
6767 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6768 config->save_crtcs[count++] = *crtc;
6769 }
6770
6771 count = 0;
6772 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6773 config->save_encoders[count++] = *encoder;
6774 }
6775
6776 count = 0;
6777 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6778 config->save_connectors[count++] = *connector;
6779 }
6780
6781 return 0;
6782 }
6783
6784 static void intel_set_config_restore_state(struct drm_device *dev,
6785 struct intel_set_config *config)
6786 {
6787 struct drm_crtc *crtc;
6788 struct drm_encoder *encoder;
6789 struct drm_connector *connector;
6790 int count;
6791
6792 count = 0;
6793 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6794 *crtc = config->save_crtcs[count++];
6795 }
6796
6797 count = 0;
6798 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6799 *encoder = config->save_encoders[count++];
6800 }
6801
6802 count = 0;
6803 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6804 *connector = config->save_connectors[count++];
6805 }
6806 }
6807
6808 static int intel_crtc_set_config(struct drm_mode_set *set)
6809 {
6810 struct drm_device *dev;
6811 struct drm_crtc *new_crtc;
6812 struct drm_encoder *new_encoder;
6813 struct drm_framebuffer *old_fb = NULL;
6814 bool mode_changed = false; /* if true do a full mode set */
6815 bool fb_changed = false; /* if true and !mode_changed just do a flip */
6816 struct drm_connector *connector;
6817 int count = 0, ro;
6818 struct drm_mode_set save_set;
6819 struct intel_set_config *config;
6820 int ret;
6821 int i;
6822
6823 DRM_DEBUG_KMS("\n");
6824
6825 if (!set)
6826 return -EINVAL;
6827
6828 if (!set->crtc)
6829 return -EINVAL;
6830
6831 if (!set->crtc->helper_private)
6832 return -EINVAL;
6833
6834 if (!set->mode)
6835 set->fb = NULL;
6836
6837 if (set->fb) {
6838 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6839 set->crtc->base.id, set->fb->base.id,
6840 (int)set->num_connectors, set->x, set->y);
6841 } else {
6842 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6843 return intel_crtc_helper_disable(set->crtc);
6844 }
6845
6846 dev = set->crtc->dev;
6847
6848 ret = -ENOMEM;
6849 config = kzalloc(sizeof(*config), GFP_KERNEL);
6850 if (!config)
6851 goto out_config;
6852
6853 ret = intel_set_config_save_state(dev, config);
6854 if (ret)
6855 goto out_config;
6856
6857 save_set.crtc = set->crtc;
6858 save_set.mode = &set->crtc->mode;
6859 save_set.x = set->crtc->x;
6860 save_set.y = set->crtc->y;
6861 save_set.fb = set->crtc->fb;
6862
6863 /* We should be able to check here if the fb has the same properties
6864 * and then just flip_or_move it */
6865 if (set->crtc->fb != set->fb) {
6866 /* If we have no fb then treat it as a full mode set */
6867 if (set->crtc->fb == NULL) {
6868 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6869 mode_changed = true;
6870 } else if (set->fb == NULL) {
6871 mode_changed = true;
6872 } else if (set->fb->depth != set->crtc->fb->depth) {
6873 mode_changed = true;
6874 } else if (set->fb->bits_per_pixel !=
6875 set->crtc->fb->bits_per_pixel) {
6876 mode_changed = true;
6877 } else
6878 fb_changed = true;
6879 }
6880
6881 if (set->x != set->crtc->x || set->y != set->crtc->y)
6882 fb_changed = true;
6883
6884 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6885 DRM_DEBUG_KMS("modes are different, full mode set\n");
6886 drm_mode_debug_printmodeline(&set->crtc->mode);
6887 drm_mode_debug_printmodeline(set->mode);
6888 mode_changed = true;
6889 }
6890
6891 /* a) traverse passed in connector list and get encoders for them */
6892 count = 0;
6893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6894 new_encoder = connector->encoder;
6895 for (ro = 0; ro < set->num_connectors; ro++) {
6896 if (set->connectors[ro] == connector) {
6897 new_encoder =
6898 &intel_attached_encoder(connector)->base;
6899 break;
6900 }
6901 }
6902
6903 if (new_encoder != connector->encoder) {
6904 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6905 mode_changed = true;
6906 /* If the encoder is reused for another connector, then
6907 * the appropriate crtc will be set later.
6908 */
6909 if (connector->encoder)
6910 connector->encoder->crtc = NULL;
6911 connector->encoder = new_encoder;
6912 }
6913 }
6914
6915 count = 0;
6916 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6917 if (!connector->encoder)
6918 continue;
6919
6920 if (connector->encoder->crtc == set->crtc)
6921 new_crtc = NULL;
6922 else
6923 new_crtc = connector->encoder->crtc;
6924
6925 for (ro = 0; ro < set->num_connectors; ro++) {
6926 if (set->connectors[ro] == connector)
6927 new_crtc = set->crtc;
6928 }
6929
6930 /* Make sure the new CRTC will work with the encoder */
6931 if (new_crtc &&
6932 !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6933 ret = -EINVAL;
6934 goto fail;
6935 }
6936 if (new_crtc != connector->encoder->crtc) {
6937 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6938 mode_changed = true;
6939 connector->encoder->crtc = new_crtc;
6940 }
6941 if (new_crtc) {
6942 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6943 connector->base.id, drm_get_connector_name(connector),
6944 new_crtc->base.id);
6945 } else {
6946 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6947 connector->base.id, drm_get_connector_name(connector));
6948 }
6949 }
6950
6951 if (mode_changed) {
6952 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6953 if (set->crtc->enabled) {
6954 DRM_DEBUG_KMS("attempting to set mode from"
6955 " userspace\n");
6956 drm_mode_debug_printmodeline(set->mode);
6957 old_fb = set->crtc->fb;
6958 set->crtc->fb = set->fb;
6959 if (!intel_set_mode(set->crtc, set->mode,
6960 set->x, set->y, old_fb)) {
6961 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6962 set->crtc->base.id);
6963 set->crtc->fb = old_fb;
6964 ret = -EINVAL;
6965 goto fail;
6966 }
6967 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6968 for (i = 0; i < set->num_connectors; i++) {
6969 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6970 drm_get_connector_name(set->connectors[i]));
6971 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6972 }
6973 }
6974 drm_helper_disable_unused_functions(dev);
6975 } else if (fb_changed) {
6976 set->crtc->x = set->x;
6977 set->crtc->y = set->y;
6978
6979 old_fb = set->crtc->fb;
6980 if (set->crtc->fb != set->fb)
6981 set->crtc->fb = set->fb;
6982 ret = intel_pipe_set_base(set->crtc,
6983 set->x, set->y, old_fb);
6984 if (ret != 0) {
6985 set->crtc->fb = old_fb;
6986 goto fail;
6987 }
6988 }
6989
6990 intel_set_config_free(config);
6991
6992 return 0;
6993
6994 fail:
6995 intel_set_config_restore_state(dev, config);
6996
6997 /* Try to restore the config */
6998 if (mode_changed &&
6999 !intel_set_mode(save_set.crtc, save_set.mode,
7000 save_set.x, save_set.y, save_set.fb))
7001 DRM_ERROR("failed to restore config after modeset failure\n");
7002
7003 out_config:
7004 intel_set_config_free(config);
7005 return ret;
7006 }
7007
7008 static const struct drm_crtc_funcs intel_crtc_funcs = {
7009 .cursor_set = intel_crtc_cursor_set,
7010 .cursor_move = intel_crtc_cursor_move,
7011 .gamma_set = intel_crtc_gamma_set,
7012 .set_config = intel_crtc_set_config,
7013 .destroy = intel_crtc_destroy,
7014 .page_flip = intel_crtc_page_flip,
7015 };
7016
7017 static void intel_pch_pll_init(struct drm_device *dev)
7018 {
7019 drm_i915_private_t *dev_priv = dev->dev_private;
7020 int i;
7021
7022 if (dev_priv->num_pch_pll == 0) {
7023 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7024 return;
7025 }
7026
7027 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7028 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7029 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7030 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7031 }
7032 }
7033
7034 static void intel_crtc_init(struct drm_device *dev, int pipe)
7035 {
7036 drm_i915_private_t *dev_priv = dev->dev_private;
7037 struct intel_crtc *intel_crtc;
7038 int i;
7039
7040 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7041 if (intel_crtc == NULL)
7042 return;
7043
7044 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7045
7046 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7047 for (i = 0; i < 256; i++) {
7048 intel_crtc->lut_r[i] = i;
7049 intel_crtc->lut_g[i] = i;
7050 intel_crtc->lut_b[i] = i;
7051 }
7052
7053 /* Swap pipes & planes for FBC on pre-965 */
7054 intel_crtc->pipe = pipe;
7055 intel_crtc->plane = pipe;
7056 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7057 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7058 intel_crtc->plane = !pipe;
7059 }
7060
7061 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7062 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7063 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7064 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7065
7066 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7067
7068 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7069 }
7070
7071 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7072 struct drm_file *file)
7073 {
7074 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7075 struct drm_mode_object *drmmode_obj;
7076 struct intel_crtc *crtc;
7077
7078 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7079 return -ENODEV;
7080
7081 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7082 DRM_MODE_OBJECT_CRTC);
7083
7084 if (!drmmode_obj) {
7085 DRM_ERROR("no such CRTC id\n");
7086 return -EINVAL;
7087 }
7088
7089 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7090 pipe_from_crtc_id->pipe = crtc->pipe;
7091
7092 return 0;
7093 }
7094
7095 static int intel_encoder_clones(struct intel_encoder *encoder)
7096 {
7097 struct drm_device *dev = encoder->base.dev;
7098 struct intel_encoder *source_encoder;
7099 int index_mask = 0;
7100 int entry = 0;
7101
7102 list_for_each_entry(source_encoder,
7103 &dev->mode_config.encoder_list, base.head) {
7104
7105 if (encoder == source_encoder)
7106 index_mask |= (1 << entry);
7107
7108 /* Intel hw has only one MUX where enocoders could be cloned. */
7109 if (encoder->cloneable && source_encoder->cloneable)
7110 index_mask |= (1 << entry);
7111
7112 entry++;
7113 }
7114
7115 return index_mask;
7116 }
7117
7118 static bool has_edp_a(struct drm_device *dev)
7119 {
7120 struct drm_i915_private *dev_priv = dev->dev_private;
7121
7122 if (!IS_MOBILE(dev))
7123 return false;
7124
7125 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7126 return false;
7127
7128 if (IS_GEN5(dev) &&
7129 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7130 return false;
7131
7132 return true;
7133 }
7134
7135 static void intel_setup_outputs(struct drm_device *dev)
7136 {
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 struct intel_encoder *encoder;
7139 bool dpd_is_edp = false;
7140 bool has_lvds;
7141
7142 has_lvds = intel_lvds_init(dev);
7143 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7144 /* disable the panel fitter on everything but LVDS */
7145 I915_WRITE(PFIT_CONTROL, 0);
7146 }
7147
7148 if (HAS_PCH_SPLIT(dev)) {
7149 dpd_is_edp = intel_dpd_is_edp(dev);
7150
7151 if (has_edp_a(dev))
7152 intel_dp_init(dev, DP_A, PORT_A);
7153
7154 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7155 intel_dp_init(dev, PCH_DP_D, PORT_D);
7156 }
7157
7158 intel_crt_init(dev);
7159
7160 if (IS_HASWELL(dev)) {
7161 int found;
7162
7163 /* Haswell uses DDI functions to detect digital outputs */
7164 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7165 /* DDI A only supports eDP */
7166 if (found)
7167 intel_ddi_init(dev, PORT_A);
7168
7169 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7170 * register */
7171 found = I915_READ(SFUSE_STRAP);
7172
7173 if (found & SFUSE_STRAP_DDIB_DETECTED)
7174 intel_ddi_init(dev, PORT_B);
7175 if (found & SFUSE_STRAP_DDIC_DETECTED)
7176 intel_ddi_init(dev, PORT_C);
7177 if (found & SFUSE_STRAP_DDID_DETECTED)
7178 intel_ddi_init(dev, PORT_D);
7179 } else if (HAS_PCH_SPLIT(dev)) {
7180 int found;
7181
7182 if (I915_READ(HDMIB) & PORT_DETECTED) {
7183 /* PCH SDVOB multiplex with HDMIB */
7184 found = intel_sdvo_init(dev, PCH_SDVOB, true);
7185 if (!found)
7186 intel_hdmi_init(dev, HDMIB, PORT_B);
7187 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7188 intel_dp_init(dev, PCH_DP_B, PORT_B);
7189 }
7190
7191 if (I915_READ(HDMIC) & PORT_DETECTED)
7192 intel_hdmi_init(dev, HDMIC, PORT_C);
7193
7194 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7195 intel_hdmi_init(dev, HDMID, PORT_D);
7196
7197 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7198 intel_dp_init(dev, PCH_DP_C, PORT_C);
7199
7200 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7201 intel_dp_init(dev, PCH_DP_D, PORT_D);
7202 } else if (IS_VALLEYVIEW(dev)) {
7203 int found;
7204
7205 if (I915_READ(SDVOB) & PORT_DETECTED) {
7206 /* SDVOB multiplex with HDMIB */
7207 found = intel_sdvo_init(dev, SDVOB, true);
7208 if (!found)
7209 intel_hdmi_init(dev, SDVOB, PORT_B);
7210 if (!found && (I915_READ(DP_B) & DP_DETECTED))
7211 intel_dp_init(dev, DP_B, PORT_B);
7212 }
7213
7214 if (I915_READ(SDVOC) & PORT_DETECTED)
7215 intel_hdmi_init(dev, SDVOC, PORT_C);
7216
7217 /* Shares lanes with HDMI on SDVOC */
7218 if (I915_READ(DP_C) & DP_DETECTED)
7219 intel_dp_init(dev, DP_C, PORT_C);
7220 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7221 bool found = false;
7222
7223 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7224 DRM_DEBUG_KMS("probing SDVOB\n");
7225 found = intel_sdvo_init(dev, SDVOB, true);
7226 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7227 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7228 intel_hdmi_init(dev, SDVOB, PORT_B);
7229 }
7230
7231 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7232 DRM_DEBUG_KMS("probing DP_B\n");
7233 intel_dp_init(dev, DP_B, PORT_B);
7234 }
7235 }
7236
7237 /* Before G4X SDVOC doesn't have its own detect register */
7238
7239 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7240 DRM_DEBUG_KMS("probing SDVOC\n");
7241 found = intel_sdvo_init(dev, SDVOC, false);
7242 }
7243
7244 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7245
7246 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7247 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7248 intel_hdmi_init(dev, SDVOC, PORT_C);
7249 }
7250 if (SUPPORTS_INTEGRATED_DP(dev)) {
7251 DRM_DEBUG_KMS("probing DP_C\n");
7252 intel_dp_init(dev, DP_C, PORT_C);
7253 }
7254 }
7255
7256 if (SUPPORTS_INTEGRATED_DP(dev) &&
7257 (I915_READ(DP_D) & DP_DETECTED)) {
7258 DRM_DEBUG_KMS("probing DP_D\n");
7259 intel_dp_init(dev, DP_D, PORT_D);
7260 }
7261 } else if (IS_GEN2(dev))
7262 intel_dvo_init(dev);
7263
7264 if (SUPPORTS_TV(dev))
7265 intel_tv_init(dev);
7266
7267 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7268 encoder->base.possible_crtcs = encoder->crtc_mask;
7269 encoder->base.possible_clones =
7270 intel_encoder_clones(encoder);
7271 }
7272
7273 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7274 ironlake_init_pch_refclk(dev);
7275 }
7276
7277 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7278 {
7279 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7280
7281 drm_framebuffer_cleanup(fb);
7282 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7283
7284 kfree(intel_fb);
7285 }
7286
7287 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7288 struct drm_file *file,
7289 unsigned int *handle)
7290 {
7291 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7292 struct drm_i915_gem_object *obj = intel_fb->obj;
7293
7294 return drm_gem_handle_create(file, &obj->base, handle);
7295 }
7296
7297 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7298 .destroy = intel_user_framebuffer_destroy,
7299 .create_handle = intel_user_framebuffer_create_handle,
7300 };
7301
7302 int intel_framebuffer_init(struct drm_device *dev,
7303 struct intel_framebuffer *intel_fb,
7304 struct drm_mode_fb_cmd2 *mode_cmd,
7305 struct drm_i915_gem_object *obj)
7306 {
7307 int ret;
7308
7309 if (obj->tiling_mode == I915_TILING_Y)
7310 return -EINVAL;
7311
7312 if (mode_cmd->pitches[0] & 63)
7313 return -EINVAL;
7314
7315 switch (mode_cmd->pixel_format) {
7316 case DRM_FORMAT_RGB332:
7317 case DRM_FORMAT_RGB565:
7318 case DRM_FORMAT_XRGB8888:
7319 case DRM_FORMAT_XBGR8888:
7320 case DRM_FORMAT_ARGB8888:
7321 case DRM_FORMAT_XRGB2101010:
7322 case DRM_FORMAT_ARGB2101010:
7323 /* RGB formats are common across chipsets */
7324 break;
7325 case DRM_FORMAT_YUYV:
7326 case DRM_FORMAT_UYVY:
7327 case DRM_FORMAT_YVYU:
7328 case DRM_FORMAT_VYUY:
7329 break;
7330 default:
7331 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7332 mode_cmd->pixel_format);
7333 return -EINVAL;
7334 }
7335
7336 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7337 if (ret) {
7338 DRM_ERROR("framebuffer init failed %d\n", ret);
7339 return ret;
7340 }
7341
7342 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7343 intel_fb->obj = obj;
7344 return 0;
7345 }
7346
7347 static struct drm_framebuffer *
7348 intel_user_framebuffer_create(struct drm_device *dev,
7349 struct drm_file *filp,
7350 struct drm_mode_fb_cmd2 *mode_cmd)
7351 {
7352 struct drm_i915_gem_object *obj;
7353
7354 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7355 mode_cmd->handles[0]));
7356 if (&obj->base == NULL)
7357 return ERR_PTR(-ENOENT);
7358
7359 return intel_framebuffer_create(dev, mode_cmd, obj);
7360 }
7361
7362 static const struct drm_mode_config_funcs intel_mode_funcs = {
7363 .fb_create = intel_user_framebuffer_create,
7364 .output_poll_changed = intel_fb_output_poll_changed,
7365 };
7366
7367 /* Set up chip specific display functions */
7368 static void intel_init_display(struct drm_device *dev)
7369 {
7370 struct drm_i915_private *dev_priv = dev->dev_private;
7371
7372 /* We always want a DPMS function */
7373 if (HAS_PCH_SPLIT(dev)) {
7374 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7375 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7376 dev_priv->display.crtc_disable = ironlake_crtc_disable;
7377 dev_priv->display.off = ironlake_crtc_off;
7378 dev_priv->display.update_plane = ironlake_update_plane;
7379 } else {
7380 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7381 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7382 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7383 dev_priv->display.off = i9xx_crtc_off;
7384 dev_priv->display.update_plane = i9xx_update_plane;
7385 }
7386
7387 /* Returns the core display clock speed */
7388 if (IS_VALLEYVIEW(dev))
7389 dev_priv->display.get_display_clock_speed =
7390 valleyview_get_display_clock_speed;
7391 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7392 dev_priv->display.get_display_clock_speed =
7393 i945_get_display_clock_speed;
7394 else if (IS_I915G(dev))
7395 dev_priv->display.get_display_clock_speed =
7396 i915_get_display_clock_speed;
7397 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7398 dev_priv->display.get_display_clock_speed =
7399 i9xx_misc_get_display_clock_speed;
7400 else if (IS_I915GM(dev))
7401 dev_priv->display.get_display_clock_speed =
7402 i915gm_get_display_clock_speed;
7403 else if (IS_I865G(dev))
7404 dev_priv->display.get_display_clock_speed =
7405 i865_get_display_clock_speed;
7406 else if (IS_I85X(dev))
7407 dev_priv->display.get_display_clock_speed =
7408 i855_get_display_clock_speed;
7409 else /* 852, 830 */
7410 dev_priv->display.get_display_clock_speed =
7411 i830_get_display_clock_speed;
7412
7413 if (HAS_PCH_SPLIT(dev)) {
7414 if (IS_GEN5(dev)) {
7415 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7416 dev_priv->display.write_eld = ironlake_write_eld;
7417 } else if (IS_GEN6(dev)) {
7418 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7419 dev_priv->display.write_eld = ironlake_write_eld;
7420 } else if (IS_IVYBRIDGE(dev)) {
7421 /* FIXME: detect B0+ stepping and use auto training */
7422 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7423 dev_priv->display.write_eld = ironlake_write_eld;
7424 } else if (IS_HASWELL(dev)) {
7425 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7426 dev_priv->display.write_eld = haswell_write_eld;
7427 } else
7428 dev_priv->display.update_wm = NULL;
7429 } else if (IS_G4X(dev)) {
7430 dev_priv->display.write_eld = g4x_write_eld;
7431 }
7432
7433 /* Default just returns -ENODEV to indicate unsupported */
7434 dev_priv->display.queue_flip = intel_default_queue_flip;
7435
7436 switch (INTEL_INFO(dev)->gen) {
7437 case 2:
7438 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7439 break;
7440
7441 case 3:
7442 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7443 break;
7444
7445 case 4:
7446 case 5:
7447 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7448 break;
7449
7450 case 6:
7451 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7452 break;
7453 case 7:
7454 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7455 break;
7456 }
7457 }
7458
7459 /*
7460 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7461 * resume, or other times. This quirk makes sure that's the case for
7462 * affected systems.
7463 */
7464 static void quirk_pipea_force(struct drm_device *dev)
7465 {
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467
7468 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7469 DRM_INFO("applying pipe a force quirk\n");
7470 }
7471
7472 /*
7473 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7474 */
7475 static void quirk_ssc_force_disable(struct drm_device *dev)
7476 {
7477 struct drm_i915_private *dev_priv = dev->dev_private;
7478 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7479 DRM_INFO("applying lvds SSC disable quirk\n");
7480 }
7481
7482 /*
7483 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7484 * brightness value
7485 */
7486 static void quirk_invert_brightness(struct drm_device *dev)
7487 {
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7490 DRM_INFO("applying inverted panel brightness quirk\n");
7491 }
7492
7493 struct intel_quirk {
7494 int device;
7495 int subsystem_vendor;
7496 int subsystem_device;
7497 void (*hook)(struct drm_device *dev);
7498 };
7499
7500 static struct intel_quirk intel_quirks[] = {
7501 /* HP Mini needs pipe A force quirk (LP: #322104) */
7502 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7503
7504 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7505 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7506
7507 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7508 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7509
7510 /* 855 & before need to leave pipe A & dpll A up */
7511 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7512 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7513 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7514
7515 /* Lenovo U160 cannot use SSC on LVDS */
7516 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7517
7518 /* Sony Vaio Y cannot use SSC on LVDS */
7519 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7520
7521 /* Acer Aspire 5734Z must invert backlight brightness */
7522 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7523 };
7524
7525 static void intel_init_quirks(struct drm_device *dev)
7526 {
7527 struct pci_dev *d = dev->pdev;
7528 int i;
7529
7530 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7531 struct intel_quirk *q = &intel_quirks[i];
7532
7533 if (d->device == q->device &&
7534 (d->subsystem_vendor == q->subsystem_vendor ||
7535 q->subsystem_vendor == PCI_ANY_ID) &&
7536 (d->subsystem_device == q->subsystem_device ||
7537 q->subsystem_device == PCI_ANY_ID))
7538 q->hook(dev);
7539 }
7540 }
7541
7542 /* Disable the VGA plane that we never use */
7543 static void i915_disable_vga(struct drm_device *dev)
7544 {
7545 struct drm_i915_private *dev_priv = dev->dev_private;
7546 u8 sr1;
7547 u32 vga_reg;
7548
7549 if (HAS_PCH_SPLIT(dev))
7550 vga_reg = CPU_VGACNTRL;
7551 else
7552 vga_reg = VGACNTRL;
7553
7554 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7555 outb(SR01, VGA_SR_INDEX);
7556 sr1 = inb(VGA_SR_DATA);
7557 outb(sr1 | 1<<5, VGA_SR_DATA);
7558 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7559 udelay(300);
7560
7561 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7562 POSTING_READ(vga_reg);
7563 }
7564
7565 void intel_modeset_init_hw(struct drm_device *dev)
7566 {
7567 /* We attempt to init the necessary power wells early in the initialization
7568 * time, so the subsystems that expect power to be enabled can work.
7569 */
7570 intel_init_power_wells(dev);
7571
7572 intel_prepare_ddi(dev);
7573
7574 intel_init_clock_gating(dev);
7575
7576 mutex_lock(&dev->struct_mutex);
7577 intel_enable_gt_powersave(dev);
7578 mutex_unlock(&dev->struct_mutex);
7579 }
7580
7581 void intel_modeset_init(struct drm_device *dev)
7582 {
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 int i, ret;
7585
7586 drm_mode_config_init(dev);
7587
7588 dev->mode_config.min_width = 0;
7589 dev->mode_config.min_height = 0;
7590
7591 dev->mode_config.preferred_depth = 24;
7592 dev->mode_config.prefer_shadow = 1;
7593
7594 dev->mode_config.funcs = &intel_mode_funcs;
7595
7596 intel_init_quirks(dev);
7597
7598 intel_init_pm(dev);
7599
7600 intel_init_display(dev);
7601
7602 if (IS_GEN2(dev)) {
7603 dev->mode_config.max_width = 2048;
7604 dev->mode_config.max_height = 2048;
7605 } else if (IS_GEN3(dev)) {
7606 dev->mode_config.max_width = 4096;
7607 dev->mode_config.max_height = 4096;
7608 } else {
7609 dev->mode_config.max_width = 8192;
7610 dev->mode_config.max_height = 8192;
7611 }
7612 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7613
7614 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7615 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7616
7617 for (i = 0; i < dev_priv->num_pipe; i++) {
7618 intel_crtc_init(dev, i);
7619 ret = intel_plane_init(dev, i);
7620 if (ret)
7621 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7622 }
7623
7624 intel_pch_pll_init(dev);
7625
7626 /* Just disable it once at startup */
7627 i915_disable_vga(dev);
7628 intel_setup_outputs(dev);
7629 }
7630
7631 static void
7632 intel_connector_break_all_links(struct intel_connector *connector)
7633 {
7634 connector->base.dpms = DRM_MODE_DPMS_OFF;
7635 connector->base.encoder = NULL;
7636 connector->encoder->connectors_active = false;
7637 connector->encoder->base.crtc = NULL;
7638 }
7639
7640 static void intel_enable_pipe_a(struct drm_device *dev)
7641 {
7642 struct intel_connector *connector;
7643 struct drm_connector *crt = NULL;
7644 struct intel_load_detect_pipe load_detect_temp;
7645
7646 /* We can't just switch on the pipe A, we need to set things up with a
7647 * proper mode and output configuration. As a gross hack, enable pipe A
7648 * by enabling the load detect pipe once. */
7649 list_for_each_entry(connector,
7650 &dev->mode_config.connector_list,
7651 base.head) {
7652 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7653 crt = &connector->base;
7654 break;
7655 }
7656 }
7657
7658 if (!crt)
7659 return;
7660
7661 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7662 intel_release_load_detect_pipe(crt, &load_detect_temp);
7663
7664
7665 }
7666
7667 static void intel_sanitize_crtc(struct intel_crtc *crtc)
7668 {
7669 struct drm_device *dev = crtc->base.dev;
7670 struct drm_i915_private *dev_priv = dev->dev_private;
7671 u32 reg, val;
7672
7673 /* Clear any frame start delays used for debugging left by the BIOS */
7674 reg = PIPECONF(crtc->pipe);
7675 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7676
7677 /* We need to sanitize the plane -> pipe mapping first because this will
7678 * disable the crtc (and hence change the state) if it is wrong. */
7679 if (!HAS_PCH_SPLIT(dev)) {
7680 struct intel_connector *connector;
7681 bool plane;
7682
7683 reg = DSPCNTR(crtc->plane);
7684 val = I915_READ(reg);
7685
7686 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7687 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7688 goto ok;
7689
7690 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7691 crtc->base.base.id);
7692
7693 /* Pipe has the wrong plane attached and the plane is active.
7694 * Temporarily change the plane mapping and disable everything
7695 * ... */
7696 plane = crtc->plane;
7697 crtc->plane = !plane;
7698 dev_priv->display.crtc_disable(&crtc->base);
7699 crtc->plane = plane;
7700
7701 /* ... and break all links. */
7702 list_for_each_entry(connector, &dev->mode_config.connector_list,
7703 base.head) {
7704 if (connector->encoder->base.crtc != &crtc->base)
7705 continue;
7706
7707 intel_connector_break_all_links(connector);
7708 }
7709
7710 WARN_ON(crtc->active);
7711 crtc->base.enabled = false;
7712 }
7713 ok:
7714
7715 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7716 crtc->pipe == PIPE_A && !crtc->active) {
7717 /* BIOS forgot to enable pipe A, this mostly happens after
7718 * resume. Force-enable the pipe to fix this, the update_dpms
7719 * call below we restore the pipe to the right state, but leave
7720 * the required bits on. */
7721 intel_enable_pipe_a(dev);
7722 }
7723
7724 /* Adjust the state of the output pipe according to whether we
7725 * have active connectors/encoders. */
7726 intel_crtc_update_dpms(&crtc->base);
7727
7728 if (crtc->active != crtc->base.enabled) {
7729 struct intel_encoder *encoder;
7730
7731 /* This can happen either due to bugs in the get_hw_state
7732 * functions or because the pipe is force-enabled due to the
7733 * pipe A quirk. */
7734 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7735 crtc->base.base.id,
7736 crtc->base.enabled ? "enabled" : "disabled",
7737 crtc->active ? "enabled" : "disabled");
7738
7739 crtc->base.enabled = crtc->active;
7740
7741 /* Because we only establish the connector -> encoder ->
7742 * crtc links if something is active, this means the
7743 * crtc is now deactivated. Break the links. connector
7744 * -> encoder links are only establish when things are
7745 * actually up, hence no need to break them. */
7746 WARN_ON(crtc->active);
7747
7748 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7749 WARN_ON(encoder->connectors_active);
7750 encoder->base.crtc = NULL;
7751 }
7752 }
7753 }
7754
7755 static void intel_sanitize_encoder(struct intel_encoder *encoder)
7756 {
7757 struct intel_connector *connector;
7758 struct drm_device *dev = encoder->base.dev;
7759
7760 /* We need to check both for a crtc link (meaning that the
7761 * encoder is active and trying to read from a pipe) and the
7762 * pipe itself being active. */
7763 bool has_active_crtc = encoder->base.crtc &&
7764 to_intel_crtc(encoder->base.crtc)->active;
7765
7766 if (encoder->connectors_active && !has_active_crtc) {
7767 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7768 encoder->base.base.id,
7769 drm_get_encoder_name(&encoder->base));
7770
7771 /* Connector is active, but has no active pipe. This is
7772 * fallout from our resume register restoring. Disable
7773 * the encoder manually again. */
7774 if (encoder->base.crtc) {
7775 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7776 encoder->base.base.id,
7777 drm_get_encoder_name(&encoder->base));
7778 encoder->disable(encoder);
7779 }
7780
7781 /* Inconsistent output/port/pipe state happens presumably due to
7782 * a bug in one of the get_hw_state functions. Or someplace else
7783 * in our code, like the register restore mess on resume. Clamp
7784 * things to off as a safer default. */
7785 list_for_each_entry(connector,
7786 &dev->mode_config.connector_list,
7787 base.head) {
7788 if (connector->encoder != encoder)
7789 continue;
7790
7791 intel_connector_break_all_links(connector);
7792 }
7793 }
7794 /* Enabled encoders without active connectors will be fixed in
7795 * the crtc fixup. */
7796 }
7797
7798 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7799 * and i915 state tracking structures. */
7800 void intel_modeset_setup_hw_state(struct drm_device *dev)
7801 {
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 enum pipe pipe;
7804 u32 tmp;
7805 struct intel_crtc *crtc;
7806 struct intel_encoder *encoder;
7807 struct intel_connector *connector;
7808
7809 for_each_pipe(pipe) {
7810 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7811
7812 tmp = I915_READ(PIPECONF(pipe));
7813 if (tmp & PIPECONF_ENABLE)
7814 crtc->active = true;
7815 else
7816 crtc->active = false;
7817
7818 crtc->base.enabled = crtc->active;
7819
7820 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7821 crtc->base.base.id,
7822 crtc->active ? "enabled" : "disabled");
7823 }
7824
7825 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7826 base.head) {
7827 pipe = 0;
7828
7829 if (encoder->get_hw_state(encoder, &pipe)) {
7830 encoder->base.crtc =
7831 dev_priv->pipe_to_crtc_mapping[pipe];
7832 } else {
7833 encoder->base.crtc = NULL;
7834 }
7835
7836 encoder->connectors_active = false;
7837 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7838 encoder->base.base.id,
7839 drm_get_encoder_name(&encoder->base),
7840 encoder->base.crtc ? "enabled" : "disabled",
7841 pipe);
7842 }
7843
7844 list_for_each_entry(connector, &dev->mode_config.connector_list,
7845 base.head) {
7846 if (connector->get_hw_state(connector)) {
7847 connector->base.dpms = DRM_MODE_DPMS_ON;
7848 connector->encoder->connectors_active = true;
7849 connector->base.encoder = &connector->encoder->base;
7850 } else {
7851 connector->base.dpms = DRM_MODE_DPMS_OFF;
7852 connector->base.encoder = NULL;
7853 }
7854 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7855 connector->base.base.id,
7856 drm_get_connector_name(&connector->base),
7857 connector->base.encoder ? "enabled" : "disabled");
7858 }
7859
7860 /* HW state is read out, now we need to sanitize this mess. */
7861 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7862 base.head) {
7863 intel_sanitize_encoder(encoder);
7864 }
7865
7866 for_each_pipe(pipe) {
7867 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7868 intel_sanitize_crtc(crtc);
7869 }
7870 }
7871
7872 void intel_modeset_gem_init(struct drm_device *dev)
7873 {
7874 intel_modeset_init_hw(dev);
7875
7876 intel_setup_overlay(dev);
7877
7878 intel_modeset_setup_hw_state(dev);
7879 }
7880
7881 void intel_modeset_cleanup(struct drm_device *dev)
7882 {
7883 struct drm_i915_private *dev_priv = dev->dev_private;
7884 struct drm_crtc *crtc;
7885 struct intel_crtc *intel_crtc;
7886
7887 drm_kms_helper_poll_fini(dev);
7888 mutex_lock(&dev->struct_mutex);
7889
7890 intel_unregister_dsm_handler();
7891
7892
7893 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7894 /* Skip inactive CRTCs */
7895 if (!crtc->fb)
7896 continue;
7897
7898 intel_crtc = to_intel_crtc(crtc);
7899 intel_increase_pllclock(crtc);
7900 }
7901
7902 intel_disable_fbc(dev);
7903
7904 intel_disable_gt_powersave(dev);
7905
7906 ironlake_teardown_rc6(dev);
7907
7908 if (IS_VALLEYVIEW(dev))
7909 vlv_init_dpio(dev);
7910
7911 mutex_unlock(&dev->struct_mutex);
7912
7913 /* Disable the irq before mode object teardown, for the irq might
7914 * enqueue unpin/hotplug work. */
7915 drm_irq_uninstall(dev);
7916 cancel_work_sync(&dev_priv->hotplug_work);
7917 cancel_work_sync(&dev_priv->rps.work);
7918
7919 /* flush any delayed tasks or pending work */
7920 flush_scheduled_work();
7921
7922 drm_mode_config_cleanup(dev);
7923 }
7924
7925 /*
7926 * Return which encoder is currently attached for connector.
7927 */
7928 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7929 {
7930 return &intel_attached_encoder(connector)->base;
7931 }
7932
7933 void intel_connector_attach_encoder(struct intel_connector *connector,
7934 struct intel_encoder *encoder)
7935 {
7936 connector->encoder = encoder;
7937 drm_mode_connector_attach_encoder(&connector->base,
7938 &encoder->base);
7939 }
7940
7941 /*
7942 * set vga decode state - true == enable VGA decode
7943 */
7944 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7945 {
7946 struct drm_i915_private *dev_priv = dev->dev_private;
7947 u16 gmch_ctrl;
7948
7949 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7950 if (state)
7951 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7952 else
7953 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7954 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7955 return 0;
7956 }
7957
7958 #ifdef CONFIG_DEBUG_FS
7959 #include <linux/seq_file.h>
7960
7961 struct intel_display_error_state {
7962 struct intel_cursor_error_state {
7963 u32 control;
7964 u32 position;
7965 u32 base;
7966 u32 size;
7967 } cursor[I915_MAX_PIPES];
7968
7969 struct intel_pipe_error_state {
7970 u32 conf;
7971 u32 source;
7972
7973 u32 htotal;
7974 u32 hblank;
7975 u32 hsync;
7976 u32 vtotal;
7977 u32 vblank;
7978 u32 vsync;
7979 } pipe[I915_MAX_PIPES];
7980
7981 struct intel_plane_error_state {
7982 u32 control;
7983 u32 stride;
7984 u32 size;
7985 u32 pos;
7986 u32 addr;
7987 u32 surface;
7988 u32 tile_offset;
7989 } plane[I915_MAX_PIPES];
7990 };
7991
7992 struct intel_display_error_state *
7993 intel_display_capture_error_state(struct drm_device *dev)
7994 {
7995 drm_i915_private_t *dev_priv = dev->dev_private;
7996 struct intel_display_error_state *error;
7997 int i;
7998
7999 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8000 if (error == NULL)
8001 return NULL;
8002
8003 for_each_pipe(i) {
8004 error->cursor[i].control = I915_READ(CURCNTR(i));
8005 error->cursor[i].position = I915_READ(CURPOS(i));
8006 error->cursor[i].base = I915_READ(CURBASE(i));
8007
8008 error->plane[i].control = I915_READ(DSPCNTR(i));
8009 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8010 error->plane[i].size = I915_READ(DSPSIZE(i));
8011 error->plane[i].pos = I915_READ(DSPPOS(i));
8012 error->plane[i].addr = I915_READ(DSPADDR(i));
8013 if (INTEL_INFO(dev)->gen >= 4) {
8014 error->plane[i].surface = I915_READ(DSPSURF(i));
8015 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8016 }
8017
8018 error->pipe[i].conf = I915_READ(PIPECONF(i));
8019 error->pipe[i].source = I915_READ(PIPESRC(i));
8020 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8021 error->pipe[i].hblank = I915_READ(HBLANK(i));
8022 error->pipe[i].hsync = I915_READ(HSYNC(i));
8023 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8024 error->pipe[i].vblank = I915_READ(VBLANK(i));
8025 error->pipe[i].vsync = I915_READ(VSYNC(i));
8026 }
8027
8028 return error;
8029 }
8030
8031 void
8032 intel_display_print_error_state(struct seq_file *m,
8033 struct drm_device *dev,
8034 struct intel_display_error_state *error)
8035 {
8036 drm_i915_private_t *dev_priv = dev->dev_private;
8037 int i;
8038
8039 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8040 for_each_pipe(i) {
8041 seq_printf(m, "Pipe [%d]:\n", i);
8042 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8043 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8044 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8045 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8046 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8047 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8048 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8049 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8050
8051 seq_printf(m, "Plane [%d]:\n", i);
8052 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8053 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8054 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8055 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8056 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8057 if (INTEL_INFO(dev)->gen >= 4) {
8058 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8059 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8060 }
8061
8062 seq_printf(m, "Cursor [%d]:\n", i);
8063 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8064 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8065 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8066 }
8067 }
8068 #endif
Linux kernel - Deliverables
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