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drm/i915/skl: Don't create a VGA connector on Skylake
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267 state = true;
1268
1269 if (!intel_display_power_enabled(dev_priv,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271 cur_state = false;
1272 } else {
1273 reg = PIPECONF(cpu_transcoder);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & PIPECONF_ENABLE);
1276 }
1277
1278 WARN(cur_state != state,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, bool state)
1285 {
1286 int reg;
1287 u32 val;
1288 bool cur_state;
1289
1290 reg = DSPCNTR(plane);
1291 val = I915_READ(reg);
1292 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293 WARN(cur_state != state,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe)
1303 {
1304 struct drm_device *dev = dev_priv->dev;
1305 int reg, i;
1306 u32 val;
1307 int cur_pipe;
1308
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev)->gen >= 4) {
1311 reg = DSPCNTR(pipe);
1312 val = I915_READ(reg);
1313 WARN(val & DISPLAY_PLANE_ENABLE,
1314 "plane %c assertion failure, should be disabled but not\n",
1315 plane_name(pipe));
1316 return;
1317 }
1318
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv, i) {
1321 reg = DSPCNTR(i);
1322 val = I915_READ(reg);
1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324 DISPPLANE_SEL_PIPE_SHIFT;
1325 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int reg, sprite;
1336 u32 val;
1337
1338 if (IS_VALLEYVIEW(dev)) {
1339 for_each_sprite(pipe, sprite) {
1340 reg = SPCNTR(pipe, sprite);
1341 val = I915_READ(reg);
1342 WARN(val & SP_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe, sprite), pipe_name(pipe));
1345 }
1346 } else if (INTEL_INFO(dev)->gen >= 7) {
1347 reg = SPRCTL(pipe);
1348 val = I915_READ(reg);
1349 WARN(val & SPRITE_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe), pipe_name(pipe));
1352 } else if (INTEL_INFO(dev)->gen >= 5) {
1353 reg = DVSCNTR(pipe);
1354 val = I915_READ(reg);
1355 WARN(val & DVS_ENABLE,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe), pipe_name(pipe));
1358 }
1359 }
1360
1361 static void assert_vblank_disabled(struct drm_crtc *crtc)
1362 {
1363 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1364 drm_crtc_vblank_put(crtc);
1365 }
1366
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1368 {
1369 u32 val;
1370 bool enabled;
1371
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1373
1374 val = I915_READ(PCH_DREF_CONTROL);
1375 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1376 DREF_SUPERSPREAD_SOURCE_MASK));
1377 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1378 }
1379
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1381 enum pipe pipe)
1382 {
1383 int reg;
1384 u32 val;
1385 bool enabled;
1386
1387 reg = PCH_TRANSCONF(pipe);
1388 val = I915_READ(reg);
1389 enabled = !!(val & TRANS_ENABLE);
1390 WARN(enabled,
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1392 pipe_name(pipe));
1393 }
1394
1395 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe, u32 port_sel, u32 val)
1397 {
1398 if ((val & DP_PORT_EN) == 0)
1399 return false;
1400
1401 if (HAS_PCH_CPT(dev_priv->dev)) {
1402 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1403 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1404 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1405 return false;
1406 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1407 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1408 return false;
1409 } else {
1410 if ((val & DP_PIPE_MASK) != (pipe << 30))
1411 return false;
1412 }
1413 return true;
1414 }
1415
1416 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 val)
1418 {
1419 if ((val & SDVO_ENABLE) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv->dev)) {
1423 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1424 return false;
1425 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1426 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1427 return false;
1428 } else {
1429 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & LVDS_PORT_EN) == 0)
1439 return false;
1440
1441 if (HAS_PCH_CPT(dev_priv->dev)) {
1442 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1443 return false;
1444 } else {
1445 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & ADPA_DAC_ENABLE) == 0)
1455 return false;
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, int reg, u32 port_sel)
1468 {
1469 u32 val = I915_READ(reg);
1470 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg, pipe_name(pipe));
1473
1474 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1475 && (val & DP_PIPEB_SELECT),
1476 "IBX PCH dp port still using transcoder B\n");
1477 }
1478
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, int reg)
1481 {
1482 u32 val = I915_READ(reg);
1483 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg, pipe_name(pipe));
1486
1487 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1488 && (val & SDVO_PIPE_B_SELECT),
1489 "IBX PCH hdmi port still using transcoder B\n");
1490 }
1491
1492 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe)
1494 {
1495 int reg;
1496 u32 val;
1497
1498 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1499 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1500 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1501
1502 reg = PCH_ADPA;
1503 val = I915_READ(reg);
1504 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1506 pipe_name(pipe));
1507
1508 reg = PCH_LVDS;
1509 val = I915_READ(reg);
1510 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1512 pipe_name(pipe));
1513
1514 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1515 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1516 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1517 }
1518
1519 static void intel_init_dpio(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 if (!IS_VALLEYVIEW(dev))
1524 return;
1525
1526 /*
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1530 */
1531 if (IS_CHERRYVIEW(dev)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1534 } else {
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1536 }
1537 }
1538
1539 static void vlv_enable_pll(struct intel_crtc *crtc)
1540 {
1541 struct drm_device *dev = crtc->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 int reg = DPLL(crtc->pipe);
1544 u32 dpll = crtc->config.dpll_hw_state.dpll;
1545
1546 assert_pipe_disabled(dev_priv, crtc->pipe);
1547
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1550
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv->dev))
1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555 I915_WRITE(reg, dpll);
1556 POSTING_READ(reg);
1557 udelay(150);
1558
1559 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1561
1562 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1563 POSTING_READ(DPLL_MD(crtc->pipe));
1564
1565 /* We do this three times for luck */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg, dpll);
1573 POSTING_READ(reg);
1574 udelay(150); /* wait for warmup */
1575 }
1576
1577 static void chv_enable_pll(struct intel_crtc *crtc)
1578 {
1579 struct drm_device *dev = crtc->base.dev;
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 int pipe = crtc->pipe;
1582 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1583 u32 tmp;
1584
1585 assert_pipe_disabled(dev_priv, crtc->pipe);
1586
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1588
1589 mutex_lock(&dev_priv->dpio_lock);
1590
1591 /* Enable back the 10bit clock to display controller */
1592 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1593 tmp |= DPIO_DCLKP_EN;
1594 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1595
1596 /*
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1598 */
1599 udelay(1);
1600
1601 /* Enable PLL */
1602 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1603
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe);
1607
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1610 POSTING_READ(DPLL_MD(pipe));
1611
1612 mutex_unlock(&dev_priv->dpio_lock);
1613 }
1614
1615 static void i9xx_enable_pll(struct intel_crtc *crtc)
1616 {
1617 struct drm_device *dev = crtc->base.dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 int reg = DPLL(crtc->pipe);
1620 u32 dpll = crtc->config.dpll_hw_state.dpll;
1621
1622 assert_pipe_disabled(dev_priv, crtc->pipe);
1623
1624 /* No really, not for ILK+ */
1625 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1626
1627 /* PLL is protected by panel, make sure we can write it */
1628 if (IS_MOBILE(dev) && !IS_I830(dev))
1629 assert_panel_unlocked(dev_priv, crtc->pipe);
1630
1631 I915_WRITE(reg, dpll);
1632
1633 /* Wait for the clocks to stabilize. */
1634 POSTING_READ(reg);
1635 udelay(150);
1636
1637 if (INTEL_INFO(dev)->gen >= 4) {
1638 I915_WRITE(DPLL_MD(crtc->pipe),
1639 crtc->config.dpll_hw_state.dpll_md);
1640 } else {
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1643 *
1644 * So write it again.
1645 */
1646 I915_WRITE(reg, dpll);
1647 }
1648
1649 /* We do this three times for luck */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg, dpll);
1657 POSTING_READ(reg);
1658 udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1665 *
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1667 *
1668 * Note! This is for pre-ILK only.
1669 */
1670 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1671 {
1672 /* Don't disable pipe or pipe PLLs if needed */
1673 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1674 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1675 return;
1676
1677 /* Make sure the pipe isn't still relying on us */
1678 assert_pipe_disabled(dev_priv, pipe);
1679
1680 I915_WRITE(DPLL(pipe), 0);
1681 POSTING_READ(DPLL(pipe));
1682 }
1683
1684 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1685 {
1686 u32 val = 0;
1687
1688 /* Make sure the pipe isn't still relying on us */
1689 assert_pipe_disabled(dev_priv, pipe);
1690
1691 /*
1692 * Leave integrated clock source and reference clock enabled for pipe B.
1693 * The latter is needed for VGA hotplug / manual detection.
1694 */
1695 if (pipe == PIPE_B)
1696 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1697 I915_WRITE(DPLL(pipe), val);
1698 POSTING_READ(DPLL(pipe));
1699
1700 }
1701
1702 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1703 {
1704 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1705 u32 val;
1706
1707 /* Make sure the pipe isn't still relying on us */
1708 assert_pipe_disabled(dev_priv, pipe);
1709
1710 /* Set PLL en = 0 */
1711 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1712 if (pipe != PIPE_A)
1713 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1714 I915_WRITE(DPLL(pipe), val);
1715 POSTING_READ(DPLL(pipe));
1716
1717 mutex_lock(&dev_priv->dpio_lock);
1718
1719 /* Disable 10bit clock to display controller */
1720 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1721 val &= ~DPIO_DCLKP_EN;
1722 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1723
1724 /* disable left/right clock distribution */
1725 if (pipe != PIPE_B) {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1727 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1728 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1729 } else {
1730 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1731 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1732 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1733 }
1734
1735 mutex_unlock(&dev_priv->dpio_lock);
1736 }
1737
1738 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1739 struct intel_digital_port *dport)
1740 {
1741 u32 port_mask;
1742 int dpll_reg;
1743
1744 switch (dport->port) {
1745 case PORT_B:
1746 port_mask = DPLL_PORTB_READY_MASK;
1747 dpll_reg = DPLL(0);
1748 break;
1749 case PORT_C:
1750 port_mask = DPLL_PORTC_READY_MASK;
1751 dpll_reg = DPLL(0);
1752 break;
1753 case PORT_D:
1754 port_mask = DPLL_PORTD_READY_MASK;
1755 dpll_reg = DPIO_PHY_STATUS;
1756 break;
1757 default:
1758 BUG();
1759 }
1760
1761 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1762 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1763 port_name(dport->port), I915_READ(dpll_reg));
1764 }
1765
1766 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1767 {
1768 struct drm_device *dev = crtc->base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1771
1772 if (WARN_ON(pll == NULL))
1773 return;
1774
1775 WARN_ON(!pll->refcount);
1776 if (pll->active == 0) {
1777 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1778 WARN_ON(pll->on);
1779 assert_shared_dpll_disabled(dev_priv, pll);
1780
1781 pll->mode_set(dev_priv, pll);
1782 }
1783 }
1784
1785 /**
1786 * intel_enable_shared_dpll - enable PCH PLL
1787 * @dev_priv: i915 private structure
1788 * @pipe: pipe PLL to enable
1789 *
1790 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1791 * drives the transcoder clock.
1792 */
1793 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1794 {
1795 struct drm_device *dev = crtc->base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1798
1799 if (WARN_ON(pll == NULL))
1800 return;
1801
1802 if (WARN_ON(pll->refcount == 0))
1803 return;
1804
1805 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1806 pll->name, pll->active, pll->on,
1807 crtc->base.base.id);
1808
1809 if (pll->active++) {
1810 WARN_ON(!pll->on);
1811 assert_shared_dpll_enabled(dev_priv, pll);
1812 return;
1813 }
1814 WARN_ON(pll->on);
1815
1816 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1817
1818 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1819 pll->enable(dev_priv, pll);
1820 pll->on = true;
1821 }
1822
1823 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1824 {
1825 struct drm_device *dev = crtc->base.dev;
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1828
1829 /* PCH only available on ILK+ */
1830 BUG_ON(INTEL_INFO(dev)->gen < 5);
1831 if (WARN_ON(pll == NULL))
1832 return;
1833
1834 if (WARN_ON(pll->refcount == 0))
1835 return;
1836
1837 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1838 pll->name, pll->active, pll->on,
1839 crtc->base.base.id);
1840
1841 if (WARN_ON(pll->active == 0)) {
1842 assert_shared_dpll_disabled(dev_priv, pll);
1843 return;
1844 }
1845
1846 assert_shared_dpll_enabled(dev_priv, pll);
1847 WARN_ON(!pll->on);
1848 if (--pll->active)
1849 return;
1850
1851 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1852 pll->disable(dev_priv, pll);
1853 pll->on = false;
1854
1855 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1856 }
1857
1858 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1859 enum pipe pipe)
1860 {
1861 struct drm_device *dev = dev_priv->dev;
1862 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1864 uint32_t reg, val, pipeconf_val;
1865
1866 /* PCH only available on ILK+ */
1867 BUG_ON(!HAS_PCH_SPLIT(dev));
1868
1869 /* Make sure PCH DPLL is enabled */
1870 assert_shared_dpll_enabled(dev_priv,
1871 intel_crtc_to_shared_dpll(intel_crtc));
1872
1873 /* FDI must be feeding us bits for PCH ports */
1874 assert_fdi_tx_enabled(dev_priv, pipe);
1875 assert_fdi_rx_enabled(dev_priv, pipe);
1876
1877 if (HAS_PCH_CPT(dev)) {
1878 /* Workaround: Set the timing override bit before enabling the
1879 * pch transcoder. */
1880 reg = TRANS_CHICKEN2(pipe);
1881 val = I915_READ(reg);
1882 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1883 I915_WRITE(reg, val);
1884 }
1885
1886 reg = PCH_TRANSCONF(pipe);
1887 val = I915_READ(reg);
1888 pipeconf_val = I915_READ(PIPECONF(pipe));
1889
1890 if (HAS_PCH_IBX(dev_priv->dev)) {
1891 /*
1892 * make the BPC in transcoder be consistent with
1893 * that in pipeconf reg.
1894 */
1895 val &= ~PIPECONF_BPC_MASK;
1896 val |= pipeconf_val & PIPECONF_BPC_MASK;
1897 }
1898
1899 val &= ~TRANS_INTERLACE_MASK;
1900 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1901 if (HAS_PCH_IBX(dev_priv->dev) &&
1902 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1903 val |= TRANS_LEGACY_INTERLACED_ILK;
1904 else
1905 val |= TRANS_INTERLACED;
1906 else
1907 val |= TRANS_PROGRESSIVE;
1908
1909 I915_WRITE(reg, val | TRANS_ENABLE);
1910 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1911 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1912 }
1913
1914 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1915 enum transcoder cpu_transcoder)
1916 {
1917 u32 val, pipeconf_val;
1918
1919 /* PCH only available on ILK+ */
1920 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1921
1922 /* FDI must be feeding us bits for PCH ports */
1923 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1924 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1925
1926 /* Workaround: set timing override bit. */
1927 val = I915_READ(_TRANSA_CHICKEN2);
1928 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1929 I915_WRITE(_TRANSA_CHICKEN2, val);
1930
1931 val = TRANS_ENABLE;
1932 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1933
1934 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1935 PIPECONF_INTERLACED_ILK)
1936 val |= TRANS_INTERLACED;
1937 else
1938 val |= TRANS_PROGRESSIVE;
1939
1940 I915_WRITE(LPT_TRANSCONF, val);
1941 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1942 DRM_ERROR("Failed to enable PCH transcoder\n");
1943 }
1944
1945 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1946 enum pipe pipe)
1947 {
1948 struct drm_device *dev = dev_priv->dev;
1949 uint32_t reg, val;
1950
1951 /* FDI relies on the transcoder */
1952 assert_fdi_tx_disabled(dev_priv, pipe);
1953 assert_fdi_rx_disabled(dev_priv, pipe);
1954
1955 /* Ports must be off as well */
1956 assert_pch_ports_disabled(dev_priv, pipe);
1957
1958 reg = PCH_TRANSCONF(pipe);
1959 val = I915_READ(reg);
1960 val &= ~TRANS_ENABLE;
1961 I915_WRITE(reg, val);
1962 /* wait for PCH transcoder off, transcoder state */
1963 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1964 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1965
1966 if (!HAS_PCH_IBX(dev)) {
1967 /* Workaround: Clear the timing override chicken bit again. */
1968 reg = TRANS_CHICKEN2(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1971 I915_WRITE(reg, val);
1972 }
1973 }
1974
1975 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1976 {
1977 u32 val;
1978
1979 val = I915_READ(LPT_TRANSCONF);
1980 val &= ~TRANS_ENABLE;
1981 I915_WRITE(LPT_TRANSCONF, val);
1982 /* wait for PCH transcoder off, transcoder state */
1983 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1984 DRM_ERROR("Failed to disable PCH transcoder\n");
1985
1986 /* Workaround: clear timing override bit. */
1987 val = I915_READ(_TRANSA_CHICKEN2);
1988 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1989 I915_WRITE(_TRANSA_CHICKEN2, val);
1990 }
1991
1992 /**
1993 * intel_enable_pipe - enable a pipe, asserting requirements
1994 * @crtc: crtc responsible for the pipe
1995 *
1996 * Enable @crtc's pipe, making sure that various hardware specific requirements
1997 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1998 */
1999 static void intel_enable_pipe(struct intel_crtc *crtc)
2000 {
2001 struct drm_device *dev = crtc->base.dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 enum pipe pipe = crtc->pipe;
2004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2005 pipe);
2006 enum pipe pch_transcoder;
2007 int reg;
2008 u32 val;
2009
2010 assert_planes_disabled(dev_priv, pipe);
2011 assert_cursor_disabled(dev_priv, pipe);
2012 assert_sprites_disabled(dev_priv, pipe);
2013
2014 if (HAS_PCH_LPT(dev_priv->dev))
2015 pch_transcoder = TRANSCODER_A;
2016 else
2017 pch_transcoder = pipe;
2018
2019 /*
2020 * A pipe without a PLL won't actually be able to drive bits from
2021 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2022 * need the check.
2023 */
2024 if (!HAS_PCH_SPLIT(dev_priv->dev))
2025 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2026 assert_dsi_pll_enabled(dev_priv);
2027 else
2028 assert_pll_enabled(dev_priv, pipe);
2029 else {
2030 if (crtc->config.has_pch_encoder) {
2031 /* if driving the PCH, we need FDI enabled */
2032 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2033 assert_fdi_tx_pll_enabled(dev_priv,
2034 (enum pipe) cpu_transcoder);
2035 }
2036 /* FIXME: assert CPU port conditions for SNB+ */
2037 }
2038
2039 reg = PIPECONF(cpu_transcoder);
2040 val = I915_READ(reg);
2041 if (val & PIPECONF_ENABLE) {
2042 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2043 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2044 return;
2045 }
2046
2047 I915_WRITE(reg, val | PIPECONF_ENABLE);
2048 POSTING_READ(reg);
2049 }
2050
2051 /**
2052 * intel_disable_pipe - disable a pipe, asserting requirements
2053 * @crtc: crtc whose pipes is to be disabled
2054 *
2055 * Disable the pipe of @crtc, making sure that various hardware
2056 * specific requirements are met, if applicable, e.g. plane
2057 * disabled, panel fitter off, etc.
2058 *
2059 * Will wait until the pipe has shut down before returning.
2060 */
2061 static void intel_disable_pipe(struct intel_crtc *crtc)
2062 {
2063 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2064 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2065 enum pipe pipe = crtc->pipe;
2066 int reg;
2067 u32 val;
2068
2069 /*
2070 * Make sure planes won't keep trying to pump pixels to us,
2071 * or we might hang the display.
2072 */
2073 assert_planes_disabled(dev_priv, pipe);
2074 assert_cursor_disabled(dev_priv, pipe);
2075 assert_sprites_disabled(dev_priv, pipe);
2076
2077 reg = PIPECONF(cpu_transcoder);
2078 val = I915_READ(reg);
2079 if ((val & PIPECONF_ENABLE) == 0)
2080 return;
2081
2082 /*
2083 * Double wide has implications for planes
2084 * so best keep it disabled when not needed.
2085 */
2086 if (crtc->config.double_wide)
2087 val &= ~PIPECONF_DOUBLE_WIDE;
2088
2089 /* Don't disable pipe or pipe PLLs if needed */
2090 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2091 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2092 val &= ~PIPECONF_ENABLE;
2093
2094 I915_WRITE(reg, val);
2095 if ((val & PIPECONF_ENABLE) == 0)
2096 intel_wait_for_pipe_off(crtc);
2097 }
2098
2099 /*
2100 * Plane regs are double buffered, going from enabled->disabled needs a
2101 * trigger in order to latch. The display address reg provides this.
2102 */
2103 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2104 enum plane plane)
2105 {
2106 struct drm_device *dev = dev_priv->dev;
2107 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2108
2109 I915_WRITE(reg, I915_READ(reg));
2110 POSTING_READ(reg);
2111 }
2112
2113 /**
2114 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2115 * @plane: plane to be enabled
2116 * @crtc: crtc for the plane
2117 *
2118 * Enable @plane on @crtc, making sure that the pipe is running first.
2119 */
2120 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2121 struct drm_crtc *crtc)
2122 {
2123 struct drm_device *dev = plane->dev;
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2129
2130 if (intel_crtc->primary_enabled)
2131 return;
2132
2133 intel_crtc->primary_enabled = true;
2134
2135 dev_priv->display.update_primary_plane(crtc, plane->fb,
2136 crtc->x, crtc->y);
2137
2138 /*
2139 * BDW signals flip done immediately if the plane
2140 * is disabled, even if the plane enable is already
2141 * armed to occur at the next vblank :(
2142 */
2143 if (IS_BROADWELL(dev))
2144 intel_wait_for_vblank(dev, intel_crtc->pipe);
2145 }
2146
2147 /**
2148 * intel_disable_primary_hw_plane - disable the primary hardware plane
2149 * @plane: plane to be disabled
2150 * @crtc: crtc for the plane
2151 *
2152 * Disable @plane on @crtc, making sure that the pipe is running first.
2153 */
2154 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2155 struct drm_crtc *crtc)
2156 {
2157 struct drm_device *dev = plane->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2160
2161 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2162
2163 if (!intel_crtc->primary_enabled)
2164 return;
2165
2166 intel_crtc->primary_enabled = false;
2167
2168 dev_priv->display.update_primary_plane(crtc, plane->fb,
2169 crtc->x, crtc->y);
2170 }
2171
2172 static bool need_vtd_wa(struct drm_device *dev)
2173 {
2174 #ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2176 return true;
2177 #endif
2178 return false;
2179 }
2180
2181 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2182 {
2183 int tile_height;
2184
2185 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2186 return ALIGN(height, tile_height);
2187 }
2188
2189 int
2190 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2191 struct drm_i915_gem_object *obj,
2192 struct intel_engine_cs *pipelined)
2193 {
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195 u32 alignment;
2196 int ret;
2197
2198 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2199
2200 switch (obj->tiling_mode) {
2201 case I915_TILING_NONE:
2202 if (INTEL_INFO(dev)->gen >= 9)
2203 alignment = 256 * 1024;
2204 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2205 alignment = 128 * 1024;
2206 else if (INTEL_INFO(dev)->gen >= 4)
2207 alignment = 4 * 1024;
2208 else
2209 alignment = 64 * 1024;
2210 break;
2211 case I915_TILING_X:
2212 if (INTEL_INFO(dev)->gen >= 9)
2213 alignment = 256 * 1024;
2214 else {
2215 /* pin() will align the object as required by fence */
2216 alignment = 0;
2217 }
2218 break;
2219 case I915_TILING_Y:
2220 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2221 return -EINVAL;
2222 default:
2223 BUG();
2224 }
2225
2226 /* Note that the w/a also requires 64 PTE of padding following the
2227 * bo. We currently fill all unused PTE with the shadow page and so
2228 * we should always have valid PTE following the scanout preventing
2229 * the VT-d warning.
2230 */
2231 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2232 alignment = 256 * 1024;
2233
2234 /*
2235 * Global gtt pte registers are special registers which actually forward
2236 * writes to a chunk of system memory. Which means that there is no risk
2237 * that the register values disappear as soon as we call
2238 * intel_runtime_pm_put(), so it is correct to wrap only the
2239 * pin/unpin/fence and not more.
2240 */
2241 intel_runtime_pm_get(dev_priv);
2242
2243 dev_priv->mm.interruptible = false;
2244 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2245 if (ret)
2246 goto err_interruptible;
2247
2248 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2249 * fence, whereas 965+ only requires a fence if using
2250 * framebuffer compression. For simplicity, we always install
2251 * a fence as the cost is not that onerous.
2252 */
2253 ret = i915_gem_object_get_fence(obj);
2254 if (ret)
2255 goto err_unpin;
2256
2257 i915_gem_object_pin_fence(obj);
2258
2259 dev_priv->mm.interruptible = true;
2260 intel_runtime_pm_put(dev_priv);
2261 return 0;
2262
2263 err_unpin:
2264 i915_gem_object_unpin_from_display_plane(obj);
2265 err_interruptible:
2266 dev_priv->mm.interruptible = true;
2267 intel_runtime_pm_put(dev_priv);
2268 return ret;
2269 }
2270
2271 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2272 {
2273 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2274
2275 i915_gem_object_unpin_fence(obj);
2276 i915_gem_object_unpin_from_display_plane(obj);
2277 }
2278
2279 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2280 * is assumed to be a power-of-two. */
2281 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2282 unsigned int tiling_mode,
2283 unsigned int cpp,
2284 unsigned int pitch)
2285 {
2286 if (tiling_mode != I915_TILING_NONE) {
2287 unsigned int tile_rows, tiles;
2288
2289 tile_rows = *y / 8;
2290 *y %= 8;
2291
2292 tiles = *x / (512/cpp);
2293 *x %= 512/cpp;
2294
2295 return tile_rows * pitch * 8 + tiles * 4096;
2296 } else {
2297 unsigned int offset;
2298
2299 offset = *y * pitch + *x * cpp;
2300 *y = 0;
2301 *x = (offset & 4095) / cpp;
2302 return offset & -4096;
2303 }
2304 }
2305
2306 int intel_format_to_fourcc(int format)
2307 {
2308 switch (format) {
2309 case DISPPLANE_8BPP:
2310 return DRM_FORMAT_C8;
2311 case DISPPLANE_BGRX555:
2312 return DRM_FORMAT_XRGB1555;
2313 case DISPPLANE_BGRX565:
2314 return DRM_FORMAT_RGB565;
2315 default:
2316 case DISPPLANE_BGRX888:
2317 return DRM_FORMAT_XRGB8888;
2318 case DISPPLANE_RGBX888:
2319 return DRM_FORMAT_XBGR8888;
2320 case DISPPLANE_BGRX101010:
2321 return DRM_FORMAT_XRGB2101010;
2322 case DISPPLANE_RGBX101010:
2323 return DRM_FORMAT_XBGR2101010;
2324 }
2325 }
2326
2327 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2328 struct intel_plane_config *plane_config)
2329 {
2330 struct drm_device *dev = crtc->base.dev;
2331 struct drm_i915_gem_object *obj = NULL;
2332 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2333 u32 base = plane_config->base;
2334
2335 if (plane_config->size == 0)
2336 return false;
2337
2338 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2339 plane_config->size);
2340 if (!obj)
2341 return false;
2342
2343 if (plane_config->tiled) {
2344 obj->tiling_mode = I915_TILING_X;
2345 obj->stride = crtc->base.primary->fb->pitches[0];
2346 }
2347
2348 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2349 mode_cmd.width = crtc->base.primary->fb->width;
2350 mode_cmd.height = crtc->base.primary->fb->height;
2351 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2352
2353 mutex_lock(&dev->struct_mutex);
2354
2355 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2356 &mode_cmd, obj)) {
2357 DRM_DEBUG_KMS("intel fb init failed\n");
2358 goto out_unref_obj;
2359 }
2360
2361 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2362 mutex_unlock(&dev->struct_mutex);
2363
2364 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2365 return true;
2366
2367 out_unref_obj:
2368 drm_gem_object_unreference(&obj->base);
2369 mutex_unlock(&dev->struct_mutex);
2370 return false;
2371 }
2372
2373 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2374 struct intel_plane_config *plane_config)
2375 {
2376 struct drm_device *dev = intel_crtc->base.dev;
2377 struct drm_crtc *c;
2378 struct intel_crtc *i;
2379 struct drm_i915_gem_object *obj;
2380
2381 if (!intel_crtc->base.primary->fb)
2382 return;
2383
2384 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2385 return;
2386
2387 kfree(intel_crtc->base.primary->fb);
2388 intel_crtc->base.primary->fb = NULL;
2389
2390 /*
2391 * Failed to alloc the obj, check to see if we should share
2392 * an fb with another CRTC instead
2393 */
2394 for_each_crtc(dev, c) {
2395 i = to_intel_crtc(c);
2396
2397 if (c == &intel_crtc->base)
2398 continue;
2399
2400 if (!i->active)
2401 continue;
2402
2403 obj = intel_fb_obj(c->primary->fb);
2404 if (obj == NULL)
2405 continue;
2406
2407 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2408 drm_framebuffer_reference(c->primary->fb);
2409 intel_crtc->base.primary->fb = c->primary->fb;
2410 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2411 break;
2412 }
2413 }
2414 }
2415
2416 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2417 struct drm_framebuffer *fb,
2418 int x, int y)
2419 {
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 struct drm_i915_gem_object *obj;
2424 int plane = intel_crtc->plane;
2425 unsigned long linear_offset;
2426 u32 dspcntr;
2427 u32 reg = DSPCNTR(plane);
2428 int pixel_size;
2429
2430 if (!intel_crtc->primary_enabled) {
2431 I915_WRITE(reg, 0);
2432 if (INTEL_INFO(dev)->gen >= 4)
2433 I915_WRITE(DSPSURF(plane), 0);
2434 else
2435 I915_WRITE(DSPADDR(plane), 0);
2436 POSTING_READ(reg);
2437 return;
2438 }
2439
2440 obj = intel_fb_obj(fb);
2441 if (WARN_ON(obj == NULL))
2442 return;
2443
2444 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2445
2446 dspcntr = DISPPLANE_GAMMA_ENABLE;
2447
2448 dspcntr |= DISPLAY_PLANE_ENABLE;
2449
2450 if (INTEL_INFO(dev)->gen < 4) {
2451 if (intel_crtc->pipe == PIPE_B)
2452 dspcntr |= DISPPLANE_SEL_PIPE_B;
2453
2454 /* pipesrc and dspsize control the size that is scaled from,
2455 * which should always be the user's requested size.
2456 */
2457 I915_WRITE(DSPSIZE(plane),
2458 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2459 (intel_crtc->config.pipe_src_w - 1));
2460 I915_WRITE(DSPPOS(plane), 0);
2461 }
2462
2463 switch (fb->pixel_format) {
2464 case DRM_FORMAT_C8:
2465 dspcntr |= DISPPLANE_8BPP;
2466 break;
2467 case DRM_FORMAT_XRGB1555:
2468 case DRM_FORMAT_ARGB1555:
2469 dspcntr |= DISPPLANE_BGRX555;
2470 break;
2471 case DRM_FORMAT_RGB565:
2472 dspcntr |= DISPPLANE_BGRX565;
2473 break;
2474 case DRM_FORMAT_XRGB8888:
2475 case DRM_FORMAT_ARGB8888:
2476 dspcntr |= DISPPLANE_BGRX888;
2477 break;
2478 case DRM_FORMAT_XBGR8888:
2479 case DRM_FORMAT_ABGR8888:
2480 dspcntr |= DISPPLANE_RGBX888;
2481 break;
2482 case DRM_FORMAT_XRGB2101010:
2483 case DRM_FORMAT_ARGB2101010:
2484 dspcntr |= DISPPLANE_BGRX101010;
2485 break;
2486 case DRM_FORMAT_XBGR2101010:
2487 case DRM_FORMAT_ABGR2101010:
2488 dspcntr |= DISPPLANE_RGBX101010;
2489 break;
2490 default:
2491 BUG();
2492 }
2493
2494 if (INTEL_INFO(dev)->gen >= 4 &&
2495 obj->tiling_mode != I915_TILING_NONE)
2496 dspcntr |= DISPPLANE_TILED;
2497
2498 if (IS_G4X(dev))
2499 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2500
2501 linear_offset = y * fb->pitches[0] + x * pixel_size;
2502
2503 if (INTEL_INFO(dev)->gen >= 4) {
2504 intel_crtc->dspaddr_offset =
2505 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2506 pixel_size,
2507 fb->pitches[0]);
2508 linear_offset -= intel_crtc->dspaddr_offset;
2509 } else {
2510 intel_crtc->dspaddr_offset = linear_offset;
2511 }
2512
2513 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2514 dspcntr |= DISPPLANE_ROTATE_180;
2515
2516 x += (intel_crtc->config.pipe_src_w - 1);
2517 y += (intel_crtc->config.pipe_src_h - 1);
2518
2519 /* Finding the last pixel of the last line of the display
2520 data and adding to linear_offset*/
2521 linear_offset +=
2522 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2523 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2524 }
2525
2526 I915_WRITE(reg, dspcntr);
2527
2528 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2529 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2530 fb->pitches[0]);
2531 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2532 if (INTEL_INFO(dev)->gen >= 4) {
2533 I915_WRITE(DSPSURF(plane),
2534 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2535 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2536 I915_WRITE(DSPLINOFF(plane), linear_offset);
2537 } else
2538 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2539 POSTING_READ(reg);
2540 }
2541
2542 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2543 struct drm_framebuffer *fb,
2544 int x, int y)
2545 {
2546 struct drm_device *dev = crtc->dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549 struct drm_i915_gem_object *obj;
2550 int plane = intel_crtc->plane;
2551 unsigned long linear_offset;
2552 u32 dspcntr;
2553 u32 reg = DSPCNTR(plane);
2554 int pixel_size;
2555
2556 if (!intel_crtc->primary_enabled) {
2557 I915_WRITE(reg, 0);
2558 I915_WRITE(DSPSURF(plane), 0);
2559 POSTING_READ(reg);
2560 return;
2561 }
2562
2563 obj = intel_fb_obj(fb);
2564 if (WARN_ON(obj == NULL))
2565 return;
2566
2567 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2568
2569 dspcntr = DISPPLANE_GAMMA_ENABLE;
2570
2571 dspcntr |= DISPLAY_PLANE_ENABLE;
2572
2573 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2574 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2575
2576 switch (fb->pixel_format) {
2577 case DRM_FORMAT_C8:
2578 dspcntr |= DISPPLANE_8BPP;
2579 break;
2580 case DRM_FORMAT_RGB565:
2581 dspcntr |= DISPPLANE_BGRX565;
2582 break;
2583 case DRM_FORMAT_XRGB8888:
2584 case DRM_FORMAT_ARGB8888:
2585 dspcntr |= DISPPLANE_BGRX888;
2586 break;
2587 case DRM_FORMAT_XBGR8888:
2588 case DRM_FORMAT_ABGR8888:
2589 dspcntr |= DISPPLANE_RGBX888;
2590 break;
2591 case DRM_FORMAT_XRGB2101010:
2592 case DRM_FORMAT_ARGB2101010:
2593 dspcntr |= DISPPLANE_BGRX101010;
2594 break;
2595 case DRM_FORMAT_XBGR2101010:
2596 case DRM_FORMAT_ABGR2101010:
2597 dspcntr |= DISPPLANE_RGBX101010;
2598 break;
2599 default:
2600 BUG();
2601 }
2602
2603 if (obj->tiling_mode != I915_TILING_NONE)
2604 dspcntr |= DISPPLANE_TILED;
2605
2606 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2607 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2608
2609 linear_offset = y * fb->pitches[0] + x * pixel_size;
2610 intel_crtc->dspaddr_offset =
2611 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2612 pixel_size,
2613 fb->pitches[0]);
2614 linear_offset -= intel_crtc->dspaddr_offset;
2615 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2616 dspcntr |= DISPPLANE_ROTATE_180;
2617
2618 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2619 x += (intel_crtc->config.pipe_src_w - 1);
2620 y += (intel_crtc->config.pipe_src_h - 1);
2621
2622 /* Finding the last pixel of the last line of the display
2623 data and adding to linear_offset*/
2624 linear_offset +=
2625 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2626 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2627 }
2628 }
2629
2630 I915_WRITE(reg, dspcntr);
2631
2632 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2633 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2634 fb->pitches[0]);
2635 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2636 I915_WRITE(DSPSURF(plane),
2637 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2638 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2639 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2640 } else {
2641 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2642 I915_WRITE(DSPLINOFF(plane), linear_offset);
2643 }
2644 POSTING_READ(reg);
2645 }
2646
2647 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2648 struct drm_framebuffer *fb,
2649 int x, int y)
2650 {
2651 struct drm_device *dev = crtc->dev;
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2654 struct intel_framebuffer *intel_fb;
2655 struct drm_i915_gem_object *obj;
2656 int pipe = intel_crtc->pipe;
2657 u32 plane_ctl, stride;
2658
2659 if (!intel_crtc->primary_enabled) {
2660 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2661 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2662 POSTING_READ(PLANE_CTL(pipe, 0));
2663 return;
2664 }
2665
2666 plane_ctl = PLANE_CTL_ENABLE |
2667 PLANE_CTL_PIPE_GAMMA_ENABLE |
2668 PLANE_CTL_PIPE_CSC_ENABLE;
2669
2670 switch (fb->pixel_format) {
2671 case DRM_FORMAT_RGB565:
2672 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2673 break;
2674 case DRM_FORMAT_XRGB8888:
2675 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2676 break;
2677 case DRM_FORMAT_XBGR8888:
2678 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2679 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2680 break;
2681 case DRM_FORMAT_XRGB2101010:
2682 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2683 break;
2684 case DRM_FORMAT_XBGR2101010:
2685 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2686 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2687 break;
2688 default:
2689 BUG();
2690 }
2691
2692 intel_fb = to_intel_framebuffer(fb);
2693 obj = intel_fb->obj;
2694
2695 /*
2696 * The stride is either expressed as a multiple of 64 bytes chunks for
2697 * linear buffers or in number of tiles for tiled buffers.
2698 */
2699 switch (obj->tiling_mode) {
2700 case I915_TILING_NONE:
2701 stride = fb->pitches[0] >> 6;
2702 break;
2703 case I915_TILING_X:
2704 plane_ctl |= PLANE_CTL_TILED_X;
2705 stride = fb->pitches[0] >> 9;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2712
2713 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2714
2715 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2716 i915_gem_obj_ggtt_offset(obj),
2717 x, y, fb->width, fb->height,
2718 fb->pitches[0]);
2719
2720 I915_WRITE(PLANE_POS(pipe, 0), 0);
2721 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2722 I915_WRITE(PLANE_SIZE(pipe, 0),
2723 (intel_crtc->config.pipe_src_h - 1) << 16 |
2724 (intel_crtc->config.pipe_src_w - 1));
2725 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2726 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2727
2728 POSTING_READ(PLANE_SURF(pipe, 0));
2729 }
2730
2731 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2732 static int
2733 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2734 int x, int y, enum mode_set_atomic state)
2735 {
2736 struct drm_device *dev = crtc->dev;
2737 struct drm_i915_private *dev_priv = dev->dev_private;
2738
2739 if (dev_priv->display.disable_fbc)
2740 dev_priv->display.disable_fbc(dev);
2741 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2742
2743 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2744
2745 return 0;
2746 }
2747
2748 void intel_display_handle_reset(struct drm_device *dev)
2749 {
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 struct drm_crtc *crtc;
2752
2753 /*
2754 * Flips in the rings have been nuked by the reset,
2755 * so complete all pending flips so that user space
2756 * will get its events and not get stuck.
2757 *
2758 * Also update the base address of all primary
2759 * planes to the the last fb to make sure we're
2760 * showing the correct fb after a reset.
2761 *
2762 * Need to make two loops over the crtcs so that we
2763 * don't try to grab a crtc mutex before the
2764 * pending_flip_queue really got woken up.
2765 */
2766
2767 for_each_crtc(dev, crtc) {
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 enum plane plane = intel_crtc->plane;
2770
2771 intel_prepare_page_flip(dev, plane);
2772 intel_finish_page_flip_plane(dev, plane);
2773 }
2774
2775 for_each_crtc(dev, crtc) {
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777
2778 drm_modeset_lock(&crtc->mutex, NULL);
2779 /*
2780 * FIXME: Once we have proper support for primary planes (and
2781 * disabling them without disabling the entire crtc) allow again
2782 * a NULL crtc->primary->fb.
2783 */
2784 if (intel_crtc->active && crtc->primary->fb)
2785 dev_priv->display.update_primary_plane(crtc,
2786 crtc->primary->fb,
2787 crtc->x,
2788 crtc->y);
2789 drm_modeset_unlock(&crtc->mutex);
2790 }
2791 }
2792
2793 static int
2794 intel_finish_fb(struct drm_framebuffer *old_fb)
2795 {
2796 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2797 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2798 bool was_interruptible = dev_priv->mm.interruptible;
2799 int ret;
2800
2801 /* Big Hammer, we also need to ensure that any pending
2802 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2803 * current scanout is retired before unpinning the old
2804 * framebuffer.
2805 *
2806 * This should only fail upon a hung GPU, in which case we
2807 * can safely continue.
2808 */
2809 dev_priv->mm.interruptible = false;
2810 ret = i915_gem_object_finish_gpu(obj);
2811 dev_priv->mm.interruptible = was_interruptible;
2812
2813 return ret;
2814 }
2815
2816 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2817 {
2818 struct drm_device *dev = crtc->dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 unsigned long flags;
2822 bool pending;
2823
2824 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2825 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2826 return false;
2827
2828 spin_lock_irqsave(&dev->event_lock, flags);
2829 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2830 spin_unlock_irqrestore(&dev->event_lock, flags);
2831
2832 return pending;
2833 }
2834
2835 static int
2836 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2837 struct drm_framebuffer *fb)
2838 {
2839 struct drm_device *dev = crtc->dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2842 enum pipe pipe = intel_crtc->pipe;
2843 struct drm_framebuffer *old_fb = crtc->primary->fb;
2844 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2845 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2846 int ret;
2847
2848 if (intel_crtc_has_pending_flip(crtc)) {
2849 DRM_ERROR("pipe is still busy with an old pageflip\n");
2850 return -EBUSY;
2851 }
2852
2853 /* no fb bound */
2854 if (!fb) {
2855 DRM_ERROR("No FB bound\n");
2856 return 0;
2857 }
2858
2859 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2860 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2861 plane_name(intel_crtc->plane),
2862 INTEL_INFO(dev)->num_pipes);
2863 return -EINVAL;
2864 }
2865
2866 mutex_lock(&dev->struct_mutex);
2867 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2868 if (ret == 0)
2869 i915_gem_track_fb(old_obj, obj,
2870 INTEL_FRONTBUFFER_PRIMARY(pipe));
2871 mutex_unlock(&dev->struct_mutex);
2872 if (ret != 0) {
2873 DRM_ERROR("pin & fence failed\n");
2874 return ret;
2875 }
2876
2877 /*
2878 * Update pipe size and adjust fitter if needed: the reason for this is
2879 * that in compute_mode_changes we check the native mode (not the pfit
2880 * mode) to see if we can flip rather than do a full mode set. In the
2881 * fastboot case, we'll flip, but if we don't update the pipesrc and
2882 * pfit state, we'll end up with a big fb scanned out into the wrong
2883 * sized surface.
2884 *
2885 * To fix this properly, we need to hoist the checks up into
2886 * compute_mode_changes (or above), check the actual pfit state and
2887 * whether the platform allows pfit disable with pipe active, and only
2888 * then update the pipesrc and pfit state, even on the flip path.
2889 */
2890 if (i915.fastboot) {
2891 const struct drm_display_mode *adjusted_mode =
2892 &intel_crtc->config.adjusted_mode;
2893
2894 I915_WRITE(PIPESRC(intel_crtc->pipe),
2895 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2896 (adjusted_mode->crtc_vdisplay - 1));
2897 if (!intel_crtc->config.pch_pfit.enabled &&
2898 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2899 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2900 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2901 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2902 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2903 }
2904 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2905 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2906 }
2907
2908 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2909
2910 if (intel_crtc->active)
2911 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2912
2913 crtc->primary->fb = fb;
2914 crtc->x = x;
2915 crtc->y = y;
2916
2917 if (old_fb) {
2918 if (intel_crtc->active && old_fb != fb)
2919 intel_wait_for_vblank(dev, intel_crtc->pipe);
2920 mutex_lock(&dev->struct_mutex);
2921 intel_unpin_fb_obj(old_obj);
2922 mutex_unlock(&dev->struct_mutex);
2923 }
2924
2925 mutex_lock(&dev->struct_mutex);
2926 intel_update_fbc(dev);
2927 mutex_unlock(&dev->struct_mutex);
2928
2929 return 0;
2930 }
2931
2932 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2933 {
2934 struct drm_device *dev = crtc->dev;
2935 struct drm_i915_private *dev_priv = dev->dev_private;
2936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2937 int pipe = intel_crtc->pipe;
2938 u32 reg, temp;
2939
2940 /* enable normal train */
2941 reg = FDI_TX_CTL(pipe);
2942 temp = I915_READ(reg);
2943 if (IS_IVYBRIDGE(dev)) {
2944 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2945 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2946 } else {
2947 temp &= ~FDI_LINK_TRAIN_NONE;
2948 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2949 }
2950 I915_WRITE(reg, temp);
2951
2952 reg = FDI_RX_CTL(pipe);
2953 temp = I915_READ(reg);
2954 if (HAS_PCH_CPT(dev)) {
2955 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2956 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2957 } else {
2958 temp &= ~FDI_LINK_TRAIN_NONE;
2959 temp |= FDI_LINK_TRAIN_NONE;
2960 }
2961 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2962
2963 /* wait one idle pattern time */
2964 POSTING_READ(reg);
2965 udelay(1000);
2966
2967 /* IVB wants error correction enabled */
2968 if (IS_IVYBRIDGE(dev))
2969 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2970 FDI_FE_ERRC_ENABLE);
2971 }
2972
2973 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2974 {
2975 return crtc->base.enabled && crtc->active &&
2976 crtc->config.has_pch_encoder;
2977 }
2978
2979 static void ivb_modeset_global_resources(struct drm_device *dev)
2980 {
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct intel_crtc *pipe_B_crtc =
2983 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2984 struct intel_crtc *pipe_C_crtc =
2985 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2986 uint32_t temp;
2987
2988 /*
2989 * When everything is off disable fdi C so that we could enable fdi B
2990 * with all lanes. Note that we don't care about enabled pipes without
2991 * an enabled pch encoder.
2992 */
2993 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2994 !pipe_has_enabled_pch(pipe_C_crtc)) {
2995 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2996 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2997
2998 temp = I915_READ(SOUTH_CHICKEN1);
2999 temp &= ~FDI_BC_BIFURCATION_SELECT;
3000 DRM_DEBUG_KMS("disabling fdi C rx\n");
3001 I915_WRITE(SOUTH_CHICKEN1, temp);
3002 }
3003 }
3004
3005 /* The FDI link training functions for ILK/Ibexpeak. */
3006 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3007 {
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int pipe = intel_crtc->pipe;
3012 u32 reg, temp, tries;
3013
3014 /* FDI needs bits from pipe first */
3015 assert_pipe_enabled(dev_priv, pipe);
3016
3017 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3018 for train result */
3019 reg = FDI_RX_IMR(pipe);
3020 temp = I915_READ(reg);
3021 temp &= ~FDI_RX_SYMBOL_LOCK;
3022 temp &= ~FDI_RX_BIT_LOCK;
3023 I915_WRITE(reg, temp);
3024 I915_READ(reg);
3025 udelay(150);
3026
3027 /* enable CPU FDI TX and PCH FDI RX */
3028 reg = FDI_TX_CTL(pipe);
3029 temp = I915_READ(reg);
3030 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3031 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3032 temp &= ~FDI_LINK_TRAIN_NONE;
3033 temp |= FDI_LINK_TRAIN_PATTERN_1;
3034 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3035
3036 reg = FDI_RX_CTL(pipe);
3037 temp = I915_READ(reg);
3038 temp &= ~FDI_LINK_TRAIN_NONE;
3039 temp |= FDI_LINK_TRAIN_PATTERN_1;
3040 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3041
3042 POSTING_READ(reg);
3043 udelay(150);
3044
3045 /* Ironlake workaround, enable clock pointer after FDI enable*/
3046 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3047 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3048 FDI_RX_PHASE_SYNC_POINTER_EN);
3049
3050 reg = FDI_RX_IIR(pipe);
3051 for (tries = 0; tries < 5; tries++) {
3052 temp = I915_READ(reg);
3053 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3054
3055 if ((temp & FDI_RX_BIT_LOCK)) {
3056 DRM_DEBUG_KMS("FDI train 1 done.\n");
3057 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3058 break;
3059 }
3060 }
3061 if (tries == 5)
3062 DRM_ERROR("FDI train 1 fail!\n");
3063
3064 /* Train 2 */
3065 reg = FDI_TX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 temp &= ~FDI_LINK_TRAIN_NONE;
3068 temp |= FDI_LINK_TRAIN_PATTERN_2;
3069 I915_WRITE(reg, temp);
3070
3071 reg = FDI_RX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 temp &= ~FDI_LINK_TRAIN_NONE;
3074 temp |= FDI_LINK_TRAIN_PATTERN_2;
3075 I915_WRITE(reg, temp);
3076
3077 POSTING_READ(reg);
3078 udelay(150);
3079
3080 reg = FDI_RX_IIR(pipe);
3081 for (tries = 0; tries < 5; tries++) {
3082 temp = I915_READ(reg);
3083 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3084
3085 if (temp & FDI_RX_SYMBOL_LOCK) {
3086 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3087 DRM_DEBUG_KMS("FDI train 2 done.\n");
3088 break;
3089 }
3090 }
3091 if (tries == 5)
3092 DRM_ERROR("FDI train 2 fail!\n");
3093
3094 DRM_DEBUG_KMS("FDI train done\n");
3095
3096 }
3097
3098 static const int snb_b_fdi_train_param[] = {
3099 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3100 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3101 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3102 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3103 };
3104
3105 /* The FDI link training functions for SNB/Cougarpoint. */
3106 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3107 {
3108 struct drm_device *dev = crtc->dev;
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3111 int pipe = intel_crtc->pipe;
3112 u32 reg, temp, i, retry;
3113
3114 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3115 for train result */
3116 reg = FDI_RX_IMR(pipe);
3117 temp = I915_READ(reg);
3118 temp &= ~FDI_RX_SYMBOL_LOCK;
3119 temp &= ~FDI_RX_BIT_LOCK;
3120 I915_WRITE(reg, temp);
3121
3122 POSTING_READ(reg);
3123 udelay(150);
3124
3125 /* enable CPU FDI TX and PCH FDI RX */
3126 reg = FDI_TX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3129 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3130 temp &= ~FDI_LINK_TRAIN_NONE;
3131 temp |= FDI_LINK_TRAIN_PATTERN_1;
3132 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3133 /* SNB-B */
3134 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3135 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3136
3137 I915_WRITE(FDI_RX_MISC(pipe),
3138 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3139
3140 reg = FDI_RX_CTL(pipe);
3141 temp = I915_READ(reg);
3142 if (HAS_PCH_CPT(dev)) {
3143 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3144 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3145 } else {
3146 temp &= ~FDI_LINK_TRAIN_NONE;
3147 temp |= FDI_LINK_TRAIN_PATTERN_1;
3148 }
3149 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3150
3151 POSTING_READ(reg);
3152 udelay(150);
3153
3154 for (i = 0; i < 4; i++) {
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3158 temp |= snb_b_fdi_train_param[i];
3159 I915_WRITE(reg, temp);
3160
3161 POSTING_READ(reg);
3162 udelay(500);
3163
3164 for (retry = 0; retry < 5; retry++) {
3165 reg = FDI_RX_IIR(pipe);
3166 temp = I915_READ(reg);
3167 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3168 if (temp & FDI_RX_BIT_LOCK) {
3169 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3170 DRM_DEBUG_KMS("FDI train 1 done.\n");
3171 break;
3172 }
3173 udelay(50);
3174 }
3175 if (retry < 5)
3176 break;
3177 }
3178 if (i == 4)
3179 DRM_ERROR("FDI train 1 fail!\n");
3180
3181 /* Train 2 */
3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~FDI_LINK_TRAIN_NONE;
3185 temp |= FDI_LINK_TRAIN_PATTERN_2;
3186 if (IS_GEN6(dev)) {
3187 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3188 /* SNB-B */
3189 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3190 }
3191 I915_WRITE(reg, temp);
3192
3193 reg = FDI_RX_CTL(pipe);
3194 temp = I915_READ(reg);
3195 if (HAS_PCH_CPT(dev)) {
3196 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3197 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3198 } else {
3199 temp &= ~FDI_LINK_TRAIN_NONE;
3200 temp |= FDI_LINK_TRAIN_PATTERN_2;
3201 }
3202 I915_WRITE(reg, temp);
3203
3204 POSTING_READ(reg);
3205 udelay(150);
3206
3207 for (i = 0; i < 4; i++) {
3208 reg = FDI_TX_CTL(pipe);
3209 temp = I915_READ(reg);
3210 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3211 temp |= snb_b_fdi_train_param[i];
3212 I915_WRITE(reg, temp);
3213
3214 POSTING_READ(reg);
3215 udelay(500);
3216
3217 for (retry = 0; retry < 5; retry++) {
3218 reg = FDI_RX_IIR(pipe);
3219 temp = I915_READ(reg);
3220 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3221 if (temp & FDI_RX_SYMBOL_LOCK) {
3222 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3223 DRM_DEBUG_KMS("FDI train 2 done.\n");
3224 break;
3225 }
3226 udelay(50);
3227 }
3228 if (retry < 5)
3229 break;
3230 }
3231 if (i == 4)
3232 DRM_ERROR("FDI train 2 fail!\n");
3233
3234 DRM_DEBUG_KMS("FDI train done.\n");
3235 }
3236
3237 /* Manual link training for Ivy Bridge A0 parts */
3238 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3239 {
3240 struct drm_device *dev = crtc->dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243 int pipe = intel_crtc->pipe;
3244 u32 reg, temp, i, j;
3245
3246 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3247 for train result */
3248 reg = FDI_RX_IMR(pipe);
3249 temp = I915_READ(reg);
3250 temp &= ~FDI_RX_SYMBOL_LOCK;
3251 temp &= ~FDI_RX_BIT_LOCK;
3252 I915_WRITE(reg, temp);
3253
3254 POSTING_READ(reg);
3255 udelay(150);
3256
3257 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3258 I915_READ(FDI_RX_IIR(pipe)));
3259
3260 /* Try each vswing and preemphasis setting twice before moving on */
3261 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3262 /* disable first in case we need to retry */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3266 temp &= ~FDI_TX_ENABLE;
3267 I915_WRITE(reg, temp);
3268
3269 reg = FDI_RX_CTL(pipe);
3270 temp = I915_READ(reg);
3271 temp &= ~FDI_LINK_TRAIN_AUTO;
3272 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3273 temp &= ~FDI_RX_ENABLE;
3274 I915_WRITE(reg, temp);
3275
3276 /* enable CPU FDI TX and PCH FDI RX */
3277 reg = FDI_TX_CTL(pipe);
3278 temp = I915_READ(reg);
3279 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3280 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3281 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3282 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3283 temp |= snb_b_fdi_train_param[j/2];
3284 temp |= FDI_COMPOSITE_SYNC;
3285 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3286
3287 I915_WRITE(FDI_RX_MISC(pipe),
3288 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3289
3290 reg = FDI_RX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3293 temp |= FDI_COMPOSITE_SYNC;
3294 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3295
3296 POSTING_READ(reg);
3297 udelay(1); /* should be 0.5us */
3298
3299 for (i = 0; i < 4; i++) {
3300 reg = FDI_RX_IIR(pipe);
3301 temp = I915_READ(reg);
3302 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3303
3304 if (temp & FDI_RX_BIT_LOCK ||
3305 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3306 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3307 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3308 i);
3309 break;
3310 }
3311 udelay(1); /* should be 0.5us */
3312 }
3313 if (i == 4) {
3314 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3315 continue;
3316 }
3317
3318 /* Train 2 */
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3322 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3323 I915_WRITE(reg, temp);
3324
3325 reg = FDI_RX_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3328 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3329 I915_WRITE(reg, temp);
3330
3331 POSTING_READ(reg);
3332 udelay(2); /* should be 1.5us */
3333
3334 for (i = 0; i < 4; i++) {
3335 reg = FDI_RX_IIR(pipe);
3336 temp = I915_READ(reg);
3337 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3338
3339 if (temp & FDI_RX_SYMBOL_LOCK ||
3340 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3341 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3342 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3343 i);
3344 goto train_done;
3345 }
3346 udelay(2); /* should be 1.5us */
3347 }
3348 if (i == 4)
3349 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3350 }
3351
3352 train_done:
3353 DRM_DEBUG_KMS("FDI train done.\n");
3354 }
3355
3356 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3357 {
3358 struct drm_device *dev = intel_crtc->base.dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 int pipe = intel_crtc->pipe;
3361 u32 reg, temp;
3362
3363
3364 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3365 reg = FDI_RX_CTL(pipe);
3366 temp = I915_READ(reg);
3367 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3368 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3369 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3370 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3371
3372 POSTING_READ(reg);
3373 udelay(200);
3374
3375 /* Switch from Rawclk to PCDclk */
3376 temp = I915_READ(reg);
3377 I915_WRITE(reg, temp | FDI_PCDCLK);
3378
3379 POSTING_READ(reg);
3380 udelay(200);
3381
3382 /* Enable CPU FDI TX PLL, always on for Ironlake */
3383 reg = FDI_TX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3386 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3387
3388 POSTING_READ(reg);
3389 udelay(100);
3390 }
3391 }
3392
3393 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3394 {
3395 struct drm_device *dev = intel_crtc->base.dev;
3396 struct drm_i915_private *dev_priv = dev->dev_private;
3397 int pipe = intel_crtc->pipe;
3398 u32 reg, temp;
3399
3400 /* Switch from PCDclk to Rawclk */
3401 reg = FDI_RX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3404
3405 /* Disable CPU FDI TX PLL */
3406 reg = FDI_TX_CTL(pipe);
3407 temp = I915_READ(reg);
3408 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3409
3410 POSTING_READ(reg);
3411 udelay(100);
3412
3413 reg = FDI_RX_CTL(pipe);
3414 temp = I915_READ(reg);
3415 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3416
3417 /* Wait for the clocks to turn off. */
3418 POSTING_READ(reg);
3419 udelay(100);
3420 }
3421
3422 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3423 {
3424 struct drm_device *dev = crtc->dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3427 int pipe = intel_crtc->pipe;
3428 u32 reg, temp;
3429
3430 /* disable CPU FDI tx and PCH FDI rx */
3431 reg = FDI_TX_CTL(pipe);
3432 temp = I915_READ(reg);
3433 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3434 POSTING_READ(reg);
3435
3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~(0x7 << 16);
3439 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3440 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
3443 udelay(100);
3444
3445 /* Ironlake workaround, disable clock pointer after downing FDI */
3446 if (HAS_PCH_IBX(dev))
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3448
3449 /* still set train pattern 1 */
3450 reg = FDI_TX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_1;
3454 I915_WRITE(reg, temp);
3455
3456 reg = FDI_RX_CTL(pipe);
3457 temp = I915_READ(reg);
3458 if (HAS_PCH_CPT(dev)) {
3459 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3460 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3461 } else {
3462 temp &= ~FDI_LINK_TRAIN_NONE;
3463 temp |= FDI_LINK_TRAIN_PATTERN_1;
3464 }
3465 /* BPC in FDI rx is consistent with that in PIPECONF */
3466 temp &= ~(0x07 << 16);
3467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468 I915_WRITE(reg, temp);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472 }
3473
3474 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3475 {
3476 struct intel_crtc *crtc;
3477
3478 /* Note that we don't need to be called with mode_config.lock here
3479 * as our list of CRTC objects is static for the lifetime of the
3480 * device and so cannot disappear as we iterate. Similarly, we can
3481 * happily treat the predicates as racy, atomic checks as userspace
3482 * cannot claim and pin a new fb without at least acquring the
3483 * struct_mutex and so serialising with us.
3484 */
3485 for_each_intel_crtc(dev, crtc) {
3486 if (atomic_read(&crtc->unpin_work_count) == 0)
3487 continue;
3488
3489 if (crtc->unpin_work)
3490 intel_wait_for_vblank(dev, crtc->pipe);
3491
3492 return true;
3493 }
3494
3495 return false;
3496 }
3497
3498 static void page_flip_completed(struct intel_crtc *intel_crtc)
3499 {
3500 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3501 struct intel_unpin_work *work = intel_crtc->unpin_work;
3502
3503 /* ensure that the unpin work is consistent wrt ->pending. */
3504 smp_rmb();
3505 intel_crtc->unpin_work = NULL;
3506
3507 if (work->event)
3508 drm_send_vblank_event(intel_crtc->base.dev,
3509 intel_crtc->pipe,
3510 work->event);
3511
3512 drm_crtc_vblank_put(&intel_crtc->base);
3513
3514 wake_up_all(&dev_priv->pending_flip_queue);
3515 queue_work(dev_priv->wq, &work->work);
3516
3517 trace_i915_flip_complete(intel_crtc->plane,
3518 work->pending_flip_obj);
3519 }
3520
3521 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3522 {
3523 struct drm_device *dev = crtc->dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525
3526 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3527 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3528 !intel_crtc_has_pending_flip(crtc),
3529 60*HZ) == 0)) {
3530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3531 unsigned long flags;
3532
3533 spin_lock_irqsave(&dev->event_lock, flags);
3534 if (intel_crtc->unpin_work) {
3535 WARN_ONCE(1, "Removing stuck page flip\n");
3536 page_flip_completed(intel_crtc);
3537 }
3538 spin_unlock_irqrestore(&dev->event_lock, flags);
3539 }
3540
3541 if (crtc->primary->fb) {
3542 mutex_lock(&dev->struct_mutex);
3543 intel_finish_fb(crtc->primary->fb);
3544 mutex_unlock(&dev->struct_mutex);
3545 }
3546 }
3547
3548 /* Program iCLKIP clock to the desired frequency */
3549 static void lpt_program_iclkip(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3554 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3555 u32 temp;
3556
3557 mutex_lock(&dev_priv->dpio_lock);
3558
3559 /* It is necessary to ungate the pixclk gate prior to programming
3560 * the divisors, and gate it back when it is done.
3561 */
3562 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3563
3564 /* Disable SSCCTL */
3565 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3566 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3567 SBI_SSCCTL_DISABLE,
3568 SBI_ICLK);
3569
3570 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3571 if (clock == 20000) {
3572 auxdiv = 1;
3573 divsel = 0x41;
3574 phaseinc = 0x20;
3575 } else {
3576 /* The iCLK virtual clock root frequency is in MHz,
3577 * but the adjusted_mode->crtc_clock in in KHz. To get the
3578 * divisors, it is necessary to divide one by another, so we
3579 * convert the virtual clock precision to KHz here for higher
3580 * precision.
3581 */
3582 u32 iclk_virtual_root_freq = 172800 * 1000;
3583 u32 iclk_pi_range = 64;
3584 u32 desired_divisor, msb_divisor_value, pi_value;
3585
3586 desired_divisor = (iclk_virtual_root_freq / clock);
3587 msb_divisor_value = desired_divisor / iclk_pi_range;
3588 pi_value = desired_divisor % iclk_pi_range;
3589
3590 auxdiv = 0;
3591 divsel = msb_divisor_value - 2;
3592 phaseinc = pi_value;
3593 }
3594
3595 /* This should not happen with any sane values */
3596 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3597 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3598 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3599 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3600
3601 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3602 clock,
3603 auxdiv,
3604 divsel,
3605 phasedir,
3606 phaseinc);
3607
3608 /* Program SSCDIVINTPHASE6 */
3609 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3610 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3611 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3612 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3613 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3614 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3615 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3616 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3617
3618 /* Program SSCAUXDIV */
3619 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3620 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3621 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3622 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3623
3624 /* Enable modulator and associated divider */
3625 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3626 temp &= ~SBI_SSCCTL_DISABLE;
3627 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3628
3629 /* Wait for initialization time */
3630 udelay(24);
3631
3632 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3633
3634 mutex_unlock(&dev_priv->dpio_lock);
3635 }
3636
3637 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3638 enum pipe pch_transcoder)
3639 {
3640 struct drm_device *dev = crtc->base.dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3643
3644 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3645 I915_READ(HTOTAL(cpu_transcoder)));
3646 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3647 I915_READ(HBLANK(cpu_transcoder)));
3648 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3649 I915_READ(HSYNC(cpu_transcoder)));
3650
3651 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3652 I915_READ(VTOTAL(cpu_transcoder)));
3653 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3654 I915_READ(VBLANK(cpu_transcoder)));
3655 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3656 I915_READ(VSYNC(cpu_transcoder)));
3657 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3658 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3659 }
3660
3661 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3662 {
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 uint32_t temp;
3665
3666 temp = I915_READ(SOUTH_CHICKEN1);
3667 if (temp & FDI_BC_BIFURCATION_SELECT)
3668 return;
3669
3670 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3671 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3672
3673 temp |= FDI_BC_BIFURCATION_SELECT;
3674 DRM_DEBUG_KMS("enabling fdi C rx\n");
3675 I915_WRITE(SOUTH_CHICKEN1, temp);
3676 POSTING_READ(SOUTH_CHICKEN1);
3677 }
3678
3679 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3680 {
3681 struct drm_device *dev = intel_crtc->base.dev;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683
3684 switch (intel_crtc->pipe) {
3685 case PIPE_A:
3686 break;
3687 case PIPE_B:
3688 if (intel_crtc->config.fdi_lanes > 2)
3689 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3690 else
3691 cpt_enable_fdi_bc_bifurcation(dev);
3692
3693 break;
3694 case PIPE_C:
3695 cpt_enable_fdi_bc_bifurcation(dev);
3696
3697 break;
3698 default:
3699 BUG();
3700 }
3701 }
3702
3703 /*
3704 * Enable PCH resources required for PCH ports:
3705 * - PCH PLLs
3706 * - FDI training & RX/TX
3707 * - update transcoder timings
3708 * - DP transcoding bits
3709 * - transcoder
3710 */
3711 static void ironlake_pch_enable(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 int pipe = intel_crtc->pipe;
3717 u32 reg, temp;
3718
3719 assert_pch_transcoder_disabled(dev_priv, pipe);
3720
3721 if (IS_IVYBRIDGE(dev))
3722 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3723
3724 /* Write the TU size bits before fdi link training, so that error
3725 * detection works. */
3726 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3727 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3728
3729 /* For PCH output, training FDI link */
3730 dev_priv->display.fdi_link_train(crtc);
3731
3732 /* We need to program the right clock selection before writing the pixel
3733 * mutliplier into the DPLL. */
3734 if (HAS_PCH_CPT(dev)) {
3735 u32 sel;
3736
3737 temp = I915_READ(PCH_DPLL_SEL);
3738 temp |= TRANS_DPLL_ENABLE(pipe);
3739 sel = TRANS_DPLLB_SEL(pipe);
3740 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3741 temp |= sel;
3742 else
3743 temp &= ~sel;
3744 I915_WRITE(PCH_DPLL_SEL, temp);
3745 }
3746
3747 /* XXX: pch pll's can be enabled any time before we enable the PCH
3748 * transcoder, and we actually should do this to not upset any PCH
3749 * transcoder that already use the clock when we share it.
3750 *
3751 * Note that enable_shared_dpll tries to do the right thing, but
3752 * get_shared_dpll unconditionally resets the pll - we need that to have
3753 * the right LVDS enable sequence. */
3754 intel_enable_shared_dpll(intel_crtc);
3755
3756 /* set transcoder timing, panel must allow it */
3757 assert_panel_unlocked(dev_priv, pipe);
3758 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3759
3760 intel_fdi_normal_train(crtc);
3761
3762 /* For PCH DP, enable TRANS_DP_CTL */
3763 if (HAS_PCH_CPT(dev) &&
3764 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3765 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3766 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3767 reg = TRANS_DP_CTL(pipe);
3768 temp = I915_READ(reg);
3769 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3770 TRANS_DP_SYNC_MASK |
3771 TRANS_DP_BPC_MASK);
3772 temp |= (TRANS_DP_OUTPUT_ENABLE |
3773 TRANS_DP_ENH_FRAMING);
3774 temp |= bpc << 9; /* same format but at 11:9 */
3775
3776 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3777 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3778 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3779 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3780
3781 switch (intel_trans_dp_port_sel(crtc)) {
3782 case PCH_DP_B:
3783 temp |= TRANS_DP_PORT_SEL_B;
3784 break;
3785 case PCH_DP_C:
3786 temp |= TRANS_DP_PORT_SEL_C;
3787 break;
3788 case PCH_DP_D:
3789 temp |= TRANS_DP_PORT_SEL_D;
3790 break;
3791 default:
3792 BUG();
3793 }
3794
3795 I915_WRITE(reg, temp);
3796 }
3797
3798 ironlake_enable_pch_transcoder(dev_priv, pipe);
3799 }
3800
3801 static void lpt_pch_enable(struct drm_crtc *crtc)
3802 {
3803 struct drm_device *dev = crtc->dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3806 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3807
3808 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3809
3810 lpt_program_iclkip(crtc);
3811
3812 /* Set transcoder timing. */
3813 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3814
3815 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3816 }
3817
3818 void intel_put_shared_dpll(struct intel_crtc *crtc)
3819 {
3820 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3821
3822 if (pll == NULL)
3823 return;
3824
3825 if (pll->refcount == 0) {
3826 WARN(1, "bad %s refcount\n", pll->name);
3827 return;
3828 }
3829
3830 if (--pll->refcount == 0) {
3831 WARN_ON(pll->on);
3832 WARN_ON(pll->active);
3833 }
3834
3835 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3836 }
3837
3838 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3839 {
3840 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3841 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3842 enum intel_dpll_id i;
3843
3844 if (pll) {
3845 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3846 crtc->base.base.id, pll->name);
3847 intel_put_shared_dpll(crtc);
3848 }
3849
3850 if (HAS_PCH_IBX(dev_priv->dev)) {
3851 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3852 i = (enum intel_dpll_id) crtc->pipe;
3853 pll = &dev_priv->shared_dplls[i];
3854
3855 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3856 crtc->base.base.id, pll->name);
3857
3858 WARN_ON(pll->refcount);
3859
3860 goto found;
3861 }
3862
3863 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3864 pll = &dev_priv->shared_dplls[i];
3865
3866 /* Only want to check enabled timings first */
3867 if (pll->refcount == 0)
3868 continue;
3869
3870 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3871 sizeof(pll->hw_state)) == 0) {
3872 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3873 crtc->base.base.id,
3874 pll->name, pll->refcount, pll->active);
3875
3876 goto found;
3877 }
3878 }
3879
3880 /* Ok no matching timings, maybe there's a free one? */
3881 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3882 pll = &dev_priv->shared_dplls[i];
3883 if (pll->refcount == 0) {
3884 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3885 crtc->base.base.id, pll->name);
3886 goto found;
3887 }
3888 }
3889
3890 return NULL;
3891
3892 found:
3893 if (pll->refcount == 0)
3894 pll->hw_state = crtc->config.dpll_hw_state;
3895
3896 crtc->config.shared_dpll = i;
3897 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3898 pipe_name(crtc->pipe));
3899
3900 pll->refcount++;
3901
3902 return pll;
3903 }
3904
3905 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3906 {
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 int dslreg = PIPEDSL(pipe);
3909 u32 temp;
3910
3911 temp = I915_READ(dslreg);
3912 udelay(500);
3913 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3914 if (wait_for(I915_READ(dslreg) != temp, 5))
3915 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3916 }
3917 }
3918
3919 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3920 {
3921 struct drm_device *dev = crtc->base.dev;
3922 struct drm_i915_private *dev_priv = dev->dev_private;
3923 int pipe = crtc->pipe;
3924
3925 if (crtc->config.pch_pfit.enabled) {
3926 /* Force use of hard-coded filter coefficients
3927 * as some pre-programmed values are broken,
3928 * e.g. x201.
3929 */
3930 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3931 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3932 PF_PIPE_SEL_IVB(pipe));
3933 else
3934 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3935 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3936 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3937 }
3938 }
3939
3940 static void intel_enable_planes(struct drm_crtc *crtc)
3941 {
3942 struct drm_device *dev = crtc->dev;
3943 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3944 struct drm_plane *plane;
3945 struct intel_plane *intel_plane;
3946
3947 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3948 intel_plane = to_intel_plane(plane);
3949 if (intel_plane->pipe == pipe)
3950 intel_plane_restore(&intel_plane->base);
3951 }
3952 }
3953
3954 static void intel_disable_planes(struct drm_crtc *crtc)
3955 {
3956 struct drm_device *dev = crtc->dev;
3957 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3958 struct drm_plane *plane;
3959 struct intel_plane *intel_plane;
3960
3961 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3962 intel_plane = to_intel_plane(plane);
3963 if (intel_plane->pipe == pipe)
3964 intel_plane_disable(&intel_plane->base);
3965 }
3966 }
3967
3968 void hsw_enable_ips(struct intel_crtc *crtc)
3969 {
3970 struct drm_device *dev = crtc->base.dev;
3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972
3973 if (!crtc->config.ips_enabled)
3974 return;
3975
3976 /* We can only enable IPS after we enable a plane and wait for a vblank */
3977 intel_wait_for_vblank(dev, crtc->pipe);
3978
3979 assert_plane_enabled(dev_priv, crtc->plane);
3980 if (IS_BROADWELL(dev)) {
3981 mutex_lock(&dev_priv->rps.hw_lock);
3982 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3983 mutex_unlock(&dev_priv->rps.hw_lock);
3984 /* Quoting Art Runyan: "its not safe to expect any particular
3985 * value in IPS_CTL bit 31 after enabling IPS through the
3986 * mailbox." Moreover, the mailbox may return a bogus state,
3987 * so we need to just enable it and continue on.
3988 */
3989 } else {
3990 I915_WRITE(IPS_CTL, IPS_ENABLE);
3991 /* The bit only becomes 1 in the next vblank, so this wait here
3992 * is essentially intel_wait_for_vblank. If we don't have this
3993 * and don't wait for vblanks until the end of crtc_enable, then
3994 * the HW state readout code will complain that the expected
3995 * IPS_CTL value is not the one we read. */
3996 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3997 DRM_ERROR("Timed out waiting for IPS enable\n");
3998 }
3999 }
4000
4001 void hsw_disable_ips(struct intel_crtc *crtc)
4002 {
4003 struct drm_device *dev = crtc->base.dev;
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005
4006 if (!crtc->config.ips_enabled)
4007 return;
4008
4009 assert_plane_enabled(dev_priv, crtc->plane);
4010 if (IS_BROADWELL(dev)) {
4011 mutex_lock(&dev_priv->rps.hw_lock);
4012 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4013 mutex_unlock(&dev_priv->rps.hw_lock);
4014 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4015 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4016 DRM_ERROR("Timed out waiting for IPS disable\n");
4017 } else {
4018 I915_WRITE(IPS_CTL, 0);
4019 POSTING_READ(IPS_CTL);
4020 }
4021
4022 /* We need to wait for a vblank before we can disable the plane. */
4023 intel_wait_for_vblank(dev, crtc->pipe);
4024 }
4025
4026 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4027 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4028 {
4029 struct drm_device *dev = crtc->dev;
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4032 enum pipe pipe = intel_crtc->pipe;
4033 int palreg = PALETTE(pipe);
4034 int i;
4035 bool reenable_ips = false;
4036
4037 /* The clocks have to be on to load the palette. */
4038 if (!crtc->enabled || !intel_crtc->active)
4039 return;
4040
4041 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4043 assert_dsi_pll_enabled(dev_priv);
4044 else
4045 assert_pll_enabled(dev_priv, pipe);
4046 }
4047
4048 /* use legacy palette for Ironlake */
4049 if (!HAS_GMCH_DISPLAY(dev))
4050 palreg = LGC_PALETTE(pipe);
4051
4052 /* Workaround : Do not read or write the pipe palette/gamma data while
4053 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4054 */
4055 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4056 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4057 GAMMA_MODE_MODE_SPLIT)) {
4058 hsw_disable_ips(intel_crtc);
4059 reenable_ips = true;
4060 }
4061
4062 for (i = 0; i < 256; i++) {
4063 I915_WRITE(palreg + 4 * i,
4064 (intel_crtc->lut_r[i] << 16) |
4065 (intel_crtc->lut_g[i] << 8) |
4066 intel_crtc->lut_b[i]);
4067 }
4068
4069 if (reenable_ips)
4070 hsw_enable_ips(intel_crtc);
4071 }
4072
4073 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4074 {
4075 if (!enable && intel_crtc->overlay) {
4076 struct drm_device *dev = intel_crtc->base.dev;
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078
4079 mutex_lock(&dev->struct_mutex);
4080 dev_priv->mm.interruptible = false;
4081 (void) intel_overlay_switch_off(intel_crtc->overlay);
4082 dev_priv->mm.interruptible = true;
4083 mutex_unlock(&dev->struct_mutex);
4084 }
4085
4086 /* Let userspace switch the overlay on again. In most cases userspace
4087 * has to recompute where to put it anyway.
4088 */
4089 }
4090
4091 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4092 {
4093 struct drm_device *dev = crtc->dev;
4094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4095 int pipe = intel_crtc->pipe;
4096
4097 assert_vblank_disabled(crtc);
4098
4099 drm_vblank_on(dev, pipe);
4100
4101 intel_enable_primary_hw_plane(crtc->primary, crtc);
4102 intel_enable_planes(crtc);
4103 intel_crtc_update_cursor(crtc, true);
4104 intel_crtc_dpms_overlay(intel_crtc, true);
4105
4106 hsw_enable_ips(intel_crtc);
4107
4108 mutex_lock(&dev->struct_mutex);
4109 intel_update_fbc(dev);
4110 mutex_unlock(&dev->struct_mutex);
4111
4112 /*
4113 * FIXME: Once we grow proper nuclear flip support out of this we need
4114 * to compute the mask of flip planes precisely. For the time being
4115 * consider this a flip from a NULL plane.
4116 */
4117 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4118 }
4119
4120 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4121 {
4122 struct drm_device *dev = crtc->dev;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4125 int pipe = intel_crtc->pipe;
4126 int plane = intel_crtc->plane;
4127
4128 intel_crtc_wait_for_pending_flips(crtc);
4129
4130 if (dev_priv->fbc.plane == plane)
4131 intel_disable_fbc(dev);
4132
4133 hsw_disable_ips(intel_crtc);
4134
4135 intel_crtc_dpms_overlay(intel_crtc, false);
4136 intel_crtc_update_cursor(crtc, false);
4137 intel_disable_planes(crtc);
4138 intel_disable_primary_hw_plane(crtc->primary, crtc);
4139
4140 /*
4141 * FIXME: Once we grow proper nuclear flip support out of this we need
4142 * to compute the mask of flip planes precisely. For the time being
4143 * consider this a flip to a NULL plane.
4144 */
4145 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4146
4147 drm_vblank_off(dev, pipe);
4148
4149 assert_vblank_disabled(crtc);
4150 }
4151
4152 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4153 {
4154 struct drm_device *dev = crtc->dev;
4155 struct drm_i915_private *dev_priv = dev->dev_private;
4156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4157 struct intel_encoder *encoder;
4158 int pipe = intel_crtc->pipe;
4159
4160 WARN_ON(!crtc->enabled);
4161
4162 if (intel_crtc->active)
4163 return;
4164
4165 if (intel_crtc->config.has_pch_encoder)
4166 intel_prepare_shared_dpll(intel_crtc);
4167
4168 if (intel_crtc->config.has_dp_encoder)
4169 intel_dp_set_m_n(intel_crtc);
4170
4171 intel_set_pipe_timings(intel_crtc);
4172
4173 if (intel_crtc->config.has_pch_encoder) {
4174 intel_cpu_transcoder_set_m_n(intel_crtc,
4175 &intel_crtc->config.fdi_m_n, NULL);
4176 }
4177
4178 ironlake_set_pipeconf(crtc);
4179
4180 intel_crtc->active = true;
4181
4182 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4183 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4184
4185 for_each_encoder_on_crtc(dev, crtc, encoder)
4186 if (encoder->pre_enable)
4187 encoder->pre_enable(encoder);
4188
4189 if (intel_crtc->config.has_pch_encoder) {
4190 /* Note: FDI PLL enabling _must_ be done before we enable the
4191 * cpu pipes, hence this is separate from all the other fdi/pch
4192 * enabling. */
4193 ironlake_fdi_pll_enable(intel_crtc);
4194 } else {
4195 assert_fdi_tx_disabled(dev_priv, pipe);
4196 assert_fdi_rx_disabled(dev_priv, pipe);
4197 }
4198
4199 ironlake_pfit_enable(intel_crtc);
4200
4201 /*
4202 * On ILK+ LUT must be loaded before the pipe is running but with
4203 * clocks enabled
4204 */
4205 intel_crtc_load_lut(crtc);
4206
4207 intel_update_watermarks(crtc);
4208 intel_enable_pipe(intel_crtc);
4209
4210 if (intel_crtc->config.has_pch_encoder)
4211 ironlake_pch_enable(crtc);
4212
4213 for_each_encoder_on_crtc(dev, crtc, encoder)
4214 encoder->enable(encoder);
4215
4216 if (HAS_PCH_CPT(dev))
4217 cpt_verify_modeset(dev, intel_crtc->pipe);
4218
4219 intel_crtc_enable_planes(crtc);
4220 }
4221
4222 /* IPS only exists on ULT machines and is tied to pipe A. */
4223 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4224 {
4225 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4226 }
4227
4228 /*
4229 * This implements the workaround described in the "notes" section of the mode
4230 * set sequence documentation. When going from no pipes or single pipe to
4231 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4232 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4233 */
4234 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4235 {
4236 struct drm_device *dev = crtc->base.dev;
4237 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4238
4239 /* We want to get the other_active_crtc only if there's only 1 other
4240 * active crtc. */
4241 for_each_intel_crtc(dev, crtc_it) {
4242 if (!crtc_it->active || crtc_it == crtc)
4243 continue;
4244
4245 if (other_active_crtc)
4246 return;
4247
4248 other_active_crtc = crtc_it;
4249 }
4250 if (!other_active_crtc)
4251 return;
4252
4253 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4254 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4255 }
4256
4257 static void haswell_crtc_enable(struct drm_crtc *crtc)
4258 {
4259 struct drm_device *dev = crtc->dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4262 struct intel_encoder *encoder;
4263 int pipe = intel_crtc->pipe;
4264
4265 WARN_ON(!crtc->enabled);
4266
4267 if (intel_crtc->active)
4268 return;
4269
4270 if (intel_crtc_to_shared_dpll(intel_crtc))
4271 intel_enable_shared_dpll(intel_crtc);
4272
4273 if (intel_crtc->config.has_dp_encoder)
4274 intel_dp_set_m_n(intel_crtc);
4275
4276 intel_set_pipe_timings(intel_crtc);
4277
4278 if (intel_crtc->config.has_pch_encoder) {
4279 intel_cpu_transcoder_set_m_n(intel_crtc,
4280 &intel_crtc->config.fdi_m_n, NULL);
4281 }
4282
4283 haswell_set_pipeconf(crtc);
4284
4285 intel_set_pipe_csc(crtc);
4286
4287 intel_crtc->active = true;
4288
4289 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4290 for_each_encoder_on_crtc(dev, crtc, encoder)
4291 if (encoder->pre_enable)
4292 encoder->pre_enable(encoder);
4293
4294 if (intel_crtc->config.has_pch_encoder) {
4295 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4296 dev_priv->display.fdi_link_train(crtc);
4297 }
4298
4299 intel_ddi_enable_pipe_clock(intel_crtc);
4300
4301 ironlake_pfit_enable(intel_crtc);
4302
4303 /*
4304 * On ILK+ LUT must be loaded before the pipe is running but with
4305 * clocks enabled
4306 */
4307 intel_crtc_load_lut(crtc);
4308
4309 intel_ddi_set_pipe_settings(crtc);
4310 intel_ddi_enable_transcoder_func(crtc);
4311
4312 intel_update_watermarks(crtc);
4313 intel_enable_pipe(intel_crtc);
4314
4315 if (intel_crtc->config.has_pch_encoder)
4316 lpt_pch_enable(crtc);
4317
4318 if (intel_crtc->config.dp_encoder_is_mst)
4319 intel_ddi_set_vc_payload_alloc(crtc, true);
4320
4321 for_each_encoder_on_crtc(dev, crtc, encoder) {
4322 encoder->enable(encoder);
4323 intel_opregion_notify_encoder(encoder, true);
4324 }
4325
4326 /* If we change the relative order between pipe/planes enabling, we need
4327 * to change the workaround. */
4328 haswell_mode_set_planes_workaround(intel_crtc);
4329 intel_crtc_enable_planes(crtc);
4330 }
4331
4332 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4333 {
4334 struct drm_device *dev = crtc->base.dev;
4335 struct drm_i915_private *dev_priv = dev->dev_private;
4336 int pipe = crtc->pipe;
4337
4338 /* To avoid upsetting the power well on haswell only disable the pfit if
4339 * it's in use. The hw state code will make sure we get this right. */
4340 if (crtc->config.pch_pfit.enabled) {
4341 I915_WRITE(PF_CTL(pipe), 0);
4342 I915_WRITE(PF_WIN_POS(pipe), 0);
4343 I915_WRITE(PF_WIN_SZ(pipe), 0);
4344 }
4345 }
4346
4347 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4348 {
4349 struct drm_device *dev = crtc->dev;
4350 struct drm_i915_private *dev_priv = dev->dev_private;
4351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4352 struct intel_encoder *encoder;
4353 int pipe = intel_crtc->pipe;
4354 u32 reg, temp;
4355
4356 if (!intel_crtc->active)
4357 return;
4358
4359 intel_crtc_disable_planes(crtc);
4360
4361 for_each_encoder_on_crtc(dev, crtc, encoder)
4362 encoder->disable(encoder);
4363
4364 if (intel_crtc->config.has_pch_encoder)
4365 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4366
4367 intel_disable_pipe(intel_crtc);
4368
4369 ironlake_pfit_disable(intel_crtc);
4370
4371 for_each_encoder_on_crtc(dev, crtc, encoder)
4372 if (encoder->post_disable)
4373 encoder->post_disable(encoder);
4374
4375 if (intel_crtc->config.has_pch_encoder) {
4376 ironlake_fdi_disable(crtc);
4377
4378 ironlake_disable_pch_transcoder(dev_priv, pipe);
4379 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4380
4381 if (HAS_PCH_CPT(dev)) {
4382 /* disable TRANS_DP_CTL */
4383 reg = TRANS_DP_CTL(pipe);
4384 temp = I915_READ(reg);
4385 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4386 TRANS_DP_PORT_SEL_MASK);
4387 temp |= TRANS_DP_PORT_SEL_NONE;
4388 I915_WRITE(reg, temp);
4389
4390 /* disable DPLL_SEL */
4391 temp = I915_READ(PCH_DPLL_SEL);
4392 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4393 I915_WRITE(PCH_DPLL_SEL, temp);
4394 }
4395
4396 /* disable PCH DPLL */
4397 intel_disable_shared_dpll(intel_crtc);
4398
4399 ironlake_fdi_pll_disable(intel_crtc);
4400 }
4401
4402 intel_crtc->active = false;
4403 intel_update_watermarks(crtc);
4404
4405 mutex_lock(&dev->struct_mutex);
4406 intel_update_fbc(dev);
4407 mutex_unlock(&dev->struct_mutex);
4408 }
4409
4410 static void haswell_crtc_disable(struct drm_crtc *crtc)
4411 {
4412 struct drm_device *dev = crtc->dev;
4413 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4415 struct intel_encoder *encoder;
4416 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4417
4418 if (!intel_crtc->active)
4419 return;
4420
4421 intel_crtc_disable_planes(crtc);
4422
4423 for_each_encoder_on_crtc(dev, crtc, encoder) {
4424 intel_opregion_notify_encoder(encoder, false);
4425 encoder->disable(encoder);
4426 }
4427
4428 if (intel_crtc->config.has_pch_encoder)
4429 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4430 intel_disable_pipe(intel_crtc);
4431
4432 if (intel_crtc->config.dp_encoder_is_mst)
4433 intel_ddi_set_vc_payload_alloc(crtc, false);
4434
4435 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4436
4437 ironlake_pfit_disable(intel_crtc);
4438
4439 intel_ddi_disable_pipe_clock(intel_crtc);
4440
4441 if (intel_crtc->config.has_pch_encoder) {
4442 lpt_disable_pch_transcoder(dev_priv);
4443 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4444 intel_ddi_fdi_disable(crtc);
4445 }
4446
4447 for_each_encoder_on_crtc(dev, crtc, encoder)
4448 if (encoder->post_disable)
4449 encoder->post_disable(encoder);
4450
4451 intel_crtc->active = false;
4452 intel_update_watermarks(crtc);
4453
4454 mutex_lock(&dev->struct_mutex);
4455 intel_update_fbc(dev);
4456 mutex_unlock(&dev->struct_mutex);
4457
4458 if (intel_crtc_to_shared_dpll(intel_crtc))
4459 intel_disable_shared_dpll(intel_crtc);
4460 }
4461
4462 static void ironlake_crtc_off(struct drm_crtc *crtc)
4463 {
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 intel_put_shared_dpll(intel_crtc);
4466 }
4467
4468
4469 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4470 {
4471 struct drm_device *dev = crtc->base.dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 struct intel_crtc_config *pipe_config = &crtc->config;
4474
4475 if (!crtc->config.gmch_pfit.control)
4476 return;
4477
4478 /*
4479 * The panel fitter should only be adjusted whilst the pipe is disabled,
4480 * according to register description and PRM.
4481 */
4482 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4483 assert_pipe_disabled(dev_priv, crtc->pipe);
4484
4485 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4486 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4487
4488 /* Border color in case we don't scale up to the full screen. Black by
4489 * default, change to something else for debugging. */
4490 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4491 }
4492
4493 static enum intel_display_power_domain port_to_power_domain(enum port port)
4494 {
4495 switch (port) {
4496 case PORT_A:
4497 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4498 case PORT_B:
4499 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4500 case PORT_C:
4501 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4502 case PORT_D:
4503 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4504 default:
4505 WARN_ON_ONCE(1);
4506 return POWER_DOMAIN_PORT_OTHER;
4507 }
4508 }
4509
4510 #define for_each_power_domain(domain, mask) \
4511 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4512 if ((1 << (domain)) & (mask))
4513
4514 enum intel_display_power_domain
4515 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4516 {
4517 struct drm_device *dev = intel_encoder->base.dev;
4518 struct intel_digital_port *intel_dig_port;
4519
4520 switch (intel_encoder->type) {
4521 case INTEL_OUTPUT_UNKNOWN:
4522 /* Only DDI platforms should ever use this output type */
4523 WARN_ON_ONCE(!HAS_DDI(dev));
4524 case INTEL_OUTPUT_DISPLAYPORT:
4525 case INTEL_OUTPUT_HDMI:
4526 case INTEL_OUTPUT_EDP:
4527 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4528 return port_to_power_domain(intel_dig_port->port);
4529 case INTEL_OUTPUT_DP_MST:
4530 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4531 return port_to_power_domain(intel_dig_port->port);
4532 case INTEL_OUTPUT_ANALOG:
4533 return POWER_DOMAIN_PORT_CRT;
4534 case INTEL_OUTPUT_DSI:
4535 return POWER_DOMAIN_PORT_DSI;
4536 default:
4537 return POWER_DOMAIN_PORT_OTHER;
4538 }
4539 }
4540
4541 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4542 {
4543 struct drm_device *dev = crtc->dev;
4544 struct intel_encoder *intel_encoder;
4545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4546 enum pipe pipe = intel_crtc->pipe;
4547 unsigned long mask;
4548 enum transcoder transcoder;
4549
4550 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4551
4552 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4553 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4554 if (intel_crtc->config.pch_pfit.enabled ||
4555 intel_crtc->config.pch_pfit.force_thru)
4556 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4557
4558 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4559 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4560
4561 return mask;
4562 }
4563
4564 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4565 bool enable)
4566 {
4567 if (dev_priv->power_domains.init_power_on == enable)
4568 return;
4569
4570 if (enable)
4571 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4572 else
4573 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4574
4575 dev_priv->power_domains.init_power_on = enable;
4576 }
4577
4578 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4579 {
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4582 struct intel_crtc *crtc;
4583
4584 /*
4585 * First get all needed power domains, then put all unneeded, to avoid
4586 * any unnecessary toggling of the power wells.
4587 */
4588 for_each_intel_crtc(dev, crtc) {
4589 enum intel_display_power_domain domain;
4590
4591 if (!crtc->base.enabled)
4592 continue;
4593
4594 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4595
4596 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4597 intel_display_power_get(dev_priv, domain);
4598 }
4599
4600 for_each_intel_crtc(dev, crtc) {
4601 enum intel_display_power_domain domain;
4602
4603 for_each_power_domain(domain, crtc->enabled_power_domains)
4604 intel_display_power_put(dev_priv, domain);
4605
4606 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4607 }
4608
4609 intel_display_set_init_power(dev_priv, false);
4610 }
4611
4612 /* returns HPLL frequency in kHz */
4613 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4614 {
4615 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4616
4617 /* Obtain SKU information */
4618 mutex_lock(&dev_priv->dpio_lock);
4619 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4620 CCK_FUSE_HPLL_FREQ_MASK;
4621 mutex_unlock(&dev_priv->dpio_lock);
4622
4623 return vco_freq[hpll_freq] * 1000;
4624 }
4625
4626 static void vlv_update_cdclk(struct drm_device *dev)
4627 {
4628 struct drm_i915_private *dev_priv = dev->dev_private;
4629
4630 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4631 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4632 dev_priv->vlv_cdclk_freq);
4633
4634 /*
4635 * Program the gmbus_freq based on the cdclk frequency.
4636 * BSpec erroneously claims we should aim for 4MHz, but
4637 * in fact 1MHz is the correct frequency.
4638 */
4639 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4640 }
4641
4642 /* Adjust CDclk dividers to allow high res or save power if possible */
4643 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4644 {
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 u32 val, cmd;
4647
4648 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4649
4650 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4651 cmd = 2;
4652 else if (cdclk == 266667)
4653 cmd = 1;
4654 else
4655 cmd = 0;
4656
4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4659 val &= ~DSPFREQGUAR_MASK;
4660 val |= (cmd << DSPFREQGUAR_SHIFT);
4661 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4662 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4663 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4664 50)) {
4665 DRM_ERROR("timed out waiting for CDclk change\n");
4666 }
4667 mutex_unlock(&dev_priv->rps.hw_lock);
4668
4669 if (cdclk == 400000) {
4670 u32 divider, vco;
4671
4672 vco = valleyview_get_vco(dev_priv);
4673 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4674
4675 mutex_lock(&dev_priv->dpio_lock);
4676 /* adjust cdclk divider */
4677 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4678 val &= ~DISPLAY_FREQUENCY_VALUES;
4679 val |= divider;
4680 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4681
4682 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4683 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4684 50))
4685 DRM_ERROR("timed out waiting for CDclk change\n");
4686 mutex_unlock(&dev_priv->dpio_lock);
4687 }
4688
4689 mutex_lock(&dev_priv->dpio_lock);
4690 /* adjust self-refresh exit latency value */
4691 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4692 val &= ~0x7f;
4693
4694 /*
4695 * For high bandwidth configs, we set a higher latency in the bunit
4696 * so that the core display fetch happens in time to avoid underruns.
4697 */
4698 if (cdclk == 400000)
4699 val |= 4500 / 250; /* 4.5 usec */
4700 else
4701 val |= 3000 / 250; /* 3.0 usec */
4702 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4703 mutex_unlock(&dev_priv->dpio_lock);
4704
4705 vlv_update_cdclk(dev);
4706 }
4707
4708 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4709 {
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 u32 val, cmd;
4712
4713 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4714
4715 switch (cdclk) {
4716 case 400000:
4717 cmd = 3;
4718 break;
4719 case 333333:
4720 case 320000:
4721 cmd = 2;
4722 break;
4723 case 266667:
4724 cmd = 1;
4725 break;
4726 case 200000:
4727 cmd = 0;
4728 break;
4729 default:
4730 WARN_ON(1);
4731 return;
4732 }
4733
4734 mutex_lock(&dev_priv->rps.hw_lock);
4735 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4736 val &= ~DSPFREQGUAR_MASK_CHV;
4737 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4738 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4739 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4740 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4741 50)) {
4742 DRM_ERROR("timed out waiting for CDclk change\n");
4743 }
4744 mutex_unlock(&dev_priv->rps.hw_lock);
4745
4746 vlv_update_cdclk(dev);
4747 }
4748
4749 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4750 int max_pixclk)
4751 {
4752 int vco = valleyview_get_vco(dev_priv);
4753 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4754
4755 /* FIXME: Punit isn't quite ready yet */
4756 if (IS_CHERRYVIEW(dev_priv->dev))
4757 return 400000;
4758
4759 /*
4760 * Really only a few cases to deal with, as only 4 CDclks are supported:
4761 * 200MHz
4762 * 267MHz
4763 * 320/333MHz (depends on HPLL freq)
4764 * 400MHz
4765 * So we check to see whether we're above 90% of the lower bin and
4766 * adjust if needed.
4767 *
4768 * We seem to get an unstable or solid color picture at 200MHz.
4769 * Not sure what's wrong. For now use 200MHz only when all pipes
4770 * are off.
4771 */
4772 if (max_pixclk > freq_320*9/10)
4773 return 400000;
4774 else if (max_pixclk > 266667*9/10)
4775 return freq_320;
4776 else if (max_pixclk > 0)
4777 return 266667;
4778 else
4779 return 200000;
4780 }
4781
4782 /* compute the max pixel clock for new configuration */
4783 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4784 {
4785 struct drm_device *dev = dev_priv->dev;
4786 struct intel_crtc *intel_crtc;
4787 int max_pixclk = 0;
4788
4789 for_each_intel_crtc(dev, intel_crtc) {
4790 if (intel_crtc->new_enabled)
4791 max_pixclk = max(max_pixclk,
4792 intel_crtc->new_config->adjusted_mode.crtc_clock);
4793 }
4794
4795 return max_pixclk;
4796 }
4797
4798 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4799 unsigned *prepare_pipes)
4800 {
4801 struct drm_i915_private *dev_priv = dev->dev_private;
4802 struct intel_crtc *intel_crtc;
4803 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4804
4805 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4806 dev_priv->vlv_cdclk_freq)
4807 return;
4808
4809 /* disable/enable all currently active pipes while we change cdclk */
4810 for_each_intel_crtc(dev, intel_crtc)
4811 if (intel_crtc->base.enabled)
4812 *prepare_pipes |= (1 << intel_crtc->pipe);
4813 }
4814
4815 static void valleyview_modeset_global_resources(struct drm_device *dev)
4816 {
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4819 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4820
4821 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4822 if (IS_CHERRYVIEW(dev))
4823 cherryview_set_cdclk(dev, req_cdclk);
4824 else
4825 valleyview_set_cdclk(dev, req_cdclk);
4826 }
4827
4828 modeset_update_crtc_power_domains(dev);
4829 }
4830
4831 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4832 {
4833 struct drm_device *dev = crtc->dev;
4834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835 struct intel_encoder *encoder;
4836 int pipe = intel_crtc->pipe;
4837 bool is_dsi;
4838
4839 WARN_ON(!crtc->enabled);
4840
4841 if (intel_crtc->active)
4842 return;
4843
4844 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4845
4846 if (!is_dsi) {
4847 if (IS_CHERRYVIEW(dev))
4848 chv_prepare_pll(intel_crtc);
4849 else
4850 vlv_prepare_pll(intel_crtc);
4851 }
4852
4853 if (intel_crtc->config.has_dp_encoder)
4854 intel_dp_set_m_n(intel_crtc);
4855
4856 intel_set_pipe_timings(intel_crtc);
4857
4858 i9xx_set_pipeconf(intel_crtc);
4859
4860 intel_crtc->active = true;
4861
4862 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4863
4864 for_each_encoder_on_crtc(dev, crtc, encoder)
4865 if (encoder->pre_pll_enable)
4866 encoder->pre_pll_enable(encoder);
4867
4868 if (!is_dsi) {
4869 if (IS_CHERRYVIEW(dev))
4870 chv_enable_pll(intel_crtc);
4871 else
4872 vlv_enable_pll(intel_crtc);
4873 }
4874
4875 for_each_encoder_on_crtc(dev, crtc, encoder)
4876 if (encoder->pre_enable)
4877 encoder->pre_enable(encoder);
4878
4879 i9xx_pfit_enable(intel_crtc);
4880
4881 intel_crtc_load_lut(crtc);
4882
4883 intel_update_watermarks(crtc);
4884 intel_enable_pipe(intel_crtc);
4885
4886 for_each_encoder_on_crtc(dev, crtc, encoder)
4887 encoder->enable(encoder);
4888
4889 intel_crtc_enable_planes(crtc);
4890
4891 /* Underruns don't raise interrupts, so check manually. */
4892 i9xx_check_fifo_underruns(dev);
4893 }
4894
4895 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4896 {
4897 struct drm_device *dev = crtc->base.dev;
4898 struct drm_i915_private *dev_priv = dev->dev_private;
4899
4900 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4901 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4902 }
4903
4904 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4905 {
4906 struct drm_device *dev = crtc->dev;
4907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4908 struct intel_encoder *encoder;
4909 int pipe = intel_crtc->pipe;
4910
4911 WARN_ON(!crtc->enabled);
4912
4913 if (intel_crtc->active)
4914 return;
4915
4916 i9xx_set_pll_dividers(intel_crtc);
4917
4918 if (intel_crtc->config.has_dp_encoder)
4919 intel_dp_set_m_n(intel_crtc);
4920
4921 intel_set_pipe_timings(intel_crtc);
4922
4923 i9xx_set_pipeconf(intel_crtc);
4924
4925 intel_crtc->active = true;
4926
4927 if (!IS_GEN2(dev))
4928 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4929
4930 for_each_encoder_on_crtc(dev, crtc, encoder)
4931 if (encoder->pre_enable)
4932 encoder->pre_enable(encoder);
4933
4934 i9xx_enable_pll(intel_crtc);
4935
4936 i9xx_pfit_enable(intel_crtc);
4937
4938 intel_crtc_load_lut(crtc);
4939
4940 intel_update_watermarks(crtc);
4941 intel_enable_pipe(intel_crtc);
4942
4943 for_each_encoder_on_crtc(dev, crtc, encoder)
4944 encoder->enable(encoder);
4945
4946 intel_crtc_enable_planes(crtc);
4947
4948 /*
4949 * Gen2 reports pipe underruns whenever all planes are disabled.
4950 * So don't enable underrun reporting before at least some planes
4951 * are enabled.
4952 * FIXME: Need to fix the logic to work when we turn off all planes
4953 * but leave the pipe running.
4954 */
4955 if (IS_GEN2(dev))
4956 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4957
4958 /* Underruns don't raise interrupts, so check manually. */
4959 i9xx_check_fifo_underruns(dev);
4960 }
4961
4962 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4963 {
4964 struct drm_device *dev = crtc->base.dev;
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966
4967 if (!crtc->config.gmch_pfit.control)
4968 return;
4969
4970 assert_pipe_disabled(dev_priv, crtc->pipe);
4971
4972 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4973 I915_READ(PFIT_CONTROL));
4974 I915_WRITE(PFIT_CONTROL, 0);
4975 }
4976
4977 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4978 {
4979 struct drm_device *dev = crtc->dev;
4980 struct drm_i915_private *dev_priv = dev->dev_private;
4981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4982 struct intel_encoder *encoder;
4983 int pipe = intel_crtc->pipe;
4984
4985 if (!intel_crtc->active)
4986 return;
4987
4988 /*
4989 * Gen2 reports pipe underruns whenever all planes are disabled.
4990 * So diasble underrun reporting before all the planes get disabled.
4991 * FIXME: Need to fix the logic to work when we turn off all planes
4992 * but leave the pipe running.
4993 */
4994 if (IS_GEN2(dev))
4995 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4996
4997 /*
4998 * Vblank time updates from the shadow to live plane control register
4999 * are blocked if the memory self-refresh mode is active at that
5000 * moment. So to make sure the plane gets truly disabled, disable
5001 * first the self-refresh mode. The self-refresh enable bit in turn
5002 * will be checked/applied by the HW only at the next frame start
5003 * event which is after the vblank start event, so we need to have a
5004 * wait-for-vblank between disabling the plane and the pipe.
5005 */
5006 intel_set_memory_cxsr(dev_priv, false);
5007 intel_crtc_disable_planes(crtc);
5008
5009 for_each_encoder_on_crtc(dev, crtc, encoder)
5010 encoder->disable(encoder);
5011
5012 /*
5013 * On gen2 planes are double buffered but the pipe isn't, so we must
5014 * wait for planes to fully turn off before disabling the pipe.
5015 * We also need to wait on all gmch platforms because of the
5016 * self-refresh mode constraint explained above.
5017 */
5018 intel_wait_for_vblank(dev, pipe);
5019
5020 intel_disable_pipe(intel_crtc);
5021
5022 i9xx_pfit_disable(intel_crtc);
5023
5024 for_each_encoder_on_crtc(dev, crtc, encoder)
5025 if (encoder->post_disable)
5026 encoder->post_disable(encoder);
5027
5028 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
5029 if (IS_CHERRYVIEW(dev))
5030 chv_disable_pll(dev_priv, pipe);
5031 else if (IS_VALLEYVIEW(dev))
5032 vlv_disable_pll(dev_priv, pipe);
5033 else
5034 i9xx_disable_pll(dev_priv, pipe);
5035 }
5036
5037 if (!IS_GEN2(dev))
5038 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5039
5040 intel_crtc->active = false;
5041 intel_update_watermarks(crtc);
5042
5043 mutex_lock(&dev->struct_mutex);
5044 intel_update_fbc(dev);
5045 mutex_unlock(&dev->struct_mutex);
5046 }
5047
5048 static void i9xx_crtc_off(struct drm_crtc *crtc)
5049 {
5050 }
5051
5052 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5053 bool enabled)
5054 {
5055 struct drm_device *dev = crtc->dev;
5056 struct drm_i915_master_private *master_priv;
5057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5058 int pipe = intel_crtc->pipe;
5059
5060 if (!dev->primary->master)
5061 return;
5062
5063 master_priv = dev->primary->master->driver_priv;
5064 if (!master_priv->sarea_priv)
5065 return;
5066
5067 switch (pipe) {
5068 case 0:
5069 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5070 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5071 break;
5072 case 1:
5073 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5074 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5075 break;
5076 default:
5077 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5078 break;
5079 }
5080 }
5081
5082 /* Master function to enable/disable CRTC and corresponding power wells */
5083 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5084 {
5085 struct drm_device *dev = crtc->dev;
5086 struct drm_i915_private *dev_priv = dev->dev_private;
5087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088 enum intel_display_power_domain domain;
5089 unsigned long domains;
5090
5091 if (enable) {
5092 if (!intel_crtc->active) {
5093 domains = get_crtc_power_domains(crtc);
5094 for_each_power_domain(domain, domains)
5095 intel_display_power_get(dev_priv, domain);
5096 intel_crtc->enabled_power_domains = domains;
5097
5098 dev_priv->display.crtc_enable(crtc);
5099 }
5100 } else {
5101 if (intel_crtc->active) {
5102 dev_priv->display.crtc_disable(crtc);
5103
5104 domains = intel_crtc->enabled_power_domains;
5105 for_each_power_domain(domain, domains)
5106 intel_display_power_put(dev_priv, domain);
5107 intel_crtc->enabled_power_domains = 0;
5108 }
5109 }
5110 }
5111
5112 /**
5113 * Sets the power management mode of the pipe and plane.
5114 */
5115 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5116 {
5117 struct drm_device *dev = crtc->dev;
5118 struct intel_encoder *intel_encoder;
5119 bool enable = false;
5120
5121 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5122 enable |= intel_encoder->connectors_active;
5123
5124 intel_crtc_control(crtc, enable);
5125
5126 intel_crtc_update_sarea(crtc, enable);
5127 }
5128
5129 static void intel_crtc_disable(struct drm_crtc *crtc)
5130 {
5131 struct drm_device *dev = crtc->dev;
5132 struct drm_connector *connector;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5135 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5136
5137 /* crtc should still be enabled when we disable it. */
5138 WARN_ON(!crtc->enabled);
5139
5140 dev_priv->display.crtc_disable(crtc);
5141 intel_crtc_update_sarea(crtc, false);
5142 dev_priv->display.off(crtc);
5143
5144 if (crtc->primary->fb) {
5145 mutex_lock(&dev->struct_mutex);
5146 intel_unpin_fb_obj(old_obj);
5147 i915_gem_track_fb(old_obj, NULL,
5148 INTEL_FRONTBUFFER_PRIMARY(pipe));
5149 mutex_unlock(&dev->struct_mutex);
5150 crtc->primary->fb = NULL;
5151 }
5152
5153 /* Update computed state. */
5154 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5155 if (!connector->encoder || !connector->encoder->crtc)
5156 continue;
5157
5158 if (connector->encoder->crtc != crtc)
5159 continue;
5160
5161 connector->dpms = DRM_MODE_DPMS_OFF;
5162 to_intel_encoder(connector->encoder)->connectors_active = false;
5163 }
5164 }
5165
5166 void intel_encoder_destroy(struct drm_encoder *encoder)
5167 {
5168 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5169
5170 drm_encoder_cleanup(encoder);
5171 kfree(intel_encoder);
5172 }
5173
5174 /* Simple dpms helper for encoders with just one connector, no cloning and only
5175 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5176 * state of the entire output pipe. */
5177 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5178 {
5179 if (mode == DRM_MODE_DPMS_ON) {
5180 encoder->connectors_active = true;
5181
5182 intel_crtc_update_dpms(encoder->base.crtc);
5183 } else {
5184 encoder->connectors_active = false;
5185
5186 intel_crtc_update_dpms(encoder->base.crtc);
5187 }
5188 }
5189
5190 /* Cross check the actual hw state with our own modeset state tracking (and it's
5191 * internal consistency). */
5192 static void intel_connector_check_state(struct intel_connector *connector)
5193 {
5194 if (connector->get_hw_state(connector)) {
5195 struct intel_encoder *encoder = connector->encoder;
5196 struct drm_crtc *crtc;
5197 bool encoder_enabled;
5198 enum pipe pipe;
5199
5200 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5201 connector->base.base.id,
5202 connector->base.name);
5203
5204 /* there is no real hw state for MST connectors */
5205 if (connector->mst_port)
5206 return;
5207
5208 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5209 "wrong connector dpms state\n");
5210 WARN(connector->base.encoder != &encoder->base,
5211 "active connector not linked to encoder\n");
5212
5213 if (encoder) {
5214 WARN(!encoder->connectors_active,
5215 "encoder->connectors_active not set\n");
5216
5217 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5218 WARN(!encoder_enabled, "encoder not enabled\n");
5219 if (WARN_ON(!encoder->base.crtc))
5220 return;
5221
5222 crtc = encoder->base.crtc;
5223
5224 WARN(!crtc->enabled, "crtc not enabled\n");
5225 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5226 WARN(pipe != to_intel_crtc(crtc)->pipe,
5227 "encoder active on the wrong pipe\n");
5228 }
5229 }
5230 }
5231
5232 /* Even simpler default implementation, if there's really no special case to
5233 * consider. */
5234 void intel_connector_dpms(struct drm_connector *connector, int mode)
5235 {
5236 /* All the simple cases only support two dpms states. */
5237 if (mode != DRM_MODE_DPMS_ON)
5238 mode = DRM_MODE_DPMS_OFF;
5239
5240 if (mode == connector->dpms)
5241 return;
5242
5243 connector->dpms = mode;
5244
5245 /* Only need to change hw state when actually enabled */
5246 if (connector->encoder)
5247 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5248
5249 intel_modeset_check_state(connector->dev);
5250 }
5251
5252 /* Simple connector->get_hw_state implementation for encoders that support only
5253 * one connector and no cloning and hence the encoder state determines the state
5254 * of the connector. */
5255 bool intel_connector_get_hw_state(struct intel_connector *connector)
5256 {
5257 enum pipe pipe = 0;
5258 struct intel_encoder *encoder = connector->encoder;
5259
5260 return encoder->get_hw_state(encoder, &pipe);
5261 }
5262
5263 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5264 struct intel_crtc_config *pipe_config)
5265 {
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267 struct intel_crtc *pipe_B_crtc =
5268 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5269
5270 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5271 pipe_name(pipe), pipe_config->fdi_lanes);
5272 if (pipe_config->fdi_lanes > 4) {
5273 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5274 pipe_name(pipe), pipe_config->fdi_lanes);
5275 return false;
5276 }
5277
5278 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5279 if (pipe_config->fdi_lanes > 2) {
5280 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5281 pipe_config->fdi_lanes);
5282 return false;
5283 } else {
5284 return true;
5285 }
5286 }
5287
5288 if (INTEL_INFO(dev)->num_pipes == 2)
5289 return true;
5290
5291 /* Ivybridge 3 pipe is really complicated */
5292 switch (pipe) {
5293 case PIPE_A:
5294 return true;
5295 case PIPE_B:
5296 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5297 pipe_config->fdi_lanes > 2) {
5298 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5299 pipe_name(pipe), pipe_config->fdi_lanes);
5300 return false;
5301 }
5302 return true;
5303 case PIPE_C:
5304 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5305 pipe_B_crtc->config.fdi_lanes <= 2) {
5306 if (pipe_config->fdi_lanes > 2) {
5307 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5308 pipe_name(pipe), pipe_config->fdi_lanes);
5309 return false;
5310 }
5311 } else {
5312 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5313 return false;
5314 }
5315 return true;
5316 default:
5317 BUG();
5318 }
5319 }
5320
5321 #define RETRY 1
5322 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5323 struct intel_crtc_config *pipe_config)
5324 {
5325 struct drm_device *dev = intel_crtc->base.dev;
5326 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5327 int lane, link_bw, fdi_dotclock;
5328 bool setup_ok, needs_recompute = false;
5329
5330 retry:
5331 /* FDI is a binary signal running at ~2.7GHz, encoding
5332 * each output octet as 10 bits. The actual frequency
5333 * is stored as a divider into a 100MHz clock, and the
5334 * mode pixel clock is stored in units of 1KHz.
5335 * Hence the bw of each lane in terms of the mode signal
5336 * is:
5337 */
5338 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5339
5340 fdi_dotclock = adjusted_mode->crtc_clock;
5341
5342 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5343 pipe_config->pipe_bpp);
5344
5345 pipe_config->fdi_lanes = lane;
5346
5347 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5348 link_bw, &pipe_config->fdi_m_n);
5349
5350 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5351 intel_crtc->pipe, pipe_config);
5352 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5353 pipe_config->pipe_bpp -= 2*3;
5354 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5355 pipe_config->pipe_bpp);
5356 needs_recompute = true;
5357 pipe_config->bw_constrained = true;
5358
5359 goto retry;
5360 }
5361
5362 if (needs_recompute)
5363 return RETRY;
5364
5365 return setup_ok ? 0 : -EINVAL;
5366 }
5367
5368 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5369 struct intel_crtc_config *pipe_config)
5370 {
5371 pipe_config->ips_enabled = i915.enable_ips &&
5372 hsw_crtc_supports_ips(crtc) &&
5373 pipe_config->pipe_bpp <= 24;
5374 }
5375
5376 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5377 struct intel_crtc_config *pipe_config)
5378 {
5379 struct drm_device *dev = crtc->base.dev;
5380 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5381
5382 /* FIXME should check pixel clock limits on all platforms */
5383 if (INTEL_INFO(dev)->gen < 4) {
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 int clock_limit =
5386 dev_priv->display.get_display_clock_speed(dev);
5387
5388 /*
5389 * Enable pixel doubling when the dot clock
5390 * is > 90% of the (display) core speed.
5391 *
5392 * GDG double wide on either pipe,
5393 * otherwise pipe A only.
5394 */
5395 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5396 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5397 clock_limit *= 2;
5398 pipe_config->double_wide = true;
5399 }
5400
5401 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5402 return -EINVAL;
5403 }
5404
5405 /*
5406 * Pipe horizontal size must be even in:
5407 * - DVO ganged mode
5408 * - LVDS dual channel mode
5409 * - Double wide pipe
5410 */
5411 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5412 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5413 pipe_config->pipe_src_w &= ~1;
5414
5415 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5416 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5417 */
5418 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5419 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5420 return -EINVAL;
5421
5422 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5423 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5424 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5425 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5426 * for lvds. */
5427 pipe_config->pipe_bpp = 8*3;
5428 }
5429
5430 if (HAS_IPS(dev))
5431 hsw_compute_ips_config(crtc, pipe_config);
5432
5433 /*
5434 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5435 * old clock survives for now.
5436 */
5437 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5438 pipe_config->shared_dpll = crtc->config.shared_dpll;
5439
5440 if (pipe_config->has_pch_encoder)
5441 return ironlake_fdi_compute_config(crtc, pipe_config);
5442
5443 return 0;
5444 }
5445
5446 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5447 {
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 int vco = valleyview_get_vco(dev_priv);
5450 u32 val;
5451 int divider;
5452
5453 /* FIXME: Punit isn't quite ready yet */
5454 if (IS_CHERRYVIEW(dev))
5455 return 400000;
5456
5457 mutex_lock(&dev_priv->dpio_lock);
5458 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5459 mutex_unlock(&dev_priv->dpio_lock);
5460
5461 divider = val & DISPLAY_FREQUENCY_VALUES;
5462
5463 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5464 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5465 "cdclk change in progress\n");
5466
5467 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5468 }
5469
5470 static int i945_get_display_clock_speed(struct drm_device *dev)
5471 {
5472 return 400000;
5473 }
5474
5475 static int i915_get_display_clock_speed(struct drm_device *dev)
5476 {
5477 return 333000;
5478 }
5479
5480 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5481 {
5482 return 200000;
5483 }
5484
5485 static int pnv_get_display_clock_speed(struct drm_device *dev)
5486 {
5487 u16 gcfgc = 0;
5488
5489 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5490
5491 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5492 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5493 return 267000;
5494 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5495 return 333000;
5496 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5497 return 444000;
5498 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5499 return 200000;
5500 default:
5501 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5502 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5503 return 133000;
5504 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5505 return 167000;
5506 }
5507 }
5508
5509 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5510 {
5511 u16 gcfgc = 0;
5512
5513 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5514
5515 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5516 return 133000;
5517 else {
5518 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5519 case GC_DISPLAY_CLOCK_333_MHZ:
5520 return 333000;
5521 default:
5522 case GC_DISPLAY_CLOCK_190_200_MHZ:
5523 return 190000;
5524 }
5525 }
5526 }
5527
5528 static int i865_get_display_clock_speed(struct drm_device *dev)
5529 {
5530 return 266000;
5531 }
5532
5533 static int i855_get_display_clock_speed(struct drm_device *dev)
5534 {
5535 u16 hpllcc = 0;
5536 /* Assume that the hardware is in the high speed state. This
5537 * should be the default.
5538 */
5539 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5540 case GC_CLOCK_133_200:
5541 case GC_CLOCK_100_200:
5542 return 200000;
5543 case GC_CLOCK_166_250:
5544 return 250000;
5545 case GC_CLOCK_100_133:
5546 return 133000;
5547 }
5548
5549 /* Shouldn't happen */
5550 return 0;
5551 }
5552
5553 static int i830_get_display_clock_speed(struct drm_device *dev)
5554 {
5555 return 133000;
5556 }
5557
5558 static void
5559 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5560 {
5561 while (*num > DATA_LINK_M_N_MASK ||
5562 *den > DATA_LINK_M_N_MASK) {
5563 *num >>= 1;
5564 *den >>= 1;
5565 }
5566 }
5567
5568 static void compute_m_n(unsigned int m, unsigned int n,
5569 uint32_t *ret_m, uint32_t *ret_n)
5570 {
5571 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5572 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5573 intel_reduce_m_n_ratio(ret_m, ret_n);
5574 }
5575
5576 void
5577 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5578 int pixel_clock, int link_clock,
5579 struct intel_link_m_n *m_n)
5580 {
5581 m_n->tu = 64;
5582
5583 compute_m_n(bits_per_pixel * pixel_clock,
5584 link_clock * nlanes * 8,
5585 &m_n->gmch_m, &m_n->gmch_n);
5586
5587 compute_m_n(pixel_clock, link_clock,
5588 &m_n->link_m, &m_n->link_n);
5589 }
5590
5591 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5592 {
5593 if (i915.panel_use_ssc >= 0)
5594 return i915.panel_use_ssc != 0;
5595 return dev_priv->vbt.lvds_use_ssc
5596 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5597 }
5598
5599 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5600 {
5601 struct drm_device *dev = crtc->dev;
5602 struct drm_i915_private *dev_priv = dev->dev_private;
5603 int refclk;
5604
5605 if (IS_VALLEYVIEW(dev)) {
5606 refclk = 100000;
5607 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5608 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5609 refclk = dev_priv->vbt.lvds_ssc_freq;
5610 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5611 } else if (!IS_GEN2(dev)) {
5612 refclk = 96000;
5613 } else {
5614 refclk = 48000;
5615 }
5616
5617 return refclk;
5618 }
5619
5620 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5621 {
5622 return (1 << dpll->n) << 16 | dpll->m2;
5623 }
5624
5625 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5626 {
5627 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5628 }
5629
5630 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5631 intel_clock_t *reduced_clock)
5632 {
5633 struct drm_device *dev = crtc->base.dev;
5634 u32 fp, fp2 = 0;
5635
5636 if (IS_PINEVIEW(dev)) {
5637 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5638 if (reduced_clock)
5639 fp2 = pnv_dpll_compute_fp(reduced_clock);
5640 } else {
5641 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5642 if (reduced_clock)
5643 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5644 }
5645
5646 crtc->config.dpll_hw_state.fp0 = fp;
5647
5648 crtc->lowfreq_avail = false;
5649 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5650 reduced_clock && i915.powersave) {
5651 crtc->config.dpll_hw_state.fp1 = fp2;
5652 crtc->lowfreq_avail = true;
5653 } else {
5654 crtc->config.dpll_hw_state.fp1 = fp;
5655 }
5656 }
5657
5658 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5659 pipe)
5660 {
5661 u32 reg_val;
5662
5663 /*
5664 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5665 * and set it to a reasonable value instead.
5666 */
5667 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5668 reg_val &= 0xffffff00;
5669 reg_val |= 0x00000030;
5670 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5671
5672 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5673 reg_val &= 0x8cffffff;
5674 reg_val = 0x8c000000;
5675 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5676
5677 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5678 reg_val &= 0xffffff00;
5679 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5680
5681 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5682 reg_val &= 0x00ffffff;
5683 reg_val |= 0xb0000000;
5684 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5685 }
5686
5687 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5688 struct intel_link_m_n *m_n)
5689 {
5690 struct drm_device *dev = crtc->base.dev;
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 int pipe = crtc->pipe;
5693
5694 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5695 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5696 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5697 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5698 }
5699
5700 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5701 struct intel_link_m_n *m_n,
5702 struct intel_link_m_n *m2_n2)
5703 {
5704 struct drm_device *dev = crtc->base.dev;
5705 struct drm_i915_private *dev_priv = dev->dev_private;
5706 int pipe = crtc->pipe;
5707 enum transcoder transcoder = crtc->config.cpu_transcoder;
5708
5709 if (INTEL_INFO(dev)->gen >= 5) {
5710 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5711 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5712 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5713 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5714 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5715 * for gen < 8) and if DRRS is supported (to make sure the
5716 * registers are not unnecessarily accessed).
5717 */
5718 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5719 crtc->config.has_drrs) {
5720 I915_WRITE(PIPE_DATA_M2(transcoder),
5721 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5722 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5723 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5724 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5725 }
5726 } else {
5727 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5728 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5729 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5730 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5731 }
5732 }
5733
5734 void intel_dp_set_m_n(struct intel_crtc *crtc)
5735 {
5736 if (crtc->config.has_pch_encoder)
5737 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5738 else
5739 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5740 &crtc->config.dp_m2_n2);
5741 }
5742
5743 static void vlv_update_pll(struct intel_crtc *crtc)
5744 {
5745 u32 dpll, dpll_md;
5746
5747 /*
5748 * Enable DPIO clock input. We should never disable the reference
5749 * clock for pipe B, since VGA hotplug / manual detection depends
5750 * on it.
5751 */
5752 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5753 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5754 /* We should never disable this, set it here for state tracking */
5755 if (crtc->pipe == PIPE_B)
5756 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5757 dpll |= DPLL_VCO_ENABLE;
5758 crtc->config.dpll_hw_state.dpll = dpll;
5759
5760 dpll_md = (crtc->config.pixel_multiplier - 1)
5761 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5762 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5763 }
5764
5765 static void vlv_prepare_pll(struct intel_crtc *crtc)
5766 {
5767 struct drm_device *dev = crtc->base.dev;
5768 struct drm_i915_private *dev_priv = dev->dev_private;
5769 int pipe = crtc->pipe;
5770 u32 mdiv;
5771 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5772 u32 coreclk, reg_val;
5773
5774 mutex_lock(&dev_priv->dpio_lock);
5775
5776 bestn = crtc->config.dpll.n;
5777 bestm1 = crtc->config.dpll.m1;
5778 bestm2 = crtc->config.dpll.m2;
5779 bestp1 = crtc->config.dpll.p1;
5780 bestp2 = crtc->config.dpll.p2;
5781
5782 /* See eDP HDMI DPIO driver vbios notes doc */
5783
5784 /* PLL B needs special handling */
5785 if (pipe == PIPE_B)
5786 vlv_pllb_recal_opamp(dev_priv, pipe);
5787
5788 /* Set up Tx target for periodic Rcomp update */
5789 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5790
5791 /* Disable target IRef on PLL */
5792 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5793 reg_val &= 0x00ffffff;
5794 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5795
5796 /* Disable fast lock */
5797 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5798
5799 /* Set idtafcrecal before PLL is enabled */
5800 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5801 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5802 mdiv |= ((bestn << DPIO_N_SHIFT));
5803 mdiv |= (1 << DPIO_K_SHIFT);
5804
5805 /*
5806 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5807 * but we don't support that).
5808 * Note: don't use the DAC post divider as it seems unstable.
5809 */
5810 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5811 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5812
5813 mdiv |= DPIO_ENABLE_CALIBRATION;
5814 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5815
5816 /* Set HBR and RBR LPF coefficients */
5817 if (crtc->config.port_clock == 162000 ||
5818 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5819 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5820 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5821 0x009f0003);
5822 else
5823 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5824 0x00d0000f);
5825
5826 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5827 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5828 /* Use SSC source */
5829 if (pipe == PIPE_A)
5830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5831 0x0df40000);
5832 else
5833 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5834 0x0df70000);
5835 } else { /* HDMI or VGA */
5836 /* Use bend source */
5837 if (pipe == PIPE_A)
5838 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5839 0x0df70000);
5840 else
5841 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5842 0x0df40000);
5843 }
5844
5845 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5846 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5847 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5848 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5849 coreclk |= 0x01000000;
5850 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5851
5852 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5853 mutex_unlock(&dev_priv->dpio_lock);
5854 }
5855
5856 static void chv_update_pll(struct intel_crtc *crtc)
5857 {
5858 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5859 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5860 DPLL_VCO_ENABLE;
5861 if (crtc->pipe != PIPE_A)
5862 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5863
5864 crtc->config.dpll_hw_state.dpll_md =
5865 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5866 }
5867
5868 static void chv_prepare_pll(struct intel_crtc *crtc)
5869 {
5870 struct drm_device *dev = crtc->base.dev;
5871 struct drm_i915_private *dev_priv = dev->dev_private;
5872 int pipe = crtc->pipe;
5873 int dpll_reg = DPLL(crtc->pipe);
5874 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5875 u32 loopfilter, intcoeff;
5876 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5877 int refclk;
5878
5879 bestn = crtc->config.dpll.n;
5880 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5881 bestm1 = crtc->config.dpll.m1;
5882 bestm2 = crtc->config.dpll.m2 >> 22;
5883 bestp1 = crtc->config.dpll.p1;
5884 bestp2 = crtc->config.dpll.p2;
5885
5886 /*
5887 * Enable Refclk and SSC
5888 */
5889 I915_WRITE(dpll_reg,
5890 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5891
5892 mutex_lock(&dev_priv->dpio_lock);
5893
5894 /* p1 and p2 divider */
5895 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5896 5 << DPIO_CHV_S1_DIV_SHIFT |
5897 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5898 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5899 1 << DPIO_CHV_K_DIV_SHIFT);
5900
5901 /* Feedback post-divider - m2 */
5902 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5903
5904 /* Feedback refclk divider - n and m1 */
5905 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5906 DPIO_CHV_M1_DIV_BY_2 |
5907 1 << DPIO_CHV_N_DIV_SHIFT);
5908
5909 /* M2 fraction division */
5910 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5911
5912 /* M2 fraction division enable */
5913 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5914 DPIO_CHV_FRAC_DIV_EN |
5915 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5916
5917 /* Loop filter */
5918 refclk = i9xx_get_refclk(&crtc->base, 0);
5919 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5920 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5921 if (refclk == 100000)
5922 intcoeff = 11;
5923 else if (refclk == 38400)
5924 intcoeff = 10;
5925 else
5926 intcoeff = 9;
5927 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5928 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5929
5930 /* AFC Recal */
5931 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5932 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5933 DPIO_AFC_RECAL);
5934
5935 mutex_unlock(&dev_priv->dpio_lock);
5936 }
5937
5938 static void i9xx_update_pll(struct intel_crtc *crtc,
5939 intel_clock_t *reduced_clock,
5940 int num_connectors)
5941 {
5942 struct drm_device *dev = crtc->base.dev;
5943 struct drm_i915_private *dev_priv = dev->dev_private;
5944 u32 dpll;
5945 bool is_sdvo;
5946 struct dpll *clock = &crtc->config.dpll;
5947
5948 i9xx_update_pll_dividers(crtc, reduced_clock);
5949
5950 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5951 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5952
5953 dpll = DPLL_VGA_MODE_DIS;
5954
5955 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5956 dpll |= DPLLB_MODE_LVDS;
5957 else
5958 dpll |= DPLLB_MODE_DAC_SERIAL;
5959
5960 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5961 dpll |= (crtc->config.pixel_multiplier - 1)
5962 << SDVO_MULTIPLIER_SHIFT_HIRES;
5963 }
5964
5965 if (is_sdvo)
5966 dpll |= DPLL_SDVO_HIGH_SPEED;
5967
5968 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5969 dpll |= DPLL_SDVO_HIGH_SPEED;
5970
5971 /* compute bitmask from p1 value */
5972 if (IS_PINEVIEW(dev))
5973 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5974 else {
5975 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5976 if (IS_G4X(dev) && reduced_clock)
5977 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5978 }
5979 switch (clock->p2) {
5980 case 5:
5981 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5982 break;
5983 case 7:
5984 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5985 break;
5986 case 10:
5987 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5988 break;
5989 case 14:
5990 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5991 break;
5992 }
5993 if (INTEL_INFO(dev)->gen >= 4)
5994 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5995
5996 if (crtc->config.sdvo_tv_clock)
5997 dpll |= PLL_REF_INPUT_TVCLKINBC;
5998 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5999 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6000 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6001 else
6002 dpll |= PLL_REF_INPUT_DREFCLK;
6003
6004 dpll |= DPLL_VCO_ENABLE;
6005 crtc->config.dpll_hw_state.dpll = dpll;
6006
6007 if (INTEL_INFO(dev)->gen >= 4) {
6008 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
6009 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6010 crtc->config.dpll_hw_state.dpll_md = dpll_md;
6011 }
6012 }
6013
6014 static void i8xx_update_pll(struct intel_crtc *crtc,
6015 intel_clock_t *reduced_clock,
6016 int num_connectors)
6017 {
6018 struct drm_device *dev = crtc->base.dev;
6019 struct drm_i915_private *dev_priv = dev->dev_private;
6020 u32 dpll;
6021 struct dpll *clock = &crtc->config.dpll;
6022
6023 i9xx_update_pll_dividers(crtc, reduced_clock);
6024
6025 dpll = DPLL_VGA_MODE_DIS;
6026
6027 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
6028 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6029 } else {
6030 if (clock->p1 == 2)
6031 dpll |= PLL_P1_DIVIDE_BY_TWO;
6032 else
6033 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6034 if (clock->p2 == 4)
6035 dpll |= PLL_P2_DIVIDE_BY_4;
6036 }
6037
6038 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
6039 dpll |= DPLL_DVO_2X_MODE;
6040
6041 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
6042 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6043 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6044 else
6045 dpll |= PLL_REF_INPUT_DREFCLK;
6046
6047 dpll |= DPLL_VCO_ENABLE;
6048 crtc->config.dpll_hw_state.dpll = dpll;
6049 }
6050
6051 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6052 {
6053 struct drm_device *dev = intel_crtc->base.dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 enum pipe pipe = intel_crtc->pipe;
6056 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6057 struct drm_display_mode *adjusted_mode =
6058 &intel_crtc->config.adjusted_mode;
6059 uint32_t crtc_vtotal, crtc_vblank_end;
6060 int vsyncshift = 0;
6061
6062 /* We need to be careful not to changed the adjusted mode, for otherwise
6063 * the hw state checker will get angry at the mismatch. */
6064 crtc_vtotal = adjusted_mode->crtc_vtotal;
6065 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6066
6067 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6068 /* the chip adds 2 halflines automatically */
6069 crtc_vtotal -= 1;
6070 crtc_vblank_end -= 1;
6071
6072 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6073 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6074 else
6075 vsyncshift = adjusted_mode->crtc_hsync_start -
6076 adjusted_mode->crtc_htotal / 2;
6077 if (vsyncshift < 0)
6078 vsyncshift += adjusted_mode->crtc_htotal;
6079 }
6080
6081 if (INTEL_INFO(dev)->gen > 3)
6082 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6083
6084 I915_WRITE(HTOTAL(cpu_transcoder),
6085 (adjusted_mode->crtc_hdisplay - 1) |
6086 ((adjusted_mode->crtc_htotal - 1) << 16));
6087 I915_WRITE(HBLANK(cpu_transcoder),
6088 (adjusted_mode->crtc_hblank_start - 1) |
6089 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6090 I915_WRITE(HSYNC(cpu_transcoder),
6091 (adjusted_mode->crtc_hsync_start - 1) |
6092 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6093
6094 I915_WRITE(VTOTAL(cpu_transcoder),
6095 (adjusted_mode->crtc_vdisplay - 1) |
6096 ((crtc_vtotal - 1) << 16));
6097 I915_WRITE(VBLANK(cpu_transcoder),
6098 (adjusted_mode->crtc_vblank_start - 1) |
6099 ((crtc_vblank_end - 1) << 16));
6100 I915_WRITE(VSYNC(cpu_transcoder),
6101 (adjusted_mode->crtc_vsync_start - 1) |
6102 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6103
6104 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6105 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6106 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6107 * bits. */
6108 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6109 (pipe == PIPE_B || pipe == PIPE_C))
6110 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6111
6112 /* pipesrc controls the size that is scaled from, which should
6113 * always be the user's requested size.
6114 */
6115 I915_WRITE(PIPESRC(pipe),
6116 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6117 (intel_crtc->config.pipe_src_h - 1));
6118 }
6119
6120 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6121 struct intel_crtc_config *pipe_config)
6122 {
6123 struct drm_device *dev = crtc->base.dev;
6124 struct drm_i915_private *dev_priv = dev->dev_private;
6125 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6126 uint32_t tmp;
6127
6128 tmp = I915_READ(HTOTAL(cpu_transcoder));
6129 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6130 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6131 tmp = I915_READ(HBLANK(cpu_transcoder));
6132 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6133 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6134 tmp = I915_READ(HSYNC(cpu_transcoder));
6135 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6136 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6137
6138 tmp = I915_READ(VTOTAL(cpu_transcoder));
6139 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6140 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6141 tmp = I915_READ(VBLANK(cpu_transcoder));
6142 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6143 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6144 tmp = I915_READ(VSYNC(cpu_transcoder));
6145 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6146 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6147
6148 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6149 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6150 pipe_config->adjusted_mode.crtc_vtotal += 1;
6151 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6152 }
6153
6154 tmp = I915_READ(PIPESRC(crtc->pipe));
6155 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6156 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6157
6158 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6159 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6160 }
6161
6162 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6163 struct intel_crtc_config *pipe_config)
6164 {
6165 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6166 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6167 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6168 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6169
6170 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6171 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6172 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6173 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6174
6175 mode->flags = pipe_config->adjusted_mode.flags;
6176
6177 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6178 mode->flags |= pipe_config->adjusted_mode.flags;
6179 }
6180
6181 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6182 {
6183 struct drm_device *dev = intel_crtc->base.dev;
6184 struct drm_i915_private *dev_priv = dev->dev_private;
6185 uint32_t pipeconf;
6186
6187 pipeconf = 0;
6188
6189 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6190 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6191 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6192
6193 if (intel_crtc->config.double_wide)
6194 pipeconf |= PIPECONF_DOUBLE_WIDE;
6195
6196 /* only g4x and later have fancy bpc/dither controls */
6197 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6198 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6199 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6200 pipeconf |= PIPECONF_DITHER_EN |
6201 PIPECONF_DITHER_TYPE_SP;
6202
6203 switch (intel_crtc->config.pipe_bpp) {
6204 case 18:
6205 pipeconf |= PIPECONF_6BPC;
6206 break;
6207 case 24:
6208 pipeconf |= PIPECONF_8BPC;
6209 break;
6210 case 30:
6211 pipeconf |= PIPECONF_10BPC;
6212 break;
6213 default:
6214 /* Case prevented by intel_choose_pipe_bpp_dither. */
6215 BUG();
6216 }
6217 }
6218
6219 if (HAS_PIPE_CXSR(dev)) {
6220 if (intel_crtc->lowfreq_avail) {
6221 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6222 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6223 } else {
6224 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6225 }
6226 }
6227
6228 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6229 if (INTEL_INFO(dev)->gen < 4 ||
6230 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6231 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6232 else
6233 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6234 } else
6235 pipeconf |= PIPECONF_PROGRESSIVE;
6236
6237 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6238 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6239
6240 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6241 POSTING_READ(PIPECONF(intel_crtc->pipe));
6242 }
6243
6244 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6245 int x, int y,
6246 struct drm_framebuffer *fb)
6247 {
6248 struct drm_device *dev = crtc->dev;
6249 struct drm_i915_private *dev_priv = dev->dev_private;
6250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6251 int refclk, num_connectors = 0;
6252 intel_clock_t clock, reduced_clock;
6253 bool ok, has_reduced_clock = false;
6254 bool is_lvds = false, is_dsi = false;
6255 struct intel_encoder *encoder;
6256 const intel_limit_t *limit;
6257
6258 for_each_encoder_on_crtc(dev, crtc, encoder) {
6259 switch (encoder->type) {
6260 case INTEL_OUTPUT_LVDS:
6261 is_lvds = true;
6262 break;
6263 case INTEL_OUTPUT_DSI:
6264 is_dsi = true;
6265 break;
6266 }
6267
6268 num_connectors++;
6269 }
6270
6271 if (is_dsi)
6272 return 0;
6273
6274 if (!intel_crtc->config.clock_set) {
6275 refclk = i9xx_get_refclk(crtc, num_connectors);
6276
6277 /*
6278 * Returns a set of divisors for the desired target clock with
6279 * the given refclk, or FALSE. The returned values represent
6280 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6281 * 2) / p1 / p2.
6282 */
6283 limit = intel_limit(crtc, refclk);
6284 ok = dev_priv->display.find_dpll(limit, crtc,
6285 intel_crtc->config.port_clock,
6286 refclk, NULL, &clock);
6287 if (!ok) {
6288 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6289 return -EINVAL;
6290 }
6291
6292 if (is_lvds && dev_priv->lvds_downclock_avail) {
6293 /*
6294 * Ensure we match the reduced clock's P to the target
6295 * clock. If the clocks don't match, we can't switch
6296 * the display clock by using the FP0/FP1. In such case
6297 * we will disable the LVDS downclock feature.
6298 */
6299 has_reduced_clock =
6300 dev_priv->display.find_dpll(limit, crtc,
6301 dev_priv->lvds_downclock,
6302 refclk, &clock,
6303 &reduced_clock);
6304 }
6305 /* Compat-code for transition, will disappear. */
6306 intel_crtc->config.dpll.n = clock.n;
6307 intel_crtc->config.dpll.m1 = clock.m1;
6308 intel_crtc->config.dpll.m2 = clock.m2;
6309 intel_crtc->config.dpll.p1 = clock.p1;
6310 intel_crtc->config.dpll.p2 = clock.p2;
6311 }
6312
6313 if (IS_GEN2(dev)) {
6314 i8xx_update_pll(intel_crtc,
6315 has_reduced_clock ? &reduced_clock : NULL,
6316 num_connectors);
6317 } else if (IS_CHERRYVIEW(dev)) {
6318 chv_update_pll(intel_crtc);
6319 } else if (IS_VALLEYVIEW(dev)) {
6320 vlv_update_pll(intel_crtc);
6321 } else {
6322 i9xx_update_pll(intel_crtc,
6323 has_reduced_clock ? &reduced_clock : NULL,
6324 num_connectors);
6325 }
6326
6327 return 0;
6328 }
6329
6330 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6331 struct intel_crtc_config *pipe_config)
6332 {
6333 struct drm_device *dev = crtc->base.dev;
6334 struct drm_i915_private *dev_priv = dev->dev_private;
6335 uint32_t tmp;
6336
6337 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6338 return;
6339
6340 tmp = I915_READ(PFIT_CONTROL);
6341 if (!(tmp & PFIT_ENABLE))
6342 return;
6343
6344 /* Check whether the pfit is attached to our pipe. */
6345 if (INTEL_INFO(dev)->gen < 4) {
6346 if (crtc->pipe != PIPE_B)
6347 return;
6348 } else {
6349 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6350 return;
6351 }
6352
6353 pipe_config->gmch_pfit.control = tmp;
6354 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6355 if (INTEL_INFO(dev)->gen < 5)
6356 pipe_config->gmch_pfit.lvds_border_bits =
6357 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6358 }
6359
6360 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6361 struct intel_crtc_config *pipe_config)
6362 {
6363 struct drm_device *dev = crtc->base.dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 int pipe = pipe_config->cpu_transcoder;
6366 intel_clock_t clock;
6367 u32 mdiv;
6368 int refclk = 100000;
6369
6370 /* In case of MIPI DPLL will not even be used */
6371 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6372 return;
6373
6374 mutex_lock(&dev_priv->dpio_lock);
6375 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6376 mutex_unlock(&dev_priv->dpio_lock);
6377
6378 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6379 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6380 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6381 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6382 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6383
6384 vlv_clock(refclk, &clock);
6385
6386 /* clock.dot is the fast clock */
6387 pipe_config->port_clock = clock.dot / 5;
6388 }
6389
6390 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6391 struct intel_plane_config *plane_config)
6392 {
6393 struct drm_device *dev = crtc->base.dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 u32 val, base, offset;
6396 int pipe = crtc->pipe, plane = crtc->plane;
6397 int fourcc, pixel_format;
6398 int aligned_height;
6399
6400 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6401 if (!crtc->base.primary->fb) {
6402 DRM_DEBUG_KMS("failed to alloc fb\n");
6403 return;
6404 }
6405
6406 val = I915_READ(DSPCNTR(plane));
6407
6408 if (INTEL_INFO(dev)->gen >= 4)
6409 if (val & DISPPLANE_TILED)
6410 plane_config->tiled = true;
6411
6412 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6413 fourcc = intel_format_to_fourcc(pixel_format);
6414 crtc->base.primary->fb->pixel_format = fourcc;
6415 crtc->base.primary->fb->bits_per_pixel =
6416 drm_format_plane_cpp(fourcc, 0) * 8;
6417
6418 if (INTEL_INFO(dev)->gen >= 4) {
6419 if (plane_config->tiled)
6420 offset = I915_READ(DSPTILEOFF(plane));
6421 else
6422 offset = I915_READ(DSPLINOFF(plane));
6423 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6424 } else {
6425 base = I915_READ(DSPADDR(plane));
6426 }
6427 plane_config->base = base;
6428
6429 val = I915_READ(PIPESRC(pipe));
6430 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6431 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6432
6433 val = I915_READ(DSPSTRIDE(pipe));
6434 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6435
6436 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6437 plane_config->tiled);
6438
6439 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6440 aligned_height);
6441
6442 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6443 pipe, plane, crtc->base.primary->fb->width,
6444 crtc->base.primary->fb->height,
6445 crtc->base.primary->fb->bits_per_pixel, base,
6446 crtc->base.primary->fb->pitches[0],
6447 plane_config->size);
6448
6449 }
6450
6451 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6452 struct intel_crtc_config *pipe_config)
6453 {
6454 struct drm_device *dev = crtc->base.dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 int pipe = pipe_config->cpu_transcoder;
6457 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6458 intel_clock_t clock;
6459 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6460 int refclk = 100000;
6461
6462 mutex_lock(&dev_priv->dpio_lock);
6463 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6464 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6465 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6466 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6467 mutex_unlock(&dev_priv->dpio_lock);
6468
6469 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6470 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6471 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6472 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6473 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6474
6475 chv_clock(refclk, &clock);
6476
6477 /* clock.dot is the fast clock */
6478 pipe_config->port_clock = clock.dot / 5;
6479 }
6480
6481 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6482 struct intel_crtc_config *pipe_config)
6483 {
6484 struct drm_device *dev = crtc->base.dev;
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486 uint32_t tmp;
6487
6488 if (!intel_display_power_enabled(dev_priv,
6489 POWER_DOMAIN_PIPE(crtc->pipe)))
6490 return false;
6491
6492 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6493 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6494
6495 tmp = I915_READ(PIPECONF(crtc->pipe));
6496 if (!(tmp & PIPECONF_ENABLE))
6497 return false;
6498
6499 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6500 switch (tmp & PIPECONF_BPC_MASK) {
6501 case PIPECONF_6BPC:
6502 pipe_config->pipe_bpp = 18;
6503 break;
6504 case PIPECONF_8BPC:
6505 pipe_config->pipe_bpp = 24;
6506 break;
6507 case PIPECONF_10BPC:
6508 pipe_config->pipe_bpp = 30;
6509 break;
6510 default:
6511 break;
6512 }
6513 }
6514
6515 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6516 pipe_config->limited_color_range = true;
6517
6518 if (INTEL_INFO(dev)->gen < 4)
6519 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6520
6521 intel_get_pipe_timings(crtc, pipe_config);
6522
6523 i9xx_get_pfit_config(crtc, pipe_config);
6524
6525 if (INTEL_INFO(dev)->gen >= 4) {
6526 tmp = I915_READ(DPLL_MD(crtc->pipe));
6527 pipe_config->pixel_multiplier =
6528 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6529 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6530 pipe_config->dpll_hw_state.dpll_md = tmp;
6531 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6532 tmp = I915_READ(DPLL(crtc->pipe));
6533 pipe_config->pixel_multiplier =
6534 ((tmp & SDVO_MULTIPLIER_MASK)
6535 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6536 } else {
6537 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6538 * port and will be fixed up in the encoder->get_config
6539 * function. */
6540 pipe_config->pixel_multiplier = 1;
6541 }
6542 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6543 if (!IS_VALLEYVIEW(dev)) {
6544 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6545 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6546 } else {
6547 /* Mask out read-only status bits. */
6548 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6549 DPLL_PORTC_READY_MASK |
6550 DPLL_PORTB_READY_MASK);
6551 }
6552
6553 if (IS_CHERRYVIEW(dev))
6554 chv_crtc_clock_get(crtc, pipe_config);
6555 else if (IS_VALLEYVIEW(dev))
6556 vlv_crtc_clock_get(crtc, pipe_config);
6557 else
6558 i9xx_crtc_clock_get(crtc, pipe_config);
6559
6560 return true;
6561 }
6562
6563 static void ironlake_init_pch_refclk(struct drm_device *dev)
6564 {
6565 struct drm_i915_private *dev_priv = dev->dev_private;
6566 struct intel_encoder *encoder;
6567 u32 val, final;
6568 bool has_lvds = false;
6569 bool has_cpu_edp = false;
6570 bool has_panel = false;
6571 bool has_ck505 = false;
6572 bool can_ssc = false;
6573
6574 /* We need to take the global config into account */
6575 for_each_intel_encoder(dev, encoder) {
6576 switch (encoder->type) {
6577 case INTEL_OUTPUT_LVDS:
6578 has_panel = true;
6579 has_lvds = true;
6580 break;
6581 case INTEL_OUTPUT_EDP:
6582 has_panel = true;
6583 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6584 has_cpu_edp = true;
6585 break;
6586 }
6587 }
6588
6589 if (HAS_PCH_IBX(dev)) {
6590 has_ck505 = dev_priv->vbt.display_clock_mode;
6591 can_ssc = has_ck505;
6592 } else {
6593 has_ck505 = false;
6594 can_ssc = true;
6595 }
6596
6597 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6598 has_panel, has_lvds, has_ck505);
6599
6600 /* Ironlake: try to setup display ref clock before DPLL
6601 * enabling. This is only under driver's control after
6602 * PCH B stepping, previous chipset stepping should be
6603 * ignoring this setting.
6604 */
6605 val = I915_READ(PCH_DREF_CONTROL);
6606
6607 /* As we must carefully and slowly disable/enable each source in turn,
6608 * compute the final state we want first and check if we need to
6609 * make any changes at all.
6610 */
6611 final = val;
6612 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6613 if (has_ck505)
6614 final |= DREF_NONSPREAD_CK505_ENABLE;
6615 else
6616 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6617
6618 final &= ~DREF_SSC_SOURCE_MASK;
6619 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6620 final &= ~DREF_SSC1_ENABLE;
6621
6622 if (has_panel) {
6623 final |= DREF_SSC_SOURCE_ENABLE;
6624
6625 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6626 final |= DREF_SSC1_ENABLE;
6627
6628 if (has_cpu_edp) {
6629 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6630 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6631 else
6632 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6633 } else
6634 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6635 } else {
6636 final |= DREF_SSC_SOURCE_DISABLE;
6637 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6638 }
6639
6640 if (final == val)
6641 return;
6642
6643 /* Always enable nonspread source */
6644 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6645
6646 if (has_ck505)
6647 val |= DREF_NONSPREAD_CK505_ENABLE;
6648 else
6649 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6650
6651 if (has_panel) {
6652 val &= ~DREF_SSC_SOURCE_MASK;
6653 val |= DREF_SSC_SOURCE_ENABLE;
6654
6655 /* SSC must be turned on before enabling the CPU output */
6656 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6657 DRM_DEBUG_KMS("Using SSC on panel\n");
6658 val |= DREF_SSC1_ENABLE;
6659 } else
6660 val &= ~DREF_SSC1_ENABLE;
6661
6662 /* Get SSC going before enabling the outputs */
6663 I915_WRITE(PCH_DREF_CONTROL, val);
6664 POSTING_READ(PCH_DREF_CONTROL);
6665 udelay(200);
6666
6667 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6668
6669 /* Enable CPU source on CPU attached eDP */
6670 if (has_cpu_edp) {
6671 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6672 DRM_DEBUG_KMS("Using SSC on eDP\n");
6673 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6674 } else
6675 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6676 } else
6677 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6678
6679 I915_WRITE(PCH_DREF_CONTROL, val);
6680 POSTING_READ(PCH_DREF_CONTROL);
6681 udelay(200);
6682 } else {
6683 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6684
6685 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6686
6687 /* Turn off CPU output */
6688 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6689
6690 I915_WRITE(PCH_DREF_CONTROL, val);
6691 POSTING_READ(PCH_DREF_CONTROL);
6692 udelay(200);
6693
6694 /* Turn off the SSC source */
6695 val &= ~DREF_SSC_SOURCE_MASK;
6696 val |= DREF_SSC_SOURCE_DISABLE;
6697
6698 /* Turn off SSC1 */
6699 val &= ~DREF_SSC1_ENABLE;
6700
6701 I915_WRITE(PCH_DREF_CONTROL, val);
6702 POSTING_READ(PCH_DREF_CONTROL);
6703 udelay(200);
6704 }
6705
6706 BUG_ON(val != final);
6707 }
6708
6709 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6710 {
6711 uint32_t tmp;
6712
6713 tmp = I915_READ(SOUTH_CHICKEN2);
6714 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6715 I915_WRITE(SOUTH_CHICKEN2, tmp);
6716
6717 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6718 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6719 DRM_ERROR("FDI mPHY reset assert timeout\n");
6720
6721 tmp = I915_READ(SOUTH_CHICKEN2);
6722 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6723 I915_WRITE(SOUTH_CHICKEN2, tmp);
6724
6725 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6726 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6727 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6728 }
6729
6730 /* WaMPhyProgramming:hsw */
6731 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6732 {
6733 uint32_t tmp;
6734
6735 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6736 tmp &= ~(0xFF << 24);
6737 tmp |= (0x12 << 24);
6738 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6739
6740 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6741 tmp |= (1 << 11);
6742 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6743
6744 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6745 tmp |= (1 << 11);
6746 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6747
6748 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6749 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6750 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6751
6752 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6753 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6754 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6755
6756 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6757 tmp &= ~(7 << 13);
6758 tmp |= (5 << 13);
6759 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6760
6761 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6762 tmp &= ~(7 << 13);
6763 tmp |= (5 << 13);
6764 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6765
6766 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6767 tmp &= ~0xFF;
6768 tmp |= 0x1C;
6769 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6770
6771 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6772 tmp &= ~0xFF;
6773 tmp |= 0x1C;
6774 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6775
6776 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6777 tmp &= ~(0xFF << 16);
6778 tmp |= (0x1C << 16);
6779 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6780
6781 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6782 tmp &= ~(0xFF << 16);
6783 tmp |= (0x1C << 16);
6784 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6785
6786 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6787 tmp |= (1 << 27);
6788 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6789
6790 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6791 tmp |= (1 << 27);
6792 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6793
6794 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6795 tmp &= ~(0xF << 28);
6796 tmp |= (4 << 28);
6797 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6798
6799 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6800 tmp &= ~(0xF << 28);
6801 tmp |= (4 << 28);
6802 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6803 }
6804
6805 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6806 * Programming" based on the parameters passed:
6807 * - Sequence to enable CLKOUT_DP
6808 * - Sequence to enable CLKOUT_DP without spread
6809 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6810 */
6811 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6812 bool with_fdi)
6813 {
6814 struct drm_i915_private *dev_priv = dev->dev_private;
6815 uint32_t reg, tmp;
6816
6817 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6818 with_spread = true;
6819 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6820 with_fdi, "LP PCH doesn't have FDI\n"))
6821 with_fdi = false;
6822
6823 mutex_lock(&dev_priv->dpio_lock);
6824
6825 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6826 tmp &= ~SBI_SSCCTL_DISABLE;
6827 tmp |= SBI_SSCCTL_PATHALT;
6828 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6829
6830 udelay(24);
6831
6832 if (with_spread) {
6833 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6834 tmp &= ~SBI_SSCCTL_PATHALT;
6835 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6836
6837 if (with_fdi) {
6838 lpt_reset_fdi_mphy(dev_priv);
6839 lpt_program_fdi_mphy(dev_priv);
6840 }
6841 }
6842
6843 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6844 SBI_GEN0 : SBI_DBUFF0;
6845 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6846 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6847 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6848
6849 mutex_unlock(&dev_priv->dpio_lock);
6850 }
6851
6852 /* Sequence to disable CLKOUT_DP */
6853 static void lpt_disable_clkout_dp(struct drm_device *dev)
6854 {
6855 struct drm_i915_private *dev_priv = dev->dev_private;
6856 uint32_t reg, tmp;
6857
6858 mutex_lock(&dev_priv->dpio_lock);
6859
6860 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6861 SBI_GEN0 : SBI_DBUFF0;
6862 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6863 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6864 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6865
6866 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6867 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6868 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6869 tmp |= SBI_SSCCTL_PATHALT;
6870 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6871 udelay(32);
6872 }
6873 tmp |= SBI_SSCCTL_DISABLE;
6874 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6875 }
6876
6877 mutex_unlock(&dev_priv->dpio_lock);
6878 }
6879
6880 static void lpt_init_pch_refclk(struct drm_device *dev)
6881 {
6882 struct intel_encoder *encoder;
6883 bool has_vga = false;
6884
6885 for_each_intel_encoder(dev, encoder) {
6886 switch (encoder->type) {
6887 case INTEL_OUTPUT_ANALOG:
6888 has_vga = true;
6889 break;
6890 }
6891 }
6892
6893 if (has_vga)
6894 lpt_enable_clkout_dp(dev, true, true);
6895 else
6896 lpt_disable_clkout_dp(dev);
6897 }
6898
6899 /*
6900 * Initialize reference clocks when the driver loads
6901 */
6902 void intel_init_pch_refclk(struct drm_device *dev)
6903 {
6904 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6905 ironlake_init_pch_refclk(dev);
6906 else if (HAS_PCH_LPT(dev))
6907 lpt_init_pch_refclk(dev);
6908 }
6909
6910 static int ironlake_get_refclk(struct drm_crtc *crtc)
6911 {
6912 struct drm_device *dev = crtc->dev;
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_encoder *encoder;
6915 int num_connectors = 0;
6916 bool is_lvds = false;
6917
6918 for_each_encoder_on_crtc(dev, crtc, encoder) {
6919 switch (encoder->type) {
6920 case INTEL_OUTPUT_LVDS:
6921 is_lvds = true;
6922 break;
6923 }
6924 num_connectors++;
6925 }
6926
6927 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6928 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6929 dev_priv->vbt.lvds_ssc_freq);
6930 return dev_priv->vbt.lvds_ssc_freq;
6931 }
6932
6933 return 120000;
6934 }
6935
6936 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6937 {
6938 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6940 int pipe = intel_crtc->pipe;
6941 uint32_t val;
6942
6943 val = 0;
6944
6945 switch (intel_crtc->config.pipe_bpp) {
6946 case 18:
6947 val |= PIPECONF_6BPC;
6948 break;
6949 case 24:
6950 val |= PIPECONF_8BPC;
6951 break;
6952 case 30:
6953 val |= PIPECONF_10BPC;
6954 break;
6955 case 36:
6956 val |= PIPECONF_12BPC;
6957 break;
6958 default:
6959 /* Case prevented by intel_choose_pipe_bpp_dither. */
6960 BUG();
6961 }
6962
6963 if (intel_crtc->config.dither)
6964 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6965
6966 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6967 val |= PIPECONF_INTERLACED_ILK;
6968 else
6969 val |= PIPECONF_PROGRESSIVE;
6970
6971 if (intel_crtc->config.limited_color_range)
6972 val |= PIPECONF_COLOR_RANGE_SELECT;
6973
6974 I915_WRITE(PIPECONF(pipe), val);
6975 POSTING_READ(PIPECONF(pipe));
6976 }
6977
6978 /*
6979 * Set up the pipe CSC unit.
6980 *
6981 * Currently only full range RGB to limited range RGB conversion
6982 * is supported, but eventually this should handle various
6983 * RGB<->YCbCr scenarios as well.
6984 */
6985 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6986 {
6987 struct drm_device *dev = crtc->dev;
6988 struct drm_i915_private *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 int pipe = intel_crtc->pipe;
6991 uint16_t coeff = 0x7800; /* 1.0 */
6992
6993 /*
6994 * TODO: Check what kind of values actually come out of the pipe
6995 * with these coeff/postoff values and adjust to get the best
6996 * accuracy. Perhaps we even need to take the bpc value into
6997 * consideration.
6998 */
6999
7000 if (intel_crtc->config.limited_color_range)
7001 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7002
7003 /*
7004 * GY/GU and RY/RU should be the other way around according
7005 * to BSpec, but reality doesn't agree. Just set them up in
7006 * a way that results in the correct picture.
7007 */
7008 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7009 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7010
7011 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7012 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7013
7014 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7015 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7016
7017 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7018 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7019 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7020
7021 if (INTEL_INFO(dev)->gen > 6) {
7022 uint16_t postoff = 0;
7023
7024 if (intel_crtc->config.limited_color_range)
7025 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7026
7027 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7028 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7029 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7030
7031 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7032 } else {
7033 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7034
7035 if (intel_crtc->config.limited_color_range)
7036 mode |= CSC_BLACK_SCREEN_OFFSET;
7037
7038 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7039 }
7040 }
7041
7042 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7043 {
7044 struct drm_device *dev = crtc->dev;
7045 struct drm_i915_private *dev_priv = dev->dev_private;
7046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047 enum pipe pipe = intel_crtc->pipe;
7048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7049 uint32_t val;
7050
7051 val = 0;
7052
7053 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7054 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7055
7056 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7057 val |= PIPECONF_INTERLACED_ILK;
7058 else
7059 val |= PIPECONF_PROGRESSIVE;
7060
7061 I915_WRITE(PIPECONF(cpu_transcoder), val);
7062 POSTING_READ(PIPECONF(cpu_transcoder));
7063
7064 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7065 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7066
7067 if (IS_BROADWELL(dev)) {
7068 val = 0;
7069
7070 switch (intel_crtc->config.pipe_bpp) {
7071 case 18:
7072 val |= PIPEMISC_DITHER_6_BPC;
7073 break;
7074 case 24:
7075 val |= PIPEMISC_DITHER_8_BPC;
7076 break;
7077 case 30:
7078 val |= PIPEMISC_DITHER_10_BPC;
7079 break;
7080 case 36:
7081 val |= PIPEMISC_DITHER_12_BPC;
7082 break;
7083 default:
7084 /* Case prevented by pipe_config_set_bpp. */
7085 BUG();
7086 }
7087
7088 if (intel_crtc->config.dither)
7089 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7090
7091 I915_WRITE(PIPEMISC(pipe), val);
7092 }
7093 }
7094
7095 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7096 intel_clock_t *clock,
7097 bool *has_reduced_clock,
7098 intel_clock_t *reduced_clock)
7099 {
7100 struct drm_device *dev = crtc->dev;
7101 struct drm_i915_private *dev_priv = dev->dev_private;
7102 struct intel_encoder *intel_encoder;
7103 int refclk;
7104 const intel_limit_t *limit;
7105 bool ret, is_lvds = false;
7106
7107 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7108 switch (intel_encoder->type) {
7109 case INTEL_OUTPUT_LVDS:
7110 is_lvds = true;
7111 break;
7112 }
7113 }
7114
7115 refclk = ironlake_get_refclk(crtc);
7116
7117 /*
7118 * Returns a set of divisors for the desired target clock with the given
7119 * refclk, or FALSE. The returned values represent the clock equation:
7120 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7121 */
7122 limit = intel_limit(crtc, refclk);
7123 ret = dev_priv->display.find_dpll(limit, crtc,
7124 to_intel_crtc(crtc)->config.port_clock,
7125 refclk, NULL, clock);
7126 if (!ret)
7127 return false;
7128
7129 if (is_lvds && dev_priv->lvds_downclock_avail) {
7130 /*
7131 * Ensure we match the reduced clock's P to the target clock.
7132 * If the clocks don't match, we can't switch the display clock
7133 * by using the FP0/FP1. In such case we will disable the LVDS
7134 * downclock feature.
7135 */
7136 *has_reduced_clock =
7137 dev_priv->display.find_dpll(limit, crtc,
7138 dev_priv->lvds_downclock,
7139 refclk, clock,
7140 reduced_clock);
7141 }
7142
7143 return true;
7144 }
7145
7146 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7147 {
7148 /*
7149 * Account for spread spectrum to avoid
7150 * oversubscribing the link. Max center spread
7151 * is 2.5%; use 5% for safety's sake.
7152 */
7153 u32 bps = target_clock * bpp * 21 / 20;
7154 return DIV_ROUND_UP(bps, link_bw * 8);
7155 }
7156
7157 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7158 {
7159 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7160 }
7161
7162 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7163 u32 *fp,
7164 intel_clock_t *reduced_clock, u32 *fp2)
7165 {
7166 struct drm_crtc *crtc = &intel_crtc->base;
7167 struct drm_device *dev = crtc->dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 struct intel_encoder *intel_encoder;
7170 uint32_t dpll;
7171 int factor, num_connectors = 0;
7172 bool is_lvds = false, is_sdvo = false;
7173
7174 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7175 switch (intel_encoder->type) {
7176 case INTEL_OUTPUT_LVDS:
7177 is_lvds = true;
7178 break;
7179 case INTEL_OUTPUT_SDVO:
7180 case INTEL_OUTPUT_HDMI:
7181 is_sdvo = true;
7182 break;
7183 }
7184
7185 num_connectors++;
7186 }
7187
7188 /* Enable autotuning of the PLL clock (if permissible) */
7189 factor = 21;
7190 if (is_lvds) {
7191 if ((intel_panel_use_ssc(dev_priv) &&
7192 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7193 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7194 factor = 25;
7195 } else if (intel_crtc->config.sdvo_tv_clock)
7196 factor = 20;
7197
7198 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7199 *fp |= FP_CB_TUNE;
7200
7201 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7202 *fp2 |= FP_CB_TUNE;
7203
7204 dpll = 0;
7205
7206 if (is_lvds)
7207 dpll |= DPLLB_MODE_LVDS;
7208 else
7209 dpll |= DPLLB_MODE_DAC_SERIAL;
7210
7211 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7212 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7213
7214 if (is_sdvo)
7215 dpll |= DPLL_SDVO_HIGH_SPEED;
7216 if (intel_crtc->config.has_dp_encoder)
7217 dpll |= DPLL_SDVO_HIGH_SPEED;
7218
7219 /* compute bitmask from p1 value */
7220 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7221 /* also FPA1 */
7222 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7223
7224 switch (intel_crtc->config.dpll.p2) {
7225 case 5:
7226 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7227 break;
7228 case 7:
7229 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7230 break;
7231 case 10:
7232 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7233 break;
7234 case 14:
7235 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7236 break;
7237 }
7238
7239 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7240 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7241 else
7242 dpll |= PLL_REF_INPUT_DREFCLK;
7243
7244 return dpll | DPLL_VCO_ENABLE;
7245 }
7246
7247 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7248 int x, int y,
7249 struct drm_framebuffer *fb)
7250 {
7251 struct drm_device *dev = crtc->dev;
7252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253 int num_connectors = 0;
7254 intel_clock_t clock, reduced_clock;
7255 u32 dpll = 0, fp = 0, fp2 = 0;
7256 bool ok, has_reduced_clock = false;
7257 bool is_lvds = false;
7258 struct intel_encoder *encoder;
7259 struct intel_shared_dpll *pll;
7260
7261 for_each_encoder_on_crtc(dev, crtc, encoder) {
7262 switch (encoder->type) {
7263 case INTEL_OUTPUT_LVDS:
7264 is_lvds = true;
7265 break;
7266 }
7267
7268 num_connectors++;
7269 }
7270
7271 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7272 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7273
7274 ok = ironlake_compute_clocks(crtc, &clock,
7275 &has_reduced_clock, &reduced_clock);
7276 if (!ok && !intel_crtc->config.clock_set) {
7277 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7278 return -EINVAL;
7279 }
7280 /* Compat-code for transition, will disappear. */
7281 if (!intel_crtc->config.clock_set) {
7282 intel_crtc->config.dpll.n = clock.n;
7283 intel_crtc->config.dpll.m1 = clock.m1;
7284 intel_crtc->config.dpll.m2 = clock.m2;
7285 intel_crtc->config.dpll.p1 = clock.p1;
7286 intel_crtc->config.dpll.p2 = clock.p2;
7287 }
7288
7289 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7290 if (intel_crtc->config.has_pch_encoder) {
7291 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7292 if (has_reduced_clock)
7293 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7294
7295 dpll = ironlake_compute_dpll(intel_crtc,
7296 &fp, &reduced_clock,
7297 has_reduced_clock ? &fp2 : NULL);
7298
7299 intel_crtc->config.dpll_hw_state.dpll = dpll;
7300 intel_crtc->config.dpll_hw_state.fp0 = fp;
7301 if (has_reduced_clock)
7302 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7303 else
7304 intel_crtc->config.dpll_hw_state.fp1 = fp;
7305
7306 pll = intel_get_shared_dpll(intel_crtc);
7307 if (pll == NULL) {
7308 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7309 pipe_name(intel_crtc->pipe));
7310 return -EINVAL;
7311 }
7312 } else
7313 intel_put_shared_dpll(intel_crtc);
7314
7315 if (is_lvds && has_reduced_clock && i915.powersave)
7316 intel_crtc->lowfreq_avail = true;
7317 else
7318 intel_crtc->lowfreq_avail = false;
7319
7320 return 0;
7321 }
7322
7323 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7324 struct intel_link_m_n *m_n)
7325 {
7326 struct drm_device *dev = crtc->base.dev;
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 enum pipe pipe = crtc->pipe;
7329
7330 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7331 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7332 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7333 & ~TU_SIZE_MASK;
7334 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7335 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7336 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7337 }
7338
7339 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7340 enum transcoder transcoder,
7341 struct intel_link_m_n *m_n,
7342 struct intel_link_m_n *m2_n2)
7343 {
7344 struct drm_device *dev = crtc->base.dev;
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 enum pipe pipe = crtc->pipe;
7347
7348 if (INTEL_INFO(dev)->gen >= 5) {
7349 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7350 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7351 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7352 & ~TU_SIZE_MASK;
7353 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7354 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7355 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7356 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7357 * gen < 8) and if DRRS is supported (to make sure the
7358 * registers are not unnecessarily read).
7359 */
7360 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7361 crtc->config.has_drrs) {
7362 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7363 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7364 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7365 & ~TU_SIZE_MASK;
7366 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7367 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7368 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7369 }
7370 } else {
7371 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7372 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7373 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7374 & ~TU_SIZE_MASK;
7375 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7376 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7377 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7378 }
7379 }
7380
7381 void intel_dp_get_m_n(struct intel_crtc *crtc,
7382 struct intel_crtc_config *pipe_config)
7383 {
7384 if (crtc->config.has_pch_encoder)
7385 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7386 else
7387 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7388 &pipe_config->dp_m_n,
7389 &pipe_config->dp_m2_n2);
7390 }
7391
7392 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7393 struct intel_crtc_config *pipe_config)
7394 {
7395 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7396 &pipe_config->fdi_m_n, NULL);
7397 }
7398
7399 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7400 struct intel_crtc_config *pipe_config)
7401 {
7402 struct drm_device *dev = crtc->base.dev;
7403 struct drm_i915_private *dev_priv = dev->dev_private;
7404 uint32_t tmp;
7405
7406 tmp = I915_READ(PF_CTL(crtc->pipe));
7407
7408 if (tmp & PF_ENABLE) {
7409 pipe_config->pch_pfit.enabled = true;
7410 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7411 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7412
7413 /* We currently do not free assignements of panel fitters on
7414 * ivb/hsw (since we don't use the higher upscaling modes which
7415 * differentiates them) so just WARN about this case for now. */
7416 if (IS_GEN7(dev)) {
7417 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7418 PF_PIPE_SEL_IVB(crtc->pipe));
7419 }
7420 }
7421 }
7422
7423 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7424 struct intel_plane_config *plane_config)
7425 {
7426 struct drm_device *dev = crtc->base.dev;
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 u32 val, base, offset;
7429 int pipe = crtc->pipe, plane = crtc->plane;
7430 int fourcc, pixel_format;
7431 int aligned_height;
7432
7433 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7434 if (!crtc->base.primary->fb) {
7435 DRM_DEBUG_KMS("failed to alloc fb\n");
7436 return;
7437 }
7438
7439 val = I915_READ(DSPCNTR(plane));
7440
7441 if (INTEL_INFO(dev)->gen >= 4)
7442 if (val & DISPPLANE_TILED)
7443 plane_config->tiled = true;
7444
7445 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7446 fourcc = intel_format_to_fourcc(pixel_format);
7447 crtc->base.primary->fb->pixel_format = fourcc;
7448 crtc->base.primary->fb->bits_per_pixel =
7449 drm_format_plane_cpp(fourcc, 0) * 8;
7450
7451 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7452 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7453 offset = I915_READ(DSPOFFSET(plane));
7454 } else {
7455 if (plane_config->tiled)
7456 offset = I915_READ(DSPTILEOFF(plane));
7457 else
7458 offset = I915_READ(DSPLINOFF(plane));
7459 }
7460 plane_config->base = base;
7461
7462 val = I915_READ(PIPESRC(pipe));
7463 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7464 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7465
7466 val = I915_READ(DSPSTRIDE(pipe));
7467 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7468
7469 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7470 plane_config->tiled);
7471
7472 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7473 aligned_height);
7474
7475 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7476 pipe, plane, crtc->base.primary->fb->width,
7477 crtc->base.primary->fb->height,
7478 crtc->base.primary->fb->bits_per_pixel, base,
7479 crtc->base.primary->fb->pitches[0],
7480 plane_config->size);
7481 }
7482
7483 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7484 struct intel_crtc_config *pipe_config)
7485 {
7486 struct drm_device *dev = crtc->base.dev;
7487 struct drm_i915_private *dev_priv = dev->dev_private;
7488 uint32_t tmp;
7489
7490 if (!intel_display_power_enabled(dev_priv,
7491 POWER_DOMAIN_PIPE(crtc->pipe)))
7492 return false;
7493
7494 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7495 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7496
7497 tmp = I915_READ(PIPECONF(crtc->pipe));
7498 if (!(tmp & PIPECONF_ENABLE))
7499 return false;
7500
7501 switch (tmp & PIPECONF_BPC_MASK) {
7502 case PIPECONF_6BPC:
7503 pipe_config->pipe_bpp = 18;
7504 break;
7505 case PIPECONF_8BPC:
7506 pipe_config->pipe_bpp = 24;
7507 break;
7508 case PIPECONF_10BPC:
7509 pipe_config->pipe_bpp = 30;
7510 break;
7511 case PIPECONF_12BPC:
7512 pipe_config->pipe_bpp = 36;
7513 break;
7514 default:
7515 break;
7516 }
7517
7518 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7519 pipe_config->limited_color_range = true;
7520
7521 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7522 struct intel_shared_dpll *pll;
7523
7524 pipe_config->has_pch_encoder = true;
7525
7526 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7527 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7528 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7529
7530 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7531
7532 if (HAS_PCH_IBX(dev_priv->dev)) {
7533 pipe_config->shared_dpll =
7534 (enum intel_dpll_id) crtc->pipe;
7535 } else {
7536 tmp = I915_READ(PCH_DPLL_SEL);
7537 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7538 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7539 else
7540 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7541 }
7542
7543 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7544
7545 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7546 &pipe_config->dpll_hw_state));
7547
7548 tmp = pipe_config->dpll_hw_state.dpll;
7549 pipe_config->pixel_multiplier =
7550 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7551 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7552
7553 ironlake_pch_clock_get(crtc, pipe_config);
7554 } else {
7555 pipe_config->pixel_multiplier = 1;
7556 }
7557
7558 intel_get_pipe_timings(crtc, pipe_config);
7559
7560 ironlake_get_pfit_config(crtc, pipe_config);
7561
7562 return true;
7563 }
7564
7565 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7566 {
7567 struct drm_device *dev = dev_priv->dev;
7568 struct intel_crtc *crtc;
7569
7570 for_each_intel_crtc(dev, crtc)
7571 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7572 pipe_name(crtc->pipe));
7573
7574 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7575 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7576 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7577 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7578 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7579 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7580 "CPU PWM1 enabled\n");
7581 if (IS_HASWELL(dev))
7582 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7583 "CPU PWM2 enabled\n");
7584 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7585 "PCH PWM1 enabled\n");
7586 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7587 "Utility pin enabled\n");
7588 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7589
7590 /*
7591 * In theory we can still leave IRQs enabled, as long as only the HPD
7592 * interrupts remain enabled. We used to check for that, but since it's
7593 * gen-specific and since we only disable LCPLL after we fully disable
7594 * the interrupts, the check below should be enough.
7595 */
7596 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7597 }
7598
7599 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7600 {
7601 struct drm_device *dev = dev_priv->dev;
7602
7603 if (IS_HASWELL(dev))
7604 return I915_READ(D_COMP_HSW);
7605 else
7606 return I915_READ(D_COMP_BDW);
7607 }
7608
7609 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7610 {
7611 struct drm_device *dev = dev_priv->dev;
7612
7613 if (IS_HASWELL(dev)) {
7614 mutex_lock(&dev_priv->rps.hw_lock);
7615 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7616 val))
7617 DRM_ERROR("Failed to write to D_COMP\n");
7618 mutex_unlock(&dev_priv->rps.hw_lock);
7619 } else {
7620 I915_WRITE(D_COMP_BDW, val);
7621 POSTING_READ(D_COMP_BDW);
7622 }
7623 }
7624
7625 /*
7626 * This function implements pieces of two sequences from BSpec:
7627 * - Sequence for display software to disable LCPLL
7628 * - Sequence for display software to allow package C8+
7629 * The steps implemented here are just the steps that actually touch the LCPLL
7630 * register. Callers should take care of disabling all the display engine
7631 * functions, doing the mode unset, fixing interrupts, etc.
7632 */
7633 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7634 bool switch_to_fclk, bool allow_power_down)
7635 {
7636 uint32_t val;
7637
7638 assert_can_disable_lcpll(dev_priv);
7639
7640 val = I915_READ(LCPLL_CTL);
7641
7642 if (switch_to_fclk) {
7643 val |= LCPLL_CD_SOURCE_FCLK;
7644 I915_WRITE(LCPLL_CTL, val);
7645
7646 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7647 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7648 DRM_ERROR("Switching to FCLK failed\n");
7649
7650 val = I915_READ(LCPLL_CTL);
7651 }
7652
7653 val |= LCPLL_PLL_DISABLE;
7654 I915_WRITE(LCPLL_CTL, val);
7655 POSTING_READ(LCPLL_CTL);
7656
7657 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7658 DRM_ERROR("LCPLL still locked\n");
7659
7660 val = hsw_read_dcomp(dev_priv);
7661 val |= D_COMP_COMP_DISABLE;
7662 hsw_write_dcomp(dev_priv, val);
7663 ndelay(100);
7664
7665 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7666 1))
7667 DRM_ERROR("D_COMP RCOMP still in progress\n");
7668
7669 if (allow_power_down) {
7670 val = I915_READ(LCPLL_CTL);
7671 val |= LCPLL_POWER_DOWN_ALLOW;
7672 I915_WRITE(LCPLL_CTL, val);
7673 POSTING_READ(LCPLL_CTL);
7674 }
7675 }
7676
7677 /*
7678 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7679 * source.
7680 */
7681 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7682 {
7683 uint32_t val;
7684 unsigned long irqflags;
7685
7686 val = I915_READ(LCPLL_CTL);
7687
7688 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7689 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7690 return;
7691
7692 /*
7693 * Make sure we're not on PC8 state before disabling PC8, otherwise
7694 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7695 *
7696 * The other problem is that hsw_restore_lcpll() is called as part of
7697 * the runtime PM resume sequence, so we can't just call
7698 * gen6_gt_force_wake_get() because that function calls
7699 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7700 * while we are on the resume sequence. So to solve this problem we have
7701 * to call special forcewake code that doesn't touch runtime PM and
7702 * doesn't enable the forcewake delayed work.
7703 */
7704 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7705 if (dev_priv->uncore.forcewake_count++ == 0)
7706 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7707 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7708
7709 if (val & LCPLL_POWER_DOWN_ALLOW) {
7710 val &= ~LCPLL_POWER_DOWN_ALLOW;
7711 I915_WRITE(LCPLL_CTL, val);
7712 POSTING_READ(LCPLL_CTL);
7713 }
7714
7715 val = hsw_read_dcomp(dev_priv);
7716 val |= D_COMP_COMP_FORCE;
7717 val &= ~D_COMP_COMP_DISABLE;
7718 hsw_write_dcomp(dev_priv, val);
7719
7720 val = I915_READ(LCPLL_CTL);
7721 val &= ~LCPLL_PLL_DISABLE;
7722 I915_WRITE(LCPLL_CTL, val);
7723
7724 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7725 DRM_ERROR("LCPLL not locked yet\n");
7726
7727 if (val & LCPLL_CD_SOURCE_FCLK) {
7728 val = I915_READ(LCPLL_CTL);
7729 val &= ~LCPLL_CD_SOURCE_FCLK;
7730 I915_WRITE(LCPLL_CTL, val);
7731
7732 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7733 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7734 DRM_ERROR("Switching back to LCPLL failed\n");
7735 }
7736
7737 /* See the big comment above. */
7738 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7739 if (--dev_priv->uncore.forcewake_count == 0)
7740 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7741 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7742 }
7743
7744 /*
7745 * Package states C8 and deeper are really deep PC states that can only be
7746 * reached when all the devices on the system allow it, so even if the graphics
7747 * device allows PC8+, it doesn't mean the system will actually get to these
7748 * states. Our driver only allows PC8+ when going into runtime PM.
7749 *
7750 * The requirements for PC8+ are that all the outputs are disabled, the power
7751 * well is disabled and most interrupts are disabled, and these are also
7752 * requirements for runtime PM. When these conditions are met, we manually do
7753 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7754 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7755 * hang the machine.
7756 *
7757 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7758 * the state of some registers, so when we come back from PC8+ we need to
7759 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7760 * need to take care of the registers kept by RC6. Notice that this happens even
7761 * if we don't put the device in PCI D3 state (which is what currently happens
7762 * because of the runtime PM support).
7763 *
7764 * For more, read "Display Sequences for Package C8" on the hardware
7765 * documentation.
7766 */
7767 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7768 {
7769 struct drm_device *dev = dev_priv->dev;
7770 uint32_t val;
7771
7772 DRM_DEBUG_KMS("Enabling package C8+\n");
7773
7774 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7775 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7776 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7777 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7778 }
7779
7780 lpt_disable_clkout_dp(dev);
7781 hsw_disable_lcpll(dev_priv, true, true);
7782 }
7783
7784 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7785 {
7786 struct drm_device *dev = dev_priv->dev;
7787 uint32_t val;
7788
7789 DRM_DEBUG_KMS("Disabling package C8+\n");
7790
7791 hsw_restore_lcpll(dev_priv);
7792 lpt_init_pch_refclk(dev);
7793
7794 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7795 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7796 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7797 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7798 }
7799
7800 intel_prepare_ddi(dev);
7801 }
7802
7803 static void snb_modeset_global_resources(struct drm_device *dev)
7804 {
7805 modeset_update_crtc_power_domains(dev);
7806 }
7807
7808 static void haswell_modeset_global_resources(struct drm_device *dev)
7809 {
7810 modeset_update_crtc_power_domains(dev);
7811 }
7812
7813 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7814 int x, int y,
7815 struct drm_framebuffer *fb)
7816 {
7817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7818
7819 if (!intel_ddi_pll_select(intel_crtc))
7820 return -EINVAL;
7821
7822 intel_crtc->lowfreq_avail = false;
7823
7824 return 0;
7825 }
7826
7827 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7828 enum port port,
7829 struct intel_crtc_config *pipe_config)
7830 {
7831 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7832
7833 switch (pipe_config->ddi_pll_sel) {
7834 case PORT_CLK_SEL_WRPLL1:
7835 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7836 break;
7837 case PORT_CLK_SEL_WRPLL2:
7838 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7839 break;
7840 }
7841 }
7842
7843 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7844 struct intel_crtc_config *pipe_config)
7845 {
7846 struct drm_device *dev = crtc->base.dev;
7847 struct drm_i915_private *dev_priv = dev->dev_private;
7848 struct intel_shared_dpll *pll;
7849 enum port port;
7850 uint32_t tmp;
7851
7852 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7853
7854 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7855
7856 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7857
7858 if (pipe_config->shared_dpll >= 0) {
7859 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7860
7861 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7862 &pipe_config->dpll_hw_state));
7863 }
7864
7865 /*
7866 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7867 * DDI E. So just check whether this pipe is wired to DDI E and whether
7868 * the PCH transcoder is on.
7869 */
7870 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7871 pipe_config->has_pch_encoder = true;
7872
7873 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7874 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7875 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7876
7877 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7878 }
7879 }
7880
7881 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7882 struct intel_crtc_config *pipe_config)
7883 {
7884 struct drm_device *dev = crtc->base.dev;
7885 struct drm_i915_private *dev_priv = dev->dev_private;
7886 enum intel_display_power_domain pfit_domain;
7887 uint32_t tmp;
7888
7889 if (!intel_display_power_enabled(dev_priv,
7890 POWER_DOMAIN_PIPE(crtc->pipe)))
7891 return false;
7892
7893 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7894 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7895
7896 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7897 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7898 enum pipe trans_edp_pipe;
7899 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7900 default:
7901 WARN(1, "unknown pipe linked to edp transcoder\n");
7902 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7903 case TRANS_DDI_EDP_INPUT_A_ON:
7904 trans_edp_pipe = PIPE_A;
7905 break;
7906 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7907 trans_edp_pipe = PIPE_B;
7908 break;
7909 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7910 trans_edp_pipe = PIPE_C;
7911 break;
7912 }
7913
7914 if (trans_edp_pipe == crtc->pipe)
7915 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7916 }
7917
7918 if (!intel_display_power_enabled(dev_priv,
7919 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7920 return false;
7921
7922 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7923 if (!(tmp & PIPECONF_ENABLE))
7924 return false;
7925
7926 haswell_get_ddi_port_state(crtc, pipe_config);
7927
7928 intel_get_pipe_timings(crtc, pipe_config);
7929
7930 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7931 if (intel_display_power_enabled(dev_priv, pfit_domain))
7932 ironlake_get_pfit_config(crtc, pipe_config);
7933
7934 if (IS_HASWELL(dev))
7935 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7936 (I915_READ(IPS_CTL) & IPS_ENABLE);
7937
7938 pipe_config->pixel_multiplier = 1;
7939
7940 return true;
7941 }
7942
7943 static struct {
7944 int clock;
7945 u32 config;
7946 } hdmi_audio_clock[] = {
7947 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7948 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7949 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7950 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7951 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7952 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7953 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7954 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7955 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7956 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7957 };
7958
7959 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7960 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7961 {
7962 int i;
7963
7964 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7965 if (mode->clock == hdmi_audio_clock[i].clock)
7966 break;
7967 }
7968
7969 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7970 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7971 i = 1;
7972 }
7973
7974 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7975 hdmi_audio_clock[i].clock,
7976 hdmi_audio_clock[i].config);
7977
7978 return hdmi_audio_clock[i].config;
7979 }
7980
7981 static bool intel_eld_uptodate(struct drm_connector *connector,
7982 int reg_eldv, uint32_t bits_eldv,
7983 int reg_elda, uint32_t bits_elda,
7984 int reg_edid)
7985 {
7986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7987 uint8_t *eld = connector->eld;
7988 uint32_t i;
7989
7990 i = I915_READ(reg_eldv);
7991 i &= bits_eldv;
7992
7993 if (!eld[0])
7994 return !i;
7995
7996 if (!i)
7997 return false;
7998
7999 i = I915_READ(reg_elda);
8000 i &= ~bits_elda;
8001 I915_WRITE(reg_elda, i);
8002
8003 for (i = 0; i < eld[2]; i++)
8004 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
8005 return false;
8006
8007 return true;
8008 }
8009
8010 static void g4x_write_eld(struct drm_connector *connector,
8011 struct drm_crtc *crtc,
8012 struct drm_display_mode *mode)
8013 {
8014 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8015 uint8_t *eld = connector->eld;
8016 uint32_t eldv;
8017 uint32_t len;
8018 uint32_t i;
8019
8020 i = I915_READ(G4X_AUD_VID_DID);
8021
8022 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
8023 eldv = G4X_ELDV_DEVCL_DEVBLC;
8024 else
8025 eldv = G4X_ELDV_DEVCTG;
8026
8027 if (intel_eld_uptodate(connector,
8028 G4X_AUD_CNTL_ST, eldv,
8029 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
8030 G4X_HDMIW_HDMIEDID))
8031 return;
8032
8033 i = I915_READ(G4X_AUD_CNTL_ST);
8034 i &= ~(eldv | G4X_ELD_ADDR);
8035 len = (i >> 9) & 0x1f; /* ELD buffer size */
8036 I915_WRITE(G4X_AUD_CNTL_ST, i);
8037
8038 if (!eld[0])
8039 return;
8040
8041 len = min_t(uint8_t, eld[2], len);
8042 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8043 for (i = 0; i < len; i++)
8044 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8045
8046 i = I915_READ(G4X_AUD_CNTL_ST);
8047 i |= eldv;
8048 I915_WRITE(G4X_AUD_CNTL_ST, i);
8049 }
8050
8051 static void haswell_write_eld(struct drm_connector *connector,
8052 struct drm_crtc *crtc,
8053 struct drm_display_mode *mode)
8054 {
8055 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8056 uint8_t *eld = connector->eld;
8057 uint32_t eldv;
8058 uint32_t i;
8059 int len;
8060 int pipe = to_intel_crtc(crtc)->pipe;
8061 int tmp;
8062
8063 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8064 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8065 int aud_config = HSW_AUD_CFG(pipe);
8066 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8067
8068 /* Audio output enable */
8069 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8070 tmp = I915_READ(aud_cntrl_st2);
8071 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8072 I915_WRITE(aud_cntrl_st2, tmp);
8073 POSTING_READ(aud_cntrl_st2);
8074
8075 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8076
8077 /* Set ELD valid state */
8078 tmp = I915_READ(aud_cntrl_st2);
8079 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8080 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8081 I915_WRITE(aud_cntrl_st2, tmp);
8082 tmp = I915_READ(aud_cntrl_st2);
8083 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8084
8085 /* Enable HDMI mode */
8086 tmp = I915_READ(aud_config);
8087 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8088 /* clear N_programing_enable and N_value_index */
8089 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8090 I915_WRITE(aud_config, tmp);
8091
8092 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8093
8094 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8095
8096 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8097 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8098 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8099 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8100 } else {
8101 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8102 }
8103
8104 if (intel_eld_uptodate(connector,
8105 aud_cntrl_st2, eldv,
8106 aud_cntl_st, IBX_ELD_ADDRESS,
8107 hdmiw_hdmiedid))
8108 return;
8109
8110 i = I915_READ(aud_cntrl_st2);
8111 i &= ~eldv;
8112 I915_WRITE(aud_cntrl_st2, i);
8113
8114 if (!eld[0])
8115 return;
8116
8117 i = I915_READ(aud_cntl_st);
8118 i &= ~IBX_ELD_ADDRESS;
8119 I915_WRITE(aud_cntl_st, i);
8120 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8121 DRM_DEBUG_DRIVER("port num:%d\n", i);
8122
8123 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8124 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8125 for (i = 0; i < len; i++)
8126 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8127
8128 i = I915_READ(aud_cntrl_st2);
8129 i |= eldv;
8130 I915_WRITE(aud_cntrl_st2, i);
8131
8132 }
8133
8134 static void ironlake_write_eld(struct drm_connector *connector,
8135 struct drm_crtc *crtc,
8136 struct drm_display_mode *mode)
8137 {
8138 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8139 uint8_t *eld = connector->eld;
8140 uint32_t eldv;
8141 uint32_t i;
8142 int len;
8143 int hdmiw_hdmiedid;
8144 int aud_config;
8145 int aud_cntl_st;
8146 int aud_cntrl_st2;
8147 int pipe = to_intel_crtc(crtc)->pipe;
8148
8149 if (HAS_PCH_IBX(connector->dev)) {
8150 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8151 aud_config = IBX_AUD_CFG(pipe);
8152 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8153 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8154 } else if (IS_VALLEYVIEW(connector->dev)) {
8155 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8156 aud_config = VLV_AUD_CFG(pipe);
8157 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8158 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8159 } else {
8160 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8161 aud_config = CPT_AUD_CFG(pipe);
8162 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8163 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8164 }
8165
8166 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8167
8168 if (IS_VALLEYVIEW(connector->dev)) {
8169 struct intel_encoder *intel_encoder;
8170 struct intel_digital_port *intel_dig_port;
8171
8172 intel_encoder = intel_attached_encoder(connector);
8173 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8174 i = intel_dig_port->port;
8175 } else {
8176 i = I915_READ(aud_cntl_st);
8177 i = (i >> 29) & DIP_PORT_SEL_MASK;
8178 /* DIP_Port_Select, 0x1 = PortB */
8179 }
8180
8181 if (!i) {
8182 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8183 /* operate blindly on all ports */
8184 eldv = IBX_ELD_VALIDB;
8185 eldv |= IBX_ELD_VALIDB << 4;
8186 eldv |= IBX_ELD_VALIDB << 8;
8187 } else {
8188 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8189 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8190 }
8191
8192 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8193 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8194 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8195 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8196 } else {
8197 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8198 }
8199
8200 if (intel_eld_uptodate(connector,
8201 aud_cntrl_st2, eldv,
8202 aud_cntl_st, IBX_ELD_ADDRESS,
8203 hdmiw_hdmiedid))
8204 return;
8205
8206 i = I915_READ(aud_cntrl_st2);
8207 i &= ~eldv;
8208 I915_WRITE(aud_cntrl_st2, i);
8209
8210 if (!eld[0])
8211 return;
8212
8213 i = I915_READ(aud_cntl_st);
8214 i &= ~IBX_ELD_ADDRESS;
8215 I915_WRITE(aud_cntl_st, i);
8216
8217 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8218 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8219 for (i = 0; i < len; i++)
8220 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8221
8222 i = I915_READ(aud_cntrl_st2);
8223 i |= eldv;
8224 I915_WRITE(aud_cntrl_st2, i);
8225 }
8226
8227 void intel_write_eld(struct drm_encoder *encoder,
8228 struct drm_display_mode *mode)
8229 {
8230 struct drm_crtc *crtc = encoder->crtc;
8231 struct drm_connector *connector;
8232 struct drm_device *dev = encoder->dev;
8233 struct drm_i915_private *dev_priv = dev->dev_private;
8234
8235 connector = drm_select_eld(encoder, mode);
8236 if (!connector)
8237 return;
8238
8239 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8240 connector->base.id,
8241 connector->name,
8242 connector->encoder->base.id,
8243 connector->encoder->name);
8244
8245 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8246
8247 if (dev_priv->display.write_eld)
8248 dev_priv->display.write_eld(connector, crtc, mode);
8249 }
8250
8251 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8252 {
8253 struct drm_device *dev = crtc->dev;
8254 struct drm_i915_private *dev_priv = dev->dev_private;
8255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8256 uint32_t cntl = 0, size = 0;
8257
8258 if (base) {
8259 unsigned int width = intel_crtc->cursor_width;
8260 unsigned int height = intel_crtc->cursor_height;
8261 unsigned int stride = roundup_pow_of_two(width) * 4;
8262
8263 switch (stride) {
8264 default:
8265 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8266 width, stride);
8267 stride = 256;
8268 /* fallthrough */
8269 case 256:
8270 case 512:
8271 case 1024:
8272 case 2048:
8273 break;
8274 }
8275
8276 cntl |= CURSOR_ENABLE |
8277 CURSOR_GAMMA_ENABLE |
8278 CURSOR_FORMAT_ARGB |
8279 CURSOR_STRIDE(stride);
8280
8281 size = (height << 12) | width;
8282 }
8283
8284 if (intel_crtc->cursor_cntl != 0 &&
8285 (intel_crtc->cursor_base != base ||
8286 intel_crtc->cursor_size != size ||
8287 intel_crtc->cursor_cntl != cntl)) {
8288 /* On these chipsets we can only modify the base/size/stride
8289 * whilst the cursor is disabled.
8290 */
8291 I915_WRITE(_CURACNTR, 0);
8292 POSTING_READ(_CURACNTR);
8293 intel_crtc->cursor_cntl = 0;
8294 }
8295
8296 if (intel_crtc->cursor_base != base)
8297 I915_WRITE(_CURABASE, base);
8298
8299 if (intel_crtc->cursor_size != size) {
8300 I915_WRITE(CURSIZE, size);
8301 intel_crtc->cursor_size = size;
8302 }
8303
8304 if (intel_crtc->cursor_cntl != cntl) {
8305 I915_WRITE(_CURACNTR, cntl);
8306 POSTING_READ(_CURACNTR);
8307 intel_crtc->cursor_cntl = cntl;
8308 }
8309 }
8310
8311 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8312 {
8313 struct drm_device *dev = crtc->dev;
8314 struct drm_i915_private *dev_priv = dev->dev_private;
8315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8316 int pipe = intel_crtc->pipe;
8317 uint32_t cntl;
8318
8319 cntl = 0;
8320 if (base) {
8321 cntl = MCURSOR_GAMMA_ENABLE;
8322 switch (intel_crtc->cursor_width) {
8323 case 64:
8324 cntl |= CURSOR_MODE_64_ARGB_AX;
8325 break;
8326 case 128:
8327 cntl |= CURSOR_MODE_128_ARGB_AX;
8328 break;
8329 case 256:
8330 cntl |= CURSOR_MODE_256_ARGB_AX;
8331 break;
8332 default:
8333 WARN_ON(1);
8334 return;
8335 }
8336 cntl |= pipe << 28; /* Connect to correct pipe */
8337 }
8338 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8339 cntl |= CURSOR_PIPE_CSC_ENABLE;
8340
8341 if (intel_crtc->cursor_cntl != cntl) {
8342 I915_WRITE(CURCNTR(pipe), cntl);
8343 POSTING_READ(CURCNTR(pipe));
8344 intel_crtc->cursor_cntl = cntl;
8345 }
8346
8347 /* and commit changes on next vblank */
8348 I915_WRITE(CURBASE(pipe), base);
8349 POSTING_READ(CURBASE(pipe));
8350 }
8351
8352 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8353 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8354 bool on)
8355 {
8356 struct drm_device *dev = crtc->dev;
8357 struct drm_i915_private *dev_priv = dev->dev_private;
8358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8359 int pipe = intel_crtc->pipe;
8360 int x = crtc->cursor_x;
8361 int y = crtc->cursor_y;
8362 u32 base = 0, pos = 0;
8363
8364 if (on)
8365 base = intel_crtc->cursor_addr;
8366
8367 if (x >= intel_crtc->config.pipe_src_w)
8368 base = 0;
8369
8370 if (y >= intel_crtc->config.pipe_src_h)
8371 base = 0;
8372
8373 if (x < 0) {
8374 if (x + intel_crtc->cursor_width <= 0)
8375 base = 0;
8376
8377 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8378 x = -x;
8379 }
8380 pos |= x << CURSOR_X_SHIFT;
8381
8382 if (y < 0) {
8383 if (y + intel_crtc->cursor_height <= 0)
8384 base = 0;
8385
8386 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8387 y = -y;
8388 }
8389 pos |= y << CURSOR_Y_SHIFT;
8390
8391 if (base == 0 && intel_crtc->cursor_base == 0)
8392 return;
8393
8394 I915_WRITE(CURPOS(pipe), pos);
8395
8396 if (IS_845G(dev) || IS_I865G(dev))
8397 i845_update_cursor(crtc, base);
8398 else
8399 i9xx_update_cursor(crtc, base);
8400 intel_crtc->cursor_base = base;
8401 }
8402
8403 static bool cursor_size_ok(struct drm_device *dev,
8404 uint32_t width, uint32_t height)
8405 {
8406 if (width == 0 || height == 0)
8407 return false;
8408
8409 /*
8410 * 845g/865g are special in that they are only limited by
8411 * the width of their cursors, the height is arbitrary up to
8412 * the precision of the register. Everything else requires
8413 * square cursors, limited to a few power-of-two sizes.
8414 */
8415 if (IS_845G(dev) || IS_I865G(dev)) {
8416 if ((width & 63) != 0)
8417 return false;
8418
8419 if (width > (IS_845G(dev) ? 64 : 512))
8420 return false;
8421
8422 if (height > 1023)
8423 return false;
8424 } else {
8425 switch (width | height) {
8426 case 256:
8427 case 128:
8428 if (IS_GEN2(dev))
8429 return false;
8430 case 64:
8431 break;
8432 default:
8433 return false;
8434 }
8435 }
8436
8437 return true;
8438 }
8439
8440 /*
8441 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8442 *
8443 * Note that the object's reference will be consumed if the update fails. If
8444 * the update succeeds, the reference of the old object (if any) will be
8445 * consumed.
8446 */
8447 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8448 struct drm_i915_gem_object *obj,
8449 uint32_t width, uint32_t height)
8450 {
8451 struct drm_device *dev = crtc->dev;
8452 struct drm_i915_private *dev_priv = dev->dev_private;
8453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8454 enum pipe pipe = intel_crtc->pipe;
8455 unsigned old_width, stride;
8456 uint32_t addr;
8457 int ret;
8458
8459 /* if we want to turn off the cursor ignore width and height */
8460 if (!obj) {
8461 DRM_DEBUG_KMS("cursor off\n");
8462 addr = 0;
8463 mutex_lock(&dev->struct_mutex);
8464 goto finish;
8465 }
8466
8467 /* Check for which cursor types we support */
8468 if (!cursor_size_ok(dev, width, height)) {
8469 DRM_DEBUG("Cursor dimension not supported\n");
8470 return -EINVAL;
8471 }
8472
8473 stride = roundup_pow_of_two(width) * 4;
8474 if (obj->base.size < stride * height) {
8475 DRM_DEBUG_KMS("buffer is too small\n");
8476 ret = -ENOMEM;
8477 goto fail;
8478 }
8479
8480 /* we only need to pin inside GTT if cursor is non-phy */
8481 mutex_lock(&dev->struct_mutex);
8482 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8483 unsigned alignment;
8484
8485 if (obj->tiling_mode) {
8486 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8487 ret = -EINVAL;
8488 goto fail_locked;
8489 }
8490
8491 /*
8492 * Global gtt pte registers are special registers which actually
8493 * forward writes to a chunk of system memory. Which means that
8494 * there is no risk that the register values disappear as soon
8495 * as we call intel_runtime_pm_put(), so it is correct to wrap
8496 * only the pin/unpin/fence and not more.
8497 */
8498 intel_runtime_pm_get(dev_priv);
8499
8500 /* Note that the w/a also requires 2 PTE of padding following
8501 * the bo. We currently fill all unused PTE with the shadow
8502 * page and so we should always have valid PTE following the
8503 * cursor preventing the VT-d warning.
8504 */
8505 alignment = 0;
8506 if (need_vtd_wa(dev))
8507 alignment = 64*1024;
8508
8509 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8510 if (ret) {
8511 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8512 intel_runtime_pm_put(dev_priv);
8513 goto fail_locked;
8514 }
8515
8516 ret = i915_gem_object_put_fence(obj);
8517 if (ret) {
8518 DRM_DEBUG_KMS("failed to release fence for cursor");
8519 intel_runtime_pm_put(dev_priv);
8520 goto fail_unpin;
8521 }
8522
8523 addr = i915_gem_obj_ggtt_offset(obj);
8524
8525 intel_runtime_pm_put(dev_priv);
8526 } else {
8527 int align = IS_I830(dev) ? 16 * 1024 : 256;
8528 ret = i915_gem_object_attach_phys(obj, align);
8529 if (ret) {
8530 DRM_DEBUG_KMS("failed to attach phys object\n");
8531 goto fail_locked;
8532 }
8533 addr = obj->phys_handle->busaddr;
8534 }
8535
8536 finish:
8537 if (intel_crtc->cursor_bo) {
8538 if (!INTEL_INFO(dev)->cursor_needs_physical)
8539 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8540 }
8541
8542 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8543 INTEL_FRONTBUFFER_CURSOR(pipe));
8544 mutex_unlock(&dev->struct_mutex);
8545
8546 old_width = intel_crtc->cursor_width;
8547
8548 intel_crtc->cursor_addr = addr;
8549 intel_crtc->cursor_bo = obj;
8550 intel_crtc->cursor_width = width;
8551 intel_crtc->cursor_height = height;
8552
8553 if (intel_crtc->active) {
8554 if (old_width != width)
8555 intel_update_watermarks(crtc);
8556 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8557 }
8558
8559 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8560
8561 return 0;
8562 fail_unpin:
8563 i915_gem_object_unpin_from_display_plane(obj);
8564 fail_locked:
8565 mutex_unlock(&dev->struct_mutex);
8566 fail:
8567 drm_gem_object_unreference_unlocked(&obj->base);
8568 return ret;
8569 }
8570
8571 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8572 u16 *blue, uint32_t start, uint32_t size)
8573 {
8574 int end = (start + size > 256) ? 256 : start + size, i;
8575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8576
8577 for (i = start; i < end; i++) {
8578 intel_crtc->lut_r[i] = red[i] >> 8;
8579 intel_crtc->lut_g[i] = green[i] >> 8;
8580 intel_crtc->lut_b[i] = blue[i] >> 8;
8581 }
8582
8583 intel_crtc_load_lut(crtc);
8584 }
8585
8586 /* VESA 640x480x72Hz mode to set on the pipe */
8587 static struct drm_display_mode load_detect_mode = {
8588 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8589 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8590 };
8591
8592 struct drm_framebuffer *
8593 __intel_framebuffer_create(struct drm_device *dev,
8594 struct drm_mode_fb_cmd2 *mode_cmd,
8595 struct drm_i915_gem_object *obj)
8596 {
8597 struct intel_framebuffer *intel_fb;
8598 int ret;
8599
8600 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8601 if (!intel_fb) {
8602 drm_gem_object_unreference_unlocked(&obj->base);
8603 return ERR_PTR(-ENOMEM);
8604 }
8605
8606 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8607 if (ret)
8608 goto err;
8609
8610 return &intel_fb->base;
8611 err:
8612 drm_gem_object_unreference_unlocked(&obj->base);
8613 kfree(intel_fb);
8614
8615 return ERR_PTR(ret);
8616 }
8617
8618 static struct drm_framebuffer *
8619 intel_framebuffer_create(struct drm_device *dev,
8620 struct drm_mode_fb_cmd2 *mode_cmd,
8621 struct drm_i915_gem_object *obj)
8622 {
8623 struct drm_framebuffer *fb;
8624 int ret;
8625
8626 ret = i915_mutex_lock_interruptible(dev);
8627 if (ret)
8628 return ERR_PTR(ret);
8629 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8630 mutex_unlock(&dev->struct_mutex);
8631
8632 return fb;
8633 }
8634
8635 static u32
8636 intel_framebuffer_pitch_for_width(int width, int bpp)
8637 {
8638 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8639 return ALIGN(pitch, 64);
8640 }
8641
8642 static u32
8643 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8644 {
8645 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8646 return PAGE_ALIGN(pitch * mode->vdisplay);
8647 }
8648
8649 static struct drm_framebuffer *
8650 intel_framebuffer_create_for_mode(struct drm_device *dev,
8651 struct drm_display_mode *mode,
8652 int depth, int bpp)
8653 {
8654 struct drm_i915_gem_object *obj;
8655 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8656
8657 obj = i915_gem_alloc_object(dev,
8658 intel_framebuffer_size_for_mode(mode, bpp));
8659 if (obj == NULL)
8660 return ERR_PTR(-ENOMEM);
8661
8662 mode_cmd.width = mode->hdisplay;
8663 mode_cmd.height = mode->vdisplay;
8664 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8665 bpp);
8666 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8667
8668 return intel_framebuffer_create(dev, &mode_cmd, obj);
8669 }
8670
8671 static struct drm_framebuffer *
8672 mode_fits_in_fbdev(struct drm_device *dev,
8673 struct drm_display_mode *mode)
8674 {
8675 #ifdef CONFIG_DRM_I915_FBDEV
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 struct drm_i915_gem_object *obj;
8678 struct drm_framebuffer *fb;
8679
8680 if (!dev_priv->fbdev)
8681 return NULL;
8682
8683 if (!dev_priv->fbdev->fb)
8684 return NULL;
8685
8686 obj = dev_priv->fbdev->fb->obj;
8687 BUG_ON(!obj);
8688
8689 fb = &dev_priv->fbdev->fb->base;
8690 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8691 fb->bits_per_pixel))
8692 return NULL;
8693
8694 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8695 return NULL;
8696
8697 return fb;
8698 #else
8699 return NULL;
8700 #endif
8701 }
8702
8703 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8704 struct drm_display_mode *mode,
8705 struct intel_load_detect_pipe *old,
8706 struct drm_modeset_acquire_ctx *ctx)
8707 {
8708 struct intel_crtc *intel_crtc;
8709 struct intel_encoder *intel_encoder =
8710 intel_attached_encoder(connector);
8711 struct drm_crtc *possible_crtc;
8712 struct drm_encoder *encoder = &intel_encoder->base;
8713 struct drm_crtc *crtc = NULL;
8714 struct drm_device *dev = encoder->dev;
8715 struct drm_framebuffer *fb;
8716 struct drm_mode_config *config = &dev->mode_config;
8717 int ret, i = -1;
8718
8719 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8720 connector->base.id, connector->name,
8721 encoder->base.id, encoder->name);
8722
8723 retry:
8724 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8725 if (ret)
8726 goto fail_unlock;
8727
8728 /*
8729 * Algorithm gets a little messy:
8730 *
8731 * - if the connector already has an assigned crtc, use it (but make
8732 * sure it's on first)
8733 *
8734 * - try to find the first unused crtc that can drive this connector,
8735 * and use that if we find one
8736 */
8737
8738 /* See if we already have a CRTC for this connector */
8739 if (encoder->crtc) {
8740 crtc = encoder->crtc;
8741
8742 ret = drm_modeset_lock(&crtc->mutex, ctx);
8743 if (ret)
8744 goto fail_unlock;
8745
8746 old->dpms_mode = connector->dpms;
8747 old->load_detect_temp = false;
8748
8749 /* Make sure the crtc and connector are running */
8750 if (connector->dpms != DRM_MODE_DPMS_ON)
8751 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8752
8753 return true;
8754 }
8755
8756 /* Find an unused one (if possible) */
8757 for_each_crtc(dev, possible_crtc) {
8758 i++;
8759 if (!(encoder->possible_crtcs & (1 << i)))
8760 continue;
8761 if (possible_crtc->enabled)
8762 continue;
8763 /* This can occur when applying the pipe A quirk on resume. */
8764 if (to_intel_crtc(possible_crtc)->new_enabled)
8765 continue;
8766
8767 crtc = possible_crtc;
8768 break;
8769 }
8770
8771 /*
8772 * If we didn't find an unused CRTC, don't use any.
8773 */
8774 if (!crtc) {
8775 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8776 goto fail_unlock;
8777 }
8778
8779 ret = drm_modeset_lock(&crtc->mutex, ctx);
8780 if (ret)
8781 goto fail_unlock;
8782 intel_encoder->new_crtc = to_intel_crtc(crtc);
8783 to_intel_connector(connector)->new_encoder = intel_encoder;
8784
8785 intel_crtc = to_intel_crtc(crtc);
8786 intel_crtc->new_enabled = true;
8787 intel_crtc->new_config = &intel_crtc->config;
8788 old->dpms_mode = connector->dpms;
8789 old->load_detect_temp = true;
8790 old->release_fb = NULL;
8791
8792 if (!mode)
8793 mode = &load_detect_mode;
8794
8795 /* We need a framebuffer large enough to accommodate all accesses
8796 * that the plane may generate whilst we perform load detection.
8797 * We can not rely on the fbcon either being present (we get called
8798 * during its initialisation to detect all boot displays, or it may
8799 * not even exist) or that it is large enough to satisfy the
8800 * requested mode.
8801 */
8802 fb = mode_fits_in_fbdev(dev, mode);
8803 if (fb == NULL) {
8804 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8805 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8806 old->release_fb = fb;
8807 } else
8808 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8809 if (IS_ERR(fb)) {
8810 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8811 goto fail;
8812 }
8813
8814 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8815 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8816 if (old->release_fb)
8817 old->release_fb->funcs->destroy(old->release_fb);
8818 goto fail;
8819 }
8820
8821 /* let the connector get through one full cycle before testing */
8822 intel_wait_for_vblank(dev, intel_crtc->pipe);
8823 return true;
8824
8825 fail:
8826 intel_crtc->new_enabled = crtc->enabled;
8827 if (intel_crtc->new_enabled)
8828 intel_crtc->new_config = &intel_crtc->config;
8829 else
8830 intel_crtc->new_config = NULL;
8831 fail_unlock:
8832 if (ret == -EDEADLK) {
8833 drm_modeset_backoff(ctx);
8834 goto retry;
8835 }
8836
8837 return false;
8838 }
8839
8840 void intel_release_load_detect_pipe(struct drm_connector *connector,
8841 struct intel_load_detect_pipe *old)
8842 {
8843 struct intel_encoder *intel_encoder =
8844 intel_attached_encoder(connector);
8845 struct drm_encoder *encoder = &intel_encoder->base;
8846 struct drm_crtc *crtc = encoder->crtc;
8847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8848
8849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8850 connector->base.id, connector->name,
8851 encoder->base.id, encoder->name);
8852
8853 if (old->load_detect_temp) {
8854 to_intel_connector(connector)->new_encoder = NULL;
8855 intel_encoder->new_crtc = NULL;
8856 intel_crtc->new_enabled = false;
8857 intel_crtc->new_config = NULL;
8858 intel_set_mode(crtc, NULL, 0, 0, NULL);
8859
8860 if (old->release_fb) {
8861 drm_framebuffer_unregister_private(old->release_fb);
8862 drm_framebuffer_unreference(old->release_fb);
8863 }
8864
8865 return;
8866 }
8867
8868 /* Switch crtc and encoder back off if necessary */
8869 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8870 connector->funcs->dpms(connector, old->dpms_mode);
8871 }
8872
8873 static int i9xx_pll_refclk(struct drm_device *dev,
8874 const struct intel_crtc_config *pipe_config)
8875 {
8876 struct drm_i915_private *dev_priv = dev->dev_private;
8877 u32 dpll = pipe_config->dpll_hw_state.dpll;
8878
8879 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8880 return dev_priv->vbt.lvds_ssc_freq;
8881 else if (HAS_PCH_SPLIT(dev))
8882 return 120000;
8883 else if (!IS_GEN2(dev))
8884 return 96000;
8885 else
8886 return 48000;
8887 }
8888
8889 /* Returns the clock of the currently programmed mode of the given pipe. */
8890 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8891 struct intel_crtc_config *pipe_config)
8892 {
8893 struct drm_device *dev = crtc->base.dev;
8894 struct drm_i915_private *dev_priv = dev->dev_private;
8895 int pipe = pipe_config->cpu_transcoder;
8896 u32 dpll = pipe_config->dpll_hw_state.dpll;
8897 u32 fp;
8898 intel_clock_t clock;
8899 int refclk = i9xx_pll_refclk(dev, pipe_config);
8900
8901 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8902 fp = pipe_config->dpll_hw_state.fp0;
8903 else
8904 fp = pipe_config->dpll_hw_state.fp1;
8905
8906 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8907 if (IS_PINEVIEW(dev)) {
8908 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8909 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8910 } else {
8911 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8912 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8913 }
8914
8915 if (!IS_GEN2(dev)) {
8916 if (IS_PINEVIEW(dev))
8917 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8918 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8919 else
8920 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8921 DPLL_FPA01_P1_POST_DIV_SHIFT);
8922
8923 switch (dpll & DPLL_MODE_MASK) {
8924 case DPLLB_MODE_DAC_SERIAL:
8925 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8926 5 : 10;
8927 break;
8928 case DPLLB_MODE_LVDS:
8929 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8930 7 : 14;
8931 break;
8932 default:
8933 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8934 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8935 return;
8936 }
8937
8938 if (IS_PINEVIEW(dev))
8939 pineview_clock(refclk, &clock);
8940 else
8941 i9xx_clock(refclk, &clock);
8942 } else {
8943 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8944 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8945
8946 if (is_lvds) {
8947 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8948 DPLL_FPA01_P1_POST_DIV_SHIFT);
8949
8950 if (lvds & LVDS_CLKB_POWER_UP)
8951 clock.p2 = 7;
8952 else
8953 clock.p2 = 14;
8954 } else {
8955 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8956 clock.p1 = 2;
8957 else {
8958 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8959 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8960 }
8961 if (dpll & PLL_P2_DIVIDE_BY_4)
8962 clock.p2 = 4;
8963 else
8964 clock.p2 = 2;
8965 }
8966
8967 i9xx_clock(refclk, &clock);
8968 }
8969
8970 /*
8971 * This value includes pixel_multiplier. We will use
8972 * port_clock to compute adjusted_mode.crtc_clock in the
8973 * encoder's get_config() function.
8974 */
8975 pipe_config->port_clock = clock.dot;
8976 }
8977
8978 int intel_dotclock_calculate(int link_freq,
8979 const struct intel_link_m_n *m_n)
8980 {
8981 /*
8982 * The calculation for the data clock is:
8983 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8984 * But we want to avoid losing precison if possible, so:
8985 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8986 *
8987 * and the link clock is simpler:
8988 * link_clock = (m * link_clock) / n
8989 */
8990
8991 if (!m_n->link_n)
8992 return 0;
8993
8994 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8995 }
8996
8997 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8998 struct intel_crtc_config *pipe_config)
8999 {
9000 struct drm_device *dev = crtc->base.dev;
9001
9002 /* read out port_clock from the DPLL */
9003 i9xx_crtc_clock_get(crtc, pipe_config);
9004
9005 /*
9006 * This value does not include pixel_multiplier.
9007 * We will check that port_clock and adjusted_mode.crtc_clock
9008 * agree once we know their relationship in the encoder's
9009 * get_config() function.
9010 */
9011 pipe_config->adjusted_mode.crtc_clock =
9012 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9013 &pipe_config->fdi_m_n);
9014 }
9015
9016 /** Returns the currently programmed mode of the given pipe. */
9017 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9018 struct drm_crtc *crtc)
9019 {
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9022 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
9023 struct drm_display_mode *mode;
9024 struct intel_crtc_config pipe_config;
9025 int htot = I915_READ(HTOTAL(cpu_transcoder));
9026 int hsync = I915_READ(HSYNC(cpu_transcoder));
9027 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9028 int vsync = I915_READ(VSYNC(cpu_transcoder));
9029 enum pipe pipe = intel_crtc->pipe;
9030
9031 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9032 if (!mode)
9033 return NULL;
9034
9035 /*
9036 * Construct a pipe_config sufficient for getting the clock info
9037 * back out of crtc_clock_get.
9038 *
9039 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9040 * to use a real value here instead.
9041 */
9042 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9043 pipe_config.pixel_multiplier = 1;
9044 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9045 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9046 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9047 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9048
9049 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9050 mode->hdisplay = (htot & 0xffff) + 1;
9051 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9052 mode->hsync_start = (hsync & 0xffff) + 1;
9053 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9054 mode->vdisplay = (vtot & 0xffff) + 1;
9055 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9056 mode->vsync_start = (vsync & 0xffff) + 1;
9057 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9058
9059 drm_mode_set_name(mode);
9060
9061 return mode;
9062 }
9063
9064 static void intel_increase_pllclock(struct drm_device *dev,
9065 enum pipe pipe)
9066 {
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 int dpll_reg = DPLL(pipe);
9069 int dpll;
9070
9071 if (!HAS_GMCH_DISPLAY(dev))
9072 return;
9073
9074 if (!dev_priv->lvds_downclock_avail)
9075 return;
9076
9077 dpll = I915_READ(dpll_reg);
9078 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9079 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9080
9081 assert_panel_unlocked(dev_priv, pipe);
9082
9083 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9084 I915_WRITE(dpll_reg, dpll);
9085 intel_wait_for_vblank(dev, pipe);
9086
9087 dpll = I915_READ(dpll_reg);
9088 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9089 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9090 }
9091 }
9092
9093 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9094 {
9095 struct drm_device *dev = crtc->dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9098
9099 if (!HAS_GMCH_DISPLAY(dev))
9100 return;
9101
9102 if (!dev_priv->lvds_downclock_avail)
9103 return;
9104
9105 /*
9106 * Since this is called by a timer, we should never get here in
9107 * the manual case.
9108 */
9109 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9110 int pipe = intel_crtc->pipe;
9111 int dpll_reg = DPLL(pipe);
9112 int dpll;
9113
9114 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9115
9116 assert_panel_unlocked(dev_priv, pipe);
9117
9118 dpll = I915_READ(dpll_reg);
9119 dpll |= DISPLAY_RATE_SELECT_FPA1;
9120 I915_WRITE(dpll_reg, dpll);
9121 intel_wait_for_vblank(dev, pipe);
9122 dpll = I915_READ(dpll_reg);
9123 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9124 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9125 }
9126
9127 }
9128
9129 void intel_mark_busy(struct drm_device *dev)
9130 {
9131 struct drm_i915_private *dev_priv = dev->dev_private;
9132
9133 if (dev_priv->mm.busy)
9134 return;
9135
9136 intel_runtime_pm_get(dev_priv);
9137 i915_update_gfx_val(dev_priv);
9138 dev_priv->mm.busy = true;
9139 }
9140
9141 void intel_mark_idle(struct drm_device *dev)
9142 {
9143 struct drm_i915_private *dev_priv = dev->dev_private;
9144 struct drm_crtc *crtc;
9145
9146 if (!dev_priv->mm.busy)
9147 return;
9148
9149 dev_priv->mm.busy = false;
9150
9151 if (!i915.powersave)
9152 goto out;
9153
9154 for_each_crtc(dev, crtc) {
9155 if (!crtc->primary->fb)
9156 continue;
9157
9158 intel_decrease_pllclock(crtc);
9159 }
9160
9161 if (INTEL_INFO(dev)->gen >= 6)
9162 gen6_rps_idle(dev->dev_private);
9163
9164 out:
9165 intel_runtime_pm_put(dev_priv);
9166 }
9167
9168
9169 /**
9170 * intel_mark_fb_busy - mark given planes as busy
9171 * @dev: DRM device
9172 * @frontbuffer_bits: bits for the affected planes
9173 * @ring: optional ring for asynchronous commands
9174 *
9175 * This function gets called every time the screen contents change. It can be
9176 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9177 */
9178 static void intel_mark_fb_busy(struct drm_device *dev,
9179 unsigned frontbuffer_bits,
9180 struct intel_engine_cs *ring)
9181 {
9182 struct drm_i915_private *dev_priv = dev->dev_private;
9183 enum pipe pipe;
9184
9185 if (!i915.powersave)
9186 return;
9187
9188 for_each_pipe(dev_priv, pipe) {
9189 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9190 continue;
9191
9192 intel_increase_pllclock(dev, pipe);
9193 if (ring && intel_fbc_enabled(dev))
9194 ring->fbc_dirty = true;
9195 }
9196 }
9197
9198 /**
9199 * intel_fb_obj_invalidate - invalidate frontbuffer object
9200 * @obj: GEM object to invalidate
9201 * @ring: set for asynchronous rendering
9202 *
9203 * This function gets called every time rendering on the given object starts and
9204 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9205 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9206 * until the rendering completes or a flip on this frontbuffer plane is
9207 * scheduled.
9208 */
9209 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9210 struct intel_engine_cs *ring)
9211 {
9212 struct drm_device *dev = obj->base.dev;
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214
9215 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9216
9217 if (!obj->frontbuffer_bits)
9218 return;
9219
9220 if (ring) {
9221 mutex_lock(&dev_priv->fb_tracking.lock);
9222 dev_priv->fb_tracking.busy_bits
9223 |= obj->frontbuffer_bits;
9224 dev_priv->fb_tracking.flip_bits
9225 &= ~obj->frontbuffer_bits;
9226 mutex_unlock(&dev_priv->fb_tracking.lock);
9227 }
9228
9229 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9230
9231 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9232 }
9233
9234 /**
9235 * intel_frontbuffer_flush - flush frontbuffer
9236 * @dev: DRM device
9237 * @frontbuffer_bits: frontbuffer plane tracking bits
9238 *
9239 * This function gets called every time rendering on the given planes has
9240 * completed and frontbuffer caching can be started again. Flushes will get
9241 * delayed if they're blocked by some oustanding asynchronous rendering.
9242 *
9243 * Can be called without any locks held.
9244 */
9245 void intel_frontbuffer_flush(struct drm_device *dev,
9246 unsigned frontbuffer_bits)
9247 {
9248 struct drm_i915_private *dev_priv = dev->dev_private;
9249
9250 /* Delay flushing when rings are still busy.*/
9251 mutex_lock(&dev_priv->fb_tracking.lock);
9252 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9253 mutex_unlock(&dev_priv->fb_tracking.lock);
9254
9255 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9256
9257 intel_edp_psr_flush(dev, frontbuffer_bits);
9258
9259 /*
9260 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9261 * needs to be reworked into a proper frontbuffer tracking scheme like
9262 * psr employs.
9263 */
9264 if (IS_BROADWELL(dev))
9265 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9266 }
9267
9268 /**
9269 * intel_fb_obj_flush - flush frontbuffer object
9270 * @obj: GEM object to flush
9271 * @retire: set when retiring asynchronous rendering
9272 *
9273 * This function gets called every time rendering on the given object has
9274 * completed and frontbuffer caching can be started again. If @retire is true
9275 * then any delayed flushes will be unblocked.
9276 */
9277 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9278 bool retire)
9279 {
9280 struct drm_device *dev = obj->base.dev;
9281 struct drm_i915_private *dev_priv = dev->dev_private;
9282 unsigned frontbuffer_bits;
9283
9284 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9285
9286 if (!obj->frontbuffer_bits)
9287 return;
9288
9289 frontbuffer_bits = obj->frontbuffer_bits;
9290
9291 if (retire) {
9292 mutex_lock(&dev_priv->fb_tracking.lock);
9293 /* Filter out new bits since rendering started. */
9294 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9295
9296 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9297 mutex_unlock(&dev_priv->fb_tracking.lock);
9298 }
9299
9300 intel_frontbuffer_flush(dev, frontbuffer_bits);
9301 }
9302
9303 /**
9304 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9305 * @dev: DRM device
9306 * @frontbuffer_bits: frontbuffer plane tracking bits
9307 *
9308 * This function gets called after scheduling a flip on @obj. The actual
9309 * frontbuffer flushing will be delayed until completion is signalled with
9310 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9311 * flush will be cancelled.
9312 *
9313 * Can be called without any locks held.
9314 */
9315 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9316 unsigned frontbuffer_bits)
9317 {
9318 struct drm_i915_private *dev_priv = dev->dev_private;
9319
9320 mutex_lock(&dev_priv->fb_tracking.lock);
9321 dev_priv->fb_tracking.flip_bits
9322 |= frontbuffer_bits;
9323 mutex_unlock(&dev_priv->fb_tracking.lock);
9324 }
9325
9326 /**
9327 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9328 * @dev: DRM device
9329 * @frontbuffer_bits: frontbuffer plane tracking bits
9330 *
9331 * This function gets called after the flip has been latched and will complete
9332 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9333 *
9334 * Can be called without any locks held.
9335 */
9336 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9337 unsigned frontbuffer_bits)
9338 {
9339 struct drm_i915_private *dev_priv = dev->dev_private;
9340
9341 mutex_lock(&dev_priv->fb_tracking.lock);
9342 /* Mask any cancelled flips. */
9343 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9344 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9345 mutex_unlock(&dev_priv->fb_tracking.lock);
9346
9347 intel_frontbuffer_flush(dev, frontbuffer_bits);
9348 }
9349
9350 static void intel_crtc_destroy(struct drm_crtc *crtc)
9351 {
9352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9353 struct drm_device *dev = crtc->dev;
9354 struct intel_unpin_work *work;
9355 unsigned long flags;
9356
9357 spin_lock_irqsave(&dev->event_lock, flags);
9358 work = intel_crtc->unpin_work;
9359 intel_crtc->unpin_work = NULL;
9360 spin_unlock_irqrestore(&dev->event_lock, flags);
9361
9362 if (work) {
9363 cancel_work_sync(&work->work);
9364 kfree(work);
9365 }
9366
9367 drm_crtc_cleanup(crtc);
9368
9369 kfree(intel_crtc);
9370 }
9371
9372 static void intel_unpin_work_fn(struct work_struct *__work)
9373 {
9374 struct intel_unpin_work *work =
9375 container_of(__work, struct intel_unpin_work, work);
9376 struct drm_device *dev = work->crtc->dev;
9377 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9378
9379 mutex_lock(&dev->struct_mutex);
9380 intel_unpin_fb_obj(work->old_fb_obj);
9381 drm_gem_object_unreference(&work->pending_flip_obj->base);
9382 drm_gem_object_unreference(&work->old_fb_obj->base);
9383
9384 intel_update_fbc(dev);
9385 mutex_unlock(&dev->struct_mutex);
9386
9387 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9388
9389 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9390 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9391
9392 kfree(work);
9393 }
9394
9395 static void do_intel_finish_page_flip(struct drm_device *dev,
9396 struct drm_crtc *crtc)
9397 {
9398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9399 struct intel_unpin_work *work;
9400 unsigned long flags;
9401
9402 /* Ignore early vblank irqs */
9403 if (intel_crtc == NULL)
9404 return;
9405
9406 spin_lock_irqsave(&dev->event_lock, flags);
9407 work = intel_crtc->unpin_work;
9408
9409 /* Ensure we don't miss a work->pending update ... */
9410 smp_rmb();
9411
9412 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9413 spin_unlock_irqrestore(&dev->event_lock, flags);
9414 return;
9415 }
9416
9417 page_flip_completed(intel_crtc);
9418
9419 spin_unlock_irqrestore(&dev->event_lock, flags);
9420 }
9421
9422 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9423 {
9424 struct drm_i915_private *dev_priv = dev->dev_private;
9425 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9426
9427 do_intel_finish_page_flip(dev, crtc);
9428 }
9429
9430 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9431 {
9432 struct drm_i915_private *dev_priv = dev->dev_private;
9433 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9434
9435 do_intel_finish_page_flip(dev, crtc);
9436 }
9437
9438 /* Is 'a' after or equal to 'b'? */
9439 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9440 {
9441 return !((a - b) & 0x80000000);
9442 }
9443
9444 static bool page_flip_finished(struct intel_crtc *crtc)
9445 {
9446 struct drm_device *dev = crtc->base.dev;
9447 struct drm_i915_private *dev_priv = dev->dev_private;
9448
9449 /*
9450 * The relevant registers doen't exist on pre-ctg.
9451 * As the flip done interrupt doesn't trigger for mmio
9452 * flips on gmch platforms, a flip count check isn't
9453 * really needed there. But since ctg has the registers,
9454 * include it in the check anyway.
9455 */
9456 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9457 return true;
9458
9459 /*
9460 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9461 * used the same base address. In that case the mmio flip might
9462 * have completed, but the CS hasn't even executed the flip yet.
9463 *
9464 * A flip count check isn't enough as the CS might have updated
9465 * the base address just after start of vblank, but before we
9466 * managed to process the interrupt. This means we'd complete the
9467 * CS flip too soon.
9468 *
9469 * Combining both checks should get us a good enough result. It may
9470 * still happen that the CS flip has been executed, but has not
9471 * yet actually completed. But in case the base address is the same
9472 * anyway, we don't really care.
9473 */
9474 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9475 crtc->unpin_work->gtt_offset &&
9476 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9477 crtc->unpin_work->flip_count);
9478 }
9479
9480 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9481 {
9482 struct drm_i915_private *dev_priv = dev->dev_private;
9483 struct intel_crtc *intel_crtc =
9484 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9485 unsigned long flags;
9486
9487 /* NB: An MMIO update of the plane base pointer will also
9488 * generate a page-flip completion irq, i.e. every modeset
9489 * is also accompanied by a spurious intel_prepare_page_flip().
9490 */
9491 spin_lock_irqsave(&dev->event_lock, flags);
9492 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9493 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9494 spin_unlock_irqrestore(&dev->event_lock, flags);
9495 }
9496
9497 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9498 {
9499 /* Ensure that the work item is consistent when activating it ... */
9500 smp_wmb();
9501 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9502 /* and that it is marked active as soon as the irq could fire. */
9503 smp_wmb();
9504 }
9505
9506 static int intel_gen2_queue_flip(struct drm_device *dev,
9507 struct drm_crtc *crtc,
9508 struct drm_framebuffer *fb,
9509 struct drm_i915_gem_object *obj,
9510 struct intel_engine_cs *ring,
9511 uint32_t flags)
9512 {
9513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9514 u32 flip_mask;
9515 int ret;
9516
9517 ret = intel_ring_begin(ring, 6);
9518 if (ret)
9519 return ret;
9520
9521 /* Can't queue multiple flips, so wait for the previous
9522 * one to finish before executing the next.
9523 */
9524 if (intel_crtc->plane)
9525 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9526 else
9527 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9528 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9529 intel_ring_emit(ring, MI_NOOP);
9530 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9531 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9532 intel_ring_emit(ring, fb->pitches[0]);
9533 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9534 intel_ring_emit(ring, 0); /* aux display base address, unused */
9535
9536 intel_mark_page_flip_active(intel_crtc);
9537 __intel_ring_advance(ring);
9538 return 0;
9539 }
9540
9541 static int intel_gen3_queue_flip(struct drm_device *dev,
9542 struct drm_crtc *crtc,
9543 struct drm_framebuffer *fb,
9544 struct drm_i915_gem_object *obj,
9545 struct intel_engine_cs *ring,
9546 uint32_t flags)
9547 {
9548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9549 u32 flip_mask;
9550 int ret;
9551
9552 ret = intel_ring_begin(ring, 6);
9553 if (ret)
9554 return ret;
9555
9556 if (intel_crtc->plane)
9557 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9558 else
9559 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9560 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9561 intel_ring_emit(ring, MI_NOOP);
9562 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9563 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9564 intel_ring_emit(ring, fb->pitches[0]);
9565 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9566 intel_ring_emit(ring, MI_NOOP);
9567
9568 intel_mark_page_flip_active(intel_crtc);
9569 __intel_ring_advance(ring);
9570 return 0;
9571 }
9572
9573 static int intel_gen4_queue_flip(struct drm_device *dev,
9574 struct drm_crtc *crtc,
9575 struct drm_framebuffer *fb,
9576 struct drm_i915_gem_object *obj,
9577 struct intel_engine_cs *ring,
9578 uint32_t flags)
9579 {
9580 struct drm_i915_private *dev_priv = dev->dev_private;
9581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9582 uint32_t pf, pipesrc;
9583 int ret;
9584
9585 ret = intel_ring_begin(ring, 4);
9586 if (ret)
9587 return ret;
9588
9589 /* i965+ uses the linear or tiled offsets from the
9590 * Display Registers (which do not change across a page-flip)
9591 * so we need only reprogram the base address.
9592 */
9593 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9594 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9595 intel_ring_emit(ring, fb->pitches[0]);
9596 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9597 obj->tiling_mode);
9598
9599 /* XXX Enabling the panel-fitter across page-flip is so far
9600 * untested on non-native modes, so ignore it for now.
9601 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9602 */
9603 pf = 0;
9604 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9605 intel_ring_emit(ring, pf | pipesrc);
9606
9607 intel_mark_page_flip_active(intel_crtc);
9608 __intel_ring_advance(ring);
9609 return 0;
9610 }
9611
9612 static int intel_gen6_queue_flip(struct drm_device *dev,
9613 struct drm_crtc *crtc,
9614 struct drm_framebuffer *fb,
9615 struct drm_i915_gem_object *obj,
9616 struct intel_engine_cs *ring,
9617 uint32_t flags)
9618 {
9619 struct drm_i915_private *dev_priv = dev->dev_private;
9620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9621 uint32_t pf, pipesrc;
9622 int ret;
9623
9624 ret = intel_ring_begin(ring, 4);
9625 if (ret)
9626 return ret;
9627
9628 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9629 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9630 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9631 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9632
9633 /* Contrary to the suggestions in the documentation,
9634 * "Enable Panel Fitter" does not seem to be required when page
9635 * flipping with a non-native mode, and worse causes a normal
9636 * modeset to fail.
9637 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9638 */
9639 pf = 0;
9640 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9641 intel_ring_emit(ring, pf | pipesrc);
9642
9643 intel_mark_page_flip_active(intel_crtc);
9644 __intel_ring_advance(ring);
9645 return 0;
9646 }
9647
9648 static int intel_gen7_queue_flip(struct drm_device *dev,
9649 struct drm_crtc *crtc,
9650 struct drm_framebuffer *fb,
9651 struct drm_i915_gem_object *obj,
9652 struct intel_engine_cs *ring,
9653 uint32_t flags)
9654 {
9655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9656 uint32_t plane_bit = 0;
9657 int len, ret;
9658
9659 switch (intel_crtc->plane) {
9660 case PLANE_A:
9661 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9662 break;
9663 case PLANE_B:
9664 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9665 break;
9666 case PLANE_C:
9667 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9668 break;
9669 default:
9670 WARN_ONCE(1, "unknown plane in flip command\n");
9671 return -ENODEV;
9672 }
9673
9674 len = 4;
9675 if (ring->id == RCS) {
9676 len += 6;
9677 /*
9678 * On Gen 8, SRM is now taking an extra dword to accommodate
9679 * 48bits addresses, and we need a NOOP for the batch size to
9680 * stay even.
9681 */
9682 if (IS_GEN8(dev))
9683 len += 2;
9684 }
9685
9686 /*
9687 * BSpec MI_DISPLAY_FLIP for IVB:
9688 * "The full packet must be contained within the same cache line."
9689 *
9690 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9691 * cacheline, if we ever start emitting more commands before
9692 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9693 * then do the cacheline alignment, and finally emit the
9694 * MI_DISPLAY_FLIP.
9695 */
9696 ret = intel_ring_cacheline_align(ring);
9697 if (ret)
9698 return ret;
9699
9700 ret = intel_ring_begin(ring, len);
9701 if (ret)
9702 return ret;
9703
9704 /* Unmask the flip-done completion message. Note that the bspec says that
9705 * we should do this for both the BCS and RCS, and that we must not unmask
9706 * more than one flip event at any time (or ensure that one flip message
9707 * can be sent by waiting for flip-done prior to queueing new flips).
9708 * Experimentation says that BCS works despite DERRMR masking all
9709 * flip-done completion events and that unmasking all planes at once
9710 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9711 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9712 */
9713 if (ring->id == RCS) {
9714 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9715 intel_ring_emit(ring, DERRMR);
9716 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9717 DERRMR_PIPEB_PRI_FLIP_DONE |
9718 DERRMR_PIPEC_PRI_FLIP_DONE));
9719 if (IS_GEN8(dev))
9720 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9721 MI_SRM_LRM_GLOBAL_GTT);
9722 else
9723 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9724 MI_SRM_LRM_GLOBAL_GTT);
9725 intel_ring_emit(ring, DERRMR);
9726 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9727 if (IS_GEN8(dev)) {
9728 intel_ring_emit(ring, 0);
9729 intel_ring_emit(ring, MI_NOOP);
9730 }
9731 }
9732
9733 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9734 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9735 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9736 intel_ring_emit(ring, (MI_NOOP));
9737
9738 intel_mark_page_flip_active(intel_crtc);
9739 __intel_ring_advance(ring);
9740 return 0;
9741 }
9742
9743 static bool use_mmio_flip(struct intel_engine_cs *ring,
9744 struct drm_i915_gem_object *obj)
9745 {
9746 /*
9747 * This is not being used for older platforms, because
9748 * non-availability of flip done interrupt forces us to use
9749 * CS flips. Older platforms derive flip done using some clever
9750 * tricks involving the flip_pending status bits and vblank irqs.
9751 * So using MMIO flips there would disrupt this mechanism.
9752 */
9753
9754 if (ring == NULL)
9755 return true;
9756
9757 if (INTEL_INFO(ring->dev)->gen < 5)
9758 return false;
9759
9760 if (i915.use_mmio_flip < 0)
9761 return false;
9762 else if (i915.use_mmio_flip > 0)
9763 return true;
9764 else if (i915.enable_execlists)
9765 return true;
9766 else
9767 return ring != obj->ring;
9768 }
9769
9770 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9771 {
9772 struct drm_device *dev = intel_crtc->base.dev;
9773 struct drm_i915_private *dev_priv = dev->dev_private;
9774 struct intel_framebuffer *intel_fb =
9775 to_intel_framebuffer(intel_crtc->base.primary->fb);
9776 struct drm_i915_gem_object *obj = intel_fb->obj;
9777 u32 dspcntr;
9778 u32 reg;
9779
9780 intel_mark_page_flip_active(intel_crtc);
9781
9782 reg = DSPCNTR(intel_crtc->plane);
9783 dspcntr = I915_READ(reg);
9784
9785 if (INTEL_INFO(dev)->gen >= 4) {
9786 if (obj->tiling_mode != I915_TILING_NONE)
9787 dspcntr |= DISPPLANE_TILED;
9788 else
9789 dspcntr &= ~DISPPLANE_TILED;
9790 }
9791 I915_WRITE(reg, dspcntr);
9792
9793 I915_WRITE(DSPSURF(intel_crtc->plane),
9794 intel_crtc->unpin_work->gtt_offset);
9795 POSTING_READ(DSPSURF(intel_crtc->plane));
9796 }
9797
9798 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9799 {
9800 struct intel_engine_cs *ring;
9801 int ret;
9802
9803 lockdep_assert_held(&obj->base.dev->struct_mutex);
9804
9805 if (!obj->last_write_seqno)
9806 return 0;
9807
9808 ring = obj->ring;
9809
9810 if (i915_seqno_passed(ring->get_seqno(ring, true),
9811 obj->last_write_seqno))
9812 return 0;
9813
9814 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9815 if (ret)
9816 return ret;
9817
9818 if (WARN_ON(!ring->irq_get(ring)))
9819 return 0;
9820
9821 return 1;
9822 }
9823
9824 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9825 {
9826 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9827 struct intel_crtc *intel_crtc;
9828 unsigned long irq_flags;
9829 u32 seqno;
9830
9831 seqno = ring->get_seqno(ring, false);
9832
9833 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9834 for_each_intel_crtc(ring->dev, intel_crtc) {
9835 struct intel_mmio_flip *mmio_flip;
9836
9837 mmio_flip = &intel_crtc->mmio_flip;
9838 if (mmio_flip->seqno == 0)
9839 continue;
9840
9841 if (ring->id != mmio_flip->ring_id)
9842 continue;
9843
9844 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9845 intel_do_mmio_flip(intel_crtc);
9846 mmio_flip->seqno = 0;
9847 ring->irq_put(ring);
9848 }
9849 }
9850 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9851 }
9852
9853 static int intel_queue_mmio_flip(struct drm_device *dev,
9854 struct drm_crtc *crtc,
9855 struct drm_framebuffer *fb,
9856 struct drm_i915_gem_object *obj,
9857 struct intel_engine_cs *ring,
9858 uint32_t flags)
9859 {
9860 struct drm_i915_private *dev_priv = dev->dev_private;
9861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9862 unsigned long irq_flags;
9863 int ret;
9864
9865 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9866 return -EBUSY;
9867
9868 ret = intel_postpone_flip(obj);
9869 if (ret < 0)
9870 return ret;
9871 if (ret == 0) {
9872 intel_do_mmio_flip(intel_crtc);
9873 return 0;
9874 }
9875
9876 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9877 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9878 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9879 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9880
9881 /*
9882 * Double check to catch cases where irq fired before
9883 * mmio flip data was ready
9884 */
9885 intel_notify_mmio_flip(obj->ring);
9886 return 0;
9887 }
9888
9889 static int intel_default_queue_flip(struct drm_device *dev,
9890 struct drm_crtc *crtc,
9891 struct drm_framebuffer *fb,
9892 struct drm_i915_gem_object *obj,
9893 struct intel_engine_cs *ring,
9894 uint32_t flags)
9895 {
9896 return -ENODEV;
9897 }
9898
9899 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9900 struct drm_crtc *crtc)
9901 {
9902 struct drm_i915_private *dev_priv = dev->dev_private;
9903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9904 struct intel_unpin_work *work = intel_crtc->unpin_work;
9905 u32 addr;
9906
9907 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9908 return true;
9909
9910 if (!work->enable_stall_check)
9911 return false;
9912
9913 if (work->flip_ready_vblank == 0) {
9914 if (work->flip_queued_ring &&
9915 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9916 work->flip_queued_seqno))
9917 return false;
9918
9919 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9920 }
9921
9922 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9923 return false;
9924
9925 /* Potential stall - if we see that the flip has happened,
9926 * assume a missed interrupt. */
9927 if (INTEL_INFO(dev)->gen >= 4)
9928 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9929 else
9930 addr = I915_READ(DSPADDR(intel_crtc->plane));
9931
9932 /* There is a potential issue here with a false positive after a flip
9933 * to the same address. We could address this by checking for a
9934 * non-incrementing frame counter.
9935 */
9936 return addr == work->gtt_offset;
9937 }
9938
9939 void intel_check_page_flip(struct drm_device *dev, int pipe)
9940 {
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9944 unsigned long flags;
9945
9946 if (crtc == NULL)
9947 return;
9948
9949 spin_lock_irqsave(&dev->event_lock, flags);
9950 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9951 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9952 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9953 page_flip_completed(intel_crtc);
9954 }
9955 spin_unlock_irqrestore(&dev->event_lock, flags);
9956 }
9957
9958 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9959 struct drm_framebuffer *fb,
9960 struct drm_pending_vblank_event *event,
9961 uint32_t page_flip_flags)
9962 {
9963 struct drm_device *dev = crtc->dev;
9964 struct drm_i915_private *dev_priv = dev->dev_private;
9965 struct drm_framebuffer *old_fb = crtc->primary->fb;
9966 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9968 enum pipe pipe = intel_crtc->pipe;
9969 struct intel_unpin_work *work;
9970 struct intel_engine_cs *ring;
9971 unsigned long flags;
9972 int ret;
9973
9974 //trigger software GT busyness calculation
9975 gen8_flip_interrupt(dev);
9976
9977 /*
9978 * drm_mode_page_flip_ioctl() should already catch this, but double
9979 * check to be safe. In the future we may enable pageflipping from
9980 * a disabled primary plane.
9981 */
9982 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9983 return -EBUSY;
9984
9985 /* Can't change pixel format via MI display flips. */
9986 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9987 return -EINVAL;
9988
9989 /*
9990 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9991 * Note that pitch changes could also affect these register.
9992 */
9993 if (INTEL_INFO(dev)->gen > 3 &&
9994 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9995 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9996 return -EINVAL;
9997
9998 if (i915_terminally_wedged(&dev_priv->gpu_error))
9999 goto out_hang;
10000
10001 work = kzalloc(sizeof(*work), GFP_KERNEL);
10002 if (work == NULL)
10003 return -ENOMEM;
10004
10005 work->event = event;
10006 work->crtc = crtc;
10007 work->old_fb_obj = intel_fb_obj(old_fb);
10008 INIT_WORK(&work->work, intel_unpin_work_fn);
10009
10010 ret = drm_crtc_vblank_get(crtc);
10011 if (ret)
10012 goto free_work;
10013
10014 /* We borrow the event spin lock for protecting unpin_work */
10015 spin_lock_irqsave(&dev->event_lock, flags);
10016 if (intel_crtc->unpin_work) {
10017 /* Before declaring the flip queue wedged, check if
10018 * the hardware completed the operation behind our backs.
10019 */
10020 if (__intel_pageflip_stall_check(dev, crtc)) {
10021 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10022 page_flip_completed(intel_crtc);
10023 } else {
10024 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10025 spin_unlock_irqrestore(&dev->event_lock, flags);
10026
10027 drm_crtc_vblank_put(crtc);
10028 kfree(work);
10029 return -EBUSY;
10030 }
10031 }
10032 intel_crtc->unpin_work = work;
10033 spin_unlock_irqrestore(&dev->event_lock, flags);
10034
10035 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10036 flush_workqueue(dev_priv->wq);
10037
10038 ret = i915_mutex_lock_interruptible(dev);
10039 if (ret)
10040 goto cleanup;
10041
10042 /* Reference the objects for the scheduled work. */
10043 drm_gem_object_reference(&work->old_fb_obj->base);
10044 drm_gem_object_reference(&obj->base);
10045
10046 crtc->primary->fb = fb;
10047
10048 work->pending_flip_obj = obj;
10049
10050 atomic_inc(&intel_crtc->unpin_work_count);
10051 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10052
10053 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10054 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10055
10056 if (IS_VALLEYVIEW(dev)) {
10057 ring = &dev_priv->ring[BCS];
10058 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10059 /* vlv: DISPLAY_FLIP fails to change tiling */
10060 ring = NULL;
10061 } else if (IS_IVYBRIDGE(dev)) {
10062 ring = &dev_priv->ring[BCS];
10063 } else if (INTEL_INFO(dev)->gen >= 7) {
10064 ring = obj->ring;
10065 if (ring == NULL || ring->id != RCS)
10066 ring = &dev_priv->ring[BCS];
10067 } else {
10068 ring = &dev_priv->ring[RCS];
10069 }
10070
10071 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10072 if (ret)
10073 goto cleanup_pending;
10074
10075 work->gtt_offset =
10076 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10077
10078 if (use_mmio_flip(ring, obj)) {
10079 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10080 page_flip_flags);
10081 if (ret)
10082 goto cleanup_unpin;
10083
10084 work->flip_queued_seqno = obj->last_write_seqno;
10085 work->flip_queued_ring = obj->ring;
10086 } else {
10087 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10088 page_flip_flags);
10089 if (ret)
10090 goto cleanup_unpin;
10091
10092 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10093 work->flip_queued_ring = ring;
10094 }
10095
10096 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10097 work->enable_stall_check = true;
10098
10099 i915_gem_track_fb(work->old_fb_obj, obj,
10100 INTEL_FRONTBUFFER_PRIMARY(pipe));
10101
10102 intel_disable_fbc(dev);
10103 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10104 mutex_unlock(&dev->struct_mutex);
10105
10106 trace_i915_flip_request(intel_crtc->plane, obj);
10107
10108 return 0;
10109
10110 cleanup_unpin:
10111 intel_unpin_fb_obj(obj);
10112 cleanup_pending:
10113 atomic_dec(&intel_crtc->unpin_work_count);
10114 crtc->primary->fb = old_fb;
10115 drm_gem_object_unreference(&work->old_fb_obj->base);
10116 drm_gem_object_unreference(&obj->base);
10117 mutex_unlock(&dev->struct_mutex);
10118
10119 cleanup:
10120 spin_lock_irqsave(&dev->event_lock, flags);
10121 intel_crtc->unpin_work = NULL;
10122 spin_unlock_irqrestore(&dev->event_lock, flags);
10123
10124 drm_crtc_vblank_put(crtc);
10125 free_work:
10126 kfree(work);
10127
10128 if (ret == -EIO) {
10129 out_hang:
10130 intel_crtc_wait_for_pending_flips(crtc);
10131 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10132 if (ret == 0 && event)
10133 drm_send_vblank_event(dev, pipe, event);
10134 }
10135 return ret;
10136 }
10137
10138 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10139 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10140 .load_lut = intel_crtc_load_lut,
10141 };
10142
10143 /**
10144 * intel_modeset_update_staged_output_state
10145 *
10146 * Updates the staged output configuration state, e.g. after we've read out the
10147 * current hw state.
10148 */
10149 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10150 {
10151 struct intel_crtc *crtc;
10152 struct intel_encoder *encoder;
10153 struct intel_connector *connector;
10154
10155 list_for_each_entry(connector, &dev->mode_config.connector_list,
10156 base.head) {
10157 connector->new_encoder =
10158 to_intel_encoder(connector->base.encoder);
10159 }
10160
10161 for_each_intel_encoder(dev, encoder) {
10162 encoder->new_crtc =
10163 to_intel_crtc(encoder->base.crtc);
10164 }
10165
10166 for_each_intel_crtc(dev, crtc) {
10167 crtc->new_enabled = crtc->base.enabled;
10168
10169 if (crtc->new_enabled)
10170 crtc->new_config = &crtc->config;
10171 else
10172 crtc->new_config = NULL;
10173 }
10174 }
10175
10176 /**
10177 * intel_modeset_commit_output_state
10178 *
10179 * This function copies the stage display pipe configuration to the real one.
10180 */
10181 static void intel_modeset_commit_output_state(struct drm_device *dev)
10182 {
10183 struct intel_crtc *crtc;
10184 struct intel_encoder *encoder;
10185 struct intel_connector *connector;
10186
10187 list_for_each_entry(connector, &dev->mode_config.connector_list,
10188 base.head) {
10189 connector->base.encoder = &connector->new_encoder->base;
10190 }
10191
10192 for_each_intel_encoder(dev, encoder) {
10193 encoder->base.crtc = &encoder->new_crtc->base;
10194 }
10195
10196 for_each_intel_crtc(dev, crtc) {
10197 crtc->base.enabled = crtc->new_enabled;
10198 }
10199 }
10200
10201 static void
10202 connected_sink_compute_bpp(struct intel_connector *connector,
10203 struct intel_crtc_config *pipe_config)
10204 {
10205 int bpp = pipe_config->pipe_bpp;
10206
10207 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10208 connector->base.base.id,
10209 connector->base.name);
10210
10211 /* Don't use an invalid EDID bpc value */
10212 if (connector->base.display_info.bpc &&
10213 connector->base.display_info.bpc * 3 < bpp) {
10214 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10215 bpp, connector->base.display_info.bpc*3);
10216 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10217 }
10218
10219 /* Clamp bpp to 8 on screens without EDID 1.4 */
10220 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10221 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10222 bpp);
10223 pipe_config->pipe_bpp = 24;
10224 }
10225 }
10226
10227 static int
10228 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10229 struct drm_framebuffer *fb,
10230 struct intel_crtc_config *pipe_config)
10231 {
10232 struct drm_device *dev = crtc->base.dev;
10233 struct intel_connector *connector;
10234 int bpp;
10235
10236 switch (fb->pixel_format) {
10237 case DRM_FORMAT_C8:
10238 bpp = 8*3; /* since we go through a colormap */
10239 break;
10240 case DRM_FORMAT_XRGB1555:
10241 case DRM_FORMAT_ARGB1555:
10242 /* checked in intel_framebuffer_init already */
10243 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10244 return -EINVAL;
10245 case DRM_FORMAT_RGB565:
10246 bpp = 6*3; /* min is 18bpp */
10247 break;
10248 case DRM_FORMAT_XBGR8888:
10249 case DRM_FORMAT_ABGR8888:
10250 /* checked in intel_framebuffer_init already */
10251 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10252 return -EINVAL;
10253 case DRM_FORMAT_XRGB8888:
10254 case DRM_FORMAT_ARGB8888:
10255 bpp = 8*3;
10256 break;
10257 case DRM_FORMAT_XRGB2101010:
10258 case DRM_FORMAT_ARGB2101010:
10259 case DRM_FORMAT_XBGR2101010:
10260 case DRM_FORMAT_ABGR2101010:
10261 /* checked in intel_framebuffer_init already */
10262 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10263 return -EINVAL;
10264 bpp = 10*3;
10265 break;
10266 /* TODO: gen4+ supports 16 bpc floating point, too. */
10267 default:
10268 DRM_DEBUG_KMS("unsupported depth\n");
10269 return -EINVAL;
10270 }
10271
10272 pipe_config->pipe_bpp = bpp;
10273
10274 /* Clamp display bpp to EDID value */
10275 list_for_each_entry(connector, &dev->mode_config.connector_list,
10276 base.head) {
10277 if (!connector->new_encoder ||
10278 connector->new_encoder->new_crtc != crtc)
10279 continue;
10280
10281 connected_sink_compute_bpp(connector, pipe_config);
10282 }
10283
10284 return bpp;
10285 }
10286
10287 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10288 {
10289 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10290 "type: 0x%x flags: 0x%x\n",
10291 mode->crtc_clock,
10292 mode->crtc_hdisplay, mode->crtc_hsync_start,
10293 mode->crtc_hsync_end, mode->crtc_htotal,
10294 mode->crtc_vdisplay, mode->crtc_vsync_start,
10295 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10296 }
10297
10298 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10299 struct intel_crtc_config *pipe_config,
10300 const char *context)
10301 {
10302 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10303 context, pipe_name(crtc->pipe));
10304
10305 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10306 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10307 pipe_config->pipe_bpp, pipe_config->dither);
10308 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10309 pipe_config->has_pch_encoder,
10310 pipe_config->fdi_lanes,
10311 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10312 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10313 pipe_config->fdi_m_n.tu);
10314 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10315 pipe_config->has_dp_encoder,
10316 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10317 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10318 pipe_config->dp_m_n.tu);
10319
10320 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10321 pipe_config->has_dp_encoder,
10322 pipe_config->dp_m2_n2.gmch_m,
10323 pipe_config->dp_m2_n2.gmch_n,
10324 pipe_config->dp_m2_n2.link_m,
10325 pipe_config->dp_m2_n2.link_n,
10326 pipe_config->dp_m2_n2.tu);
10327
10328 DRM_DEBUG_KMS("requested mode:\n");
10329 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10330 DRM_DEBUG_KMS("adjusted mode:\n");
10331 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10332 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10333 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10334 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10335 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10336 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10337 pipe_config->gmch_pfit.control,
10338 pipe_config->gmch_pfit.pgm_ratios,
10339 pipe_config->gmch_pfit.lvds_border_bits);
10340 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10341 pipe_config->pch_pfit.pos,
10342 pipe_config->pch_pfit.size,
10343 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10344 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10345 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10346 }
10347
10348 static bool encoders_cloneable(const struct intel_encoder *a,
10349 const struct intel_encoder *b)
10350 {
10351 /* masks could be asymmetric, so check both ways */
10352 return a == b || (a->cloneable & (1 << b->type) &&
10353 b->cloneable & (1 << a->type));
10354 }
10355
10356 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10357 struct intel_encoder *encoder)
10358 {
10359 struct drm_device *dev = crtc->base.dev;
10360 struct intel_encoder *source_encoder;
10361
10362 for_each_intel_encoder(dev, source_encoder) {
10363 if (source_encoder->new_crtc != crtc)
10364 continue;
10365
10366 if (!encoders_cloneable(encoder, source_encoder))
10367 return false;
10368 }
10369
10370 return true;
10371 }
10372
10373 static bool check_encoder_cloning(struct intel_crtc *crtc)
10374 {
10375 struct drm_device *dev = crtc->base.dev;
10376 struct intel_encoder *encoder;
10377
10378 for_each_intel_encoder(dev, encoder) {
10379 if (encoder->new_crtc != crtc)
10380 continue;
10381
10382 if (!check_single_encoder_cloning(crtc, encoder))
10383 return false;
10384 }
10385
10386 return true;
10387 }
10388
10389 static struct intel_crtc_config *
10390 intel_modeset_pipe_config(struct drm_crtc *crtc,
10391 struct drm_framebuffer *fb,
10392 struct drm_display_mode *mode)
10393 {
10394 struct drm_device *dev = crtc->dev;
10395 struct intel_encoder *encoder;
10396 struct intel_crtc_config *pipe_config;
10397 int plane_bpp, ret = -EINVAL;
10398 bool retry = true;
10399
10400 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10401 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10402 return ERR_PTR(-EINVAL);
10403 }
10404
10405 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10406 if (!pipe_config)
10407 return ERR_PTR(-ENOMEM);
10408
10409 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10410 drm_mode_copy(&pipe_config->requested_mode, mode);
10411
10412 pipe_config->cpu_transcoder =
10413 (enum transcoder) to_intel_crtc(crtc)->pipe;
10414 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10415
10416 /*
10417 * Sanitize sync polarity flags based on requested ones. If neither
10418 * positive or negative polarity is requested, treat this as meaning
10419 * negative polarity.
10420 */
10421 if (!(pipe_config->adjusted_mode.flags &
10422 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10423 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10424
10425 if (!(pipe_config->adjusted_mode.flags &
10426 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10427 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10428
10429 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10430 * plane pixel format and any sink constraints into account. Returns the
10431 * source plane bpp so that dithering can be selected on mismatches
10432 * after encoders and crtc also have had their say. */
10433 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10434 fb, pipe_config);
10435 if (plane_bpp < 0)
10436 goto fail;
10437
10438 /*
10439 * Determine the real pipe dimensions. Note that stereo modes can
10440 * increase the actual pipe size due to the frame doubling and
10441 * insertion of additional space for blanks between the frame. This
10442 * is stored in the crtc timings. We use the requested mode to do this
10443 * computation to clearly distinguish it from the adjusted mode, which
10444 * can be changed by the connectors in the below retry loop.
10445 */
10446 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10447 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10448 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10449
10450 encoder_retry:
10451 /* Ensure the port clock defaults are reset when retrying. */
10452 pipe_config->port_clock = 0;
10453 pipe_config->pixel_multiplier = 1;
10454
10455 /* Fill in default crtc timings, allow encoders to overwrite them. */
10456 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10457
10458 /* Pass our mode to the connectors and the CRTC to give them a chance to
10459 * adjust it according to limitations or connector properties, and also
10460 * a chance to reject the mode entirely.
10461 */
10462 for_each_intel_encoder(dev, encoder) {
10463
10464 if (&encoder->new_crtc->base != crtc)
10465 continue;
10466
10467 if (!(encoder->compute_config(encoder, pipe_config))) {
10468 DRM_DEBUG_KMS("Encoder config failure\n");
10469 goto fail;
10470 }
10471 }
10472
10473 /* Set default port clock if not overwritten by the encoder. Needs to be
10474 * done afterwards in case the encoder adjusts the mode. */
10475 if (!pipe_config->port_clock)
10476 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10477 * pipe_config->pixel_multiplier;
10478
10479 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10480 if (ret < 0) {
10481 DRM_DEBUG_KMS("CRTC fixup failed\n");
10482 goto fail;
10483 }
10484
10485 if (ret == RETRY) {
10486 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10487 ret = -EINVAL;
10488 goto fail;
10489 }
10490
10491 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10492 retry = false;
10493 goto encoder_retry;
10494 }
10495
10496 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10497 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10498 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10499
10500 return pipe_config;
10501 fail:
10502 kfree(pipe_config);
10503 return ERR_PTR(ret);
10504 }
10505
10506 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10507 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10508 static void
10509 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10510 unsigned *prepare_pipes, unsigned *disable_pipes)
10511 {
10512 struct intel_crtc *intel_crtc;
10513 struct drm_device *dev = crtc->dev;
10514 struct intel_encoder *encoder;
10515 struct intel_connector *connector;
10516 struct drm_crtc *tmp_crtc;
10517
10518 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10519
10520 /* Check which crtcs have changed outputs connected to them, these need
10521 * to be part of the prepare_pipes mask. We don't (yet) support global
10522 * modeset across multiple crtcs, so modeset_pipes will only have one
10523 * bit set at most. */
10524 list_for_each_entry(connector, &dev->mode_config.connector_list,
10525 base.head) {
10526 if (connector->base.encoder == &connector->new_encoder->base)
10527 continue;
10528
10529 if (connector->base.encoder) {
10530 tmp_crtc = connector->base.encoder->crtc;
10531
10532 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10533 }
10534
10535 if (connector->new_encoder)
10536 *prepare_pipes |=
10537 1 << connector->new_encoder->new_crtc->pipe;
10538 }
10539
10540 for_each_intel_encoder(dev, encoder) {
10541 if (encoder->base.crtc == &encoder->new_crtc->base)
10542 continue;
10543
10544 if (encoder->base.crtc) {
10545 tmp_crtc = encoder->base.crtc;
10546
10547 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10548 }
10549
10550 if (encoder->new_crtc)
10551 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10552 }
10553
10554 /* Check for pipes that will be enabled/disabled ... */
10555 for_each_intel_crtc(dev, intel_crtc) {
10556 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10557 continue;
10558
10559 if (!intel_crtc->new_enabled)
10560 *disable_pipes |= 1 << intel_crtc->pipe;
10561 else
10562 *prepare_pipes |= 1 << intel_crtc->pipe;
10563 }
10564
10565
10566 /* set_mode is also used to update properties on life display pipes. */
10567 intel_crtc = to_intel_crtc(crtc);
10568 if (intel_crtc->new_enabled)
10569 *prepare_pipes |= 1 << intel_crtc->pipe;
10570
10571 /*
10572 * For simplicity do a full modeset on any pipe where the output routing
10573 * changed. We could be more clever, but that would require us to be
10574 * more careful with calling the relevant encoder->mode_set functions.
10575 */
10576 if (*prepare_pipes)
10577 *modeset_pipes = *prepare_pipes;
10578
10579 /* ... and mask these out. */
10580 *modeset_pipes &= ~(*disable_pipes);
10581 *prepare_pipes &= ~(*disable_pipes);
10582
10583 /*
10584 * HACK: We don't (yet) fully support global modesets. intel_set_config
10585 * obies this rule, but the modeset restore mode of
10586 * intel_modeset_setup_hw_state does not.
10587 */
10588 *modeset_pipes &= 1 << intel_crtc->pipe;
10589 *prepare_pipes &= 1 << intel_crtc->pipe;
10590
10591 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10592 *modeset_pipes, *prepare_pipes, *disable_pipes);
10593 }
10594
10595 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10596 {
10597 struct drm_encoder *encoder;
10598 struct drm_device *dev = crtc->dev;
10599
10600 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10601 if (encoder->crtc == crtc)
10602 return true;
10603
10604 return false;
10605 }
10606
10607 static void
10608 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10609 {
10610 struct intel_encoder *intel_encoder;
10611 struct intel_crtc *intel_crtc;
10612 struct drm_connector *connector;
10613
10614 for_each_intel_encoder(dev, intel_encoder) {
10615 if (!intel_encoder->base.crtc)
10616 continue;
10617
10618 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10619
10620 if (prepare_pipes & (1 << intel_crtc->pipe))
10621 intel_encoder->connectors_active = false;
10622 }
10623
10624 intel_modeset_commit_output_state(dev);
10625
10626 /* Double check state. */
10627 for_each_intel_crtc(dev, intel_crtc) {
10628 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10629 WARN_ON(intel_crtc->new_config &&
10630 intel_crtc->new_config != &intel_crtc->config);
10631 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10632 }
10633
10634 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10635 if (!connector->encoder || !connector->encoder->crtc)
10636 continue;
10637
10638 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10639
10640 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10641 struct drm_property *dpms_property =
10642 dev->mode_config.dpms_property;
10643
10644 connector->dpms = DRM_MODE_DPMS_ON;
10645 drm_object_property_set_value(&connector->base,
10646 dpms_property,
10647 DRM_MODE_DPMS_ON);
10648
10649 intel_encoder = to_intel_encoder(connector->encoder);
10650 intel_encoder->connectors_active = true;
10651 }
10652 }
10653
10654 }
10655
10656 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10657 {
10658 int diff;
10659
10660 if (clock1 == clock2)
10661 return true;
10662
10663 if (!clock1 || !clock2)
10664 return false;
10665
10666 diff = abs(clock1 - clock2);
10667
10668 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10669 return true;
10670
10671 return false;
10672 }
10673
10674 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10675 list_for_each_entry((intel_crtc), \
10676 &(dev)->mode_config.crtc_list, \
10677 base.head) \
10678 if (mask & (1 <<(intel_crtc)->pipe))
10679
10680 static bool
10681 intel_pipe_config_compare(struct drm_device *dev,
10682 struct intel_crtc_config *current_config,
10683 struct intel_crtc_config *pipe_config)
10684 {
10685 #define PIPE_CONF_CHECK_X(name) \
10686 if (current_config->name != pipe_config->name) { \
10687 DRM_ERROR("mismatch in " #name " " \
10688 "(expected 0x%08x, found 0x%08x)\n", \
10689 current_config->name, \
10690 pipe_config->name); \
10691 return false; \
10692 }
10693
10694 #define PIPE_CONF_CHECK_I(name) \
10695 if (current_config->name != pipe_config->name) { \
10696 DRM_ERROR("mismatch in " #name " " \
10697 "(expected %i, found %i)\n", \
10698 current_config->name, \
10699 pipe_config->name); \
10700 return false; \
10701 }
10702
10703 /* This is required for BDW+ where there is only one set of registers for
10704 * switching between high and low RR.
10705 * This macro can be used whenever a comparison has to be made between one
10706 * hw state and multiple sw state variables.
10707 */
10708 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10709 if ((current_config->name != pipe_config->name) && \
10710 (current_config->alt_name != pipe_config->name)) { \
10711 DRM_ERROR("mismatch in " #name " " \
10712 "(expected %i or %i, found %i)\n", \
10713 current_config->name, \
10714 current_config->alt_name, \
10715 pipe_config->name); \
10716 return false; \
10717 }
10718
10719 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10720 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10721 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10722 "(expected %i, found %i)\n", \
10723 current_config->name & (mask), \
10724 pipe_config->name & (mask)); \
10725 return false; \
10726 }
10727
10728 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10729 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10730 DRM_ERROR("mismatch in " #name " " \
10731 "(expected %i, found %i)\n", \
10732 current_config->name, \
10733 pipe_config->name); \
10734 return false; \
10735 }
10736
10737 #define PIPE_CONF_QUIRK(quirk) \
10738 ((current_config->quirks | pipe_config->quirks) & (quirk))
10739
10740 PIPE_CONF_CHECK_I(cpu_transcoder);
10741
10742 PIPE_CONF_CHECK_I(has_pch_encoder);
10743 PIPE_CONF_CHECK_I(fdi_lanes);
10744 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10745 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10746 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10747 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10748 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10749
10750 PIPE_CONF_CHECK_I(has_dp_encoder);
10751
10752 if (INTEL_INFO(dev)->gen < 8) {
10753 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10754 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10755 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10756 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10757 PIPE_CONF_CHECK_I(dp_m_n.tu);
10758
10759 if (current_config->has_drrs) {
10760 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10761 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10762 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10763 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10764 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10765 }
10766 } else {
10767 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10768 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10769 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10770 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10771 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10772 }
10773
10774 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10775 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10776 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10777 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10778 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10779 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10780
10781 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10782 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10783 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10784 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10785 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10786 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10787
10788 PIPE_CONF_CHECK_I(pixel_multiplier);
10789 PIPE_CONF_CHECK_I(has_hdmi_sink);
10790 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10791 IS_VALLEYVIEW(dev))
10792 PIPE_CONF_CHECK_I(limited_color_range);
10793
10794 PIPE_CONF_CHECK_I(has_audio);
10795
10796 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10797 DRM_MODE_FLAG_INTERLACE);
10798
10799 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10800 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10801 DRM_MODE_FLAG_PHSYNC);
10802 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10803 DRM_MODE_FLAG_NHSYNC);
10804 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10805 DRM_MODE_FLAG_PVSYNC);
10806 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10807 DRM_MODE_FLAG_NVSYNC);
10808 }
10809
10810 PIPE_CONF_CHECK_I(pipe_src_w);
10811 PIPE_CONF_CHECK_I(pipe_src_h);
10812
10813 /*
10814 * FIXME: BIOS likes to set up a cloned config with lvds+external
10815 * screen. Since we don't yet re-compute the pipe config when moving
10816 * just the lvds port away to another pipe the sw tracking won't match.
10817 *
10818 * Proper atomic modesets with recomputed global state will fix this.
10819 * Until then just don't check gmch state for inherited modes.
10820 */
10821 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10822 PIPE_CONF_CHECK_I(gmch_pfit.control);
10823 /* pfit ratios are autocomputed by the hw on gen4+ */
10824 if (INTEL_INFO(dev)->gen < 4)
10825 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10826 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10827 }
10828
10829 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10830 if (current_config->pch_pfit.enabled) {
10831 PIPE_CONF_CHECK_I(pch_pfit.pos);
10832 PIPE_CONF_CHECK_I(pch_pfit.size);
10833 }
10834
10835 /* BDW+ don't expose a synchronous way to read the state */
10836 if (IS_HASWELL(dev))
10837 PIPE_CONF_CHECK_I(ips_enabled);
10838
10839 PIPE_CONF_CHECK_I(double_wide);
10840
10841 PIPE_CONF_CHECK_X(ddi_pll_sel);
10842
10843 PIPE_CONF_CHECK_I(shared_dpll);
10844 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10845 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10846 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10847 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10848 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10849
10850 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10851 PIPE_CONF_CHECK_I(pipe_bpp);
10852
10853 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10854 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10855
10856 #undef PIPE_CONF_CHECK_X
10857 #undef PIPE_CONF_CHECK_I
10858 #undef PIPE_CONF_CHECK_I_ALT
10859 #undef PIPE_CONF_CHECK_FLAGS
10860 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10861 #undef PIPE_CONF_QUIRK
10862
10863 return true;
10864 }
10865
10866 static void
10867 check_connector_state(struct drm_device *dev)
10868 {
10869 struct intel_connector *connector;
10870
10871 list_for_each_entry(connector, &dev->mode_config.connector_list,
10872 base.head) {
10873 /* This also checks the encoder/connector hw state with the
10874 * ->get_hw_state callbacks. */
10875 intel_connector_check_state(connector);
10876
10877 WARN(&connector->new_encoder->base != connector->base.encoder,
10878 "connector's staged encoder doesn't match current encoder\n");
10879 }
10880 }
10881
10882 static void
10883 check_encoder_state(struct drm_device *dev)
10884 {
10885 struct intel_encoder *encoder;
10886 struct intel_connector *connector;
10887
10888 for_each_intel_encoder(dev, encoder) {
10889 bool enabled = false;
10890 bool active = false;
10891 enum pipe pipe, tracked_pipe;
10892
10893 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10894 encoder->base.base.id,
10895 encoder->base.name);
10896
10897 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10898 "encoder's stage crtc doesn't match current crtc\n");
10899 WARN(encoder->connectors_active && !encoder->base.crtc,
10900 "encoder's active_connectors set, but no crtc\n");
10901
10902 list_for_each_entry(connector, &dev->mode_config.connector_list,
10903 base.head) {
10904 if (connector->base.encoder != &encoder->base)
10905 continue;
10906 enabled = true;
10907 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10908 active = true;
10909 }
10910 /*
10911 * for MST connectors if we unplug the connector is gone
10912 * away but the encoder is still connected to a crtc
10913 * until a modeset happens in response to the hotplug.
10914 */
10915 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10916 continue;
10917
10918 WARN(!!encoder->base.crtc != enabled,
10919 "encoder's enabled state mismatch "
10920 "(expected %i, found %i)\n",
10921 !!encoder->base.crtc, enabled);
10922 WARN(active && !encoder->base.crtc,
10923 "active encoder with no crtc\n");
10924
10925 WARN(encoder->connectors_active != active,
10926 "encoder's computed active state doesn't match tracked active state "
10927 "(expected %i, found %i)\n", active, encoder->connectors_active);
10928
10929 active = encoder->get_hw_state(encoder, &pipe);
10930 WARN(active != encoder->connectors_active,
10931 "encoder's hw state doesn't match sw tracking "
10932 "(expected %i, found %i)\n",
10933 encoder->connectors_active, active);
10934
10935 if (!encoder->base.crtc)
10936 continue;
10937
10938 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10939 WARN(active && pipe != tracked_pipe,
10940 "active encoder's pipe doesn't match"
10941 "(expected %i, found %i)\n",
10942 tracked_pipe, pipe);
10943
10944 }
10945 }
10946
10947 static void
10948 check_crtc_state(struct drm_device *dev)
10949 {
10950 struct drm_i915_private *dev_priv = dev->dev_private;
10951 struct intel_crtc *crtc;
10952 struct intel_encoder *encoder;
10953 struct intel_crtc_config pipe_config;
10954
10955 for_each_intel_crtc(dev, crtc) {
10956 bool enabled = false;
10957 bool active = false;
10958
10959 memset(&pipe_config, 0, sizeof(pipe_config));
10960
10961 DRM_DEBUG_KMS("[CRTC:%d]\n",
10962 crtc->base.base.id);
10963
10964 WARN(crtc->active && !crtc->base.enabled,
10965 "active crtc, but not enabled in sw tracking\n");
10966
10967 for_each_intel_encoder(dev, encoder) {
10968 if (encoder->base.crtc != &crtc->base)
10969 continue;
10970 enabled = true;
10971 if (encoder->connectors_active)
10972 active = true;
10973 }
10974
10975 WARN(active != crtc->active,
10976 "crtc's computed active state doesn't match tracked active state "
10977 "(expected %i, found %i)\n", active, crtc->active);
10978 WARN(enabled != crtc->base.enabled,
10979 "crtc's computed enabled state doesn't match tracked enabled state "
10980 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10981
10982 active = dev_priv->display.get_pipe_config(crtc,
10983 &pipe_config);
10984
10985 /* hw state is inconsistent with the pipe quirk */
10986 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10987 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10988 active = crtc->active;
10989
10990 for_each_intel_encoder(dev, encoder) {
10991 enum pipe pipe;
10992 if (encoder->base.crtc != &crtc->base)
10993 continue;
10994 if (encoder->get_hw_state(encoder, &pipe))
10995 encoder->get_config(encoder, &pipe_config);
10996 }
10997
10998 WARN(crtc->active != active,
10999 "crtc active state doesn't match with hw state "
11000 "(expected %i, found %i)\n", crtc->active, active);
11001
11002 if (active &&
11003 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
11004 WARN(1, "pipe state doesn't match!\n");
11005 intel_dump_pipe_config(crtc, &pipe_config,
11006 "[hw state]");
11007 intel_dump_pipe_config(crtc, &crtc->config,
11008 "[sw state]");
11009 }
11010 }
11011 }
11012
11013 static void
11014 check_shared_dpll_state(struct drm_device *dev)
11015 {
11016 struct drm_i915_private *dev_priv = dev->dev_private;
11017 struct intel_crtc *crtc;
11018 struct intel_dpll_hw_state dpll_hw_state;
11019 int i;
11020
11021 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11022 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11023 int enabled_crtcs = 0, active_crtcs = 0;
11024 bool active;
11025
11026 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11027
11028 DRM_DEBUG_KMS("%s\n", pll->name);
11029
11030 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11031
11032 WARN(pll->active > pll->refcount,
11033 "more active pll users than references: %i vs %i\n",
11034 pll->active, pll->refcount);
11035 WARN(pll->active && !pll->on,
11036 "pll in active use but not on in sw tracking\n");
11037 WARN(pll->on && !pll->active,
11038 "pll in on but not on in use in sw tracking\n");
11039 WARN(pll->on != active,
11040 "pll on state mismatch (expected %i, found %i)\n",
11041 pll->on, active);
11042
11043 for_each_intel_crtc(dev, crtc) {
11044 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11045 enabled_crtcs++;
11046 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11047 active_crtcs++;
11048 }
11049 WARN(pll->active != active_crtcs,
11050 "pll active crtcs mismatch (expected %i, found %i)\n",
11051 pll->active, active_crtcs);
11052 WARN(pll->refcount != enabled_crtcs,
11053 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11054 pll->refcount, enabled_crtcs);
11055
11056 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11057 sizeof(dpll_hw_state)),
11058 "pll hw state mismatch\n");
11059 }
11060 }
11061
11062 void
11063 intel_modeset_check_state(struct drm_device *dev)
11064 {
11065 check_connector_state(dev);
11066 check_encoder_state(dev);
11067 check_crtc_state(dev);
11068 check_shared_dpll_state(dev);
11069 }
11070
11071 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11072 int dotclock)
11073 {
11074 /*
11075 * FDI already provided one idea for the dotclock.
11076 * Yell if the encoder disagrees.
11077 */
11078 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11079 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11080 pipe_config->adjusted_mode.crtc_clock, dotclock);
11081 }
11082
11083 static void update_scanline_offset(struct intel_crtc *crtc)
11084 {
11085 struct drm_device *dev = crtc->base.dev;
11086
11087 /*
11088 * The scanline counter increments at the leading edge of hsync.
11089 *
11090 * On most platforms it starts counting from vtotal-1 on the
11091 * first active line. That means the scanline counter value is
11092 * always one less than what we would expect. Ie. just after
11093 * start of vblank, which also occurs at start of hsync (on the
11094 * last active line), the scanline counter will read vblank_start-1.
11095 *
11096 * On gen2 the scanline counter starts counting from 1 instead
11097 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11098 * to keep the value positive), instead of adding one.
11099 *
11100 * On HSW+ the behaviour of the scanline counter depends on the output
11101 * type. For DP ports it behaves like most other platforms, but on HDMI
11102 * there's an extra 1 line difference. So we need to add two instead of
11103 * one to the value.
11104 */
11105 if (IS_GEN2(dev)) {
11106 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11107 int vtotal;
11108
11109 vtotal = mode->crtc_vtotal;
11110 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11111 vtotal /= 2;
11112
11113 crtc->scanline_offset = vtotal - 1;
11114 } else if (HAS_DDI(dev) &&
11115 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11116 crtc->scanline_offset = 2;
11117 } else
11118 crtc->scanline_offset = 1;
11119 }
11120
11121 static int __intel_set_mode(struct drm_crtc *crtc,
11122 struct drm_display_mode *mode,
11123 int x, int y, struct drm_framebuffer *fb)
11124 {
11125 struct drm_device *dev = crtc->dev;
11126 struct drm_i915_private *dev_priv = dev->dev_private;
11127 struct drm_display_mode *saved_mode;
11128 struct intel_crtc_config *pipe_config = NULL;
11129 struct intel_crtc *intel_crtc;
11130 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11131 int ret = 0;
11132
11133 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11134 if (!saved_mode)
11135 return -ENOMEM;
11136
11137 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11138 &prepare_pipes, &disable_pipes);
11139
11140 *saved_mode = crtc->mode;
11141
11142 /* Hack: Because we don't (yet) support global modeset on multiple
11143 * crtcs, we don't keep track of the new mode for more than one crtc.
11144 * Hence simply check whether any bit is set in modeset_pipes in all the
11145 * pieces of code that are not yet converted to deal with mutliple crtcs
11146 * changing their mode at the same time. */
11147 if (modeset_pipes) {
11148 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11149 if (IS_ERR(pipe_config)) {
11150 ret = PTR_ERR(pipe_config);
11151 pipe_config = NULL;
11152
11153 goto out;
11154 }
11155 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11156 "[modeset]");
11157 to_intel_crtc(crtc)->new_config = pipe_config;
11158 }
11159
11160 /*
11161 * See if the config requires any additional preparation, e.g.
11162 * to adjust global state with pipes off. We need to do this
11163 * here so we can get the modeset_pipe updated config for the new
11164 * mode set on this crtc. For other crtcs we need to use the
11165 * adjusted_mode bits in the crtc directly.
11166 */
11167 if (IS_VALLEYVIEW(dev)) {
11168 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11169
11170 /* may have added more to prepare_pipes than we should */
11171 prepare_pipes &= ~disable_pipes;
11172 }
11173
11174 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11175 intel_crtc_disable(&intel_crtc->base);
11176
11177 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11178 if (intel_crtc->base.enabled)
11179 dev_priv->display.crtc_disable(&intel_crtc->base);
11180 }
11181
11182 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11183 * to set it here already despite that we pass it down the callchain.
11184 */
11185 if (modeset_pipes) {
11186 crtc->mode = *mode;
11187 /* mode_set/enable/disable functions rely on a correct pipe
11188 * config. */
11189 to_intel_crtc(crtc)->config = *pipe_config;
11190 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11191
11192 /*
11193 * Calculate and store various constants which
11194 * are later needed by vblank and swap-completion
11195 * timestamping. They are derived from true hwmode.
11196 */
11197 drm_calc_timestamping_constants(crtc,
11198 &pipe_config->adjusted_mode);
11199 }
11200
11201 /* Only after disabling all output pipelines that will be changed can we
11202 * update the the output configuration. */
11203 intel_modeset_update_state(dev, prepare_pipes);
11204
11205 if (dev_priv->display.modeset_global_resources)
11206 dev_priv->display.modeset_global_resources(dev);
11207
11208 /* Set up the DPLL and any encoders state that needs to adjust or depend
11209 * on the DPLL.
11210 */
11211 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11212 struct drm_framebuffer *old_fb = crtc->primary->fb;
11213 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11214 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11215
11216 mutex_lock(&dev->struct_mutex);
11217 ret = intel_pin_and_fence_fb_obj(dev,
11218 obj,
11219 NULL);
11220 if (ret != 0) {
11221 DRM_ERROR("pin & fence failed\n");
11222 mutex_unlock(&dev->struct_mutex);
11223 goto done;
11224 }
11225 if (old_fb)
11226 intel_unpin_fb_obj(old_obj);
11227 i915_gem_track_fb(old_obj, obj,
11228 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11229 mutex_unlock(&dev->struct_mutex);
11230
11231 crtc->primary->fb = fb;
11232 crtc->x = x;
11233 crtc->y = y;
11234
11235 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11236 x, y, fb);
11237 if (ret)
11238 goto done;
11239 }
11240
11241 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11242 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11243 update_scanline_offset(intel_crtc);
11244
11245 dev_priv->display.crtc_enable(&intel_crtc->base);
11246 }
11247
11248 /* FIXME: add subpixel order */
11249 done:
11250 if (ret && crtc->enabled)
11251 crtc->mode = *saved_mode;
11252
11253 out:
11254 kfree(pipe_config);
11255 kfree(saved_mode);
11256 return ret;
11257 }
11258
11259 static int intel_set_mode(struct drm_crtc *crtc,
11260 struct drm_display_mode *mode,
11261 int x, int y, struct drm_framebuffer *fb)
11262 {
11263 int ret;
11264
11265 ret = __intel_set_mode(crtc, mode, x, y, fb);
11266
11267 if (ret == 0)
11268 intel_modeset_check_state(crtc->dev);
11269
11270 return ret;
11271 }
11272
11273 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11274 {
11275 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11276 }
11277
11278 #undef for_each_intel_crtc_masked
11279
11280 static void intel_set_config_free(struct intel_set_config *config)
11281 {
11282 if (!config)
11283 return;
11284
11285 kfree(config->save_connector_encoders);
11286 kfree(config->save_encoder_crtcs);
11287 kfree(config->save_crtc_enabled);
11288 kfree(config);
11289 }
11290
11291 static int intel_set_config_save_state(struct drm_device *dev,
11292 struct intel_set_config *config)
11293 {
11294 struct drm_crtc *crtc;
11295 struct drm_encoder *encoder;
11296 struct drm_connector *connector;
11297 int count;
11298
11299 config->save_crtc_enabled =
11300 kcalloc(dev->mode_config.num_crtc,
11301 sizeof(bool), GFP_KERNEL);
11302 if (!config->save_crtc_enabled)
11303 return -ENOMEM;
11304
11305 config->save_encoder_crtcs =
11306 kcalloc(dev->mode_config.num_encoder,
11307 sizeof(struct drm_crtc *), GFP_KERNEL);
11308 if (!config->save_encoder_crtcs)
11309 return -ENOMEM;
11310
11311 config->save_connector_encoders =
11312 kcalloc(dev->mode_config.num_connector,
11313 sizeof(struct drm_encoder *), GFP_KERNEL);
11314 if (!config->save_connector_encoders)
11315 return -ENOMEM;
11316
11317 /* Copy data. Note that driver private data is not affected.
11318 * Should anything bad happen only the expected state is
11319 * restored, not the drivers personal bookkeeping.
11320 */
11321 count = 0;
11322 for_each_crtc(dev, crtc) {
11323 config->save_crtc_enabled[count++] = crtc->enabled;
11324 }
11325
11326 count = 0;
11327 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11328 config->save_encoder_crtcs[count++] = encoder->crtc;
11329 }
11330
11331 count = 0;
11332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11333 config->save_connector_encoders[count++] = connector->encoder;
11334 }
11335
11336 return 0;
11337 }
11338
11339 static void intel_set_config_restore_state(struct drm_device *dev,
11340 struct intel_set_config *config)
11341 {
11342 struct intel_crtc *crtc;
11343 struct intel_encoder *encoder;
11344 struct intel_connector *connector;
11345 int count;
11346
11347 count = 0;
11348 for_each_intel_crtc(dev, crtc) {
11349 crtc->new_enabled = config->save_crtc_enabled[count++];
11350
11351 if (crtc->new_enabled)
11352 crtc->new_config = &crtc->config;
11353 else
11354 crtc->new_config = NULL;
11355 }
11356
11357 count = 0;
11358 for_each_intel_encoder(dev, encoder) {
11359 encoder->new_crtc =
11360 to_intel_crtc(config->save_encoder_crtcs[count++]);
11361 }
11362
11363 count = 0;
11364 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11365 connector->new_encoder =
11366 to_intel_encoder(config->save_connector_encoders[count++]);
11367 }
11368 }
11369
11370 static bool
11371 is_crtc_connector_off(struct drm_mode_set *set)
11372 {
11373 int i;
11374
11375 if (set->num_connectors == 0)
11376 return false;
11377
11378 if (WARN_ON(set->connectors == NULL))
11379 return false;
11380
11381 for (i = 0; i < set->num_connectors; i++)
11382 if (set->connectors[i]->encoder &&
11383 set->connectors[i]->encoder->crtc == set->crtc &&
11384 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11385 return true;
11386
11387 return false;
11388 }
11389
11390 static void
11391 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11392 struct intel_set_config *config)
11393 {
11394
11395 /* We should be able to check here if the fb has the same properties
11396 * and then just flip_or_move it */
11397 if (is_crtc_connector_off(set)) {
11398 config->mode_changed = true;
11399 } else if (set->crtc->primary->fb != set->fb) {
11400 /*
11401 * If we have no fb, we can only flip as long as the crtc is
11402 * active, otherwise we need a full mode set. The crtc may
11403 * be active if we've only disabled the primary plane, or
11404 * in fastboot situations.
11405 */
11406 if (set->crtc->primary->fb == NULL) {
11407 struct intel_crtc *intel_crtc =
11408 to_intel_crtc(set->crtc);
11409
11410 if (intel_crtc->active) {
11411 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11412 config->fb_changed = true;
11413 } else {
11414 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11415 config->mode_changed = true;
11416 }
11417 } else if (set->fb == NULL) {
11418 config->mode_changed = true;
11419 } else if (set->fb->pixel_format !=
11420 set->crtc->primary->fb->pixel_format) {
11421 config->mode_changed = true;
11422 } else {
11423 config->fb_changed = true;
11424 }
11425 }
11426
11427 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11428 config->fb_changed = true;
11429
11430 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11431 DRM_DEBUG_KMS("modes are different, full mode set\n");
11432 drm_mode_debug_printmodeline(&set->crtc->mode);
11433 drm_mode_debug_printmodeline(set->mode);
11434 config->mode_changed = true;
11435 }
11436
11437 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11438 set->crtc->base.id, config->mode_changed, config->fb_changed);
11439 }
11440
11441 static int
11442 intel_modeset_stage_output_state(struct drm_device *dev,
11443 struct drm_mode_set *set,
11444 struct intel_set_config *config)
11445 {
11446 struct intel_connector *connector;
11447 struct intel_encoder *encoder;
11448 struct intel_crtc *crtc;
11449 int ro;
11450
11451 /* The upper layers ensure that we either disable a crtc or have a list
11452 * of connectors. For paranoia, double-check this. */
11453 WARN_ON(!set->fb && (set->num_connectors != 0));
11454 WARN_ON(set->fb && (set->num_connectors == 0));
11455
11456 list_for_each_entry(connector, &dev->mode_config.connector_list,
11457 base.head) {
11458 /* Otherwise traverse passed in connector list and get encoders
11459 * for them. */
11460 for (ro = 0; ro < set->num_connectors; ro++) {
11461 if (set->connectors[ro] == &connector->base) {
11462 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11463 break;
11464 }
11465 }
11466
11467 /* If we disable the crtc, disable all its connectors. Also, if
11468 * the connector is on the changing crtc but not on the new
11469 * connector list, disable it. */
11470 if ((!set->fb || ro == set->num_connectors) &&
11471 connector->base.encoder &&
11472 connector->base.encoder->crtc == set->crtc) {
11473 connector->new_encoder = NULL;
11474
11475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11476 connector->base.base.id,
11477 connector->base.name);
11478 }
11479
11480
11481 if (&connector->new_encoder->base != connector->base.encoder) {
11482 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11483 config->mode_changed = true;
11484 }
11485 }
11486 /* connector->new_encoder is now updated for all connectors. */
11487
11488 /* Update crtc of enabled connectors. */
11489 list_for_each_entry(connector, &dev->mode_config.connector_list,
11490 base.head) {
11491 struct drm_crtc *new_crtc;
11492
11493 if (!connector->new_encoder)
11494 continue;
11495
11496 new_crtc = connector->new_encoder->base.crtc;
11497
11498 for (ro = 0; ro < set->num_connectors; ro++) {
11499 if (set->connectors[ro] == &connector->base)
11500 new_crtc = set->crtc;
11501 }
11502
11503 /* Make sure the new CRTC will work with the encoder */
11504 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11505 new_crtc)) {
11506 return -EINVAL;
11507 }
11508 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11509
11510 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11511 connector->base.base.id,
11512 connector->base.name,
11513 new_crtc->base.id);
11514 }
11515
11516 /* Check for any encoders that needs to be disabled. */
11517 for_each_intel_encoder(dev, encoder) {
11518 int num_connectors = 0;
11519 list_for_each_entry(connector,
11520 &dev->mode_config.connector_list,
11521 base.head) {
11522 if (connector->new_encoder == encoder) {
11523 WARN_ON(!connector->new_encoder->new_crtc);
11524 num_connectors++;
11525 }
11526 }
11527
11528 if (num_connectors == 0)
11529 encoder->new_crtc = NULL;
11530 else if (num_connectors > 1)
11531 return -EINVAL;
11532
11533 /* Only now check for crtc changes so we don't miss encoders
11534 * that will be disabled. */
11535 if (&encoder->new_crtc->base != encoder->base.crtc) {
11536 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11537 config->mode_changed = true;
11538 }
11539 }
11540 /* Now we've also updated encoder->new_crtc for all encoders. */
11541 list_for_each_entry(connector, &dev->mode_config.connector_list,
11542 base.head) {
11543 if (connector->new_encoder)
11544 if (connector->new_encoder != connector->encoder)
11545 connector->encoder = connector->new_encoder;
11546 }
11547 for_each_intel_crtc(dev, crtc) {
11548 crtc->new_enabled = false;
11549
11550 for_each_intel_encoder(dev, encoder) {
11551 if (encoder->new_crtc == crtc) {
11552 crtc->new_enabled = true;
11553 break;
11554 }
11555 }
11556
11557 if (crtc->new_enabled != crtc->base.enabled) {
11558 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11559 crtc->new_enabled ? "en" : "dis");
11560 config->mode_changed = true;
11561 }
11562
11563 if (crtc->new_enabled)
11564 crtc->new_config = &crtc->config;
11565 else
11566 crtc->new_config = NULL;
11567 }
11568
11569 return 0;
11570 }
11571
11572 static void disable_crtc_nofb(struct intel_crtc *crtc)
11573 {
11574 struct drm_device *dev = crtc->base.dev;
11575 struct intel_encoder *encoder;
11576 struct intel_connector *connector;
11577
11578 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11579 pipe_name(crtc->pipe));
11580
11581 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11582 if (connector->new_encoder &&
11583 connector->new_encoder->new_crtc == crtc)
11584 connector->new_encoder = NULL;
11585 }
11586
11587 for_each_intel_encoder(dev, encoder) {
11588 if (encoder->new_crtc == crtc)
11589 encoder->new_crtc = NULL;
11590 }
11591
11592 crtc->new_enabled = false;
11593 crtc->new_config = NULL;
11594 }
11595
11596 static int intel_crtc_set_config(struct drm_mode_set *set)
11597 {
11598 struct drm_device *dev;
11599 struct drm_mode_set save_set;
11600 struct intel_set_config *config;
11601 int ret;
11602
11603 BUG_ON(!set);
11604 BUG_ON(!set->crtc);
11605 BUG_ON(!set->crtc->helper_private);
11606
11607 /* Enforce sane interface api - has been abused by the fb helper. */
11608 BUG_ON(!set->mode && set->fb);
11609 BUG_ON(set->fb && set->num_connectors == 0);
11610
11611 if (set->fb) {
11612 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11613 set->crtc->base.id, set->fb->base.id,
11614 (int)set->num_connectors, set->x, set->y);
11615 } else {
11616 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11617 }
11618
11619 dev = set->crtc->dev;
11620
11621 ret = -ENOMEM;
11622 config = kzalloc(sizeof(*config), GFP_KERNEL);
11623 if (!config)
11624 goto out_config;
11625
11626 ret = intel_set_config_save_state(dev, config);
11627 if (ret)
11628 goto out_config;
11629
11630 save_set.crtc = set->crtc;
11631 save_set.mode = &set->crtc->mode;
11632 save_set.x = set->crtc->x;
11633 save_set.y = set->crtc->y;
11634 save_set.fb = set->crtc->primary->fb;
11635
11636 /* Compute whether we need a full modeset, only an fb base update or no
11637 * change at all. In the future we might also check whether only the
11638 * mode changed, e.g. for LVDS where we only change the panel fitter in
11639 * such cases. */
11640 intel_set_config_compute_mode_changes(set, config);
11641
11642 ret = intel_modeset_stage_output_state(dev, set, config);
11643 if (ret)
11644 goto fail;
11645
11646 if (config->mode_changed) {
11647 ret = intel_set_mode(set->crtc, set->mode,
11648 set->x, set->y, set->fb);
11649 } else if (config->fb_changed) {
11650 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11651
11652 intel_crtc_wait_for_pending_flips(set->crtc);
11653
11654 ret = intel_pipe_set_base(set->crtc,
11655 set->x, set->y, set->fb);
11656
11657 /*
11658 * We need to make sure the primary plane is re-enabled if it
11659 * has previously been turned off.
11660 */
11661 if (!intel_crtc->primary_enabled && ret == 0) {
11662 WARN_ON(!intel_crtc->active);
11663 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11664 }
11665
11666 /*
11667 * In the fastboot case this may be our only check of the
11668 * state after boot. It would be better to only do it on
11669 * the first update, but we don't have a nice way of doing that
11670 * (and really, set_config isn't used much for high freq page
11671 * flipping, so increasing its cost here shouldn't be a big
11672 * deal).
11673 */
11674 if (i915.fastboot && ret == 0)
11675 intel_modeset_check_state(set->crtc->dev);
11676 }
11677
11678 if (ret) {
11679 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11680 set->crtc->base.id, ret);
11681 fail:
11682 intel_set_config_restore_state(dev, config);
11683
11684 /*
11685 * HACK: if the pipe was on, but we didn't have a framebuffer,
11686 * force the pipe off to avoid oopsing in the modeset code
11687 * due to fb==NULL. This should only happen during boot since
11688 * we don't yet reconstruct the FB from the hardware state.
11689 */
11690 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11691 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11692
11693 /* Try to restore the config */
11694 if (config->mode_changed &&
11695 intel_set_mode(save_set.crtc, save_set.mode,
11696 save_set.x, save_set.y, save_set.fb))
11697 DRM_ERROR("failed to restore config after modeset failure\n");
11698 }
11699
11700 out_config:
11701 intel_set_config_free(config);
11702 return ret;
11703 }
11704
11705 static const struct drm_crtc_funcs intel_crtc_funcs = {
11706 .gamma_set = intel_crtc_gamma_set,
11707 .set_config = intel_crtc_set_config,
11708 .destroy = intel_crtc_destroy,
11709 .page_flip = intel_crtc_page_flip,
11710 };
11711
11712 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11713 struct intel_shared_dpll *pll,
11714 struct intel_dpll_hw_state *hw_state)
11715 {
11716 uint32_t val;
11717
11718 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11719 return false;
11720
11721 val = I915_READ(PCH_DPLL(pll->id));
11722 hw_state->dpll = val;
11723 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11724 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11725
11726 return val & DPLL_VCO_ENABLE;
11727 }
11728
11729 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11730 struct intel_shared_dpll *pll)
11731 {
11732 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11733 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11734 }
11735
11736 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11737 struct intel_shared_dpll *pll)
11738 {
11739 /* PCH refclock must be enabled first */
11740 ibx_assert_pch_refclk_enabled(dev_priv);
11741
11742 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11743
11744 /* Wait for the clocks to stabilize. */
11745 POSTING_READ(PCH_DPLL(pll->id));
11746 udelay(150);
11747
11748 /* The pixel multiplier can only be updated once the
11749 * DPLL is enabled and the clocks are stable.
11750 *
11751 * So write it again.
11752 */
11753 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11754 POSTING_READ(PCH_DPLL(pll->id));
11755 udelay(200);
11756 }
11757
11758 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11759 struct intel_shared_dpll *pll)
11760 {
11761 struct drm_device *dev = dev_priv->dev;
11762 struct intel_crtc *crtc;
11763
11764 /* Make sure no transcoder isn't still depending on us. */
11765 for_each_intel_crtc(dev, crtc) {
11766 if (intel_crtc_to_shared_dpll(crtc) == pll)
11767 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11768 }
11769
11770 I915_WRITE(PCH_DPLL(pll->id), 0);
11771 POSTING_READ(PCH_DPLL(pll->id));
11772 udelay(200);
11773 }
11774
11775 static char *ibx_pch_dpll_names[] = {
11776 "PCH DPLL A",
11777 "PCH DPLL B",
11778 };
11779
11780 static void ibx_pch_dpll_init(struct drm_device *dev)
11781 {
11782 struct drm_i915_private *dev_priv = dev->dev_private;
11783 int i;
11784
11785 dev_priv->num_shared_dpll = 2;
11786
11787 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11788 dev_priv->shared_dplls[i].id = i;
11789 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11790 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11791 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11792 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11793 dev_priv->shared_dplls[i].get_hw_state =
11794 ibx_pch_dpll_get_hw_state;
11795 }
11796 }
11797
11798 static void intel_shared_dpll_init(struct drm_device *dev)
11799 {
11800 struct drm_i915_private *dev_priv = dev->dev_private;
11801
11802 if (HAS_DDI(dev))
11803 intel_ddi_pll_init(dev);
11804 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11805 ibx_pch_dpll_init(dev);
11806 else
11807 dev_priv->num_shared_dpll = 0;
11808
11809 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11810 }
11811
11812 static int
11813 intel_primary_plane_disable(struct drm_plane *plane)
11814 {
11815 struct drm_device *dev = plane->dev;
11816 struct intel_crtc *intel_crtc;
11817
11818 if (!plane->fb)
11819 return 0;
11820
11821 BUG_ON(!plane->crtc);
11822
11823 intel_crtc = to_intel_crtc(plane->crtc);
11824
11825 /*
11826 * Even though we checked plane->fb above, it's still possible that
11827 * the primary plane has been implicitly disabled because the crtc
11828 * coordinates given weren't visible, or because we detected
11829 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11830 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11831 * In either case, we need to unpin the FB and let the fb pointer get
11832 * updated, but otherwise we don't need to touch the hardware.
11833 */
11834 if (!intel_crtc->primary_enabled)
11835 goto disable_unpin;
11836
11837 intel_crtc_wait_for_pending_flips(plane->crtc);
11838 intel_disable_primary_hw_plane(plane, plane->crtc);
11839
11840 disable_unpin:
11841 mutex_lock(&dev->struct_mutex);
11842 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11843 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11844 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11845 mutex_unlock(&dev->struct_mutex);
11846 plane->fb = NULL;
11847
11848 return 0;
11849 }
11850
11851 static int
11852 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11853 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11854 unsigned int crtc_w, unsigned int crtc_h,
11855 uint32_t src_x, uint32_t src_y,
11856 uint32_t src_w, uint32_t src_h)
11857 {
11858 struct drm_device *dev = crtc->dev;
11859 struct drm_i915_private *dev_priv = dev->dev_private;
11860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11861 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11862 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11863 struct drm_rect dest = {
11864 /* integer pixels */
11865 .x1 = crtc_x,
11866 .y1 = crtc_y,
11867 .x2 = crtc_x + crtc_w,
11868 .y2 = crtc_y + crtc_h,
11869 };
11870 struct drm_rect src = {
11871 /* 16.16 fixed point */
11872 .x1 = src_x,
11873 .y1 = src_y,
11874 .x2 = src_x + src_w,
11875 .y2 = src_y + src_h,
11876 };
11877 const struct drm_rect clip = {
11878 /* integer pixels */
11879 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11880 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11881 };
11882 const struct {
11883 int crtc_x, crtc_y;
11884 unsigned int crtc_w, crtc_h;
11885 uint32_t src_x, src_y, src_w, src_h;
11886 } orig = {
11887 .crtc_x = crtc_x,
11888 .crtc_y = crtc_y,
11889 .crtc_w = crtc_w,
11890 .crtc_h = crtc_h,
11891 .src_x = src_x,
11892 .src_y = src_y,
11893 .src_w = src_w,
11894 .src_h = src_h,
11895 };
11896 struct intel_plane *intel_plane = to_intel_plane(plane);
11897 bool visible;
11898 int ret;
11899
11900 ret = drm_plane_helper_check_update(plane, crtc, fb,
11901 &src, &dest, &clip,
11902 DRM_PLANE_HELPER_NO_SCALING,
11903 DRM_PLANE_HELPER_NO_SCALING,
11904 false, true, &visible);
11905
11906 if (ret)
11907 return ret;
11908
11909 /*
11910 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11911 * updating the fb pointer, and returning without touching the
11912 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11913 * turn on the display with all planes setup as desired.
11914 */
11915 if (!crtc->enabled) {
11916 mutex_lock(&dev->struct_mutex);
11917
11918 /*
11919 * If we already called setplane while the crtc was disabled,
11920 * we may have an fb pinned; unpin it.
11921 */
11922 if (plane->fb)
11923 intel_unpin_fb_obj(old_obj);
11924
11925 i915_gem_track_fb(old_obj, obj,
11926 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11927
11928 /* Pin and return without programming hardware */
11929 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11930 mutex_unlock(&dev->struct_mutex);
11931
11932 return ret;
11933 }
11934
11935 intel_crtc_wait_for_pending_flips(crtc);
11936
11937 /*
11938 * If clipping results in a non-visible primary plane, we'll disable
11939 * the primary plane. Note that this is a bit different than what
11940 * happens if userspace explicitly disables the plane by passing fb=0
11941 * because plane->fb still gets set and pinned.
11942 */
11943 if (!visible) {
11944 mutex_lock(&dev->struct_mutex);
11945
11946 /*
11947 * Try to pin the new fb first so that we can bail out if we
11948 * fail.
11949 */
11950 if (plane->fb != fb) {
11951 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11952 if (ret) {
11953 mutex_unlock(&dev->struct_mutex);
11954 return ret;
11955 }
11956 }
11957
11958 i915_gem_track_fb(old_obj, obj,
11959 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11960
11961 if (intel_crtc->primary_enabled)
11962 intel_disable_primary_hw_plane(plane, crtc);
11963
11964
11965 if (plane->fb != fb)
11966 if (plane->fb)
11967 intel_unpin_fb_obj(old_obj);
11968
11969 mutex_unlock(&dev->struct_mutex);
11970
11971 } else {
11972 if (intel_crtc && intel_crtc->active &&
11973 intel_crtc->primary_enabled) {
11974 /*
11975 * FBC does not work on some platforms for rotated
11976 * planes, so disable it when rotation is not 0 and
11977 * update it when rotation is set back to 0.
11978 *
11979 * FIXME: This is redundant with the fbc update done in
11980 * the primary plane enable function except that that
11981 * one is done too late. We eventually need to unify
11982 * this.
11983 */
11984 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11985 dev_priv->fbc.plane == intel_crtc->plane &&
11986 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11987 intel_disable_fbc(dev);
11988 }
11989 }
11990 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11991 if (ret)
11992 return ret;
11993
11994 if (!intel_crtc->primary_enabled)
11995 intel_enable_primary_hw_plane(plane, crtc);
11996 }
11997
11998 intel_plane->crtc_x = orig.crtc_x;
11999 intel_plane->crtc_y = orig.crtc_y;
12000 intel_plane->crtc_w = orig.crtc_w;
12001 intel_plane->crtc_h = orig.crtc_h;
12002 intel_plane->src_x = orig.src_x;
12003 intel_plane->src_y = orig.src_y;
12004 intel_plane->src_w = orig.src_w;
12005 intel_plane->src_h = orig.src_h;
12006 intel_plane->obj = obj;
12007
12008 return 0;
12009 }
12010
12011 /* Common destruction function for both primary and cursor planes */
12012 static void intel_plane_destroy(struct drm_plane *plane)
12013 {
12014 struct intel_plane *intel_plane = to_intel_plane(plane);
12015 drm_plane_cleanup(plane);
12016 kfree(intel_plane);
12017 }
12018
12019 static const struct drm_plane_funcs intel_primary_plane_funcs = {
12020 .update_plane = intel_primary_plane_setplane,
12021 .disable_plane = intel_primary_plane_disable,
12022 .destroy = intel_plane_destroy,
12023 .set_property = intel_plane_set_property
12024 };
12025
12026 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12027 int pipe)
12028 {
12029 struct intel_plane *primary;
12030 const uint32_t *intel_primary_formats;
12031 int num_formats;
12032
12033 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12034 if (primary == NULL)
12035 return NULL;
12036
12037 primary->can_scale = false;
12038 primary->max_downscale = 1;
12039 primary->pipe = pipe;
12040 primary->plane = pipe;
12041 primary->rotation = BIT(DRM_ROTATE_0);
12042 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12043 primary->plane = !pipe;
12044
12045 if (INTEL_INFO(dev)->gen <= 3) {
12046 intel_primary_formats = intel_primary_formats_gen2;
12047 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12048 } else {
12049 intel_primary_formats = intel_primary_formats_gen4;
12050 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12051 }
12052
12053 drm_universal_plane_init(dev, &primary->base, 0,
12054 &intel_primary_plane_funcs,
12055 intel_primary_formats, num_formats,
12056 DRM_PLANE_TYPE_PRIMARY);
12057
12058 if (INTEL_INFO(dev)->gen >= 4) {
12059 if (!dev->mode_config.rotation_property)
12060 dev->mode_config.rotation_property =
12061 drm_mode_create_rotation_property(dev,
12062 BIT(DRM_ROTATE_0) |
12063 BIT(DRM_ROTATE_180));
12064 if (dev->mode_config.rotation_property)
12065 drm_object_attach_property(&primary->base.base,
12066 dev->mode_config.rotation_property,
12067 primary->rotation);
12068 }
12069
12070 return &primary->base;
12071 }
12072
12073 static int
12074 intel_cursor_plane_disable(struct drm_plane *plane)
12075 {
12076 if (!plane->fb)
12077 return 0;
12078
12079 BUG_ON(!plane->crtc);
12080
12081 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12082 }
12083
12084 static int
12085 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12086 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12087 unsigned int crtc_w, unsigned int crtc_h,
12088 uint32_t src_x, uint32_t src_y,
12089 uint32_t src_w, uint32_t src_h)
12090 {
12091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12092 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12093 struct drm_i915_gem_object *obj = intel_fb->obj;
12094 struct drm_rect dest = {
12095 /* integer pixels */
12096 .x1 = crtc_x,
12097 .y1 = crtc_y,
12098 .x2 = crtc_x + crtc_w,
12099 .y2 = crtc_y + crtc_h,
12100 };
12101 struct drm_rect src = {
12102 /* 16.16 fixed point */
12103 .x1 = src_x,
12104 .y1 = src_y,
12105 .x2 = src_x + src_w,
12106 .y2 = src_y + src_h,
12107 };
12108 const struct drm_rect clip = {
12109 /* integer pixels */
12110 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12111 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12112 };
12113 bool visible;
12114 int ret;
12115
12116 ret = drm_plane_helper_check_update(plane, crtc, fb,
12117 &src, &dest, &clip,
12118 DRM_PLANE_HELPER_NO_SCALING,
12119 DRM_PLANE_HELPER_NO_SCALING,
12120 true, true, &visible);
12121 if (ret)
12122 return ret;
12123
12124 crtc->cursor_x = crtc_x;
12125 crtc->cursor_y = crtc_y;
12126 if (fb != crtc->cursor->fb) {
12127 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12128 } else {
12129 intel_crtc_update_cursor(crtc, visible);
12130
12131 intel_frontbuffer_flip(crtc->dev,
12132 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12133
12134 return 0;
12135 }
12136 }
12137 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12138 .update_plane = intel_cursor_plane_update,
12139 .disable_plane = intel_cursor_plane_disable,
12140 .destroy = intel_plane_destroy,
12141 };
12142
12143 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12144 int pipe)
12145 {
12146 struct intel_plane *cursor;
12147
12148 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12149 if (cursor == NULL)
12150 return NULL;
12151
12152 cursor->can_scale = false;
12153 cursor->max_downscale = 1;
12154 cursor->pipe = pipe;
12155 cursor->plane = pipe;
12156
12157 drm_universal_plane_init(dev, &cursor->base, 0,
12158 &intel_cursor_plane_funcs,
12159 intel_cursor_formats,
12160 ARRAY_SIZE(intel_cursor_formats),
12161 DRM_PLANE_TYPE_CURSOR);
12162 return &cursor->base;
12163 }
12164
12165 static void intel_crtc_init(struct drm_device *dev, int pipe)
12166 {
12167 struct drm_i915_private *dev_priv = dev->dev_private;
12168 struct intel_crtc *intel_crtc;
12169 struct drm_plane *primary = NULL;
12170 struct drm_plane *cursor = NULL;
12171 int i, ret;
12172
12173 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12174 if (intel_crtc == NULL)
12175 return;
12176
12177 primary = intel_primary_plane_create(dev, pipe);
12178 if (!primary)
12179 goto fail;
12180
12181 cursor = intel_cursor_plane_create(dev, pipe);
12182 if (!cursor)
12183 goto fail;
12184
12185 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12186 cursor, &intel_crtc_funcs);
12187 if (ret)
12188 goto fail;
12189
12190 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12191 for (i = 0; i < 256; i++) {
12192 intel_crtc->lut_r[i] = i;
12193 intel_crtc->lut_g[i] = i;
12194 intel_crtc->lut_b[i] = i;
12195 }
12196
12197 /*
12198 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12199 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12200 */
12201 intel_crtc->pipe = pipe;
12202 intel_crtc->plane = pipe;
12203 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12204 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12205 intel_crtc->plane = !pipe;
12206 }
12207
12208 intel_crtc->cursor_base = ~0;
12209 intel_crtc->cursor_cntl = ~0;
12210 intel_crtc->cursor_size = ~0;
12211
12212 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12213 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12214 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12215 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12216
12217 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12218
12219 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12220 return;
12221
12222 fail:
12223 if (primary)
12224 drm_plane_cleanup(primary);
12225 if (cursor)
12226 drm_plane_cleanup(cursor);
12227 kfree(intel_crtc);
12228 }
12229
12230 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12231 {
12232 struct drm_encoder *encoder = connector->base.encoder;
12233 struct drm_device *dev = connector->base.dev;
12234
12235 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12236
12237 if (!encoder)
12238 return INVALID_PIPE;
12239
12240 return to_intel_crtc(encoder->crtc)->pipe;
12241 }
12242
12243 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12244 struct drm_file *file)
12245 {
12246 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12247 struct drm_crtc *drmmode_crtc;
12248 struct intel_crtc *crtc;
12249
12250 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12251 return -ENODEV;
12252
12253 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12254
12255 if (!drmmode_crtc) {
12256 DRM_ERROR("no such CRTC id\n");
12257 return -ENOENT;
12258 }
12259
12260 crtc = to_intel_crtc(drmmode_crtc);
12261 pipe_from_crtc_id->pipe = crtc->pipe;
12262
12263 return 0;
12264 }
12265
12266 static int intel_encoder_clones(struct intel_encoder *encoder)
12267 {
12268 struct drm_device *dev = encoder->base.dev;
12269 struct intel_encoder *source_encoder;
12270 int index_mask = 0;
12271 int entry = 0;
12272
12273 for_each_intel_encoder(dev, source_encoder) {
12274 if (encoders_cloneable(encoder, source_encoder))
12275 index_mask |= (1 << entry);
12276
12277 entry++;
12278 }
12279
12280 return index_mask;
12281 }
12282
12283 static bool has_edp_a(struct drm_device *dev)
12284 {
12285 struct drm_i915_private *dev_priv = dev->dev_private;
12286
12287 if (!IS_MOBILE(dev))
12288 return false;
12289
12290 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12291 return false;
12292
12293 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12294 return false;
12295
12296 return true;
12297 }
12298
12299 const char *intel_output_name(int output)
12300 {
12301 static const char *names[] = {
12302 [INTEL_OUTPUT_UNUSED] = "Unused",
12303 [INTEL_OUTPUT_ANALOG] = "Analog",
12304 [INTEL_OUTPUT_DVO] = "DVO",
12305 [INTEL_OUTPUT_SDVO] = "SDVO",
12306 [INTEL_OUTPUT_LVDS] = "LVDS",
12307 [INTEL_OUTPUT_TVOUT] = "TV",
12308 [INTEL_OUTPUT_HDMI] = "HDMI",
12309 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12310 [INTEL_OUTPUT_EDP] = "eDP",
12311 [INTEL_OUTPUT_DSI] = "DSI",
12312 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12313 };
12314
12315 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12316 return "Invalid";
12317
12318 return names[output];
12319 }
12320
12321 static bool intel_crt_present(struct drm_device *dev)
12322 {
12323 struct drm_i915_private *dev_priv = dev->dev_private;
12324
12325 if (INTEL_INFO(dev)->gen >= 9)
12326 return false;
12327
12328 if (IS_ULT(dev))
12329 return false;
12330
12331 if (IS_CHERRYVIEW(dev))
12332 return false;
12333
12334 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12335 return false;
12336
12337 return true;
12338 }
12339
12340 static void intel_setup_outputs(struct drm_device *dev)
12341 {
12342 struct drm_i915_private *dev_priv = dev->dev_private;
12343 struct intel_encoder *encoder;
12344 bool dpd_is_edp = false;
12345
12346 intel_lvds_init(dev);
12347
12348 if (intel_crt_present(dev))
12349 intel_crt_init(dev);
12350
12351 if (HAS_DDI(dev)) {
12352 int found;
12353
12354 /* Haswell uses DDI functions to detect digital outputs */
12355 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12356 /* DDI A only supports eDP */
12357 if (found)
12358 intel_ddi_init(dev, PORT_A);
12359
12360 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12361 * register */
12362 found = I915_READ(SFUSE_STRAP);
12363
12364 if (found & SFUSE_STRAP_DDIB_DETECTED)
12365 intel_ddi_init(dev, PORT_B);
12366 if (found & SFUSE_STRAP_DDIC_DETECTED)
12367 intel_ddi_init(dev, PORT_C);
12368 if (found & SFUSE_STRAP_DDID_DETECTED)
12369 intel_ddi_init(dev, PORT_D);
12370 } else if (HAS_PCH_SPLIT(dev)) {
12371 int found;
12372 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12373
12374 if (has_edp_a(dev))
12375 intel_dp_init(dev, DP_A, PORT_A);
12376
12377 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12378 /* PCH SDVOB multiplex with HDMIB */
12379 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12380 if (!found)
12381 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12382 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12383 intel_dp_init(dev, PCH_DP_B, PORT_B);
12384 }
12385
12386 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12387 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12388
12389 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12390 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12391
12392 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12393 intel_dp_init(dev, PCH_DP_C, PORT_C);
12394
12395 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12396 intel_dp_init(dev, PCH_DP_D, PORT_D);
12397 } else if (IS_VALLEYVIEW(dev)) {
12398 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12399 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12400 PORT_B);
12401 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12402 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12403 }
12404
12405 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12406 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12407 PORT_C);
12408 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12409 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12410 }
12411
12412 if (IS_CHERRYVIEW(dev)) {
12413 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12414 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12415 PORT_D);
12416 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12417 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12418 }
12419 }
12420
12421 intel_dsi_init(dev);
12422 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12423 bool found = false;
12424
12425 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12426 DRM_DEBUG_KMS("probing SDVOB\n");
12427 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12428 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12429 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12430 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12431 }
12432
12433 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12434 intel_dp_init(dev, DP_B, PORT_B);
12435 }
12436
12437 /* Before G4X SDVOC doesn't have its own detect register */
12438
12439 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12440 DRM_DEBUG_KMS("probing SDVOC\n");
12441 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12442 }
12443
12444 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12445
12446 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12447 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12448 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12449 }
12450 if (SUPPORTS_INTEGRATED_DP(dev))
12451 intel_dp_init(dev, DP_C, PORT_C);
12452 }
12453
12454 if (SUPPORTS_INTEGRATED_DP(dev) &&
12455 (I915_READ(DP_D) & DP_DETECTED))
12456 intel_dp_init(dev, DP_D, PORT_D);
12457 } else if (IS_GEN2(dev))
12458 intel_dvo_init(dev);
12459
12460 if (SUPPORTS_TV(dev))
12461 intel_tv_init(dev);
12462
12463 intel_edp_psr_init(dev);
12464
12465 for_each_intel_encoder(dev, encoder) {
12466 encoder->base.possible_crtcs = encoder->crtc_mask;
12467 encoder->base.possible_clones =
12468 intel_encoder_clones(encoder);
12469 }
12470
12471 intel_init_pch_refclk(dev);
12472
12473 drm_helper_move_panel_connectors_to_head(dev);
12474 }
12475
12476 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12477 {
12478 struct drm_device *dev = fb->dev;
12479 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12480
12481 drm_framebuffer_cleanup(fb);
12482 mutex_lock(&dev->struct_mutex);
12483 WARN_ON(!intel_fb->obj->framebuffer_references--);
12484 drm_gem_object_unreference(&intel_fb->obj->base);
12485 mutex_unlock(&dev->struct_mutex);
12486 kfree(intel_fb);
12487 }
12488
12489 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12490 struct drm_file *file,
12491 unsigned int *handle)
12492 {
12493 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12494 struct drm_i915_gem_object *obj = intel_fb->obj;
12495
12496 return drm_gem_handle_create(file, &obj->base, handle);
12497 }
12498
12499 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12500 .destroy = intel_user_framebuffer_destroy,
12501 .create_handle = intel_user_framebuffer_create_handle,
12502 };
12503
12504 static int intel_framebuffer_init(struct drm_device *dev,
12505 struct intel_framebuffer *intel_fb,
12506 struct drm_mode_fb_cmd2 *mode_cmd,
12507 struct drm_i915_gem_object *obj)
12508 {
12509 int aligned_height;
12510 int pitch_limit;
12511 int ret;
12512
12513 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12514
12515 if (obj->tiling_mode == I915_TILING_Y) {
12516 DRM_DEBUG("hardware does not support tiling Y\n");
12517 return -EINVAL;
12518 }
12519
12520 if (mode_cmd->pitches[0] & 63) {
12521 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12522 mode_cmd->pitches[0]);
12523 return -EINVAL;
12524 }
12525
12526 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12527 pitch_limit = 32*1024;
12528 } else if (INTEL_INFO(dev)->gen >= 4) {
12529 if (obj->tiling_mode)
12530 pitch_limit = 16*1024;
12531 else
12532 pitch_limit = 32*1024;
12533 } else if (INTEL_INFO(dev)->gen >= 3) {
12534 if (obj->tiling_mode)
12535 pitch_limit = 8*1024;
12536 else
12537 pitch_limit = 16*1024;
12538 } else
12539 /* XXX DSPC is limited to 4k tiled */
12540 pitch_limit = 8*1024;
12541
12542 if (mode_cmd->pitches[0] > pitch_limit) {
12543 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12544 obj->tiling_mode ? "tiled" : "linear",
12545 mode_cmd->pitches[0], pitch_limit);
12546 return -EINVAL;
12547 }
12548
12549 if (obj->tiling_mode != I915_TILING_NONE &&
12550 mode_cmd->pitches[0] != obj->stride) {
12551 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12552 mode_cmd->pitches[0], obj->stride);
12553 return -EINVAL;
12554 }
12555
12556 /* Reject formats not supported by any plane early. */
12557 switch (mode_cmd->pixel_format) {
12558 case DRM_FORMAT_C8:
12559 case DRM_FORMAT_RGB565:
12560 case DRM_FORMAT_XRGB8888:
12561 case DRM_FORMAT_ARGB8888:
12562 break;
12563 case DRM_FORMAT_XRGB1555:
12564 case DRM_FORMAT_ARGB1555:
12565 if (INTEL_INFO(dev)->gen > 3) {
12566 DRM_DEBUG("unsupported pixel format: %s\n",
12567 drm_get_format_name(mode_cmd->pixel_format));
12568 return -EINVAL;
12569 }
12570 break;
12571 case DRM_FORMAT_XBGR8888:
12572 case DRM_FORMAT_ABGR8888:
12573 case DRM_FORMAT_XRGB2101010:
12574 case DRM_FORMAT_ARGB2101010:
12575 case DRM_FORMAT_XBGR2101010:
12576 case DRM_FORMAT_ABGR2101010:
12577 if (INTEL_INFO(dev)->gen < 4) {
12578 DRM_DEBUG("unsupported pixel format: %s\n",
12579 drm_get_format_name(mode_cmd->pixel_format));
12580 return -EINVAL;
12581 }
12582 break;
12583 case DRM_FORMAT_YUYV:
12584 case DRM_FORMAT_UYVY:
12585 case DRM_FORMAT_YVYU:
12586 case DRM_FORMAT_VYUY:
12587 if (INTEL_INFO(dev)->gen < 5) {
12588 DRM_DEBUG("unsupported pixel format: %s\n",
12589 drm_get_format_name(mode_cmd->pixel_format));
12590 return -EINVAL;
12591 }
12592 break;
12593 default:
12594 DRM_DEBUG("unsupported pixel format: %s\n",
12595 drm_get_format_name(mode_cmd->pixel_format));
12596 return -EINVAL;
12597 }
12598
12599 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12600 if (mode_cmd->offsets[0] != 0)
12601 return -EINVAL;
12602
12603 aligned_height = intel_align_height(dev, mode_cmd->height,
12604 obj->tiling_mode);
12605 /* FIXME drm helper for size checks (especially planar formats)? */
12606 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12607 return -EINVAL;
12608
12609 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12610 intel_fb->obj = obj;
12611 intel_fb->obj->framebuffer_references++;
12612
12613 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12614 if (ret) {
12615 DRM_ERROR("framebuffer init failed %d\n", ret);
12616 return ret;
12617 }
12618
12619 return 0;
12620 }
12621
12622 static struct drm_framebuffer *
12623 intel_user_framebuffer_create(struct drm_device *dev,
12624 struct drm_file *filp,
12625 struct drm_mode_fb_cmd2 *mode_cmd)
12626 {
12627 struct drm_i915_gem_object *obj;
12628
12629 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12630 mode_cmd->handles[0]));
12631 if (&obj->base == NULL)
12632 return ERR_PTR(-ENOENT);
12633
12634 return intel_framebuffer_create(dev, mode_cmd, obj);
12635 }
12636
12637 #ifndef CONFIG_DRM_I915_FBDEV
12638 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12639 {
12640 }
12641 #endif
12642
12643 static const struct drm_mode_config_funcs intel_mode_funcs = {
12644 .fb_create = intel_user_framebuffer_create,
12645 .output_poll_changed = intel_fbdev_output_poll_changed,
12646 };
12647
12648 /* Set up chip specific display functions */
12649 static void intel_init_display(struct drm_device *dev)
12650 {
12651 struct drm_i915_private *dev_priv = dev->dev_private;
12652
12653 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12654 dev_priv->display.find_dpll = g4x_find_best_dpll;
12655 else if (IS_CHERRYVIEW(dev))
12656 dev_priv->display.find_dpll = chv_find_best_dpll;
12657 else if (IS_VALLEYVIEW(dev))
12658 dev_priv->display.find_dpll = vlv_find_best_dpll;
12659 else if (IS_PINEVIEW(dev))
12660 dev_priv->display.find_dpll = pnv_find_best_dpll;
12661 else
12662 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12663
12664 if (HAS_DDI(dev)) {
12665 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12666 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12667 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12668 dev_priv->display.crtc_enable = haswell_crtc_enable;
12669 dev_priv->display.crtc_disable = haswell_crtc_disable;
12670 dev_priv->display.off = ironlake_crtc_off;
12671 if (INTEL_INFO(dev)->gen >= 9)
12672 dev_priv->display.update_primary_plane =
12673 skylake_update_primary_plane;
12674 else
12675 dev_priv->display.update_primary_plane =
12676 ironlake_update_primary_plane;
12677 } else if (HAS_PCH_SPLIT(dev)) {
12678 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12679 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12680 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12681 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12682 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12683 dev_priv->display.off = ironlake_crtc_off;
12684 dev_priv->display.update_primary_plane =
12685 ironlake_update_primary_plane;
12686 } else if (IS_VALLEYVIEW(dev)) {
12687 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12688 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12689 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12690 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12691 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12692 dev_priv->display.off = i9xx_crtc_off;
12693 dev_priv->display.update_primary_plane =
12694 i9xx_update_primary_plane;
12695 } else {
12696 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12697 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12698 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12699 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12700 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12701 dev_priv->display.off = i9xx_crtc_off;
12702 dev_priv->display.update_primary_plane =
12703 i9xx_update_primary_plane;
12704 }
12705
12706 /* Returns the core display clock speed */
12707 if (IS_VALLEYVIEW(dev))
12708 dev_priv->display.get_display_clock_speed =
12709 valleyview_get_display_clock_speed;
12710 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12711 dev_priv->display.get_display_clock_speed =
12712 i945_get_display_clock_speed;
12713 else if (IS_I915G(dev))
12714 dev_priv->display.get_display_clock_speed =
12715 i915_get_display_clock_speed;
12716 else if (IS_I945GM(dev) || IS_845G(dev))
12717 dev_priv->display.get_display_clock_speed =
12718 i9xx_misc_get_display_clock_speed;
12719 else if (IS_PINEVIEW(dev))
12720 dev_priv->display.get_display_clock_speed =
12721 pnv_get_display_clock_speed;
12722 else if (IS_I915GM(dev))
12723 dev_priv->display.get_display_clock_speed =
12724 i915gm_get_display_clock_speed;
12725 else if (IS_I865G(dev))
12726 dev_priv->display.get_display_clock_speed =
12727 i865_get_display_clock_speed;
12728 else if (IS_I85X(dev))
12729 dev_priv->display.get_display_clock_speed =
12730 i855_get_display_clock_speed;
12731 else /* 852, 830 */
12732 dev_priv->display.get_display_clock_speed =
12733 i830_get_display_clock_speed;
12734
12735 if (IS_G4X(dev)) {
12736 dev_priv->display.write_eld = g4x_write_eld;
12737 } else if (IS_GEN5(dev)) {
12738 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12739 dev_priv->display.write_eld = ironlake_write_eld;
12740 } else if (IS_GEN6(dev)) {
12741 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12742 dev_priv->display.write_eld = ironlake_write_eld;
12743 dev_priv->display.modeset_global_resources =
12744 snb_modeset_global_resources;
12745 } else if (IS_IVYBRIDGE(dev)) {
12746 /* FIXME: detect B0+ stepping and use auto training */
12747 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12748 dev_priv->display.write_eld = ironlake_write_eld;
12749 dev_priv->display.modeset_global_resources =
12750 ivb_modeset_global_resources;
12751 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12752 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12753 dev_priv->display.write_eld = haswell_write_eld;
12754 dev_priv->display.modeset_global_resources =
12755 haswell_modeset_global_resources;
12756 } else if (IS_VALLEYVIEW(dev)) {
12757 dev_priv->display.modeset_global_resources =
12758 valleyview_modeset_global_resources;
12759 dev_priv->display.write_eld = ironlake_write_eld;
12760 }
12761
12762 /* Default just returns -ENODEV to indicate unsupported */
12763 dev_priv->display.queue_flip = intel_default_queue_flip;
12764
12765 switch (INTEL_INFO(dev)->gen) {
12766 case 2:
12767 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12768 break;
12769
12770 case 3:
12771 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12772 break;
12773
12774 case 4:
12775 case 5:
12776 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12777 break;
12778
12779 case 6:
12780 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12781 break;
12782 case 7:
12783 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12784 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12785 break;
12786 }
12787
12788 intel_panel_init_backlight_funcs(dev);
12789
12790 mutex_init(&dev_priv->pps_mutex);
12791 }
12792
12793 /*
12794 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12795 * resume, or other times. This quirk makes sure that's the case for
12796 * affected systems.
12797 */
12798 static void quirk_pipea_force(struct drm_device *dev)
12799 {
12800 struct drm_i915_private *dev_priv = dev->dev_private;
12801
12802 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12803 DRM_INFO("applying pipe a force quirk\n");
12804 }
12805
12806 static void quirk_pipeb_force(struct drm_device *dev)
12807 {
12808 struct drm_i915_private *dev_priv = dev->dev_private;
12809
12810 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12811 DRM_INFO("applying pipe b force quirk\n");
12812 }
12813
12814 /*
12815 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12816 */
12817 static void quirk_ssc_force_disable(struct drm_device *dev)
12818 {
12819 struct drm_i915_private *dev_priv = dev->dev_private;
12820 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12821 DRM_INFO("applying lvds SSC disable quirk\n");
12822 }
12823
12824 /*
12825 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12826 * brightness value
12827 */
12828 static void quirk_invert_brightness(struct drm_device *dev)
12829 {
12830 struct drm_i915_private *dev_priv = dev->dev_private;
12831 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12832 DRM_INFO("applying inverted panel brightness quirk\n");
12833 }
12834
12835 /* Some VBT's incorrectly indicate no backlight is present */
12836 static void quirk_backlight_present(struct drm_device *dev)
12837 {
12838 struct drm_i915_private *dev_priv = dev->dev_private;
12839 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12840 DRM_INFO("applying backlight present quirk\n");
12841 }
12842
12843 struct intel_quirk {
12844 int device;
12845 int subsystem_vendor;
12846 int subsystem_device;
12847 void (*hook)(struct drm_device *dev);
12848 };
12849
12850 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12851 struct intel_dmi_quirk {
12852 void (*hook)(struct drm_device *dev);
12853 const struct dmi_system_id (*dmi_id_list)[];
12854 };
12855
12856 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12857 {
12858 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12859 return 1;
12860 }
12861
12862 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12863 {
12864 .dmi_id_list = &(const struct dmi_system_id[]) {
12865 {
12866 .callback = intel_dmi_reverse_brightness,
12867 .ident = "NCR Corporation",
12868 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12869 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12870 },
12871 },
12872 { } /* terminating entry */
12873 },
12874 .hook = quirk_invert_brightness,
12875 },
12876 };
12877
12878 static struct intel_quirk intel_quirks[] = {
12879 /* HP Mini needs pipe A force quirk (LP: #322104) */
12880 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12881
12882 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12883 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12884
12885 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12886 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12887
12888 /* 830 needs to leave pipe A & dpll A up */
12889 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12890
12891 /* 830 needs to leave pipe B & dpll B up */
12892 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12893
12894 /* Lenovo U160 cannot use SSC on LVDS */
12895 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12896
12897 /* Sony Vaio Y cannot use SSC on LVDS */
12898 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12899
12900 /* Acer Aspire 5734Z must invert backlight brightness */
12901 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12902
12903 /* Acer/eMachines G725 */
12904 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12905
12906 /* Acer/eMachines e725 */
12907 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12908
12909 /* Acer/Packard Bell NCL20 */
12910 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12911
12912 /* Acer Aspire 4736Z */
12913 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12914
12915 /* Acer Aspire 5336 */
12916 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12917
12918 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12919 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12920
12921 /* Acer C720 Chromebook (Core i3 4005U) */
12922 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12923
12924 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12925 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12926
12927 /* HP Chromebook 14 (Celeron 2955U) */
12928 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12929 };
12930
12931 static void intel_init_quirks(struct drm_device *dev)
12932 {
12933 struct pci_dev *d = dev->pdev;
12934 int i;
12935
12936 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12937 struct intel_quirk *q = &intel_quirks[i];
12938
12939 if (d->device == q->device &&
12940 (d->subsystem_vendor == q->subsystem_vendor ||
12941 q->subsystem_vendor == PCI_ANY_ID) &&
12942 (d->subsystem_device == q->subsystem_device ||
12943 q->subsystem_device == PCI_ANY_ID))
12944 q->hook(dev);
12945 }
12946 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12947 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12948 intel_dmi_quirks[i].hook(dev);
12949 }
12950 }
12951
12952 /* Disable the VGA plane that we never use */
12953 static void i915_disable_vga(struct drm_device *dev)
12954 {
12955 struct drm_i915_private *dev_priv = dev->dev_private;
12956 u8 sr1;
12957 u32 vga_reg = i915_vgacntrl_reg(dev);
12958
12959 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12960 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12961 outb(SR01, VGA_SR_INDEX);
12962 sr1 = inb(VGA_SR_DATA);
12963 outb(sr1 | 1<<5, VGA_SR_DATA);
12964 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12965 udelay(300);
12966
12967 /*
12968 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12969 * from S3 without preserving (some of?) the other bits.
12970 */
12971 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12972 POSTING_READ(vga_reg);
12973 }
12974
12975 void intel_modeset_init_hw(struct drm_device *dev)
12976 {
12977 intel_prepare_ddi(dev);
12978
12979 if (IS_VALLEYVIEW(dev))
12980 vlv_update_cdclk(dev);
12981
12982 intel_init_clock_gating(dev);
12983
12984 intel_enable_gt_powersave(dev);
12985 }
12986
12987 void intel_modeset_suspend_hw(struct drm_device *dev)
12988 {
12989 intel_suspend_hw(dev);
12990 }
12991
12992 void intel_modeset_init(struct drm_device *dev)
12993 {
12994 struct drm_i915_private *dev_priv = dev->dev_private;
12995 int sprite, ret;
12996 enum pipe pipe;
12997 struct intel_crtc *crtc;
12998
12999 drm_mode_config_init(dev);
13000
13001 dev->mode_config.min_width = 0;
13002 dev->mode_config.min_height = 0;
13003
13004 dev->mode_config.preferred_depth = 24;
13005 dev->mode_config.prefer_shadow = 1;
13006
13007 dev->mode_config.funcs = &intel_mode_funcs;
13008
13009 intel_init_quirks(dev);
13010
13011 intel_init_pm(dev);
13012
13013 if (INTEL_INFO(dev)->num_pipes == 0)
13014 return;
13015
13016 intel_init_display(dev);
13017
13018 if (IS_GEN2(dev)) {
13019 dev->mode_config.max_width = 2048;
13020 dev->mode_config.max_height = 2048;
13021 } else if (IS_GEN3(dev)) {
13022 dev->mode_config.max_width = 4096;
13023 dev->mode_config.max_height = 4096;
13024 } else {
13025 dev->mode_config.max_width = 8192;
13026 dev->mode_config.max_height = 8192;
13027 }
13028
13029 if (IS_845G(dev) || IS_I865G(dev)) {
13030 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13031 dev->mode_config.cursor_height = 1023;
13032 } else if (IS_GEN2(dev)) {
13033 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13034 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13035 } else {
13036 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13037 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13038 }
13039
13040 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13041
13042 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13043 INTEL_INFO(dev)->num_pipes,
13044 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13045
13046 for_each_pipe(dev_priv, pipe) {
13047 intel_crtc_init(dev, pipe);
13048 for_each_sprite(pipe, sprite) {
13049 ret = intel_plane_init(dev, pipe, sprite);
13050 if (ret)
13051 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13052 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13053 }
13054 }
13055
13056 intel_init_dpio(dev);
13057
13058 intel_shared_dpll_init(dev);
13059
13060 /* save the BIOS value before clobbering it */
13061 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13062 /* Just disable it once at startup */
13063 i915_disable_vga(dev);
13064 intel_setup_outputs(dev);
13065
13066 /* Just in case the BIOS is doing something questionable. */
13067 intel_disable_fbc(dev);
13068
13069 drm_modeset_lock_all(dev);
13070 intel_modeset_setup_hw_state(dev, false);
13071 drm_modeset_unlock_all(dev);
13072
13073 for_each_intel_crtc(dev, crtc) {
13074 if (!crtc->active)
13075 continue;
13076
13077 /*
13078 * Note that reserving the BIOS fb up front prevents us
13079 * from stuffing other stolen allocations like the ring
13080 * on top. This prevents some ugliness at boot time, and
13081 * can even allow for smooth boot transitions if the BIOS
13082 * fb is large enough for the active pipe configuration.
13083 */
13084 if (dev_priv->display.get_plane_config) {
13085 dev_priv->display.get_plane_config(crtc,
13086 &crtc->plane_config);
13087 /*
13088 * If the fb is shared between multiple heads, we'll
13089 * just get the first one.
13090 */
13091 intel_find_plane_obj(crtc, &crtc->plane_config);
13092 }
13093 }
13094 }
13095
13096 static void intel_enable_pipe_a(struct drm_device *dev)
13097 {
13098 struct intel_connector *connector;
13099 struct drm_connector *crt = NULL;
13100 struct intel_load_detect_pipe load_detect_temp;
13101 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13102
13103 /* We can't just switch on the pipe A, we need to set things up with a
13104 * proper mode and output configuration. As a gross hack, enable pipe A
13105 * by enabling the load detect pipe once. */
13106 list_for_each_entry(connector,
13107 &dev->mode_config.connector_list,
13108 base.head) {
13109 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13110 crt = &connector->base;
13111 break;
13112 }
13113 }
13114
13115 if (!crt)
13116 return;
13117
13118 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13119 intel_release_load_detect_pipe(crt, &load_detect_temp);
13120 }
13121
13122 static bool
13123 intel_check_plane_mapping(struct intel_crtc *crtc)
13124 {
13125 struct drm_device *dev = crtc->base.dev;
13126 struct drm_i915_private *dev_priv = dev->dev_private;
13127 u32 reg, val;
13128
13129 if (INTEL_INFO(dev)->num_pipes == 1)
13130 return true;
13131
13132 reg = DSPCNTR(!crtc->plane);
13133 val = I915_READ(reg);
13134
13135 if ((val & DISPLAY_PLANE_ENABLE) &&
13136 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13137 return false;
13138
13139 return true;
13140 }
13141
13142 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13143 {
13144 struct drm_device *dev = crtc->base.dev;
13145 struct drm_i915_private *dev_priv = dev->dev_private;
13146 u32 reg;
13147
13148 /* Clear any frame start delays used for debugging left by the BIOS */
13149 reg = PIPECONF(crtc->config.cpu_transcoder);
13150 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13151
13152 /* restore vblank interrupts to correct state */
13153 if (crtc->active) {
13154 update_scanline_offset(crtc);
13155 drm_vblank_on(dev, crtc->pipe);
13156 } else
13157 drm_vblank_off(dev, crtc->pipe);
13158
13159 /* We need to sanitize the plane -> pipe mapping first because this will
13160 * disable the crtc (and hence change the state) if it is wrong. Note
13161 * that gen4+ has a fixed plane -> pipe mapping. */
13162 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13163 struct intel_connector *connector;
13164 bool plane;
13165
13166 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13167 crtc->base.base.id);
13168
13169 /* Pipe has the wrong plane attached and the plane is active.
13170 * Temporarily change the plane mapping and disable everything
13171 * ... */
13172 plane = crtc->plane;
13173 crtc->plane = !plane;
13174 crtc->primary_enabled = true;
13175 dev_priv->display.crtc_disable(&crtc->base);
13176 crtc->plane = plane;
13177
13178 /* ... and break all links. */
13179 list_for_each_entry(connector, &dev->mode_config.connector_list,
13180 base.head) {
13181 if (connector->encoder->base.crtc != &crtc->base)
13182 continue;
13183
13184 connector->base.dpms = DRM_MODE_DPMS_OFF;
13185 connector->base.encoder = NULL;
13186 }
13187 /* multiple connectors may have the same encoder:
13188 * handle them and break crtc link separately */
13189 list_for_each_entry(connector, &dev->mode_config.connector_list,
13190 base.head)
13191 if (connector->encoder->base.crtc == &crtc->base) {
13192 connector->encoder->base.crtc = NULL;
13193 connector->encoder->connectors_active = false;
13194 }
13195
13196 WARN_ON(crtc->active);
13197 crtc->base.enabled = false;
13198 }
13199
13200 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13201 crtc->pipe == PIPE_A && !crtc->active) {
13202 /* BIOS forgot to enable pipe A, this mostly happens after
13203 * resume. Force-enable the pipe to fix this, the update_dpms
13204 * call below we restore the pipe to the right state, but leave
13205 * the required bits on. */
13206 intel_enable_pipe_a(dev);
13207 }
13208
13209 /* Adjust the state of the output pipe according to whether we
13210 * have active connectors/encoders. */
13211 intel_crtc_update_dpms(&crtc->base);
13212
13213 if (crtc->active != crtc->base.enabled) {
13214 struct intel_encoder *encoder;
13215
13216 /* This can happen either due to bugs in the get_hw_state
13217 * functions or because the pipe is force-enabled due to the
13218 * pipe A quirk. */
13219 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13220 crtc->base.base.id,
13221 crtc->base.enabled ? "enabled" : "disabled",
13222 crtc->active ? "enabled" : "disabled");
13223
13224 crtc->base.enabled = crtc->active;
13225
13226 /* Because we only establish the connector -> encoder ->
13227 * crtc links if something is active, this means the
13228 * crtc is now deactivated. Break the links. connector
13229 * -> encoder links are only establish when things are
13230 * actually up, hence no need to break them. */
13231 WARN_ON(crtc->active);
13232
13233 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13234 WARN_ON(encoder->connectors_active);
13235 encoder->base.crtc = NULL;
13236 }
13237 }
13238
13239 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13240 /*
13241 * We start out with underrun reporting disabled to avoid races.
13242 * For correct bookkeeping mark this on active crtcs.
13243 *
13244 * Also on gmch platforms we dont have any hardware bits to
13245 * disable the underrun reporting. Which means we need to start
13246 * out with underrun reporting disabled also on inactive pipes,
13247 * since otherwise we'll complain about the garbage we read when
13248 * e.g. coming up after runtime pm.
13249 *
13250 * No protection against concurrent access is required - at
13251 * worst a fifo underrun happens which also sets this to false.
13252 */
13253 crtc->cpu_fifo_underrun_disabled = true;
13254 crtc->pch_fifo_underrun_disabled = true;
13255 }
13256 }
13257
13258 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13259 {
13260 struct intel_connector *connector;
13261 struct drm_device *dev = encoder->base.dev;
13262
13263 /* We need to check both for a crtc link (meaning that the
13264 * encoder is active and trying to read from a pipe) and the
13265 * pipe itself being active. */
13266 bool has_active_crtc = encoder->base.crtc &&
13267 to_intel_crtc(encoder->base.crtc)->active;
13268
13269 if (encoder->connectors_active && !has_active_crtc) {
13270 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13271 encoder->base.base.id,
13272 encoder->base.name);
13273
13274 /* Connector is active, but has no active pipe. This is
13275 * fallout from our resume register restoring. Disable
13276 * the encoder manually again. */
13277 if (encoder->base.crtc) {
13278 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13279 encoder->base.base.id,
13280 encoder->base.name);
13281 encoder->disable(encoder);
13282 if (encoder->post_disable)
13283 encoder->post_disable(encoder);
13284 }
13285 encoder->base.crtc = NULL;
13286 encoder->connectors_active = false;
13287
13288 /* Inconsistent output/port/pipe state happens presumably due to
13289 * a bug in one of the get_hw_state functions. Or someplace else
13290 * in our code, like the register restore mess on resume. Clamp
13291 * things to off as a safer default. */
13292 list_for_each_entry(connector,
13293 &dev->mode_config.connector_list,
13294 base.head) {
13295 if (connector->encoder != encoder)
13296 continue;
13297 connector->base.dpms = DRM_MODE_DPMS_OFF;
13298 connector->base.encoder = NULL;
13299 }
13300 }
13301 /* Enabled encoders without active connectors will be fixed in
13302 * the crtc fixup. */
13303 }
13304
13305 void i915_redisable_vga_power_on(struct drm_device *dev)
13306 {
13307 struct drm_i915_private *dev_priv = dev->dev_private;
13308 u32 vga_reg = i915_vgacntrl_reg(dev);
13309
13310 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13311 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13312 i915_disable_vga(dev);
13313 }
13314 }
13315
13316 void i915_redisable_vga(struct drm_device *dev)
13317 {
13318 struct drm_i915_private *dev_priv = dev->dev_private;
13319
13320 /* This function can be called both from intel_modeset_setup_hw_state or
13321 * at a very early point in our resume sequence, where the power well
13322 * structures are not yet restored. Since this function is at a very
13323 * paranoid "someone might have enabled VGA while we were not looking"
13324 * level, just check if the power well is enabled instead of trying to
13325 * follow the "don't touch the power well if we don't need it" policy
13326 * the rest of the driver uses. */
13327 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13328 return;
13329
13330 i915_redisable_vga_power_on(dev);
13331 }
13332
13333 static bool primary_get_hw_state(struct intel_crtc *crtc)
13334 {
13335 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13336
13337 if (!crtc->active)
13338 return false;
13339
13340 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13341 }
13342
13343 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13344 {
13345 struct drm_i915_private *dev_priv = dev->dev_private;
13346 enum pipe pipe;
13347 struct intel_crtc *crtc;
13348 struct intel_encoder *encoder;
13349 struct intel_connector *connector;
13350 int i;
13351
13352 for_each_intel_crtc(dev, crtc) {
13353 memset(&crtc->config, 0, sizeof(crtc->config));
13354
13355 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13356
13357 crtc->active = dev_priv->display.get_pipe_config(crtc,
13358 &crtc->config);
13359
13360 crtc->base.enabled = crtc->active;
13361 crtc->primary_enabled = primary_get_hw_state(crtc);
13362
13363 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13364 crtc->base.base.id,
13365 crtc->active ? "enabled" : "disabled");
13366 }
13367
13368 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13369 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13370
13371 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13372 pll->active = 0;
13373 for_each_intel_crtc(dev, crtc) {
13374 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13375 pll->active++;
13376 }
13377 pll->refcount = pll->active;
13378
13379 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13380 pll->name, pll->refcount, pll->on);
13381
13382 if (pll->refcount)
13383 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13384 }
13385
13386 for_each_intel_encoder(dev, encoder) {
13387 pipe = 0;
13388
13389 if (encoder->get_hw_state(encoder, &pipe)) {
13390 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13391 encoder->base.crtc = &crtc->base;
13392 encoder->get_config(encoder, &crtc->config);
13393 } else {
13394 encoder->base.crtc = NULL;
13395 }
13396
13397 encoder->connectors_active = false;
13398 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13399 encoder->base.base.id,
13400 encoder->base.name,
13401 encoder->base.crtc ? "enabled" : "disabled",
13402 pipe_name(pipe));
13403 }
13404
13405 list_for_each_entry(connector, &dev->mode_config.connector_list,
13406 base.head) {
13407 if (connector->get_hw_state(connector)) {
13408 connector->base.dpms = DRM_MODE_DPMS_ON;
13409 connector->encoder->connectors_active = true;
13410 connector->base.encoder = &connector->encoder->base;
13411 } else {
13412 connector->base.dpms = DRM_MODE_DPMS_OFF;
13413 connector->base.encoder = NULL;
13414 }
13415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13416 connector->base.base.id,
13417 connector->base.name,
13418 connector->base.encoder ? "enabled" : "disabled");
13419 }
13420 }
13421
13422 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13423 * and i915 state tracking structures. */
13424 void intel_modeset_setup_hw_state(struct drm_device *dev,
13425 bool force_restore)
13426 {
13427 struct drm_i915_private *dev_priv = dev->dev_private;
13428 enum pipe pipe;
13429 struct intel_crtc *crtc;
13430 struct intel_encoder *encoder;
13431 int i;
13432
13433 intel_modeset_readout_hw_state(dev);
13434
13435 /*
13436 * Now that we have the config, copy it to each CRTC struct
13437 * Note that this could go away if we move to using crtc_config
13438 * checking everywhere.
13439 */
13440 for_each_intel_crtc(dev, crtc) {
13441 if (crtc->active && i915.fastboot) {
13442 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13443 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13444 crtc->base.base.id);
13445 drm_mode_debug_printmodeline(&crtc->base.mode);
13446 }
13447 }
13448
13449 /* HW state is read out, now we need to sanitize this mess. */
13450 for_each_intel_encoder(dev, encoder) {
13451 intel_sanitize_encoder(encoder);
13452 }
13453
13454 for_each_pipe(dev_priv, pipe) {
13455 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13456 intel_sanitize_crtc(crtc);
13457 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13458 }
13459
13460 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13461 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13462
13463 if (!pll->on || pll->active)
13464 continue;
13465
13466 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13467
13468 pll->disable(dev_priv, pll);
13469 pll->on = false;
13470 }
13471
13472 if (HAS_PCH_SPLIT(dev))
13473 ilk_wm_get_hw_state(dev);
13474
13475 if (force_restore) {
13476 i915_redisable_vga(dev);
13477
13478 /*
13479 * We need to use raw interfaces for restoring state to avoid
13480 * checking (bogus) intermediate states.
13481 */
13482 for_each_pipe(dev_priv, pipe) {
13483 struct drm_crtc *crtc =
13484 dev_priv->pipe_to_crtc_mapping[pipe];
13485
13486 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13487 crtc->primary->fb);
13488 }
13489 } else {
13490 intel_modeset_update_staged_output_state(dev);
13491 }
13492
13493 intel_modeset_check_state(dev);
13494 }
13495
13496 void intel_modeset_gem_init(struct drm_device *dev)
13497 {
13498 struct drm_crtc *c;
13499 struct drm_i915_gem_object *obj;
13500
13501 mutex_lock(&dev->struct_mutex);
13502 intel_init_gt_powersave(dev);
13503 mutex_unlock(&dev->struct_mutex);
13504
13505 intel_modeset_init_hw(dev);
13506
13507 intel_setup_overlay(dev);
13508
13509 /*
13510 * Make sure any fbs we allocated at startup are properly
13511 * pinned & fenced. When we do the allocation it's too early
13512 * for this.
13513 */
13514 mutex_lock(&dev->struct_mutex);
13515 for_each_crtc(dev, c) {
13516 obj = intel_fb_obj(c->primary->fb);
13517 if (obj == NULL)
13518 continue;
13519
13520 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13521 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13522 to_intel_crtc(c)->pipe);
13523 drm_framebuffer_unreference(c->primary->fb);
13524 c->primary->fb = NULL;
13525 }
13526 }
13527 mutex_unlock(&dev->struct_mutex);
13528 }
13529
13530 void intel_connector_unregister(struct intel_connector *intel_connector)
13531 {
13532 struct drm_connector *connector = &intel_connector->base;
13533
13534 intel_panel_destroy_backlight(connector);
13535 drm_connector_unregister(connector);
13536 }
13537
13538 void intel_modeset_cleanup(struct drm_device *dev)
13539 {
13540 struct drm_i915_private *dev_priv = dev->dev_private;
13541 struct drm_connector *connector;
13542
13543 /*
13544 * Interrupts and polling as the first thing to avoid creating havoc.
13545 * Too much stuff here (turning of rps, connectors, ...) would
13546 * experience fancy races otherwise.
13547 */
13548 drm_irq_uninstall(dev);
13549 intel_hpd_cancel_work(dev_priv);
13550 dev_priv->pm._irqs_disabled = true;
13551
13552 /*
13553 * Due to the hpd irq storm handling the hotplug work can re-arm the
13554 * poll handlers. Hence disable polling after hpd handling is shut down.
13555 */
13556 drm_kms_helper_poll_fini(dev);
13557
13558 mutex_lock(&dev->struct_mutex);
13559
13560 intel_unregister_dsm_handler();
13561
13562 intel_disable_fbc(dev);
13563
13564 intel_disable_gt_powersave(dev);
13565
13566 ironlake_teardown_rc6(dev);
13567
13568 mutex_unlock(&dev->struct_mutex);
13569
13570 /* flush any delayed tasks or pending work */
13571 flush_scheduled_work();
13572
13573 /* destroy the backlight and sysfs files before encoders/connectors */
13574 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13575 struct intel_connector *intel_connector;
13576
13577 intel_connector = to_intel_connector(connector);
13578 intel_connector->unregister(intel_connector);
13579 }
13580
13581 drm_mode_config_cleanup(dev);
13582
13583 intel_cleanup_overlay(dev);
13584
13585 mutex_lock(&dev->struct_mutex);
13586 intel_cleanup_gt_powersave(dev);
13587 mutex_unlock(&dev->struct_mutex);
13588 }
13589
13590 /*
13591 * Return which encoder is currently attached for connector.
13592 */
13593 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13594 {
13595 return &intel_attached_encoder(connector)->base;
13596 }
13597
13598 void intel_connector_attach_encoder(struct intel_connector *connector,
13599 struct intel_encoder *encoder)
13600 {
13601 connector->encoder = encoder;
13602 drm_mode_connector_attach_encoder(&connector->base,
13603 &encoder->base);
13604 }
13605
13606 /*
13607 * set vga decode state - true == enable VGA decode
13608 */
13609 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13610 {
13611 struct drm_i915_private *dev_priv = dev->dev_private;
13612 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13613 u16 gmch_ctrl;
13614
13615 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13616 DRM_ERROR("failed to read control word\n");
13617 return -EIO;
13618 }
13619
13620 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13621 return 0;
13622
13623 if (state)
13624 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13625 else
13626 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13627
13628 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13629 DRM_ERROR("failed to write control word\n");
13630 return -EIO;
13631 }
13632
13633 return 0;
13634 }
13635
13636 struct intel_display_error_state {
13637
13638 u32 power_well_driver;
13639
13640 int num_transcoders;
13641
13642 struct intel_cursor_error_state {
13643 u32 control;
13644 u32 position;
13645 u32 base;
13646 u32 size;
13647 } cursor[I915_MAX_PIPES];
13648
13649 struct intel_pipe_error_state {
13650 bool power_domain_on;
13651 u32 source;
13652 u32 stat;
13653 } pipe[I915_MAX_PIPES];
13654
13655 struct intel_plane_error_state {
13656 u32 control;
13657 u32 stride;
13658 u32 size;
13659 u32 pos;
13660 u32 addr;
13661 u32 surface;
13662 u32 tile_offset;
13663 } plane[I915_MAX_PIPES];
13664
13665 struct intel_transcoder_error_state {
13666 bool power_domain_on;
13667 enum transcoder cpu_transcoder;
13668
13669 u32 conf;
13670
13671 u32 htotal;
13672 u32 hblank;
13673 u32 hsync;
13674 u32 vtotal;
13675 u32 vblank;
13676 u32 vsync;
13677 } transcoder[4];
13678 };
13679
13680 struct intel_display_error_state *
13681 intel_display_capture_error_state(struct drm_device *dev)
13682 {
13683 struct drm_i915_private *dev_priv = dev->dev_private;
13684 struct intel_display_error_state *error;
13685 int transcoders[] = {
13686 TRANSCODER_A,
13687 TRANSCODER_B,
13688 TRANSCODER_C,
13689 TRANSCODER_EDP,
13690 };
13691 int i;
13692
13693 if (INTEL_INFO(dev)->num_pipes == 0)
13694 return NULL;
13695
13696 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13697 if (error == NULL)
13698 return NULL;
13699
13700 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13701 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13702
13703 for_each_pipe(dev_priv, i) {
13704 error->pipe[i].power_domain_on =
13705 intel_display_power_enabled_unlocked(dev_priv,
13706 POWER_DOMAIN_PIPE(i));
13707 if (!error->pipe[i].power_domain_on)
13708 continue;
13709
13710 error->cursor[i].control = I915_READ(CURCNTR(i));
13711 error->cursor[i].position = I915_READ(CURPOS(i));
13712 error->cursor[i].base = I915_READ(CURBASE(i));
13713
13714 error->plane[i].control = I915_READ(DSPCNTR(i));
13715 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13716 if (INTEL_INFO(dev)->gen <= 3) {
13717 error->plane[i].size = I915_READ(DSPSIZE(i));
13718 error->plane[i].pos = I915_READ(DSPPOS(i));
13719 }
13720 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13721 error->plane[i].addr = I915_READ(DSPADDR(i));
13722 if (INTEL_INFO(dev)->gen >= 4) {
13723 error->plane[i].surface = I915_READ(DSPSURF(i));
13724 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13725 }
13726
13727 error->pipe[i].source = I915_READ(PIPESRC(i));
13728
13729 if (HAS_GMCH_DISPLAY(dev))
13730 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13731 }
13732
13733 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13734 if (HAS_DDI(dev_priv->dev))
13735 error->num_transcoders++; /* Account for eDP. */
13736
13737 for (i = 0; i < error->num_transcoders; i++) {
13738 enum transcoder cpu_transcoder = transcoders[i];
13739
13740 error->transcoder[i].power_domain_on =
13741 intel_display_power_enabled_unlocked(dev_priv,
13742 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13743 if (!error->transcoder[i].power_domain_on)
13744 continue;
13745
13746 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13747
13748 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13749 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13750 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13751 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13752 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13753 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13754 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13755 }
13756
13757 return error;
13758 }
13759
13760 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13761
13762 void
13763 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13764 struct drm_device *dev,
13765 struct intel_display_error_state *error)
13766 {
13767 struct drm_i915_private *dev_priv = dev->dev_private;
13768 int i;
13769
13770 if (!error)
13771 return;
13772
13773 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13774 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13775 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13776 error->power_well_driver);
13777 for_each_pipe(dev_priv, i) {
13778 err_printf(m, "Pipe [%d]:\n", i);
13779 err_printf(m, " Power: %s\n",
13780 error->pipe[i].power_domain_on ? "on" : "off");
13781 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13782 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13783
13784 err_printf(m, "Plane [%d]:\n", i);
13785 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13786 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13787 if (INTEL_INFO(dev)->gen <= 3) {
13788 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13789 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13790 }
13791 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13792 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13793 if (INTEL_INFO(dev)->gen >= 4) {
13794 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13795 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13796 }
13797
13798 err_printf(m, "Cursor [%d]:\n", i);
13799 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13800 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13801 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13802 }
13803
13804 for (i = 0; i < error->num_transcoders; i++) {
13805 err_printf(m, "CPU transcoder: %c\n",
13806 transcoder_name(error->transcoder[i].cpu_transcoder));
13807 err_printf(m, " Power: %s\n",
13808 error->transcoder[i].power_domain_on ? "on" : "off");
13809 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13810 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13811 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13812 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13813 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13814 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13815 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13816 }
13817 }
13818
13819 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13820 {
13821 struct intel_crtc *crtc;
13822
13823 for_each_intel_crtc(dev, crtc) {
13824 struct intel_unpin_work *work;
13825 unsigned long irqflags;
13826
13827 spin_lock_irqsave(&dev->event_lock, irqflags);
13828
13829 work = crtc->unpin_work;
13830
13831 if (work && work->event &&
13832 work->event->base.file_priv == file) {
13833 kfree(work->event);
13834 work->event = NULL;
13835 }
13836
13837 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13838 }
13839 }
Linux kernel - Deliverables
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