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drm/i915: remove !enabled handling from commit primary plane step
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267 state = true;
1268
1269 if (!intel_display_power_enabled(dev_priv,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271 cur_state = false;
1272 } else {
1273 reg = PIPECONF(cpu_transcoder);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & PIPECONF_ENABLE);
1276 }
1277
1278 WARN(cur_state != state,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, bool state)
1285 {
1286 int reg;
1287 u32 val;
1288 bool cur_state;
1289
1290 reg = DSPCNTR(plane);
1291 val = I915_READ(reg);
1292 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293 WARN(cur_state != state,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe)
1303 {
1304 struct drm_device *dev = dev_priv->dev;
1305 int reg, i;
1306 u32 val;
1307 int cur_pipe;
1308
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev)->gen >= 4) {
1311 reg = DSPCNTR(pipe);
1312 val = I915_READ(reg);
1313 WARN(val & DISPLAY_PLANE_ENABLE,
1314 "plane %c assertion failure, should be disabled but not\n",
1315 plane_name(pipe));
1316 return;
1317 }
1318
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv, i) {
1321 reg = DSPCNTR(i);
1322 val = I915_READ(reg);
1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324 DISPPLANE_SEL_PIPE_SHIFT;
1325 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int reg, sprite;
1336 u32 val;
1337
1338 if (IS_VALLEYVIEW(dev)) {
1339 for_each_sprite(pipe, sprite) {
1340 reg = SPCNTR(pipe, sprite);
1341 val = I915_READ(reg);
1342 WARN(val & SP_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe, sprite), pipe_name(pipe));
1345 }
1346 } else if (INTEL_INFO(dev)->gen >= 7) {
1347 reg = SPRCTL(pipe);
1348 val = I915_READ(reg);
1349 WARN(val & SPRITE_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe), pipe_name(pipe));
1352 } else if (INTEL_INFO(dev)->gen >= 5) {
1353 reg = DVSCNTR(pipe);
1354 val = I915_READ(reg);
1355 WARN(val & DVS_ENABLE,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe), pipe_name(pipe));
1358 }
1359 }
1360
1361 static void assert_vblank_disabled(struct drm_crtc *crtc)
1362 {
1363 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1364 drm_crtc_vblank_put(crtc);
1365 }
1366
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1368 {
1369 u32 val;
1370 bool enabled;
1371
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1373
1374 val = I915_READ(PCH_DREF_CONTROL);
1375 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1376 DREF_SUPERSPREAD_SOURCE_MASK));
1377 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1378 }
1379
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1381 enum pipe pipe)
1382 {
1383 int reg;
1384 u32 val;
1385 bool enabled;
1386
1387 reg = PCH_TRANSCONF(pipe);
1388 val = I915_READ(reg);
1389 enabled = !!(val & TRANS_ENABLE);
1390 WARN(enabled,
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1392 pipe_name(pipe));
1393 }
1394
1395 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe, u32 port_sel, u32 val)
1397 {
1398 if ((val & DP_PORT_EN) == 0)
1399 return false;
1400
1401 if (HAS_PCH_CPT(dev_priv->dev)) {
1402 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1403 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1404 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1405 return false;
1406 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1407 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1408 return false;
1409 } else {
1410 if ((val & DP_PIPE_MASK) != (pipe << 30))
1411 return false;
1412 }
1413 return true;
1414 }
1415
1416 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 val)
1418 {
1419 if ((val & SDVO_ENABLE) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv->dev)) {
1423 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1424 return false;
1425 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1426 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1427 return false;
1428 } else {
1429 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & LVDS_PORT_EN) == 0)
1439 return false;
1440
1441 if (HAS_PCH_CPT(dev_priv->dev)) {
1442 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1443 return false;
1444 } else {
1445 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & ADPA_DAC_ENABLE) == 0)
1455 return false;
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, int reg, u32 port_sel)
1468 {
1469 u32 val = I915_READ(reg);
1470 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg, pipe_name(pipe));
1473
1474 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1475 && (val & DP_PIPEB_SELECT),
1476 "IBX PCH dp port still using transcoder B\n");
1477 }
1478
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, int reg)
1481 {
1482 u32 val = I915_READ(reg);
1483 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg, pipe_name(pipe));
1486
1487 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1488 && (val & SDVO_PIPE_B_SELECT),
1489 "IBX PCH hdmi port still using transcoder B\n");
1490 }
1491
1492 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe)
1494 {
1495 int reg;
1496 u32 val;
1497
1498 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1499 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1500 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1501
1502 reg = PCH_ADPA;
1503 val = I915_READ(reg);
1504 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1506 pipe_name(pipe));
1507
1508 reg = PCH_LVDS;
1509 val = I915_READ(reg);
1510 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1512 pipe_name(pipe));
1513
1514 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1515 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1516 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1517 }
1518
1519 static void intel_init_dpio(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 if (!IS_VALLEYVIEW(dev))
1524 return;
1525
1526 /*
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1530 */
1531 if (IS_CHERRYVIEW(dev)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1534 } else {
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1536 }
1537 }
1538
1539 static void vlv_enable_pll(struct intel_crtc *crtc)
1540 {
1541 struct drm_device *dev = crtc->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 int reg = DPLL(crtc->pipe);
1544 u32 dpll = crtc->config.dpll_hw_state.dpll;
1545
1546 assert_pipe_disabled(dev_priv, crtc->pipe);
1547
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1550
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv->dev))
1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555 I915_WRITE(reg, dpll);
1556 POSTING_READ(reg);
1557 udelay(150);
1558
1559 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1561
1562 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1563 POSTING_READ(DPLL_MD(crtc->pipe));
1564
1565 /* We do this three times for luck */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg, dpll);
1573 POSTING_READ(reg);
1574 udelay(150); /* wait for warmup */
1575 }
1576
1577 static void chv_enable_pll(struct intel_crtc *crtc)
1578 {
1579 struct drm_device *dev = crtc->base.dev;
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 int pipe = crtc->pipe;
1582 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1583 u32 tmp;
1584
1585 assert_pipe_disabled(dev_priv, crtc->pipe);
1586
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1588
1589 mutex_lock(&dev_priv->dpio_lock);
1590
1591 /* Enable back the 10bit clock to display controller */
1592 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1593 tmp |= DPIO_DCLKP_EN;
1594 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1595
1596 /*
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1598 */
1599 udelay(1);
1600
1601 /* Enable PLL */
1602 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1603
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe);
1607
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1610 POSTING_READ(DPLL_MD(pipe));
1611
1612 mutex_unlock(&dev_priv->dpio_lock);
1613 }
1614
1615 static int intel_num_dvo_pipes(struct drm_device *dev)
1616 {
1617 struct intel_crtc *crtc;
1618 int count = 0;
1619
1620 for_each_intel_crtc(dev, crtc)
1621 count += crtc->active &&
1622 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1623
1624 return count;
1625 }
1626
1627 static void i9xx_enable_pll(struct intel_crtc *crtc)
1628 {
1629 struct drm_device *dev = crtc->base.dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 int reg = DPLL(crtc->pipe);
1632 u32 dpll = crtc->config.dpll_hw_state.dpll;
1633
1634 assert_pipe_disabled(dev_priv, crtc->pipe);
1635
1636 /* No really, not for ILK+ */
1637 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1638
1639 /* PLL is protected by panel, make sure we can write it */
1640 if (IS_MOBILE(dev) && !IS_I830(dev))
1641 assert_panel_unlocked(dev_priv, crtc->pipe);
1642
1643 /* Enable DVO 2x clock on both PLLs if necessary */
1644 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1645 /*
1646 * It appears to be important that we don't enable this
1647 * for the current pipe before otherwise configuring the
1648 * PLL. No idea how this should be handled if multiple
1649 * DVO outputs are enabled simultaneosly.
1650 */
1651 dpll |= DPLL_DVO_2X_MODE;
1652 I915_WRITE(DPLL(!crtc->pipe),
1653 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1654 }
1655
1656 /* Wait for the clocks to stabilize. */
1657 POSTING_READ(reg);
1658 udelay(150);
1659
1660 if (INTEL_INFO(dev)->gen >= 4) {
1661 I915_WRITE(DPLL_MD(crtc->pipe),
1662 crtc->config.dpll_hw_state.dpll_md);
1663 } else {
1664 /* The pixel multiplier can only be updated once the
1665 * DPLL is enabled and the clocks are stable.
1666 *
1667 * So write it again.
1668 */
1669 I915_WRITE(reg, dpll);
1670 }
1671
1672 /* We do this three times for luck */
1673 I915_WRITE(reg, dpll);
1674 POSTING_READ(reg);
1675 udelay(150); /* wait for warmup */
1676 I915_WRITE(reg, dpll);
1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
1679 I915_WRITE(reg, dpll);
1680 POSTING_READ(reg);
1681 udelay(150); /* wait for warmup */
1682 }
1683
1684 /**
1685 * i9xx_disable_pll - disable a PLL
1686 * @dev_priv: i915 private structure
1687 * @pipe: pipe PLL to disable
1688 *
1689 * Disable the PLL for @pipe, making sure the pipe is off first.
1690 *
1691 * Note! This is for pre-ILK only.
1692 */
1693 static void i9xx_disable_pll(struct intel_crtc *crtc)
1694 {
1695 struct drm_device *dev = crtc->base.dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 enum pipe pipe = crtc->pipe;
1698
1699 /* Disable DVO 2x clock on both PLLs if necessary */
1700 if (IS_I830(dev) &&
1701 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1702 intel_num_dvo_pipes(dev) == 1) {
1703 I915_WRITE(DPLL(PIPE_B),
1704 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1705 I915_WRITE(DPLL(PIPE_A),
1706 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1707 }
1708
1709 /* Don't disable pipe or pipe PLLs if needed */
1710 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1711 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1712 return;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 I915_WRITE(DPLL(pipe), 0);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 u32 val = 0;
1724
1725 /* Make sure the pipe isn't still relying on us */
1726 assert_pipe_disabled(dev_priv, pipe);
1727
1728 /*
1729 * Leave integrated clock source and reference clock enabled for pipe B.
1730 * The latter is needed for VGA hotplug / manual detection.
1731 */
1732 if (pipe == PIPE_B)
1733 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 }
1738
1739 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1740 {
1741 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1742 u32 val;
1743
1744 /* Make sure the pipe isn't still relying on us */
1745 assert_pipe_disabled(dev_priv, pipe);
1746
1747 /* Set PLL en = 0 */
1748 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1749 if (pipe != PIPE_A)
1750 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754 mutex_lock(&dev_priv->dpio_lock);
1755
1756 /* Disable 10bit clock to display controller */
1757 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1758 val &= ~DPIO_DCLKP_EN;
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1760
1761 /* disable left/right clock distribution */
1762 if (pipe != PIPE_B) {
1763 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1764 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1765 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1766 } else {
1767 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1768 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1769 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1770 }
1771
1772 mutex_unlock(&dev_priv->dpio_lock);
1773 }
1774
1775 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1776 struct intel_digital_port *dport)
1777 {
1778 u32 port_mask;
1779 int dpll_reg;
1780
1781 switch (dport->port) {
1782 case PORT_B:
1783 port_mask = DPLL_PORTB_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 break;
1786 case PORT_C:
1787 port_mask = DPLL_PORTC_READY_MASK;
1788 dpll_reg = DPLL(0);
1789 break;
1790 case PORT_D:
1791 port_mask = DPLL_PORTD_READY_MASK;
1792 dpll_reg = DPIO_PHY_STATUS;
1793 break;
1794 default:
1795 BUG();
1796 }
1797
1798 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1799 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1800 port_name(dport->port), I915_READ(dpll_reg));
1801 }
1802
1803 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 WARN_ON(!pll->refcount);
1813 if (pll->active == 0) {
1814 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1815 WARN_ON(pll->on);
1816 assert_shared_dpll_disabled(dev_priv, pll);
1817
1818 pll->mode_set(dev_priv, pll);
1819 }
1820 }
1821
1822 /**
1823 * intel_enable_shared_dpll - enable PCH PLL
1824 * @dev_priv: i915 private structure
1825 * @pipe: pipe PLL to enable
1826 *
1827 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1828 * drives the transcoder clock.
1829 */
1830 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 if (WARN_ON(pll == NULL))
1837 return;
1838
1839 if (WARN_ON(pll->refcount == 0))
1840 return;
1841
1842 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1843 pll->name, pll->active, pll->on,
1844 crtc->base.base.id);
1845
1846 if (pll->active++) {
1847 WARN_ON(!pll->on);
1848 assert_shared_dpll_enabled(dev_priv, pll);
1849 return;
1850 }
1851 WARN_ON(pll->on);
1852
1853 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1854
1855 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1856 pll->enable(dev_priv, pll);
1857 pll->on = true;
1858 }
1859
1860 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1861 {
1862 struct drm_device *dev = crtc->base.dev;
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1865
1866 /* PCH only available on ILK+ */
1867 BUG_ON(INTEL_INFO(dev)->gen < 5);
1868 if (WARN_ON(pll == NULL))
1869 return;
1870
1871 if (WARN_ON(pll->refcount == 0))
1872 return;
1873
1874 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1875 pll->name, pll->active, pll->on,
1876 crtc->base.base.id);
1877
1878 if (WARN_ON(pll->active == 0)) {
1879 assert_shared_dpll_disabled(dev_priv, pll);
1880 return;
1881 }
1882
1883 assert_shared_dpll_enabled(dev_priv, pll);
1884 WARN_ON(!pll->on);
1885 if (--pll->active)
1886 return;
1887
1888 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1889 pll->disable(dev_priv, pll);
1890 pll->on = false;
1891
1892 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1893 }
1894
1895 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1896 enum pipe pipe)
1897 {
1898 struct drm_device *dev = dev_priv->dev;
1899 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1901 uint32_t reg, val, pipeconf_val;
1902
1903 /* PCH only available on ILK+ */
1904 BUG_ON(!HAS_PCH_SPLIT(dev));
1905
1906 /* Make sure PCH DPLL is enabled */
1907 assert_shared_dpll_enabled(dev_priv,
1908 intel_crtc_to_shared_dpll(intel_crtc));
1909
1910 /* FDI must be feeding us bits for PCH ports */
1911 assert_fdi_tx_enabled(dev_priv, pipe);
1912 assert_fdi_rx_enabled(dev_priv, pipe);
1913
1914 if (HAS_PCH_CPT(dev)) {
1915 /* Workaround: Set the timing override bit before enabling the
1916 * pch transcoder. */
1917 reg = TRANS_CHICKEN2(pipe);
1918 val = I915_READ(reg);
1919 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1920 I915_WRITE(reg, val);
1921 }
1922
1923 reg = PCH_TRANSCONF(pipe);
1924 val = I915_READ(reg);
1925 pipeconf_val = I915_READ(PIPECONF(pipe));
1926
1927 if (HAS_PCH_IBX(dev_priv->dev)) {
1928 /*
1929 * make the BPC in transcoder be consistent with
1930 * that in pipeconf reg.
1931 */
1932 val &= ~PIPECONF_BPC_MASK;
1933 val |= pipeconf_val & PIPECONF_BPC_MASK;
1934 }
1935
1936 val &= ~TRANS_INTERLACE_MASK;
1937 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1938 if (HAS_PCH_IBX(dev_priv->dev) &&
1939 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1940 val |= TRANS_LEGACY_INTERLACED_ILK;
1941 else
1942 val |= TRANS_INTERLACED;
1943 else
1944 val |= TRANS_PROGRESSIVE;
1945
1946 I915_WRITE(reg, val | TRANS_ENABLE);
1947 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1948 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1949 }
1950
1951 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1952 enum transcoder cpu_transcoder)
1953 {
1954 u32 val, pipeconf_val;
1955
1956 /* PCH only available on ILK+ */
1957 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1958
1959 /* FDI must be feeding us bits for PCH ports */
1960 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1961 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1962
1963 /* Workaround: set timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(_TRANSA_CHICKEN2, val);
1967
1968 val = TRANS_ENABLE;
1969 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1970
1971 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1972 PIPECONF_INTERLACED_ILK)
1973 val |= TRANS_INTERLACED;
1974 else
1975 val |= TRANS_PROGRESSIVE;
1976
1977 I915_WRITE(LPT_TRANSCONF, val);
1978 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1979 DRM_ERROR("Failed to enable PCH transcoder\n");
1980 }
1981
1982 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1983 enum pipe pipe)
1984 {
1985 struct drm_device *dev = dev_priv->dev;
1986 uint32_t reg, val;
1987
1988 /* FDI relies on the transcoder */
1989 assert_fdi_tx_disabled(dev_priv, pipe);
1990 assert_fdi_rx_disabled(dev_priv, pipe);
1991
1992 /* Ports must be off as well */
1993 assert_pch_ports_disabled(dev_priv, pipe);
1994
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 val &= ~TRANS_ENABLE;
1998 I915_WRITE(reg, val);
1999 /* wait for PCH transcoder off, transcoder state */
2000 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2001 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2002
2003 if (!HAS_PCH_IBX(dev)) {
2004 /* Workaround: Clear the timing override chicken bit again. */
2005 reg = TRANS_CHICKEN2(pipe);
2006 val = I915_READ(reg);
2007 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(reg, val);
2009 }
2010 }
2011
2012 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2013 {
2014 u32 val;
2015
2016 val = I915_READ(LPT_TRANSCONF);
2017 val &= ~TRANS_ENABLE;
2018 I915_WRITE(LPT_TRANSCONF, val);
2019 /* wait for PCH transcoder off, transcoder state */
2020 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2021 DRM_ERROR("Failed to disable PCH transcoder\n");
2022
2023 /* Workaround: clear timing override bit. */
2024 val = I915_READ(_TRANSA_CHICKEN2);
2025 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(_TRANSA_CHICKEN2, val);
2027 }
2028
2029 /**
2030 * intel_enable_pipe - enable a pipe, asserting requirements
2031 * @crtc: crtc responsible for the pipe
2032 *
2033 * Enable @crtc's pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2035 */
2036 static void intel_enable_pipe(struct intel_crtc *crtc)
2037 {
2038 struct drm_device *dev = crtc->base.dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 enum pipe pipe = crtc->pipe;
2041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
2043 enum pipe pch_transcoder;
2044 int reg;
2045 u32 val;
2046
2047 assert_planes_disabled(dev_priv, pipe);
2048 assert_cursor_disabled(dev_priv, pipe);
2049 assert_sprites_disabled(dev_priv, pipe);
2050
2051 if (HAS_PCH_LPT(dev_priv->dev))
2052 pch_transcoder = TRANSCODER_A;
2053 else
2054 pch_transcoder = pipe;
2055
2056 /*
2057 * A pipe without a PLL won't actually be able to drive bits from
2058 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2059 * need the check.
2060 */
2061 if (!HAS_PCH_SPLIT(dev_priv->dev))
2062 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2063 assert_dsi_pll_enabled(dev_priv);
2064 else
2065 assert_pll_enabled(dev_priv, pipe);
2066 else {
2067 if (crtc->config.has_pch_encoder) {
2068 /* if driving the PCH, we need FDI enabled */
2069 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2070 assert_fdi_tx_pll_enabled(dev_priv,
2071 (enum pipe) cpu_transcoder);
2072 }
2073 /* FIXME: assert CPU port conditions for SNB+ */
2074 }
2075
2076 reg = PIPECONF(cpu_transcoder);
2077 val = I915_READ(reg);
2078 if (val & PIPECONF_ENABLE) {
2079 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2080 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2081 return;
2082 }
2083
2084 I915_WRITE(reg, val | PIPECONF_ENABLE);
2085 POSTING_READ(reg);
2086 }
2087
2088 /**
2089 * intel_disable_pipe - disable a pipe, asserting requirements
2090 * @crtc: crtc whose pipes is to be disabled
2091 *
2092 * Disable the pipe of @crtc, making sure that various hardware
2093 * specific requirements are met, if applicable, e.g. plane
2094 * disabled, panel fitter off, etc.
2095 *
2096 * Will wait until the pipe has shut down before returning.
2097 */
2098 static void intel_disable_pipe(struct intel_crtc *crtc)
2099 {
2100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2101 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2102 enum pipe pipe = crtc->pipe;
2103 int reg;
2104 u32 val;
2105
2106 /*
2107 * Make sure planes won't keep trying to pump pixels to us,
2108 * or we might hang the display.
2109 */
2110 assert_planes_disabled(dev_priv, pipe);
2111 assert_cursor_disabled(dev_priv, pipe);
2112 assert_sprites_disabled(dev_priv, pipe);
2113
2114 reg = PIPECONF(cpu_transcoder);
2115 val = I915_READ(reg);
2116 if ((val & PIPECONF_ENABLE) == 0)
2117 return;
2118
2119 /*
2120 * Double wide has implications for planes
2121 * so best keep it disabled when not needed.
2122 */
2123 if (crtc->config.double_wide)
2124 val &= ~PIPECONF_DOUBLE_WIDE;
2125
2126 /* Don't disable pipe or pipe PLLs if needed */
2127 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2128 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2129 val &= ~PIPECONF_ENABLE;
2130
2131 I915_WRITE(reg, val);
2132 if ((val & PIPECONF_ENABLE) == 0)
2133 intel_wait_for_pipe_off(crtc);
2134 }
2135
2136 /*
2137 * Plane regs are double buffered, going from enabled->disabled needs a
2138 * trigger in order to latch. The display address reg provides this.
2139 */
2140 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2141 enum plane plane)
2142 {
2143 struct drm_device *dev = dev_priv->dev;
2144 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2145
2146 I915_WRITE(reg, I915_READ(reg));
2147 POSTING_READ(reg);
2148 }
2149
2150 /**
2151 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2152 * @plane: plane to be enabled
2153 * @crtc: crtc for the plane
2154 *
2155 * Enable @plane on @crtc, making sure that the pipe is running first.
2156 */
2157 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2158 struct drm_crtc *crtc)
2159 {
2160 struct drm_device *dev = plane->dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2163
2164 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2165 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2166
2167 if (intel_crtc->primary_enabled)
2168 return;
2169
2170 intel_crtc->primary_enabled = true;
2171
2172 dev_priv->display.update_primary_plane(crtc, plane->fb,
2173 crtc->x, crtc->y);
2174
2175 /*
2176 * BDW signals flip done immediately if the plane
2177 * is disabled, even if the plane enable is already
2178 * armed to occur at the next vblank :(
2179 */
2180 if (IS_BROADWELL(dev))
2181 intel_wait_for_vblank(dev, intel_crtc->pipe);
2182 }
2183
2184 /**
2185 * intel_disable_primary_hw_plane - disable the primary hardware plane
2186 * @plane: plane to be disabled
2187 * @crtc: crtc for the plane
2188 *
2189 * Disable @plane on @crtc, making sure that the pipe is running first.
2190 */
2191 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2192 struct drm_crtc *crtc)
2193 {
2194 struct drm_device *dev = plane->dev;
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2199
2200 if (!intel_crtc->primary_enabled)
2201 return;
2202
2203 intel_crtc->primary_enabled = false;
2204
2205 dev_priv->display.update_primary_plane(crtc, plane->fb,
2206 crtc->x, crtc->y);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213 return true;
2214 #endif
2215 return false;
2216 }
2217
2218 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2219 {
2220 int tile_height;
2221
2222 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2223 return ALIGN(height, tile_height);
2224 }
2225
2226 int
2227 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2228 struct drm_i915_gem_object *obj,
2229 struct intel_engine_cs *pipelined)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 u32 alignment;
2233 int ret;
2234
2235 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2236
2237 switch (obj->tiling_mode) {
2238 case I915_TILING_NONE:
2239 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2240 alignment = 128 * 1024;
2241 else if (INTEL_INFO(dev)->gen >= 4)
2242 alignment = 4 * 1024;
2243 else
2244 alignment = 64 * 1024;
2245 break;
2246 case I915_TILING_X:
2247 /* pin() will align the object as required by fence */
2248 alignment = 0;
2249 break;
2250 case I915_TILING_Y:
2251 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2252 return -EINVAL;
2253 default:
2254 BUG();
2255 }
2256
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2260 * the VT-d warning.
2261 */
2262 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2263 alignment = 256 * 1024;
2264
2265 /*
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2271 */
2272 intel_runtime_pm_get(dev_priv);
2273
2274 dev_priv->mm.interruptible = false;
2275 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2276 if (ret)
2277 goto err_interruptible;
2278
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2283 */
2284 ret = i915_gem_object_get_fence(obj);
2285 if (ret)
2286 goto err_unpin;
2287
2288 i915_gem_object_pin_fence(obj);
2289
2290 dev_priv->mm.interruptible = true;
2291 intel_runtime_pm_put(dev_priv);
2292 return 0;
2293
2294 err_unpin:
2295 i915_gem_object_unpin_from_display_plane(obj);
2296 err_interruptible:
2297 dev_priv->mm.interruptible = true;
2298 intel_runtime_pm_put(dev_priv);
2299 return ret;
2300 }
2301
2302 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2303 {
2304 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2305
2306 i915_gem_object_unpin_fence(obj);
2307 i915_gem_object_unpin_from_display_plane(obj);
2308 }
2309
2310 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2311 * is assumed to be a power-of-two. */
2312 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2313 unsigned int tiling_mode,
2314 unsigned int cpp,
2315 unsigned int pitch)
2316 {
2317 if (tiling_mode != I915_TILING_NONE) {
2318 unsigned int tile_rows, tiles;
2319
2320 tile_rows = *y / 8;
2321 *y %= 8;
2322
2323 tiles = *x / (512/cpp);
2324 *x %= 512/cpp;
2325
2326 return tile_rows * pitch * 8 + tiles * 4096;
2327 } else {
2328 unsigned int offset;
2329
2330 offset = *y * pitch + *x * cpp;
2331 *y = 0;
2332 *x = (offset & 4095) / cpp;
2333 return offset & -4096;
2334 }
2335 }
2336
2337 int intel_format_to_fourcc(int format)
2338 {
2339 switch (format) {
2340 case DISPPLANE_8BPP:
2341 return DRM_FORMAT_C8;
2342 case DISPPLANE_BGRX555:
2343 return DRM_FORMAT_XRGB1555;
2344 case DISPPLANE_BGRX565:
2345 return DRM_FORMAT_RGB565;
2346 default:
2347 case DISPPLANE_BGRX888:
2348 return DRM_FORMAT_XRGB8888;
2349 case DISPPLANE_RGBX888:
2350 return DRM_FORMAT_XBGR8888;
2351 case DISPPLANE_BGRX101010:
2352 return DRM_FORMAT_XRGB2101010;
2353 case DISPPLANE_RGBX101010:
2354 return DRM_FORMAT_XBGR2101010;
2355 }
2356 }
2357
2358 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2359 struct intel_plane_config *plane_config)
2360 {
2361 struct drm_device *dev = crtc->base.dev;
2362 struct drm_i915_gem_object *obj = NULL;
2363 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2364 u32 base = plane_config->base;
2365
2366 if (plane_config->size == 0)
2367 return false;
2368
2369 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2370 plane_config->size);
2371 if (!obj)
2372 return false;
2373
2374 if (plane_config->tiled) {
2375 obj->tiling_mode = I915_TILING_X;
2376 obj->stride = crtc->base.primary->fb->pitches[0];
2377 }
2378
2379 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2380 mode_cmd.width = crtc->base.primary->fb->width;
2381 mode_cmd.height = crtc->base.primary->fb->height;
2382 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2383
2384 mutex_lock(&dev->struct_mutex);
2385
2386 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2387 &mode_cmd, obj)) {
2388 DRM_DEBUG_KMS("intel fb init failed\n");
2389 goto out_unref_obj;
2390 }
2391
2392 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2393 mutex_unlock(&dev->struct_mutex);
2394
2395 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2396 return true;
2397
2398 out_unref_obj:
2399 drm_gem_object_unreference(&obj->base);
2400 mutex_unlock(&dev->struct_mutex);
2401 return false;
2402 }
2403
2404 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2405 struct intel_plane_config *plane_config)
2406 {
2407 struct drm_device *dev = intel_crtc->base.dev;
2408 struct drm_crtc *c;
2409 struct intel_crtc *i;
2410 struct drm_i915_gem_object *obj;
2411
2412 if (!intel_crtc->base.primary->fb)
2413 return;
2414
2415 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2416 return;
2417
2418 kfree(intel_crtc->base.primary->fb);
2419 intel_crtc->base.primary->fb = NULL;
2420
2421 /*
2422 * Failed to alloc the obj, check to see if we should share
2423 * an fb with another CRTC instead
2424 */
2425 for_each_crtc(dev, c) {
2426 i = to_intel_crtc(c);
2427
2428 if (c == &intel_crtc->base)
2429 continue;
2430
2431 if (!i->active)
2432 continue;
2433
2434 obj = intel_fb_obj(c->primary->fb);
2435 if (obj == NULL)
2436 continue;
2437
2438 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2439 drm_framebuffer_reference(c->primary->fb);
2440 intel_crtc->base.primary->fb = c->primary->fb;
2441 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2442 break;
2443 }
2444 }
2445 }
2446
2447 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2448 struct drm_framebuffer *fb,
2449 int x, int y)
2450 {
2451 struct drm_device *dev = crtc->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454 struct drm_i915_gem_object *obj;
2455 int plane = intel_crtc->plane;
2456 unsigned long linear_offset;
2457 u32 dspcntr;
2458 u32 reg = DSPCNTR(plane);
2459 int pixel_size;
2460
2461 if (!intel_crtc->primary_enabled) {
2462 I915_WRITE(reg, 0);
2463 if (INTEL_INFO(dev)->gen >= 4)
2464 I915_WRITE(DSPSURF(plane), 0);
2465 else
2466 I915_WRITE(DSPADDR(plane), 0);
2467 POSTING_READ(reg);
2468 return;
2469 }
2470
2471 obj = intel_fb_obj(fb);
2472 if (WARN_ON(obj == NULL))
2473 return;
2474
2475 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2476
2477 dspcntr = DISPPLANE_GAMMA_ENABLE;
2478
2479 dspcntr |= DISPLAY_PLANE_ENABLE;
2480
2481 if (INTEL_INFO(dev)->gen < 4) {
2482 if (intel_crtc->pipe == PIPE_B)
2483 dspcntr |= DISPPLANE_SEL_PIPE_B;
2484
2485 /* pipesrc and dspsize control the size that is scaled from,
2486 * which should always be the user's requested size.
2487 */
2488 I915_WRITE(DSPSIZE(plane),
2489 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2490 (intel_crtc->config.pipe_src_w - 1));
2491 I915_WRITE(DSPPOS(plane), 0);
2492 }
2493
2494 switch (fb->pixel_format) {
2495 case DRM_FORMAT_C8:
2496 dspcntr |= DISPPLANE_8BPP;
2497 break;
2498 case DRM_FORMAT_XRGB1555:
2499 case DRM_FORMAT_ARGB1555:
2500 dspcntr |= DISPPLANE_BGRX555;
2501 break;
2502 case DRM_FORMAT_RGB565:
2503 dspcntr |= DISPPLANE_BGRX565;
2504 break;
2505 case DRM_FORMAT_XRGB8888:
2506 case DRM_FORMAT_ARGB8888:
2507 dspcntr |= DISPPLANE_BGRX888;
2508 break;
2509 case DRM_FORMAT_XBGR8888:
2510 case DRM_FORMAT_ABGR8888:
2511 dspcntr |= DISPPLANE_RGBX888;
2512 break;
2513 case DRM_FORMAT_XRGB2101010:
2514 case DRM_FORMAT_ARGB2101010:
2515 dspcntr |= DISPPLANE_BGRX101010;
2516 break;
2517 case DRM_FORMAT_XBGR2101010:
2518 case DRM_FORMAT_ABGR2101010:
2519 dspcntr |= DISPPLANE_RGBX101010;
2520 break;
2521 default:
2522 BUG();
2523 }
2524
2525 if (INTEL_INFO(dev)->gen >= 4 &&
2526 obj->tiling_mode != I915_TILING_NONE)
2527 dspcntr |= DISPPLANE_TILED;
2528
2529 if (IS_G4X(dev))
2530 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2531
2532 linear_offset = y * fb->pitches[0] + x * pixel_size;
2533
2534 if (INTEL_INFO(dev)->gen >= 4) {
2535 intel_crtc->dspaddr_offset =
2536 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2537 pixel_size,
2538 fb->pitches[0]);
2539 linear_offset -= intel_crtc->dspaddr_offset;
2540 } else {
2541 intel_crtc->dspaddr_offset = linear_offset;
2542 }
2543
2544 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2545 dspcntr |= DISPPLANE_ROTATE_180;
2546
2547 x += (intel_crtc->config.pipe_src_w - 1);
2548 y += (intel_crtc->config.pipe_src_h - 1);
2549
2550 /* Finding the last pixel of the last line of the display
2551 data and adding to linear_offset*/
2552 linear_offset +=
2553 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2554 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2555 }
2556
2557 I915_WRITE(reg, dspcntr);
2558
2559 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2560 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2561 fb->pitches[0]);
2562 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2563 if (INTEL_INFO(dev)->gen >= 4) {
2564 I915_WRITE(DSPSURF(plane),
2565 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2566 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2567 I915_WRITE(DSPLINOFF(plane), linear_offset);
2568 } else
2569 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2570 POSTING_READ(reg);
2571 }
2572
2573 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2574 struct drm_framebuffer *fb,
2575 int x, int y)
2576 {
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 struct drm_i915_gem_object *obj;
2581 int plane = intel_crtc->plane;
2582 unsigned long linear_offset;
2583 u32 dspcntr;
2584 u32 reg = DSPCNTR(plane);
2585 int pixel_size;
2586
2587 if (!intel_crtc->primary_enabled) {
2588 I915_WRITE(reg, 0);
2589 I915_WRITE(DSPSURF(plane), 0);
2590 POSTING_READ(reg);
2591 return;
2592 }
2593
2594 obj = intel_fb_obj(fb);
2595 if (WARN_ON(obj == NULL))
2596 return;
2597
2598 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2599
2600 dspcntr = DISPPLANE_GAMMA_ENABLE;
2601
2602 dspcntr |= DISPLAY_PLANE_ENABLE;
2603
2604 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2605 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2606
2607 switch (fb->pixel_format) {
2608 case DRM_FORMAT_C8:
2609 dspcntr |= DISPPLANE_8BPP;
2610 break;
2611 case DRM_FORMAT_RGB565:
2612 dspcntr |= DISPPLANE_BGRX565;
2613 break;
2614 case DRM_FORMAT_XRGB8888:
2615 case DRM_FORMAT_ARGB8888:
2616 dspcntr |= DISPPLANE_BGRX888;
2617 break;
2618 case DRM_FORMAT_XBGR8888:
2619 case DRM_FORMAT_ABGR8888:
2620 dspcntr |= DISPPLANE_RGBX888;
2621 break;
2622 case DRM_FORMAT_XRGB2101010:
2623 case DRM_FORMAT_ARGB2101010:
2624 dspcntr |= DISPPLANE_BGRX101010;
2625 break;
2626 case DRM_FORMAT_XBGR2101010:
2627 case DRM_FORMAT_ABGR2101010:
2628 dspcntr |= DISPPLANE_RGBX101010;
2629 break;
2630 default:
2631 BUG();
2632 }
2633
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dspcntr |= DISPPLANE_TILED;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2638 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2639
2640 linear_offset = y * fb->pitches[0] + x * pixel_size;
2641 intel_crtc->dspaddr_offset =
2642 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2643 pixel_size,
2644 fb->pitches[0]);
2645 linear_offset -= intel_crtc->dspaddr_offset;
2646 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2650 x += (intel_crtc->config.pipe_src_w - 1);
2651 y += (intel_crtc->config.pipe_src_h - 1);
2652
2653 /* Finding the last pixel of the last line of the display
2654 data and adding to linear_offset*/
2655 linear_offset +=
2656 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2657 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2658 }
2659 }
2660
2661 I915_WRITE(reg, dspcntr);
2662
2663 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2664 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2665 fb->pitches[0]);
2666 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2667 I915_WRITE(DSPSURF(plane),
2668 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2669 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2670 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2671 } else {
2672 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2673 I915_WRITE(DSPLINOFF(plane), linear_offset);
2674 }
2675 POSTING_READ(reg);
2676 }
2677
2678 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2679 static int
2680 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2681 int x, int y, enum mode_set_atomic state)
2682 {
2683 struct drm_device *dev = crtc->dev;
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2685
2686 if (dev_priv->display.disable_fbc)
2687 dev_priv->display.disable_fbc(dev);
2688 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2689
2690 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2691
2692 return 0;
2693 }
2694
2695 void intel_display_handle_reset(struct drm_device *dev)
2696 {
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct drm_crtc *crtc;
2699
2700 /*
2701 * Flips in the rings have been nuked by the reset,
2702 * so complete all pending flips so that user space
2703 * will get its events and not get stuck.
2704 *
2705 * Also update the base address of all primary
2706 * planes to the the last fb to make sure we're
2707 * showing the correct fb after a reset.
2708 *
2709 * Need to make two loops over the crtcs so that we
2710 * don't try to grab a crtc mutex before the
2711 * pending_flip_queue really got woken up.
2712 */
2713
2714 for_each_crtc(dev, crtc) {
2715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2716 enum plane plane = intel_crtc->plane;
2717
2718 intel_prepare_page_flip(dev, plane);
2719 intel_finish_page_flip_plane(dev, plane);
2720 }
2721
2722 for_each_crtc(dev, crtc) {
2723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724
2725 drm_modeset_lock(&crtc->mutex, NULL);
2726 /*
2727 * FIXME: Once we have proper support for primary planes (and
2728 * disabling them without disabling the entire crtc) allow again
2729 * a NULL crtc->primary->fb.
2730 */
2731 if (intel_crtc->active && crtc->primary->fb)
2732 dev_priv->display.update_primary_plane(crtc,
2733 crtc->primary->fb,
2734 crtc->x,
2735 crtc->y);
2736 drm_modeset_unlock(&crtc->mutex);
2737 }
2738 }
2739
2740 static int
2741 intel_finish_fb(struct drm_framebuffer *old_fb)
2742 {
2743 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2744 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2745 bool was_interruptible = dev_priv->mm.interruptible;
2746 int ret;
2747
2748 /* Big Hammer, we also need to ensure that any pending
2749 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2750 * current scanout is retired before unpinning the old
2751 * framebuffer.
2752 *
2753 * This should only fail upon a hung GPU, in which case we
2754 * can safely continue.
2755 */
2756 dev_priv->mm.interruptible = false;
2757 ret = i915_gem_object_finish_gpu(obj);
2758 dev_priv->mm.interruptible = was_interruptible;
2759
2760 return ret;
2761 }
2762
2763 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 unsigned long flags;
2769 bool pending;
2770
2771 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2772 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2773 return false;
2774
2775 spin_lock_irqsave(&dev->event_lock, flags);
2776 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2777 spin_unlock_irqrestore(&dev->event_lock, flags);
2778
2779 return pending;
2780 }
2781
2782 static int
2783 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2784 struct drm_framebuffer *fb)
2785 {
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum pipe pipe = intel_crtc->pipe;
2790 struct drm_framebuffer *old_fb = crtc->primary->fb;
2791 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2792 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2793 int ret;
2794
2795 if (intel_crtc_has_pending_flip(crtc)) {
2796 DRM_ERROR("pipe is still busy with an old pageflip\n");
2797 return -EBUSY;
2798 }
2799
2800 /* no fb bound */
2801 if (!fb) {
2802 DRM_ERROR("No FB bound\n");
2803 return 0;
2804 }
2805
2806 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2807 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2808 plane_name(intel_crtc->plane),
2809 INTEL_INFO(dev)->num_pipes);
2810 return -EINVAL;
2811 }
2812
2813 mutex_lock(&dev->struct_mutex);
2814 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2815 if (ret == 0)
2816 i915_gem_track_fb(old_obj, obj,
2817 INTEL_FRONTBUFFER_PRIMARY(pipe));
2818 mutex_unlock(&dev->struct_mutex);
2819 if (ret != 0) {
2820 DRM_ERROR("pin & fence failed\n");
2821 return ret;
2822 }
2823
2824 /*
2825 * Update pipe size and adjust fitter if needed: the reason for this is
2826 * that in compute_mode_changes we check the native mode (not the pfit
2827 * mode) to see if we can flip rather than do a full mode set. In the
2828 * fastboot case, we'll flip, but if we don't update the pipesrc and
2829 * pfit state, we'll end up with a big fb scanned out into the wrong
2830 * sized surface.
2831 *
2832 * To fix this properly, we need to hoist the checks up into
2833 * compute_mode_changes (or above), check the actual pfit state and
2834 * whether the platform allows pfit disable with pipe active, and only
2835 * then update the pipesrc and pfit state, even on the flip path.
2836 */
2837 if (i915.fastboot) {
2838 const struct drm_display_mode *adjusted_mode =
2839 &intel_crtc->config.adjusted_mode;
2840
2841 I915_WRITE(PIPESRC(intel_crtc->pipe),
2842 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2843 (adjusted_mode->crtc_vdisplay - 1));
2844 if (!intel_crtc->config.pch_pfit.enabled &&
2845 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2846 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2847 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2848 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2849 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2850 }
2851 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2852 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2853 }
2854
2855 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2856
2857 if (intel_crtc->active)
2858 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2859
2860 crtc->primary->fb = fb;
2861 crtc->x = x;
2862 crtc->y = y;
2863
2864 if (old_fb) {
2865 if (intel_crtc->active && old_fb != fb)
2866 intel_wait_for_vblank(dev, intel_crtc->pipe);
2867 mutex_lock(&dev->struct_mutex);
2868 intel_unpin_fb_obj(old_obj);
2869 mutex_unlock(&dev->struct_mutex);
2870 }
2871
2872 mutex_lock(&dev->struct_mutex);
2873 intel_update_fbc(dev);
2874 mutex_unlock(&dev->struct_mutex);
2875
2876 return 0;
2877 }
2878
2879 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2880 {
2881 struct drm_device *dev = crtc->dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884 int pipe = intel_crtc->pipe;
2885 u32 reg, temp;
2886
2887 /* enable normal train */
2888 reg = FDI_TX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 if (IS_IVYBRIDGE(dev)) {
2891 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2892 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2893 } else {
2894 temp &= ~FDI_LINK_TRAIN_NONE;
2895 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2896 }
2897 I915_WRITE(reg, temp);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 if (HAS_PCH_CPT(dev)) {
2902 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2903 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2904 } else {
2905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_NONE;
2907 }
2908 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2909
2910 /* wait one idle pattern time */
2911 POSTING_READ(reg);
2912 udelay(1000);
2913
2914 /* IVB wants error correction enabled */
2915 if (IS_IVYBRIDGE(dev))
2916 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2917 FDI_FE_ERRC_ENABLE);
2918 }
2919
2920 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2921 {
2922 return crtc->base.enabled && crtc->active &&
2923 crtc->config.has_pch_encoder;
2924 }
2925
2926 static void ivb_modeset_global_resources(struct drm_device *dev)
2927 {
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 struct intel_crtc *pipe_B_crtc =
2930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2931 struct intel_crtc *pipe_C_crtc =
2932 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2933 uint32_t temp;
2934
2935 /*
2936 * When everything is off disable fdi C so that we could enable fdi B
2937 * with all lanes. Note that we don't care about enabled pipes without
2938 * an enabled pch encoder.
2939 */
2940 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2941 !pipe_has_enabled_pch(pipe_C_crtc)) {
2942 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2944
2945 temp = I915_READ(SOUTH_CHICKEN1);
2946 temp &= ~FDI_BC_BIFURCATION_SELECT;
2947 DRM_DEBUG_KMS("disabling fdi C rx\n");
2948 I915_WRITE(SOUTH_CHICKEN1, temp);
2949 }
2950 }
2951
2952 /* The FDI link training functions for ILK/Ibexpeak. */
2953 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2954 {
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2958 int pipe = intel_crtc->pipe;
2959 u32 reg, temp, tries;
2960
2961 /* FDI needs bits from pipe first */
2962 assert_pipe_enabled(dev_priv, pipe);
2963
2964 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2965 for train result */
2966 reg = FDI_RX_IMR(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_RX_SYMBOL_LOCK;
2969 temp &= ~FDI_RX_BIT_LOCK;
2970 I915_WRITE(reg, temp);
2971 I915_READ(reg);
2972 udelay(150);
2973
2974 /* enable CPU FDI TX and PCH FDI RX */
2975 reg = FDI_TX_CTL(pipe);
2976 temp = I915_READ(reg);
2977 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2978 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2979 temp &= ~FDI_LINK_TRAIN_NONE;
2980 temp |= FDI_LINK_TRAIN_PATTERN_1;
2981 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2982
2983 reg = FDI_RX_CTL(pipe);
2984 temp = I915_READ(reg);
2985 temp &= ~FDI_LINK_TRAIN_NONE;
2986 temp |= FDI_LINK_TRAIN_PATTERN_1;
2987 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2988
2989 POSTING_READ(reg);
2990 udelay(150);
2991
2992 /* Ironlake workaround, enable clock pointer after FDI enable*/
2993 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2994 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2995 FDI_RX_PHASE_SYNC_POINTER_EN);
2996
2997 reg = FDI_RX_IIR(pipe);
2998 for (tries = 0; tries < 5; tries++) {
2999 temp = I915_READ(reg);
3000 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3001
3002 if ((temp & FDI_RX_BIT_LOCK)) {
3003 DRM_DEBUG_KMS("FDI train 1 done.\n");
3004 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3005 break;
3006 }
3007 }
3008 if (tries == 5)
3009 DRM_ERROR("FDI train 1 fail!\n");
3010
3011 /* Train 2 */
3012 reg = FDI_TX_CTL(pipe);
3013 temp = I915_READ(reg);
3014 temp &= ~FDI_LINK_TRAIN_NONE;
3015 temp |= FDI_LINK_TRAIN_PATTERN_2;
3016 I915_WRITE(reg, temp);
3017
3018 reg = FDI_RX_CTL(pipe);
3019 temp = I915_READ(reg);
3020 temp &= ~FDI_LINK_TRAIN_NONE;
3021 temp |= FDI_LINK_TRAIN_PATTERN_2;
3022 I915_WRITE(reg, temp);
3023
3024 POSTING_READ(reg);
3025 udelay(150);
3026
3027 reg = FDI_RX_IIR(pipe);
3028 for (tries = 0; tries < 5; tries++) {
3029 temp = I915_READ(reg);
3030 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3031
3032 if (temp & FDI_RX_SYMBOL_LOCK) {
3033 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3034 DRM_DEBUG_KMS("FDI train 2 done.\n");
3035 break;
3036 }
3037 }
3038 if (tries == 5)
3039 DRM_ERROR("FDI train 2 fail!\n");
3040
3041 DRM_DEBUG_KMS("FDI train done\n");
3042
3043 }
3044
3045 static const int snb_b_fdi_train_param[] = {
3046 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3047 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3048 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3049 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3050 };
3051
3052 /* The FDI link training functions for SNB/Cougarpoint. */
3053 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3054 {
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058 int pipe = intel_crtc->pipe;
3059 u32 reg, temp, i, retry;
3060
3061 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3062 for train result */
3063 reg = FDI_RX_IMR(pipe);
3064 temp = I915_READ(reg);
3065 temp &= ~FDI_RX_SYMBOL_LOCK;
3066 temp &= ~FDI_RX_BIT_LOCK;
3067 I915_WRITE(reg, temp);
3068
3069 POSTING_READ(reg);
3070 udelay(150);
3071
3072 /* enable CPU FDI TX and PCH FDI RX */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3076 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3077 temp &= ~FDI_LINK_TRAIN_NONE;
3078 temp |= FDI_LINK_TRAIN_PATTERN_1;
3079 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3080 /* SNB-B */
3081 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3082 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3083
3084 I915_WRITE(FDI_RX_MISC(pipe),
3085 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3086
3087 reg = FDI_RX_CTL(pipe);
3088 temp = I915_READ(reg);
3089 if (HAS_PCH_CPT(dev)) {
3090 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3091 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3092 } else {
3093 temp &= ~FDI_LINK_TRAIN_NONE;
3094 temp |= FDI_LINK_TRAIN_PATTERN_1;
3095 }
3096 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3097
3098 POSTING_READ(reg);
3099 udelay(150);
3100
3101 for (i = 0; i < 4; i++) {
3102 reg = FDI_TX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3105 temp |= snb_b_fdi_train_param[i];
3106 I915_WRITE(reg, temp);
3107
3108 POSTING_READ(reg);
3109 udelay(500);
3110
3111 for (retry = 0; retry < 5; retry++) {
3112 reg = FDI_RX_IIR(pipe);
3113 temp = I915_READ(reg);
3114 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3115 if (temp & FDI_RX_BIT_LOCK) {
3116 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3117 DRM_DEBUG_KMS("FDI train 1 done.\n");
3118 break;
3119 }
3120 udelay(50);
3121 }
3122 if (retry < 5)
3123 break;
3124 }
3125 if (i == 4)
3126 DRM_ERROR("FDI train 1 fail!\n");
3127
3128 /* Train 2 */
3129 reg = FDI_TX_CTL(pipe);
3130 temp = I915_READ(reg);
3131 temp &= ~FDI_LINK_TRAIN_NONE;
3132 temp |= FDI_LINK_TRAIN_PATTERN_2;
3133 if (IS_GEN6(dev)) {
3134 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3135 /* SNB-B */
3136 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3137 }
3138 I915_WRITE(reg, temp);
3139
3140 reg = FDI_RX_CTL(pipe);
3141 temp = I915_READ(reg);
3142 if (HAS_PCH_CPT(dev)) {
3143 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3144 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3145 } else {
3146 temp &= ~FDI_LINK_TRAIN_NONE;
3147 temp |= FDI_LINK_TRAIN_PATTERN_2;
3148 }
3149 I915_WRITE(reg, temp);
3150
3151 POSTING_READ(reg);
3152 udelay(150);
3153
3154 for (i = 0; i < 4; i++) {
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3158 temp |= snb_b_fdi_train_param[i];
3159 I915_WRITE(reg, temp);
3160
3161 POSTING_READ(reg);
3162 udelay(500);
3163
3164 for (retry = 0; retry < 5; retry++) {
3165 reg = FDI_RX_IIR(pipe);
3166 temp = I915_READ(reg);
3167 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3168 if (temp & FDI_RX_SYMBOL_LOCK) {
3169 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170 DRM_DEBUG_KMS("FDI train 2 done.\n");
3171 break;
3172 }
3173 udelay(50);
3174 }
3175 if (retry < 5)
3176 break;
3177 }
3178 if (i == 4)
3179 DRM_ERROR("FDI train 2 fail!\n");
3180
3181 DRM_DEBUG_KMS("FDI train done.\n");
3182 }
3183
3184 /* Manual link training for Ivy Bridge A0 parts */
3185 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3186 {
3187 struct drm_device *dev = crtc->dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190 int pipe = intel_crtc->pipe;
3191 u32 reg, temp, i, j;
3192
3193 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3194 for train result */
3195 reg = FDI_RX_IMR(pipe);
3196 temp = I915_READ(reg);
3197 temp &= ~FDI_RX_SYMBOL_LOCK;
3198 temp &= ~FDI_RX_BIT_LOCK;
3199 I915_WRITE(reg, temp);
3200
3201 POSTING_READ(reg);
3202 udelay(150);
3203
3204 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3205 I915_READ(FDI_RX_IIR(pipe)));
3206
3207 /* Try each vswing and preemphasis setting twice before moving on */
3208 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3209 /* disable first in case we need to retry */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3213 temp &= ~FDI_TX_ENABLE;
3214 I915_WRITE(reg, temp);
3215
3216 reg = FDI_RX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_LINK_TRAIN_AUTO;
3219 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3220 temp &= ~FDI_RX_ENABLE;
3221 I915_WRITE(reg, temp);
3222
3223 /* enable CPU FDI TX and PCH FDI RX */
3224 reg = FDI_TX_CTL(pipe);
3225 temp = I915_READ(reg);
3226 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3227 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3228 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3229 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3230 temp |= snb_b_fdi_train_param[j/2];
3231 temp |= FDI_COMPOSITE_SYNC;
3232 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3233
3234 I915_WRITE(FDI_RX_MISC(pipe),
3235 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3236
3237 reg = FDI_RX_CTL(pipe);
3238 temp = I915_READ(reg);
3239 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240 temp |= FDI_COMPOSITE_SYNC;
3241 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3242
3243 POSTING_READ(reg);
3244 udelay(1); /* should be 0.5us */
3245
3246 for (i = 0; i < 4; i++) {
3247 reg = FDI_RX_IIR(pipe);
3248 temp = I915_READ(reg);
3249 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3250
3251 if (temp & FDI_RX_BIT_LOCK ||
3252 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3253 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3254 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3255 i);
3256 break;
3257 }
3258 udelay(1); /* should be 0.5us */
3259 }
3260 if (i == 4) {
3261 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3262 continue;
3263 }
3264
3265 /* Train 2 */
3266 reg = FDI_TX_CTL(pipe);
3267 temp = I915_READ(reg);
3268 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3269 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3270 I915_WRITE(reg, temp);
3271
3272 reg = FDI_RX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3275 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3276 I915_WRITE(reg, temp);
3277
3278 POSTING_READ(reg);
3279 udelay(2); /* should be 1.5us */
3280
3281 for (i = 0; i < 4; i++) {
3282 reg = FDI_RX_IIR(pipe);
3283 temp = I915_READ(reg);
3284 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3285
3286 if (temp & FDI_RX_SYMBOL_LOCK ||
3287 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3288 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3289 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3290 i);
3291 goto train_done;
3292 }
3293 udelay(2); /* should be 1.5us */
3294 }
3295 if (i == 4)
3296 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3297 }
3298
3299 train_done:
3300 DRM_DEBUG_KMS("FDI train done.\n");
3301 }
3302
3303 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3304 {
3305 struct drm_device *dev = intel_crtc->base.dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 int pipe = intel_crtc->pipe;
3308 u32 reg, temp;
3309
3310
3311 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3312 reg = FDI_RX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3315 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3316 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3317 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3318
3319 POSTING_READ(reg);
3320 udelay(200);
3321
3322 /* Switch from Rawclk to PCDclk */
3323 temp = I915_READ(reg);
3324 I915_WRITE(reg, temp | FDI_PCDCLK);
3325
3326 POSTING_READ(reg);
3327 udelay(200);
3328
3329 /* Enable CPU FDI TX PLL, always on for Ironlake */
3330 reg = FDI_TX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3333 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3334
3335 POSTING_READ(reg);
3336 udelay(100);
3337 }
3338 }
3339
3340 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3341 {
3342 struct drm_device *dev = intel_crtc->base.dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 int pipe = intel_crtc->pipe;
3345 u32 reg, temp;
3346
3347 /* Switch from PCDclk to Rawclk */
3348 reg = FDI_RX_CTL(pipe);
3349 temp = I915_READ(reg);
3350 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3351
3352 /* Disable CPU FDI TX PLL */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3356
3357 POSTING_READ(reg);
3358 udelay(100);
3359
3360 reg = FDI_RX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3363
3364 /* Wait for the clocks to turn off. */
3365 POSTING_READ(reg);
3366 udelay(100);
3367 }
3368
3369 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3370 {
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 int pipe = intel_crtc->pipe;
3375 u32 reg, temp;
3376
3377 /* disable CPU FDI tx and PCH FDI rx */
3378 reg = FDI_TX_CTL(pipe);
3379 temp = I915_READ(reg);
3380 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3381 POSTING_READ(reg);
3382
3383 reg = FDI_RX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 temp &= ~(0x7 << 16);
3386 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3387 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3388
3389 POSTING_READ(reg);
3390 udelay(100);
3391
3392 /* Ironlake workaround, disable clock pointer after downing FDI */
3393 if (HAS_PCH_IBX(dev))
3394 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3395
3396 /* still set train pattern 1 */
3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_LINK_TRAIN_NONE;
3400 temp |= FDI_LINK_TRAIN_PATTERN_1;
3401 I915_WRITE(reg, temp);
3402
3403 reg = FDI_RX_CTL(pipe);
3404 temp = I915_READ(reg);
3405 if (HAS_PCH_CPT(dev)) {
3406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3408 } else {
3409 temp &= ~FDI_LINK_TRAIN_NONE;
3410 temp |= FDI_LINK_TRAIN_PATTERN_1;
3411 }
3412 /* BPC in FDI rx is consistent with that in PIPECONF */
3413 temp &= ~(0x07 << 16);
3414 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3415 I915_WRITE(reg, temp);
3416
3417 POSTING_READ(reg);
3418 udelay(100);
3419 }
3420
3421 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3422 {
3423 struct intel_crtc *crtc;
3424
3425 /* Note that we don't need to be called with mode_config.lock here
3426 * as our list of CRTC objects is static for the lifetime of the
3427 * device and so cannot disappear as we iterate. Similarly, we can
3428 * happily treat the predicates as racy, atomic checks as userspace
3429 * cannot claim and pin a new fb without at least acquring the
3430 * struct_mutex and so serialising with us.
3431 */
3432 for_each_intel_crtc(dev, crtc) {
3433 if (atomic_read(&crtc->unpin_work_count) == 0)
3434 continue;
3435
3436 if (crtc->unpin_work)
3437 intel_wait_for_vblank(dev, crtc->pipe);
3438
3439 return true;
3440 }
3441
3442 return false;
3443 }
3444
3445 static void page_flip_completed(struct intel_crtc *intel_crtc)
3446 {
3447 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3448 struct intel_unpin_work *work = intel_crtc->unpin_work;
3449
3450 /* ensure that the unpin work is consistent wrt ->pending. */
3451 smp_rmb();
3452 intel_crtc->unpin_work = NULL;
3453
3454 if (work->event)
3455 drm_send_vblank_event(intel_crtc->base.dev,
3456 intel_crtc->pipe,
3457 work->event);
3458
3459 drm_crtc_vblank_put(&intel_crtc->base);
3460
3461 wake_up_all(&dev_priv->pending_flip_queue);
3462 queue_work(dev_priv->wq, &work->work);
3463
3464 trace_i915_flip_complete(intel_crtc->plane,
3465 work->pending_flip_obj);
3466 }
3467
3468 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3469 {
3470 struct drm_device *dev = crtc->dev;
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472
3473 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3474 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3475 !intel_crtc_has_pending_flip(crtc),
3476 60*HZ) == 0)) {
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 unsigned long flags;
3479
3480 spin_lock_irqsave(&dev->event_lock, flags);
3481 if (intel_crtc->unpin_work) {
3482 WARN_ONCE(1, "Removing stuck page flip\n");
3483 page_flip_completed(intel_crtc);
3484 }
3485 spin_unlock_irqrestore(&dev->event_lock, flags);
3486 }
3487
3488 if (crtc->primary->fb) {
3489 mutex_lock(&dev->struct_mutex);
3490 intel_finish_fb(crtc->primary->fb);
3491 mutex_unlock(&dev->struct_mutex);
3492 }
3493 }
3494
3495 /* Program iCLKIP clock to the desired frequency */
3496 static void lpt_program_iclkip(struct drm_crtc *crtc)
3497 {
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3501 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3502 u32 temp;
3503
3504 mutex_lock(&dev_priv->dpio_lock);
3505
3506 /* It is necessary to ungate the pixclk gate prior to programming
3507 * the divisors, and gate it back when it is done.
3508 */
3509 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3510
3511 /* Disable SSCCTL */
3512 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3513 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3514 SBI_SSCCTL_DISABLE,
3515 SBI_ICLK);
3516
3517 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3518 if (clock == 20000) {
3519 auxdiv = 1;
3520 divsel = 0x41;
3521 phaseinc = 0x20;
3522 } else {
3523 /* The iCLK virtual clock root frequency is in MHz,
3524 * but the adjusted_mode->crtc_clock in in KHz. To get the
3525 * divisors, it is necessary to divide one by another, so we
3526 * convert the virtual clock precision to KHz here for higher
3527 * precision.
3528 */
3529 u32 iclk_virtual_root_freq = 172800 * 1000;
3530 u32 iclk_pi_range = 64;
3531 u32 desired_divisor, msb_divisor_value, pi_value;
3532
3533 desired_divisor = (iclk_virtual_root_freq / clock);
3534 msb_divisor_value = desired_divisor / iclk_pi_range;
3535 pi_value = desired_divisor % iclk_pi_range;
3536
3537 auxdiv = 0;
3538 divsel = msb_divisor_value - 2;
3539 phaseinc = pi_value;
3540 }
3541
3542 /* This should not happen with any sane values */
3543 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3544 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3545 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3546 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3547
3548 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3549 clock,
3550 auxdiv,
3551 divsel,
3552 phasedir,
3553 phaseinc);
3554
3555 /* Program SSCDIVINTPHASE6 */
3556 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3557 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3558 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3559 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3560 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3561 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3562 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3563 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3564
3565 /* Program SSCAUXDIV */
3566 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3567 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3568 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3569 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3570
3571 /* Enable modulator and associated divider */
3572 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3573 temp &= ~SBI_SSCCTL_DISABLE;
3574 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3575
3576 /* Wait for initialization time */
3577 udelay(24);
3578
3579 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3580
3581 mutex_unlock(&dev_priv->dpio_lock);
3582 }
3583
3584 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3585 enum pipe pch_transcoder)
3586 {
3587 struct drm_device *dev = crtc->base.dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3590
3591 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3592 I915_READ(HTOTAL(cpu_transcoder)));
3593 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3594 I915_READ(HBLANK(cpu_transcoder)));
3595 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3596 I915_READ(HSYNC(cpu_transcoder)));
3597
3598 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3599 I915_READ(VTOTAL(cpu_transcoder)));
3600 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3601 I915_READ(VBLANK(cpu_transcoder)));
3602 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3603 I915_READ(VSYNC(cpu_transcoder)));
3604 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3605 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3606 }
3607
3608 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3609 {
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 uint32_t temp;
3612
3613 temp = I915_READ(SOUTH_CHICKEN1);
3614 if (temp & FDI_BC_BIFURCATION_SELECT)
3615 return;
3616
3617 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3618 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3619
3620 temp |= FDI_BC_BIFURCATION_SELECT;
3621 DRM_DEBUG_KMS("enabling fdi C rx\n");
3622 I915_WRITE(SOUTH_CHICKEN1, temp);
3623 POSTING_READ(SOUTH_CHICKEN1);
3624 }
3625
3626 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3627 {
3628 struct drm_device *dev = intel_crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630
3631 switch (intel_crtc->pipe) {
3632 case PIPE_A:
3633 break;
3634 case PIPE_B:
3635 if (intel_crtc->config.fdi_lanes > 2)
3636 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3637 else
3638 cpt_enable_fdi_bc_bifurcation(dev);
3639
3640 break;
3641 case PIPE_C:
3642 cpt_enable_fdi_bc_bifurcation(dev);
3643
3644 break;
3645 default:
3646 BUG();
3647 }
3648 }
3649
3650 /*
3651 * Enable PCH resources required for PCH ports:
3652 * - PCH PLLs
3653 * - FDI training & RX/TX
3654 * - update transcoder timings
3655 * - DP transcoding bits
3656 * - transcoder
3657 */
3658 static void ironlake_pch_enable(struct drm_crtc *crtc)
3659 {
3660 struct drm_device *dev = crtc->dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663 int pipe = intel_crtc->pipe;
3664 u32 reg, temp;
3665
3666 assert_pch_transcoder_disabled(dev_priv, pipe);
3667
3668 if (IS_IVYBRIDGE(dev))
3669 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3670
3671 /* Write the TU size bits before fdi link training, so that error
3672 * detection works. */
3673 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3674 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3675
3676 /* For PCH output, training FDI link */
3677 dev_priv->display.fdi_link_train(crtc);
3678
3679 /* We need to program the right clock selection before writing the pixel
3680 * mutliplier into the DPLL. */
3681 if (HAS_PCH_CPT(dev)) {
3682 u32 sel;
3683
3684 temp = I915_READ(PCH_DPLL_SEL);
3685 temp |= TRANS_DPLL_ENABLE(pipe);
3686 sel = TRANS_DPLLB_SEL(pipe);
3687 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3688 temp |= sel;
3689 else
3690 temp &= ~sel;
3691 I915_WRITE(PCH_DPLL_SEL, temp);
3692 }
3693
3694 /* XXX: pch pll's can be enabled any time before we enable the PCH
3695 * transcoder, and we actually should do this to not upset any PCH
3696 * transcoder that already use the clock when we share it.
3697 *
3698 * Note that enable_shared_dpll tries to do the right thing, but
3699 * get_shared_dpll unconditionally resets the pll - we need that to have
3700 * the right LVDS enable sequence. */
3701 intel_enable_shared_dpll(intel_crtc);
3702
3703 /* set transcoder timing, panel must allow it */
3704 assert_panel_unlocked(dev_priv, pipe);
3705 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3706
3707 intel_fdi_normal_train(crtc);
3708
3709 /* For PCH DP, enable TRANS_DP_CTL */
3710 if (HAS_PCH_CPT(dev) &&
3711 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3712 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3713 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3714 reg = TRANS_DP_CTL(pipe);
3715 temp = I915_READ(reg);
3716 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3717 TRANS_DP_SYNC_MASK |
3718 TRANS_DP_BPC_MASK);
3719 temp |= (TRANS_DP_OUTPUT_ENABLE |
3720 TRANS_DP_ENH_FRAMING);
3721 temp |= bpc << 9; /* same format but at 11:9 */
3722
3723 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3724 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3725 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3726 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3727
3728 switch (intel_trans_dp_port_sel(crtc)) {
3729 case PCH_DP_B:
3730 temp |= TRANS_DP_PORT_SEL_B;
3731 break;
3732 case PCH_DP_C:
3733 temp |= TRANS_DP_PORT_SEL_C;
3734 break;
3735 case PCH_DP_D:
3736 temp |= TRANS_DP_PORT_SEL_D;
3737 break;
3738 default:
3739 BUG();
3740 }
3741
3742 I915_WRITE(reg, temp);
3743 }
3744
3745 ironlake_enable_pch_transcoder(dev_priv, pipe);
3746 }
3747
3748 static void lpt_pch_enable(struct drm_crtc *crtc)
3749 {
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3754
3755 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3756
3757 lpt_program_iclkip(crtc);
3758
3759 /* Set transcoder timing. */
3760 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3761
3762 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3763 }
3764
3765 void intel_put_shared_dpll(struct intel_crtc *crtc)
3766 {
3767 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3768
3769 if (pll == NULL)
3770 return;
3771
3772 if (pll->refcount == 0) {
3773 WARN(1, "bad %s refcount\n", pll->name);
3774 return;
3775 }
3776
3777 if (--pll->refcount == 0) {
3778 WARN_ON(pll->on);
3779 WARN_ON(pll->active);
3780 }
3781
3782 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3783 }
3784
3785 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3786 {
3787 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3788 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3789 enum intel_dpll_id i;
3790
3791 if (pll) {
3792 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3793 crtc->base.base.id, pll->name);
3794 intel_put_shared_dpll(crtc);
3795 }
3796
3797 if (HAS_PCH_IBX(dev_priv->dev)) {
3798 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3799 i = (enum intel_dpll_id) crtc->pipe;
3800 pll = &dev_priv->shared_dplls[i];
3801
3802 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3803 crtc->base.base.id, pll->name);
3804
3805 WARN_ON(pll->refcount);
3806
3807 goto found;
3808 }
3809
3810 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3811 pll = &dev_priv->shared_dplls[i];
3812
3813 /* Only want to check enabled timings first */
3814 if (pll->refcount == 0)
3815 continue;
3816
3817 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3818 sizeof(pll->hw_state)) == 0) {
3819 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3820 crtc->base.base.id,
3821 pll->name, pll->refcount, pll->active);
3822
3823 goto found;
3824 }
3825 }
3826
3827 /* Ok no matching timings, maybe there's a free one? */
3828 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3829 pll = &dev_priv->shared_dplls[i];
3830 if (pll->refcount == 0) {
3831 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3832 crtc->base.base.id, pll->name);
3833 goto found;
3834 }
3835 }
3836
3837 return NULL;
3838
3839 found:
3840 if (pll->refcount == 0)
3841 pll->hw_state = crtc->config.dpll_hw_state;
3842
3843 crtc->config.shared_dpll = i;
3844 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3845 pipe_name(crtc->pipe));
3846
3847 pll->refcount++;
3848
3849 return pll;
3850 }
3851
3852 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3853 {
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 int dslreg = PIPEDSL(pipe);
3856 u32 temp;
3857
3858 temp = I915_READ(dslreg);
3859 udelay(500);
3860 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3861 if (wait_for(I915_READ(dslreg) != temp, 5))
3862 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3863 }
3864 }
3865
3866 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3867 {
3868 struct drm_device *dev = crtc->base.dev;
3869 struct drm_i915_private *dev_priv = dev->dev_private;
3870 int pipe = crtc->pipe;
3871
3872 if (crtc->config.pch_pfit.enabled) {
3873 /* Force use of hard-coded filter coefficients
3874 * as some pre-programmed values are broken,
3875 * e.g. x201.
3876 */
3877 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3878 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3879 PF_PIPE_SEL_IVB(pipe));
3880 else
3881 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3882 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3883 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3884 }
3885 }
3886
3887 static void intel_enable_planes(struct drm_crtc *crtc)
3888 {
3889 struct drm_device *dev = crtc->dev;
3890 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3891 struct drm_plane *plane;
3892 struct intel_plane *intel_plane;
3893
3894 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3895 intel_plane = to_intel_plane(plane);
3896 if (intel_plane->pipe == pipe)
3897 intel_plane_restore(&intel_plane->base);
3898 }
3899 }
3900
3901 static void intel_disable_planes(struct drm_crtc *crtc)
3902 {
3903 struct drm_device *dev = crtc->dev;
3904 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3905 struct drm_plane *plane;
3906 struct intel_plane *intel_plane;
3907
3908 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3909 intel_plane = to_intel_plane(plane);
3910 if (intel_plane->pipe == pipe)
3911 intel_plane_disable(&intel_plane->base);
3912 }
3913 }
3914
3915 void hsw_enable_ips(struct intel_crtc *crtc)
3916 {
3917 struct drm_device *dev = crtc->base.dev;
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919
3920 if (!crtc->config.ips_enabled)
3921 return;
3922
3923 /* We can only enable IPS after we enable a plane and wait for a vblank */
3924 intel_wait_for_vblank(dev, crtc->pipe);
3925
3926 assert_plane_enabled(dev_priv, crtc->plane);
3927 if (IS_BROADWELL(dev)) {
3928 mutex_lock(&dev_priv->rps.hw_lock);
3929 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3930 mutex_unlock(&dev_priv->rps.hw_lock);
3931 /* Quoting Art Runyan: "its not safe to expect any particular
3932 * value in IPS_CTL bit 31 after enabling IPS through the
3933 * mailbox." Moreover, the mailbox may return a bogus state,
3934 * so we need to just enable it and continue on.
3935 */
3936 } else {
3937 I915_WRITE(IPS_CTL, IPS_ENABLE);
3938 /* The bit only becomes 1 in the next vblank, so this wait here
3939 * is essentially intel_wait_for_vblank. If we don't have this
3940 * and don't wait for vblanks until the end of crtc_enable, then
3941 * the HW state readout code will complain that the expected
3942 * IPS_CTL value is not the one we read. */
3943 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3944 DRM_ERROR("Timed out waiting for IPS enable\n");
3945 }
3946 }
3947
3948 void hsw_disable_ips(struct intel_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->base.dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952
3953 if (!crtc->config.ips_enabled)
3954 return;
3955
3956 assert_plane_enabled(dev_priv, crtc->plane);
3957 if (IS_BROADWELL(dev)) {
3958 mutex_lock(&dev_priv->rps.hw_lock);
3959 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3960 mutex_unlock(&dev_priv->rps.hw_lock);
3961 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3962 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3963 DRM_ERROR("Timed out waiting for IPS disable\n");
3964 } else {
3965 I915_WRITE(IPS_CTL, 0);
3966 POSTING_READ(IPS_CTL);
3967 }
3968
3969 /* We need to wait for a vblank before we can disable the plane. */
3970 intel_wait_for_vblank(dev, crtc->pipe);
3971 }
3972
3973 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3974 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3975 {
3976 struct drm_device *dev = crtc->dev;
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979 enum pipe pipe = intel_crtc->pipe;
3980 int palreg = PALETTE(pipe);
3981 int i;
3982 bool reenable_ips = false;
3983
3984 /* The clocks have to be on to load the palette. */
3985 if (!crtc->enabled || !intel_crtc->active)
3986 return;
3987
3988 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3989 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3990 assert_dsi_pll_enabled(dev_priv);
3991 else
3992 assert_pll_enabled(dev_priv, pipe);
3993 }
3994
3995 /* use legacy palette for Ironlake */
3996 if (!HAS_GMCH_DISPLAY(dev))
3997 palreg = LGC_PALETTE(pipe);
3998
3999 /* Workaround : Do not read or write the pipe palette/gamma data while
4000 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4001 */
4002 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4003 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4004 GAMMA_MODE_MODE_SPLIT)) {
4005 hsw_disable_ips(intel_crtc);
4006 reenable_ips = true;
4007 }
4008
4009 for (i = 0; i < 256; i++) {
4010 I915_WRITE(palreg + 4 * i,
4011 (intel_crtc->lut_r[i] << 16) |
4012 (intel_crtc->lut_g[i] << 8) |
4013 intel_crtc->lut_b[i]);
4014 }
4015
4016 if (reenable_ips)
4017 hsw_enable_ips(intel_crtc);
4018 }
4019
4020 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4021 {
4022 if (!enable && intel_crtc->overlay) {
4023 struct drm_device *dev = intel_crtc->base.dev;
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4025
4026 mutex_lock(&dev->struct_mutex);
4027 dev_priv->mm.interruptible = false;
4028 (void) intel_overlay_switch_off(intel_crtc->overlay);
4029 dev_priv->mm.interruptible = true;
4030 mutex_unlock(&dev->struct_mutex);
4031 }
4032
4033 /* Let userspace switch the overlay on again. In most cases userspace
4034 * has to recompute where to put it anyway.
4035 */
4036 }
4037
4038 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4039 {
4040 struct drm_device *dev = crtc->dev;
4041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4042 int pipe = intel_crtc->pipe;
4043
4044 assert_vblank_disabled(crtc);
4045
4046 drm_vblank_on(dev, pipe);
4047
4048 intel_enable_primary_hw_plane(crtc->primary, crtc);
4049 intel_enable_planes(crtc);
4050 intel_crtc_update_cursor(crtc, true);
4051 intel_crtc_dpms_overlay(intel_crtc, true);
4052
4053 hsw_enable_ips(intel_crtc);
4054
4055 mutex_lock(&dev->struct_mutex);
4056 intel_update_fbc(dev);
4057 mutex_unlock(&dev->struct_mutex);
4058
4059 /*
4060 * FIXME: Once we grow proper nuclear flip support out of this we need
4061 * to compute the mask of flip planes precisely. For the time being
4062 * consider this a flip from a NULL plane.
4063 */
4064 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4065 }
4066
4067 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4068 {
4069 struct drm_device *dev = crtc->dev;
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4072 int pipe = intel_crtc->pipe;
4073 int plane = intel_crtc->plane;
4074
4075 intel_crtc_wait_for_pending_flips(crtc);
4076
4077 if (dev_priv->fbc.plane == plane)
4078 intel_disable_fbc(dev);
4079
4080 hsw_disable_ips(intel_crtc);
4081
4082 intel_crtc_dpms_overlay(intel_crtc, false);
4083 intel_crtc_update_cursor(crtc, false);
4084 intel_disable_planes(crtc);
4085 intel_disable_primary_hw_plane(crtc->primary, crtc);
4086
4087 /*
4088 * FIXME: Once we grow proper nuclear flip support out of this we need
4089 * to compute the mask of flip planes precisely. For the time being
4090 * consider this a flip to a NULL plane.
4091 */
4092 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4093
4094 drm_vblank_off(dev, pipe);
4095
4096 assert_vblank_disabled(crtc);
4097 }
4098
4099 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4100 {
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 struct intel_encoder *encoder;
4105 int pipe = intel_crtc->pipe;
4106
4107 WARN_ON(!crtc->enabled);
4108
4109 if (intel_crtc->active)
4110 return;
4111
4112 if (intel_crtc->config.has_pch_encoder)
4113 intel_prepare_shared_dpll(intel_crtc);
4114
4115 if (intel_crtc->config.has_dp_encoder)
4116 intel_dp_set_m_n(intel_crtc);
4117
4118 intel_set_pipe_timings(intel_crtc);
4119
4120 if (intel_crtc->config.has_pch_encoder) {
4121 intel_cpu_transcoder_set_m_n(intel_crtc,
4122 &intel_crtc->config.fdi_m_n, NULL);
4123 }
4124
4125 ironlake_set_pipeconf(crtc);
4126
4127 intel_crtc->active = true;
4128
4129 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4130 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4131
4132 for_each_encoder_on_crtc(dev, crtc, encoder)
4133 if (encoder->pre_enable)
4134 encoder->pre_enable(encoder);
4135
4136 if (intel_crtc->config.has_pch_encoder) {
4137 /* Note: FDI PLL enabling _must_ be done before we enable the
4138 * cpu pipes, hence this is separate from all the other fdi/pch
4139 * enabling. */
4140 ironlake_fdi_pll_enable(intel_crtc);
4141 } else {
4142 assert_fdi_tx_disabled(dev_priv, pipe);
4143 assert_fdi_rx_disabled(dev_priv, pipe);
4144 }
4145
4146 ironlake_pfit_enable(intel_crtc);
4147
4148 /*
4149 * On ILK+ LUT must be loaded before the pipe is running but with
4150 * clocks enabled
4151 */
4152 intel_crtc_load_lut(crtc);
4153
4154 intel_update_watermarks(crtc);
4155 intel_enable_pipe(intel_crtc);
4156
4157 if (intel_crtc->config.has_pch_encoder)
4158 ironlake_pch_enable(crtc);
4159
4160 for_each_encoder_on_crtc(dev, crtc, encoder)
4161 encoder->enable(encoder);
4162
4163 if (HAS_PCH_CPT(dev))
4164 cpt_verify_modeset(dev, intel_crtc->pipe);
4165
4166 intel_crtc_enable_planes(crtc);
4167 }
4168
4169 /* IPS only exists on ULT machines and is tied to pipe A. */
4170 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4171 {
4172 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4173 }
4174
4175 /*
4176 * This implements the workaround described in the "notes" section of the mode
4177 * set sequence documentation. When going from no pipes or single pipe to
4178 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4179 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4180 */
4181 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4182 {
4183 struct drm_device *dev = crtc->base.dev;
4184 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4185
4186 /* We want to get the other_active_crtc only if there's only 1 other
4187 * active crtc. */
4188 for_each_intel_crtc(dev, crtc_it) {
4189 if (!crtc_it->active || crtc_it == crtc)
4190 continue;
4191
4192 if (other_active_crtc)
4193 return;
4194
4195 other_active_crtc = crtc_it;
4196 }
4197 if (!other_active_crtc)
4198 return;
4199
4200 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4201 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4202 }
4203
4204 static void haswell_crtc_enable(struct drm_crtc *crtc)
4205 {
4206 struct drm_device *dev = crtc->dev;
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209 struct intel_encoder *encoder;
4210 int pipe = intel_crtc->pipe;
4211
4212 WARN_ON(!crtc->enabled);
4213
4214 if (intel_crtc->active)
4215 return;
4216
4217 if (intel_crtc_to_shared_dpll(intel_crtc))
4218 intel_enable_shared_dpll(intel_crtc);
4219
4220 if (intel_crtc->config.has_dp_encoder)
4221 intel_dp_set_m_n(intel_crtc);
4222
4223 intel_set_pipe_timings(intel_crtc);
4224
4225 if (intel_crtc->config.has_pch_encoder) {
4226 intel_cpu_transcoder_set_m_n(intel_crtc,
4227 &intel_crtc->config.fdi_m_n, NULL);
4228 }
4229
4230 haswell_set_pipeconf(crtc);
4231
4232 intel_set_pipe_csc(crtc);
4233
4234 intel_crtc->active = true;
4235
4236 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4237 for_each_encoder_on_crtc(dev, crtc, encoder)
4238 if (encoder->pre_enable)
4239 encoder->pre_enable(encoder);
4240
4241 if (intel_crtc->config.has_pch_encoder) {
4242 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4243 dev_priv->display.fdi_link_train(crtc);
4244 }
4245
4246 intel_ddi_enable_pipe_clock(intel_crtc);
4247
4248 ironlake_pfit_enable(intel_crtc);
4249
4250 /*
4251 * On ILK+ LUT must be loaded before the pipe is running but with
4252 * clocks enabled
4253 */
4254 intel_crtc_load_lut(crtc);
4255
4256 intel_ddi_set_pipe_settings(crtc);
4257 intel_ddi_enable_transcoder_func(crtc);
4258
4259 intel_update_watermarks(crtc);
4260 intel_enable_pipe(intel_crtc);
4261
4262 if (intel_crtc->config.has_pch_encoder)
4263 lpt_pch_enable(crtc);
4264
4265 if (intel_crtc->config.dp_encoder_is_mst)
4266 intel_ddi_set_vc_payload_alloc(crtc, true);
4267
4268 for_each_encoder_on_crtc(dev, crtc, encoder) {
4269 encoder->enable(encoder);
4270 intel_opregion_notify_encoder(encoder, true);
4271 }
4272
4273 /* If we change the relative order between pipe/planes enabling, we need
4274 * to change the workaround. */
4275 haswell_mode_set_planes_workaround(intel_crtc);
4276 intel_crtc_enable_planes(crtc);
4277 }
4278
4279 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4280 {
4281 struct drm_device *dev = crtc->base.dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 int pipe = crtc->pipe;
4284
4285 /* To avoid upsetting the power well on haswell only disable the pfit if
4286 * it's in use. The hw state code will make sure we get this right. */
4287 if (crtc->config.pch_pfit.enabled) {
4288 I915_WRITE(PF_CTL(pipe), 0);
4289 I915_WRITE(PF_WIN_POS(pipe), 0);
4290 I915_WRITE(PF_WIN_SZ(pipe), 0);
4291 }
4292 }
4293
4294 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4295 {
4296 struct drm_device *dev = crtc->dev;
4297 struct drm_i915_private *dev_priv = dev->dev_private;
4298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299 struct intel_encoder *encoder;
4300 int pipe = intel_crtc->pipe;
4301 u32 reg, temp;
4302
4303 if (!intel_crtc->active)
4304 return;
4305
4306 intel_crtc_disable_planes(crtc);
4307
4308 for_each_encoder_on_crtc(dev, crtc, encoder)
4309 encoder->disable(encoder);
4310
4311 if (intel_crtc->config.has_pch_encoder)
4312 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4313
4314 intel_disable_pipe(intel_crtc);
4315
4316 ironlake_pfit_disable(intel_crtc);
4317
4318 for_each_encoder_on_crtc(dev, crtc, encoder)
4319 if (encoder->post_disable)
4320 encoder->post_disable(encoder);
4321
4322 if (intel_crtc->config.has_pch_encoder) {
4323 ironlake_fdi_disable(crtc);
4324
4325 ironlake_disable_pch_transcoder(dev_priv, pipe);
4326 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4327
4328 if (HAS_PCH_CPT(dev)) {
4329 /* disable TRANS_DP_CTL */
4330 reg = TRANS_DP_CTL(pipe);
4331 temp = I915_READ(reg);
4332 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4333 TRANS_DP_PORT_SEL_MASK);
4334 temp |= TRANS_DP_PORT_SEL_NONE;
4335 I915_WRITE(reg, temp);
4336
4337 /* disable DPLL_SEL */
4338 temp = I915_READ(PCH_DPLL_SEL);
4339 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4340 I915_WRITE(PCH_DPLL_SEL, temp);
4341 }
4342
4343 /* disable PCH DPLL */
4344 intel_disable_shared_dpll(intel_crtc);
4345
4346 ironlake_fdi_pll_disable(intel_crtc);
4347 }
4348
4349 intel_crtc->active = false;
4350 intel_update_watermarks(crtc);
4351
4352 mutex_lock(&dev->struct_mutex);
4353 intel_update_fbc(dev);
4354 mutex_unlock(&dev->struct_mutex);
4355 }
4356
4357 static void haswell_crtc_disable(struct drm_crtc *crtc)
4358 {
4359 struct drm_device *dev = crtc->dev;
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4362 struct intel_encoder *encoder;
4363 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4364
4365 if (!intel_crtc->active)
4366 return;
4367
4368 intel_crtc_disable_planes(crtc);
4369
4370 for_each_encoder_on_crtc(dev, crtc, encoder) {
4371 intel_opregion_notify_encoder(encoder, false);
4372 encoder->disable(encoder);
4373 }
4374
4375 if (intel_crtc->config.has_pch_encoder)
4376 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4377 intel_disable_pipe(intel_crtc);
4378
4379 if (intel_crtc->config.dp_encoder_is_mst)
4380 intel_ddi_set_vc_payload_alloc(crtc, false);
4381
4382 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4383
4384 ironlake_pfit_disable(intel_crtc);
4385
4386 intel_ddi_disable_pipe_clock(intel_crtc);
4387
4388 if (intel_crtc->config.has_pch_encoder) {
4389 lpt_disable_pch_transcoder(dev_priv);
4390 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4391 intel_ddi_fdi_disable(crtc);
4392 }
4393
4394 for_each_encoder_on_crtc(dev, crtc, encoder)
4395 if (encoder->post_disable)
4396 encoder->post_disable(encoder);
4397
4398 intel_crtc->active = false;
4399 intel_update_watermarks(crtc);
4400
4401 mutex_lock(&dev->struct_mutex);
4402 intel_update_fbc(dev);
4403 mutex_unlock(&dev->struct_mutex);
4404
4405 if (intel_crtc_to_shared_dpll(intel_crtc))
4406 intel_disable_shared_dpll(intel_crtc);
4407 }
4408
4409 static void ironlake_crtc_off(struct drm_crtc *crtc)
4410 {
4411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412 intel_put_shared_dpll(intel_crtc);
4413 }
4414
4415
4416 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4417 {
4418 struct drm_device *dev = crtc->base.dev;
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_crtc_config *pipe_config = &crtc->config;
4421
4422 if (!crtc->config.gmch_pfit.control)
4423 return;
4424
4425 /*
4426 * The panel fitter should only be adjusted whilst the pipe is disabled,
4427 * according to register description and PRM.
4428 */
4429 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4430 assert_pipe_disabled(dev_priv, crtc->pipe);
4431
4432 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4433 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4434
4435 /* Border color in case we don't scale up to the full screen. Black by
4436 * default, change to something else for debugging. */
4437 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4438 }
4439
4440 static enum intel_display_power_domain port_to_power_domain(enum port port)
4441 {
4442 switch (port) {
4443 case PORT_A:
4444 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4445 case PORT_B:
4446 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4447 case PORT_C:
4448 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4449 case PORT_D:
4450 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4451 default:
4452 WARN_ON_ONCE(1);
4453 return POWER_DOMAIN_PORT_OTHER;
4454 }
4455 }
4456
4457 #define for_each_power_domain(domain, mask) \
4458 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4459 if ((1 << (domain)) & (mask))
4460
4461 enum intel_display_power_domain
4462 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4463 {
4464 struct drm_device *dev = intel_encoder->base.dev;
4465 struct intel_digital_port *intel_dig_port;
4466
4467 switch (intel_encoder->type) {
4468 case INTEL_OUTPUT_UNKNOWN:
4469 /* Only DDI platforms should ever use this output type */
4470 WARN_ON_ONCE(!HAS_DDI(dev));
4471 case INTEL_OUTPUT_DISPLAYPORT:
4472 case INTEL_OUTPUT_HDMI:
4473 case INTEL_OUTPUT_EDP:
4474 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4475 return port_to_power_domain(intel_dig_port->port);
4476 case INTEL_OUTPUT_DP_MST:
4477 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4478 return port_to_power_domain(intel_dig_port->port);
4479 case INTEL_OUTPUT_ANALOG:
4480 return POWER_DOMAIN_PORT_CRT;
4481 case INTEL_OUTPUT_DSI:
4482 return POWER_DOMAIN_PORT_DSI;
4483 default:
4484 return POWER_DOMAIN_PORT_OTHER;
4485 }
4486 }
4487
4488 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4489 {
4490 struct drm_device *dev = crtc->dev;
4491 struct intel_encoder *intel_encoder;
4492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4493 enum pipe pipe = intel_crtc->pipe;
4494 unsigned long mask;
4495 enum transcoder transcoder;
4496
4497 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4498
4499 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4500 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4501 if (intel_crtc->config.pch_pfit.enabled ||
4502 intel_crtc->config.pch_pfit.force_thru)
4503 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4504
4505 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4506 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4507
4508 return mask;
4509 }
4510
4511 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4512 bool enable)
4513 {
4514 if (dev_priv->power_domains.init_power_on == enable)
4515 return;
4516
4517 if (enable)
4518 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4519 else
4520 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4521
4522 dev_priv->power_domains.init_power_on = enable;
4523 }
4524
4525 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4526 {
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4529 struct intel_crtc *crtc;
4530
4531 /*
4532 * First get all needed power domains, then put all unneeded, to avoid
4533 * any unnecessary toggling of the power wells.
4534 */
4535 for_each_intel_crtc(dev, crtc) {
4536 enum intel_display_power_domain domain;
4537
4538 if (!crtc->base.enabled)
4539 continue;
4540
4541 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4542
4543 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4544 intel_display_power_get(dev_priv, domain);
4545 }
4546
4547 for_each_intel_crtc(dev, crtc) {
4548 enum intel_display_power_domain domain;
4549
4550 for_each_power_domain(domain, crtc->enabled_power_domains)
4551 intel_display_power_put(dev_priv, domain);
4552
4553 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4554 }
4555
4556 intel_display_set_init_power(dev_priv, false);
4557 }
4558
4559 /* returns HPLL frequency in kHz */
4560 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4561 {
4562 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4563
4564 /* Obtain SKU information */
4565 mutex_lock(&dev_priv->dpio_lock);
4566 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4567 CCK_FUSE_HPLL_FREQ_MASK;
4568 mutex_unlock(&dev_priv->dpio_lock);
4569
4570 return vco_freq[hpll_freq] * 1000;
4571 }
4572
4573 static void vlv_update_cdclk(struct drm_device *dev)
4574 {
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576
4577 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4578 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4579 dev_priv->vlv_cdclk_freq);
4580
4581 /*
4582 * Program the gmbus_freq based on the cdclk frequency.
4583 * BSpec erroneously claims we should aim for 4MHz, but
4584 * in fact 1MHz is the correct frequency.
4585 */
4586 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4587 }
4588
4589 /* Adjust CDclk dividers to allow high res or save power if possible */
4590 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4591 {
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 u32 val, cmd;
4594
4595 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4596
4597 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4598 cmd = 2;
4599 else if (cdclk == 266667)
4600 cmd = 1;
4601 else
4602 cmd = 0;
4603
4604 mutex_lock(&dev_priv->rps.hw_lock);
4605 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4606 val &= ~DSPFREQGUAR_MASK;
4607 val |= (cmd << DSPFREQGUAR_SHIFT);
4608 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4609 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4610 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4611 50)) {
4612 DRM_ERROR("timed out waiting for CDclk change\n");
4613 }
4614 mutex_unlock(&dev_priv->rps.hw_lock);
4615
4616 if (cdclk == 400000) {
4617 u32 divider, vco;
4618
4619 vco = valleyview_get_vco(dev_priv);
4620 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4621
4622 mutex_lock(&dev_priv->dpio_lock);
4623 /* adjust cdclk divider */
4624 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4625 val &= ~DISPLAY_FREQUENCY_VALUES;
4626 val |= divider;
4627 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4628
4629 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4630 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4631 50))
4632 DRM_ERROR("timed out waiting for CDclk change\n");
4633 mutex_unlock(&dev_priv->dpio_lock);
4634 }
4635
4636 mutex_lock(&dev_priv->dpio_lock);
4637 /* adjust self-refresh exit latency value */
4638 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4639 val &= ~0x7f;
4640
4641 /*
4642 * For high bandwidth configs, we set a higher latency in the bunit
4643 * so that the core display fetch happens in time to avoid underruns.
4644 */
4645 if (cdclk == 400000)
4646 val |= 4500 / 250; /* 4.5 usec */
4647 else
4648 val |= 3000 / 250; /* 3.0 usec */
4649 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4650 mutex_unlock(&dev_priv->dpio_lock);
4651
4652 vlv_update_cdclk(dev);
4653 }
4654
4655 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4656 {
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 u32 val, cmd;
4659
4660 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4661
4662 switch (cdclk) {
4663 case 400000:
4664 cmd = 3;
4665 break;
4666 case 333333:
4667 case 320000:
4668 cmd = 2;
4669 break;
4670 case 266667:
4671 cmd = 1;
4672 break;
4673 case 200000:
4674 cmd = 0;
4675 break;
4676 default:
4677 WARN_ON(1);
4678 return;
4679 }
4680
4681 mutex_lock(&dev_priv->rps.hw_lock);
4682 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4683 val &= ~DSPFREQGUAR_MASK_CHV;
4684 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4685 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4686 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4687 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4688 50)) {
4689 DRM_ERROR("timed out waiting for CDclk change\n");
4690 }
4691 mutex_unlock(&dev_priv->rps.hw_lock);
4692
4693 vlv_update_cdclk(dev);
4694 }
4695
4696 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4697 int max_pixclk)
4698 {
4699 int vco = valleyview_get_vco(dev_priv);
4700 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4701
4702 /* FIXME: Punit isn't quite ready yet */
4703 if (IS_CHERRYVIEW(dev_priv->dev))
4704 return 400000;
4705
4706 /*
4707 * Really only a few cases to deal with, as only 4 CDclks are supported:
4708 * 200MHz
4709 * 267MHz
4710 * 320/333MHz (depends on HPLL freq)
4711 * 400MHz
4712 * So we check to see whether we're above 90% of the lower bin and
4713 * adjust if needed.
4714 *
4715 * We seem to get an unstable or solid color picture at 200MHz.
4716 * Not sure what's wrong. For now use 200MHz only when all pipes
4717 * are off.
4718 */
4719 if (max_pixclk > freq_320*9/10)
4720 return 400000;
4721 else if (max_pixclk > 266667*9/10)
4722 return freq_320;
4723 else if (max_pixclk > 0)
4724 return 266667;
4725 else
4726 return 200000;
4727 }
4728
4729 /* compute the max pixel clock for new configuration */
4730 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4731 {
4732 struct drm_device *dev = dev_priv->dev;
4733 struct intel_crtc *intel_crtc;
4734 int max_pixclk = 0;
4735
4736 for_each_intel_crtc(dev, intel_crtc) {
4737 if (intel_crtc->new_enabled)
4738 max_pixclk = max(max_pixclk,
4739 intel_crtc->new_config->adjusted_mode.crtc_clock);
4740 }
4741
4742 return max_pixclk;
4743 }
4744
4745 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4746 unsigned *prepare_pipes)
4747 {
4748 struct drm_i915_private *dev_priv = dev->dev_private;
4749 struct intel_crtc *intel_crtc;
4750 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4751
4752 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4753 dev_priv->vlv_cdclk_freq)
4754 return;
4755
4756 /* disable/enable all currently active pipes while we change cdclk */
4757 for_each_intel_crtc(dev, intel_crtc)
4758 if (intel_crtc->base.enabled)
4759 *prepare_pipes |= (1 << intel_crtc->pipe);
4760 }
4761
4762 static void valleyview_modeset_global_resources(struct drm_device *dev)
4763 {
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4766 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4767
4768 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4769 if (IS_CHERRYVIEW(dev))
4770 cherryview_set_cdclk(dev, req_cdclk);
4771 else
4772 valleyview_set_cdclk(dev, req_cdclk);
4773 }
4774
4775 modeset_update_crtc_power_domains(dev);
4776 }
4777
4778 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4779 {
4780 struct drm_device *dev = crtc->dev;
4781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782 struct intel_encoder *encoder;
4783 int pipe = intel_crtc->pipe;
4784 bool is_dsi;
4785
4786 WARN_ON(!crtc->enabled);
4787
4788 if (intel_crtc->active)
4789 return;
4790
4791 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4792
4793 if (!is_dsi) {
4794 if (IS_CHERRYVIEW(dev))
4795 chv_prepare_pll(intel_crtc);
4796 else
4797 vlv_prepare_pll(intel_crtc);
4798 }
4799
4800 if (intel_crtc->config.has_dp_encoder)
4801 intel_dp_set_m_n(intel_crtc);
4802
4803 intel_set_pipe_timings(intel_crtc);
4804
4805 i9xx_set_pipeconf(intel_crtc);
4806
4807 intel_crtc->active = true;
4808
4809 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4810
4811 for_each_encoder_on_crtc(dev, crtc, encoder)
4812 if (encoder->pre_pll_enable)
4813 encoder->pre_pll_enable(encoder);
4814
4815 if (!is_dsi) {
4816 if (IS_CHERRYVIEW(dev))
4817 chv_enable_pll(intel_crtc);
4818 else
4819 vlv_enable_pll(intel_crtc);
4820 }
4821
4822 for_each_encoder_on_crtc(dev, crtc, encoder)
4823 if (encoder->pre_enable)
4824 encoder->pre_enable(encoder);
4825
4826 i9xx_pfit_enable(intel_crtc);
4827
4828 intel_crtc_load_lut(crtc);
4829
4830 intel_update_watermarks(crtc);
4831 intel_enable_pipe(intel_crtc);
4832
4833 for_each_encoder_on_crtc(dev, crtc, encoder)
4834 encoder->enable(encoder);
4835
4836 intel_crtc_enable_planes(crtc);
4837
4838 /* Underruns don't raise interrupts, so check manually. */
4839 i9xx_check_fifo_underruns(dev);
4840 }
4841
4842 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4843 {
4844 struct drm_device *dev = crtc->base.dev;
4845 struct drm_i915_private *dev_priv = dev->dev_private;
4846
4847 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4848 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4849 }
4850
4851 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4852 {
4853 struct drm_device *dev = crtc->dev;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 struct intel_encoder *encoder;
4856 int pipe = intel_crtc->pipe;
4857
4858 WARN_ON(!crtc->enabled);
4859
4860 if (intel_crtc->active)
4861 return;
4862
4863 i9xx_set_pll_dividers(intel_crtc);
4864
4865 if (intel_crtc->config.has_dp_encoder)
4866 intel_dp_set_m_n(intel_crtc);
4867
4868 intel_set_pipe_timings(intel_crtc);
4869
4870 i9xx_set_pipeconf(intel_crtc);
4871
4872 intel_crtc->active = true;
4873
4874 if (!IS_GEN2(dev))
4875 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4876
4877 for_each_encoder_on_crtc(dev, crtc, encoder)
4878 if (encoder->pre_enable)
4879 encoder->pre_enable(encoder);
4880
4881 i9xx_enable_pll(intel_crtc);
4882
4883 i9xx_pfit_enable(intel_crtc);
4884
4885 intel_crtc_load_lut(crtc);
4886
4887 intel_update_watermarks(crtc);
4888 intel_enable_pipe(intel_crtc);
4889
4890 for_each_encoder_on_crtc(dev, crtc, encoder)
4891 encoder->enable(encoder);
4892
4893 intel_crtc_enable_planes(crtc);
4894
4895 /*
4896 * Gen2 reports pipe underruns whenever all planes are disabled.
4897 * So don't enable underrun reporting before at least some planes
4898 * are enabled.
4899 * FIXME: Need to fix the logic to work when we turn off all planes
4900 * but leave the pipe running.
4901 */
4902 if (IS_GEN2(dev))
4903 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4904
4905 /* Underruns don't raise interrupts, so check manually. */
4906 i9xx_check_fifo_underruns(dev);
4907 }
4908
4909 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4910 {
4911 struct drm_device *dev = crtc->base.dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913
4914 if (!crtc->config.gmch_pfit.control)
4915 return;
4916
4917 assert_pipe_disabled(dev_priv, crtc->pipe);
4918
4919 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4920 I915_READ(PFIT_CONTROL));
4921 I915_WRITE(PFIT_CONTROL, 0);
4922 }
4923
4924 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4925 {
4926 struct drm_device *dev = crtc->dev;
4927 struct drm_i915_private *dev_priv = dev->dev_private;
4928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4929 struct intel_encoder *encoder;
4930 int pipe = intel_crtc->pipe;
4931
4932 if (!intel_crtc->active)
4933 return;
4934
4935 /*
4936 * Gen2 reports pipe underruns whenever all planes are disabled.
4937 * So diasble underrun reporting before all the planes get disabled.
4938 * FIXME: Need to fix the logic to work when we turn off all planes
4939 * but leave the pipe running.
4940 */
4941 if (IS_GEN2(dev))
4942 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4943
4944 /*
4945 * Vblank time updates from the shadow to live plane control register
4946 * are blocked if the memory self-refresh mode is active at that
4947 * moment. So to make sure the plane gets truly disabled, disable
4948 * first the self-refresh mode. The self-refresh enable bit in turn
4949 * will be checked/applied by the HW only at the next frame start
4950 * event which is after the vblank start event, so we need to have a
4951 * wait-for-vblank between disabling the plane and the pipe.
4952 */
4953 intel_set_memory_cxsr(dev_priv, false);
4954 intel_crtc_disable_planes(crtc);
4955
4956 for_each_encoder_on_crtc(dev, crtc, encoder)
4957 encoder->disable(encoder);
4958
4959 /*
4960 * On gen2 planes are double buffered but the pipe isn't, so we must
4961 * wait for planes to fully turn off before disabling the pipe.
4962 * We also need to wait on all gmch platforms because of the
4963 * self-refresh mode constraint explained above.
4964 */
4965 intel_wait_for_vblank(dev, pipe);
4966
4967 intel_disable_pipe(intel_crtc);
4968
4969 i9xx_pfit_disable(intel_crtc);
4970
4971 for_each_encoder_on_crtc(dev, crtc, encoder)
4972 if (encoder->post_disable)
4973 encoder->post_disable(encoder);
4974
4975 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4976 if (IS_CHERRYVIEW(dev))
4977 chv_disable_pll(dev_priv, pipe);
4978 else if (IS_VALLEYVIEW(dev))
4979 vlv_disable_pll(dev_priv, pipe);
4980 else
4981 i9xx_disable_pll(intel_crtc);
4982 }
4983
4984 if (!IS_GEN2(dev))
4985 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4986
4987 intel_crtc->active = false;
4988 intel_update_watermarks(crtc);
4989
4990 mutex_lock(&dev->struct_mutex);
4991 intel_update_fbc(dev);
4992 mutex_unlock(&dev->struct_mutex);
4993 }
4994
4995 static void i9xx_crtc_off(struct drm_crtc *crtc)
4996 {
4997 }
4998
4999 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5000 bool enabled)
5001 {
5002 struct drm_device *dev = crtc->dev;
5003 struct drm_i915_master_private *master_priv;
5004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5005 int pipe = intel_crtc->pipe;
5006
5007 if (!dev->primary->master)
5008 return;
5009
5010 master_priv = dev->primary->master->driver_priv;
5011 if (!master_priv->sarea_priv)
5012 return;
5013
5014 switch (pipe) {
5015 case 0:
5016 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5017 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5018 break;
5019 case 1:
5020 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5021 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5022 break;
5023 default:
5024 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5025 break;
5026 }
5027 }
5028
5029 /* Master function to enable/disable CRTC and corresponding power wells */
5030 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5031 {
5032 struct drm_device *dev = crtc->dev;
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5035 enum intel_display_power_domain domain;
5036 unsigned long domains;
5037
5038 if (enable) {
5039 if (!intel_crtc->active) {
5040 domains = get_crtc_power_domains(crtc);
5041 for_each_power_domain(domain, domains)
5042 intel_display_power_get(dev_priv, domain);
5043 intel_crtc->enabled_power_domains = domains;
5044
5045 dev_priv->display.crtc_enable(crtc);
5046 }
5047 } else {
5048 if (intel_crtc->active) {
5049 dev_priv->display.crtc_disable(crtc);
5050
5051 domains = intel_crtc->enabled_power_domains;
5052 for_each_power_domain(domain, domains)
5053 intel_display_power_put(dev_priv, domain);
5054 intel_crtc->enabled_power_domains = 0;
5055 }
5056 }
5057 }
5058
5059 /**
5060 * Sets the power management mode of the pipe and plane.
5061 */
5062 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5063 {
5064 struct drm_device *dev = crtc->dev;
5065 struct intel_encoder *intel_encoder;
5066 bool enable = false;
5067
5068 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5069 enable |= intel_encoder->connectors_active;
5070
5071 intel_crtc_control(crtc, enable);
5072
5073 intel_crtc_update_sarea(crtc, enable);
5074 }
5075
5076 static void intel_crtc_disable(struct drm_crtc *crtc)
5077 {
5078 struct drm_device *dev = crtc->dev;
5079 struct drm_connector *connector;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5082 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5083
5084 /* crtc should still be enabled when we disable it. */
5085 WARN_ON(!crtc->enabled);
5086
5087 dev_priv->display.crtc_disable(crtc);
5088 intel_crtc_update_sarea(crtc, false);
5089 dev_priv->display.off(crtc);
5090
5091 if (crtc->primary->fb) {
5092 mutex_lock(&dev->struct_mutex);
5093 intel_unpin_fb_obj(old_obj);
5094 i915_gem_track_fb(old_obj, NULL,
5095 INTEL_FRONTBUFFER_PRIMARY(pipe));
5096 mutex_unlock(&dev->struct_mutex);
5097 crtc->primary->fb = NULL;
5098 }
5099
5100 /* Update computed state. */
5101 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5102 if (!connector->encoder || !connector->encoder->crtc)
5103 continue;
5104
5105 if (connector->encoder->crtc != crtc)
5106 continue;
5107
5108 connector->dpms = DRM_MODE_DPMS_OFF;
5109 to_intel_encoder(connector->encoder)->connectors_active = false;
5110 }
5111 }
5112
5113 void intel_encoder_destroy(struct drm_encoder *encoder)
5114 {
5115 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5116
5117 drm_encoder_cleanup(encoder);
5118 kfree(intel_encoder);
5119 }
5120
5121 /* Simple dpms helper for encoders with just one connector, no cloning and only
5122 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5123 * state of the entire output pipe. */
5124 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5125 {
5126 if (mode == DRM_MODE_DPMS_ON) {
5127 encoder->connectors_active = true;
5128
5129 intel_crtc_update_dpms(encoder->base.crtc);
5130 } else {
5131 encoder->connectors_active = false;
5132
5133 intel_crtc_update_dpms(encoder->base.crtc);
5134 }
5135 }
5136
5137 /* Cross check the actual hw state with our own modeset state tracking (and it's
5138 * internal consistency). */
5139 static void intel_connector_check_state(struct intel_connector *connector)
5140 {
5141 if (connector->get_hw_state(connector)) {
5142 struct intel_encoder *encoder = connector->encoder;
5143 struct drm_crtc *crtc;
5144 bool encoder_enabled;
5145 enum pipe pipe;
5146
5147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5148 connector->base.base.id,
5149 connector->base.name);
5150
5151 /* there is no real hw state for MST connectors */
5152 if (connector->mst_port)
5153 return;
5154
5155 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5156 "wrong connector dpms state\n");
5157 WARN(connector->base.encoder != &encoder->base,
5158 "active connector not linked to encoder\n");
5159
5160 if (encoder) {
5161 WARN(!encoder->connectors_active,
5162 "encoder->connectors_active not set\n");
5163
5164 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5165 WARN(!encoder_enabled, "encoder not enabled\n");
5166 if (WARN_ON(!encoder->base.crtc))
5167 return;
5168
5169 crtc = encoder->base.crtc;
5170
5171 WARN(!crtc->enabled, "crtc not enabled\n");
5172 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5173 WARN(pipe != to_intel_crtc(crtc)->pipe,
5174 "encoder active on the wrong pipe\n");
5175 }
5176 }
5177 }
5178
5179 /* Even simpler default implementation, if there's really no special case to
5180 * consider. */
5181 void intel_connector_dpms(struct drm_connector *connector, int mode)
5182 {
5183 /* All the simple cases only support two dpms states. */
5184 if (mode != DRM_MODE_DPMS_ON)
5185 mode = DRM_MODE_DPMS_OFF;
5186
5187 if (mode == connector->dpms)
5188 return;
5189
5190 connector->dpms = mode;
5191
5192 /* Only need to change hw state when actually enabled */
5193 if (connector->encoder)
5194 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5195
5196 intel_modeset_check_state(connector->dev);
5197 }
5198
5199 /* Simple connector->get_hw_state implementation for encoders that support only
5200 * one connector and no cloning and hence the encoder state determines the state
5201 * of the connector. */
5202 bool intel_connector_get_hw_state(struct intel_connector *connector)
5203 {
5204 enum pipe pipe = 0;
5205 struct intel_encoder *encoder = connector->encoder;
5206
5207 return encoder->get_hw_state(encoder, &pipe);
5208 }
5209
5210 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5211 struct intel_crtc_config *pipe_config)
5212 {
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 struct intel_crtc *pipe_B_crtc =
5215 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5216
5217 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5218 pipe_name(pipe), pipe_config->fdi_lanes);
5219 if (pipe_config->fdi_lanes > 4) {
5220 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5221 pipe_name(pipe), pipe_config->fdi_lanes);
5222 return false;
5223 }
5224
5225 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5226 if (pipe_config->fdi_lanes > 2) {
5227 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5228 pipe_config->fdi_lanes);
5229 return false;
5230 } else {
5231 return true;
5232 }
5233 }
5234
5235 if (INTEL_INFO(dev)->num_pipes == 2)
5236 return true;
5237
5238 /* Ivybridge 3 pipe is really complicated */
5239 switch (pipe) {
5240 case PIPE_A:
5241 return true;
5242 case PIPE_B:
5243 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5244 pipe_config->fdi_lanes > 2) {
5245 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5246 pipe_name(pipe), pipe_config->fdi_lanes);
5247 return false;
5248 }
5249 return true;
5250 case PIPE_C:
5251 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5252 pipe_B_crtc->config.fdi_lanes <= 2) {
5253 if (pipe_config->fdi_lanes > 2) {
5254 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5255 pipe_name(pipe), pipe_config->fdi_lanes);
5256 return false;
5257 }
5258 } else {
5259 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5260 return false;
5261 }
5262 return true;
5263 default:
5264 BUG();
5265 }
5266 }
5267
5268 #define RETRY 1
5269 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5270 struct intel_crtc_config *pipe_config)
5271 {
5272 struct drm_device *dev = intel_crtc->base.dev;
5273 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5274 int lane, link_bw, fdi_dotclock;
5275 bool setup_ok, needs_recompute = false;
5276
5277 retry:
5278 /* FDI is a binary signal running at ~2.7GHz, encoding
5279 * each output octet as 10 bits. The actual frequency
5280 * is stored as a divider into a 100MHz clock, and the
5281 * mode pixel clock is stored in units of 1KHz.
5282 * Hence the bw of each lane in terms of the mode signal
5283 * is:
5284 */
5285 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5286
5287 fdi_dotclock = adjusted_mode->crtc_clock;
5288
5289 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5290 pipe_config->pipe_bpp);
5291
5292 pipe_config->fdi_lanes = lane;
5293
5294 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5295 link_bw, &pipe_config->fdi_m_n);
5296
5297 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5298 intel_crtc->pipe, pipe_config);
5299 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5300 pipe_config->pipe_bpp -= 2*3;
5301 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5302 pipe_config->pipe_bpp);
5303 needs_recompute = true;
5304 pipe_config->bw_constrained = true;
5305
5306 goto retry;
5307 }
5308
5309 if (needs_recompute)
5310 return RETRY;
5311
5312 return setup_ok ? 0 : -EINVAL;
5313 }
5314
5315 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5316 struct intel_crtc_config *pipe_config)
5317 {
5318 pipe_config->ips_enabled = i915.enable_ips &&
5319 hsw_crtc_supports_ips(crtc) &&
5320 pipe_config->pipe_bpp <= 24;
5321 }
5322
5323 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5324 struct intel_crtc_config *pipe_config)
5325 {
5326 struct drm_device *dev = crtc->base.dev;
5327 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5328
5329 /* FIXME should check pixel clock limits on all platforms */
5330 if (INTEL_INFO(dev)->gen < 4) {
5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 int clock_limit =
5333 dev_priv->display.get_display_clock_speed(dev);
5334
5335 /*
5336 * Enable pixel doubling when the dot clock
5337 * is > 90% of the (display) core speed.
5338 *
5339 * GDG double wide on either pipe,
5340 * otherwise pipe A only.
5341 */
5342 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5343 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5344 clock_limit *= 2;
5345 pipe_config->double_wide = true;
5346 }
5347
5348 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5349 return -EINVAL;
5350 }
5351
5352 /*
5353 * Pipe horizontal size must be even in:
5354 * - DVO ganged mode
5355 * - LVDS dual channel mode
5356 * - Double wide pipe
5357 */
5358 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5359 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5360 pipe_config->pipe_src_w &= ~1;
5361
5362 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5363 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5364 */
5365 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5366 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5367 return -EINVAL;
5368
5369 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5370 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5371 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5372 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5373 * for lvds. */
5374 pipe_config->pipe_bpp = 8*3;
5375 }
5376
5377 if (HAS_IPS(dev))
5378 hsw_compute_ips_config(crtc, pipe_config);
5379
5380 /*
5381 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5382 * old clock survives for now.
5383 */
5384 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5385 pipe_config->shared_dpll = crtc->config.shared_dpll;
5386
5387 if (pipe_config->has_pch_encoder)
5388 return ironlake_fdi_compute_config(crtc, pipe_config);
5389
5390 return 0;
5391 }
5392
5393 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5394 {
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 int vco = valleyview_get_vco(dev_priv);
5397 u32 val;
5398 int divider;
5399
5400 /* FIXME: Punit isn't quite ready yet */
5401 if (IS_CHERRYVIEW(dev))
5402 return 400000;
5403
5404 mutex_lock(&dev_priv->dpio_lock);
5405 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5406 mutex_unlock(&dev_priv->dpio_lock);
5407
5408 divider = val & DISPLAY_FREQUENCY_VALUES;
5409
5410 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5411 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5412 "cdclk change in progress\n");
5413
5414 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5415 }
5416
5417 static int i945_get_display_clock_speed(struct drm_device *dev)
5418 {
5419 return 400000;
5420 }
5421
5422 static int i915_get_display_clock_speed(struct drm_device *dev)
5423 {
5424 return 333000;
5425 }
5426
5427 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5428 {
5429 return 200000;
5430 }
5431
5432 static int pnv_get_display_clock_speed(struct drm_device *dev)
5433 {
5434 u16 gcfgc = 0;
5435
5436 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5437
5438 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5439 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5440 return 267000;
5441 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5442 return 333000;
5443 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5444 return 444000;
5445 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5446 return 200000;
5447 default:
5448 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5449 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5450 return 133000;
5451 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5452 return 167000;
5453 }
5454 }
5455
5456 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5457 {
5458 u16 gcfgc = 0;
5459
5460 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5461
5462 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5463 return 133000;
5464 else {
5465 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5466 case GC_DISPLAY_CLOCK_333_MHZ:
5467 return 333000;
5468 default:
5469 case GC_DISPLAY_CLOCK_190_200_MHZ:
5470 return 190000;
5471 }
5472 }
5473 }
5474
5475 static int i865_get_display_clock_speed(struct drm_device *dev)
5476 {
5477 return 266000;
5478 }
5479
5480 static int i855_get_display_clock_speed(struct drm_device *dev)
5481 {
5482 u16 hpllcc = 0;
5483 /* Assume that the hardware is in the high speed state. This
5484 * should be the default.
5485 */
5486 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5487 case GC_CLOCK_133_200:
5488 case GC_CLOCK_100_200:
5489 return 200000;
5490 case GC_CLOCK_166_250:
5491 return 250000;
5492 case GC_CLOCK_100_133:
5493 return 133000;
5494 }
5495
5496 /* Shouldn't happen */
5497 return 0;
5498 }
5499
5500 static int i830_get_display_clock_speed(struct drm_device *dev)
5501 {
5502 return 133000;
5503 }
5504
5505 static void
5506 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5507 {
5508 while (*num > DATA_LINK_M_N_MASK ||
5509 *den > DATA_LINK_M_N_MASK) {
5510 *num >>= 1;
5511 *den >>= 1;
5512 }
5513 }
5514
5515 static void compute_m_n(unsigned int m, unsigned int n,
5516 uint32_t *ret_m, uint32_t *ret_n)
5517 {
5518 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5519 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5520 intel_reduce_m_n_ratio(ret_m, ret_n);
5521 }
5522
5523 void
5524 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5525 int pixel_clock, int link_clock,
5526 struct intel_link_m_n *m_n)
5527 {
5528 m_n->tu = 64;
5529
5530 compute_m_n(bits_per_pixel * pixel_clock,
5531 link_clock * nlanes * 8,
5532 &m_n->gmch_m, &m_n->gmch_n);
5533
5534 compute_m_n(pixel_clock, link_clock,
5535 &m_n->link_m, &m_n->link_n);
5536 }
5537
5538 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5539 {
5540 if (i915.panel_use_ssc >= 0)
5541 return i915.panel_use_ssc != 0;
5542 return dev_priv->vbt.lvds_use_ssc
5543 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5544 }
5545
5546 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5547 {
5548 struct drm_device *dev = crtc->dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550 int refclk;
5551
5552 if (IS_VALLEYVIEW(dev)) {
5553 refclk = 100000;
5554 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5555 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5556 refclk = dev_priv->vbt.lvds_ssc_freq;
5557 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5558 } else if (!IS_GEN2(dev)) {
5559 refclk = 96000;
5560 } else {
5561 refclk = 48000;
5562 }
5563
5564 return refclk;
5565 }
5566
5567 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5568 {
5569 return (1 << dpll->n) << 16 | dpll->m2;
5570 }
5571
5572 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5573 {
5574 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5575 }
5576
5577 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5578 intel_clock_t *reduced_clock)
5579 {
5580 struct drm_device *dev = crtc->base.dev;
5581 u32 fp, fp2 = 0;
5582
5583 if (IS_PINEVIEW(dev)) {
5584 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5585 if (reduced_clock)
5586 fp2 = pnv_dpll_compute_fp(reduced_clock);
5587 } else {
5588 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5589 if (reduced_clock)
5590 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5591 }
5592
5593 crtc->config.dpll_hw_state.fp0 = fp;
5594
5595 crtc->lowfreq_avail = false;
5596 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5597 reduced_clock && i915.powersave) {
5598 crtc->config.dpll_hw_state.fp1 = fp2;
5599 crtc->lowfreq_avail = true;
5600 } else {
5601 crtc->config.dpll_hw_state.fp1 = fp;
5602 }
5603 }
5604
5605 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5606 pipe)
5607 {
5608 u32 reg_val;
5609
5610 /*
5611 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5612 * and set it to a reasonable value instead.
5613 */
5614 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5615 reg_val &= 0xffffff00;
5616 reg_val |= 0x00000030;
5617 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5618
5619 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5620 reg_val &= 0x8cffffff;
5621 reg_val = 0x8c000000;
5622 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5623
5624 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5625 reg_val &= 0xffffff00;
5626 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5627
5628 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5629 reg_val &= 0x00ffffff;
5630 reg_val |= 0xb0000000;
5631 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5632 }
5633
5634 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5635 struct intel_link_m_n *m_n)
5636 {
5637 struct drm_device *dev = crtc->base.dev;
5638 struct drm_i915_private *dev_priv = dev->dev_private;
5639 int pipe = crtc->pipe;
5640
5641 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5642 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5643 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5644 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5645 }
5646
5647 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5648 struct intel_link_m_n *m_n,
5649 struct intel_link_m_n *m2_n2)
5650 {
5651 struct drm_device *dev = crtc->base.dev;
5652 struct drm_i915_private *dev_priv = dev->dev_private;
5653 int pipe = crtc->pipe;
5654 enum transcoder transcoder = crtc->config.cpu_transcoder;
5655
5656 if (INTEL_INFO(dev)->gen >= 5) {
5657 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5658 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5659 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5660 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5661 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5662 * for gen < 8) and if DRRS is supported (to make sure the
5663 * registers are not unnecessarily accessed).
5664 */
5665 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5666 crtc->config.has_drrs) {
5667 I915_WRITE(PIPE_DATA_M2(transcoder),
5668 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5669 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5670 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5671 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5672 }
5673 } else {
5674 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5675 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5676 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5677 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5678 }
5679 }
5680
5681 void intel_dp_set_m_n(struct intel_crtc *crtc)
5682 {
5683 if (crtc->config.has_pch_encoder)
5684 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5685 else
5686 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5687 &crtc->config.dp_m2_n2);
5688 }
5689
5690 static void vlv_update_pll(struct intel_crtc *crtc)
5691 {
5692 u32 dpll, dpll_md;
5693
5694 /*
5695 * Enable DPIO clock input. We should never disable the reference
5696 * clock for pipe B, since VGA hotplug / manual detection depends
5697 * on it.
5698 */
5699 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5700 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5701 /* We should never disable this, set it here for state tracking */
5702 if (crtc->pipe == PIPE_B)
5703 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5704 dpll |= DPLL_VCO_ENABLE;
5705 crtc->config.dpll_hw_state.dpll = dpll;
5706
5707 dpll_md = (crtc->config.pixel_multiplier - 1)
5708 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5709 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5710 }
5711
5712 static void vlv_prepare_pll(struct intel_crtc *crtc)
5713 {
5714 struct drm_device *dev = crtc->base.dev;
5715 struct drm_i915_private *dev_priv = dev->dev_private;
5716 int pipe = crtc->pipe;
5717 u32 mdiv;
5718 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5719 u32 coreclk, reg_val;
5720
5721 mutex_lock(&dev_priv->dpio_lock);
5722
5723 bestn = crtc->config.dpll.n;
5724 bestm1 = crtc->config.dpll.m1;
5725 bestm2 = crtc->config.dpll.m2;
5726 bestp1 = crtc->config.dpll.p1;
5727 bestp2 = crtc->config.dpll.p2;
5728
5729 /* See eDP HDMI DPIO driver vbios notes doc */
5730
5731 /* PLL B needs special handling */
5732 if (pipe == PIPE_B)
5733 vlv_pllb_recal_opamp(dev_priv, pipe);
5734
5735 /* Set up Tx target for periodic Rcomp update */
5736 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5737
5738 /* Disable target IRef on PLL */
5739 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5740 reg_val &= 0x00ffffff;
5741 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5742
5743 /* Disable fast lock */
5744 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5745
5746 /* Set idtafcrecal before PLL is enabled */
5747 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5748 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5749 mdiv |= ((bestn << DPIO_N_SHIFT));
5750 mdiv |= (1 << DPIO_K_SHIFT);
5751
5752 /*
5753 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5754 * but we don't support that).
5755 * Note: don't use the DAC post divider as it seems unstable.
5756 */
5757 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5758 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5759
5760 mdiv |= DPIO_ENABLE_CALIBRATION;
5761 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5762
5763 /* Set HBR and RBR LPF coefficients */
5764 if (crtc->config.port_clock == 162000 ||
5765 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5766 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5767 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5768 0x009f0003);
5769 else
5770 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5771 0x00d0000f);
5772
5773 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5774 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5775 /* Use SSC source */
5776 if (pipe == PIPE_A)
5777 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5778 0x0df40000);
5779 else
5780 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5781 0x0df70000);
5782 } else { /* HDMI or VGA */
5783 /* Use bend source */
5784 if (pipe == PIPE_A)
5785 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5786 0x0df70000);
5787 else
5788 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5789 0x0df40000);
5790 }
5791
5792 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5793 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5794 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5795 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5796 coreclk |= 0x01000000;
5797 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5798
5799 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5800 mutex_unlock(&dev_priv->dpio_lock);
5801 }
5802
5803 static void chv_update_pll(struct intel_crtc *crtc)
5804 {
5805 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5806 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5807 DPLL_VCO_ENABLE;
5808 if (crtc->pipe != PIPE_A)
5809 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5810
5811 crtc->config.dpll_hw_state.dpll_md =
5812 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5813 }
5814
5815 static void chv_prepare_pll(struct intel_crtc *crtc)
5816 {
5817 struct drm_device *dev = crtc->base.dev;
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 int pipe = crtc->pipe;
5820 int dpll_reg = DPLL(crtc->pipe);
5821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5822 u32 loopfilter, intcoeff;
5823 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5824 int refclk;
5825
5826 bestn = crtc->config.dpll.n;
5827 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5828 bestm1 = crtc->config.dpll.m1;
5829 bestm2 = crtc->config.dpll.m2 >> 22;
5830 bestp1 = crtc->config.dpll.p1;
5831 bestp2 = crtc->config.dpll.p2;
5832
5833 /*
5834 * Enable Refclk and SSC
5835 */
5836 I915_WRITE(dpll_reg,
5837 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5838
5839 mutex_lock(&dev_priv->dpio_lock);
5840
5841 /* p1 and p2 divider */
5842 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5843 5 << DPIO_CHV_S1_DIV_SHIFT |
5844 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5845 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5846 1 << DPIO_CHV_K_DIV_SHIFT);
5847
5848 /* Feedback post-divider - m2 */
5849 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5850
5851 /* Feedback refclk divider - n and m1 */
5852 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5853 DPIO_CHV_M1_DIV_BY_2 |
5854 1 << DPIO_CHV_N_DIV_SHIFT);
5855
5856 /* M2 fraction division */
5857 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5858
5859 /* M2 fraction division enable */
5860 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5861 DPIO_CHV_FRAC_DIV_EN |
5862 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5863
5864 /* Loop filter */
5865 refclk = i9xx_get_refclk(&crtc->base, 0);
5866 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5867 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5868 if (refclk == 100000)
5869 intcoeff = 11;
5870 else if (refclk == 38400)
5871 intcoeff = 10;
5872 else
5873 intcoeff = 9;
5874 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5875 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5876
5877 /* AFC Recal */
5878 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5879 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5880 DPIO_AFC_RECAL);
5881
5882 mutex_unlock(&dev_priv->dpio_lock);
5883 }
5884
5885 static void i9xx_update_pll(struct intel_crtc *crtc,
5886 intel_clock_t *reduced_clock,
5887 int num_connectors)
5888 {
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 u32 dpll;
5892 bool is_sdvo;
5893 struct dpll *clock = &crtc->config.dpll;
5894
5895 i9xx_update_pll_dividers(crtc, reduced_clock);
5896
5897 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5898 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5899
5900 dpll = DPLL_VGA_MODE_DIS;
5901
5902 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5903 dpll |= DPLLB_MODE_LVDS;
5904 else
5905 dpll |= DPLLB_MODE_DAC_SERIAL;
5906
5907 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5908 dpll |= (crtc->config.pixel_multiplier - 1)
5909 << SDVO_MULTIPLIER_SHIFT_HIRES;
5910 }
5911
5912 if (is_sdvo)
5913 dpll |= DPLL_SDVO_HIGH_SPEED;
5914
5915 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5916 dpll |= DPLL_SDVO_HIGH_SPEED;
5917
5918 /* compute bitmask from p1 value */
5919 if (IS_PINEVIEW(dev))
5920 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5921 else {
5922 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5923 if (IS_G4X(dev) && reduced_clock)
5924 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5925 }
5926 switch (clock->p2) {
5927 case 5:
5928 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5929 break;
5930 case 7:
5931 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5932 break;
5933 case 10:
5934 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5935 break;
5936 case 14:
5937 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5938 break;
5939 }
5940 if (INTEL_INFO(dev)->gen >= 4)
5941 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5942
5943 if (crtc->config.sdvo_tv_clock)
5944 dpll |= PLL_REF_INPUT_TVCLKINBC;
5945 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5946 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5947 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5948 else
5949 dpll |= PLL_REF_INPUT_DREFCLK;
5950
5951 dpll |= DPLL_VCO_ENABLE;
5952 crtc->config.dpll_hw_state.dpll = dpll;
5953
5954 if (INTEL_INFO(dev)->gen >= 4) {
5955 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5956 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5957 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5958 }
5959 }
5960
5961 static void i8xx_update_pll(struct intel_crtc *crtc,
5962 intel_clock_t *reduced_clock,
5963 int num_connectors)
5964 {
5965 struct drm_device *dev = crtc->base.dev;
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 u32 dpll;
5968 struct dpll *clock = &crtc->config.dpll;
5969
5970 i9xx_update_pll_dividers(crtc, reduced_clock);
5971
5972 dpll = DPLL_VGA_MODE_DIS;
5973
5974 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5975 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5976 } else {
5977 if (clock->p1 == 2)
5978 dpll |= PLL_P1_DIVIDE_BY_TWO;
5979 else
5980 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5981 if (clock->p2 == 4)
5982 dpll |= PLL_P2_DIVIDE_BY_4;
5983 }
5984
5985 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5986 dpll |= DPLL_DVO_2X_MODE;
5987
5988 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5989 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5991 else
5992 dpll |= PLL_REF_INPUT_DREFCLK;
5993
5994 dpll |= DPLL_VCO_ENABLE;
5995 crtc->config.dpll_hw_state.dpll = dpll;
5996 }
5997
5998 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5999 {
6000 struct drm_device *dev = intel_crtc->base.dev;
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 enum pipe pipe = intel_crtc->pipe;
6003 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6004 struct drm_display_mode *adjusted_mode =
6005 &intel_crtc->config.adjusted_mode;
6006 uint32_t crtc_vtotal, crtc_vblank_end;
6007 int vsyncshift = 0;
6008
6009 /* We need to be careful not to changed the adjusted mode, for otherwise
6010 * the hw state checker will get angry at the mismatch. */
6011 crtc_vtotal = adjusted_mode->crtc_vtotal;
6012 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6013
6014 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6015 /* the chip adds 2 halflines automatically */
6016 crtc_vtotal -= 1;
6017 crtc_vblank_end -= 1;
6018
6019 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6020 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6021 else
6022 vsyncshift = adjusted_mode->crtc_hsync_start -
6023 adjusted_mode->crtc_htotal / 2;
6024 if (vsyncshift < 0)
6025 vsyncshift += adjusted_mode->crtc_htotal;
6026 }
6027
6028 if (INTEL_INFO(dev)->gen > 3)
6029 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6030
6031 I915_WRITE(HTOTAL(cpu_transcoder),
6032 (adjusted_mode->crtc_hdisplay - 1) |
6033 ((adjusted_mode->crtc_htotal - 1) << 16));
6034 I915_WRITE(HBLANK(cpu_transcoder),
6035 (adjusted_mode->crtc_hblank_start - 1) |
6036 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6037 I915_WRITE(HSYNC(cpu_transcoder),
6038 (adjusted_mode->crtc_hsync_start - 1) |
6039 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6040
6041 I915_WRITE(VTOTAL(cpu_transcoder),
6042 (adjusted_mode->crtc_vdisplay - 1) |
6043 ((crtc_vtotal - 1) << 16));
6044 I915_WRITE(VBLANK(cpu_transcoder),
6045 (adjusted_mode->crtc_vblank_start - 1) |
6046 ((crtc_vblank_end - 1) << 16));
6047 I915_WRITE(VSYNC(cpu_transcoder),
6048 (adjusted_mode->crtc_vsync_start - 1) |
6049 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6050
6051 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6052 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6053 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6054 * bits. */
6055 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6056 (pipe == PIPE_B || pipe == PIPE_C))
6057 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6058
6059 /* pipesrc controls the size that is scaled from, which should
6060 * always be the user's requested size.
6061 */
6062 I915_WRITE(PIPESRC(pipe),
6063 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6064 (intel_crtc->config.pipe_src_h - 1));
6065 }
6066
6067 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6068 struct intel_crtc_config *pipe_config)
6069 {
6070 struct drm_device *dev = crtc->base.dev;
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6073 uint32_t tmp;
6074
6075 tmp = I915_READ(HTOTAL(cpu_transcoder));
6076 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6077 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6078 tmp = I915_READ(HBLANK(cpu_transcoder));
6079 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6080 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6081 tmp = I915_READ(HSYNC(cpu_transcoder));
6082 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6083 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6084
6085 tmp = I915_READ(VTOTAL(cpu_transcoder));
6086 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6087 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6088 tmp = I915_READ(VBLANK(cpu_transcoder));
6089 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6090 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6091 tmp = I915_READ(VSYNC(cpu_transcoder));
6092 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6093 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6094
6095 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6096 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6097 pipe_config->adjusted_mode.crtc_vtotal += 1;
6098 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6099 }
6100
6101 tmp = I915_READ(PIPESRC(crtc->pipe));
6102 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6103 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6104
6105 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6106 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6107 }
6108
6109 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6110 struct intel_crtc_config *pipe_config)
6111 {
6112 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6113 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6114 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6115 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6116
6117 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6118 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6119 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6120 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6121
6122 mode->flags = pipe_config->adjusted_mode.flags;
6123
6124 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6125 mode->flags |= pipe_config->adjusted_mode.flags;
6126 }
6127
6128 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6129 {
6130 struct drm_device *dev = intel_crtc->base.dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 uint32_t pipeconf;
6133
6134 pipeconf = 0;
6135
6136 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6137 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6138 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6139
6140 if (intel_crtc->config.double_wide)
6141 pipeconf |= PIPECONF_DOUBLE_WIDE;
6142
6143 /* only g4x and later have fancy bpc/dither controls */
6144 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6145 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6146 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6147 pipeconf |= PIPECONF_DITHER_EN |
6148 PIPECONF_DITHER_TYPE_SP;
6149
6150 switch (intel_crtc->config.pipe_bpp) {
6151 case 18:
6152 pipeconf |= PIPECONF_6BPC;
6153 break;
6154 case 24:
6155 pipeconf |= PIPECONF_8BPC;
6156 break;
6157 case 30:
6158 pipeconf |= PIPECONF_10BPC;
6159 break;
6160 default:
6161 /* Case prevented by intel_choose_pipe_bpp_dither. */
6162 BUG();
6163 }
6164 }
6165
6166 if (HAS_PIPE_CXSR(dev)) {
6167 if (intel_crtc->lowfreq_avail) {
6168 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6169 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6170 } else {
6171 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6172 }
6173 }
6174
6175 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6176 if (INTEL_INFO(dev)->gen < 4 ||
6177 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6178 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6179 else
6180 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6181 } else
6182 pipeconf |= PIPECONF_PROGRESSIVE;
6183
6184 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6185 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6186
6187 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6188 POSTING_READ(PIPECONF(intel_crtc->pipe));
6189 }
6190
6191 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6192 int x, int y,
6193 struct drm_framebuffer *fb)
6194 {
6195 struct drm_device *dev = crtc->dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6198 int refclk, num_connectors = 0;
6199 intel_clock_t clock, reduced_clock;
6200 bool ok, has_reduced_clock = false;
6201 bool is_lvds = false, is_dsi = false;
6202 struct intel_encoder *encoder;
6203 const intel_limit_t *limit;
6204
6205 for_each_encoder_on_crtc(dev, crtc, encoder) {
6206 switch (encoder->type) {
6207 case INTEL_OUTPUT_LVDS:
6208 is_lvds = true;
6209 break;
6210 case INTEL_OUTPUT_DSI:
6211 is_dsi = true;
6212 break;
6213 }
6214
6215 num_connectors++;
6216 }
6217
6218 if (is_dsi)
6219 return 0;
6220
6221 if (!intel_crtc->config.clock_set) {
6222 refclk = i9xx_get_refclk(crtc, num_connectors);
6223
6224 /*
6225 * Returns a set of divisors for the desired target clock with
6226 * the given refclk, or FALSE. The returned values represent
6227 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6228 * 2) / p1 / p2.
6229 */
6230 limit = intel_limit(crtc, refclk);
6231 ok = dev_priv->display.find_dpll(limit, crtc,
6232 intel_crtc->config.port_clock,
6233 refclk, NULL, &clock);
6234 if (!ok) {
6235 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6236 return -EINVAL;
6237 }
6238
6239 if (is_lvds && dev_priv->lvds_downclock_avail) {
6240 /*
6241 * Ensure we match the reduced clock's P to the target
6242 * clock. If the clocks don't match, we can't switch
6243 * the display clock by using the FP0/FP1. In such case
6244 * we will disable the LVDS downclock feature.
6245 */
6246 has_reduced_clock =
6247 dev_priv->display.find_dpll(limit, crtc,
6248 dev_priv->lvds_downclock,
6249 refclk, &clock,
6250 &reduced_clock);
6251 }
6252 /* Compat-code for transition, will disappear. */
6253 intel_crtc->config.dpll.n = clock.n;
6254 intel_crtc->config.dpll.m1 = clock.m1;
6255 intel_crtc->config.dpll.m2 = clock.m2;
6256 intel_crtc->config.dpll.p1 = clock.p1;
6257 intel_crtc->config.dpll.p2 = clock.p2;
6258 }
6259
6260 if (IS_GEN2(dev)) {
6261 i8xx_update_pll(intel_crtc,
6262 has_reduced_clock ? &reduced_clock : NULL,
6263 num_connectors);
6264 } else if (IS_CHERRYVIEW(dev)) {
6265 chv_update_pll(intel_crtc);
6266 } else if (IS_VALLEYVIEW(dev)) {
6267 vlv_update_pll(intel_crtc);
6268 } else {
6269 i9xx_update_pll(intel_crtc,
6270 has_reduced_clock ? &reduced_clock : NULL,
6271 num_connectors);
6272 }
6273
6274 return 0;
6275 }
6276
6277 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6278 struct intel_crtc_config *pipe_config)
6279 {
6280 struct drm_device *dev = crtc->base.dev;
6281 struct drm_i915_private *dev_priv = dev->dev_private;
6282 uint32_t tmp;
6283
6284 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6285 return;
6286
6287 tmp = I915_READ(PFIT_CONTROL);
6288 if (!(tmp & PFIT_ENABLE))
6289 return;
6290
6291 /* Check whether the pfit is attached to our pipe. */
6292 if (INTEL_INFO(dev)->gen < 4) {
6293 if (crtc->pipe != PIPE_B)
6294 return;
6295 } else {
6296 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6297 return;
6298 }
6299
6300 pipe_config->gmch_pfit.control = tmp;
6301 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6302 if (INTEL_INFO(dev)->gen < 5)
6303 pipe_config->gmch_pfit.lvds_border_bits =
6304 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6305 }
6306
6307 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6308 struct intel_crtc_config *pipe_config)
6309 {
6310 struct drm_device *dev = crtc->base.dev;
6311 struct drm_i915_private *dev_priv = dev->dev_private;
6312 int pipe = pipe_config->cpu_transcoder;
6313 intel_clock_t clock;
6314 u32 mdiv;
6315 int refclk = 100000;
6316
6317 /* In case of MIPI DPLL will not even be used */
6318 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6319 return;
6320
6321 mutex_lock(&dev_priv->dpio_lock);
6322 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6323 mutex_unlock(&dev_priv->dpio_lock);
6324
6325 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6326 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6327 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6328 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6329 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6330
6331 vlv_clock(refclk, &clock);
6332
6333 /* clock.dot is the fast clock */
6334 pipe_config->port_clock = clock.dot / 5;
6335 }
6336
6337 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6338 struct intel_plane_config *plane_config)
6339 {
6340 struct drm_device *dev = crtc->base.dev;
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 u32 val, base, offset;
6343 int pipe = crtc->pipe, plane = crtc->plane;
6344 int fourcc, pixel_format;
6345 int aligned_height;
6346
6347 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6348 if (!crtc->base.primary->fb) {
6349 DRM_DEBUG_KMS("failed to alloc fb\n");
6350 return;
6351 }
6352
6353 val = I915_READ(DSPCNTR(plane));
6354
6355 if (INTEL_INFO(dev)->gen >= 4)
6356 if (val & DISPPLANE_TILED)
6357 plane_config->tiled = true;
6358
6359 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6360 fourcc = intel_format_to_fourcc(pixel_format);
6361 crtc->base.primary->fb->pixel_format = fourcc;
6362 crtc->base.primary->fb->bits_per_pixel =
6363 drm_format_plane_cpp(fourcc, 0) * 8;
6364
6365 if (INTEL_INFO(dev)->gen >= 4) {
6366 if (plane_config->tiled)
6367 offset = I915_READ(DSPTILEOFF(plane));
6368 else
6369 offset = I915_READ(DSPLINOFF(plane));
6370 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6371 } else {
6372 base = I915_READ(DSPADDR(plane));
6373 }
6374 plane_config->base = base;
6375
6376 val = I915_READ(PIPESRC(pipe));
6377 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6378 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6379
6380 val = I915_READ(DSPSTRIDE(pipe));
6381 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6382
6383 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6384 plane_config->tiled);
6385
6386 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6387 aligned_height);
6388
6389 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6390 pipe, plane, crtc->base.primary->fb->width,
6391 crtc->base.primary->fb->height,
6392 crtc->base.primary->fb->bits_per_pixel, base,
6393 crtc->base.primary->fb->pitches[0],
6394 plane_config->size);
6395
6396 }
6397
6398 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6399 struct intel_crtc_config *pipe_config)
6400 {
6401 struct drm_device *dev = crtc->base.dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 int pipe = pipe_config->cpu_transcoder;
6404 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6405 intel_clock_t clock;
6406 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6407 int refclk = 100000;
6408
6409 mutex_lock(&dev_priv->dpio_lock);
6410 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6411 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6412 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6413 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6414 mutex_unlock(&dev_priv->dpio_lock);
6415
6416 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6417 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6418 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6419 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6420 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6421
6422 chv_clock(refclk, &clock);
6423
6424 /* clock.dot is the fast clock */
6425 pipe_config->port_clock = clock.dot / 5;
6426 }
6427
6428 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6429 struct intel_crtc_config *pipe_config)
6430 {
6431 struct drm_device *dev = crtc->base.dev;
6432 struct drm_i915_private *dev_priv = dev->dev_private;
6433 uint32_t tmp;
6434
6435 if (!intel_display_power_enabled(dev_priv,
6436 POWER_DOMAIN_PIPE(crtc->pipe)))
6437 return false;
6438
6439 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6440 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6441
6442 tmp = I915_READ(PIPECONF(crtc->pipe));
6443 if (!(tmp & PIPECONF_ENABLE))
6444 return false;
6445
6446 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6447 switch (tmp & PIPECONF_BPC_MASK) {
6448 case PIPECONF_6BPC:
6449 pipe_config->pipe_bpp = 18;
6450 break;
6451 case PIPECONF_8BPC:
6452 pipe_config->pipe_bpp = 24;
6453 break;
6454 case PIPECONF_10BPC:
6455 pipe_config->pipe_bpp = 30;
6456 break;
6457 default:
6458 break;
6459 }
6460 }
6461
6462 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6463 pipe_config->limited_color_range = true;
6464
6465 if (INTEL_INFO(dev)->gen < 4)
6466 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6467
6468 intel_get_pipe_timings(crtc, pipe_config);
6469
6470 i9xx_get_pfit_config(crtc, pipe_config);
6471
6472 if (INTEL_INFO(dev)->gen >= 4) {
6473 tmp = I915_READ(DPLL_MD(crtc->pipe));
6474 pipe_config->pixel_multiplier =
6475 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6476 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6477 pipe_config->dpll_hw_state.dpll_md = tmp;
6478 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6479 tmp = I915_READ(DPLL(crtc->pipe));
6480 pipe_config->pixel_multiplier =
6481 ((tmp & SDVO_MULTIPLIER_MASK)
6482 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6483 } else {
6484 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6485 * port and will be fixed up in the encoder->get_config
6486 * function. */
6487 pipe_config->pixel_multiplier = 1;
6488 }
6489 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6490 if (!IS_VALLEYVIEW(dev)) {
6491 /*
6492 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6493 * on 830. Filter it out here so that we don't
6494 * report errors due to that.
6495 */
6496 if (IS_I830(dev))
6497 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6498
6499 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6500 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6501 } else {
6502 /* Mask out read-only status bits. */
6503 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6504 DPLL_PORTC_READY_MASK |
6505 DPLL_PORTB_READY_MASK);
6506 }
6507
6508 if (IS_CHERRYVIEW(dev))
6509 chv_crtc_clock_get(crtc, pipe_config);
6510 else if (IS_VALLEYVIEW(dev))
6511 vlv_crtc_clock_get(crtc, pipe_config);
6512 else
6513 i9xx_crtc_clock_get(crtc, pipe_config);
6514
6515 return true;
6516 }
6517
6518 static void ironlake_init_pch_refclk(struct drm_device *dev)
6519 {
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 struct intel_encoder *encoder;
6522 u32 val, final;
6523 bool has_lvds = false;
6524 bool has_cpu_edp = false;
6525 bool has_panel = false;
6526 bool has_ck505 = false;
6527 bool can_ssc = false;
6528
6529 /* We need to take the global config into account */
6530 for_each_intel_encoder(dev, encoder) {
6531 switch (encoder->type) {
6532 case INTEL_OUTPUT_LVDS:
6533 has_panel = true;
6534 has_lvds = true;
6535 break;
6536 case INTEL_OUTPUT_EDP:
6537 has_panel = true;
6538 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6539 has_cpu_edp = true;
6540 break;
6541 }
6542 }
6543
6544 if (HAS_PCH_IBX(dev)) {
6545 has_ck505 = dev_priv->vbt.display_clock_mode;
6546 can_ssc = has_ck505;
6547 } else {
6548 has_ck505 = false;
6549 can_ssc = true;
6550 }
6551
6552 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6553 has_panel, has_lvds, has_ck505);
6554
6555 /* Ironlake: try to setup display ref clock before DPLL
6556 * enabling. This is only under driver's control after
6557 * PCH B stepping, previous chipset stepping should be
6558 * ignoring this setting.
6559 */
6560 val = I915_READ(PCH_DREF_CONTROL);
6561
6562 /* As we must carefully and slowly disable/enable each source in turn,
6563 * compute the final state we want first and check if we need to
6564 * make any changes at all.
6565 */
6566 final = val;
6567 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6568 if (has_ck505)
6569 final |= DREF_NONSPREAD_CK505_ENABLE;
6570 else
6571 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6572
6573 final &= ~DREF_SSC_SOURCE_MASK;
6574 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6575 final &= ~DREF_SSC1_ENABLE;
6576
6577 if (has_panel) {
6578 final |= DREF_SSC_SOURCE_ENABLE;
6579
6580 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6581 final |= DREF_SSC1_ENABLE;
6582
6583 if (has_cpu_edp) {
6584 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6585 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6586 else
6587 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6588 } else
6589 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6590 } else {
6591 final |= DREF_SSC_SOURCE_DISABLE;
6592 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6593 }
6594
6595 if (final == val)
6596 return;
6597
6598 /* Always enable nonspread source */
6599 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6600
6601 if (has_ck505)
6602 val |= DREF_NONSPREAD_CK505_ENABLE;
6603 else
6604 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6605
6606 if (has_panel) {
6607 val &= ~DREF_SSC_SOURCE_MASK;
6608 val |= DREF_SSC_SOURCE_ENABLE;
6609
6610 /* SSC must be turned on before enabling the CPU output */
6611 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6612 DRM_DEBUG_KMS("Using SSC on panel\n");
6613 val |= DREF_SSC1_ENABLE;
6614 } else
6615 val &= ~DREF_SSC1_ENABLE;
6616
6617 /* Get SSC going before enabling the outputs */
6618 I915_WRITE(PCH_DREF_CONTROL, val);
6619 POSTING_READ(PCH_DREF_CONTROL);
6620 udelay(200);
6621
6622 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6623
6624 /* Enable CPU source on CPU attached eDP */
6625 if (has_cpu_edp) {
6626 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6627 DRM_DEBUG_KMS("Using SSC on eDP\n");
6628 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6629 } else
6630 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6631 } else
6632 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6633
6634 I915_WRITE(PCH_DREF_CONTROL, val);
6635 POSTING_READ(PCH_DREF_CONTROL);
6636 udelay(200);
6637 } else {
6638 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6639
6640 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6641
6642 /* Turn off CPU output */
6643 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6644
6645 I915_WRITE(PCH_DREF_CONTROL, val);
6646 POSTING_READ(PCH_DREF_CONTROL);
6647 udelay(200);
6648
6649 /* Turn off the SSC source */
6650 val &= ~DREF_SSC_SOURCE_MASK;
6651 val |= DREF_SSC_SOURCE_DISABLE;
6652
6653 /* Turn off SSC1 */
6654 val &= ~DREF_SSC1_ENABLE;
6655
6656 I915_WRITE(PCH_DREF_CONTROL, val);
6657 POSTING_READ(PCH_DREF_CONTROL);
6658 udelay(200);
6659 }
6660
6661 BUG_ON(val != final);
6662 }
6663
6664 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6665 {
6666 uint32_t tmp;
6667
6668 tmp = I915_READ(SOUTH_CHICKEN2);
6669 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6670 I915_WRITE(SOUTH_CHICKEN2, tmp);
6671
6672 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6673 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6674 DRM_ERROR("FDI mPHY reset assert timeout\n");
6675
6676 tmp = I915_READ(SOUTH_CHICKEN2);
6677 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6678 I915_WRITE(SOUTH_CHICKEN2, tmp);
6679
6680 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6681 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6682 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6683 }
6684
6685 /* WaMPhyProgramming:hsw */
6686 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6687 {
6688 uint32_t tmp;
6689
6690 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6691 tmp &= ~(0xFF << 24);
6692 tmp |= (0x12 << 24);
6693 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6694
6695 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6696 tmp |= (1 << 11);
6697 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6698
6699 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6700 tmp |= (1 << 11);
6701 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6702
6703 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6704 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6705 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6706
6707 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6708 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6709 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6710
6711 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6712 tmp &= ~(7 << 13);
6713 tmp |= (5 << 13);
6714 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6715
6716 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6717 tmp &= ~(7 << 13);
6718 tmp |= (5 << 13);
6719 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6720
6721 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6722 tmp &= ~0xFF;
6723 tmp |= 0x1C;
6724 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6725
6726 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6727 tmp &= ~0xFF;
6728 tmp |= 0x1C;
6729 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6730
6731 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6732 tmp &= ~(0xFF << 16);
6733 tmp |= (0x1C << 16);
6734 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6735
6736 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6737 tmp &= ~(0xFF << 16);
6738 tmp |= (0x1C << 16);
6739 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6740
6741 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6742 tmp |= (1 << 27);
6743 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6744
6745 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6746 tmp |= (1 << 27);
6747 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6748
6749 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6750 tmp &= ~(0xF << 28);
6751 tmp |= (4 << 28);
6752 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6753
6754 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6755 tmp &= ~(0xF << 28);
6756 tmp |= (4 << 28);
6757 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6758 }
6759
6760 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6761 * Programming" based on the parameters passed:
6762 * - Sequence to enable CLKOUT_DP
6763 * - Sequence to enable CLKOUT_DP without spread
6764 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6765 */
6766 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6767 bool with_fdi)
6768 {
6769 struct drm_i915_private *dev_priv = dev->dev_private;
6770 uint32_t reg, tmp;
6771
6772 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6773 with_spread = true;
6774 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6775 with_fdi, "LP PCH doesn't have FDI\n"))
6776 with_fdi = false;
6777
6778 mutex_lock(&dev_priv->dpio_lock);
6779
6780 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6781 tmp &= ~SBI_SSCCTL_DISABLE;
6782 tmp |= SBI_SSCCTL_PATHALT;
6783 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6784
6785 udelay(24);
6786
6787 if (with_spread) {
6788 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6789 tmp &= ~SBI_SSCCTL_PATHALT;
6790 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6791
6792 if (with_fdi) {
6793 lpt_reset_fdi_mphy(dev_priv);
6794 lpt_program_fdi_mphy(dev_priv);
6795 }
6796 }
6797
6798 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6799 SBI_GEN0 : SBI_DBUFF0;
6800 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6801 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6802 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6803
6804 mutex_unlock(&dev_priv->dpio_lock);
6805 }
6806
6807 /* Sequence to disable CLKOUT_DP */
6808 static void lpt_disable_clkout_dp(struct drm_device *dev)
6809 {
6810 struct drm_i915_private *dev_priv = dev->dev_private;
6811 uint32_t reg, tmp;
6812
6813 mutex_lock(&dev_priv->dpio_lock);
6814
6815 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6816 SBI_GEN0 : SBI_DBUFF0;
6817 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6818 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6819 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6820
6821 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6822 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6823 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6824 tmp |= SBI_SSCCTL_PATHALT;
6825 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6826 udelay(32);
6827 }
6828 tmp |= SBI_SSCCTL_DISABLE;
6829 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6830 }
6831
6832 mutex_unlock(&dev_priv->dpio_lock);
6833 }
6834
6835 static void lpt_init_pch_refclk(struct drm_device *dev)
6836 {
6837 struct intel_encoder *encoder;
6838 bool has_vga = false;
6839
6840 for_each_intel_encoder(dev, encoder) {
6841 switch (encoder->type) {
6842 case INTEL_OUTPUT_ANALOG:
6843 has_vga = true;
6844 break;
6845 }
6846 }
6847
6848 if (has_vga)
6849 lpt_enable_clkout_dp(dev, true, true);
6850 else
6851 lpt_disable_clkout_dp(dev);
6852 }
6853
6854 /*
6855 * Initialize reference clocks when the driver loads
6856 */
6857 void intel_init_pch_refclk(struct drm_device *dev)
6858 {
6859 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6860 ironlake_init_pch_refclk(dev);
6861 else if (HAS_PCH_LPT(dev))
6862 lpt_init_pch_refclk(dev);
6863 }
6864
6865 static int ironlake_get_refclk(struct drm_crtc *crtc)
6866 {
6867 struct drm_device *dev = crtc->dev;
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_encoder *encoder;
6870 int num_connectors = 0;
6871 bool is_lvds = false;
6872
6873 for_each_encoder_on_crtc(dev, crtc, encoder) {
6874 switch (encoder->type) {
6875 case INTEL_OUTPUT_LVDS:
6876 is_lvds = true;
6877 break;
6878 }
6879 num_connectors++;
6880 }
6881
6882 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6883 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6884 dev_priv->vbt.lvds_ssc_freq);
6885 return dev_priv->vbt.lvds_ssc_freq;
6886 }
6887
6888 return 120000;
6889 }
6890
6891 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6892 {
6893 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895 int pipe = intel_crtc->pipe;
6896 uint32_t val;
6897
6898 val = 0;
6899
6900 switch (intel_crtc->config.pipe_bpp) {
6901 case 18:
6902 val |= PIPECONF_6BPC;
6903 break;
6904 case 24:
6905 val |= PIPECONF_8BPC;
6906 break;
6907 case 30:
6908 val |= PIPECONF_10BPC;
6909 break;
6910 case 36:
6911 val |= PIPECONF_12BPC;
6912 break;
6913 default:
6914 /* Case prevented by intel_choose_pipe_bpp_dither. */
6915 BUG();
6916 }
6917
6918 if (intel_crtc->config.dither)
6919 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6920
6921 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6922 val |= PIPECONF_INTERLACED_ILK;
6923 else
6924 val |= PIPECONF_PROGRESSIVE;
6925
6926 if (intel_crtc->config.limited_color_range)
6927 val |= PIPECONF_COLOR_RANGE_SELECT;
6928
6929 I915_WRITE(PIPECONF(pipe), val);
6930 POSTING_READ(PIPECONF(pipe));
6931 }
6932
6933 /*
6934 * Set up the pipe CSC unit.
6935 *
6936 * Currently only full range RGB to limited range RGB conversion
6937 * is supported, but eventually this should handle various
6938 * RGB<->YCbCr scenarios as well.
6939 */
6940 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6941 {
6942 struct drm_device *dev = crtc->dev;
6943 struct drm_i915_private *dev_priv = dev->dev_private;
6944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6945 int pipe = intel_crtc->pipe;
6946 uint16_t coeff = 0x7800; /* 1.0 */
6947
6948 /*
6949 * TODO: Check what kind of values actually come out of the pipe
6950 * with these coeff/postoff values and adjust to get the best
6951 * accuracy. Perhaps we even need to take the bpc value into
6952 * consideration.
6953 */
6954
6955 if (intel_crtc->config.limited_color_range)
6956 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6957
6958 /*
6959 * GY/GU and RY/RU should be the other way around according
6960 * to BSpec, but reality doesn't agree. Just set them up in
6961 * a way that results in the correct picture.
6962 */
6963 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6964 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6965
6966 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6967 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6968
6969 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6970 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6971
6972 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6973 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6974 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6975
6976 if (INTEL_INFO(dev)->gen > 6) {
6977 uint16_t postoff = 0;
6978
6979 if (intel_crtc->config.limited_color_range)
6980 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6981
6982 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6983 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6984 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6985
6986 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6987 } else {
6988 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6989
6990 if (intel_crtc->config.limited_color_range)
6991 mode |= CSC_BLACK_SCREEN_OFFSET;
6992
6993 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6994 }
6995 }
6996
6997 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6998 {
6999 struct drm_device *dev = crtc->dev;
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7002 enum pipe pipe = intel_crtc->pipe;
7003 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7004 uint32_t val;
7005
7006 val = 0;
7007
7008 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7009 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7010
7011 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7012 val |= PIPECONF_INTERLACED_ILK;
7013 else
7014 val |= PIPECONF_PROGRESSIVE;
7015
7016 I915_WRITE(PIPECONF(cpu_transcoder), val);
7017 POSTING_READ(PIPECONF(cpu_transcoder));
7018
7019 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7020 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7021
7022 if (IS_BROADWELL(dev)) {
7023 val = 0;
7024
7025 switch (intel_crtc->config.pipe_bpp) {
7026 case 18:
7027 val |= PIPEMISC_DITHER_6_BPC;
7028 break;
7029 case 24:
7030 val |= PIPEMISC_DITHER_8_BPC;
7031 break;
7032 case 30:
7033 val |= PIPEMISC_DITHER_10_BPC;
7034 break;
7035 case 36:
7036 val |= PIPEMISC_DITHER_12_BPC;
7037 break;
7038 default:
7039 /* Case prevented by pipe_config_set_bpp. */
7040 BUG();
7041 }
7042
7043 if (intel_crtc->config.dither)
7044 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7045
7046 I915_WRITE(PIPEMISC(pipe), val);
7047 }
7048 }
7049
7050 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7051 intel_clock_t *clock,
7052 bool *has_reduced_clock,
7053 intel_clock_t *reduced_clock)
7054 {
7055 struct drm_device *dev = crtc->dev;
7056 struct drm_i915_private *dev_priv = dev->dev_private;
7057 struct intel_encoder *intel_encoder;
7058 int refclk;
7059 const intel_limit_t *limit;
7060 bool ret, is_lvds = false;
7061
7062 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7063 switch (intel_encoder->type) {
7064 case INTEL_OUTPUT_LVDS:
7065 is_lvds = true;
7066 break;
7067 }
7068 }
7069
7070 refclk = ironlake_get_refclk(crtc);
7071
7072 /*
7073 * Returns a set of divisors for the desired target clock with the given
7074 * refclk, or FALSE. The returned values represent the clock equation:
7075 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7076 */
7077 limit = intel_limit(crtc, refclk);
7078 ret = dev_priv->display.find_dpll(limit, crtc,
7079 to_intel_crtc(crtc)->config.port_clock,
7080 refclk, NULL, clock);
7081 if (!ret)
7082 return false;
7083
7084 if (is_lvds && dev_priv->lvds_downclock_avail) {
7085 /*
7086 * Ensure we match the reduced clock's P to the target clock.
7087 * If the clocks don't match, we can't switch the display clock
7088 * by using the FP0/FP1. In such case we will disable the LVDS
7089 * downclock feature.
7090 */
7091 *has_reduced_clock =
7092 dev_priv->display.find_dpll(limit, crtc,
7093 dev_priv->lvds_downclock,
7094 refclk, clock,
7095 reduced_clock);
7096 }
7097
7098 return true;
7099 }
7100
7101 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7102 {
7103 /*
7104 * Account for spread spectrum to avoid
7105 * oversubscribing the link. Max center spread
7106 * is 2.5%; use 5% for safety's sake.
7107 */
7108 u32 bps = target_clock * bpp * 21 / 20;
7109 return DIV_ROUND_UP(bps, link_bw * 8);
7110 }
7111
7112 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7113 {
7114 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7115 }
7116
7117 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7118 u32 *fp,
7119 intel_clock_t *reduced_clock, u32 *fp2)
7120 {
7121 struct drm_crtc *crtc = &intel_crtc->base;
7122 struct drm_device *dev = crtc->dev;
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 struct intel_encoder *intel_encoder;
7125 uint32_t dpll;
7126 int factor, num_connectors = 0;
7127 bool is_lvds = false, is_sdvo = false;
7128
7129 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7130 switch (intel_encoder->type) {
7131 case INTEL_OUTPUT_LVDS:
7132 is_lvds = true;
7133 break;
7134 case INTEL_OUTPUT_SDVO:
7135 case INTEL_OUTPUT_HDMI:
7136 is_sdvo = true;
7137 break;
7138 }
7139
7140 num_connectors++;
7141 }
7142
7143 /* Enable autotuning of the PLL clock (if permissible) */
7144 factor = 21;
7145 if (is_lvds) {
7146 if ((intel_panel_use_ssc(dev_priv) &&
7147 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7148 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7149 factor = 25;
7150 } else if (intel_crtc->config.sdvo_tv_clock)
7151 factor = 20;
7152
7153 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7154 *fp |= FP_CB_TUNE;
7155
7156 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7157 *fp2 |= FP_CB_TUNE;
7158
7159 dpll = 0;
7160
7161 if (is_lvds)
7162 dpll |= DPLLB_MODE_LVDS;
7163 else
7164 dpll |= DPLLB_MODE_DAC_SERIAL;
7165
7166 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7167 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7168
7169 if (is_sdvo)
7170 dpll |= DPLL_SDVO_HIGH_SPEED;
7171 if (intel_crtc->config.has_dp_encoder)
7172 dpll |= DPLL_SDVO_HIGH_SPEED;
7173
7174 /* compute bitmask from p1 value */
7175 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7176 /* also FPA1 */
7177 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7178
7179 switch (intel_crtc->config.dpll.p2) {
7180 case 5:
7181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7182 break;
7183 case 7:
7184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7185 break;
7186 case 10:
7187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7188 break;
7189 case 14:
7190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7191 break;
7192 }
7193
7194 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7195 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7196 else
7197 dpll |= PLL_REF_INPUT_DREFCLK;
7198
7199 return dpll | DPLL_VCO_ENABLE;
7200 }
7201
7202 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7203 int x, int y,
7204 struct drm_framebuffer *fb)
7205 {
7206 struct drm_device *dev = crtc->dev;
7207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7208 int num_connectors = 0;
7209 intel_clock_t clock, reduced_clock;
7210 u32 dpll = 0, fp = 0, fp2 = 0;
7211 bool ok, has_reduced_clock = false;
7212 bool is_lvds = false;
7213 struct intel_encoder *encoder;
7214 struct intel_shared_dpll *pll;
7215
7216 for_each_encoder_on_crtc(dev, crtc, encoder) {
7217 switch (encoder->type) {
7218 case INTEL_OUTPUT_LVDS:
7219 is_lvds = true;
7220 break;
7221 }
7222
7223 num_connectors++;
7224 }
7225
7226 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7227 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7228
7229 ok = ironlake_compute_clocks(crtc, &clock,
7230 &has_reduced_clock, &reduced_clock);
7231 if (!ok && !intel_crtc->config.clock_set) {
7232 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7233 return -EINVAL;
7234 }
7235 /* Compat-code for transition, will disappear. */
7236 if (!intel_crtc->config.clock_set) {
7237 intel_crtc->config.dpll.n = clock.n;
7238 intel_crtc->config.dpll.m1 = clock.m1;
7239 intel_crtc->config.dpll.m2 = clock.m2;
7240 intel_crtc->config.dpll.p1 = clock.p1;
7241 intel_crtc->config.dpll.p2 = clock.p2;
7242 }
7243
7244 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7245 if (intel_crtc->config.has_pch_encoder) {
7246 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7247 if (has_reduced_clock)
7248 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7249
7250 dpll = ironlake_compute_dpll(intel_crtc,
7251 &fp, &reduced_clock,
7252 has_reduced_clock ? &fp2 : NULL);
7253
7254 intel_crtc->config.dpll_hw_state.dpll = dpll;
7255 intel_crtc->config.dpll_hw_state.fp0 = fp;
7256 if (has_reduced_clock)
7257 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7258 else
7259 intel_crtc->config.dpll_hw_state.fp1 = fp;
7260
7261 pll = intel_get_shared_dpll(intel_crtc);
7262 if (pll == NULL) {
7263 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7264 pipe_name(intel_crtc->pipe));
7265 return -EINVAL;
7266 }
7267 } else
7268 intel_put_shared_dpll(intel_crtc);
7269
7270 if (is_lvds && has_reduced_clock && i915.powersave)
7271 intel_crtc->lowfreq_avail = true;
7272 else
7273 intel_crtc->lowfreq_avail = false;
7274
7275 return 0;
7276 }
7277
7278 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7279 struct intel_link_m_n *m_n)
7280 {
7281 struct drm_device *dev = crtc->base.dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 enum pipe pipe = crtc->pipe;
7284
7285 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7286 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7287 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7288 & ~TU_SIZE_MASK;
7289 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7290 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7291 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7292 }
7293
7294 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7295 enum transcoder transcoder,
7296 struct intel_link_m_n *m_n,
7297 struct intel_link_m_n *m2_n2)
7298 {
7299 struct drm_device *dev = crtc->base.dev;
7300 struct drm_i915_private *dev_priv = dev->dev_private;
7301 enum pipe pipe = crtc->pipe;
7302
7303 if (INTEL_INFO(dev)->gen >= 5) {
7304 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7305 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7306 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7307 & ~TU_SIZE_MASK;
7308 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7309 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7310 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7311 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7312 * gen < 8) and if DRRS is supported (to make sure the
7313 * registers are not unnecessarily read).
7314 */
7315 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7316 crtc->config.has_drrs) {
7317 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7318 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7319 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7320 & ~TU_SIZE_MASK;
7321 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7322 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7323 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7324 }
7325 } else {
7326 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7327 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7328 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7329 & ~TU_SIZE_MASK;
7330 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7331 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7332 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7333 }
7334 }
7335
7336 void intel_dp_get_m_n(struct intel_crtc *crtc,
7337 struct intel_crtc_config *pipe_config)
7338 {
7339 if (crtc->config.has_pch_encoder)
7340 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7341 else
7342 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7343 &pipe_config->dp_m_n,
7344 &pipe_config->dp_m2_n2);
7345 }
7346
7347 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7348 struct intel_crtc_config *pipe_config)
7349 {
7350 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7351 &pipe_config->fdi_m_n, NULL);
7352 }
7353
7354 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7355 struct intel_crtc_config *pipe_config)
7356 {
7357 struct drm_device *dev = crtc->base.dev;
7358 struct drm_i915_private *dev_priv = dev->dev_private;
7359 uint32_t tmp;
7360
7361 tmp = I915_READ(PF_CTL(crtc->pipe));
7362
7363 if (tmp & PF_ENABLE) {
7364 pipe_config->pch_pfit.enabled = true;
7365 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7366 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7367
7368 /* We currently do not free assignements of panel fitters on
7369 * ivb/hsw (since we don't use the higher upscaling modes which
7370 * differentiates them) so just WARN about this case for now. */
7371 if (IS_GEN7(dev)) {
7372 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7373 PF_PIPE_SEL_IVB(crtc->pipe));
7374 }
7375 }
7376 }
7377
7378 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7379 struct intel_plane_config *plane_config)
7380 {
7381 struct drm_device *dev = crtc->base.dev;
7382 struct drm_i915_private *dev_priv = dev->dev_private;
7383 u32 val, base, offset;
7384 int pipe = crtc->pipe, plane = crtc->plane;
7385 int fourcc, pixel_format;
7386 int aligned_height;
7387
7388 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7389 if (!crtc->base.primary->fb) {
7390 DRM_DEBUG_KMS("failed to alloc fb\n");
7391 return;
7392 }
7393
7394 val = I915_READ(DSPCNTR(plane));
7395
7396 if (INTEL_INFO(dev)->gen >= 4)
7397 if (val & DISPPLANE_TILED)
7398 plane_config->tiled = true;
7399
7400 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7401 fourcc = intel_format_to_fourcc(pixel_format);
7402 crtc->base.primary->fb->pixel_format = fourcc;
7403 crtc->base.primary->fb->bits_per_pixel =
7404 drm_format_plane_cpp(fourcc, 0) * 8;
7405
7406 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7407 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7408 offset = I915_READ(DSPOFFSET(plane));
7409 } else {
7410 if (plane_config->tiled)
7411 offset = I915_READ(DSPTILEOFF(plane));
7412 else
7413 offset = I915_READ(DSPLINOFF(plane));
7414 }
7415 plane_config->base = base;
7416
7417 val = I915_READ(PIPESRC(pipe));
7418 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7419 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7420
7421 val = I915_READ(DSPSTRIDE(pipe));
7422 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7423
7424 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7425 plane_config->tiled);
7426
7427 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7428 aligned_height);
7429
7430 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7431 pipe, plane, crtc->base.primary->fb->width,
7432 crtc->base.primary->fb->height,
7433 crtc->base.primary->fb->bits_per_pixel, base,
7434 crtc->base.primary->fb->pitches[0],
7435 plane_config->size);
7436 }
7437
7438 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7439 struct intel_crtc_config *pipe_config)
7440 {
7441 struct drm_device *dev = crtc->base.dev;
7442 struct drm_i915_private *dev_priv = dev->dev_private;
7443 uint32_t tmp;
7444
7445 if (!intel_display_power_enabled(dev_priv,
7446 POWER_DOMAIN_PIPE(crtc->pipe)))
7447 return false;
7448
7449 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7450 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7451
7452 tmp = I915_READ(PIPECONF(crtc->pipe));
7453 if (!(tmp & PIPECONF_ENABLE))
7454 return false;
7455
7456 switch (tmp & PIPECONF_BPC_MASK) {
7457 case PIPECONF_6BPC:
7458 pipe_config->pipe_bpp = 18;
7459 break;
7460 case PIPECONF_8BPC:
7461 pipe_config->pipe_bpp = 24;
7462 break;
7463 case PIPECONF_10BPC:
7464 pipe_config->pipe_bpp = 30;
7465 break;
7466 case PIPECONF_12BPC:
7467 pipe_config->pipe_bpp = 36;
7468 break;
7469 default:
7470 break;
7471 }
7472
7473 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7474 pipe_config->limited_color_range = true;
7475
7476 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7477 struct intel_shared_dpll *pll;
7478
7479 pipe_config->has_pch_encoder = true;
7480
7481 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7482 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7483 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7484
7485 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7486
7487 if (HAS_PCH_IBX(dev_priv->dev)) {
7488 pipe_config->shared_dpll =
7489 (enum intel_dpll_id) crtc->pipe;
7490 } else {
7491 tmp = I915_READ(PCH_DPLL_SEL);
7492 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7493 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7494 else
7495 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7496 }
7497
7498 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7499
7500 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7501 &pipe_config->dpll_hw_state));
7502
7503 tmp = pipe_config->dpll_hw_state.dpll;
7504 pipe_config->pixel_multiplier =
7505 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7506 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7507
7508 ironlake_pch_clock_get(crtc, pipe_config);
7509 } else {
7510 pipe_config->pixel_multiplier = 1;
7511 }
7512
7513 intel_get_pipe_timings(crtc, pipe_config);
7514
7515 ironlake_get_pfit_config(crtc, pipe_config);
7516
7517 return true;
7518 }
7519
7520 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7521 {
7522 struct drm_device *dev = dev_priv->dev;
7523 struct intel_crtc *crtc;
7524
7525 for_each_intel_crtc(dev, crtc)
7526 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7527 pipe_name(crtc->pipe));
7528
7529 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7530 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7531 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7532 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7533 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7534 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7535 "CPU PWM1 enabled\n");
7536 if (IS_HASWELL(dev))
7537 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7538 "CPU PWM2 enabled\n");
7539 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7540 "PCH PWM1 enabled\n");
7541 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7542 "Utility pin enabled\n");
7543 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7544
7545 /*
7546 * In theory we can still leave IRQs enabled, as long as only the HPD
7547 * interrupts remain enabled. We used to check for that, but since it's
7548 * gen-specific and since we only disable LCPLL after we fully disable
7549 * the interrupts, the check below should be enough.
7550 */
7551 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7552 }
7553
7554 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7555 {
7556 struct drm_device *dev = dev_priv->dev;
7557
7558 if (IS_HASWELL(dev))
7559 return I915_READ(D_COMP_HSW);
7560 else
7561 return I915_READ(D_COMP_BDW);
7562 }
7563
7564 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7565 {
7566 struct drm_device *dev = dev_priv->dev;
7567
7568 if (IS_HASWELL(dev)) {
7569 mutex_lock(&dev_priv->rps.hw_lock);
7570 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7571 val))
7572 DRM_ERROR("Failed to write to D_COMP\n");
7573 mutex_unlock(&dev_priv->rps.hw_lock);
7574 } else {
7575 I915_WRITE(D_COMP_BDW, val);
7576 POSTING_READ(D_COMP_BDW);
7577 }
7578 }
7579
7580 /*
7581 * This function implements pieces of two sequences from BSpec:
7582 * - Sequence for display software to disable LCPLL
7583 * - Sequence for display software to allow package C8+
7584 * The steps implemented here are just the steps that actually touch the LCPLL
7585 * register. Callers should take care of disabling all the display engine
7586 * functions, doing the mode unset, fixing interrupts, etc.
7587 */
7588 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7589 bool switch_to_fclk, bool allow_power_down)
7590 {
7591 uint32_t val;
7592
7593 assert_can_disable_lcpll(dev_priv);
7594
7595 val = I915_READ(LCPLL_CTL);
7596
7597 if (switch_to_fclk) {
7598 val |= LCPLL_CD_SOURCE_FCLK;
7599 I915_WRITE(LCPLL_CTL, val);
7600
7601 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7602 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7603 DRM_ERROR("Switching to FCLK failed\n");
7604
7605 val = I915_READ(LCPLL_CTL);
7606 }
7607
7608 val |= LCPLL_PLL_DISABLE;
7609 I915_WRITE(LCPLL_CTL, val);
7610 POSTING_READ(LCPLL_CTL);
7611
7612 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7613 DRM_ERROR("LCPLL still locked\n");
7614
7615 val = hsw_read_dcomp(dev_priv);
7616 val |= D_COMP_COMP_DISABLE;
7617 hsw_write_dcomp(dev_priv, val);
7618 ndelay(100);
7619
7620 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7621 1))
7622 DRM_ERROR("D_COMP RCOMP still in progress\n");
7623
7624 if (allow_power_down) {
7625 val = I915_READ(LCPLL_CTL);
7626 val |= LCPLL_POWER_DOWN_ALLOW;
7627 I915_WRITE(LCPLL_CTL, val);
7628 POSTING_READ(LCPLL_CTL);
7629 }
7630 }
7631
7632 /*
7633 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7634 * source.
7635 */
7636 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7637 {
7638 uint32_t val;
7639 unsigned long irqflags;
7640
7641 val = I915_READ(LCPLL_CTL);
7642
7643 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7644 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7645 return;
7646
7647 /*
7648 * Make sure we're not on PC8 state before disabling PC8, otherwise
7649 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7650 *
7651 * The other problem is that hsw_restore_lcpll() is called as part of
7652 * the runtime PM resume sequence, so we can't just call
7653 * gen6_gt_force_wake_get() because that function calls
7654 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7655 * while we are on the resume sequence. So to solve this problem we have
7656 * to call special forcewake code that doesn't touch runtime PM and
7657 * doesn't enable the forcewake delayed work.
7658 */
7659 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7660 if (dev_priv->uncore.forcewake_count++ == 0)
7661 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7662 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7663
7664 if (val & LCPLL_POWER_DOWN_ALLOW) {
7665 val &= ~LCPLL_POWER_DOWN_ALLOW;
7666 I915_WRITE(LCPLL_CTL, val);
7667 POSTING_READ(LCPLL_CTL);
7668 }
7669
7670 val = hsw_read_dcomp(dev_priv);
7671 val |= D_COMP_COMP_FORCE;
7672 val &= ~D_COMP_COMP_DISABLE;
7673 hsw_write_dcomp(dev_priv, val);
7674
7675 val = I915_READ(LCPLL_CTL);
7676 val &= ~LCPLL_PLL_DISABLE;
7677 I915_WRITE(LCPLL_CTL, val);
7678
7679 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7680 DRM_ERROR("LCPLL not locked yet\n");
7681
7682 if (val & LCPLL_CD_SOURCE_FCLK) {
7683 val = I915_READ(LCPLL_CTL);
7684 val &= ~LCPLL_CD_SOURCE_FCLK;
7685 I915_WRITE(LCPLL_CTL, val);
7686
7687 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7688 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7689 DRM_ERROR("Switching back to LCPLL failed\n");
7690 }
7691
7692 /* See the big comment above. */
7693 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7694 if (--dev_priv->uncore.forcewake_count == 0)
7695 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7696 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7697 }
7698
7699 /*
7700 * Package states C8 and deeper are really deep PC states that can only be
7701 * reached when all the devices on the system allow it, so even if the graphics
7702 * device allows PC8+, it doesn't mean the system will actually get to these
7703 * states. Our driver only allows PC8+ when going into runtime PM.
7704 *
7705 * The requirements for PC8+ are that all the outputs are disabled, the power
7706 * well is disabled and most interrupts are disabled, and these are also
7707 * requirements for runtime PM. When these conditions are met, we manually do
7708 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7709 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7710 * hang the machine.
7711 *
7712 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7713 * the state of some registers, so when we come back from PC8+ we need to
7714 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7715 * need to take care of the registers kept by RC6. Notice that this happens even
7716 * if we don't put the device in PCI D3 state (which is what currently happens
7717 * because of the runtime PM support).
7718 *
7719 * For more, read "Display Sequences for Package C8" on the hardware
7720 * documentation.
7721 */
7722 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7723 {
7724 struct drm_device *dev = dev_priv->dev;
7725 uint32_t val;
7726
7727 DRM_DEBUG_KMS("Enabling package C8+\n");
7728
7729 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7730 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7731 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7732 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7733 }
7734
7735 lpt_disable_clkout_dp(dev);
7736 hsw_disable_lcpll(dev_priv, true, true);
7737 }
7738
7739 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7740 {
7741 struct drm_device *dev = dev_priv->dev;
7742 uint32_t val;
7743
7744 DRM_DEBUG_KMS("Disabling package C8+\n");
7745
7746 hsw_restore_lcpll(dev_priv);
7747 lpt_init_pch_refclk(dev);
7748
7749 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7750 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7751 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7752 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7753 }
7754
7755 intel_prepare_ddi(dev);
7756 }
7757
7758 static void snb_modeset_global_resources(struct drm_device *dev)
7759 {
7760 modeset_update_crtc_power_domains(dev);
7761 }
7762
7763 static void haswell_modeset_global_resources(struct drm_device *dev)
7764 {
7765 modeset_update_crtc_power_domains(dev);
7766 }
7767
7768 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7769 int x, int y,
7770 struct drm_framebuffer *fb)
7771 {
7772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7773
7774 if (!intel_ddi_pll_select(intel_crtc))
7775 return -EINVAL;
7776
7777 intel_crtc->lowfreq_avail = false;
7778
7779 return 0;
7780 }
7781
7782 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7783 enum port port,
7784 struct intel_crtc_config *pipe_config)
7785 {
7786 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7787
7788 switch (pipe_config->ddi_pll_sel) {
7789 case PORT_CLK_SEL_WRPLL1:
7790 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7791 break;
7792 case PORT_CLK_SEL_WRPLL2:
7793 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7794 break;
7795 }
7796 }
7797
7798 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7799 struct intel_crtc_config *pipe_config)
7800 {
7801 struct drm_device *dev = crtc->base.dev;
7802 struct drm_i915_private *dev_priv = dev->dev_private;
7803 struct intel_shared_dpll *pll;
7804 enum port port;
7805 uint32_t tmp;
7806
7807 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7808
7809 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7810
7811 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7812
7813 if (pipe_config->shared_dpll >= 0) {
7814 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7815
7816 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7817 &pipe_config->dpll_hw_state));
7818 }
7819
7820 /*
7821 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7822 * DDI E. So just check whether this pipe is wired to DDI E and whether
7823 * the PCH transcoder is on.
7824 */
7825 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7826 pipe_config->has_pch_encoder = true;
7827
7828 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7829 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7830 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7831
7832 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7833 }
7834 }
7835
7836 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7837 struct intel_crtc_config *pipe_config)
7838 {
7839 struct drm_device *dev = crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 enum intel_display_power_domain pfit_domain;
7842 uint32_t tmp;
7843
7844 if (!intel_display_power_enabled(dev_priv,
7845 POWER_DOMAIN_PIPE(crtc->pipe)))
7846 return false;
7847
7848 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7849 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7850
7851 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7852 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7853 enum pipe trans_edp_pipe;
7854 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7855 default:
7856 WARN(1, "unknown pipe linked to edp transcoder\n");
7857 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7858 case TRANS_DDI_EDP_INPUT_A_ON:
7859 trans_edp_pipe = PIPE_A;
7860 break;
7861 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7862 trans_edp_pipe = PIPE_B;
7863 break;
7864 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7865 trans_edp_pipe = PIPE_C;
7866 break;
7867 }
7868
7869 if (trans_edp_pipe == crtc->pipe)
7870 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7871 }
7872
7873 if (!intel_display_power_enabled(dev_priv,
7874 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7875 return false;
7876
7877 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7878 if (!(tmp & PIPECONF_ENABLE))
7879 return false;
7880
7881 haswell_get_ddi_port_state(crtc, pipe_config);
7882
7883 intel_get_pipe_timings(crtc, pipe_config);
7884
7885 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7886 if (intel_display_power_enabled(dev_priv, pfit_domain))
7887 ironlake_get_pfit_config(crtc, pipe_config);
7888
7889 if (IS_HASWELL(dev))
7890 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7891 (I915_READ(IPS_CTL) & IPS_ENABLE);
7892
7893 pipe_config->pixel_multiplier = 1;
7894
7895 return true;
7896 }
7897
7898 static struct {
7899 int clock;
7900 u32 config;
7901 } hdmi_audio_clock[] = {
7902 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7903 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7904 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7905 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7906 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7907 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7908 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7909 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7910 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7911 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7912 };
7913
7914 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7915 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7916 {
7917 int i;
7918
7919 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7920 if (mode->clock == hdmi_audio_clock[i].clock)
7921 break;
7922 }
7923
7924 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7925 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7926 i = 1;
7927 }
7928
7929 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7930 hdmi_audio_clock[i].clock,
7931 hdmi_audio_clock[i].config);
7932
7933 return hdmi_audio_clock[i].config;
7934 }
7935
7936 static bool intel_eld_uptodate(struct drm_connector *connector,
7937 int reg_eldv, uint32_t bits_eldv,
7938 int reg_elda, uint32_t bits_elda,
7939 int reg_edid)
7940 {
7941 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7942 uint8_t *eld = connector->eld;
7943 uint32_t i;
7944
7945 i = I915_READ(reg_eldv);
7946 i &= bits_eldv;
7947
7948 if (!eld[0])
7949 return !i;
7950
7951 if (!i)
7952 return false;
7953
7954 i = I915_READ(reg_elda);
7955 i &= ~bits_elda;
7956 I915_WRITE(reg_elda, i);
7957
7958 for (i = 0; i < eld[2]; i++)
7959 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7960 return false;
7961
7962 return true;
7963 }
7964
7965 static void g4x_write_eld(struct drm_connector *connector,
7966 struct drm_crtc *crtc,
7967 struct drm_display_mode *mode)
7968 {
7969 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7970 uint8_t *eld = connector->eld;
7971 uint32_t eldv;
7972 uint32_t len;
7973 uint32_t i;
7974
7975 i = I915_READ(G4X_AUD_VID_DID);
7976
7977 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7978 eldv = G4X_ELDV_DEVCL_DEVBLC;
7979 else
7980 eldv = G4X_ELDV_DEVCTG;
7981
7982 if (intel_eld_uptodate(connector,
7983 G4X_AUD_CNTL_ST, eldv,
7984 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7985 G4X_HDMIW_HDMIEDID))
7986 return;
7987
7988 i = I915_READ(G4X_AUD_CNTL_ST);
7989 i &= ~(eldv | G4X_ELD_ADDR);
7990 len = (i >> 9) & 0x1f; /* ELD buffer size */
7991 I915_WRITE(G4X_AUD_CNTL_ST, i);
7992
7993 if (!eld[0])
7994 return;
7995
7996 len = min_t(uint8_t, eld[2], len);
7997 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7998 for (i = 0; i < len; i++)
7999 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8000
8001 i = I915_READ(G4X_AUD_CNTL_ST);
8002 i |= eldv;
8003 I915_WRITE(G4X_AUD_CNTL_ST, i);
8004 }
8005
8006 static void haswell_write_eld(struct drm_connector *connector,
8007 struct drm_crtc *crtc,
8008 struct drm_display_mode *mode)
8009 {
8010 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8011 uint8_t *eld = connector->eld;
8012 uint32_t eldv;
8013 uint32_t i;
8014 int len;
8015 int pipe = to_intel_crtc(crtc)->pipe;
8016 int tmp;
8017
8018 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8019 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8020 int aud_config = HSW_AUD_CFG(pipe);
8021 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8022
8023 /* Audio output enable */
8024 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8025 tmp = I915_READ(aud_cntrl_st2);
8026 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8027 I915_WRITE(aud_cntrl_st2, tmp);
8028 POSTING_READ(aud_cntrl_st2);
8029
8030 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8031
8032 /* Set ELD valid state */
8033 tmp = I915_READ(aud_cntrl_st2);
8034 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8035 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8036 I915_WRITE(aud_cntrl_st2, tmp);
8037 tmp = I915_READ(aud_cntrl_st2);
8038 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8039
8040 /* Enable HDMI mode */
8041 tmp = I915_READ(aud_config);
8042 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8043 /* clear N_programing_enable and N_value_index */
8044 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8045 I915_WRITE(aud_config, tmp);
8046
8047 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8048
8049 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8050
8051 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8052 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8053 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8054 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8055 } else {
8056 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8057 }
8058
8059 if (intel_eld_uptodate(connector,
8060 aud_cntrl_st2, eldv,
8061 aud_cntl_st, IBX_ELD_ADDRESS,
8062 hdmiw_hdmiedid))
8063 return;
8064
8065 i = I915_READ(aud_cntrl_st2);
8066 i &= ~eldv;
8067 I915_WRITE(aud_cntrl_st2, i);
8068
8069 if (!eld[0])
8070 return;
8071
8072 i = I915_READ(aud_cntl_st);
8073 i &= ~IBX_ELD_ADDRESS;
8074 I915_WRITE(aud_cntl_st, i);
8075 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8076 DRM_DEBUG_DRIVER("port num:%d\n", i);
8077
8078 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8079 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8080 for (i = 0; i < len; i++)
8081 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8082
8083 i = I915_READ(aud_cntrl_st2);
8084 i |= eldv;
8085 I915_WRITE(aud_cntrl_st2, i);
8086
8087 }
8088
8089 static void ironlake_write_eld(struct drm_connector *connector,
8090 struct drm_crtc *crtc,
8091 struct drm_display_mode *mode)
8092 {
8093 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8094 uint8_t *eld = connector->eld;
8095 uint32_t eldv;
8096 uint32_t i;
8097 int len;
8098 int hdmiw_hdmiedid;
8099 int aud_config;
8100 int aud_cntl_st;
8101 int aud_cntrl_st2;
8102 int pipe = to_intel_crtc(crtc)->pipe;
8103
8104 if (HAS_PCH_IBX(connector->dev)) {
8105 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8106 aud_config = IBX_AUD_CFG(pipe);
8107 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8108 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8109 } else if (IS_VALLEYVIEW(connector->dev)) {
8110 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8111 aud_config = VLV_AUD_CFG(pipe);
8112 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8113 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8114 } else {
8115 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8116 aud_config = CPT_AUD_CFG(pipe);
8117 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8118 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8119 }
8120
8121 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8122
8123 if (IS_VALLEYVIEW(connector->dev)) {
8124 struct intel_encoder *intel_encoder;
8125 struct intel_digital_port *intel_dig_port;
8126
8127 intel_encoder = intel_attached_encoder(connector);
8128 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8129 i = intel_dig_port->port;
8130 } else {
8131 i = I915_READ(aud_cntl_st);
8132 i = (i >> 29) & DIP_PORT_SEL_MASK;
8133 /* DIP_Port_Select, 0x1 = PortB */
8134 }
8135
8136 if (!i) {
8137 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8138 /* operate blindly on all ports */
8139 eldv = IBX_ELD_VALIDB;
8140 eldv |= IBX_ELD_VALIDB << 4;
8141 eldv |= IBX_ELD_VALIDB << 8;
8142 } else {
8143 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8144 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8145 }
8146
8147 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8148 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8149 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8150 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8151 } else {
8152 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8153 }
8154
8155 if (intel_eld_uptodate(connector,
8156 aud_cntrl_st2, eldv,
8157 aud_cntl_st, IBX_ELD_ADDRESS,
8158 hdmiw_hdmiedid))
8159 return;
8160
8161 i = I915_READ(aud_cntrl_st2);
8162 i &= ~eldv;
8163 I915_WRITE(aud_cntrl_st2, i);
8164
8165 if (!eld[0])
8166 return;
8167
8168 i = I915_READ(aud_cntl_st);
8169 i &= ~IBX_ELD_ADDRESS;
8170 I915_WRITE(aud_cntl_st, i);
8171
8172 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8173 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8174 for (i = 0; i < len; i++)
8175 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8176
8177 i = I915_READ(aud_cntrl_st2);
8178 i |= eldv;
8179 I915_WRITE(aud_cntrl_st2, i);
8180 }
8181
8182 void intel_write_eld(struct drm_encoder *encoder,
8183 struct drm_display_mode *mode)
8184 {
8185 struct drm_crtc *crtc = encoder->crtc;
8186 struct drm_connector *connector;
8187 struct drm_device *dev = encoder->dev;
8188 struct drm_i915_private *dev_priv = dev->dev_private;
8189
8190 connector = drm_select_eld(encoder, mode);
8191 if (!connector)
8192 return;
8193
8194 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8195 connector->base.id,
8196 connector->name,
8197 connector->encoder->base.id,
8198 connector->encoder->name);
8199
8200 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8201
8202 if (dev_priv->display.write_eld)
8203 dev_priv->display.write_eld(connector, crtc, mode);
8204 }
8205
8206 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8207 {
8208 struct drm_device *dev = crtc->dev;
8209 struct drm_i915_private *dev_priv = dev->dev_private;
8210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8211 uint32_t cntl = 0, size = 0;
8212
8213 if (base) {
8214 unsigned int width = intel_crtc->cursor_width;
8215 unsigned int height = intel_crtc->cursor_height;
8216 unsigned int stride = roundup_pow_of_two(width) * 4;
8217
8218 switch (stride) {
8219 default:
8220 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8221 width, stride);
8222 stride = 256;
8223 /* fallthrough */
8224 case 256:
8225 case 512:
8226 case 1024:
8227 case 2048:
8228 break;
8229 }
8230
8231 cntl |= CURSOR_ENABLE |
8232 CURSOR_GAMMA_ENABLE |
8233 CURSOR_FORMAT_ARGB |
8234 CURSOR_STRIDE(stride);
8235
8236 size = (height << 12) | width;
8237 }
8238
8239 if (intel_crtc->cursor_cntl != 0 &&
8240 (intel_crtc->cursor_base != base ||
8241 intel_crtc->cursor_size != size ||
8242 intel_crtc->cursor_cntl != cntl)) {
8243 /* On these chipsets we can only modify the base/size/stride
8244 * whilst the cursor is disabled.
8245 */
8246 I915_WRITE(_CURACNTR, 0);
8247 POSTING_READ(_CURACNTR);
8248 intel_crtc->cursor_cntl = 0;
8249 }
8250
8251 if (intel_crtc->cursor_base != base)
8252 I915_WRITE(_CURABASE, base);
8253
8254 if (intel_crtc->cursor_size != size) {
8255 I915_WRITE(CURSIZE, size);
8256 intel_crtc->cursor_size = size;
8257 }
8258
8259 if (intel_crtc->cursor_cntl != cntl) {
8260 I915_WRITE(_CURACNTR, cntl);
8261 POSTING_READ(_CURACNTR);
8262 intel_crtc->cursor_cntl = cntl;
8263 }
8264 }
8265
8266 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8267 {
8268 struct drm_device *dev = crtc->dev;
8269 struct drm_i915_private *dev_priv = dev->dev_private;
8270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8271 int pipe = intel_crtc->pipe;
8272 uint32_t cntl;
8273
8274 cntl = 0;
8275 if (base) {
8276 cntl = MCURSOR_GAMMA_ENABLE;
8277 switch (intel_crtc->cursor_width) {
8278 case 64:
8279 cntl |= CURSOR_MODE_64_ARGB_AX;
8280 break;
8281 case 128:
8282 cntl |= CURSOR_MODE_128_ARGB_AX;
8283 break;
8284 case 256:
8285 cntl |= CURSOR_MODE_256_ARGB_AX;
8286 break;
8287 default:
8288 WARN_ON(1);
8289 return;
8290 }
8291 cntl |= pipe << 28; /* Connect to correct pipe */
8292 }
8293 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8294 cntl |= CURSOR_PIPE_CSC_ENABLE;
8295
8296 if (intel_crtc->cursor_cntl != cntl) {
8297 I915_WRITE(CURCNTR(pipe), cntl);
8298 POSTING_READ(CURCNTR(pipe));
8299 intel_crtc->cursor_cntl = cntl;
8300 }
8301
8302 /* and commit changes on next vblank */
8303 I915_WRITE(CURBASE(pipe), base);
8304 POSTING_READ(CURBASE(pipe));
8305 }
8306
8307 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8308 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8309 bool on)
8310 {
8311 struct drm_device *dev = crtc->dev;
8312 struct drm_i915_private *dev_priv = dev->dev_private;
8313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8314 int pipe = intel_crtc->pipe;
8315 int x = crtc->cursor_x;
8316 int y = crtc->cursor_y;
8317 u32 base = 0, pos = 0;
8318
8319 if (on)
8320 base = intel_crtc->cursor_addr;
8321
8322 if (x >= intel_crtc->config.pipe_src_w)
8323 base = 0;
8324
8325 if (y >= intel_crtc->config.pipe_src_h)
8326 base = 0;
8327
8328 if (x < 0) {
8329 if (x + intel_crtc->cursor_width <= 0)
8330 base = 0;
8331
8332 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8333 x = -x;
8334 }
8335 pos |= x << CURSOR_X_SHIFT;
8336
8337 if (y < 0) {
8338 if (y + intel_crtc->cursor_height <= 0)
8339 base = 0;
8340
8341 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8342 y = -y;
8343 }
8344 pos |= y << CURSOR_Y_SHIFT;
8345
8346 if (base == 0 && intel_crtc->cursor_base == 0)
8347 return;
8348
8349 I915_WRITE(CURPOS(pipe), pos);
8350
8351 if (IS_845G(dev) || IS_I865G(dev))
8352 i845_update_cursor(crtc, base);
8353 else
8354 i9xx_update_cursor(crtc, base);
8355 intel_crtc->cursor_base = base;
8356 }
8357
8358 static bool cursor_size_ok(struct drm_device *dev,
8359 uint32_t width, uint32_t height)
8360 {
8361 if (width == 0 || height == 0)
8362 return false;
8363
8364 /*
8365 * 845g/865g are special in that they are only limited by
8366 * the width of their cursors, the height is arbitrary up to
8367 * the precision of the register. Everything else requires
8368 * square cursors, limited to a few power-of-two sizes.
8369 */
8370 if (IS_845G(dev) || IS_I865G(dev)) {
8371 if ((width & 63) != 0)
8372 return false;
8373
8374 if (width > (IS_845G(dev) ? 64 : 512))
8375 return false;
8376
8377 if (height > 1023)
8378 return false;
8379 } else {
8380 switch (width | height) {
8381 case 256:
8382 case 128:
8383 if (IS_GEN2(dev))
8384 return false;
8385 case 64:
8386 break;
8387 default:
8388 return false;
8389 }
8390 }
8391
8392 return true;
8393 }
8394
8395 /*
8396 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8397 *
8398 * Note that the object's reference will be consumed if the update fails. If
8399 * the update succeeds, the reference of the old object (if any) will be
8400 * consumed.
8401 */
8402 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8403 struct drm_i915_gem_object *obj,
8404 uint32_t width, uint32_t height)
8405 {
8406 struct drm_device *dev = crtc->dev;
8407 struct drm_i915_private *dev_priv = dev->dev_private;
8408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8409 enum pipe pipe = intel_crtc->pipe;
8410 unsigned old_width, stride;
8411 uint32_t addr;
8412 int ret;
8413
8414 /* if we want to turn off the cursor ignore width and height */
8415 if (!obj) {
8416 DRM_DEBUG_KMS("cursor off\n");
8417 addr = 0;
8418 mutex_lock(&dev->struct_mutex);
8419 goto finish;
8420 }
8421
8422 /* Check for which cursor types we support */
8423 if (!cursor_size_ok(dev, width, height)) {
8424 DRM_DEBUG("Cursor dimension not supported\n");
8425 return -EINVAL;
8426 }
8427
8428 stride = roundup_pow_of_two(width) * 4;
8429 if (obj->base.size < stride * height) {
8430 DRM_DEBUG_KMS("buffer is too small\n");
8431 ret = -ENOMEM;
8432 goto fail;
8433 }
8434
8435 /* we only need to pin inside GTT if cursor is non-phy */
8436 mutex_lock(&dev->struct_mutex);
8437 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8438 unsigned alignment;
8439
8440 if (obj->tiling_mode) {
8441 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8442 ret = -EINVAL;
8443 goto fail_locked;
8444 }
8445
8446 /*
8447 * Global gtt pte registers are special registers which actually
8448 * forward writes to a chunk of system memory. Which means that
8449 * there is no risk that the register values disappear as soon
8450 * as we call intel_runtime_pm_put(), so it is correct to wrap
8451 * only the pin/unpin/fence and not more.
8452 */
8453 intel_runtime_pm_get(dev_priv);
8454
8455 /* Note that the w/a also requires 2 PTE of padding following
8456 * the bo. We currently fill all unused PTE with the shadow
8457 * page and so we should always have valid PTE following the
8458 * cursor preventing the VT-d warning.
8459 */
8460 alignment = 0;
8461 if (need_vtd_wa(dev))
8462 alignment = 64*1024;
8463
8464 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8465 if (ret) {
8466 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8467 intel_runtime_pm_put(dev_priv);
8468 goto fail_locked;
8469 }
8470
8471 ret = i915_gem_object_put_fence(obj);
8472 if (ret) {
8473 DRM_DEBUG_KMS("failed to release fence for cursor");
8474 intel_runtime_pm_put(dev_priv);
8475 goto fail_unpin;
8476 }
8477
8478 addr = i915_gem_obj_ggtt_offset(obj);
8479
8480 intel_runtime_pm_put(dev_priv);
8481 } else {
8482 int align = IS_I830(dev) ? 16 * 1024 : 256;
8483 ret = i915_gem_object_attach_phys(obj, align);
8484 if (ret) {
8485 DRM_DEBUG_KMS("failed to attach phys object\n");
8486 goto fail_locked;
8487 }
8488 addr = obj->phys_handle->busaddr;
8489 }
8490
8491 finish:
8492 if (intel_crtc->cursor_bo) {
8493 if (!INTEL_INFO(dev)->cursor_needs_physical)
8494 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8495 }
8496
8497 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8498 INTEL_FRONTBUFFER_CURSOR(pipe));
8499 mutex_unlock(&dev->struct_mutex);
8500
8501 old_width = intel_crtc->cursor_width;
8502
8503 intel_crtc->cursor_addr = addr;
8504 intel_crtc->cursor_bo = obj;
8505 intel_crtc->cursor_width = width;
8506 intel_crtc->cursor_height = height;
8507
8508 if (intel_crtc->active) {
8509 if (old_width != width)
8510 intel_update_watermarks(crtc);
8511 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8512 }
8513
8514 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8515
8516 return 0;
8517 fail_unpin:
8518 i915_gem_object_unpin_from_display_plane(obj);
8519 fail_locked:
8520 mutex_unlock(&dev->struct_mutex);
8521 fail:
8522 drm_gem_object_unreference_unlocked(&obj->base);
8523 return ret;
8524 }
8525
8526 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8527 u16 *blue, uint32_t start, uint32_t size)
8528 {
8529 int end = (start + size > 256) ? 256 : start + size, i;
8530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8531
8532 for (i = start; i < end; i++) {
8533 intel_crtc->lut_r[i] = red[i] >> 8;
8534 intel_crtc->lut_g[i] = green[i] >> 8;
8535 intel_crtc->lut_b[i] = blue[i] >> 8;
8536 }
8537
8538 intel_crtc_load_lut(crtc);
8539 }
8540
8541 /* VESA 640x480x72Hz mode to set on the pipe */
8542 static struct drm_display_mode load_detect_mode = {
8543 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8544 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8545 };
8546
8547 struct drm_framebuffer *
8548 __intel_framebuffer_create(struct drm_device *dev,
8549 struct drm_mode_fb_cmd2 *mode_cmd,
8550 struct drm_i915_gem_object *obj)
8551 {
8552 struct intel_framebuffer *intel_fb;
8553 int ret;
8554
8555 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8556 if (!intel_fb) {
8557 drm_gem_object_unreference_unlocked(&obj->base);
8558 return ERR_PTR(-ENOMEM);
8559 }
8560
8561 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8562 if (ret)
8563 goto err;
8564
8565 return &intel_fb->base;
8566 err:
8567 drm_gem_object_unreference_unlocked(&obj->base);
8568 kfree(intel_fb);
8569
8570 return ERR_PTR(ret);
8571 }
8572
8573 static struct drm_framebuffer *
8574 intel_framebuffer_create(struct drm_device *dev,
8575 struct drm_mode_fb_cmd2 *mode_cmd,
8576 struct drm_i915_gem_object *obj)
8577 {
8578 struct drm_framebuffer *fb;
8579 int ret;
8580
8581 ret = i915_mutex_lock_interruptible(dev);
8582 if (ret)
8583 return ERR_PTR(ret);
8584 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8585 mutex_unlock(&dev->struct_mutex);
8586
8587 return fb;
8588 }
8589
8590 static u32
8591 intel_framebuffer_pitch_for_width(int width, int bpp)
8592 {
8593 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8594 return ALIGN(pitch, 64);
8595 }
8596
8597 static u32
8598 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8599 {
8600 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8601 return PAGE_ALIGN(pitch * mode->vdisplay);
8602 }
8603
8604 static struct drm_framebuffer *
8605 intel_framebuffer_create_for_mode(struct drm_device *dev,
8606 struct drm_display_mode *mode,
8607 int depth, int bpp)
8608 {
8609 struct drm_i915_gem_object *obj;
8610 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8611
8612 obj = i915_gem_alloc_object(dev,
8613 intel_framebuffer_size_for_mode(mode, bpp));
8614 if (obj == NULL)
8615 return ERR_PTR(-ENOMEM);
8616
8617 mode_cmd.width = mode->hdisplay;
8618 mode_cmd.height = mode->vdisplay;
8619 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8620 bpp);
8621 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8622
8623 return intel_framebuffer_create(dev, &mode_cmd, obj);
8624 }
8625
8626 static struct drm_framebuffer *
8627 mode_fits_in_fbdev(struct drm_device *dev,
8628 struct drm_display_mode *mode)
8629 {
8630 #ifdef CONFIG_DRM_I915_FBDEV
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8632 struct drm_i915_gem_object *obj;
8633 struct drm_framebuffer *fb;
8634
8635 if (!dev_priv->fbdev)
8636 return NULL;
8637
8638 if (!dev_priv->fbdev->fb)
8639 return NULL;
8640
8641 obj = dev_priv->fbdev->fb->obj;
8642 BUG_ON(!obj);
8643
8644 fb = &dev_priv->fbdev->fb->base;
8645 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8646 fb->bits_per_pixel))
8647 return NULL;
8648
8649 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8650 return NULL;
8651
8652 return fb;
8653 #else
8654 return NULL;
8655 #endif
8656 }
8657
8658 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8659 struct drm_display_mode *mode,
8660 struct intel_load_detect_pipe *old,
8661 struct drm_modeset_acquire_ctx *ctx)
8662 {
8663 struct intel_crtc *intel_crtc;
8664 struct intel_encoder *intel_encoder =
8665 intel_attached_encoder(connector);
8666 struct drm_crtc *possible_crtc;
8667 struct drm_encoder *encoder = &intel_encoder->base;
8668 struct drm_crtc *crtc = NULL;
8669 struct drm_device *dev = encoder->dev;
8670 struct drm_framebuffer *fb;
8671 struct drm_mode_config *config = &dev->mode_config;
8672 int ret, i = -1;
8673
8674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8675 connector->base.id, connector->name,
8676 encoder->base.id, encoder->name);
8677
8678 retry:
8679 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8680 if (ret)
8681 goto fail_unlock;
8682
8683 /*
8684 * Algorithm gets a little messy:
8685 *
8686 * - if the connector already has an assigned crtc, use it (but make
8687 * sure it's on first)
8688 *
8689 * - try to find the first unused crtc that can drive this connector,
8690 * and use that if we find one
8691 */
8692
8693 /* See if we already have a CRTC for this connector */
8694 if (encoder->crtc) {
8695 crtc = encoder->crtc;
8696
8697 ret = drm_modeset_lock(&crtc->mutex, ctx);
8698 if (ret)
8699 goto fail_unlock;
8700
8701 old->dpms_mode = connector->dpms;
8702 old->load_detect_temp = false;
8703
8704 /* Make sure the crtc and connector are running */
8705 if (connector->dpms != DRM_MODE_DPMS_ON)
8706 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8707
8708 return true;
8709 }
8710
8711 /* Find an unused one (if possible) */
8712 for_each_crtc(dev, possible_crtc) {
8713 i++;
8714 if (!(encoder->possible_crtcs & (1 << i)))
8715 continue;
8716 if (possible_crtc->enabled)
8717 continue;
8718 /* This can occur when applying the pipe A quirk on resume. */
8719 if (to_intel_crtc(possible_crtc)->new_enabled)
8720 continue;
8721
8722 crtc = possible_crtc;
8723 break;
8724 }
8725
8726 /*
8727 * If we didn't find an unused CRTC, don't use any.
8728 */
8729 if (!crtc) {
8730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8731 goto fail_unlock;
8732 }
8733
8734 ret = drm_modeset_lock(&crtc->mutex, ctx);
8735 if (ret)
8736 goto fail_unlock;
8737 intel_encoder->new_crtc = to_intel_crtc(crtc);
8738 to_intel_connector(connector)->new_encoder = intel_encoder;
8739
8740 intel_crtc = to_intel_crtc(crtc);
8741 intel_crtc->new_enabled = true;
8742 intel_crtc->new_config = &intel_crtc->config;
8743 old->dpms_mode = connector->dpms;
8744 old->load_detect_temp = true;
8745 old->release_fb = NULL;
8746
8747 if (!mode)
8748 mode = &load_detect_mode;
8749
8750 /* We need a framebuffer large enough to accommodate all accesses
8751 * that the plane may generate whilst we perform load detection.
8752 * We can not rely on the fbcon either being present (we get called
8753 * during its initialisation to detect all boot displays, or it may
8754 * not even exist) or that it is large enough to satisfy the
8755 * requested mode.
8756 */
8757 fb = mode_fits_in_fbdev(dev, mode);
8758 if (fb == NULL) {
8759 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8760 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8761 old->release_fb = fb;
8762 } else
8763 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8764 if (IS_ERR(fb)) {
8765 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8766 goto fail;
8767 }
8768
8769 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8770 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8771 if (old->release_fb)
8772 old->release_fb->funcs->destroy(old->release_fb);
8773 goto fail;
8774 }
8775
8776 /* let the connector get through one full cycle before testing */
8777 intel_wait_for_vblank(dev, intel_crtc->pipe);
8778 return true;
8779
8780 fail:
8781 intel_crtc->new_enabled = crtc->enabled;
8782 if (intel_crtc->new_enabled)
8783 intel_crtc->new_config = &intel_crtc->config;
8784 else
8785 intel_crtc->new_config = NULL;
8786 fail_unlock:
8787 if (ret == -EDEADLK) {
8788 drm_modeset_backoff(ctx);
8789 goto retry;
8790 }
8791
8792 return false;
8793 }
8794
8795 void intel_release_load_detect_pipe(struct drm_connector *connector,
8796 struct intel_load_detect_pipe *old)
8797 {
8798 struct intel_encoder *intel_encoder =
8799 intel_attached_encoder(connector);
8800 struct drm_encoder *encoder = &intel_encoder->base;
8801 struct drm_crtc *crtc = encoder->crtc;
8802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8803
8804 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8805 connector->base.id, connector->name,
8806 encoder->base.id, encoder->name);
8807
8808 if (old->load_detect_temp) {
8809 to_intel_connector(connector)->new_encoder = NULL;
8810 intel_encoder->new_crtc = NULL;
8811 intel_crtc->new_enabled = false;
8812 intel_crtc->new_config = NULL;
8813 intel_set_mode(crtc, NULL, 0, 0, NULL);
8814
8815 if (old->release_fb) {
8816 drm_framebuffer_unregister_private(old->release_fb);
8817 drm_framebuffer_unreference(old->release_fb);
8818 }
8819
8820 return;
8821 }
8822
8823 /* Switch crtc and encoder back off if necessary */
8824 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8825 connector->funcs->dpms(connector, old->dpms_mode);
8826 }
8827
8828 static int i9xx_pll_refclk(struct drm_device *dev,
8829 const struct intel_crtc_config *pipe_config)
8830 {
8831 struct drm_i915_private *dev_priv = dev->dev_private;
8832 u32 dpll = pipe_config->dpll_hw_state.dpll;
8833
8834 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8835 return dev_priv->vbt.lvds_ssc_freq;
8836 else if (HAS_PCH_SPLIT(dev))
8837 return 120000;
8838 else if (!IS_GEN2(dev))
8839 return 96000;
8840 else
8841 return 48000;
8842 }
8843
8844 /* Returns the clock of the currently programmed mode of the given pipe. */
8845 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8846 struct intel_crtc_config *pipe_config)
8847 {
8848 struct drm_device *dev = crtc->base.dev;
8849 struct drm_i915_private *dev_priv = dev->dev_private;
8850 int pipe = pipe_config->cpu_transcoder;
8851 u32 dpll = pipe_config->dpll_hw_state.dpll;
8852 u32 fp;
8853 intel_clock_t clock;
8854 int refclk = i9xx_pll_refclk(dev, pipe_config);
8855
8856 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8857 fp = pipe_config->dpll_hw_state.fp0;
8858 else
8859 fp = pipe_config->dpll_hw_state.fp1;
8860
8861 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8862 if (IS_PINEVIEW(dev)) {
8863 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8864 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8865 } else {
8866 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8867 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8868 }
8869
8870 if (!IS_GEN2(dev)) {
8871 if (IS_PINEVIEW(dev))
8872 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8873 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8874 else
8875 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8876 DPLL_FPA01_P1_POST_DIV_SHIFT);
8877
8878 switch (dpll & DPLL_MODE_MASK) {
8879 case DPLLB_MODE_DAC_SERIAL:
8880 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8881 5 : 10;
8882 break;
8883 case DPLLB_MODE_LVDS:
8884 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8885 7 : 14;
8886 break;
8887 default:
8888 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8889 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8890 return;
8891 }
8892
8893 if (IS_PINEVIEW(dev))
8894 pineview_clock(refclk, &clock);
8895 else
8896 i9xx_clock(refclk, &clock);
8897 } else {
8898 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8899 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8900
8901 if (is_lvds) {
8902 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8903 DPLL_FPA01_P1_POST_DIV_SHIFT);
8904
8905 if (lvds & LVDS_CLKB_POWER_UP)
8906 clock.p2 = 7;
8907 else
8908 clock.p2 = 14;
8909 } else {
8910 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8911 clock.p1 = 2;
8912 else {
8913 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8914 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8915 }
8916 if (dpll & PLL_P2_DIVIDE_BY_4)
8917 clock.p2 = 4;
8918 else
8919 clock.p2 = 2;
8920 }
8921
8922 i9xx_clock(refclk, &clock);
8923 }
8924
8925 /*
8926 * This value includes pixel_multiplier. We will use
8927 * port_clock to compute adjusted_mode.crtc_clock in the
8928 * encoder's get_config() function.
8929 */
8930 pipe_config->port_clock = clock.dot;
8931 }
8932
8933 int intel_dotclock_calculate(int link_freq,
8934 const struct intel_link_m_n *m_n)
8935 {
8936 /*
8937 * The calculation for the data clock is:
8938 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8939 * But we want to avoid losing precison if possible, so:
8940 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8941 *
8942 * and the link clock is simpler:
8943 * link_clock = (m * link_clock) / n
8944 */
8945
8946 if (!m_n->link_n)
8947 return 0;
8948
8949 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8950 }
8951
8952 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8953 struct intel_crtc_config *pipe_config)
8954 {
8955 struct drm_device *dev = crtc->base.dev;
8956
8957 /* read out port_clock from the DPLL */
8958 i9xx_crtc_clock_get(crtc, pipe_config);
8959
8960 /*
8961 * This value does not include pixel_multiplier.
8962 * We will check that port_clock and adjusted_mode.crtc_clock
8963 * agree once we know their relationship in the encoder's
8964 * get_config() function.
8965 */
8966 pipe_config->adjusted_mode.crtc_clock =
8967 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8968 &pipe_config->fdi_m_n);
8969 }
8970
8971 /** Returns the currently programmed mode of the given pipe. */
8972 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8973 struct drm_crtc *crtc)
8974 {
8975 struct drm_i915_private *dev_priv = dev->dev_private;
8976 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8977 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8978 struct drm_display_mode *mode;
8979 struct intel_crtc_config pipe_config;
8980 int htot = I915_READ(HTOTAL(cpu_transcoder));
8981 int hsync = I915_READ(HSYNC(cpu_transcoder));
8982 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8983 int vsync = I915_READ(VSYNC(cpu_transcoder));
8984 enum pipe pipe = intel_crtc->pipe;
8985
8986 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8987 if (!mode)
8988 return NULL;
8989
8990 /*
8991 * Construct a pipe_config sufficient for getting the clock info
8992 * back out of crtc_clock_get.
8993 *
8994 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8995 * to use a real value here instead.
8996 */
8997 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8998 pipe_config.pixel_multiplier = 1;
8999 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9000 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9001 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9002 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9003
9004 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9005 mode->hdisplay = (htot & 0xffff) + 1;
9006 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9007 mode->hsync_start = (hsync & 0xffff) + 1;
9008 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9009 mode->vdisplay = (vtot & 0xffff) + 1;
9010 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9011 mode->vsync_start = (vsync & 0xffff) + 1;
9012 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9013
9014 drm_mode_set_name(mode);
9015
9016 return mode;
9017 }
9018
9019 static void intel_increase_pllclock(struct drm_device *dev,
9020 enum pipe pipe)
9021 {
9022 struct drm_i915_private *dev_priv = dev->dev_private;
9023 int dpll_reg = DPLL(pipe);
9024 int dpll;
9025
9026 if (!HAS_GMCH_DISPLAY(dev))
9027 return;
9028
9029 if (!dev_priv->lvds_downclock_avail)
9030 return;
9031
9032 dpll = I915_READ(dpll_reg);
9033 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9034 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9035
9036 assert_panel_unlocked(dev_priv, pipe);
9037
9038 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9039 I915_WRITE(dpll_reg, dpll);
9040 intel_wait_for_vblank(dev, pipe);
9041
9042 dpll = I915_READ(dpll_reg);
9043 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9044 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9045 }
9046 }
9047
9048 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9049 {
9050 struct drm_device *dev = crtc->dev;
9051 struct drm_i915_private *dev_priv = dev->dev_private;
9052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9053
9054 if (!HAS_GMCH_DISPLAY(dev))
9055 return;
9056
9057 if (!dev_priv->lvds_downclock_avail)
9058 return;
9059
9060 /*
9061 * Since this is called by a timer, we should never get here in
9062 * the manual case.
9063 */
9064 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9065 int pipe = intel_crtc->pipe;
9066 int dpll_reg = DPLL(pipe);
9067 int dpll;
9068
9069 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9070
9071 assert_panel_unlocked(dev_priv, pipe);
9072
9073 dpll = I915_READ(dpll_reg);
9074 dpll |= DISPLAY_RATE_SELECT_FPA1;
9075 I915_WRITE(dpll_reg, dpll);
9076 intel_wait_for_vblank(dev, pipe);
9077 dpll = I915_READ(dpll_reg);
9078 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9079 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9080 }
9081
9082 }
9083
9084 void intel_mark_busy(struct drm_device *dev)
9085 {
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9087
9088 if (dev_priv->mm.busy)
9089 return;
9090
9091 intel_runtime_pm_get(dev_priv);
9092 i915_update_gfx_val(dev_priv);
9093 dev_priv->mm.busy = true;
9094 }
9095
9096 void intel_mark_idle(struct drm_device *dev)
9097 {
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9099 struct drm_crtc *crtc;
9100
9101 if (!dev_priv->mm.busy)
9102 return;
9103
9104 dev_priv->mm.busy = false;
9105
9106 if (!i915.powersave)
9107 goto out;
9108
9109 for_each_crtc(dev, crtc) {
9110 if (!crtc->primary->fb)
9111 continue;
9112
9113 intel_decrease_pllclock(crtc);
9114 }
9115
9116 if (INTEL_INFO(dev)->gen >= 6)
9117 gen6_rps_idle(dev->dev_private);
9118
9119 out:
9120 intel_runtime_pm_put(dev_priv);
9121 }
9122
9123
9124 /**
9125 * intel_mark_fb_busy - mark given planes as busy
9126 * @dev: DRM device
9127 * @frontbuffer_bits: bits for the affected planes
9128 * @ring: optional ring for asynchronous commands
9129 *
9130 * This function gets called every time the screen contents change. It can be
9131 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9132 */
9133 static void intel_mark_fb_busy(struct drm_device *dev,
9134 unsigned frontbuffer_bits,
9135 struct intel_engine_cs *ring)
9136 {
9137 struct drm_i915_private *dev_priv = dev->dev_private;
9138 enum pipe pipe;
9139
9140 if (!i915.powersave)
9141 return;
9142
9143 for_each_pipe(dev_priv, pipe) {
9144 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9145 continue;
9146
9147 intel_increase_pllclock(dev, pipe);
9148 if (ring && intel_fbc_enabled(dev))
9149 ring->fbc_dirty = true;
9150 }
9151 }
9152
9153 /**
9154 * intel_fb_obj_invalidate - invalidate frontbuffer object
9155 * @obj: GEM object to invalidate
9156 * @ring: set for asynchronous rendering
9157 *
9158 * This function gets called every time rendering on the given object starts and
9159 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9160 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9161 * until the rendering completes or a flip on this frontbuffer plane is
9162 * scheduled.
9163 */
9164 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9165 struct intel_engine_cs *ring)
9166 {
9167 struct drm_device *dev = obj->base.dev;
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169
9170 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9171
9172 if (!obj->frontbuffer_bits)
9173 return;
9174
9175 if (ring) {
9176 mutex_lock(&dev_priv->fb_tracking.lock);
9177 dev_priv->fb_tracking.busy_bits
9178 |= obj->frontbuffer_bits;
9179 dev_priv->fb_tracking.flip_bits
9180 &= ~obj->frontbuffer_bits;
9181 mutex_unlock(&dev_priv->fb_tracking.lock);
9182 }
9183
9184 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9185
9186 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9187 }
9188
9189 /**
9190 * intel_frontbuffer_flush - flush frontbuffer
9191 * @dev: DRM device
9192 * @frontbuffer_bits: frontbuffer plane tracking bits
9193 *
9194 * This function gets called every time rendering on the given planes has
9195 * completed and frontbuffer caching can be started again. Flushes will get
9196 * delayed if they're blocked by some oustanding asynchronous rendering.
9197 *
9198 * Can be called without any locks held.
9199 */
9200 void intel_frontbuffer_flush(struct drm_device *dev,
9201 unsigned frontbuffer_bits)
9202 {
9203 struct drm_i915_private *dev_priv = dev->dev_private;
9204
9205 /* Delay flushing when rings are still busy.*/
9206 mutex_lock(&dev_priv->fb_tracking.lock);
9207 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9208 mutex_unlock(&dev_priv->fb_tracking.lock);
9209
9210 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9211
9212 intel_edp_psr_flush(dev, frontbuffer_bits);
9213
9214 /*
9215 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9216 * needs to be reworked into a proper frontbuffer tracking scheme like
9217 * psr employs.
9218 */
9219 if (IS_BROADWELL(dev))
9220 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9221 }
9222
9223 /**
9224 * intel_fb_obj_flush - flush frontbuffer object
9225 * @obj: GEM object to flush
9226 * @retire: set when retiring asynchronous rendering
9227 *
9228 * This function gets called every time rendering on the given object has
9229 * completed and frontbuffer caching can be started again. If @retire is true
9230 * then any delayed flushes will be unblocked.
9231 */
9232 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9233 bool retire)
9234 {
9235 struct drm_device *dev = obj->base.dev;
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237 unsigned frontbuffer_bits;
9238
9239 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9240
9241 if (!obj->frontbuffer_bits)
9242 return;
9243
9244 frontbuffer_bits = obj->frontbuffer_bits;
9245
9246 if (retire) {
9247 mutex_lock(&dev_priv->fb_tracking.lock);
9248 /* Filter out new bits since rendering started. */
9249 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9250
9251 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9252 mutex_unlock(&dev_priv->fb_tracking.lock);
9253 }
9254
9255 intel_frontbuffer_flush(dev, frontbuffer_bits);
9256 }
9257
9258 /**
9259 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9260 * @dev: DRM device
9261 * @frontbuffer_bits: frontbuffer plane tracking bits
9262 *
9263 * This function gets called after scheduling a flip on @obj. The actual
9264 * frontbuffer flushing will be delayed until completion is signalled with
9265 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9266 * flush will be cancelled.
9267 *
9268 * Can be called without any locks held.
9269 */
9270 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9271 unsigned frontbuffer_bits)
9272 {
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274
9275 mutex_lock(&dev_priv->fb_tracking.lock);
9276 dev_priv->fb_tracking.flip_bits
9277 |= frontbuffer_bits;
9278 mutex_unlock(&dev_priv->fb_tracking.lock);
9279 }
9280
9281 /**
9282 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9283 * @dev: DRM device
9284 * @frontbuffer_bits: frontbuffer plane tracking bits
9285 *
9286 * This function gets called after the flip has been latched and will complete
9287 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9288 *
9289 * Can be called without any locks held.
9290 */
9291 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9292 unsigned frontbuffer_bits)
9293 {
9294 struct drm_i915_private *dev_priv = dev->dev_private;
9295
9296 mutex_lock(&dev_priv->fb_tracking.lock);
9297 /* Mask any cancelled flips. */
9298 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9299 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9300 mutex_unlock(&dev_priv->fb_tracking.lock);
9301
9302 intel_frontbuffer_flush(dev, frontbuffer_bits);
9303 }
9304
9305 static void intel_crtc_destroy(struct drm_crtc *crtc)
9306 {
9307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9308 struct drm_device *dev = crtc->dev;
9309 struct intel_unpin_work *work;
9310 unsigned long flags;
9311
9312 spin_lock_irqsave(&dev->event_lock, flags);
9313 work = intel_crtc->unpin_work;
9314 intel_crtc->unpin_work = NULL;
9315 spin_unlock_irqrestore(&dev->event_lock, flags);
9316
9317 if (work) {
9318 cancel_work_sync(&work->work);
9319 kfree(work);
9320 }
9321
9322 drm_crtc_cleanup(crtc);
9323
9324 kfree(intel_crtc);
9325 }
9326
9327 static void intel_unpin_work_fn(struct work_struct *__work)
9328 {
9329 struct intel_unpin_work *work =
9330 container_of(__work, struct intel_unpin_work, work);
9331 struct drm_device *dev = work->crtc->dev;
9332 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9333
9334 mutex_lock(&dev->struct_mutex);
9335 intel_unpin_fb_obj(work->old_fb_obj);
9336 drm_gem_object_unreference(&work->pending_flip_obj->base);
9337 drm_gem_object_unreference(&work->old_fb_obj->base);
9338
9339 intel_update_fbc(dev);
9340 mutex_unlock(&dev->struct_mutex);
9341
9342 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9343
9344 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9345 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9346
9347 kfree(work);
9348 }
9349
9350 static void do_intel_finish_page_flip(struct drm_device *dev,
9351 struct drm_crtc *crtc)
9352 {
9353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9354 struct intel_unpin_work *work;
9355 unsigned long flags;
9356
9357 /* Ignore early vblank irqs */
9358 if (intel_crtc == NULL)
9359 return;
9360
9361 spin_lock_irqsave(&dev->event_lock, flags);
9362 work = intel_crtc->unpin_work;
9363
9364 /* Ensure we don't miss a work->pending update ... */
9365 smp_rmb();
9366
9367 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9368 spin_unlock_irqrestore(&dev->event_lock, flags);
9369 return;
9370 }
9371
9372 page_flip_completed(intel_crtc);
9373
9374 spin_unlock_irqrestore(&dev->event_lock, flags);
9375 }
9376
9377 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9378 {
9379 struct drm_i915_private *dev_priv = dev->dev_private;
9380 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9381
9382 do_intel_finish_page_flip(dev, crtc);
9383 }
9384
9385 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9386 {
9387 struct drm_i915_private *dev_priv = dev->dev_private;
9388 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9389
9390 do_intel_finish_page_flip(dev, crtc);
9391 }
9392
9393 /* Is 'a' after or equal to 'b'? */
9394 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9395 {
9396 return !((a - b) & 0x80000000);
9397 }
9398
9399 static bool page_flip_finished(struct intel_crtc *crtc)
9400 {
9401 struct drm_device *dev = crtc->base.dev;
9402 struct drm_i915_private *dev_priv = dev->dev_private;
9403
9404 /*
9405 * The relevant registers doen't exist on pre-ctg.
9406 * As the flip done interrupt doesn't trigger for mmio
9407 * flips on gmch platforms, a flip count check isn't
9408 * really needed there. But since ctg has the registers,
9409 * include it in the check anyway.
9410 */
9411 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9412 return true;
9413
9414 /*
9415 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9416 * used the same base address. In that case the mmio flip might
9417 * have completed, but the CS hasn't even executed the flip yet.
9418 *
9419 * A flip count check isn't enough as the CS might have updated
9420 * the base address just after start of vblank, but before we
9421 * managed to process the interrupt. This means we'd complete the
9422 * CS flip too soon.
9423 *
9424 * Combining both checks should get us a good enough result. It may
9425 * still happen that the CS flip has been executed, but has not
9426 * yet actually completed. But in case the base address is the same
9427 * anyway, we don't really care.
9428 */
9429 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9430 crtc->unpin_work->gtt_offset &&
9431 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9432 crtc->unpin_work->flip_count);
9433 }
9434
9435 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9436 {
9437 struct drm_i915_private *dev_priv = dev->dev_private;
9438 struct intel_crtc *intel_crtc =
9439 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9440 unsigned long flags;
9441
9442 /* NB: An MMIO update of the plane base pointer will also
9443 * generate a page-flip completion irq, i.e. every modeset
9444 * is also accompanied by a spurious intel_prepare_page_flip().
9445 */
9446 spin_lock_irqsave(&dev->event_lock, flags);
9447 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9448 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9449 spin_unlock_irqrestore(&dev->event_lock, flags);
9450 }
9451
9452 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9453 {
9454 /* Ensure that the work item is consistent when activating it ... */
9455 smp_wmb();
9456 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9457 /* and that it is marked active as soon as the irq could fire. */
9458 smp_wmb();
9459 }
9460
9461 static int intel_gen2_queue_flip(struct drm_device *dev,
9462 struct drm_crtc *crtc,
9463 struct drm_framebuffer *fb,
9464 struct drm_i915_gem_object *obj,
9465 struct intel_engine_cs *ring,
9466 uint32_t flags)
9467 {
9468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9469 u32 flip_mask;
9470 int ret;
9471
9472 ret = intel_ring_begin(ring, 6);
9473 if (ret)
9474 return ret;
9475
9476 /* Can't queue multiple flips, so wait for the previous
9477 * one to finish before executing the next.
9478 */
9479 if (intel_crtc->plane)
9480 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9481 else
9482 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9483 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9484 intel_ring_emit(ring, MI_NOOP);
9485 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9486 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9487 intel_ring_emit(ring, fb->pitches[0]);
9488 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9489 intel_ring_emit(ring, 0); /* aux display base address, unused */
9490
9491 intel_mark_page_flip_active(intel_crtc);
9492 __intel_ring_advance(ring);
9493 return 0;
9494 }
9495
9496 static int intel_gen3_queue_flip(struct drm_device *dev,
9497 struct drm_crtc *crtc,
9498 struct drm_framebuffer *fb,
9499 struct drm_i915_gem_object *obj,
9500 struct intel_engine_cs *ring,
9501 uint32_t flags)
9502 {
9503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9504 u32 flip_mask;
9505 int ret;
9506
9507 ret = intel_ring_begin(ring, 6);
9508 if (ret)
9509 return ret;
9510
9511 if (intel_crtc->plane)
9512 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9513 else
9514 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9515 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9516 intel_ring_emit(ring, MI_NOOP);
9517 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9518 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9519 intel_ring_emit(ring, fb->pitches[0]);
9520 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9521 intel_ring_emit(ring, MI_NOOP);
9522
9523 intel_mark_page_flip_active(intel_crtc);
9524 __intel_ring_advance(ring);
9525 return 0;
9526 }
9527
9528 static int intel_gen4_queue_flip(struct drm_device *dev,
9529 struct drm_crtc *crtc,
9530 struct drm_framebuffer *fb,
9531 struct drm_i915_gem_object *obj,
9532 struct intel_engine_cs *ring,
9533 uint32_t flags)
9534 {
9535 struct drm_i915_private *dev_priv = dev->dev_private;
9536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9537 uint32_t pf, pipesrc;
9538 int ret;
9539
9540 ret = intel_ring_begin(ring, 4);
9541 if (ret)
9542 return ret;
9543
9544 /* i965+ uses the linear or tiled offsets from the
9545 * Display Registers (which do not change across a page-flip)
9546 * so we need only reprogram the base address.
9547 */
9548 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9549 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9550 intel_ring_emit(ring, fb->pitches[0]);
9551 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9552 obj->tiling_mode);
9553
9554 /* XXX Enabling the panel-fitter across page-flip is so far
9555 * untested on non-native modes, so ignore it for now.
9556 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9557 */
9558 pf = 0;
9559 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9560 intel_ring_emit(ring, pf | pipesrc);
9561
9562 intel_mark_page_flip_active(intel_crtc);
9563 __intel_ring_advance(ring);
9564 return 0;
9565 }
9566
9567 static int intel_gen6_queue_flip(struct drm_device *dev,
9568 struct drm_crtc *crtc,
9569 struct drm_framebuffer *fb,
9570 struct drm_i915_gem_object *obj,
9571 struct intel_engine_cs *ring,
9572 uint32_t flags)
9573 {
9574 struct drm_i915_private *dev_priv = dev->dev_private;
9575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9576 uint32_t pf, pipesrc;
9577 int ret;
9578
9579 ret = intel_ring_begin(ring, 4);
9580 if (ret)
9581 return ret;
9582
9583 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9584 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9585 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9586 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9587
9588 /* Contrary to the suggestions in the documentation,
9589 * "Enable Panel Fitter" does not seem to be required when page
9590 * flipping with a non-native mode, and worse causes a normal
9591 * modeset to fail.
9592 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9593 */
9594 pf = 0;
9595 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9596 intel_ring_emit(ring, pf | pipesrc);
9597
9598 intel_mark_page_flip_active(intel_crtc);
9599 __intel_ring_advance(ring);
9600 return 0;
9601 }
9602
9603 static int intel_gen7_queue_flip(struct drm_device *dev,
9604 struct drm_crtc *crtc,
9605 struct drm_framebuffer *fb,
9606 struct drm_i915_gem_object *obj,
9607 struct intel_engine_cs *ring,
9608 uint32_t flags)
9609 {
9610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9611 uint32_t plane_bit = 0;
9612 int len, ret;
9613
9614 switch (intel_crtc->plane) {
9615 case PLANE_A:
9616 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9617 break;
9618 case PLANE_B:
9619 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9620 break;
9621 case PLANE_C:
9622 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9623 break;
9624 default:
9625 WARN_ONCE(1, "unknown plane in flip command\n");
9626 return -ENODEV;
9627 }
9628
9629 len = 4;
9630 if (ring->id == RCS) {
9631 len += 6;
9632 /*
9633 * On Gen 8, SRM is now taking an extra dword to accommodate
9634 * 48bits addresses, and we need a NOOP for the batch size to
9635 * stay even.
9636 */
9637 if (IS_GEN8(dev))
9638 len += 2;
9639 }
9640
9641 /*
9642 * BSpec MI_DISPLAY_FLIP for IVB:
9643 * "The full packet must be contained within the same cache line."
9644 *
9645 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9646 * cacheline, if we ever start emitting more commands before
9647 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9648 * then do the cacheline alignment, and finally emit the
9649 * MI_DISPLAY_FLIP.
9650 */
9651 ret = intel_ring_cacheline_align(ring);
9652 if (ret)
9653 return ret;
9654
9655 ret = intel_ring_begin(ring, len);
9656 if (ret)
9657 return ret;
9658
9659 /* Unmask the flip-done completion message. Note that the bspec says that
9660 * we should do this for both the BCS and RCS, and that we must not unmask
9661 * more than one flip event at any time (or ensure that one flip message
9662 * can be sent by waiting for flip-done prior to queueing new flips).
9663 * Experimentation says that BCS works despite DERRMR masking all
9664 * flip-done completion events and that unmasking all planes at once
9665 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9666 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9667 */
9668 if (ring->id == RCS) {
9669 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9670 intel_ring_emit(ring, DERRMR);
9671 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9672 DERRMR_PIPEB_PRI_FLIP_DONE |
9673 DERRMR_PIPEC_PRI_FLIP_DONE));
9674 if (IS_GEN8(dev))
9675 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9676 MI_SRM_LRM_GLOBAL_GTT);
9677 else
9678 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9679 MI_SRM_LRM_GLOBAL_GTT);
9680 intel_ring_emit(ring, DERRMR);
9681 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9682 if (IS_GEN8(dev)) {
9683 intel_ring_emit(ring, 0);
9684 intel_ring_emit(ring, MI_NOOP);
9685 }
9686 }
9687
9688 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9689 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9690 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9691 intel_ring_emit(ring, (MI_NOOP));
9692
9693 intel_mark_page_flip_active(intel_crtc);
9694 __intel_ring_advance(ring);
9695 return 0;
9696 }
9697
9698 static bool use_mmio_flip(struct intel_engine_cs *ring,
9699 struct drm_i915_gem_object *obj)
9700 {
9701 /*
9702 * This is not being used for older platforms, because
9703 * non-availability of flip done interrupt forces us to use
9704 * CS flips. Older platforms derive flip done using some clever
9705 * tricks involving the flip_pending status bits and vblank irqs.
9706 * So using MMIO flips there would disrupt this mechanism.
9707 */
9708
9709 if (ring == NULL)
9710 return true;
9711
9712 if (INTEL_INFO(ring->dev)->gen < 5)
9713 return false;
9714
9715 if (i915.use_mmio_flip < 0)
9716 return false;
9717 else if (i915.use_mmio_flip > 0)
9718 return true;
9719 else if (i915.enable_execlists)
9720 return true;
9721 else
9722 return ring != obj->ring;
9723 }
9724
9725 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9726 {
9727 struct drm_device *dev = intel_crtc->base.dev;
9728 struct drm_i915_private *dev_priv = dev->dev_private;
9729 struct intel_framebuffer *intel_fb =
9730 to_intel_framebuffer(intel_crtc->base.primary->fb);
9731 struct drm_i915_gem_object *obj = intel_fb->obj;
9732 u32 dspcntr;
9733 u32 reg;
9734
9735 intel_mark_page_flip_active(intel_crtc);
9736
9737 reg = DSPCNTR(intel_crtc->plane);
9738 dspcntr = I915_READ(reg);
9739
9740 if (INTEL_INFO(dev)->gen >= 4) {
9741 if (obj->tiling_mode != I915_TILING_NONE)
9742 dspcntr |= DISPPLANE_TILED;
9743 else
9744 dspcntr &= ~DISPPLANE_TILED;
9745 }
9746 I915_WRITE(reg, dspcntr);
9747
9748 I915_WRITE(DSPSURF(intel_crtc->plane),
9749 intel_crtc->unpin_work->gtt_offset);
9750 POSTING_READ(DSPSURF(intel_crtc->plane));
9751 }
9752
9753 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9754 {
9755 struct intel_engine_cs *ring;
9756 int ret;
9757
9758 lockdep_assert_held(&obj->base.dev->struct_mutex);
9759
9760 if (!obj->last_write_seqno)
9761 return 0;
9762
9763 ring = obj->ring;
9764
9765 if (i915_seqno_passed(ring->get_seqno(ring, true),
9766 obj->last_write_seqno))
9767 return 0;
9768
9769 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9770 if (ret)
9771 return ret;
9772
9773 if (WARN_ON(!ring->irq_get(ring)))
9774 return 0;
9775
9776 return 1;
9777 }
9778
9779 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9780 {
9781 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9782 struct intel_crtc *intel_crtc;
9783 unsigned long irq_flags;
9784 u32 seqno;
9785
9786 seqno = ring->get_seqno(ring, false);
9787
9788 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9789 for_each_intel_crtc(ring->dev, intel_crtc) {
9790 struct intel_mmio_flip *mmio_flip;
9791
9792 mmio_flip = &intel_crtc->mmio_flip;
9793 if (mmio_flip->seqno == 0)
9794 continue;
9795
9796 if (ring->id != mmio_flip->ring_id)
9797 continue;
9798
9799 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9800 intel_do_mmio_flip(intel_crtc);
9801 mmio_flip->seqno = 0;
9802 ring->irq_put(ring);
9803 }
9804 }
9805 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9806 }
9807
9808 static int intel_queue_mmio_flip(struct drm_device *dev,
9809 struct drm_crtc *crtc,
9810 struct drm_framebuffer *fb,
9811 struct drm_i915_gem_object *obj,
9812 struct intel_engine_cs *ring,
9813 uint32_t flags)
9814 {
9815 struct drm_i915_private *dev_priv = dev->dev_private;
9816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9817 unsigned long irq_flags;
9818 int ret;
9819
9820 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9821 return -EBUSY;
9822
9823 ret = intel_postpone_flip(obj);
9824 if (ret < 0)
9825 return ret;
9826 if (ret == 0) {
9827 intel_do_mmio_flip(intel_crtc);
9828 return 0;
9829 }
9830
9831 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9832 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9833 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9834 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9835
9836 /*
9837 * Double check to catch cases where irq fired before
9838 * mmio flip data was ready
9839 */
9840 intel_notify_mmio_flip(obj->ring);
9841 return 0;
9842 }
9843
9844 static int intel_default_queue_flip(struct drm_device *dev,
9845 struct drm_crtc *crtc,
9846 struct drm_framebuffer *fb,
9847 struct drm_i915_gem_object *obj,
9848 struct intel_engine_cs *ring,
9849 uint32_t flags)
9850 {
9851 return -ENODEV;
9852 }
9853
9854 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9855 struct drm_crtc *crtc)
9856 {
9857 struct drm_i915_private *dev_priv = dev->dev_private;
9858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9859 struct intel_unpin_work *work = intel_crtc->unpin_work;
9860 u32 addr;
9861
9862 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9863 return true;
9864
9865 if (!work->enable_stall_check)
9866 return false;
9867
9868 if (work->flip_ready_vblank == 0) {
9869 if (work->flip_queued_ring &&
9870 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9871 work->flip_queued_seqno))
9872 return false;
9873
9874 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9875 }
9876
9877 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9878 return false;
9879
9880 /* Potential stall - if we see that the flip has happened,
9881 * assume a missed interrupt. */
9882 if (INTEL_INFO(dev)->gen >= 4)
9883 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9884 else
9885 addr = I915_READ(DSPADDR(intel_crtc->plane));
9886
9887 /* There is a potential issue here with a false positive after a flip
9888 * to the same address. We could address this by checking for a
9889 * non-incrementing frame counter.
9890 */
9891 return addr == work->gtt_offset;
9892 }
9893
9894 void intel_check_page_flip(struct drm_device *dev, int pipe)
9895 {
9896 struct drm_i915_private *dev_priv = dev->dev_private;
9897 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9899 unsigned long flags;
9900
9901 if (crtc == NULL)
9902 return;
9903
9904 spin_lock_irqsave(&dev->event_lock, flags);
9905 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9906 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9907 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9908 page_flip_completed(intel_crtc);
9909 }
9910 spin_unlock_irqrestore(&dev->event_lock, flags);
9911 }
9912
9913 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9914 struct drm_framebuffer *fb,
9915 struct drm_pending_vblank_event *event,
9916 uint32_t page_flip_flags)
9917 {
9918 struct drm_device *dev = crtc->dev;
9919 struct drm_i915_private *dev_priv = dev->dev_private;
9920 struct drm_framebuffer *old_fb = crtc->primary->fb;
9921 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9923 enum pipe pipe = intel_crtc->pipe;
9924 struct intel_unpin_work *work;
9925 struct intel_engine_cs *ring;
9926 unsigned long flags;
9927 int ret;
9928
9929 //trigger software GT busyness calculation
9930 gen8_flip_interrupt(dev);
9931
9932 /*
9933 * drm_mode_page_flip_ioctl() should already catch this, but double
9934 * check to be safe. In the future we may enable pageflipping from
9935 * a disabled primary plane.
9936 */
9937 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9938 return -EBUSY;
9939
9940 /* Can't change pixel format via MI display flips. */
9941 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9942 return -EINVAL;
9943
9944 /*
9945 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9946 * Note that pitch changes could also affect these register.
9947 */
9948 if (INTEL_INFO(dev)->gen > 3 &&
9949 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9950 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9951 return -EINVAL;
9952
9953 if (i915_terminally_wedged(&dev_priv->gpu_error))
9954 goto out_hang;
9955
9956 work = kzalloc(sizeof(*work), GFP_KERNEL);
9957 if (work == NULL)
9958 return -ENOMEM;
9959
9960 work->event = event;
9961 work->crtc = crtc;
9962 work->old_fb_obj = intel_fb_obj(old_fb);
9963 INIT_WORK(&work->work, intel_unpin_work_fn);
9964
9965 ret = drm_crtc_vblank_get(crtc);
9966 if (ret)
9967 goto free_work;
9968
9969 /* We borrow the event spin lock for protecting unpin_work */
9970 spin_lock_irqsave(&dev->event_lock, flags);
9971 if (intel_crtc->unpin_work) {
9972 /* Before declaring the flip queue wedged, check if
9973 * the hardware completed the operation behind our backs.
9974 */
9975 if (__intel_pageflip_stall_check(dev, crtc)) {
9976 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9977 page_flip_completed(intel_crtc);
9978 } else {
9979 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9980 spin_unlock_irqrestore(&dev->event_lock, flags);
9981
9982 drm_crtc_vblank_put(crtc);
9983 kfree(work);
9984 return -EBUSY;
9985 }
9986 }
9987 intel_crtc->unpin_work = work;
9988 spin_unlock_irqrestore(&dev->event_lock, flags);
9989
9990 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9991 flush_workqueue(dev_priv->wq);
9992
9993 ret = i915_mutex_lock_interruptible(dev);
9994 if (ret)
9995 goto cleanup;
9996
9997 /* Reference the objects for the scheduled work. */
9998 drm_gem_object_reference(&work->old_fb_obj->base);
9999 drm_gem_object_reference(&obj->base);
10000
10001 crtc->primary->fb = fb;
10002
10003 work->pending_flip_obj = obj;
10004
10005 atomic_inc(&intel_crtc->unpin_work_count);
10006 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10007
10008 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10009 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10010
10011 if (IS_VALLEYVIEW(dev)) {
10012 ring = &dev_priv->ring[BCS];
10013 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10014 /* vlv: DISPLAY_FLIP fails to change tiling */
10015 ring = NULL;
10016 } else if (IS_IVYBRIDGE(dev)) {
10017 ring = &dev_priv->ring[BCS];
10018 } else if (INTEL_INFO(dev)->gen >= 7) {
10019 ring = obj->ring;
10020 if (ring == NULL || ring->id != RCS)
10021 ring = &dev_priv->ring[BCS];
10022 } else {
10023 ring = &dev_priv->ring[RCS];
10024 }
10025
10026 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10027 if (ret)
10028 goto cleanup_pending;
10029
10030 work->gtt_offset =
10031 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10032
10033 if (use_mmio_flip(ring, obj)) {
10034 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10035 page_flip_flags);
10036 if (ret)
10037 goto cleanup_unpin;
10038
10039 work->flip_queued_seqno = obj->last_write_seqno;
10040 work->flip_queued_ring = obj->ring;
10041 } else {
10042 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10043 page_flip_flags);
10044 if (ret)
10045 goto cleanup_unpin;
10046
10047 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10048 work->flip_queued_ring = ring;
10049 }
10050
10051 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10052 work->enable_stall_check = true;
10053
10054 i915_gem_track_fb(work->old_fb_obj, obj,
10055 INTEL_FRONTBUFFER_PRIMARY(pipe));
10056
10057 intel_disable_fbc(dev);
10058 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10059 mutex_unlock(&dev->struct_mutex);
10060
10061 trace_i915_flip_request(intel_crtc->plane, obj);
10062
10063 return 0;
10064
10065 cleanup_unpin:
10066 intel_unpin_fb_obj(obj);
10067 cleanup_pending:
10068 atomic_dec(&intel_crtc->unpin_work_count);
10069 crtc->primary->fb = old_fb;
10070 drm_gem_object_unreference(&work->old_fb_obj->base);
10071 drm_gem_object_unreference(&obj->base);
10072 mutex_unlock(&dev->struct_mutex);
10073
10074 cleanup:
10075 spin_lock_irqsave(&dev->event_lock, flags);
10076 intel_crtc->unpin_work = NULL;
10077 spin_unlock_irqrestore(&dev->event_lock, flags);
10078
10079 drm_crtc_vblank_put(crtc);
10080 free_work:
10081 kfree(work);
10082
10083 if (ret == -EIO) {
10084 out_hang:
10085 intel_crtc_wait_for_pending_flips(crtc);
10086 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10087 if (ret == 0 && event) {
10088 spin_lock_irqsave(&dev->event_lock, flags);
10089 drm_send_vblank_event(dev, pipe, event);
10090 spin_unlock_irqrestore(&dev->event_lock, flags);
10091 }
10092 }
10093 return ret;
10094 }
10095
10096 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10097 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10098 .load_lut = intel_crtc_load_lut,
10099 };
10100
10101 /**
10102 * intel_modeset_update_staged_output_state
10103 *
10104 * Updates the staged output configuration state, e.g. after we've read out the
10105 * current hw state.
10106 */
10107 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10108 {
10109 struct intel_crtc *crtc;
10110 struct intel_encoder *encoder;
10111 struct intel_connector *connector;
10112
10113 list_for_each_entry(connector, &dev->mode_config.connector_list,
10114 base.head) {
10115 connector->new_encoder =
10116 to_intel_encoder(connector->base.encoder);
10117 }
10118
10119 for_each_intel_encoder(dev, encoder) {
10120 encoder->new_crtc =
10121 to_intel_crtc(encoder->base.crtc);
10122 }
10123
10124 for_each_intel_crtc(dev, crtc) {
10125 crtc->new_enabled = crtc->base.enabled;
10126
10127 if (crtc->new_enabled)
10128 crtc->new_config = &crtc->config;
10129 else
10130 crtc->new_config = NULL;
10131 }
10132 }
10133
10134 /**
10135 * intel_modeset_commit_output_state
10136 *
10137 * This function copies the stage display pipe configuration to the real one.
10138 */
10139 static void intel_modeset_commit_output_state(struct drm_device *dev)
10140 {
10141 struct intel_crtc *crtc;
10142 struct intel_encoder *encoder;
10143 struct intel_connector *connector;
10144
10145 list_for_each_entry(connector, &dev->mode_config.connector_list,
10146 base.head) {
10147 connector->base.encoder = &connector->new_encoder->base;
10148 }
10149
10150 for_each_intel_encoder(dev, encoder) {
10151 encoder->base.crtc = &encoder->new_crtc->base;
10152 }
10153
10154 for_each_intel_crtc(dev, crtc) {
10155 crtc->base.enabled = crtc->new_enabled;
10156 }
10157 }
10158
10159 static void
10160 connected_sink_compute_bpp(struct intel_connector *connector,
10161 struct intel_crtc_config *pipe_config)
10162 {
10163 int bpp = pipe_config->pipe_bpp;
10164
10165 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10166 connector->base.base.id,
10167 connector->base.name);
10168
10169 /* Don't use an invalid EDID bpc value */
10170 if (connector->base.display_info.bpc &&
10171 connector->base.display_info.bpc * 3 < bpp) {
10172 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10173 bpp, connector->base.display_info.bpc*3);
10174 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10175 }
10176
10177 /* Clamp bpp to 8 on screens without EDID 1.4 */
10178 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10179 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10180 bpp);
10181 pipe_config->pipe_bpp = 24;
10182 }
10183 }
10184
10185 static int
10186 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10187 struct drm_framebuffer *fb,
10188 struct intel_crtc_config *pipe_config)
10189 {
10190 struct drm_device *dev = crtc->base.dev;
10191 struct intel_connector *connector;
10192 int bpp;
10193
10194 switch (fb->pixel_format) {
10195 case DRM_FORMAT_C8:
10196 bpp = 8*3; /* since we go through a colormap */
10197 break;
10198 case DRM_FORMAT_XRGB1555:
10199 case DRM_FORMAT_ARGB1555:
10200 /* checked in intel_framebuffer_init already */
10201 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10202 return -EINVAL;
10203 case DRM_FORMAT_RGB565:
10204 bpp = 6*3; /* min is 18bpp */
10205 break;
10206 case DRM_FORMAT_XBGR8888:
10207 case DRM_FORMAT_ABGR8888:
10208 /* checked in intel_framebuffer_init already */
10209 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10210 return -EINVAL;
10211 case DRM_FORMAT_XRGB8888:
10212 case DRM_FORMAT_ARGB8888:
10213 bpp = 8*3;
10214 break;
10215 case DRM_FORMAT_XRGB2101010:
10216 case DRM_FORMAT_ARGB2101010:
10217 case DRM_FORMAT_XBGR2101010:
10218 case DRM_FORMAT_ABGR2101010:
10219 /* checked in intel_framebuffer_init already */
10220 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10221 return -EINVAL;
10222 bpp = 10*3;
10223 break;
10224 /* TODO: gen4+ supports 16 bpc floating point, too. */
10225 default:
10226 DRM_DEBUG_KMS("unsupported depth\n");
10227 return -EINVAL;
10228 }
10229
10230 pipe_config->pipe_bpp = bpp;
10231
10232 /* Clamp display bpp to EDID value */
10233 list_for_each_entry(connector, &dev->mode_config.connector_list,
10234 base.head) {
10235 if (!connector->new_encoder ||
10236 connector->new_encoder->new_crtc != crtc)
10237 continue;
10238
10239 connected_sink_compute_bpp(connector, pipe_config);
10240 }
10241
10242 return bpp;
10243 }
10244
10245 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10246 {
10247 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10248 "type: 0x%x flags: 0x%x\n",
10249 mode->crtc_clock,
10250 mode->crtc_hdisplay, mode->crtc_hsync_start,
10251 mode->crtc_hsync_end, mode->crtc_htotal,
10252 mode->crtc_vdisplay, mode->crtc_vsync_start,
10253 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10254 }
10255
10256 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10257 struct intel_crtc_config *pipe_config,
10258 const char *context)
10259 {
10260 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10261 context, pipe_name(crtc->pipe));
10262
10263 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10264 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10265 pipe_config->pipe_bpp, pipe_config->dither);
10266 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10267 pipe_config->has_pch_encoder,
10268 pipe_config->fdi_lanes,
10269 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10270 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10271 pipe_config->fdi_m_n.tu);
10272 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10273 pipe_config->has_dp_encoder,
10274 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10275 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10276 pipe_config->dp_m_n.tu);
10277
10278 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10279 pipe_config->has_dp_encoder,
10280 pipe_config->dp_m2_n2.gmch_m,
10281 pipe_config->dp_m2_n2.gmch_n,
10282 pipe_config->dp_m2_n2.link_m,
10283 pipe_config->dp_m2_n2.link_n,
10284 pipe_config->dp_m2_n2.tu);
10285
10286 DRM_DEBUG_KMS("requested mode:\n");
10287 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10288 DRM_DEBUG_KMS("adjusted mode:\n");
10289 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10290 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10291 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10292 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10293 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10294 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10295 pipe_config->gmch_pfit.control,
10296 pipe_config->gmch_pfit.pgm_ratios,
10297 pipe_config->gmch_pfit.lvds_border_bits);
10298 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10299 pipe_config->pch_pfit.pos,
10300 pipe_config->pch_pfit.size,
10301 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10302 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10303 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10304 }
10305
10306 static bool encoders_cloneable(const struct intel_encoder *a,
10307 const struct intel_encoder *b)
10308 {
10309 /* masks could be asymmetric, so check both ways */
10310 return a == b || (a->cloneable & (1 << b->type) &&
10311 b->cloneable & (1 << a->type));
10312 }
10313
10314 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10315 struct intel_encoder *encoder)
10316 {
10317 struct drm_device *dev = crtc->base.dev;
10318 struct intel_encoder *source_encoder;
10319
10320 for_each_intel_encoder(dev, source_encoder) {
10321 if (source_encoder->new_crtc != crtc)
10322 continue;
10323
10324 if (!encoders_cloneable(encoder, source_encoder))
10325 return false;
10326 }
10327
10328 return true;
10329 }
10330
10331 static bool check_encoder_cloning(struct intel_crtc *crtc)
10332 {
10333 struct drm_device *dev = crtc->base.dev;
10334 struct intel_encoder *encoder;
10335
10336 for_each_intel_encoder(dev, encoder) {
10337 if (encoder->new_crtc != crtc)
10338 continue;
10339
10340 if (!check_single_encoder_cloning(crtc, encoder))
10341 return false;
10342 }
10343
10344 return true;
10345 }
10346
10347 static struct intel_crtc_config *
10348 intel_modeset_pipe_config(struct drm_crtc *crtc,
10349 struct drm_framebuffer *fb,
10350 struct drm_display_mode *mode)
10351 {
10352 struct drm_device *dev = crtc->dev;
10353 struct intel_encoder *encoder;
10354 struct intel_crtc_config *pipe_config;
10355 int plane_bpp, ret = -EINVAL;
10356 bool retry = true;
10357
10358 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10359 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10360 return ERR_PTR(-EINVAL);
10361 }
10362
10363 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10364 if (!pipe_config)
10365 return ERR_PTR(-ENOMEM);
10366
10367 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10368 drm_mode_copy(&pipe_config->requested_mode, mode);
10369
10370 pipe_config->cpu_transcoder =
10371 (enum transcoder) to_intel_crtc(crtc)->pipe;
10372 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10373
10374 /*
10375 * Sanitize sync polarity flags based on requested ones. If neither
10376 * positive or negative polarity is requested, treat this as meaning
10377 * negative polarity.
10378 */
10379 if (!(pipe_config->adjusted_mode.flags &
10380 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10381 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10382
10383 if (!(pipe_config->adjusted_mode.flags &
10384 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10385 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10386
10387 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10388 * plane pixel format and any sink constraints into account. Returns the
10389 * source plane bpp so that dithering can be selected on mismatches
10390 * after encoders and crtc also have had their say. */
10391 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10392 fb, pipe_config);
10393 if (plane_bpp < 0)
10394 goto fail;
10395
10396 /*
10397 * Determine the real pipe dimensions. Note that stereo modes can
10398 * increase the actual pipe size due to the frame doubling and
10399 * insertion of additional space for blanks between the frame. This
10400 * is stored in the crtc timings. We use the requested mode to do this
10401 * computation to clearly distinguish it from the adjusted mode, which
10402 * can be changed by the connectors in the below retry loop.
10403 */
10404 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10405 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10406 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10407
10408 encoder_retry:
10409 /* Ensure the port clock defaults are reset when retrying. */
10410 pipe_config->port_clock = 0;
10411 pipe_config->pixel_multiplier = 1;
10412
10413 /* Fill in default crtc timings, allow encoders to overwrite them. */
10414 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10415
10416 /* Pass our mode to the connectors and the CRTC to give them a chance to
10417 * adjust it according to limitations or connector properties, and also
10418 * a chance to reject the mode entirely.
10419 */
10420 for_each_intel_encoder(dev, encoder) {
10421
10422 if (&encoder->new_crtc->base != crtc)
10423 continue;
10424
10425 if (!(encoder->compute_config(encoder, pipe_config))) {
10426 DRM_DEBUG_KMS("Encoder config failure\n");
10427 goto fail;
10428 }
10429 }
10430
10431 /* Set default port clock if not overwritten by the encoder. Needs to be
10432 * done afterwards in case the encoder adjusts the mode. */
10433 if (!pipe_config->port_clock)
10434 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10435 * pipe_config->pixel_multiplier;
10436
10437 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10438 if (ret < 0) {
10439 DRM_DEBUG_KMS("CRTC fixup failed\n");
10440 goto fail;
10441 }
10442
10443 if (ret == RETRY) {
10444 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10445 ret = -EINVAL;
10446 goto fail;
10447 }
10448
10449 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10450 retry = false;
10451 goto encoder_retry;
10452 }
10453
10454 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10455 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10456 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10457
10458 return pipe_config;
10459 fail:
10460 kfree(pipe_config);
10461 return ERR_PTR(ret);
10462 }
10463
10464 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10465 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10466 static void
10467 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10468 unsigned *prepare_pipes, unsigned *disable_pipes)
10469 {
10470 struct intel_crtc *intel_crtc;
10471 struct drm_device *dev = crtc->dev;
10472 struct intel_encoder *encoder;
10473 struct intel_connector *connector;
10474 struct drm_crtc *tmp_crtc;
10475
10476 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10477
10478 /* Check which crtcs have changed outputs connected to them, these need
10479 * to be part of the prepare_pipes mask. We don't (yet) support global
10480 * modeset across multiple crtcs, so modeset_pipes will only have one
10481 * bit set at most. */
10482 list_for_each_entry(connector, &dev->mode_config.connector_list,
10483 base.head) {
10484 if (connector->base.encoder == &connector->new_encoder->base)
10485 continue;
10486
10487 if (connector->base.encoder) {
10488 tmp_crtc = connector->base.encoder->crtc;
10489
10490 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10491 }
10492
10493 if (connector->new_encoder)
10494 *prepare_pipes |=
10495 1 << connector->new_encoder->new_crtc->pipe;
10496 }
10497
10498 for_each_intel_encoder(dev, encoder) {
10499 if (encoder->base.crtc == &encoder->new_crtc->base)
10500 continue;
10501
10502 if (encoder->base.crtc) {
10503 tmp_crtc = encoder->base.crtc;
10504
10505 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10506 }
10507
10508 if (encoder->new_crtc)
10509 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10510 }
10511
10512 /* Check for pipes that will be enabled/disabled ... */
10513 for_each_intel_crtc(dev, intel_crtc) {
10514 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10515 continue;
10516
10517 if (!intel_crtc->new_enabled)
10518 *disable_pipes |= 1 << intel_crtc->pipe;
10519 else
10520 *prepare_pipes |= 1 << intel_crtc->pipe;
10521 }
10522
10523
10524 /* set_mode is also used to update properties on life display pipes. */
10525 intel_crtc = to_intel_crtc(crtc);
10526 if (intel_crtc->new_enabled)
10527 *prepare_pipes |= 1 << intel_crtc->pipe;
10528
10529 /*
10530 * For simplicity do a full modeset on any pipe where the output routing
10531 * changed. We could be more clever, but that would require us to be
10532 * more careful with calling the relevant encoder->mode_set functions.
10533 */
10534 if (*prepare_pipes)
10535 *modeset_pipes = *prepare_pipes;
10536
10537 /* ... and mask these out. */
10538 *modeset_pipes &= ~(*disable_pipes);
10539 *prepare_pipes &= ~(*disable_pipes);
10540
10541 /*
10542 * HACK: We don't (yet) fully support global modesets. intel_set_config
10543 * obies this rule, but the modeset restore mode of
10544 * intel_modeset_setup_hw_state does not.
10545 */
10546 *modeset_pipes &= 1 << intel_crtc->pipe;
10547 *prepare_pipes &= 1 << intel_crtc->pipe;
10548
10549 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10550 *modeset_pipes, *prepare_pipes, *disable_pipes);
10551 }
10552
10553 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10554 {
10555 struct drm_encoder *encoder;
10556 struct drm_device *dev = crtc->dev;
10557
10558 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10559 if (encoder->crtc == crtc)
10560 return true;
10561
10562 return false;
10563 }
10564
10565 static void
10566 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10567 {
10568 struct intel_encoder *intel_encoder;
10569 struct intel_crtc *intel_crtc;
10570 struct drm_connector *connector;
10571
10572 for_each_intel_encoder(dev, intel_encoder) {
10573 if (!intel_encoder->base.crtc)
10574 continue;
10575
10576 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10577
10578 if (prepare_pipes & (1 << intel_crtc->pipe))
10579 intel_encoder->connectors_active = false;
10580 }
10581
10582 intel_modeset_commit_output_state(dev);
10583
10584 /* Double check state. */
10585 for_each_intel_crtc(dev, intel_crtc) {
10586 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10587 WARN_ON(intel_crtc->new_config &&
10588 intel_crtc->new_config != &intel_crtc->config);
10589 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10590 }
10591
10592 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10593 if (!connector->encoder || !connector->encoder->crtc)
10594 continue;
10595
10596 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10597
10598 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10599 struct drm_property *dpms_property =
10600 dev->mode_config.dpms_property;
10601
10602 connector->dpms = DRM_MODE_DPMS_ON;
10603 drm_object_property_set_value(&connector->base,
10604 dpms_property,
10605 DRM_MODE_DPMS_ON);
10606
10607 intel_encoder = to_intel_encoder(connector->encoder);
10608 intel_encoder->connectors_active = true;
10609 }
10610 }
10611
10612 }
10613
10614 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10615 {
10616 int diff;
10617
10618 if (clock1 == clock2)
10619 return true;
10620
10621 if (!clock1 || !clock2)
10622 return false;
10623
10624 diff = abs(clock1 - clock2);
10625
10626 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10627 return true;
10628
10629 return false;
10630 }
10631
10632 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10633 list_for_each_entry((intel_crtc), \
10634 &(dev)->mode_config.crtc_list, \
10635 base.head) \
10636 if (mask & (1 <<(intel_crtc)->pipe))
10637
10638 static bool
10639 intel_pipe_config_compare(struct drm_device *dev,
10640 struct intel_crtc_config *current_config,
10641 struct intel_crtc_config *pipe_config)
10642 {
10643 #define PIPE_CONF_CHECK_X(name) \
10644 if (current_config->name != pipe_config->name) { \
10645 DRM_ERROR("mismatch in " #name " " \
10646 "(expected 0x%08x, found 0x%08x)\n", \
10647 current_config->name, \
10648 pipe_config->name); \
10649 return false; \
10650 }
10651
10652 #define PIPE_CONF_CHECK_I(name) \
10653 if (current_config->name != pipe_config->name) { \
10654 DRM_ERROR("mismatch in " #name " " \
10655 "(expected %i, found %i)\n", \
10656 current_config->name, \
10657 pipe_config->name); \
10658 return false; \
10659 }
10660
10661 /* This is required for BDW+ where there is only one set of registers for
10662 * switching between high and low RR.
10663 * This macro can be used whenever a comparison has to be made between one
10664 * hw state and multiple sw state variables.
10665 */
10666 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10667 if ((current_config->name != pipe_config->name) && \
10668 (current_config->alt_name != pipe_config->name)) { \
10669 DRM_ERROR("mismatch in " #name " " \
10670 "(expected %i or %i, found %i)\n", \
10671 current_config->name, \
10672 current_config->alt_name, \
10673 pipe_config->name); \
10674 return false; \
10675 }
10676
10677 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10678 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10679 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10680 "(expected %i, found %i)\n", \
10681 current_config->name & (mask), \
10682 pipe_config->name & (mask)); \
10683 return false; \
10684 }
10685
10686 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10687 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10688 DRM_ERROR("mismatch in " #name " " \
10689 "(expected %i, found %i)\n", \
10690 current_config->name, \
10691 pipe_config->name); \
10692 return false; \
10693 }
10694
10695 #define PIPE_CONF_QUIRK(quirk) \
10696 ((current_config->quirks | pipe_config->quirks) & (quirk))
10697
10698 PIPE_CONF_CHECK_I(cpu_transcoder);
10699
10700 PIPE_CONF_CHECK_I(has_pch_encoder);
10701 PIPE_CONF_CHECK_I(fdi_lanes);
10702 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10703 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10704 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10705 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10706 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10707
10708 PIPE_CONF_CHECK_I(has_dp_encoder);
10709
10710 if (INTEL_INFO(dev)->gen < 8) {
10711 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10712 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10713 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10714 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10715 PIPE_CONF_CHECK_I(dp_m_n.tu);
10716
10717 if (current_config->has_drrs) {
10718 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10719 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10720 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10721 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10722 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10723 }
10724 } else {
10725 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10726 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10727 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10728 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10729 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10730 }
10731
10732 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10733 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10734 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10735 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10736 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10737 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10738
10739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10742 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10743 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10744 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10745
10746 PIPE_CONF_CHECK_I(pixel_multiplier);
10747 PIPE_CONF_CHECK_I(has_hdmi_sink);
10748 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10749 IS_VALLEYVIEW(dev))
10750 PIPE_CONF_CHECK_I(limited_color_range);
10751
10752 PIPE_CONF_CHECK_I(has_audio);
10753
10754 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10755 DRM_MODE_FLAG_INTERLACE);
10756
10757 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10758 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10759 DRM_MODE_FLAG_PHSYNC);
10760 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10761 DRM_MODE_FLAG_NHSYNC);
10762 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10763 DRM_MODE_FLAG_PVSYNC);
10764 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10765 DRM_MODE_FLAG_NVSYNC);
10766 }
10767
10768 PIPE_CONF_CHECK_I(pipe_src_w);
10769 PIPE_CONF_CHECK_I(pipe_src_h);
10770
10771 /*
10772 * FIXME: BIOS likes to set up a cloned config with lvds+external
10773 * screen. Since we don't yet re-compute the pipe config when moving
10774 * just the lvds port away to another pipe the sw tracking won't match.
10775 *
10776 * Proper atomic modesets with recomputed global state will fix this.
10777 * Until then just don't check gmch state for inherited modes.
10778 */
10779 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10780 PIPE_CONF_CHECK_I(gmch_pfit.control);
10781 /* pfit ratios are autocomputed by the hw on gen4+ */
10782 if (INTEL_INFO(dev)->gen < 4)
10783 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10784 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10785 }
10786
10787 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10788 if (current_config->pch_pfit.enabled) {
10789 PIPE_CONF_CHECK_I(pch_pfit.pos);
10790 PIPE_CONF_CHECK_I(pch_pfit.size);
10791 }
10792
10793 /* BDW+ don't expose a synchronous way to read the state */
10794 if (IS_HASWELL(dev))
10795 PIPE_CONF_CHECK_I(ips_enabled);
10796
10797 PIPE_CONF_CHECK_I(double_wide);
10798
10799 PIPE_CONF_CHECK_X(ddi_pll_sel);
10800
10801 PIPE_CONF_CHECK_I(shared_dpll);
10802 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10803 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10804 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10805 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10806 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10807
10808 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10809 PIPE_CONF_CHECK_I(pipe_bpp);
10810
10811 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10812 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10813
10814 #undef PIPE_CONF_CHECK_X
10815 #undef PIPE_CONF_CHECK_I
10816 #undef PIPE_CONF_CHECK_I_ALT
10817 #undef PIPE_CONF_CHECK_FLAGS
10818 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10819 #undef PIPE_CONF_QUIRK
10820
10821 return true;
10822 }
10823
10824 static void
10825 check_connector_state(struct drm_device *dev)
10826 {
10827 struct intel_connector *connector;
10828
10829 list_for_each_entry(connector, &dev->mode_config.connector_list,
10830 base.head) {
10831 /* This also checks the encoder/connector hw state with the
10832 * ->get_hw_state callbacks. */
10833 intel_connector_check_state(connector);
10834
10835 WARN(&connector->new_encoder->base != connector->base.encoder,
10836 "connector's staged encoder doesn't match current encoder\n");
10837 }
10838 }
10839
10840 static void
10841 check_encoder_state(struct drm_device *dev)
10842 {
10843 struct intel_encoder *encoder;
10844 struct intel_connector *connector;
10845
10846 for_each_intel_encoder(dev, encoder) {
10847 bool enabled = false;
10848 bool active = false;
10849 enum pipe pipe, tracked_pipe;
10850
10851 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10852 encoder->base.base.id,
10853 encoder->base.name);
10854
10855 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10856 "encoder's stage crtc doesn't match current crtc\n");
10857 WARN(encoder->connectors_active && !encoder->base.crtc,
10858 "encoder's active_connectors set, but no crtc\n");
10859
10860 list_for_each_entry(connector, &dev->mode_config.connector_list,
10861 base.head) {
10862 if (connector->base.encoder != &encoder->base)
10863 continue;
10864 enabled = true;
10865 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10866 active = true;
10867 }
10868 /*
10869 * for MST connectors if we unplug the connector is gone
10870 * away but the encoder is still connected to a crtc
10871 * until a modeset happens in response to the hotplug.
10872 */
10873 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10874 continue;
10875
10876 WARN(!!encoder->base.crtc != enabled,
10877 "encoder's enabled state mismatch "
10878 "(expected %i, found %i)\n",
10879 !!encoder->base.crtc, enabled);
10880 WARN(active && !encoder->base.crtc,
10881 "active encoder with no crtc\n");
10882
10883 WARN(encoder->connectors_active != active,
10884 "encoder's computed active state doesn't match tracked active state "
10885 "(expected %i, found %i)\n", active, encoder->connectors_active);
10886
10887 active = encoder->get_hw_state(encoder, &pipe);
10888 WARN(active != encoder->connectors_active,
10889 "encoder's hw state doesn't match sw tracking "
10890 "(expected %i, found %i)\n",
10891 encoder->connectors_active, active);
10892
10893 if (!encoder->base.crtc)
10894 continue;
10895
10896 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10897 WARN(active && pipe != tracked_pipe,
10898 "active encoder's pipe doesn't match"
10899 "(expected %i, found %i)\n",
10900 tracked_pipe, pipe);
10901
10902 }
10903 }
10904
10905 static void
10906 check_crtc_state(struct drm_device *dev)
10907 {
10908 struct drm_i915_private *dev_priv = dev->dev_private;
10909 struct intel_crtc *crtc;
10910 struct intel_encoder *encoder;
10911 struct intel_crtc_config pipe_config;
10912
10913 for_each_intel_crtc(dev, crtc) {
10914 bool enabled = false;
10915 bool active = false;
10916
10917 memset(&pipe_config, 0, sizeof(pipe_config));
10918
10919 DRM_DEBUG_KMS("[CRTC:%d]\n",
10920 crtc->base.base.id);
10921
10922 WARN(crtc->active && !crtc->base.enabled,
10923 "active crtc, but not enabled in sw tracking\n");
10924
10925 for_each_intel_encoder(dev, encoder) {
10926 if (encoder->base.crtc != &crtc->base)
10927 continue;
10928 enabled = true;
10929 if (encoder->connectors_active)
10930 active = true;
10931 }
10932
10933 WARN(active != crtc->active,
10934 "crtc's computed active state doesn't match tracked active state "
10935 "(expected %i, found %i)\n", active, crtc->active);
10936 WARN(enabled != crtc->base.enabled,
10937 "crtc's computed enabled state doesn't match tracked enabled state "
10938 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10939
10940 active = dev_priv->display.get_pipe_config(crtc,
10941 &pipe_config);
10942
10943 /* hw state is inconsistent with the pipe quirk */
10944 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10945 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10946 active = crtc->active;
10947
10948 for_each_intel_encoder(dev, encoder) {
10949 enum pipe pipe;
10950 if (encoder->base.crtc != &crtc->base)
10951 continue;
10952 if (encoder->get_hw_state(encoder, &pipe))
10953 encoder->get_config(encoder, &pipe_config);
10954 }
10955
10956 WARN(crtc->active != active,
10957 "crtc active state doesn't match with hw state "
10958 "(expected %i, found %i)\n", crtc->active, active);
10959
10960 if (active &&
10961 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10962 WARN(1, "pipe state doesn't match!\n");
10963 intel_dump_pipe_config(crtc, &pipe_config,
10964 "[hw state]");
10965 intel_dump_pipe_config(crtc, &crtc->config,
10966 "[sw state]");
10967 }
10968 }
10969 }
10970
10971 static void
10972 check_shared_dpll_state(struct drm_device *dev)
10973 {
10974 struct drm_i915_private *dev_priv = dev->dev_private;
10975 struct intel_crtc *crtc;
10976 struct intel_dpll_hw_state dpll_hw_state;
10977 int i;
10978
10979 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10980 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10981 int enabled_crtcs = 0, active_crtcs = 0;
10982 bool active;
10983
10984 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10985
10986 DRM_DEBUG_KMS("%s\n", pll->name);
10987
10988 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10989
10990 WARN(pll->active > pll->refcount,
10991 "more active pll users than references: %i vs %i\n",
10992 pll->active, pll->refcount);
10993 WARN(pll->active && !pll->on,
10994 "pll in active use but not on in sw tracking\n");
10995 WARN(pll->on && !pll->active,
10996 "pll in on but not on in use in sw tracking\n");
10997 WARN(pll->on != active,
10998 "pll on state mismatch (expected %i, found %i)\n",
10999 pll->on, active);
11000
11001 for_each_intel_crtc(dev, crtc) {
11002 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11003 enabled_crtcs++;
11004 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11005 active_crtcs++;
11006 }
11007 WARN(pll->active != active_crtcs,
11008 "pll active crtcs mismatch (expected %i, found %i)\n",
11009 pll->active, active_crtcs);
11010 WARN(pll->refcount != enabled_crtcs,
11011 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11012 pll->refcount, enabled_crtcs);
11013
11014 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11015 sizeof(dpll_hw_state)),
11016 "pll hw state mismatch\n");
11017 }
11018 }
11019
11020 void
11021 intel_modeset_check_state(struct drm_device *dev)
11022 {
11023 check_connector_state(dev);
11024 check_encoder_state(dev);
11025 check_crtc_state(dev);
11026 check_shared_dpll_state(dev);
11027 }
11028
11029 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11030 int dotclock)
11031 {
11032 /*
11033 * FDI already provided one idea for the dotclock.
11034 * Yell if the encoder disagrees.
11035 */
11036 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11037 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11038 pipe_config->adjusted_mode.crtc_clock, dotclock);
11039 }
11040
11041 static void update_scanline_offset(struct intel_crtc *crtc)
11042 {
11043 struct drm_device *dev = crtc->base.dev;
11044
11045 /*
11046 * The scanline counter increments at the leading edge of hsync.
11047 *
11048 * On most platforms it starts counting from vtotal-1 on the
11049 * first active line. That means the scanline counter value is
11050 * always one less than what we would expect. Ie. just after
11051 * start of vblank, which also occurs at start of hsync (on the
11052 * last active line), the scanline counter will read vblank_start-1.
11053 *
11054 * On gen2 the scanline counter starts counting from 1 instead
11055 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11056 * to keep the value positive), instead of adding one.
11057 *
11058 * On HSW+ the behaviour of the scanline counter depends on the output
11059 * type. For DP ports it behaves like most other platforms, but on HDMI
11060 * there's an extra 1 line difference. So we need to add two instead of
11061 * one to the value.
11062 */
11063 if (IS_GEN2(dev)) {
11064 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11065 int vtotal;
11066
11067 vtotal = mode->crtc_vtotal;
11068 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11069 vtotal /= 2;
11070
11071 crtc->scanline_offset = vtotal - 1;
11072 } else if (HAS_DDI(dev) &&
11073 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11074 crtc->scanline_offset = 2;
11075 } else
11076 crtc->scanline_offset = 1;
11077 }
11078
11079 static int __intel_set_mode(struct drm_crtc *crtc,
11080 struct drm_display_mode *mode,
11081 int x, int y, struct drm_framebuffer *fb)
11082 {
11083 struct drm_device *dev = crtc->dev;
11084 struct drm_i915_private *dev_priv = dev->dev_private;
11085 struct drm_display_mode *saved_mode;
11086 struct intel_crtc_config *pipe_config = NULL;
11087 struct intel_crtc *intel_crtc;
11088 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11089 int ret = 0;
11090
11091 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11092 if (!saved_mode)
11093 return -ENOMEM;
11094
11095 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11096 &prepare_pipes, &disable_pipes);
11097
11098 *saved_mode = crtc->mode;
11099
11100 /* Hack: Because we don't (yet) support global modeset on multiple
11101 * crtcs, we don't keep track of the new mode for more than one crtc.
11102 * Hence simply check whether any bit is set in modeset_pipes in all the
11103 * pieces of code that are not yet converted to deal with mutliple crtcs
11104 * changing their mode at the same time. */
11105 if (modeset_pipes) {
11106 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11107 if (IS_ERR(pipe_config)) {
11108 ret = PTR_ERR(pipe_config);
11109 pipe_config = NULL;
11110
11111 goto out;
11112 }
11113 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11114 "[modeset]");
11115 to_intel_crtc(crtc)->new_config = pipe_config;
11116 }
11117
11118 /*
11119 * See if the config requires any additional preparation, e.g.
11120 * to adjust global state with pipes off. We need to do this
11121 * here so we can get the modeset_pipe updated config for the new
11122 * mode set on this crtc. For other crtcs we need to use the
11123 * adjusted_mode bits in the crtc directly.
11124 */
11125 if (IS_VALLEYVIEW(dev)) {
11126 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11127
11128 /* may have added more to prepare_pipes than we should */
11129 prepare_pipes &= ~disable_pipes;
11130 }
11131
11132 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11133 intel_crtc_disable(&intel_crtc->base);
11134
11135 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11136 if (intel_crtc->base.enabled)
11137 dev_priv->display.crtc_disable(&intel_crtc->base);
11138 }
11139
11140 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11141 * to set it here already despite that we pass it down the callchain.
11142 */
11143 if (modeset_pipes) {
11144 crtc->mode = *mode;
11145 /* mode_set/enable/disable functions rely on a correct pipe
11146 * config. */
11147 to_intel_crtc(crtc)->config = *pipe_config;
11148 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11149
11150 /*
11151 * Calculate and store various constants which
11152 * are later needed by vblank and swap-completion
11153 * timestamping. They are derived from true hwmode.
11154 */
11155 drm_calc_timestamping_constants(crtc,
11156 &pipe_config->adjusted_mode);
11157 }
11158
11159 /* Only after disabling all output pipelines that will be changed can we
11160 * update the the output configuration. */
11161 intel_modeset_update_state(dev, prepare_pipes);
11162
11163 if (dev_priv->display.modeset_global_resources)
11164 dev_priv->display.modeset_global_resources(dev);
11165
11166 /* Set up the DPLL and any encoders state that needs to adjust or depend
11167 * on the DPLL.
11168 */
11169 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11170 struct drm_framebuffer *old_fb = crtc->primary->fb;
11171 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11172 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11173
11174 mutex_lock(&dev->struct_mutex);
11175 ret = intel_pin_and_fence_fb_obj(dev,
11176 obj,
11177 NULL);
11178 if (ret != 0) {
11179 DRM_ERROR("pin & fence failed\n");
11180 mutex_unlock(&dev->struct_mutex);
11181 goto done;
11182 }
11183 if (old_fb)
11184 intel_unpin_fb_obj(old_obj);
11185 i915_gem_track_fb(old_obj, obj,
11186 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11187 mutex_unlock(&dev->struct_mutex);
11188
11189 crtc->primary->fb = fb;
11190 crtc->x = x;
11191 crtc->y = y;
11192
11193 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11194 x, y, fb);
11195 if (ret)
11196 goto done;
11197 }
11198
11199 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11200 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11201 update_scanline_offset(intel_crtc);
11202
11203 dev_priv->display.crtc_enable(&intel_crtc->base);
11204 }
11205
11206 /* FIXME: add subpixel order */
11207 done:
11208 if (ret && crtc->enabled)
11209 crtc->mode = *saved_mode;
11210
11211 out:
11212 kfree(pipe_config);
11213 kfree(saved_mode);
11214 return ret;
11215 }
11216
11217 static int intel_set_mode(struct drm_crtc *crtc,
11218 struct drm_display_mode *mode,
11219 int x, int y, struct drm_framebuffer *fb)
11220 {
11221 int ret;
11222
11223 ret = __intel_set_mode(crtc, mode, x, y, fb);
11224
11225 if (ret == 0)
11226 intel_modeset_check_state(crtc->dev);
11227
11228 return ret;
11229 }
11230
11231 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11232 {
11233 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11234 }
11235
11236 #undef for_each_intel_crtc_masked
11237
11238 static void intel_set_config_free(struct intel_set_config *config)
11239 {
11240 if (!config)
11241 return;
11242
11243 kfree(config->save_connector_encoders);
11244 kfree(config->save_encoder_crtcs);
11245 kfree(config->save_crtc_enabled);
11246 kfree(config);
11247 }
11248
11249 static int intel_set_config_save_state(struct drm_device *dev,
11250 struct intel_set_config *config)
11251 {
11252 struct drm_crtc *crtc;
11253 struct drm_encoder *encoder;
11254 struct drm_connector *connector;
11255 int count;
11256
11257 config->save_crtc_enabled =
11258 kcalloc(dev->mode_config.num_crtc,
11259 sizeof(bool), GFP_KERNEL);
11260 if (!config->save_crtc_enabled)
11261 return -ENOMEM;
11262
11263 config->save_encoder_crtcs =
11264 kcalloc(dev->mode_config.num_encoder,
11265 sizeof(struct drm_crtc *), GFP_KERNEL);
11266 if (!config->save_encoder_crtcs)
11267 return -ENOMEM;
11268
11269 config->save_connector_encoders =
11270 kcalloc(dev->mode_config.num_connector,
11271 sizeof(struct drm_encoder *), GFP_KERNEL);
11272 if (!config->save_connector_encoders)
11273 return -ENOMEM;
11274
11275 /* Copy data. Note that driver private data is not affected.
11276 * Should anything bad happen only the expected state is
11277 * restored, not the drivers personal bookkeeping.
11278 */
11279 count = 0;
11280 for_each_crtc(dev, crtc) {
11281 config->save_crtc_enabled[count++] = crtc->enabled;
11282 }
11283
11284 count = 0;
11285 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11286 config->save_encoder_crtcs[count++] = encoder->crtc;
11287 }
11288
11289 count = 0;
11290 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11291 config->save_connector_encoders[count++] = connector->encoder;
11292 }
11293
11294 return 0;
11295 }
11296
11297 static void intel_set_config_restore_state(struct drm_device *dev,
11298 struct intel_set_config *config)
11299 {
11300 struct intel_crtc *crtc;
11301 struct intel_encoder *encoder;
11302 struct intel_connector *connector;
11303 int count;
11304
11305 count = 0;
11306 for_each_intel_crtc(dev, crtc) {
11307 crtc->new_enabled = config->save_crtc_enabled[count++];
11308
11309 if (crtc->new_enabled)
11310 crtc->new_config = &crtc->config;
11311 else
11312 crtc->new_config = NULL;
11313 }
11314
11315 count = 0;
11316 for_each_intel_encoder(dev, encoder) {
11317 encoder->new_crtc =
11318 to_intel_crtc(config->save_encoder_crtcs[count++]);
11319 }
11320
11321 count = 0;
11322 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11323 connector->new_encoder =
11324 to_intel_encoder(config->save_connector_encoders[count++]);
11325 }
11326 }
11327
11328 static bool
11329 is_crtc_connector_off(struct drm_mode_set *set)
11330 {
11331 int i;
11332
11333 if (set->num_connectors == 0)
11334 return false;
11335
11336 if (WARN_ON(set->connectors == NULL))
11337 return false;
11338
11339 for (i = 0; i < set->num_connectors; i++)
11340 if (set->connectors[i]->encoder &&
11341 set->connectors[i]->encoder->crtc == set->crtc &&
11342 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11343 return true;
11344
11345 return false;
11346 }
11347
11348 static void
11349 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11350 struct intel_set_config *config)
11351 {
11352
11353 /* We should be able to check here if the fb has the same properties
11354 * and then just flip_or_move it */
11355 if (is_crtc_connector_off(set)) {
11356 config->mode_changed = true;
11357 } else if (set->crtc->primary->fb != set->fb) {
11358 /*
11359 * If we have no fb, we can only flip as long as the crtc is
11360 * active, otherwise we need a full mode set. The crtc may
11361 * be active if we've only disabled the primary plane, or
11362 * in fastboot situations.
11363 */
11364 if (set->crtc->primary->fb == NULL) {
11365 struct intel_crtc *intel_crtc =
11366 to_intel_crtc(set->crtc);
11367
11368 if (intel_crtc->active) {
11369 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11370 config->fb_changed = true;
11371 } else {
11372 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11373 config->mode_changed = true;
11374 }
11375 } else if (set->fb == NULL) {
11376 config->mode_changed = true;
11377 } else if (set->fb->pixel_format !=
11378 set->crtc->primary->fb->pixel_format) {
11379 config->mode_changed = true;
11380 } else {
11381 config->fb_changed = true;
11382 }
11383 }
11384
11385 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11386 config->fb_changed = true;
11387
11388 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11389 DRM_DEBUG_KMS("modes are different, full mode set\n");
11390 drm_mode_debug_printmodeline(&set->crtc->mode);
11391 drm_mode_debug_printmodeline(set->mode);
11392 config->mode_changed = true;
11393 }
11394
11395 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11396 set->crtc->base.id, config->mode_changed, config->fb_changed);
11397 }
11398
11399 static int
11400 intel_modeset_stage_output_state(struct drm_device *dev,
11401 struct drm_mode_set *set,
11402 struct intel_set_config *config)
11403 {
11404 struct intel_connector *connector;
11405 struct intel_encoder *encoder;
11406 struct intel_crtc *crtc;
11407 int ro;
11408
11409 /* The upper layers ensure that we either disable a crtc or have a list
11410 * of connectors. For paranoia, double-check this. */
11411 WARN_ON(!set->fb && (set->num_connectors != 0));
11412 WARN_ON(set->fb && (set->num_connectors == 0));
11413
11414 list_for_each_entry(connector, &dev->mode_config.connector_list,
11415 base.head) {
11416 /* Otherwise traverse passed in connector list and get encoders
11417 * for them. */
11418 for (ro = 0; ro < set->num_connectors; ro++) {
11419 if (set->connectors[ro] == &connector->base) {
11420 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11421 break;
11422 }
11423 }
11424
11425 /* If we disable the crtc, disable all its connectors. Also, if
11426 * the connector is on the changing crtc but not on the new
11427 * connector list, disable it. */
11428 if ((!set->fb || ro == set->num_connectors) &&
11429 connector->base.encoder &&
11430 connector->base.encoder->crtc == set->crtc) {
11431 connector->new_encoder = NULL;
11432
11433 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11434 connector->base.base.id,
11435 connector->base.name);
11436 }
11437
11438
11439 if (&connector->new_encoder->base != connector->base.encoder) {
11440 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11441 config->mode_changed = true;
11442 }
11443 }
11444 /* connector->new_encoder is now updated for all connectors. */
11445
11446 /* Update crtc of enabled connectors. */
11447 list_for_each_entry(connector, &dev->mode_config.connector_list,
11448 base.head) {
11449 struct drm_crtc *new_crtc;
11450
11451 if (!connector->new_encoder)
11452 continue;
11453
11454 new_crtc = connector->new_encoder->base.crtc;
11455
11456 for (ro = 0; ro < set->num_connectors; ro++) {
11457 if (set->connectors[ro] == &connector->base)
11458 new_crtc = set->crtc;
11459 }
11460
11461 /* Make sure the new CRTC will work with the encoder */
11462 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11463 new_crtc)) {
11464 return -EINVAL;
11465 }
11466 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11467
11468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11469 connector->base.base.id,
11470 connector->base.name,
11471 new_crtc->base.id);
11472 }
11473
11474 /* Check for any encoders that needs to be disabled. */
11475 for_each_intel_encoder(dev, encoder) {
11476 int num_connectors = 0;
11477 list_for_each_entry(connector,
11478 &dev->mode_config.connector_list,
11479 base.head) {
11480 if (connector->new_encoder == encoder) {
11481 WARN_ON(!connector->new_encoder->new_crtc);
11482 num_connectors++;
11483 }
11484 }
11485
11486 if (num_connectors == 0)
11487 encoder->new_crtc = NULL;
11488 else if (num_connectors > 1)
11489 return -EINVAL;
11490
11491 /* Only now check for crtc changes so we don't miss encoders
11492 * that will be disabled. */
11493 if (&encoder->new_crtc->base != encoder->base.crtc) {
11494 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11495 config->mode_changed = true;
11496 }
11497 }
11498 /* Now we've also updated encoder->new_crtc for all encoders. */
11499 list_for_each_entry(connector, &dev->mode_config.connector_list,
11500 base.head) {
11501 if (connector->new_encoder)
11502 if (connector->new_encoder != connector->encoder)
11503 connector->encoder = connector->new_encoder;
11504 }
11505 for_each_intel_crtc(dev, crtc) {
11506 crtc->new_enabled = false;
11507
11508 for_each_intel_encoder(dev, encoder) {
11509 if (encoder->new_crtc == crtc) {
11510 crtc->new_enabled = true;
11511 break;
11512 }
11513 }
11514
11515 if (crtc->new_enabled != crtc->base.enabled) {
11516 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11517 crtc->new_enabled ? "en" : "dis");
11518 config->mode_changed = true;
11519 }
11520
11521 if (crtc->new_enabled)
11522 crtc->new_config = &crtc->config;
11523 else
11524 crtc->new_config = NULL;
11525 }
11526
11527 return 0;
11528 }
11529
11530 static void disable_crtc_nofb(struct intel_crtc *crtc)
11531 {
11532 struct drm_device *dev = crtc->base.dev;
11533 struct intel_encoder *encoder;
11534 struct intel_connector *connector;
11535
11536 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11537 pipe_name(crtc->pipe));
11538
11539 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11540 if (connector->new_encoder &&
11541 connector->new_encoder->new_crtc == crtc)
11542 connector->new_encoder = NULL;
11543 }
11544
11545 for_each_intel_encoder(dev, encoder) {
11546 if (encoder->new_crtc == crtc)
11547 encoder->new_crtc = NULL;
11548 }
11549
11550 crtc->new_enabled = false;
11551 crtc->new_config = NULL;
11552 }
11553
11554 static int intel_crtc_set_config(struct drm_mode_set *set)
11555 {
11556 struct drm_device *dev;
11557 struct drm_mode_set save_set;
11558 struct intel_set_config *config;
11559 int ret;
11560
11561 BUG_ON(!set);
11562 BUG_ON(!set->crtc);
11563 BUG_ON(!set->crtc->helper_private);
11564
11565 /* Enforce sane interface api - has been abused by the fb helper. */
11566 BUG_ON(!set->mode && set->fb);
11567 BUG_ON(set->fb && set->num_connectors == 0);
11568
11569 if (set->fb) {
11570 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11571 set->crtc->base.id, set->fb->base.id,
11572 (int)set->num_connectors, set->x, set->y);
11573 } else {
11574 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11575 }
11576
11577 dev = set->crtc->dev;
11578
11579 ret = -ENOMEM;
11580 config = kzalloc(sizeof(*config), GFP_KERNEL);
11581 if (!config)
11582 goto out_config;
11583
11584 ret = intel_set_config_save_state(dev, config);
11585 if (ret)
11586 goto out_config;
11587
11588 save_set.crtc = set->crtc;
11589 save_set.mode = &set->crtc->mode;
11590 save_set.x = set->crtc->x;
11591 save_set.y = set->crtc->y;
11592 save_set.fb = set->crtc->primary->fb;
11593
11594 /* Compute whether we need a full modeset, only an fb base update or no
11595 * change at all. In the future we might also check whether only the
11596 * mode changed, e.g. for LVDS where we only change the panel fitter in
11597 * such cases. */
11598 intel_set_config_compute_mode_changes(set, config);
11599
11600 ret = intel_modeset_stage_output_state(dev, set, config);
11601 if (ret)
11602 goto fail;
11603
11604 if (config->mode_changed) {
11605 ret = intel_set_mode(set->crtc, set->mode,
11606 set->x, set->y, set->fb);
11607 } else if (config->fb_changed) {
11608 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11609
11610 intel_crtc_wait_for_pending_flips(set->crtc);
11611
11612 ret = intel_pipe_set_base(set->crtc,
11613 set->x, set->y, set->fb);
11614
11615 /*
11616 * We need to make sure the primary plane is re-enabled if it
11617 * has previously been turned off.
11618 */
11619 if (!intel_crtc->primary_enabled && ret == 0) {
11620 WARN_ON(!intel_crtc->active);
11621 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11622 }
11623
11624 /*
11625 * In the fastboot case this may be our only check of the
11626 * state after boot. It would be better to only do it on
11627 * the first update, but we don't have a nice way of doing that
11628 * (and really, set_config isn't used much for high freq page
11629 * flipping, so increasing its cost here shouldn't be a big
11630 * deal).
11631 */
11632 if (i915.fastboot && ret == 0)
11633 intel_modeset_check_state(set->crtc->dev);
11634 }
11635
11636 if (ret) {
11637 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11638 set->crtc->base.id, ret);
11639 fail:
11640 intel_set_config_restore_state(dev, config);
11641
11642 /*
11643 * HACK: if the pipe was on, but we didn't have a framebuffer,
11644 * force the pipe off to avoid oopsing in the modeset code
11645 * due to fb==NULL. This should only happen during boot since
11646 * we don't yet reconstruct the FB from the hardware state.
11647 */
11648 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11649 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11650
11651 /* Try to restore the config */
11652 if (config->mode_changed &&
11653 intel_set_mode(save_set.crtc, save_set.mode,
11654 save_set.x, save_set.y, save_set.fb))
11655 DRM_ERROR("failed to restore config after modeset failure\n");
11656 }
11657
11658 out_config:
11659 intel_set_config_free(config);
11660 return ret;
11661 }
11662
11663 static const struct drm_crtc_funcs intel_crtc_funcs = {
11664 .gamma_set = intel_crtc_gamma_set,
11665 .set_config = intel_crtc_set_config,
11666 .destroy = intel_crtc_destroy,
11667 .page_flip = intel_crtc_page_flip,
11668 };
11669
11670 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11671 struct intel_shared_dpll *pll,
11672 struct intel_dpll_hw_state *hw_state)
11673 {
11674 uint32_t val;
11675
11676 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11677 return false;
11678
11679 val = I915_READ(PCH_DPLL(pll->id));
11680 hw_state->dpll = val;
11681 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11682 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11683
11684 return val & DPLL_VCO_ENABLE;
11685 }
11686
11687 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11688 struct intel_shared_dpll *pll)
11689 {
11690 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11691 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11692 }
11693
11694 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11695 struct intel_shared_dpll *pll)
11696 {
11697 /* PCH refclock must be enabled first */
11698 ibx_assert_pch_refclk_enabled(dev_priv);
11699
11700 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11701
11702 /* Wait for the clocks to stabilize. */
11703 POSTING_READ(PCH_DPLL(pll->id));
11704 udelay(150);
11705
11706 /* The pixel multiplier can only be updated once the
11707 * DPLL is enabled and the clocks are stable.
11708 *
11709 * So write it again.
11710 */
11711 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11712 POSTING_READ(PCH_DPLL(pll->id));
11713 udelay(200);
11714 }
11715
11716 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11717 struct intel_shared_dpll *pll)
11718 {
11719 struct drm_device *dev = dev_priv->dev;
11720 struct intel_crtc *crtc;
11721
11722 /* Make sure no transcoder isn't still depending on us. */
11723 for_each_intel_crtc(dev, crtc) {
11724 if (intel_crtc_to_shared_dpll(crtc) == pll)
11725 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11726 }
11727
11728 I915_WRITE(PCH_DPLL(pll->id), 0);
11729 POSTING_READ(PCH_DPLL(pll->id));
11730 udelay(200);
11731 }
11732
11733 static char *ibx_pch_dpll_names[] = {
11734 "PCH DPLL A",
11735 "PCH DPLL B",
11736 };
11737
11738 static void ibx_pch_dpll_init(struct drm_device *dev)
11739 {
11740 struct drm_i915_private *dev_priv = dev->dev_private;
11741 int i;
11742
11743 dev_priv->num_shared_dpll = 2;
11744
11745 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11746 dev_priv->shared_dplls[i].id = i;
11747 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11748 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11749 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11750 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11751 dev_priv->shared_dplls[i].get_hw_state =
11752 ibx_pch_dpll_get_hw_state;
11753 }
11754 }
11755
11756 static void intel_shared_dpll_init(struct drm_device *dev)
11757 {
11758 struct drm_i915_private *dev_priv = dev->dev_private;
11759
11760 if (HAS_DDI(dev))
11761 intel_ddi_pll_init(dev);
11762 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11763 ibx_pch_dpll_init(dev);
11764 else
11765 dev_priv->num_shared_dpll = 0;
11766
11767 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11768 }
11769
11770 static int
11771 intel_primary_plane_disable(struct drm_plane *plane)
11772 {
11773 struct drm_device *dev = plane->dev;
11774 struct intel_crtc *intel_crtc;
11775
11776 if (!plane->fb)
11777 return 0;
11778
11779 BUG_ON(!plane->crtc);
11780
11781 intel_crtc = to_intel_crtc(plane->crtc);
11782
11783 /*
11784 * Even though we checked plane->fb above, it's still possible that
11785 * the primary plane has been implicitly disabled because the crtc
11786 * coordinates given weren't visible, or because we detected
11787 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11788 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11789 * In either case, we need to unpin the FB and let the fb pointer get
11790 * updated, but otherwise we don't need to touch the hardware.
11791 */
11792 if (!intel_crtc->primary_enabled)
11793 goto disable_unpin;
11794
11795 intel_crtc_wait_for_pending_flips(plane->crtc);
11796 intel_disable_primary_hw_plane(plane, plane->crtc);
11797
11798 disable_unpin:
11799 mutex_lock(&dev->struct_mutex);
11800 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11801 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11802 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11803 mutex_unlock(&dev->struct_mutex);
11804 plane->fb = NULL;
11805
11806 return 0;
11807 }
11808
11809 static int
11810 intel_check_primary_plane(struct drm_plane *plane,
11811 struct intel_plane_state *state)
11812 {
11813 struct drm_crtc *crtc = state->crtc;
11814 struct drm_framebuffer *fb = state->fb;
11815 struct drm_rect *dest = &state->dst;
11816 struct drm_rect *src = &state->src;
11817 const struct drm_rect *clip = &state->clip;
11818
11819 return drm_plane_helper_check_update(plane, crtc, fb,
11820 src, dest, clip,
11821 DRM_PLANE_HELPER_NO_SCALING,
11822 DRM_PLANE_HELPER_NO_SCALING,
11823 false, true, &state->visible);
11824 }
11825
11826 static int
11827 intel_commit_primary_plane(struct drm_plane *plane,
11828 struct intel_plane_state *state)
11829 {
11830 struct drm_crtc *crtc = state->crtc;
11831 struct drm_framebuffer *fb = state->fb;
11832 struct drm_device *dev = crtc->dev;
11833 struct drm_i915_private *dev_priv = dev->dev_private;
11834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11835 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11836 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11837 struct intel_plane *intel_plane = to_intel_plane(plane);
11838 struct drm_rect *src = &state->src;
11839 int ret;
11840
11841 intel_crtc_wait_for_pending_flips(crtc);
11842
11843 /*
11844 * If clipping results in a non-visible primary plane, we'll disable
11845 * the primary plane. Note that this is a bit different than what
11846 * happens if userspace explicitly disables the plane by passing fb=0
11847 * because plane->fb still gets set and pinned.
11848 */
11849 if (!state->visible) {
11850 mutex_lock(&dev->struct_mutex);
11851
11852 /*
11853 * Try to pin the new fb first so that we can bail out if we
11854 * fail.
11855 */
11856 if (plane->fb != fb) {
11857 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11858 if (ret) {
11859 mutex_unlock(&dev->struct_mutex);
11860 return ret;
11861 }
11862 }
11863
11864 i915_gem_track_fb(old_obj, obj,
11865 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11866
11867 if (intel_crtc->primary_enabled)
11868 intel_disable_primary_hw_plane(plane, crtc);
11869
11870
11871 if (plane->fb != fb)
11872 if (plane->fb)
11873 intel_unpin_fb_obj(old_obj);
11874
11875 mutex_unlock(&dev->struct_mutex);
11876
11877 } else {
11878 if (intel_crtc && intel_crtc->active &&
11879 intel_crtc->primary_enabled) {
11880 /*
11881 * FBC does not work on some platforms for rotated
11882 * planes, so disable it when rotation is not 0 and
11883 * update it when rotation is set back to 0.
11884 *
11885 * FIXME: This is redundant with the fbc update done in
11886 * the primary plane enable function except that that
11887 * one is done too late. We eventually need to unify
11888 * this.
11889 */
11890 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11891 dev_priv->fbc.plane == intel_crtc->plane &&
11892 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11893 intel_disable_fbc(dev);
11894 }
11895 }
11896 ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb);
11897 if (ret)
11898 return ret;
11899
11900 if (!intel_crtc->primary_enabled)
11901 intel_enable_primary_hw_plane(plane, crtc);
11902 }
11903
11904 intel_plane->crtc_x = state->orig_dst.x1;
11905 intel_plane->crtc_y = state->orig_dst.y1;
11906 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11907 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11908 intel_plane->src_x = state->orig_src.x1;
11909 intel_plane->src_y = state->orig_src.y1;
11910 intel_plane->src_w = drm_rect_width(&state->orig_src);
11911 intel_plane->src_h = drm_rect_height(&state->orig_src);
11912 intel_plane->obj = obj;
11913
11914 return 0;
11915 }
11916
11917 static int
11918 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11919 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11920 unsigned int crtc_w, unsigned int crtc_h,
11921 uint32_t src_x, uint32_t src_y,
11922 uint32_t src_w, uint32_t src_h)
11923 {
11924 struct intel_plane_state state;
11925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11926 int ret;
11927
11928 state.crtc = crtc;
11929 state.fb = fb;
11930
11931 /* sample coordinates in 16.16 fixed point */
11932 state.src.x1 = src_x;
11933 state.src.x2 = src_x + src_w;
11934 state.src.y1 = src_y;
11935 state.src.y2 = src_y + src_h;
11936
11937 /* integer pixels */
11938 state.dst.x1 = crtc_x;
11939 state.dst.x2 = crtc_x + crtc_w;
11940 state.dst.y1 = crtc_y;
11941 state.dst.y2 = crtc_y + crtc_h;
11942
11943 state.clip.x1 = 0;
11944 state.clip.y1 = 0;
11945 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11946 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11947
11948 state.orig_src = state.src;
11949 state.orig_dst = state.dst;
11950
11951 ret = intel_check_primary_plane(plane, &state);
11952 if (ret)
11953 return ret;
11954
11955 intel_commit_primary_plane(plane, &state);
11956
11957 return 0;
11958 }
11959
11960 /* Common destruction function for both primary and cursor planes */
11961 static void intel_plane_destroy(struct drm_plane *plane)
11962 {
11963 struct intel_plane *intel_plane = to_intel_plane(plane);
11964 drm_plane_cleanup(plane);
11965 kfree(intel_plane);
11966 }
11967
11968 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11969 .update_plane = intel_primary_plane_setplane,
11970 .disable_plane = intel_primary_plane_disable,
11971 .destroy = intel_plane_destroy,
11972 .set_property = intel_plane_set_property
11973 };
11974
11975 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11976 int pipe)
11977 {
11978 struct intel_plane *primary;
11979 const uint32_t *intel_primary_formats;
11980 int num_formats;
11981
11982 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11983 if (primary == NULL)
11984 return NULL;
11985
11986 primary->can_scale = false;
11987 primary->max_downscale = 1;
11988 primary->pipe = pipe;
11989 primary->plane = pipe;
11990 primary->rotation = BIT(DRM_ROTATE_0);
11991 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11992 primary->plane = !pipe;
11993
11994 if (INTEL_INFO(dev)->gen <= 3) {
11995 intel_primary_formats = intel_primary_formats_gen2;
11996 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11997 } else {
11998 intel_primary_formats = intel_primary_formats_gen4;
11999 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12000 }
12001
12002 drm_universal_plane_init(dev, &primary->base, 0,
12003 &intel_primary_plane_funcs,
12004 intel_primary_formats, num_formats,
12005 DRM_PLANE_TYPE_PRIMARY);
12006
12007 if (INTEL_INFO(dev)->gen >= 4) {
12008 if (!dev->mode_config.rotation_property)
12009 dev->mode_config.rotation_property =
12010 drm_mode_create_rotation_property(dev,
12011 BIT(DRM_ROTATE_0) |
12012 BIT(DRM_ROTATE_180));
12013 if (dev->mode_config.rotation_property)
12014 drm_object_attach_property(&primary->base.base,
12015 dev->mode_config.rotation_property,
12016 primary->rotation);
12017 }
12018
12019 return &primary->base;
12020 }
12021
12022 static int
12023 intel_cursor_plane_disable(struct drm_plane *plane)
12024 {
12025 if (!plane->fb)
12026 return 0;
12027
12028 BUG_ON(!plane->crtc);
12029
12030 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12031 }
12032
12033 static int
12034 intel_check_cursor_plane(struct drm_plane *plane,
12035 struct intel_plane_state *state)
12036 {
12037 struct drm_crtc *crtc = state->crtc;
12038 struct drm_framebuffer *fb = state->fb;
12039 struct drm_rect *dest = &state->dst;
12040 struct drm_rect *src = &state->src;
12041 const struct drm_rect *clip = &state->clip;
12042
12043 return drm_plane_helper_check_update(plane, crtc, fb,
12044 src, dest, clip,
12045 DRM_PLANE_HELPER_NO_SCALING,
12046 DRM_PLANE_HELPER_NO_SCALING,
12047 true, true, &state->visible);
12048 }
12049
12050 static int
12051 intel_commit_cursor_plane(struct drm_plane *plane,
12052 struct intel_plane_state *state)
12053 {
12054 struct drm_crtc *crtc = state->crtc;
12055 struct drm_framebuffer *fb = state->fb;
12056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12057 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12058 struct drm_i915_gem_object *obj = intel_fb->obj;
12059 int crtc_w, crtc_h;
12060
12061 crtc->cursor_x = state->orig_dst.x1;
12062 crtc->cursor_y = state->orig_dst.y1;
12063 if (fb != crtc->cursor->fb) {
12064 crtc_w = drm_rect_width(&state->orig_dst);
12065 crtc_h = drm_rect_height(&state->orig_dst);
12066 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12067 } else {
12068 intel_crtc_update_cursor(crtc, state->visible);
12069
12070 intel_frontbuffer_flip(crtc->dev,
12071 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12072
12073 return 0;
12074 }
12075 }
12076
12077 static int
12078 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12079 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12080 unsigned int crtc_w, unsigned int crtc_h,
12081 uint32_t src_x, uint32_t src_y,
12082 uint32_t src_w, uint32_t src_h)
12083 {
12084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12085 struct intel_plane_state state;
12086 int ret;
12087
12088 state.crtc = crtc;
12089 state.fb = fb;
12090
12091 /* sample coordinates in 16.16 fixed point */
12092 state.src.x1 = src_x;
12093 state.src.x2 = src_x + src_w;
12094 state.src.y1 = src_y;
12095 state.src.y2 = src_y + src_h;
12096
12097 /* integer pixels */
12098 state.dst.x1 = crtc_x;
12099 state.dst.x2 = crtc_x + crtc_w;
12100 state.dst.y1 = crtc_y;
12101 state.dst.y2 = crtc_y + crtc_h;
12102
12103 state.clip.x1 = 0;
12104 state.clip.y1 = 0;
12105 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
12106 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
12107
12108 state.orig_src = state.src;
12109 state.orig_dst = state.dst;
12110
12111 ret = intel_check_cursor_plane(plane, &state);
12112 if (ret)
12113 return ret;
12114
12115 return intel_commit_cursor_plane(plane, &state);
12116 }
12117
12118 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12119 .update_plane = intel_cursor_plane_update,
12120 .disable_plane = intel_cursor_plane_disable,
12121 .destroy = intel_plane_destroy,
12122 };
12123
12124 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12125 int pipe)
12126 {
12127 struct intel_plane *cursor;
12128
12129 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12130 if (cursor == NULL)
12131 return NULL;
12132
12133 cursor->can_scale = false;
12134 cursor->max_downscale = 1;
12135 cursor->pipe = pipe;
12136 cursor->plane = pipe;
12137
12138 drm_universal_plane_init(dev, &cursor->base, 0,
12139 &intel_cursor_plane_funcs,
12140 intel_cursor_formats,
12141 ARRAY_SIZE(intel_cursor_formats),
12142 DRM_PLANE_TYPE_CURSOR);
12143 return &cursor->base;
12144 }
12145
12146 static void intel_crtc_init(struct drm_device *dev, int pipe)
12147 {
12148 struct drm_i915_private *dev_priv = dev->dev_private;
12149 struct intel_crtc *intel_crtc;
12150 struct drm_plane *primary = NULL;
12151 struct drm_plane *cursor = NULL;
12152 int i, ret;
12153
12154 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12155 if (intel_crtc == NULL)
12156 return;
12157
12158 primary = intel_primary_plane_create(dev, pipe);
12159 if (!primary)
12160 goto fail;
12161
12162 cursor = intel_cursor_plane_create(dev, pipe);
12163 if (!cursor)
12164 goto fail;
12165
12166 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12167 cursor, &intel_crtc_funcs);
12168 if (ret)
12169 goto fail;
12170
12171 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12172 for (i = 0; i < 256; i++) {
12173 intel_crtc->lut_r[i] = i;
12174 intel_crtc->lut_g[i] = i;
12175 intel_crtc->lut_b[i] = i;
12176 }
12177
12178 /*
12179 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12180 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12181 */
12182 intel_crtc->pipe = pipe;
12183 intel_crtc->plane = pipe;
12184 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12185 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12186 intel_crtc->plane = !pipe;
12187 }
12188
12189 intel_crtc->cursor_base = ~0;
12190 intel_crtc->cursor_cntl = ~0;
12191 intel_crtc->cursor_size = ~0;
12192
12193 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12194 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12195 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12196 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12197
12198 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12199
12200 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12201 return;
12202
12203 fail:
12204 if (primary)
12205 drm_plane_cleanup(primary);
12206 if (cursor)
12207 drm_plane_cleanup(cursor);
12208 kfree(intel_crtc);
12209 }
12210
12211 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12212 {
12213 struct drm_encoder *encoder = connector->base.encoder;
12214 struct drm_device *dev = connector->base.dev;
12215
12216 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12217
12218 if (!encoder)
12219 return INVALID_PIPE;
12220
12221 return to_intel_crtc(encoder->crtc)->pipe;
12222 }
12223
12224 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12225 struct drm_file *file)
12226 {
12227 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12228 struct drm_crtc *drmmode_crtc;
12229 struct intel_crtc *crtc;
12230
12231 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12232 return -ENODEV;
12233
12234 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12235
12236 if (!drmmode_crtc) {
12237 DRM_ERROR("no such CRTC id\n");
12238 return -ENOENT;
12239 }
12240
12241 crtc = to_intel_crtc(drmmode_crtc);
12242 pipe_from_crtc_id->pipe = crtc->pipe;
12243
12244 return 0;
12245 }
12246
12247 static int intel_encoder_clones(struct intel_encoder *encoder)
12248 {
12249 struct drm_device *dev = encoder->base.dev;
12250 struct intel_encoder *source_encoder;
12251 int index_mask = 0;
12252 int entry = 0;
12253
12254 for_each_intel_encoder(dev, source_encoder) {
12255 if (encoders_cloneable(encoder, source_encoder))
12256 index_mask |= (1 << entry);
12257
12258 entry++;
12259 }
12260
12261 return index_mask;
12262 }
12263
12264 static bool has_edp_a(struct drm_device *dev)
12265 {
12266 struct drm_i915_private *dev_priv = dev->dev_private;
12267
12268 if (!IS_MOBILE(dev))
12269 return false;
12270
12271 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12272 return false;
12273
12274 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12275 return false;
12276
12277 return true;
12278 }
12279
12280 const char *intel_output_name(int output)
12281 {
12282 static const char *names[] = {
12283 [INTEL_OUTPUT_UNUSED] = "Unused",
12284 [INTEL_OUTPUT_ANALOG] = "Analog",
12285 [INTEL_OUTPUT_DVO] = "DVO",
12286 [INTEL_OUTPUT_SDVO] = "SDVO",
12287 [INTEL_OUTPUT_LVDS] = "LVDS",
12288 [INTEL_OUTPUT_TVOUT] = "TV",
12289 [INTEL_OUTPUT_HDMI] = "HDMI",
12290 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12291 [INTEL_OUTPUT_EDP] = "eDP",
12292 [INTEL_OUTPUT_DSI] = "DSI",
12293 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12294 };
12295
12296 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12297 return "Invalid";
12298
12299 return names[output];
12300 }
12301
12302 static bool intel_crt_present(struct drm_device *dev)
12303 {
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305
12306 if (IS_ULT(dev))
12307 return false;
12308
12309 if (IS_CHERRYVIEW(dev))
12310 return false;
12311
12312 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12313 return false;
12314
12315 return true;
12316 }
12317
12318 static void intel_setup_outputs(struct drm_device *dev)
12319 {
12320 struct drm_i915_private *dev_priv = dev->dev_private;
12321 struct intel_encoder *encoder;
12322 bool dpd_is_edp = false;
12323
12324 intel_lvds_init(dev);
12325
12326 if (intel_crt_present(dev))
12327 intel_crt_init(dev);
12328
12329 if (HAS_DDI(dev)) {
12330 int found;
12331
12332 /* Haswell uses DDI functions to detect digital outputs */
12333 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12334 /* DDI A only supports eDP */
12335 if (found)
12336 intel_ddi_init(dev, PORT_A);
12337
12338 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12339 * register */
12340 found = I915_READ(SFUSE_STRAP);
12341
12342 if (found & SFUSE_STRAP_DDIB_DETECTED)
12343 intel_ddi_init(dev, PORT_B);
12344 if (found & SFUSE_STRAP_DDIC_DETECTED)
12345 intel_ddi_init(dev, PORT_C);
12346 if (found & SFUSE_STRAP_DDID_DETECTED)
12347 intel_ddi_init(dev, PORT_D);
12348 } else if (HAS_PCH_SPLIT(dev)) {
12349 int found;
12350 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12351
12352 if (has_edp_a(dev))
12353 intel_dp_init(dev, DP_A, PORT_A);
12354
12355 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12356 /* PCH SDVOB multiplex with HDMIB */
12357 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12358 if (!found)
12359 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12360 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12361 intel_dp_init(dev, PCH_DP_B, PORT_B);
12362 }
12363
12364 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12365 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12366
12367 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12368 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12369
12370 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12371 intel_dp_init(dev, PCH_DP_C, PORT_C);
12372
12373 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12374 intel_dp_init(dev, PCH_DP_D, PORT_D);
12375 } else if (IS_VALLEYVIEW(dev)) {
12376 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12377 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12378 PORT_B);
12379 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12380 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12381 }
12382
12383 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12384 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12385 PORT_C);
12386 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12387 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12388 }
12389
12390 if (IS_CHERRYVIEW(dev)) {
12391 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12392 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12393 PORT_D);
12394 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12395 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12396 }
12397 }
12398
12399 intel_dsi_init(dev);
12400 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12401 bool found = false;
12402
12403 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12404 DRM_DEBUG_KMS("probing SDVOB\n");
12405 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12406 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12407 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12408 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12409 }
12410
12411 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12412 intel_dp_init(dev, DP_B, PORT_B);
12413 }
12414
12415 /* Before G4X SDVOC doesn't have its own detect register */
12416
12417 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12418 DRM_DEBUG_KMS("probing SDVOC\n");
12419 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12420 }
12421
12422 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12423
12424 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12425 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12426 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12427 }
12428 if (SUPPORTS_INTEGRATED_DP(dev))
12429 intel_dp_init(dev, DP_C, PORT_C);
12430 }
12431
12432 if (SUPPORTS_INTEGRATED_DP(dev) &&
12433 (I915_READ(DP_D) & DP_DETECTED))
12434 intel_dp_init(dev, DP_D, PORT_D);
12435 } else if (IS_GEN2(dev))
12436 intel_dvo_init(dev);
12437
12438 if (SUPPORTS_TV(dev))
12439 intel_tv_init(dev);
12440
12441 intel_edp_psr_init(dev);
12442
12443 for_each_intel_encoder(dev, encoder) {
12444 encoder->base.possible_crtcs = encoder->crtc_mask;
12445 encoder->base.possible_clones =
12446 intel_encoder_clones(encoder);
12447 }
12448
12449 intel_init_pch_refclk(dev);
12450
12451 drm_helper_move_panel_connectors_to_head(dev);
12452 }
12453
12454 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12455 {
12456 struct drm_device *dev = fb->dev;
12457 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12458
12459 drm_framebuffer_cleanup(fb);
12460 mutex_lock(&dev->struct_mutex);
12461 WARN_ON(!intel_fb->obj->framebuffer_references--);
12462 drm_gem_object_unreference(&intel_fb->obj->base);
12463 mutex_unlock(&dev->struct_mutex);
12464 kfree(intel_fb);
12465 }
12466
12467 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12468 struct drm_file *file,
12469 unsigned int *handle)
12470 {
12471 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12472 struct drm_i915_gem_object *obj = intel_fb->obj;
12473
12474 return drm_gem_handle_create(file, &obj->base, handle);
12475 }
12476
12477 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12478 .destroy = intel_user_framebuffer_destroy,
12479 .create_handle = intel_user_framebuffer_create_handle,
12480 };
12481
12482 static int intel_framebuffer_init(struct drm_device *dev,
12483 struct intel_framebuffer *intel_fb,
12484 struct drm_mode_fb_cmd2 *mode_cmd,
12485 struct drm_i915_gem_object *obj)
12486 {
12487 int aligned_height;
12488 int pitch_limit;
12489 int ret;
12490
12491 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12492
12493 if (obj->tiling_mode == I915_TILING_Y) {
12494 DRM_DEBUG("hardware does not support tiling Y\n");
12495 return -EINVAL;
12496 }
12497
12498 if (mode_cmd->pitches[0] & 63) {
12499 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12500 mode_cmd->pitches[0]);
12501 return -EINVAL;
12502 }
12503
12504 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12505 pitch_limit = 32*1024;
12506 } else if (INTEL_INFO(dev)->gen >= 4) {
12507 if (obj->tiling_mode)
12508 pitch_limit = 16*1024;
12509 else
12510 pitch_limit = 32*1024;
12511 } else if (INTEL_INFO(dev)->gen >= 3) {
12512 if (obj->tiling_mode)
12513 pitch_limit = 8*1024;
12514 else
12515 pitch_limit = 16*1024;
12516 } else
12517 /* XXX DSPC is limited to 4k tiled */
12518 pitch_limit = 8*1024;
12519
12520 if (mode_cmd->pitches[0] > pitch_limit) {
12521 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12522 obj->tiling_mode ? "tiled" : "linear",
12523 mode_cmd->pitches[0], pitch_limit);
12524 return -EINVAL;
12525 }
12526
12527 if (obj->tiling_mode != I915_TILING_NONE &&
12528 mode_cmd->pitches[0] != obj->stride) {
12529 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12530 mode_cmd->pitches[0], obj->stride);
12531 return -EINVAL;
12532 }
12533
12534 /* Reject formats not supported by any plane early. */
12535 switch (mode_cmd->pixel_format) {
12536 case DRM_FORMAT_C8:
12537 case DRM_FORMAT_RGB565:
12538 case DRM_FORMAT_XRGB8888:
12539 case DRM_FORMAT_ARGB8888:
12540 break;
12541 case DRM_FORMAT_XRGB1555:
12542 case DRM_FORMAT_ARGB1555:
12543 if (INTEL_INFO(dev)->gen > 3) {
12544 DRM_DEBUG("unsupported pixel format: %s\n",
12545 drm_get_format_name(mode_cmd->pixel_format));
12546 return -EINVAL;
12547 }
12548 break;
12549 case DRM_FORMAT_XBGR8888:
12550 case DRM_FORMAT_ABGR8888:
12551 case DRM_FORMAT_XRGB2101010:
12552 case DRM_FORMAT_ARGB2101010:
12553 case DRM_FORMAT_XBGR2101010:
12554 case DRM_FORMAT_ABGR2101010:
12555 if (INTEL_INFO(dev)->gen < 4) {
12556 DRM_DEBUG("unsupported pixel format: %s\n",
12557 drm_get_format_name(mode_cmd->pixel_format));
12558 return -EINVAL;
12559 }
12560 break;
12561 case DRM_FORMAT_YUYV:
12562 case DRM_FORMAT_UYVY:
12563 case DRM_FORMAT_YVYU:
12564 case DRM_FORMAT_VYUY:
12565 if (INTEL_INFO(dev)->gen < 5) {
12566 DRM_DEBUG("unsupported pixel format: %s\n",
12567 drm_get_format_name(mode_cmd->pixel_format));
12568 return -EINVAL;
12569 }
12570 break;
12571 default:
12572 DRM_DEBUG("unsupported pixel format: %s\n",
12573 drm_get_format_name(mode_cmd->pixel_format));
12574 return -EINVAL;
12575 }
12576
12577 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12578 if (mode_cmd->offsets[0] != 0)
12579 return -EINVAL;
12580
12581 aligned_height = intel_align_height(dev, mode_cmd->height,
12582 obj->tiling_mode);
12583 /* FIXME drm helper for size checks (especially planar formats)? */
12584 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12585 return -EINVAL;
12586
12587 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12588 intel_fb->obj = obj;
12589 intel_fb->obj->framebuffer_references++;
12590
12591 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12592 if (ret) {
12593 DRM_ERROR("framebuffer init failed %d\n", ret);
12594 return ret;
12595 }
12596
12597 return 0;
12598 }
12599
12600 static struct drm_framebuffer *
12601 intel_user_framebuffer_create(struct drm_device *dev,
12602 struct drm_file *filp,
12603 struct drm_mode_fb_cmd2 *mode_cmd)
12604 {
12605 struct drm_i915_gem_object *obj;
12606
12607 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12608 mode_cmd->handles[0]));
12609 if (&obj->base == NULL)
12610 return ERR_PTR(-ENOENT);
12611
12612 return intel_framebuffer_create(dev, mode_cmd, obj);
12613 }
12614
12615 #ifndef CONFIG_DRM_I915_FBDEV
12616 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12617 {
12618 }
12619 #endif
12620
12621 static const struct drm_mode_config_funcs intel_mode_funcs = {
12622 .fb_create = intel_user_framebuffer_create,
12623 .output_poll_changed = intel_fbdev_output_poll_changed,
12624 };
12625
12626 /* Set up chip specific display functions */
12627 static void intel_init_display(struct drm_device *dev)
12628 {
12629 struct drm_i915_private *dev_priv = dev->dev_private;
12630
12631 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12632 dev_priv->display.find_dpll = g4x_find_best_dpll;
12633 else if (IS_CHERRYVIEW(dev))
12634 dev_priv->display.find_dpll = chv_find_best_dpll;
12635 else if (IS_VALLEYVIEW(dev))
12636 dev_priv->display.find_dpll = vlv_find_best_dpll;
12637 else if (IS_PINEVIEW(dev))
12638 dev_priv->display.find_dpll = pnv_find_best_dpll;
12639 else
12640 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12641
12642 if (HAS_DDI(dev)) {
12643 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12644 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12645 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12646 dev_priv->display.crtc_enable = haswell_crtc_enable;
12647 dev_priv->display.crtc_disable = haswell_crtc_disable;
12648 dev_priv->display.off = ironlake_crtc_off;
12649 dev_priv->display.update_primary_plane =
12650 ironlake_update_primary_plane;
12651 } else if (HAS_PCH_SPLIT(dev)) {
12652 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12653 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12654 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12655 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12656 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12657 dev_priv->display.off = ironlake_crtc_off;
12658 dev_priv->display.update_primary_plane =
12659 ironlake_update_primary_plane;
12660 } else if (IS_VALLEYVIEW(dev)) {
12661 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12662 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12663 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12664 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12665 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12666 dev_priv->display.off = i9xx_crtc_off;
12667 dev_priv->display.update_primary_plane =
12668 i9xx_update_primary_plane;
12669 } else {
12670 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12671 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12672 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12673 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12674 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12675 dev_priv->display.off = i9xx_crtc_off;
12676 dev_priv->display.update_primary_plane =
12677 i9xx_update_primary_plane;
12678 }
12679
12680 /* Returns the core display clock speed */
12681 if (IS_VALLEYVIEW(dev))
12682 dev_priv->display.get_display_clock_speed =
12683 valleyview_get_display_clock_speed;
12684 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12685 dev_priv->display.get_display_clock_speed =
12686 i945_get_display_clock_speed;
12687 else if (IS_I915G(dev))
12688 dev_priv->display.get_display_clock_speed =
12689 i915_get_display_clock_speed;
12690 else if (IS_I945GM(dev) || IS_845G(dev))
12691 dev_priv->display.get_display_clock_speed =
12692 i9xx_misc_get_display_clock_speed;
12693 else if (IS_PINEVIEW(dev))
12694 dev_priv->display.get_display_clock_speed =
12695 pnv_get_display_clock_speed;
12696 else if (IS_I915GM(dev))
12697 dev_priv->display.get_display_clock_speed =
12698 i915gm_get_display_clock_speed;
12699 else if (IS_I865G(dev))
12700 dev_priv->display.get_display_clock_speed =
12701 i865_get_display_clock_speed;
12702 else if (IS_I85X(dev))
12703 dev_priv->display.get_display_clock_speed =
12704 i855_get_display_clock_speed;
12705 else /* 852, 830 */
12706 dev_priv->display.get_display_clock_speed =
12707 i830_get_display_clock_speed;
12708
12709 if (IS_G4X(dev)) {
12710 dev_priv->display.write_eld = g4x_write_eld;
12711 } else if (IS_GEN5(dev)) {
12712 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12713 dev_priv->display.write_eld = ironlake_write_eld;
12714 } else if (IS_GEN6(dev)) {
12715 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12716 dev_priv->display.write_eld = ironlake_write_eld;
12717 dev_priv->display.modeset_global_resources =
12718 snb_modeset_global_resources;
12719 } else if (IS_IVYBRIDGE(dev)) {
12720 /* FIXME: detect B0+ stepping and use auto training */
12721 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12722 dev_priv->display.write_eld = ironlake_write_eld;
12723 dev_priv->display.modeset_global_resources =
12724 ivb_modeset_global_resources;
12725 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12726 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12727 dev_priv->display.write_eld = haswell_write_eld;
12728 dev_priv->display.modeset_global_resources =
12729 haswell_modeset_global_resources;
12730 } else if (IS_VALLEYVIEW(dev)) {
12731 dev_priv->display.modeset_global_resources =
12732 valleyview_modeset_global_resources;
12733 dev_priv->display.write_eld = ironlake_write_eld;
12734 }
12735
12736 /* Default just returns -ENODEV to indicate unsupported */
12737 dev_priv->display.queue_flip = intel_default_queue_flip;
12738
12739 switch (INTEL_INFO(dev)->gen) {
12740 case 2:
12741 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12742 break;
12743
12744 case 3:
12745 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12746 break;
12747
12748 case 4:
12749 case 5:
12750 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12751 break;
12752
12753 case 6:
12754 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12755 break;
12756 case 7:
12757 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12758 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12759 break;
12760 }
12761
12762 intel_panel_init_backlight_funcs(dev);
12763
12764 mutex_init(&dev_priv->pps_mutex);
12765 }
12766
12767 /*
12768 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12769 * resume, or other times. This quirk makes sure that's the case for
12770 * affected systems.
12771 */
12772 static void quirk_pipea_force(struct drm_device *dev)
12773 {
12774 struct drm_i915_private *dev_priv = dev->dev_private;
12775
12776 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12777 DRM_INFO("applying pipe a force quirk\n");
12778 }
12779
12780 static void quirk_pipeb_force(struct drm_device *dev)
12781 {
12782 struct drm_i915_private *dev_priv = dev->dev_private;
12783
12784 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12785 DRM_INFO("applying pipe b force quirk\n");
12786 }
12787
12788 /*
12789 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12790 */
12791 static void quirk_ssc_force_disable(struct drm_device *dev)
12792 {
12793 struct drm_i915_private *dev_priv = dev->dev_private;
12794 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12795 DRM_INFO("applying lvds SSC disable quirk\n");
12796 }
12797
12798 /*
12799 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12800 * brightness value
12801 */
12802 static void quirk_invert_brightness(struct drm_device *dev)
12803 {
12804 struct drm_i915_private *dev_priv = dev->dev_private;
12805 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12806 DRM_INFO("applying inverted panel brightness quirk\n");
12807 }
12808
12809 /* Some VBT's incorrectly indicate no backlight is present */
12810 static void quirk_backlight_present(struct drm_device *dev)
12811 {
12812 struct drm_i915_private *dev_priv = dev->dev_private;
12813 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12814 DRM_INFO("applying backlight present quirk\n");
12815 }
12816
12817 struct intel_quirk {
12818 int device;
12819 int subsystem_vendor;
12820 int subsystem_device;
12821 void (*hook)(struct drm_device *dev);
12822 };
12823
12824 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12825 struct intel_dmi_quirk {
12826 void (*hook)(struct drm_device *dev);
12827 const struct dmi_system_id (*dmi_id_list)[];
12828 };
12829
12830 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12831 {
12832 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12833 return 1;
12834 }
12835
12836 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12837 {
12838 .dmi_id_list = &(const struct dmi_system_id[]) {
12839 {
12840 .callback = intel_dmi_reverse_brightness,
12841 .ident = "NCR Corporation",
12842 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12843 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12844 },
12845 },
12846 { } /* terminating entry */
12847 },
12848 .hook = quirk_invert_brightness,
12849 },
12850 };
12851
12852 static struct intel_quirk intel_quirks[] = {
12853 /* HP Mini needs pipe A force quirk (LP: #322104) */
12854 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12855
12856 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12857 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12858
12859 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12860 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12861
12862 /* 830 needs to leave pipe A & dpll A up */
12863 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12864
12865 /* 830 needs to leave pipe B & dpll B up */
12866 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12867
12868 /* Lenovo U160 cannot use SSC on LVDS */
12869 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12870
12871 /* Sony Vaio Y cannot use SSC on LVDS */
12872 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12873
12874 /* Acer Aspire 5734Z must invert backlight brightness */
12875 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12876
12877 /* Acer/eMachines G725 */
12878 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12879
12880 /* Acer/eMachines e725 */
12881 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12882
12883 /* Acer/Packard Bell NCL20 */
12884 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12885
12886 /* Acer Aspire 4736Z */
12887 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12888
12889 /* Acer Aspire 5336 */
12890 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12891
12892 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12893 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12894
12895 /* Acer C720 Chromebook (Core i3 4005U) */
12896 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12897
12898 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12899 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12900
12901 /* HP Chromebook 14 (Celeron 2955U) */
12902 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12903 };
12904
12905 static void intel_init_quirks(struct drm_device *dev)
12906 {
12907 struct pci_dev *d = dev->pdev;
12908 int i;
12909
12910 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12911 struct intel_quirk *q = &intel_quirks[i];
12912
12913 if (d->device == q->device &&
12914 (d->subsystem_vendor == q->subsystem_vendor ||
12915 q->subsystem_vendor == PCI_ANY_ID) &&
12916 (d->subsystem_device == q->subsystem_device ||
12917 q->subsystem_device == PCI_ANY_ID))
12918 q->hook(dev);
12919 }
12920 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12921 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12922 intel_dmi_quirks[i].hook(dev);
12923 }
12924 }
12925
12926 /* Disable the VGA plane that we never use */
12927 static void i915_disable_vga(struct drm_device *dev)
12928 {
12929 struct drm_i915_private *dev_priv = dev->dev_private;
12930 u8 sr1;
12931 u32 vga_reg = i915_vgacntrl_reg(dev);
12932
12933 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12934 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12935 outb(SR01, VGA_SR_INDEX);
12936 sr1 = inb(VGA_SR_DATA);
12937 outb(sr1 | 1<<5, VGA_SR_DATA);
12938 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12939 udelay(300);
12940
12941 /*
12942 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12943 * from S3 without preserving (some of?) the other bits.
12944 */
12945 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12946 POSTING_READ(vga_reg);
12947 }
12948
12949 void intel_modeset_init_hw(struct drm_device *dev)
12950 {
12951 intel_prepare_ddi(dev);
12952
12953 if (IS_VALLEYVIEW(dev))
12954 vlv_update_cdclk(dev);
12955
12956 intel_init_clock_gating(dev);
12957
12958 intel_enable_gt_powersave(dev);
12959 }
12960
12961 void intel_modeset_suspend_hw(struct drm_device *dev)
12962 {
12963 intel_suspend_hw(dev);
12964 }
12965
12966 void intel_modeset_init(struct drm_device *dev)
12967 {
12968 struct drm_i915_private *dev_priv = dev->dev_private;
12969 int sprite, ret;
12970 enum pipe pipe;
12971 struct intel_crtc *crtc;
12972
12973 drm_mode_config_init(dev);
12974
12975 dev->mode_config.min_width = 0;
12976 dev->mode_config.min_height = 0;
12977
12978 dev->mode_config.preferred_depth = 24;
12979 dev->mode_config.prefer_shadow = 1;
12980
12981 dev->mode_config.funcs = &intel_mode_funcs;
12982
12983 intel_init_quirks(dev);
12984
12985 intel_init_pm(dev);
12986
12987 if (INTEL_INFO(dev)->num_pipes == 0)
12988 return;
12989
12990 intel_init_display(dev);
12991
12992 if (IS_GEN2(dev)) {
12993 dev->mode_config.max_width = 2048;
12994 dev->mode_config.max_height = 2048;
12995 } else if (IS_GEN3(dev)) {
12996 dev->mode_config.max_width = 4096;
12997 dev->mode_config.max_height = 4096;
12998 } else {
12999 dev->mode_config.max_width = 8192;
13000 dev->mode_config.max_height = 8192;
13001 }
13002
13003 if (IS_845G(dev) || IS_I865G(dev)) {
13004 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13005 dev->mode_config.cursor_height = 1023;
13006 } else if (IS_GEN2(dev)) {
13007 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13008 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13009 } else {
13010 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13011 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13012 }
13013
13014 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13015
13016 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13017 INTEL_INFO(dev)->num_pipes,
13018 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13019
13020 for_each_pipe(dev_priv, pipe) {
13021 intel_crtc_init(dev, pipe);
13022 for_each_sprite(pipe, sprite) {
13023 ret = intel_plane_init(dev, pipe, sprite);
13024 if (ret)
13025 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13026 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13027 }
13028 }
13029
13030 intel_init_dpio(dev);
13031
13032 intel_shared_dpll_init(dev);
13033
13034 /* save the BIOS value before clobbering it */
13035 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13036 /* Just disable it once at startup */
13037 i915_disable_vga(dev);
13038 intel_setup_outputs(dev);
13039
13040 /* Just in case the BIOS is doing something questionable. */
13041 intel_disable_fbc(dev);
13042
13043 drm_modeset_lock_all(dev);
13044 intel_modeset_setup_hw_state(dev, false);
13045 drm_modeset_unlock_all(dev);
13046
13047 for_each_intel_crtc(dev, crtc) {
13048 if (!crtc->active)
13049 continue;
13050
13051 /*
13052 * Note that reserving the BIOS fb up front prevents us
13053 * from stuffing other stolen allocations like the ring
13054 * on top. This prevents some ugliness at boot time, and
13055 * can even allow for smooth boot transitions if the BIOS
13056 * fb is large enough for the active pipe configuration.
13057 */
13058 if (dev_priv->display.get_plane_config) {
13059 dev_priv->display.get_plane_config(crtc,
13060 &crtc->plane_config);
13061 /*
13062 * If the fb is shared between multiple heads, we'll
13063 * just get the first one.
13064 */
13065 intel_find_plane_obj(crtc, &crtc->plane_config);
13066 }
13067 }
13068 }
13069
13070 static void intel_enable_pipe_a(struct drm_device *dev)
13071 {
13072 struct intel_connector *connector;
13073 struct drm_connector *crt = NULL;
13074 struct intel_load_detect_pipe load_detect_temp;
13075 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13076
13077 /* We can't just switch on the pipe A, we need to set things up with a
13078 * proper mode and output configuration. As a gross hack, enable pipe A
13079 * by enabling the load detect pipe once. */
13080 list_for_each_entry(connector,
13081 &dev->mode_config.connector_list,
13082 base.head) {
13083 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13084 crt = &connector->base;
13085 break;
13086 }
13087 }
13088
13089 if (!crt)
13090 return;
13091
13092 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13093 intel_release_load_detect_pipe(crt, &load_detect_temp);
13094 }
13095
13096 static bool
13097 intel_check_plane_mapping(struct intel_crtc *crtc)
13098 {
13099 struct drm_device *dev = crtc->base.dev;
13100 struct drm_i915_private *dev_priv = dev->dev_private;
13101 u32 reg, val;
13102
13103 if (INTEL_INFO(dev)->num_pipes == 1)
13104 return true;
13105
13106 reg = DSPCNTR(!crtc->plane);
13107 val = I915_READ(reg);
13108
13109 if ((val & DISPLAY_PLANE_ENABLE) &&
13110 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13111 return false;
13112
13113 return true;
13114 }
13115
13116 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13117 {
13118 struct drm_device *dev = crtc->base.dev;
13119 struct drm_i915_private *dev_priv = dev->dev_private;
13120 u32 reg;
13121
13122 /* Clear any frame start delays used for debugging left by the BIOS */
13123 reg = PIPECONF(crtc->config.cpu_transcoder);
13124 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13125
13126 /* restore vblank interrupts to correct state */
13127 if (crtc->active) {
13128 update_scanline_offset(crtc);
13129 drm_vblank_on(dev, crtc->pipe);
13130 } else
13131 drm_vblank_off(dev, crtc->pipe);
13132
13133 /* We need to sanitize the plane -> pipe mapping first because this will
13134 * disable the crtc (and hence change the state) if it is wrong. Note
13135 * that gen4+ has a fixed plane -> pipe mapping. */
13136 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13137 struct intel_connector *connector;
13138 bool plane;
13139
13140 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13141 crtc->base.base.id);
13142
13143 /* Pipe has the wrong plane attached and the plane is active.
13144 * Temporarily change the plane mapping and disable everything
13145 * ... */
13146 plane = crtc->plane;
13147 crtc->plane = !plane;
13148 crtc->primary_enabled = true;
13149 dev_priv->display.crtc_disable(&crtc->base);
13150 crtc->plane = plane;
13151
13152 /* ... and break all links. */
13153 list_for_each_entry(connector, &dev->mode_config.connector_list,
13154 base.head) {
13155 if (connector->encoder->base.crtc != &crtc->base)
13156 continue;
13157
13158 connector->base.dpms = DRM_MODE_DPMS_OFF;
13159 connector->base.encoder = NULL;
13160 }
13161 /* multiple connectors may have the same encoder:
13162 * handle them and break crtc link separately */
13163 list_for_each_entry(connector, &dev->mode_config.connector_list,
13164 base.head)
13165 if (connector->encoder->base.crtc == &crtc->base) {
13166 connector->encoder->base.crtc = NULL;
13167 connector->encoder->connectors_active = false;
13168 }
13169
13170 WARN_ON(crtc->active);
13171 crtc->base.enabled = false;
13172 }
13173
13174 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13175 crtc->pipe == PIPE_A && !crtc->active) {
13176 /* BIOS forgot to enable pipe A, this mostly happens after
13177 * resume. Force-enable the pipe to fix this, the update_dpms
13178 * call below we restore the pipe to the right state, but leave
13179 * the required bits on. */
13180 intel_enable_pipe_a(dev);
13181 }
13182
13183 /* Adjust the state of the output pipe according to whether we
13184 * have active connectors/encoders. */
13185 intel_crtc_update_dpms(&crtc->base);
13186
13187 if (crtc->active != crtc->base.enabled) {
13188 struct intel_encoder *encoder;
13189
13190 /* This can happen either due to bugs in the get_hw_state
13191 * functions or because the pipe is force-enabled due to the
13192 * pipe A quirk. */
13193 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13194 crtc->base.base.id,
13195 crtc->base.enabled ? "enabled" : "disabled",
13196 crtc->active ? "enabled" : "disabled");
13197
13198 crtc->base.enabled = crtc->active;
13199
13200 /* Because we only establish the connector -> encoder ->
13201 * crtc links if something is active, this means the
13202 * crtc is now deactivated. Break the links. connector
13203 * -> encoder links are only establish when things are
13204 * actually up, hence no need to break them. */
13205 WARN_ON(crtc->active);
13206
13207 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13208 WARN_ON(encoder->connectors_active);
13209 encoder->base.crtc = NULL;
13210 }
13211 }
13212
13213 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13214 /*
13215 * We start out with underrun reporting disabled to avoid races.
13216 * For correct bookkeeping mark this on active crtcs.
13217 *
13218 * Also on gmch platforms we dont have any hardware bits to
13219 * disable the underrun reporting. Which means we need to start
13220 * out with underrun reporting disabled also on inactive pipes,
13221 * since otherwise we'll complain about the garbage we read when
13222 * e.g. coming up after runtime pm.
13223 *
13224 * No protection against concurrent access is required - at
13225 * worst a fifo underrun happens which also sets this to false.
13226 */
13227 crtc->cpu_fifo_underrun_disabled = true;
13228 crtc->pch_fifo_underrun_disabled = true;
13229 }
13230 }
13231
13232 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13233 {
13234 struct intel_connector *connector;
13235 struct drm_device *dev = encoder->base.dev;
13236
13237 /* We need to check both for a crtc link (meaning that the
13238 * encoder is active and trying to read from a pipe) and the
13239 * pipe itself being active. */
13240 bool has_active_crtc = encoder->base.crtc &&
13241 to_intel_crtc(encoder->base.crtc)->active;
13242
13243 if (encoder->connectors_active && !has_active_crtc) {
13244 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13245 encoder->base.base.id,
13246 encoder->base.name);
13247
13248 /* Connector is active, but has no active pipe. This is
13249 * fallout from our resume register restoring. Disable
13250 * the encoder manually again. */
13251 if (encoder->base.crtc) {
13252 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13253 encoder->base.base.id,
13254 encoder->base.name);
13255 encoder->disable(encoder);
13256 if (encoder->post_disable)
13257 encoder->post_disable(encoder);
13258 }
13259 encoder->base.crtc = NULL;
13260 encoder->connectors_active = false;
13261
13262 /* Inconsistent output/port/pipe state happens presumably due to
13263 * a bug in one of the get_hw_state functions. Or someplace else
13264 * in our code, like the register restore mess on resume. Clamp
13265 * things to off as a safer default. */
13266 list_for_each_entry(connector,
13267 &dev->mode_config.connector_list,
13268 base.head) {
13269 if (connector->encoder != encoder)
13270 continue;
13271 connector->base.dpms = DRM_MODE_DPMS_OFF;
13272 connector->base.encoder = NULL;
13273 }
13274 }
13275 /* Enabled encoders without active connectors will be fixed in
13276 * the crtc fixup. */
13277 }
13278
13279 void i915_redisable_vga_power_on(struct drm_device *dev)
13280 {
13281 struct drm_i915_private *dev_priv = dev->dev_private;
13282 u32 vga_reg = i915_vgacntrl_reg(dev);
13283
13284 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13285 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13286 i915_disable_vga(dev);
13287 }
13288 }
13289
13290 void i915_redisable_vga(struct drm_device *dev)
13291 {
13292 struct drm_i915_private *dev_priv = dev->dev_private;
13293
13294 /* This function can be called both from intel_modeset_setup_hw_state or
13295 * at a very early point in our resume sequence, where the power well
13296 * structures are not yet restored. Since this function is at a very
13297 * paranoid "someone might have enabled VGA while we were not looking"
13298 * level, just check if the power well is enabled instead of trying to
13299 * follow the "don't touch the power well if we don't need it" policy
13300 * the rest of the driver uses. */
13301 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13302 return;
13303
13304 i915_redisable_vga_power_on(dev);
13305 }
13306
13307 static bool primary_get_hw_state(struct intel_crtc *crtc)
13308 {
13309 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13310
13311 if (!crtc->active)
13312 return false;
13313
13314 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13315 }
13316
13317 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13318 {
13319 struct drm_i915_private *dev_priv = dev->dev_private;
13320 enum pipe pipe;
13321 struct intel_crtc *crtc;
13322 struct intel_encoder *encoder;
13323 struct intel_connector *connector;
13324 int i;
13325
13326 for_each_intel_crtc(dev, crtc) {
13327 memset(&crtc->config, 0, sizeof(crtc->config));
13328
13329 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13330
13331 crtc->active = dev_priv->display.get_pipe_config(crtc,
13332 &crtc->config);
13333
13334 crtc->base.enabled = crtc->active;
13335 crtc->primary_enabled = primary_get_hw_state(crtc);
13336
13337 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13338 crtc->base.base.id,
13339 crtc->active ? "enabled" : "disabled");
13340 }
13341
13342 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13343 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13344
13345 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13346 pll->active = 0;
13347 for_each_intel_crtc(dev, crtc) {
13348 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13349 pll->active++;
13350 }
13351 pll->refcount = pll->active;
13352
13353 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13354 pll->name, pll->refcount, pll->on);
13355
13356 if (pll->refcount)
13357 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13358 }
13359
13360 for_each_intel_encoder(dev, encoder) {
13361 pipe = 0;
13362
13363 if (encoder->get_hw_state(encoder, &pipe)) {
13364 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13365 encoder->base.crtc = &crtc->base;
13366 encoder->get_config(encoder, &crtc->config);
13367 } else {
13368 encoder->base.crtc = NULL;
13369 }
13370
13371 encoder->connectors_active = false;
13372 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13373 encoder->base.base.id,
13374 encoder->base.name,
13375 encoder->base.crtc ? "enabled" : "disabled",
13376 pipe_name(pipe));
13377 }
13378
13379 list_for_each_entry(connector, &dev->mode_config.connector_list,
13380 base.head) {
13381 if (connector->get_hw_state(connector)) {
13382 connector->base.dpms = DRM_MODE_DPMS_ON;
13383 connector->encoder->connectors_active = true;
13384 connector->base.encoder = &connector->encoder->base;
13385 } else {
13386 connector->base.dpms = DRM_MODE_DPMS_OFF;
13387 connector->base.encoder = NULL;
13388 }
13389 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13390 connector->base.base.id,
13391 connector->base.name,
13392 connector->base.encoder ? "enabled" : "disabled");
13393 }
13394 }
13395
13396 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13397 * and i915 state tracking structures. */
13398 void intel_modeset_setup_hw_state(struct drm_device *dev,
13399 bool force_restore)
13400 {
13401 struct drm_i915_private *dev_priv = dev->dev_private;
13402 enum pipe pipe;
13403 struct intel_crtc *crtc;
13404 struct intel_encoder *encoder;
13405 int i;
13406
13407 intel_modeset_readout_hw_state(dev);
13408
13409 /*
13410 * Now that we have the config, copy it to each CRTC struct
13411 * Note that this could go away if we move to using crtc_config
13412 * checking everywhere.
13413 */
13414 for_each_intel_crtc(dev, crtc) {
13415 if (crtc->active && i915.fastboot) {
13416 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13417 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13418 crtc->base.base.id);
13419 drm_mode_debug_printmodeline(&crtc->base.mode);
13420 }
13421 }
13422
13423 /* HW state is read out, now we need to sanitize this mess. */
13424 for_each_intel_encoder(dev, encoder) {
13425 intel_sanitize_encoder(encoder);
13426 }
13427
13428 for_each_pipe(dev_priv, pipe) {
13429 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13430 intel_sanitize_crtc(crtc);
13431 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13432 }
13433
13434 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13435 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13436
13437 if (!pll->on || pll->active)
13438 continue;
13439
13440 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13441
13442 pll->disable(dev_priv, pll);
13443 pll->on = false;
13444 }
13445
13446 if (HAS_PCH_SPLIT(dev))
13447 ilk_wm_get_hw_state(dev);
13448
13449 if (force_restore) {
13450 i915_redisable_vga(dev);
13451
13452 /*
13453 * We need to use raw interfaces for restoring state to avoid
13454 * checking (bogus) intermediate states.
13455 */
13456 for_each_pipe(dev_priv, pipe) {
13457 struct drm_crtc *crtc =
13458 dev_priv->pipe_to_crtc_mapping[pipe];
13459
13460 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13461 crtc->primary->fb);
13462 }
13463 } else {
13464 intel_modeset_update_staged_output_state(dev);
13465 }
13466
13467 intel_modeset_check_state(dev);
13468 }
13469
13470 void intel_modeset_gem_init(struct drm_device *dev)
13471 {
13472 struct drm_crtc *c;
13473 struct drm_i915_gem_object *obj;
13474
13475 mutex_lock(&dev->struct_mutex);
13476 intel_init_gt_powersave(dev);
13477 mutex_unlock(&dev->struct_mutex);
13478
13479 intel_modeset_init_hw(dev);
13480
13481 intel_setup_overlay(dev);
13482
13483 /*
13484 * Make sure any fbs we allocated at startup are properly
13485 * pinned & fenced. When we do the allocation it's too early
13486 * for this.
13487 */
13488 mutex_lock(&dev->struct_mutex);
13489 for_each_crtc(dev, c) {
13490 obj = intel_fb_obj(c->primary->fb);
13491 if (obj == NULL)
13492 continue;
13493
13494 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13495 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13496 to_intel_crtc(c)->pipe);
13497 drm_framebuffer_unreference(c->primary->fb);
13498 c->primary->fb = NULL;
13499 }
13500 }
13501 mutex_unlock(&dev->struct_mutex);
13502 }
13503
13504 void intel_connector_unregister(struct intel_connector *intel_connector)
13505 {
13506 struct drm_connector *connector = &intel_connector->base;
13507
13508 intel_panel_destroy_backlight(connector);
13509 drm_connector_unregister(connector);
13510 }
13511
13512 void intel_modeset_cleanup(struct drm_device *dev)
13513 {
13514 struct drm_i915_private *dev_priv = dev->dev_private;
13515 struct drm_connector *connector;
13516
13517 /*
13518 * Interrupts and polling as the first thing to avoid creating havoc.
13519 * Too much stuff here (turning of rps, connectors, ...) would
13520 * experience fancy races otherwise.
13521 */
13522 drm_irq_uninstall(dev);
13523 intel_hpd_cancel_work(dev_priv);
13524 dev_priv->pm._irqs_disabled = true;
13525
13526 /*
13527 * Due to the hpd irq storm handling the hotplug work can re-arm the
13528 * poll handlers. Hence disable polling after hpd handling is shut down.
13529 */
13530 drm_kms_helper_poll_fini(dev);
13531
13532 mutex_lock(&dev->struct_mutex);
13533
13534 intel_unregister_dsm_handler();
13535
13536 intel_disable_fbc(dev);
13537
13538 intel_disable_gt_powersave(dev);
13539
13540 ironlake_teardown_rc6(dev);
13541
13542 mutex_unlock(&dev->struct_mutex);
13543
13544 /* flush any delayed tasks or pending work */
13545 flush_scheduled_work();
13546
13547 /* destroy the backlight and sysfs files before encoders/connectors */
13548 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13549 struct intel_connector *intel_connector;
13550
13551 intel_connector = to_intel_connector(connector);
13552 intel_connector->unregister(intel_connector);
13553 }
13554
13555 drm_mode_config_cleanup(dev);
13556
13557 intel_cleanup_overlay(dev);
13558
13559 mutex_lock(&dev->struct_mutex);
13560 intel_cleanup_gt_powersave(dev);
13561 mutex_unlock(&dev->struct_mutex);
13562 }
13563
13564 /*
13565 * Return which encoder is currently attached for connector.
13566 */
13567 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13568 {
13569 return &intel_attached_encoder(connector)->base;
13570 }
13571
13572 void intel_connector_attach_encoder(struct intel_connector *connector,
13573 struct intel_encoder *encoder)
13574 {
13575 connector->encoder = encoder;
13576 drm_mode_connector_attach_encoder(&connector->base,
13577 &encoder->base);
13578 }
13579
13580 /*
13581 * set vga decode state - true == enable VGA decode
13582 */
13583 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13584 {
13585 struct drm_i915_private *dev_priv = dev->dev_private;
13586 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13587 u16 gmch_ctrl;
13588
13589 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13590 DRM_ERROR("failed to read control word\n");
13591 return -EIO;
13592 }
13593
13594 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13595 return 0;
13596
13597 if (state)
13598 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13599 else
13600 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13601
13602 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13603 DRM_ERROR("failed to write control word\n");
13604 return -EIO;
13605 }
13606
13607 return 0;
13608 }
13609
13610 struct intel_display_error_state {
13611
13612 u32 power_well_driver;
13613
13614 int num_transcoders;
13615
13616 struct intel_cursor_error_state {
13617 u32 control;
13618 u32 position;
13619 u32 base;
13620 u32 size;
13621 } cursor[I915_MAX_PIPES];
13622
13623 struct intel_pipe_error_state {
13624 bool power_domain_on;
13625 u32 source;
13626 u32 stat;
13627 } pipe[I915_MAX_PIPES];
13628
13629 struct intel_plane_error_state {
13630 u32 control;
13631 u32 stride;
13632 u32 size;
13633 u32 pos;
13634 u32 addr;
13635 u32 surface;
13636 u32 tile_offset;
13637 } plane[I915_MAX_PIPES];
13638
13639 struct intel_transcoder_error_state {
13640 bool power_domain_on;
13641 enum transcoder cpu_transcoder;
13642
13643 u32 conf;
13644
13645 u32 htotal;
13646 u32 hblank;
13647 u32 hsync;
13648 u32 vtotal;
13649 u32 vblank;
13650 u32 vsync;
13651 } transcoder[4];
13652 };
13653
13654 struct intel_display_error_state *
13655 intel_display_capture_error_state(struct drm_device *dev)
13656 {
13657 struct drm_i915_private *dev_priv = dev->dev_private;
13658 struct intel_display_error_state *error;
13659 int transcoders[] = {
13660 TRANSCODER_A,
13661 TRANSCODER_B,
13662 TRANSCODER_C,
13663 TRANSCODER_EDP,
13664 };
13665 int i;
13666
13667 if (INTEL_INFO(dev)->num_pipes == 0)
13668 return NULL;
13669
13670 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13671 if (error == NULL)
13672 return NULL;
13673
13674 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13675 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13676
13677 for_each_pipe(dev_priv, i) {
13678 error->pipe[i].power_domain_on =
13679 intel_display_power_enabled_unlocked(dev_priv,
13680 POWER_DOMAIN_PIPE(i));
13681 if (!error->pipe[i].power_domain_on)
13682 continue;
13683
13684 error->cursor[i].control = I915_READ(CURCNTR(i));
13685 error->cursor[i].position = I915_READ(CURPOS(i));
13686 error->cursor[i].base = I915_READ(CURBASE(i));
13687
13688 error->plane[i].control = I915_READ(DSPCNTR(i));
13689 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13690 if (INTEL_INFO(dev)->gen <= 3) {
13691 error->plane[i].size = I915_READ(DSPSIZE(i));
13692 error->plane[i].pos = I915_READ(DSPPOS(i));
13693 }
13694 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13695 error->plane[i].addr = I915_READ(DSPADDR(i));
13696 if (INTEL_INFO(dev)->gen >= 4) {
13697 error->plane[i].surface = I915_READ(DSPSURF(i));
13698 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13699 }
13700
13701 error->pipe[i].source = I915_READ(PIPESRC(i));
13702
13703 if (HAS_GMCH_DISPLAY(dev))
13704 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13705 }
13706
13707 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13708 if (HAS_DDI(dev_priv->dev))
13709 error->num_transcoders++; /* Account for eDP. */
13710
13711 for (i = 0; i < error->num_transcoders; i++) {
13712 enum transcoder cpu_transcoder = transcoders[i];
13713
13714 error->transcoder[i].power_domain_on =
13715 intel_display_power_enabled_unlocked(dev_priv,
13716 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13717 if (!error->transcoder[i].power_domain_on)
13718 continue;
13719
13720 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13721
13722 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13723 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13724 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13725 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13726 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13727 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13728 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13729 }
13730
13731 return error;
13732 }
13733
13734 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13735
13736 void
13737 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13738 struct drm_device *dev,
13739 struct intel_display_error_state *error)
13740 {
13741 struct drm_i915_private *dev_priv = dev->dev_private;
13742 int i;
13743
13744 if (!error)
13745 return;
13746
13747 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13748 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13749 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13750 error->power_well_driver);
13751 for_each_pipe(dev_priv, i) {
13752 err_printf(m, "Pipe [%d]:\n", i);
13753 err_printf(m, " Power: %s\n",
13754 error->pipe[i].power_domain_on ? "on" : "off");
13755 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13756 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13757
13758 err_printf(m, "Plane [%d]:\n", i);
13759 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13760 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13761 if (INTEL_INFO(dev)->gen <= 3) {
13762 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13763 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13764 }
13765 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13766 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13767 if (INTEL_INFO(dev)->gen >= 4) {
13768 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13769 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13770 }
13771
13772 err_printf(m, "Cursor [%d]:\n", i);
13773 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13774 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13775 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13776 }
13777
13778 for (i = 0; i < error->num_transcoders; i++) {
13779 err_printf(m, "CPU transcoder: %c\n",
13780 transcoder_name(error->transcoder[i].cpu_transcoder));
13781 err_printf(m, " Power: %s\n",
13782 error->transcoder[i].power_domain_on ? "on" : "off");
13783 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13784 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13785 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13786 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13787 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13788 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13789 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13790 }
13791 }
13792
13793 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13794 {
13795 struct intel_crtc *crtc;
13796
13797 for_each_intel_crtc(dev, crtc) {
13798 struct intel_unpin_work *work;
13799 unsigned long irqflags;
13800
13801 spin_lock_irqsave(&dev->event_lock, irqflags);
13802
13803 work = crtc->unpin_work;
13804
13805 if (work && work->event &&
13806 work->event->base.file_priv == file) {
13807 kfree(work->event);
13808 work->event = NULL;
13809 }
13810
13811 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13812 }
13813 }
Linux kernel - Deliverables
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