projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Cache ringbuf pointer in request structure
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 */
900 return intel_crtc->active && crtc->primary->fb &&
901 intel_crtc->config->base.adjusted_mode.crtc_clock;
902 }
903
904 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
905 enum pipe pipe)
906 {
907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
909
910 return intel_crtc->config->cpu_transcoder;
911 }
912
913 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
914 {
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 u32 reg = PIPEDSL(pipe);
917 u32 line1, line2;
918 u32 line_mask;
919
920 if (IS_GEN2(dev))
921 line_mask = DSL_LINEMASK_GEN2;
922 else
923 line_mask = DSL_LINEMASK_GEN3;
924
925 line1 = I915_READ(reg) & line_mask;
926 mdelay(5);
927 line2 = I915_READ(reg) & line_mask;
928
929 return line1 == line2;
930 }
931
932 /*
933 * intel_wait_for_pipe_off - wait for pipe to turn off
934 * @crtc: crtc whose pipe to wait for
935 *
936 * After disabling a pipe, we can't wait for vblank in the usual way,
937 * spinning on the vblank interrupt status bit, since we won't actually
938 * see an interrupt when the pipe is disabled.
939 *
940 * On Gen4 and above:
941 * wait for the pipe register state bit to turn off
942 *
943 * Otherwise:
944 * wait for the display line value to settle (it usually
945 * ends up stopping at the start of the next frame).
946 *
947 */
948 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
949 {
950 struct drm_device *dev = crtc->base.dev;
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
953 enum pipe pipe = crtc->pipe;
954
955 if (INTEL_INFO(dev)->gen >= 4) {
956 int reg = PIPECONF(cpu_transcoder);
957
958 /* Wait for the Pipe State to go off */
959 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
960 100))
961 WARN(1, "pipe_off wait timed out\n");
962 } else {
963 /* Wait for the display line to settle */
964 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
965 WARN(1, "pipe_off wait timed out\n");
966 }
967 }
968
969 /*
970 * ibx_digital_port_connected - is the specified port connected?
971 * @dev_priv: i915 private structure
972 * @port: the port to test
973 *
974 * Returns true if @port is connected, false otherwise.
975 */
976 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
977 struct intel_digital_port *port)
978 {
979 u32 bit;
980
981 if (HAS_PCH_IBX(dev_priv->dev)) {
982 switch (port->port) {
983 case PORT_B:
984 bit = SDE_PORTB_HOTPLUG;
985 break;
986 case PORT_C:
987 bit = SDE_PORTC_HOTPLUG;
988 break;
989 case PORT_D:
990 bit = SDE_PORTD_HOTPLUG;
991 break;
992 default:
993 return true;
994 }
995 } else {
996 switch (port->port) {
997 case PORT_B:
998 bit = SDE_PORTB_HOTPLUG_CPT;
999 break;
1000 case PORT_C:
1001 bit = SDE_PORTC_HOTPLUG_CPT;
1002 break;
1003 case PORT_D:
1004 bit = SDE_PORTD_HOTPLUG_CPT;
1005 break;
1006 default:
1007 return true;
1008 }
1009 }
1010
1011 return I915_READ(SDEISR) & bit;
1012 }
1013
1014 static const char *state_string(bool enabled)
1015 {
1016 return enabled ? "on" : "off";
1017 }
1018
1019 /* Only for pre-ILK configs */
1020 void assert_pll(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, bool state)
1022 {
1023 int reg;
1024 u32 val;
1025 bool cur_state;
1026
1027 reg = DPLL(pipe);
1028 val = I915_READ(reg);
1029 cur_state = !!(val & DPLL_VCO_ENABLE);
1030 I915_STATE_WARN(cur_state != state,
1031 "PLL state assertion failure (expected %s, current %s)\n",
1032 state_string(state), state_string(cur_state));
1033 }
1034
1035 /* XXX: the dsi pll is shared between MIPI DSI ports */
1036 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1037 {
1038 u32 val;
1039 bool cur_state;
1040
1041 mutex_lock(&dev_priv->dpio_lock);
1042 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1043 mutex_unlock(&dev_priv->dpio_lock);
1044
1045 cur_state = val & DSI_PLL_VCO_EN;
1046 I915_STATE_WARN(cur_state != state,
1047 "DSI PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049 }
1050 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1051 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1052
1053 struct intel_shared_dpll *
1054 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1055 {
1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1057
1058 if (crtc->config->shared_dpll < 0)
1059 return NULL;
1060
1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1062 }
1063
1064 /* For ILK+ */
1065 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1066 struct intel_shared_dpll *pll,
1067 bool state)
1068 {
1069 bool cur_state;
1070 struct intel_dpll_hw_state hw_state;
1071
1072 if (WARN (!pll,
1073 "asserting DPLL %s with no DPLL\n", state_string(state)))
1074 return;
1075
1076 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1077 I915_STATE_WARN(cur_state != state,
1078 "%s assertion failure (expected %s, current %s)\n",
1079 pll->name, state_string(state), state_string(cur_state));
1080 }
1081
1082 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1083 enum pipe pipe, bool state)
1084 {
1085 int reg;
1086 u32 val;
1087 bool cur_state;
1088 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1089 pipe);
1090
1091 if (HAS_DDI(dev_priv->dev)) {
1092 /* DDI does not have a specific FDI_TX register */
1093 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1094 val = I915_READ(reg);
1095 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1096 } else {
1097 reg = FDI_TX_CTL(pipe);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & FDI_TX_ENABLE);
1100 }
1101 I915_STATE_WARN(cur_state != state,
1102 "FDI TX state assertion failure (expected %s, current %s)\n",
1103 state_string(state), state_string(cur_state));
1104 }
1105 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1106 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1107
1108 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1109 enum pipe pipe, bool state)
1110 {
1111 int reg;
1112 u32 val;
1113 bool cur_state;
1114
1115 reg = FDI_RX_CTL(pipe);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & FDI_RX_ENABLE);
1118 I915_STATE_WARN(cur_state != state,
1119 "FDI RX state assertion failure (expected %s, current %s)\n",
1120 state_string(state), state_string(cur_state));
1121 }
1122 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1123 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1124
1125 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127 {
1128 int reg;
1129 u32 val;
1130
1131 /* ILK FDI PLL is always enabled */
1132 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1133 return;
1134
1135 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1136 if (HAS_DDI(dev_priv->dev))
1137 return;
1138
1139 reg = FDI_TX_CTL(pipe);
1140 val = I915_READ(reg);
1141 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1142 }
1143
1144 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1154 I915_STATE_WARN(cur_state != state,
1155 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158
1159 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 struct drm_device *dev = dev_priv->dev;
1163 int pp_reg;
1164 u32 val;
1165 enum pipe panel_pipe = PIPE_A;
1166 bool locked = true;
1167
1168 if (WARN_ON(HAS_DDI(dev)))
1169 return;
1170
1171 if (HAS_PCH_SPLIT(dev)) {
1172 u32 port_sel;
1173
1174 pp_reg = PCH_PP_CONTROL;
1175 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1176
1177 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1178 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1179 panel_pipe = PIPE_B;
1180 /* XXX: else fix for eDP */
1181 } else if (IS_VALLEYVIEW(dev)) {
1182 /* presumably write lock depends on pipe, not port select */
1183 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1184 panel_pipe = pipe;
1185 } else {
1186 pp_reg = PP_CONTROL;
1187 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1188 panel_pipe = PIPE_B;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 I915_STATE_WARN(panel_pipe == pipe && locked,
1197 "panel assertion failure, pipe %c regs locked\n",
1198 pipe_name(pipe));
1199 }
1200
1201 static void assert_cursor(struct drm_i915_private *dev_priv,
1202 enum pipe pipe, bool state)
1203 {
1204 struct drm_device *dev = dev_priv->dev;
1205 bool cur_state;
1206
1207 if (IS_845G(dev) || IS_I865G(dev))
1208 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1209 else
1210 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1211
1212 I915_STATE_WARN(cur_state != state,
1213 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1214 pipe_name(pipe), state_string(state), state_string(cur_state));
1215 }
1216 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1217 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 int reg;
1223 u32 val;
1224 bool cur_state;
1225 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1226 pipe);
1227
1228 /* if we need the pipe quirk it must be always on */
1229 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1230 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1231 state = true;
1232
1233 if (!intel_display_power_is_enabled(dev_priv,
1234 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1235 cur_state = false;
1236 } else {
1237 reg = PIPECONF(cpu_transcoder);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & PIPECONF_ENABLE);
1240 }
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246
1247 static void assert_plane(struct drm_i915_private *dev_priv,
1248 enum plane plane, bool state)
1249 {
1250 int reg;
1251 u32 val;
1252 bool cur_state;
1253
1254 reg = DSPCNTR(plane);
1255 val = I915_READ(reg);
1256 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1257 I915_STATE_WARN(cur_state != state,
1258 "plane %c assertion failure (expected %s, current %s)\n",
1259 plane_name(plane), state_string(state), state_string(cur_state));
1260 }
1261
1262 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1263 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1264
1265 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267 {
1268 struct drm_device *dev = dev_priv->dev;
1269 int reg, i;
1270 u32 val;
1271 int cur_pipe;
1272
1273 /* Primary planes are fixed to pipes on gen4+ */
1274 if (INTEL_INFO(dev)->gen >= 4) {
1275 reg = DSPCNTR(pipe);
1276 val = I915_READ(reg);
1277 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1278 "plane %c assertion failure, should be disabled but not\n",
1279 plane_name(pipe));
1280 return;
1281 }
1282
1283 /* Need to check both planes against the pipe */
1284 for_each_pipe(dev_priv, i) {
1285 reg = DSPCNTR(i);
1286 val = I915_READ(reg);
1287 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1288 DISPPLANE_SEL_PIPE_SHIFT;
1289 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1290 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1291 plane_name(i), pipe_name(pipe));
1292 }
1293 }
1294
1295 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, sprite;
1300 u32 val;
1301
1302 if (INTEL_INFO(dev)->gen >= 9) {
1303 for_each_sprite(pipe, sprite) {
1304 val = I915_READ(PLANE_CTL(pipe, sprite));
1305 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1306 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1307 sprite, pipe_name(pipe));
1308 }
1309 } else if (IS_VALLEYVIEW(dev)) {
1310 for_each_sprite(pipe, sprite) {
1311 reg = SPCNTR(pipe, sprite);
1312 val = I915_READ(reg);
1313 I915_STATE_WARN(val & SP_ENABLE,
1314 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1315 sprite_name(pipe, sprite), pipe_name(pipe));
1316 }
1317 } else if (INTEL_INFO(dev)->gen >= 7) {
1318 reg = SPRCTL(pipe);
1319 val = I915_READ(reg);
1320 I915_STATE_WARN(val & SPRITE_ENABLE,
1321 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1322 plane_name(pipe), pipe_name(pipe));
1323 } else if (INTEL_INFO(dev)->gen >= 5) {
1324 reg = DVSCNTR(pipe);
1325 val = I915_READ(reg);
1326 I915_STATE_WARN(val & DVS_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 plane_name(pipe), pipe_name(pipe));
1329 }
1330 }
1331
1332 static void assert_vblank_disabled(struct drm_crtc *crtc)
1333 {
1334 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1335 drm_crtc_vblank_put(crtc);
1336 }
1337
1338 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1339 {
1340 u32 val;
1341 bool enabled;
1342
1343 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1344
1345 val = I915_READ(PCH_DREF_CONTROL);
1346 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1347 DREF_SUPERSPREAD_SOURCE_MASK));
1348 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1349 }
1350
1351 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe)
1353 {
1354 int reg;
1355 u32 val;
1356 bool enabled;
1357
1358 reg = PCH_TRANSCONF(pipe);
1359 val = I915_READ(reg);
1360 enabled = !!(val & TRANS_ENABLE);
1361 I915_STATE_WARN(enabled,
1362 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 pipe_name(pipe));
1364 }
1365
1366 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1367 enum pipe pipe, u32 port_sel, u32 val)
1368 {
1369 if ((val & DP_PORT_EN) == 0)
1370 return false;
1371
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1374 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1375 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1376 return false;
1377 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1378 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1379 return false;
1380 } else {
1381 if ((val & DP_PIPE_MASK) != (pipe << 30))
1382 return false;
1383 }
1384 return true;
1385 }
1386
1387 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, u32 val)
1389 {
1390 if ((val & SDVO_ENABLE) == 0)
1391 return false;
1392
1393 if (HAS_PCH_CPT(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1395 return false;
1396 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1397 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1398 return false;
1399 } else {
1400 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1401 return false;
1402 }
1403 return true;
1404 }
1405
1406 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1407 enum pipe pipe, u32 val)
1408 {
1409 if ((val & LVDS_PORT_EN) == 0)
1410 return false;
1411
1412 if (HAS_PCH_CPT(dev_priv->dev)) {
1413 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1414 return false;
1415 } else {
1416 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1417 return false;
1418 }
1419 return true;
1420 }
1421
1422 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe, u32 val)
1424 {
1425 if ((val & ADPA_DAC_ENABLE) == 0)
1426 return false;
1427 if (HAS_PCH_CPT(dev_priv->dev)) {
1428 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1429 return false;
1430 } else {
1431 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1432 return false;
1433 }
1434 return true;
1435 }
1436
1437 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, int reg, u32 port_sel)
1439 {
1440 u32 val = I915_READ(reg);
1441 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1442 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1443 reg, pipe_name(pipe));
1444
1445 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1446 && (val & DP_PIPEB_SELECT),
1447 "IBX PCH dp port still using transcoder B\n");
1448 }
1449
1450 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg)
1452 {
1453 u32 val = I915_READ(reg);
1454 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1455 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1459 && (val & SDVO_PIPE_B_SELECT),
1460 "IBX PCH hdmi port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 int reg;
1467 u32 val;
1468
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1472
1473 reg = PCH_ADPA;
1474 val = I915_READ(reg);
1475 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1476 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 pipe_name(pipe));
1478
1479 reg = PCH_LVDS;
1480 val = I915_READ(reg);
1481 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1482 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1483 pipe_name(pipe));
1484
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1488 }
1489
1490 static void intel_init_dpio(struct drm_device *dev)
1491 {
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493
1494 if (!IS_VALLEYVIEW(dev))
1495 return;
1496
1497 /*
1498 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1499 * CHV x1 PHY (DP/HDMI D)
1500 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1501 */
1502 if (IS_CHERRYVIEW(dev)) {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1505 } else {
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1507 }
1508 }
1509
1510 static void vlv_enable_pll(struct intel_crtc *crtc,
1511 const struct intel_crtc_state *pipe_config)
1512 {
1513 struct drm_device *dev = crtc->base.dev;
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 int reg = DPLL(crtc->pipe);
1516 u32 dpll = pipe_config->dpll_hw_state.dpll;
1517
1518 assert_pipe_disabled(dev_priv, crtc->pipe);
1519
1520 /* No really, not for ILK+ */
1521 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1522
1523 /* PLL is protected by panel, make sure we can write it */
1524 if (IS_MOBILE(dev_priv->dev))
1525 assert_panel_unlocked(dev_priv, crtc->pipe);
1526
1527 I915_WRITE(reg, dpll);
1528 POSTING_READ(reg);
1529 udelay(150);
1530
1531 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1532 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1533
1534 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1535 POSTING_READ(DPLL_MD(crtc->pipe));
1536
1537 /* We do this three times for luck */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 I915_WRITE(reg, dpll);
1545 POSTING_READ(reg);
1546 udelay(150); /* wait for warmup */
1547 }
1548
1549 static void chv_enable_pll(struct intel_crtc *crtc,
1550 const struct intel_crtc_state *pipe_config)
1551 {
1552 struct drm_device *dev = crtc->base.dev;
1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 int pipe = crtc->pipe;
1555 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1556 u32 tmp;
1557
1558 assert_pipe_disabled(dev_priv, crtc->pipe);
1559
1560 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1561
1562 mutex_lock(&dev_priv->dpio_lock);
1563
1564 /* Enable back the 10bit clock to display controller */
1565 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1566 tmp |= DPIO_DCLKP_EN;
1567 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1568
1569 /*
1570 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1571 */
1572 udelay(1);
1573
1574 /* Enable PLL */
1575 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1576
1577 /* Check PLL is locked */
1578 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1579 DRM_ERROR("PLL %d failed to lock\n", pipe);
1580
1581 /* not sure when this should be written */
1582 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1583 POSTING_READ(DPLL_MD(pipe));
1584
1585 mutex_unlock(&dev_priv->dpio_lock);
1586 }
1587
1588 static int intel_num_dvo_pipes(struct drm_device *dev)
1589 {
1590 struct intel_crtc *crtc;
1591 int count = 0;
1592
1593 for_each_intel_crtc(dev, crtc)
1594 count += crtc->active &&
1595 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1596
1597 return count;
1598 }
1599
1600 static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 int reg = DPLL(crtc->pipe);
1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* No really, not for ILK+ */
1610 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1611
1612 /* PLL is protected by panel, make sure we can write it */
1613 if (IS_MOBILE(dev) && !IS_I830(dev))
1614 assert_panel_unlocked(dev_priv, crtc->pipe);
1615
1616 /* Enable DVO 2x clock on both PLLs if necessary */
1617 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1618 /*
1619 * It appears to be important that we don't enable this
1620 * for the current pipe before otherwise configuring the
1621 * PLL. No idea how this should be handled if multiple
1622 * DVO outputs are enabled simultaneosly.
1623 */
1624 dpll |= DPLL_DVO_2X_MODE;
1625 I915_WRITE(DPLL(!crtc->pipe),
1626 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1627 }
1628
1629 /* Wait for the clocks to stabilize. */
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (INTEL_INFO(dev)->gen >= 4) {
1634 I915_WRITE(DPLL_MD(crtc->pipe),
1635 crtc->config->dpll_hw_state.dpll_md);
1636 } else {
1637 /* The pixel multiplier can only be updated once the
1638 * DPLL is enabled and the clocks are stable.
1639 *
1640 * So write it again.
1641 */
1642 I915_WRITE(reg, dpll);
1643 }
1644
1645 /* We do this three times for luck */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 I915_WRITE(reg, dpll);
1653 POSTING_READ(reg);
1654 udelay(150); /* wait for warmup */
1655 }
1656
1657 /**
1658 * i9xx_disable_pll - disable a PLL
1659 * @dev_priv: i915 private structure
1660 * @pipe: pipe PLL to disable
1661 *
1662 * Disable the PLL for @pipe, making sure the pipe is off first.
1663 *
1664 * Note! This is for pre-ILK only.
1665 */
1666 static void i9xx_disable_pll(struct intel_crtc *crtc)
1667 {
1668 struct drm_device *dev = crtc->base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 enum pipe pipe = crtc->pipe;
1671
1672 /* Disable DVO 2x clock on both PLLs if necessary */
1673 if (IS_I830(dev) &&
1674 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1675 intel_num_dvo_pipes(dev) == 1) {
1676 I915_WRITE(DPLL(PIPE_B),
1677 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1678 I915_WRITE(DPLL(PIPE_A),
1679 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1680 }
1681
1682 /* Don't disable pipe or pipe PLLs if needed */
1683 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1684 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1685 return;
1686
1687 /* Make sure the pipe isn't still relying on us */
1688 assert_pipe_disabled(dev_priv, pipe);
1689
1690 I915_WRITE(DPLL(pipe), 0);
1691 POSTING_READ(DPLL(pipe));
1692 }
1693
1694 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 u32 val = 0;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /*
1702 * Leave integrated clock source and reference clock enabled for pipe B.
1703 * The latter is needed for VGA hotplug / manual detection.
1704 */
1705 if (pipe == PIPE_B)
1706 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 }
1711
1712 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1713 {
1714 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1715 u32 val;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 /* Set PLL en = 0 */
1721 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1722 if (pipe != PIPE_A)
1723 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1726
1727 mutex_lock(&dev_priv->dpio_lock);
1728
1729 /* Disable 10bit clock to display controller */
1730 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1731 val &= ~DPIO_DCLKP_EN;
1732 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1733
1734 /* disable left/right clock distribution */
1735 if (pipe != PIPE_B) {
1736 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1737 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1738 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1739 } else {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1741 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1743 }
1744
1745 mutex_unlock(&dev_priv->dpio_lock);
1746 }
1747
1748 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1749 struct intel_digital_port *dport)
1750 {
1751 u32 port_mask;
1752 int dpll_reg;
1753
1754 switch (dport->port) {
1755 case PORT_B:
1756 port_mask = DPLL_PORTB_READY_MASK;
1757 dpll_reg = DPLL(0);
1758 break;
1759 case PORT_C:
1760 port_mask = DPLL_PORTC_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_D:
1764 port_mask = DPLL_PORTD_READY_MASK;
1765 dpll_reg = DPIO_PHY_STATUS;
1766 break;
1767 default:
1768 BUG();
1769 }
1770
1771 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1772 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1773 port_name(dport->port), I915_READ(dpll_reg));
1774 }
1775
1776 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 WARN_ON(!pll->config.crtc_mask);
1786 if (pll->active == 0) {
1787 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1788 WARN_ON(pll->on);
1789 assert_shared_dpll_disabled(dev_priv, pll);
1790
1791 pll->mode_set(dev_priv, pll);
1792 }
1793 }
1794
1795 /**
1796 * intel_enable_shared_dpll - enable PCH PLL
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe PLL to enable
1799 *
1800 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1801 * drives the transcoder clock.
1802 */
1803 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 if (WARN_ON(pll->config.crtc_mask == 0))
1813 return;
1814
1815 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1816 pll->name, pll->active, pll->on,
1817 crtc->base.base.id);
1818
1819 if (pll->active++) {
1820 WARN_ON(!pll->on);
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 return;
1823 }
1824 WARN_ON(pll->on);
1825
1826 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1827
1828 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1829 pll->enable(dev_priv, pll);
1830 pll->on = true;
1831 }
1832
1833 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841 if (WARN_ON(pll == NULL))
1842 return;
1843
1844 if (WARN_ON(pll->config.crtc_mask == 0))
1845 return;
1846
1847 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1848 pll->name, pll->active, pll->on,
1849 crtc->base.base.id);
1850
1851 if (WARN_ON(pll->active == 0)) {
1852 assert_shared_dpll_disabled(dev_priv, pll);
1853 return;
1854 }
1855
1856 assert_shared_dpll_enabled(dev_priv, pll);
1857 WARN_ON(!pll->on);
1858 if (--pll->active)
1859 return;
1860
1861 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1862 pll->disable(dev_priv, pll);
1863 pll->on = false;
1864
1865 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1866 }
1867
1868 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1869 enum pipe pipe)
1870 {
1871 struct drm_device *dev = dev_priv->dev;
1872 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1874 uint32_t reg, val, pipeconf_val;
1875
1876 /* PCH only available on ILK+ */
1877 BUG_ON(!HAS_PCH_SPLIT(dev));
1878
1879 /* Make sure PCH DPLL is enabled */
1880 assert_shared_dpll_enabled(dev_priv,
1881 intel_crtc_to_shared_dpll(intel_crtc));
1882
1883 /* FDI must be feeding us bits for PCH ports */
1884 assert_fdi_tx_enabled(dev_priv, pipe);
1885 assert_fdi_rx_enabled(dev_priv, pipe);
1886
1887 if (HAS_PCH_CPT(dev)) {
1888 /* Workaround: Set the timing override bit before enabling the
1889 * pch transcoder. */
1890 reg = TRANS_CHICKEN2(pipe);
1891 val = I915_READ(reg);
1892 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1893 I915_WRITE(reg, val);
1894 }
1895
1896 reg = PCH_TRANSCONF(pipe);
1897 val = I915_READ(reg);
1898 pipeconf_val = I915_READ(PIPECONF(pipe));
1899
1900 if (HAS_PCH_IBX(dev_priv->dev)) {
1901 /*
1902 * make the BPC in transcoder be consistent with
1903 * that in pipeconf reg.
1904 */
1905 val &= ~PIPECONF_BPC_MASK;
1906 val |= pipeconf_val & PIPECONF_BPC_MASK;
1907 }
1908
1909 val &= ~TRANS_INTERLACE_MASK;
1910 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1911 if (HAS_PCH_IBX(dev_priv->dev) &&
1912 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1913 val |= TRANS_LEGACY_INTERLACED_ILK;
1914 else
1915 val |= TRANS_INTERLACED;
1916 else
1917 val |= TRANS_PROGRESSIVE;
1918
1919 I915_WRITE(reg, val | TRANS_ENABLE);
1920 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1921 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1922 }
1923
1924 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1925 enum transcoder cpu_transcoder)
1926 {
1927 u32 val, pipeconf_val;
1928
1929 /* PCH only available on ILK+ */
1930 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1931
1932 /* FDI must be feeding us bits for PCH ports */
1933 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1934 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1935
1936 /* Workaround: set timing override bit. */
1937 val = I915_READ(_TRANSA_CHICKEN2);
1938 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1939 I915_WRITE(_TRANSA_CHICKEN2, val);
1940
1941 val = TRANS_ENABLE;
1942 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1943
1944 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1945 PIPECONF_INTERLACED_ILK)
1946 val |= TRANS_INTERLACED;
1947 else
1948 val |= TRANS_PROGRESSIVE;
1949
1950 I915_WRITE(LPT_TRANSCONF, val);
1951 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1952 DRM_ERROR("Failed to enable PCH transcoder\n");
1953 }
1954
1955 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1956 enum pipe pipe)
1957 {
1958 struct drm_device *dev = dev_priv->dev;
1959 uint32_t reg, val;
1960
1961 /* FDI relies on the transcoder */
1962 assert_fdi_tx_disabled(dev_priv, pipe);
1963 assert_fdi_rx_disabled(dev_priv, pipe);
1964
1965 /* Ports must be off as well */
1966 assert_pch_ports_disabled(dev_priv, pipe);
1967
1968 reg = PCH_TRANSCONF(pipe);
1969 val = I915_READ(reg);
1970 val &= ~TRANS_ENABLE;
1971 I915_WRITE(reg, val);
1972 /* wait for PCH transcoder off, transcoder state */
1973 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1974 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1975
1976 if (!HAS_PCH_IBX(dev)) {
1977 /* Workaround: Clear the timing override chicken bit again. */
1978 reg = TRANS_CHICKEN2(pipe);
1979 val = I915_READ(reg);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(reg, val);
1982 }
1983 }
1984
1985 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1986 {
1987 u32 val;
1988
1989 val = I915_READ(LPT_TRANSCONF);
1990 val &= ~TRANS_ENABLE;
1991 I915_WRITE(LPT_TRANSCONF, val);
1992 /* wait for PCH transcoder off, transcoder state */
1993 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1994 DRM_ERROR("Failed to disable PCH transcoder\n");
1995
1996 /* Workaround: clear timing override bit. */
1997 val = I915_READ(_TRANSA_CHICKEN2);
1998 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1999 I915_WRITE(_TRANSA_CHICKEN2, val);
2000 }
2001
2002 /**
2003 * intel_enable_pipe - enable a pipe, asserting requirements
2004 * @crtc: crtc responsible for the pipe
2005 *
2006 * Enable @crtc's pipe, making sure that various hardware specific requirements
2007 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2008 */
2009 static void intel_enable_pipe(struct intel_crtc *crtc)
2010 {
2011 struct drm_device *dev = crtc->base.dev;
2012 struct drm_i915_private *dev_priv = dev->dev_private;
2013 enum pipe pipe = crtc->pipe;
2014 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2015 pipe);
2016 enum pipe pch_transcoder;
2017 int reg;
2018 u32 val;
2019
2020 assert_planes_disabled(dev_priv, pipe);
2021 assert_cursor_disabled(dev_priv, pipe);
2022 assert_sprites_disabled(dev_priv, pipe);
2023
2024 if (HAS_PCH_LPT(dev_priv->dev))
2025 pch_transcoder = TRANSCODER_A;
2026 else
2027 pch_transcoder = pipe;
2028
2029 /*
2030 * A pipe without a PLL won't actually be able to drive bits from
2031 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2032 * need the check.
2033 */
2034 if (!HAS_PCH_SPLIT(dev_priv->dev))
2035 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2036 assert_dsi_pll_enabled(dev_priv);
2037 else
2038 assert_pll_enabled(dev_priv, pipe);
2039 else {
2040 if (crtc->config->has_pch_encoder) {
2041 /* if driving the PCH, we need FDI enabled */
2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2043 assert_fdi_tx_pll_enabled(dev_priv,
2044 (enum pipe) cpu_transcoder);
2045 }
2046 /* FIXME: assert CPU port conditions for SNB+ */
2047 }
2048
2049 reg = PIPECONF(cpu_transcoder);
2050 val = I915_READ(reg);
2051 if (val & PIPECONF_ENABLE) {
2052 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2053 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2054 return;
2055 }
2056
2057 I915_WRITE(reg, val | PIPECONF_ENABLE);
2058 POSTING_READ(reg);
2059 }
2060
2061 /**
2062 * intel_disable_pipe - disable a pipe, asserting requirements
2063 * @crtc: crtc whose pipes is to be disabled
2064 *
2065 * Disable the pipe of @crtc, making sure that various hardware
2066 * specific requirements are met, if applicable, e.g. plane
2067 * disabled, panel fitter off, etc.
2068 *
2069 * Will wait until the pipe has shut down before returning.
2070 */
2071 static void intel_disable_pipe(struct intel_crtc *crtc)
2072 {
2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2075 enum pipe pipe = crtc->pipe;
2076 int reg;
2077 u32 val;
2078
2079 /*
2080 * Make sure planes won't keep trying to pump pixels to us,
2081 * or we might hang the display.
2082 */
2083 assert_planes_disabled(dev_priv, pipe);
2084 assert_cursor_disabled(dev_priv, pipe);
2085 assert_sprites_disabled(dev_priv, pipe);
2086
2087 reg = PIPECONF(cpu_transcoder);
2088 val = I915_READ(reg);
2089 if ((val & PIPECONF_ENABLE) == 0)
2090 return;
2091
2092 /*
2093 * Double wide has implications for planes
2094 * so best keep it disabled when not needed.
2095 */
2096 if (crtc->config->double_wide)
2097 val &= ~PIPECONF_DOUBLE_WIDE;
2098
2099 /* Don't disable pipe or pipe PLLs if needed */
2100 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2101 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2102 val &= ~PIPECONF_ENABLE;
2103
2104 I915_WRITE(reg, val);
2105 if ((val & PIPECONF_ENABLE) == 0)
2106 intel_wait_for_pipe_off(crtc);
2107 }
2108
2109 /*
2110 * Plane regs are double buffered, going from enabled->disabled needs a
2111 * trigger in order to latch. The display address reg provides this.
2112 */
2113 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2114 enum plane plane)
2115 {
2116 struct drm_device *dev = dev_priv->dev;
2117 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2118
2119 I915_WRITE(reg, I915_READ(reg));
2120 POSTING_READ(reg);
2121 }
2122
2123 /**
2124 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2125 * @plane: plane to be enabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Enable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2138 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2139
2140 if (intel_crtc->primary_enabled)
2141 return;
2142
2143 intel_crtc->primary_enabled = true;
2144
2145 dev_priv->display.update_primary_plane(crtc, plane->fb,
2146 crtc->x, crtc->y);
2147
2148 /*
2149 * BDW signals flip done immediately if the plane
2150 * is disabled, even if the plane enable is already
2151 * armed to occur at the next vblank :(
2152 */
2153 if (IS_BROADWELL(dev))
2154 intel_wait_for_vblank(dev, intel_crtc->pipe);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @plane: plane to be disabled
2160 * @crtc: crtc for the plane
2161 *
2162 * Disable @plane on @crtc, making sure that the pipe is running first.
2163 */
2164 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2165 struct drm_crtc *crtc)
2166 {
2167 struct drm_device *dev = plane->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170
2171 if (WARN_ON(!intel_crtc->active))
2172 return;
2173
2174 if (!intel_crtc->primary_enabled)
2175 return;
2176
2177 intel_crtc->primary_enabled = false;
2178
2179 dev_priv->display.update_primary_plane(crtc, plane->fb,
2180 crtc->x, crtc->y);
2181 }
2182
2183 static bool need_vtd_wa(struct drm_device *dev)
2184 {
2185 #ifdef CONFIG_INTEL_IOMMU
2186 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2187 return true;
2188 #endif
2189 return false;
2190 }
2191
2192 int
2193 intel_fb_align_height(struct drm_device *dev, int height,
2194 uint32_t pixel_format,
2195 uint64_t fb_format_modifier)
2196 {
2197 int tile_height;
2198
2199 tile_height = fb_format_modifier == I915_FORMAT_MOD_X_TILED ?
2200 (IS_GEN2(dev) ? 16 : 8) : 1;
2201
2202 return ALIGN(height, tile_height);
2203 }
2204
2205 int
2206 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2207 struct drm_framebuffer *fb,
2208 struct intel_engine_cs *pipelined)
2209 {
2210 struct drm_device *dev = fb->dev;
2211 struct drm_i915_private *dev_priv = dev->dev_private;
2212 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2213 u32 alignment;
2214 int ret;
2215
2216 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2217
2218 switch (fb->modifier[0]) {
2219 case DRM_FORMAT_MOD_NONE:
2220 if (INTEL_INFO(dev)->gen >= 9)
2221 alignment = 256 * 1024;
2222 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2223 alignment = 128 * 1024;
2224 else if (INTEL_INFO(dev)->gen >= 4)
2225 alignment = 4 * 1024;
2226 else
2227 alignment = 64 * 1024;
2228 break;
2229 case I915_FORMAT_MOD_X_TILED:
2230 if (INTEL_INFO(dev)->gen >= 9)
2231 alignment = 256 * 1024;
2232 else {
2233 /* pin() will align the object as required by fence */
2234 alignment = 0;
2235 }
2236 break;
2237 case I915_FORMAT_MOD_Y_TILED:
2238 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2239 return -EINVAL;
2240 default:
2241 MISSING_CASE(fb->modifier[0]);
2242 return -EINVAL;
2243 }
2244
2245 /* Note that the w/a also requires 64 PTE of padding following the
2246 * bo. We currently fill all unused PTE with the shadow page and so
2247 * we should always have valid PTE following the scanout preventing
2248 * the VT-d warning.
2249 */
2250 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2251 alignment = 256 * 1024;
2252
2253 /*
2254 * Global gtt pte registers are special registers which actually forward
2255 * writes to a chunk of system memory. Which means that there is no risk
2256 * that the register values disappear as soon as we call
2257 * intel_runtime_pm_put(), so it is correct to wrap only the
2258 * pin/unpin/fence and not more.
2259 */
2260 intel_runtime_pm_get(dev_priv);
2261
2262 dev_priv->mm.interruptible = false;
2263 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2264 if (ret)
2265 goto err_interruptible;
2266
2267 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2268 * fence, whereas 965+ only requires a fence if using
2269 * framebuffer compression. For simplicity, we always install
2270 * a fence as the cost is not that onerous.
2271 */
2272 ret = i915_gem_object_get_fence(obj);
2273 if (ret)
2274 goto err_unpin;
2275
2276 i915_gem_object_pin_fence(obj);
2277
2278 dev_priv->mm.interruptible = true;
2279 intel_runtime_pm_put(dev_priv);
2280 return 0;
2281
2282 err_unpin:
2283 i915_gem_object_unpin_from_display_plane(obj);
2284 err_interruptible:
2285 dev_priv->mm.interruptible = true;
2286 intel_runtime_pm_put(dev_priv);
2287 return ret;
2288 }
2289
2290 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2291 {
2292 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2293
2294 i915_gem_object_unpin_fence(obj);
2295 i915_gem_object_unpin_from_display_plane(obj);
2296 }
2297
2298 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2299 * is assumed to be a power-of-two. */
2300 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2301 unsigned int tiling_mode,
2302 unsigned int cpp,
2303 unsigned int pitch)
2304 {
2305 if (tiling_mode != I915_TILING_NONE) {
2306 unsigned int tile_rows, tiles;
2307
2308 tile_rows = *y / 8;
2309 *y %= 8;
2310
2311 tiles = *x / (512/cpp);
2312 *x %= 512/cpp;
2313
2314 return tile_rows * pitch * 8 + tiles * 4096;
2315 } else {
2316 unsigned int offset;
2317
2318 offset = *y * pitch + *x * cpp;
2319 *y = 0;
2320 *x = (offset & 4095) / cpp;
2321 return offset & -4096;
2322 }
2323 }
2324
2325 static int i9xx_format_to_fourcc(int format)
2326 {
2327 switch (format) {
2328 case DISPPLANE_8BPP:
2329 return DRM_FORMAT_C8;
2330 case DISPPLANE_BGRX555:
2331 return DRM_FORMAT_XRGB1555;
2332 case DISPPLANE_BGRX565:
2333 return DRM_FORMAT_RGB565;
2334 default:
2335 case DISPPLANE_BGRX888:
2336 return DRM_FORMAT_XRGB8888;
2337 case DISPPLANE_RGBX888:
2338 return DRM_FORMAT_XBGR8888;
2339 case DISPPLANE_BGRX101010:
2340 return DRM_FORMAT_XRGB2101010;
2341 case DISPPLANE_RGBX101010:
2342 return DRM_FORMAT_XBGR2101010;
2343 }
2344 }
2345
2346 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2347 {
2348 switch (format) {
2349 case PLANE_CTL_FORMAT_RGB_565:
2350 return DRM_FORMAT_RGB565;
2351 default:
2352 case PLANE_CTL_FORMAT_XRGB_8888:
2353 if (rgb_order) {
2354 if (alpha)
2355 return DRM_FORMAT_ABGR8888;
2356 else
2357 return DRM_FORMAT_XBGR8888;
2358 } else {
2359 if (alpha)
2360 return DRM_FORMAT_ARGB8888;
2361 else
2362 return DRM_FORMAT_XRGB8888;
2363 }
2364 case PLANE_CTL_FORMAT_XRGB_2101010:
2365 if (rgb_order)
2366 return DRM_FORMAT_XBGR2101010;
2367 else
2368 return DRM_FORMAT_XRGB2101010;
2369 }
2370 }
2371
2372 static bool
2373 intel_alloc_plane_obj(struct intel_crtc *crtc,
2374 struct intel_initial_plane_config *plane_config)
2375 {
2376 struct drm_device *dev = crtc->base.dev;
2377 struct drm_i915_gem_object *obj = NULL;
2378 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2379 struct drm_framebuffer *fb = &plane_config->fb->base;
2380 u32 base = plane_config->base;
2381
2382 if (plane_config->size == 0)
2383 return false;
2384
2385 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2386 plane_config->size);
2387 if (!obj)
2388 return false;
2389
2390 obj->tiling_mode = plane_config->tiling;
2391 if (obj->tiling_mode == I915_TILING_X)
2392 obj->stride = fb->pitches[0];
2393
2394 mode_cmd.pixel_format = fb->pixel_format;
2395 mode_cmd.width = fb->width;
2396 mode_cmd.height = fb->height;
2397 mode_cmd.pitches[0] = fb->pitches[0];
2398 mode_cmd.modifier[0] = fb->modifier[0];
2399 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2400
2401 mutex_lock(&dev->struct_mutex);
2402
2403 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2404 &mode_cmd, obj)) {
2405 DRM_DEBUG_KMS("intel fb init failed\n");
2406 goto out_unref_obj;
2407 }
2408
2409 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2410 mutex_unlock(&dev->struct_mutex);
2411
2412 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2413 return true;
2414
2415 out_unref_obj:
2416 drm_gem_object_unreference(&obj->base);
2417 mutex_unlock(&dev->struct_mutex);
2418 return false;
2419 }
2420
2421 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2422 static void
2423 update_state_fb(struct drm_plane *plane)
2424 {
2425 if (plane->fb == plane->state->fb)
2426 return;
2427
2428 if (plane->state->fb)
2429 drm_framebuffer_unreference(plane->state->fb);
2430 plane->state->fb = plane->fb;
2431 if (plane->state->fb)
2432 drm_framebuffer_reference(plane->state->fb);
2433 }
2434
2435 static void
2436 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2437 struct intel_initial_plane_config *plane_config)
2438 {
2439 struct drm_device *dev = intel_crtc->base.dev;
2440 struct drm_i915_private *dev_priv = dev->dev_private;
2441 struct drm_crtc *c;
2442 struct intel_crtc *i;
2443 struct drm_i915_gem_object *obj;
2444
2445 if (!plane_config->fb)
2446 return;
2447
2448 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2449 struct drm_plane *primary = intel_crtc->base.primary;
2450
2451 primary->fb = &plane_config->fb->base;
2452 primary->state->crtc = &intel_crtc->base;
2453 update_state_fb(primary);
2454
2455 return;
2456 }
2457
2458 kfree(plane_config->fb);
2459
2460 /*
2461 * Failed to alloc the obj, check to see if we should share
2462 * an fb with another CRTC instead
2463 */
2464 for_each_crtc(dev, c) {
2465 i = to_intel_crtc(c);
2466
2467 if (c == &intel_crtc->base)
2468 continue;
2469
2470 if (!i->active)
2471 continue;
2472
2473 obj = intel_fb_obj(c->primary->fb);
2474 if (obj == NULL)
2475 continue;
2476
2477 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2478 struct drm_plane *primary = intel_crtc->base.primary;
2479
2480 if (obj->tiling_mode != I915_TILING_NONE)
2481 dev_priv->preserve_bios_swizzle = true;
2482
2483 drm_framebuffer_reference(c->primary->fb);
2484 primary->fb = c->primary->fb;
2485 primary->state->crtc = &intel_crtc->base;
2486 update_state_fb(intel_crtc->base.primary);
2487 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2488 break;
2489 }
2490 }
2491
2492 }
2493
2494 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2495 struct drm_framebuffer *fb,
2496 int x, int y)
2497 {
2498 struct drm_device *dev = crtc->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501 struct drm_i915_gem_object *obj;
2502 int plane = intel_crtc->plane;
2503 unsigned long linear_offset;
2504 u32 dspcntr;
2505 u32 reg = DSPCNTR(plane);
2506 int pixel_size;
2507
2508 if (!intel_crtc->primary_enabled) {
2509 I915_WRITE(reg, 0);
2510 if (INTEL_INFO(dev)->gen >= 4)
2511 I915_WRITE(DSPSURF(plane), 0);
2512 else
2513 I915_WRITE(DSPADDR(plane), 0);
2514 POSTING_READ(reg);
2515 return;
2516 }
2517
2518 obj = intel_fb_obj(fb);
2519 if (WARN_ON(obj == NULL))
2520 return;
2521
2522 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2523
2524 dspcntr = DISPPLANE_GAMMA_ENABLE;
2525
2526 dspcntr |= DISPLAY_PLANE_ENABLE;
2527
2528 if (INTEL_INFO(dev)->gen < 4) {
2529 if (intel_crtc->pipe == PIPE_B)
2530 dspcntr |= DISPPLANE_SEL_PIPE_B;
2531
2532 /* pipesrc and dspsize control the size that is scaled from,
2533 * which should always be the user's requested size.
2534 */
2535 I915_WRITE(DSPSIZE(plane),
2536 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2537 (intel_crtc->config->pipe_src_w - 1));
2538 I915_WRITE(DSPPOS(plane), 0);
2539 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2540 I915_WRITE(PRIMSIZE(plane),
2541 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2542 (intel_crtc->config->pipe_src_w - 1));
2543 I915_WRITE(PRIMPOS(plane), 0);
2544 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2545 }
2546
2547 switch (fb->pixel_format) {
2548 case DRM_FORMAT_C8:
2549 dspcntr |= DISPPLANE_8BPP;
2550 break;
2551 case DRM_FORMAT_XRGB1555:
2552 case DRM_FORMAT_ARGB1555:
2553 dspcntr |= DISPPLANE_BGRX555;
2554 break;
2555 case DRM_FORMAT_RGB565:
2556 dspcntr |= DISPPLANE_BGRX565;
2557 break;
2558 case DRM_FORMAT_XRGB8888:
2559 case DRM_FORMAT_ARGB8888:
2560 dspcntr |= DISPPLANE_BGRX888;
2561 break;
2562 case DRM_FORMAT_XBGR8888:
2563 case DRM_FORMAT_ABGR8888:
2564 dspcntr |= DISPPLANE_RGBX888;
2565 break;
2566 case DRM_FORMAT_XRGB2101010:
2567 case DRM_FORMAT_ARGB2101010:
2568 dspcntr |= DISPPLANE_BGRX101010;
2569 break;
2570 case DRM_FORMAT_XBGR2101010:
2571 case DRM_FORMAT_ABGR2101010:
2572 dspcntr |= DISPPLANE_RGBX101010;
2573 break;
2574 default:
2575 BUG();
2576 }
2577
2578 if (INTEL_INFO(dev)->gen >= 4 &&
2579 obj->tiling_mode != I915_TILING_NONE)
2580 dspcntr |= DISPPLANE_TILED;
2581
2582 if (IS_G4X(dev))
2583 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2584
2585 linear_offset = y * fb->pitches[0] + x * pixel_size;
2586
2587 if (INTEL_INFO(dev)->gen >= 4) {
2588 intel_crtc->dspaddr_offset =
2589 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2590 pixel_size,
2591 fb->pitches[0]);
2592 linear_offset -= intel_crtc->dspaddr_offset;
2593 } else {
2594 intel_crtc->dspaddr_offset = linear_offset;
2595 }
2596
2597 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2598 dspcntr |= DISPPLANE_ROTATE_180;
2599
2600 x += (intel_crtc->config->pipe_src_w - 1);
2601 y += (intel_crtc->config->pipe_src_h - 1);
2602
2603 /* Finding the last pixel of the last line of the display
2604 data and adding to linear_offset*/
2605 linear_offset +=
2606 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2607 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2608 }
2609
2610 I915_WRITE(reg, dspcntr);
2611
2612 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2613 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2614 fb->pitches[0]);
2615 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2616 if (INTEL_INFO(dev)->gen >= 4) {
2617 I915_WRITE(DSPSURF(plane),
2618 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2619 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2620 I915_WRITE(DSPLINOFF(plane), linear_offset);
2621 } else
2622 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2623 POSTING_READ(reg);
2624 }
2625
2626 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2627 struct drm_framebuffer *fb,
2628 int x, int y)
2629 {
2630 struct drm_device *dev = crtc->dev;
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2633 struct drm_i915_gem_object *obj;
2634 int plane = intel_crtc->plane;
2635 unsigned long linear_offset;
2636 u32 dspcntr;
2637 u32 reg = DSPCNTR(plane);
2638 int pixel_size;
2639
2640 if (!intel_crtc->primary_enabled) {
2641 I915_WRITE(reg, 0);
2642 I915_WRITE(DSPSURF(plane), 0);
2643 POSTING_READ(reg);
2644 return;
2645 }
2646
2647 obj = intel_fb_obj(fb);
2648 if (WARN_ON(obj == NULL))
2649 return;
2650
2651 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2652
2653 dspcntr = DISPPLANE_GAMMA_ENABLE;
2654
2655 dspcntr |= DISPLAY_PLANE_ENABLE;
2656
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2658 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2659
2660 switch (fb->pixel_format) {
2661 case DRM_FORMAT_C8:
2662 dspcntr |= DISPPLANE_8BPP;
2663 break;
2664 case DRM_FORMAT_RGB565:
2665 dspcntr |= DISPPLANE_BGRX565;
2666 break;
2667 case DRM_FORMAT_XRGB8888:
2668 case DRM_FORMAT_ARGB8888:
2669 dspcntr |= DISPPLANE_BGRX888;
2670 break;
2671 case DRM_FORMAT_XBGR8888:
2672 case DRM_FORMAT_ABGR8888:
2673 dspcntr |= DISPPLANE_RGBX888;
2674 break;
2675 case DRM_FORMAT_XRGB2101010:
2676 case DRM_FORMAT_ARGB2101010:
2677 dspcntr |= DISPPLANE_BGRX101010;
2678 break;
2679 case DRM_FORMAT_XBGR2101010:
2680 case DRM_FORMAT_ABGR2101010:
2681 dspcntr |= DISPPLANE_RGBX101010;
2682 break;
2683 default:
2684 BUG();
2685 }
2686
2687 if (obj->tiling_mode != I915_TILING_NONE)
2688 dspcntr |= DISPPLANE_TILED;
2689
2690 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2691 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2692
2693 linear_offset = y * fb->pitches[0] + x * pixel_size;
2694 intel_crtc->dspaddr_offset =
2695 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2696 pixel_size,
2697 fb->pitches[0]);
2698 linear_offset -= intel_crtc->dspaddr_offset;
2699 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2700 dspcntr |= DISPPLANE_ROTATE_180;
2701
2702 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2703 x += (intel_crtc->config->pipe_src_w - 1);
2704 y += (intel_crtc->config->pipe_src_h - 1);
2705
2706 /* Finding the last pixel of the last line of the display
2707 data and adding to linear_offset*/
2708 linear_offset +=
2709 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2710 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2711 }
2712 }
2713
2714 I915_WRITE(reg, dspcntr);
2715
2716 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2717 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2718 fb->pitches[0]);
2719 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2720 I915_WRITE(DSPSURF(plane),
2721 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2722 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2723 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2724 } else {
2725 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2726 I915_WRITE(DSPLINOFF(plane), linear_offset);
2727 }
2728 POSTING_READ(reg);
2729 }
2730
2731 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2732 struct drm_framebuffer *fb,
2733 int x, int y)
2734 {
2735 struct drm_device *dev = crtc->dev;
2736 struct drm_i915_private *dev_priv = dev->dev_private;
2737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2738 struct intel_framebuffer *intel_fb;
2739 struct drm_i915_gem_object *obj;
2740 int pipe = intel_crtc->pipe;
2741 u32 plane_ctl, stride;
2742
2743 if (!intel_crtc->primary_enabled) {
2744 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2745 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2746 POSTING_READ(PLANE_CTL(pipe, 0));
2747 return;
2748 }
2749
2750 plane_ctl = PLANE_CTL_ENABLE |
2751 PLANE_CTL_PIPE_GAMMA_ENABLE |
2752 PLANE_CTL_PIPE_CSC_ENABLE;
2753
2754 switch (fb->pixel_format) {
2755 case DRM_FORMAT_RGB565:
2756 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2757 break;
2758 case DRM_FORMAT_XRGB8888:
2759 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2760 break;
2761 case DRM_FORMAT_XBGR8888:
2762 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2763 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2764 break;
2765 case DRM_FORMAT_XRGB2101010:
2766 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2767 break;
2768 case DRM_FORMAT_XBGR2101010:
2769 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2770 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2771 break;
2772 default:
2773 BUG();
2774 }
2775
2776 intel_fb = to_intel_framebuffer(fb);
2777 obj = intel_fb->obj;
2778
2779 /*
2780 * The stride is either expressed as a multiple of 64 bytes chunks for
2781 * linear buffers or in number of tiles for tiled buffers.
2782 */
2783 switch (fb->modifier[0]) {
2784 case DRM_FORMAT_MOD_NONE:
2785 stride = fb->pitches[0] >> 6;
2786 break;
2787 case I915_FORMAT_MOD_X_TILED:
2788 plane_ctl |= PLANE_CTL_TILED_X;
2789 stride = fb->pitches[0] >> 9;
2790 break;
2791 default:
2792 BUG();
2793 }
2794
2795 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2796 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2797 plane_ctl |= PLANE_CTL_ROTATE_180;
2798
2799 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2800
2801 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2802 i915_gem_obj_ggtt_offset(obj),
2803 x, y, fb->width, fb->height,
2804 fb->pitches[0]);
2805
2806 I915_WRITE(PLANE_POS(pipe, 0), 0);
2807 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2808 I915_WRITE(PLANE_SIZE(pipe, 0),
2809 (intel_crtc->config->pipe_src_h - 1) << 16 |
2810 (intel_crtc->config->pipe_src_w - 1));
2811 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2812 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2813
2814 POSTING_READ(PLANE_SURF(pipe, 0));
2815 }
2816
2817 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2818 static int
2819 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2820 int x, int y, enum mode_set_atomic state)
2821 {
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824
2825 if (dev_priv->display.disable_fbc)
2826 dev_priv->display.disable_fbc(dev);
2827
2828 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2829
2830 return 0;
2831 }
2832
2833 static void intel_complete_page_flips(struct drm_device *dev)
2834 {
2835 struct drm_crtc *crtc;
2836
2837 for_each_crtc(dev, crtc) {
2838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2839 enum plane plane = intel_crtc->plane;
2840
2841 intel_prepare_page_flip(dev, plane);
2842 intel_finish_page_flip_plane(dev, plane);
2843 }
2844 }
2845
2846 static void intel_update_primary_planes(struct drm_device *dev)
2847 {
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 struct drm_crtc *crtc;
2850
2851 for_each_crtc(dev, crtc) {
2852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853
2854 drm_modeset_lock(&crtc->mutex, NULL);
2855 /*
2856 * FIXME: Once we have proper support for primary planes (and
2857 * disabling them without disabling the entire crtc) allow again
2858 * a NULL crtc->primary->fb.
2859 */
2860 if (intel_crtc->active && crtc->primary->fb)
2861 dev_priv->display.update_primary_plane(crtc,
2862 crtc->primary->fb,
2863 crtc->x,
2864 crtc->y);
2865 drm_modeset_unlock(&crtc->mutex);
2866 }
2867 }
2868
2869 void intel_prepare_reset(struct drm_device *dev)
2870 {
2871 struct drm_i915_private *dev_priv = to_i915(dev);
2872 struct intel_crtc *crtc;
2873
2874 /* no reset support for gen2 */
2875 if (IS_GEN2(dev))
2876 return;
2877
2878 /* reset doesn't touch the display */
2879 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2880 return;
2881
2882 drm_modeset_lock_all(dev);
2883
2884 /*
2885 * Disabling the crtcs gracefully seems nicer. Also the
2886 * g33 docs say we should at least disable all the planes.
2887 */
2888 for_each_intel_crtc(dev, crtc) {
2889 if (crtc->active)
2890 dev_priv->display.crtc_disable(&crtc->base);
2891 }
2892 }
2893
2894 void intel_finish_reset(struct drm_device *dev)
2895 {
2896 struct drm_i915_private *dev_priv = to_i915(dev);
2897
2898 /*
2899 * Flips in the rings will be nuked by the reset,
2900 * so complete all pending flips so that user space
2901 * will get its events and not get stuck.
2902 */
2903 intel_complete_page_flips(dev);
2904
2905 /* no reset support for gen2 */
2906 if (IS_GEN2(dev))
2907 return;
2908
2909 /* reset doesn't touch the display */
2910 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2911 /*
2912 * Flips in the rings have been nuked by the reset,
2913 * so update the base address of all primary
2914 * planes to the the last fb to make sure we're
2915 * showing the correct fb after a reset.
2916 */
2917 intel_update_primary_planes(dev);
2918 return;
2919 }
2920
2921 /*
2922 * The display has been reset as well,
2923 * so need a full re-initialization.
2924 */
2925 intel_runtime_pm_disable_interrupts(dev_priv);
2926 intel_runtime_pm_enable_interrupts(dev_priv);
2927
2928 intel_modeset_init_hw(dev);
2929
2930 spin_lock_irq(&dev_priv->irq_lock);
2931 if (dev_priv->display.hpd_irq_setup)
2932 dev_priv->display.hpd_irq_setup(dev);
2933 spin_unlock_irq(&dev_priv->irq_lock);
2934
2935 intel_modeset_setup_hw_state(dev, true);
2936
2937 intel_hpd_init(dev_priv);
2938
2939 drm_modeset_unlock_all(dev);
2940 }
2941
2942 static int
2943 intel_finish_fb(struct drm_framebuffer *old_fb)
2944 {
2945 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2946 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2947 bool was_interruptible = dev_priv->mm.interruptible;
2948 int ret;
2949
2950 /* Big Hammer, we also need to ensure that any pending
2951 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2952 * current scanout is retired before unpinning the old
2953 * framebuffer.
2954 *
2955 * This should only fail upon a hung GPU, in which case we
2956 * can safely continue.
2957 */
2958 dev_priv->mm.interruptible = false;
2959 ret = i915_gem_object_finish_gpu(obj);
2960 dev_priv->mm.interruptible = was_interruptible;
2961
2962 return ret;
2963 }
2964
2965 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2966 {
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
2969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2970 bool pending;
2971
2972 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2973 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2974 return false;
2975
2976 spin_lock_irq(&dev->event_lock);
2977 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2978 spin_unlock_irq(&dev->event_lock);
2979
2980 return pending;
2981 }
2982
2983 static void intel_update_pipe_size(struct intel_crtc *crtc)
2984 {
2985 struct drm_device *dev = crtc->base.dev;
2986 struct drm_i915_private *dev_priv = dev->dev_private;
2987 const struct drm_display_mode *adjusted_mode;
2988
2989 if (!i915.fastboot)
2990 return;
2991
2992 /*
2993 * Update pipe size and adjust fitter if needed: the reason for this is
2994 * that in compute_mode_changes we check the native mode (not the pfit
2995 * mode) to see if we can flip rather than do a full mode set. In the
2996 * fastboot case, we'll flip, but if we don't update the pipesrc and
2997 * pfit state, we'll end up with a big fb scanned out into the wrong
2998 * sized surface.
2999 *
3000 * To fix this properly, we need to hoist the checks up into
3001 * compute_mode_changes (or above), check the actual pfit state and
3002 * whether the platform allows pfit disable with pipe active, and only
3003 * then update the pipesrc and pfit state, even on the flip path.
3004 */
3005
3006 adjusted_mode = &crtc->config->base.adjusted_mode;
3007
3008 I915_WRITE(PIPESRC(crtc->pipe),
3009 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3010 (adjusted_mode->crtc_vdisplay - 1));
3011 if (!crtc->config->pch_pfit.enabled &&
3012 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3013 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3014 I915_WRITE(PF_CTL(crtc->pipe), 0);
3015 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3016 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3017 }
3018 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3019 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3020 }
3021
3022 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3023 {
3024 struct drm_device *dev = crtc->dev;
3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3027 int pipe = intel_crtc->pipe;
3028 u32 reg, temp;
3029
3030 /* enable normal train */
3031 reg = FDI_TX_CTL(pipe);
3032 temp = I915_READ(reg);
3033 if (IS_IVYBRIDGE(dev)) {
3034 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3035 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3036 } else {
3037 temp &= ~FDI_LINK_TRAIN_NONE;
3038 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3039 }
3040 I915_WRITE(reg, temp);
3041
3042 reg = FDI_RX_CTL(pipe);
3043 temp = I915_READ(reg);
3044 if (HAS_PCH_CPT(dev)) {
3045 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3046 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3047 } else {
3048 temp &= ~FDI_LINK_TRAIN_NONE;
3049 temp |= FDI_LINK_TRAIN_NONE;
3050 }
3051 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3052
3053 /* wait one idle pattern time */
3054 POSTING_READ(reg);
3055 udelay(1000);
3056
3057 /* IVB wants error correction enabled */
3058 if (IS_IVYBRIDGE(dev))
3059 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3060 FDI_FE_ERRC_ENABLE);
3061 }
3062
3063 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3064 {
3065 return crtc->base.enabled && crtc->active &&
3066 crtc->config->has_pch_encoder;
3067 }
3068
3069 static void ivb_modeset_global_resources(struct drm_device *dev)
3070 {
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *pipe_B_crtc =
3073 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3074 struct intel_crtc *pipe_C_crtc =
3075 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3076 uint32_t temp;
3077
3078 /*
3079 * When everything is off disable fdi C so that we could enable fdi B
3080 * with all lanes. Note that we don't care about enabled pipes without
3081 * an enabled pch encoder.
3082 */
3083 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3084 !pipe_has_enabled_pch(pipe_C_crtc)) {
3085 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3087
3088 temp = I915_READ(SOUTH_CHICKEN1);
3089 temp &= ~FDI_BC_BIFURCATION_SELECT;
3090 DRM_DEBUG_KMS("disabling fdi C rx\n");
3091 I915_WRITE(SOUTH_CHICKEN1, temp);
3092 }
3093 }
3094
3095 /* The FDI link training functions for ILK/Ibexpeak. */
3096 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3097 {
3098 struct drm_device *dev = crtc->dev;
3099 struct drm_i915_private *dev_priv = dev->dev_private;
3100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3101 int pipe = intel_crtc->pipe;
3102 u32 reg, temp, tries;
3103
3104 /* FDI needs bits from pipe first */
3105 assert_pipe_enabled(dev_priv, pipe);
3106
3107 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3108 for train result */
3109 reg = FDI_RX_IMR(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_RX_SYMBOL_LOCK;
3112 temp &= ~FDI_RX_BIT_LOCK;
3113 I915_WRITE(reg, temp);
3114 I915_READ(reg);
3115 udelay(150);
3116
3117 /* enable CPU FDI TX and PCH FDI RX */
3118 reg = FDI_TX_CTL(pipe);
3119 temp = I915_READ(reg);
3120 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3121 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3122 temp &= ~FDI_LINK_TRAIN_NONE;
3123 temp |= FDI_LINK_TRAIN_PATTERN_1;
3124 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3125
3126 reg = FDI_RX_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~FDI_LINK_TRAIN_NONE;
3129 temp |= FDI_LINK_TRAIN_PATTERN_1;
3130 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3131
3132 POSTING_READ(reg);
3133 udelay(150);
3134
3135 /* Ironlake workaround, enable clock pointer after FDI enable*/
3136 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3137 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3138 FDI_RX_PHASE_SYNC_POINTER_EN);
3139
3140 reg = FDI_RX_IIR(pipe);
3141 for (tries = 0; tries < 5; tries++) {
3142 temp = I915_READ(reg);
3143 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3144
3145 if ((temp & FDI_RX_BIT_LOCK)) {
3146 DRM_DEBUG_KMS("FDI train 1 done.\n");
3147 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3148 break;
3149 }
3150 }
3151 if (tries == 5)
3152 DRM_ERROR("FDI train 1 fail!\n");
3153
3154 /* Train 2 */
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_NONE;
3158 temp |= FDI_LINK_TRAIN_PATTERN_2;
3159 I915_WRITE(reg, temp);
3160
3161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~FDI_LINK_TRAIN_NONE;
3164 temp |= FDI_LINK_TRAIN_PATTERN_2;
3165 I915_WRITE(reg, temp);
3166
3167 POSTING_READ(reg);
3168 udelay(150);
3169
3170 reg = FDI_RX_IIR(pipe);
3171 for (tries = 0; tries < 5; tries++) {
3172 temp = I915_READ(reg);
3173 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3174
3175 if (temp & FDI_RX_SYMBOL_LOCK) {
3176 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3177 DRM_DEBUG_KMS("FDI train 2 done.\n");
3178 break;
3179 }
3180 }
3181 if (tries == 5)
3182 DRM_ERROR("FDI train 2 fail!\n");
3183
3184 DRM_DEBUG_KMS("FDI train done\n");
3185
3186 }
3187
3188 static const int snb_b_fdi_train_param[] = {
3189 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3190 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3191 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3192 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3193 };
3194
3195 /* The FDI link training functions for SNB/Cougarpoint. */
3196 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3197 {
3198 struct drm_device *dev = crtc->dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201 int pipe = intel_crtc->pipe;
3202 u32 reg, temp, i, retry;
3203
3204 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3205 for train result */
3206 reg = FDI_RX_IMR(pipe);
3207 temp = I915_READ(reg);
3208 temp &= ~FDI_RX_SYMBOL_LOCK;
3209 temp &= ~FDI_RX_BIT_LOCK;
3210 I915_WRITE(reg, temp);
3211
3212 POSTING_READ(reg);
3213 udelay(150);
3214
3215 /* enable CPU FDI TX and PCH FDI RX */
3216 reg = FDI_TX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3219 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3220 temp &= ~FDI_LINK_TRAIN_NONE;
3221 temp |= FDI_LINK_TRAIN_PATTERN_1;
3222 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3223 /* SNB-B */
3224 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3225 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3226
3227 I915_WRITE(FDI_RX_MISC(pipe),
3228 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3229
3230 reg = FDI_RX_CTL(pipe);
3231 temp = I915_READ(reg);
3232 if (HAS_PCH_CPT(dev)) {
3233 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3234 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3235 } else {
3236 temp &= ~FDI_LINK_TRAIN_NONE;
3237 temp |= FDI_LINK_TRAIN_PATTERN_1;
3238 }
3239 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3240
3241 POSTING_READ(reg);
3242 udelay(150);
3243
3244 for (i = 0; i < 4; i++) {
3245 reg = FDI_TX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3248 temp |= snb_b_fdi_train_param[i];
3249 I915_WRITE(reg, temp);
3250
3251 POSTING_READ(reg);
3252 udelay(500);
3253
3254 for (retry = 0; retry < 5; retry++) {
3255 reg = FDI_RX_IIR(pipe);
3256 temp = I915_READ(reg);
3257 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3258 if (temp & FDI_RX_BIT_LOCK) {
3259 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3260 DRM_DEBUG_KMS("FDI train 1 done.\n");
3261 break;
3262 }
3263 udelay(50);
3264 }
3265 if (retry < 5)
3266 break;
3267 }
3268 if (i == 4)
3269 DRM_ERROR("FDI train 1 fail!\n");
3270
3271 /* Train 2 */
3272 reg = FDI_TX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_PATTERN_2;
3276 if (IS_GEN6(dev)) {
3277 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3278 /* SNB-B */
3279 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3280 }
3281 I915_WRITE(reg, temp);
3282
3283 reg = FDI_RX_CTL(pipe);
3284 temp = I915_READ(reg);
3285 if (HAS_PCH_CPT(dev)) {
3286 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3287 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3288 } else {
3289 temp &= ~FDI_LINK_TRAIN_NONE;
3290 temp |= FDI_LINK_TRAIN_PATTERN_2;
3291 }
3292 I915_WRITE(reg, temp);
3293
3294 POSTING_READ(reg);
3295 udelay(150);
3296
3297 for (i = 0; i < 4; i++) {
3298 reg = FDI_TX_CTL(pipe);
3299 temp = I915_READ(reg);
3300 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3301 temp |= snb_b_fdi_train_param[i];
3302 I915_WRITE(reg, temp);
3303
3304 POSTING_READ(reg);
3305 udelay(500);
3306
3307 for (retry = 0; retry < 5; retry++) {
3308 reg = FDI_RX_IIR(pipe);
3309 temp = I915_READ(reg);
3310 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3311 if (temp & FDI_RX_SYMBOL_LOCK) {
3312 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3313 DRM_DEBUG_KMS("FDI train 2 done.\n");
3314 break;
3315 }
3316 udelay(50);
3317 }
3318 if (retry < 5)
3319 break;
3320 }
3321 if (i == 4)
3322 DRM_ERROR("FDI train 2 fail!\n");
3323
3324 DRM_DEBUG_KMS("FDI train done.\n");
3325 }
3326
3327 /* Manual link training for Ivy Bridge A0 parts */
3328 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3329 {
3330 struct drm_device *dev = crtc->dev;
3331 struct drm_i915_private *dev_priv = dev->dev_private;
3332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3333 int pipe = intel_crtc->pipe;
3334 u32 reg, temp, i, j;
3335
3336 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3337 for train result */
3338 reg = FDI_RX_IMR(pipe);
3339 temp = I915_READ(reg);
3340 temp &= ~FDI_RX_SYMBOL_LOCK;
3341 temp &= ~FDI_RX_BIT_LOCK;
3342 I915_WRITE(reg, temp);
3343
3344 POSTING_READ(reg);
3345 udelay(150);
3346
3347 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3348 I915_READ(FDI_RX_IIR(pipe)));
3349
3350 /* Try each vswing and preemphasis setting twice before moving on */
3351 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3352 /* disable first in case we need to retry */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3356 temp &= ~FDI_TX_ENABLE;
3357 I915_WRITE(reg, temp);
3358
3359 reg = FDI_RX_CTL(pipe);
3360 temp = I915_READ(reg);
3361 temp &= ~FDI_LINK_TRAIN_AUTO;
3362 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3363 temp &= ~FDI_RX_ENABLE;
3364 I915_WRITE(reg, temp);
3365
3366 /* enable CPU FDI TX and PCH FDI RX */
3367 reg = FDI_TX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3370 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3371 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3372 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3373 temp |= snb_b_fdi_train_param[j/2];
3374 temp |= FDI_COMPOSITE_SYNC;
3375 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3376
3377 I915_WRITE(FDI_RX_MISC(pipe),
3378 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3379
3380 reg = FDI_RX_CTL(pipe);
3381 temp = I915_READ(reg);
3382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3383 temp |= FDI_COMPOSITE_SYNC;
3384 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3385
3386 POSTING_READ(reg);
3387 udelay(1); /* should be 0.5us */
3388
3389 for (i = 0; i < 4; i++) {
3390 reg = FDI_RX_IIR(pipe);
3391 temp = I915_READ(reg);
3392 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3393
3394 if (temp & FDI_RX_BIT_LOCK ||
3395 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3396 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3397 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3398 i);
3399 break;
3400 }
3401 udelay(1); /* should be 0.5us */
3402 }
3403 if (i == 4) {
3404 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3405 continue;
3406 }
3407
3408 /* Train 2 */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3412 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3413 I915_WRITE(reg, temp);
3414
3415 reg = FDI_RX_CTL(pipe);
3416 temp = I915_READ(reg);
3417 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3418 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3419 I915_WRITE(reg, temp);
3420
3421 POSTING_READ(reg);
3422 udelay(2); /* should be 1.5us */
3423
3424 for (i = 0; i < 4; i++) {
3425 reg = FDI_RX_IIR(pipe);
3426 temp = I915_READ(reg);
3427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3428
3429 if (temp & FDI_RX_SYMBOL_LOCK ||
3430 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3432 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3433 i);
3434 goto train_done;
3435 }
3436 udelay(2); /* should be 1.5us */
3437 }
3438 if (i == 4)
3439 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3440 }
3441
3442 train_done:
3443 DRM_DEBUG_KMS("FDI train done.\n");
3444 }
3445
3446 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3447 {
3448 struct drm_device *dev = intel_crtc->base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 int pipe = intel_crtc->pipe;
3451 u32 reg, temp;
3452
3453
3454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3455 reg = FDI_RX_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3458 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3459 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3460 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3461
3462 POSTING_READ(reg);
3463 udelay(200);
3464
3465 /* Switch from Rawclk to PCDclk */
3466 temp = I915_READ(reg);
3467 I915_WRITE(reg, temp | FDI_PCDCLK);
3468
3469 POSTING_READ(reg);
3470 udelay(200);
3471
3472 /* Enable CPU FDI TX PLL, always on for Ironlake */
3473 reg = FDI_TX_CTL(pipe);
3474 temp = I915_READ(reg);
3475 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3476 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3477
3478 POSTING_READ(reg);
3479 udelay(100);
3480 }
3481 }
3482
3483 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3484 {
3485 struct drm_device *dev = intel_crtc->base.dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 int pipe = intel_crtc->pipe;
3488 u32 reg, temp;
3489
3490 /* Switch from PCDclk to Rawclk */
3491 reg = FDI_RX_CTL(pipe);
3492 temp = I915_READ(reg);
3493 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3494
3495 /* Disable CPU FDI TX PLL */
3496 reg = FDI_TX_CTL(pipe);
3497 temp = I915_READ(reg);
3498 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3499
3500 POSTING_READ(reg);
3501 udelay(100);
3502
3503 reg = FDI_RX_CTL(pipe);
3504 temp = I915_READ(reg);
3505 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3506
3507 /* Wait for the clocks to turn off. */
3508 POSTING_READ(reg);
3509 udelay(100);
3510 }
3511
3512 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3513 {
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
3518 u32 reg, temp;
3519
3520 /* disable CPU FDI tx and PCH FDI rx */
3521 reg = FDI_TX_CTL(pipe);
3522 temp = I915_READ(reg);
3523 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3524 POSTING_READ(reg);
3525
3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~(0x7 << 16);
3529 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3530 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3531
3532 POSTING_READ(reg);
3533 udelay(100);
3534
3535 /* Ironlake workaround, disable clock pointer after downing FDI */
3536 if (HAS_PCH_IBX(dev))
3537 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3538
3539 /* still set train pattern 1 */
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_1;
3544 I915_WRITE(reg, temp);
3545
3546 reg = FDI_RX_CTL(pipe);
3547 temp = I915_READ(reg);
3548 if (HAS_PCH_CPT(dev)) {
3549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551 } else {
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554 }
3555 /* BPC in FDI rx is consistent with that in PIPECONF */
3556 temp &= ~(0x07 << 16);
3557 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3558 I915_WRITE(reg, temp);
3559
3560 POSTING_READ(reg);
3561 udelay(100);
3562 }
3563
3564 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3565 {
3566 struct intel_crtc *crtc;
3567
3568 /* Note that we don't need to be called with mode_config.lock here
3569 * as our list of CRTC objects is static for the lifetime of the
3570 * device and so cannot disappear as we iterate. Similarly, we can
3571 * happily treat the predicates as racy, atomic checks as userspace
3572 * cannot claim and pin a new fb without at least acquring the
3573 * struct_mutex and so serialising with us.
3574 */
3575 for_each_intel_crtc(dev, crtc) {
3576 if (atomic_read(&crtc->unpin_work_count) == 0)
3577 continue;
3578
3579 if (crtc->unpin_work)
3580 intel_wait_for_vblank(dev, crtc->pipe);
3581
3582 return true;
3583 }
3584
3585 return false;
3586 }
3587
3588 static void page_flip_completed(struct intel_crtc *intel_crtc)
3589 {
3590 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3591 struct intel_unpin_work *work = intel_crtc->unpin_work;
3592
3593 /* ensure that the unpin work is consistent wrt ->pending. */
3594 smp_rmb();
3595 intel_crtc->unpin_work = NULL;
3596
3597 if (work->event)
3598 drm_send_vblank_event(intel_crtc->base.dev,
3599 intel_crtc->pipe,
3600 work->event);
3601
3602 drm_crtc_vblank_put(&intel_crtc->base);
3603
3604 wake_up_all(&dev_priv->pending_flip_queue);
3605 queue_work(dev_priv->wq, &work->work);
3606
3607 trace_i915_flip_complete(intel_crtc->plane,
3608 work->pending_flip_obj);
3609 }
3610
3611 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3612 {
3613 struct drm_device *dev = crtc->dev;
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3617 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3618 !intel_crtc_has_pending_flip(crtc),
3619 60*HZ) == 0)) {
3620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3621
3622 spin_lock_irq(&dev->event_lock);
3623 if (intel_crtc->unpin_work) {
3624 WARN_ONCE(1, "Removing stuck page flip\n");
3625 page_flip_completed(intel_crtc);
3626 }
3627 spin_unlock_irq(&dev->event_lock);
3628 }
3629
3630 if (crtc->primary->fb) {
3631 mutex_lock(&dev->struct_mutex);
3632 intel_finish_fb(crtc->primary->fb);
3633 mutex_unlock(&dev->struct_mutex);
3634 }
3635 }
3636
3637 /* Program iCLKIP clock to the desired frequency */
3638 static void lpt_program_iclkip(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3643 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3644 u32 temp;
3645
3646 mutex_lock(&dev_priv->dpio_lock);
3647
3648 /* It is necessary to ungate the pixclk gate prior to programming
3649 * the divisors, and gate it back when it is done.
3650 */
3651 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3652
3653 /* Disable SSCCTL */
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3655 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3656 SBI_SSCCTL_DISABLE,
3657 SBI_ICLK);
3658
3659 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3660 if (clock == 20000) {
3661 auxdiv = 1;
3662 divsel = 0x41;
3663 phaseinc = 0x20;
3664 } else {
3665 /* The iCLK virtual clock root frequency is in MHz,
3666 * but the adjusted_mode->crtc_clock in in KHz. To get the
3667 * divisors, it is necessary to divide one by another, so we
3668 * convert the virtual clock precision to KHz here for higher
3669 * precision.
3670 */
3671 u32 iclk_virtual_root_freq = 172800 * 1000;
3672 u32 iclk_pi_range = 64;
3673 u32 desired_divisor, msb_divisor_value, pi_value;
3674
3675 desired_divisor = (iclk_virtual_root_freq / clock);
3676 msb_divisor_value = desired_divisor / iclk_pi_range;
3677 pi_value = desired_divisor % iclk_pi_range;
3678
3679 auxdiv = 0;
3680 divsel = msb_divisor_value - 2;
3681 phaseinc = pi_value;
3682 }
3683
3684 /* This should not happen with any sane values */
3685 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3686 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3687 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3688 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3689
3690 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3691 clock,
3692 auxdiv,
3693 divsel,
3694 phasedir,
3695 phaseinc);
3696
3697 /* Program SSCDIVINTPHASE6 */
3698 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3699 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3700 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3701 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3702 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3703 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3704 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3705 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3706
3707 /* Program SSCAUXDIV */
3708 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3709 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3710 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3711 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3712
3713 /* Enable modulator and associated divider */
3714 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3715 temp &= ~SBI_SSCCTL_DISABLE;
3716 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3717
3718 /* Wait for initialization time */
3719 udelay(24);
3720
3721 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3722
3723 mutex_unlock(&dev_priv->dpio_lock);
3724 }
3725
3726 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3727 enum pipe pch_transcoder)
3728 {
3729 struct drm_device *dev = crtc->base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3732
3733 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3734 I915_READ(HTOTAL(cpu_transcoder)));
3735 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3736 I915_READ(HBLANK(cpu_transcoder)));
3737 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3738 I915_READ(HSYNC(cpu_transcoder)));
3739
3740 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3741 I915_READ(VTOTAL(cpu_transcoder)));
3742 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3743 I915_READ(VBLANK(cpu_transcoder)));
3744 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3745 I915_READ(VSYNC(cpu_transcoder)));
3746 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3747 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3748 }
3749
3750 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3751 {
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 uint32_t temp;
3754
3755 temp = I915_READ(SOUTH_CHICKEN1);
3756 if (temp & FDI_BC_BIFURCATION_SELECT)
3757 return;
3758
3759 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3760 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3761
3762 temp |= FDI_BC_BIFURCATION_SELECT;
3763 DRM_DEBUG_KMS("enabling fdi C rx\n");
3764 I915_WRITE(SOUTH_CHICKEN1, temp);
3765 POSTING_READ(SOUTH_CHICKEN1);
3766 }
3767
3768 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3769 {
3770 struct drm_device *dev = intel_crtc->base.dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772
3773 switch (intel_crtc->pipe) {
3774 case PIPE_A:
3775 break;
3776 case PIPE_B:
3777 if (intel_crtc->config->fdi_lanes > 2)
3778 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3779 else
3780 cpt_enable_fdi_bc_bifurcation(dev);
3781
3782 break;
3783 case PIPE_C:
3784 cpt_enable_fdi_bc_bifurcation(dev);
3785
3786 break;
3787 default:
3788 BUG();
3789 }
3790 }
3791
3792 /*
3793 * Enable PCH resources required for PCH ports:
3794 * - PCH PLLs
3795 * - FDI training & RX/TX
3796 * - update transcoder timings
3797 * - DP transcoding bits
3798 * - transcoder
3799 */
3800 static void ironlake_pch_enable(struct drm_crtc *crtc)
3801 {
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3805 int pipe = intel_crtc->pipe;
3806 u32 reg, temp;
3807
3808 assert_pch_transcoder_disabled(dev_priv, pipe);
3809
3810 if (IS_IVYBRIDGE(dev))
3811 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3812
3813 /* Write the TU size bits before fdi link training, so that error
3814 * detection works. */
3815 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3816 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3817
3818 /* For PCH output, training FDI link */
3819 dev_priv->display.fdi_link_train(crtc);
3820
3821 /* We need to program the right clock selection before writing the pixel
3822 * mutliplier into the DPLL. */
3823 if (HAS_PCH_CPT(dev)) {
3824 u32 sel;
3825
3826 temp = I915_READ(PCH_DPLL_SEL);
3827 temp |= TRANS_DPLL_ENABLE(pipe);
3828 sel = TRANS_DPLLB_SEL(pipe);
3829 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3830 temp |= sel;
3831 else
3832 temp &= ~sel;
3833 I915_WRITE(PCH_DPLL_SEL, temp);
3834 }
3835
3836 /* XXX: pch pll's can be enabled any time before we enable the PCH
3837 * transcoder, and we actually should do this to not upset any PCH
3838 * transcoder that already use the clock when we share it.
3839 *
3840 * Note that enable_shared_dpll tries to do the right thing, but
3841 * get_shared_dpll unconditionally resets the pll - we need that to have
3842 * the right LVDS enable sequence. */
3843 intel_enable_shared_dpll(intel_crtc);
3844
3845 /* set transcoder timing, panel must allow it */
3846 assert_panel_unlocked(dev_priv, pipe);
3847 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3848
3849 intel_fdi_normal_train(crtc);
3850
3851 /* For PCH DP, enable TRANS_DP_CTL */
3852 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3853 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3854 reg = TRANS_DP_CTL(pipe);
3855 temp = I915_READ(reg);
3856 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3857 TRANS_DP_SYNC_MASK |
3858 TRANS_DP_BPC_MASK);
3859 temp |= (TRANS_DP_OUTPUT_ENABLE |
3860 TRANS_DP_ENH_FRAMING);
3861 temp |= bpc << 9; /* same format but at 11:9 */
3862
3863 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3864 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3865 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3866 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3867
3868 switch (intel_trans_dp_port_sel(crtc)) {
3869 case PCH_DP_B:
3870 temp |= TRANS_DP_PORT_SEL_B;
3871 break;
3872 case PCH_DP_C:
3873 temp |= TRANS_DP_PORT_SEL_C;
3874 break;
3875 case PCH_DP_D:
3876 temp |= TRANS_DP_PORT_SEL_D;
3877 break;
3878 default:
3879 BUG();
3880 }
3881
3882 I915_WRITE(reg, temp);
3883 }
3884
3885 ironlake_enable_pch_transcoder(dev_priv, pipe);
3886 }
3887
3888 static void lpt_pch_enable(struct drm_crtc *crtc)
3889 {
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3893 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3894
3895 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3896
3897 lpt_program_iclkip(crtc);
3898
3899 /* Set transcoder timing. */
3900 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3901
3902 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3903 }
3904
3905 void intel_put_shared_dpll(struct intel_crtc *crtc)
3906 {
3907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3908
3909 if (pll == NULL)
3910 return;
3911
3912 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3913 WARN(1, "bad %s crtc mask\n", pll->name);
3914 return;
3915 }
3916
3917 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3918 if (pll->config.crtc_mask == 0) {
3919 WARN_ON(pll->on);
3920 WARN_ON(pll->active);
3921 }
3922
3923 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3924 }
3925
3926 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3927 struct intel_crtc_state *crtc_state)
3928 {
3929 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3930 struct intel_shared_dpll *pll;
3931 enum intel_dpll_id i;
3932
3933 if (HAS_PCH_IBX(dev_priv->dev)) {
3934 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3935 i = (enum intel_dpll_id) crtc->pipe;
3936 pll = &dev_priv->shared_dplls[i];
3937
3938 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3939 crtc->base.base.id, pll->name);
3940
3941 WARN_ON(pll->new_config->crtc_mask);
3942
3943 goto found;
3944 }
3945
3946 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3947 pll = &dev_priv->shared_dplls[i];
3948
3949 /* Only want to check enabled timings first */
3950 if (pll->new_config->crtc_mask == 0)
3951 continue;
3952
3953 if (memcmp(&crtc_state->dpll_hw_state,
3954 &pll->new_config->hw_state,
3955 sizeof(pll->new_config->hw_state)) == 0) {
3956 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3957 crtc->base.base.id, pll->name,
3958 pll->new_config->crtc_mask,
3959 pll->active);
3960 goto found;
3961 }
3962 }
3963
3964 /* Ok no matching timings, maybe there's a free one? */
3965 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3966 pll = &dev_priv->shared_dplls[i];
3967 if (pll->new_config->crtc_mask == 0) {
3968 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3969 crtc->base.base.id, pll->name);
3970 goto found;
3971 }
3972 }
3973
3974 return NULL;
3975
3976 found:
3977 if (pll->new_config->crtc_mask == 0)
3978 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3979
3980 crtc_state->shared_dpll = i;
3981 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3982 pipe_name(crtc->pipe));
3983
3984 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3985
3986 return pll;
3987 }
3988
3989 /**
3990 * intel_shared_dpll_start_config - start a new PLL staged config
3991 * @dev_priv: DRM device
3992 * @clear_pipes: mask of pipes that will have their PLLs freed
3993 *
3994 * Starts a new PLL staged config, copying the current config but
3995 * releasing the references of pipes specified in clear_pipes.
3996 */
3997 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3998 unsigned clear_pipes)
3999 {
4000 struct intel_shared_dpll *pll;
4001 enum intel_dpll_id i;
4002
4003 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4004 pll = &dev_priv->shared_dplls[i];
4005
4006 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4007 GFP_KERNEL);
4008 if (!pll->new_config)
4009 goto cleanup;
4010
4011 pll->new_config->crtc_mask &= ~clear_pipes;
4012 }
4013
4014 return 0;
4015
4016 cleanup:
4017 while (--i >= 0) {
4018 pll = &dev_priv->shared_dplls[i];
4019 kfree(pll->new_config);
4020 pll->new_config = NULL;
4021 }
4022
4023 return -ENOMEM;
4024 }
4025
4026 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4027 {
4028 struct intel_shared_dpll *pll;
4029 enum intel_dpll_id i;
4030
4031 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4032 pll = &dev_priv->shared_dplls[i];
4033
4034 WARN_ON(pll->new_config == &pll->config);
4035
4036 pll->config = *pll->new_config;
4037 kfree(pll->new_config);
4038 pll->new_config = NULL;
4039 }
4040 }
4041
4042 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4043 {
4044 struct intel_shared_dpll *pll;
4045 enum intel_dpll_id i;
4046
4047 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4048 pll = &dev_priv->shared_dplls[i];
4049
4050 WARN_ON(pll->new_config == &pll->config);
4051
4052 kfree(pll->new_config);
4053 pll->new_config = NULL;
4054 }
4055 }
4056
4057 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4058 {
4059 struct drm_i915_private *dev_priv = dev->dev_private;
4060 int dslreg = PIPEDSL(pipe);
4061 u32 temp;
4062
4063 temp = I915_READ(dslreg);
4064 udelay(500);
4065 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4066 if (wait_for(I915_READ(dslreg) != temp, 5))
4067 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4068 }
4069 }
4070
4071 static void skylake_pfit_enable(struct intel_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->base.dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 int pipe = crtc->pipe;
4076
4077 if (crtc->config->pch_pfit.enabled) {
4078 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4079 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4080 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4081 }
4082 }
4083
4084 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4085 {
4086 struct drm_device *dev = crtc->base.dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 int pipe = crtc->pipe;
4089
4090 if (crtc->config->pch_pfit.enabled) {
4091 /* Force use of hard-coded filter coefficients
4092 * as some pre-programmed values are broken,
4093 * e.g. x201.
4094 */
4095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4096 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4097 PF_PIPE_SEL_IVB(pipe));
4098 else
4099 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4100 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4101 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4102 }
4103 }
4104
4105 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4106 {
4107 struct drm_device *dev = crtc->dev;
4108 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4109 struct drm_plane *plane;
4110 struct intel_plane *intel_plane;
4111
4112 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4113 intel_plane = to_intel_plane(plane);
4114 if (intel_plane->pipe == pipe)
4115 intel_plane_restore(&intel_plane->base);
4116 }
4117 }
4118
4119 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4120 {
4121 struct drm_device *dev = crtc->dev;
4122 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4123 struct drm_plane *plane;
4124 struct intel_plane *intel_plane;
4125
4126 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4127 intel_plane = to_intel_plane(plane);
4128 if (intel_plane->pipe == pipe)
4129 plane->funcs->disable_plane(plane);
4130 }
4131 }
4132
4133 void hsw_enable_ips(struct intel_crtc *crtc)
4134 {
4135 struct drm_device *dev = crtc->base.dev;
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137
4138 if (!crtc->config->ips_enabled)
4139 return;
4140
4141 /* We can only enable IPS after we enable a plane and wait for a vblank */
4142 intel_wait_for_vblank(dev, crtc->pipe);
4143
4144 assert_plane_enabled(dev_priv, crtc->plane);
4145 if (IS_BROADWELL(dev)) {
4146 mutex_lock(&dev_priv->rps.hw_lock);
4147 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4148 mutex_unlock(&dev_priv->rps.hw_lock);
4149 /* Quoting Art Runyan: "its not safe to expect any particular
4150 * value in IPS_CTL bit 31 after enabling IPS through the
4151 * mailbox." Moreover, the mailbox may return a bogus state,
4152 * so we need to just enable it and continue on.
4153 */
4154 } else {
4155 I915_WRITE(IPS_CTL, IPS_ENABLE);
4156 /* The bit only becomes 1 in the next vblank, so this wait here
4157 * is essentially intel_wait_for_vblank. If we don't have this
4158 * and don't wait for vblanks until the end of crtc_enable, then
4159 * the HW state readout code will complain that the expected
4160 * IPS_CTL value is not the one we read. */
4161 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4162 DRM_ERROR("Timed out waiting for IPS enable\n");
4163 }
4164 }
4165
4166 void hsw_disable_ips(struct intel_crtc *crtc)
4167 {
4168 struct drm_device *dev = crtc->base.dev;
4169 struct drm_i915_private *dev_priv = dev->dev_private;
4170
4171 if (!crtc->config->ips_enabled)
4172 return;
4173
4174 assert_plane_enabled(dev_priv, crtc->plane);
4175 if (IS_BROADWELL(dev)) {
4176 mutex_lock(&dev_priv->rps.hw_lock);
4177 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4178 mutex_unlock(&dev_priv->rps.hw_lock);
4179 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4180 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4181 DRM_ERROR("Timed out waiting for IPS disable\n");
4182 } else {
4183 I915_WRITE(IPS_CTL, 0);
4184 POSTING_READ(IPS_CTL);
4185 }
4186
4187 /* We need to wait for a vblank before we can disable the plane. */
4188 intel_wait_for_vblank(dev, crtc->pipe);
4189 }
4190
4191 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4192 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4193 {
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
4196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197 enum pipe pipe = intel_crtc->pipe;
4198 int palreg = PALETTE(pipe);
4199 int i;
4200 bool reenable_ips = false;
4201
4202 /* The clocks have to be on to load the palette. */
4203 if (!crtc->enabled || !intel_crtc->active)
4204 return;
4205
4206 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4207 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4208 assert_dsi_pll_enabled(dev_priv);
4209 else
4210 assert_pll_enabled(dev_priv, pipe);
4211 }
4212
4213 /* use legacy palette for Ironlake */
4214 if (!HAS_GMCH_DISPLAY(dev))
4215 palreg = LGC_PALETTE(pipe);
4216
4217 /* Workaround : Do not read or write the pipe palette/gamma data while
4218 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4219 */
4220 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4221 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4222 GAMMA_MODE_MODE_SPLIT)) {
4223 hsw_disable_ips(intel_crtc);
4224 reenable_ips = true;
4225 }
4226
4227 for (i = 0; i < 256; i++) {
4228 I915_WRITE(palreg + 4 * i,
4229 (intel_crtc->lut_r[i] << 16) |
4230 (intel_crtc->lut_g[i] << 8) |
4231 intel_crtc->lut_b[i]);
4232 }
4233
4234 if (reenable_ips)
4235 hsw_enable_ips(intel_crtc);
4236 }
4237
4238 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4239 {
4240 if (!enable && intel_crtc->overlay) {
4241 struct drm_device *dev = intel_crtc->base.dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243
4244 mutex_lock(&dev->struct_mutex);
4245 dev_priv->mm.interruptible = false;
4246 (void) intel_overlay_switch_off(intel_crtc->overlay);
4247 dev_priv->mm.interruptible = true;
4248 mutex_unlock(&dev->struct_mutex);
4249 }
4250
4251 /* Let userspace switch the overlay on again. In most cases userspace
4252 * has to recompute where to put it anyway.
4253 */
4254 }
4255
4256 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4257 {
4258 struct drm_device *dev = crtc->dev;
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 int pipe = intel_crtc->pipe;
4261
4262 intel_enable_primary_hw_plane(crtc->primary, crtc);
4263 intel_enable_sprite_planes(crtc);
4264 intel_crtc_update_cursor(crtc, true);
4265 intel_crtc_dpms_overlay(intel_crtc, true);
4266
4267 hsw_enable_ips(intel_crtc);
4268
4269 mutex_lock(&dev->struct_mutex);
4270 intel_fbc_update(dev);
4271 mutex_unlock(&dev->struct_mutex);
4272
4273 /*
4274 * FIXME: Once we grow proper nuclear flip support out of this we need
4275 * to compute the mask of flip planes precisely. For the time being
4276 * consider this a flip from a NULL plane.
4277 */
4278 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4279 }
4280
4281 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4282 {
4283 struct drm_device *dev = crtc->dev;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4286 int pipe = intel_crtc->pipe;
4287
4288 intel_crtc_wait_for_pending_flips(crtc);
4289
4290 if (dev_priv->fbc.crtc == intel_crtc)
4291 intel_fbc_disable(dev);
4292
4293 hsw_disable_ips(intel_crtc);
4294
4295 intel_crtc_dpms_overlay(intel_crtc, false);
4296 intel_crtc_update_cursor(crtc, false);
4297 intel_disable_sprite_planes(crtc);
4298 intel_disable_primary_hw_plane(crtc->primary, crtc);
4299
4300 /*
4301 * FIXME: Once we grow proper nuclear flip support out of this we need
4302 * to compute the mask of flip planes precisely. For the time being
4303 * consider this a flip to a NULL plane.
4304 */
4305 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4306 }
4307
4308 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4309 {
4310 struct drm_device *dev = crtc->dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 struct intel_encoder *encoder;
4314 int pipe = intel_crtc->pipe;
4315
4316 WARN_ON(!crtc->enabled);
4317
4318 if (intel_crtc->active)
4319 return;
4320
4321 if (intel_crtc->config->has_pch_encoder)
4322 intel_prepare_shared_dpll(intel_crtc);
4323
4324 if (intel_crtc->config->has_dp_encoder)
4325 intel_dp_set_m_n(intel_crtc, M1_N1);
4326
4327 intel_set_pipe_timings(intel_crtc);
4328
4329 if (intel_crtc->config->has_pch_encoder) {
4330 intel_cpu_transcoder_set_m_n(intel_crtc,
4331 &intel_crtc->config->fdi_m_n, NULL);
4332 }
4333
4334 ironlake_set_pipeconf(crtc);
4335
4336 intel_crtc->active = true;
4337
4338 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4339 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4340
4341 for_each_encoder_on_crtc(dev, crtc, encoder)
4342 if (encoder->pre_enable)
4343 encoder->pre_enable(encoder);
4344
4345 if (intel_crtc->config->has_pch_encoder) {
4346 /* Note: FDI PLL enabling _must_ be done before we enable the
4347 * cpu pipes, hence this is separate from all the other fdi/pch
4348 * enabling. */
4349 ironlake_fdi_pll_enable(intel_crtc);
4350 } else {
4351 assert_fdi_tx_disabled(dev_priv, pipe);
4352 assert_fdi_rx_disabled(dev_priv, pipe);
4353 }
4354
4355 ironlake_pfit_enable(intel_crtc);
4356
4357 /*
4358 * On ILK+ LUT must be loaded before the pipe is running but with
4359 * clocks enabled
4360 */
4361 intel_crtc_load_lut(crtc);
4362
4363 intel_update_watermarks(crtc);
4364 intel_enable_pipe(intel_crtc);
4365
4366 if (intel_crtc->config->has_pch_encoder)
4367 ironlake_pch_enable(crtc);
4368
4369 assert_vblank_disabled(crtc);
4370 drm_crtc_vblank_on(crtc);
4371
4372 for_each_encoder_on_crtc(dev, crtc, encoder)
4373 encoder->enable(encoder);
4374
4375 if (HAS_PCH_CPT(dev))
4376 cpt_verify_modeset(dev, intel_crtc->pipe);
4377
4378 intel_crtc_enable_planes(crtc);
4379 }
4380
4381 /* IPS only exists on ULT machines and is tied to pipe A. */
4382 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4383 {
4384 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4385 }
4386
4387 /*
4388 * This implements the workaround described in the "notes" section of the mode
4389 * set sequence documentation. When going from no pipes or single pipe to
4390 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4391 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4392 */
4393 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->base.dev;
4396 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4397
4398 /* We want to get the other_active_crtc only if there's only 1 other
4399 * active crtc. */
4400 for_each_intel_crtc(dev, crtc_it) {
4401 if (!crtc_it->active || crtc_it == crtc)
4402 continue;
4403
4404 if (other_active_crtc)
4405 return;
4406
4407 other_active_crtc = crtc_it;
4408 }
4409 if (!other_active_crtc)
4410 return;
4411
4412 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4413 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4414 }
4415
4416 static void haswell_crtc_enable(struct drm_crtc *crtc)
4417 {
4418 struct drm_device *dev = crtc->dev;
4419 struct drm_i915_private *dev_priv = dev->dev_private;
4420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4421 struct intel_encoder *encoder;
4422 int pipe = intel_crtc->pipe;
4423
4424 WARN_ON(!crtc->enabled);
4425
4426 if (intel_crtc->active)
4427 return;
4428
4429 if (intel_crtc_to_shared_dpll(intel_crtc))
4430 intel_enable_shared_dpll(intel_crtc);
4431
4432 if (intel_crtc->config->has_dp_encoder)
4433 intel_dp_set_m_n(intel_crtc, M1_N1);
4434
4435 intel_set_pipe_timings(intel_crtc);
4436
4437 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4438 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4439 intel_crtc->config->pixel_multiplier - 1);
4440 }
4441
4442 if (intel_crtc->config->has_pch_encoder) {
4443 intel_cpu_transcoder_set_m_n(intel_crtc,
4444 &intel_crtc->config->fdi_m_n, NULL);
4445 }
4446
4447 haswell_set_pipeconf(crtc);
4448
4449 intel_set_pipe_csc(crtc);
4450
4451 intel_crtc->active = true;
4452
4453 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4454 for_each_encoder_on_crtc(dev, crtc, encoder)
4455 if (encoder->pre_enable)
4456 encoder->pre_enable(encoder);
4457
4458 if (intel_crtc->config->has_pch_encoder) {
4459 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4460 true);
4461 dev_priv->display.fdi_link_train(crtc);
4462 }
4463
4464 intel_ddi_enable_pipe_clock(intel_crtc);
4465
4466 if (IS_SKYLAKE(dev))
4467 skylake_pfit_enable(intel_crtc);
4468 else
4469 ironlake_pfit_enable(intel_crtc);
4470
4471 /*
4472 * On ILK+ LUT must be loaded before the pipe is running but with
4473 * clocks enabled
4474 */
4475 intel_crtc_load_lut(crtc);
4476
4477 intel_ddi_set_pipe_settings(crtc);
4478 intel_ddi_enable_transcoder_func(crtc);
4479
4480 intel_update_watermarks(crtc);
4481 intel_enable_pipe(intel_crtc);
4482
4483 if (intel_crtc->config->has_pch_encoder)
4484 lpt_pch_enable(crtc);
4485
4486 if (intel_crtc->config->dp_encoder_is_mst)
4487 intel_ddi_set_vc_payload_alloc(crtc, true);
4488
4489 assert_vblank_disabled(crtc);
4490 drm_crtc_vblank_on(crtc);
4491
4492 for_each_encoder_on_crtc(dev, crtc, encoder) {
4493 encoder->enable(encoder);
4494 intel_opregion_notify_encoder(encoder, true);
4495 }
4496
4497 /* If we change the relative order between pipe/planes enabling, we need
4498 * to change the workaround. */
4499 haswell_mode_set_planes_workaround(intel_crtc);
4500 intel_crtc_enable_planes(crtc);
4501 }
4502
4503 static void skylake_pfit_disable(struct intel_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->base.dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 int pipe = crtc->pipe;
4508
4509 /* To avoid upsetting the power well on haswell only disable the pfit if
4510 * it's in use. The hw state code will make sure we get this right. */
4511 if (crtc->config->pch_pfit.enabled) {
4512 I915_WRITE(PS_CTL(pipe), 0);
4513 I915_WRITE(PS_WIN_POS(pipe), 0);
4514 I915_WRITE(PS_WIN_SZ(pipe), 0);
4515 }
4516 }
4517
4518 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4519 {
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 int pipe = crtc->pipe;
4523
4524 /* To avoid upsetting the power well on haswell only disable the pfit if
4525 * it's in use. The hw state code will make sure we get this right. */
4526 if (crtc->config->pch_pfit.enabled) {
4527 I915_WRITE(PF_CTL(pipe), 0);
4528 I915_WRITE(PF_WIN_POS(pipe), 0);
4529 I915_WRITE(PF_WIN_SZ(pipe), 0);
4530 }
4531 }
4532
4533 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4534 {
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 struct intel_encoder *encoder;
4539 int pipe = intel_crtc->pipe;
4540 u32 reg, temp;
4541
4542 if (!intel_crtc->active)
4543 return;
4544
4545 intel_crtc_disable_planes(crtc);
4546
4547 for_each_encoder_on_crtc(dev, crtc, encoder)
4548 encoder->disable(encoder);
4549
4550 drm_crtc_vblank_off(crtc);
4551 assert_vblank_disabled(crtc);
4552
4553 if (intel_crtc->config->has_pch_encoder)
4554 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4555
4556 intel_disable_pipe(intel_crtc);
4557
4558 ironlake_pfit_disable(intel_crtc);
4559
4560 for_each_encoder_on_crtc(dev, crtc, encoder)
4561 if (encoder->post_disable)
4562 encoder->post_disable(encoder);
4563
4564 if (intel_crtc->config->has_pch_encoder) {
4565 ironlake_fdi_disable(crtc);
4566
4567 ironlake_disable_pch_transcoder(dev_priv, pipe);
4568
4569 if (HAS_PCH_CPT(dev)) {
4570 /* disable TRANS_DP_CTL */
4571 reg = TRANS_DP_CTL(pipe);
4572 temp = I915_READ(reg);
4573 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4574 TRANS_DP_PORT_SEL_MASK);
4575 temp |= TRANS_DP_PORT_SEL_NONE;
4576 I915_WRITE(reg, temp);
4577
4578 /* disable DPLL_SEL */
4579 temp = I915_READ(PCH_DPLL_SEL);
4580 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4581 I915_WRITE(PCH_DPLL_SEL, temp);
4582 }
4583
4584 /* disable PCH DPLL */
4585 intel_disable_shared_dpll(intel_crtc);
4586
4587 ironlake_fdi_pll_disable(intel_crtc);
4588 }
4589
4590 intel_crtc->active = false;
4591 intel_update_watermarks(crtc);
4592
4593 mutex_lock(&dev->struct_mutex);
4594 intel_fbc_update(dev);
4595 mutex_unlock(&dev->struct_mutex);
4596 }
4597
4598 static void haswell_crtc_disable(struct drm_crtc *crtc)
4599 {
4600 struct drm_device *dev = crtc->dev;
4601 struct drm_i915_private *dev_priv = dev->dev_private;
4602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4603 struct intel_encoder *encoder;
4604 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4605
4606 if (!intel_crtc->active)
4607 return;
4608
4609 intel_crtc_disable_planes(crtc);
4610
4611 for_each_encoder_on_crtc(dev, crtc, encoder) {
4612 intel_opregion_notify_encoder(encoder, false);
4613 encoder->disable(encoder);
4614 }
4615
4616 drm_crtc_vblank_off(crtc);
4617 assert_vblank_disabled(crtc);
4618
4619 if (intel_crtc->config->has_pch_encoder)
4620 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4621 false);
4622 intel_disable_pipe(intel_crtc);
4623
4624 if (intel_crtc->config->dp_encoder_is_mst)
4625 intel_ddi_set_vc_payload_alloc(crtc, false);
4626
4627 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4628
4629 if (IS_SKYLAKE(dev))
4630 skylake_pfit_disable(intel_crtc);
4631 else
4632 ironlake_pfit_disable(intel_crtc);
4633
4634 intel_ddi_disable_pipe_clock(intel_crtc);
4635
4636 if (intel_crtc->config->has_pch_encoder) {
4637 lpt_disable_pch_transcoder(dev_priv);
4638 intel_ddi_fdi_disable(crtc);
4639 }
4640
4641 for_each_encoder_on_crtc(dev, crtc, encoder)
4642 if (encoder->post_disable)
4643 encoder->post_disable(encoder);
4644
4645 intel_crtc->active = false;
4646 intel_update_watermarks(crtc);
4647
4648 mutex_lock(&dev->struct_mutex);
4649 intel_fbc_update(dev);
4650 mutex_unlock(&dev->struct_mutex);
4651
4652 if (intel_crtc_to_shared_dpll(intel_crtc))
4653 intel_disable_shared_dpll(intel_crtc);
4654 }
4655
4656 static void ironlake_crtc_off(struct drm_crtc *crtc)
4657 {
4658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659 intel_put_shared_dpll(intel_crtc);
4660 }
4661
4662
4663 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4664 {
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_crtc_state *pipe_config = crtc->config;
4668
4669 if (!pipe_config->gmch_pfit.control)
4670 return;
4671
4672 /*
4673 * The panel fitter should only be adjusted whilst the pipe is disabled,
4674 * according to register description and PRM.
4675 */
4676 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4677 assert_pipe_disabled(dev_priv, crtc->pipe);
4678
4679 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4680 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4681
4682 /* Border color in case we don't scale up to the full screen. Black by
4683 * default, change to something else for debugging. */
4684 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4685 }
4686
4687 static enum intel_display_power_domain port_to_power_domain(enum port port)
4688 {
4689 switch (port) {
4690 case PORT_A:
4691 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4692 case PORT_B:
4693 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4694 case PORT_C:
4695 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4696 case PORT_D:
4697 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4698 default:
4699 WARN_ON_ONCE(1);
4700 return POWER_DOMAIN_PORT_OTHER;
4701 }
4702 }
4703
4704 #define for_each_power_domain(domain, mask) \
4705 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4706 if ((1 << (domain)) & (mask))
4707
4708 enum intel_display_power_domain
4709 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4710 {
4711 struct drm_device *dev = intel_encoder->base.dev;
4712 struct intel_digital_port *intel_dig_port;
4713
4714 switch (intel_encoder->type) {
4715 case INTEL_OUTPUT_UNKNOWN:
4716 /* Only DDI platforms should ever use this output type */
4717 WARN_ON_ONCE(!HAS_DDI(dev));
4718 case INTEL_OUTPUT_DISPLAYPORT:
4719 case INTEL_OUTPUT_HDMI:
4720 case INTEL_OUTPUT_EDP:
4721 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4722 return port_to_power_domain(intel_dig_port->port);
4723 case INTEL_OUTPUT_DP_MST:
4724 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4725 return port_to_power_domain(intel_dig_port->port);
4726 case INTEL_OUTPUT_ANALOG:
4727 return POWER_DOMAIN_PORT_CRT;
4728 case INTEL_OUTPUT_DSI:
4729 return POWER_DOMAIN_PORT_DSI;
4730 default:
4731 return POWER_DOMAIN_PORT_OTHER;
4732 }
4733 }
4734
4735 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4736 {
4737 struct drm_device *dev = crtc->dev;
4738 struct intel_encoder *intel_encoder;
4739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4740 enum pipe pipe = intel_crtc->pipe;
4741 unsigned long mask;
4742 enum transcoder transcoder;
4743
4744 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4745
4746 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4747 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4748 if (intel_crtc->config->pch_pfit.enabled ||
4749 intel_crtc->config->pch_pfit.force_thru)
4750 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4751
4752 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4753 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4754
4755 return mask;
4756 }
4757
4758 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4759 {
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4762 struct intel_crtc *crtc;
4763
4764 /*
4765 * First get all needed power domains, then put all unneeded, to avoid
4766 * any unnecessary toggling of the power wells.
4767 */
4768 for_each_intel_crtc(dev, crtc) {
4769 enum intel_display_power_domain domain;
4770
4771 if (!crtc->base.enabled)
4772 continue;
4773
4774 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4775
4776 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4777 intel_display_power_get(dev_priv, domain);
4778 }
4779
4780 if (dev_priv->display.modeset_global_resources)
4781 dev_priv->display.modeset_global_resources(dev);
4782
4783 for_each_intel_crtc(dev, crtc) {
4784 enum intel_display_power_domain domain;
4785
4786 for_each_power_domain(domain, crtc->enabled_power_domains)
4787 intel_display_power_put(dev_priv, domain);
4788
4789 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4790 }
4791
4792 intel_display_set_init_power(dev_priv, false);
4793 }
4794
4795 /* returns HPLL frequency in kHz */
4796 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4797 {
4798 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4799
4800 /* Obtain SKU information */
4801 mutex_lock(&dev_priv->dpio_lock);
4802 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4803 CCK_FUSE_HPLL_FREQ_MASK;
4804 mutex_unlock(&dev_priv->dpio_lock);
4805
4806 return vco_freq[hpll_freq] * 1000;
4807 }
4808
4809 static void vlv_update_cdclk(struct drm_device *dev)
4810 {
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812
4813 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4814 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4815 dev_priv->vlv_cdclk_freq);
4816
4817 /*
4818 * Program the gmbus_freq based on the cdclk frequency.
4819 * BSpec erroneously claims we should aim for 4MHz, but
4820 * in fact 1MHz is the correct frequency.
4821 */
4822 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4823 }
4824
4825 /* Adjust CDclk dividers to allow high res or save power if possible */
4826 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4827 {
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 u32 val, cmd;
4830
4831 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4832
4833 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4834 cmd = 2;
4835 else if (cdclk == 266667)
4836 cmd = 1;
4837 else
4838 cmd = 0;
4839
4840 mutex_lock(&dev_priv->rps.hw_lock);
4841 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4842 val &= ~DSPFREQGUAR_MASK;
4843 val |= (cmd << DSPFREQGUAR_SHIFT);
4844 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4845 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4846 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4847 50)) {
4848 DRM_ERROR("timed out waiting for CDclk change\n");
4849 }
4850 mutex_unlock(&dev_priv->rps.hw_lock);
4851
4852 if (cdclk == 400000) {
4853 u32 divider;
4854
4855 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4856
4857 mutex_lock(&dev_priv->dpio_lock);
4858 /* adjust cdclk divider */
4859 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4860 val &= ~DISPLAY_FREQUENCY_VALUES;
4861 val |= divider;
4862 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4863
4864 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4865 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4866 50))
4867 DRM_ERROR("timed out waiting for CDclk change\n");
4868 mutex_unlock(&dev_priv->dpio_lock);
4869 }
4870
4871 mutex_lock(&dev_priv->dpio_lock);
4872 /* adjust self-refresh exit latency value */
4873 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4874 val &= ~0x7f;
4875
4876 /*
4877 * For high bandwidth configs, we set a higher latency in the bunit
4878 * so that the core display fetch happens in time to avoid underruns.
4879 */
4880 if (cdclk == 400000)
4881 val |= 4500 / 250; /* 4.5 usec */
4882 else
4883 val |= 3000 / 250; /* 3.0 usec */
4884 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4885 mutex_unlock(&dev_priv->dpio_lock);
4886
4887 vlv_update_cdclk(dev);
4888 }
4889
4890 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4891 {
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 u32 val, cmd;
4894
4895 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4896
4897 switch (cdclk) {
4898 case 400000:
4899 cmd = 3;
4900 break;
4901 case 333333:
4902 case 320000:
4903 cmd = 2;
4904 break;
4905 case 266667:
4906 cmd = 1;
4907 break;
4908 case 200000:
4909 cmd = 0;
4910 break;
4911 default:
4912 MISSING_CASE(cdclk);
4913 return;
4914 }
4915
4916 mutex_lock(&dev_priv->rps.hw_lock);
4917 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4918 val &= ~DSPFREQGUAR_MASK_CHV;
4919 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4920 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4921 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4922 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4923 50)) {
4924 DRM_ERROR("timed out waiting for CDclk change\n");
4925 }
4926 mutex_unlock(&dev_priv->rps.hw_lock);
4927
4928 vlv_update_cdclk(dev);
4929 }
4930
4931 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4932 int max_pixclk)
4933 {
4934 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4935
4936 /* FIXME: Punit isn't quite ready yet */
4937 if (IS_CHERRYVIEW(dev_priv->dev))
4938 return 400000;
4939
4940 /*
4941 * Really only a few cases to deal with, as only 4 CDclks are supported:
4942 * 200MHz
4943 * 267MHz
4944 * 320/333MHz (depends on HPLL freq)
4945 * 400MHz
4946 * So we check to see whether we're above 90% of the lower bin and
4947 * adjust if needed.
4948 *
4949 * We seem to get an unstable or solid color picture at 200MHz.
4950 * Not sure what's wrong. For now use 200MHz only when all pipes
4951 * are off.
4952 */
4953 if (max_pixclk > freq_320*9/10)
4954 return 400000;
4955 else if (max_pixclk > 266667*9/10)
4956 return freq_320;
4957 else if (max_pixclk > 0)
4958 return 266667;
4959 else
4960 return 200000;
4961 }
4962
4963 /* compute the max pixel clock for new configuration */
4964 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4965 {
4966 struct drm_device *dev = dev_priv->dev;
4967 struct intel_crtc *intel_crtc;
4968 int max_pixclk = 0;
4969
4970 for_each_intel_crtc(dev, intel_crtc) {
4971 if (intel_crtc->new_enabled)
4972 max_pixclk = max(max_pixclk,
4973 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4974 }
4975
4976 return max_pixclk;
4977 }
4978
4979 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4980 unsigned *prepare_pipes)
4981 {
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983 struct intel_crtc *intel_crtc;
4984 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4985
4986 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4987 dev_priv->vlv_cdclk_freq)
4988 return;
4989
4990 /* disable/enable all currently active pipes while we change cdclk */
4991 for_each_intel_crtc(dev, intel_crtc)
4992 if (intel_crtc->base.enabled)
4993 *prepare_pipes |= (1 << intel_crtc->pipe);
4994 }
4995
4996 static void valleyview_modeset_global_resources(struct drm_device *dev)
4997 {
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5000 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5001
5002 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5003 /*
5004 * FIXME: We can end up here with all power domains off, yet
5005 * with a CDCLK frequency other than the minimum. To account
5006 * for this take the PIPE-A power domain, which covers the HW
5007 * blocks needed for the following programming. This can be
5008 * removed once it's guaranteed that we get here either with
5009 * the minimum CDCLK set, or the required power domains
5010 * enabled.
5011 */
5012 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5013
5014 if (IS_CHERRYVIEW(dev))
5015 cherryview_set_cdclk(dev, req_cdclk);
5016 else
5017 valleyview_set_cdclk(dev, req_cdclk);
5018
5019 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5020 }
5021 }
5022
5023 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5024 {
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = to_i915(dev);
5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 struct intel_encoder *encoder;
5029 int pipe = intel_crtc->pipe;
5030 bool is_dsi;
5031
5032 WARN_ON(!crtc->enabled);
5033
5034 if (intel_crtc->active)
5035 return;
5036
5037 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5038
5039 if (!is_dsi) {
5040 if (IS_CHERRYVIEW(dev))
5041 chv_prepare_pll(intel_crtc, intel_crtc->config);
5042 else
5043 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5044 }
5045
5046 if (intel_crtc->config->has_dp_encoder)
5047 intel_dp_set_m_n(intel_crtc, M1_N1);
5048
5049 intel_set_pipe_timings(intel_crtc);
5050
5051 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5052 struct drm_i915_private *dev_priv = dev->dev_private;
5053
5054 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5055 I915_WRITE(CHV_CANVAS(pipe), 0);
5056 }
5057
5058 i9xx_set_pipeconf(intel_crtc);
5059
5060 intel_crtc->active = true;
5061
5062 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5063
5064 for_each_encoder_on_crtc(dev, crtc, encoder)
5065 if (encoder->pre_pll_enable)
5066 encoder->pre_pll_enable(encoder);
5067
5068 if (!is_dsi) {
5069 if (IS_CHERRYVIEW(dev))
5070 chv_enable_pll(intel_crtc, intel_crtc->config);
5071 else
5072 vlv_enable_pll(intel_crtc, intel_crtc->config);
5073 }
5074
5075 for_each_encoder_on_crtc(dev, crtc, encoder)
5076 if (encoder->pre_enable)
5077 encoder->pre_enable(encoder);
5078
5079 i9xx_pfit_enable(intel_crtc);
5080
5081 intel_crtc_load_lut(crtc);
5082
5083 intel_update_watermarks(crtc);
5084 intel_enable_pipe(intel_crtc);
5085
5086 assert_vblank_disabled(crtc);
5087 drm_crtc_vblank_on(crtc);
5088
5089 for_each_encoder_on_crtc(dev, crtc, encoder)
5090 encoder->enable(encoder);
5091
5092 intel_crtc_enable_planes(crtc);
5093
5094 /* Underruns don't raise interrupts, so check manually. */
5095 i9xx_check_fifo_underruns(dev_priv);
5096 }
5097
5098 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5099 {
5100 struct drm_device *dev = crtc->base.dev;
5101 struct drm_i915_private *dev_priv = dev->dev_private;
5102
5103 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5104 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5105 }
5106
5107 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5108 {
5109 struct drm_device *dev = crtc->dev;
5110 struct drm_i915_private *dev_priv = to_i915(dev);
5111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112 struct intel_encoder *encoder;
5113 int pipe = intel_crtc->pipe;
5114
5115 WARN_ON(!crtc->enabled);
5116
5117 if (intel_crtc->active)
5118 return;
5119
5120 i9xx_set_pll_dividers(intel_crtc);
5121
5122 if (intel_crtc->config->has_dp_encoder)
5123 intel_dp_set_m_n(intel_crtc, M1_N1);
5124
5125 intel_set_pipe_timings(intel_crtc);
5126
5127 i9xx_set_pipeconf(intel_crtc);
5128
5129 intel_crtc->active = true;
5130
5131 if (!IS_GEN2(dev))
5132 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5133
5134 for_each_encoder_on_crtc(dev, crtc, encoder)
5135 if (encoder->pre_enable)
5136 encoder->pre_enable(encoder);
5137
5138 i9xx_enable_pll(intel_crtc);
5139
5140 i9xx_pfit_enable(intel_crtc);
5141
5142 intel_crtc_load_lut(crtc);
5143
5144 intel_update_watermarks(crtc);
5145 intel_enable_pipe(intel_crtc);
5146
5147 assert_vblank_disabled(crtc);
5148 drm_crtc_vblank_on(crtc);
5149
5150 for_each_encoder_on_crtc(dev, crtc, encoder)
5151 encoder->enable(encoder);
5152
5153 intel_crtc_enable_planes(crtc);
5154
5155 /*
5156 * Gen2 reports pipe underruns whenever all planes are disabled.
5157 * So don't enable underrun reporting before at least some planes
5158 * are enabled.
5159 * FIXME: Need to fix the logic to work when we turn off all planes
5160 * but leave the pipe running.
5161 */
5162 if (IS_GEN2(dev))
5163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5164
5165 /* Underruns don't raise interrupts, so check manually. */
5166 i9xx_check_fifo_underruns(dev_priv);
5167 }
5168
5169 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5170 {
5171 struct drm_device *dev = crtc->base.dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173
5174 if (!crtc->config->gmch_pfit.control)
5175 return;
5176
5177 assert_pipe_disabled(dev_priv, crtc->pipe);
5178
5179 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5180 I915_READ(PFIT_CONTROL));
5181 I915_WRITE(PFIT_CONTROL, 0);
5182 }
5183
5184 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5185 {
5186 struct drm_device *dev = crtc->dev;
5187 struct drm_i915_private *dev_priv = dev->dev_private;
5188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5189 struct intel_encoder *encoder;
5190 int pipe = intel_crtc->pipe;
5191
5192 if (!intel_crtc->active)
5193 return;
5194
5195 /*
5196 * Gen2 reports pipe underruns whenever all planes are disabled.
5197 * So diasble underrun reporting before all the planes get disabled.
5198 * FIXME: Need to fix the logic to work when we turn off all planes
5199 * but leave the pipe running.
5200 */
5201 if (IS_GEN2(dev))
5202 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5203
5204 /*
5205 * Vblank time updates from the shadow to live plane control register
5206 * are blocked if the memory self-refresh mode is active at that
5207 * moment. So to make sure the plane gets truly disabled, disable
5208 * first the self-refresh mode. The self-refresh enable bit in turn
5209 * will be checked/applied by the HW only at the next frame start
5210 * event which is after the vblank start event, so we need to have a
5211 * wait-for-vblank between disabling the plane and the pipe.
5212 */
5213 intel_set_memory_cxsr(dev_priv, false);
5214 intel_crtc_disable_planes(crtc);
5215
5216 /*
5217 * On gen2 planes are double buffered but the pipe isn't, so we must
5218 * wait for planes to fully turn off before disabling the pipe.
5219 * We also need to wait on all gmch platforms because of the
5220 * self-refresh mode constraint explained above.
5221 */
5222 intel_wait_for_vblank(dev, pipe);
5223
5224 for_each_encoder_on_crtc(dev, crtc, encoder)
5225 encoder->disable(encoder);
5226
5227 drm_crtc_vblank_off(crtc);
5228 assert_vblank_disabled(crtc);
5229
5230 intel_disable_pipe(intel_crtc);
5231
5232 i9xx_pfit_disable(intel_crtc);
5233
5234 for_each_encoder_on_crtc(dev, crtc, encoder)
5235 if (encoder->post_disable)
5236 encoder->post_disable(encoder);
5237
5238 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5239 if (IS_CHERRYVIEW(dev))
5240 chv_disable_pll(dev_priv, pipe);
5241 else if (IS_VALLEYVIEW(dev))
5242 vlv_disable_pll(dev_priv, pipe);
5243 else
5244 i9xx_disable_pll(intel_crtc);
5245 }
5246
5247 if (!IS_GEN2(dev))
5248 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5249
5250 intel_crtc->active = false;
5251 intel_update_watermarks(crtc);
5252
5253 mutex_lock(&dev->struct_mutex);
5254 intel_fbc_update(dev);
5255 mutex_unlock(&dev->struct_mutex);
5256 }
5257
5258 static void i9xx_crtc_off(struct drm_crtc *crtc)
5259 {
5260 }
5261
5262 /* Master function to enable/disable CRTC and corresponding power wells */
5263 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5264 {
5265 struct drm_device *dev = crtc->dev;
5266 struct drm_i915_private *dev_priv = dev->dev_private;
5267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5268 enum intel_display_power_domain domain;
5269 unsigned long domains;
5270
5271 if (enable) {
5272 if (!intel_crtc->active) {
5273 domains = get_crtc_power_domains(crtc);
5274 for_each_power_domain(domain, domains)
5275 intel_display_power_get(dev_priv, domain);
5276 intel_crtc->enabled_power_domains = domains;
5277
5278 dev_priv->display.crtc_enable(crtc);
5279 }
5280 } else {
5281 if (intel_crtc->active) {
5282 dev_priv->display.crtc_disable(crtc);
5283
5284 domains = intel_crtc->enabled_power_domains;
5285 for_each_power_domain(domain, domains)
5286 intel_display_power_put(dev_priv, domain);
5287 intel_crtc->enabled_power_domains = 0;
5288 }
5289 }
5290 }
5291
5292 /**
5293 * Sets the power management mode of the pipe and plane.
5294 */
5295 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5296 {
5297 struct drm_device *dev = crtc->dev;
5298 struct intel_encoder *intel_encoder;
5299 bool enable = false;
5300
5301 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5302 enable |= intel_encoder->connectors_active;
5303
5304 intel_crtc_control(crtc, enable);
5305 }
5306
5307 static void intel_crtc_disable(struct drm_crtc *crtc)
5308 {
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_connector *connector;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312
5313 /* crtc should still be enabled when we disable it. */
5314 WARN_ON(!crtc->enabled);
5315
5316 dev_priv->display.crtc_disable(crtc);
5317 dev_priv->display.off(crtc);
5318
5319 crtc->primary->funcs->disable_plane(crtc->primary);
5320
5321 /* Update computed state. */
5322 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5323 if (!connector->encoder || !connector->encoder->crtc)
5324 continue;
5325
5326 if (connector->encoder->crtc != crtc)
5327 continue;
5328
5329 connector->dpms = DRM_MODE_DPMS_OFF;
5330 to_intel_encoder(connector->encoder)->connectors_active = false;
5331 }
5332 }
5333
5334 void intel_encoder_destroy(struct drm_encoder *encoder)
5335 {
5336 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5337
5338 drm_encoder_cleanup(encoder);
5339 kfree(intel_encoder);
5340 }
5341
5342 /* Simple dpms helper for encoders with just one connector, no cloning and only
5343 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5344 * state of the entire output pipe. */
5345 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5346 {
5347 if (mode == DRM_MODE_DPMS_ON) {
5348 encoder->connectors_active = true;
5349
5350 intel_crtc_update_dpms(encoder->base.crtc);
5351 } else {
5352 encoder->connectors_active = false;
5353
5354 intel_crtc_update_dpms(encoder->base.crtc);
5355 }
5356 }
5357
5358 /* Cross check the actual hw state with our own modeset state tracking (and it's
5359 * internal consistency). */
5360 static void intel_connector_check_state(struct intel_connector *connector)
5361 {
5362 if (connector->get_hw_state(connector)) {
5363 struct intel_encoder *encoder = connector->encoder;
5364 struct drm_crtc *crtc;
5365 bool encoder_enabled;
5366 enum pipe pipe;
5367
5368 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5369 connector->base.base.id,
5370 connector->base.name);
5371
5372 /* there is no real hw state for MST connectors */
5373 if (connector->mst_port)
5374 return;
5375
5376 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5377 "wrong connector dpms state\n");
5378 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5379 "active connector not linked to encoder\n");
5380
5381 if (encoder) {
5382 I915_STATE_WARN(!encoder->connectors_active,
5383 "encoder->connectors_active not set\n");
5384
5385 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5386 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5387 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5388 return;
5389
5390 crtc = encoder->base.crtc;
5391
5392 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5393 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5394 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5395 "encoder active on the wrong pipe\n");
5396 }
5397 }
5398 }
5399
5400 /* Even simpler default implementation, if there's really no special case to
5401 * consider. */
5402 void intel_connector_dpms(struct drm_connector *connector, int mode)
5403 {
5404 /* All the simple cases only support two dpms states. */
5405 if (mode != DRM_MODE_DPMS_ON)
5406 mode = DRM_MODE_DPMS_OFF;
5407
5408 if (mode == connector->dpms)
5409 return;
5410
5411 connector->dpms = mode;
5412
5413 /* Only need to change hw state when actually enabled */
5414 if (connector->encoder)
5415 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5416
5417 intel_modeset_check_state(connector->dev);
5418 }
5419
5420 /* Simple connector->get_hw_state implementation for encoders that support only
5421 * one connector and no cloning and hence the encoder state determines the state
5422 * of the connector. */
5423 bool intel_connector_get_hw_state(struct intel_connector *connector)
5424 {
5425 enum pipe pipe = 0;
5426 struct intel_encoder *encoder = connector->encoder;
5427
5428 return encoder->get_hw_state(encoder, &pipe);
5429 }
5430
5431 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5432 struct intel_crtc_state *pipe_config)
5433 {
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 struct intel_crtc *pipe_B_crtc =
5436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5437
5438 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5439 pipe_name(pipe), pipe_config->fdi_lanes);
5440 if (pipe_config->fdi_lanes > 4) {
5441 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5442 pipe_name(pipe), pipe_config->fdi_lanes);
5443 return false;
5444 }
5445
5446 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5447 if (pipe_config->fdi_lanes > 2) {
5448 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5449 pipe_config->fdi_lanes);
5450 return false;
5451 } else {
5452 return true;
5453 }
5454 }
5455
5456 if (INTEL_INFO(dev)->num_pipes == 2)
5457 return true;
5458
5459 /* Ivybridge 3 pipe is really complicated */
5460 switch (pipe) {
5461 case PIPE_A:
5462 return true;
5463 case PIPE_B:
5464 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5465 pipe_config->fdi_lanes > 2) {
5466 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5467 pipe_name(pipe), pipe_config->fdi_lanes);
5468 return false;
5469 }
5470 return true;
5471 case PIPE_C:
5472 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5473 pipe_B_crtc->config->fdi_lanes <= 2) {
5474 if (pipe_config->fdi_lanes > 2) {
5475 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5476 pipe_name(pipe), pipe_config->fdi_lanes);
5477 return false;
5478 }
5479 } else {
5480 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5481 return false;
5482 }
5483 return true;
5484 default:
5485 BUG();
5486 }
5487 }
5488
5489 #define RETRY 1
5490 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5491 struct intel_crtc_state *pipe_config)
5492 {
5493 struct drm_device *dev = intel_crtc->base.dev;
5494 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5495 int lane, link_bw, fdi_dotclock;
5496 bool setup_ok, needs_recompute = false;
5497
5498 retry:
5499 /* FDI is a binary signal running at ~2.7GHz, encoding
5500 * each output octet as 10 bits. The actual frequency
5501 * is stored as a divider into a 100MHz clock, and the
5502 * mode pixel clock is stored in units of 1KHz.
5503 * Hence the bw of each lane in terms of the mode signal
5504 * is:
5505 */
5506 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5507
5508 fdi_dotclock = adjusted_mode->crtc_clock;
5509
5510 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5511 pipe_config->pipe_bpp);
5512
5513 pipe_config->fdi_lanes = lane;
5514
5515 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5516 link_bw, &pipe_config->fdi_m_n);
5517
5518 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5519 intel_crtc->pipe, pipe_config);
5520 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5521 pipe_config->pipe_bpp -= 2*3;
5522 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5523 pipe_config->pipe_bpp);
5524 needs_recompute = true;
5525 pipe_config->bw_constrained = true;
5526
5527 goto retry;
5528 }
5529
5530 if (needs_recompute)
5531 return RETRY;
5532
5533 return setup_ok ? 0 : -EINVAL;
5534 }
5535
5536 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5537 struct intel_crtc_state *pipe_config)
5538 {
5539 pipe_config->ips_enabled = i915.enable_ips &&
5540 hsw_crtc_supports_ips(crtc) &&
5541 pipe_config->pipe_bpp <= 24;
5542 }
5543
5544 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5545 struct intel_crtc_state *pipe_config)
5546 {
5547 struct drm_device *dev = crtc->base.dev;
5548 struct drm_i915_private *dev_priv = dev->dev_private;
5549 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5550
5551 /* FIXME should check pixel clock limits on all platforms */
5552 if (INTEL_INFO(dev)->gen < 4) {
5553 int clock_limit =
5554 dev_priv->display.get_display_clock_speed(dev);
5555
5556 /*
5557 * Enable pixel doubling when the dot clock
5558 * is > 90% of the (display) core speed.
5559 *
5560 * GDG double wide on either pipe,
5561 * otherwise pipe A only.
5562 */
5563 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5564 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5565 clock_limit *= 2;
5566 pipe_config->double_wide = true;
5567 }
5568
5569 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5570 return -EINVAL;
5571 }
5572
5573 /*
5574 * Pipe horizontal size must be even in:
5575 * - DVO ganged mode
5576 * - LVDS dual channel mode
5577 * - Double wide pipe
5578 */
5579 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5580 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5581 pipe_config->pipe_src_w &= ~1;
5582
5583 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5584 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5585 */
5586 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5587 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5588 return -EINVAL;
5589
5590 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5591 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5592 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5593 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5594 * for lvds. */
5595 pipe_config->pipe_bpp = 8*3;
5596 }
5597
5598 if (HAS_IPS(dev))
5599 hsw_compute_ips_config(crtc, pipe_config);
5600
5601 if (pipe_config->has_pch_encoder)
5602 return ironlake_fdi_compute_config(crtc, pipe_config);
5603
5604 return 0;
5605 }
5606
5607 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5608 {
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610 u32 val;
5611 int divider;
5612
5613 /* FIXME: Punit isn't quite ready yet */
5614 if (IS_CHERRYVIEW(dev))
5615 return 400000;
5616
5617 if (dev_priv->hpll_freq == 0)
5618 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5619
5620 mutex_lock(&dev_priv->dpio_lock);
5621 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5622 mutex_unlock(&dev_priv->dpio_lock);
5623
5624 divider = val & DISPLAY_FREQUENCY_VALUES;
5625
5626 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5627 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5628 "cdclk change in progress\n");
5629
5630 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5631 }
5632
5633 static int i945_get_display_clock_speed(struct drm_device *dev)
5634 {
5635 return 400000;
5636 }
5637
5638 static int i915_get_display_clock_speed(struct drm_device *dev)
5639 {
5640 return 333000;
5641 }
5642
5643 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5644 {
5645 return 200000;
5646 }
5647
5648 static int pnv_get_display_clock_speed(struct drm_device *dev)
5649 {
5650 u16 gcfgc = 0;
5651
5652 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5653
5654 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5655 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5656 return 267000;
5657 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5658 return 333000;
5659 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5660 return 444000;
5661 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5662 return 200000;
5663 default:
5664 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5665 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5666 return 133000;
5667 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5668 return 167000;
5669 }
5670 }
5671
5672 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5673 {
5674 u16 gcfgc = 0;
5675
5676 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5677
5678 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5679 return 133000;
5680 else {
5681 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5682 case GC_DISPLAY_CLOCK_333_MHZ:
5683 return 333000;
5684 default:
5685 case GC_DISPLAY_CLOCK_190_200_MHZ:
5686 return 190000;
5687 }
5688 }
5689 }
5690
5691 static int i865_get_display_clock_speed(struct drm_device *dev)
5692 {
5693 return 266000;
5694 }
5695
5696 static int i855_get_display_clock_speed(struct drm_device *dev)
5697 {
5698 u16 hpllcc = 0;
5699 /* Assume that the hardware is in the high speed state. This
5700 * should be the default.
5701 */
5702 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5703 case GC_CLOCK_133_200:
5704 case GC_CLOCK_100_200:
5705 return 200000;
5706 case GC_CLOCK_166_250:
5707 return 250000;
5708 case GC_CLOCK_100_133:
5709 return 133000;
5710 }
5711
5712 /* Shouldn't happen */
5713 return 0;
5714 }
5715
5716 static int i830_get_display_clock_speed(struct drm_device *dev)
5717 {
5718 return 133000;
5719 }
5720
5721 static void
5722 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5723 {
5724 while (*num > DATA_LINK_M_N_MASK ||
5725 *den > DATA_LINK_M_N_MASK) {
5726 *num >>= 1;
5727 *den >>= 1;
5728 }
5729 }
5730
5731 static void compute_m_n(unsigned int m, unsigned int n,
5732 uint32_t *ret_m, uint32_t *ret_n)
5733 {
5734 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5735 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5736 intel_reduce_m_n_ratio(ret_m, ret_n);
5737 }
5738
5739 void
5740 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5741 int pixel_clock, int link_clock,
5742 struct intel_link_m_n *m_n)
5743 {
5744 m_n->tu = 64;
5745
5746 compute_m_n(bits_per_pixel * pixel_clock,
5747 link_clock * nlanes * 8,
5748 &m_n->gmch_m, &m_n->gmch_n);
5749
5750 compute_m_n(pixel_clock, link_clock,
5751 &m_n->link_m, &m_n->link_n);
5752 }
5753
5754 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5755 {
5756 if (i915.panel_use_ssc >= 0)
5757 return i915.panel_use_ssc != 0;
5758 return dev_priv->vbt.lvds_use_ssc
5759 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5760 }
5761
5762 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 int refclk;
5767
5768 if (IS_VALLEYVIEW(dev)) {
5769 refclk = 100000;
5770 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5771 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5772 refclk = dev_priv->vbt.lvds_ssc_freq;
5773 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5774 } else if (!IS_GEN2(dev)) {
5775 refclk = 96000;
5776 } else {
5777 refclk = 48000;
5778 }
5779
5780 return refclk;
5781 }
5782
5783 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5784 {
5785 return (1 << dpll->n) << 16 | dpll->m2;
5786 }
5787
5788 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5789 {
5790 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5791 }
5792
5793 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5794 struct intel_crtc_state *crtc_state,
5795 intel_clock_t *reduced_clock)
5796 {
5797 struct drm_device *dev = crtc->base.dev;
5798 u32 fp, fp2 = 0;
5799
5800 if (IS_PINEVIEW(dev)) {
5801 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5802 if (reduced_clock)
5803 fp2 = pnv_dpll_compute_fp(reduced_clock);
5804 } else {
5805 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5806 if (reduced_clock)
5807 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5808 }
5809
5810 crtc_state->dpll_hw_state.fp0 = fp;
5811
5812 crtc->lowfreq_avail = false;
5813 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5814 reduced_clock && i915.powersave) {
5815 crtc_state->dpll_hw_state.fp1 = fp2;
5816 crtc->lowfreq_avail = true;
5817 } else {
5818 crtc_state->dpll_hw_state.fp1 = fp;
5819 }
5820 }
5821
5822 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5823 pipe)
5824 {
5825 u32 reg_val;
5826
5827 /*
5828 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5829 * and set it to a reasonable value instead.
5830 */
5831 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5832 reg_val &= 0xffffff00;
5833 reg_val |= 0x00000030;
5834 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5835
5836 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5837 reg_val &= 0x8cffffff;
5838 reg_val = 0x8c000000;
5839 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5840
5841 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5842 reg_val &= 0xffffff00;
5843 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5844
5845 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5846 reg_val &= 0x00ffffff;
5847 reg_val |= 0xb0000000;
5848 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5849 }
5850
5851 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5852 struct intel_link_m_n *m_n)
5853 {
5854 struct drm_device *dev = crtc->base.dev;
5855 struct drm_i915_private *dev_priv = dev->dev_private;
5856 int pipe = crtc->pipe;
5857
5858 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5859 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5860 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5861 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5862 }
5863
5864 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5865 struct intel_link_m_n *m_n,
5866 struct intel_link_m_n *m2_n2)
5867 {
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 int pipe = crtc->pipe;
5871 enum transcoder transcoder = crtc->config->cpu_transcoder;
5872
5873 if (INTEL_INFO(dev)->gen >= 5) {
5874 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5875 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5876 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5877 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5878 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5879 * for gen < 8) and if DRRS is supported (to make sure the
5880 * registers are not unnecessarily accessed).
5881 */
5882 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5883 crtc->config->has_drrs) {
5884 I915_WRITE(PIPE_DATA_M2(transcoder),
5885 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5886 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5887 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5888 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5889 }
5890 } else {
5891 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5892 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5893 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5894 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5895 }
5896 }
5897
5898 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
5899 {
5900 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
5901
5902 if (m_n == M1_N1) {
5903 dp_m_n = &crtc->config->dp_m_n;
5904 dp_m2_n2 = &crtc->config->dp_m2_n2;
5905 } else if (m_n == M2_N2) {
5906
5907 /*
5908 * M2_N2 registers are not supported. Hence m2_n2 divider value
5909 * needs to be programmed into M1_N1.
5910 */
5911 dp_m_n = &crtc->config->dp_m2_n2;
5912 } else {
5913 DRM_ERROR("Unsupported divider value\n");
5914 return;
5915 }
5916
5917 if (crtc->config->has_pch_encoder)
5918 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5919 else
5920 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
5921 }
5922
5923 static void vlv_update_pll(struct intel_crtc *crtc,
5924 struct intel_crtc_state *pipe_config)
5925 {
5926 u32 dpll, dpll_md;
5927
5928 /*
5929 * Enable DPIO clock input. We should never disable the reference
5930 * clock for pipe B, since VGA hotplug / manual detection depends
5931 * on it.
5932 */
5933 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5934 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5935 /* We should never disable this, set it here for state tracking */
5936 if (crtc->pipe == PIPE_B)
5937 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5938 dpll |= DPLL_VCO_ENABLE;
5939 pipe_config->dpll_hw_state.dpll = dpll;
5940
5941 dpll_md = (pipe_config->pixel_multiplier - 1)
5942 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5943 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5944 }
5945
5946 static void vlv_prepare_pll(struct intel_crtc *crtc,
5947 const struct intel_crtc_state *pipe_config)
5948 {
5949 struct drm_device *dev = crtc->base.dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 int pipe = crtc->pipe;
5952 u32 mdiv;
5953 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5954 u32 coreclk, reg_val;
5955
5956 mutex_lock(&dev_priv->dpio_lock);
5957
5958 bestn = pipe_config->dpll.n;
5959 bestm1 = pipe_config->dpll.m1;
5960 bestm2 = pipe_config->dpll.m2;
5961 bestp1 = pipe_config->dpll.p1;
5962 bestp2 = pipe_config->dpll.p2;
5963
5964 /* See eDP HDMI DPIO driver vbios notes doc */
5965
5966 /* PLL B needs special handling */
5967 if (pipe == PIPE_B)
5968 vlv_pllb_recal_opamp(dev_priv, pipe);
5969
5970 /* Set up Tx target for periodic Rcomp update */
5971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5972
5973 /* Disable target IRef on PLL */
5974 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5975 reg_val &= 0x00ffffff;
5976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5977
5978 /* Disable fast lock */
5979 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5980
5981 /* Set idtafcrecal before PLL is enabled */
5982 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5983 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5984 mdiv |= ((bestn << DPIO_N_SHIFT));
5985 mdiv |= (1 << DPIO_K_SHIFT);
5986
5987 /*
5988 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5989 * but we don't support that).
5990 * Note: don't use the DAC post divider as it seems unstable.
5991 */
5992 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5993 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5994
5995 mdiv |= DPIO_ENABLE_CALIBRATION;
5996 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5997
5998 /* Set HBR and RBR LPF coefficients */
5999 if (pipe_config->port_clock == 162000 ||
6000 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6001 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6002 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6003 0x009f0003);
6004 else
6005 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6006 0x00d0000f);
6007
6008 if (pipe_config->has_dp_encoder) {
6009 /* Use SSC source */
6010 if (pipe == PIPE_A)
6011 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6012 0x0df40000);
6013 else
6014 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6015 0x0df70000);
6016 } else { /* HDMI or VGA */
6017 /* Use bend source */
6018 if (pipe == PIPE_A)
6019 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6020 0x0df70000);
6021 else
6022 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6023 0x0df40000);
6024 }
6025
6026 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6027 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6028 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6029 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6030 coreclk |= 0x01000000;
6031 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6032
6033 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6034 mutex_unlock(&dev_priv->dpio_lock);
6035 }
6036
6037 static void chv_update_pll(struct intel_crtc *crtc,
6038 struct intel_crtc_state *pipe_config)
6039 {
6040 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6041 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6042 DPLL_VCO_ENABLE;
6043 if (crtc->pipe != PIPE_A)
6044 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6045
6046 pipe_config->dpll_hw_state.dpll_md =
6047 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6048 }
6049
6050 static void chv_prepare_pll(struct intel_crtc *crtc,
6051 const struct intel_crtc_state *pipe_config)
6052 {
6053 struct drm_device *dev = crtc->base.dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 int pipe = crtc->pipe;
6056 int dpll_reg = DPLL(crtc->pipe);
6057 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6058 u32 loopfilter, intcoeff;
6059 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6060 int refclk;
6061
6062 bestn = pipe_config->dpll.n;
6063 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6064 bestm1 = pipe_config->dpll.m1;
6065 bestm2 = pipe_config->dpll.m2 >> 22;
6066 bestp1 = pipe_config->dpll.p1;
6067 bestp2 = pipe_config->dpll.p2;
6068
6069 /*
6070 * Enable Refclk and SSC
6071 */
6072 I915_WRITE(dpll_reg,
6073 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6074
6075 mutex_lock(&dev_priv->dpio_lock);
6076
6077 /* p1 and p2 divider */
6078 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6079 5 << DPIO_CHV_S1_DIV_SHIFT |
6080 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6081 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6082 1 << DPIO_CHV_K_DIV_SHIFT);
6083
6084 /* Feedback post-divider - m2 */
6085 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6086
6087 /* Feedback refclk divider - n and m1 */
6088 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6089 DPIO_CHV_M1_DIV_BY_2 |
6090 1 << DPIO_CHV_N_DIV_SHIFT);
6091
6092 /* M2 fraction division */
6093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6094
6095 /* M2 fraction division enable */
6096 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6097 DPIO_CHV_FRAC_DIV_EN |
6098 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6099
6100 /* Loop filter */
6101 refclk = i9xx_get_refclk(crtc, 0);
6102 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6103 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6104 if (refclk == 100000)
6105 intcoeff = 11;
6106 else if (refclk == 38400)
6107 intcoeff = 10;
6108 else
6109 intcoeff = 9;
6110 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6111 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6112
6113 /* AFC Recal */
6114 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6115 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6116 DPIO_AFC_RECAL);
6117
6118 mutex_unlock(&dev_priv->dpio_lock);
6119 }
6120
6121 /**
6122 * vlv_force_pll_on - forcibly enable just the PLL
6123 * @dev_priv: i915 private structure
6124 * @pipe: pipe PLL to enable
6125 * @dpll: PLL configuration
6126 *
6127 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6128 * in cases where we need the PLL enabled even when @pipe is not going to
6129 * be enabled.
6130 */
6131 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6132 const struct dpll *dpll)
6133 {
6134 struct intel_crtc *crtc =
6135 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6136 struct intel_crtc_state pipe_config = {
6137 .pixel_multiplier = 1,
6138 .dpll = *dpll,
6139 };
6140
6141 if (IS_CHERRYVIEW(dev)) {
6142 chv_update_pll(crtc, &pipe_config);
6143 chv_prepare_pll(crtc, &pipe_config);
6144 chv_enable_pll(crtc, &pipe_config);
6145 } else {
6146 vlv_update_pll(crtc, &pipe_config);
6147 vlv_prepare_pll(crtc, &pipe_config);
6148 vlv_enable_pll(crtc, &pipe_config);
6149 }
6150 }
6151
6152 /**
6153 * vlv_force_pll_off - forcibly disable just the PLL
6154 * @dev_priv: i915 private structure
6155 * @pipe: pipe PLL to disable
6156 *
6157 * Disable the PLL for @pipe. To be used in cases where we need
6158 * the PLL enabled even when @pipe is not going to be enabled.
6159 */
6160 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6161 {
6162 if (IS_CHERRYVIEW(dev))
6163 chv_disable_pll(to_i915(dev), pipe);
6164 else
6165 vlv_disable_pll(to_i915(dev), pipe);
6166 }
6167
6168 static void i9xx_update_pll(struct intel_crtc *crtc,
6169 struct intel_crtc_state *crtc_state,
6170 intel_clock_t *reduced_clock,
6171 int num_connectors)
6172 {
6173 struct drm_device *dev = crtc->base.dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 u32 dpll;
6176 bool is_sdvo;
6177 struct dpll *clock = &crtc_state->dpll;
6178
6179 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6180
6181 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6182 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6183
6184 dpll = DPLL_VGA_MODE_DIS;
6185
6186 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6187 dpll |= DPLLB_MODE_LVDS;
6188 else
6189 dpll |= DPLLB_MODE_DAC_SERIAL;
6190
6191 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6192 dpll |= (crtc_state->pixel_multiplier - 1)
6193 << SDVO_MULTIPLIER_SHIFT_HIRES;
6194 }
6195
6196 if (is_sdvo)
6197 dpll |= DPLL_SDVO_HIGH_SPEED;
6198
6199 if (crtc_state->has_dp_encoder)
6200 dpll |= DPLL_SDVO_HIGH_SPEED;
6201
6202 /* compute bitmask from p1 value */
6203 if (IS_PINEVIEW(dev))
6204 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6205 else {
6206 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6207 if (IS_G4X(dev) && reduced_clock)
6208 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6209 }
6210 switch (clock->p2) {
6211 case 5:
6212 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6213 break;
6214 case 7:
6215 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6216 break;
6217 case 10:
6218 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6219 break;
6220 case 14:
6221 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6222 break;
6223 }
6224 if (INTEL_INFO(dev)->gen >= 4)
6225 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6226
6227 if (crtc_state->sdvo_tv_clock)
6228 dpll |= PLL_REF_INPUT_TVCLKINBC;
6229 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6230 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6231 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6232 else
6233 dpll |= PLL_REF_INPUT_DREFCLK;
6234
6235 dpll |= DPLL_VCO_ENABLE;
6236 crtc_state->dpll_hw_state.dpll = dpll;
6237
6238 if (INTEL_INFO(dev)->gen >= 4) {
6239 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6240 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6241 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6242 }
6243 }
6244
6245 static void i8xx_update_pll(struct intel_crtc *crtc,
6246 struct intel_crtc_state *crtc_state,
6247 intel_clock_t *reduced_clock,
6248 int num_connectors)
6249 {
6250 struct drm_device *dev = crtc->base.dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252 u32 dpll;
6253 struct dpll *clock = &crtc_state->dpll;
6254
6255 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6256
6257 dpll = DPLL_VGA_MODE_DIS;
6258
6259 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6260 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6261 } else {
6262 if (clock->p1 == 2)
6263 dpll |= PLL_P1_DIVIDE_BY_TWO;
6264 else
6265 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6266 if (clock->p2 == 4)
6267 dpll |= PLL_P2_DIVIDE_BY_4;
6268 }
6269
6270 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6271 dpll |= DPLL_DVO_2X_MODE;
6272
6273 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6274 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6275 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6276 else
6277 dpll |= PLL_REF_INPUT_DREFCLK;
6278
6279 dpll |= DPLL_VCO_ENABLE;
6280 crtc_state->dpll_hw_state.dpll = dpll;
6281 }
6282
6283 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6284 {
6285 struct drm_device *dev = intel_crtc->base.dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 enum pipe pipe = intel_crtc->pipe;
6288 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6289 struct drm_display_mode *adjusted_mode =
6290 &intel_crtc->config->base.adjusted_mode;
6291 uint32_t crtc_vtotal, crtc_vblank_end;
6292 int vsyncshift = 0;
6293
6294 /* We need to be careful not to changed the adjusted mode, for otherwise
6295 * the hw state checker will get angry at the mismatch. */
6296 crtc_vtotal = adjusted_mode->crtc_vtotal;
6297 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6298
6299 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6300 /* the chip adds 2 halflines automatically */
6301 crtc_vtotal -= 1;
6302 crtc_vblank_end -= 1;
6303
6304 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6305 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6306 else
6307 vsyncshift = adjusted_mode->crtc_hsync_start -
6308 adjusted_mode->crtc_htotal / 2;
6309 if (vsyncshift < 0)
6310 vsyncshift += adjusted_mode->crtc_htotal;
6311 }
6312
6313 if (INTEL_INFO(dev)->gen > 3)
6314 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6315
6316 I915_WRITE(HTOTAL(cpu_transcoder),
6317 (adjusted_mode->crtc_hdisplay - 1) |
6318 ((adjusted_mode->crtc_htotal - 1) << 16));
6319 I915_WRITE(HBLANK(cpu_transcoder),
6320 (adjusted_mode->crtc_hblank_start - 1) |
6321 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6322 I915_WRITE(HSYNC(cpu_transcoder),
6323 (adjusted_mode->crtc_hsync_start - 1) |
6324 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6325
6326 I915_WRITE(VTOTAL(cpu_transcoder),
6327 (adjusted_mode->crtc_vdisplay - 1) |
6328 ((crtc_vtotal - 1) << 16));
6329 I915_WRITE(VBLANK(cpu_transcoder),
6330 (adjusted_mode->crtc_vblank_start - 1) |
6331 ((crtc_vblank_end - 1) << 16));
6332 I915_WRITE(VSYNC(cpu_transcoder),
6333 (adjusted_mode->crtc_vsync_start - 1) |
6334 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6335
6336 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6337 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6338 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6339 * bits. */
6340 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6341 (pipe == PIPE_B || pipe == PIPE_C))
6342 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6343
6344 /* pipesrc controls the size that is scaled from, which should
6345 * always be the user's requested size.
6346 */
6347 I915_WRITE(PIPESRC(pipe),
6348 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6349 (intel_crtc->config->pipe_src_h - 1));
6350 }
6351
6352 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6353 struct intel_crtc_state *pipe_config)
6354 {
6355 struct drm_device *dev = crtc->base.dev;
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6358 uint32_t tmp;
6359
6360 tmp = I915_READ(HTOTAL(cpu_transcoder));
6361 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6362 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6363 tmp = I915_READ(HBLANK(cpu_transcoder));
6364 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6365 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6366 tmp = I915_READ(HSYNC(cpu_transcoder));
6367 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6368 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6369
6370 tmp = I915_READ(VTOTAL(cpu_transcoder));
6371 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6372 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6373 tmp = I915_READ(VBLANK(cpu_transcoder));
6374 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6375 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6376 tmp = I915_READ(VSYNC(cpu_transcoder));
6377 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6378 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6379
6380 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6381 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6382 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6383 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6384 }
6385
6386 tmp = I915_READ(PIPESRC(crtc->pipe));
6387 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6388 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6389
6390 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6391 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6392 }
6393
6394 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6395 struct intel_crtc_state *pipe_config)
6396 {
6397 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6398 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6399 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6400 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6401
6402 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6403 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6404 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6405 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6406
6407 mode->flags = pipe_config->base.adjusted_mode.flags;
6408
6409 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6410 mode->flags |= pipe_config->base.adjusted_mode.flags;
6411 }
6412
6413 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6414 {
6415 struct drm_device *dev = intel_crtc->base.dev;
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 uint32_t pipeconf;
6418
6419 pipeconf = 0;
6420
6421 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6422 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6423 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6424
6425 if (intel_crtc->config->double_wide)
6426 pipeconf |= PIPECONF_DOUBLE_WIDE;
6427
6428 /* only g4x and later have fancy bpc/dither controls */
6429 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6430 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6431 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6432 pipeconf |= PIPECONF_DITHER_EN |
6433 PIPECONF_DITHER_TYPE_SP;
6434
6435 switch (intel_crtc->config->pipe_bpp) {
6436 case 18:
6437 pipeconf |= PIPECONF_6BPC;
6438 break;
6439 case 24:
6440 pipeconf |= PIPECONF_8BPC;
6441 break;
6442 case 30:
6443 pipeconf |= PIPECONF_10BPC;
6444 break;
6445 default:
6446 /* Case prevented by intel_choose_pipe_bpp_dither. */
6447 BUG();
6448 }
6449 }
6450
6451 if (HAS_PIPE_CXSR(dev)) {
6452 if (intel_crtc->lowfreq_avail) {
6453 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6454 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6455 } else {
6456 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6457 }
6458 }
6459
6460 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6461 if (INTEL_INFO(dev)->gen < 4 ||
6462 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6463 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6464 else
6465 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6466 } else
6467 pipeconf |= PIPECONF_PROGRESSIVE;
6468
6469 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6470 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6471
6472 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6473 POSTING_READ(PIPECONF(intel_crtc->pipe));
6474 }
6475
6476 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6477 struct intel_crtc_state *crtc_state)
6478 {
6479 struct drm_device *dev = crtc->base.dev;
6480 struct drm_i915_private *dev_priv = dev->dev_private;
6481 int refclk, num_connectors = 0;
6482 intel_clock_t clock, reduced_clock;
6483 bool ok, has_reduced_clock = false;
6484 bool is_lvds = false, is_dsi = false;
6485 struct intel_encoder *encoder;
6486 const intel_limit_t *limit;
6487
6488 for_each_intel_encoder(dev, encoder) {
6489 if (encoder->new_crtc != crtc)
6490 continue;
6491
6492 switch (encoder->type) {
6493 case INTEL_OUTPUT_LVDS:
6494 is_lvds = true;
6495 break;
6496 case INTEL_OUTPUT_DSI:
6497 is_dsi = true;
6498 break;
6499 default:
6500 break;
6501 }
6502
6503 num_connectors++;
6504 }
6505
6506 if (is_dsi)
6507 return 0;
6508
6509 if (!crtc_state->clock_set) {
6510 refclk = i9xx_get_refclk(crtc, num_connectors);
6511
6512 /*
6513 * Returns a set of divisors for the desired target clock with
6514 * the given refclk, or FALSE. The returned values represent
6515 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6516 * 2) / p1 / p2.
6517 */
6518 limit = intel_limit(crtc, refclk);
6519 ok = dev_priv->display.find_dpll(limit, crtc,
6520 crtc_state->port_clock,
6521 refclk, NULL, &clock);
6522 if (!ok) {
6523 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6524 return -EINVAL;
6525 }
6526
6527 if (is_lvds && dev_priv->lvds_downclock_avail) {
6528 /*
6529 * Ensure we match the reduced clock's P to the target
6530 * clock. If the clocks don't match, we can't switch
6531 * the display clock by using the FP0/FP1. In such case
6532 * we will disable the LVDS downclock feature.
6533 */
6534 has_reduced_clock =
6535 dev_priv->display.find_dpll(limit, crtc,
6536 dev_priv->lvds_downclock,
6537 refclk, &clock,
6538 &reduced_clock);
6539 }
6540 /* Compat-code for transition, will disappear. */
6541 crtc_state->dpll.n = clock.n;
6542 crtc_state->dpll.m1 = clock.m1;
6543 crtc_state->dpll.m2 = clock.m2;
6544 crtc_state->dpll.p1 = clock.p1;
6545 crtc_state->dpll.p2 = clock.p2;
6546 }
6547
6548 if (IS_GEN2(dev)) {
6549 i8xx_update_pll(crtc, crtc_state,
6550 has_reduced_clock ? &reduced_clock : NULL,
6551 num_connectors);
6552 } else if (IS_CHERRYVIEW(dev)) {
6553 chv_update_pll(crtc, crtc_state);
6554 } else if (IS_VALLEYVIEW(dev)) {
6555 vlv_update_pll(crtc, crtc_state);
6556 } else {
6557 i9xx_update_pll(crtc, crtc_state,
6558 has_reduced_clock ? &reduced_clock : NULL,
6559 num_connectors);
6560 }
6561
6562 return 0;
6563 }
6564
6565 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6566 struct intel_crtc_state *pipe_config)
6567 {
6568 struct drm_device *dev = crtc->base.dev;
6569 struct drm_i915_private *dev_priv = dev->dev_private;
6570 uint32_t tmp;
6571
6572 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6573 return;
6574
6575 tmp = I915_READ(PFIT_CONTROL);
6576 if (!(tmp & PFIT_ENABLE))
6577 return;
6578
6579 /* Check whether the pfit is attached to our pipe. */
6580 if (INTEL_INFO(dev)->gen < 4) {
6581 if (crtc->pipe != PIPE_B)
6582 return;
6583 } else {
6584 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6585 return;
6586 }
6587
6588 pipe_config->gmch_pfit.control = tmp;
6589 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6590 if (INTEL_INFO(dev)->gen < 5)
6591 pipe_config->gmch_pfit.lvds_border_bits =
6592 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6593 }
6594
6595 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6596 struct intel_crtc_state *pipe_config)
6597 {
6598 struct drm_device *dev = crtc->base.dev;
6599 struct drm_i915_private *dev_priv = dev->dev_private;
6600 int pipe = pipe_config->cpu_transcoder;
6601 intel_clock_t clock;
6602 u32 mdiv;
6603 int refclk = 100000;
6604
6605 /* In case of MIPI DPLL will not even be used */
6606 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6607 return;
6608
6609 mutex_lock(&dev_priv->dpio_lock);
6610 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6611 mutex_unlock(&dev_priv->dpio_lock);
6612
6613 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6614 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6615 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6616 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6617 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6618
6619 vlv_clock(refclk, &clock);
6620
6621 /* clock.dot is the fast clock */
6622 pipe_config->port_clock = clock.dot / 5;
6623 }
6624
6625 static void
6626 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6627 struct intel_initial_plane_config *plane_config)
6628 {
6629 struct drm_device *dev = crtc->base.dev;
6630 struct drm_i915_private *dev_priv = dev->dev_private;
6631 u32 val, base, offset;
6632 int pipe = crtc->pipe, plane = crtc->plane;
6633 int fourcc, pixel_format;
6634 int aligned_height;
6635 struct drm_framebuffer *fb;
6636 struct intel_framebuffer *intel_fb;
6637
6638 val = I915_READ(DSPCNTR(plane));
6639 if (!(val & DISPLAY_PLANE_ENABLE))
6640 return;
6641
6642 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6643 if (!intel_fb) {
6644 DRM_DEBUG_KMS("failed to alloc fb\n");
6645 return;
6646 }
6647
6648 fb = &intel_fb->base;
6649
6650 if (INTEL_INFO(dev)->gen >= 4) {
6651 if (val & DISPPLANE_TILED) {
6652 plane_config->tiling = I915_TILING_X;
6653 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6654 }
6655 }
6656
6657 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6658 fourcc = i9xx_format_to_fourcc(pixel_format);
6659 fb->pixel_format = fourcc;
6660 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6661
6662 if (INTEL_INFO(dev)->gen >= 4) {
6663 if (plane_config->tiling)
6664 offset = I915_READ(DSPTILEOFF(plane));
6665 else
6666 offset = I915_READ(DSPLINOFF(plane));
6667 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6668 } else {
6669 base = I915_READ(DSPADDR(plane));
6670 }
6671 plane_config->base = base;
6672
6673 val = I915_READ(PIPESRC(pipe));
6674 fb->width = ((val >> 16) & 0xfff) + 1;
6675 fb->height = ((val >> 0) & 0xfff) + 1;
6676
6677 val = I915_READ(DSPSTRIDE(pipe));
6678 fb->pitches[0] = val & 0xffffffc0;
6679
6680 aligned_height = intel_fb_align_height(dev, fb->height,
6681 fb->pixel_format,
6682 fb->modifier[0]);
6683
6684 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6685
6686 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6687 pipe_name(pipe), plane, fb->width, fb->height,
6688 fb->bits_per_pixel, base, fb->pitches[0],
6689 plane_config->size);
6690
6691 plane_config->fb = intel_fb;
6692 }
6693
6694 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6695 struct intel_crtc_state *pipe_config)
6696 {
6697 struct drm_device *dev = crtc->base.dev;
6698 struct drm_i915_private *dev_priv = dev->dev_private;
6699 int pipe = pipe_config->cpu_transcoder;
6700 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6701 intel_clock_t clock;
6702 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6703 int refclk = 100000;
6704
6705 mutex_lock(&dev_priv->dpio_lock);
6706 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6707 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6708 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6709 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6710 mutex_unlock(&dev_priv->dpio_lock);
6711
6712 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6713 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6714 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6715 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6716 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6717
6718 chv_clock(refclk, &clock);
6719
6720 /* clock.dot is the fast clock */
6721 pipe_config->port_clock = clock.dot / 5;
6722 }
6723
6724 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6725 struct intel_crtc_state *pipe_config)
6726 {
6727 struct drm_device *dev = crtc->base.dev;
6728 struct drm_i915_private *dev_priv = dev->dev_private;
6729 uint32_t tmp;
6730
6731 if (!intel_display_power_is_enabled(dev_priv,
6732 POWER_DOMAIN_PIPE(crtc->pipe)))
6733 return false;
6734
6735 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6736 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6737
6738 tmp = I915_READ(PIPECONF(crtc->pipe));
6739 if (!(tmp & PIPECONF_ENABLE))
6740 return false;
6741
6742 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6743 switch (tmp & PIPECONF_BPC_MASK) {
6744 case PIPECONF_6BPC:
6745 pipe_config->pipe_bpp = 18;
6746 break;
6747 case PIPECONF_8BPC:
6748 pipe_config->pipe_bpp = 24;
6749 break;
6750 case PIPECONF_10BPC:
6751 pipe_config->pipe_bpp = 30;
6752 break;
6753 default:
6754 break;
6755 }
6756 }
6757
6758 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6759 pipe_config->limited_color_range = true;
6760
6761 if (INTEL_INFO(dev)->gen < 4)
6762 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6763
6764 intel_get_pipe_timings(crtc, pipe_config);
6765
6766 i9xx_get_pfit_config(crtc, pipe_config);
6767
6768 if (INTEL_INFO(dev)->gen >= 4) {
6769 tmp = I915_READ(DPLL_MD(crtc->pipe));
6770 pipe_config->pixel_multiplier =
6771 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6772 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6773 pipe_config->dpll_hw_state.dpll_md = tmp;
6774 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6775 tmp = I915_READ(DPLL(crtc->pipe));
6776 pipe_config->pixel_multiplier =
6777 ((tmp & SDVO_MULTIPLIER_MASK)
6778 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6779 } else {
6780 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6781 * port and will be fixed up in the encoder->get_config
6782 * function. */
6783 pipe_config->pixel_multiplier = 1;
6784 }
6785 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6786 if (!IS_VALLEYVIEW(dev)) {
6787 /*
6788 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6789 * on 830. Filter it out here so that we don't
6790 * report errors due to that.
6791 */
6792 if (IS_I830(dev))
6793 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6794
6795 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6796 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6797 } else {
6798 /* Mask out read-only status bits. */
6799 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6800 DPLL_PORTC_READY_MASK |
6801 DPLL_PORTB_READY_MASK);
6802 }
6803
6804 if (IS_CHERRYVIEW(dev))
6805 chv_crtc_clock_get(crtc, pipe_config);
6806 else if (IS_VALLEYVIEW(dev))
6807 vlv_crtc_clock_get(crtc, pipe_config);
6808 else
6809 i9xx_crtc_clock_get(crtc, pipe_config);
6810
6811 return true;
6812 }
6813
6814 static void ironlake_init_pch_refclk(struct drm_device *dev)
6815 {
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817 struct intel_encoder *encoder;
6818 u32 val, final;
6819 bool has_lvds = false;
6820 bool has_cpu_edp = false;
6821 bool has_panel = false;
6822 bool has_ck505 = false;
6823 bool can_ssc = false;
6824
6825 /* We need to take the global config into account */
6826 for_each_intel_encoder(dev, encoder) {
6827 switch (encoder->type) {
6828 case INTEL_OUTPUT_LVDS:
6829 has_panel = true;
6830 has_lvds = true;
6831 break;
6832 case INTEL_OUTPUT_EDP:
6833 has_panel = true;
6834 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6835 has_cpu_edp = true;
6836 break;
6837 default:
6838 break;
6839 }
6840 }
6841
6842 if (HAS_PCH_IBX(dev)) {
6843 has_ck505 = dev_priv->vbt.display_clock_mode;
6844 can_ssc = has_ck505;
6845 } else {
6846 has_ck505 = false;
6847 can_ssc = true;
6848 }
6849
6850 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6851 has_panel, has_lvds, has_ck505);
6852
6853 /* Ironlake: try to setup display ref clock before DPLL
6854 * enabling. This is only under driver's control after
6855 * PCH B stepping, previous chipset stepping should be
6856 * ignoring this setting.
6857 */
6858 val = I915_READ(PCH_DREF_CONTROL);
6859
6860 /* As we must carefully and slowly disable/enable each source in turn,
6861 * compute the final state we want first and check if we need to
6862 * make any changes at all.
6863 */
6864 final = val;
6865 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6866 if (has_ck505)
6867 final |= DREF_NONSPREAD_CK505_ENABLE;
6868 else
6869 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6870
6871 final &= ~DREF_SSC_SOURCE_MASK;
6872 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6873 final &= ~DREF_SSC1_ENABLE;
6874
6875 if (has_panel) {
6876 final |= DREF_SSC_SOURCE_ENABLE;
6877
6878 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6879 final |= DREF_SSC1_ENABLE;
6880
6881 if (has_cpu_edp) {
6882 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6883 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6884 else
6885 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6886 } else
6887 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6888 } else {
6889 final |= DREF_SSC_SOURCE_DISABLE;
6890 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6891 }
6892
6893 if (final == val)
6894 return;
6895
6896 /* Always enable nonspread source */
6897 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6898
6899 if (has_ck505)
6900 val |= DREF_NONSPREAD_CK505_ENABLE;
6901 else
6902 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6903
6904 if (has_panel) {
6905 val &= ~DREF_SSC_SOURCE_MASK;
6906 val |= DREF_SSC_SOURCE_ENABLE;
6907
6908 /* SSC must be turned on before enabling the CPU output */
6909 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6910 DRM_DEBUG_KMS("Using SSC on panel\n");
6911 val |= DREF_SSC1_ENABLE;
6912 } else
6913 val &= ~DREF_SSC1_ENABLE;
6914
6915 /* Get SSC going before enabling the outputs */
6916 I915_WRITE(PCH_DREF_CONTROL, val);
6917 POSTING_READ(PCH_DREF_CONTROL);
6918 udelay(200);
6919
6920 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6921
6922 /* Enable CPU source on CPU attached eDP */
6923 if (has_cpu_edp) {
6924 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6925 DRM_DEBUG_KMS("Using SSC on eDP\n");
6926 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6927 } else
6928 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6929 } else
6930 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6931
6932 I915_WRITE(PCH_DREF_CONTROL, val);
6933 POSTING_READ(PCH_DREF_CONTROL);
6934 udelay(200);
6935 } else {
6936 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6937
6938 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6939
6940 /* Turn off CPU output */
6941 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6942
6943 I915_WRITE(PCH_DREF_CONTROL, val);
6944 POSTING_READ(PCH_DREF_CONTROL);
6945 udelay(200);
6946
6947 /* Turn off the SSC source */
6948 val &= ~DREF_SSC_SOURCE_MASK;
6949 val |= DREF_SSC_SOURCE_DISABLE;
6950
6951 /* Turn off SSC1 */
6952 val &= ~DREF_SSC1_ENABLE;
6953
6954 I915_WRITE(PCH_DREF_CONTROL, val);
6955 POSTING_READ(PCH_DREF_CONTROL);
6956 udelay(200);
6957 }
6958
6959 BUG_ON(val != final);
6960 }
6961
6962 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6963 {
6964 uint32_t tmp;
6965
6966 tmp = I915_READ(SOUTH_CHICKEN2);
6967 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6968 I915_WRITE(SOUTH_CHICKEN2, tmp);
6969
6970 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6971 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6972 DRM_ERROR("FDI mPHY reset assert timeout\n");
6973
6974 tmp = I915_READ(SOUTH_CHICKEN2);
6975 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6976 I915_WRITE(SOUTH_CHICKEN2, tmp);
6977
6978 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6979 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6980 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6981 }
6982
6983 /* WaMPhyProgramming:hsw */
6984 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6985 {
6986 uint32_t tmp;
6987
6988 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6989 tmp &= ~(0xFF << 24);
6990 tmp |= (0x12 << 24);
6991 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6992
6993 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6994 tmp |= (1 << 11);
6995 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6996
6997 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6998 tmp |= (1 << 11);
6999 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7000
7001 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7002 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7003 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7004
7005 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7006 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7007 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7008
7009 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7010 tmp &= ~(7 << 13);
7011 tmp |= (5 << 13);
7012 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7013
7014 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7015 tmp &= ~(7 << 13);
7016 tmp |= (5 << 13);
7017 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7018
7019 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7020 tmp &= ~0xFF;
7021 tmp |= 0x1C;
7022 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7023
7024 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7025 tmp &= ~0xFF;
7026 tmp |= 0x1C;
7027 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7028
7029 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7030 tmp &= ~(0xFF << 16);
7031 tmp |= (0x1C << 16);
7032 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7033
7034 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7035 tmp &= ~(0xFF << 16);
7036 tmp |= (0x1C << 16);
7037 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7038
7039 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7040 tmp |= (1 << 27);
7041 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7042
7043 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7044 tmp |= (1 << 27);
7045 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7046
7047 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7048 tmp &= ~(0xF << 28);
7049 tmp |= (4 << 28);
7050 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7051
7052 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7053 tmp &= ~(0xF << 28);
7054 tmp |= (4 << 28);
7055 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7056 }
7057
7058 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7059 * Programming" based on the parameters passed:
7060 * - Sequence to enable CLKOUT_DP
7061 * - Sequence to enable CLKOUT_DP without spread
7062 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7063 */
7064 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7065 bool with_fdi)
7066 {
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068 uint32_t reg, tmp;
7069
7070 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7071 with_spread = true;
7072 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7073 with_fdi, "LP PCH doesn't have FDI\n"))
7074 with_fdi = false;
7075
7076 mutex_lock(&dev_priv->dpio_lock);
7077
7078 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7079 tmp &= ~SBI_SSCCTL_DISABLE;
7080 tmp |= SBI_SSCCTL_PATHALT;
7081 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7082
7083 udelay(24);
7084
7085 if (with_spread) {
7086 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7087 tmp &= ~SBI_SSCCTL_PATHALT;
7088 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7089
7090 if (with_fdi) {
7091 lpt_reset_fdi_mphy(dev_priv);
7092 lpt_program_fdi_mphy(dev_priv);
7093 }
7094 }
7095
7096 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7097 SBI_GEN0 : SBI_DBUFF0;
7098 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7099 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7100 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7101
7102 mutex_unlock(&dev_priv->dpio_lock);
7103 }
7104
7105 /* Sequence to disable CLKOUT_DP */
7106 static void lpt_disable_clkout_dp(struct drm_device *dev)
7107 {
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109 uint32_t reg, tmp;
7110
7111 mutex_lock(&dev_priv->dpio_lock);
7112
7113 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7114 SBI_GEN0 : SBI_DBUFF0;
7115 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7116 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7117 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7118
7119 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7120 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7121 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7122 tmp |= SBI_SSCCTL_PATHALT;
7123 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7124 udelay(32);
7125 }
7126 tmp |= SBI_SSCCTL_DISABLE;
7127 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7128 }
7129
7130 mutex_unlock(&dev_priv->dpio_lock);
7131 }
7132
7133 static void lpt_init_pch_refclk(struct drm_device *dev)
7134 {
7135 struct intel_encoder *encoder;
7136 bool has_vga = false;
7137
7138 for_each_intel_encoder(dev, encoder) {
7139 switch (encoder->type) {
7140 case INTEL_OUTPUT_ANALOG:
7141 has_vga = true;
7142 break;
7143 default:
7144 break;
7145 }
7146 }
7147
7148 if (has_vga)
7149 lpt_enable_clkout_dp(dev, true, true);
7150 else
7151 lpt_disable_clkout_dp(dev);
7152 }
7153
7154 /*
7155 * Initialize reference clocks when the driver loads
7156 */
7157 void intel_init_pch_refclk(struct drm_device *dev)
7158 {
7159 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7160 ironlake_init_pch_refclk(dev);
7161 else if (HAS_PCH_LPT(dev))
7162 lpt_init_pch_refclk(dev);
7163 }
7164
7165 static int ironlake_get_refclk(struct drm_crtc *crtc)
7166 {
7167 struct drm_device *dev = crtc->dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 struct intel_encoder *encoder;
7170 int num_connectors = 0;
7171 bool is_lvds = false;
7172
7173 for_each_intel_encoder(dev, encoder) {
7174 if (encoder->new_crtc != to_intel_crtc(crtc))
7175 continue;
7176
7177 switch (encoder->type) {
7178 case INTEL_OUTPUT_LVDS:
7179 is_lvds = true;
7180 break;
7181 default:
7182 break;
7183 }
7184 num_connectors++;
7185 }
7186
7187 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7188 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7189 dev_priv->vbt.lvds_ssc_freq);
7190 return dev_priv->vbt.lvds_ssc_freq;
7191 }
7192
7193 return 120000;
7194 }
7195
7196 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7197 {
7198 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7200 int pipe = intel_crtc->pipe;
7201 uint32_t val;
7202
7203 val = 0;
7204
7205 switch (intel_crtc->config->pipe_bpp) {
7206 case 18:
7207 val |= PIPECONF_6BPC;
7208 break;
7209 case 24:
7210 val |= PIPECONF_8BPC;
7211 break;
7212 case 30:
7213 val |= PIPECONF_10BPC;
7214 break;
7215 case 36:
7216 val |= PIPECONF_12BPC;
7217 break;
7218 default:
7219 /* Case prevented by intel_choose_pipe_bpp_dither. */
7220 BUG();
7221 }
7222
7223 if (intel_crtc->config->dither)
7224 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7225
7226 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7227 val |= PIPECONF_INTERLACED_ILK;
7228 else
7229 val |= PIPECONF_PROGRESSIVE;
7230
7231 if (intel_crtc->config->limited_color_range)
7232 val |= PIPECONF_COLOR_RANGE_SELECT;
7233
7234 I915_WRITE(PIPECONF(pipe), val);
7235 POSTING_READ(PIPECONF(pipe));
7236 }
7237
7238 /*
7239 * Set up the pipe CSC unit.
7240 *
7241 * Currently only full range RGB to limited range RGB conversion
7242 * is supported, but eventually this should handle various
7243 * RGB<->YCbCr scenarios as well.
7244 */
7245 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7246 {
7247 struct drm_device *dev = crtc->dev;
7248 struct drm_i915_private *dev_priv = dev->dev_private;
7249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7250 int pipe = intel_crtc->pipe;
7251 uint16_t coeff = 0x7800; /* 1.0 */
7252
7253 /*
7254 * TODO: Check what kind of values actually come out of the pipe
7255 * with these coeff/postoff values and adjust to get the best
7256 * accuracy. Perhaps we even need to take the bpc value into
7257 * consideration.
7258 */
7259
7260 if (intel_crtc->config->limited_color_range)
7261 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7262
7263 /*
7264 * GY/GU and RY/RU should be the other way around according
7265 * to BSpec, but reality doesn't agree. Just set them up in
7266 * a way that results in the correct picture.
7267 */
7268 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7269 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7270
7271 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7272 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7273
7274 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7275 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7276
7277 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7278 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7279 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7280
7281 if (INTEL_INFO(dev)->gen > 6) {
7282 uint16_t postoff = 0;
7283
7284 if (intel_crtc->config->limited_color_range)
7285 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7286
7287 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7288 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7289 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7290
7291 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7292 } else {
7293 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7294
7295 if (intel_crtc->config->limited_color_range)
7296 mode |= CSC_BLACK_SCREEN_OFFSET;
7297
7298 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7299 }
7300 }
7301
7302 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7303 {
7304 struct drm_device *dev = crtc->dev;
7305 struct drm_i915_private *dev_priv = dev->dev_private;
7306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7307 enum pipe pipe = intel_crtc->pipe;
7308 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7309 uint32_t val;
7310
7311 val = 0;
7312
7313 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7314 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7315
7316 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7317 val |= PIPECONF_INTERLACED_ILK;
7318 else
7319 val |= PIPECONF_PROGRESSIVE;
7320
7321 I915_WRITE(PIPECONF(cpu_transcoder), val);
7322 POSTING_READ(PIPECONF(cpu_transcoder));
7323
7324 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7325 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7326
7327 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7328 val = 0;
7329
7330 switch (intel_crtc->config->pipe_bpp) {
7331 case 18:
7332 val |= PIPEMISC_DITHER_6_BPC;
7333 break;
7334 case 24:
7335 val |= PIPEMISC_DITHER_8_BPC;
7336 break;
7337 case 30:
7338 val |= PIPEMISC_DITHER_10_BPC;
7339 break;
7340 case 36:
7341 val |= PIPEMISC_DITHER_12_BPC;
7342 break;
7343 default:
7344 /* Case prevented by pipe_config_set_bpp. */
7345 BUG();
7346 }
7347
7348 if (intel_crtc->config->dither)
7349 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7350
7351 I915_WRITE(PIPEMISC(pipe), val);
7352 }
7353 }
7354
7355 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7356 struct intel_crtc_state *crtc_state,
7357 intel_clock_t *clock,
7358 bool *has_reduced_clock,
7359 intel_clock_t *reduced_clock)
7360 {
7361 struct drm_device *dev = crtc->dev;
7362 struct drm_i915_private *dev_priv = dev->dev_private;
7363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7364 int refclk;
7365 const intel_limit_t *limit;
7366 bool ret, is_lvds = false;
7367
7368 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7369
7370 refclk = ironlake_get_refclk(crtc);
7371
7372 /*
7373 * Returns a set of divisors for the desired target clock with the given
7374 * refclk, or FALSE. The returned values represent the clock equation:
7375 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7376 */
7377 limit = intel_limit(intel_crtc, refclk);
7378 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7379 crtc_state->port_clock,
7380 refclk, NULL, clock);
7381 if (!ret)
7382 return false;
7383
7384 if (is_lvds && dev_priv->lvds_downclock_avail) {
7385 /*
7386 * Ensure we match the reduced clock's P to the target clock.
7387 * If the clocks don't match, we can't switch the display clock
7388 * by using the FP0/FP1. In such case we will disable the LVDS
7389 * downclock feature.
7390 */
7391 *has_reduced_clock =
7392 dev_priv->display.find_dpll(limit, intel_crtc,
7393 dev_priv->lvds_downclock,
7394 refclk, clock,
7395 reduced_clock);
7396 }
7397
7398 return true;
7399 }
7400
7401 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7402 {
7403 /*
7404 * Account for spread spectrum to avoid
7405 * oversubscribing the link. Max center spread
7406 * is 2.5%; use 5% for safety's sake.
7407 */
7408 u32 bps = target_clock * bpp * 21 / 20;
7409 return DIV_ROUND_UP(bps, link_bw * 8);
7410 }
7411
7412 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7413 {
7414 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7415 }
7416
7417 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7418 struct intel_crtc_state *crtc_state,
7419 u32 *fp,
7420 intel_clock_t *reduced_clock, u32 *fp2)
7421 {
7422 struct drm_crtc *crtc = &intel_crtc->base;
7423 struct drm_device *dev = crtc->dev;
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425 struct intel_encoder *intel_encoder;
7426 uint32_t dpll;
7427 int factor, num_connectors = 0;
7428 bool is_lvds = false, is_sdvo = false;
7429
7430 for_each_intel_encoder(dev, intel_encoder) {
7431 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7432 continue;
7433
7434 switch (intel_encoder->type) {
7435 case INTEL_OUTPUT_LVDS:
7436 is_lvds = true;
7437 break;
7438 case INTEL_OUTPUT_SDVO:
7439 case INTEL_OUTPUT_HDMI:
7440 is_sdvo = true;
7441 break;
7442 default:
7443 break;
7444 }
7445
7446 num_connectors++;
7447 }
7448
7449 /* Enable autotuning of the PLL clock (if permissible) */
7450 factor = 21;
7451 if (is_lvds) {
7452 if ((intel_panel_use_ssc(dev_priv) &&
7453 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7454 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7455 factor = 25;
7456 } else if (crtc_state->sdvo_tv_clock)
7457 factor = 20;
7458
7459 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7460 *fp |= FP_CB_TUNE;
7461
7462 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7463 *fp2 |= FP_CB_TUNE;
7464
7465 dpll = 0;
7466
7467 if (is_lvds)
7468 dpll |= DPLLB_MODE_LVDS;
7469 else
7470 dpll |= DPLLB_MODE_DAC_SERIAL;
7471
7472 dpll |= (crtc_state->pixel_multiplier - 1)
7473 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7474
7475 if (is_sdvo)
7476 dpll |= DPLL_SDVO_HIGH_SPEED;
7477 if (crtc_state->has_dp_encoder)
7478 dpll |= DPLL_SDVO_HIGH_SPEED;
7479
7480 /* compute bitmask from p1 value */
7481 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7482 /* also FPA1 */
7483 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7484
7485 switch (crtc_state->dpll.p2) {
7486 case 5:
7487 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7488 break;
7489 case 7:
7490 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7491 break;
7492 case 10:
7493 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7494 break;
7495 case 14:
7496 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7497 break;
7498 }
7499
7500 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7501 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7502 else
7503 dpll |= PLL_REF_INPUT_DREFCLK;
7504
7505 return dpll | DPLL_VCO_ENABLE;
7506 }
7507
7508 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7509 struct intel_crtc_state *crtc_state)
7510 {
7511 struct drm_device *dev = crtc->base.dev;
7512 intel_clock_t clock, reduced_clock;
7513 u32 dpll = 0, fp = 0, fp2 = 0;
7514 bool ok, has_reduced_clock = false;
7515 bool is_lvds = false;
7516 struct intel_shared_dpll *pll;
7517
7518 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7519
7520 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7521 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7522
7523 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7524 &has_reduced_clock, &reduced_clock);
7525 if (!ok && !crtc_state->clock_set) {
7526 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7527 return -EINVAL;
7528 }
7529 /* Compat-code for transition, will disappear. */
7530 if (!crtc_state->clock_set) {
7531 crtc_state->dpll.n = clock.n;
7532 crtc_state->dpll.m1 = clock.m1;
7533 crtc_state->dpll.m2 = clock.m2;
7534 crtc_state->dpll.p1 = clock.p1;
7535 crtc_state->dpll.p2 = clock.p2;
7536 }
7537
7538 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7539 if (crtc_state->has_pch_encoder) {
7540 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7541 if (has_reduced_clock)
7542 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7543
7544 dpll = ironlake_compute_dpll(crtc, crtc_state,
7545 &fp, &reduced_clock,
7546 has_reduced_clock ? &fp2 : NULL);
7547
7548 crtc_state->dpll_hw_state.dpll = dpll;
7549 crtc_state->dpll_hw_state.fp0 = fp;
7550 if (has_reduced_clock)
7551 crtc_state->dpll_hw_state.fp1 = fp2;
7552 else
7553 crtc_state->dpll_hw_state.fp1 = fp;
7554
7555 pll = intel_get_shared_dpll(crtc, crtc_state);
7556 if (pll == NULL) {
7557 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7558 pipe_name(crtc->pipe));
7559 return -EINVAL;
7560 }
7561 }
7562
7563 if (is_lvds && has_reduced_clock && i915.powersave)
7564 crtc->lowfreq_avail = true;
7565 else
7566 crtc->lowfreq_avail = false;
7567
7568 return 0;
7569 }
7570
7571 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7572 struct intel_link_m_n *m_n)
7573 {
7574 struct drm_device *dev = crtc->base.dev;
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576 enum pipe pipe = crtc->pipe;
7577
7578 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7579 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7580 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7581 & ~TU_SIZE_MASK;
7582 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7583 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7584 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7585 }
7586
7587 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7588 enum transcoder transcoder,
7589 struct intel_link_m_n *m_n,
7590 struct intel_link_m_n *m2_n2)
7591 {
7592 struct drm_device *dev = crtc->base.dev;
7593 struct drm_i915_private *dev_priv = dev->dev_private;
7594 enum pipe pipe = crtc->pipe;
7595
7596 if (INTEL_INFO(dev)->gen >= 5) {
7597 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7598 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7599 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7600 & ~TU_SIZE_MASK;
7601 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7602 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7603 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7604 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7605 * gen < 8) and if DRRS is supported (to make sure the
7606 * registers are not unnecessarily read).
7607 */
7608 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7609 crtc->config->has_drrs) {
7610 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7611 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7612 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7613 & ~TU_SIZE_MASK;
7614 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7615 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7616 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7617 }
7618 } else {
7619 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7620 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7621 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7622 & ~TU_SIZE_MASK;
7623 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7624 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7625 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7626 }
7627 }
7628
7629 void intel_dp_get_m_n(struct intel_crtc *crtc,
7630 struct intel_crtc_state *pipe_config)
7631 {
7632 if (pipe_config->has_pch_encoder)
7633 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7634 else
7635 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7636 &pipe_config->dp_m_n,
7637 &pipe_config->dp_m2_n2);
7638 }
7639
7640 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7641 struct intel_crtc_state *pipe_config)
7642 {
7643 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7644 &pipe_config->fdi_m_n, NULL);
7645 }
7646
7647 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7648 struct intel_crtc_state *pipe_config)
7649 {
7650 struct drm_device *dev = crtc->base.dev;
7651 struct drm_i915_private *dev_priv = dev->dev_private;
7652 uint32_t tmp;
7653
7654 tmp = I915_READ(PS_CTL(crtc->pipe));
7655
7656 if (tmp & PS_ENABLE) {
7657 pipe_config->pch_pfit.enabled = true;
7658 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7659 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7660 }
7661 }
7662
7663 static void
7664 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7665 struct intel_initial_plane_config *plane_config)
7666 {
7667 struct drm_device *dev = crtc->base.dev;
7668 struct drm_i915_private *dev_priv = dev->dev_private;
7669 u32 val, base, offset, stride_mult;
7670 int pipe = crtc->pipe;
7671 int fourcc, pixel_format;
7672 int aligned_height;
7673 struct drm_framebuffer *fb;
7674 struct intel_framebuffer *intel_fb;
7675
7676 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7677 if (!intel_fb) {
7678 DRM_DEBUG_KMS("failed to alloc fb\n");
7679 return;
7680 }
7681
7682 fb = &intel_fb->base;
7683
7684 val = I915_READ(PLANE_CTL(pipe, 0));
7685 if (!(val & PLANE_CTL_ENABLE))
7686 goto error;
7687
7688 if (val & PLANE_CTL_TILED_MASK) {
7689 plane_config->tiling = I915_TILING_X;
7690 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7691 }
7692
7693 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7694 fourcc = skl_format_to_fourcc(pixel_format,
7695 val & PLANE_CTL_ORDER_RGBX,
7696 val & PLANE_CTL_ALPHA_MASK);
7697 fb->pixel_format = fourcc;
7698 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7699
7700 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7701 plane_config->base = base;
7702
7703 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7704
7705 val = I915_READ(PLANE_SIZE(pipe, 0));
7706 fb->height = ((val >> 16) & 0xfff) + 1;
7707 fb->width = ((val >> 0) & 0x1fff) + 1;
7708
7709 val = I915_READ(PLANE_STRIDE(pipe, 0));
7710 switch (plane_config->tiling) {
7711 case I915_TILING_NONE:
7712 stride_mult = 64;
7713 break;
7714 case I915_TILING_X:
7715 stride_mult = 512;
7716 break;
7717 default:
7718 MISSING_CASE(plane_config->tiling);
7719 goto error;
7720 }
7721 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7722
7723 aligned_height = intel_fb_align_height(dev, fb->height,
7724 fb->pixel_format,
7725 fb->modifier[0]);
7726
7727 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7728
7729 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7730 pipe_name(pipe), fb->width, fb->height,
7731 fb->bits_per_pixel, base, fb->pitches[0],
7732 plane_config->size);
7733
7734 plane_config->fb = intel_fb;
7735 return;
7736
7737 error:
7738 kfree(fb);
7739 }
7740
7741 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7742 struct intel_crtc_state *pipe_config)
7743 {
7744 struct drm_device *dev = crtc->base.dev;
7745 struct drm_i915_private *dev_priv = dev->dev_private;
7746 uint32_t tmp;
7747
7748 tmp = I915_READ(PF_CTL(crtc->pipe));
7749
7750 if (tmp & PF_ENABLE) {
7751 pipe_config->pch_pfit.enabled = true;
7752 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7753 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7754
7755 /* We currently do not free assignements of panel fitters on
7756 * ivb/hsw (since we don't use the higher upscaling modes which
7757 * differentiates them) so just WARN about this case for now. */
7758 if (IS_GEN7(dev)) {
7759 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7760 PF_PIPE_SEL_IVB(crtc->pipe));
7761 }
7762 }
7763 }
7764
7765 static void
7766 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7767 struct intel_initial_plane_config *plane_config)
7768 {
7769 struct drm_device *dev = crtc->base.dev;
7770 struct drm_i915_private *dev_priv = dev->dev_private;
7771 u32 val, base, offset;
7772 int pipe = crtc->pipe;
7773 int fourcc, pixel_format;
7774 int aligned_height;
7775 struct drm_framebuffer *fb;
7776 struct intel_framebuffer *intel_fb;
7777
7778 val = I915_READ(DSPCNTR(pipe));
7779 if (!(val & DISPLAY_PLANE_ENABLE))
7780 return;
7781
7782 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7783 if (!intel_fb) {
7784 DRM_DEBUG_KMS("failed to alloc fb\n");
7785 return;
7786 }
7787
7788 fb = &intel_fb->base;
7789
7790 if (INTEL_INFO(dev)->gen >= 4) {
7791 if (val & DISPPLANE_TILED) {
7792 plane_config->tiling = I915_TILING_X;
7793 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7794 }
7795 }
7796
7797 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7798 fourcc = i9xx_format_to_fourcc(pixel_format);
7799 fb->pixel_format = fourcc;
7800 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7801
7802 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7803 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7804 offset = I915_READ(DSPOFFSET(pipe));
7805 } else {
7806 if (plane_config->tiling)
7807 offset = I915_READ(DSPTILEOFF(pipe));
7808 else
7809 offset = I915_READ(DSPLINOFF(pipe));
7810 }
7811 plane_config->base = base;
7812
7813 val = I915_READ(PIPESRC(pipe));
7814 fb->width = ((val >> 16) & 0xfff) + 1;
7815 fb->height = ((val >> 0) & 0xfff) + 1;
7816
7817 val = I915_READ(DSPSTRIDE(pipe));
7818 fb->pitches[0] = val & 0xffffffc0;
7819
7820 aligned_height = intel_fb_align_height(dev, fb->height,
7821 fb->pixel_format,
7822 fb->modifier[0]);
7823
7824 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7825
7826 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7827 pipe_name(pipe), fb->width, fb->height,
7828 fb->bits_per_pixel, base, fb->pitches[0],
7829 plane_config->size);
7830
7831 plane_config->fb = intel_fb;
7832 }
7833
7834 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7835 struct intel_crtc_state *pipe_config)
7836 {
7837 struct drm_device *dev = crtc->base.dev;
7838 struct drm_i915_private *dev_priv = dev->dev_private;
7839 uint32_t tmp;
7840
7841 if (!intel_display_power_is_enabled(dev_priv,
7842 POWER_DOMAIN_PIPE(crtc->pipe)))
7843 return false;
7844
7845 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7846 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7847
7848 tmp = I915_READ(PIPECONF(crtc->pipe));
7849 if (!(tmp & PIPECONF_ENABLE))
7850 return false;
7851
7852 switch (tmp & PIPECONF_BPC_MASK) {
7853 case PIPECONF_6BPC:
7854 pipe_config->pipe_bpp = 18;
7855 break;
7856 case PIPECONF_8BPC:
7857 pipe_config->pipe_bpp = 24;
7858 break;
7859 case PIPECONF_10BPC:
7860 pipe_config->pipe_bpp = 30;
7861 break;
7862 case PIPECONF_12BPC:
7863 pipe_config->pipe_bpp = 36;
7864 break;
7865 default:
7866 break;
7867 }
7868
7869 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7870 pipe_config->limited_color_range = true;
7871
7872 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7873 struct intel_shared_dpll *pll;
7874
7875 pipe_config->has_pch_encoder = true;
7876
7877 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7878 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7879 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7880
7881 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7882
7883 if (HAS_PCH_IBX(dev_priv->dev)) {
7884 pipe_config->shared_dpll =
7885 (enum intel_dpll_id) crtc->pipe;
7886 } else {
7887 tmp = I915_READ(PCH_DPLL_SEL);
7888 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7889 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7890 else
7891 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7892 }
7893
7894 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7895
7896 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7897 &pipe_config->dpll_hw_state));
7898
7899 tmp = pipe_config->dpll_hw_state.dpll;
7900 pipe_config->pixel_multiplier =
7901 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7902 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7903
7904 ironlake_pch_clock_get(crtc, pipe_config);
7905 } else {
7906 pipe_config->pixel_multiplier = 1;
7907 }
7908
7909 intel_get_pipe_timings(crtc, pipe_config);
7910
7911 ironlake_get_pfit_config(crtc, pipe_config);
7912
7913 return true;
7914 }
7915
7916 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7917 {
7918 struct drm_device *dev = dev_priv->dev;
7919 struct intel_crtc *crtc;
7920
7921 for_each_intel_crtc(dev, crtc)
7922 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7923 pipe_name(crtc->pipe));
7924
7925 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7926 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7927 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7928 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7929 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7930 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7931 "CPU PWM1 enabled\n");
7932 if (IS_HASWELL(dev))
7933 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7934 "CPU PWM2 enabled\n");
7935 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7936 "PCH PWM1 enabled\n");
7937 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7938 "Utility pin enabled\n");
7939 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7940
7941 /*
7942 * In theory we can still leave IRQs enabled, as long as only the HPD
7943 * interrupts remain enabled. We used to check for that, but since it's
7944 * gen-specific and since we only disable LCPLL after we fully disable
7945 * the interrupts, the check below should be enough.
7946 */
7947 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7948 }
7949
7950 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7951 {
7952 struct drm_device *dev = dev_priv->dev;
7953
7954 if (IS_HASWELL(dev))
7955 return I915_READ(D_COMP_HSW);
7956 else
7957 return I915_READ(D_COMP_BDW);
7958 }
7959
7960 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7961 {
7962 struct drm_device *dev = dev_priv->dev;
7963
7964 if (IS_HASWELL(dev)) {
7965 mutex_lock(&dev_priv->rps.hw_lock);
7966 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7967 val))
7968 DRM_ERROR("Failed to write to D_COMP\n");
7969 mutex_unlock(&dev_priv->rps.hw_lock);
7970 } else {
7971 I915_WRITE(D_COMP_BDW, val);
7972 POSTING_READ(D_COMP_BDW);
7973 }
7974 }
7975
7976 /*
7977 * This function implements pieces of two sequences from BSpec:
7978 * - Sequence for display software to disable LCPLL
7979 * - Sequence for display software to allow package C8+
7980 * The steps implemented here are just the steps that actually touch the LCPLL
7981 * register. Callers should take care of disabling all the display engine
7982 * functions, doing the mode unset, fixing interrupts, etc.
7983 */
7984 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7985 bool switch_to_fclk, bool allow_power_down)
7986 {
7987 uint32_t val;
7988
7989 assert_can_disable_lcpll(dev_priv);
7990
7991 val = I915_READ(LCPLL_CTL);
7992
7993 if (switch_to_fclk) {
7994 val |= LCPLL_CD_SOURCE_FCLK;
7995 I915_WRITE(LCPLL_CTL, val);
7996
7997 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7998 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7999 DRM_ERROR("Switching to FCLK failed\n");
8000
8001 val = I915_READ(LCPLL_CTL);
8002 }
8003
8004 val |= LCPLL_PLL_DISABLE;
8005 I915_WRITE(LCPLL_CTL, val);
8006 POSTING_READ(LCPLL_CTL);
8007
8008 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8009 DRM_ERROR("LCPLL still locked\n");
8010
8011 val = hsw_read_dcomp(dev_priv);
8012 val |= D_COMP_COMP_DISABLE;
8013 hsw_write_dcomp(dev_priv, val);
8014 ndelay(100);
8015
8016 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8017 1))
8018 DRM_ERROR("D_COMP RCOMP still in progress\n");
8019
8020 if (allow_power_down) {
8021 val = I915_READ(LCPLL_CTL);
8022 val |= LCPLL_POWER_DOWN_ALLOW;
8023 I915_WRITE(LCPLL_CTL, val);
8024 POSTING_READ(LCPLL_CTL);
8025 }
8026 }
8027
8028 /*
8029 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8030 * source.
8031 */
8032 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8033 {
8034 uint32_t val;
8035
8036 val = I915_READ(LCPLL_CTL);
8037
8038 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8039 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8040 return;
8041
8042 /*
8043 * Make sure we're not on PC8 state before disabling PC8, otherwise
8044 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8045 */
8046 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8047
8048 if (val & LCPLL_POWER_DOWN_ALLOW) {
8049 val &= ~LCPLL_POWER_DOWN_ALLOW;
8050 I915_WRITE(LCPLL_CTL, val);
8051 POSTING_READ(LCPLL_CTL);
8052 }
8053
8054 val = hsw_read_dcomp(dev_priv);
8055 val |= D_COMP_COMP_FORCE;
8056 val &= ~D_COMP_COMP_DISABLE;
8057 hsw_write_dcomp(dev_priv, val);
8058
8059 val = I915_READ(LCPLL_CTL);
8060 val &= ~LCPLL_PLL_DISABLE;
8061 I915_WRITE(LCPLL_CTL, val);
8062
8063 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8064 DRM_ERROR("LCPLL not locked yet\n");
8065
8066 if (val & LCPLL_CD_SOURCE_FCLK) {
8067 val = I915_READ(LCPLL_CTL);
8068 val &= ~LCPLL_CD_SOURCE_FCLK;
8069 I915_WRITE(LCPLL_CTL, val);
8070
8071 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8072 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8073 DRM_ERROR("Switching back to LCPLL failed\n");
8074 }
8075
8076 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8077 }
8078
8079 /*
8080 * Package states C8 and deeper are really deep PC states that can only be
8081 * reached when all the devices on the system allow it, so even if the graphics
8082 * device allows PC8+, it doesn't mean the system will actually get to these
8083 * states. Our driver only allows PC8+ when going into runtime PM.
8084 *
8085 * The requirements for PC8+ are that all the outputs are disabled, the power
8086 * well is disabled and most interrupts are disabled, and these are also
8087 * requirements for runtime PM. When these conditions are met, we manually do
8088 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8089 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8090 * hang the machine.
8091 *
8092 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8093 * the state of some registers, so when we come back from PC8+ we need to
8094 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8095 * need to take care of the registers kept by RC6. Notice that this happens even
8096 * if we don't put the device in PCI D3 state (which is what currently happens
8097 * because of the runtime PM support).
8098 *
8099 * For more, read "Display Sequences for Package C8" on the hardware
8100 * documentation.
8101 */
8102 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8103 {
8104 struct drm_device *dev = dev_priv->dev;
8105 uint32_t val;
8106
8107 DRM_DEBUG_KMS("Enabling package C8+\n");
8108
8109 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8110 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8111 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8112 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8113 }
8114
8115 lpt_disable_clkout_dp(dev);
8116 hsw_disable_lcpll(dev_priv, true, true);
8117 }
8118
8119 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8120 {
8121 struct drm_device *dev = dev_priv->dev;
8122 uint32_t val;
8123
8124 DRM_DEBUG_KMS("Disabling package C8+\n");
8125
8126 hsw_restore_lcpll(dev_priv);
8127 lpt_init_pch_refclk(dev);
8128
8129 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8130 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8131 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8132 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8133 }
8134
8135 intel_prepare_ddi(dev);
8136 }
8137
8138 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8139 struct intel_crtc_state *crtc_state)
8140 {
8141 if (!intel_ddi_pll_select(crtc, crtc_state))
8142 return -EINVAL;
8143
8144 crtc->lowfreq_avail = false;
8145
8146 return 0;
8147 }
8148
8149 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8150 enum port port,
8151 struct intel_crtc_state *pipe_config)
8152 {
8153 u32 temp, dpll_ctl1;
8154
8155 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8156 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8157
8158 switch (pipe_config->ddi_pll_sel) {
8159 case SKL_DPLL0:
8160 /*
8161 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8162 * of the shared DPLL framework and thus needs to be read out
8163 * separately
8164 */
8165 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8166 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8167 break;
8168 case SKL_DPLL1:
8169 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8170 break;
8171 case SKL_DPLL2:
8172 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8173 break;
8174 case SKL_DPLL3:
8175 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8176 break;
8177 }
8178 }
8179
8180 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8181 enum port port,
8182 struct intel_crtc_state *pipe_config)
8183 {
8184 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8185
8186 switch (pipe_config->ddi_pll_sel) {
8187 case PORT_CLK_SEL_WRPLL1:
8188 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8189 break;
8190 case PORT_CLK_SEL_WRPLL2:
8191 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8192 break;
8193 }
8194 }
8195
8196 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8197 struct intel_crtc_state *pipe_config)
8198 {
8199 struct drm_device *dev = crtc->base.dev;
8200 struct drm_i915_private *dev_priv = dev->dev_private;
8201 struct intel_shared_dpll *pll;
8202 enum port port;
8203 uint32_t tmp;
8204
8205 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8206
8207 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8208
8209 if (IS_SKYLAKE(dev))
8210 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8211 else
8212 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8213
8214 if (pipe_config->shared_dpll >= 0) {
8215 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8216
8217 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8218 &pipe_config->dpll_hw_state));
8219 }
8220
8221 /*
8222 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8223 * DDI E. So just check whether this pipe is wired to DDI E and whether
8224 * the PCH transcoder is on.
8225 */
8226 if (INTEL_INFO(dev)->gen < 9 &&
8227 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8228 pipe_config->has_pch_encoder = true;
8229
8230 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8231 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8232 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8233
8234 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8235 }
8236 }
8237
8238 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8239 struct intel_crtc_state *pipe_config)
8240 {
8241 struct drm_device *dev = crtc->base.dev;
8242 struct drm_i915_private *dev_priv = dev->dev_private;
8243 enum intel_display_power_domain pfit_domain;
8244 uint32_t tmp;
8245
8246 if (!intel_display_power_is_enabled(dev_priv,
8247 POWER_DOMAIN_PIPE(crtc->pipe)))
8248 return false;
8249
8250 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8251 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8252
8253 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8254 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8255 enum pipe trans_edp_pipe;
8256 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8257 default:
8258 WARN(1, "unknown pipe linked to edp transcoder\n");
8259 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8260 case TRANS_DDI_EDP_INPUT_A_ON:
8261 trans_edp_pipe = PIPE_A;
8262 break;
8263 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8264 trans_edp_pipe = PIPE_B;
8265 break;
8266 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8267 trans_edp_pipe = PIPE_C;
8268 break;
8269 }
8270
8271 if (trans_edp_pipe == crtc->pipe)
8272 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8273 }
8274
8275 if (!intel_display_power_is_enabled(dev_priv,
8276 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8277 return false;
8278
8279 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8280 if (!(tmp & PIPECONF_ENABLE))
8281 return false;
8282
8283 haswell_get_ddi_port_state(crtc, pipe_config);
8284
8285 intel_get_pipe_timings(crtc, pipe_config);
8286
8287 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8288 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8289 if (IS_SKYLAKE(dev))
8290 skylake_get_pfit_config(crtc, pipe_config);
8291 else
8292 ironlake_get_pfit_config(crtc, pipe_config);
8293 }
8294
8295 if (IS_HASWELL(dev))
8296 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8297 (I915_READ(IPS_CTL) & IPS_ENABLE);
8298
8299 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8300 pipe_config->pixel_multiplier =
8301 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8302 } else {
8303 pipe_config->pixel_multiplier = 1;
8304 }
8305
8306 return true;
8307 }
8308
8309 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8310 {
8311 struct drm_device *dev = crtc->dev;
8312 struct drm_i915_private *dev_priv = dev->dev_private;
8313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8314 uint32_t cntl = 0, size = 0;
8315
8316 if (base) {
8317 unsigned int width = intel_crtc->cursor_width;
8318 unsigned int height = intel_crtc->cursor_height;
8319 unsigned int stride = roundup_pow_of_two(width) * 4;
8320
8321 switch (stride) {
8322 default:
8323 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8324 width, stride);
8325 stride = 256;
8326 /* fallthrough */
8327 case 256:
8328 case 512:
8329 case 1024:
8330 case 2048:
8331 break;
8332 }
8333
8334 cntl |= CURSOR_ENABLE |
8335 CURSOR_GAMMA_ENABLE |
8336 CURSOR_FORMAT_ARGB |
8337 CURSOR_STRIDE(stride);
8338
8339 size = (height << 12) | width;
8340 }
8341
8342 if (intel_crtc->cursor_cntl != 0 &&
8343 (intel_crtc->cursor_base != base ||
8344 intel_crtc->cursor_size != size ||
8345 intel_crtc->cursor_cntl != cntl)) {
8346 /* On these chipsets we can only modify the base/size/stride
8347 * whilst the cursor is disabled.
8348 */
8349 I915_WRITE(_CURACNTR, 0);
8350 POSTING_READ(_CURACNTR);
8351 intel_crtc->cursor_cntl = 0;
8352 }
8353
8354 if (intel_crtc->cursor_base != base) {
8355 I915_WRITE(_CURABASE, base);
8356 intel_crtc->cursor_base = base;
8357 }
8358
8359 if (intel_crtc->cursor_size != size) {
8360 I915_WRITE(CURSIZE, size);
8361 intel_crtc->cursor_size = size;
8362 }
8363
8364 if (intel_crtc->cursor_cntl != cntl) {
8365 I915_WRITE(_CURACNTR, cntl);
8366 POSTING_READ(_CURACNTR);
8367 intel_crtc->cursor_cntl = cntl;
8368 }
8369 }
8370
8371 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8372 {
8373 struct drm_device *dev = crtc->dev;
8374 struct drm_i915_private *dev_priv = dev->dev_private;
8375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8376 int pipe = intel_crtc->pipe;
8377 uint32_t cntl;
8378
8379 cntl = 0;
8380 if (base) {
8381 cntl = MCURSOR_GAMMA_ENABLE;
8382 switch (intel_crtc->cursor_width) {
8383 case 64:
8384 cntl |= CURSOR_MODE_64_ARGB_AX;
8385 break;
8386 case 128:
8387 cntl |= CURSOR_MODE_128_ARGB_AX;
8388 break;
8389 case 256:
8390 cntl |= CURSOR_MODE_256_ARGB_AX;
8391 break;
8392 default:
8393 MISSING_CASE(intel_crtc->cursor_width);
8394 return;
8395 }
8396 cntl |= pipe << 28; /* Connect to correct pipe */
8397
8398 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8399 cntl |= CURSOR_PIPE_CSC_ENABLE;
8400 }
8401
8402 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8403 cntl |= CURSOR_ROTATE_180;
8404
8405 if (intel_crtc->cursor_cntl != cntl) {
8406 I915_WRITE(CURCNTR(pipe), cntl);
8407 POSTING_READ(CURCNTR(pipe));
8408 intel_crtc->cursor_cntl = cntl;
8409 }
8410
8411 /* and commit changes on next vblank */
8412 I915_WRITE(CURBASE(pipe), base);
8413 POSTING_READ(CURBASE(pipe));
8414
8415 intel_crtc->cursor_base = base;
8416 }
8417
8418 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8419 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8420 bool on)
8421 {
8422 struct drm_device *dev = crtc->dev;
8423 struct drm_i915_private *dev_priv = dev->dev_private;
8424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8425 int pipe = intel_crtc->pipe;
8426 int x = crtc->cursor_x;
8427 int y = crtc->cursor_y;
8428 u32 base = 0, pos = 0;
8429
8430 if (on)
8431 base = intel_crtc->cursor_addr;
8432
8433 if (x >= intel_crtc->config->pipe_src_w)
8434 base = 0;
8435
8436 if (y >= intel_crtc->config->pipe_src_h)
8437 base = 0;
8438
8439 if (x < 0) {
8440 if (x + intel_crtc->cursor_width <= 0)
8441 base = 0;
8442
8443 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8444 x = -x;
8445 }
8446 pos |= x << CURSOR_X_SHIFT;
8447
8448 if (y < 0) {
8449 if (y + intel_crtc->cursor_height <= 0)
8450 base = 0;
8451
8452 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8453 y = -y;
8454 }
8455 pos |= y << CURSOR_Y_SHIFT;
8456
8457 if (base == 0 && intel_crtc->cursor_base == 0)
8458 return;
8459
8460 I915_WRITE(CURPOS(pipe), pos);
8461
8462 /* ILK+ do this automagically */
8463 if (HAS_GMCH_DISPLAY(dev) &&
8464 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8465 base += (intel_crtc->cursor_height *
8466 intel_crtc->cursor_width - 1) * 4;
8467 }
8468
8469 if (IS_845G(dev) || IS_I865G(dev))
8470 i845_update_cursor(crtc, base);
8471 else
8472 i9xx_update_cursor(crtc, base);
8473 }
8474
8475 static bool cursor_size_ok(struct drm_device *dev,
8476 uint32_t width, uint32_t height)
8477 {
8478 if (width == 0 || height == 0)
8479 return false;
8480
8481 /*
8482 * 845g/865g are special in that they are only limited by
8483 * the width of their cursors, the height is arbitrary up to
8484 * the precision of the register. Everything else requires
8485 * square cursors, limited to a few power-of-two sizes.
8486 */
8487 if (IS_845G(dev) || IS_I865G(dev)) {
8488 if ((width & 63) != 0)
8489 return false;
8490
8491 if (width > (IS_845G(dev) ? 64 : 512))
8492 return false;
8493
8494 if (height > 1023)
8495 return false;
8496 } else {
8497 switch (width | height) {
8498 case 256:
8499 case 128:
8500 if (IS_GEN2(dev))
8501 return false;
8502 case 64:
8503 break;
8504 default:
8505 return false;
8506 }
8507 }
8508
8509 return true;
8510 }
8511
8512 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8513 u16 *blue, uint32_t start, uint32_t size)
8514 {
8515 int end = (start + size > 256) ? 256 : start + size, i;
8516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8517
8518 for (i = start; i < end; i++) {
8519 intel_crtc->lut_r[i] = red[i] >> 8;
8520 intel_crtc->lut_g[i] = green[i] >> 8;
8521 intel_crtc->lut_b[i] = blue[i] >> 8;
8522 }
8523
8524 intel_crtc_load_lut(crtc);
8525 }
8526
8527 /* VESA 640x480x72Hz mode to set on the pipe */
8528 static struct drm_display_mode load_detect_mode = {
8529 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8530 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8531 };
8532
8533 struct drm_framebuffer *
8534 __intel_framebuffer_create(struct drm_device *dev,
8535 struct drm_mode_fb_cmd2 *mode_cmd,
8536 struct drm_i915_gem_object *obj)
8537 {
8538 struct intel_framebuffer *intel_fb;
8539 int ret;
8540
8541 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8542 if (!intel_fb) {
8543 drm_gem_object_unreference(&obj->base);
8544 return ERR_PTR(-ENOMEM);
8545 }
8546
8547 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8548 if (ret)
8549 goto err;
8550
8551 return &intel_fb->base;
8552 err:
8553 drm_gem_object_unreference(&obj->base);
8554 kfree(intel_fb);
8555
8556 return ERR_PTR(ret);
8557 }
8558
8559 static struct drm_framebuffer *
8560 intel_framebuffer_create(struct drm_device *dev,
8561 struct drm_mode_fb_cmd2 *mode_cmd,
8562 struct drm_i915_gem_object *obj)
8563 {
8564 struct drm_framebuffer *fb;
8565 int ret;
8566
8567 ret = i915_mutex_lock_interruptible(dev);
8568 if (ret)
8569 return ERR_PTR(ret);
8570 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8571 mutex_unlock(&dev->struct_mutex);
8572
8573 return fb;
8574 }
8575
8576 static u32
8577 intel_framebuffer_pitch_for_width(int width, int bpp)
8578 {
8579 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8580 return ALIGN(pitch, 64);
8581 }
8582
8583 static u32
8584 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8585 {
8586 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8587 return PAGE_ALIGN(pitch * mode->vdisplay);
8588 }
8589
8590 static struct drm_framebuffer *
8591 intel_framebuffer_create_for_mode(struct drm_device *dev,
8592 struct drm_display_mode *mode,
8593 int depth, int bpp)
8594 {
8595 struct drm_i915_gem_object *obj;
8596 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8597
8598 obj = i915_gem_alloc_object(dev,
8599 intel_framebuffer_size_for_mode(mode, bpp));
8600 if (obj == NULL)
8601 return ERR_PTR(-ENOMEM);
8602
8603 mode_cmd.width = mode->hdisplay;
8604 mode_cmd.height = mode->vdisplay;
8605 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8606 bpp);
8607 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8608
8609 return intel_framebuffer_create(dev, &mode_cmd, obj);
8610 }
8611
8612 static struct drm_framebuffer *
8613 mode_fits_in_fbdev(struct drm_device *dev,
8614 struct drm_display_mode *mode)
8615 {
8616 #ifdef CONFIG_DRM_I915_FBDEV
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618 struct drm_i915_gem_object *obj;
8619 struct drm_framebuffer *fb;
8620
8621 if (!dev_priv->fbdev)
8622 return NULL;
8623
8624 if (!dev_priv->fbdev->fb)
8625 return NULL;
8626
8627 obj = dev_priv->fbdev->fb->obj;
8628 BUG_ON(!obj);
8629
8630 fb = &dev_priv->fbdev->fb->base;
8631 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8632 fb->bits_per_pixel))
8633 return NULL;
8634
8635 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8636 return NULL;
8637
8638 return fb;
8639 #else
8640 return NULL;
8641 #endif
8642 }
8643
8644 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8645 struct drm_display_mode *mode,
8646 struct intel_load_detect_pipe *old,
8647 struct drm_modeset_acquire_ctx *ctx)
8648 {
8649 struct intel_crtc *intel_crtc;
8650 struct intel_encoder *intel_encoder =
8651 intel_attached_encoder(connector);
8652 struct drm_crtc *possible_crtc;
8653 struct drm_encoder *encoder = &intel_encoder->base;
8654 struct drm_crtc *crtc = NULL;
8655 struct drm_device *dev = encoder->dev;
8656 struct drm_framebuffer *fb;
8657 struct drm_mode_config *config = &dev->mode_config;
8658 int ret, i = -1;
8659
8660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8661 connector->base.id, connector->name,
8662 encoder->base.id, encoder->name);
8663
8664 retry:
8665 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8666 if (ret)
8667 goto fail_unlock;
8668
8669 /*
8670 * Algorithm gets a little messy:
8671 *
8672 * - if the connector already has an assigned crtc, use it (but make
8673 * sure it's on first)
8674 *
8675 * - try to find the first unused crtc that can drive this connector,
8676 * and use that if we find one
8677 */
8678
8679 /* See if we already have a CRTC for this connector */
8680 if (encoder->crtc) {
8681 crtc = encoder->crtc;
8682
8683 ret = drm_modeset_lock(&crtc->mutex, ctx);
8684 if (ret)
8685 goto fail_unlock;
8686 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8687 if (ret)
8688 goto fail_unlock;
8689
8690 old->dpms_mode = connector->dpms;
8691 old->load_detect_temp = false;
8692
8693 /* Make sure the crtc and connector are running */
8694 if (connector->dpms != DRM_MODE_DPMS_ON)
8695 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8696
8697 return true;
8698 }
8699
8700 /* Find an unused one (if possible) */
8701 for_each_crtc(dev, possible_crtc) {
8702 i++;
8703 if (!(encoder->possible_crtcs & (1 << i)))
8704 continue;
8705 if (possible_crtc->enabled)
8706 continue;
8707 /* This can occur when applying the pipe A quirk on resume. */
8708 if (to_intel_crtc(possible_crtc)->new_enabled)
8709 continue;
8710
8711 crtc = possible_crtc;
8712 break;
8713 }
8714
8715 /*
8716 * If we didn't find an unused CRTC, don't use any.
8717 */
8718 if (!crtc) {
8719 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8720 goto fail_unlock;
8721 }
8722
8723 ret = drm_modeset_lock(&crtc->mutex, ctx);
8724 if (ret)
8725 goto fail_unlock;
8726 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8727 if (ret)
8728 goto fail_unlock;
8729 intel_encoder->new_crtc = to_intel_crtc(crtc);
8730 to_intel_connector(connector)->new_encoder = intel_encoder;
8731
8732 intel_crtc = to_intel_crtc(crtc);
8733 intel_crtc->new_enabled = true;
8734 intel_crtc->new_config = intel_crtc->config;
8735 old->dpms_mode = connector->dpms;
8736 old->load_detect_temp = true;
8737 old->release_fb = NULL;
8738
8739 if (!mode)
8740 mode = &load_detect_mode;
8741
8742 /* We need a framebuffer large enough to accommodate all accesses
8743 * that the plane may generate whilst we perform load detection.
8744 * We can not rely on the fbcon either being present (we get called
8745 * during its initialisation to detect all boot displays, or it may
8746 * not even exist) or that it is large enough to satisfy the
8747 * requested mode.
8748 */
8749 fb = mode_fits_in_fbdev(dev, mode);
8750 if (fb == NULL) {
8751 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8752 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8753 old->release_fb = fb;
8754 } else
8755 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8756 if (IS_ERR(fb)) {
8757 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8758 goto fail;
8759 }
8760
8761 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8762 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8763 if (old->release_fb)
8764 old->release_fb->funcs->destroy(old->release_fb);
8765 goto fail;
8766 }
8767
8768 /* let the connector get through one full cycle before testing */
8769 intel_wait_for_vblank(dev, intel_crtc->pipe);
8770 return true;
8771
8772 fail:
8773 intel_crtc->new_enabled = crtc->enabled;
8774 if (intel_crtc->new_enabled)
8775 intel_crtc->new_config = intel_crtc->config;
8776 else
8777 intel_crtc->new_config = NULL;
8778 fail_unlock:
8779 if (ret == -EDEADLK) {
8780 drm_modeset_backoff(ctx);
8781 goto retry;
8782 }
8783
8784 return false;
8785 }
8786
8787 void intel_release_load_detect_pipe(struct drm_connector *connector,
8788 struct intel_load_detect_pipe *old)
8789 {
8790 struct intel_encoder *intel_encoder =
8791 intel_attached_encoder(connector);
8792 struct drm_encoder *encoder = &intel_encoder->base;
8793 struct drm_crtc *crtc = encoder->crtc;
8794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8795
8796 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8797 connector->base.id, connector->name,
8798 encoder->base.id, encoder->name);
8799
8800 if (old->load_detect_temp) {
8801 to_intel_connector(connector)->new_encoder = NULL;
8802 intel_encoder->new_crtc = NULL;
8803 intel_crtc->new_enabled = false;
8804 intel_crtc->new_config = NULL;
8805 intel_set_mode(crtc, NULL, 0, 0, NULL);
8806
8807 if (old->release_fb) {
8808 drm_framebuffer_unregister_private(old->release_fb);
8809 drm_framebuffer_unreference(old->release_fb);
8810 }
8811
8812 return;
8813 }
8814
8815 /* Switch crtc and encoder back off if necessary */
8816 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8817 connector->funcs->dpms(connector, old->dpms_mode);
8818 }
8819
8820 static int i9xx_pll_refclk(struct drm_device *dev,
8821 const struct intel_crtc_state *pipe_config)
8822 {
8823 struct drm_i915_private *dev_priv = dev->dev_private;
8824 u32 dpll = pipe_config->dpll_hw_state.dpll;
8825
8826 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8827 return dev_priv->vbt.lvds_ssc_freq;
8828 else if (HAS_PCH_SPLIT(dev))
8829 return 120000;
8830 else if (!IS_GEN2(dev))
8831 return 96000;
8832 else
8833 return 48000;
8834 }
8835
8836 /* Returns the clock of the currently programmed mode of the given pipe. */
8837 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8838 struct intel_crtc_state *pipe_config)
8839 {
8840 struct drm_device *dev = crtc->base.dev;
8841 struct drm_i915_private *dev_priv = dev->dev_private;
8842 int pipe = pipe_config->cpu_transcoder;
8843 u32 dpll = pipe_config->dpll_hw_state.dpll;
8844 u32 fp;
8845 intel_clock_t clock;
8846 int refclk = i9xx_pll_refclk(dev, pipe_config);
8847
8848 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8849 fp = pipe_config->dpll_hw_state.fp0;
8850 else
8851 fp = pipe_config->dpll_hw_state.fp1;
8852
8853 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8854 if (IS_PINEVIEW(dev)) {
8855 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8856 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8857 } else {
8858 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8859 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8860 }
8861
8862 if (!IS_GEN2(dev)) {
8863 if (IS_PINEVIEW(dev))
8864 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8865 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8866 else
8867 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8868 DPLL_FPA01_P1_POST_DIV_SHIFT);
8869
8870 switch (dpll & DPLL_MODE_MASK) {
8871 case DPLLB_MODE_DAC_SERIAL:
8872 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8873 5 : 10;
8874 break;
8875 case DPLLB_MODE_LVDS:
8876 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8877 7 : 14;
8878 break;
8879 default:
8880 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8881 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8882 return;
8883 }
8884
8885 if (IS_PINEVIEW(dev))
8886 pineview_clock(refclk, &clock);
8887 else
8888 i9xx_clock(refclk, &clock);
8889 } else {
8890 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8891 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8892
8893 if (is_lvds) {
8894 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8895 DPLL_FPA01_P1_POST_DIV_SHIFT);
8896
8897 if (lvds & LVDS_CLKB_POWER_UP)
8898 clock.p2 = 7;
8899 else
8900 clock.p2 = 14;
8901 } else {
8902 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8903 clock.p1 = 2;
8904 else {
8905 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8906 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8907 }
8908 if (dpll & PLL_P2_DIVIDE_BY_4)
8909 clock.p2 = 4;
8910 else
8911 clock.p2 = 2;
8912 }
8913
8914 i9xx_clock(refclk, &clock);
8915 }
8916
8917 /*
8918 * This value includes pixel_multiplier. We will use
8919 * port_clock to compute adjusted_mode.crtc_clock in the
8920 * encoder's get_config() function.
8921 */
8922 pipe_config->port_clock = clock.dot;
8923 }
8924
8925 int intel_dotclock_calculate(int link_freq,
8926 const struct intel_link_m_n *m_n)
8927 {
8928 /*
8929 * The calculation for the data clock is:
8930 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8931 * But we want to avoid losing precison if possible, so:
8932 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8933 *
8934 * and the link clock is simpler:
8935 * link_clock = (m * link_clock) / n
8936 */
8937
8938 if (!m_n->link_n)
8939 return 0;
8940
8941 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8942 }
8943
8944 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8945 struct intel_crtc_state *pipe_config)
8946 {
8947 struct drm_device *dev = crtc->base.dev;
8948
8949 /* read out port_clock from the DPLL */
8950 i9xx_crtc_clock_get(crtc, pipe_config);
8951
8952 /*
8953 * This value does not include pixel_multiplier.
8954 * We will check that port_clock and adjusted_mode.crtc_clock
8955 * agree once we know their relationship in the encoder's
8956 * get_config() function.
8957 */
8958 pipe_config->base.adjusted_mode.crtc_clock =
8959 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8960 &pipe_config->fdi_m_n);
8961 }
8962
8963 /** Returns the currently programmed mode of the given pipe. */
8964 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8965 struct drm_crtc *crtc)
8966 {
8967 struct drm_i915_private *dev_priv = dev->dev_private;
8968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8969 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8970 struct drm_display_mode *mode;
8971 struct intel_crtc_state pipe_config;
8972 int htot = I915_READ(HTOTAL(cpu_transcoder));
8973 int hsync = I915_READ(HSYNC(cpu_transcoder));
8974 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8975 int vsync = I915_READ(VSYNC(cpu_transcoder));
8976 enum pipe pipe = intel_crtc->pipe;
8977
8978 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8979 if (!mode)
8980 return NULL;
8981
8982 /*
8983 * Construct a pipe_config sufficient for getting the clock info
8984 * back out of crtc_clock_get.
8985 *
8986 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8987 * to use a real value here instead.
8988 */
8989 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8990 pipe_config.pixel_multiplier = 1;
8991 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8992 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8993 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8994 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8995
8996 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8997 mode->hdisplay = (htot & 0xffff) + 1;
8998 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8999 mode->hsync_start = (hsync & 0xffff) + 1;
9000 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9001 mode->vdisplay = (vtot & 0xffff) + 1;
9002 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9003 mode->vsync_start = (vsync & 0xffff) + 1;
9004 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9005
9006 drm_mode_set_name(mode);
9007
9008 return mode;
9009 }
9010
9011 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9012 {
9013 struct drm_device *dev = crtc->dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private;
9015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9016
9017 if (!HAS_GMCH_DISPLAY(dev))
9018 return;
9019
9020 if (!dev_priv->lvds_downclock_avail)
9021 return;
9022
9023 /*
9024 * Since this is called by a timer, we should never get here in
9025 * the manual case.
9026 */
9027 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9028 int pipe = intel_crtc->pipe;
9029 int dpll_reg = DPLL(pipe);
9030 int dpll;
9031
9032 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9033
9034 assert_panel_unlocked(dev_priv, pipe);
9035
9036 dpll = I915_READ(dpll_reg);
9037 dpll |= DISPLAY_RATE_SELECT_FPA1;
9038 I915_WRITE(dpll_reg, dpll);
9039 intel_wait_for_vblank(dev, pipe);
9040 dpll = I915_READ(dpll_reg);
9041 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9042 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9043 }
9044
9045 }
9046
9047 void intel_mark_busy(struct drm_device *dev)
9048 {
9049 struct drm_i915_private *dev_priv = dev->dev_private;
9050
9051 if (dev_priv->mm.busy)
9052 return;
9053
9054 intel_runtime_pm_get(dev_priv);
9055 i915_update_gfx_val(dev_priv);
9056 dev_priv->mm.busy = true;
9057 }
9058
9059 void intel_mark_idle(struct drm_device *dev)
9060 {
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 struct drm_crtc *crtc;
9063
9064 if (!dev_priv->mm.busy)
9065 return;
9066
9067 dev_priv->mm.busy = false;
9068
9069 if (!i915.powersave)
9070 goto out;
9071
9072 for_each_crtc(dev, crtc) {
9073 if (!crtc->primary->fb)
9074 continue;
9075
9076 intel_decrease_pllclock(crtc);
9077 }
9078
9079 if (INTEL_INFO(dev)->gen >= 6)
9080 gen6_rps_idle(dev->dev_private);
9081
9082 out:
9083 intel_runtime_pm_put(dev_priv);
9084 }
9085
9086 static void intel_crtc_set_state(struct intel_crtc *crtc,
9087 struct intel_crtc_state *crtc_state)
9088 {
9089 kfree(crtc->config);
9090 crtc->config = crtc_state;
9091 crtc->base.state = &crtc_state->base;
9092 }
9093
9094 static void intel_crtc_destroy(struct drm_crtc *crtc)
9095 {
9096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9097 struct drm_device *dev = crtc->dev;
9098 struct intel_unpin_work *work;
9099
9100 spin_lock_irq(&dev->event_lock);
9101 work = intel_crtc->unpin_work;
9102 intel_crtc->unpin_work = NULL;
9103 spin_unlock_irq(&dev->event_lock);
9104
9105 if (work) {
9106 cancel_work_sync(&work->work);
9107 kfree(work);
9108 }
9109
9110 intel_crtc_set_state(intel_crtc, NULL);
9111 drm_crtc_cleanup(crtc);
9112
9113 kfree(intel_crtc);
9114 }
9115
9116 static void intel_unpin_work_fn(struct work_struct *__work)
9117 {
9118 struct intel_unpin_work *work =
9119 container_of(__work, struct intel_unpin_work, work);
9120 struct drm_device *dev = work->crtc->dev;
9121 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9122
9123 mutex_lock(&dev->struct_mutex);
9124 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9125 drm_gem_object_unreference(&work->pending_flip_obj->base);
9126 drm_framebuffer_unreference(work->old_fb);
9127
9128 intel_fbc_update(dev);
9129
9130 if (work->flip_queued_req)
9131 i915_gem_request_assign(&work->flip_queued_req, NULL);
9132 mutex_unlock(&dev->struct_mutex);
9133
9134 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9135
9136 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9137 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9138
9139 kfree(work);
9140 }
9141
9142 static void do_intel_finish_page_flip(struct drm_device *dev,
9143 struct drm_crtc *crtc)
9144 {
9145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9146 struct intel_unpin_work *work;
9147 unsigned long flags;
9148
9149 /* Ignore early vblank irqs */
9150 if (intel_crtc == NULL)
9151 return;
9152
9153 /*
9154 * This is called both by irq handlers and the reset code (to complete
9155 * lost pageflips) so needs the full irqsave spinlocks.
9156 */
9157 spin_lock_irqsave(&dev->event_lock, flags);
9158 work = intel_crtc->unpin_work;
9159
9160 /* Ensure we don't miss a work->pending update ... */
9161 smp_rmb();
9162
9163 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9164 spin_unlock_irqrestore(&dev->event_lock, flags);
9165 return;
9166 }
9167
9168 page_flip_completed(intel_crtc);
9169
9170 spin_unlock_irqrestore(&dev->event_lock, flags);
9171 }
9172
9173 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9174 {
9175 struct drm_i915_private *dev_priv = dev->dev_private;
9176 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9177
9178 do_intel_finish_page_flip(dev, crtc);
9179 }
9180
9181 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9182 {
9183 struct drm_i915_private *dev_priv = dev->dev_private;
9184 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9185
9186 do_intel_finish_page_flip(dev, crtc);
9187 }
9188
9189 /* Is 'a' after or equal to 'b'? */
9190 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9191 {
9192 return !((a - b) & 0x80000000);
9193 }
9194
9195 static bool page_flip_finished(struct intel_crtc *crtc)
9196 {
9197 struct drm_device *dev = crtc->base.dev;
9198 struct drm_i915_private *dev_priv = dev->dev_private;
9199
9200 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9201 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9202 return true;
9203
9204 /*
9205 * The relevant registers doen't exist on pre-ctg.
9206 * As the flip done interrupt doesn't trigger for mmio
9207 * flips on gmch platforms, a flip count check isn't
9208 * really needed there. But since ctg has the registers,
9209 * include it in the check anyway.
9210 */
9211 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9212 return true;
9213
9214 /*
9215 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9216 * used the same base address. In that case the mmio flip might
9217 * have completed, but the CS hasn't even executed the flip yet.
9218 *
9219 * A flip count check isn't enough as the CS might have updated
9220 * the base address just after start of vblank, but before we
9221 * managed to process the interrupt. This means we'd complete the
9222 * CS flip too soon.
9223 *
9224 * Combining both checks should get us a good enough result. It may
9225 * still happen that the CS flip has been executed, but has not
9226 * yet actually completed. But in case the base address is the same
9227 * anyway, we don't really care.
9228 */
9229 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9230 crtc->unpin_work->gtt_offset &&
9231 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9232 crtc->unpin_work->flip_count);
9233 }
9234
9235 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9236 {
9237 struct drm_i915_private *dev_priv = dev->dev_private;
9238 struct intel_crtc *intel_crtc =
9239 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9240 unsigned long flags;
9241
9242
9243 /*
9244 * This is called both by irq handlers and the reset code (to complete
9245 * lost pageflips) so needs the full irqsave spinlocks.
9246 *
9247 * NB: An MMIO update of the plane base pointer will also
9248 * generate a page-flip completion irq, i.e. every modeset
9249 * is also accompanied by a spurious intel_prepare_page_flip().
9250 */
9251 spin_lock_irqsave(&dev->event_lock, flags);
9252 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9253 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9254 spin_unlock_irqrestore(&dev->event_lock, flags);
9255 }
9256
9257 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9258 {
9259 /* Ensure that the work item is consistent when activating it ... */
9260 smp_wmb();
9261 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9262 /* and that it is marked active as soon as the irq could fire. */
9263 smp_wmb();
9264 }
9265
9266 static int intel_gen2_queue_flip(struct drm_device *dev,
9267 struct drm_crtc *crtc,
9268 struct drm_framebuffer *fb,
9269 struct drm_i915_gem_object *obj,
9270 struct intel_engine_cs *ring,
9271 uint32_t flags)
9272 {
9273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9274 u32 flip_mask;
9275 int ret;
9276
9277 ret = intel_ring_begin(ring, 6);
9278 if (ret)
9279 return ret;
9280
9281 /* Can't queue multiple flips, so wait for the previous
9282 * one to finish before executing the next.
9283 */
9284 if (intel_crtc->plane)
9285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9286 else
9287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9289 intel_ring_emit(ring, MI_NOOP);
9290 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9292 intel_ring_emit(ring, fb->pitches[0]);
9293 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9294 intel_ring_emit(ring, 0); /* aux display base address, unused */
9295
9296 intel_mark_page_flip_active(intel_crtc);
9297 __intel_ring_advance(ring);
9298 return 0;
9299 }
9300
9301 static int intel_gen3_queue_flip(struct drm_device *dev,
9302 struct drm_crtc *crtc,
9303 struct drm_framebuffer *fb,
9304 struct drm_i915_gem_object *obj,
9305 struct intel_engine_cs *ring,
9306 uint32_t flags)
9307 {
9308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9309 u32 flip_mask;
9310 int ret;
9311
9312 ret = intel_ring_begin(ring, 6);
9313 if (ret)
9314 return ret;
9315
9316 if (intel_crtc->plane)
9317 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9318 else
9319 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9320 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9321 intel_ring_emit(ring, MI_NOOP);
9322 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9323 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9324 intel_ring_emit(ring, fb->pitches[0]);
9325 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9326 intel_ring_emit(ring, MI_NOOP);
9327
9328 intel_mark_page_flip_active(intel_crtc);
9329 __intel_ring_advance(ring);
9330 return 0;
9331 }
9332
9333 static int intel_gen4_queue_flip(struct drm_device *dev,
9334 struct drm_crtc *crtc,
9335 struct drm_framebuffer *fb,
9336 struct drm_i915_gem_object *obj,
9337 struct intel_engine_cs *ring,
9338 uint32_t flags)
9339 {
9340 struct drm_i915_private *dev_priv = dev->dev_private;
9341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9342 uint32_t pf, pipesrc;
9343 int ret;
9344
9345 ret = intel_ring_begin(ring, 4);
9346 if (ret)
9347 return ret;
9348
9349 /* i965+ uses the linear or tiled offsets from the
9350 * Display Registers (which do not change across a page-flip)
9351 * so we need only reprogram the base address.
9352 */
9353 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9354 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9355 intel_ring_emit(ring, fb->pitches[0]);
9356 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9357 obj->tiling_mode);
9358
9359 /* XXX Enabling the panel-fitter across page-flip is so far
9360 * untested on non-native modes, so ignore it for now.
9361 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9362 */
9363 pf = 0;
9364 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9365 intel_ring_emit(ring, pf | pipesrc);
9366
9367 intel_mark_page_flip_active(intel_crtc);
9368 __intel_ring_advance(ring);
9369 return 0;
9370 }
9371
9372 static int intel_gen6_queue_flip(struct drm_device *dev,
9373 struct drm_crtc *crtc,
9374 struct drm_framebuffer *fb,
9375 struct drm_i915_gem_object *obj,
9376 struct intel_engine_cs *ring,
9377 uint32_t flags)
9378 {
9379 struct drm_i915_private *dev_priv = dev->dev_private;
9380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9381 uint32_t pf, pipesrc;
9382 int ret;
9383
9384 ret = intel_ring_begin(ring, 4);
9385 if (ret)
9386 return ret;
9387
9388 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9389 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9390 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9391 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9392
9393 /* Contrary to the suggestions in the documentation,
9394 * "Enable Panel Fitter" does not seem to be required when page
9395 * flipping with a non-native mode, and worse causes a normal
9396 * modeset to fail.
9397 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9398 */
9399 pf = 0;
9400 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9401 intel_ring_emit(ring, pf | pipesrc);
9402
9403 intel_mark_page_flip_active(intel_crtc);
9404 __intel_ring_advance(ring);
9405 return 0;
9406 }
9407
9408 static int intel_gen7_queue_flip(struct drm_device *dev,
9409 struct drm_crtc *crtc,
9410 struct drm_framebuffer *fb,
9411 struct drm_i915_gem_object *obj,
9412 struct intel_engine_cs *ring,
9413 uint32_t flags)
9414 {
9415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9416 uint32_t plane_bit = 0;
9417 int len, ret;
9418
9419 switch (intel_crtc->plane) {
9420 case PLANE_A:
9421 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9422 break;
9423 case PLANE_B:
9424 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9425 break;
9426 case PLANE_C:
9427 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9428 break;
9429 default:
9430 WARN_ONCE(1, "unknown plane in flip command\n");
9431 return -ENODEV;
9432 }
9433
9434 len = 4;
9435 if (ring->id == RCS) {
9436 len += 6;
9437 /*
9438 * On Gen 8, SRM is now taking an extra dword to accommodate
9439 * 48bits addresses, and we need a NOOP for the batch size to
9440 * stay even.
9441 */
9442 if (IS_GEN8(dev))
9443 len += 2;
9444 }
9445
9446 /*
9447 * BSpec MI_DISPLAY_FLIP for IVB:
9448 * "The full packet must be contained within the same cache line."
9449 *
9450 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9451 * cacheline, if we ever start emitting more commands before
9452 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9453 * then do the cacheline alignment, and finally emit the
9454 * MI_DISPLAY_FLIP.
9455 */
9456 ret = intel_ring_cacheline_align(ring);
9457 if (ret)
9458 return ret;
9459
9460 ret = intel_ring_begin(ring, len);
9461 if (ret)
9462 return ret;
9463
9464 /* Unmask the flip-done completion message. Note that the bspec says that
9465 * we should do this for both the BCS and RCS, and that we must not unmask
9466 * more than one flip event at any time (or ensure that one flip message
9467 * can be sent by waiting for flip-done prior to queueing new flips).
9468 * Experimentation says that BCS works despite DERRMR masking all
9469 * flip-done completion events and that unmasking all planes at once
9470 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9471 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9472 */
9473 if (ring->id == RCS) {
9474 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9475 intel_ring_emit(ring, DERRMR);
9476 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9477 DERRMR_PIPEB_PRI_FLIP_DONE |
9478 DERRMR_PIPEC_PRI_FLIP_DONE));
9479 if (IS_GEN8(dev))
9480 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9481 MI_SRM_LRM_GLOBAL_GTT);
9482 else
9483 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9484 MI_SRM_LRM_GLOBAL_GTT);
9485 intel_ring_emit(ring, DERRMR);
9486 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9487 if (IS_GEN8(dev)) {
9488 intel_ring_emit(ring, 0);
9489 intel_ring_emit(ring, MI_NOOP);
9490 }
9491 }
9492
9493 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9494 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9495 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9496 intel_ring_emit(ring, (MI_NOOP));
9497
9498 intel_mark_page_flip_active(intel_crtc);
9499 __intel_ring_advance(ring);
9500 return 0;
9501 }
9502
9503 static bool use_mmio_flip(struct intel_engine_cs *ring,
9504 struct drm_i915_gem_object *obj)
9505 {
9506 /*
9507 * This is not being used for older platforms, because
9508 * non-availability of flip done interrupt forces us to use
9509 * CS flips. Older platforms derive flip done using some clever
9510 * tricks involving the flip_pending status bits and vblank irqs.
9511 * So using MMIO flips there would disrupt this mechanism.
9512 */
9513
9514 if (ring == NULL)
9515 return true;
9516
9517 if (INTEL_INFO(ring->dev)->gen < 5)
9518 return false;
9519
9520 if (i915.use_mmio_flip < 0)
9521 return false;
9522 else if (i915.use_mmio_flip > 0)
9523 return true;
9524 else if (i915.enable_execlists)
9525 return true;
9526 else
9527 return ring != i915_gem_request_get_ring(obj->last_read_req);
9528 }
9529
9530 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9531 {
9532 struct drm_device *dev = intel_crtc->base.dev;
9533 struct drm_i915_private *dev_priv = dev->dev_private;
9534 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9535 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9536 struct drm_i915_gem_object *obj = intel_fb->obj;
9537 const enum pipe pipe = intel_crtc->pipe;
9538 u32 ctl, stride;
9539
9540 ctl = I915_READ(PLANE_CTL(pipe, 0));
9541 ctl &= ~PLANE_CTL_TILED_MASK;
9542 if (obj->tiling_mode == I915_TILING_X)
9543 ctl |= PLANE_CTL_TILED_X;
9544
9545 /*
9546 * The stride is either expressed as a multiple of 64 bytes chunks for
9547 * linear buffers or in number of tiles for tiled buffers.
9548 */
9549 stride = fb->pitches[0] >> 6;
9550 if (obj->tiling_mode == I915_TILING_X)
9551 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9552
9553 /*
9554 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9555 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9556 */
9557 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9558 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9559
9560 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9561 POSTING_READ(PLANE_SURF(pipe, 0));
9562 }
9563
9564 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9565 {
9566 struct drm_device *dev = intel_crtc->base.dev;
9567 struct drm_i915_private *dev_priv = dev->dev_private;
9568 struct intel_framebuffer *intel_fb =
9569 to_intel_framebuffer(intel_crtc->base.primary->fb);
9570 struct drm_i915_gem_object *obj = intel_fb->obj;
9571 u32 dspcntr;
9572 u32 reg;
9573
9574 reg = DSPCNTR(intel_crtc->plane);
9575 dspcntr = I915_READ(reg);
9576
9577 if (obj->tiling_mode != I915_TILING_NONE)
9578 dspcntr |= DISPPLANE_TILED;
9579 else
9580 dspcntr &= ~DISPPLANE_TILED;
9581
9582 I915_WRITE(reg, dspcntr);
9583
9584 I915_WRITE(DSPSURF(intel_crtc->plane),
9585 intel_crtc->unpin_work->gtt_offset);
9586 POSTING_READ(DSPSURF(intel_crtc->plane));
9587
9588 }
9589
9590 /*
9591 * XXX: This is the temporary way to update the plane registers until we get
9592 * around to using the usual plane update functions for MMIO flips
9593 */
9594 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9595 {
9596 struct drm_device *dev = intel_crtc->base.dev;
9597 bool atomic_update;
9598 u32 start_vbl_count;
9599
9600 intel_mark_page_flip_active(intel_crtc);
9601
9602 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9603
9604 if (INTEL_INFO(dev)->gen >= 9)
9605 skl_do_mmio_flip(intel_crtc);
9606 else
9607 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9608 ilk_do_mmio_flip(intel_crtc);
9609
9610 if (atomic_update)
9611 intel_pipe_update_end(intel_crtc, start_vbl_count);
9612 }
9613
9614 static void intel_mmio_flip_work_func(struct work_struct *work)
9615 {
9616 struct intel_crtc *crtc =
9617 container_of(work, struct intel_crtc, mmio_flip.work);
9618 struct intel_mmio_flip *mmio_flip;
9619
9620 mmio_flip = &crtc->mmio_flip;
9621 if (mmio_flip->req)
9622 WARN_ON(__i915_wait_request(mmio_flip->req,
9623 crtc->reset_counter,
9624 false, NULL, NULL) != 0);
9625
9626 intel_do_mmio_flip(crtc);
9627 if (mmio_flip->req) {
9628 mutex_lock(&crtc->base.dev->struct_mutex);
9629 i915_gem_request_assign(&mmio_flip->req, NULL);
9630 mutex_unlock(&crtc->base.dev->struct_mutex);
9631 }
9632 }
9633
9634 static int intel_queue_mmio_flip(struct drm_device *dev,
9635 struct drm_crtc *crtc,
9636 struct drm_framebuffer *fb,
9637 struct drm_i915_gem_object *obj,
9638 struct intel_engine_cs *ring,
9639 uint32_t flags)
9640 {
9641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9642
9643 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9644 obj->last_write_req);
9645
9646 schedule_work(&intel_crtc->mmio_flip.work);
9647
9648 return 0;
9649 }
9650
9651 static int intel_default_queue_flip(struct drm_device *dev,
9652 struct drm_crtc *crtc,
9653 struct drm_framebuffer *fb,
9654 struct drm_i915_gem_object *obj,
9655 struct intel_engine_cs *ring,
9656 uint32_t flags)
9657 {
9658 return -ENODEV;
9659 }
9660
9661 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9662 struct drm_crtc *crtc)
9663 {
9664 struct drm_i915_private *dev_priv = dev->dev_private;
9665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9666 struct intel_unpin_work *work = intel_crtc->unpin_work;
9667 u32 addr;
9668
9669 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9670 return true;
9671
9672 if (!work->enable_stall_check)
9673 return false;
9674
9675 if (work->flip_ready_vblank == 0) {
9676 if (work->flip_queued_req &&
9677 !i915_gem_request_completed(work->flip_queued_req, true))
9678 return false;
9679
9680 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9681 }
9682
9683 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9684 return false;
9685
9686 /* Potential stall - if we see that the flip has happened,
9687 * assume a missed interrupt. */
9688 if (INTEL_INFO(dev)->gen >= 4)
9689 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9690 else
9691 addr = I915_READ(DSPADDR(intel_crtc->plane));
9692
9693 /* There is a potential issue here with a false positive after a flip
9694 * to the same address. We could address this by checking for a
9695 * non-incrementing frame counter.
9696 */
9697 return addr == work->gtt_offset;
9698 }
9699
9700 void intel_check_page_flip(struct drm_device *dev, int pipe)
9701 {
9702 struct drm_i915_private *dev_priv = dev->dev_private;
9703 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9705
9706 WARN_ON(!in_irq());
9707
9708 if (crtc == NULL)
9709 return;
9710
9711 spin_lock(&dev->event_lock);
9712 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9713 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9714 intel_crtc->unpin_work->flip_queued_vblank,
9715 drm_vblank_count(dev, pipe));
9716 page_flip_completed(intel_crtc);
9717 }
9718 spin_unlock(&dev->event_lock);
9719 }
9720
9721 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9722 struct drm_framebuffer *fb,
9723 struct drm_pending_vblank_event *event,
9724 uint32_t page_flip_flags)
9725 {
9726 struct drm_device *dev = crtc->dev;
9727 struct drm_i915_private *dev_priv = dev->dev_private;
9728 struct drm_framebuffer *old_fb = crtc->primary->fb;
9729 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9731 struct drm_plane *primary = crtc->primary;
9732 enum pipe pipe = intel_crtc->pipe;
9733 struct intel_unpin_work *work;
9734 struct intel_engine_cs *ring;
9735 int ret;
9736
9737 /*
9738 * drm_mode_page_flip_ioctl() should already catch this, but double
9739 * check to be safe. In the future we may enable pageflipping from
9740 * a disabled primary plane.
9741 */
9742 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9743 return -EBUSY;
9744
9745 /* Can't change pixel format via MI display flips. */
9746 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9747 return -EINVAL;
9748
9749 /*
9750 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9751 * Note that pitch changes could also affect these register.
9752 */
9753 if (INTEL_INFO(dev)->gen > 3 &&
9754 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9755 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9756 return -EINVAL;
9757
9758 if (i915_terminally_wedged(&dev_priv->gpu_error))
9759 goto out_hang;
9760
9761 work = kzalloc(sizeof(*work), GFP_KERNEL);
9762 if (work == NULL)
9763 return -ENOMEM;
9764
9765 work->event = event;
9766 work->crtc = crtc;
9767 work->old_fb = old_fb;
9768 INIT_WORK(&work->work, intel_unpin_work_fn);
9769
9770 ret = drm_crtc_vblank_get(crtc);
9771 if (ret)
9772 goto free_work;
9773
9774 /* We borrow the event spin lock for protecting unpin_work */
9775 spin_lock_irq(&dev->event_lock);
9776 if (intel_crtc->unpin_work) {
9777 /* Before declaring the flip queue wedged, check if
9778 * the hardware completed the operation behind our backs.
9779 */
9780 if (__intel_pageflip_stall_check(dev, crtc)) {
9781 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9782 page_flip_completed(intel_crtc);
9783 } else {
9784 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9785 spin_unlock_irq(&dev->event_lock);
9786
9787 drm_crtc_vblank_put(crtc);
9788 kfree(work);
9789 return -EBUSY;
9790 }
9791 }
9792 intel_crtc->unpin_work = work;
9793 spin_unlock_irq(&dev->event_lock);
9794
9795 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9796 flush_workqueue(dev_priv->wq);
9797
9798 ret = i915_mutex_lock_interruptible(dev);
9799 if (ret)
9800 goto cleanup;
9801
9802 /* Reference the objects for the scheduled work. */
9803 drm_framebuffer_reference(work->old_fb);
9804 drm_gem_object_reference(&obj->base);
9805
9806 crtc->primary->fb = fb;
9807 update_state_fb(crtc->primary);
9808
9809 work->pending_flip_obj = obj;
9810
9811 atomic_inc(&intel_crtc->unpin_work_count);
9812 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9813
9814 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9815 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9816
9817 if (IS_VALLEYVIEW(dev)) {
9818 ring = &dev_priv->ring[BCS];
9819 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9820 /* vlv: DISPLAY_FLIP fails to change tiling */
9821 ring = NULL;
9822 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9823 ring = &dev_priv->ring[BCS];
9824 } else if (INTEL_INFO(dev)->gen >= 7) {
9825 ring = i915_gem_request_get_ring(obj->last_read_req);
9826 if (ring == NULL || ring->id != RCS)
9827 ring = &dev_priv->ring[BCS];
9828 } else {
9829 ring = &dev_priv->ring[RCS];
9830 }
9831
9832 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9833 if (ret)
9834 goto cleanup_pending;
9835
9836 work->gtt_offset =
9837 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9838
9839 if (use_mmio_flip(ring, obj)) {
9840 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9841 page_flip_flags);
9842 if (ret)
9843 goto cleanup_unpin;
9844
9845 i915_gem_request_assign(&work->flip_queued_req,
9846 obj->last_write_req);
9847 } else {
9848 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9849 page_flip_flags);
9850 if (ret)
9851 goto cleanup_unpin;
9852
9853 i915_gem_request_assign(&work->flip_queued_req,
9854 intel_ring_get_request(ring));
9855 }
9856
9857 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9858 work->enable_stall_check = true;
9859
9860 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9861 INTEL_FRONTBUFFER_PRIMARY(pipe));
9862
9863 intel_fbc_disable(dev);
9864 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9865 mutex_unlock(&dev->struct_mutex);
9866
9867 trace_i915_flip_request(intel_crtc->plane, obj);
9868
9869 return 0;
9870
9871 cleanup_unpin:
9872 intel_unpin_fb_obj(obj);
9873 cleanup_pending:
9874 atomic_dec(&intel_crtc->unpin_work_count);
9875 crtc->primary->fb = old_fb;
9876 update_state_fb(crtc->primary);
9877 drm_framebuffer_unreference(work->old_fb);
9878 drm_gem_object_unreference(&obj->base);
9879 mutex_unlock(&dev->struct_mutex);
9880
9881 cleanup:
9882 spin_lock_irq(&dev->event_lock);
9883 intel_crtc->unpin_work = NULL;
9884 spin_unlock_irq(&dev->event_lock);
9885
9886 drm_crtc_vblank_put(crtc);
9887 free_work:
9888 kfree(work);
9889
9890 if (ret == -EIO) {
9891 out_hang:
9892 ret = intel_plane_restore(primary);
9893 if (ret == 0 && event) {
9894 spin_lock_irq(&dev->event_lock);
9895 drm_send_vblank_event(dev, pipe, event);
9896 spin_unlock_irq(&dev->event_lock);
9897 }
9898 }
9899 return ret;
9900 }
9901
9902 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9903 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9904 .load_lut = intel_crtc_load_lut,
9905 .atomic_begin = intel_begin_crtc_commit,
9906 .atomic_flush = intel_finish_crtc_commit,
9907 };
9908
9909 /**
9910 * intel_modeset_update_staged_output_state
9911 *
9912 * Updates the staged output configuration state, e.g. after we've read out the
9913 * current hw state.
9914 */
9915 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9916 {
9917 struct intel_crtc *crtc;
9918 struct intel_encoder *encoder;
9919 struct intel_connector *connector;
9920
9921 list_for_each_entry(connector, &dev->mode_config.connector_list,
9922 base.head) {
9923 connector->new_encoder =
9924 to_intel_encoder(connector->base.encoder);
9925 }
9926
9927 for_each_intel_encoder(dev, encoder) {
9928 encoder->new_crtc =
9929 to_intel_crtc(encoder->base.crtc);
9930 }
9931
9932 for_each_intel_crtc(dev, crtc) {
9933 crtc->new_enabled = crtc->base.enabled;
9934
9935 if (crtc->new_enabled)
9936 crtc->new_config = crtc->config;
9937 else
9938 crtc->new_config = NULL;
9939 }
9940 }
9941
9942 /**
9943 * intel_modeset_commit_output_state
9944 *
9945 * This function copies the stage display pipe configuration to the real one.
9946 */
9947 static void intel_modeset_commit_output_state(struct drm_device *dev)
9948 {
9949 struct intel_crtc *crtc;
9950 struct intel_encoder *encoder;
9951 struct intel_connector *connector;
9952
9953 list_for_each_entry(connector, &dev->mode_config.connector_list,
9954 base.head) {
9955 connector->base.encoder = &connector->new_encoder->base;
9956 }
9957
9958 for_each_intel_encoder(dev, encoder) {
9959 encoder->base.crtc = &encoder->new_crtc->base;
9960 }
9961
9962 for_each_intel_crtc(dev, crtc) {
9963 crtc->base.enabled = crtc->new_enabled;
9964 }
9965 }
9966
9967 static void
9968 connected_sink_compute_bpp(struct intel_connector *connector,
9969 struct intel_crtc_state *pipe_config)
9970 {
9971 int bpp = pipe_config->pipe_bpp;
9972
9973 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9974 connector->base.base.id,
9975 connector->base.name);
9976
9977 /* Don't use an invalid EDID bpc value */
9978 if (connector->base.display_info.bpc &&
9979 connector->base.display_info.bpc * 3 < bpp) {
9980 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9981 bpp, connector->base.display_info.bpc*3);
9982 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9983 }
9984
9985 /* Clamp bpp to 8 on screens without EDID 1.4 */
9986 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9987 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9988 bpp);
9989 pipe_config->pipe_bpp = 24;
9990 }
9991 }
9992
9993 static int
9994 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9995 struct drm_framebuffer *fb,
9996 struct intel_crtc_state *pipe_config)
9997 {
9998 struct drm_device *dev = crtc->base.dev;
9999 struct intel_connector *connector;
10000 int bpp;
10001
10002 switch (fb->pixel_format) {
10003 case DRM_FORMAT_C8:
10004 bpp = 8*3; /* since we go through a colormap */
10005 break;
10006 case DRM_FORMAT_XRGB1555:
10007 case DRM_FORMAT_ARGB1555:
10008 /* checked in intel_framebuffer_init already */
10009 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10010 return -EINVAL;
10011 case DRM_FORMAT_RGB565:
10012 bpp = 6*3; /* min is 18bpp */
10013 break;
10014 case DRM_FORMAT_XBGR8888:
10015 case DRM_FORMAT_ABGR8888:
10016 /* checked in intel_framebuffer_init already */
10017 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10018 return -EINVAL;
10019 case DRM_FORMAT_XRGB8888:
10020 case DRM_FORMAT_ARGB8888:
10021 bpp = 8*3;
10022 break;
10023 case DRM_FORMAT_XRGB2101010:
10024 case DRM_FORMAT_ARGB2101010:
10025 case DRM_FORMAT_XBGR2101010:
10026 case DRM_FORMAT_ABGR2101010:
10027 /* checked in intel_framebuffer_init already */
10028 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10029 return -EINVAL;
10030 bpp = 10*3;
10031 break;
10032 /* TODO: gen4+ supports 16 bpc floating point, too. */
10033 default:
10034 DRM_DEBUG_KMS("unsupported depth\n");
10035 return -EINVAL;
10036 }
10037
10038 pipe_config->pipe_bpp = bpp;
10039
10040 /* Clamp display bpp to EDID value */
10041 list_for_each_entry(connector, &dev->mode_config.connector_list,
10042 base.head) {
10043 if (!connector->new_encoder ||
10044 connector->new_encoder->new_crtc != crtc)
10045 continue;
10046
10047 connected_sink_compute_bpp(connector, pipe_config);
10048 }
10049
10050 return bpp;
10051 }
10052
10053 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10054 {
10055 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10056 "type: 0x%x flags: 0x%x\n",
10057 mode->crtc_clock,
10058 mode->crtc_hdisplay, mode->crtc_hsync_start,
10059 mode->crtc_hsync_end, mode->crtc_htotal,
10060 mode->crtc_vdisplay, mode->crtc_vsync_start,
10061 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10062 }
10063
10064 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10065 struct intel_crtc_state *pipe_config,
10066 const char *context)
10067 {
10068 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10069 context, pipe_name(crtc->pipe));
10070
10071 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10072 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10073 pipe_config->pipe_bpp, pipe_config->dither);
10074 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10075 pipe_config->has_pch_encoder,
10076 pipe_config->fdi_lanes,
10077 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10078 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10079 pipe_config->fdi_m_n.tu);
10080 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10081 pipe_config->has_dp_encoder,
10082 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10083 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10084 pipe_config->dp_m_n.tu);
10085
10086 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10087 pipe_config->has_dp_encoder,
10088 pipe_config->dp_m2_n2.gmch_m,
10089 pipe_config->dp_m2_n2.gmch_n,
10090 pipe_config->dp_m2_n2.link_m,
10091 pipe_config->dp_m2_n2.link_n,
10092 pipe_config->dp_m2_n2.tu);
10093
10094 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10095 pipe_config->has_audio,
10096 pipe_config->has_infoframe);
10097
10098 DRM_DEBUG_KMS("requested mode:\n");
10099 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10100 DRM_DEBUG_KMS("adjusted mode:\n");
10101 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10102 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10103 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10104 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10105 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10106 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10107 pipe_config->gmch_pfit.control,
10108 pipe_config->gmch_pfit.pgm_ratios,
10109 pipe_config->gmch_pfit.lvds_border_bits);
10110 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10111 pipe_config->pch_pfit.pos,
10112 pipe_config->pch_pfit.size,
10113 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10114 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10115 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10116 }
10117
10118 static bool encoders_cloneable(const struct intel_encoder *a,
10119 const struct intel_encoder *b)
10120 {
10121 /* masks could be asymmetric, so check both ways */
10122 return a == b || (a->cloneable & (1 << b->type) &&
10123 b->cloneable & (1 << a->type));
10124 }
10125
10126 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10127 struct intel_encoder *encoder)
10128 {
10129 struct drm_device *dev = crtc->base.dev;
10130 struct intel_encoder *source_encoder;
10131
10132 for_each_intel_encoder(dev, source_encoder) {
10133 if (source_encoder->new_crtc != crtc)
10134 continue;
10135
10136 if (!encoders_cloneable(encoder, source_encoder))
10137 return false;
10138 }
10139
10140 return true;
10141 }
10142
10143 static bool check_encoder_cloning(struct intel_crtc *crtc)
10144 {
10145 struct drm_device *dev = crtc->base.dev;
10146 struct intel_encoder *encoder;
10147
10148 for_each_intel_encoder(dev, encoder) {
10149 if (encoder->new_crtc != crtc)
10150 continue;
10151
10152 if (!check_single_encoder_cloning(crtc, encoder))
10153 return false;
10154 }
10155
10156 return true;
10157 }
10158
10159 static bool check_digital_port_conflicts(struct drm_device *dev)
10160 {
10161 struct intel_connector *connector;
10162 unsigned int used_ports = 0;
10163
10164 /*
10165 * Walk the connector list instead of the encoder
10166 * list to detect the problem on ddi platforms
10167 * where there's just one encoder per digital port.
10168 */
10169 list_for_each_entry(connector,
10170 &dev->mode_config.connector_list, base.head) {
10171 struct intel_encoder *encoder = connector->new_encoder;
10172
10173 if (!encoder)
10174 continue;
10175
10176 WARN_ON(!encoder->new_crtc);
10177
10178 switch (encoder->type) {
10179 unsigned int port_mask;
10180 case INTEL_OUTPUT_UNKNOWN:
10181 if (WARN_ON(!HAS_DDI(dev)))
10182 break;
10183 case INTEL_OUTPUT_DISPLAYPORT:
10184 case INTEL_OUTPUT_HDMI:
10185 case INTEL_OUTPUT_EDP:
10186 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10187
10188 /* the same port mustn't appear more than once */
10189 if (used_ports & port_mask)
10190 return false;
10191
10192 used_ports |= port_mask;
10193 default:
10194 break;
10195 }
10196 }
10197
10198 return true;
10199 }
10200
10201 static struct intel_crtc_state *
10202 intel_modeset_pipe_config(struct drm_crtc *crtc,
10203 struct drm_framebuffer *fb,
10204 struct drm_display_mode *mode)
10205 {
10206 struct drm_device *dev = crtc->dev;
10207 struct intel_encoder *encoder;
10208 struct intel_crtc_state *pipe_config;
10209 int plane_bpp, ret = -EINVAL;
10210 bool retry = true;
10211
10212 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10213 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10214 return ERR_PTR(-EINVAL);
10215 }
10216
10217 if (!check_digital_port_conflicts(dev)) {
10218 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10219 return ERR_PTR(-EINVAL);
10220 }
10221
10222 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10223 if (!pipe_config)
10224 return ERR_PTR(-ENOMEM);
10225
10226 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10227 drm_mode_copy(&pipe_config->base.mode, mode);
10228
10229 pipe_config->cpu_transcoder =
10230 (enum transcoder) to_intel_crtc(crtc)->pipe;
10231 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10232
10233 /*
10234 * Sanitize sync polarity flags based on requested ones. If neither
10235 * positive or negative polarity is requested, treat this as meaning
10236 * negative polarity.
10237 */
10238 if (!(pipe_config->base.adjusted_mode.flags &
10239 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10240 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10241
10242 if (!(pipe_config->base.adjusted_mode.flags &
10243 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10244 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10245
10246 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10247 * plane pixel format and any sink constraints into account. Returns the
10248 * source plane bpp so that dithering can be selected on mismatches
10249 * after encoders and crtc also have had their say. */
10250 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10251 fb, pipe_config);
10252 if (plane_bpp < 0)
10253 goto fail;
10254
10255 /*
10256 * Determine the real pipe dimensions. Note that stereo modes can
10257 * increase the actual pipe size due to the frame doubling and
10258 * insertion of additional space for blanks between the frame. This
10259 * is stored in the crtc timings. We use the requested mode to do this
10260 * computation to clearly distinguish it from the adjusted mode, which
10261 * can be changed by the connectors in the below retry loop.
10262 */
10263 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10264 &pipe_config->pipe_src_w,
10265 &pipe_config->pipe_src_h);
10266
10267 encoder_retry:
10268 /* Ensure the port clock defaults are reset when retrying. */
10269 pipe_config->port_clock = 0;
10270 pipe_config->pixel_multiplier = 1;
10271
10272 /* Fill in default crtc timings, allow encoders to overwrite them. */
10273 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10274 CRTC_STEREO_DOUBLE);
10275
10276 /* Pass our mode to the connectors and the CRTC to give them a chance to
10277 * adjust it according to limitations or connector properties, and also
10278 * a chance to reject the mode entirely.
10279 */
10280 for_each_intel_encoder(dev, encoder) {
10281
10282 if (&encoder->new_crtc->base != crtc)
10283 continue;
10284
10285 if (!(encoder->compute_config(encoder, pipe_config))) {
10286 DRM_DEBUG_KMS("Encoder config failure\n");
10287 goto fail;
10288 }
10289 }
10290
10291 /* Set default port clock if not overwritten by the encoder. Needs to be
10292 * done afterwards in case the encoder adjusts the mode. */
10293 if (!pipe_config->port_clock)
10294 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10295 * pipe_config->pixel_multiplier;
10296
10297 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10298 if (ret < 0) {
10299 DRM_DEBUG_KMS("CRTC fixup failed\n");
10300 goto fail;
10301 }
10302
10303 if (ret == RETRY) {
10304 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10305 ret = -EINVAL;
10306 goto fail;
10307 }
10308
10309 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10310 retry = false;
10311 goto encoder_retry;
10312 }
10313
10314 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10315 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10316 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10317
10318 return pipe_config;
10319 fail:
10320 kfree(pipe_config);
10321 return ERR_PTR(ret);
10322 }
10323
10324 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10325 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10326 static void
10327 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10328 unsigned *prepare_pipes, unsigned *disable_pipes)
10329 {
10330 struct intel_crtc *intel_crtc;
10331 struct drm_device *dev = crtc->dev;
10332 struct intel_encoder *encoder;
10333 struct intel_connector *connector;
10334 struct drm_crtc *tmp_crtc;
10335
10336 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10337
10338 /* Check which crtcs have changed outputs connected to them, these need
10339 * to be part of the prepare_pipes mask. We don't (yet) support global
10340 * modeset across multiple crtcs, so modeset_pipes will only have one
10341 * bit set at most. */
10342 list_for_each_entry(connector, &dev->mode_config.connector_list,
10343 base.head) {
10344 if (connector->base.encoder == &connector->new_encoder->base)
10345 continue;
10346
10347 if (connector->base.encoder) {
10348 tmp_crtc = connector->base.encoder->crtc;
10349
10350 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10351 }
10352
10353 if (connector->new_encoder)
10354 *prepare_pipes |=
10355 1 << connector->new_encoder->new_crtc->pipe;
10356 }
10357
10358 for_each_intel_encoder(dev, encoder) {
10359 if (encoder->base.crtc == &encoder->new_crtc->base)
10360 continue;
10361
10362 if (encoder->base.crtc) {
10363 tmp_crtc = encoder->base.crtc;
10364
10365 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10366 }
10367
10368 if (encoder->new_crtc)
10369 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10370 }
10371
10372 /* Check for pipes that will be enabled/disabled ... */
10373 for_each_intel_crtc(dev, intel_crtc) {
10374 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10375 continue;
10376
10377 if (!intel_crtc->new_enabled)
10378 *disable_pipes |= 1 << intel_crtc->pipe;
10379 else
10380 *prepare_pipes |= 1 << intel_crtc->pipe;
10381 }
10382
10383
10384 /* set_mode is also used to update properties on life display pipes. */
10385 intel_crtc = to_intel_crtc(crtc);
10386 if (intel_crtc->new_enabled)
10387 *prepare_pipes |= 1 << intel_crtc->pipe;
10388
10389 /*
10390 * For simplicity do a full modeset on any pipe where the output routing
10391 * changed. We could be more clever, but that would require us to be
10392 * more careful with calling the relevant encoder->mode_set functions.
10393 */
10394 if (*prepare_pipes)
10395 *modeset_pipes = *prepare_pipes;
10396
10397 /* ... and mask these out. */
10398 *modeset_pipes &= ~(*disable_pipes);
10399 *prepare_pipes &= ~(*disable_pipes);
10400
10401 /*
10402 * HACK: We don't (yet) fully support global modesets. intel_set_config
10403 * obies this rule, but the modeset restore mode of
10404 * intel_modeset_setup_hw_state does not.
10405 */
10406 *modeset_pipes &= 1 << intel_crtc->pipe;
10407 *prepare_pipes &= 1 << intel_crtc->pipe;
10408
10409 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10410 *modeset_pipes, *prepare_pipes, *disable_pipes);
10411 }
10412
10413 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10414 {
10415 struct drm_encoder *encoder;
10416 struct drm_device *dev = crtc->dev;
10417
10418 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10419 if (encoder->crtc == crtc)
10420 return true;
10421
10422 return false;
10423 }
10424
10425 static void
10426 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10427 {
10428 struct drm_i915_private *dev_priv = dev->dev_private;
10429 struct intel_encoder *intel_encoder;
10430 struct intel_crtc *intel_crtc;
10431 struct drm_connector *connector;
10432
10433 intel_shared_dpll_commit(dev_priv);
10434
10435 for_each_intel_encoder(dev, intel_encoder) {
10436 if (!intel_encoder->base.crtc)
10437 continue;
10438
10439 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10440
10441 if (prepare_pipes & (1 << intel_crtc->pipe))
10442 intel_encoder->connectors_active = false;
10443 }
10444
10445 intel_modeset_commit_output_state(dev);
10446
10447 /* Double check state. */
10448 for_each_intel_crtc(dev, intel_crtc) {
10449 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10450 WARN_ON(intel_crtc->new_config &&
10451 intel_crtc->new_config != intel_crtc->config);
10452 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10453 }
10454
10455 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10456 if (!connector->encoder || !connector->encoder->crtc)
10457 continue;
10458
10459 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10460
10461 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10462 struct drm_property *dpms_property =
10463 dev->mode_config.dpms_property;
10464
10465 connector->dpms = DRM_MODE_DPMS_ON;
10466 drm_object_property_set_value(&connector->base,
10467 dpms_property,
10468 DRM_MODE_DPMS_ON);
10469
10470 intel_encoder = to_intel_encoder(connector->encoder);
10471 intel_encoder->connectors_active = true;
10472 }
10473 }
10474
10475 }
10476
10477 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10478 {
10479 int diff;
10480
10481 if (clock1 == clock2)
10482 return true;
10483
10484 if (!clock1 || !clock2)
10485 return false;
10486
10487 diff = abs(clock1 - clock2);
10488
10489 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10490 return true;
10491
10492 return false;
10493 }
10494
10495 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10496 list_for_each_entry((intel_crtc), \
10497 &(dev)->mode_config.crtc_list, \
10498 base.head) \
10499 if (mask & (1 <<(intel_crtc)->pipe))
10500
10501 static bool
10502 intel_pipe_config_compare(struct drm_device *dev,
10503 struct intel_crtc_state *current_config,
10504 struct intel_crtc_state *pipe_config)
10505 {
10506 #define PIPE_CONF_CHECK_X(name) \
10507 if (current_config->name != pipe_config->name) { \
10508 DRM_ERROR("mismatch in " #name " " \
10509 "(expected 0x%08x, found 0x%08x)\n", \
10510 current_config->name, \
10511 pipe_config->name); \
10512 return false; \
10513 }
10514
10515 #define PIPE_CONF_CHECK_I(name) \
10516 if (current_config->name != pipe_config->name) { \
10517 DRM_ERROR("mismatch in " #name " " \
10518 "(expected %i, found %i)\n", \
10519 current_config->name, \
10520 pipe_config->name); \
10521 return false; \
10522 }
10523
10524 /* This is required for BDW+ where there is only one set of registers for
10525 * switching between high and low RR.
10526 * This macro can be used whenever a comparison has to be made between one
10527 * hw state and multiple sw state variables.
10528 */
10529 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10530 if ((current_config->name != pipe_config->name) && \
10531 (current_config->alt_name != pipe_config->name)) { \
10532 DRM_ERROR("mismatch in " #name " " \
10533 "(expected %i or %i, found %i)\n", \
10534 current_config->name, \
10535 current_config->alt_name, \
10536 pipe_config->name); \
10537 return false; \
10538 }
10539
10540 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10541 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10542 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10543 "(expected %i, found %i)\n", \
10544 current_config->name & (mask), \
10545 pipe_config->name & (mask)); \
10546 return false; \
10547 }
10548
10549 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10550 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10551 DRM_ERROR("mismatch in " #name " " \
10552 "(expected %i, found %i)\n", \
10553 current_config->name, \
10554 pipe_config->name); \
10555 return false; \
10556 }
10557
10558 #define PIPE_CONF_QUIRK(quirk) \
10559 ((current_config->quirks | pipe_config->quirks) & (quirk))
10560
10561 PIPE_CONF_CHECK_I(cpu_transcoder);
10562
10563 PIPE_CONF_CHECK_I(has_pch_encoder);
10564 PIPE_CONF_CHECK_I(fdi_lanes);
10565 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10566 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10567 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10568 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10569 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10570
10571 PIPE_CONF_CHECK_I(has_dp_encoder);
10572
10573 if (INTEL_INFO(dev)->gen < 8) {
10574 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10575 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10576 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10577 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10578 PIPE_CONF_CHECK_I(dp_m_n.tu);
10579
10580 if (current_config->has_drrs) {
10581 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10582 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10583 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10584 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10585 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10586 }
10587 } else {
10588 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10589 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10590 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10591 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10592 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10593 }
10594
10595 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10601
10602 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10603 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10604 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10605 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10606 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10607 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10608
10609 PIPE_CONF_CHECK_I(pixel_multiplier);
10610 PIPE_CONF_CHECK_I(has_hdmi_sink);
10611 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10612 IS_VALLEYVIEW(dev))
10613 PIPE_CONF_CHECK_I(limited_color_range);
10614 PIPE_CONF_CHECK_I(has_infoframe);
10615
10616 PIPE_CONF_CHECK_I(has_audio);
10617
10618 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10619 DRM_MODE_FLAG_INTERLACE);
10620
10621 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10622 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10623 DRM_MODE_FLAG_PHSYNC);
10624 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10625 DRM_MODE_FLAG_NHSYNC);
10626 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10627 DRM_MODE_FLAG_PVSYNC);
10628 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10629 DRM_MODE_FLAG_NVSYNC);
10630 }
10631
10632 PIPE_CONF_CHECK_I(pipe_src_w);
10633 PIPE_CONF_CHECK_I(pipe_src_h);
10634
10635 /*
10636 * FIXME: BIOS likes to set up a cloned config with lvds+external
10637 * screen. Since we don't yet re-compute the pipe config when moving
10638 * just the lvds port away to another pipe the sw tracking won't match.
10639 *
10640 * Proper atomic modesets with recomputed global state will fix this.
10641 * Until then just don't check gmch state for inherited modes.
10642 */
10643 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10644 PIPE_CONF_CHECK_I(gmch_pfit.control);
10645 /* pfit ratios are autocomputed by the hw on gen4+ */
10646 if (INTEL_INFO(dev)->gen < 4)
10647 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10648 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10649 }
10650
10651 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10652 if (current_config->pch_pfit.enabled) {
10653 PIPE_CONF_CHECK_I(pch_pfit.pos);
10654 PIPE_CONF_CHECK_I(pch_pfit.size);
10655 }
10656
10657 /* BDW+ don't expose a synchronous way to read the state */
10658 if (IS_HASWELL(dev))
10659 PIPE_CONF_CHECK_I(ips_enabled);
10660
10661 PIPE_CONF_CHECK_I(double_wide);
10662
10663 PIPE_CONF_CHECK_X(ddi_pll_sel);
10664
10665 PIPE_CONF_CHECK_I(shared_dpll);
10666 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10667 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10668 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10669 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10670 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10671 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10672 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10673 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10674
10675 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10676 PIPE_CONF_CHECK_I(pipe_bpp);
10677
10678 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10679 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10680
10681 #undef PIPE_CONF_CHECK_X
10682 #undef PIPE_CONF_CHECK_I
10683 #undef PIPE_CONF_CHECK_I_ALT
10684 #undef PIPE_CONF_CHECK_FLAGS
10685 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10686 #undef PIPE_CONF_QUIRK
10687
10688 return true;
10689 }
10690
10691 static void check_wm_state(struct drm_device *dev)
10692 {
10693 struct drm_i915_private *dev_priv = dev->dev_private;
10694 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10695 struct intel_crtc *intel_crtc;
10696 int plane;
10697
10698 if (INTEL_INFO(dev)->gen < 9)
10699 return;
10700
10701 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10702 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10703
10704 for_each_intel_crtc(dev, intel_crtc) {
10705 struct skl_ddb_entry *hw_entry, *sw_entry;
10706 const enum pipe pipe = intel_crtc->pipe;
10707
10708 if (!intel_crtc->active)
10709 continue;
10710
10711 /* planes */
10712 for_each_plane(pipe, plane) {
10713 hw_entry = &hw_ddb.plane[pipe][plane];
10714 sw_entry = &sw_ddb->plane[pipe][plane];
10715
10716 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10717 continue;
10718
10719 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10720 "(expected (%u,%u), found (%u,%u))\n",
10721 pipe_name(pipe), plane + 1,
10722 sw_entry->start, sw_entry->end,
10723 hw_entry->start, hw_entry->end);
10724 }
10725
10726 /* cursor */
10727 hw_entry = &hw_ddb.cursor[pipe];
10728 sw_entry = &sw_ddb->cursor[pipe];
10729
10730 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10731 continue;
10732
10733 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10734 "(expected (%u,%u), found (%u,%u))\n",
10735 pipe_name(pipe),
10736 sw_entry->start, sw_entry->end,
10737 hw_entry->start, hw_entry->end);
10738 }
10739 }
10740
10741 static void
10742 check_connector_state(struct drm_device *dev)
10743 {
10744 struct intel_connector *connector;
10745
10746 list_for_each_entry(connector, &dev->mode_config.connector_list,
10747 base.head) {
10748 /* This also checks the encoder/connector hw state with the
10749 * ->get_hw_state callbacks. */
10750 intel_connector_check_state(connector);
10751
10752 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10753 "connector's staged encoder doesn't match current encoder\n");
10754 }
10755 }
10756
10757 static void
10758 check_encoder_state(struct drm_device *dev)
10759 {
10760 struct intel_encoder *encoder;
10761 struct intel_connector *connector;
10762
10763 for_each_intel_encoder(dev, encoder) {
10764 bool enabled = false;
10765 bool active = false;
10766 enum pipe pipe, tracked_pipe;
10767
10768 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10769 encoder->base.base.id,
10770 encoder->base.name);
10771
10772 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10773 "encoder's stage crtc doesn't match current crtc\n");
10774 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10775 "encoder's active_connectors set, but no crtc\n");
10776
10777 list_for_each_entry(connector, &dev->mode_config.connector_list,
10778 base.head) {
10779 if (connector->base.encoder != &encoder->base)
10780 continue;
10781 enabled = true;
10782 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10783 active = true;
10784 }
10785 /*
10786 * for MST connectors if we unplug the connector is gone
10787 * away but the encoder is still connected to a crtc
10788 * until a modeset happens in response to the hotplug.
10789 */
10790 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10791 continue;
10792
10793 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10794 "encoder's enabled state mismatch "
10795 "(expected %i, found %i)\n",
10796 !!encoder->base.crtc, enabled);
10797 I915_STATE_WARN(active && !encoder->base.crtc,
10798 "active encoder with no crtc\n");
10799
10800 I915_STATE_WARN(encoder->connectors_active != active,
10801 "encoder's computed active state doesn't match tracked active state "
10802 "(expected %i, found %i)\n", active, encoder->connectors_active);
10803
10804 active = encoder->get_hw_state(encoder, &pipe);
10805 I915_STATE_WARN(active != encoder->connectors_active,
10806 "encoder's hw state doesn't match sw tracking "
10807 "(expected %i, found %i)\n",
10808 encoder->connectors_active, active);
10809
10810 if (!encoder->base.crtc)
10811 continue;
10812
10813 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10814 I915_STATE_WARN(active && pipe != tracked_pipe,
10815 "active encoder's pipe doesn't match"
10816 "(expected %i, found %i)\n",
10817 tracked_pipe, pipe);
10818
10819 }
10820 }
10821
10822 static void
10823 check_crtc_state(struct drm_device *dev)
10824 {
10825 struct drm_i915_private *dev_priv = dev->dev_private;
10826 struct intel_crtc *crtc;
10827 struct intel_encoder *encoder;
10828 struct intel_crtc_state pipe_config;
10829
10830 for_each_intel_crtc(dev, crtc) {
10831 bool enabled = false;
10832 bool active = false;
10833
10834 memset(&pipe_config, 0, sizeof(pipe_config));
10835
10836 DRM_DEBUG_KMS("[CRTC:%d]\n",
10837 crtc->base.base.id);
10838
10839 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10840 "active crtc, but not enabled in sw tracking\n");
10841
10842 for_each_intel_encoder(dev, encoder) {
10843 if (encoder->base.crtc != &crtc->base)
10844 continue;
10845 enabled = true;
10846 if (encoder->connectors_active)
10847 active = true;
10848 }
10849
10850 I915_STATE_WARN(active != crtc->active,
10851 "crtc's computed active state doesn't match tracked active state "
10852 "(expected %i, found %i)\n", active, crtc->active);
10853 I915_STATE_WARN(enabled != crtc->base.enabled,
10854 "crtc's computed enabled state doesn't match tracked enabled state "
10855 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10856
10857 active = dev_priv->display.get_pipe_config(crtc,
10858 &pipe_config);
10859
10860 /* hw state is inconsistent with the pipe quirk */
10861 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10862 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10863 active = crtc->active;
10864
10865 for_each_intel_encoder(dev, encoder) {
10866 enum pipe pipe;
10867 if (encoder->base.crtc != &crtc->base)
10868 continue;
10869 if (encoder->get_hw_state(encoder, &pipe))
10870 encoder->get_config(encoder, &pipe_config);
10871 }
10872
10873 I915_STATE_WARN(crtc->active != active,
10874 "crtc active state doesn't match with hw state "
10875 "(expected %i, found %i)\n", crtc->active, active);
10876
10877 if (active &&
10878 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10879 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10880 intel_dump_pipe_config(crtc, &pipe_config,
10881 "[hw state]");
10882 intel_dump_pipe_config(crtc, crtc->config,
10883 "[sw state]");
10884 }
10885 }
10886 }
10887
10888 static void
10889 check_shared_dpll_state(struct drm_device *dev)
10890 {
10891 struct drm_i915_private *dev_priv = dev->dev_private;
10892 struct intel_crtc *crtc;
10893 struct intel_dpll_hw_state dpll_hw_state;
10894 int i;
10895
10896 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10897 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10898 int enabled_crtcs = 0, active_crtcs = 0;
10899 bool active;
10900
10901 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10902
10903 DRM_DEBUG_KMS("%s\n", pll->name);
10904
10905 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10906
10907 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10908 "more active pll users than references: %i vs %i\n",
10909 pll->active, hweight32(pll->config.crtc_mask));
10910 I915_STATE_WARN(pll->active && !pll->on,
10911 "pll in active use but not on in sw tracking\n");
10912 I915_STATE_WARN(pll->on && !pll->active,
10913 "pll in on but not on in use in sw tracking\n");
10914 I915_STATE_WARN(pll->on != active,
10915 "pll on state mismatch (expected %i, found %i)\n",
10916 pll->on, active);
10917
10918 for_each_intel_crtc(dev, crtc) {
10919 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10920 enabled_crtcs++;
10921 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10922 active_crtcs++;
10923 }
10924 I915_STATE_WARN(pll->active != active_crtcs,
10925 "pll active crtcs mismatch (expected %i, found %i)\n",
10926 pll->active, active_crtcs);
10927 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10928 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10929 hweight32(pll->config.crtc_mask), enabled_crtcs);
10930
10931 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10932 sizeof(dpll_hw_state)),
10933 "pll hw state mismatch\n");
10934 }
10935 }
10936
10937 void
10938 intel_modeset_check_state(struct drm_device *dev)
10939 {
10940 check_wm_state(dev);
10941 check_connector_state(dev);
10942 check_encoder_state(dev);
10943 check_crtc_state(dev);
10944 check_shared_dpll_state(dev);
10945 }
10946
10947 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10948 int dotclock)
10949 {
10950 /*
10951 * FDI already provided one idea for the dotclock.
10952 * Yell if the encoder disagrees.
10953 */
10954 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10955 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10956 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10957 }
10958
10959 static void update_scanline_offset(struct intel_crtc *crtc)
10960 {
10961 struct drm_device *dev = crtc->base.dev;
10962
10963 /*
10964 * The scanline counter increments at the leading edge of hsync.
10965 *
10966 * On most platforms it starts counting from vtotal-1 on the
10967 * first active line. That means the scanline counter value is
10968 * always one less than what we would expect. Ie. just after
10969 * start of vblank, which also occurs at start of hsync (on the
10970 * last active line), the scanline counter will read vblank_start-1.
10971 *
10972 * On gen2 the scanline counter starts counting from 1 instead
10973 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10974 * to keep the value positive), instead of adding one.
10975 *
10976 * On HSW+ the behaviour of the scanline counter depends on the output
10977 * type. For DP ports it behaves like most other platforms, but on HDMI
10978 * there's an extra 1 line difference. So we need to add two instead of
10979 * one to the value.
10980 */
10981 if (IS_GEN2(dev)) {
10982 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10983 int vtotal;
10984
10985 vtotal = mode->crtc_vtotal;
10986 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10987 vtotal /= 2;
10988
10989 crtc->scanline_offset = vtotal - 1;
10990 } else if (HAS_DDI(dev) &&
10991 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10992 crtc->scanline_offset = 2;
10993 } else
10994 crtc->scanline_offset = 1;
10995 }
10996
10997 static struct intel_crtc_state *
10998 intel_modeset_compute_config(struct drm_crtc *crtc,
10999 struct drm_display_mode *mode,
11000 struct drm_framebuffer *fb,
11001 unsigned *modeset_pipes,
11002 unsigned *prepare_pipes,
11003 unsigned *disable_pipes)
11004 {
11005 struct intel_crtc_state *pipe_config = NULL;
11006
11007 intel_modeset_affected_pipes(crtc, modeset_pipes,
11008 prepare_pipes, disable_pipes);
11009
11010 if ((*modeset_pipes) == 0)
11011 goto out;
11012
11013 /*
11014 * Note this needs changes when we start tracking multiple modes
11015 * and crtcs. At that point we'll need to compute the whole config
11016 * (i.e. one pipe_config for each crtc) rather than just the one
11017 * for this crtc.
11018 */
11019 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11020 if (IS_ERR(pipe_config)) {
11021 goto out;
11022 }
11023 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11024 "[modeset]");
11025
11026 out:
11027 return pipe_config;
11028 }
11029
11030 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11031 unsigned modeset_pipes,
11032 unsigned disable_pipes)
11033 {
11034 struct drm_i915_private *dev_priv = to_i915(dev);
11035 unsigned clear_pipes = modeset_pipes | disable_pipes;
11036 struct intel_crtc *intel_crtc;
11037 int ret = 0;
11038
11039 if (!dev_priv->display.crtc_compute_clock)
11040 return 0;
11041
11042 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11043 if (ret)
11044 goto done;
11045
11046 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11047 struct intel_crtc_state *state = intel_crtc->new_config;
11048 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11049 state);
11050 if (ret) {
11051 intel_shared_dpll_abort_config(dev_priv);
11052 goto done;
11053 }
11054 }
11055
11056 done:
11057 return ret;
11058 }
11059
11060 static int __intel_set_mode(struct drm_crtc *crtc,
11061 struct drm_display_mode *mode,
11062 int x, int y, struct drm_framebuffer *fb,
11063 struct intel_crtc_state *pipe_config,
11064 unsigned modeset_pipes,
11065 unsigned prepare_pipes,
11066 unsigned disable_pipes)
11067 {
11068 struct drm_device *dev = crtc->dev;
11069 struct drm_i915_private *dev_priv = dev->dev_private;
11070 struct drm_display_mode *saved_mode;
11071 struct intel_crtc *intel_crtc;
11072 int ret = 0;
11073
11074 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11075 if (!saved_mode)
11076 return -ENOMEM;
11077
11078 *saved_mode = crtc->mode;
11079
11080 if (modeset_pipes)
11081 to_intel_crtc(crtc)->new_config = pipe_config;
11082
11083 /*
11084 * See if the config requires any additional preparation, e.g.
11085 * to adjust global state with pipes off. We need to do this
11086 * here so we can get the modeset_pipe updated config for the new
11087 * mode set on this crtc. For other crtcs we need to use the
11088 * adjusted_mode bits in the crtc directly.
11089 */
11090 if (IS_VALLEYVIEW(dev)) {
11091 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11092
11093 /* may have added more to prepare_pipes than we should */
11094 prepare_pipes &= ~disable_pipes;
11095 }
11096
11097 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11098 if (ret)
11099 goto done;
11100
11101 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11102 intel_crtc_disable(&intel_crtc->base);
11103
11104 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11105 if (intel_crtc->base.enabled)
11106 dev_priv->display.crtc_disable(&intel_crtc->base);
11107 }
11108
11109 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11110 * to set it here already despite that we pass it down the callchain.
11111 *
11112 * Note we'll need to fix this up when we start tracking multiple
11113 * pipes; here we assume a single modeset_pipe and only track the
11114 * single crtc and mode.
11115 */
11116 if (modeset_pipes) {
11117 crtc->mode = *mode;
11118 /* mode_set/enable/disable functions rely on a correct pipe
11119 * config. */
11120 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11121
11122 /*
11123 * Calculate and store various constants which
11124 * are later needed by vblank and swap-completion
11125 * timestamping. They are derived from true hwmode.
11126 */
11127 drm_calc_timestamping_constants(crtc,
11128 &pipe_config->base.adjusted_mode);
11129 }
11130
11131 /* Only after disabling all output pipelines that will be changed can we
11132 * update the the output configuration. */
11133 intel_modeset_update_state(dev, prepare_pipes);
11134
11135 modeset_update_crtc_power_domains(dev);
11136
11137 /* Set up the DPLL and any encoders state that needs to adjust or depend
11138 * on the DPLL.
11139 */
11140 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11141 struct drm_plane *primary = intel_crtc->base.primary;
11142 int vdisplay, hdisplay;
11143
11144 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11145 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11146 fb, 0, 0,
11147 hdisplay, vdisplay,
11148 x << 16, y << 16,
11149 hdisplay << 16, vdisplay << 16);
11150 }
11151
11152 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11153 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11154 update_scanline_offset(intel_crtc);
11155
11156 dev_priv->display.crtc_enable(&intel_crtc->base);
11157 }
11158
11159 /* FIXME: add subpixel order */
11160 done:
11161 if (ret && crtc->enabled)
11162 crtc->mode = *saved_mode;
11163
11164 kfree(saved_mode);
11165 return ret;
11166 }
11167
11168 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11169 struct drm_display_mode *mode,
11170 int x, int y, struct drm_framebuffer *fb,
11171 struct intel_crtc_state *pipe_config,
11172 unsigned modeset_pipes,
11173 unsigned prepare_pipes,
11174 unsigned disable_pipes)
11175 {
11176 int ret;
11177
11178 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11179 prepare_pipes, disable_pipes);
11180
11181 if (ret == 0)
11182 intel_modeset_check_state(crtc->dev);
11183
11184 return ret;
11185 }
11186
11187 static int intel_set_mode(struct drm_crtc *crtc,
11188 struct drm_display_mode *mode,
11189 int x, int y, struct drm_framebuffer *fb)
11190 {
11191 struct intel_crtc_state *pipe_config;
11192 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11193
11194 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11195 &modeset_pipes,
11196 &prepare_pipes,
11197 &disable_pipes);
11198
11199 if (IS_ERR(pipe_config))
11200 return PTR_ERR(pipe_config);
11201
11202 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11203 modeset_pipes, prepare_pipes,
11204 disable_pipes);
11205 }
11206
11207 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11208 {
11209 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11210 }
11211
11212 #undef for_each_intel_crtc_masked
11213
11214 static void intel_set_config_free(struct intel_set_config *config)
11215 {
11216 if (!config)
11217 return;
11218
11219 kfree(config->save_connector_encoders);
11220 kfree(config->save_encoder_crtcs);
11221 kfree(config->save_crtc_enabled);
11222 kfree(config);
11223 }
11224
11225 static int intel_set_config_save_state(struct drm_device *dev,
11226 struct intel_set_config *config)
11227 {
11228 struct drm_crtc *crtc;
11229 struct drm_encoder *encoder;
11230 struct drm_connector *connector;
11231 int count;
11232
11233 config->save_crtc_enabled =
11234 kcalloc(dev->mode_config.num_crtc,
11235 sizeof(bool), GFP_KERNEL);
11236 if (!config->save_crtc_enabled)
11237 return -ENOMEM;
11238
11239 config->save_encoder_crtcs =
11240 kcalloc(dev->mode_config.num_encoder,
11241 sizeof(struct drm_crtc *), GFP_KERNEL);
11242 if (!config->save_encoder_crtcs)
11243 return -ENOMEM;
11244
11245 config->save_connector_encoders =
11246 kcalloc(dev->mode_config.num_connector,
11247 sizeof(struct drm_encoder *), GFP_KERNEL);
11248 if (!config->save_connector_encoders)
11249 return -ENOMEM;
11250
11251 /* Copy data. Note that driver private data is not affected.
11252 * Should anything bad happen only the expected state is
11253 * restored, not the drivers personal bookkeeping.
11254 */
11255 count = 0;
11256 for_each_crtc(dev, crtc) {
11257 config->save_crtc_enabled[count++] = crtc->enabled;
11258 }
11259
11260 count = 0;
11261 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11262 config->save_encoder_crtcs[count++] = encoder->crtc;
11263 }
11264
11265 count = 0;
11266 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11267 config->save_connector_encoders[count++] = connector->encoder;
11268 }
11269
11270 return 0;
11271 }
11272
11273 static void intel_set_config_restore_state(struct drm_device *dev,
11274 struct intel_set_config *config)
11275 {
11276 struct intel_crtc *crtc;
11277 struct intel_encoder *encoder;
11278 struct intel_connector *connector;
11279 int count;
11280
11281 count = 0;
11282 for_each_intel_crtc(dev, crtc) {
11283 crtc->new_enabled = config->save_crtc_enabled[count++];
11284
11285 if (crtc->new_enabled)
11286 crtc->new_config = crtc->config;
11287 else
11288 crtc->new_config = NULL;
11289 }
11290
11291 count = 0;
11292 for_each_intel_encoder(dev, encoder) {
11293 encoder->new_crtc =
11294 to_intel_crtc(config->save_encoder_crtcs[count++]);
11295 }
11296
11297 count = 0;
11298 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11299 connector->new_encoder =
11300 to_intel_encoder(config->save_connector_encoders[count++]);
11301 }
11302 }
11303
11304 static bool
11305 is_crtc_connector_off(struct drm_mode_set *set)
11306 {
11307 int i;
11308
11309 if (set->num_connectors == 0)
11310 return false;
11311
11312 if (WARN_ON(set->connectors == NULL))
11313 return false;
11314
11315 for (i = 0; i < set->num_connectors; i++)
11316 if (set->connectors[i]->encoder &&
11317 set->connectors[i]->encoder->crtc == set->crtc &&
11318 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11319 return true;
11320
11321 return false;
11322 }
11323
11324 static void
11325 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11326 struct intel_set_config *config)
11327 {
11328
11329 /* We should be able to check here if the fb has the same properties
11330 * and then just flip_or_move it */
11331 if (is_crtc_connector_off(set)) {
11332 config->mode_changed = true;
11333 } else if (set->crtc->primary->fb != set->fb) {
11334 /*
11335 * If we have no fb, we can only flip as long as the crtc is
11336 * active, otherwise we need a full mode set. The crtc may
11337 * be active if we've only disabled the primary plane, or
11338 * in fastboot situations.
11339 */
11340 if (set->crtc->primary->fb == NULL) {
11341 struct intel_crtc *intel_crtc =
11342 to_intel_crtc(set->crtc);
11343
11344 if (intel_crtc->active) {
11345 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11346 config->fb_changed = true;
11347 } else {
11348 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11349 config->mode_changed = true;
11350 }
11351 } else if (set->fb == NULL) {
11352 config->mode_changed = true;
11353 } else if (set->fb->pixel_format !=
11354 set->crtc->primary->fb->pixel_format) {
11355 config->mode_changed = true;
11356 } else {
11357 config->fb_changed = true;
11358 }
11359 }
11360
11361 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11362 config->fb_changed = true;
11363
11364 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11365 DRM_DEBUG_KMS("modes are different, full mode set\n");
11366 drm_mode_debug_printmodeline(&set->crtc->mode);
11367 drm_mode_debug_printmodeline(set->mode);
11368 config->mode_changed = true;
11369 }
11370
11371 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11372 set->crtc->base.id, config->mode_changed, config->fb_changed);
11373 }
11374
11375 static int
11376 intel_modeset_stage_output_state(struct drm_device *dev,
11377 struct drm_mode_set *set,
11378 struct intel_set_config *config)
11379 {
11380 struct intel_connector *connector;
11381 struct intel_encoder *encoder;
11382 struct intel_crtc *crtc;
11383 int ro;
11384
11385 /* The upper layers ensure that we either disable a crtc or have a list
11386 * of connectors. For paranoia, double-check this. */
11387 WARN_ON(!set->fb && (set->num_connectors != 0));
11388 WARN_ON(set->fb && (set->num_connectors == 0));
11389
11390 list_for_each_entry(connector, &dev->mode_config.connector_list,
11391 base.head) {
11392 /* Otherwise traverse passed in connector list and get encoders
11393 * for them. */
11394 for (ro = 0; ro < set->num_connectors; ro++) {
11395 if (set->connectors[ro] == &connector->base) {
11396 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11397 break;
11398 }
11399 }
11400
11401 /* If we disable the crtc, disable all its connectors. Also, if
11402 * the connector is on the changing crtc but not on the new
11403 * connector list, disable it. */
11404 if ((!set->fb || ro == set->num_connectors) &&
11405 connector->base.encoder &&
11406 connector->base.encoder->crtc == set->crtc) {
11407 connector->new_encoder = NULL;
11408
11409 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11410 connector->base.base.id,
11411 connector->base.name);
11412 }
11413
11414
11415 if (&connector->new_encoder->base != connector->base.encoder) {
11416 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11417 config->mode_changed = true;
11418 }
11419 }
11420 /* connector->new_encoder is now updated for all connectors. */
11421
11422 /* Update crtc of enabled connectors. */
11423 list_for_each_entry(connector, &dev->mode_config.connector_list,
11424 base.head) {
11425 struct drm_crtc *new_crtc;
11426
11427 if (!connector->new_encoder)
11428 continue;
11429
11430 new_crtc = connector->new_encoder->base.crtc;
11431
11432 for (ro = 0; ro < set->num_connectors; ro++) {
11433 if (set->connectors[ro] == &connector->base)
11434 new_crtc = set->crtc;
11435 }
11436
11437 /* Make sure the new CRTC will work with the encoder */
11438 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11439 new_crtc)) {
11440 return -EINVAL;
11441 }
11442 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11443
11444 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11445 connector->base.base.id,
11446 connector->base.name,
11447 new_crtc->base.id);
11448 }
11449
11450 /* Check for any encoders that needs to be disabled. */
11451 for_each_intel_encoder(dev, encoder) {
11452 int num_connectors = 0;
11453 list_for_each_entry(connector,
11454 &dev->mode_config.connector_list,
11455 base.head) {
11456 if (connector->new_encoder == encoder) {
11457 WARN_ON(!connector->new_encoder->new_crtc);
11458 num_connectors++;
11459 }
11460 }
11461
11462 if (num_connectors == 0)
11463 encoder->new_crtc = NULL;
11464 else if (num_connectors > 1)
11465 return -EINVAL;
11466
11467 /* Only now check for crtc changes so we don't miss encoders
11468 * that will be disabled. */
11469 if (&encoder->new_crtc->base != encoder->base.crtc) {
11470 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11471 config->mode_changed = true;
11472 }
11473 }
11474 /* Now we've also updated encoder->new_crtc for all encoders. */
11475 list_for_each_entry(connector, &dev->mode_config.connector_list,
11476 base.head) {
11477 if (connector->new_encoder)
11478 if (connector->new_encoder != connector->encoder)
11479 connector->encoder = connector->new_encoder;
11480 }
11481 for_each_intel_crtc(dev, crtc) {
11482 crtc->new_enabled = false;
11483
11484 for_each_intel_encoder(dev, encoder) {
11485 if (encoder->new_crtc == crtc) {
11486 crtc->new_enabled = true;
11487 break;
11488 }
11489 }
11490
11491 if (crtc->new_enabled != crtc->base.enabled) {
11492 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11493 crtc->new_enabled ? "en" : "dis");
11494 config->mode_changed = true;
11495 }
11496
11497 if (crtc->new_enabled)
11498 crtc->new_config = crtc->config;
11499 else
11500 crtc->new_config = NULL;
11501 }
11502
11503 return 0;
11504 }
11505
11506 static void disable_crtc_nofb(struct intel_crtc *crtc)
11507 {
11508 struct drm_device *dev = crtc->base.dev;
11509 struct intel_encoder *encoder;
11510 struct intel_connector *connector;
11511
11512 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11513 pipe_name(crtc->pipe));
11514
11515 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11516 if (connector->new_encoder &&
11517 connector->new_encoder->new_crtc == crtc)
11518 connector->new_encoder = NULL;
11519 }
11520
11521 for_each_intel_encoder(dev, encoder) {
11522 if (encoder->new_crtc == crtc)
11523 encoder->new_crtc = NULL;
11524 }
11525
11526 crtc->new_enabled = false;
11527 crtc->new_config = NULL;
11528 }
11529
11530 static int intel_crtc_set_config(struct drm_mode_set *set)
11531 {
11532 struct drm_device *dev;
11533 struct drm_mode_set save_set;
11534 struct intel_set_config *config;
11535 struct intel_crtc_state *pipe_config;
11536 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11537 int ret;
11538
11539 BUG_ON(!set);
11540 BUG_ON(!set->crtc);
11541 BUG_ON(!set->crtc->helper_private);
11542
11543 /* Enforce sane interface api - has been abused by the fb helper. */
11544 BUG_ON(!set->mode && set->fb);
11545 BUG_ON(set->fb && set->num_connectors == 0);
11546
11547 if (set->fb) {
11548 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11549 set->crtc->base.id, set->fb->base.id,
11550 (int)set->num_connectors, set->x, set->y);
11551 } else {
11552 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11553 }
11554
11555 dev = set->crtc->dev;
11556
11557 ret = -ENOMEM;
11558 config = kzalloc(sizeof(*config), GFP_KERNEL);
11559 if (!config)
11560 goto out_config;
11561
11562 ret = intel_set_config_save_state(dev, config);
11563 if (ret)
11564 goto out_config;
11565
11566 save_set.crtc = set->crtc;
11567 save_set.mode = &set->crtc->mode;
11568 save_set.x = set->crtc->x;
11569 save_set.y = set->crtc->y;
11570 save_set.fb = set->crtc->primary->fb;
11571
11572 /* Compute whether we need a full modeset, only an fb base update or no
11573 * change at all. In the future we might also check whether only the
11574 * mode changed, e.g. for LVDS where we only change the panel fitter in
11575 * such cases. */
11576 intel_set_config_compute_mode_changes(set, config);
11577
11578 ret = intel_modeset_stage_output_state(dev, set, config);
11579 if (ret)
11580 goto fail;
11581
11582 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11583 set->fb,
11584 &modeset_pipes,
11585 &prepare_pipes,
11586 &disable_pipes);
11587 if (IS_ERR(pipe_config)) {
11588 ret = PTR_ERR(pipe_config);
11589 goto fail;
11590 } else if (pipe_config) {
11591 if (pipe_config->has_audio !=
11592 to_intel_crtc(set->crtc)->config->has_audio)
11593 config->mode_changed = true;
11594
11595 /*
11596 * Note we have an issue here with infoframes: current code
11597 * only updates them on the full mode set path per hw
11598 * requirements. So here we should be checking for any
11599 * required changes and forcing a mode set.
11600 */
11601 }
11602
11603 /* set_mode will free it in the mode_changed case */
11604 if (!config->mode_changed)
11605 kfree(pipe_config);
11606
11607 intel_update_pipe_size(to_intel_crtc(set->crtc));
11608
11609 if (config->mode_changed) {
11610 ret = intel_set_mode_pipes(set->crtc, set->mode,
11611 set->x, set->y, set->fb, pipe_config,
11612 modeset_pipes, prepare_pipes,
11613 disable_pipes);
11614 } else if (config->fb_changed) {
11615 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11616 struct drm_plane *primary = set->crtc->primary;
11617 int vdisplay, hdisplay;
11618
11619 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11620 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11621 0, 0, hdisplay, vdisplay,
11622 set->x << 16, set->y << 16,
11623 hdisplay << 16, vdisplay << 16);
11624
11625 /*
11626 * We need to make sure the primary plane is re-enabled if it
11627 * has previously been turned off.
11628 */
11629 if (!intel_crtc->primary_enabled && ret == 0) {
11630 WARN_ON(!intel_crtc->active);
11631 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11632 }
11633
11634 /*
11635 * In the fastboot case this may be our only check of the
11636 * state after boot. It would be better to only do it on
11637 * the first update, but we don't have a nice way of doing that
11638 * (and really, set_config isn't used much for high freq page
11639 * flipping, so increasing its cost here shouldn't be a big
11640 * deal).
11641 */
11642 if (i915.fastboot && ret == 0)
11643 intel_modeset_check_state(set->crtc->dev);
11644 }
11645
11646 if (ret) {
11647 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11648 set->crtc->base.id, ret);
11649 fail:
11650 intel_set_config_restore_state(dev, config);
11651
11652 /*
11653 * HACK: if the pipe was on, but we didn't have a framebuffer,
11654 * force the pipe off to avoid oopsing in the modeset code
11655 * due to fb==NULL. This should only happen during boot since
11656 * we don't yet reconstruct the FB from the hardware state.
11657 */
11658 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11659 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11660
11661 /* Try to restore the config */
11662 if (config->mode_changed &&
11663 intel_set_mode(save_set.crtc, save_set.mode,
11664 save_set.x, save_set.y, save_set.fb))
11665 DRM_ERROR("failed to restore config after modeset failure\n");
11666 }
11667
11668 out_config:
11669 intel_set_config_free(config);
11670 return ret;
11671 }
11672
11673 static const struct drm_crtc_funcs intel_crtc_funcs = {
11674 .gamma_set = intel_crtc_gamma_set,
11675 .set_config = intel_crtc_set_config,
11676 .destroy = intel_crtc_destroy,
11677 .page_flip = intel_crtc_page_flip,
11678 .atomic_duplicate_state = intel_crtc_duplicate_state,
11679 .atomic_destroy_state = intel_crtc_destroy_state,
11680 };
11681
11682 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11683 struct intel_shared_dpll *pll,
11684 struct intel_dpll_hw_state *hw_state)
11685 {
11686 uint32_t val;
11687
11688 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11689 return false;
11690
11691 val = I915_READ(PCH_DPLL(pll->id));
11692 hw_state->dpll = val;
11693 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11694 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11695
11696 return val & DPLL_VCO_ENABLE;
11697 }
11698
11699 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11700 struct intel_shared_dpll *pll)
11701 {
11702 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11703 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11704 }
11705
11706 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11707 struct intel_shared_dpll *pll)
11708 {
11709 /* PCH refclock must be enabled first */
11710 ibx_assert_pch_refclk_enabled(dev_priv);
11711
11712 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11713
11714 /* Wait for the clocks to stabilize. */
11715 POSTING_READ(PCH_DPLL(pll->id));
11716 udelay(150);
11717
11718 /* The pixel multiplier can only be updated once the
11719 * DPLL is enabled and the clocks are stable.
11720 *
11721 * So write it again.
11722 */
11723 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11724 POSTING_READ(PCH_DPLL(pll->id));
11725 udelay(200);
11726 }
11727
11728 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11729 struct intel_shared_dpll *pll)
11730 {
11731 struct drm_device *dev = dev_priv->dev;
11732 struct intel_crtc *crtc;
11733
11734 /* Make sure no transcoder isn't still depending on us. */
11735 for_each_intel_crtc(dev, crtc) {
11736 if (intel_crtc_to_shared_dpll(crtc) == pll)
11737 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11738 }
11739
11740 I915_WRITE(PCH_DPLL(pll->id), 0);
11741 POSTING_READ(PCH_DPLL(pll->id));
11742 udelay(200);
11743 }
11744
11745 static char *ibx_pch_dpll_names[] = {
11746 "PCH DPLL A",
11747 "PCH DPLL B",
11748 };
11749
11750 static void ibx_pch_dpll_init(struct drm_device *dev)
11751 {
11752 struct drm_i915_private *dev_priv = dev->dev_private;
11753 int i;
11754
11755 dev_priv->num_shared_dpll = 2;
11756
11757 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11758 dev_priv->shared_dplls[i].id = i;
11759 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11760 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11761 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11762 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11763 dev_priv->shared_dplls[i].get_hw_state =
11764 ibx_pch_dpll_get_hw_state;
11765 }
11766 }
11767
11768 static void intel_shared_dpll_init(struct drm_device *dev)
11769 {
11770 struct drm_i915_private *dev_priv = dev->dev_private;
11771
11772 if (HAS_DDI(dev))
11773 intel_ddi_pll_init(dev);
11774 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11775 ibx_pch_dpll_init(dev);
11776 else
11777 dev_priv->num_shared_dpll = 0;
11778
11779 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11780 }
11781
11782 /**
11783 * intel_prepare_plane_fb - Prepare fb for usage on plane
11784 * @plane: drm plane to prepare for
11785 * @fb: framebuffer to prepare for presentation
11786 *
11787 * Prepares a framebuffer for usage on a display plane. Generally this
11788 * involves pinning the underlying object and updating the frontbuffer tracking
11789 * bits. Some older platforms need special physical address handling for
11790 * cursor planes.
11791 *
11792 * Returns 0 on success, negative error code on failure.
11793 */
11794 int
11795 intel_prepare_plane_fb(struct drm_plane *plane,
11796 struct drm_framebuffer *fb)
11797 {
11798 struct drm_device *dev = plane->dev;
11799 struct intel_plane *intel_plane = to_intel_plane(plane);
11800 enum pipe pipe = intel_plane->pipe;
11801 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11802 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11803 unsigned frontbuffer_bits = 0;
11804 int ret = 0;
11805
11806 if (!obj)
11807 return 0;
11808
11809 switch (plane->type) {
11810 case DRM_PLANE_TYPE_PRIMARY:
11811 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11812 break;
11813 case DRM_PLANE_TYPE_CURSOR:
11814 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11815 break;
11816 case DRM_PLANE_TYPE_OVERLAY:
11817 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11818 break;
11819 }
11820
11821 mutex_lock(&dev->struct_mutex);
11822
11823 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11824 INTEL_INFO(dev)->cursor_needs_physical) {
11825 int align = IS_I830(dev) ? 16 * 1024 : 256;
11826 ret = i915_gem_object_attach_phys(obj, align);
11827 if (ret)
11828 DRM_DEBUG_KMS("failed to attach phys object\n");
11829 } else {
11830 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11831 }
11832
11833 if (ret == 0)
11834 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11835
11836 mutex_unlock(&dev->struct_mutex);
11837
11838 return ret;
11839 }
11840
11841 /**
11842 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11843 * @plane: drm plane to clean up for
11844 * @fb: old framebuffer that was on plane
11845 *
11846 * Cleans up a framebuffer that has just been removed from a plane.
11847 */
11848 void
11849 intel_cleanup_plane_fb(struct drm_plane *plane,
11850 struct drm_framebuffer *fb)
11851 {
11852 struct drm_device *dev = plane->dev;
11853 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11854
11855 if (WARN_ON(!obj))
11856 return;
11857
11858 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11859 !INTEL_INFO(dev)->cursor_needs_physical) {
11860 mutex_lock(&dev->struct_mutex);
11861 intel_unpin_fb_obj(obj);
11862 mutex_unlock(&dev->struct_mutex);
11863 }
11864 }
11865
11866 static int
11867 intel_check_primary_plane(struct drm_plane *plane,
11868 struct intel_plane_state *state)
11869 {
11870 struct drm_device *dev = plane->dev;
11871 struct drm_i915_private *dev_priv = dev->dev_private;
11872 struct drm_crtc *crtc = state->base.crtc;
11873 struct intel_crtc *intel_crtc;
11874 struct drm_framebuffer *fb = state->base.fb;
11875 struct drm_rect *dest = &state->dst;
11876 struct drm_rect *src = &state->src;
11877 const struct drm_rect *clip = &state->clip;
11878 int ret;
11879
11880 crtc = crtc ? crtc : plane->crtc;
11881 intel_crtc = to_intel_crtc(crtc);
11882
11883 ret = drm_plane_helper_check_update(plane, crtc, fb,
11884 src, dest, clip,
11885 DRM_PLANE_HELPER_NO_SCALING,
11886 DRM_PLANE_HELPER_NO_SCALING,
11887 false, true, &state->visible);
11888 if (ret)
11889 return ret;
11890
11891 if (intel_crtc->active) {
11892 intel_crtc->atomic.wait_for_flips = true;
11893
11894 /*
11895 * FBC does not work on some platforms for rotated
11896 * planes, so disable it when rotation is not 0 and
11897 * update it when rotation is set back to 0.
11898 *
11899 * FIXME: This is redundant with the fbc update done in
11900 * the primary plane enable function except that that
11901 * one is done too late. We eventually need to unify
11902 * this.
11903 */
11904 if (intel_crtc->primary_enabled &&
11905 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11906 dev_priv->fbc.crtc == intel_crtc &&
11907 state->base.rotation != BIT(DRM_ROTATE_0)) {
11908 intel_crtc->atomic.disable_fbc = true;
11909 }
11910
11911 if (state->visible) {
11912 /*
11913 * BDW signals flip done immediately if the plane
11914 * is disabled, even if the plane enable is already
11915 * armed to occur at the next vblank :(
11916 */
11917 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11918 intel_crtc->atomic.wait_vblank = true;
11919 }
11920
11921 intel_crtc->atomic.fb_bits |=
11922 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11923
11924 intel_crtc->atomic.update_fbc = true;
11925 }
11926
11927 return 0;
11928 }
11929
11930 static void
11931 intel_commit_primary_plane(struct drm_plane *plane,
11932 struct intel_plane_state *state)
11933 {
11934 struct drm_crtc *crtc = state->base.crtc;
11935 struct drm_framebuffer *fb = state->base.fb;
11936 struct drm_device *dev = plane->dev;
11937 struct drm_i915_private *dev_priv = dev->dev_private;
11938 struct intel_crtc *intel_crtc;
11939 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11940 struct intel_plane *intel_plane = to_intel_plane(plane);
11941 struct drm_rect *src = &state->src;
11942
11943 crtc = crtc ? crtc : plane->crtc;
11944 intel_crtc = to_intel_crtc(crtc);
11945
11946 plane->fb = fb;
11947 crtc->x = src->x1 >> 16;
11948 crtc->y = src->y1 >> 16;
11949
11950 intel_plane->obj = obj;
11951
11952 if (intel_crtc->active) {
11953 if (state->visible) {
11954 /* FIXME: kill this fastboot hack */
11955 intel_update_pipe_size(intel_crtc);
11956
11957 intel_crtc->primary_enabled = true;
11958
11959 dev_priv->display.update_primary_plane(crtc, plane->fb,
11960 crtc->x, crtc->y);
11961 } else {
11962 /*
11963 * If clipping results in a non-visible primary plane,
11964 * we'll disable the primary plane. Note that this is
11965 * a bit different than what happens if userspace
11966 * explicitly disables the plane by passing fb=0
11967 * because plane->fb still gets set and pinned.
11968 */
11969 intel_disable_primary_hw_plane(plane, crtc);
11970 }
11971 }
11972 }
11973
11974 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11975 {
11976 struct drm_device *dev = crtc->dev;
11977 struct drm_i915_private *dev_priv = dev->dev_private;
11978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11979 struct intel_plane *intel_plane;
11980 struct drm_plane *p;
11981 unsigned fb_bits = 0;
11982
11983 /* Track fb's for any planes being disabled */
11984 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11985 intel_plane = to_intel_plane(p);
11986
11987 if (intel_crtc->atomic.disabled_planes &
11988 (1 << drm_plane_index(p))) {
11989 switch (p->type) {
11990 case DRM_PLANE_TYPE_PRIMARY:
11991 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11992 break;
11993 case DRM_PLANE_TYPE_CURSOR:
11994 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11995 break;
11996 case DRM_PLANE_TYPE_OVERLAY:
11997 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11998 break;
11999 }
12000
12001 mutex_lock(&dev->struct_mutex);
12002 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12003 mutex_unlock(&dev->struct_mutex);
12004 }
12005 }
12006
12007 if (intel_crtc->atomic.wait_for_flips)
12008 intel_crtc_wait_for_pending_flips(crtc);
12009
12010 if (intel_crtc->atomic.disable_fbc)
12011 intel_fbc_disable(dev);
12012
12013 if (intel_crtc->atomic.pre_disable_primary)
12014 intel_pre_disable_primary(crtc);
12015
12016 if (intel_crtc->atomic.update_wm)
12017 intel_update_watermarks(crtc);
12018
12019 intel_runtime_pm_get(dev_priv);
12020
12021 /* Perform vblank evasion around commit operation */
12022 if (intel_crtc->active)
12023 intel_crtc->atomic.evade =
12024 intel_pipe_update_start(intel_crtc,
12025 &intel_crtc->atomic.start_vbl_count);
12026 }
12027
12028 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12029 {
12030 struct drm_device *dev = crtc->dev;
12031 struct drm_i915_private *dev_priv = dev->dev_private;
12032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12033 struct drm_plane *p;
12034
12035 if (intel_crtc->atomic.evade)
12036 intel_pipe_update_end(intel_crtc,
12037 intel_crtc->atomic.start_vbl_count);
12038
12039 intel_runtime_pm_put(dev_priv);
12040
12041 if (intel_crtc->atomic.wait_vblank)
12042 intel_wait_for_vblank(dev, intel_crtc->pipe);
12043
12044 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12045
12046 if (intel_crtc->atomic.update_fbc) {
12047 mutex_lock(&dev->struct_mutex);
12048 intel_fbc_update(dev);
12049 mutex_unlock(&dev->struct_mutex);
12050 }
12051
12052 if (intel_crtc->atomic.post_enable_primary)
12053 intel_post_enable_primary(crtc);
12054
12055 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12056 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12057 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12058 false, false);
12059
12060 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12061 }
12062
12063 /**
12064 * intel_plane_destroy - destroy a plane
12065 * @plane: plane to destroy
12066 *
12067 * Common destruction function for all types of planes (primary, cursor,
12068 * sprite).
12069 */
12070 void intel_plane_destroy(struct drm_plane *plane)
12071 {
12072 struct intel_plane *intel_plane = to_intel_plane(plane);
12073 drm_plane_cleanup(plane);
12074 kfree(intel_plane);
12075 }
12076
12077 const struct drm_plane_funcs intel_plane_funcs = {
12078 .update_plane = drm_atomic_helper_update_plane,
12079 .disable_plane = drm_atomic_helper_disable_plane,
12080 .destroy = intel_plane_destroy,
12081 .set_property = drm_atomic_helper_plane_set_property,
12082 .atomic_get_property = intel_plane_atomic_get_property,
12083 .atomic_set_property = intel_plane_atomic_set_property,
12084 .atomic_duplicate_state = intel_plane_duplicate_state,
12085 .atomic_destroy_state = intel_plane_destroy_state,
12086
12087 };
12088
12089 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12090 int pipe)
12091 {
12092 struct intel_plane *primary;
12093 struct intel_plane_state *state;
12094 const uint32_t *intel_primary_formats;
12095 int num_formats;
12096
12097 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12098 if (primary == NULL)
12099 return NULL;
12100
12101 state = intel_create_plane_state(&primary->base);
12102 if (!state) {
12103 kfree(primary);
12104 return NULL;
12105 }
12106 primary->base.state = &state->base;
12107
12108 primary->can_scale = false;
12109 primary->max_downscale = 1;
12110 primary->pipe = pipe;
12111 primary->plane = pipe;
12112 primary->check_plane = intel_check_primary_plane;
12113 primary->commit_plane = intel_commit_primary_plane;
12114 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12115 primary->plane = !pipe;
12116
12117 if (INTEL_INFO(dev)->gen <= 3) {
12118 intel_primary_formats = intel_primary_formats_gen2;
12119 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12120 } else {
12121 intel_primary_formats = intel_primary_formats_gen4;
12122 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12123 }
12124
12125 drm_universal_plane_init(dev, &primary->base, 0,
12126 &intel_plane_funcs,
12127 intel_primary_formats, num_formats,
12128 DRM_PLANE_TYPE_PRIMARY);
12129
12130 if (INTEL_INFO(dev)->gen >= 4) {
12131 if (!dev->mode_config.rotation_property)
12132 dev->mode_config.rotation_property =
12133 drm_mode_create_rotation_property(dev,
12134 BIT(DRM_ROTATE_0) |
12135 BIT(DRM_ROTATE_180));
12136 if (dev->mode_config.rotation_property)
12137 drm_object_attach_property(&primary->base.base,
12138 dev->mode_config.rotation_property,
12139 state->base.rotation);
12140 }
12141
12142 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12143
12144 return &primary->base;
12145 }
12146
12147 static int
12148 intel_check_cursor_plane(struct drm_plane *plane,
12149 struct intel_plane_state *state)
12150 {
12151 struct drm_crtc *crtc = state->base.crtc;
12152 struct drm_device *dev = plane->dev;
12153 struct drm_framebuffer *fb = state->base.fb;
12154 struct drm_rect *dest = &state->dst;
12155 struct drm_rect *src = &state->src;
12156 const struct drm_rect *clip = &state->clip;
12157 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12158 struct intel_crtc *intel_crtc;
12159 unsigned stride;
12160 int ret;
12161
12162 crtc = crtc ? crtc : plane->crtc;
12163 intel_crtc = to_intel_crtc(crtc);
12164
12165 ret = drm_plane_helper_check_update(plane, crtc, fb,
12166 src, dest, clip,
12167 DRM_PLANE_HELPER_NO_SCALING,
12168 DRM_PLANE_HELPER_NO_SCALING,
12169 true, true, &state->visible);
12170 if (ret)
12171 return ret;
12172
12173
12174 /* if we want to turn off the cursor ignore width and height */
12175 if (!obj)
12176 goto finish;
12177
12178 /* Check for which cursor types we support */
12179 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12180 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12181 state->base.crtc_w, state->base.crtc_h);
12182 return -EINVAL;
12183 }
12184
12185 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12186 if (obj->base.size < stride * state->base.crtc_h) {
12187 DRM_DEBUG_KMS("buffer is too small\n");
12188 return -ENOMEM;
12189 }
12190
12191 if (fb == crtc->cursor->fb)
12192 return 0;
12193
12194 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12195 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12196 ret = -EINVAL;
12197 }
12198
12199 finish:
12200 if (intel_crtc->active) {
12201 if (intel_crtc->cursor_width != state->base.crtc_w)
12202 intel_crtc->atomic.update_wm = true;
12203
12204 intel_crtc->atomic.fb_bits |=
12205 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12206 }
12207
12208 return ret;
12209 }
12210
12211 static void
12212 intel_commit_cursor_plane(struct drm_plane *plane,
12213 struct intel_plane_state *state)
12214 {
12215 struct drm_crtc *crtc = state->base.crtc;
12216 struct drm_device *dev = plane->dev;
12217 struct intel_crtc *intel_crtc;
12218 struct intel_plane *intel_plane = to_intel_plane(plane);
12219 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12220 uint32_t addr;
12221
12222 crtc = crtc ? crtc : plane->crtc;
12223 intel_crtc = to_intel_crtc(crtc);
12224
12225 plane->fb = state->base.fb;
12226 crtc->cursor_x = state->base.crtc_x;
12227 crtc->cursor_y = state->base.crtc_y;
12228
12229 intel_plane->obj = obj;
12230
12231 if (intel_crtc->cursor_bo == obj)
12232 goto update;
12233
12234 if (!obj)
12235 addr = 0;
12236 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12237 addr = i915_gem_obj_ggtt_offset(obj);
12238 else
12239 addr = obj->phys_handle->busaddr;
12240
12241 intel_crtc->cursor_addr = addr;
12242 intel_crtc->cursor_bo = obj;
12243 update:
12244 intel_crtc->cursor_width = state->base.crtc_w;
12245 intel_crtc->cursor_height = state->base.crtc_h;
12246
12247 if (intel_crtc->active)
12248 intel_crtc_update_cursor(crtc, state->visible);
12249 }
12250
12251 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12252 int pipe)
12253 {
12254 struct intel_plane *cursor;
12255 struct intel_plane_state *state;
12256
12257 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12258 if (cursor == NULL)
12259 return NULL;
12260
12261 state = intel_create_plane_state(&cursor->base);
12262 if (!state) {
12263 kfree(cursor);
12264 return NULL;
12265 }
12266 cursor->base.state = &state->base;
12267
12268 cursor->can_scale = false;
12269 cursor->max_downscale = 1;
12270 cursor->pipe = pipe;
12271 cursor->plane = pipe;
12272 cursor->check_plane = intel_check_cursor_plane;
12273 cursor->commit_plane = intel_commit_cursor_plane;
12274
12275 drm_universal_plane_init(dev, &cursor->base, 0,
12276 &intel_plane_funcs,
12277 intel_cursor_formats,
12278 ARRAY_SIZE(intel_cursor_formats),
12279 DRM_PLANE_TYPE_CURSOR);
12280
12281 if (INTEL_INFO(dev)->gen >= 4) {
12282 if (!dev->mode_config.rotation_property)
12283 dev->mode_config.rotation_property =
12284 drm_mode_create_rotation_property(dev,
12285 BIT(DRM_ROTATE_0) |
12286 BIT(DRM_ROTATE_180));
12287 if (dev->mode_config.rotation_property)
12288 drm_object_attach_property(&cursor->base.base,
12289 dev->mode_config.rotation_property,
12290 state->base.rotation);
12291 }
12292
12293 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12294
12295 return &cursor->base;
12296 }
12297
12298 static void intel_crtc_init(struct drm_device *dev, int pipe)
12299 {
12300 struct drm_i915_private *dev_priv = dev->dev_private;
12301 struct intel_crtc *intel_crtc;
12302 struct intel_crtc_state *crtc_state = NULL;
12303 struct drm_plane *primary = NULL;
12304 struct drm_plane *cursor = NULL;
12305 int i, ret;
12306
12307 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12308 if (intel_crtc == NULL)
12309 return;
12310
12311 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12312 if (!crtc_state)
12313 goto fail;
12314 intel_crtc_set_state(intel_crtc, crtc_state);
12315
12316 primary = intel_primary_plane_create(dev, pipe);
12317 if (!primary)
12318 goto fail;
12319
12320 cursor = intel_cursor_plane_create(dev, pipe);
12321 if (!cursor)
12322 goto fail;
12323
12324 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12325 cursor, &intel_crtc_funcs);
12326 if (ret)
12327 goto fail;
12328
12329 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12330 for (i = 0; i < 256; i++) {
12331 intel_crtc->lut_r[i] = i;
12332 intel_crtc->lut_g[i] = i;
12333 intel_crtc->lut_b[i] = i;
12334 }
12335
12336 /*
12337 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12338 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12339 */
12340 intel_crtc->pipe = pipe;
12341 intel_crtc->plane = pipe;
12342 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12343 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12344 intel_crtc->plane = !pipe;
12345 }
12346
12347 intel_crtc->cursor_base = ~0;
12348 intel_crtc->cursor_cntl = ~0;
12349 intel_crtc->cursor_size = ~0;
12350
12351 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12352 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12353 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12354 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12355
12356 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12357
12358 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12359
12360 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12361 return;
12362
12363 fail:
12364 if (primary)
12365 drm_plane_cleanup(primary);
12366 if (cursor)
12367 drm_plane_cleanup(cursor);
12368 kfree(crtc_state);
12369 kfree(intel_crtc);
12370 }
12371
12372 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12373 {
12374 struct drm_encoder *encoder = connector->base.encoder;
12375 struct drm_device *dev = connector->base.dev;
12376
12377 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12378
12379 if (!encoder || WARN_ON(!encoder->crtc))
12380 return INVALID_PIPE;
12381
12382 return to_intel_crtc(encoder->crtc)->pipe;
12383 }
12384
12385 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12386 struct drm_file *file)
12387 {
12388 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12389 struct drm_crtc *drmmode_crtc;
12390 struct intel_crtc *crtc;
12391
12392 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12393 return -ENODEV;
12394
12395 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12396
12397 if (!drmmode_crtc) {
12398 DRM_ERROR("no such CRTC id\n");
12399 return -ENOENT;
12400 }
12401
12402 crtc = to_intel_crtc(drmmode_crtc);
12403 pipe_from_crtc_id->pipe = crtc->pipe;
12404
12405 return 0;
12406 }
12407
12408 static int intel_encoder_clones(struct intel_encoder *encoder)
12409 {
12410 struct drm_device *dev = encoder->base.dev;
12411 struct intel_encoder *source_encoder;
12412 int index_mask = 0;
12413 int entry = 0;
12414
12415 for_each_intel_encoder(dev, source_encoder) {
12416 if (encoders_cloneable(encoder, source_encoder))
12417 index_mask |= (1 << entry);
12418
12419 entry++;
12420 }
12421
12422 return index_mask;
12423 }
12424
12425 static bool has_edp_a(struct drm_device *dev)
12426 {
12427 struct drm_i915_private *dev_priv = dev->dev_private;
12428
12429 if (!IS_MOBILE(dev))
12430 return false;
12431
12432 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12433 return false;
12434
12435 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12436 return false;
12437
12438 return true;
12439 }
12440
12441 static bool intel_crt_present(struct drm_device *dev)
12442 {
12443 struct drm_i915_private *dev_priv = dev->dev_private;
12444
12445 if (INTEL_INFO(dev)->gen >= 9)
12446 return false;
12447
12448 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12449 return false;
12450
12451 if (IS_CHERRYVIEW(dev))
12452 return false;
12453
12454 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12455 return false;
12456
12457 return true;
12458 }
12459
12460 static void intel_setup_outputs(struct drm_device *dev)
12461 {
12462 struct drm_i915_private *dev_priv = dev->dev_private;
12463 struct intel_encoder *encoder;
12464 struct drm_connector *connector;
12465 bool dpd_is_edp = false;
12466
12467 intel_lvds_init(dev);
12468
12469 if (intel_crt_present(dev))
12470 intel_crt_init(dev);
12471
12472 if (HAS_DDI(dev)) {
12473 int found;
12474
12475 /* Haswell uses DDI functions to detect digital outputs */
12476 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12477 /* DDI A only supports eDP */
12478 if (found)
12479 intel_ddi_init(dev, PORT_A);
12480
12481 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12482 * register */
12483 found = I915_READ(SFUSE_STRAP);
12484
12485 if (found & SFUSE_STRAP_DDIB_DETECTED)
12486 intel_ddi_init(dev, PORT_B);
12487 if (found & SFUSE_STRAP_DDIC_DETECTED)
12488 intel_ddi_init(dev, PORT_C);
12489 if (found & SFUSE_STRAP_DDID_DETECTED)
12490 intel_ddi_init(dev, PORT_D);
12491 } else if (HAS_PCH_SPLIT(dev)) {
12492 int found;
12493 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12494
12495 if (has_edp_a(dev))
12496 intel_dp_init(dev, DP_A, PORT_A);
12497
12498 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12499 /* PCH SDVOB multiplex with HDMIB */
12500 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12501 if (!found)
12502 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12503 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12504 intel_dp_init(dev, PCH_DP_B, PORT_B);
12505 }
12506
12507 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12508 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12509
12510 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12511 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12512
12513 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12514 intel_dp_init(dev, PCH_DP_C, PORT_C);
12515
12516 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12517 intel_dp_init(dev, PCH_DP_D, PORT_D);
12518 } else if (IS_VALLEYVIEW(dev)) {
12519 /*
12520 * The DP_DETECTED bit is the latched state of the DDC
12521 * SDA pin at boot. However since eDP doesn't require DDC
12522 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12523 * eDP ports may have been muxed to an alternate function.
12524 * Thus we can't rely on the DP_DETECTED bit alone to detect
12525 * eDP ports. Consult the VBT as well as DP_DETECTED to
12526 * detect eDP ports.
12527 */
12528 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12529 !intel_dp_is_edp(dev, PORT_B))
12530 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12531 PORT_B);
12532 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12533 intel_dp_is_edp(dev, PORT_B))
12534 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12535
12536 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12537 !intel_dp_is_edp(dev, PORT_C))
12538 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12539 PORT_C);
12540 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12541 intel_dp_is_edp(dev, PORT_C))
12542 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12543
12544 if (IS_CHERRYVIEW(dev)) {
12545 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12546 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12547 PORT_D);
12548 /* eDP not supported on port D, so don't check VBT */
12549 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12550 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12551 }
12552
12553 intel_dsi_init(dev);
12554 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12555 bool found = false;
12556
12557 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12558 DRM_DEBUG_KMS("probing SDVOB\n");
12559 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12560 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12561 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12562 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12563 }
12564
12565 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12566 intel_dp_init(dev, DP_B, PORT_B);
12567 }
12568
12569 /* Before G4X SDVOC doesn't have its own detect register */
12570
12571 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12572 DRM_DEBUG_KMS("probing SDVOC\n");
12573 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12574 }
12575
12576 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12577
12578 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12579 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12580 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12581 }
12582 if (SUPPORTS_INTEGRATED_DP(dev))
12583 intel_dp_init(dev, DP_C, PORT_C);
12584 }
12585
12586 if (SUPPORTS_INTEGRATED_DP(dev) &&
12587 (I915_READ(DP_D) & DP_DETECTED))
12588 intel_dp_init(dev, DP_D, PORT_D);
12589 } else if (IS_GEN2(dev))
12590 intel_dvo_init(dev);
12591
12592 if (SUPPORTS_TV(dev))
12593 intel_tv_init(dev);
12594
12595 /*
12596 * FIXME: We don't have full atomic support yet, but we want to be
12597 * able to enable/test plane updates via the atomic interface in the
12598 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12599 * will take some atomic codepaths to lookup properties during
12600 * drmModeGetConnector() that unconditionally dereference
12601 * connector->state.
12602 *
12603 * We create a dummy connector state here for each connector to ensure
12604 * the DRM core doesn't try to dereference a NULL connector->state.
12605 * The actual connector properties will never be updated or contain
12606 * useful information, but since we're doing this specifically for
12607 * testing/debug of the plane operations (and only when a specific
12608 * kernel module option is given), that shouldn't really matter.
12609 *
12610 * Once atomic support for crtc's + connectors lands, this loop should
12611 * be removed since we'll be setting up real connector state, which
12612 * will contain Intel-specific properties.
12613 */
12614 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12615 list_for_each_entry(connector,
12616 &dev->mode_config.connector_list,
12617 head) {
12618 if (!WARN_ON(connector->state)) {
12619 connector->state =
12620 kzalloc(sizeof(*connector->state),
12621 GFP_KERNEL);
12622 }
12623 }
12624 }
12625
12626 intel_psr_init(dev);
12627
12628 for_each_intel_encoder(dev, encoder) {
12629 encoder->base.possible_crtcs = encoder->crtc_mask;
12630 encoder->base.possible_clones =
12631 intel_encoder_clones(encoder);
12632 }
12633
12634 intel_init_pch_refclk(dev);
12635
12636 drm_helper_move_panel_connectors_to_head(dev);
12637 }
12638
12639 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12640 {
12641 struct drm_device *dev = fb->dev;
12642 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12643
12644 drm_framebuffer_cleanup(fb);
12645 mutex_lock(&dev->struct_mutex);
12646 WARN_ON(!intel_fb->obj->framebuffer_references--);
12647 drm_gem_object_unreference(&intel_fb->obj->base);
12648 mutex_unlock(&dev->struct_mutex);
12649 kfree(intel_fb);
12650 }
12651
12652 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12653 struct drm_file *file,
12654 unsigned int *handle)
12655 {
12656 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12657 struct drm_i915_gem_object *obj = intel_fb->obj;
12658
12659 return drm_gem_handle_create(file, &obj->base, handle);
12660 }
12661
12662 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12663 .destroy = intel_user_framebuffer_destroy,
12664 .create_handle = intel_user_framebuffer_create_handle,
12665 };
12666
12667 static int intel_framebuffer_init(struct drm_device *dev,
12668 struct intel_framebuffer *intel_fb,
12669 struct drm_mode_fb_cmd2 *mode_cmd,
12670 struct drm_i915_gem_object *obj)
12671 {
12672 int aligned_height;
12673 int pitch_limit;
12674 int ret;
12675
12676 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12677
12678 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12679 /* Enforce that fb modifier and tiling mode match, but only for
12680 * X-tiled. This is needed for FBC. */
12681 if (!!(obj->tiling_mode == I915_TILING_X) !=
12682 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12683 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12684 return -EINVAL;
12685 }
12686 } else {
12687 if (obj->tiling_mode == I915_TILING_X)
12688 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12689 else if (obj->tiling_mode == I915_TILING_Y) {
12690 DRM_DEBUG("No Y tiling for legacy addfb\n");
12691 return -EINVAL;
12692 }
12693 }
12694
12695 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_Y_TILED) {
12696 DRM_DEBUG("hardware does not support tiling Y\n");
12697 return -EINVAL;
12698 }
12699
12700 if (mode_cmd->pitches[0] & 63) {
12701 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12702 mode_cmd->pitches[0]);
12703 return -EINVAL;
12704 }
12705
12706 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12707 pitch_limit = 32*1024;
12708 } else if (INTEL_INFO(dev)->gen >= 4) {
12709 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12710 pitch_limit = 16*1024;
12711 else
12712 pitch_limit = 32*1024;
12713 } else if (INTEL_INFO(dev)->gen >= 3) {
12714 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)
12715 pitch_limit = 8*1024;
12716 else
12717 pitch_limit = 16*1024;
12718 } else
12719 /* XXX DSPC is limited to 4k tiled */
12720 pitch_limit = 8*1024;
12721
12722 if (mode_cmd->pitches[0] > pitch_limit) {
12723 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12724 mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED ?
12725 "tiled" : "linear",
12726 mode_cmd->pitches[0], pitch_limit);
12727 return -EINVAL;
12728 }
12729
12730 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12731 mode_cmd->pitches[0] != obj->stride) {
12732 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12733 mode_cmd->pitches[0], obj->stride);
12734 return -EINVAL;
12735 }
12736
12737 /* Reject formats not supported by any plane early. */
12738 switch (mode_cmd->pixel_format) {
12739 case DRM_FORMAT_C8:
12740 case DRM_FORMAT_RGB565:
12741 case DRM_FORMAT_XRGB8888:
12742 case DRM_FORMAT_ARGB8888:
12743 break;
12744 case DRM_FORMAT_XRGB1555:
12745 case DRM_FORMAT_ARGB1555:
12746 if (INTEL_INFO(dev)->gen > 3) {
12747 DRM_DEBUG("unsupported pixel format: %s\n",
12748 drm_get_format_name(mode_cmd->pixel_format));
12749 return -EINVAL;
12750 }
12751 break;
12752 case DRM_FORMAT_XBGR8888:
12753 case DRM_FORMAT_ABGR8888:
12754 case DRM_FORMAT_XRGB2101010:
12755 case DRM_FORMAT_ARGB2101010:
12756 case DRM_FORMAT_XBGR2101010:
12757 case DRM_FORMAT_ABGR2101010:
12758 if (INTEL_INFO(dev)->gen < 4) {
12759 DRM_DEBUG("unsupported pixel format: %s\n",
12760 drm_get_format_name(mode_cmd->pixel_format));
12761 return -EINVAL;
12762 }
12763 break;
12764 case DRM_FORMAT_YUYV:
12765 case DRM_FORMAT_UYVY:
12766 case DRM_FORMAT_YVYU:
12767 case DRM_FORMAT_VYUY:
12768 if (INTEL_INFO(dev)->gen < 5) {
12769 DRM_DEBUG("unsupported pixel format: %s\n",
12770 drm_get_format_name(mode_cmd->pixel_format));
12771 return -EINVAL;
12772 }
12773 break;
12774 default:
12775 DRM_DEBUG("unsupported pixel format: %s\n",
12776 drm_get_format_name(mode_cmd->pixel_format));
12777 return -EINVAL;
12778 }
12779
12780 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12781 if (mode_cmd->offsets[0] != 0)
12782 return -EINVAL;
12783
12784 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12785 mode_cmd->pixel_format,
12786 mode_cmd->modifier[0]);
12787 /* FIXME drm helper for size checks (especially planar formats)? */
12788 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12789 return -EINVAL;
12790
12791 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12792 intel_fb->obj = obj;
12793 intel_fb->obj->framebuffer_references++;
12794
12795 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12796 if (ret) {
12797 DRM_ERROR("framebuffer init failed %d\n", ret);
12798 return ret;
12799 }
12800
12801 return 0;
12802 }
12803
12804 static struct drm_framebuffer *
12805 intel_user_framebuffer_create(struct drm_device *dev,
12806 struct drm_file *filp,
12807 struct drm_mode_fb_cmd2 *mode_cmd)
12808 {
12809 struct drm_i915_gem_object *obj;
12810
12811 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12812 mode_cmd->handles[0]));
12813 if (&obj->base == NULL)
12814 return ERR_PTR(-ENOENT);
12815
12816 return intel_framebuffer_create(dev, mode_cmd, obj);
12817 }
12818
12819 #ifndef CONFIG_DRM_I915_FBDEV
12820 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12821 {
12822 }
12823 #endif
12824
12825 static const struct drm_mode_config_funcs intel_mode_funcs = {
12826 .fb_create = intel_user_framebuffer_create,
12827 .output_poll_changed = intel_fbdev_output_poll_changed,
12828 .atomic_check = intel_atomic_check,
12829 .atomic_commit = intel_atomic_commit,
12830 };
12831
12832 /* Set up chip specific display functions */
12833 static void intel_init_display(struct drm_device *dev)
12834 {
12835 struct drm_i915_private *dev_priv = dev->dev_private;
12836
12837 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12838 dev_priv->display.find_dpll = g4x_find_best_dpll;
12839 else if (IS_CHERRYVIEW(dev))
12840 dev_priv->display.find_dpll = chv_find_best_dpll;
12841 else if (IS_VALLEYVIEW(dev))
12842 dev_priv->display.find_dpll = vlv_find_best_dpll;
12843 else if (IS_PINEVIEW(dev))
12844 dev_priv->display.find_dpll = pnv_find_best_dpll;
12845 else
12846 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12847
12848 if (INTEL_INFO(dev)->gen >= 9) {
12849 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12850 dev_priv->display.get_initial_plane_config =
12851 skylake_get_initial_plane_config;
12852 dev_priv->display.crtc_compute_clock =
12853 haswell_crtc_compute_clock;
12854 dev_priv->display.crtc_enable = haswell_crtc_enable;
12855 dev_priv->display.crtc_disable = haswell_crtc_disable;
12856 dev_priv->display.off = ironlake_crtc_off;
12857 dev_priv->display.update_primary_plane =
12858 skylake_update_primary_plane;
12859 } else if (HAS_DDI(dev)) {
12860 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12861 dev_priv->display.get_initial_plane_config =
12862 ironlake_get_initial_plane_config;
12863 dev_priv->display.crtc_compute_clock =
12864 haswell_crtc_compute_clock;
12865 dev_priv->display.crtc_enable = haswell_crtc_enable;
12866 dev_priv->display.crtc_disable = haswell_crtc_disable;
12867 dev_priv->display.off = ironlake_crtc_off;
12868 dev_priv->display.update_primary_plane =
12869 ironlake_update_primary_plane;
12870 } else if (HAS_PCH_SPLIT(dev)) {
12871 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12872 dev_priv->display.get_initial_plane_config =
12873 ironlake_get_initial_plane_config;
12874 dev_priv->display.crtc_compute_clock =
12875 ironlake_crtc_compute_clock;
12876 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12877 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12878 dev_priv->display.off = ironlake_crtc_off;
12879 dev_priv->display.update_primary_plane =
12880 ironlake_update_primary_plane;
12881 } else if (IS_VALLEYVIEW(dev)) {
12882 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12883 dev_priv->display.get_initial_plane_config =
12884 i9xx_get_initial_plane_config;
12885 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12886 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12887 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12888 dev_priv->display.off = i9xx_crtc_off;
12889 dev_priv->display.update_primary_plane =
12890 i9xx_update_primary_plane;
12891 } else {
12892 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12893 dev_priv->display.get_initial_plane_config =
12894 i9xx_get_initial_plane_config;
12895 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12896 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12897 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12898 dev_priv->display.off = i9xx_crtc_off;
12899 dev_priv->display.update_primary_plane =
12900 i9xx_update_primary_plane;
12901 }
12902
12903 /* Returns the core display clock speed */
12904 if (IS_VALLEYVIEW(dev))
12905 dev_priv->display.get_display_clock_speed =
12906 valleyview_get_display_clock_speed;
12907 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12908 dev_priv->display.get_display_clock_speed =
12909 i945_get_display_clock_speed;
12910 else if (IS_I915G(dev))
12911 dev_priv->display.get_display_clock_speed =
12912 i915_get_display_clock_speed;
12913 else if (IS_I945GM(dev) || IS_845G(dev))
12914 dev_priv->display.get_display_clock_speed =
12915 i9xx_misc_get_display_clock_speed;
12916 else if (IS_PINEVIEW(dev))
12917 dev_priv->display.get_display_clock_speed =
12918 pnv_get_display_clock_speed;
12919 else if (IS_I915GM(dev))
12920 dev_priv->display.get_display_clock_speed =
12921 i915gm_get_display_clock_speed;
12922 else if (IS_I865G(dev))
12923 dev_priv->display.get_display_clock_speed =
12924 i865_get_display_clock_speed;
12925 else if (IS_I85X(dev))
12926 dev_priv->display.get_display_clock_speed =
12927 i855_get_display_clock_speed;
12928 else /* 852, 830 */
12929 dev_priv->display.get_display_clock_speed =
12930 i830_get_display_clock_speed;
12931
12932 if (IS_GEN5(dev)) {
12933 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12934 } else if (IS_GEN6(dev)) {
12935 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12936 } else if (IS_IVYBRIDGE(dev)) {
12937 /* FIXME: detect B0+ stepping and use auto training */
12938 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12939 dev_priv->display.modeset_global_resources =
12940 ivb_modeset_global_resources;
12941 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12942 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12943 } else if (IS_VALLEYVIEW(dev)) {
12944 dev_priv->display.modeset_global_resources =
12945 valleyview_modeset_global_resources;
12946 }
12947
12948 switch (INTEL_INFO(dev)->gen) {
12949 case 2:
12950 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12951 break;
12952
12953 case 3:
12954 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12955 break;
12956
12957 case 4:
12958 case 5:
12959 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12960 break;
12961
12962 case 6:
12963 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12964 break;
12965 case 7:
12966 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12967 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12968 break;
12969 case 9:
12970 /* Drop through - unsupported since execlist only. */
12971 default:
12972 /* Default just returns -ENODEV to indicate unsupported */
12973 dev_priv->display.queue_flip = intel_default_queue_flip;
12974 }
12975
12976 intel_panel_init_backlight_funcs(dev);
12977
12978 mutex_init(&dev_priv->pps_mutex);
12979 }
12980
12981 /*
12982 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12983 * resume, or other times. This quirk makes sure that's the case for
12984 * affected systems.
12985 */
12986 static void quirk_pipea_force(struct drm_device *dev)
12987 {
12988 struct drm_i915_private *dev_priv = dev->dev_private;
12989
12990 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12991 DRM_INFO("applying pipe a force quirk\n");
12992 }
12993
12994 static void quirk_pipeb_force(struct drm_device *dev)
12995 {
12996 struct drm_i915_private *dev_priv = dev->dev_private;
12997
12998 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12999 DRM_INFO("applying pipe b force quirk\n");
13000 }
13001
13002 /*
13003 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13004 */
13005 static void quirk_ssc_force_disable(struct drm_device *dev)
13006 {
13007 struct drm_i915_private *dev_priv = dev->dev_private;
13008 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13009 DRM_INFO("applying lvds SSC disable quirk\n");
13010 }
13011
13012 /*
13013 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13014 * brightness value
13015 */
13016 static void quirk_invert_brightness(struct drm_device *dev)
13017 {
13018 struct drm_i915_private *dev_priv = dev->dev_private;
13019 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13020 DRM_INFO("applying inverted panel brightness quirk\n");
13021 }
13022
13023 /* Some VBT's incorrectly indicate no backlight is present */
13024 static void quirk_backlight_present(struct drm_device *dev)
13025 {
13026 struct drm_i915_private *dev_priv = dev->dev_private;
13027 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13028 DRM_INFO("applying backlight present quirk\n");
13029 }
13030
13031 struct intel_quirk {
13032 int device;
13033 int subsystem_vendor;
13034 int subsystem_device;
13035 void (*hook)(struct drm_device *dev);
13036 };
13037
13038 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13039 struct intel_dmi_quirk {
13040 void (*hook)(struct drm_device *dev);
13041 const struct dmi_system_id (*dmi_id_list)[];
13042 };
13043
13044 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13045 {
13046 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13047 return 1;
13048 }
13049
13050 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13051 {
13052 .dmi_id_list = &(const struct dmi_system_id[]) {
13053 {
13054 .callback = intel_dmi_reverse_brightness,
13055 .ident = "NCR Corporation",
13056 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13057 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13058 },
13059 },
13060 { } /* terminating entry */
13061 },
13062 .hook = quirk_invert_brightness,
13063 },
13064 };
13065
13066 static struct intel_quirk intel_quirks[] = {
13067 /* HP Mini needs pipe A force quirk (LP: #322104) */
13068 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13069
13070 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13071 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13072
13073 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13074 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13075
13076 /* 830 needs to leave pipe A & dpll A up */
13077 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13078
13079 /* 830 needs to leave pipe B & dpll B up */
13080 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13081
13082 /* Lenovo U160 cannot use SSC on LVDS */
13083 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13084
13085 /* Sony Vaio Y cannot use SSC on LVDS */
13086 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13087
13088 /* Acer Aspire 5734Z must invert backlight brightness */
13089 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13090
13091 /* Acer/eMachines G725 */
13092 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13093
13094 /* Acer/eMachines e725 */
13095 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13096
13097 /* Acer/Packard Bell NCL20 */
13098 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13099
13100 /* Acer Aspire 4736Z */
13101 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13102
13103 /* Acer Aspire 5336 */
13104 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13105
13106 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13107 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13108
13109 /* Acer C720 Chromebook (Core i3 4005U) */
13110 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13111
13112 /* Apple Macbook 2,1 (Core 2 T7400) */
13113 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13114
13115 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13116 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13117
13118 /* HP Chromebook 14 (Celeron 2955U) */
13119 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13120 };
13121
13122 static void intel_init_quirks(struct drm_device *dev)
13123 {
13124 struct pci_dev *d = dev->pdev;
13125 int i;
13126
13127 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13128 struct intel_quirk *q = &intel_quirks[i];
13129
13130 if (d->device == q->device &&
13131 (d->subsystem_vendor == q->subsystem_vendor ||
13132 q->subsystem_vendor == PCI_ANY_ID) &&
13133 (d->subsystem_device == q->subsystem_device ||
13134 q->subsystem_device == PCI_ANY_ID))
13135 q->hook(dev);
13136 }
13137 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13138 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13139 intel_dmi_quirks[i].hook(dev);
13140 }
13141 }
13142
13143 /* Disable the VGA plane that we never use */
13144 static void i915_disable_vga(struct drm_device *dev)
13145 {
13146 struct drm_i915_private *dev_priv = dev->dev_private;
13147 u8 sr1;
13148 u32 vga_reg = i915_vgacntrl_reg(dev);
13149
13150 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13151 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13152 outb(SR01, VGA_SR_INDEX);
13153 sr1 = inb(VGA_SR_DATA);
13154 outb(sr1 | 1<<5, VGA_SR_DATA);
13155 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13156 udelay(300);
13157
13158 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13159 POSTING_READ(vga_reg);
13160 }
13161
13162 void intel_modeset_init_hw(struct drm_device *dev)
13163 {
13164 intel_prepare_ddi(dev);
13165
13166 if (IS_VALLEYVIEW(dev))
13167 vlv_update_cdclk(dev);
13168
13169 intel_init_clock_gating(dev);
13170
13171 intel_enable_gt_powersave(dev);
13172 }
13173
13174 void intel_modeset_init(struct drm_device *dev)
13175 {
13176 struct drm_i915_private *dev_priv = dev->dev_private;
13177 int sprite, ret;
13178 enum pipe pipe;
13179 struct intel_crtc *crtc;
13180
13181 drm_mode_config_init(dev);
13182
13183 dev->mode_config.min_width = 0;
13184 dev->mode_config.min_height = 0;
13185
13186 dev->mode_config.preferred_depth = 24;
13187 dev->mode_config.prefer_shadow = 1;
13188
13189 dev->mode_config.allow_fb_modifiers = true;
13190
13191 dev->mode_config.funcs = &intel_mode_funcs;
13192
13193 intel_init_quirks(dev);
13194
13195 intel_init_pm(dev);
13196
13197 if (INTEL_INFO(dev)->num_pipes == 0)
13198 return;
13199
13200 intel_init_display(dev);
13201 intel_init_audio(dev);
13202
13203 if (IS_GEN2(dev)) {
13204 dev->mode_config.max_width = 2048;
13205 dev->mode_config.max_height = 2048;
13206 } else if (IS_GEN3(dev)) {
13207 dev->mode_config.max_width = 4096;
13208 dev->mode_config.max_height = 4096;
13209 } else {
13210 dev->mode_config.max_width = 8192;
13211 dev->mode_config.max_height = 8192;
13212 }
13213
13214 if (IS_845G(dev) || IS_I865G(dev)) {
13215 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13216 dev->mode_config.cursor_height = 1023;
13217 } else if (IS_GEN2(dev)) {
13218 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13219 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13220 } else {
13221 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13222 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13223 }
13224
13225 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13226
13227 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13228 INTEL_INFO(dev)->num_pipes,
13229 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13230
13231 for_each_pipe(dev_priv, pipe) {
13232 intel_crtc_init(dev, pipe);
13233 for_each_sprite(pipe, sprite) {
13234 ret = intel_plane_init(dev, pipe, sprite);
13235 if (ret)
13236 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13237 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13238 }
13239 }
13240
13241 intel_init_dpio(dev);
13242
13243 intel_shared_dpll_init(dev);
13244
13245 /* Just disable it once at startup */
13246 i915_disable_vga(dev);
13247 intel_setup_outputs(dev);
13248
13249 /* Just in case the BIOS is doing something questionable. */
13250 intel_fbc_disable(dev);
13251
13252 drm_modeset_lock_all(dev);
13253 intel_modeset_setup_hw_state(dev, false);
13254 drm_modeset_unlock_all(dev);
13255
13256 for_each_intel_crtc(dev, crtc) {
13257 if (!crtc->active)
13258 continue;
13259
13260 /*
13261 * Note that reserving the BIOS fb up front prevents us
13262 * from stuffing other stolen allocations like the ring
13263 * on top. This prevents some ugliness at boot time, and
13264 * can even allow for smooth boot transitions if the BIOS
13265 * fb is large enough for the active pipe configuration.
13266 */
13267 if (dev_priv->display.get_initial_plane_config) {
13268 dev_priv->display.get_initial_plane_config(crtc,
13269 &crtc->plane_config);
13270 /*
13271 * If the fb is shared between multiple heads, we'll
13272 * just get the first one.
13273 */
13274 intel_find_plane_obj(crtc, &crtc->plane_config);
13275 }
13276 }
13277 }
13278
13279 static void intel_enable_pipe_a(struct drm_device *dev)
13280 {
13281 struct intel_connector *connector;
13282 struct drm_connector *crt = NULL;
13283 struct intel_load_detect_pipe load_detect_temp;
13284 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13285
13286 /* We can't just switch on the pipe A, we need to set things up with a
13287 * proper mode and output configuration. As a gross hack, enable pipe A
13288 * by enabling the load detect pipe once. */
13289 list_for_each_entry(connector,
13290 &dev->mode_config.connector_list,
13291 base.head) {
13292 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13293 crt = &connector->base;
13294 break;
13295 }
13296 }
13297
13298 if (!crt)
13299 return;
13300
13301 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13302 intel_release_load_detect_pipe(crt, &load_detect_temp);
13303 }
13304
13305 static bool
13306 intel_check_plane_mapping(struct intel_crtc *crtc)
13307 {
13308 struct drm_device *dev = crtc->base.dev;
13309 struct drm_i915_private *dev_priv = dev->dev_private;
13310 u32 reg, val;
13311
13312 if (INTEL_INFO(dev)->num_pipes == 1)
13313 return true;
13314
13315 reg = DSPCNTR(!crtc->plane);
13316 val = I915_READ(reg);
13317
13318 if ((val & DISPLAY_PLANE_ENABLE) &&
13319 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13320 return false;
13321
13322 return true;
13323 }
13324
13325 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13326 {
13327 struct drm_device *dev = crtc->base.dev;
13328 struct drm_i915_private *dev_priv = dev->dev_private;
13329 u32 reg;
13330
13331 /* Clear any frame start delays used for debugging left by the BIOS */
13332 reg = PIPECONF(crtc->config->cpu_transcoder);
13333 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13334
13335 /* restore vblank interrupts to correct state */
13336 drm_crtc_vblank_reset(&crtc->base);
13337 if (crtc->active) {
13338 update_scanline_offset(crtc);
13339 drm_crtc_vblank_on(&crtc->base);
13340 }
13341
13342 /* We need to sanitize the plane -> pipe mapping first because this will
13343 * disable the crtc (and hence change the state) if it is wrong. Note
13344 * that gen4+ has a fixed plane -> pipe mapping. */
13345 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13346 struct intel_connector *connector;
13347 bool plane;
13348
13349 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13350 crtc->base.base.id);
13351
13352 /* Pipe has the wrong plane attached and the plane is active.
13353 * Temporarily change the plane mapping and disable everything
13354 * ... */
13355 plane = crtc->plane;
13356 crtc->plane = !plane;
13357 crtc->primary_enabled = true;
13358 dev_priv->display.crtc_disable(&crtc->base);
13359 crtc->plane = plane;
13360
13361 /* ... and break all links. */
13362 list_for_each_entry(connector, &dev->mode_config.connector_list,
13363 base.head) {
13364 if (connector->encoder->base.crtc != &crtc->base)
13365 continue;
13366
13367 connector->base.dpms = DRM_MODE_DPMS_OFF;
13368 connector->base.encoder = NULL;
13369 }
13370 /* multiple connectors may have the same encoder:
13371 * handle them and break crtc link separately */
13372 list_for_each_entry(connector, &dev->mode_config.connector_list,
13373 base.head)
13374 if (connector->encoder->base.crtc == &crtc->base) {
13375 connector->encoder->base.crtc = NULL;
13376 connector->encoder->connectors_active = false;
13377 }
13378
13379 WARN_ON(crtc->active);
13380 crtc->base.enabled = false;
13381 }
13382
13383 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13384 crtc->pipe == PIPE_A && !crtc->active) {
13385 /* BIOS forgot to enable pipe A, this mostly happens after
13386 * resume. Force-enable the pipe to fix this, the update_dpms
13387 * call below we restore the pipe to the right state, but leave
13388 * the required bits on. */
13389 intel_enable_pipe_a(dev);
13390 }
13391
13392 /* Adjust the state of the output pipe according to whether we
13393 * have active connectors/encoders. */
13394 intel_crtc_update_dpms(&crtc->base);
13395
13396 if (crtc->active != crtc->base.enabled) {
13397 struct intel_encoder *encoder;
13398
13399 /* This can happen either due to bugs in the get_hw_state
13400 * functions or because the pipe is force-enabled due to the
13401 * pipe A quirk. */
13402 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13403 crtc->base.base.id,
13404 crtc->base.enabled ? "enabled" : "disabled",
13405 crtc->active ? "enabled" : "disabled");
13406
13407 crtc->base.enabled = crtc->active;
13408
13409 /* Because we only establish the connector -> encoder ->
13410 * crtc links if something is active, this means the
13411 * crtc is now deactivated. Break the links. connector
13412 * -> encoder links are only establish when things are
13413 * actually up, hence no need to break them. */
13414 WARN_ON(crtc->active);
13415
13416 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13417 WARN_ON(encoder->connectors_active);
13418 encoder->base.crtc = NULL;
13419 }
13420 }
13421
13422 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13423 /*
13424 * We start out with underrun reporting disabled to avoid races.
13425 * For correct bookkeeping mark this on active crtcs.
13426 *
13427 * Also on gmch platforms we dont have any hardware bits to
13428 * disable the underrun reporting. Which means we need to start
13429 * out with underrun reporting disabled also on inactive pipes,
13430 * since otherwise we'll complain about the garbage we read when
13431 * e.g. coming up after runtime pm.
13432 *
13433 * No protection against concurrent access is required - at
13434 * worst a fifo underrun happens which also sets this to false.
13435 */
13436 crtc->cpu_fifo_underrun_disabled = true;
13437 crtc->pch_fifo_underrun_disabled = true;
13438 }
13439 }
13440
13441 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13442 {
13443 struct intel_connector *connector;
13444 struct drm_device *dev = encoder->base.dev;
13445
13446 /* We need to check both for a crtc link (meaning that the
13447 * encoder is active and trying to read from a pipe) and the
13448 * pipe itself being active. */
13449 bool has_active_crtc = encoder->base.crtc &&
13450 to_intel_crtc(encoder->base.crtc)->active;
13451
13452 if (encoder->connectors_active && !has_active_crtc) {
13453 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13454 encoder->base.base.id,
13455 encoder->base.name);
13456
13457 /* Connector is active, but has no active pipe. This is
13458 * fallout from our resume register restoring. Disable
13459 * the encoder manually again. */
13460 if (encoder->base.crtc) {
13461 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13462 encoder->base.base.id,
13463 encoder->base.name);
13464 encoder->disable(encoder);
13465 if (encoder->post_disable)
13466 encoder->post_disable(encoder);
13467 }
13468 encoder->base.crtc = NULL;
13469 encoder->connectors_active = false;
13470
13471 /* Inconsistent output/port/pipe state happens presumably due to
13472 * a bug in one of the get_hw_state functions. Or someplace else
13473 * in our code, like the register restore mess on resume. Clamp
13474 * things to off as a safer default. */
13475 list_for_each_entry(connector,
13476 &dev->mode_config.connector_list,
13477 base.head) {
13478 if (connector->encoder != encoder)
13479 continue;
13480 connector->base.dpms = DRM_MODE_DPMS_OFF;
13481 connector->base.encoder = NULL;
13482 }
13483 }
13484 /* Enabled encoders without active connectors will be fixed in
13485 * the crtc fixup. */
13486 }
13487
13488 void i915_redisable_vga_power_on(struct drm_device *dev)
13489 {
13490 struct drm_i915_private *dev_priv = dev->dev_private;
13491 u32 vga_reg = i915_vgacntrl_reg(dev);
13492
13493 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13494 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13495 i915_disable_vga(dev);
13496 }
13497 }
13498
13499 void i915_redisable_vga(struct drm_device *dev)
13500 {
13501 struct drm_i915_private *dev_priv = dev->dev_private;
13502
13503 /* This function can be called both from intel_modeset_setup_hw_state or
13504 * at a very early point in our resume sequence, where the power well
13505 * structures are not yet restored. Since this function is at a very
13506 * paranoid "someone might have enabled VGA while we were not looking"
13507 * level, just check if the power well is enabled instead of trying to
13508 * follow the "don't touch the power well if we don't need it" policy
13509 * the rest of the driver uses. */
13510 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13511 return;
13512
13513 i915_redisable_vga_power_on(dev);
13514 }
13515
13516 static bool primary_get_hw_state(struct intel_crtc *crtc)
13517 {
13518 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13519
13520 if (!crtc->active)
13521 return false;
13522
13523 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13524 }
13525
13526 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13527 {
13528 struct drm_i915_private *dev_priv = dev->dev_private;
13529 enum pipe pipe;
13530 struct intel_crtc *crtc;
13531 struct intel_encoder *encoder;
13532 struct intel_connector *connector;
13533 int i;
13534
13535 for_each_intel_crtc(dev, crtc) {
13536 memset(crtc->config, 0, sizeof(*crtc->config));
13537
13538 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13539
13540 crtc->active = dev_priv->display.get_pipe_config(crtc,
13541 crtc->config);
13542
13543 crtc->base.enabled = crtc->active;
13544 crtc->primary_enabled = primary_get_hw_state(crtc);
13545
13546 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13547 crtc->base.base.id,
13548 crtc->active ? "enabled" : "disabled");
13549 }
13550
13551 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13552 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13553
13554 pll->on = pll->get_hw_state(dev_priv, pll,
13555 &pll->config.hw_state);
13556 pll->active = 0;
13557 pll->config.crtc_mask = 0;
13558 for_each_intel_crtc(dev, crtc) {
13559 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13560 pll->active++;
13561 pll->config.crtc_mask |= 1 << crtc->pipe;
13562 }
13563 }
13564
13565 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13566 pll->name, pll->config.crtc_mask, pll->on);
13567
13568 if (pll->config.crtc_mask)
13569 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13570 }
13571
13572 for_each_intel_encoder(dev, encoder) {
13573 pipe = 0;
13574
13575 if (encoder->get_hw_state(encoder, &pipe)) {
13576 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13577 encoder->base.crtc = &crtc->base;
13578 encoder->get_config(encoder, crtc->config);
13579 } else {
13580 encoder->base.crtc = NULL;
13581 }
13582
13583 encoder->connectors_active = false;
13584 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13585 encoder->base.base.id,
13586 encoder->base.name,
13587 encoder->base.crtc ? "enabled" : "disabled",
13588 pipe_name(pipe));
13589 }
13590
13591 list_for_each_entry(connector, &dev->mode_config.connector_list,
13592 base.head) {
13593 if (connector->get_hw_state(connector)) {
13594 connector->base.dpms = DRM_MODE_DPMS_ON;
13595 connector->encoder->connectors_active = true;
13596 connector->base.encoder = &connector->encoder->base;
13597 } else {
13598 connector->base.dpms = DRM_MODE_DPMS_OFF;
13599 connector->base.encoder = NULL;
13600 }
13601 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13602 connector->base.base.id,
13603 connector->base.name,
13604 connector->base.encoder ? "enabled" : "disabled");
13605 }
13606 }
13607
13608 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13609 * and i915 state tracking structures. */
13610 void intel_modeset_setup_hw_state(struct drm_device *dev,
13611 bool force_restore)
13612 {
13613 struct drm_i915_private *dev_priv = dev->dev_private;
13614 enum pipe pipe;
13615 struct intel_crtc *crtc;
13616 struct intel_encoder *encoder;
13617 int i;
13618
13619 intel_modeset_readout_hw_state(dev);
13620
13621 /*
13622 * Now that we have the config, copy it to each CRTC struct
13623 * Note that this could go away if we move to using crtc_config
13624 * checking everywhere.
13625 */
13626 for_each_intel_crtc(dev, crtc) {
13627 if (crtc->active && i915.fastboot) {
13628 intel_mode_from_pipe_config(&crtc->base.mode,
13629 crtc->config);
13630 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13631 crtc->base.base.id);
13632 drm_mode_debug_printmodeline(&crtc->base.mode);
13633 }
13634 }
13635
13636 /* HW state is read out, now we need to sanitize this mess. */
13637 for_each_intel_encoder(dev, encoder) {
13638 intel_sanitize_encoder(encoder);
13639 }
13640
13641 for_each_pipe(dev_priv, pipe) {
13642 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13643 intel_sanitize_crtc(crtc);
13644 intel_dump_pipe_config(crtc, crtc->config,
13645 "[setup_hw_state]");
13646 }
13647
13648 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13649 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13650
13651 if (!pll->on || pll->active)
13652 continue;
13653
13654 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13655
13656 pll->disable(dev_priv, pll);
13657 pll->on = false;
13658 }
13659
13660 if (IS_GEN9(dev))
13661 skl_wm_get_hw_state(dev);
13662 else if (HAS_PCH_SPLIT(dev))
13663 ilk_wm_get_hw_state(dev);
13664
13665 if (force_restore) {
13666 i915_redisable_vga(dev);
13667
13668 /*
13669 * We need to use raw interfaces for restoring state to avoid
13670 * checking (bogus) intermediate states.
13671 */
13672 for_each_pipe(dev_priv, pipe) {
13673 struct drm_crtc *crtc =
13674 dev_priv->pipe_to_crtc_mapping[pipe];
13675
13676 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13677 crtc->primary->fb);
13678 }
13679 } else {
13680 intel_modeset_update_staged_output_state(dev);
13681 }
13682
13683 intel_modeset_check_state(dev);
13684 }
13685
13686 void intel_modeset_gem_init(struct drm_device *dev)
13687 {
13688 struct drm_i915_private *dev_priv = dev->dev_private;
13689 struct drm_crtc *c;
13690 struct drm_i915_gem_object *obj;
13691
13692 mutex_lock(&dev->struct_mutex);
13693 intel_init_gt_powersave(dev);
13694 mutex_unlock(&dev->struct_mutex);
13695
13696 /*
13697 * There may be no VBT; and if the BIOS enabled SSC we can
13698 * just keep using it to avoid unnecessary flicker. Whereas if the
13699 * BIOS isn't using it, don't assume it will work even if the VBT
13700 * indicates as much.
13701 */
13702 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13703 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13704 DREF_SSC1_ENABLE);
13705
13706 intel_modeset_init_hw(dev);
13707
13708 intel_setup_overlay(dev);
13709
13710 /*
13711 * Make sure any fbs we allocated at startup are properly
13712 * pinned & fenced. When we do the allocation it's too early
13713 * for this.
13714 */
13715 mutex_lock(&dev->struct_mutex);
13716 for_each_crtc(dev, c) {
13717 obj = intel_fb_obj(c->primary->fb);
13718 if (obj == NULL)
13719 continue;
13720
13721 if (intel_pin_and_fence_fb_obj(c->primary,
13722 c->primary->fb,
13723 NULL)) {
13724 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13725 to_intel_crtc(c)->pipe);
13726 drm_framebuffer_unreference(c->primary->fb);
13727 c->primary->fb = NULL;
13728 update_state_fb(c->primary);
13729 }
13730 }
13731 mutex_unlock(&dev->struct_mutex);
13732
13733 intel_backlight_register(dev);
13734 }
13735
13736 void intel_connector_unregister(struct intel_connector *intel_connector)
13737 {
13738 struct drm_connector *connector = &intel_connector->base;
13739
13740 intel_panel_destroy_backlight(connector);
13741 drm_connector_unregister(connector);
13742 }
13743
13744 void intel_modeset_cleanup(struct drm_device *dev)
13745 {
13746 struct drm_i915_private *dev_priv = dev->dev_private;
13747 struct drm_connector *connector;
13748
13749 intel_disable_gt_powersave(dev);
13750
13751 intel_backlight_unregister(dev);
13752
13753 /*
13754 * Interrupts and polling as the first thing to avoid creating havoc.
13755 * Too much stuff here (turning of connectors, ...) would
13756 * experience fancy races otherwise.
13757 */
13758 intel_irq_uninstall(dev_priv);
13759
13760 /*
13761 * Due to the hpd irq storm handling the hotplug work can re-arm the
13762 * poll handlers. Hence disable polling after hpd handling is shut down.
13763 */
13764 drm_kms_helper_poll_fini(dev);
13765
13766 mutex_lock(&dev->struct_mutex);
13767
13768 intel_unregister_dsm_handler();
13769
13770 intel_fbc_disable(dev);
13771
13772 ironlake_teardown_rc6(dev);
13773
13774 mutex_unlock(&dev->struct_mutex);
13775
13776 /* flush any delayed tasks or pending work */
13777 flush_scheduled_work();
13778
13779 /* destroy the backlight and sysfs files before encoders/connectors */
13780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13781 struct intel_connector *intel_connector;
13782
13783 intel_connector = to_intel_connector(connector);
13784 intel_connector->unregister(intel_connector);
13785 }
13786
13787 drm_mode_config_cleanup(dev);
13788
13789 intel_cleanup_overlay(dev);
13790
13791 mutex_lock(&dev->struct_mutex);
13792 intel_cleanup_gt_powersave(dev);
13793 mutex_unlock(&dev->struct_mutex);
13794 }
13795
13796 /*
13797 * Return which encoder is currently attached for connector.
13798 */
13799 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13800 {
13801 return &intel_attached_encoder(connector)->base;
13802 }
13803
13804 void intel_connector_attach_encoder(struct intel_connector *connector,
13805 struct intel_encoder *encoder)
13806 {
13807 connector->encoder = encoder;
13808 drm_mode_connector_attach_encoder(&connector->base,
13809 &encoder->base);
13810 }
13811
13812 /*
13813 * set vga decode state - true == enable VGA decode
13814 */
13815 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13816 {
13817 struct drm_i915_private *dev_priv = dev->dev_private;
13818 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13819 u16 gmch_ctrl;
13820
13821 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13822 DRM_ERROR("failed to read control word\n");
13823 return -EIO;
13824 }
13825
13826 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13827 return 0;
13828
13829 if (state)
13830 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13831 else
13832 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13833
13834 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13835 DRM_ERROR("failed to write control word\n");
13836 return -EIO;
13837 }
13838
13839 return 0;
13840 }
13841
13842 struct intel_display_error_state {
13843
13844 u32 power_well_driver;
13845
13846 int num_transcoders;
13847
13848 struct intel_cursor_error_state {
13849 u32 control;
13850 u32 position;
13851 u32 base;
13852 u32 size;
13853 } cursor[I915_MAX_PIPES];
13854
13855 struct intel_pipe_error_state {
13856 bool power_domain_on;
13857 u32 source;
13858 u32 stat;
13859 } pipe[I915_MAX_PIPES];
13860
13861 struct intel_plane_error_state {
13862 u32 control;
13863 u32 stride;
13864 u32 size;
13865 u32 pos;
13866 u32 addr;
13867 u32 surface;
13868 u32 tile_offset;
13869 } plane[I915_MAX_PIPES];
13870
13871 struct intel_transcoder_error_state {
13872 bool power_domain_on;
13873 enum transcoder cpu_transcoder;
13874
13875 u32 conf;
13876
13877 u32 htotal;
13878 u32 hblank;
13879 u32 hsync;
13880 u32 vtotal;
13881 u32 vblank;
13882 u32 vsync;
13883 } transcoder[4];
13884 };
13885
13886 struct intel_display_error_state *
13887 intel_display_capture_error_state(struct drm_device *dev)
13888 {
13889 struct drm_i915_private *dev_priv = dev->dev_private;
13890 struct intel_display_error_state *error;
13891 int transcoders[] = {
13892 TRANSCODER_A,
13893 TRANSCODER_B,
13894 TRANSCODER_C,
13895 TRANSCODER_EDP,
13896 };
13897 int i;
13898
13899 if (INTEL_INFO(dev)->num_pipes == 0)
13900 return NULL;
13901
13902 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13903 if (error == NULL)
13904 return NULL;
13905
13906 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13907 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13908
13909 for_each_pipe(dev_priv, i) {
13910 error->pipe[i].power_domain_on =
13911 __intel_display_power_is_enabled(dev_priv,
13912 POWER_DOMAIN_PIPE(i));
13913 if (!error->pipe[i].power_domain_on)
13914 continue;
13915
13916 error->cursor[i].control = I915_READ(CURCNTR(i));
13917 error->cursor[i].position = I915_READ(CURPOS(i));
13918 error->cursor[i].base = I915_READ(CURBASE(i));
13919
13920 error->plane[i].control = I915_READ(DSPCNTR(i));
13921 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13922 if (INTEL_INFO(dev)->gen <= 3) {
13923 error->plane[i].size = I915_READ(DSPSIZE(i));
13924 error->plane[i].pos = I915_READ(DSPPOS(i));
13925 }
13926 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13927 error->plane[i].addr = I915_READ(DSPADDR(i));
13928 if (INTEL_INFO(dev)->gen >= 4) {
13929 error->plane[i].surface = I915_READ(DSPSURF(i));
13930 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13931 }
13932
13933 error->pipe[i].source = I915_READ(PIPESRC(i));
13934
13935 if (HAS_GMCH_DISPLAY(dev))
13936 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13937 }
13938
13939 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13940 if (HAS_DDI(dev_priv->dev))
13941 error->num_transcoders++; /* Account for eDP. */
13942
13943 for (i = 0; i < error->num_transcoders; i++) {
13944 enum transcoder cpu_transcoder = transcoders[i];
13945
13946 error->transcoder[i].power_domain_on =
13947 __intel_display_power_is_enabled(dev_priv,
13948 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13949 if (!error->transcoder[i].power_domain_on)
13950 continue;
13951
13952 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13953
13954 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13955 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13956 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13957 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13958 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13959 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13960 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13961 }
13962
13963 return error;
13964 }
13965
13966 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13967
13968 void
13969 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13970 struct drm_device *dev,
13971 struct intel_display_error_state *error)
13972 {
13973 struct drm_i915_private *dev_priv = dev->dev_private;
13974 int i;
13975
13976 if (!error)
13977 return;
13978
13979 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13980 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13981 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13982 error->power_well_driver);
13983 for_each_pipe(dev_priv, i) {
13984 err_printf(m, "Pipe [%d]:\n", i);
13985 err_printf(m, " Power: %s\n",
13986 error->pipe[i].power_domain_on ? "on" : "off");
13987 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13988 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13989
13990 err_printf(m, "Plane [%d]:\n", i);
13991 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13992 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13993 if (INTEL_INFO(dev)->gen <= 3) {
13994 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13995 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13996 }
13997 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13998 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13999 if (INTEL_INFO(dev)->gen >= 4) {
14000 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14001 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14002 }
14003
14004 err_printf(m, "Cursor [%d]:\n", i);
14005 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14006 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14007 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14008 }
14009
14010 for (i = 0; i < error->num_transcoders; i++) {
14011 err_printf(m, "CPU transcoder: %c\n",
14012 transcoder_name(error->transcoder[i].cpu_transcoder));
14013 err_printf(m, " Power: %s\n",
14014 error->transcoder[i].power_domain_on ? "on" : "off");
14015 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14016 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14017 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14018 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14019 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14020 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14021 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14022 }
14023 }
14024
14025 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14026 {
14027 struct intel_crtc *crtc;
14028
14029 for_each_intel_crtc(dev, crtc) {
14030 struct intel_unpin_work *work;
14031
14032 spin_lock_irq(&dev->event_lock);
14033
14034 work = crtc->unpin_work;
14035
14036 if (work && work->event &&
14037 work->event->base.file_priv == file) {
14038 kfree(work->event);
14039 work->event = NULL;
14040 }
14041
14042 spin_unlock_irq(&dev->event_lock);
14043 }
14044 }
Linux kernel - Deliverables
This page took 0.318201 seconds and 6 git commands to generate.