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Merge tag 'iwlwifi-for-john-2014-11-10' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
971 *
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
975 *
976 * On Gen4 and above:
977 * wait for the pipe register state bit to turn off
978 *
979 * Otherwise:
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
982 *
983 */
984 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
985 {
986 struct drm_device *dev = crtc->base.dev;
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
989 enum pipe pipe = crtc->pipe;
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1266 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1267 state = true;
1268
1269 if (!intel_display_power_enabled(dev_priv,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1271 cur_state = false;
1272 } else {
1273 reg = PIPECONF(cpu_transcoder);
1274 val = I915_READ(reg);
1275 cur_state = !!(val & PIPECONF_ENABLE);
1276 }
1277
1278 WARN(cur_state != state,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe), state_string(state), state_string(cur_state));
1281 }
1282
1283 static void assert_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, bool state)
1285 {
1286 int reg;
1287 u32 val;
1288 bool cur_state;
1289
1290 reg = DSPCNTR(plane);
1291 val = I915_READ(reg);
1292 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1293 WARN(cur_state != state,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane), state_string(state), state_string(cur_state));
1296 }
1297
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300
1301 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe)
1303 {
1304 struct drm_device *dev = dev_priv->dev;
1305 int reg, i;
1306 u32 val;
1307 int cur_pipe;
1308
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev)->gen >= 4) {
1311 reg = DSPCNTR(pipe);
1312 val = I915_READ(reg);
1313 WARN(val & DISPLAY_PLANE_ENABLE,
1314 "plane %c assertion failure, should be disabled but not\n",
1315 plane_name(pipe));
1316 return;
1317 }
1318
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv, i) {
1321 reg = DSPCNTR(i);
1322 val = I915_READ(reg);
1323 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1324 DISPPLANE_SEL_PIPE_SHIFT;
1325 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe)
1333 {
1334 struct drm_device *dev = dev_priv->dev;
1335 int reg, sprite;
1336 u32 val;
1337
1338 if (IS_VALLEYVIEW(dev)) {
1339 for_each_sprite(pipe, sprite) {
1340 reg = SPCNTR(pipe, sprite);
1341 val = I915_READ(reg);
1342 WARN(val & SP_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe, sprite), pipe_name(pipe));
1345 }
1346 } else if (INTEL_INFO(dev)->gen >= 7) {
1347 reg = SPRCTL(pipe);
1348 val = I915_READ(reg);
1349 WARN(val & SPRITE_ENABLE,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe), pipe_name(pipe));
1352 } else if (INTEL_INFO(dev)->gen >= 5) {
1353 reg = DVSCNTR(pipe);
1354 val = I915_READ(reg);
1355 WARN(val & DVS_ENABLE,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe), pipe_name(pipe));
1358 }
1359 }
1360
1361 static void assert_vblank_disabled(struct drm_crtc *crtc)
1362 {
1363 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1364 drm_crtc_vblank_put(crtc);
1365 }
1366
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1368 {
1369 u32 val;
1370 bool enabled;
1371
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1373
1374 val = I915_READ(PCH_DREF_CONTROL);
1375 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1376 DREF_SUPERSPREAD_SOURCE_MASK));
1377 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1378 }
1379
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1381 enum pipe pipe)
1382 {
1383 int reg;
1384 u32 val;
1385 bool enabled;
1386
1387 reg = PCH_TRANSCONF(pipe);
1388 val = I915_READ(reg);
1389 enabled = !!(val & TRANS_ENABLE);
1390 WARN(enabled,
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1392 pipe_name(pipe));
1393 }
1394
1395 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe, u32 port_sel, u32 val)
1397 {
1398 if ((val & DP_PORT_EN) == 0)
1399 return false;
1400
1401 if (HAS_PCH_CPT(dev_priv->dev)) {
1402 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1403 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1404 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1405 return false;
1406 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1407 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1408 return false;
1409 } else {
1410 if ((val & DP_PIPE_MASK) != (pipe << 30))
1411 return false;
1412 }
1413 return true;
1414 }
1415
1416 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 val)
1418 {
1419 if ((val & SDVO_ENABLE) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv->dev)) {
1423 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1424 return false;
1425 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1426 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1427 return false;
1428 } else {
1429 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & LVDS_PORT_EN) == 0)
1439 return false;
1440
1441 if (HAS_PCH_CPT(dev_priv->dev)) {
1442 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1443 return false;
1444 } else {
1445 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & ADPA_DAC_ENABLE) == 0)
1455 return false;
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1461 return false;
1462 }
1463 return true;
1464 }
1465
1466 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, int reg, u32 port_sel)
1468 {
1469 u32 val = I915_READ(reg);
1470 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg, pipe_name(pipe));
1473
1474 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1475 && (val & DP_PIPEB_SELECT),
1476 "IBX PCH dp port still using transcoder B\n");
1477 }
1478
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, int reg)
1481 {
1482 u32 val = I915_READ(reg);
1483 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg, pipe_name(pipe));
1486
1487 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1488 && (val & SDVO_PIPE_B_SELECT),
1489 "IBX PCH hdmi port still using transcoder B\n");
1490 }
1491
1492 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe)
1494 {
1495 int reg;
1496 u32 val;
1497
1498 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1499 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1500 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1501
1502 reg = PCH_ADPA;
1503 val = I915_READ(reg);
1504 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1506 pipe_name(pipe));
1507
1508 reg = PCH_LVDS;
1509 val = I915_READ(reg);
1510 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1512 pipe_name(pipe));
1513
1514 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1515 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1516 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1517 }
1518
1519 static void intel_init_dpio(struct drm_device *dev)
1520 {
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523 if (!IS_VALLEYVIEW(dev))
1524 return;
1525
1526 /*
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1530 */
1531 if (IS_CHERRYVIEW(dev)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1534 } else {
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1536 }
1537 }
1538
1539 static void vlv_enable_pll(struct intel_crtc *crtc)
1540 {
1541 struct drm_device *dev = crtc->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543 int reg = DPLL(crtc->pipe);
1544 u32 dpll = crtc->config.dpll_hw_state.dpll;
1545
1546 assert_pipe_disabled(dev_priv, crtc->pipe);
1547
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1550
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv->dev))
1553 assert_panel_unlocked(dev_priv, crtc->pipe);
1554
1555 I915_WRITE(reg, dpll);
1556 POSTING_READ(reg);
1557 udelay(150);
1558
1559 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1561
1562 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1563 POSTING_READ(DPLL_MD(crtc->pipe));
1564
1565 /* We do this three times for luck */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg, dpll);
1573 POSTING_READ(reg);
1574 udelay(150); /* wait for warmup */
1575 }
1576
1577 static void chv_enable_pll(struct intel_crtc *crtc)
1578 {
1579 struct drm_device *dev = crtc->base.dev;
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 int pipe = crtc->pipe;
1582 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1583 u32 tmp;
1584
1585 assert_pipe_disabled(dev_priv, crtc->pipe);
1586
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1588
1589 mutex_lock(&dev_priv->dpio_lock);
1590
1591 /* Enable back the 10bit clock to display controller */
1592 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1593 tmp |= DPIO_DCLKP_EN;
1594 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1595
1596 /*
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1598 */
1599 udelay(1);
1600
1601 /* Enable PLL */
1602 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1603
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe);
1607
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1610 POSTING_READ(DPLL_MD(pipe));
1611
1612 mutex_unlock(&dev_priv->dpio_lock);
1613 }
1614
1615 static int intel_num_dvo_pipes(struct drm_device *dev)
1616 {
1617 struct intel_crtc *crtc;
1618 int count = 0;
1619
1620 for_each_intel_crtc(dev, crtc)
1621 count += crtc->active &&
1622 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO);
1623
1624 return count;
1625 }
1626
1627 static void i9xx_enable_pll(struct intel_crtc *crtc)
1628 {
1629 struct drm_device *dev = crtc->base.dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 int reg = DPLL(crtc->pipe);
1632 u32 dpll = crtc->config.dpll_hw_state.dpll;
1633
1634 assert_pipe_disabled(dev_priv, crtc->pipe);
1635
1636 /* No really, not for ILK+ */
1637 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1638
1639 /* PLL is protected by panel, make sure we can write it */
1640 if (IS_MOBILE(dev) && !IS_I830(dev))
1641 assert_panel_unlocked(dev_priv, crtc->pipe);
1642
1643 /* Enable DVO 2x clock on both PLLs if necessary */
1644 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1645 /*
1646 * It appears to be important that we don't enable this
1647 * for the current pipe before otherwise configuring the
1648 * PLL. No idea how this should be handled if multiple
1649 * DVO outputs are enabled simultaneosly.
1650 */
1651 dpll |= DPLL_DVO_2X_MODE;
1652 I915_WRITE(DPLL(!crtc->pipe),
1653 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1654 }
1655
1656 /* Wait for the clocks to stabilize. */
1657 POSTING_READ(reg);
1658 udelay(150);
1659
1660 if (INTEL_INFO(dev)->gen >= 4) {
1661 I915_WRITE(DPLL_MD(crtc->pipe),
1662 crtc->config.dpll_hw_state.dpll_md);
1663 } else {
1664 /* The pixel multiplier can only be updated once the
1665 * DPLL is enabled and the clocks are stable.
1666 *
1667 * So write it again.
1668 */
1669 I915_WRITE(reg, dpll);
1670 }
1671
1672 /* We do this three times for luck */
1673 I915_WRITE(reg, dpll);
1674 POSTING_READ(reg);
1675 udelay(150); /* wait for warmup */
1676 I915_WRITE(reg, dpll);
1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
1679 I915_WRITE(reg, dpll);
1680 POSTING_READ(reg);
1681 udelay(150); /* wait for warmup */
1682 }
1683
1684 /**
1685 * i9xx_disable_pll - disable a PLL
1686 * @dev_priv: i915 private structure
1687 * @pipe: pipe PLL to disable
1688 *
1689 * Disable the PLL for @pipe, making sure the pipe is off first.
1690 *
1691 * Note! This is for pre-ILK only.
1692 */
1693 static void i9xx_disable_pll(struct intel_crtc *crtc)
1694 {
1695 struct drm_device *dev = crtc->base.dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697 enum pipe pipe = crtc->pipe;
1698
1699 /* Disable DVO 2x clock on both PLLs if necessary */
1700 if (IS_I830(dev) &&
1701 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) &&
1702 intel_num_dvo_pipes(dev) == 1) {
1703 I915_WRITE(DPLL(PIPE_B),
1704 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1705 I915_WRITE(DPLL(PIPE_A),
1706 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1707 }
1708
1709 /* Don't disable pipe or pipe PLLs if needed */
1710 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1711 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1712 return;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 I915_WRITE(DPLL(pipe), 0);
1718 POSTING_READ(DPLL(pipe));
1719 }
1720
1721 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1722 {
1723 u32 val = 0;
1724
1725 /* Make sure the pipe isn't still relying on us */
1726 assert_pipe_disabled(dev_priv, pipe);
1727
1728 /*
1729 * Leave integrated clock source and reference clock enabled for pipe B.
1730 * The latter is needed for VGA hotplug / manual detection.
1731 */
1732 if (pipe == PIPE_B)
1733 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1734 I915_WRITE(DPLL(pipe), val);
1735 POSTING_READ(DPLL(pipe));
1736
1737 }
1738
1739 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1740 {
1741 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1742 u32 val;
1743
1744 /* Make sure the pipe isn't still relying on us */
1745 assert_pipe_disabled(dev_priv, pipe);
1746
1747 /* Set PLL en = 0 */
1748 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1749 if (pipe != PIPE_A)
1750 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
1753
1754 mutex_lock(&dev_priv->dpio_lock);
1755
1756 /* Disable 10bit clock to display controller */
1757 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1758 val &= ~DPIO_DCLKP_EN;
1759 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1760
1761 /* disable left/right clock distribution */
1762 if (pipe != PIPE_B) {
1763 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1764 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1765 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1766 } else {
1767 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1768 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1769 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1770 }
1771
1772 mutex_unlock(&dev_priv->dpio_lock);
1773 }
1774
1775 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1776 struct intel_digital_port *dport)
1777 {
1778 u32 port_mask;
1779 int dpll_reg;
1780
1781 switch (dport->port) {
1782 case PORT_B:
1783 port_mask = DPLL_PORTB_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 break;
1786 case PORT_C:
1787 port_mask = DPLL_PORTC_READY_MASK;
1788 dpll_reg = DPLL(0);
1789 break;
1790 case PORT_D:
1791 port_mask = DPLL_PORTD_READY_MASK;
1792 dpll_reg = DPIO_PHY_STATUS;
1793 break;
1794 default:
1795 BUG();
1796 }
1797
1798 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1799 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1800 port_name(dport->port), I915_READ(dpll_reg));
1801 }
1802
1803 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1804 {
1805 struct drm_device *dev = crtc->base.dev;
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1808
1809 if (WARN_ON(pll == NULL))
1810 return;
1811
1812 WARN_ON(!pll->refcount);
1813 if (pll->active == 0) {
1814 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1815 WARN_ON(pll->on);
1816 assert_shared_dpll_disabled(dev_priv, pll);
1817
1818 pll->mode_set(dev_priv, pll);
1819 }
1820 }
1821
1822 /**
1823 * intel_enable_shared_dpll - enable PCH PLL
1824 * @dev_priv: i915 private structure
1825 * @pipe: pipe PLL to enable
1826 *
1827 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1828 * drives the transcoder clock.
1829 */
1830 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 if (WARN_ON(pll == NULL))
1837 return;
1838
1839 if (WARN_ON(pll->refcount == 0))
1840 return;
1841
1842 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1843 pll->name, pll->active, pll->on,
1844 crtc->base.base.id);
1845
1846 if (pll->active++) {
1847 WARN_ON(!pll->on);
1848 assert_shared_dpll_enabled(dev_priv, pll);
1849 return;
1850 }
1851 WARN_ON(pll->on);
1852
1853 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1854
1855 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1856 pll->enable(dev_priv, pll);
1857 pll->on = true;
1858 }
1859
1860 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1861 {
1862 struct drm_device *dev = crtc->base.dev;
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1865
1866 /* PCH only available on ILK+ */
1867 BUG_ON(INTEL_INFO(dev)->gen < 5);
1868 if (WARN_ON(pll == NULL))
1869 return;
1870
1871 if (WARN_ON(pll->refcount == 0))
1872 return;
1873
1874 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1875 pll->name, pll->active, pll->on,
1876 crtc->base.base.id);
1877
1878 if (WARN_ON(pll->active == 0)) {
1879 assert_shared_dpll_disabled(dev_priv, pll);
1880 return;
1881 }
1882
1883 assert_shared_dpll_enabled(dev_priv, pll);
1884 WARN_ON(!pll->on);
1885 if (--pll->active)
1886 return;
1887
1888 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1889 pll->disable(dev_priv, pll);
1890 pll->on = false;
1891
1892 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1893 }
1894
1895 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1896 enum pipe pipe)
1897 {
1898 struct drm_device *dev = dev_priv->dev;
1899 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1901 uint32_t reg, val, pipeconf_val;
1902
1903 /* PCH only available on ILK+ */
1904 BUG_ON(!HAS_PCH_SPLIT(dev));
1905
1906 /* Make sure PCH DPLL is enabled */
1907 assert_shared_dpll_enabled(dev_priv,
1908 intel_crtc_to_shared_dpll(intel_crtc));
1909
1910 /* FDI must be feeding us bits for PCH ports */
1911 assert_fdi_tx_enabled(dev_priv, pipe);
1912 assert_fdi_rx_enabled(dev_priv, pipe);
1913
1914 if (HAS_PCH_CPT(dev)) {
1915 /* Workaround: Set the timing override bit before enabling the
1916 * pch transcoder. */
1917 reg = TRANS_CHICKEN2(pipe);
1918 val = I915_READ(reg);
1919 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1920 I915_WRITE(reg, val);
1921 }
1922
1923 reg = PCH_TRANSCONF(pipe);
1924 val = I915_READ(reg);
1925 pipeconf_val = I915_READ(PIPECONF(pipe));
1926
1927 if (HAS_PCH_IBX(dev_priv->dev)) {
1928 /*
1929 * make the BPC in transcoder be consistent with
1930 * that in pipeconf reg.
1931 */
1932 val &= ~PIPECONF_BPC_MASK;
1933 val |= pipeconf_val & PIPECONF_BPC_MASK;
1934 }
1935
1936 val &= ~TRANS_INTERLACE_MASK;
1937 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1938 if (HAS_PCH_IBX(dev_priv->dev) &&
1939 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1940 val |= TRANS_LEGACY_INTERLACED_ILK;
1941 else
1942 val |= TRANS_INTERLACED;
1943 else
1944 val |= TRANS_PROGRESSIVE;
1945
1946 I915_WRITE(reg, val | TRANS_ENABLE);
1947 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1948 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1949 }
1950
1951 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1952 enum transcoder cpu_transcoder)
1953 {
1954 u32 val, pipeconf_val;
1955
1956 /* PCH only available on ILK+ */
1957 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1958
1959 /* FDI must be feeding us bits for PCH ports */
1960 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1961 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1962
1963 /* Workaround: set timing override bit. */
1964 val = I915_READ(_TRANSA_CHICKEN2);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(_TRANSA_CHICKEN2, val);
1967
1968 val = TRANS_ENABLE;
1969 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1970
1971 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1972 PIPECONF_INTERLACED_ILK)
1973 val |= TRANS_INTERLACED;
1974 else
1975 val |= TRANS_PROGRESSIVE;
1976
1977 I915_WRITE(LPT_TRANSCONF, val);
1978 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1979 DRM_ERROR("Failed to enable PCH transcoder\n");
1980 }
1981
1982 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1983 enum pipe pipe)
1984 {
1985 struct drm_device *dev = dev_priv->dev;
1986 uint32_t reg, val;
1987
1988 /* FDI relies on the transcoder */
1989 assert_fdi_tx_disabled(dev_priv, pipe);
1990 assert_fdi_rx_disabled(dev_priv, pipe);
1991
1992 /* Ports must be off as well */
1993 assert_pch_ports_disabled(dev_priv, pipe);
1994
1995 reg = PCH_TRANSCONF(pipe);
1996 val = I915_READ(reg);
1997 val &= ~TRANS_ENABLE;
1998 I915_WRITE(reg, val);
1999 /* wait for PCH transcoder off, transcoder state */
2000 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2001 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2002
2003 if (!HAS_PCH_IBX(dev)) {
2004 /* Workaround: Clear the timing override chicken bit again. */
2005 reg = TRANS_CHICKEN2(pipe);
2006 val = I915_READ(reg);
2007 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(reg, val);
2009 }
2010 }
2011
2012 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2013 {
2014 u32 val;
2015
2016 val = I915_READ(LPT_TRANSCONF);
2017 val &= ~TRANS_ENABLE;
2018 I915_WRITE(LPT_TRANSCONF, val);
2019 /* wait for PCH transcoder off, transcoder state */
2020 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2021 DRM_ERROR("Failed to disable PCH transcoder\n");
2022
2023 /* Workaround: clear timing override bit. */
2024 val = I915_READ(_TRANSA_CHICKEN2);
2025 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(_TRANSA_CHICKEN2, val);
2027 }
2028
2029 /**
2030 * intel_enable_pipe - enable a pipe, asserting requirements
2031 * @crtc: crtc responsible for the pipe
2032 *
2033 * Enable @crtc's pipe, making sure that various hardware specific requirements
2034 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2035 */
2036 static void intel_enable_pipe(struct intel_crtc *crtc)
2037 {
2038 struct drm_device *dev = crtc->base.dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 enum pipe pipe = crtc->pipe;
2041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
2043 enum pipe pch_transcoder;
2044 int reg;
2045 u32 val;
2046
2047 assert_planes_disabled(dev_priv, pipe);
2048 assert_cursor_disabled(dev_priv, pipe);
2049 assert_sprites_disabled(dev_priv, pipe);
2050
2051 if (HAS_PCH_LPT(dev_priv->dev))
2052 pch_transcoder = TRANSCODER_A;
2053 else
2054 pch_transcoder = pipe;
2055
2056 /*
2057 * A pipe without a PLL won't actually be able to drive bits from
2058 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2059 * need the check.
2060 */
2061 if (!HAS_PCH_SPLIT(dev_priv->dev))
2062 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2063 assert_dsi_pll_enabled(dev_priv);
2064 else
2065 assert_pll_enabled(dev_priv, pipe);
2066 else {
2067 if (crtc->config.has_pch_encoder) {
2068 /* if driving the PCH, we need FDI enabled */
2069 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2070 assert_fdi_tx_pll_enabled(dev_priv,
2071 (enum pipe) cpu_transcoder);
2072 }
2073 /* FIXME: assert CPU port conditions for SNB+ */
2074 }
2075
2076 reg = PIPECONF(cpu_transcoder);
2077 val = I915_READ(reg);
2078 if (val & PIPECONF_ENABLE) {
2079 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2080 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2081 return;
2082 }
2083
2084 I915_WRITE(reg, val | PIPECONF_ENABLE);
2085 POSTING_READ(reg);
2086 }
2087
2088 /**
2089 * intel_disable_pipe - disable a pipe, asserting requirements
2090 * @crtc: crtc whose pipes is to be disabled
2091 *
2092 * Disable the pipe of @crtc, making sure that various hardware
2093 * specific requirements are met, if applicable, e.g. plane
2094 * disabled, panel fitter off, etc.
2095 *
2096 * Will wait until the pipe has shut down before returning.
2097 */
2098 static void intel_disable_pipe(struct intel_crtc *crtc)
2099 {
2100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2101 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2102 enum pipe pipe = crtc->pipe;
2103 int reg;
2104 u32 val;
2105
2106 /*
2107 * Make sure planes won't keep trying to pump pixels to us,
2108 * or we might hang the display.
2109 */
2110 assert_planes_disabled(dev_priv, pipe);
2111 assert_cursor_disabled(dev_priv, pipe);
2112 assert_sprites_disabled(dev_priv, pipe);
2113
2114 reg = PIPECONF(cpu_transcoder);
2115 val = I915_READ(reg);
2116 if ((val & PIPECONF_ENABLE) == 0)
2117 return;
2118
2119 /*
2120 * Double wide has implications for planes
2121 * so best keep it disabled when not needed.
2122 */
2123 if (crtc->config.double_wide)
2124 val &= ~PIPECONF_DOUBLE_WIDE;
2125
2126 /* Don't disable pipe or pipe PLLs if needed */
2127 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2128 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2129 val &= ~PIPECONF_ENABLE;
2130
2131 I915_WRITE(reg, val);
2132 if ((val & PIPECONF_ENABLE) == 0)
2133 intel_wait_for_pipe_off(crtc);
2134 }
2135
2136 /*
2137 * Plane regs are double buffered, going from enabled->disabled needs a
2138 * trigger in order to latch. The display address reg provides this.
2139 */
2140 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2141 enum plane plane)
2142 {
2143 struct drm_device *dev = dev_priv->dev;
2144 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2145
2146 I915_WRITE(reg, I915_READ(reg));
2147 POSTING_READ(reg);
2148 }
2149
2150 /**
2151 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2152 * @plane: plane to be enabled
2153 * @crtc: crtc for the plane
2154 *
2155 * Enable @plane on @crtc, making sure that the pipe is running first.
2156 */
2157 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2158 struct drm_crtc *crtc)
2159 {
2160 struct drm_device *dev = plane->dev;
2161 struct drm_i915_private *dev_priv = dev->dev_private;
2162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2163
2164 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2165 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2166
2167 if (intel_crtc->primary_enabled)
2168 return;
2169
2170 intel_crtc->primary_enabled = true;
2171
2172 dev_priv->display.update_primary_plane(crtc, plane->fb,
2173 crtc->x, crtc->y);
2174
2175 /*
2176 * BDW signals flip done immediately if the plane
2177 * is disabled, even if the plane enable is already
2178 * armed to occur at the next vblank :(
2179 */
2180 if (IS_BROADWELL(dev))
2181 intel_wait_for_vblank(dev, intel_crtc->pipe);
2182 }
2183
2184 /**
2185 * intel_disable_primary_hw_plane - disable the primary hardware plane
2186 * @plane: plane to be disabled
2187 * @crtc: crtc for the plane
2188 *
2189 * Disable @plane on @crtc, making sure that the pipe is running first.
2190 */
2191 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2192 struct drm_crtc *crtc)
2193 {
2194 struct drm_device *dev = plane->dev;
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2199
2200 if (!intel_crtc->primary_enabled)
2201 return;
2202
2203 intel_crtc->primary_enabled = false;
2204
2205 dev_priv->display.update_primary_plane(crtc, plane->fb,
2206 crtc->x, crtc->y);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213 return true;
2214 #endif
2215 return false;
2216 }
2217
2218 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2219 {
2220 int tile_height;
2221
2222 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2223 return ALIGN(height, tile_height);
2224 }
2225
2226 int
2227 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2228 struct drm_i915_gem_object *obj,
2229 struct intel_engine_cs *pipelined)
2230 {
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 u32 alignment;
2233 int ret;
2234
2235 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2236
2237 switch (obj->tiling_mode) {
2238 case I915_TILING_NONE:
2239 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2240 alignment = 128 * 1024;
2241 else if (INTEL_INFO(dev)->gen >= 4)
2242 alignment = 4 * 1024;
2243 else
2244 alignment = 64 * 1024;
2245 break;
2246 case I915_TILING_X:
2247 /* pin() will align the object as required by fence */
2248 alignment = 0;
2249 break;
2250 case I915_TILING_Y:
2251 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2252 return -EINVAL;
2253 default:
2254 BUG();
2255 }
2256
2257 /* Note that the w/a also requires 64 PTE of padding following the
2258 * bo. We currently fill all unused PTE with the shadow page and so
2259 * we should always have valid PTE following the scanout preventing
2260 * the VT-d warning.
2261 */
2262 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2263 alignment = 256 * 1024;
2264
2265 /*
2266 * Global gtt pte registers are special registers which actually forward
2267 * writes to a chunk of system memory. Which means that there is no risk
2268 * that the register values disappear as soon as we call
2269 * intel_runtime_pm_put(), so it is correct to wrap only the
2270 * pin/unpin/fence and not more.
2271 */
2272 intel_runtime_pm_get(dev_priv);
2273
2274 dev_priv->mm.interruptible = false;
2275 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2276 if (ret)
2277 goto err_interruptible;
2278
2279 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always install
2282 * a fence as the cost is not that onerous.
2283 */
2284 ret = i915_gem_object_get_fence(obj);
2285 if (ret)
2286 goto err_unpin;
2287
2288 i915_gem_object_pin_fence(obj);
2289
2290 dev_priv->mm.interruptible = true;
2291 intel_runtime_pm_put(dev_priv);
2292 return 0;
2293
2294 err_unpin:
2295 i915_gem_object_unpin_from_display_plane(obj);
2296 err_interruptible:
2297 dev_priv->mm.interruptible = true;
2298 intel_runtime_pm_put(dev_priv);
2299 return ret;
2300 }
2301
2302 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2303 {
2304 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2305
2306 i915_gem_object_unpin_fence(obj);
2307 i915_gem_object_unpin_from_display_plane(obj);
2308 }
2309
2310 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2311 * is assumed to be a power-of-two. */
2312 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2313 unsigned int tiling_mode,
2314 unsigned int cpp,
2315 unsigned int pitch)
2316 {
2317 if (tiling_mode != I915_TILING_NONE) {
2318 unsigned int tile_rows, tiles;
2319
2320 tile_rows = *y / 8;
2321 *y %= 8;
2322
2323 tiles = *x / (512/cpp);
2324 *x %= 512/cpp;
2325
2326 return tile_rows * pitch * 8 + tiles * 4096;
2327 } else {
2328 unsigned int offset;
2329
2330 offset = *y * pitch + *x * cpp;
2331 *y = 0;
2332 *x = (offset & 4095) / cpp;
2333 return offset & -4096;
2334 }
2335 }
2336
2337 int intel_format_to_fourcc(int format)
2338 {
2339 switch (format) {
2340 case DISPPLANE_8BPP:
2341 return DRM_FORMAT_C8;
2342 case DISPPLANE_BGRX555:
2343 return DRM_FORMAT_XRGB1555;
2344 case DISPPLANE_BGRX565:
2345 return DRM_FORMAT_RGB565;
2346 default:
2347 case DISPPLANE_BGRX888:
2348 return DRM_FORMAT_XRGB8888;
2349 case DISPPLANE_RGBX888:
2350 return DRM_FORMAT_XBGR8888;
2351 case DISPPLANE_BGRX101010:
2352 return DRM_FORMAT_XRGB2101010;
2353 case DISPPLANE_RGBX101010:
2354 return DRM_FORMAT_XBGR2101010;
2355 }
2356 }
2357
2358 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2359 struct intel_plane_config *plane_config)
2360 {
2361 struct drm_device *dev = crtc->base.dev;
2362 struct drm_i915_gem_object *obj = NULL;
2363 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2364 u32 base = plane_config->base;
2365
2366 if (plane_config->size == 0)
2367 return false;
2368
2369 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2370 plane_config->size);
2371 if (!obj)
2372 return false;
2373
2374 if (plane_config->tiled) {
2375 obj->tiling_mode = I915_TILING_X;
2376 obj->stride = crtc->base.primary->fb->pitches[0];
2377 }
2378
2379 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2380 mode_cmd.width = crtc->base.primary->fb->width;
2381 mode_cmd.height = crtc->base.primary->fb->height;
2382 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2383
2384 mutex_lock(&dev->struct_mutex);
2385
2386 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2387 &mode_cmd, obj)) {
2388 DRM_DEBUG_KMS("intel fb init failed\n");
2389 goto out_unref_obj;
2390 }
2391
2392 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2393 mutex_unlock(&dev->struct_mutex);
2394
2395 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2396 return true;
2397
2398 out_unref_obj:
2399 drm_gem_object_unreference(&obj->base);
2400 mutex_unlock(&dev->struct_mutex);
2401 return false;
2402 }
2403
2404 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2405 struct intel_plane_config *plane_config)
2406 {
2407 struct drm_device *dev = intel_crtc->base.dev;
2408 struct drm_crtc *c;
2409 struct intel_crtc *i;
2410 struct drm_i915_gem_object *obj;
2411
2412 if (!intel_crtc->base.primary->fb)
2413 return;
2414
2415 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2416 return;
2417
2418 kfree(intel_crtc->base.primary->fb);
2419 intel_crtc->base.primary->fb = NULL;
2420
2421 /*
2422 * Failed to alloc the obj, check to see if we should share
2423 * an fb with another CRTC instead
2424 */
2425 for_each_crtc(dev, c) {
2426 i = to_intel_crtc(c);
2427
2428 if (c == &intel_crtc->base)
2429 continue;
2430
2431 if (!i->active)
2432 continue;
2433
2434 obj = intel_fb_obj(c->primary->fb);
2435 if (obj == NULL)
2436 continue;
2437
2438 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2439 drm_framebuffer_reference(c->primary->fb);
2440 intel_crtc->base.primary->fb = c->primary->fb;
2441 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2442 break;
2443 }
2444 }
2445 }
2446
2447 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2448 struct drm_framebuffer *fb,
2449 int x, int y)
2450 {
2451 struct drm_device *dev = crtc->dev;
2452 struct drm_i915_private *dev_priv = dev->dev_private;
2453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2454 struct drm_i915_gem_object *obj;
2455 int plane = intel_crtc->plane;
2456 unsigned long linear_offset;
2457 u32 dspcntr;
2458 u32 reg = DSPCNTR(plane);
2459 int pixel_size;
2460
2461 if (!intel_crtc->primary_enabled) {
2462 I915_WRITE(reg, 0);
2463 if (INTEL_INFO(dev)->gen >= 4)
2464 I915_WRITE(DSPSURF(plane), 0);
2465 else
2466 I915_WRITE(DSPADDR(plane), 0);
2467 POSTING_READ(reg);
2468 return;
2469 }
2470
2471 obj = intel_fb_obj(fb);
2472 if (WARN_ON(obj == NULL))
2473 return;
2474
2475 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2476
2477 dspcntr = DISPPLANE_GAMMA_ENABLE;
2478
2479 dspcntr |= DISPLAY_PLANE_ENABLE;
2480
2481 if (INTEL_INFO(dev)->gen < 4) {
2482 if (intel_crtc->pipe == PIPE_B)
2483 dspcntr |= DISPPLANE_SEL_PIPE_B;
2484
2485 /* pipesrc and dspsize control the size that is scaled from,
2486 * which should always be the user's requested size.
2487 */
2488 I915_WRITE(DSPSIZE(plane),
2489 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2490 (intel_crtc->config.pipe_src_w - 1));
2491 I915_WRITE(DSPPOS(plane), 0);
2492 }
2493
2494 switch (fb->pixel_format) {
2495 case DRM_FORMAT_C8:
2496 dspcntr |= DISPPLANE_8BPP;
2497 break;
2498 case DRM_FORMAT_XRGB1555:
2499 case DRM_FORMAT_ARGB1555:
2500 dspcntr |= DISPPLANE_BGRX555;
2501 break;
2502 case DRM_FORMAT_RGB565:
2503 dspcntr |= DISPPLANE_BGRX565;
2504 break;
2505 case DRM_FORMAT_XRGB8888:
2506 case DRM_FORMAT_ARGB8888:
2507 dspcntr |= DISPPLANE_BGRX888;
2508 break;
2509 case DRM_FORMAT_XBGR8888:
2510 case DRM_FORMAT_ABGR8888:
2511 dspcntr |= DISPPLANE_RGBX888;
2512 break;
2513 case DRM_FORMAT_XRGB2101010:
2514 case DRM_FORMAT_ARGB2101010:
2515 dspcntr |= DISPPLANE_BGRX101010;
2516 break;
2517 case DRM_FORMAT_XBGR2101010:
2518 case DRM_FORMAT_ABGR2101010:
2519 dspcntr |= DISPPLANE_RGBX101010;
2520 break;
2521 default:
2522 BUG();
2523 }
2524
2525 if (INTEL_INFO(dev)->gen >= 4 &&
2526 obj->tiling_mode != I915_TILING_NONE)
2527 dspcntr |= DISPPLANE_TILED;
2528
2529 if (IS_G4X(dev))
2530 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2531
2532 linear_offset = y * fb->pitches[0] + x * pixel_size;
2533
2534 if (INTEL_INFO(dev)->gen >= 4) {
2535 intel_crtc->dspaddr_offset =
2536 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2537 pixel_size,
2538 fb->pitches[0]);
2539 linear_offset -= intel_crtc->dspaddr_offset;
2540 } else {
2541 intel_crtc->dspaddr_offset = linear_offset;
2542 }
2543
2544 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2545 dspcntr |= DISPPLANE_ROTATE_180;
2546
2547 x += (intel_crtc->config.pipe_src_w - 1);
2548 y += (intel_crtc->config.pipe_src_h - 1);
2549
2550 /* Finding the last pixel of the last line of the display
2551 data and adding to linear_offset*/
2552 linear_offset +=
2553 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2554 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2555 }
2556
2557 I915_WRITE(reg, dspcntr);
2558
2559 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2560 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2561 fb->pitches[0]);
2562 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2563 if (INTEL_INFO(dev)->gen >= 4) {
2564 I915_WRITE(DSPSURF(plane),
2565 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2566 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2567 I915_WRITE(DSPLINOFF(plane), linear_offset);
2568 } else
2569 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2570 POSTING_READ(reg);
2571 }
2572
2573 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2574 struct drm_framebuffer *fb,
2575 int x, int y)
2576 {
2577 struct drm_device *dev = crtc->dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
2579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2580 struct drm_i915_gem_object *obj;
2581 int plane = intel_crtc->plane;
2582 unsigned long linear_offset;
2583 u32 dspcntr;
2584 u32 reg = DSPCNTR(plane);
2585 int pixel_size;
2586
2587 if (!intel_crtc->primary_enabled) {
2588 I915_WRITE(reg, 0);
2589 I915_WRITE(DSPSURF(plane), 0);
2590 POSTING_READ(reg);
2591 return;
2592 }
2593
2594 obj = intel_fb_obj(fb);
2595 if (WARN_ON(obj == NULL))
2596 return;
2597
2598 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2599
2600 dspcntr = DISPPLANE_GAMMA_ENABLE;
2601
2602 dspcntr |= DISPLAY_PLANE_ENABLE;
2603
2604 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2605 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2606
2607 switch (fb->pixel_format) {
2608 case DRM_FORMAT_C8:
2609 dspcntr |= DISPPLANE_8BPP;
2610 break;
2611 case DRM_FORMAT_RGB565:
2612 dspcntr |= DISPPLANE_BGRX565;
2613 break;
2614 case DRM_FORMAT_XRGB8888:
2615 case DRM_FORMAT_ARGB8888:
2616 dspcntr |= DISPPLANE_BGRX888;
2617 break;
2618 case DRM_FORMAT_XBGR8888:
2619 case DRM_FORMAT_ABGR8888:
2620 dspcntr |= DISPPLANE_RGBX888;
2621 break;
2622 case DRM_FORMAT_XRGB2101010:
2623 case DRM_FORMAT_ARGB2101010:
2624 dspcntr |= DISPPLANE_BGRX101010;
2625 break;
2626 case DRM_FORMAT_XBGR2101010:
2627 case DRM_FORMAT_ABGR2101010:
2628 dspcntr |= DISPPLANE_RGBX101010;
2629 break;
2630 default:
2631 BUG();
2632 }
2633
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dspcntr |= DISPPLANE_TILED;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2638 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2639
2640 linear_offset = y * fb->pitches[0] + x * pixel_size;
2641 intel_crtc->dspaddr_offset =
2642 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2643 pixel_size,
2644 fb->pitches[0]);
2645 linear_offset -= intel_crtc->dspaddr_offset;
2646 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2650 x += (intel_crtc->config.pipe_src_w - 1);
2651 y += (intel_crtc->config.pipe_src_h - 1);
2652
2653 /* Finding the last pixel of the last line of the display
2654 data and adding to linear_offset*/
2655 linear_offset +=
2656 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2657 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2658 }
2659 }
2660
2661 I915_WRITE(reg, dspcntr);
2662
2663 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2664 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2665 fb->pitches[0]);
2666 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2667 I915_WRITE(DSPSURF(plane),
2668 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2669 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2670 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2671 } else {
2672 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2673 I915_WRITE(DSPLINOFF(plane), linear_offset);
2674 }
2675 POSTING_READ(reg);
2676 }
2677
2678 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2679 static int
2680 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2681 int x, int y, enum mode_set_atomic state)
2682 {
2683 struct drm_device *dev = crtc->dev;
2684 struct drm_i915_private *dev_priv = dev->dev_private;
2685
2686 if (dev_priv->display.disable_fbc)
2687 dev_priv->display.disable_fbc(dev);
2688 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2689
2690 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2691
2692 return 0;
2693 }
2694
2695 void intel_display_handle_reset(struct drm_device *dev)
2696 {
2697 struct drm_i915_private *dev_priv = dev->dev_private;
2698 struct drm_crtc *crtc;
2699
2700 /*
2701 * Flips in the rings have been nuked by the reset,
2702 * so complete all pending flips so that user space
2703 * will get its events and not get stuck.
2704 *
2705 * Also update the base address of all primary
2706 * planes to the the last fb to make sure we're
2707 * showing the correct fb after a reset.
2708 *
2709 * Need to make two loops over the crtcs so that we
2710 * don't try to grab a crtc mutex before the
2711 * pending_flip_queue really got woken up.
2712 */
2713
2714 for_each_crtc(dev, crtc) {
2715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2716 enum plane plane = intel_crtc->plane;
2717
2718 intel_prepare_page_flip(dev, plane);
2719 intel_finish_page_flip_plane(dev, plane);
2720 }
2721
2722 for_each_crtc(dev, crtc) {
2723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2724
2725 drm_modeset_lock(&crtc->mutex, NULL);
2726 /*
2727 * FIXME: Once we have proper support for primary planes (and
2728 * disabling them without disabling the entire crtc) allow again
2729 * a NULL crtc->primary->fb.
2730 */
2731 if (intel_crtc->active && crtc->primary->fb)
2732 dev_priv->display.update_primary_plane(crtc,
2733 crtc->primary->fb,
2734 crtc->x,
2735 crtc->y);
2736 drm_modeset_unlock(&crtc->mutex);
2737 }
2738 }
2739
2740 static int
2741 intel_finish_fb(struct drm_framebuffer *old_fb)
2742 {
2743 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2744 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2745 bool was_interruptible = dev_priv->mm.interruptible;
2746 int ret;
2747
2748 /* Big Hammer, we also need to ensure that any pending
2749 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2750 * current scanout is retired before unpinning the old
2751 * framebuffer.
2752 *
2753 * This should only fail upon a hung GPU, in which case we
2754 * can safely continue.
2755 */
2756 dev_priv->mm.interruptible = false;
2757 ret = i915_gem_object_finish_gpu(obj);
2758 dev_priv->mm.interruptible = was_interruptible;
2759
2760 return ret;
2761 }
2762
2763 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2764 {
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2768 unsigned long flags;
2769 bool pending;
2770
2771 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2772 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2773 return false;
2774
2775 spin_lock_irqsave(&dev->event_lock, flags);
2776 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2777 spin_unlock_irqrestore(&dev->event_lock, flags);
2778
2779 return pending;
2780 }
2781
2782 static int
2783 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2784 struct drm_framebuffer *fb)
2785 {
2786 struct drm_device *dev = crtc->dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum pipe pipe = intel_crtc->pipe;
2790 struct drm_framebuffer *old_fb = crtc->primary->fb;
2791 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2792 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2793 int ret;
2794
2795 if (intel_crtc_has_pending_flip(crtc)) {
2796 DRM_ERROR("pipe is still busy with an old pageflip\n");
2797 return -EBUSY;
2798 }
2799
2800 /* no fb bound */
2801 if (!fb) {
2802 DRM_ERROR("No FB bound\n");
2803 return 0;
2804 }
2805
2806 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2807 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2808 plane_name(intel_crtc->plane),
2809 INTEL_INFO(dev)->num_pipes);
2810 return -EINVAL;
2811 }
2812
2813 mutex_lock(&dev->struct_mutex);
2814 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2815 if (ret == 0)
2816 i915_gem_track_fb(old_obj, obj,
2817 INTEL_FRONTBUFFER_PRIMARY(pipe));
2818 mutex_unlock(&dev->struct_mutex);
2819 if (ret != 0) {
2820 DRM_ERROR("pin & fence failed\n");
2821 return ret;
2822 }
2823
2824 /*
2825 * Update pipe size and adjust fitter if needed: the reason for this is
2826 * that in compute_mode_changes we check the native mode (not the pfit
2827 * mode) to see if we can flip rather than do a full mode set. In the
2828 * fastboot case, we'll flip, but if we don't update the pipesrc and
2829 * pfit state, we'll end up with a big fb scanned out into the wrong
2830 * sized surface.
2831 *
2832 * To fix this properly, we need to hoist the checks up into
2833 * compute_mode_changes (or above), check the actual pfit state and
2834 * whether the platform allows pfit disable with pipe active, and only
2835 * then update the pipesrc and pfit state, even on the flip path.
2836 */
2837 if (i915.fastboot) {
2838 const struct drm_display_mode *adjusted_mode =
2839 &intel_crtc->config.adjusted_mode;
2840
2841 I915_WRITE(PIPESRC(intel_crtc->pipe),
2842 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2843 (adjusted_mode->crtc_vdisplay - 1));
2844 if (!intel_crtc->config.pch_pfit.enabled &&
2845 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2846 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2847 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2848 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2849 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2850 }
2851 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2852 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2853 }
2854
2855 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2856
2857 if (intel_crtc->active)
2858 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2859
2860 crtc->primary->fb = fb;
2861 crtc->x = x;
2862 crtc->y = y;
2863
2864 if (old_fb) {
2865 if (intel_crtc->active && old_fb != fb)
2866 intel_wait_for_vblank(dev, intel_crtc->pipe);
2867 mutex_lock(&dev->struct_mutex);
2868 intel_unpin_fb_obj(old_obj);
2869 mutex_unlock(&dev->struct_mutex);
2870 }
2871
2872 mutex_lock(&dev->struct_mutex);
2873 intel_update_fbc(dev);
2874 mutex_unlock(&dev->struct_mutex);
2875
2876 return 0;
2877 }
2878
2879 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2880 {
2881 struct drm_device *dev = crtc->dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2884 int pipe = intel_crtc->pipe;
2885 u32 reg, temp;
2886
2887 /* enable normal train */
2888 reg = FDI_TX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 if (IS_IVYBRIDGE(dev)) {
2891 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2892 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2893 } else {
2894 temp &= ~FDI_LINK_TRAIN_NONE;
2895 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2896 }
2897 I915_WRITE(reg, temp);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 if (HAS_PCH_CPT(dev)) {
2902 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2903 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2904 } else {
2905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_NONE;
2907 }
2908 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2909
2910 /* wait one idle pattern time */
2911 POSTING_READ(reg);
2912 udelay(1000);
2913
2914 /* IVB wants error correction enabled */
2915 if (IS_IVYBRIDGE(dev))
2916 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2917 FDI_FE_ERRC_ENABLE);
2918 }
2919
2920 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2921 {
2922 return crtc->base.enabled && crtc->active &&
2923 crtc->config.has_pch_encoder;
2924 }
2925
2926 static void ivb_modeset_global_resources(struct drm_device *dev)
2927 {
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 struct intel_crtc *pipe_B_crtc =
2930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2931 struct intel_crtc *pipe_C_crtc =
2932 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2933 uint32_t temp;
2934
2935 /*
2936 * When everything is off disable fdi C so that we could enable fdi B
2937 * with all lanes. Note that we don't care about enabled pipes without
2938 * an enabled pch encoder.
2939 */
2940 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2941 !pipe_has_enabled_pch(pipe_C_crtc)) {
2942 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2943 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2944
2945 temp = I915_READ(SOUTH_CHICKEN1);
2946 temp &= ~FDI_BC_BIFURCATION_SELECT;
2947 DRM_DEBUG_KMS("disabling fdi C rx\n");
2948 I915_WRITE(SOUTH_CHICKEN1, temp);
2949 }
2950 }
2951
2952 /* The FDI link training functions for ILK/Ibexpeak. */
2953 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2954 {
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2958 int pipe = intel_crtc->pipe;
2959 u32 reg, temp, tries;
2960
2961 /* FDI needs bits from pipe first */
2962 assert_pipe_enabled(dev_priv, pipe);
2963
2964 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2965 for train result */
2966 reg = FDI_RX_IMR(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_RX_SYMBOL_LOCK;
2969 temp &= ~FDI_RX_BIT_LOCK;
2970 I915_WRITE(reg, temp);
2971 I915_READ(reg);
2972 udelay(150);
2973
2974 /* enable CPU FDI TX and PCH FDI RX */
2975 reg = FDI_TX_CTL(pipe);
2976 temp = I915_READ(reg);
2977 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2978 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2979 temp &= ~FDI_LINK_TRAIN_NONE;
2980 temp |= FDI_LINK_TRAIN_PATTERN_1;
2981 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2982
2983 reg = FDI_RX_CTL(pipe);
2984 temp = I915_READ(reg);
2985 temp &= ~FDI_LINK_TRAIN_NONE;
2986 temp |= FDI_LINK_TRAIN_PATTERN_1;
2987 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2988
2989 POSTING_READ(reg);
2990 udelay(150);
2991
2992 /* Ironlake workaround, enable clock pointer after FDI enable*/
2993 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2994 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2995 FDI_RX_PHASE_SYNC_POINTER_EN);
2996
2997 reg = FDI_RX_IIR(pipe);
2998 for (tries = 0; tries < 5; tries++) {
2999 temp = I915_READ(reg);
3000 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3001
3002 if ((temp & FDI_RX_BIT_LOCK)) {
3003 DRM_DEBUG_KMS("FDI train 1 done.\n");
3004 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3005 break;
3006 }
3007 }
3008 if (tries == 5)
3009 DRM_ERROR("FDI train 1 fail!\n");
3010
3011 /* Train 2 */
3012 reg = FDI_TX_CTL(pipe);
3013 temp = I915_READ(reg);
3014 temp &= ~FDI_LINK_TRAIN_NONE;
3015 temp |= FDI_LINK_TRAIN_PATTERN_2;
3016 I915_WRITE(reg, temp);
3017
3018 reg = FDI_RX_CTL(pipe);
3019 temp = I915_READ(reg);
3020 temp &= ~FDI_LINK_TRAIN_NONE;
3021 temp |= FDI_LINK_TRAIN_PATTERN_2;
3022 I915_WRITE(reg, temp);
3023
3024 POSTING_READ(reg);
3025 udelay(150);
3026
3027 reg = FDI_RX_IIR(pipe);
3028 for (tries = 0; tries < 5; tries++) {
3029 temp = I915_READ(reg);
3030 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3031
3032 if (temp & FDI_RX_SYMBOL_LOCK) {
3033 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3034 DRM_DEBUG_KMS("FDI train 2 done.\n");
3035 break;
3036 }
3037 }
3038 if (tries == 5)
3039 DRM_ERROR("FDI train 2 fail!\n");
3040
3041 DRM_DEBUG_KMS("FDI train done\n");
3042
3043 }
3044
3045 static const int snb_b_fdi_train_param[] = {
3046 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3047 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3048 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3049 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3050 };
3051
3052 /* The FDI link training functions for SNB/Cougarpoint. */
3053 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3054 {
3055 struct drm_device *dev = crtc->dev;
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3058 int pipe = intel_crtc->pipe;
3059 u32 reg, temp, i, retry;
3060
3061 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3062 for train result */
3063 reg = FDI_RX_IMR(pipe);
3064 temp = I915_READ(reg);
3065 temp &= ~FDI_RX_SYMBOL_LOCK;
3066 temp &= ~FDI_RX_BIT_LOCK;
3067 I915_WRITE(reg, temp);
3068
3069 POSTING_READ(reg);
3070 udelay(150);
3071
3072 /* enable CPU FDI TX and PCH FDI RX */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3076 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3077 temp &= ~FDI_LINK_TRAIN_NONE;
3078 temp |= FDI_LINK_TRAIN_PATTERN_1;
3079 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3080 /* SNB-B */
3081 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3082 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3083
3084 I915_WRITE(FDI_RX_MISC(pipe),
3085 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3086
3087 reg = FDI_RX_CTL(pipe);
3088 temp = I915_READ(reg);
3089 if (HAS_PCH_CPT(dev)) {
3090 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3091 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3092 } else {
3093 temp &= ~FDI_LINK_TRAIN_NONE;
3094 temp |= FDI_LINK_TRAIN_PATTERN_1;
3095 }
3096 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3097
3098 POSTING_READ(reg);
3099 udelay(150);
3100
3101 for (i = 0; i < 4; i++) {
3102 reg = FDI_TX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3105 temp |= snb_b_fdi_train_param[i];
3106 I915_WRITE(reg, temp);
3107
3108 POSTING_READ(reg);
3109 udelay(500);
3110
3111 for (retry = 0; retry < 5; retry++) {
3112 reg = FDI_RX_IIR(pipe);
3113 temp = I915_READ(reg);
3114 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3115 if (temp & FDI_RX_BIT_LOCK) {
3116 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3117 DRM_DEBUG_KMS("FDI train 1 done.\n");
3118 break;
3119 }
3120 udelay(50);
3121 }
3122 if (retry < 5)
3123 break;
3124 }
3125 if (i == 4)
3126 DRM_ERROR("FDI train 1 fail!\n");
3127
3128 /* Train 2 */
3129 reg = FDI_TX_CTL(pipe);
3130 temp = I915_READ(reg);
3131 temp &= ~FDI_LINK_TRAIN_NONE;
3132 temp |= FDI_LINK_TRAIN_PATTERN_2;
3133 if (IS_GEN6(dev)) {
3134 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3135 /* SNB-B */
3136 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3137 }
3138 I915_WRITE(reg, temp);
3139
3140 reg = FDI_RX_CTL(pipe);
3141 temp = I915_READ(reg);
3142 if (HAS_PCH_CPT(dev)) {
3143 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3144 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3145 } else {
3146 temp &= ~FDI_LINK_TRAIN_NONE;
3147 temp |= FDI_LINK_TRAIN_PATTERN_2;
3148 }
3149 I915_WRITE(reg, temp);
3150
3151 POSTING_READ(reg);
3152 udelay(150);
3153
3154 for (i = 0; i < 4; i++) {
3155 reg = FDI_TX_CTL(pipe);
3156 temp = I915_READ(reg);
3157 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3158 temp |= snb_b_fdi_train_param[i];
3159 I915_WRITE(reg, temp);
3160
3161 POSTING_READ(reg);
3162 udelay(500);
3163
3164 for (retry = 0; retry < 5; retry++) {
3165 reg = FDI_RX_IIR(pipe);
3166 temp = I915_READ(reg);
3167 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3168 if (temp & FDI_RX_SYMBOL_LOCK) {
3169 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3170 DRM_DEBUG_KMS("FDI train 2 done.\n");
3171 break;
3172 }
3173 udelay(50);
3174 }
3175 if (retry < 5)
3176 break;
3177 }
3178 if (i == 4)
3179 DRM_ERROR("FDI train 2 fail!\n");
3180
3181 DRM_DEBUG_KMS("FDI train done.\n");
3182 }
3183
3184 /* Manual link training for Ivy Bridge A0 parts */
3185 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3186 {
3187 struct drm_device *dev = crtc->dev;
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3190 int pipe = intel_crtc->pipe;
3191 u32 reg, temp, i, j;
3192
3193 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3194 for train result */
3195 reg = FDI_RX_IMR(pipe);
3196 temp = I915_READ(reg);
3197 temp &= ~FDI_RX_SYMBOL_LOCK;
3198 temp &= ~FDI_RX_BIT_LOCK;
3199 I915_WRITE(reg, temp);
3200
3201 POSTING_READ(reg);
3202 udelay(150);
3203
3204 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3205 I915_READ(FDI_RX_IIR(pipe)));
3206
3207 /* Try each vswing and preemphasis setting twice before moving on */
3208 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3209 /* disable first in case we need to retry */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3213 temp &= ~FDI_TX_ENABLE;
3214 I915_WRITE(reg, temp);
3215
3216 reg = FDI_RX_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~FDI_LINK_TRAIN_AUTO;
3219 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3220 temp &= ~FDI_RX_ENABLE;
3221 I915_WRITE(reg, temp);
3222
3223 /* enable CPU FDI TX and PCH FDI RX */
3224 reg = FDI_TX_CTL(pipe);
3225 temp = I915_READ(reg);
3226 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3227 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3228 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3229 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3230 temp |= snb_b_fdi_train_param[j/2];
3231 temp |= FDI_COMPOSITE_SYNC;
3232 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3233
3234 I915_WRITE(FDI_RX_MISC(pipe),
3235 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3236
3237 reg = FDI_RX_CTL(pipe);
3238 temp = I915_READ(reg);
3239 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3240 temp |= FDI_COMPOSITE_SYNC;
3241 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3242
3243 POSTING_READ(reg);
3244 udelay(1); /* should be 0.5us */
3245
3246 for (i = 0; i < 4; i++) {
3247 reg = FDI_RX_IIR(pipe);
3248 temp = I915_READ(reg);
3249 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3250
3251 if (temp & FDI_RX_BIT_LOCK ||
3252 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3253 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3254 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3255 i);
3256 break;
3257 }
3258 udelay(1); /* should be 0.5us */
3259 }
3260 if (i == 4) {
3261 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3262 continue;
3263 }
3264
3265 /* Train 2 */
3266 reg = FDI_TX_CTL(pipe);
3267 temp = I915_READ(reg);
3268 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3269 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3270 I915_WRITE(reg, temp);
3271
3272 reg = FDI_RX_CTL(pipe);
3273 temp = I915_READ(reg);
3274 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3275 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3276 I915_WRITE(reg, temp);
3277
3278 POSTING_READ(reg);
3279 udelay(2); /* should be 1.5us */
3280
3281 for (i = 0; i < 4; i++) {
3282 reg = FDI_RX_IIR(pipe);
3283 temp = I915_READ(reg);
3284 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3285
3286 if (temp & FDI_RX_SYMBOL_LOCK ||
3287 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3288 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3289 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3290 i);
3291 goto train_done;
3292 }
3293 udelay(2); /* should be 1.5us */
3294 }
3295 if (i == 4)
3296 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3297 }
3298
3299 train_done:
3300 DRM_DEBUG_KMS("FDI train done.\n");
3301 }
3302
3303 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3304 {
3305 struct drm_device *dev = intel_crtc->base.dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 int pipe = intel_crtc->pipe;
3308 u32 reg, temp;
3309
3310
3311 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3312 reg = FDI_RX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3315 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3316 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3317 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3318
3319 POSTING_READ(reg);
3320 udelay(200);
3321
3322 /* Switch from Rawclk to PCDclk */
3323 temp = I915_READ(reg);
3324 I915_WRITE(reg, temp | FDI_PCDCLK);
3325
3326 POSTING_READ(reg);
3327 udelay(200);
3328
3329 /* Enable CPU FDI TX PLL, always on for Ironlake */
3330 reg = FDI_TX_CTL(pipe);
3331 temp = I915_READ(reg);
3332 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3333 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3334
3335 POSTING_READ(reg);
3336 udelay(100);
3337 }
3338 }
3339
3340 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3341 {
3342 struct drm_device *dev = intel_crtc->base.dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 int pipe = intel_crtc->pipe;
3345 u32 reg, temp;
3346
3347 /* Switch from PCDclk to Rawclk */
3348 reg = FDI_RX_CTL(pipe);
3349 temp = I915_READ(reg);
3350 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3351
3352 /* Disable CPU FDI TX PLL */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3356
3357 POSTING_READ(reg);
3358 udelay(100);
3359
3360 reg = FDI_RX_CTL(pipe);
3361 temp = I915_READ(reg);
3362 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3363
3364 /* Wait for the clocks to turn off. */
3365 POSTING_READ(reg);
3366 udelay(100);
3367 }
3368
3369 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3370 {
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3374 int pipe = intel_crtc->pipe;
3375 u32 reg, temp;
3376
3377 /* disable CPU FDI tx and PCH FDI rx */
3378 reg = FDI_TX_CTL(pipe);
3379 temp = I915_READ(reg);
3380 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3381 POSTING_READ(reg);
3382
3383 reg = FDI_RX_CTL(pipe);
3384 temp = I915_READ(reg);
3385 temp &= ~(0x7 << 16);
3386 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3387 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3388
3389 POSTING_READ(reg);
3390 udelay(100);
3391
3392 /* Ironlake workaround, disable clock pointer after downing FDI */
3393 if (HAS_PCH_IBX(dev))
3394 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3395
3396 /* still set train pattern 1 */
3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_LINK_TRAIN_NONE;
3400 temp |= FDI_LINK_TRAIN_PATTERN_1;
3401 I915_WRITE(reg, temp);
3402
3403 reg = FDI_RX_CTL(pipe);
3404 temp = I915_READ(reg);
3405 if (HAS_PCH_CPT(dev)) {
3406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3407 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3408 } else {
3409 temp &= ~FDI_LINK_TRAIN_NONE;
3410 temp |= FDI_LINK_TRAIN_PATTERN_1;
3411 }
3412 /* BPC in FDI rx is consistent with that in PIPECONF */
3413 temp &= ~(0x07 << 16);
3414 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3415 I915_WRITE(reg, temp);
3416
3417 POSTING_READ(reg);
3418 udelay(100);
3419 }
3420
3421 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3422 {
3423 struct intel_crtc *crtc;
3424
3425 /* Note that we don't need to be called with mode_config.lock here
3426 * as our list of CRTC objects is static for the lifetime of the
3427 * device and so cannot disappear as we iterate. Similarly, we can
3428 * happily treat the predicates as racy, atomic checks as userspace
3429 * cannot claim and pin a new fb without at least acquring the
3430 * struct_mutex and so serialising with us.
3431 */
3432 for_each_intel_crtc(dev, crtc) {
3433 if (atomic_read(&crtc->unpin_work_count) == 0)
3434 continue;
3435
3436 if (crtc->unpin_work)
3437 intel_wait_for_vblank(dev, crtc->pipe);
3438
3439 return true;
3440 }
3441
3442 return false;
3443 }
3444
3445 static void page_flip_completed(struct intel_crtc *intel_crtc)
3446 {
3447 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3448 struct intel_unpin_work *work = intel_crtc->unpin_work;
3449
3450 /* ensure that the unpin work is consistent wrt ->pending. */
3451 smp_rmb();
3452 intel_crtc->unpin_work = NULL;
3453
3454 if (work->event)
3455 drm_send_vblank_event(intel_crtc->base.dev,
3456 intel_crtc->pipe,
3457 work->event);
3458
3459 drm_crtc_vblank_put(&intel_crtc->base);
3460
3461 wake_up_all(&dev_priv->pending_flip_queue);
3462 queue_work(dev_priv->wq, &work->work);
3463
3464 trace_i915_flip_complete(intel_crtc->plane,
3465 work->pending_flip_obj);
3466 }
3467
3468 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3469 {
3470 struct drm_device *dev = crtc->dev;
3471 struct drm_i915_private *dev_priv = dev->dev_private;
3472
3473 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3474 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3475 !intel_crtc_has_pending_flip(crtc),
3476 60*HZ) == 0)) {
3477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3478 unsigned long flags;
3479
3480 spin_lock_irqsave(&dev->event_lock, flags);
3481 if (intel_crtc->unpin_work) {
3482 WARN_ONCE(1, "Removing stuck page flip\n");
3483 page_flip_completed(intel_crtc);
3484 }
3485 spin_unlock_irqrestore(&dev->event_lock, flags);
3486 }
3487
3488 if (crtc->primary->fb) {
3489 mutex_lock(&dev->struct_mutex);
3490 intel_finish_fb(crtc->primary->fb);
3491 mutex_unlock(&dev->struct_mutex);
3492 }
3493 }
3494
3495 /* Program iCLKIP clock to the desired frequency */
3496 static void lpt_program_iclkip(struct drm_crtc *crtc)
3497 {
3498 struct drm_device *dev = crtc->dev;
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3501 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3502 u32 temp;
3503
3504 mutex_lock(&dev_priv->dpio_lock);
3505
3506 /* It is necessary to ungate the pixclk gate prior to programming
3507 * the divisors, and gate it back when it is done.
3508 */
3509 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3510
3511 /* Disable SSCCTL */
3512 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3513 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3514 SBI_SSCCTL_DISABLE,
3515 SBI_ICLK);
3516
3517 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3518 if (clock == 20000) {
3519 auxdiv = 1;
3520 divsel = 0x41;
3521 phaseinc = 0x20;
3522 } else {
3523 /* The iCLK virtual clock root frequency is in MHz,
3524 * but the adjusted_mode->crtc_clock in in KHz. To get the
3525 * divisors, it is necessary to divide one by another, so we
3526 * convert the virtual clock precision to KHz here for higher
3527 * precision.
3528 */
3529 u32 iclk_virtual_root_freq = 172800 * 1000;
3530 u32 iclk_pi_range = 64;
3531 u32 desired_divisor, msb_divisor_value, pi_value;
3532
3533 desired_divisor = (iclk_virtual_root_freq / clock);
3534 msb_divisor_value = desired_divisor / iclk_pi_range;
3535 pi_value = desired_divisor % iclk_pi_range;
3536
3537 auxdiv = 0;
3538 divsel = msb_divisor_value - 2;
3539 phaseinc = pi_value;
3540 }
3541
3542 /* This should not happen with any sane values */
3543 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3544 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3545 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3546 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3547
3548 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3549 clock,
3550 auxdiv,
3551 divsel,
3552 phasedir,
3553 phaseinc);
3554
3555 /* Program SSCDIVINTPHASE6 */
3556 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3557 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3558 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3559 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3560 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3561 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3562 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3563 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3564
3565 /* Program SSCAUXDIV */
3566 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3567 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3568 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3569 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3570
3571 /* Enable modulator and associated divider */
3572 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3573 temp &= ~SBI_SSCCTL_DISABLE;
3574 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3575
3576 /* Wait for initialization time */
3577 udelay(24);
3578
3579 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3580
3581 mutex_unlock(&dev_priv->dpio_lock);
3582 }
3583
3584 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3585 enum pipe pch_transcoder)
3586 {
3587 struct drm_device *dev = crtc->base.dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3590
3591 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3592 I915_READ(HTOTAL(cpu_transcoder)));
3593 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3594 I915_READ(HBLANK(cpu_transcoder)));
3595 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3596 I915_READ(HSYNC(cpu_transcoder)));
3597
3598 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3599 I915_READ(VTOTAL(cpu_transcoder)));
3600 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3601 I915_READ(VBLANK(cpu_transcoder)));
3602 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3603 I915_READ(VSYNC(cpu_transcoder)));
3604 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3605 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3606 }
3607
3608 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3609 {
3610 struct drm_i915_private *dev_priv = dev->dev_private;
3611 uint32_t temp;
3612
3613 temp = I915_READ(SOUTH_CHICKEN1);
3614 if (temp & FDI_BC_BIFURCATION_SELECT)
3615 return;
3616
3617 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3618 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3619
3620 temp |= FDI_BC_BIFURCATION_SELECT;
3621 DRM_DEBUG_KMS("enabling fdi C rx\n");
3622 I915_WRITE(SOUTH_CHICKEN1, temp);
3623 POSTING_READ(SOUTH_CHICKEN1);
3624 }
3625
3626 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3627 {
3628 struct drm_device *dev = intel_crtc->base.dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630
3631 switch (intel_crtc->pipe) {
3632 case PIPE_A:
3633 break;
3634 case PIPE_B:
3635 if (intel_crtc->config.fdi_lanes > 2)
3636 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3637 else
3638 cpt_enable_fdi_bc_bifurcation(dev);
3639
3640 break;
3641 case PIPE_C:
3642 cpt_enable_fdi_bc_bifurcation(dev);
3643
3644 break;
3645 default:
3646 BUG();
3647 }
3648 }
3649
3650 /*
3651 * Enable PCH resources required for PCH ports:
3652 * - PCH PLLs
3653 * - FDI training & RX/TX
3654 * - update transcoder timings
3655 * - DP transcoding bits
3656 * - transcoder
3657 */
3658 static void ironlake_pch_enable(struct drm_crtc *crtc)
3659 {
3660 struct drm_device *dev = crtc->dev;
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663 int pipe = intel_crtc->pipe;
3664 u32 reg, temp;
3665
3666 assert_pch_transcoder_disabled(dev_priv, pipe);
3667
3668 if (IS_IVYBRIDGE(dev))
3669 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3670
3671 /* Write the TU size bits before fdi link training, so that error
3672 * detection works. */
3673 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3674 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3675
3676 /* For PCH output, training FDI link */
3677 dev_priv->display.fdi_link_train(crtc);
3678
3679 /* We need to program the right clock selection before writing the pixel
3680 * mutliplier into the DPLL. */
3681 if (HAS_PCH_CPT(dev)) {
3682 u32 sel;
3683
3684 temp = I915_READ(PCH_DPLL_SEL);
3685 temp |= TRANS_DPLL_ENABLE(pipe);
3686 sel = TRANS_DPLLB_SEL(pipe);
3687 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3688 temp |= sel;
3689 else
3690 temp &= ~sel;
3691 I915_WRITE(PCH_DPLL_SEL, temp);
3692 }
3693
3694 /* XXX: pch pll's can be enabled any time before we enable the PCH
3695 * transcoder, and we actually should do this to not upset any PCH
3696 * transcoder that already use the clock when we share it.
3697 *
3698 * Note that enable_shared_dpll tries to do the right thing, but
3699 * get_shared_dpll unconditionally resets the pll - we need that to have
3700 * the right LVDS enable sequence. */
3701 intel_enable_shared_dpll(intel_crtc);
3702
3703 /* set transcoder timing, panel must allow it */
3704 assert_panel_unlocked(dev_priv, pipe);
3705 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3706
3707 intel_fdi_normal_train(crtc);
3708
3709 /* For PCH DP, enable TRANS_DP_CTL */
3710 if (HAS_PCH_CPT(dev) &&
3711 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3712 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3713 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3714 reg = TRANS_DP_CTL(pipe);
3715 temp = I915_READ(reg);
3716 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3717 TRANS_DP_SYNC_MASK |
3718 TRANS_DP_BPC_MASK);
3719 temp |= (TRANS_DP_OUTPUT_ENABLE |
3720 TRANS_DP_ENH_FRAMING);
3721 temp |= bpc << 9; /* same format but at 11:9 */
3722
3723 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3724 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3725 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3726 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3727
3728 switch (intel_trans_dp_port_sel(crtc)) {
3729 case PCH_DP_B:
3730 temp |= TRANS_DP_PORT_SEL_B;
3731 break;
3732 case PCH_DP_C:
3733 temp |= TRANS_DP_PORT_SEL_C;
3734 break;
3735 case PCH_DP_D:
3736 temp |= TRANS_DP_PORT_SEL_D;
3737 break;
3738 default:
3739 BUG();
3740 }
3741
3742 I915_WRITE(reg, temp);
3743 }
3744
3745 ironlake_enable_pch_transcoder(dev_priv, pipe);
3746 }
3747
3748 static void lpt_pch_enable(struct drm_crtc *crtc)
3749 {
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3754
3755 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3756
3757 lpt_program_iclkip(crtc);
3758
3759 /* Set transcoder timing. */
3760 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3761
3762 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3763 }
3764
3765 void intel_put_shared_dpll(struct intel_crtc *crtc)
3766 {
3767 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3768
3769 if (pll == NULL)
3770 return;
3771
3772 if (pll->refcount == 0) {
3773 WARN(1, "bad %s refcount\n", pll->name);
3774 return;
3775 }
3776
3777 if (--pll->refcount == 0) {
3778 WARN_ON(pll->on);
3779 WARN_ON(pll->active);
3780 }
3781
3782 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3783 }
3784
3785 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3786 {
3787 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3788 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3789 enum intel_dpll_id i;
3790
3791 if (pll) {
3792 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3793 crtc->base.base.id, pll->name);
3794 intel_put_shared_dpll(crtc);
3795 }
3796
3797 if (HAS_PCH_IBX(dev_priv->dev)) {
3798 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3799 i = (enum intel_dpll_id) crtc->pipe;
3800 pll = &dev_priv->shared_dplls[i];
3801
3802 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3803 crtc->base.base.id, pll->name);
3804
3805 WARN_ON(pll->refcount);
3806
3807 goto found;
3808 }
3809
3810 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3811 pll = &dev_priv->shared_dplls[i];
3812
3813 /* Only want to check enabled timings first */
3814 if (pll->refcount == 0)
3815 continue;
3816
3817 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3818 sizeof(pll->hw_state)) == 0) {
3819 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3820 crtc->base.base.id,
3821 pll->name, pll->refcount, pll->active);
3822
3823 goto found;
3824 }
3825 }
3826
3827 /* Ok no matching timings, maybe there's a free one? */
3828 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3829 pll = &dev_priv->shared_dplls[i];
3830 if (pll->refcount == 0) {
3831 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3832 crtc->base.base.id, pll->name);
3833 goto found;
3834 }
3835 }
3836
3837 return NULL;
3838
3839 found:
3840 if (pll->refcount == 0)
3841 pll->hw_state = crtc->config.dpll_hw_state;
3842
3843 crtc->config.shared_dpll = i;
3844 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3845 pipe_name(crtc->pipe));
3846
3847 pll->refcount++;
3848
3849 return pll;
3850 }
3851
3852 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3853 {
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 int dslreg = PIPEDSL(pipe);
3856 u32 temp;
3857
3858 temp = I915_READ(dslreg);
3859 udelay(500);
3860 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3861 if (wait_for(I915_READ(dslreg) != temp, 5))
3862 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3863 }
3864 }
3865
3866 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3867 {
3868 struct drm_device *dev = crtc->base.dev;
3869 struct drm_i915_private *dev_priv = dev->dev_private;
3870 int pipe = crtc->pipe;
3871
3872 if (crtc->config.pch_pfit.enabled) {
3873 /* Force use of hard-coded filter coefficients
3874 * as some pre-programmed values are broken,
3875 * e.g. x201.
3876 */
3877 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3878 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3879 PF_PIPE_SEL_IVB(pipe));
3880 else
3881 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3882 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3883 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3884 }
3885 }
3886
3887 static void intel_enable_planes(struct drm_crtc *crtc)
3888 {
3889 struct drm_device *dev = crtc->dev;
3890 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3891 struct drm_plane *plane;
3892 struct intel_plane *intel_plane;
3893
3894 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3895 intel_plane = to_intel_plane(plane);
3896 if (intel_plane->pipe == pipe)
3897 intel_plane_restore(&intel_plane->base);
3898 }
3899 }
3900
3901 static void intel_disable_planes(struct drm_crtc *crtc)
3902 {
3903 struct drm_device *dev = crtc->dev;
3904 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3905 struct drm_plane *plane;
3906 struct intel_plane *intel_plane;
3907
3908 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3909 intel_plane = to_intel_plane(plane);
3910 if (intel_plane->pipe == pipe)
3911 intel_plane_disable(&intel_plane->base);
3912 }
3913 }
3914
3915 void hsw_enable_ips(struct intel_crtc *crtc)
3916 {
3917 struct drm_device *dev = crtc->base.dev;
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919
3920 if (!crtc->config.ips_enabled)
3921 return;
3922
3923 /* We can only enable IPS after we enable a plane and wait for a vblank */
3924 intel_wait_for_vblank(dev, crtc->pipe);
3925
3926 assert_plane_enabled(dev_priv, crtc->plane);
3927 if (IS_BROADWELL(dev)) {
3928 mutex_lock(&dev_priv->rps.hw_lock);
3929 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3930 mutex_unlock(&dev_priv->rps.hw_lock);
3931 /* Quoting Art Runyan: "its not safe to expect any particular
3932 * value in IPS_CTL bit 31 after enabling IPS through the
3933 * mailbox." Moreover, the mailbox may return a bogus state,
3934 * so we need to just enable it and continue on.
3935 */
3936 } else {
3937 I915_WRITE(IPS_CTL, IPS_ENABLE);
3938 /* The bit only becomes 1 in the next vblank, so this wait here
3939 * is essentially intel_wait_for_vblank. If we don't have this
3940 * and don't wait for vblanks until the end of crtc_enable, then
3941 * the HW state readout code will complain that the expected
3942 * IPS_CTL value is not the one we read. */
3943 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3944 DRM_ERROR("Timed out waiting for IPS enable\n");
3945 }
3946 }
3947
3948 void hsw_disable_ips(struct intel_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->base.dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952
3953 if (!crtc->config.ips_enabled)
3954 return;
3955
3956 assert_plane_enabled(dev_priv, crtc->plane);
3957 if (IS_BROADWELL(dev)) {
3958 mutex_lock(&dev_priv->rps.hw_lock);
3959 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3960 mutex_unlock(&dev_priv->rps.hw_lock);
3961 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3962 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3963 DRM_ERROR("Timed out waiting for IPS disable\n");
3964 } else {
3965 I915_WRITE(IPS_CTL, 0);
3966 POSTING_READ(IPS_CTL);
3967 }
3968
3969 /* We need to wait for a vblank before we can disable the plane. */
3970 intel_wait_for_vblank(dev, crtc->pipe);
3971 }
3972
3973 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3974 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3975 {
3976 struct drm_device *dev = crtc->dev;
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3979 enum pipe pipe = intel_crtc->pipe;
3980 int palreg = PALETTE(pipe);
3981 int i;
3982 bool reenable_ips = false;
3983
3984 /* The clocks have to be on to load the palette. */
3985 if (!crtc->enabled || !intel_crtc->active)
3986 return;
3987
3988 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3989 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3990 assert_dsi_pll_enabled(dev_priv);
3991 else
3992 assert_pll_enabled(dev_priv, pipe);
3993 }
3994
3995 /* use legacy palette for Ironlake */
3996 if (!HAS_GMCH_DISPLAY(dev))
3997 palreg = LGC_PALETTE(pipe);
3998
3999 /* Workaround : Do not read or write the pipe palette/gamma data while
4000 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4001 */
4002 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4003 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4004 GAMMA_MODE_MODE_SPLIT)) {
4005 hsw_disable_ips(intel_crtc);
4006 reenable_ips = true;
4007 }
4008
4009 for (i = 0; i < 256; i++) {
4010 I915_WRITE(palreg + 4 * i,
4011 (intel_crtc->lut_r[i] << 16) |
4012 (intel_crtc->lut_g[i] << 8) |
4013 intel_crtc->lut_b[i]);
4014 }
4015
4016 if (reenable_ips)
4017 hsw_enable_ips(intel_crtc);
4018 }
4019
4020 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4021 {
4022 if (!enable && intel_crtc->overlay) {
4023 struct drm_device *dev = intel_crtc->base.dev;
4024 struct drm_i915_private *dev_priv = dev->dev_private;
4025
4026 mutex_lock(&dev->struct_mutex);
4027 dev_priv->mm.interruptible = false;
4028 (void) intel_overlay_switch_off(intel_crtc->overlay);
4029 dev_priv->mm.interruptible = true;
4030 mutex_unlock(&dev->struct_mutex);
4031 }
4032
4033 /* Let userspace switch the overlay on again. In most cases userspace
4034 * has to recompute where to put it anyway.
4035 */
4036 }
4037
4038 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4039 {
4040 struct drm_device *dev = crtc->dev;
4041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4042 int pipe = intel_crtc->pipe;
4043
4044 assert_vblank_disabled(crtc);
4045
4046 drm_vblank_on(dev, pipe);
4047
4048 intel_enable_primary_hw_plane(crtc->primary, crtc);
4049 intel_enable_planes(crtc);
4050 intel_crtc_update_cursor(crtc, true);
4051 intel_crtc_dpms_overlay(intel_crtc, true);
4052
4053 hsw_enable_ips(intel_crtc);
4054
4055 mutex_lock(&dev->struct_mutex);
4056 intel_update_fbc(dev);
4057 mutex_unlock(&dev->struct_mutex);
4058
4059 /*
4060 * FIXME: Once we grow proper nuclear flip support out of this we need
4061 * to compute the mask of flip planes precisely. For the time being
4062 * consider this a flip from a NULL plane.
4063 */
4064 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4065 }
4066
4067 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4068 {
4069 struct drm_device *dev = crtc->dev;
4070 struct drm_i915_private *dev_priv = dev->dev_private;
4071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4072 int pipe = intel_crtc->pipe;
4073 int plane = intel_crtc->plane;
4074
4075 intel_crtc_wait_for_pending_flips(crtc);
4076
4077 if (dev_priv->fbc.plane == plane)
4078 intel_disable_fbc(dev);
4079
4080 hsw_disable_ips(intel_crtc);
4081
4082 intel_crtc_dpms_overlay(intel_crtc, false);
4083 intel_crtc_update_cursor(crtc, false);
4084 intel_disable_planes(crtc);
4085 intel_disable_primary_hw_plane(crtc->primary, crtc);
4086
4087 /*
4088 * FIXME: Once we grow proper nuclear flip support out of this we need
4089 * to compute the mask of flip planes precisely. For the time being
4090 * consider this a flip to a NULL plane.
4091 */
4092 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4093
4094 drm_vblank_off(dev, pipe);
4095
4096 assert_vblank_disabled(crtc);
4097 }
4098
4099 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4100 {
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4104 struct intel_encoder *encoder;
4105 int pipe = intel_crtc->pipe;
4106
4107 WARN_ON(!crtc->enabled);
4108
4109 if (intel_crtc->active)
4110 return;
4111
4112 if (intel_crtc->config.has_pch_encoder)
4113 intel_prepare_shared_dpll(intel_crtc);
4114
4115 if (intel_crtc->config.has_dp_encoder)
4116 intel_dp_set_m_n(intel_crtc);
4117
4118 intel_set_pipe_timings(intel_crtc);
4119
4120 if (intel_crtc->config.has_pch_encoder) {
4121 intel_cpu_transcoder_set_m_n(intel_crtc,
4122 &intel_crtc->config.fdi_m_n, NULL);
4123 }
4124
4125 ironlake_set_pipeconf(crtc);
4126
4127 intel_crtc->active = true;
4128
4129 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4130 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4131
4132 for_each_encoder_on_crtc(dev, crtc, encoder)
4133 if (encoder->pre_enable)
4134 encoder->pre_enable(encoder);
4135
4136 if (intel_crtc->config.has_pch_encoder) {
4137 /* Note: FDI PLL enabling _must_ be done before we enable the
4138 * cpu pipes, hence this is separate from all the other fdi/pch
4139 * enabling. */
4140 ironlake_fdi_pll_enable(intel_crtc);
4141 } else {
4142 assert_fdi_tx_disabled(dev_priv, pipe);
4143 assert_fdi_rx_disabled(dev_priv, pipe);
4144 }
4145
4146 ironlake_pfit_enable(intel_crtc);
4147
4148 /*
4149 * On ILK+ LUT must be loaded before the pipe is running but with
4150 * clocks enabled
4151 */
4152 intel_crtc_load_lut(crtc);
4153
4154 intel_update_watermarks(crtc);
4155 intel_enable_pipe(intel_crtc);
4156
4157 if (intel_crtc->config.has_pch_encoder)
4158 ironlake_pch_enable(crtc);
4159
4160 for_each_encoder_on_crtc(dev, crtc, encoder)
4161 encoder->enable(encoder);
4162
4163 if (HAS_PCH_CPT(dev))
4164 cpt_verify_modeset(dev, intel_crtc->pipe);
4165
4166 intel_crtc_enable_planes(crtc);
4167 }
4168
4169 /* IPS only exists on ULT machines and is tied to pipe A. */
4170 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4171 {
4172 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4173 }
4174
4175 /*
4176 * This implements the workaround described in the "notes" section of the mode
4177 * set sequence documentation. When going from no pipes or single pipe to
4178 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4179 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4180 */
4181 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4182 {
4183 struct drm_device *dev = crtc->base.dev;
4184 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4185
4186 /* We want to get the other_active_crtc only if there's only 1 other
4187 * active crtc. */
4188 for_each_intel_crtc(dev, crtc_it) {
4189 if (!crtc_it->active || crtc_it == crtc)
4190 continue;
4191
4192 if (other_active_crtc)
4193 return;
4194
4195 other_active_crtc = crtc_it;
4196 }
4197 if (!other_active_crtc)
4198 return;
4199
4200 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4201 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4202 }
4203
4204 static void haswell_crtc_enable(struct drm_crtc *crtc)
4205 {
4206 struct drm_device *dev = crtc->dev;
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209 struct intel_encoder *encoder;
4210 int pipe = intel_crtc->pipe;
4211
4212 WARN_ON(!crtc->enabled);
4213
4214 if (intel_crtc->active)
4215 return;
4216
4217 if (intel_crtc_to_shared_dpll(intel_crtc))
4218 intel_enable_shared_dpll(intel_crtc);
4219
4220 if (intel_crtc->config.has_dp_encoder)
4221 intel_dp_set_m_n(intel_crtc);
4222
4223 intel_set_pipe_timings(intel_crtc);
4224
4225 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4226 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4227 intel_crtc->config.pixel_multiplier - 1);
4228 }
4229
4230 if (intel_crtc->config.has_pch_encoder) {
4231 intel_cpu_transcoder_set_m_n(intel_crtc,
4232 &intel_crtc->config.fdi_m_n, NULL);
4233 }
4234
4235 haswell_set_pipeconf(crtc);
4236
4237 intel_set_pipe_csc(crtc);
4238
4239 intel_crtc->active = true;
4240
4241 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4242 for_each_encoder_on_crtc(dev, crtc, encoder)
4243 if (encoder->pre_enable)
4244 encoder->pre_enable(encoder);
4245
4246 if (intel_crtc->config.has_pch_encoder) {
4247 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4248 dev_priv->display.fdi_link_train(crtc);
4249 }
4250
4251 intel_ddi_enable_pipe_clock(intel_crtc);
4252
4253 ironlake_pfit_enable(intel_crtc);
4254
4255 /*
4256 * On ILK+ LUT must be loaded before the pipe is running but with
4257 * clocks enabled
4258 */
4259 intel_crtc_load_lut(crtc);
4260
4261 intel_ddi_set_pipe_settings(crtc);
4262 intel_ddi_enable_transcoder_func(crtc);
4263
4264 intel_update_watermarks(crtc);
4265 intel_enable_pipe(intel_crtc);
4266
4267 if (intel_crtc->config.has_pch_encoder)
4268 lpt_pch_enable(crtc);
4269
4270 if (intel_crtc->config.dp_encoder_is_mst)
4271 intel_ddi_set_vc_payload_alloc(crtc, true);
4272
4273 for_each_encoder_on_crtc(dev, crtc, encoder) {
4274 encoder->enable(encoder);
4275 intel_opregion_notify_encoder(encoder, true);
4276 }
4277
4278 /* If we change the relative order between pipe/planes enabling, we need
4279 * to change the workaround. */
4280 haswell_mode_set_planes_workaround(intel_crtc);
4281 intel_crtc_enable_planes(crtc);
4282 }
4283
4284 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4285 {
4286 struct drm_device *dev = crtc->base.dev;
4287 struct drm_i915_private *dev_priv = dev->dev_private;
4288 int pipe = crtc->pipe;
4289
4290 /* To avoid upsetting the power well on haswell only disable the pfit if
4291 * it's in use. The hw state code will make sure we get this right. */
4292 if (crtc->config.pch_pfit.enabled) {
4293 I915_WRITE(PF_CTL(pipe), 0);
4294 I915_WRITE(PF_WIN_POS(pipe), 0);
4295 I915_WRITE(PF_WIN_SZ(pipe), 0);
4296 }
4297 }
4298
4299 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4300 {
4301 struct drm_device *dev = crtc->dev;
4302 struct drm_i915_private *dev_priv = dev->dev_private;
4303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4304 struct intel_encoder *encoder;
4305 int pipe = intel_crtc->pipe;
4306 u32 reg, temp;
4307
4308 if (!intel_crtc->active)
4309 return;
4310
4311 intel_crtc_disable_planes(crtc);
4312
4313 for_each_encoder_on_crtc(dev, crtc, encoder)
4314 encoder->disable(encoder);
4315
4316 if (intel_crtc->config.has_pch_encoder)
4317 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4318
4319 intel_disable_pipe(intel_crtc);
4320
4321 ironlake_pfit_disable(intel_crtc);
4322
4323 for_each_encoder_on_crtc(dev, crtc, encoder)
4324 if (encoder->post_disable)
4325 encoder->post_disable(encoder);
4326
4327 if (intel_crtc->config.has_pch_encoder) {
4328 ironlake_fdi_disable(crtc);
4329
4330 ironlake_disable_pch_transcoder(dev_priv, pipe);
4331 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4332
4333 if (HAS_PCH_CPT(dev)) {
4334 /* disable TRANS_DP_CTL */
4335 reg = TRANS_DP_CTL(pipe);
4336 temp = I915_READ(reg);
4337 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4338 TRANS_DP_PORT_SEL_MASK);
4339 temp |= TRANS_DP_PORT_SEL_NONE;
4340 I915_WRITE(reg, temp);
4341
4342 /* disable DPLL_SEL */
4343 temp = I915_READ(PCH_DPLL_SEL);
4344 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4345 I915_WRITE(PCH_DPLL_SEL, temp);
4346 }
4347
4348 /* disable PCH DPLL */
4349 intel_disable_shared_dpll(intel_crtc);
4350
4351 ironlake_fdi_pll_disable(intel_crtc);
4352 }
4353
4354 intel_crtc->active = false;
4355 intel_update_watermarks(crtc);
4356
4357 mutex_lock(&dev->struct_mutex);
4358 intel_update_fbc(dev);
4359 mutex_unlock(&dev->struct_mutex);
4360 }
4361
4362 static void haswell_crtc_disable(struct drm_crtc *crtc)
4363 {
4364 struct drm_device *dev = crtc->dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4367 struct intel_encoder *encoder;
4368 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4369
4370 if (!intel_crtc->active)
4371 return;
4372
4373 intel_crtc_disable_planes(crtc);
4374
4375 for_each_encoder_on_crtc(dev, crtc, encoder) {
4376 intel_opregion_notify_encoder(encoder, false);
4377 encoder->disable(encoder);
4378 }
4379
4380 if (intel_crtc->config.has_pch_encoder)
4381 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4382 intel_disable_pipe(intel_crtc);
4383
4384 if (intel_crtc->config.dp_encoder_is_mst)
4385 intel_ddi_set_vc_payload_alloc(crtc, false);
4386
4387 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4388
4389 ironlake_pfit_disable(intel_crtc);
4390
4391 intel_ddi_disable_pipe_clock(intel_crtc);
4392
4393 if (intel_crtc->config.has_pch_encoder) {
4394 lpt_disable_pch_transcoder(dev_priv);
4395 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4396 intel_ddi_fdi_disable(crtc);
4397 }
4398
4399 for_each_encoder_on_crtc(dev, crtc, encoder)
4400 if (encoder->post_disable)
4401 encoder->post_disable(encoder);
4402
4403 intel_crtc->active = false;
4404 intel_update_watermarks(crtc);
4405
4406 mutex_lock(&dev->struct_mutex);
4407 intel_update_fbc(dev);
4408 mutex_unlock(&dev->struct_mutex);
4409
4410 if (intel_crtc_to_shared_dpll(intel_crtc))
4411 intel_disable_shared_dpll(intel_crtc);
4412 }
4413
4414 static void ironlake_crtc_off(struct drm_crtc *crtc)
4415 {
4416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4417 intel_put_shared_dpll(intel_crtc);
4418 }
4419
4420
4421 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4422 {
4423 struct drm_device *dev = crtc->base.dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 struct intel_crtc_config *pipe_config = &crtc->config;
4426
4427 if (!crtc->config.gmch_pfit.control)
4428 return;
4429
4430 /*
4431 * The panel fitter should only be adjusted whilst the pipe is disabled,
4432 * according to register description and PRM.
4433 */
4434 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4435 assert_pipe_disabled(dev_priv, crtc->pipe);
4436
4437 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4438 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4439
4440 /* Border color in case we don't scale up to the full screen. Black by
4441 * default, change to something else for debugging. */
4442 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4443 }
4444
4445 static enum intel_display_power_domain port_to_power_domain(enum port port)
4446 {
4447 switch (port) {
4448 case PORT_A:
4449 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4450 case PORT_B:
4451 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4452 case PORT_C:
4453 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4454 case PORT_D:
4455 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4456 default:
4457 WARN_ON_ONCE(1);
4458 return POWER_DOMAIN_PORT_OTHER;
4459 }
4460 }
4461
4462 #define for_each_power_domain(domain, mask) \
4463 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4464 if ((1 << (domain)) & (mask))
4465
4466 enum intel_display_power_domain
4467 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4468 {
4469 struct drm_device *dev = intel_encoder->base.dev;
4470 struct intel_digital_port *intel_dig_port;
4471
4472 switch (intel_encoder->type) {
4473 case INTEL_OUTPUT_UNKNOWN:
4474 /* Only DDI platforms should ever use this output type */
4475 WARN_ON_ONCE(!HAS_DDI(dev));
4476 case INTEL_OUTPUT_DISPLAYPORT:
4477 case INTEL_OUTPUT_HDMI:
4478 case INTEL_OUTPUT_EDP:
4479 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4480 return port_to_power_domain(intel_dig_port->port);
4481 case INTEL_OUTPUT_DP_MST:
4482 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4483 return port_to_power_domain(intel_dig_port->port);
4484 case INTEL_OUTPUT_ANALOG:
4485 return POWER_DOMAIN_PORT_CRT;
4486 case INTEL_OUTPUT_DSI:
4487 return POWER_DOMAIN_PORT_DSI;
4488 default:
4489 return POWER_DOMAIN_PORT_OTHER;
4490 }
4491 }
4492
4493 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4494 {
4495 struct drm_device *dev = crtc->dev;
4496 struct intel_encoder *intel_encoder;
4497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4498 enum pipe pipe = intel_crtc->pipe;
4499 unsigned long mask;
4500 enum transcoder transcoder;
4501
4502 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4503
4504 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4505 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4506 if (intel_crtc->config.pch_pfit.enabled ||
4507 intel_crtc->config.pch_pfit.force_thru)
4508 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4509
4510 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4511 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4512
4513 return mask;
4514 }
4515
4516 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4517 bool enable)
4518 {
4519 if (dev_priv->power_domains.init_power_on == enable)
4520 return;
4521
4522 if (enable)
4523 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4524 else
4525 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4526
4527 dev_priv->power_domains.init_power_on = enable;
4528 }
4529
4530 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4531 {
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4534 struct intel_crtc *crtc;
4535
4536 /*
4537 * First get all needed power domains, then put all unneeded, to avoid
4538 * any unnecessary toggling of the power wells.
4539 */
4540 for_each_intel_crtc(dev, crtc) {
4541 enum intel_display_power_domain domain;
4542
4543 if (!crtc->base.enabled)
4544 continue;
4545
4546 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4547
4548 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4549 intel_display_power_get(dev_priv, domain);
4550 }
4551
4552 for_each_intel_crtc(dev, crtc) {
4553 enum intel_display_power_domain domain;
4554
4555 for_each_power_domain(domain, crtc->enabled_power_domains)
4556 intel_display_power_put(dev_priv, domain);
4557
4558 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4559 }
4560
4561 intel_display_set_init_power(dev_priv, false);
4562 }
4563
4564 /* returns HPLL frequency in kHz */
4565 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4566 {
4567 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4568
4569 /* Obtain SKU information */
4570 mutex_lock(&dev_priv->dpio_lock);
4571 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4572 CCK_FUSE_HPLL_FREQ_MASK;
4573 mutex_unlock(&dev_priv->dpio_lock);
4574
4575 return vco_freq[hpll_freq] * 1000;
4576 }
4577
4578 static void vlv_update_cdclk(struct drm_device *dev)
4579 {
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581
4582 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4583 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4584 dev_priv->vlv_cdclk_freq);
4585
4586 /*
4587 * Program the gmbus_freq based on the cdclk frequency.
4588 * BSpec erroneously claims we should aim for 4MHz, but
4589 * in fact 1MHz is the correct frequency.
4590 */
4591 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4592 }
4593
4594 /* Adjust CDclk dividers to allow high res or save power if possible */
4595 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4596 {
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 u32 val, cmd;
4599
4600 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4601
4602 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4603 cmd = 2;
4604 else if (cdclk == 266667)
4605 cmd = 1;
4606 else
4607 cmd = 0;
4608
4609 mutex_lock(&dev_priv->rps.hw_lock);
4610 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4611 val &= ~DSPFREQGUAR_MASK;
4612 val |= (cmd << DSPFREQGUAR_SHIFT);
4613 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4614 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4615 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4616 50)) {
4617 DRM_ERROR("timed out waiting for CDclk change\n");
4618 }
4619 mutex_unlock(&dev_priv->rps.hw_lock);
4620
4621 if (cdclk == 400000) {
4622 u32 divider, vco;
4623
4624 vco = valleyview_get_vco(dev_priv);
4625 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4626
4627 mutex_lock(&dev_priv->dpio_lock);
4628 /* adjust cdclk divider */
4629 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4630 val &= ~DISPLAY_FREQUENCY_VALUES;
4631 val |= divider;
4632 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4633
4634 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4635 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4636 50))
4637 DRM_ERROR("timed out waiting for CDclk change\n");
4638 mutex_unlock(&dev_priv->dpio_lock);
4639 }
4640
4641 mutex_lock(&dev_priv->dpio_lock);
4642 /* adjust self-refresh exit latency value */
4643 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4644 val &= ~0x7f;
4645
4646 /*
4647 * For high bandwidth configs, we set a higher latency in the bunit
4648 * so that the core display fetch happens in time to avoid underruns.
4649 */
4650 if (cdclk == 400000)
4651 val |= 4500 / 250; /* 4.5 usec */
4652 else
4653 val |= 3000 / 250; /* 3.0 usec */
4654 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4655 mutex_unlock(&dev_priv->dpio_lock);
4656
4657 vlv_update_cdclk(dev);
4658 }
4659
4660 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4661 {
4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 u32 val, cmd;
4664
4665 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4666
4667 switch (cdclk) {
4668 case 400000:
4669 cmd = 3;
4670 break;
4671 case 333333:
4672 case 320000:
4673 cmd = 2;
4674 break;
4675 case 266667:
4676 cmd = 1;
4677 break;
4678 case 200000:
4679 cmd = 0;
4680 break;
4681 default:
4682 WARN_ON(1);
4683 return;
4684 }
4685
4686 mutex_lock(&dev_priv->rps.hw_lock);
4687 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4688 val &= ~DSPFREQGUAR_MASK_CHV;
4689 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4690 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4691 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4692 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4693 50)) {
4694 DRM_ERROR("timed out waiting for CDclk change\n");
4695 }
4696 mutex_unlock(&dev_priv->rps.hw_lock);
4697
4698 vlv_update_cdclk(dev);
4699 }
4700
4701 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4702 int max_pixclk)
4703 {
4704 int vco = valleyview_get_vco(dev_priv);
4705 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4706
4707 /* FIXME: Punit isn't quite ready yet */
4708 if (IS_CHERRYVIEW(dev_priv->dev))
4709 return 400000;
4710
4711 /*
4712 * Really only a few cases to deal with, as only 4 CDclks are supported:
4713 * 200MHz
4714 * 267MHz
4715 * 320/333MHz (depends on HPLL freq)
4716 * 400MHz
4717 * So we check to see whether we're above 90% of the lower bin and
4718 * adjust if needed.
4719 *
4720 * We seem to get an unstable or solid color picture at 200MHz.
4721 * Not sure what's wrong. For now use 200MHz only when all pipes
4722 * are off.
4723 */
4724 if (max_pixclk > freq_320*9/10)
4725 return 400000;
4726 else if (max_pixclk > 266667*9/10)
4727 return freq_320;
4728 else if (max_pixclk > 0)
4729 return 266667;
4730 else
4731 return 200000;
4732 }
4733
4734 /* compute the max pixel clock for new configuration */
4735 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4736 {
4737 struct drm_device *dev = dev_priv->dev;
4738 struct intel_crtc *intel_crtc;
4739 int max_pixclk = 0;
4740
4741 for_each_intel_crtc(dev, intel_crtc) {
4742 if (intel_crtc->new_enabled)
4743 max_pixclk = max(max_pixclk,
4744 intel_crtc->new_config->adjusted_mode.crtc_clock);
4745 }
4746
4747 return max_pixclk;
4748 }
4749
4750 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4751 unsigned *prepare_pipes)
4752 {
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_crtc *intel_crtc;
4755 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4756
4757 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4758 dev_priv->vlv_cdclk_freq)
4759 return;
4760
4761 /* disable/enable all currently active pipes while we change cdclk */
4762 for_each_intel_crtc(dev, intel_crtc)
4763 if (intel_crtc->base.enabled)
4764 *prepare_pipes |= (1 << intel_crtc->pipe);
4765 }
4766
4767 static void valleyview_modeset_global_resources(struct drm_device *dev)
4768 {
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4771 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4772
4773 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4774 if (IS_CHERRYVIEW(dev))
4775 cherryview_set_cdclk(dev, req_cdclk);
4776 else
4777 valleyview_set_cdclk(dev, req_cdclk);
4778 }
4779
4780 modeset_update_crtc_power_domains(dev);
4781 }
4782
4783 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4784 {
4785 struct drm_device *dev = crtc->dev;
4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4787 struct intel_encoder *encoder;
4788 int pipe = intel_crtc->pipe;
4789 bool is_dsi;
4790
4791 WARN_ON(!crtc->enabled);
4792
4793 if (intel_crtc->active)
4794 return;
4795
4796 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4797
4798 if (!is_dsi) {
4799 if (IS_CHERRYVIEW(dev))
4800 chv_prepare_pll(intel_crtc);
4801 else
4802 vlv_prepare_pll(intel_crtc);
4803 }
4804
4805 if (intel_crtc->config.has_dp_encoder)
4806 intel_dp_set_m_n(intel_crtc);
4807
4808 intel_set_pipe_timings(intel_crtc);
4809
4810 i9xx_set_pipeconf(intel_crtc);
4811
4812 intel_crtc->active = true;
4813
4814 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4815
4816 for_each_encoder_on_crtc(dev, crtc, encoder)
4817 if (encoder->pre_pll_enable)
4818 encoder->pre_pll_enable(encoder);
4819
4820 if (!is_dsi) {
4821 if (IS_CHERRYVIEW(dev))
4822 chv_enable_pll(intel_crtc);
4823 else
4824 vlv_enable_pll(intel_crtc);
4825 }
4826
4827 for_each_encoder_on_crtc(dev, crtc, encoder)
4828 if (encoder->pre_enable)
4829 encoder->pre_enable(encoder);
4830
4831 i9xx_pfit_enable(intel_crtc);
4832
4833 intel_crtc_load_lut(crtc);
4834
4835 intel_update_watermarks(crtc);
4836 intel_enable_pipe(intel_crtc);
4837
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 encoder->enable(encoder);
4840
4841 intel_crtc_enable_planes(crtc);
4842
4843 /* Underruns don't raise interrupts, so check manually. */
4844 i9xx_check_fifo_underruns(dev);
4845 }
4846
4847 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4848 {
4849 struct drm_device *dev = crtc->base.dev;
4850 struct drm_i915_private *dev_priv = dev->dev_private;
4851
4852 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4853 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4854 }
4855
4856 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4857 {
4858 struct drm_device *dev = crtc->dev;
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 struct intel_encoder *encoder;
4861 int pipe = intel_crtc->pipe;
4862
4863 WARN_ON(!crtc->enabled);
4864
4865 if (intel_crtc->active)
4866 return;
4867
4868 i9xx_set_pll_dividers(intel_crtc);
4869
4870 if (intel_crtc->config.has_dp_encoder)
4871 intel_dp_set_m_n(intel_crtc);
4872
4873 intel_set_pipe_timings(intel_crtc);
4874
4875 i9xx_set_pipeconf(intel_crtc);
4876
4877 intel_crtc->active = true;
4878
4879 if (!IS_GEN2(dev))
4880 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4881
4882 for_each_encoder_on_crtc(dev, crtc, encoder)
4883 if (encoder->pre_enable)
4884 encoder->pre_enable(encoder);
4885
4886 i9xx_enable_pll(intel_crtc);
4887
4888 i9xx_pfit_enable(intel_crtc);
4889
4890 intel_crtc_load_lut(crtc);
4891
4892 intel_update_watermarks(crtc);
4893 intel_enable_pipe(intel_crtc);
4894
4895 for_each_encoder_on_crtc(dev, crtc, encoder)
4896 encoder->enable(encoder);
4897
4898 intel_crtc_enable_planes(crtc);
4899
4900 /*
4901 * Gen2 reports pipe underruns whenever all planes are disabled.
4902 * So don't enable underrun reporting before at least some planes
4903 * are enabled.
4904 * FIXME: Need to fix the logic to work when we turn off all planes
4905 * but leave the pipe running.
4906 */
4907 if (IS_GEN2(dev))
4908 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4909
4910 /* Underruns don't raise interrupts, so check manually. */
4911 i9xx_check_fifo_underruns(dev);
4912 }
4913
4914 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4915 {
4916 struct drm_device *dev = crtc->base.dev;
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918
4919 if (!crtc->config.gmch_pfit.control)
4920 return;
4921
4922 assert_pipe_disabled(dev_priv, crtc->pipe);
4923
4924 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4925 I915_READ(PFIT_CONTROL));
4926 I915_WRITE(PFIT_CONTROL, 0);
4927 }
4928
4929 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4930 {
4931 struct drm_device *dev = crtc->dev;
4932 struct drm_i915_private *dev_priv = dev->dev_private;
4933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4934 struct intel_encoder *encoder;
4935 int pipe = intel_crtc->pipe;
4936
4937 if (!intel_crtc->active)
4938 return;
4939
4940 /*
4941 * Gen2 reports pipe underruns whenever all planes are disabled.
4942 * So diasble underrun reporting before all the planes get disabled.
4943 * FIXME: Need to fix the logic to work when we turn off all planes
4944 * but leave the pipe running.
4945 */
4946 if (IS_GEN2(dev))
4947 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4948
4949 /*
4950 * Vblank time updates from the shadow to live plane control register
4951 * are blocked if the memory self-refresh mode is active at that
4952 * moment. So to make sure the plane gets truly disabled, disable
4953 * first the self-refresh mode. The self-refresh enable bit in turn
4954 * will be checked/applied by the HW only at the next frame start
4955 * event which is after the vblank start event, so we need to have a
4956 * wait-for-vblank between disabling the plane and the pipe.
4957 */
4958 intel_set_memory_cxsr(dev_priv, false);
4959 intel_crtc_disable_planes(crtc);
4960
4961 for_each_encoder_on_crtc(dev, crtc, encoder)
4962 encoder->disable(encoder);
4963
4964 /*
4965 * On gen2 planes are double buffered but the pipe isn't, so we must
4966 * wait for planes to fully turn off before disabling the pipe.
4967 * We also need to wait on all gmch platforms because of the
4968 * self-refresh mode constraint explained above.
4969 */
4970 intel_wait_for_vblank(dev, pipe);
4971
4972 intel_disable_pipe(intel_crtc);
4973
4974 i9xx_pfit_disable(intel_crtc);
4975
4976 for_each_encoder_on_crtc(dev, crtc, encoder)
4977 if (encoder->post_disable)
4978 encoder->post_disable(encoder);
4979
4980 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4981 if (IS_CHERRYVIEW(dev))
4982 chv_disable_pll(dev_priv, pipe);
4983 else if (IS_VALLEYVIEW(dev))
4984 vlv_disable_pll(dev_priv, pipe);
4985 else
4986 i9xx_disable_pll(intel_crtc);
4987 }
4988
4989 if (!IS_GEN2(dev))
4990 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4991
4992 intel_crtc->active = false;
4993 intel_update_watermarks(crtc);
4994
4995 mutex_lock(&dev->struct_mutex);
4996 intel_update_fbc(dev);
4997 mutex_unlock(&dev->struct_mutex);
4998 }
4999
5000 static void i9xx_crtc_off(struct drm_crtc *crtc)
5001 {
5002 }
5003
5004 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5005 bool enabled)
5006 {
5007 struct drm_device *dev = crtc->dev;
5008 struct drm_i915_master_private *master_priv;
5009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010 int pipe = intel_crtc->pipe;
5011
5012 if (!dev->primary->master)
5013 return;
5014
5015 master_priv = dev->primary->master->driver_priv;
5016 if (!master_priv->sarea_priv)
5017 return;
5018
5019 switch (pipe) {
5020 case 0:
5021 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5022 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5023 break;
5024 case 1:
5025 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5026 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5027 break;
5028 default:
5029 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5030 break;
5031 }
5032 }
5033
5034 /* Master function to enable/disable CRTC and corresponding power wells */
5035 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5036 {
5037 struct drm_device *dev = crtc->dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5040 enum intel_display_power_domain domain;
5041 unsigned long domains;
5042
5043 if (enable) {
5044 if (!intel_crtc->active) {
5045 domains = get_crtc_power_domains(crtc);
5046 for_each_power_domain(domain, domains)
5047 intel_display_power_get(dev_priv, domain);
5048 intel_crtc->enabled_power_domains = domains;
5049
5050 dev_priv->display.crtc_enable(crtc);
5051 }
5052 } else {
5053 if (intel_crtc->active) {
5054 dev_priv->display.crtc_disable(crtc);
5055
5056 domains = intel_crtc->enabled_power_domains;
5057 for_each_power_domain(domain, domains)
5058 intel_display_power_put(dev_priv, domain);
5059 intel_crtc->enabled_power_domains = 0;
5060 }
5061 }
5062 }
5063
5064 /**
5065 * Sets the power management mode of the pipe and plane.
5066 */
5067 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5068 {
5069 struct drm_device *dev = crtc->dev;
5070 struct intel_encoder *intel_encoder;
5071 bool enable = false;
5072
5073 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5074 enable |= intel_encoder->connectors_active;
5075
5076 intel_crtc_control(crtc, enable);
5077
5078 intel_crtc_update_sarea(crtc, enable);
5079 }
5080
5081 static void intel_crtc_disable(struct drm_crtc *crtc)
5082 {
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_connector *connector;
5085 struct drm_i915_private *dev_priv = dev->dev_private;
5086 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5087 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5088
5089 /* crtc should still be enabled when we disable it. */
5090 WARN_ON(!crtc->enabled);
5091
5092 dev_priv->display.crtc_disable(crtc);
5093 intel_crtc_update_sarea(crtc, false);
5094 dev_priv->display.off(crtc);
5095
5096 if (crtc->primary->fb) {
5097 mutex_lock(&dev->struct_mutex);
5098 intel_unpin_fb_obj(old_obj);
5099 i915_gem_track_fb(old_obj, NULL,
5100 INTEL_FRONTBUFFER_PRIMARY(pipe));
5101 mutex_unlock(&dev->struct_mutex);
5102 crtc->primary->fb = NULL;
5103 }
5104
5105 /* Update computed state. */
5106 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5107 if (!connector->encoder || !connector->encoder->crtc)
5108 continue;
5109
5110 if (connector->encoder->crtc != crtc)
5111 continue;
5112
5113 connector->dpms = DRM_MODE_DPMS_OFF;
5114 to_intel_encoder(connector->encoder)->connectors_active = false;
5115 }
5116 }
5117
5118 void intel_encoder_destroy(struct drm_encoder *encoder)
5119 {
5120 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5121
5122 drm_encoder_cleanup(encoder);
5123 kfree(intel_encoder);
5124 }
5125
5126 /* Simple dpms helper for encoders with just one connector, no cloning and only
5127 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5128 * state of the entire output pipe. */
5129 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5130 {
5131 if (mode == DRM_MODE_DPMS_ON) {
5132 encoder->connectors_active = true;
5133
5134 intel_crtc_update_dpms(encoder->base.crtc);
5135 } else {
5136 encoder->connectors_active = false;
5137
5138 intel_crtc_update_dpms(encoder->base.crtc);
5139 }
5140 }
5141
5142 /* Cross check the actual hw state with our own modeset state tracking (and it's
5143 * internal consistency). */
5144 static void intel_connector_check_state(struct intel_connector *connector)
5145 {
5146 if (connector->get_hw_state(connector)) {
5147 struct intel_encoder *encoder = connector->encoder;
5148 struct drm_crtc *crtc;
5149 bool encoder_enabled;
5150 enum pipe pipe;
5151
5152 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5153 connector->base.base.id,
5154 connector->base.name);
5155
5156 /* there is no real hw state for MST connectors */
5157 if (connector->mst_port)
5158 return;
5159
5160 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5161 "wrong connector dpms state\n");
5162 WARN(connector->base.encoder != &encoder->base,
5163 "active connector not linked to encoder\n");
5164
5165 if (encoder) {
5166 WARN(!encoder->connectors_active,
5167 "encoder->connectors_active not set\n");
5168
5169 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5170 WARN(!encoder_enabled, "encoder not enabled\n");
5171 if (WARN_ON(!encoder->base.crtc))
5172 return;
5173
5174 crtc = encoder->base.crtc;
5175
5176 WARN(!crtc->enabled, "crtc not enabled\n");
5177 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5178 WARN(pipe != to_intel_crtc(crtc)->pipe,
5179 "encoder active on the wrong pipe\n");
5180 }
5181 }
5182 }
5183
5184 /* Even simpler default implementation, if there's really no special case to
5185 * consider. */
5186 void intel_connector_dpms(struct drm_connector *connector, int mode)
5187 {
5188 /* All the simple cases only support two dpms states. */
5189 if (mode != DRM_MODE_DPMS_ON)
5190 mode = DRM_MODE_DPMS_OFF;
5191
5192 if (mode == connector->dpms)
5193 return;
5194
5195 connector->dpms = mode;
5196
5197 /* Only need to change hw state when actually enabled */
5198 if (connector->encoder)
5199 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5200
5201 intel_modeset_check_state(connector->dev);
5202 }
5203
5204 /* Simple connector->get_hw_state implementation for encoders that support only
5205 * one connector and no cloning and hence the encoder state determines the state
5206 * of the connector. */
5207 bool intel_connector_get_hw_state(struct intel_connector *connector)
5208 {
5209 enum pipe pipe = 0;
5210 struct intel_encoder *encoder = connector->encoder;
5211
5212 return encoder->get_hw_state(encoder, &pipe);
5213 }
5214
5215 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5216 struct intel_crtc_config *pipe_config)
5217 {
5218 struct drm_i915_private *dev_priv = dev->dev_private;
5219 struct intel_crtc *pipe_B_crtc =
5220 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5221
5222 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5223 pipe_name(pipe), pipe_config->fdi_lanes);
5224 if (pipe_config->fdi_lanes > 4) {
5225 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5226 pipe_name(pipe), pipe_config->fdi_lanes);
5227 return false;
5228 }
5229
5230 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5231 if (pipe_config->fdi_lanes > 2) {
5232 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5233 pipe_config->fdi_lanes);
5234 return false;
5235 } else {
5236 return true;
5237 }
5238 }
5239
5240 if (INTEL_INFO(dev)->num_pipes == 2)
5241 return true;
5242
5243 /* Ivybridge 3 pipe is really complicated */
5244 switch (pipe) {
5245 case PIPE_A:
5246 return true;
5247 case PIPE_B:
5248 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5249 pipe_config->fdi_lanes > 2) {
5250 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5251 pipe_name(pipe), pipe_config->fdi_lanes);
5252 return false;
5253 }
5254 return true;
5255 case PIPE_C:
5256 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5257 pipe_B_crtc->config.fdi_lanes <= 2) {
5258 if (pipe_config->fdi_lanes > 2) {
5259 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5260 pipe_name(pipe), pipe_config->fdi_lanes);
5261 return false;
5262 }
5263 } else {
5264 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5265 return false;
5266 }
5267 return true;
5268 default:
5269 BUG();
5270 }
5271 }
5272
5273 #define RETRY 1
5274 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5275 struct intel_crtc_config *pipe_config)
5276 {
5277 struct drm_device *dev = intel_crtc->base.dev;
5278 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5279 int lane, link_bw, fdi_dotclock;
5280 bool setup_ok, needs_recompute = false;
5281
5282 retry:
5283 /* FDI is a binary signal running at ~2.7GHz, encoding
5284 * each output octet as 10 bits. The actual frequency
5285 * is stored as a divider into a 100MHz clock, and the
5286 * mode pixel clock is stored in units of 1KHz.
5287 * Hence the bw of each lane in terms of the mode signal
5288 * is:
5289 */
5290 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5291
5292 fdi_dotclock = adjusted_mode->crtc_clock;
5293
5294 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5295 pipe_config->pipe_bpp);
5296
5297 pipe_config->fdi_lanes = lane;
5298
5299 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5300 link_bw, &pipe_config->fdi_m_n);
5301
5302 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5303 intel_crtc->pipe, pipe_config);
5304 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5305 pipe_config->pipe_bpp -= 2*3;
5306 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5307 pipe_config->pipe_bpp);
5308 needs_recompute = true;
5309 pipe_config->bw_constrained = true;
5310
5311 goto retry;
5312 }
5313
5314 if (needs_recompute)
5315 return RETRY;
5316
5317 return setup_ok ? 0 : -EINVAL;
5318 }
5319
5320 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5321 struct intel_crtc_config *pipe_config)
5322 {
5323 pipe_config->ips_enabled = i915.enable_ips &&
5324 hsw_crtc_supports_ips(crtc) &&
5325 pipe_config->pipe_bpp <= 24;
5326 }
5327
5328 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5329 struct intel_crtc_config *pipe_config)
5330 {
5331 struct drm_device *dev = crtc->base.dev;
5332 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5333
5334 /* FIXME should check pixel clock limits on all platforms */
5335 if (INTEL_INFO(dev)->gen < 4) {
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 int clock_limit =
5338 dev_priv->display.get_display_clock_speed(dev);
5339
5340 /*
5341 * Enable pixel doubling when the dot clock
5342 * is > 90% of the (display) core speed.
5343 *
5344 * GDG double wide on either pipe,
5345 * otherwise pipe A only.
5346 */
5347 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5348 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5349 clock_limit *= 2;
5350 pipe_config->double_wide = true;
5351 }
5352
5353 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5354 return -EINVAL;
5355 }
5356
5357 /*
5358 * Pipe horizontal size must be even in:
5359 * - DVO ganged mode
5360 * - LVDS dual channel mode
5361 * - Double wide pipe
5362 */
5363 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5364 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5365 pipe_config->pipe_src_w &= ~1;
5366
5367 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5368 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5369 */
5370 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5371 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5372 return -EINVAL;
5373
5374 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5375 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5376 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5377 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5378 * for lvds. */
5379 pipe_config->pipe_bpp = 8*3;
5380 }
5381
5382 if (HAS_IPS(dev))
5383 hsw_compute_ips_config(crtc, pipe_config);
5384
5385 /*
5386 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5387 * old clock survives for now.
5388 */
5389 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5390 pipe_config->shared_dpll = crtc->config.shared_dpll;
5391
5392 if (pipe_config->has_pch_encoder)
5393 return ironlake_fdi_compute_config(crtc, pipe_config);
5394
5395 return 0;
5396 }
5397
5398 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5399 {
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 int vco = valleyview_get_vco(dev_priv);
5402 u32 val;
5403 int divider;
5404
5405 /* FIXME: Punit isn't quite ready yet */
5406 if (IS_CHERRYVIEW(dev))
5407 return 400000;
5408
5409 mutex_lock(&dev_priv->dpio_lock);
5410 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5411 mutex_unlock(&dev_priv->dpio_lock);
5412
5413 divider = val & DISPLAY_FREQUENCY_VALUES;
5414
5415 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5416 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5417 "cdclk change in progress\n");
5418
5419 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5420 }
5421
5422 static int i945_get_display_clock_speed(struct drm_device *dev)
5423 {
5424 return 400000;
5425 }
5426
5427 static int i915_get_display_clock_speed(struct drm_device *dev)
5428 {
5429 return 333000;
5430 }
5431
5432 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5433 {
5434 return 200000;
5435 }
5436
5437 static int pnv_get_display_clock_speed(struct drm_device *dev)
5438 {
5439 u16 gcfgc = 0;
5440
5441 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5442
5443 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5444 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5445 return 267000;
5446 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5447 return 333000;
5448 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5449 return 444000;
5450 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5451 return 200000;
5452 default:
5453 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5454 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5455 return 133000;
5456 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5457 return 167000;
5458 }
5459 }
5460
5461 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5462 {
5463 u16 gcfgc = 0;
5464
5465 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5466
5467 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5468 return 133000;
5469 else {
5470 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5471 case GC_DISPLAY_CLOCK_333_MHZ:
5472 return 333000;
5473 default:
5474 case GC_DISPLAY_CLOCK_190_200_MHZ:
5475 return 190000;
5476 }
5477 }
5478 }
5479
5480 static int i865_get_display_clock_speed(struct drm_device *dev)
5481 {
5482 return 266000;
5483 }
5484
5485 static int i855_get_display_clock_speed(struct drm_device *dev)
5486 {
5487 u16 hpllcc = 0;
5488 /* Assume that the hardware is in the high speed state. This
5489 * should be the default.
5490 */
5491 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5492 case GC_CLOCK_133_200:
5493 case GC_CLOCK_100_200:
5494 return 200000;
5495 case GC_CLOCK_166_250:
5496 return 250000;
5497 case GC_CLOCK_100_133:
5498 return 133000;
5499 }
5500
5501 /* Shouldn't happen */
5502 return 0;
5503 }
5504
5505 static int i830_get_display_clock_speed(struct drm_device *dev)
5506 {
5507 return 133000;
5508 }
5509
5510 static void
5511 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5512 {
5513 while (*num > DATA_LINK_M_N_MASK ||
5514 *den > DATA_LINK_M_N_MASK) {
5515 *num >>= 1;
5516 *den >>= 1;
5517 }
5518 }
5519
5520 static void compute_m_n(unsigned int m, unsigned int n,
5521 uint32_t *ret_m, uint32_t *ret_n)
5522 {
5523 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5524 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5525 intel_reduce_m_n_ratio(ret_m, ret_n);
5526 }
5527
5528 void
5529 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5530 int pixel_clock, int link_clock,
5531 struct intel_link_m_n *m_n)
5532 {
5533 m_n->tu = 64;
5534
5535 compute_m_n(bits_per_pixel * pixel_clock,
5536 link_clock * nlanes * 8,
5537 &m_n->gmch_m, &m_n->gmch_n);
5538
5539 compute_m_n(pixel_clock, link_clock,
5540 &m_n->link_m, &m_n->link_n);
5541 }
5542
5543 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5544 {
5545 if (i915.panel_use_ssc >= 0)
5546 return i915.panel_use_ssc != 0;
5547 return dev_priv->vbt.lvds_use_ssc
5548 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5549 }
5550
5551 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5552 {
5553 struct drm_device *dev = crtc->dev;
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555 int refclk;
5556
5557 if (IS_VALLEYVIEW(dev)) {
5558 refclk = 100000;
5559 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5560 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5561 refclk = dev_priv->vbt.lvds_ssc_freq;
5562 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5563 } else if (!IS_GEN2(dev)) {
5564 refclk = 96000;
5565 } else {
5566 refclk = 48000;
5567 }
5568
5569 return refclk;
5570 }
5571
5572 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5573 {
5574 return (1 << dpll->n) << 16 | dpll->m2;
5575 }
5576
5577 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5578 {
5579 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5580 }
5581
5582 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5583 intel_clock_t *reduced_clock)
5584 {
5585 struct drm_device *dev = crtc->base.dev;
5586 u32 fp, fp2 = 0;
5587
5588 if (IS_PINEVIEW(dev)) {
5589 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5590 if (reduced_clock)
5591 fp2 = pnv_dpll_compute_fp(reduced_clock);
5592 } else {
5593 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5594 if (reduced_clock)
5595 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5596 }
5597
5598 crtc->config.dpll_hw_state.fp0 = fp;
5599
5600 crtc->lowfreq_avail = false;
5601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5602 reduced_clock && i915.powersave) {
5603 crtc->config.dpll_hw_state.fp1 = fp2;
5604 crtc->lowfreq_avail = true;
5605 } else {
5606 crtc->config.dpll_hw_state.fp1 = fp;
5607 }
5608 }
5609
5610 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5611 pipe)
5612 {
5613 u32 reg_val;
5614
5615 /*
5616 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5617 * and set it to a reasonable value instead.
5618 */
5619 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5620 reg_val &= 0xffffff00;
5621 reg_val |= 0x00000030;
5622 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5623
5624 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5625 reg_val &= 0x8cffffff;
5626 reg_val = 0x8c000000;
5627 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5628
5629 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5630 reg_val &= 0xffffff00;
5631 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5632
5633 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5634 reg_val &= 0x00ffffff;
5635 reg_val |= 0xb0000000;
5636 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5637 }
5638
5639 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5640 struct intel_link_m_n *m_n)
5641 {
5642 struct drm_device *dev = crtc->base.dev;
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644 int pipe = crtc->pipe;
5645
5646 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5647 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5648 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5649 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5650 }
5651
5652 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5653 struct intel_link_m_n *m_n,
5654 struct intel_link_m_n *m2_n2)
5655 {
5656 struct drm_device *dev = crtc->base.dev;
5657 struct drm_i915_private *dev_priv = dev->dev_private;
5658 int pipe = crtc->pipe;
5659 enum transcoder transcoder = crtc->config.cpu_transcoder;
5660
5661 if (INTEL_INFO(dev)->gen >= 5) {
5662 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5663 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5664 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5665 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5666 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5667 * for gen < 8) and if DRRS is supported (to make sure the
5668 * registers are not unnecessarily accessed).
5669 */
5670 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5671 crtc->config.has_drrs) {
5672 I915_WRITE(PIPE_DATA_M2(transcoder),
5673 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5674 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5675 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5676 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5677 }
5678 } else {
5679 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5680 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5681 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5682 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5683 }
5684 }
5685
5686 void intel_dp_set_m_n(struct intel_crtc *crtc)
5687 {
5688 if (crtc->config.has_pch_encoder)
5689 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5690 else
5691 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5692 &crtc->config.dp_m2_n2);
5693 }
5694
5695 static void vlv_update_pll(struct intel_crtc *crtc)
5696 {
5697 u32 dpll, dpll_md;
5698
5699 /*
5700 * Enable DPIO clock input. We should never disable the reference
5701 * clock for pipe B, since VGA hotplug / manual detection depends
5702 * on it.
5703 */
5704 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5705 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5706 /* We should never disable this, set it here for state tracking */
5707 if (crtc->pipe == PIPE_B)
5708 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5709 dpll |= DPLL_VCO_ENABLE;
5710 crtc->config.dpll_hw_state.dpll = dpll;
5711
5712 dpll_md = (crtc->config.pixel_multiplier - 1)
5713 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5714 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5715 }
5716
5717 static void vlv_prepare_pll(struct intel_crtc *crtc)
5718 {
5719 struct drm_device *dev = crtc->base.dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 int pipe = crtc->pipe;
5722 u32 mdiv;
5723 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5724 u32 coreclk, reg_val;
5725
5726 mutex_lock(&dev_priv->dpio_lock);
5727
5728 bestn = crtc->config.dpll.n;
5729 bestm1 = crtc->config.dpll.m1;
5730 bestm2 = crtc->config.dpll.m2;
5731 bestp1 = crtc->config.dpll.p1;
5732 bestp2 = crtc->config.dpll.p2;
5733
5734 /* See eDP HDMI DPIO driver vbios notes doc */
5735
5736 /* PLL B needs special handling */
5737 if (pipe == PIPE_B)
5738 vlv_pllb_recal_opamp(dev_priv, pipe);
5739
5740 /* Set up Tx target for periodic Rcomp update */
5741 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5742
5743 /* Disable target IRef on PLL */
5744 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5745 reg_val &= 0x00ffffff;
5746 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5747
5748 /* Disable fast lock */
5749 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5750
5751 /* Set idtafcrecal before PLL is enabled */
5752 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5753 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5754 mdiv |= ((bestn << DPIO_N_SHIFT));
5755 mdiv |= (1 << DPIO_K_SHIFT);
5756
5757 /*
5758 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5759 * but we don't support that).
5760 * Note: don't use the DAC post divider as it seems unstable.
5761 */
5762 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5763 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5764
5765 mdiv |= DPIO_ENABLE_CALIBRATION;
5766 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5767
5768 /* Set HBR and RBR LPF coefficients */
5769 if (crtc->config.port_clock == 162000 ||
5770 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5771 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5772 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5773 0x009f0003);
5774 else
5775 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5776 0x00d0000f);
5777
5778 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5779 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5780 /* Use SSC source */
5781 if (pipe == PIPE_A)
5782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5783 0x0df40000);
5784 else
5785 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5786 0x0df70000);
5787 } else { /* HDMI or VGA */
5788 /* Use bend source */
5789 if (pipe == PIPE_A)
5790 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5791 0x0df70000);
5792 else
5793 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5794 0x0df40000);
5795 }
5796
5797 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5798 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5799 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5800 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5801 coreclk |= 0x01000000;
5802 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5803
5804 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5805 mutex_unlock(&dev_priv->dpio_lock);
5806 }
5807
5808 static void chv_update_pll(struct intel_crtc *crtc)
5809 {
5810 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5811 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5812 DPLL_VCO_ENABLE;
5813 if (crtc->pipe != PIPE_A)
5814 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5815
5816 crtc->config.dpll_hw_state.dpll_md =
5817 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5818 }
5819
5820 static void chv_prepare_pll(struct intel_crtc *crtc)
5821 {
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 int pipe = crtc->pipe;
5825 int dpll_reg = DPLL(crtc->pipe);
5826 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5827 u32 loopfilter, intcoeff;
5828 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5829 int refclk;
5830
5831 bestn = crtc->config.dpll.n;
5832 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5833 bestm1 = crtc->config.dpll.m1;
5834 bestm2 = crtc->config.dpll.m2 >> 22;
5835 bestp1 = crtc->config.dpll.p1;
5836 bestp2 = crtc->config.dpll.p2;
5837
5838 /*
5839 * Enable Refclk and SSC
5840 */
5841 I915_WRITE(dpll_reg,
5842 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5843
5844 mutex_lock(&dev_priv->dpio_lock);
5845
5846 /* p1 and p2 divider */
5847 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5848 5 << DPIO_CHV_S1_DIV_SHIFT |
5849 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5850 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5851 1 << DPIO_CHV_K_DIV_SHIFT);
5852
5853 /* Feedback post-divider - m2 */
5854 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5855
5856 /* Feedback refclk divider - n and m1 */
5857 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5858 DPIO_CHV_M1_DIV_BY_2 |
5859 1 << DPIO_CHV_N_DIV_SHIFT);
5860
5861 /* M2 fraction division */
5862 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5863
5864 /* M2 fraction division enable */
5865 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5866 DPIO_CHV_FRAC_DIV_EN |
5867 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5868
5869 /* Loop filter */
5870 refclk = i9xx_get_refclk(&crtc->base, 0);
5871 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5872 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5873 if (refclk == 100000)
5874 intcoeff = 11;
5875 else if (refclk == 38400)
5876 intcoeff = 10;
5877 else
5878 intcoeff = 9;
5879 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5880 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5881
5882 /* AFC Recal */
5883 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5884 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5885 DPIO_AFC_RECAL);
5886
5887 mutex_unlock(&dev_priv->dpio_lock);
5888 }
5889
5890 static void i9xx_update_pll(struct intel_crtc *crtc,
5891 intel_clock_t *reduced_clock,
5892 int num_connectors)
5893 {
5894 struct drm_device *dev = crtc->base.dev;
5895 struct drm_i915_private *dev_priv = dev->dev_private;
5896 u32 dpll;
5897 bool is_sdvo;
5898 struct dpll *clock = &crtc->config.dpll;
5899
5900 i9xx_update_pll_dividers(crtc, reduced_clock);
5901
5902 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5903 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5904
5905 dpll = DPLL_VGA_MODE_DIS;
5906
5907 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5908 dpll |= DPLLB_MODE_LVDS;
5909 else
5910 dpll |= DPLLB_MODE_DAC_SERIAL;
5911
5912 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5913 dpll |= (crtc->config.pixel_multiplier - 1)
5914 << SDVO_MULTIPLIER_SHIFT_HIRES;
5915 }
5916
5917 if (is_sdvo)
5918 dpll |= DPLL_SDVO_HIGH_SPEED;
5919
5920 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5921 dpll |= DPLL_SDVO_HIGH_SPEED;
5922
5923 /* compute bitmask from p1 value */
5924 if (IS_PINEVIEW(dev))
5925 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5926 else {
5927 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5928 if (IS_G4X(dev) && reduced_clock)
5929 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5930 }
5931 switch (clock->p2) {
5932 case 5:
5933 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5934 break;
5935 case 7:
5936 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5937 break;
5938 case 10:
5939 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5940 break;
5941 case 14:
5942 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5943 break;
5944 }
5945 if (INTEL_INFO(dev)->gen >= 4)
5946 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5947
5948 if (crtc->config.sdvo_tv_clock)
5949 dpll |= PLL_REF_INPUT_TVCLKINBC;
5950 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5951 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5952 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5953 else
5954 dpll |= PLL_REF_INPUT_DREFCLK;
5955
5956 dpll |= DPLL_VCO_ENABLE;
5957 crtc->config.dpll_hw_state.dpll = dpll;
5958
5959 if (INTEL_INFO(dev)->gen >= 4) {
5960 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5961 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5962 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5963 }
5964 }
5965
5966 static void i8xx_update_pll(struct intel_crtc *crtc,
5967 intel_clock_t *reduced_clock,
5968 int num_connectors)
5969 {
5970 struct drm_device *dev = crtc->base.dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 u32 dpll;
5973 struct dpll *clock = &crtc->config.dpll;
5974
5975 i9xx_update_pll_dividers(crtc, reduced_clock);
5976
5977 dpll = DPLL_VGA_MODE_DIS;
5978
5979 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5980 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5981 } else {
5982 if (clock->p1 == 2)
5983 dpll |= PLL_P1_DIVIDE_BY_TWO;
5984 else
5985 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5986 if (clock->p2 == 4)
5987 dpll |= PLL_P2_DIVIDE_BY_4;
5988 }
5989
5990 if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5991 dpll |= DPLL_DVO_2X_MODE;
5992
5993 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5994 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5995 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5996 else
5997 dpll |= PLL_REF_INPUT_DREFCLK;
5998
5999 dpll |= DPLL_VCO_ENABLE;
6000 crtc->config.dpll_hw_state.dpll = dpll;
6001 }
6002
6003 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6004 {
6005 struct drm_device *dev = intel_crtc->base.dev;
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007 enum pipe pipe = intel_crtc->pipe;
6008 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6009 struct drm_display_mode *adjusted_mode =
6010 &intel_crtc->config.adjusted_mode;
6011 uint32_t crtc_vtotal, crtc_vblank_end;
6012 int vsyncshift = 0;
6013
6014 /* We need to be careful not to changed the adjusted mode, for otherwise
6015 * the hw state checker will get angry at the mismatch. */
6016 crtc_vtotal = adjusted_mode->crtc_vtotal;
6017 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6018
6019 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6020 /* the chip adds 2 halflines automatically */
6021 crtc_vtotal -= 1;
6022 crtc_vblank_end -= 1;
6023
6024 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6025 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6026 else
6027 vsyncshift = adjusted_mode->crtc_hsync_start -
6028 adjusted_mode->crtc_htotal / 2;
6029 if (vsyncshift < 0)
6030 vsyncshift += adjusted_mode->crtc_htotal;
6031 }
6032
6033 if (INTEL_INFO(dev)->gen > 3)
6034 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6035
6036 I915_WRITE(HTOTAL(cpu_transcoder),
6037 (adjusted_mode->crtc_hdisplay - 1) |
6038 ((adjusted_mode->crtc_htotal - 1) << 16));
6039 I915_WRITE(HBLANK(cpu_transcoder),
6040 (adjusted_mode->crtc_hblank_start - 1) |
6041 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6042 I915_WRITE(HSYNC(cpu_transcoder),
6043 (adjusted_mode->crtc_hsync_start - 1) |
6044 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6045
6046 I915_WRITE(VTOTAL(cpu_transcoder),
6047 (adjusted_mode->crtc_vdisplay - 1) |
6048 ((crtc_vtotal - 1) << 16));
6049 I915_WRITE(VBLANK(cpu_transcoder),
6050 (adjusted_mode->crtc_vblank_start - 1) |
6051 ((crtc_vblank_end - 1) << 16));
6052 I915_WRITE(VSYNC(cpu_transcoder),
6053 (adjusted_mode->crtc_vsync_start - 1) |
6054 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6055
6056 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6057 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6058 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6059 * bits. */
6060 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6061 (pipe == PIPE_B || pipe == PIPE_C))
6062 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6063
6064 /* pipesrc controls the size that is scaled from, which should
6065 * always be the user's requested size.
6066 */
6067 I915_WRITE(PIPESRC(pipe),
6068 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6069 (intel_crtc->config.pipe_src_h - 1));
6070 }
6071
6072 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6073 struct intel_crtc_config *pipe_config)
6074 {
6075 struct drm_device *dev = crtc->base.dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6078 uint32_t tmp;
6079
6080 tmp = I915_READ(HTOTAL(cpu_transcoder));
6081 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6082 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6083 tmp = I915_READ(HBLANK(cpu_transcoder));
6084 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6085 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6086 tmp = I915_READ(HSYNC(cpu_transcoder));
6087 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6088 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6089
6090 tmp = I915_READ(VTOTAL(cpu_transcoder));
6091 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6092 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6093 tmp = I915_READ(VBLANK(cpu_transcoder));
6094 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6095 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6096 tmp = I915_READ(VSYNC(cpu_transcoder));
6097 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6098 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6099
6100 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6101 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6102 pipe_config->adjusted_mode.crtc_vtotal += 1;
6103 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6104 }
6105
6106 tmp = I915_READ(PIPESRC(crtc->pipe));
6107 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6108 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6109
6110 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6111 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6112 }
6113
6114 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6115 struct intel_crtc_config *pipe_config)
6116 {
6117 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6118 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6119 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6120 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6121
6122 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6123 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6124 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6125 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6126
6127 mode->flags = pipe_config->adjusted_mode.flags;
6128
6129 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6130 mode->flags |= pipe_config->adjusted_mode.flags;
6131 }
6132
6133 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6134 {
6135 struct drm_device *dev = intel_crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 uint32_t pipeconf;
6138
6139 pipeconf = 0;
6140
6141 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6142 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6143 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6144
6145 if (intel_crtc->config.double_wide)
6146 pipeconf |= PIPECONF_DOUBLE_WIDE;
6147
6148 /* only g4x and later have fancy bpc/dither controls */
6149 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6150 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6151 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6152 pipeconf |= PIPECONF_DITHER_EN |
6153 PIPECONF_DITHER_TYPE_SP;
6154
6155 switch (intel_crtc->config.pipe_bpp) {
6156 case 18:
6157 pipeconf |= PIPECONF_6BPC;
6158 break;
6159 case 24:
6160 pipeconf |= PIPECONF_8BPC;
6161 break;
6162 case 30:
6163 pipeconf |= PIPECONF_10BPC;
6164 break;
6165 default:
6166 /* Case prevented by intel_choose_pipe_bpp_dither. */
6167 BUG();
6168 }
6169 }
6170
6171 if (HAS_PIPE_CXSR(dev)) {
6172 if (intel_crtc->lowfreq_avail) {
6173 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6174 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6175 } else {
6176 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6177 }
6178 }
6179
6180 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6181 if (INTEL_INFO(dev)->gen < 4 ||
6182 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6183 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6184 else
6185 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6186 } else
6187 pipeconf |= PIPECONF_PROGRESSIVE;
6188
6189 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6190 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6191
6192 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6193 POSTING_READ(PIPECONF(intel_crtc->pipe));
6194 }
6195
6196 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6197 int x, int y,
6198 struct drm_framebuffer *fb)
6199 {
6200 struct drm_device *dev = crtc->dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 int refclk, num_connectors = 0;
6204 intel_clock_t clock, reduced_clock;
6205 bool ok, has_reduced_clock = false;
6206 bool is_lvds = false, is_dsi = false;
6207 struct intel_encoder *encoder;
6208 const intel_limit_t *limit;
6209
6210 for_each_encoder_on_crtc(dev, crtc, encoder) {
6211 switch (encoder->type) {
6212 case INTEL_OUTPUT_LVDS:
6213 is_lvds = true;
6214 break;
6215 case INTEL_OUTPUT_DSI:
6216 is_dsi = true;
6217 break;
6218 }
6219
6220 num_connectors++;
6221 }
6222
6223 if (is_dsi)
6224 return 0;
6225
6226 if (!intel_crtc->config.clock_set) {
6227 refclk = i9xx_get_refclk(crtc, num_connectors);
6228
6229 /*
6230 * Returns a set of divisors for the desired target clock with
6231 * the given refclk, or FALSE. The returned values represent
6232 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6233 * 2) / p1 / p2.
6234 */
6235 limit = intel_limit(crtc, refclk);
6236 ok = dev_priv->display.find_dpll(limit, crtc,
6237 intel_crtc->config.port_clock,
6238 refclk, NULL, &clock);
6239 if (!ok) {
6240 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6241 return -EINVAL;
6242 }
6243
6244 if (is_lvds && dev_priv->lvds_downclock_avail) {
6245 /*
6246 * Ensure we match the reduced clock's P to the target
6247 * clock. If the clocks don't match, we can't switch
6248 * the display clock by using the FP0/FP1. In such case
6249 * we will disable the LVDS downclock feature.
6250 */
6251 has_reduced_clock =
6252 dev_priv->display.find_dpll(limit, crtc,
6253 dev_priv->lvds_downclock,
6254 refclk, &clock,
6255 &reduced_clock);
6256 }
6257 /* Compat-code for transition, will disappear. */
6258 intel_crtc->config.dpll.n = clock.n;
6259 intel_crtc->config.dpll.m1 = clock.m1;
6260 intel_crtc->config.dpll.m2 = clock.m2;
6261 intel_crtc->config.dpll.p1 = clock.p1;
6262 intel_crtc->config.dpll.p2 = clock.p2;
6263 }
6264
6265 if (IS_GEN2(dev)) {
6266 i8xx_update_pll(intel_crtc,
6267 has_reduced_clock ? &reduced_clock : NULL,
6268 num_connectors);
6269 } else if (IS_CHERRYVIEW(dev)) {
6270 chv_update_pll(intel_crtc);
6271 } else if (IS_VALLEYVIEW(dev)) {
6272 vlv_update_pll(intel_crtc);
6273 } else {
6274 i9xx_update_pll(intel_crtc,
6275 has_reduced_clock ? &reduced_clock : NULL,
6276 num_connectors);
6277 }
6278
6279 return 0;
6280 }
6281
6282 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6283 struct intel_crtc_config *pipe_config)
6284 {
6285 struct drm_device *dev = crtc->base.dev;
6286 struct drm_i915_private *dev_priv = dev->dev_private;
6287 uint32_t tmp;
6288
6289 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6290 return;
6291
6292 tmp = I915_READ(PFIT_CONTROL);
6293 if (!(tmp & PFIT_ENABLE))
6294 return;
6295
6296 /* Check whether the pfit is attached to our pipe. */
6297 if (INTEL_INFO(dev)->gen < 4) {
6298 if (crtc->pipe != PIPE_B)
6299 return;
6300 } else {
6301 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6302 return;
6303 }
6304
6305 pipe_config->gmch_pfit.control = tmp;
6306 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6307 if (INTEL_INFO(dev)->gen < 5)
6308 pipe_config->gmch_pfit.lvds_border_bits =
6309 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6310 }
6311
6312 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6313 struct intel_crtc_config *pipe_config)
6314 {
6315 struct drm_device *dev = crtc->base.dev;
6316 struct drm_i915_private *dev_priv = dev->dev_private;
6317 int pipe = pipe_config->cpu_transcoder;
6318 intel_clock_t clock;
6319 u32 mdiv;
6320 int refclk = 100000;
6321
6322 /* In case of MIPI DPLL will not even be used */
6323 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6324 return;
6325
6326 mutex_lock(&dev_priv->dpio_lock);
6327 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6328 mutex_unlock(&dev_priv->dpio_lock);
6329
6330 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6331 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6332 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6333 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6334 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6335
6336 vlv_clock(refclk, &clock);
6337
6338 /* clock.dot is the fast clock */
6339 pipe_config->port_clock = clock.dot / 5;
6340 }
6341
6342 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6343 struct intel_plane_config *plane_config)
6344 {
6345 struct drm_device *dev = crtc->base.dev;
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 u32 val, base, offset;
6348 int pipe = crtc->pipe, plane = crtc->plane;
6349 int fourcc, pixel_format;
6350 int aligned_height;
6351
6352 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6353 if (!crtc->base.primary->fb) {
6354 DRM_DEBUG_KMS("failed to alloc fb\n");
6355 return;
6356 }
6357
6358 val = I915_READ(DSPCNTR(plane));
6359
6360 if (INTEL_INFO(dev)->gen >= 4)
6361 if (val & DISPPLANE_TILED)
6362 plane_config->tiled = true;
6363
6364 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6365 fourcc = intel_format_to_fourcc(pixel_format);
6366 crtc->base.primary->fb->pixel_format = fourcc;
6367 crtc->base.primary->fb->bits_per_pixel =
6368 drm_format_plane_cpp(fourcc, 0) * 8;
6369
6370 if (INTEL_INFO(dev)->gen >= 4) {
6371 if (plane_config->tiled)
6372 offset = I915_READ(DSPTILEOFF(plane));
6373 else
6374 offset = I915_READ(DSPLINOFF(plane));
6375 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6376 } else {
6377 base = I915_READ(DSPADDR(plane));
6378 }
6379 plane_config->base = base;
6380
6381 val = I915_READ(PIPESRC(pipe));
6382 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6383 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6384
6385 val = I915_READ(DSPSTRIDE(pipe));
6386 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6387
6388 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6389 plane_config->tiled);
6390
6391 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6392 aligned_height);
6393
6394 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6395 pipe, plane, crtc->base.primary->fb->width,
6396 crtc->base.primary->fb->height,
6397 crtc->base.primary->fb->bits_per_pixel, base,
6398 crtc->base.primary->fb->pitches[0],
6399 plane_config->size);
6400
6401 }
6402
6403 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6404 struct intel_crtc_config *pipe_config)
6405 {
6406 struct drm_device *dev = crtc->base.dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 int pipe = pipe_config->cpu_transcoder;
6409 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6410 intel_clock_t clock;
6411 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6412 int refclk = 100000;
6413
6414 mutex_lock(&dev_priv->dpio_lock);
6415 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6416 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6417 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6418 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6419 mutex_unlock(&dev_priv->dpio_lock);
6420
6421 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6422 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6423 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6424 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6425 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6426
6427 chv_clock(refclk, &clock);
6428
6429 /* clock.dot is the fast clock */
6430 pipe_config->port_clock = clock.dot / 5;
6431 }
6432
6433 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6434 struct intel_crtc_config *pipe_config)
6435 {
6436 struct drm_device *dev = crtc->base.dev;
6437 struct drm_i915_private *dev_priv = dev->dev_private;
6438 uint32_t tmp;
6439
6440 if (!intel_display_power_enabled(dev_priv,
6441 POWER_DOMAIN_PIPE(crtc->pipe)))
6442 return false;
6443
6444 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6445 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6446
6447 tmp = I915_READ(PIPECONF(crtc->pipe));
6448 if (!(tmp & PIPECONF_ENABLE))
6449 return false;
6450
6451 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6452 switch (tmp & PIPECONF_BPC_MASK) {
6453 case PIPECONF_6BPC:
6454 pipe_config->pipe_bpp = 18;
6455 break;
6456 case PIPECONF_8BPC:
6457 pipe_config->pipe_bpp = 24;
6458 break;
6459 case PIPECONF_10BPC:
6460 pipe_config->pipe_bpp = 30;
6461 break;
6462 default:
6463 break;
6464 }
6465 }
6466
6467 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6468 pipe_config->limited_color_range = true;
6469
6470 if (INTEL_INFO(dev)->gen < 4)
6471 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6472
6473 intel_get_pipe_timings(crtc, pipe_config);
6474
6475 i9xx_get_pfit_config(crtc, pipe_config);
6476
6477 if (INTEL_INFO(dev)->gen >= 4) {
6478 tmp = I915_READ(DPLL_MD(crtc->pipe));
6479 pipe_config->pixel_multiplier =
6480 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6481 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6482 pipe_config->dpll_hw_state.dpll_md = tmp;
6483 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6484 tmp = I915_READ(DPLL(crtc->pipe));
6485 pipe_config->pixel_multiplier =
6486 ((tmp & SDVO_MULTIPLIER_MASK)
6487 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6488 } else {
6489 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6490 * port and will be fixed up in the encoder->get_config
6491 * function. */
6492 pipe_config->pixel_multiplier = 1;
6493 }
6494 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6495 if (!IS_VALLEYVIEW(dev)) {
6496 /*
6497 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6498 * on 830. Filter it out here so that we don't
6499 * report errors due to that.
6500 */
6501 if (IS_I830(dev))
6502 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6503
6504 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6505 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6506 } else {
6507 /* Mask out read-only status bits. */
6508 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6509 DPLL_PORTC_READY_MASK |
6510 DPLL_PORTB_READY_MASK);
6511 }
6512
6513 if (IS_CHERRYVIEW(dev))
6514 chv_crtc_clock_get(crtc, pipe_config);
6515 else if (IS_VALLEYVIEW(dev))
6516 vlv_crtc_clock_get(crtc, pipe_config);
6517 else
6518 i9xx_crtc_clock_get(crtc, pipe_config);
6519
6520 return true;
6521 }
6522
6523 static void ironlake_init_pch_refclk(struct drm_device *dev)
6524 {
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 struct intel_encoder *encoder;
6527 u32 val, final;
6528 bool has_lvds = false;
6529 bool has_cpu_edp = false;
6530 bool has_panel = false;
6531 bool has_ck505 = false;
6532 bool can_ssc = false;
6533
6534 /* We need to take the global config into account */
6535 for_each_intel_encoder(dev, encoder) {
6536 switch (encoder->type) {
6537 case INTEL_OUTPUT_LVDS:
6538 has_panel = true;
6539 has_lvds = true;
6540 break;
6541 case INTEL_OUTPUT_EDP:
6542 has_panel = true;
6543 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6544 has_cpu_edp = true;
6545 break;
6546 }
6547 }
6548
6549 if (HAS_PCH_IBX(dev)) {
6550 has_ck505 = dev_priv->vbt.display_clock_mode;
6551 can_ssc = has_ck505;
6552 } else {
6553 has_ck505 = false;
6554 can_ssc = true;
6555 }
6556
6557 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6558 has_panel, has_lvds, has_ck505);
6559
6560 /* Ironlake: try to setup display ref clock before DPLL
6561 * enabling. This is only under driver's control after
6562 * PCH B stepping, previous chipset stepping should be
6563 * ignoring this setting.
6564 */
6565 val = I915_READ(PCH_DREF_CONTROL);
6566
6567 /* As we must carefully and slowly disable/enable each source in turn,
6568 * compute the final state we want first and check if we need to
6569 * make any changes at all.
6570 */
6571 final = val;
6572 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6573 if (has_ck505)
6574 final |= DREF_NONSPREAD_CK505_ENABLE;
6575 else
6576 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6577
6578 final &= ~DREF_SSC_SOURCE_MASK;
6579 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6580 final &= ~DREF_SSC1_ENABLE;
6581
6582 if (has_panel) {
6583 final |= DREF_SSC_SOURCE_ENABLE;
6584
6585 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6586 final |= DREF_SSC1_ENABLE;
6587
6588 if (has_cpu_edp) {
6589 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6590 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6591 else
6592 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6593 } else
6594 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6595 } else {
6596 final |= DREF_SSC_SOURCE_DISABLE;
6597 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6598 }
6599
6600 if (final == val)
6601 return;
6602
6603 /* Always enable nonspread source */
6604 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6605
6606 if (has_ck505)
6607 val |= DREF_NONSPREAD_CK505_ENABLE;
6608 else
6609 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6610
6611 if (has_panel) {
6612 val &= ~DREF_SSC_SOURCE_MASK;
6613 val |= DREF_SSC_SOURCE_ENABLE;
6614
6615 /* SSC must be turned on before enabling the CPU output */
6616 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6617 DRM_DEBUG_KMS("Using SSC on panel\n");
6618 val |= DREF_SSC1_ENABLE;
6619 } else
6620 val &= ~DREF_SSC1_ENABLE;
6621
6622 /* Get SSC going before enabling the outputs */
6623 I915_WRITE(PCH_DREF_CONTROL, val);
6624 POSTING_READ(PCH_DREF_CONTROL);
6625 udelay(200);
6626
6627 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6628
6629 /* Enable CPU source on CPU attached eDP */
6630 if (has_cpu_edp) {
6631 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6632 DRM_DEBUG_KMS("Using SSC on eDP\n");
6633 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6634 } else
6635 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6636 } else
6637 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6638
6639 I915_WRITE(PCH_DREF_CONTROL, val);
6640 POSTING_READ(PCH_DREF_CONTROL);
6641 udelay(200);
6642 } else {
6643 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6644
6645 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6646
6647 /* Turn off CPU output */
6648 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6649
6650 I915_WRITE(PCH_DREF_CONTROL, val);
6651 POSTING_READ(PCH_DREF_CONTROL);
6652 udelay(200);
6653
6654 /* Turn off the SSC source */
6655 val &= ~DREF_SSC_SOURCE_MASK;
6656 val |= DREF_SSC_SOURCE_DISABLE;
6657
6658 /* Turn off SSC1 */
6659 val &= ~DREF_SSC1_ENABLE;
6660
6661 I915_WRITE(PCH_DREF_CONTROL, val);
6662 POSTING_READ(PCH_DREF_CONTROL);
6663 udelay(200);
6664 }
6665
6666 BUG_ON(val != final);
6667 }
6668
6669 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6670 {
6671 uint32_t tmp;
6672
6673 tmp = I915_READ(SOUTH_CHICKEN2);
6674 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6675 I915_WRITE(SOUTH_CHICKEN2, tmp);
6676
6677 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6678 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6679 DRM_ERROR("FDI mPHY reset assert timeout\n");
6680
6681 tmp = I915_READ(SOUTH_CHICKEN2);
6682 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6683 I915_WRITE(SOUTH_CHICKEN2, tmp);
6684
6685 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6686 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6687 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6688 }
6689
6690 /* WaMPhyProgramming:hsw */
6691 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6692 {
6693 uint32_t tmp;
6694
6695 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6696 tmp &= ~(0xFF << 24);
6697 tmp |= (0x12 << 24);
6698 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6699
6700 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6701 tmp |= (1 << 11);
6702 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6703
6704 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6705 tmp |= (1 << 11);
6706 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6707
6708 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6709 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6710 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6711
6712 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6713 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6714 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6715
6716 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6717 tmp &= ~(7 << 13);
6718 tmp |= (5 << 13);
6719 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6720
6721 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6722 tmp &= ~(7 << 13);
6723 tmp |= (5 << 13);
6724 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6725
6726 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6727 tmp &= ~0xFF;
6728 tmp |= 0x1C;
6729 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6730
6731 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6732 tmp &= ~0xFF;
6733 tmp |= 0x1C;
6734 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6735
6736 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6737 tmp &= ~(0xFF << 16);
6738 tmp |= (0x1C << 16);
6739 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6740
6741 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6742 tmp &= ~(0xFF << 16);
6743 tmp |= (0x1C << 16);
6744 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6745
6746 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6747 tmp |= (1 << 27);
6748 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6749
6750 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6751 tmp |= (1 << 27);
6752 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6753
6754 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6755 tmp &= ~(0xF << 28);
6756 tmp |= (4 << 28);
6757 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6758
6759 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6760 tmp &= ~(0xF << 28);
6761 tmp |= (4 << 28);
6762 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6763 }
6764
6765 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6766 * Programming" based on the parameters passed:
6767 * - Sequence to enable CLKOUT_DP
6768 * - Sequence to enable CLKOUT_DP without spread
6769 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6770 */
6771 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6772 bool with_fdi)
6773 {
6774 struct drm_i915_private *dev_priv = dev->dev_private;
6775 uint32_t reg, tmp;
6776
6777 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6778 with_spread = true;
6779 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6780 with_fdi, "LP PCH doesn't have FDI\n"))
6781 with_fdi = false;
6782
6783 mutex_lock(&dev_priv->dpio_lock);
6784
6785 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6786 tmp &= ~SBI_SSCCTL_DISABLE;
6787 tmp |= SBI_SSCCTL_PATHALT;
6788 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6789
6790 udelay(24);
6791
6792 if (with_spread) {
6793 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6794 tmp &= ~SBI_SSCCTL_PATHALT;
6795 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6796
6797 if (with_fdi) {
6798 lpt_reset_fdi_mphy(dev_priv);
6799 lpt_program_fdi_mphy(dev_priv);
6800 }
6801 }
6802
6803 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6804 SBI_GEN0 : SBI_DBUFF0;
6805 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6806 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6807 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6808
6809 mutex_unlock(&dev_priv->dpio_lock);
6810 }
6811
6812 /* Sequence to disable CLKOUT_DP */
6813 static void lpt_disable_clkout_dp(struct drm_device *dev)
6814 {
6815 struct drm_i915_private *dev_priv = dev->dev_private;
6816 uint32_t reg, tmp;
6817
6818 mutex_lock(&dev_priv->dpio_lock);
6819
6820 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6821 SBI_GEN0 : SBI_DBUFF0;
6822 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6823 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6824 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6825
6826 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6827 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6828 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6829 tmp |= SBI_SSCCTL_PATHALT;
6830 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6831 udelay(32);
6832 }
6833 tmp |= SBI_SSCCTL_DISABLE;
6834 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6835 }
6836
6837 mutex_unlock(&dev_priv->dpio_lock);
6838 }
6839
6840 static void lpt_init_pch_refclk(struct drm_device *dev)
6841 {
6842 struct intel_encoder *encoder;
6843 bool has_vga = false;
6844
6845 for_each_intel_encoder(dev, encoder) {
6846 switch (encoder->type) {
6847 case INTEL_OUTPUT_ANALOG:
6848 has_vga = true;
6849 break;
6850 }
6851 }
6852
6853 if (has_vga)
6854 lpt_enable_clkout_dp(dev, true, true);
6855 else
6856 lpt_disable_clkout_dp(dev);
6857 }
6858
6859 /*
6860 * Initialize reference clocks when the driver loads
6861 */
6862 void intel_init_pch_refclk(struct drm_device *dev)
6863 {
6864 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6865 ironlake_init_pch_refclk(dev);
6866 else if (HAS_PCH_LPT(dev))
6867 lpt_init_pch_refclk(dev);
6868 }
6869
6870 static int ironlake_get_refclk(struct drm_crtc *crtc)
6871 {
6872 struct drm_device *dev = crtc->dev;
6873 struct drm_i915_private *dev_priv = dev->dev_private;
6874 struct intel_encoder *encoder;
6875 int num_connectors = 0;
6876 bool is_lvds = false;
6877
6878 for_each_encoder_on_crtc(dev, crtc, encoder) {
6879 switch (encoder->type) {
6880 case INTEL_OUTPUT_LVDS:
6881 is_lvds = true;
6882 break;
6883 }
6884 num_connectors++;
6885 }
6886
6887 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6888 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6889 dev_priv->vbt.lvds_ssc_freq);
6890 return dev_priv->vbt.lvds_ssc_freq;
6891 }
6892
6893 return 120000;
6894 }
6895
6896 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6897 {
6898 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6900 int pipe = intel_crtc->pipe;
6901 uint32_t val;
6902
6903 val = 0;
6904
6905 switch (intel_crtc->config.pipe_bpp) {
6906 case 18:
6907 val |= PIPECONF_6BPC;
6908 break;
6909 case 24:
6910 val |= PIPECONF_8BPC;
6911 break;
6912 case 30:
6913 val |= PIPECONF_10BPC;
6914 break;
6915 case 36:
6916 val |= PIPECONF_12BPC;
6917 break;
6918 default:
6919 /* Case prevented by intel_choose_pipe_bpp_dither. */
6920 BUG();
6921 }
6922
6923 if (intel_crtc->config.dither)
6924 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6925
6926 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6927 val |= PIPECONF_INTERLACED_ILK;
6928 else
6929 val |= PIPECONF_PROGRESSIVE;
6930
6931 if (intel_crtc->config.limited_color_range)
6932 val |= PIPECONF_COLOR_RANGE_SELECT;
6933
6934 I915_WRITE(PIPECONF(pipe), val);
6935 POSTING_READ(PIPECONF(pipe));
6936 }
6937
6938 /*
6939 * Set up the pipe CSC unit.
6940 *
6941 * Currently only full range RGB to limited range RGB conversion
6942 * is supported, but eventually this should handle various
6943 * RGB<->YCbCr scenarios as well.
6944 */
6945 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6946 {
6947 struct drm_device *dev = crtc->dev;
6948 struct drm_i915_private *dev_priv = dev->dev_private;
6949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6950 int pipe = intel_crtc->pipe;
6951 uint16_t coeff = 0x7800; /* 1.0 */
6952
6953 /*
6954 * TODO: Check what kind of values actually come out of the pipe
6955 * with these coeff/postoff values and adjust to get the best
6956 * accuracy. Perhaps we even need to take the bpc value into
6957 * consideration.
6958 */
6959
6960 if (intel_crtc->config.limited_color_range)
6961 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6962
6963 /*
6964 * GY/GU and RY/RU should be the other way around according
6965 * to BSpec, but reality doesn't agree. Just set them up in
6966 * a way that results in the correct picture.
6967 */
6968 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6969 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6970
6971 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6972 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6973
6974 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6975 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6976
6977 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6978 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6979 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6980
6981 if (INTEL_INFO(dev)->gen > 6) {
6982 uint16_t postoff = 0;
6983
6984 if (intel_crtc->config.limited_color_range)
6985 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6986
6987 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6988 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6989 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6990
6991 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6992 } else {
6993 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6994
6995 if (intel_crtc->config.limited_color_range)
6996 mode |= CSC_BLACK_SCREEN_OFFSET;
6997
6998 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6999 }
7000 }
7001
7002 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7003 {
7004 struct drm_device *dev = crtc->dev;
7005 struct drm_i915_private *dev_priv = dev->dev_private;
7006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7007 enum pipe pipe = intel_crtc->pipe;
7008 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7009 uint32_t val;
7010
7011 val = 0;
7012
7013 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7014 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7015
7016 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7017 val |= PIPECONF_INTERLACED_ILK;
7018 else
7019 val |= PIPECONF_PROGRESSIVE;
7020
7021 I915_WRITE(PIPECONF(cpu_transcoder), val);
7022 POSTING_READ(PIPECONF(cpu_transcoder));
7023
7024 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7025 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7026
7027 if (IS_BROADWELL(dev)) {
7028 val = 0;
7029
7030 switch (intel_crtc->config.pipe_bpp) {
7031 case 18:
7032 val |= PIPEMISC_DITHER_6_BPC;
7033 break;
7034 case 24:
7035 val |= PIPEMISC_DITHER_8_BPC;
7036 break;
7037 case 30:
7038 val |= PIPEMISC_DITHER_10_BPC;
7039 break;
7040 case 36:
7041 val |= PIPEMISC_DITHER_12_BPC;
7042 break;
7043 default:
7044 /* Case prevented by pipe_config_set_bpp. */
7045 BUG();
7046 }
7047
7048 if (intel_crtc->config.dither)
7049 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7050
7051 I915_WRITE(PIPEMISC(pipe), val);
7052 }
7053 }
7054
7055 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7056 intel_clock_t *clock,
7057 bool *has_reduced_clock,
7058 intel_clock_t *reduced_clock)
7059 {
7060 struct drm_device *dev = crtc->dev;
7061 struct drm_i915_private *dev_priv = dev->dev_private;
7062 struct intel_encoder *intel_encoder;
7063 int refclk;
7064 const intel_limit_t *limit;
7065 bool ret, is_lvds = false;
7066
7067 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7068 switch (intel_encoder->type) {
7069 case INTEL_OUTPUT_LVDS:
7070 is_lvds = true;
7071 break;
7072 }
7073 }
7074
7075 refclk = ironlake_get_refclk(crtc);
7076
7077 /*
7078 * Returns a set of divisors for the desired target clock with the given
7079 * refclk, or FALSE. The returned values represent the clock equation:
7080 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7081 */
7082 limit = intel_limit(crtc, refclk);
7083 ret = dev_priv->display.find_dpll(limit, crtc,
7084 to_intel_crtc(crtc)->config.port_clock,
7085 refclk, NULL, clock);
7086 if (!ret)
7087 return false;
7088
7089 if (is_lvds && dev_priv->lvds_downclock_avail) {
7090 /*
7091 * Ensure we match the reduced clock's P to the target clock.
7092 * If the clocks don't match, we can't switch the display clock
7093 * by using the FP0/FP1. In such case we will disable the LVDS
7094 * downclock feature.
7095 */
7096 *has_reduced_clock =
7097 dev_priv->display.find_dpll(limit, crtc,
7098 dev_priv->lvds_downclock,
7099 refclk, clock,
7100 reduced_clock);
7101 }
7102
7103 return true;
7104 }
7105
7106 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7107 {
7108 /*
7109 * Account for spread spectrum to avoid
7110 * oversubscribing the link. Max center spread
7111 * is 2.5%; use 5% for safety's sake.
7112 */
7113 u32 bps = target_clock * bpp * 21 / 20;
7114 return DIV_ROUND_UP(bps, link_bw * 8);
7115 }
7116
7117 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7118 {
7119 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7120 }
7121
7122 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7123 u32 *fp,
7124 intel_clock_t *reduced_clock, u32 *fp2)
7125 {
7126 struct drm_crtc *crtc = &intel_crtc->base;
7127 struct drm_device *dev = crtc->dev;
7128 struct drm_i915_private *dev_priv = dev->dev_private;
7129 struct intel_encoder *intel_encoder;
7130 uint32_t dpll;
7131 int factor, num_connectors = 0;
7132 bool is_lvds = false, is_sdvo = false;
7133
7134 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7135 switch (intel_encoder->type) {
7136 case INTEL_OUTPUT_LVDS:
7137 is_lvds = true;
7138 break;
7139 case INTEL_OUTPUT_SDVO:
7140 case INTEL_OUTPUT_HDMI:
7141 is_sdvo = true;
7142 break;
7143 }
7144
7145 num_connectors++;
7146 }
7147
7148 /* Enable autotuning of the PLL clock (if permissible) */
7149 factor = 21;
7150 if (is_lvds) {
7151 if ((intel_panel_use_ssc(dev_priv) &&
7152 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7153 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7154 factor = 25;
7155 } else if (intel_crtc->config.sdvo_tv_clock)
7156 factor = 20;
7157
7158 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7159 *fp |= FP_CB_TUNE;
7160
7161 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7162 *fp2 |= FP_CB_TUNE;
7163
7164 dpll = 0;
7165
7166 if (is_lvds)
7167 dpll |= DPLLB_MODE_LVDS;
7168 else
7169 dpll |= DPLLB_MODE_DAC_SERIAL;
7170
7171 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7172 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7173
7174 if (is_sdvo)
7175 dpll |= DPLL_SDVO_HIGH_SPEED;
7176 if (intel_crtc->config.has_dp_encoder)
7177 dpll |= DPLL_SDVO_HIGH_SPEED;
7178
7179 /* compute bitmask from p1 value */
7180 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7181 /* also FPA1 */
7182 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7183
7184 switch (intel_crtc->config.dpll.p2) {
7185 case 5:
7186 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7187 break;
7188 case 7:
7189 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7190 break;
7191 case 10:
7192 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7193 break;
7194 case 14:
7195 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7196 break;
7197 }
7198
7199 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7200 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7201 else
7202 dpll |= PLL_REF_INPUT_DREFCLK;
7203
7204 return dpll | DPLL_VCO_ENABLE;
7205 }
7206
7207 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7208 int x, int y,
7209 struct drm_framebuffer *fb)
7210 {
7211 struct drm_device *dev = crtc->dev;
7212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7213 int num_connectors = 0;
7214 intel_clock_t clock, reduced_clock;
7215 u32 dpll = 0, fp = 0, fp2 = 0;
7216 bool ok, has_reduced_clock = false;
7217 bool is_lvds = false;
7218 struct intel_encoder *encoder;
7219 struct intel_shared_dpll *pll;
7220
7221 for_each_encoder_on_crtc(dev, crtc, encoder) {
7222 switch (encoder->type) {
7223 case INTEL_OUTPUT_LVDS:
7224 is_lvds = true;
7225 break;
7226 }
7227
7228 num_connectors++;
7229 }
7230
7231 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7232 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7233
7234 ok = ironlake_compute_clocks(crtc, &clock,
7235 &has_reduced_clock, &reduced_clock);
7236 if (!ok && !intel_crtc->config.clock_set) {
7237 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7238 return -EINVAL;
7239 }
7240 /* Compat-code for transition, will disappear. */
7241 if (!intel_crtc->config.clock_set) {
7242 intel_crtc->config.dpll.n = clock.n;
7243 intel_crtc->config.dpll.m1 = clock.m1;
7244 intel_crtc->config.dpll.m2 = clock.m2;
7245 intel_crtc->config.dpll.p1 = clock.p1;
7246 intel_crtc->config.dpll.p2 = clock.p2;
7247 }
7248
7249 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7250 if (intel_crtc->config.has_pch_encoder) {
7251 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7252 if (has_reduced_clock)
7253 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7254
7255 dpll = ironlake_compute_dpll(intel_crtc,
7256 &fp, &reduced_clock,
7257 has_reduced_clock ? &fp2 : NULL);
7258
7259 intel_crtc->config.dpll_hw_state.dpll = dpll;
7260 intel_crtc->config.dpll_hw_state.fp0 = fp;
7261 if (has_reduced_clock)
7262 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7263 else
7264 intel_crtc->config.dpll_hw_state.fp1 = fp;
7265
7266 pll = intel_get_shared_dpll(intel_crtc);
7267 if (pll == NULL) {
7268 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7269 pipe_name(intel_crtc->pipe));
7270 return -EINVAL;
7271 }
7272 } else
7273 intel_put_shared_dpll(intel_crtc);
7274
7275 if (is_lvds && has_reduced_clock && i915.powersave)
7276 intel_crtc->lowfreq_avail = true;
7277 else
7278 intel_crtc->lowfreq_avail = false;
7279
7280 return 0;
7281 }
7282
7283 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7284 struct intel_link_m_n *m_n)
7285 {
7286 struct drm_device *dev = crtc->base.dev;
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 enum pipe pipe = crtc->pipe;
7289
7290 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7291 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7292 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7293 & ~TU_SIZE_MASK;
7294 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7295 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7296 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7297 }
7298
7299 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7300 enum transcoder transcoder,
7301 struct intel_link_m_n *m_n,
7302 struct intel_link_m_n *m2_n2)
7303 {
7304 struct drm_device *dev = crtc->base.dev;
7305 struct drm_i915_private *dev_priv = dev->dev_private;
7306 enum pipe pipe = crtc->pipe;
7307
7308 if (INTEL_INFO(dev)->gen >= 5) {
7309 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7310 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7311 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7312 & ~TU_SIZE_MASK;
7313 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7314 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7315 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7316 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7317 * gen < 8) and if DRRS is supported (to make sure the
7318 * registers are not unnecessarily read).
7319 */
7320 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7321 crtc->config.has_drrs) {
7322 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7323 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7324 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7325 & ~TU_SIZE_MASK;
7326 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7327 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7328 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7329 }
7330 } else {
7331 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7332 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7333 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7334 & ~TU_SIZE_MASK;
7335 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7336 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7337 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7338 }
7339 }
7340
7341 void intel_dp_get_m_n(struct intel_crtc *crtc,
7342 struct intel_crtc_config *pipe_config)
7343 {
7344 if (crtc->config.has_pch_encoder)
7345 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7346 else
7347 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7348 &pipe_config->dp_m_n,
7349 &pipe_config->dp_m2_n2);
7350 }
7351
7352 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7353 struct intel_crtc_config *pipe_config)
7354 {
7355 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7356 &pipe_config->fdi_m_n, NULL);
7357 }
7358
7359 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7360 struct intel_crtc_config *pipe_config)
7361 {
7362 struct drm_device *dev = crtc->base.dev;
7363 struct drm_i915_private *dev_priv = dev->dev_private;
7364 uint32_t tmp;
7365
7366 tmp = I915_READ(PF_CTL(crtc->pipe));
7367
7368 if (tmp & PF_ENABLE) {
7369 pipe_config->pch_pfit.enabled = true;
7370 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7371 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7372
7373 /* We currently do not free assignements of panel fitters on
7374 * ivb/hsw (since we don't use the higher upscaling modes which
7375 * differentiates them) so just WARN about this case for now. */
7376 if (IS_GEN7(dev)) {
7377 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7378 PF_PIPE_SEL_IVB(crtc->pipe));
7379 }
7380 }
7381 }
7382
7383 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7384 struct intel_plane_config *plane_config)
7385 {
7386 struct drm_device *dev = crtc->base.dev;
7387 struct drm_i915_private *dev_priv = dev->dev_private;
7388 u32 val, base, offset;
7389 int pipe = crtc->pipe, plane = crtc->plane;
7390 int fourcc, pixel_format;
7391 int aligned_height;
7392
7393 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7394 if (!crtc->base.primary->fb) {
7395 DRM_DEBUG_KMS("failed to alloc fb\n");
7396 return;
7397 }
7398
7399 val = I915_READ(DSPCNTR(plane));
7400
7401 if (INTEL_INFO(dev)->gen >= 4)
7402 if (val & DISPPLANE_TILED)
7403 plane_config->tiled = true;
7404
7405 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7406 fourcc = intel_format_to_fourcc(pixel_format);
7407 crtc->base.primary->fb->pixel_format = fourcc;
7408 crtc->base.primary->fb->bits_per_pixel =
7409 drm_format_plane_cpp(fourcc, 0) * 8;
7410
7411 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7412 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7413 offset = I915_READ(DSPOFFSET(plane));
7414 } else {
7415 if (plane_config->tiled)
7416 offset = I915_READ(DSPTILEOFF(plane));
7417 else
7418 offset = I915_READ(DSPLINOFF(plane));
7419 }
7420 plane_config->base = base;
7421
7422 val = I915_READ(PIPESRC(pipe));
7423 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7424 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7425
7426 val = I915_READ(DSPSTRIDE(pipe));
7427 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7428
7429 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7430 plane_config->tiled);
7431
7432 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7433 aligned_height);
7434
7435 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7436 pipe, plane, crtc->base.primary->fb->width,
7437 crtc->base.primary->fb->height,
7438 crtc->base.primary->fb->bits_per_pixel, base,
7439 crtc->base.primary->fb->pitches[0],
7440 plane_config->size);
7441 }
7442
7443 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7444 struct intel_crtc_config *pipe_config)
7445 {
7446 struct drm_device *dev = crtc->base.dev;
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 uint32_t tmp;
7449
7450 if (!intel_display_power_enabled(dev_priv,
7451 POWER_DOMAIN_PIPE(crtc->pipe)))
7452 return false;
7453
7454 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7455 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7456
7457 tmp = I915_READ(PIPECONF(crtc->pipe));
7458 if (!(tmp & PIPECONF_ENABLE))
7459 return false;
7460
7461 switch (tmp & PIPECONF_BPC_MASK) {
7462 case PIPECONF_6BPC:
7463 pipe_config->pipe_bpp = 18;
7464 break;
7465 case PIPECONF_8BPC:
7466 pipe_config->pipe_bpp = 24;
7467 break;
7468 case PIPECONF_10BPC:
7469 pipe_config->pipe_bpp = 30;
7470 break;
7471 case PIPECONF_12BPC:
7472 pipe_config->pipe_bpp = 36;
7473 break;
7474 default:
7475 break;
7476 }
7477
7478 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7479 pipe_config->limited_color_range = true;
7480
7481 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7482 struct intel_shared_dpll *pll;
7483
7484 pipe_config->has_pch_encoder = true;
7485
7486 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7487 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7488 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7489
7490 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7491
7492 if (HAS_PCH_IBX(dev_priv->dev)) {
7493 pipe_config->shared_dpll =
7494 (enum intel_dpll_id) crtc->pipe;
7495 } else {
7496 tmp = I915_READ(PCH_DPLL_SEL);
7497 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7498 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7499 else
7500 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7501 }
7502
7503 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7504
7505 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7506 &pipe_config->dpll_hw_state));
7507
7508 tmp = pipe_config->dpll_hw_state.dpll;
7509 pipe_config->pixel_multiplier =
7510 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7511 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7512
7513 ironlake_pch_clock_get(crtc, pipe_config);
7514 } else {
7515 pipe_config->pixel_multiplier = 1;
7516 }
7517
7518 intel_get_pipe_timings(crtc, pipe_config);
7519
7520 ironlake_get_pfit_config(crtc, pipe_config);
7521
7522 return true;
7523 }
7524
7525 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7526 {
7527 struct drm_device *dev = dev_priv->dev;
7528 struct intel_crtc *crtc;
7529
7530 for_each_intel_crtc(dev, crtc)
7531 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7532 pipe_name(crtc->pipe));
7533
7534 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7535 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7536 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7537 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7538 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7539 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7540 "CPU PWM1 enabled\n");
7541 if (IS_HASWELL(dev))
7542 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7543 "CPU PWM2 enabled\n");
7544 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7545 "PCH PWM1 enabled\n");
7546 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7547 "Utility pin enabled\n");
7548 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7549
7550 /*
7551 * In theory we can still leave IRQs enabled, as long as only the HPD
7552 * interrupts remain enabled. We used to check for that, but since it's
7553 * gen-specific and since we only disable LCPLL after we fully disable
7554 * the interrupts, the check below should be enough.
7555 */
7556 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7557 }
7558
7559 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7560 {
7561 struct drm_device *dev = dev_priv->dev;
7562
7563 if (IS_HASWELL(dev))
7564 return I915_READ(D_COMP_HSW);
7565 else
7566 return I915_READ(D_COMP_BDW);
7567 }
7568
7569 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7570 {
7571 struct drm_device *dev = dev_priv->dev;
7572
7573 if (IS_HASWELL(dev)) {
7574 mutex_lock(&dev_priv->rps.hw_lock);
7575 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7576 val))
7577 DRM_ERROR("Failed to write to D_COMP\n");
7578 mutex_unlock(&dev_priv->rps.hw_lock);
7579 } else {
7580 I915_WRITE(D_COMP_BDW, val);
7581 POSTING_READ(D_COMP_BDW);
7582 }
7583 }
7584
7585 /*
7586 * This function implements pieces of two sequences from BSpec:
7587 * - Sequence for display software to disable LCPLL
7588 * - Sequence for display software to allow package C8+
7589 * The steps implemented here are just the steps that actually touch the LCPLL
7590 * register. Callers should take care of disabling all the display engine
7591 * functions, doing the mode unset, fixing interrupts, etc.
7592 */
7593 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7594 bool switch_to_fclk, bool allow_power_down)
7595 {
7596 uint32_t val;
7597
7598 assert_can_disable_lcpll(dev_priv);
7599
7600 val = I915_READ(LCPLL_CTL);
7601
7602 if (switch_to_fclk) {
7603 val |= LCPLL_CD_SOURCE_FCLK;
7604 I915_WRITE(LCPLL_CTL, val);
7605
7606 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7607 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7608 DRM_ERROR("Switching to FCLK failed\n");
7609
7610 val = I915_READ(LCPLL_CTL);
7611 }
7612
7613 val |= LCPLL_PLL_DISABLE;
7614 I915_WRITE(LCPLL_CTL, val);
7615 POSTING_READ(LCPLL_CTL);
7616
7617 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7618 DRM_ERROR("LCPLL still locked\n");
7619
7620 val = hsw_read_dcomp(dev_priv);
7621 val |= D_COMP_COMP_DISABLE;
7622 hsw_write_dcomp(dev_priv, val);
7623 ndelay(100);
7624
7625 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7626 1))
7627 DRM_ERROR("D_COMP RCOMP still in progress\n");
7628
7629 if (allow_power_down) {
7630 val = I915_READ(LCPLL_CTL);
7631 val |= LCPLL_POWER_DOWN_ALLOW;
7632 I915_WRITE(LCPLL_CTL, val);
7633 POSTING_READ(LCPLL_CTL);
7634 }
7635 }
7636
7637 /*
7638 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7639 * source.
7640 */
7641 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7642 {
7643 uint32_t val;
7644 unsigned long irqflags;
7645
7646 val = I915_READ(LCPLL_CTL);
7647
7648 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7649 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7650 return;
7651
7652 /*
7653 * Make sure we're not on PC8 state before disabling PC8, otherwise
7654 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7655 *
7656 * The other problem is that hsw_restore_lcpll() is called as part of
7657 * the runtime PM resume sequence, so we can't just call
7658 * gen6_gt_force_wake_get() because that function calls
7659 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7660 * while we are on the resume sequence. So to solve this problem we have
7661 * to call special forcewake code that doesn't touch runtime PM and
7662 * doesn't enable the forcewake delayed work.
7663 */
7664 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7665 if (dev_priv->uncore.forcewake_count++ == 0)
7666 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7667 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7668
7669 if (val & LCPLL_POWER_DOWN_ALLOW) {
7670 val &= ~LCPLL_POWER_DOWN_ALLOW;
7671 I915_WRITE(LCPLL_CTL, val);
7672 POSTING_READ(LCPLL_CTL);
7673 }
7674
7675 val = hsw_read_dcomp(dev_priv);
7676 val |= D_COMP_COMP_FORCE;
7677 val &= ~D_COMP_COMP_DISABLE;
7678 hsw_write_dcomp(dev_priv, val);
7679
7680 val = I915_READ(LCPLL_CTL);
7681 val &= ~LCPLL_PLL_DISABLE;
7682 I915_WRITE(LCPLL_CTL, val);
7683
7684 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7685 DRM_ERROR("LCPLL not locked yet\n");
7686
7687 if (val & LCPLL_CD_SOURCE_FCLK) {
7688 val = I915_READ(LCPLL_CTL);
7689 val &= ~LCPLL_CD_SOURCE_FCLK;
7690 I915_WRITE(LCPLL_CTL, val);
7691
7692 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7693 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7694 DRM_ERROR("Switching back to LCPLL failed\n");
7695 }
7696
7697 /* See the big comment above. */
7698 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7699 if (--dev_priv->uncore.forcewake_count == 0)
7700 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7701 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7702 }
7703
7704 /*
7705 * Package states C8 and deeper are really deep PC states that can only be
7706 * reached when all the devices on the system allow it, so even if the graphics
7707 * device allows PC8+, it doesn't mean the system will actually get to these
7708 * states. Our driver only allows PC8+ when going into runtime PM.
7709 *
7710 * The requirements for PC8+ are that all the outputs are disabled, the power
7711 * well is disabled and most interrupts are disabled, and these are also
7712 * requirements for runtime PM. When these conditions are met, we manually do
7713 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7714 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7715 * hang the machine.
7716 *
7717 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7718 * the state of some registers, so when we come back from PC8+ we need to
7719 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7720 * need to take care of the registers kept by RC6. Notice that this happens even
7721 * if we don't put the device in PCI D3 state (which is what currently happens
7722 * because of the runtime PM support).
7723 *
7724 * For more, read "Display Sequences for Package C8" on the hardware
7725 * documentation.
7726 */
7727 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7728 {
7729 struct drm_device *dev = dev_priv->dev;
7730 uint32_t val;
7731
7732 DRM_DEBUG_KMS("Enabling package C8+\n");
7733
7734 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7735 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7736 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7737 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7738 }
7739
7740 lpt_disable_clkout_dp(dev);
7741 hsw_disable_lcpll(dev_priv, true, true);
7742 }
7743
7744 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7745 {
7746 struct drm_device *dev = dev_priv->dev;
7747 uint32_t val;
7748
7749 DRM_DEBUG_KMS("Disabling package C8+\n");
7750
7751 hsw_restore_lcpll(dev_priv);
7752 lpt_init_pch_refclk(dev);
7753
7754 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7755 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7756 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7757 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7758 }
7759
7760 intel_prepare_ddi(dev);
7761 }
7762
7763 static void snb_modeset_global_resources(struct drm_device *dev)
7764 {
7765 modeset_update_crtc_power_domains(dev);
7766 }
7767
7768 static void haswell_modeset_global_resources(struct drm_device *dev)
7769 {
7770 modeset_update_crtc_power_domains(dev);
7771 }
7772
7773 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7774 int x, int y,
7775 struct drm_framebuffer *fb)
7776 {
7777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7778
7779 if (!intel_ddi_pll_select(intel_crtc))
7780 return -EINVAL;
7781
7782 intel_crtc->lowfreq_avail = false;
7783
7784 return 0;
7785 }
7786
7787 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7788 enum port port,
7789 struct intel_crtc_config *pipe_config)
7790 {
7791 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7792
7793 switch (pipe_config->ddi_pll_sel) {
7794 case PORT_CLK_SEL_WRPLL1:
7795 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7796 break;
7797 case PORT_CLK_SEL_WRPLL2:
7798 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7799 break;
7800 }
7801 }
7802
7803 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7804 struct intel_crtc_config *pipe_config)
7805 {
7806 struct drm_device *dev = crtc->base.dev;
7807 struct drm_i915_private *dev_priv = dev->dev_private;
7808 struct intel_shared_dpll *pll;
7809 enum port port;
7810 uint32_t tmp;
7811
7812 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7813
7814 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7815
7816 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7817
7818 if (pipe_config->shared_dpll >= 0) {
7819 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7820
7821 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7822 &pipe_config->dpll_hw_state));
7823 }
7824
7825 /*
7826 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7827 * DDI E. So just check whether this pipe is wired to DDI E and whether
7828 * the PCH transcoder is on.
7829 */
7830 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7831 pipe_config->has_pch_encoder = true;
7832
7833 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7834 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7835 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7836
7837 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7838 }
7839 }
7840
7841 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7842 struct intel_crtc_config *pipe_config)
7843 {
7844 struct drm_device *dev = crtc->base.dev;
7845 struct drm_i915_private *dev_priv = dev->dev_private;
7846 enum intel_display_power_domain pfit_domain;
7847 uint32_t tmp;
7848
7849 if (!intel_display_power_enabled(dev_priv,
7850 POWER_DOMAIN_PIPE(crtc->pipe)))
7851 return false;
7852
7853 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7854 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7855
7856 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7857 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7858 enum pipe trans_edp_pipe;
7859 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7860 default:
7861 WARN(1, "unknown pipe linked to edp transcoder\n");
7862 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7863 case TRANS_DDI_EDP_INPUT_A_ON:
7864 trans_edp_pipe = PIPE_A;
7865 break;
7866 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7867 trans_edp_pipe = PIPE_B;
7868 break;
7869 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7870 trans_edp_pipe = PIPE_C;
7871 break;
7872 }
7873
7874 if (trans_edp_pipe == crtc->pipe)
7875 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7876 }
7877
7878 if (!intel_display_power_enabled(dev_priv,
7879 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7880 return false;
7881
7882 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7883 if (!(tmp & PIPECONF_ENABLE))
7884 return false;
7885
7886 haswell_get_ddi_port_state(crtc, pipe_config);
7887
7888 intel_get_pipe_timings(crtc, pipe_config);
7889
7890 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7891 if (intel_display_power_enabled(dev_priv, pfit_domain))
7892 ironlake_get_pfit_config(crtc, pipe_config);
7893
7894 if (IS_HASWELL(dev))
7895 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7896 (I915_READ(IPS_CTL) & IPS_ENABLE);
7897
7898 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
7899 pipe_config->pixel_multiplier =
7900 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
7901 } else {
7902 pipe_config->pixel_multiplier = 1;
7903 }
7904
7905 return true;
7906 }
7907
7908 static struct {
7909 int clock;
7910 u32 config;
7911 } hdmi_audio_clock[] = {
7912 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7913 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7914 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7915 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7916 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7917 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7918 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7919 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7920 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7921 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7922 };
7923
7924 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7925 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7926 {
7927 int i;
7928
7929 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7930 if (mode->clock == hdmi_audio_clock[i].clock)
7931 break;
7932 }
7933
7934 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7935 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7936 i = 1;
7937 }
7938
7939 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7940 hdmi_audio_clock[i].clock,
7941 hdmi_audio_clock[i].config);
7942
7943 return hdmi_audio_clock[i].config;
7944 }
7945
7946 static bool intel_eld_uptodate(struct drm_connector *connector,
7947 int reg_eldv, uint32_t bits_eldv,
7948 int reg_elda, uint32_t bits_elda,
7949 int reg_edid)
7950 {
7951 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7952 uint8_t *eld = connector->eld;
7953 uint32_t i;
7954
7955 i = I915_READ(reg_eldv);
7956 i &= bits_eldv;
7957
7958 if (!eld[0])
7959 return !i;
7960
7961 if (!i)
7962 return false;
7963
7964 i = I915_READ(reg_elda);
7965 i &= ~bits_elda;
7966 I915_WRITE(reg_elda, i);
7967
7968 for (i = 0; i < eld[2]; i++)
7969 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7970 return false;
7971
7972 return true;
7973 }
7974
7975 static void g4x_write_eld(struct drm_connector *connector,
7976 struct drm_crtc *crtc,
7977 struct drm_display_mode *mode)
7978 {
7979 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7980 uint8_t *eld = connector->eld;
7981 uint32_t eldv;
7982 uint32_t len;
7983 uint32_t i;
7984
7985 i = I915_READ(G4X_AUD_VID_DID);
7986
7987 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7988 eldv = G4X_ELDV_DEVCL_DEVBLC;
7989 else
7990 eldv = G4X_ELDV_DEVCTG;
7991
7992 if (intel_eld_uptodate(connector,
7993 G4X_AUD_CNTL_ST, eldv,
7994 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7995 G4X_HDMIW_HDMIEDID))
7996 return;
7997
7998 i = I915_READ(G4X_AUD_CNTL_ST);
7999 i &= ~(eldv | G4X_ELD_ADDR);
8000 len = (i >> 9) & 0x1f; /* ELD buffer size */
8001 I915_WRITE(G4X_AUD_CNTL_ST, i);
8002
8003 if (!eld[0])
8004 return;
8005
8006 len = min_t(uint8_t, eld[2], len);
8007 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8008 for (i = 0; i < len; i++)
8009 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
8010
8011 i = I915_READ(G4X_AUD_CNTL_ST);
8012 i |= eldv;
8013 I915_WRITE(G4X_AUD_CNTL_ST, i);
8014 }
8015
8016 static void haswell_write_eld(struct drm_connector *connector,
8017 struct drm_crtc *crtc,
8018 struct drm_display_mode *mode)
8019 {
8020 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8021 uint8_t *eld = connector->eld;
8022 uint32_t eldv;
8023 uint32_t i;
8024 int len;
8025 int pipe = to_intel_crtc(crtc)->pipe;
8026 int tmp;
8027
8028 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
8029 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
8030 int aud_config = HSW_AUD_CFG(pipe);
8031 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
8032
8033 /* Audio output enable */
8034 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
8035 tmp = I915_READ(aud_cntrl_st2);
8036 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
8037 I915_WRITE(aud_cntrl_st2, tmp);
8038 POSTING_READ(aud_cntrl_st2);
8039
8040 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
8041
8042 /* Set ELD valid state */
8043 tmp = I915_READ(aud_cntrl_st2);
8044 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
8045 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
8046 I915_WRITE(aud_cntrl_st2, tmp);
8047 tmp = I915_READ(aud_cntrl_st2);
8048 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
8049
8050 /* Enable HDMI mode */
8051 tmp = I915_READ(aud_config);
8052 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
8053 /* clear N_programing_enable and N_value_index */
8054 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
8055 I915_WRITE(aud_config, tmp);
8056
8057 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8058
8059 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
8060
8061 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8062 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8063 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8064 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8065 } else {
8066 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8067 }
8068
8069 if (intel_eld_uptodate(connector,
8070 aud_cntrl_st2, eldv,
8071 aud_cntl_st, IBX_ELD_ADDRESS,
8072 hdmiw_hdmiedid))
8073 return;
8074
8075 i = I915_READ(aud_cntrl_st2);
8076 i &= ~eldv;
8077 I915_WRITE(aud_cntrl_st2, i);
8078
8079 if (!eld[0])
8080 return;
8081
8082 i = I915_READ(aud_cntl_st);
8083 i &= ~IBX_ELD_ADDRESS;
8084 I915_WRITE(aud_cntl_st, i);
8085 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
8086 DRM_DEBUG_DRIVER("port num:%d\n", i);
8087
8088 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8089 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8090 for (i = 0; i < len; i++)
8091 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8092
8093 i = I915_READ(aud_cntrl_st2);
8094 i |= eldv;
8095 I915_WRITE(aud_cntrl_st2, i);
8096
8097 }
8098
8099 static void ironlake_write_eld(struct drm_connector *connector,
8100 struct drm_crtc *crtc,
8101 struct drm_display_mode *mode)
8102 {
8103 struct drm_i915_private *dev_priv = connector->dev->dev_private;
8104 uint8_t *eld = connector->eld;
8105 uint32_t eldv;
8106 uint32_t i;
8107 int len;
8108 int hdmiw_hdmiedid;
8109 int aud_config;
8110 int aud_cntl_st;
8111 int aud_cntrl_st2;
8112 int pipe = to_intel_crtc(crtc)->pipe;
8113
8114 if (HAS_PCH_IBX(connector->dev)) {
8115 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
8116 aud_config = IBX_AUD_CFG(pipe);
8117 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8118 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8119 } else if (IS_VALLEYVIEW(connector->dev)) {
8120 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8121 aud_config = VLV_AUD_CFG(pipe);
8122 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8123 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8124 } else {
8125 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8126 aud_config = CPT_AUD_CFG(pipe);
8127 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8128 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8129 }
8130
8131 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8132
8133 if (IS_VALLEYVIEW(connector->dev)) {
8134 struct intel_encoder *intel_encoder;
8135 struct intel_digital_port *intel_dig_port;
8136
8137 intel_encoder = intel_attached_encoder(connector);
8138 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8139 i = intel_dig_port->port;
8140 } else {
8141 i = I915_READ(aud_cntl_st);
8142 i = (i >> 29) & DIP_PORT_SEL_MASK;
8143 /* DIP_Port_Select, 0x1 = PortB */
8144 }
8145
8146 if (!i) {
8147 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8148 /* operate blindly on all ports */
8149 eldv = IBX_ELD_VALIDB;
8150 eldv |= IBX_ELD_VALIDB << 4;
8151 eldv |= IBX_ELD_VALIDB << 8;
8152 } else {
8153 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8154 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8155 }
8156
8157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8158 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8159 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8160 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8161 } else {
8162 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8163 }
8164
8165 if (intel_eld_uptodate(connector,
8166 aud_cntrl_st2, eldv,
8167 aud_cntl_st, IBX_ELD_ADDRESS,
8168 hdmiw_hdmiedid))
8169 return;
8170
8171 i = I915_READ(aud_cntrl_st2);
8172 i &= ~eldv;
8173 I915_WRITE(aud_cntrl_st2, i);
8174
8175 if (!eld[0])
8176 return;
8177
8178 i = I915_READ(aud_cntl_st);
8179 i &= ~IBX_ELD_ADDRESS;
8180 I915_WRITE(aud_cntl_st, i);
8181
8182 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8183 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8184 for (i = 0; i < len; i++)
8185 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8186
8187 i = I915_READ(aud_cntrl_st2);
8188 i |= eldv;
8189 I915_WRITE(aud_cntrl_st2, i);
8190 }
8191
8192 void intel_write_eld(struct drm_encoder *encoder,
8193 struct drm_display_mode *mode)
8194 {
8195 struct drm_crtc *crtc = encoder->crtc;
8196 struct drm_connector *connector;
8197 struct drm_device *dev = encoder->dev;
8198 struct drm_i915_private *dev_priv = dev->dev_private;
8199
8200 connector = drm_select_eld(encoder, mode);
8201 if (!connector)
8202 return;
8203
8204 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8205 connector->base.id,
8206 connector->name,
8207 connector->encoder->base.id,
8208 connector->encoder->name);
8209
8210 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8211
8212 if (dev_priv->display.write_eld)
8213 dev_priv->display.write_eld(connector, crtc, mode);
8214 }
8215
8216 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8217 {
8218 struct drm_device *dev = crtc->dev;
8219 struct drm_i915_private *dev_priv = dev->dev_private;
8220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8221 uint32_t cntl = 0, size = 0;
8222
8223 if (base) {
8224 unsigned int width = intel_crtc->cursor_width;
8225 unsigned int height = intel_crtc->cursor_height;
8226 unsigned int stride = roundup_pow_of_two(width) * 4;
8227
8228 switch (stride) {
8229 default:
8230 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8231 width, stride);
8232 stride = 256;
8233 /* fallthrough */
8234 case 256:
8235 case 512:
8236 case 1024:
8237 case 2048:
8238 break;
8239 }
8240
8241 cntl |= CURSOR_ENABLE |
8242 CURSOR_GAMMA_ENABLE |
8243 CURSOR_FORMAT_ARGB |
8244 CURSOR_STRIDE(stride);
8245
8246 size = (height << 12) | width;
8247 }
8248
8249 if (intel_crtc->cursor_cntl != 0 &&
8250 (intel_crtc->cursor_base != base ||
8251 intel_crtc->cursor_size != size ||
8252 intel_crtc->cursor_cntl != cntl)) {
8253 /* On these chipsets we can only modify the base/size/stride
8254 * whilst the cursor is disabled.
8255 */
8256 I915_WRITE(_CURACNTR, 0);
8257 POSTING_READ(_CURACNTR);
8258 intel_crtc->cursor_cntl = 0;
8259 }
8260
8261 if (intel_crtc->cursor_base != base)
8262 I915_WRITE(_CURABASE, base);
8263
8264 if (intel_crtc->cursor_size != size) {
8265 I915_WRITE(CURSIZE, size);
8266 intel_crtc->cursor_size = size;
8267 }
8268
8269 if (intel_crtc->cursor_cntl != cntl) {
8270 I915_WRITE(_CURACNTR, cntl);
8271 POSTING_READ(_CURACNTR);
8272 intel_crtc->cursor_cntl = cntl;
8273 }
8274 }
8275
8276 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8277 {
8278 struct drm_device *dev = crtc->dev;
8279 struct drm_i915_private *dev_priv = dev->dev_private;
8280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8281 int pipe = intel_crtc->pipe;
8282 uint32_t cntl;
8283
8284 cntl = 0;
8285 if (base) {
8286 cntl = MCURSOR_GAMMA_ENABLE;
8287 switch (intel_crtc->cursor_width) {
8288 case 64:
8289 cntl |= CURSOR_MODE_64_ARGB_AX;
8290 break;
8291 case 128:
8292 cntl |= CURSOR_MODE_128_ARGB_AX;
8293 break;
8294 case 256:
8295 cntl |= CURSOR_MODE_256_ARGB_AX;
8296 break;
8297 default:
8298 WARN_ON(1);
8299 return;
8300 }
8301 cntl |= pipe << 28; /* Connect to correct pipe */
8302 }
8303 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8304 cntl |= CURSOR_PIPE_CSC_ENABLE;
8305
8306 if (intel_crtc->cursor_cntl != cntl) {
8307 I915_WRITE(CURCNTR(pipe), cntl);
8308 POSTING_READ(CURCNTR(pipe));
8309 intel_crtc->cursor_cntl = cntl;
8310 }
8311
8312 /* and commit changes on next vblank */
8313 I915_WRITE(CURBASE(pipe), base);
8314 POSTING_READ(CURBASE(pipe));
8315 }
8316
8317 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8318 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8319 bool on)
8320 {
8321 struct drm_device *dev = crtc->dev;
8322 struct drm_i915_private *dev_priv = dev->dev_private;
8323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8324 int pipe = intel_crtc->pipe;
8325 int x = crtc->cursor_x;
8326 int y = crtc->cursor_y;
8327 u32 base = 0, pos = 0;
8328
8329 if (on)
8330 base = intel_crtc->cursor_addr;
8331
8332 if (x >= intel_crtc->config.pipe_src_w)
8333 base = 0;
8334
8335 if (y >= intel_crtc->config.pipe_src_h)
8336 base = 0;
8337
8338 if (x < 0) {
8339 if (x + intel_crtc->cursor_width <= 0)
8340 base = 0;
8341
8342 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8343 x = -x;
8344 }
8345 pos |= x << CURSOR_X_SHIFT;
8346
8347 if (y < 0) {
8348 if (y + intel_crtc->cursor_height <= 0)
8349 base = 0;
8350
8351 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8352 y = -y;
8353 }
8354 pos |= y << CURSOR_Y_SHIFT;
8355
8356 if (base == 0 && intel_crtc->cursor_base == 0)
8357 return;
8358
8359 I915_WRITE(CURPOS(pipe), pos);
8360
8361 if (IS_845G(dev) || IS_I865G(dev))
8362 i845_update_cursor(crtc, base);
8363 else
8364 i9xx_update_cursor(crtc, base);
8365 intel_crtc->cursor_base = base;
8366 }
8367
8368 static bool cursor_size_ok(struct drm_device *dev,
8369 uint32_t width, uint32_t height)
8370 {
8371 if (width == 0 || height == 0)
8372 return false;
8373
8374 /*
8375 * 845g/865g are special in that they are only limited by
8376 * the width of their cursors, the height is arbitrary up to
8377 * the precision of the register. Everything else requires
8378 * square cursors, limited to a few power-of-two sizes.
8379 */
8380 if (IS_845G(dev) || IS_I865G(dev)) {
8381 if ((width & 63) != 0)
8382 return false;
8383
8384 if (width > (IS_845G(dev) ? 64 : 512))
8385 return false;
8386
8387 if (height > 1023)
8388 return false;
8389 } else {
8390 switch (width | height) {
8391 case 256:
8392 case 128:
8393 if (IS_GEN2(dev))
8394 return false;
8395 case 64:
8396 break;
8397 default:
8398 return false;
8399 }
8400 }
8401
8402 return true;
8403 }
8404
8405 /*
8406 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8407 *
8408 * Note that the object's reference will be consumed if the update fails. If
8409 * the update succeeds, the reference of the old object (if any) will be
8410 * consumed.
8411 */
8412 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8413 struct drm_i915_gem_object *obj,
8414 uint32_t width, uint32_t height)
8415 {
8416 struct drm_device *dev = crtc->dev;
8417 struct drm_i915_private *dev_priv = dev->dev_private;
8418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8419 enum pipe pipe = intel_crtc->pipe;
8420 unsigned old_width, stride;
8421 uint32_t addr;
8422 int ret;
8423
8424 /* if we want to turn off the cursor ignore width and height */
8425 if (!obj) {
8426 DRM_DEBUG_KMS("cursor off\n");
8427 addr = 0;
8428 mutex_lock(&dev->struct_mutex);
8429 goto finish;
8430 }
8431
8432 /* Check for which cursor types we support */
8433 if (!cursor_size_ok(dev, width, height)) {
8434 DRM_DEBUG("Cursor dimension not supported\n");
8435 return -EINVAL;
8436 }
8437
8438 stride = roundup_pow_of_two(width) * 4;
8439 if (obj->base.size < stride * height) {
8440 DRM_DEBUG_KMS("buffer is too small\n");
8441 ret = -ENOMEM;
8442 goto fail;
8443 }
8444
8445 /* we only need to pin inside GTT if cursor is non-phy */
8446 mutex_lock(&dev->struct_mutex);
8447 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8448 unsigned alignment;
8449
8450 if (obj->tiling_mode) {
8451 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8452 ret = -EINVAL;
8453 goto fail_locked;
8454 }
8455
8456 /*
8457 * Global gtt pte registers are special registers which actually
8458 * forward writes to a chunk of system memory. Which means that
8459 * there is no risk that the register values disappear as soon
8460 * as we call intel_runtime_pm_put(), so it is correct to wrap
8461 * only the pin/unpin/fence and not more.
8462 */
8463 intel_runtime_pm_get(dev_priv);
8464
8465 /* Note that the w/a also requires 2 PTE of padding following
8466 * the bo. We currently fill all unused PTE with the shadow
8467 * page and so we should always have valid PTE following the
8468 * cursor preventing the VT-d warning.
8469 */
8470 alignment = 0;
8471 if (need_vtd_wa(dev))
8472 alignment = 64*1024;
8473
8474 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8475 if (ret) {
8476 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8477 intel_runtime_pm_put(dev_priv);
8478 goto fail_locked;
8479 }
8480
8481 ret = i915_gem_object_put_fence(obj);
8482 if (ret) {
8483 DRM_DEBUG_KMS("failed to release fence for cursor");
8484 intel_runtime_pm_put(dev_priv);
8485 goto fail_unpin;
8486 }
8487
8488 addr = i915_gem_obj_ggtt_offset(obj);
8489
8490 intel_runtime_pm_put(dev_priv);
8491 } else {
8492 int align = IS_I830(dev) ? 16 * 1024 : 256;
8493 ret = i915_gem_object_attach_phys(obj, align);
8494 if (ret) {
8495 DRM_DEBUG_KMS("failed to attach phys object\n");
8496 goto fail_locked;
8497 }
8498 addr = obj->phys_handle->busaddr;
8499 }
8500
8501 finish:
8502 if (intel_crtc->cursor_bo) {
8503 if (!INTEL_INFO(dev)->cursor_needs_physical)
8504 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8505 }
8506
8507 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8508 INTEL_FRONTBUFFER_CURSOR(pipe));
8509 mutex_unlock(&dev->struct_mutex);
8510
8511 old_width = intel_crtc->cursor_width;
8512
8513 intel_crtc->cursor_addr = addr;
8514 intel_crtc->cursor_bo = obj;
8515 intel_crtc->cursor_width = width;
8516 intel_crtc->cursor_height = height;
8517
8518 if (intel_crtc->active) {
8519 if (old_width != width)
8520 intel_update_watermarks(crtc);
8521 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8522 }
8523
8524 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8525
8526 return 0;
8527 fail_unpin:
8528 i915_gem_object_unpin_from_display_plane(obj);
8529 fail_locked:
8530 mutex_unlock(&dev->struct_mutex);
8531 fail:
8532 drm_gem_object_unreference_unlocked(&obj->base);
8533 return ret;
8534 }
8535
8536 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8537 u16 *blue, uint32_t start, uint32_t size)
8538 {
8539 int end = (start + size > 256) ? 256 : start + size, i;
8540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8541
8542 for (i = start; i < end; i++) {
8543 intel_crtc->lut_r[i] = red[i] >> 8;
8544 intel_crtc->lut_g[i] = green[i] >> 8;
8545 intel_crtc->lut_b[i] = blue[i] >> 8;
8546 }
8547
8548 intel_crtc_load_lut(crtc);
8549 }
8550
8551 /* VESA 640x480x72Hz mode to set on the pipe */
8552 static struct drm_display_mode load_detect_mode = {
8553 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8554 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8555 };
8556
8557 struct drm_framebuffer *
8558 __intel_framebuffer_create(struct drm_device *dev,
8559 struct drm_mode_fb_cmd2 *mode_cmd,
8560 struct drm_i915_gem_object *obj)
8561 {
8562 struct intel_framebuffer *intel_fb;
8563 int ret;
8564
8565 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8566 if (!intel_fb) {
8567 drm_gem_object_unreference_unlocked(&obj->base);
8568 return ERR_PTR(-ENOMEM);
8569 }
8570
8571 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8572 if (ret)
8573 goto err;
8574
8575 return &intel_fb->base;
8576 err:
8577 drm_gem_object_unreference_unlocked(&obj->base);
8578 kfree(intel_fb);
8579
8580 return ERR_PTR(ret);
8581 }
8582
8583 static struct drm_framebuffer *
8584 intel_framebuffer_create(struct drm_device *dev,
8585 struct drm_mode_fb_cmd2 *mode_cmd,
8586 struct drm_i915_gem_object *obj)
8587 {
8588 struct drm_framebuffer *fb;
8589 int ret;
8590
8591 ret = i915_mutex_lock_interruptible(dev);
8592 if (ret)
8593 return ERR_PTR(ret);
8594 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8595 mutex_unlock(&dev->struct_mutex);
8596
8597 return fb;
8598 }
8599
8600 static u32
8601 intel_framebuffer_pitch_for_width(int width, int bpp)
8602 {
8603 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8604 return ALIGN(pitch, 64);
8605 }
8606
8607 static u32
8608 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8609 {
8610 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8611 return PAGE_ALIGN(pitch * mode->vdisplay);
8612 }
8613
8614 static struct drm_framebuffer *
8615 intel_framebuffer_create_for_mode(struct drm_device *dev,
8616 struct drm_display_mode *mode,
8617 int depth, int bpp)
8618 {
8619 struct drm_i915_gem_object *obj;
8620 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8621
8622 obj = i915_gem_alloc_object(dev,
8623 intel_framebuffer_size_for_mode(mode, bpp));
8624 if (obj == NULL)
8625 return ERR_PTR(-ENOMEM);
8626
8627 mode_cmd.width = mode->hdisplay;
8628 mode_cmd.height = mode->vdisplay;
8629 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8630 bpp);
8631 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8632
8633 return intel_framebuffer_create(dev, &mode_cmd, obj);
8634 }
8635
8636 static struct drm_framebuffer *
8637 mode_fits_in_fbdev(struct drm_device *dev,
8638 struct drm_display_mode *mode)
8639 {
8640 #ifdef CONFIG_DRM_I915_FBDEV
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 struct drm_i915_gem_object *obj;
8643 struct drm_framebuffer *fb;
8644
8645 if (!dev_priv->fbdev)
8646 return NULL;
8647
8648 if (!dev_priv->fbdev->fb)
8649 return NULL;
8650
8651 obj = dev_priv->fbdev->fb->obj;
8652 BUG_ON(!obj);
8653
8654 fb = &dev_priv->fbdev->fb->base;
8655 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8656 fb->bits_per_pixel))
8657 return NULL;
8658
8659 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8660 return NULL;
8661
8662 return fb;
8663 #else
8664 return NULL;
8665 #endif
8666 }
8667
8668 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8669 struct drm_display_mode *mode,
8670 struct intel_load_detect_pipe *old,
8671 struct drm_modeset_acquire_ctx *ctx)
8672 {
8673 struct intel_crtc *intel_crtc;
8674 struct intel_encoder *intel_encoder =
8675 intel_attached_encoder(connector);
8676 struct drm_crtc *possible_crtc;
8677 struct drm_encoder *encoder = &intel_encoder->base;
8678 struct drm_crtc *crtc = NULL;
8679 struct drm_device *dev = encoder->dev;
8680 struct drm_framebuffer *fb;
8681 struct drm_mode_config *config = &dev->mode_config;
8682 int ret, i = -1;
8683
8684 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8685 connector->base.id, connector->name,
8686 encoder->base.id, encoder->name);
8687
8688 retry:
8689 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8690 if (ret)
8691 goto fail_unlock;
8692
8693 /*
8694 * Algorithm gets a little messy:
8695 *
8696 * - if the connector already has an assigned crtc, use it (but make
8697 * sure it's on first)
8698 *
8699 * - try to find the first unused crtc that can drive this connector,
8700 * and use that if we find one
8701 */
8702
8703 /* See if we already have a CRTC for this connector */
8704 if (encoder->crtc) {
8705 crtc = encoder->crtc;
8706
8707 ret = drm_modeset_lock(&crtc->mutex, ctx);
8708 if (ret)
8709 goto fail_unlock;
8710
8711 old->dpms_mode = connector->dpms;
8712 old->load_detect_temp = false;
8713
8714 /* Make sure the crtc and connector are running */
8715 if (connector->dpms != DRM_MODE_DPMS_ON)
8716 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8717
8718 return true;
8719 }
8720
8721 /* Find an unused one (if possible) */
8722 for_each_crtc(dev, possible_crtc) {
8723 i++;
8724 if (!(encoder->possible_crtcs & (1 << i)))
8725 continue;
8726 if (possible_crtc->enabled)
8727 continue;
8728 /* This can occur when applying the pipe A quirk on resume. */
8729 if (to_intel_crtc(possible_crtc)->new_enabled)
8730 continue;
8731
8732 crtc = possible_crtc;
8733 break;
8734 }
8735
8736 /*
8737 * If we didn't find an unused CRTC, don't use any.
8738 */
8739 if (!crtc) {
8740 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8741 goto fail_unlock;
8742 }
8743
8744 ret = drm_modeset_lock(&crtc->mutex, ctx);
8745 if (ret)
8746 goto fail_unlock;
8747 intel_encoder->new_crtc = to_intel_crtc(crtc);
8748 to_intel_connector(connector)->new_encoder = intel_encoder;
8749
8750 intel_crtc = to_intel_crtc(crtc);
8751 intel_crtc->new_enabled = true;
8752 intel_crtc->new_config = &intel_crtc->config;
8753 old->dpms_mode = connector->dpms;
8754 old->load_detect_temp = true;
8755 old->release_fb = NULL;
8756
8757 if (!mode)
8758 mode = &load_detect_mode;
8759
8760 /* We need a framebuffer large enough to accommodate all accesses
8761 * that the plane may generate whilst we perform load detection.
8762 * We can not rely on the fbcon either being present (we get called
8763 * during its initialisation to detect all boot displays, or it may
8764 * not even exist) or that it is large enough to satisfy the
8765 * requested mode.
8766 */
8767 fb = mode_fits_in_fbdev(dev, mode);
8768 if (fb == NULL) {
8769 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8770 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8771 old->release_fb = fb;
8772 } else
8773 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8774 if (IS_ERR(fb)) {
8775 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8776 goto fail;
8777 }
8778
8779 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8780 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8781 if (old->release_fb)
8782 old->release_fb->funcs->destroy(old->release_fb);
8783 goto fail;
8784 }
8785
8786 /* let the connector get through one full cycle before testing */
8787 intel_wait_for_vblank(dev, intel_crtc->pipe);
8788 return true;
8789
8790 fail:
8791 intel_crtc->new_enabled = crtc->enabled;
8792 if (intel_crtc->new_enabled)
8793 intel_crtc->new_config = &intel_crtc->config;
8794 else
8795 intel_crtc->new_config = NULL;
8796 fail_unlock:
8797 if (ret == -EDEADLK) {
8798 drm_modeset_backoff(ctx);
8799 goto retry;
8800 }
8801
8802 return false;
8803 }
8804
8805 void intel_release_load_detect_pipe(struct drm_connector *connector,
8806 struct intel_load_detect_pipe *old)
8807 {
8808 struct intel_encoder *intel_encoder =
8809 intel_attached_encoder(connector);
8810 struct drm_encoder *encoder = &intel_encoder->base;
8811 struct drm_crtc *crtc = encoder->crtc;
8812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8813
8814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8815 connector->base.id, connector->name,
8816 encoder->base.id, encoder->name);
8817
8818 if (old->load_detect_temp) {
8819 to_intel_connector(connector)->new_encoder = NULL;
8820 intel_encoder->new_crtc = NULL;
8821 intel_crtc->new_enabled = false;
8822 intel_crtc->new_config = NULL;
8823 intel_set_mode(crtc, NULL, 0, 0, NULL);
8824
8825 if (old->release_fb) {
8826 drm_framebuffer_unregister_private(old->release_fb);
8827 drm_framebuffer_unreference(old->release_fb);
8828 }
8829
8830 return;
8831 }
8832
8833 /* Switch crtc and encoder back off if necessary */
8834 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8835 connector->funcs->dpms(connector, old->dpms_mode);
8836 }
8837
8838 static int i9xx_pll_refclk(struct drm_device *dev,
8839 const struct intel_crtc_config *pipe_config)
8840 {
8841 struct drm_i915_private *dev_priv = dev->dev_private;
8842 u32 dpll = pipe_config->dpll_hw_state.dpll;
8843
8844 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8845 return dev_priv->vbt.lvds_ssc_freq;
8846 else if (HAS_PCH_SPLIT(dev))
8847 return 120000;
8848 else if (!IS_GEN2(dev))
8849 return 96000;
8850 else
8851 return 48000;
8852 }
8853
8854 /* Returns the clock of the currently programmed mode of the given pipe. */
8855 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8856 struct intel_crtc_config *pipe_config)
8857 {
8858 struct drm_device *dev = crtc->base.dev;
8859 struct drm_i915_private *dev_priv = dev->dev_private;
8860 int pipe = pipe_config->cpu_transcoder;
8861 u32 dpll = pipe_config->dpll_hw_state.dpll;
8862 u32 fp;
8863 intel_clock_t clock;
8864 int refclk = i9xx_pll_refclk(dev, pipe_config);
8865
8866 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8867 fp = pipe_config->dpll_hw_state.fp0;
8868 else
8869 fp = pipe_config->dpll_hw_state.fp1;
8870
8871 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8872 if (IS_PINEVIEW(dev)) {
8873 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8874 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8875 } else {
8876 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8877 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8878 }
8879
8880 if (!IS_GEN2(dev)) {
8881 if (IS_PINEVIEW(dev))
8882 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8883 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8884 else
8885 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8886 DPLL_FPA01_P1_POST_DIV_SHIFT);
8887
8888 switch (dpll & DPLL_MODE_MASK) {
8889 case DPLLB_MODE_DAC_SERIAL:
8890 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8891 5 : 10;
8892 break;
8893 case DPLLB_MODE_LVDS:
8894 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8895 7 : 14;
8896 break;
8897 default:
8898 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8899 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8900 return;
8901 }
8902
8903 if (IS_PINEVIEW(dev))
8904 pineview_clock(refclk, &clock);
8905 else
8906 i9xx_clock(refclk, &clock);
8907 } else {
8908 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8909 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8910
8911 if (is_lvds) {
8912 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8913 DPLL_FPA01_P1_POST_DIV_SHIFT);
8914
8915 if (lvds & LVDS_CLKB_POWER_UP)
8916 clock.p2 = 7;
8917 else
8918 clock.p2 = 14;
8919 } else {
8920 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8921 clock.p1 = 2;
8922 else {
8923 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8924 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8925 }
8926 if (dpll & PLL_P2_DIVIDE_BY_4)
8927 clock.p2 = 4;
8928 else
8929 clock.p2 = 2;
8930 }
8931
8932 i9xx_clock(refclk, &clock);
8933 }
8934
8935 /*
8936 * This value includes pixel_multiplier. We will use
8937 * port_clock to compute adjusted_mode.crtc_clock in the
8938 * encoder's get_config() function.
8939 */
8940 pipe_config->port_clock = clock.dot;
8941 }
8942
8943 int intel_dotclock_calculate(int link_freq,
8944 const struct intel_link_m_n *m_n)
8945 {
8946 /*
8947 * The calculation for the data clock is:
8948 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8949 * But we want to avoid losing precison if possible, so:
8950 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8951 *
8952 * and the link clock is simpler:
8953 * link_clock = (m * link_clock) / n
8954 */
8955
8956 if (!m_n->link_n)
8957 return 0;
8958
8959 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8960 }
8961
8962 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8963 struct intel_crtc_config *pipe_config)
8964 {
8965 struct drm_device *dev = crtc->base.dev;
8966
8967 /* read out port_clock from the DPLL */
8968 i9xx_crtc_clock_get(crtc, pipe_config);
8969
8970 /*
8971 * This value does not include pixel_multiplier.
8972 * We will check that port_clock and adjusted_mode.crtc_clock
8973 * agree once we know their relationship in the encoder's
8974 * get_config() function.
8975 */
8976 pipe_config->adjusted_mode.crtc_clock =
8977 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8978 &pipe_config->fdi_m_n);
8979 }
8980
8981 /** Returns the currently programmed mode of the given pipe. */
8982 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8983 struct drm_crtc *crtc)
8984 {
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8987 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8988 struct drm_display_mode *mode;
8989 struct intel_crtc_config pipe_config;
8990 int htot = I915_READ(HTOTAL(cpu_transcoder));
8991 int hsync = I915_READ(HSYNC(cpu_transcoder));
8992 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8993 int vsync = I915_READ(VSYNC(cpu_transcoder));
8994 enum pipe pipe = intel_crtc->pipe;
8995
8996 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8997 if (!mode)
8998 return NULL;
8999
9000 /*
9001 * Construct a pipe_config sufficient for getting the clock info
9002 * back out of crtc_clock_get.
9003 *
9004 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9005 * to use a real value here instead.
9006 */
9007 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9008 pipe_config.pixel_multiplier = 1;
9009 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9010 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9011 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9012 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9013
9014 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9015 mode->hdisplay = (htot & 0xffff) + 1;
9016 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9017 mode->hsync_start = (hsync & 0xffff) + 1;
9018 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9019 mode->vdisplay = (vtot & 0xffff) + 1;
9020 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9021 mode->vsync_start = (vsync & 0xffff) + 1;
9022 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9023
9024 drm_mode_set_name(mode);
9025
9026 return mode;
9027 }
9028
9029 static void intel_increase_pllclock(struct drm_device *dev,
9030 enum pipe pipe)
9031 {
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 int dpll_reg = DPLL(pipe);
9034 int dpll;
9035
9036 if (!HAS_GMCH_DISPLAY(dev))
9037 return;
9038
9039 if (!dev_priv->lvds_downclock_avail)
9040 return;
9041
9042 dpll = I915_READ(dpll_reg);
9043 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
9044 DRM_DEBUG_DRIVER("upclocking LVDS\n");
9045
9046 assert_panel_unlocked(dev_priv, pipe);
9047
9048 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
9049 I915_WRITE(dpll_reg, dpll);
9050 intel_wait_for_vblank(dev, pipe);
9051
9052 dpll = I915_READ(dpll_reg);
9053 if (dpll & DISPLAY_RATE_SELECT_FPA1)
9054 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9055 }
9056 }
9057
9058 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9059 {
9060 struct drm_device *dev = crtc->dev;
9061 struct drm_i915_private *dev_priv = dev->dev_private;
9062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9063
9064 if (!HAS_GMCH_DISPLAY(dev))
9065 return;
9066
9067 if (!dev_priv->lvds_downclock_avail)
9068 return;
9069
9070 /*
9071 * Since this is called by a timer, we should never get here in
9072 * the manual case.
9073 */
9074 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9075 int pipe = intel_crtc->pipe;
9076 int dpll_reg = DPLL(pipe);
9077 int dpll;
9078
9079 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9080
9081 assert_panel_unlocked(dev_priv, pipe);
9082
9083 dpll = I915_READ(dpll_reg);
9084 dpll |= DISPLAY_RATE_SELECT_FPA1;
9085 I915_WRITE(dpll_reg, dpll);
9086 intel_wait_for_vblank(dev, pipe);
9087 dpll = I915_READ(dpll_reg);
9088 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9089 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9090 }
9091
9092 }
9093
9094 void intel_mark_busy(struct drm_device *dev)
9095 {
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097
9098 if (dev_priv->mm.busy)
9099 return;
9100
9101 intel_runtime_pm_get(dev_priv);
9102 i915_update_gfx_val(dev_priv);
9103 dev_priv->mm.busy = true;
9104 }
9105
9106 void intel_mark_idle(struct drm_device *dev)
9107 {
9108 struct drm_i915_private *dev_priv = dev->dev_private;
9109 struct drm_crtc *crtc;
9110
9111 if (!dev_priv->mm.busy)
9112 return;
9113
9114 dev_priv->mm.busy = false;
9115
9116 if (!i915.powersave)
9117 goto out;
9118
9119 for_each_crtc(dev, crtc) {
9120 if (!crtc->primary->fb)
9121 continue;
9122
9123 intel_decrease_pllclock(crtc);
9124 }
9125
9126 if (INTEL_INFO(dev)->gen >= 6)
9127 gen6_rps_idle(dev->dev_private);
9128
9129 out:
9130 intel_runtime_pm_put(dev_priv);
9131 }
9132
9133
9134 /**
9135 * intel_mark_fb_busy - mark given planes as busy
9136 * @dev: DRM device
9137 * @frontbuffer_bits: bits for the affected planes
9138 * @ring: optional ring for asynchronous commands
9139 *
9140 * This function gets called every time the screen contents change. It can be
9141 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9142 */
9143 static void intel_mark_fb_busy(struct drm_device *dev,
9144 unsigned frontbuffer_bits,
9145 struct intel_engine_cs *ring)
9146 {
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9148 enum pipe pipe;
9149
9150 if (!i915.powersave)
9151 return;
9152
9153 for_each_pipe(dev_priv, pipe) {
9154 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9155 continue;
9156
9157 intel_increase_pllclock(dev, pipe);
9158 if (ring && intel_fbc_enabled(dev))
9159 ring->fbc_dirty = true;
9160 }
9161 }
9162
9163 /**
9164 * intel_fb_obj_invalidate - invalidate frontbuffer object
9165 * @obj: GEM object to invalidate
9166 * @ring: set for asynchronous rendering
9167 *
9168 * This function gets called every time rendering on the given object starts and
9169 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9170 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9171 * until the rendering completes or a flip on this frontbuffer plane is
9172 * scheduled.
9173 */
9174 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9175 struct intel_engine_cs *ring)
9176 {
9177 struct drm_device *dev = obj->base.dev;
9178 struct drm_i915_private *dev_priv = dev->dev_private;
9179
9180 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9181
9182 if (!obj->frontbuffer_bits)
9183 return;
9184
9185 if (ring) {
9186 mutex_lock(&dev_priv->fb_tracking.lock);
9187 dev_priv->fb_tracking.busy_bits
9188 |= obj->frontbuffer_bits;
9189 dev_priv->fb_tracking.flip_bits
9190 &= ~obj->frontbuffer_bits;
9191 mutex_unlock(&dev_priv->fb_tracking.lock);
9192 }
9193
9194 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9195
9196 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9197 }
9198
9199 /**
9200 * intel_frontbuffer_flush - flush frontbuffer
9201 * @dev: DRM device
9202 * @frontbuffer_bits: frontbuffer plane tracking bits
9203 *
9204 * This function gets called every time rendering on the given planes has
9205 * completed and frontbuffer caching can be started again. Flushes will get
9206 * delayed if they're blocked by some oustanding asynchronous rendering.
9207 *
9208 * Can be called without any locks held.
9209 */
9210 void intel_frontbuffer_flush(struct drm_device *dev,
9211 unsigned frontbuffer_bits)
9212 {
9213 struct drm_i915_private *dev_priv = dev->dev_private;
9214
9215 /* Delay flushing when rings are still busy.*/
9216 mutex_lock(&dev_priv->fb_tracking.lock);
9217 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9218 mutex_unlock(&dev_priv->fb_tracking.lock);
9219
9220 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9221
9222 intel_edp_psr_flush(dev, frontbuffer_bits);
9223
9224 /*
9225 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9226 * needs to be reworked into a proper frontbuffer tracking scheme like
9227 * psr employs.
9228 */
9229 if (IS_BROADWELL(dev))
9230 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9231 }
9232
9233 /**
9234 * intel_fb_obj_flush - flush frontbuffer object
9235 * @obj: GEM object to flush
9236 * @retire: set when retiring asynchronous rendering
9237 *
9238 * This function gets called every time rendering on the given object has
9239 * completed and frontbuffer caching can be started again. If @retire is true
9240 * then any delayed flushes will be unblocked.
9241 */
9242 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9243 bool retire)
9244 {
9245 struct drm_device *dev = obj->base.dev;
9246 struct drm_i915_private *dev_priv = dev->dev_private;
9247 unsigned frontbuffer_bits;
9248
9249 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9250
9251 if (!obj->frontbuffer_bits)
9252 return;
9253
9254 frontbuffer_bits = obj->frontbuffer_bits;
9255
9256 if (retire) {
9257 mutex_lock(&dev_priv->fb_tracking.lock);
9258 /* Filter out new bits since rendering started. */
9259 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9260
9261 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9262 mutex_unlock(&dev_priv->fb_tracking.lock);
9263 }
9264
9265 intel_frontbuffer_flush(dev, frontbuffer_bits);
9266 }
9267
9268 /**
9269 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9270 * @dev: DRM device
9271 * @frontbuffer_bits: frontbuffer plane tracking bits
9272 *
9273 * This function gets called after scheduling a flip on @obj. The actual
9274 * frontbuffer flushing will be delayed until completion is signalled with
9275 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9276 * flush will be cancelled.
9277 *
9278 * Can be called without any locks held.
9279 */
9280 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9281 unsigned frontbuffer_bits)
9282 {
9283 struct drm_i915_private *dev_priv = dev->dev_private;
9284
9285 mutex_lock(&dev_priv->fb_tracking.lock);
9286 dev_priv->fb_tracking.flip_bits
9287 |= frontbuffer_bits;
9288 mutex_unlock(&dev_priv->fb_tracking.lock);
9289 }
9290
9291 /**
9292 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9293 * @dev: DRM device
9294 * @frontbuffer_bits: frontbuffer plane tracking bits
9295 *
9296 * This function gets called after the flip has been latched and will complete
9297 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9298 *
9299 * Can be called without any locks held.
9300 */
9301 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9302 unsigned frontbuffer_bits)
9303 {
9304 struct drm_i915_private *dev_priv = dev->dev_private;
9305
9306 mutex_lock(&dev_priv->fb_tracking.lock);
9307 /* Mask any cancelled flips. */
9308 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9309 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9310 mutex_unlock(&dev_priv->fb_tracking.lock);
9311
9312 intel_frontbuffer_flush(dev, frontbuffer_bits);
9313 }
9314
9315 static void intel_crtc_destroy(struct drm_crtc *crtc)
9316 {
9317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9318 struct drm_device *dev = crtc->dev;
9319 struct intel_unpin_work *work;
9320 unsigned long flags;
9321
9322 spin_lock_irqsave(&dev->event_lock, flags);
9323 work = intel_crtc->unpin_work;
9324 intel_crtc->unpin_work = NULL;
9325 spin_unlock_irqrestore(&dev->event_lock, flags);
9326
9327 if (work) {
9328 cancel_work_sync(&work->work);
9329 kfree(work);
9330 }
9331
9332 drm_crtc_cleanup(crtc);
9333
9334 kfree(intel_crtc);
9335 }
9336
9337 static void intel_unpin_work_fn(struct work_struct *__work)
9338 {
9339 struct intel_unpin_work *work =
9340 container_of(__work, struct intel_unpin_work, work);
9341 struct drm_device *dev = work->crtc->dev;
9342 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9343
9344 mutex_lock(&dev->struct_mutex);
9345 intel_unpin_fb_obj(work->old_fb_obj);
9346 drm_gem_object_unreference(&work->pending_flip_obj->base);
9347 drm_gem_object_unreference(&work->old_fb_obj->base);
9348
9349 intel_update_fbc(dev);
9350 mutex_unlock(&dev->struct_mutex);
9351
9352 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9353
9354 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9355 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9356
9357 kfree(work);
9358 }
9359
9360 static void do_intel_finish_page_flip(struct drm_device *dev,
9361 struct drm_crtc *crtc)
9362 {
9363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9364 struct intel_unpin_work *work;
9365 unsigned long flags;
9366
9367 /* Ignore early vblank irqs */
9368 if (intel_crtc == NULL)
9369 return;
9370
9371 spin_lock_irqsave(&dev->event_lock, flags);
9372 work = intel_crtc->unpin_work;
9373
9374 /* Ensure we don't miss a work->pending update ... */
9375 smp_rmb();
9376
9377 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9378 spin_unlock_irqrestore(&dev->event_lock, flags);
9379 return;
9380 }
9381
9382 page_flip_completed(intel_crtc);
9383
9384 spin_unlock_irqrestore(&dev->event_lock, flags);
9385 }
9386
9387 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9388 {
9389 struct drm_i915_private *dev_priv = dev->dev_private;
9390 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9391
9392 do_intel_finish_page_flip(dev, crtc);
9393 }
9394
9395 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9396 {
9397 struct drm_i915_private *dev_priv = dev->dev_private;
9398 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9399
9400 do_intel_finish_page_flip(dev, crtc);
9401 }
9402
9403 /* Is 'a' after or equal to 'b'? */
9404 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9405 {
9406 return !((a - b) & 0x80000000);
9407 }
9408
9409 static bool page_flip_finished(struct intel_crtc *crtc)
9410 {
9411 struct drm_device *dev = crtc->base.dev;
9412 struct drm_i915_private *dev_priv = dev->dev_private;
9413
9414 /*
9415 * The relevant registers doen't exist on pre-ctg.
9416 * As the flip done interrupt doesn't trigger for mmio
9417 * flips on gmch platforms, a flip count check isn't
9418 * really needed there. But since ctg has the registers,
9419 * include it in the check anyway.
9420 */
9421 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9422 return true;
9423
9424 /*
9425 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9426 * used the same base address. In that case the mmio flip might
9427 * have completed, but the CS hasn't even executed the flip yet.
9428 *
9429 * A flip count check isn't enough as the CS might have updated
9430 * the base address just after start of vblank, but before we
9431 * managed to process the interrupt. This means we'd complete the
9432 * CS flip too soon.
9433 *
9434 * Combining both checks should get us a good enough result. It may
9435 * still happen that the CS flip has been executed, but has not
9436 * yet actually completed. But in case the base address is the same
9437 * anyway, we don't really care.
9438 */
9439 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9440 crtc->unpin_work->gtt_offset &&
9441 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9442 crtc->unpin_work->flip_count);
9443 }
9444
9445 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9446 {
9447 struct drm_i915_private *dev_priv = dev->dev_private;
9448 struct intel_crtc *intel_crtc =
9449 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9450 unsigned long flags;
9451
9452 /* NB: An MMIO update of the plane base pointer will also
9453 * generate a page-flip completion irq, i.e. every modeset
9454 * is also accompanied by a spurious intel_prepare_page_flip().
9455 */
9456 spin_lock_irqsave(&dev->event_lock, flags);
9457 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9458 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9459 spin_unlock_irqrestore(&dev->event_lock, flags);
9460 }
9461
9462 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9463 {
9464 /* Ensure that the work item is consistent when activating it ... */
9465 smp_wmb();
9466 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9467 /* and that it is marked active as soon as the irq could fire. */
9468 smp_wmb();
9469 }
9470
9471 static int intel_gen2_queue_flip(struct drm_device *dev,
9472 struct drm_crtc *crtc,
9473 struct drm_framebuffer *fb,
9474 struct drm_i915_gem_object *obj,
9475 struct intel_engine_cs *ring,
9476 uint32_t flags)
9477 {
9478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9479 u32 flip_mask;
9480 int ret;
9481
9482 ret = intel_ring_begin(ring, 6);
9483 if (ret)
9484 return ret;
9485
9486 /* Can't queue multiple flips, so wait for the previous
9487 * one to finish before executing the next.
9488 */
9489 if (intel_crtc->plane)
9490 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9491 else
9492 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9493 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9494 intel_ring_emit(ring, MI_NOOP);
9495 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9496 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9497 intel_ring_emit(ring, fb->pitches[0]);
9498 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9499 intel_ring_emit(ring, 0); /* aux display base address, unused */
9500
9501 intel_mark_page_flip_active(intel_crtc);
9502 __intel_ring_advance(ring);
9503 return 0;
9504 }
9505
9506 static int intel_gen3_queue_flip(struct drm_device *dev,
9507 struct drm_crtc *crtc,
9508 struct drm_framebuffer *fb,
9509 struct drm_i915_gem_object *obj,
9510 struct intel_engine_cs *ring,
9511 uint32_t flags)
9512 {
9513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9514 u32 flip_mask;
9515 int ret;
9516
9517 ret = intel_ring_begin(ring, 6);
9518 if (ret)
9519 return ret;
9520
9521 if (intel_crtc->plane)
9522 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9523 else
9524 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9525 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9526 intel_ring_emit(ring, MI_NOOP);
9527 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9528 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9529 intel_ring_emit(ring, fb->pitches[0]);
9530 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9531 intel_ring_emit(ring, MI_NOOP);
9532
9533 intel_mark_page_flip_active(intel_crtc);
9534 __intel_ring_advance(ring);
9535 return 0;
9536 }
9537
9538 static int intel_gen4_queue_flip(struct drm_device *dev,
9539 struct drm_crtc *crtc,
9540 struct drm_framebuffer *fb,
9541 struct drm_i915_gem_object *obj,
9542 struct intel_engine_cs *ring,
9543 uint32_t flags)
9544 {
9545 struct drm_i915_private *dev_priv = dev->dev_private;
9546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9547 uint32_t pf, pipesrc;
9548 int ret;
9549
9550 ret = intel_ring_begin(ring, 4);
9551 if (ret)
9552 return ret;
9553
9554 /* i965+ uses the linear or tiled offsets from the
9555 * Display Registers (which do not change across a page-flip)
9556 * so we need only reprogram the base address.
9557 */
9558 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9559 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9560 intel_ring_emit(ring, fb->pitches[0]);
9561 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9562 obj->tiling_mode);
9563
9564 /* XXX Enabling the panel-fitter across page-flip is so far
9565 * untested on non-native modes, so ignore it for now.
9566 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9567 */
9568 pf = 0;
9569 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9570 intel_ring_emit(ring, pf | pipesrc);
9571
9572 intel_mark_page_flip_active(intel_crtc);
9573 __intel_ring_advance(ring);
9574 return 0;
9575 }
9576
9577 static int intel_gen6_queue_flip(struct drm_device *dev,
9578 struct drm_crtc *crtc,
9579 struct drm_framebuffer *fb,
9580 struct drm_i915_gem_object *obj,
9581 struct intel_engine_cs *ring,
9582 uint32_t flags)
9583 {
9584 struct drm_i915_private *dev_priv = dev->dev_private;
9585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9586 uint32_t pf, pipesrc;
9587 int ret;
9588
9589 ret = intel_ring_begin(ring, 4);
9590 if (ret)
9591 return ret;
9592
9593 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9594 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9595 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9596 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9597
9598 /* Contrary to the suggestions in the documentation,
9599 * "Enable Panel Fitter" does not seem to be required when page
9600 * flipping with a non-native mode, and worse causes a normal
9601 * modeset to fail.
9602 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9603 */
9604 pf = 0;
9605 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9606 intel_ring_emit(ring, pf | pipesrc);
9607
9608 intel_mark_page_flip_active(intel_crtc);
9609 __intel_ring_advance(ring);
9610 return 0;
9611 }
9612
9613 static int intel_gen7_queue_flip(struct drm_device *dev,
9614 struct drm_crtc *crtc,
9615 struct drm_framebuffer *fb,
9616 struct drm_i915_gem_object *obj,
9617 struct intel_engine_cs *ring,
9618 uint32_t flags)
9619 {
9620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9621 uint32_t plane_bit = 0;
9622 int len, ret;
9623
9624 switch (intel_crtc->plane) {
9625 case PLANE_A:
9626 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9627 break;
9628 case PLANE_B:
9629 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9630 break;
9631 case PLANE_C:
9632 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9633 break;
9634 default:
9635 WARN_ONCE(1, "unknown plane in flip command\n");
9636 return -ENODEV;
9637 }
9638
9639 len = 4;
9640 if (ring->id == RCS) {
9641 len += 6;
9642 /*
9643 * On Gen 8, SRM is now taking an extra dword to accommodate
9644 * 48bits addresses, and we need a NOOP for the batch size to
9645 * stay even.
9646 */
9647 if (IS_GEN8(dev))
9648 len += 2;
9649 }
9650
9651 /*
9652 * BSpec MI_DISPLAY_FLIP for IVB:
9653 * "The full packet must be contained within the same cache line."
9654 *
9655 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9656 * cacheline, if we ever start emitting more commands before
9657 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9658 * then do the cacheline alignment, and finally emit the
9659 * MI_DISPLAY_FLIP.
9660 */
9661 ret = intel_ring_cacheline_align(ring);
9662 if (ret)
9663 return ret;
9664
9665 ret = intel_ring_begin(ring, len);
9666 if (ret)
9667 return ret;
9668
9669 /* Unmask the flip-done completion message. Note that the bspec says that
9670 * we should do this for both the BCS and RCS, and that we must not unmask
9671 * more than one flip event at any time (or ensure that one flip message
9672 * can be sent by waiting for flip-done prior to queueing new flips).
9673 * Experimentation says that BCS works despite DERRMR masking all
9674 * flip-done completion events and that unmasking all planes at once
9675 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9676 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9677 */
9678 if (ring->id == RCS) {
9679 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9680 intel_ring_emit(ring, DERRMR);
9681 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9682 DERRMR_PIPEB_PRI_FLIP_DONE |
9683 DERRMR_PIPEC_PRI_FLIP_DONE));
9684 if (IS_GEN8(dev))
9685 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9686 MI_SRM_LRM_GLOBAL_GTT);
9687 else
9688 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9689 MI_SRM_LRM_GLOBAL_GTT);
9690 intel_ring_emit(ring, DERRMR);
9691 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9692 if (IS_GEN8(dev)) {
9693 intel_ring_emit(ring, 0);
9694 intel_ring_emit(ring, MI_NOOP);
9695 }
9696 }
9697
9698 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9699 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9700 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9701 intel_ring_emit(ring, (MI_NOOP));
9702
9703 intel_mark_page_flip_active(intel_crtc);
9704 __intel_ring_advance(ring);
9705 return 0;
9706 }
9707
9708 static bool use_mmio_flip(struct intel_engine_cs *ring,
9709 struct drm_i915_gem_object *obj)
9710 {
9711 /*
9712 * This is not being used for older platforms, because
9713 * non-availability of flip done interrupt forces us to use
9714 * CS flips. Older platforms derive flip done using some clever
9715 * tricks involving the flip_pending status bits and vblank irqs.
9716 * So using MMIO flips there would disrupt this mechanism.
9717 */
9718
9719 if (ring == NULL)
9720 return true;
9721
9722 if (INTEL_INFO(ring->dev)->gen < 5)
9723 return false;
9724
9725 if (i915.use_mmio_flip < 0)
9726 return false;
9727 else if (i915.use_mmio_flip > 0)
9728 return true;
9729 else if (i915.enable_execlists)
9730 return true;
9731 else
9732 return ring != obj->ring;
9733 }
9734
9735 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9736 {
9737 struct drm_device *dev = intel_crtc->base.dev;
9738 struct drm_i915_private *dev_priv = dev->dev_private;
9739 struct intel_framebuffer *intel_fb =
9740 to_intel_framebuffer(intel_crtc->base.primary->fb);
9741 struct drm_i915_gem_object *obj = intel_fb->obj;
9742 u32 dspcntr;
9743 u32 reg;
9744
9745 intel_mark_page_flip_active(intel_crtc);
9746
9747 reg = DSPCNTR(intel_crtc->plane);
9748 dspcntr = I915_READ(reg);
9749
9750 if (INTEL_INFO(dev)->gen >= 4) {
9751 if (obj->tiling_mode != I915_TILING_NONE)
9752 dspcntr |= DISPPLANE_TILED;
9753 else
9754 dspcntr &= ~DISPPLANE_TILED;
9755 }
9756 I915_WRITE(reg, dspcntr);
9757
9758 I915_WRITE(DSPSURF(intel_crtc->plane),
9759 intel_crtc->unpin_work->gtt_offset);
9760 POSTING_READ(DSPSURF(intel_crtc->plane));
9761 }
9762
9763 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9764 {
9765 struct intel_engine_cs *ring;
9766 int ret;
9767
9768 lockdep_assert_held(&obj->base.dev->struct_mutex);
9769
9770 if (!obj->last_write_seqno)
9771 return 0;
9772
9773 ring = obj->ring;
9774
9775 if (i915_seqno_passed(ring->get_seqno(ring, true),
9776 obj->last_write_seqno))
9777 return 0;
9778
9779 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9780 if (ret)
9781 return ret;
9782
9783 if (WARN_ON(!ring->irq_get(ring)))
9784 return 0;
9785
9786 return 1;
9787 }
9788
9789 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9790 {
9791 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9792 struct intel_crtc *intel_crtc;
9793 unsigned long irq_flags;
9794 u32 seqno;
9795
9796 seqno = ring->get_seqno(ring, false);
9797
9798 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9799 for_each_intel_crtc(ring->dev, intel_crtc) {
9800 struct intel_mmio_flip *mmio_flip;
9801
9802 mmio_flip = &intel_crtc->mmio_flip;
9803 if (mmio_flip->seqno == 0)
9804 continue;
9805
9806 if (ring->id != mmio_flip->ring_id)
9807 continue;
9808
9809 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9810 intel_do_mmio_flip(intel_crtc);
9811 mmio_flip->seqno = 0;
9812 ring->irq_put(ring);
9813 }
9814 }
9815 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9816 }
9817
9818 static int intel_queue_mmio_flip(struct drm_device *dev,
9819 struct drm_crtc *crtc,
9820 struct drm_framebuffer *fb,
9821 struct drm_i915_gem_object *obj,
9822 struct intel_engine_cs *ring,
9823 uint32_t flags)
9824 {
9825 struct drm_i915_private *dev_priv = dev->dev_private;
9826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9827 unsigned long irq_flags;
9828 int ret;
9829
9830 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9831 return -EBUSY;
9832
9833 ret = intel_postpone_flip(obj);
9834 if (ret < 0)
9835 return ret;
9836 if (ret == 0) {
9837 intel_do_mmio_flip(intel_crtc);
9838 return 0;
9839 }
9840
9841 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9842 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9843 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9844 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9845
9846 /*
9847 * Double check to catch cases where irq fired before
9848 * mmio flip data was ready
9849 */
9850 intel_notify_mmio_flip(obj->ring);
9851 return 0;
9852 }
9853
9854 static int intel_default_queue_flip(struct drm_device *dev,
9855 struct drm_crtc *crtc,
9856 struct drm_framebuffer *fb,
9857 struct drm_i915_gem_object *obj,
9858 struct intel_engine_cs *ring,
9859 uint32_t flags)
9860 {
9861 return -ENODEV;
9862 }
9863
9864 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9865 struct drm_crtc *crtc)
9866 {
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9869 struct intel_unpin_work *work = intel_crtc->unpin_work;
9870 u32 addr;
9871
9872 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9873 return true;
9874
9875 if (!work->enable_stall_check)
9876 return false;
9877
9878 if (work->flip_ready_vblank == 0) {
9879 if (work->flip_queued_ring &&
9880 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9881 work->flip_queued_seqno))
9882 return false;
9883
9884 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9885 }
9886
9887 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9888 return false;
9889
9890 /* Potential stall - if we see that the flip has happened,
9891 * assume a missed interrupt. */
9892 if (INTEL_INFO(dev)->gen >= 4)
9893 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9894 else
9895 addr = I915_READ(DSPADDR(intel_crtc->plane));
9896
9897 /* There is a potential issue here with a false positive after a flip
9898 * to the same address. We could address this by checking for a
9899 * non-incrementing frame counter.
9900 */
9901 return addr == work->gtt_offset;
9902 }
9903
9904 void intel_check_page_flip(struct drm_device *dev, int pipe)
9905 {
9906 struct drm_i915_private *dev_priv = dev->dev_private;
9907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9909 unsigned long flags;
9910
9911 if (crtc == NULL)
9912 return;
9913
9914 spin_lock_irqsave(&dev->event_lock, flags);
9915 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9916 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9917 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9918 page_flip_completed(intel_crtc);
9919 }
9920 spin_unlock_irqrestore(&dev->event_lock, flags);
9921 }
9922
9923 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9924 struct drm_framebuffer *fb,
9925 struct drm_pending_vblank_event *event,
9926 uint32_t page_flip_flags)
9927 {
9928 struct drm_device *dev = crtc->dev;
9929 struct drm_i915_private *dev_priv = dev->dev_private;
9930 struct drm_framebuffer *old_fb = crtc->primary->fb;
9931 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933 enum pipe pipe = intel_crtc->pipe;
9934 struct intel_unpin_work *work;
9935 struct intel_engine_cs *ring;
9936 unsigned long flags;
9937 int ret;
9938
9939 /*
9940 * drm_mode_page_flip_ioctl() should already catch this, but double
9941 * check to be safe. In the future we may enable pageflipping from
9942 * a disabled primary plane.
9943 */
9944 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9945 return -EBUSY;
9946
9947 /* Can't change pixel format via MI display flips. */
9948 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9949 return -EINVAL;
9950
9951 /*
9952 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9953 * Note that pitch changes could also affect these register.
9954 */
9955 if (INTEL_INFO(dev)->gen > 3 &&
9956 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9957 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9958 return -EINVAL;
9959
9960 if (i915_terminally_wedged(&dev_priv->gpu_error))
9961 goto out_hang;
9962
9963 work = kzalloc(sizeof(*work), GFP_KERNEL);
9964 if (work == NULL)
9965 return -ENOMEM;
9966
9967 work->event = event;
9968 work->crtc = crtc;
9969 work->old_fb_obj = intel_fb_obj(old_fb);
9970 INIT_WORK(&work->work, intel_unpin_work_fn);
9971
9972 ret = drm_crtc_vblank_get(crtc);
9973 if (ret)
9974 goto free_work;
9975
9976 /* We borrow the event spin lock for protecting unpin_work */
9977 spin_lock_irqsave(&dev->event_lock, flags);
9978 if (intel_crtc->unpin_work) {
9979 /* Before declaring the flip queue wedged, check if
9980 * the hardware completed the operation behind our backs.
9981 */
9982 if (__intel_pageflip_stall_check(dev, crtc)) {
9983 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9984 page_flip_completed(intel_crtc);
9985 } else {
9986 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9987 spin_unlock_irqrestore(&dev->event_lock, flags);
9988
9989 drm_crtc_vblank_put(crtc);
9990 kfree(work);
9991 return -EBUSY;
9992 }
9993 }
9994 intel_crtc->unpin_work = work;
9995 spin_unlock_irqrestore(&dev->event_lock, flags);
9996
9997 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9998 flush_workqueue(dev_priv->wq);
9999
10000 ret = i915_mutex_lock_interruptible(dev);
10001 if (ret)
10002 goto cleanup;
10003
10004 /* Reference the objects for the scheduled work. */
10005 drm_gem_object_reference(&work->old_fb_obj->base);
10006 drm_gem_object_reference(&obj->base);
10007
10008 crtc->primary->fb = fb;
10009
10010 work->pending_flip_obj = obj;
10011
10012 atomic_inc(&intel_crtc->unpin_work_count);
10013 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10014
10015 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10016 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10017
10018 if (IS_VALLEYVIEW(dev)) {
10019 ring = &dev_priv->ring[BCS];
10020 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
10021 /* vlv: DISPLAY_FLIP fails to change tiling */
10022 ring = NULL;
10023 } else if (IS_IVYBRIDGE(dev)) {
10024 ring = &dev_priv->ring[BCS];
10025 } else if (INTEL_INFO(dev)->gen >= 7) {
10026 ring = obj->ring;
10027 if (ring == NULL || ring->id != RCS)
10028 ring = &dev_priv->ring[BCS];
10029 } else {
10030 ring = &dev_priv->ring[RCS];
10031 }
10032
10033 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
10034 if (ret)
10035 goto cleanup_pending;
10036
10037 work->gtt_offset =
10038 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10039
10040 if (use_mmio_flip(ring, obj)) {
10041 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10042 page_flip_flags);
10043 if (ret)
10044 goto cleanup_unpin;
10045
10046 work->flip_queued_seqno = obj->last_write_seqno;
10047 work->flip_queued_ring = obj->ring;
10048 } else {
10049 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10050 page_flip_flags);
10051 if (ret)
10052 goto cleanup_unpin;
10053
10054 work->flip_queued_seqno = intel_ring_get_seqno(ring);
10055 work->flip_queued_ring = ring;
10056 }
10057
10058 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
10059 work->enable_stall_check = true;
10060
10061 i915_gem_track_fb(work->old_fb_obj, obj,
10062 INTEL_FRONTBUFFER_PRIMARY(pipe));
10063
10064 intel_disable_fbc(dev);
10065 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10066 mutex_unlock(&dev->struct_mutex);
10067
10068 trace_i915_flip_request(intel_crtc->plane, obj);
10069
10070 return 0;
10071
10072 cleanup_unpin:
10073 intel_unpin_fb_obj(obj);
10074 cleanup_pending:
10075 atomic_dec(&intel_crtc->unpin_work_count);
10076 crtc->primary->fb = old_fb;
10077 drm_gem_object_unreference(&work->old_fb_obj->base);
10078 drm_gem_object_unreference(&obj->base);
10079 mutex_unlock(&dev->struct_mutex);
10080
10081 cleanup:
10082 spin_lock_irqsave(&dev->event_lock, flags);
10083 intel_crtc->unpin_work = NULL;
10084 spin_unlock_irqrestore(&dev->event_lock, flags);
10085
10086 drm_crtc_vblank_put(crtc);
10087 free_work:
10088 kfree(work);
10089
10090 if (ret == -EIO) {
10091 out_hang:
10092 intel_crtc_wait_for_pending_flips(crtc);
10093 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
10094 if (ret == 0 && event) {
10095 spin_lock_irqsave(&dev->event_lock, flags);
10096 drm_send_vblank_event(dev, pipe, event);
10097 spin_unlock_irqrestore(&dev->event_lock, flags);
10098 }
10099 }
10100 return ret;
10101 }
10102
10103 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10104 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10105 .load_lut = intel_crtc_load_lut,
10106 };
10107
10108 /**
10109 * intel_modeset_update_staged_output_state
10110 *
10111 * Updates the staged output configuration state, e.g. after we've read out the
10112 * current hw state.
10113 */
10114 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10115 {
10116 struct intel_crtc *crtc;
10117 struct intel_encoder *encoder;
10118 struct intel_connector *connector;
10119
10120 list_for_each_entry(connector, &dev->mode_config.connector_list,
10121 base.head) {
10122 connector->new_encoder =
10123 to_intel_encoder(connector->base.encoder);
10124 }
10125
10126 for_each_intel_encoder(dev, encoder) {
10127 encoder->new_crtc =
10128 to_intel_crtc(encoder->base.crtc);
10129 }
10130
10131 for_each_intel_crtc(dev, crtc) {
10132 crtc->new_enabled = crtc->base.enabled;
10133
10134 if (crtc->new_enabled)
10135 crtc->new_config = &crtc->config;
10136 else
10137 crtc->new_config = NULL;
10138 }
10139 }
10140
10141 /**
10142 * intel_modeset_commit_output_state
10143 *
10144 * This function copies the stage display pipe configuration to the real one.
10145 */
10146 static void intel_modeset_commit_output_state(struct drm_device *dev)
10147 {
10148 struct intel_crtc *crtc;
10149 struct intel_encoder *encoder;
10150 struct intel_connector *connector;
10151
10152 list_for_each_entry(connector, &dev->mode_config.connector_list,
10153 base.head) {
10154 connector->base.encoder = &connector->new_encoder->base;
10155 }
10156
10157 for_each_intel_encoder(dev, encoder) {
10158 encoder->base.crtc = &encoder->new_crtc->base;
10159 }
10160
10161 for_each_intel_crtc(dev, crtc) {
10162 crtc->base.enabled = crtc->new_enabled;
10163 }
10164 }
10165
10166 static void
10167 connected_sink_compute_bpp(struct intel_connector *connector,
10168 struct intel_crtc_config *pipe_config)
10169 {
10170 int bpp = pipe_config->pipe_bpp;
10171
10172 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10173 connector->base.base.id,
10174 connector->base.name);
10175
10176 /* Don't use an invalid EDID bpc value */
10177 if (connector->base.display_info.bpc &&
10178 connector->base.display_info.bpc * 3 < bpp) {
10179 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10180 bpp, connector->base.display_info.bpc*3);
10181 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10182 }
10183
10184 /* Clamp bpp to 8 on screens without EDID 1.4 */
10185 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10186 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10187 bpp);
10188 pipe_config->pipe_bpp = 24;
10189 }
10190 }
10191
10192 static int
10193 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10194 struct drm_framebuffer *fb,
10195 struct intel_crtc_config *pipe_config)
10196 {
10197 struct drm_device *dev = crtc->base.dev;
10198 struct intel_connector *connector;
10199 int bpp;
10200
10201 switch (fb->pixel_format) {
10202 case DRM_FORMAT_C8:
10203 bpp = 8*3; /* since we go through a colormap */
10204 break;
10205 case DRM_FORMAT_XRGB1555:
10206 case DRM_FORMAT_ARGB1555:
10207 /* checked in intel_framebuffer_init already */
10208 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10209 return -EINVAL;
10210 case DRM_FORMAT_RGB565:
10211 bpp = 6*3; /* min is 18bpp */
10212 break;
10213 case DRM_FORMAT_XBGR8888:
10214 case DRM_FORMAT_ABGR8888:
10215 /* checked in intel_framebuffer_init already */
10216 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10217 return -EINVAL;
10218 case DRM_FORMAT_XRGB8888:
10219 case DRM_FORMAT_ARGB8888:
10220 bpp = 8*3;
10221 break;
10222 case DRM_FORMAT_XRGB2101010:
10223 case DRM_FORMAT_ARGB2101010:
10224 case DRM_FORMAT_XBGR2101010:
10225 case DRM_FORMAT_ABGR2101010:
10226 /* checked in intel_framebuffer_init already */
10227 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10228 return -EINVAL;
10229 bpp = 10*3;
10230 break;
10231 /* TODO: gen4+ supports 16 bpc floating point, too. */
10232 default:
10233 DRM_DEBUG_KMS("unsupported depth\n");
10234 return -EINVAL;
10235 }
10236
10237 pipe_config->pipe_bpp = bpp;
10238
10239 /* Clamp display bpp to EDID value */
10240 list_for_each_entry(connector, &dev->mode_config.connector_list,
10241 base.head) {
10242 if (!connector->new_encoder ||
10243 connector->new_encoder->new_crtc != crtc)
10244 continue;
10245
10246 connected_sink_compute_bpp(connector, pipe_config);
10247 }
10248
10249 return bpp;
10250 }
10251
10252 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10253 {
10254 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10255 "type: 0x%x flags: 0x%x\n",
10256 mode->crtc_clock,
10257 mode->crtc_hdisplay, mode->crtc_hsync_start,
10258 mode->crtc_hsync_end, mode->crtc_htotal,
10259 mode->crtc_vdisplay, mode->crtc_vsync_start,
10260 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10261 }
10262
10263 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10264 struct intel_crtc_config *pipe_config,
10265 const char *context)
10266 {
10267 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10268 context, pipe_name(crtc->pipe));
10269
10270 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10271 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10272 pipe_config->pipe_bpp, pipe_config->dither);
10273 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10274 pipe_config->has_pch_encoder,
10275 pipe_config->fdi_lanes,
10276 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10277 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10278 pipe_config->fdi_m_n.tu);
10279 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10280 pipe_config->has_dp_encoder,
10281 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10282 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10283 pipe_config->dp_m_n.tu);
10284
10285 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10286 pipe_config->has_dp_encoder,
10287 pipe_config->dp_m2_n2.gmch_m,
10288 pipe_config->dp_m2_n2.gmch_n,
10289 pipe_config->dp_m2_n2.link_m,
10290 pipe_config->dp_m2_n2.link_n,
10291 pipe_config->dp_m2_n2.tu);
10292
10293 DRM_DEBUG_KMS("requested mode:\n");
10294 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10295 DRM_DEBUG_KMS("adjusted mode:\n");
10296 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10297 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10298 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10299 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10300 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10301 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10302 pipe_config->gmch_pfit.control,
10303 pipe_config->gmch_pfit.pgm_ratios,
10304 pipe_config->gmch_pfit.lvds_border_bits);
10305 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10306 pipe_config->pch_pfit.pos,
10307 pipe_config->pch_pfit.size,
10308 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10309 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10310 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10311 }
10312
10313 static bool encoders_cloneable(const struct intel_encoder *a,
10314 const struct intel_encoder *b)
10315 {
10316 /* masks could be asymmetric, so check both ways */
10317 return a == b || (a->cloneable & (1 << b->type) &&
10318 b->cloneable & (1 << a->type));
10319 }
10320
10321 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10322 struct intel_encoder *encoder)
10323 {
10324 struct drm_device *dev = crtc->base.dev;
10325 struct intel_encoder *source_encoder;
10326
10327 for_each_intel_encoder(dev, source_encoder) {
10328 if (source_encoder->new_crtc != crtc)
10329 continue;
10330
10331 if (!encoders_cloneable(encoder, source_encoder))
10332 return false;
10333 }
10334
10335 return true;
10336 }
10337
10338 static bool check_encoder_cloning(struct intel_crtc *crtc)
10339 {
10340 struct drm_device *dev = crtc->base.dev;
10341 struct intel_encoder *encoder;
10342
10343 for_each_intel_encoder(dev, encoder) {
10344 if (encoder->new_crtc != crtc)
10345 continue;
10346
10347 if (!check_single_encoder_cloning(crtc, encoder))
10348 return false;
10349 }
10350
10351 return true;
10352 }
10353
10354 static struct intel_crtc_config *
10355 intel_modeset_pipe_config(struct drm_crtc *crtc,
10356 struct drm_framebuffer *fb,
10357 struct drm_display_mode *mode)
10358 {
10359 struct drm_device *dev = crtc->dev;
10360 struct intel_encoder *encoder;
10361 struct intel_crtc_config *pipe_config;
10362 int plane_bpp, ret = -EINVAL;
10363 bool retry = true;
10364
10365 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10366 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10367 return ERR_PTR(-EINVAL);
10368 }
10369
10370 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10371 if (!pipe_config)
10372 return ERR_PTR(-ENOMEM);
10373
10374 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10375 drm_mode_copy(&pipe_config->requested_mode, mode);
10376
10377 pipe_config->cpu_transcoder =
10378 (enum transcoder) to_intel_crtc(crtc)->pipe;
10379 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10380
10381 /*
10382 * Sanitize sync polarity flags based on requested ones. If neither
10383 * positive or negative polarity is requested, treat this as meaning
10384 * negative polarity.
10385 */
10386 if (!(pipe_config->adjusted_mode.flags &
10387 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10388 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10389
10390 if (!(pipe_config->adjusted_mode.flags &
10391 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10392 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10393
10394 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10395 * plane pixel format and any sink constraints into account. Returns the
10396 * source plane bpp so that dithering can be selected on mismatches
10397 * after encoders and crtc also have had their say. */
10398 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10399 fb, pipe_config);
10400 if (plane_bpp < 0)
10401 goto fail;
10402
10403 /*
10404 * Determine the real pipe dimensions. Note that stereo modes can
10405 * increase the actual pipe size due to the frame doubling and
10406 * insertion of additional space for blanks between the frame. This
10407 * is stored in the crtc timings. We use the requested mode to do this
10408 * computation to clearly distinguish it from the adjusted mode, which
10409 * can be changed by the connectors in the below retry loop.
10410 */
10411 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10412 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10413 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10414
10415 encoder_retry:
10416 /* Ensure the port clock defaults are reset when retrying. */
10417 pipe_config->port_clock = 0;
10418 pipe_config->pixel_multiplier = 1;
10419
10420 /* Fill in default crtc timings, allow encoders to overwrite them. */
10421 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10422
10423 /* Pass our mode to the connectors and the CRTC to give them a chance to
10424 * adjust it according to limitations or connector properties, and also
10425 * a chance to reject the mode entirely.
10426 */
10427 for_each_intel_encoder(dev, encoder) {
10428
10429 if (&encoder->new_crtc->base != crtc)
10430 continue;
10431
10432 if (!(encoder->compute_config(encoder, pipe_config))) {
10433 DRM_DEBUG_KMS("Encoder config failure\n");
10434 goto fail;
10435 }
10436 }
10437
10438 /* Set default port clock if not overwritten by the encoder. Needs to be
10439 * done afterwards in case the encoder adjusts the mode. */
10440 if (!pipe_config->port_clock)
10441 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10442 * pipe_config->pixel_multiplier;
10443
10444 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10445 if (ret < 0) {
10446 DRM_DEBUG_KMS("CRTC fixup failed\n");
10447 goto fail;
10448 }
10449
10450 if (ret == RETRY) {
10451 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10452 ret = -EINVAL;
10453 goto fail;
10454 }
10455
10456 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10457 retry = false;
10458 goto encoder_retry;
10459 }
10460
10461 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10462 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10463 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10464
10465 return pipe_config;
10466 fail:
10467 kfree(pipe_config);
10468 return ERR_PTR(ret);
10469 }
10470
10471 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10472 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10473 static void
10474 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10475 unsigned *prepare_pipes, unsigned *disable_pipes)
10476 {
10477 struct intel_crtc *intel_crtc;
10478 struct drm_device *dev = crtc->dev;
10479 struct intel_encoder *encoder;
10480 struct intel_connector *connector;
10481 struct drm_crtc *tmp_crtc;
10482
10483 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10484
10485 /* Check which crtcs have changed outputs connected to them, these need
10486 * to be part of the prepare_pipes mask. We don't (yet) support global
10487 * modeset across multiple crtcs, so modeset_pipes will only have one
10488 * bit set at most. */
10489 list_for_each_entry(connector, &dev->mode_config.connector_list,
10490 base.head) {
10491 if (connector->base.encoder == &connector->new_encoder->base)
10492 continue;
10493
10494 if (connector->base.encoder) {
10495 tmp_crtc = connector->base.encoder->crtc;
10496
10497 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10498 }
10499
10500 if (connector->new_encoder)
10501 *prepare_pipes |=
10502 1 << connector->new_encoder->new_crtc->pipe;
10503 }
10504
10505 for_each_intel_encoder(dev, encoder) {
10506 if (encoder->base.crtc == &encoder->new_crtc->base)
10507 continue;
10508
10509 if (encoder->base.crtc) {
10510 tmp_crtc = encoder->base.crtc;
10511
10512 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10513 }
10514
10515 if (encoder->new_crtc)
10516 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10517 }
10518
10519 /* Check for pipes that will be enabled/disabled ... */
10520 for_each_intel_crtc(dev, intel_crtc) {
10521 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10522 continue;
10523
10524 if (!intel_crtc->new_enabled)
10525 *disable_pipes |= 1 << intel_crtc->pipe;
10526 else
10527 *prepare_pipes |= 1 << intel_crtc->pipe;
10528 }
10529
10530
10531 /* set_mode is also used to update properties on life display pipes. */
10532 intel_crtc = to_intel_crtc(crtc);
10533 if (intel_crtc->new_enabled)
10534 *prepare_pipes |= 1 << intel_crtc->pipe;
10535
10536 /*
10537 * For simplicity do a full modeset on any pipe where the output routing
10538 * changed. We could be more clever, but that would require us to be
10539 * more careful with calling the relevant encoder->mode_set functions.
10540 */
10541 if (*prepare_pipes)
10542 *modeset_pipes = *prepare_pipes;
10543
10544 /* ... and mask these out. */
10545 *modeset_pipes &= ~(*disable_pipes);
10546 *prepare_pipes &= ~(*disable_pipes);
10547
10548 /*
10549 * HACK: We don't (yet) fully support global modesets. intel_set_config
10550 * obies this rule, but the modeset restore mode of
10551 * intel_modeset_setup_hw_state does not.
10552 */
10553 *modeset_pipes &= 1 << intel_crtc->pipe;
10554 *prepare_pipes &= 1 << intel_crtc->pipe;
10555
10556 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10557 *modeset_pipes, *prepare_pipes, *disable_pipes);
10558 }
10559
10560 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10561 {
10562 struct drm_encoder *encoder;
10563 struct drm_device *dev = crtc->dev;
10564
10565 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10566 if (encoder->crtc == crtc)
10567 return true;
10568
10569 return false;
10570 }
10571
10572 static void
10573 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10574 {
10575 struct intel_encoder *intel_encoder;
10576 struct intel_crtc *intel_crtc;
10577 struct drm_connector *connector;
10578
10579 for_each_intel_encoder(dev, intel_encoder) {
10580 if (!intel_encoder->base.crtc)
10581 continue;
10582
10583 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10584
10585 if (prepare_pipes & (1 << intel_crtc->pipe))
10586 intel_encoder->connectors_active = false;
10587 }
10588
10589 intel_modeset_commit_output_state(dev);
10590
10591 /* Double check state. */
10592 for_each_intel_crtc(dev, intel_crtc) {
10593 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10594 WARN_ON(intel_crtc->new_config &&
10595 intel_crtc->new_config != &intel_crtc->config);
10596 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10597 }
10598
10599 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10600 if (!connector->encoder || !connector->encoder->crtc)
10601 continue;
10602
10603 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10604
10605 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10606 struct drm_property *dpms_property =
10607 dev->mode_config.dpms_property;
10608
10609 connector->dpms = DRM_MODE_DPMS_ON;
10610 drm_object_property_set_value(&connector->base,
10611 dpms_property,
10612 DRM_MODE_DPMS_ON);
10613
10614 intel_encoder = to_intel_encoder(connector->encoder);
10615 intel_encoder->connectors_active = true;
10616 }
10617 }
10618
10619 }
10620
10621 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10622 {
10623 int diff;
10624
10625 if (clock1 == clock2)
10626 return true;
10627
10628 if (!clock1 || !clock2)
10629 return false;
10630
10631 diff = abs(clock1 - clock2);
10632
10633 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10634 return true;
10635
10636 return false;
10637 }
10638
10639 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10640 list_for_each_entry((intel_crtc), \
10641 &(dev)->mode_config.crtc_list, \
10642 base.head) \
10643 if (mask & (1 <<(intel_crtc)->pipe))
10644
10645 static bool
10646 intel_pipe_config_compare(struct drm_device *dev,
10647 struct intel_crtc_config *current_config,
10648 struct intel_crtc_config *pipe_config)
10649 {
10650 #define PIPE_CONF_CHECK_X(name) \
10651 if (current_config->name != pipe_config->name) { \
10652 DRM_ERROR("mismatch in " #name " " \
10653 "(expected 0x%08x, found 0x%08x)\n", \
10654 current_config->name, \
10655 pipe_config->name); \
10656 return false; \
10657 }
10658
10659 #define PIPE_CONF_CHECK_I(name) \
10660 if (current_config->name != pipe_config->name) { \
10661 DRM_ERROR("mismatch in " #name " " \
10662 "(expected %i, found %i)\n", \
10663 current_config->name, \
10664 pipe_config->name); \
10665 return false; \
10666 }
10667
10668 /* This is required for BDW+ where there is only one set of registers for
10669 * switching between high and low RR.
10670 * This macro can be used whenever a comparison has to be made between one
10671 * hw state and multiple sw state variables.
10672 */
10673 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10674 if ((current_config->name != pipe_config->name) && \
10675 (current_config->alt_name != pipe_config->name)) { \
10676 DRM_ERROR("mismatch in " #name " " \
10677 "(expected %i or %i, found %i)\n", \
10678 current_config->name, \
10679 current_config->alt_name, \
10680 pipe_config->name); \
10681 return false; \
10682 }
10683
10684 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10685 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10686 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10687 "(expected %i, found %i)\n", \
10688 current_config->name & (mask), \
10689 pipe_config->name & (mask)); \
10690 return false; \
10691 }
10692
10693 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10694 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10695 DRM_ERROR("mismatch in " #name " " \
10696 "(expected %i, found %i)\n", \
10697 current_config->name, \
10698 pipe_config->name); \
10699 return false; \
10700 }
10701
10702 #define PIPE_CONF_QUIRK(quirk) \
10703 ((current_config->quirks | pipe_config->quirks) & (quirk))
10704
10705 PIPE_CONF_CHECK_I(cpu_transcoder);
10706
10707 PIPE_CONF_CHECK_I(has_pch_encoder);
10708 PIPE_CONF_CHECK_I(fdi_lanes);
10709 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10710 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10711 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10712 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10713 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10714
10715 PIPE_CONF_CHECK_I(has_dp_encoder);
10716
10717 if (INTEL_INFO(dev)->gen < 8) {
10718 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10719 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10720 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10721 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10722 PIPE_CONF_CHECK_I(dp_m_n.tu);
10723
10724 if (current_config->has_drrs) {
10725 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10726 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10727 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10728 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10729 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10730 }
10731 } else {
10732 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10733 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10734 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10735 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10736 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10737 }
10738
10739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10742 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10743 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10744 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10745
10746 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10747 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10748 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10749 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10750 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10751 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10752
10753 PIPE_CONF_CHECK_I(pixel_multiplier);
10754 PIPE_CONF_CHECK_I(has_hdmi_sink);
10755 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10756 IS_VALLEYVIEW(dev))
10757 PIPE_CONF_CHECK_I(limited_color_range);
10758
10759 PIPE_CONF_CHECK_I(has_audio);
10760
10761 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10762 DRM_MODE_FLAG_INTERLACE);
10763
10764 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10765 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10766 DRM_MODE_FLAG_PHSYNC);
10767 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10768 DRM_MODE_FLAG_NHSYNC);
10769 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10770 DRM_MODE_FLAG_PVSYNC);
10771 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10772 DRM_MODE_FLAG_NVSYNC);
10773 }
10774
10775 PIPE_CONF_CHECK_I(pipe_src_w);
10776 PIPE_CONF_CHECK_I(pipe_src_h);
10777
10778 /*
10779 * FIXME: BIOS likes to set up a cloned config with lvds+external
10780 * screen. Since we don't yet re-compute the pipe config when moving
10781 * just the lvds port away to another pipe the sw tracking won't match.
10782 *
10783 * Proper atomic modesets with recomputed global state will fix this.
10784 * Until then just don't check gmch state for inherited modes.
10785 */
10786 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10787 PIPE_CONF_CHECK_I(gmch_pfit.control);
10788 /* pfit ratios are autocomputed by the hw on gen4+ */
10789 if (INTEL_INFO(dev)->gen < 4)
10790 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10791 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10792 }
10793
10794 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10795 if (current_config->pch_pfit.enabled) {
10796 PIPE_CONF_CHECK_I(pch_pfit.pos);
10797 PIPE_CONF_CHECK_I(pch_pfit.size);
10798 }
10799
10800 /* BDW+ don't expose a synchronous way to read the state */
10801 if (IS_HASWELL(dev))
10802 PIPE_CONF_CHECK_I(ips_enabled);
10803
10804 PIPE_CONF_CHECK_I(double_wide);
10805
10806 PIPE_CONF_CHECK_X(ddi_pll_sel);
10807
10808 PIPE_CONF_CHECK_I(shared_dpll);
10809 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10810 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10811 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10812 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10813 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10814
10815 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10816 PIPE_CONF_CHECK_I(pipe_bpp);
10817
10818 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10819 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10820
10821 #undef PIPE_CONF_CHECK_X
10822 #undef PIPE_CONF_CHECK_I
10823 #undef PIPE_CONF_CHECK_I_ALT
10824 #undef PIPE_CONF_CHECK_FLAGS
10825 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10826 #undef PIPE_CONF_QUIRK
10827
10828 return true;
10829 }
10830
10831 static void
10832 check_connector_state(struct drm_device *dev)
10833 {
10834 struct intel_connector *connector;
10835
10836 list_for_each_entry(connector, &dev->mode_config.connector_list,
10837 base.head) {
10838 /* This also checks the encoder/connector hw state with the
10839 * ->get_hw_state callbacks. */
10840 intel_connector_check_state(connector);
10841
10842 WARN(&connector->new_encoder->base != connector->base.encoder,
10843 "connector's staged encoder doesn't match current encoder\n");
10844 }
10845 }
10846
10847 static void
10848 check_encoder_state(struct drm_device *dev)
10849 {
10850 struct intel_encoder *encoder;
10851 struct intel_connector *connector;
10852
10853 for_each_intel_encoder(dev, encoder) {
10854 bool enabled = false;
10855 bool active = false;
10856 enum pipe pipe, tracked_pipe;
10857
10858 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10859 encoder->base.base.id,
10860 encoder->base.name);
10861
10862 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10863 "encoder's stage crtc doesn't match current crtc\n");
10864 WARN(encoder->connectors_active && !encoder->base.crtc,
10865 "encoder's active_connectors set, but no crtc\n");
10866
10867 list_for_each_entry(connector, &dev->mode_config.connector_list,
10868 base.head) {
10869 if (connector->base.encoder != &encoder->base)
10870 continue;
10871 enabled = true;
10872 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10873 active = true;
10874 }
10875 /*
10876 * for MST connectors if we unplug the connector is gone
10877 * away but the encoder is still connected to a crtc
10878 * until a modeset happens in response to the hotplug.
10879 */
10880 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10881 continue;
10882
10883 WARN(!!encoder->base.crtc != enabled,
10884 "encoder's enabled state mismatch "
10885 "(expected %i, found %i)\n",
10886 !!encoder->base.crtc, enabled);
10887 WARN(active && !encoder->base.crtc,
10888 "active encoder with no crtc\n");
10889
10890 WARN(encoder->connectors_active != active,
10891 "encoder's computed active state doesn't match tracked active state "
10892 "(expected %i, found %i)\n", active, encoder->connectors_active);
10893
10894 active = encoder->get_hw_state(encoder, &pipe);
10895 WARN(active != encoder->connectors_active,
10896 "encoder's hw state doesn't match sw tracking "
10897 "(expected %i, found %i)\n",
10898 encoder->connectors_active, active);
10899
10900 if (!encoder->base.crtc)
10901 continue;
10902
10903 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10904 WARN(active && pipe != tracked_pipe,
10905 "active encoder's pipe doesn't match"
10906 "(expected %i, found %i)\n",
10907 tracked_pipe, pipe);
10908
10909 }
10910 }
10911
10912 static void
10913 check_crtc_state(struct drm_device *dev)
10914 {
10915 struct drm_i915_private *dev_priv = dev->dev_private;
10916 struct intel_crtc *crtc;
10917 struct intel_encoder *encoder;
10918 struct intel_crtc_config pipe_config;
10919
10920 for_each_intel_crtc(dev, crtc) {
10921 bool enabled = false;
10922 bool active = false;
10923
10924 memset(&pipe_config, 0, sizeof(pipe_config));
10925
10926 DRM_DEBUG_KMS("[CRTC:%d]\n",
10927 crtc->base.base.id);
10928
10929 WARN(crtc->active && !crtc->base.enabled,
10930 "active crtc, but not enabled in sw tracking\n");
10931
10932 for_each_intel_encoder(dev, encoder) {
10933 if (encoder->base.crtc != &crtc->base)
10934 continue;
10935 enabled = true;
10936 if (encoder->connectors_active)
10937 active = true;
10938 }
10939
10940 WARN(active != crtc->active,
10941 "crtc's computed active state doesn't match tracked active state "
10942 "(expected %i, found %i)\n", active, crtc->active);
10943 WARN(enabled != crtc->base.enabled,
10944 "crtc's computed enabled state doesn't match tracked enabled state "
10945 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10946
10947 active = dev_priv->display.get_pipe_config(crtc,
10948 &pipe_config);
10949
10950 /* hw state is inconsistent with the pipe quirk */
10951 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10952 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10953 active = crtc->active;
10954
10955 for_each_intel_encoder(dev, encoder) {
10956 enum pipe pipe;
10957 if (encoder->base.crtc != &crtc->base)
10958 continue;
10959 if (encoder->get_hw_state(encoder, &pipe))
10960 encoder->get_config(encoder, &pipe_config);
10961 }
10962
10963 WARN(crtc->active != active,
10964 "crtc active state doesn't match with hw state "
10965 "(expected %i, found %i)\n", crtc->active, active);
10966
10967 if (active &&
10968 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10969 WARN(1, "pipe state doesn't match!\n");
10970 intel_dump_pipe_config(crtc, &pipe_config,
10971 "[hw state]");
10972 intel_dump_pipe_config(crtc, &crtc->config,
10973 "[sw state]");
10974 }
10975 }
10976 }
10977
10978 static void
10979 check_shared_dpll_state(struct drm_device *dev)
10980 {
10981 struct drm_i915_private *dev_priv = dev->dev_private;
10982 struct intel_crtc *crtc;
10983 struct intel_dpll_hw_state dpll_hw_state;
10984 int i;
10985
10986 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10987 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10988 int enabled_crtcs = 0, active_crtcs = 0;
10989 bool active;
10990
10991 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10992
10993 DRM_DEBUG_KMS("%s\n", pll->name);
10994
10995 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10996
10997 WARN(pll->active > pll->refcount,
10998 "more active pll users than references: %i vs %i\n",
10999 pll->active, pll->refcount);
11000 WARN(pll->active && !pll->on,
11001 "pll in active use but not on in sw tracking\n");
11002 WARN(pll->on && !pll->active,
11003 "pll in on but not on in use in sw tracking\n");
11004 WARN(pll->on != active,
11005 "pll on state mismatch (expected %i, found %i)\n",
11006 pll->on, active);
11007
11008 for_each_intel_crtc(dev, crtc) {
11009 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
11010 enabled_crtcs++;
11011 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11012 active_crtcs++;
11013 }
11014 WARN(pll->active != active_crtcs,
11015 "pll active crtcs mismatch (expected %i, found %i)\n",
11016 pll->active, active_crtcs);
11017 WARN(pll->refcount != enabled_crtcs,
11018 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11019 pll->refcount, enabled_crtcs);
11020
11021 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
11022 sizeof(dpll_hw_state)),
11023 "pll hw state mismatch\n");
11024 }
11025 }
11026
11027 void
11028 intel_modeset_check_state(struct drm_device *dev)
11029 {
11030 check_connector_state(dev);
11031 check_encoder_state(dev);
11032 check_crtc_state(dev);
11033 check_shared_dpll_state(dev);
11034 }
11035
11036 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
11037 int dotclock)
11038 {
11039 /*
11040 * FDI already provided one idea for the dotclock.
11041 * Yell if the encoder disagrees.
11042 */
11043 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
11044 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11045 pipe_config->adjusted_mode.crtc_clock, dotclock);
11046 }
11047
11048 static void update_scanline_offset(struct intel_crtc *crtc)
11049 {
11050 struct drm_device *dev = crtc->base.dev;
11051
11052 /*
11053 * The scanline counter increments at the leading edge of hsync.
11054 *
11055 * On most platforms it starts counting from vtotal-1 on the
11056 * first active line. That means the scanline counter value is
11057 * always one less than what we would expect. Ie. just after
11058 * start of vblank, which also occurs at start of hsync (on the
11059 * last active line), the scanline counter will read vblank_start-1.
11060 *
11061 * On gen2 the scanline counter starts counting from 1 instead
11062 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11063 * to keep the value positive), instead of adding one.
11064 *
11065 * On HSW+ the behaviour of the scanline counter depends on the output
11066 * type. For DP ports it behaves like most other platforms, but on HDMI
11067 * there's an extra 1 line difference. So we need to add two instead of
11068 * one to the value.
11069 */
11070 if (IS_GEN2(dev)) {
11071 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
11072 int vtotal;
11073
11074 vtotal = mode->crtc_vtotal;
11075 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11076 vtotal /= 2;
11077
11078 crtc->scanline_offset = vtotal - 1;
11079 } else if (HAS_DDI(dev) &&
11080 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
11081 crtc->scanline_offset = 2;
11082 } else
11083 crtc->scanline_offset = 1;
11084 }
11085
11086 static int __intel_set_mode(struct drm_crtc *crtc,
11087 struct drm_display_mode *mode,
11088 int x, int y, struct drm_framebuffer *fb)
11089 {
11090 struct drm_device *dev = crtc->dev;
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct drm_display_mode *saved_mode;
11093 struct intel_crtc_config *pipe_config = NULL;
11094 struct intel_crtc *intel_crtc;
11095 unsigned disable_pipes, prepare_pipes, modeset_pipes;
11096 int ret = 0;
11097
11098 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11099 if (!saved_mode)
11100 return -ENOMEM;
11101
11102 intel_modeset_affected_pipes(crtc, &modeset_pipes,
11103 &prepare_pipes, &disable_pipes);
11104
11105 *saved_mode = crtc->mode;
11106
11107 /* Hack: Because we don't (yet) support global modeset on multiple
11108 * crtcs, we don't keep track of the new mode for more than one crtc.
11109 * Hence simply check whether any bit is set in modeset_pipes in all the
11110 * pieces of code that are not yet converted to deal with mutliple crtcs
11111 * changing their mode at the same time. */
11112 if (modeset_pipes) {
11113 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11114 if (IS_ERR(pipe_config)) {
11115 ret = PTR_ERR(pipe_config);
11116 pipe_config = NULL;
11117
11118 goto out;
11119 }
11120 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11121 "[modeset]");
11122 to_intel_crtc(crtc)->new_config = pipe_config;
11123 }
11124
11125 /*
11126 * See if the config requires any additional preparation, e.g.
11127 * to adjust global state with pipes off. We need to do this
11128 * here so we can get the modeset_pipe updated config for the new
11129 * mode set on this crtc. For other crtcs we need to use the
11130 * adjusted_mode bits in the crtc directly.
11131 */
11132 if (IS_VALLEYVIEW(dev)) {
11133 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11134
11135 /* may have added more to prepare_pipes than we should */
11136 prepare_pipes &= ~disable_pipes;
11137 }
11138
11139 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11140 intel_crtc_disable(&intel_crtc->base);
11141
11142 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11143 if (intel_crtc->base.enabled)
11144 dev_priv->display.crtc_disable(&intel_crtc->base);
11145 }
11146
11147 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11148 * to set it here already despite that we pass it down the callchain.
11149 */
11150 if (modeset_pipes) {
11151 crtc->mode = *mode;
11152 /* mode_set/enable/disable functions rely on a correct pipe
11153 * config. */
11154 to_intel_crtc(crtc)->config = *pipe_config;
11155 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
11156
11157 /*
11158 * Calculate and store various constants which
11159 * are later needed by vblank and swap-completion
11160 * timestamping. They are derived from true hwmode.
11161 */
11162 drm_calc_timestamping_constants(crtc,
11163 &pipe_config->adjusted_mode);
11164 }
11165
11166 /* Only after disabling all output pipelines that will be changed can we
11167 * update the the output configuration. */
11168 intel_modeset_update_state(dev, prepare_pipes);
11169
11170 if (dev_priv->display.modeset_global_resources)
11171 dev_priv->display.modeset_global_resources(dev);
11172
11173 /* Set up the DPLL and any encoders state that needs to adjust or depend
11174 * on the DPLL.
11175 */
11176 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11177 struct drm_framebuffer *old_fb = crtc->primary->fb;
11178 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
11179 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11180
11181 mutex_lock(&dev->struct_mutex);
11182 ret = intel_pin_and_fence_fb_obj(dev,
11183 obj,
11184 NULL);
11185 if (ret != 0) {
11186 DRM_ERROR("pin & fence failed\n");
11187 mutex_unlock(&dev->struct_mutex);
11188 goto done;
11189 }
11190 if (old_fb)
11191 intel_unpin_fb_obj(old_obj);
11192 i915_gem_track_fb(old_obj, obj,
11193 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11194 mutex_unlock(&dev->struct_mutex);
11195
11196 crtc->primary->fb = fb;
11197 crtc->x = x;
11198 crtc->y = y;
11199
11200 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11201 x, y, fb);
11202 if (ret)
11203 goto done;
11204 }
11205
11206 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11207 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11208 update_scanline_offset(intel_crtc);
11209
11210 dev_priv->display.crtc_enable(&intel_crtc->base);
11211 }
11212
11213 /* FIXME: add subpixel order */
11214 done:
11215 if (ret && crtc->enabled)
11216 crtc->mode = *saved_mode;
11217
11218 out:
11219 kfree(pipe_config);
11220 kfree(saved_mode);
11221 return ret;
11222 }
11223
11224 static int intel_set_mode(struct drm_crtc *crtc,
11225 struct drm_display_mode *mode,
11226 int x, int y, struct drm_framebuffer *fb)
11227 {
11228 int ret;
11229
11230 ret = __intel_set_mode(crtc, mode, x, y, fb);
11231
11232 if (ret == 0)
11233 intel_modeset_check_state(crtc->dev);
11234
11235 return ret;
11236 }
11237
11238 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11239 {
11240 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11241 }
11242
11243 #undef for_each_intel_crtc_masked
11244
11245 static void intel_set_config_free(struct intel_set_config *config)
11246 {
11247 if (!config)
11248 return;
11249
11250 kfree(config->save_connector_encoders);
11251 kfree(config->save_encoder_crtcs);
11252 kfree(config->save_crtc_enabled);
11253 kfree(config);
11254 }
11255
11256 static int intel_set_config_save_state(struct drm_device *dev,
11257 struct intel_set_config *config)
11258 {
11259 struct drm_crtc *crtc;
11260 struct drm_encoder *encoder;
11261 struct drm_connector *connector;
11262 int count;
11263
11264 config->save_crtc_enabled =
11265 kcalloc(dev->mode_config.num_crtc,
11266 sizeof(bool), GFP_KERNEL);
11267 if (!config->save_crtc_enabled)
11268 return -ENOMEM;
11269
11270 config->save_encoder_crtcs =
11271 kcalloc(dev->mode_config.num_encoder,
11272 sizeof(struct drm_crtc *), GFP_KERNEL);
11273 if (!config->save_encoder_crtcs)
11274 return -ENOMEM;
11275
11276 config->save_connector_encoders =
11277 kcalloc(dev->mode_config.num_connector,
11278 sizeof(struct drm_encoder *), GFP_KERNEL);
11279 if (!config->save_connector_encoders)
11280 return -ENOMEM;
11281
11282 /* Copy data. Note that driver private data is not affected.
11283 * Should anything bad happen only the expected state is
11284 * restored, not the drivers personal bookkeeping.
11285 */
11286 count = 0;
11287 for_each_crtc(dev, crtc) {
11288 config->save_crtc_enabled[count++] = crtc->enabled;
11289 }
11290
11291 count = 0;
11292 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11293 config->save_encoder_crtcs[count++] = encoder->crtc;
11294 }
11295
11296 count = 0;
11297 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11298 config->save_connector_encoders[count++] = connector->encoder;
11299 }
11300
11301 return 0;
11302 }
11303
11304 static void intel_set_config_restore_state(struct drm_device *dev,
11305 struct intel_set_config *config)
11306 {
11307 struct intel_crtc *crtc;
11308 struct intel_encoder *encoder;
11309 struct intel_connector *connector;
11310 int count;
11311
11312 count = 0;
11313 for_each_intel_crtc(dev, crtc) {
11314 crtc->new_enabled = config->save_crtc_enabled[count++];
11315
11316 if (crtc->new_enabled)
11317 crtc->new_config = &crtc->config;
11318 else
11319 crtc->new_config = NULL;
11320 }
11321
11322 count = 0;
11323 for_each_intel_encoder(dev, encoder) {
11324 encoder->new_crtc =
11325 to_intel_crtc(config->save_encoder_crtcs[count++]);
11326 }
11327
11328 count = 0;
11329 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11330 connector->new_encoder =
11331 to_intel_encoder(config->save_connector_encoders[count++]);
11332 }
11333 }
11334
11335 static bool
11336 is_crtc_connector_off(struct drm_mode_set *set)
11337 {
11338 int i;
11339
11340 if (set->num_connectors == 0)
11341 return false;
11342
11343 if (WARN_ON(set->connectors == NULL))
11344 return false;
11345
11346 for (i = 0; i < set->num_connectors; i++)
11347 if (set->connectors[i]->encoder &&
11348 set->connectors[i]->encoder->crtc == set->crtc &&
11349 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11350 return true;
11351
11352 return false;
11353 }
11354
11355 static void
11356 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11357 struct intel_set_config *config)
11358 {
11359
11360 /* We should be able to check here if the fb has the same properties
11361 * and then just flip_or_move it */
11362 if (is_crtc_connector_off(set)) {
11363 config->mode_changed = true;
11364 } else if (set->crtc->primary->fb != set->fb) {
11365 /*
11366 * If we have no fb, we can only flip as long as the crtc is
11367 * active, otherwise we need a full mode set. The crtc may
11368 * be active if we've only disabled the primary plane, or
11369 * in fastboot situations.
11370 */
11371 if (set->crtc->primary->fb == NULL) {
11372 struct intel_crtc *intel_crtc =
11373 to_intel_crtc(set->crtc);
11374
11375 if (intel_crtc->active) {
11376 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11377 config->fb_changed = true;
11378 } else {
11379 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11380 config->mode_changed = true;
11381 }
11382 } else if (set->fb == NULL) {
11383 config->mode_changed = true;
11384 } else if (set->fb->pixel_format !=
11385 set->crtc->primary->fb->pixel_format) {
11386 config->mode_changed = true;
11387 } else {
11388 config->fb_changed = true;
11389 }
11390 }
11391
11392 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11393 config->fb_changed = true;
11394
11395 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11396 DRM_DEBUG_KMS("modes are different, full mode set\n");
11397 drm_mode_debug_printmodeline(&set->crtc->mode);
11398 drm_mode_debug_printmodeline(set->mode);
11399 config->mode_changed = true;
11400 }
11401
11402 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11403 set->crtc->base.id, config->mode_changed, config->fb_changed);
11404 }
11405
11406 static int
11407 intel_modeset_stage_output_state(struct drm_device *dev,
11408 struct drm_mode_set *set,
11409 struct intel_set_config *config)
11410 {
11411 struct intel_connector *connector;
11412 struct intel_encoder *encoder;
11413 struct intel_crtc *crtc;
11414 int ro;
11415
11416 /* The upper layers ensure that we either disable a crtc or have a list
11417 * of connectors. For paranoia, double-check this. */
11418 WARN_ON(!set->fb && (set->num_connectors != 0));
11419 WARN_ON(set->fb && (set->num_connectors == 0));
11420
11421 list_for_each_entry(connector, &dev->mode_config.connector_list,
11422 base.head) {
11423 /* Otherwise traverse passed in connector list and get encoders
11424 * for them. */
11425 for (ro = 0; ro < set->num_connectors; ro++) {
11426 if (set->connectors[ro] == &connector->base) {
11427 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11428 break;
11429 }
11430 }
11431
11432 /* If we disable the crtc, disable all its connectors. Also, if
11433 * the connector is on the changing crtc but not on the new
11434 * connector list, disable it. */
11435 if ((!set->fb || ro == set->num_connectors) &&
11436 connector->base.encoder &&
11437 connector->base.encoder->crtc == set->crtc) {
11438 connector->new_encoder = NULL;
11439
11440 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11441 connector->base.base.id,
11442 connector->base.name);
11443 }
11444
11445
11446 if (&connector->new_encoder->base != connector->base.encoder) {
11447 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11448 config->mode_changed = true;
11449 }
11450 }
11451 /* connector->new_encoder is now updated for all connectors. */
11452
11453 /* Update crtc of enabled connectors. */
11454 list_for_each_entry(connector, &dev->mode_config.connector_list,
11455 base.head) {
11456 struct drm_crtc *new_crtc;
11457
11458 if (!connector->new_encoder)
11459 continue;
11460
11461 new_crtc = connector->new_encoder->base.crtc;
11462
11463 for (ro = 0; ro < set->num_connectors; ro++) {
11464 if (set->connectors[ro] == &connector->base)
11465 new_crtc = set->crtc;
11466 }
11467
11468 /* Make sure the new CRTC will work with the encoder */
11469 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11470 new_crtc)) {
11471 return -EINVAL;
11472 }
11473 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11474
11475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11476 connector->base.base.id,
11477 connector->base.name,
11478 new_crtc->base.id);
11479 }
11480
11481 /* Check for any encoders that needs to be disabled. */
11482 for_each_intel_encoder(dev, encoder) {
11483 int num_connectors = 0;
11484 list_for_each_entry(connector,
11485 &dev->mode_config.connector_list,
11486 base.head) {
11487 if (connector->new_encoder == encoder) {
11488 WARN_ON(!connector->new_encoder->new_crtc);
11489 num_connectors++;
11490 }
11491 }
11492
11493 if (num_connectors == 0)
11494 encoder->new_crtc = NULL;
11495 else if (num_connectors > 1)
11496 return -EINVAL;
11497
11498 /* Only now check for crtc changes so we don't miss encoders
11499 * that will be disabled. */
11500 if (&encoder->new_crtc->base != encoder->base.crtc) {
11501 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11502 config->mode_changed = true;
11503 }
11504 }
11505 /* Now we've also updated encoder->new_crtc for all encoders. */
11506 list_for_each_entry(connector, &dev->mode_config.connector_list,
11507 base.head) {
11508 if (connector->new_encoder)
11509 if (connector->new_encoder != connector->encoder)
11510 connector->encoder = connector->new_encoder;
11511 }
11512 for_each_intel_crtc(dev, crtc) {
11513 crtc->new_enabled = false;
11514
11515 for_each_intel_encoder(dev, encoder) {
11516 if (encoder->new_crtc == crtc) {
11517 crtc->new_enabled = true;
11518 break;
11519 }
11520 }
11521
11522 if (crtc->new_enabled != crtc->base.enabled) {
11523 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11524 crtc->new_enabled ? "en" : "dis");
11525 config->mode_changed = true;
11526 }
11527
11528 if (crtc->new_enabled)
11529 crtc->new_config = &crtc->config;
11530 else
11531 crtc->new_config = NULL;
11532 }
11533
11534 return 0;
11535 }
11536
11537 static void disable_crtc_nofb(struct intel_crtc *crtc)
11538 {
11539 struct drm_device *dev = crtc->base.dev;
11540 struct intel_encoder *encoder;
11541 struct intel_connector *connector;
11542
11543 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11544 pipe_name(crtc->pipe));
11545
11546 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11547 if (connector->new_encoder &&
11548 connector->new_encoder->new_crtc == crtc)
11549 connector->new_encoder = NULL;
11550 }
11551
11552 for_each_intel_encoder(dev, encoder) {
11553 if (encoder->new_crtc == crtc)
11554 encoder->new_crtc = NULL;
11555 }
11556
11557 crtc->new_enabled = false;
11558 crtc->new_config = NULL;
11559 }
11560
11561 static int intel_crtc_set_config(struct drm_mode_set *set)
11562 {
11563 struct drm_device *dev;
11564 struct drm_mode_set save_set;
11565 struct intel_set_config *config;
11566 int ret;
11567
11568 BUG_ON(!set);
11569 BUG_ON(!set->crtc);
11570 BUG_ON(!set->crtc->helper_private);
11571
11572 /* Enforce sane interface api - has been abused by the fb helper. */
11573 BUG_ON(!set->mode && set->fb);
11574 BUG_ON(set->fb && set->num_connectors == 0);
11575
11576 if (set->fb) {
11577 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11578 set->crtc->base.id, set->fb->base.id,
11579 (int)set->num_connectors, set->x, set->y);
11580 } else {
11581 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11582 }
11583
11584 dev = set->crtc->dev;
11585
11586 ret = -ENOMEM;
11587 config = kzalloc(sizeof(*config), GFP_KERNEL);
11588 if (!config)
11589 goto out_config;
11590
11591 ret = intel_set_config_save_state(dev, config);
11592 if (ret)
11593 goto out_config;
11594
11595 save_set.crtc = set->crtc;
11596 save_set.mode = &set->crtc->mode;
11597 save_set.x = set->crtc->x;
11598 save_set.y = set->crtc->y;
11599 save_set.fb = set->crtc->primary->fb;
11600
11601 /* Compute whether we need a full modeset, only an fb base update or no
11602 * change at all. In the future we might also check whether only the
11603 * mode changed, e.g. for LVDS where we only change the panel fitter in
11604 * such cases. */
11605 intel_set_config_compute_mode_changes(set, config);
11606
11607 ret = intel_modeset_stage_output_state(dev, set, config);
11608 if (ret)
11609 goto fail;
11610
11611 if (config->mode_changed) {
11612 ret = intel_set_mode(set->crtc, set->mode,
11613 set->x, set->y, set->fb);
11614 } else if (config->fb_changed) {
11615 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11616
11617 intel_crtc_wait_for_pending_flips(set->crtc);
11618
11619 ret = intel_pipe_set_base(set->crtc,
11620 set->x, set->y, set->fb);
11621
11622 /*
11623 * We need to make sure the primary plane is re-enabled if it
11624 * has previously been turned off.
11625 */
11626 if (!intel_crtc->primary_enabled && ret == 0) {
11627 WARN_ON(!intel_crtc->active);
11628 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11629 }
11630
11631 /*
11632 * In the fastboot case this may be our only check of the
11633 * state after boot. It would be better to only do it on
11634 * the first update, but we don't have a nice way of doing that
11635 * (and really, set_config isn't used much for high freq page
11636 * flipping, so increasing its cost here shouldn't be a big
11637 * deal).
11638 */
11639 if (i915.fastboot && ret == 0)
11640 intel_modeset_check_state(set->crtc->dev);
11641 }
11642
11643 if (ret) {
11644 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11645 set->crtc->base.id, ret);
11646 fail:
11647 intel_set_config_restore_state(dev, config);
11648
11649 /*
11650 * HACK: if the pipe was on, but we didn't have a framebuffer,
11651 * force the pipe off to avoid oopsing in the modeset code
11652 * due to fb==NULL. This should only happen during boot since
11653 * we don't yet reconstruct the FB from the hardware state.
11654 */
11655 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11656 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11657
11658 /* Try to restore the config */
11659 if (config->mode_changed &&
11660 intel_set_mode(save_set.crtc, save_set.mode,
11661 save_set.x, save_set.y, save_set.fb))
11662 DRM_ERROR("failed to restore config after modeset failure\n");
11663 }
11664
11665 out_config:
11666 intel_set_config_free(config);
11667 return ret;
11668 }
11669
11670 static const struct drm_crtc_funcs intel_crtc_funcs = {
11671 .gamma_set = intel_crtc_gamma_set,
11672 .set_config = intel_crtc_set_config,
11673 .destroy = intel_crtc_destroy,
11674 .page_flip = intel_crtc_page_flip,
11675 };
11676
11677 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11678 struct intel_shared_dpll *pll,
11679 struct intel_dpll_hw_state *hw_state)
11680 {
11681 uint32_t val;
11682
11683 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11684 return false;
11685
11686 val = I915_READ(PCH_DPLL(pll->id));
11687 hw_state->dpll = val;
11688 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11689 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11690
11691 return val & DPLL_VCO_ENABLE;
11692 }
11693
11694 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11695 struct intel_shared_dpll *pll)
11696 {
11697 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11698 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11699 }
11700
11701 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11702 struct intel_shared_dpll *pll)
11703 {
11704 /* PCH refclock must be enabled first */
11705 ibx_assert_pch_refclk_enabled(dev_priv);
11706
11707 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11708
11709 /* Wait for the clocks to stabilize. */
11710 POSTING_READ(PCH_DPLL(pll->id));
11711 udelay(150);
11712
11713 /* The pixel multiplier can only be updated once the
11714 * DPLL is enabled and the clocks are stable.
11715 *
11716 * So write it again.
11717 */
11718 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11719 POSTING_READ(PCH_DPLL(pll->id));
11720 udelay(200);
11721 }
11722
11723 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11724 struct intel_shared_dpll *pll)
11725 {
11726 struct drm_device *dev = dev_priv->dev;
11727 struct intel_crtc *crtc;
11728
11729 /* Make sure no transcoder isn't still depending on us. */
11730 for_each_intel_crtc(dev, crtc) {
11731 if (intel_crtc_to_shared_dpll(crtc) == pll)
11732 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11733 }
11734
11735 I915_WRITE(PCH_DPLL(pll->id), 0);
11736 POSTING_READ(PCH_DPLL(pll->id));
11737 udelay(200);
11738 }
11739
11740 static char *ibx_pch_dpll_names[] = {
11741 "PCH DPLL A",
11742 "PCH DPLL B",
11743 };
11744
11745 static void ibx_pch_dpll_init(struct drm_device *dev)
11746 {
11747 struct drm_i915_private *dev_priv = dev->dev_private;
11748 int i;
11749
11750 dev_priv->num_shared_dpll = 2;
11751
11752 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11753 dev_priv->shared_dplls[i].id = i;
11754 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11755 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11756 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11757 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11758 dev_priv->shared_dplls[i].get_hw_state =
11759 ibx_pch_dpll_get_hw_state;
11760 }
11761 }
11762
11763 static void intel_shared_dpll_init(struct drm_device *dev)
11764 {
11765 struct drm_i915_private *dev_priv = dev->dev_private;
11766
11767 if (HAS_DDI(dev))
11768 intel_ddi_pll_init(dev);
11769 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11770 ibx_pch_dpll_init(dev);
11771 else
11772 dev_priv->num_shared_dpll = 0;
11773
11774 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11775 }
11776
11777 static int
11778 intel_primary_plane_disable(struct drm_plane *plane)
11779 {
11780 struct drm_device *dev = plane->dev;
11781 struct intel_crtc *intel_crtc;
11782
11783 if (!plane->fb)
11784 return 0;
11785
11786 BUG_ON(!plane->crtc);
11787
11788 intel_crtc = to_intel_crtc(plane->crtc);
11789
11790 /*
11791 * Even though we checked plane->fb above, it's still possible that
11792 * the primary plane has been implicitly disabled because the crtc
11793 * coordinates given weren't visible, or because we detected
11794 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11795 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11796 * In either case, we need to unpin the FB and let the fb pointer get
11797 * updated, but otherwise we don't need to touch the hardware.
11798 */
11799 if (!intel_crtc->primary_enabled)
11800 goto disable_unpin;
11801
11802 intel_crtc_wait_for_pending_flips(plane->crtc);
11803 intel_disable_primary_hw_plane(plane, plane->crtc);
11804
11805 disable_unpin:
11806 mutex_lock(&dev->struct_mutex);
11807 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11808 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11809 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11810 mutex_unlock(&dev->struct_mutex);
11811 plane->fb = NULL;
11812
11813 return 0;
11814 }
11815
11816 static int
11817 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11818 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11819 unsigned int crtc_w, unsigned int crtc_h,
11820 uint32_t src_x, uint32_t src_y,
11821 uint32_t src_w, uint32_t src_h)
11822 {
11823 struct drm_device *dev = crtc->dev;
11824 struct drm_i915_private *dev_priv = dev->dev_private;
11825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11826 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11827 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11828 struct drm_rect dest = {
11829 /* integer pixels */
11830 .x1 = crtc_x,
11831 .y1 = crtc_y,
11832 .x2 = crtc_x + crtc_w,
11833 .y2 = crtc_y + crtc_h,
11834 };
11835 struct drm_rect src = {
11836 /* 16.16 fixed point */
11837 .x1 = src_x,
11838 .y1 = src_y,
11839 .x2 = src_x + src_w,
11840 .y2 = src_y + src_h,
11841 };
11842 const struct drm_rect clip = {
11843 /* integer pixels */
11844 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11845 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11846 };
11847 const struct {
11848 int crtc_x, crtc_y;
11849 unsigned int crtc_w, crtc_h;
11850 uint32_t src_x, src_y, src_w, src_h;
11851 } orig = {
11852 .crtc_x = crtc_x,
11853 .crtc_y = crtc_y,
11854 .crtc_w = crtc_w,
11855 .crtc_h = crtc_h,
11856 .src_x = src_x,
11857 .src_y = src_y,
11858 .src_w = src_w,
11859 .src_h = src_h,
11860 };
11861 struct intel_plane *intel_plane = to_intel_plane(plane);
11862 bool visible;
11863 int ret;
11864
11865 ret = drm_plane_helper_check_update(plane, crtc, fb,
11866 &src, &dest, &clip,
11867 DRM_PLANE_HELPER_NO_SCALING,
11868 DRM_PLANE_HELPER_NO_SCALING,
11869 false, true, &visible);
11870
11871 if (ret)
11872 return ret;
11873
11874 /*
11875 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11876 * updating the fb pointer, and returning without touching the
11877 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11878 * turn on the display with all planes setup as desired.
11879 */
11880 if (!crtc->enabled) {
11881 mutex_lock(&dev->struct_mutex);
11882
11883 /*
11884 * If we already called setplane while the crtc was disabled,
11885 * we may have an fb pinned; unpin it.
11886 */
11887 if (plane->fb)
11888 intel_unpin_fb_obj(old_obj);
11889
11890 i915_gem_track_fb(old_obj, obj,
11891 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11892
11893 /* Pin and return without programming hardware */
11894 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11895 mutex_unlock(&dev->struct_mutex);
11896
11897 return ret;
11898 }
11899
11900 intel_crtc_wait_for_pending_flips(crtc);
11901
11902 /*
11903 * If clipping results in a non-visible primary plane, we'll disable
11904 * the primary plane. Note that this is a bit different than what
11905 * happens if userspace explicitly disables the plane by passing fb=0
11906 * because plane->fb still gets set and pinned.
11907 */
11908 if (!visible) {
11909 mutex_lock(&dev->struct_mutex);
11910
11911 /*
11912 * Try to pin the new fb first so that we can bail out if we
11913 * fail.
11914 */
11915 if (plane->fb != fb) {
11916 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11917 if (ret) {
11918 mutex_unlock(&dev->struct_mutex);
11919 return ret;
11920 }
11921 }
11922
11923 i915_gem_track_fb(old_obj, obj,
11924 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11925
11926 if (intel_crtc->primary_enabled)
11927 intel_disable_primary_hw_plane(plane, crtc);
11928
11929
11930 if (plane->fb != fb)
11931 if (plane->fb)
11932 intel_unpin_fb_obj(old_obj);
11933
11934 mutex_unlock(&dev->struct_mutex);
11935
11936 } else {
11937 if (intel_crtc && intel_crtc->active &&
11938 intel_crtc->primary_enabled) {
11939 /*
11940 * FBC does not work on some platforms for rotated
11941 * planes, so disable it when rotation is not 0 and
11942 * update it when rotation is set back to 0.
11943 *
11944 * FIXME: This is redundant with the fbc update done in
11945 * the primary plane enable function except that that
11946 * one is done too late. We eventually need to unify
11947 * this.
11948 */
11949 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11950 dev_priv->fbc.plane == intel_crtc->plane &&
11951 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11952 intel_disable_fbc(dev);
11953 }
11954 }
11955 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11956 if (ret)
11957 return ret;
11958
11959 if (!intel_crtc->primary_enabled)
11960 intel_enable_primary_hw_plane(plane, crtc);
11961 }
11962
11963 intel_plane->crtc_x = orig.crtc_x;
11964 intel_plane->crtc_y = orig.crtc_y;
11965 intel_plane->crtc_w = orig.crtc_w;
11966 intel_plane->crtc_h = orig.crtc_h;
11967 intel_plane->src_x = orig.src_x;
11968 intel_plane->src_y = orig.src_y;
11969 intel_plane->src_w = orig.src_w;
11970 intel_plane->src_h = orig.src_h;
11971 intel_plane->obj = obj;
11972
11973 return 0;
11974 }
11975
11976 /* Common destruction function for both primary and cursor planes */
11977 static void intel_plane_destroy(struct drm_plane *plane)
11978 {
11979 struct intel_plane *intel_plane = to_intel_plane(plane);
11980 drm_plane_cleanup(plane);
11981 kfree(intel_plane);
11982 }
11983
11984 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11985 .update_plane = intel_primary_plane_setplane,
11986 .disable_plane = intel_primary_plane_disable,
11987 .destroy = intel_plane_destroy,
11988 .set_property = intel_plane_set_property
11989 };
11990
11991 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11992 int pipe)
11993 {
11994 struct intel_plane *primary;
11995 const uint32_t *intel_primary_formats;
11996 int num_formats;
11997
11998 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11999 if (primary == NULL)
12000 return NULL;
12001
12002 primary->can_scale = false;
12003 primary->max_downscale = 1;
12004 primary->pipe = pipe;
12005 primary->plane = pipe;
12006 primary->rotation = BIT(DRM_ROTATE_0);
12007 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12008 primary->plane = !pipe;
12009
12010 if (INTEL_INFO(dev)->gen <= 3) {
12011 intel_primary_formats = intel_primary_formats_gen2;
12012 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12013 } else {
12014 intel_primary_formats = intel_primary_formats_gen4;
12015 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12016 }
12017
12018 drm_universal_plane_init(dev, &primary->base, 0,
12019 &intel_primary_plane_funcs,
12020 intel_primary_formats, num_formats,
12021 DRM_PLANE_TYPE_PRIMARY);
12022
12023 if (INTEL_INFO(dev)->gen >= 4) {
12024 if (!dev->mode_config.rotation_property)
12025 dev->mode_config.rotation_property =
12026 drm_mode_create_rotation_property(dev,
12027 BIT(DRM_ROTATE_0) |
12028 BIT(DRM_ROTATE_180));
12029 if (dev->mode_config.rotation_property)
12030 drm_object_attach_property(&primary->base.base,
12031 dev->mode_config.rotation_property,
12032 primary->rotation);
12033 }
12034
12035 return &primary->base;
12036 }
12037
12038 static int
12039 intel_cursor_plane_disable(struct drm_plane *plane)
12040 {
12041 if (!plane->fb)
12042 return 0;
12043
12044 BUG_ON(!plane->crtc);
12045
12046 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
12047 }
12048
12049 static int
12050 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
12051 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
12052 unsigned int crtc_w, unsigned int crtc_h,
12053 uint32_t src_x, uint32_t src_y,
12054 uint32_t src_w, uint32_t src_h)
12055 {
12056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12057 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12058 struct drm_i915_gem_object *obj = intel_fb->obj;
12059 struct drm_rect dest = {
12060 /* integer pixels */
12061 .x1 = crtc_x,
12062 .y1 = crtc_y,
12063 .x2 = crtc_x + crtc_w,
12064 .y2 = crtc_y + crtc_h,
12065 };
12066 struct drm_rect src = {
12067 /* 16.16 fixed point */
12068 .x1 = src_x,
12069 .y1 = src_y,
12070 .x2 = src_x + src_w,
12071 .y2 = src_y + src_h,
12072 };
12073 const struct drm_rect clip = {
12074 /* integer pixels */
12075 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
12076 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
12077 };
12078 bool visible;
12079 int ret;
12080
12081 ret = drm_plane_helper_check_update(plane, crtc, fb,
12082 &src, &dest, &clip,
12083 DRM_PLANE_HELPER_NO_SCALING,
12084 DRM_PLANE_HELPER_NO_SCALING,
12085 true, true, &visible);
12086 if (ret)
12087 return ret;
12088
12089 crtc->cursor_x = crtc_x;
12090 crtc->cursor_y = crtc_y;
12091 if (fb != crtc->cursor->fb) {
12092 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
12093 } else {
12094 intel_crtc_update_cursor(crtc, visible);
12095
12096 intel_frontbuffer_flip(crtc->dev,
12097 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
12098
12099 return 0;
12100 }
12101 }
12102 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12103 .update_plane = intel_cursor_plane_update,
12104 .disable_plane = intel_cursor_plane_disable,
12105 .destroy = intel_plane_destroy,
12106 };
12107
12108 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12109 int pipe)
12110 {
12111 struct intel_plane *cursor;
12112
12113 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12114 if (cursor == NULL)
12115 return NULL;
12116
12117 cursor->can_scale = false;
12118 cursor->max_downscale = 1;
12119 cursor->pipe = pipe;
12120 cursor->plane = pipe;
12121
12122 drm_universal_plane_init(dev, &cursor->base, 0,
12123 &intel_cursor_plane_funcs,
12124 intel_cursor_formats,
12125 ARRAY_SIZE(intel_cursor_formats),
12126 DRM_PLANE_TYPE_CURSOR);
12127 return &cursor->base;
12128 }
12129
12130 static void intel_crtc_init(struct drm_device *dev, int pipe)
12131 {
12132 struct drm_i915_private *dev_priv = dev->dev_private;
12133 struct intel_crtc *intel_crtc;
12134 struct drm_plane *primary = NULL;
12135 struct drm_plane *cursor = NULL;
12136 int i, ret;
12137
12138 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12139 if (intel_crtc == NULL)
12140 return;
12141
12142 primary = intel_primary_plane_create(dev, pipe);
12143 if (!primary)
12144 goto fail;
12145
12146 cursor = intel_cursor_plane_create(dev, pipe);
12147 if (!cursor)
12148 goto fail;
12149
12150 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12151 cursor, &intel_crtc_funcs);
12152 if (ret)
12153 goto fail;
12154
12155 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12156 for (i = 0; i < 256; i++) {
12157 intel_crtc->lut_r[i] = i;
12158 intel_crtc->lut_g[i] = i;
12159 intel_crtc->lut_b[i] = i;
12160 }
12161
12162 /*
12163 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12164 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12165 */
12166 intel_crtc->pipe = pipe;
12167 intel_crtc->plane = pipe;
12168 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12169 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12170 intel_crtc->plane = !pipe;
12171 }
12172
12173 intel_crtc->cursor_base = ~0;
12174 intel_crtc->cursor_cntl = ~0;
12175 intel_crtc->cursor_size = ~0;
12176
12177 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12178 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12179 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12180 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12181
12182 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12183
12184 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12185 return;
12186
12187 fail:
12188 if (primary)
12189 drm_plane_cleanup(primary);
12190 if (cursor)
12191 drm_plane_cleanup(cursor);
12192 kfree(intel_crtc);
12193 }
12194
12195 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12196 {
12197 struct drm_encoder *encoder = connector->base.encoder;
12198 struct drm_device *dev = connector->base.dev;
12199
12200 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12201
12202 if (!encoder)
12203 return INVALID_PIPE;
12204
12205 return to_intel_crtc(encoder->crtc)->pipe;
12206 }
12207
12208 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12209 struct drm_file *file)
12210 {
12211 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12212 struct drm_crtc *drmmode_crtc;
12213 struct intel_crtc *crtc;
12214
12215 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12216 return -ENODEV;
12217
12218 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12219
12220 if (!drmmode_crtc) {
12221 DRM_ERROR("no such CRTC id\n");
12222 return -ENOENT;
12223 }
12224
12225 crtc = to_intel_crtc(drmmode_crtc);
12226 pipe_from_crtc_id->pipe = crtc->pipe;
12227
12228 return 0;
12229 }
12230
12231 static int intel_encoder_clones(struct intel_encoder *encoder)
12232 {
12233 struct drm_device *dev = encoder->base.dev;
12234 struct intel_encoder *source_encoder;
12235 int index_mask = 0;
12236 int entry = 0;
12237
12238 for_each_intel_encoder(dev, source_encoder) {
12239 if (encoders_cloneable(encoder, source_encoder))
12240 index_mask |= (1 << entry);
12241
12242 entry++;
12243 }
12244
12245 return index_mask;
12246 }
12247
12248 static bool has_edp_a(struct drm_device *dev)
12249 {
12250 struct drm_i915_private *dev_priv = dev->dev_private;
12251
12252 if (!IS_MOBILE(dev))
12253 return false;
12254
12255 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12256 return false;
12257
12258 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12259 return false;
12260
12261 return true;
12262 }
12263
12264 const char *intel_output_name(int output)
12265 {
12266 static const char *names[] = {
12267 [INTEL_OUTPUT_UNUSED] = "Unused",
12268 [INTEL_OUTPUT_ANALOG] = "Analog",
12269 [INTEL_OUTPUT_DVO] = "DVO",
12270 [INTEL_OUTPUT_SDVO] = "SDVO",
12271 [INTEL_OUTPUT_LVDS] = "LVDS",
12272 [INTEL_OUTPUT_TVOUT] = "TV",
12273 [INTEL_OUTPUT_HDMI] = "HDMI",
12274 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12275 [INTEL_OUTPUT_EDP] = "eDP",
12276 [INTEL_OUTPUT_DSI] = "DSI",
12277 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12278 };
12279
12280 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12281 return "Invalid";
12282
12283 return names[output];
12284 }
12285
12286 static bool intel_crt_present(struct drm_device *dev)
12287 {
12288 struct drm_i915_private *dev_priv = dev->dev_private;
12289
12290 if (IS_ULT(dev))
12291 return false;
12292
12293 if (IS_CHERRYVIEW(dev))
12294 return false;
12295
12296 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12297 return false;
12298
12299 return true;
12300 }
12301
12302 static void intel_setup_outputs(struct drm_device *dev)
12303 {
12304 struct drm_i915_private *dev_priv = dev->dev_private;
12305 struct intel_encoder *encoder;
12306 bool dpd_is_edp = false;
12307
12308 intel_lvds_init(dev);
12309
12310 if (intel_crt_present(dev))
12311 intel_crt_init(dev);
12312
12313 if (HAS_DDI(dev)) {
12314 int found;
12315
12316 /* Haswell uses DDI functions to detect digital outputs */
12317 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12318 /* DDI A only supports eDP */
12319 if (found)
12320 intel_ddi_init(dev, PORT_A);
12321
12322 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12323 * register */
12324 found = I915_READ(SFUSE_STRAP);
12325
12326 if (found & SFUSE_STRAP_DDIB_DETECTED)
12327 intel_ddi_init(dev, PORT_B);
12328 if (found & SFUSE_STRAP_DDIC_DETECTED)
12329 intel_ddi_init(dev, PORT_C);
12330 if (found & SFUSE_STRAP_DDID_DETECTED)
12331 intel_ddi_init(dev, PORT_D);
12332 } else if (HAS_PCH_SPLIT(dev)) {
12333 int found;
12334 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12335
12336 if (has_edp_a(dev))
12337 intel_dp_init(dev, DP_A, PORT_A);
12338
12339 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12340 /* PCH SDVOB multiplex with HDMIB */
12341 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12342 if (!found)
12343 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12344 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12345 intel_dp_init(dev, PCH_DP_B, PORT_B);
12346 }
12347
12348 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12349 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12350
12351 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12352 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12353
12354 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12355 intel_dp_init(dev, PCH_DP_C, PORT_C);
12356
12357 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12358 intel_dp_init(dev, PCH_DP_D, PORT_D);
12359 } else if (IS_VALLEYVIEW(dev)) {
12360 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12361 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12362 PORT_B);
12363 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12364 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12365 }
12366
12367 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12368 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12369 PORT_C);
12370 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12371 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12372 }
12373
12374 if (IS_CHERRYVIEW(dev)) {
12375 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12376 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12377 PORT_D);
12378 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12379 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12380 }
12381 }
12382
12383 intel_dsi_init(dev);
12384 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12385 bool found = false;
12386
12387 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12388 DRM_DEBUG_KMS("probing SDVOB\n");
12389 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12390 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12391 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12392 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12393 }
12394
12395 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12396 intel_dp_init(dev, DP_B, PORT_B);
12397 }
12398
12399 /* Before G4X SDVOC doesn't have its own detect register */
12400
12401 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12402 DRM_DEBUG_KMS("probing SDVOC\n");
12403 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12404 }
12405
12406 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12407
12408 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12409 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12410 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12411 }
12412 if (SUPPORTS_INTEGRATED_DP(dev))
12413 intel_dp_init(dev, DP_C, PORT_C);
12414 }
12415
12416 if (SUPPORTS_INTEGRATED_DP(dev) &&
12417 (I915_READ(DP_D) & DP_DETECTED))
12418 intel_dp_init(dev, DP_D, PORT_D);
12419 } else if (IS_GEN2(dev))
12420 intel_dvo_init(dev);
12421
12422 if (SUPPORTS_TV(dev))
12423 intel_tv_init(dev);
12424
12425 intel_edp_psr_init(dev);
12426
12427 for_each_intel_encoder(dev, encoder) {
12428 encoder->base.possible_crtcs = encoder->crtc_mask;
12429 encoder->base.possible_clones =
12430 intel_encoder_clones(encoder);
12431 }
12432
12433 intel_init_pch_refclk(dev);
12434
12435 drm_helper_move_panel_connectors_to_head(dev);
12436 }
12437
12438 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12439 {
12440 struct drm_device *dev = fb->dev;
12441 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12442
12443 drm_framebuffer_cleanup(fb);
12444 mutex_lock(&dev->struct_mutex);
12445 WARN_ON(!intel_fb->obj->framebuffer_references--);
12446 drm_gem_object_unreference(&intel_fb->obj->base);
12447 mutex_unlock(&dev->struct_mutex);
12448 kfree(intel_fb);
12449 }
12450
12451 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12452 struct drm_file *file,
12453 unsigned int *handle)
12454 {
12455 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12456 struct drm_i915_gem_object *obj = intel_fb->obj;
12457
12458 return drm_gem_handle_create(file, &obj->base, handle);
12459 }
12460
12461 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12462 .destroy = intel_user_framebuffer_destroy,
12463 .create_handle = intel_user_framebuffer_create_handle,
12464 };
12465
12466 static int intel_framebuffer_init(struct drm_device *dev,
12467 struct intel_framebuffer *intel_fb,
12468 struct drm_mode_fb_cmd2 *mode_cmd,
12469 struct drm_i915_gem_object *obj)
12470 {
12471 int aligned_height;
12472 int pitch_limit;
12473 int ret;
12474
12475 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12476
12477 if (obj->tiling_mode == I915_TILING_Y) {
12478 DRM_DEBUG("hardware does not support tiling Y\n");
12479 return -EINVAL;
12480 }
12481
12482 if (mode_cmd->pitches[0] & 63) {
12483 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12484 mode_cmd->pitches[0]);
12485 return -EINVAL;
12486 }
12487
12488 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12489 pitch_limit = 32*1024;
12490 } else if (INTEL_INFO(dev)->gen >= 4) {
12491 if (obj->tiling_mode)
12492 pitch_limit = 16*1024;
12493 else
12494 pitch_limit = 32*1024;
12495 } else if (INTEL_INFO(dev)->gen >= 3) {
12496 if (obj->tiling_mode)
12497 pitch_limit = 8*1024;
12498 else
12499 pitch_limit = 16*1024;
12500 } else
12501 /* XXX DSPC is limited to 4k tiled */
12502 pitch_limit = 8*1024;
12503
12504 if (mode_cmd->pitches[0] > pitch_limit) {
12505 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12506 obj->tiling_mode ? "tiled" : "linear",
12507 mode_cmd->pitches[0], pitch_limit);
12508 return -EINVAL;
12509 }
12510
12511 if (obj->tiling_mode != I915_TILING_NONE &&
12512 mode_cmd->pitches[0] != obj->stride) {
12513 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12514 mode_cmd->pitches[0], obj->stride);
12515 return -EINVAL;
12516 }
12517
12518 /* Reject formats not supported by any plane early. */
12519 switch (mode_cmd->pixel_format) {
12520 case DRM_FORMAT_C8:
12521 case DRM_FORMAT_RGB565:
12522 case DRM_FORMAT_XRGB8888:
12523 case DRM_FORMAT_ARGB8888:
12524 break;
12525 case DRM_FORMAT_XRGB1555:
12526 case DRM_FORMAT_ARGB1555:
12527 if (INTEL_INFO(dev)->gen > 3) {
12528 DRM_DEBUG("unsupported pixel format: %s\n",
12529 drm_get_format_name(mode_cmd->pixel_format));
12530 return -EINVAL;
12531 }
12532 break;
12533 case DRM_FORMAT_XBGR8888:
12534 case DRM_FORMAT_ABGR8888:
12535 case DRM_FORMAT_XRGB2101010:
12536 case DRM_FORMAT_ARGB2101010:
12537 case DRM_FORMAT_XBGR2101010:
12538 case DRM_FORMAT_ABGR2101010:
12539 if (INTEL_INFO(dev)->gen < 4) {
12540 DRM_DEBUG("unsupported pixel format: %s\n",
12541 drm_get_format_name(mode_cmd->pixel_format));
12542 return -EINVAL;
12543 }
12544 break;
12545 case DRM_FORMAT_YUYV:
12546 case DRM_FORMAT_UYVY:
12547 case DRM_FORMAT_YVYU:
12548 case DRM_FORMAT_VYUY:
12549 if (INTEL_INFO(dev)->gen < 5) {
12550 DRM_DEBUG("unsupported pixel format: %s\n",
12551 drm_get_format_name(mode_cmd->pixel_format));
12552 return -EINVAL;
12553 }
12554 break;
12555 default:
12556 DRM_DEBUG("unsupported pixel format: %s\n",
12557 drm_get_format_name(mode_cmd->pixel_format));
12558 return -EINVAL;
12559 }
12560
12561 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12562 if (mode_cmd->offsets[0] != 0)
12563 return -EINVAL;
12564
12565 aligned_height = intel_align_height(dev, mode_cmd->height,
12566 obj->tiling_mode);
12567 /* FIXME drm helper for size checks (especially planar formats)? */
12568 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12569 return -EINVAL;
12570
12571 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12572 intel_fb->obj = obj;
12573 intel_fb->obj->framebuffer_references++;
12574
12575 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12576 if (ret) {
12577 DRM_ERROR("framebuffer init failed %d\n", ret);
12578 return ret;
12579 }
12580
12581 return 0;
12582 }
12583
12584 static struct drm_framebuffer *
12585 intel_user_framebuffer_create(struct drm_device *dev,
12586 struct drm_file *filp,
12587 struct drm_mode_fb_cmd2 *mode_cmd)
12588 {
12589 struct drm_i915_gem_object *obj;
12590
12591 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12592 mode_cmd->handles[0]));
12593 if (&obj->base == NULL)
12594 return ERR_PTR(-ENOENT);
12595
12596 return intel_framebuffer_create(dev, mode_cmd, obj);
12597 }
12598
12599 #ifndef CONFIG_DRM_I915_FBDEV
12600 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12601 {
12602 }
12603 #endif
12604
12605 static const struct drm_mode_config_funcs intel_mode_funcs = {
12606 .fb_create = intel_user_framebuffer_create,
12607 .output_poll_changed = intel_fbdev_output_poll_changed,
12608 };
12609
12610 /* Set up chip specific display functions */
12611 static void intel_init_display(struct drm_device *dev)
12612 {
12613 struct drm_i915_private *dev_priv = dev->dev_private;
12614
12615 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12616 dev_priv->display.find_dpll = g4x_find_best_dpll;
12617 else if (IS_CHERRYVIEW(dev))
12618 dev_priv->display.find_dpll = chv_find_best_dpll;
12619 else if (IS_VALLEYVIEW(dev))
12620 dev_priv->display.find_dpll = vlv_find_best_dpll;
12621 else if (IS_PINEVIEW(dev))
12622 dev_priv->display.find_dpll = pnv_find_best_dpll;
12623 else
12624 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12625
12626 if (HAS_DDI(dev)) {
12627 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12628 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12629 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12630 dev_priv->display.crtc_enable = haswell_crtc_enable;
12631 dev_priv->display.crtc_disable = haswell_crtc_disable;
12632 dev_priv->display.off = ironlake_crtc_off;
12633 dev_priv->display.update_primary_plane =
12634 ironlake_update_primary_plane;
12635 } else if (HAS_PCH_SPLIT(dev)) {
12636 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12637 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12638 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12639 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12640 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12641 dev_priv->display.off = ironlake_crtc_off;
12642 dev_priv->display.update_primary_plane =
12643 ironlake_update_primary_plane;
12644 } else if (IS_VALLEYVIEW(dev)) {
12645 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12646 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12647 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12648 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12649 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12650 dev_priv->display.off = i9xx_crtc_off;
12651 dev_priv->display.update_primary_plane =
12652 i9xx_update_primary_plane;
12653 } else {
12654 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12655 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12656 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12657 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12658 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12659 dev_priv->display.off = i9xx_crtc_off;
12660 dev_priv->display.update_primary_plane =
12661 i9xx_update_primary_plane;
12662 }
12663
12664 /* Returns the core display clock speed */
12665 if (IS_VALLEYVIEW(dev))
12666 dev_priv->display.get_display_clock_speed =
12667 valleyview_get_display_clock_speed;
12668 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12669 dev_priv->display.get_display_clock_speed =
12670 i945_get_display_clock_speed;
12671 else if (IS_I915G(dev))
12672 dev_priv->display.get_display_clock_speed =
12673 i915_get_display_clock_speed;
12674 else if (IS_I945GM(dev) || IS_845G(dev))
12675 dev_priv->display.get_display_clock_speed =
12676 i9xx_misc_get_display_clock_speed;
12677 else if (IS_PINEVIEW(dev))
12678 dev_priv->display.get_display_clock_speed =
12679 pnv_get_display_clock_speed;
12680 else if (IS_I915GM(dev))
12681 dev_priv->display.get_display_clock_speed =
12682 i915gm_get_display_clock_speed;
12683 else if (IS_I865G(dev))
12684 dev_priv->display.get_display_clock_speed =
12685 i865_get_display_clock_speed;
12686 else if (IS_I85X(dev))
12687 dev_priv->display.get_display_clock_speed =
12688 i855_get_display_clock_speed;
12689 else /* 852, 830 */
12690 dev_priv->display.get_display_clock_speed =
12691 i830_get_display_clock_speed;
12692
12693 if (IS_G4X(dev)) {
12694 dev_priv->display.write_eld = g4x_write_eld;
12695 } else if (IS_GEN5(dev)) {
12696 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12697 dev_priv->display.write_eld = ironlake_write_eld;
12698 } else if (IS_GEN6(dev)) {
12699 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12700 dev_priv->display.write_eld = ironlake_write_eld;
12701 dev_priv->display.modeset_global_resources =
12702 snb_modeset_global_resources;
12703 } else if (IS_IVYBRIDGE(dev)) {
12704 /* FIXME: detect B0+ stepping and use auto training */
12705 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12706 dev_priv->display.write_eld = ironlake_write_eld;
12707 dev_priv->display.modeset_global_resources =
12708 ivb_modeset_global_resources;
12709 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12710 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12711 dev_priv->display.write_eld = haswell_write_eld;
12712 dev_priv->display.modeset_global_resources =
12713 haswell_modeset_global_resources;
12714 } else if (IS_VALLEYVIEW(dev)) {
12715 dev_priv->display.modeset_global_resources =
12716 valleyview_modeset_global_resources;
12717 dev_priv->display.write_eld = ironlake_write_eld;
12718 }
12719
12720 /* Default just returns -ENODEV to indicate unsupported */
12721 dev_priv->display.queue_flip = intel_default_queue_flip;
12722
12723 switch (INTEL_INFO(dev)->gen) {
12724 case 2:
12725 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12726 break;
12727
12728 case 3:
12729 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12730 break;
12731
12732 case 4:
12733 case 5:
12734 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12735 break;
12736
12737 case 6:
12738 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12739 break;
12740 case 7:
12741 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12742 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12743 break;
12744 }
12745
12746 intel_panel_init_backlight_funcs(dev);
12747
12748 mutex_init(&dev_priv->pps_mutex);
12749 }
12750
12751 /*
12752 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12753 * resume, or other times. This quirk makes sure that's the case for
12754 * affected systems.
12755 */
12756 static void quirk_pipea_force(struct drm_device *dev)
12757 {
12758 struct drm_i915_private *dev_priv = dev->dev_private;
12759
12760 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12761 DRM_INFO("applying pipe a force quirk\n");
12762 }
12763
12764 static void quirk_pipeb_force(struct drm_device *dev)
12765 {
12766 struct drm_i915_private *dev_priv = dev->dev_private;
12767
12768 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12769 DRM_INFO("applying pipe b force quirk\n");
12770 }
12771
12772 /*
12773 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12774 */
12775 static void quirk_ssc_force_disable(struct drm_device *dev)
12776 {
12777 struct drm_i915_private *dev_priv = dev->dev_private;
12778 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12779 DRM_INFO("applying lvds SSC disable quirk\n");
12780 }
12781
12782 /*
12783 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12784 * brightness value
12785 */
12786 static void quirk_invert_brightness(struct drm_device *dev)
12787 {
12788 struct drm_i915_private *dev_priv = dev->dev_private;
12789 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12790 DRM_INFO("applying inverted panel brightness quirk\n");
12791 }
12792
12793 /* Some VBT's incorrectly indicate no backlight is present */
12794 static void quirk_backlight_present(struct drm_device *dev)
12795 {
12796 struct drm_i915_private *dev_priv = dev->dev_private;
12797 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12798 DRM_INFO("applying backlight present quirk\n");
12799 }
12800
12801 struct intel_quirk {
12802 int device;
12803 int subsystem_vendor;
12804 int subsystem_device;
12805 void (*hook)(struct drm_device *dev);
12806 };
12807
12808 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12809 struct intel_dmi_quirk {
12810 void (*hook)(struct drm_device *dev);
12811 const struct dmi_system_id (*dmi_id_list)[];
12812 };
12813
12814 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12815 {
12816 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12817 return 1;
12818 }
12819
12820 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12821 {
12822 .dmi_id_list = &(const struct dmi_system_id[]) {
12823 {
12824 .callback = intel_dmi_reverse_brightness,
12825 .ident = "NCR Corporation",
12826 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12827 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12828 },
12829 },
12830 { } /* terminating entry */
12831 },
12832 .hook = quirk_invert_brightness,
12833 },
12834 };
12835
12836 static struct intel_quirk intel_quirks[] = {
12837 /* HP Mini needs pipe A force quirk (LP: #322104) */
12838 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12839
12840 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12841 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12842
12843 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12844 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12845
12846 /* 830 needs to leave pipe A & dpll A up */
12847 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12848
12849 /* 830 needs to leave pipe B & dpll B up */
12850 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12851
12852 /* Lenovo U160 cannot use SSC on LVDS */
12853 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12854
12855 /* Sony Vaio Y cannot use SSC on LVDS */
12856 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12857
12858 /* Acer Aspire 5734Z must invert backlight brightness */
12859 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12860
12861 /* Acer/eMachines G725 */
12862 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12863
12864 /* Acer/eMachines e725 */
12865 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12866
12867 /* Acer/Packard Bell NCL20 */
12868 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12869
12870 /* Acer Aspire 4736Z */
12871 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12872
12873 /* Acer Aspire 5336 */
12874 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12875
12876 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12877 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12878
12879 /* Acer C720 Chromebook (Core i3 4005U) */
12880 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12881
12882 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12883 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12884
12885 /* HP Chromebook 14 (Celeron 2955U) */
12886 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12887 };
12888
12889 static void intel_init_quirks(struct drm_device *dev)
12890 {
12891 struct pci_dev *d = dev->pdev;
12892 int i;
12893
12894 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12895 struct intel_quirk *q = &intel_quirks[i];
12896
12897 if (d->device == q->device &&
12898 (d->subsystem_vendor == q->subsystem_vendor ||
12899 q->subsystem_vendor == PCI_ANY_ID) &&
12900 (d->subsystem_device == q->subsystem_device ||
12901 q->subsystem_device == PCI_ANY_ID))
12902 q->hook(dev);
12903 }
12904 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12905 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12906 intel_dmi_quirks[i].hook(dev);
12907 }
12908 }
12909
12910 /* Disable the VGA plane that we never use */
12911 static void i915_disable_vga(struct drm_device *dev)
12912 {
12913 struct drm_i915_private *dev_priv = dev->dev_private;
12914 u8 sr1;
12915 u32 vga_reg = i915_vgacntrl_reg(dev);
12916
12917 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12918 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12919 outb(SR01, VGA_SR_INDEX);
12920 sr1 = inb(VGA_SR_DATA);
12921 outb(sr1 | 1<<5, VGA_SR_DATA);
12922 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12923 udelay(300);
12924
12925 /*
12926 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12927 * from S3 without preserving (some of?) the other bits.
12928 */
12929 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12930 POSTING_READ(vga_reg);
12931 }
12932
12933 void intel_modeset_init_hw(struct drm_device *dev)
12934 {
12935 intel_prepare_ddi(dev);
12936
12937 if (IS_VALLEYVIEW(dev))
12938 vlv_update_cdclk(dev);
12939
12940 intel_init_clock_gating(dev);
12941
12942 intel_enable_gt_powersave(dev);
12943 }
12944
12945 void intel_modeset_suspend_hw(struct drm_device *dev)
12946 {
12947 intel_suspend_hw(dev);
12948 }
12949
12950 void intel_modeset_init(struct drm_device *dev)
12951 {
12952 struct drm_i915_private *dev_priv = dev->dev_private;
12953 int sprite, ret;
12954 enum pipe pipe;
12955 struct intel_crtc *crtc;
12956
12957 drm_mode_config_init(dev);
12958
12959 dev->mode_config.min_width = 0;
12960 dev->mode_config.min_height = 0;
12961
12962 dev->mode_config.preferred_depth = 24;
12963 dev->mode_config.prefer_shadow = 1;
12964
12965 dev->mode_config.funcs = &intel_mode_funcs;
12966
12967 intel_init_quirks(dev);
12968
12969 intel_init_pm(dev);
12970
12971 if (INTEL_INFO(dev)->num_pipes == 0)
12972 return;
12973
12974 intel_init_display(dev);
12975
12976 if (IS_GEN2(dev)) {
12977 dev->mode_config.max_width = 2048;
12978 dev->mode_config.max_height = 2048;
12979 } else if (IS_GEN3(dev)) {
12980 dev->mode_config.max_width = 4096;
12981 dev->mode_config.max_height = 4096;
12982 } else {
12983 dev->mode_config.max_width = 8192;
12984 dev->mode_config.max_height = 8192;
12985 }
12986
12987 if (IS_845G(dev) || IS_I865G(dev)) {
12988 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12989 dev->mode_config.cursor_height = 1023;
12990 } else if (IS_GEN2(dev)) {
12991 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12992 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12993 } else {
12994 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12995 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12996 }
12997
12998 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12999
13000 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13001 INTEL_INFO(dev)->num_pipes,
13002 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13003
13004 for_each_pipe(dev_priv, pipe) {
13005 intel_crtc_init(dev, pipe);
13006 for_each_sprite(pipe, sprite) {
13007 ret = intel_plane_init(dev, pipe, sprite);
13008 if (ret)
13009 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13010 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13011 }
13012 }
13013
13014 intel_init_dpio(dev);
13015
13016 intel_shared_dpll_init(dev);
13017
13018 /* save the BIOS value before clobbering it */
13019 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
13020 /* Just disable it once at startup */
13021 i915_disable_vga(dev);
13022 intel_setup_outputs(dev);
13023
13024 /* Just in case the BIOS is doing something questionable. */
13025 intel_disable_fbc(dev);
13026
13027 drm_modeset_lock_all(dev);
13028 intel_modeset_setup_hw_state(dev, false);
13029 drm_modeset_unlock_all(dev);
13030
13031 for_each_intel_crtc(dev, crtc) {
13032 if (!crtc->active)
13033 continue;
13034
13035 /*
13036 * Note that reserving the BIOS fb up front prevents us
13037 * from stuffing other stolen allocations like the ring
13038 * on top. This prevents some ugliness at boot time, and
13039 * can even allow for smooth boot transitions if the BIOS
13040 * fb is large enough for the active pipe configuration.
13041 */
13042 if (dev_priv->display.get_plane_config) {
13043 dev_priv->display.get_plane_config(crtc,
13044 &crtc->plane_config);
13045 /*
13046 * If the fb is shared between multiple heads, we'll
13047 * just get the first one.
13048 */
13049 intel_find_plane_obj(crtc, &crtc->plane_config);
13050 }
13051 }
13052 }
13053
13054 static void intel_enable_pipe_a(struct drm_device *dev)
13055 {
13056 struct intel_connector *connector;
13057 struct drm_connector *crt = NULL;
13058 struct intel_load_detect_pipe load_detect_temp;
13059 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13060
13061 /* We can't just switch on the pipe A, we need to set things up with a
13062 * proper mode and output configuration. As a gross hack, enable pipe A
13063 * by enabling the load detect pipe once. */
13064 list_for_each_entry(connector,
13065 &dev->mode_config.connector_list,
13066 base.head) {
13067 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13068 crt = &connector->base;
13069 break;
13070 }
13071 }
13072
13073 if (!crt)
13074 return;
13075
13076 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13077 intel_release_load_detect_pipe(crt, &load_detect_temp);
13078 }
13079
13080 static bool
13081 intel_check_plane_mapping(struct intel_crtc *crtc)
13082 {
13083 struct drm_device *dev = crtc->base.dev;
13084 struct drm_i915_private *dev_priv = dev->dev_private;
13085 u32 reg, val;
13086
13087 if (INTEL_INFO(dev)->num_pipes == 1)
13088 return true;
13089
13090 reg = DSPCNTR(!crtc->plane);
13091 val = I915_READ(reg);
13092
13093 if ((val & DISPLAY_PLANE_ENABLE) &&
13094 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13095 return false;
13096
13097 return true;
13098 }
13099
13100 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13101 {
13102 struct drm_device *dev = crtc->base.dev;
13103 struct drm_i915_private *dev_priv = dev->dev_private;
13104 u32 reg;
13105
13106 /* Clear any frame start delays used for debugging left by the BIOS */
13107 reg = PIPECONF(crtc->config.cpu_transcoder);
13108 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13109
13110 /* restore vblank interrupts to correct state */
13111 if (crtc->active) {
13112 update_scanline_offset(crtc);
13113 drm_vblank_on(dev, crtc->pipe);
13114 } else
13115 drm_vblank_off(dev, crtc->pipe);
13116
13117 /* We need to sanitize the plane -> pipe mapping first because this will
13118 * disable the crtc (and hence change the state) if it is wrong. Note
13119 * that gen4+ has a fixed plane -> pipe mapping. */
13120 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13121 struct intel_connector *connector;
13122 bool plane;
13123
13124 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13125 crtc->base.base.id);
13126
13127 /* Pipe has the wrong plane attached and the plane is active.
13128 * Temporarily change the plane mapping and disable everything
13129 * ... */
13130 plane = crtc->plane;
13131 crtc->plane = !plane;
13132 crtc->primary_enabled = true;
13133 dev_priv->display.crtc_disable(&crtc->base);
13134 crtc->plane = plane;
13135
13136 /* ... and break all links. */
13137 list_for_each_entry(connector, &dev->mode_config.connector_list,
13138 base.head) {
13139 if (connector->encoder->base.crtc != &crtc->base)
13140 continue;
13141
13142 connector->base.dpms = DRM_MODE_DPMS_OFF;
13143 connector->base.encoder = NULL;
13144 }
13145 /* multiple connectors may have the same encoder:
13146 * handle them and break crtc link separately */
13147 list_for_each_entry(connector, &dev->mode_config.connector_list,
13148 base.head)
13149 if (connector->encoder->base.crtc == &crtc->base) {
13150 connector->encoder->base.crtc = NULL;
13151 connector->encoder->connectors_active = false;
13152 }
13153
13154 WARN_ON(crtc->active);
13155 crtc->base.enabled = false;
13156 }
13157
13158 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13159 crtc->pipe == PIPE_A && !crtc->active) {
13160 /* BIOS forgot to enable pipe A, this mostly happens after
13161 * resume. Force-enable the pipe to fix this, the update_dpms
13162 * call below we restore the pipe to the right state, but leave
13163 * the required bits on. */
13164 intel_enable_pipe_a(dev);
13165 }
13166
13167 /* Adjust the state of the output pipe according to whether we
13168 * have active connectors/encoders. */
13169 intel_crtc_update_dpms(&crtc->base);
13170
13171 if (crtc->active != crtc->base.enabled) {
13172 struct intel_encoder *encoder;
13173
13174 /* This can happen either due to bugs in the get_hw_state
13175 * functions or because the pipe is force-enabled due to the
13176 * pipe A quirk. */
13177 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13178 crtc->base.base.id,
13179 crtc->base.enabled ? "enabled" : "disabled",
13180 crtc->active ? "enabled" : "disabled");
13181
13182 crtc->base.enabled = crtc->active;
13183
13184 /* Because we only establish the connector -> encoder ->
13185 * crtc links if something is active, this means the
13186 * crtc is now deactivated. Break the links. connector
13187 * -> encoder links are only establish when things are
13188 * actually up, hence no need to break them. */
13189 WARN_ON(crtc->active);
13190
13191 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13192 WARN_ON(encoder->connectors_active);
13193 encoder->base.crtc = NULL;
13194 }
13195 }
13196
13197 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13198 /*
13199 * We start out with underrun reporting disabled to avoid races.
13200 * For correct bookkeeping mark this on active crtcs.
13201 *
13202 * Also on gmch platforms we dont have any hardware bits to
13203 * disable the underrun reporting. Which means we need to start
13204 * out with underrun reporting disabled also on inactive pipes,
13205 * since otherwise we'll complain about the garbage we read when
13206 * e.g. coming up after runtime pm.
13207 *
13208 * No protection against concurrent access is required - at
13209 * worst a fifo underrun happens which also sets this to false.
13210 */
13211 crtc->cpu_fifo_underrun_disabled = true;
13212 crtc->pch_fifo_underrun_disabled = true;
13213 }
13214 }
13215
13216 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13217 {
13218 struct intel_connector *connector;
13219 struct drm_device *dev = encoder->base.dev;
13220
13221 /* We need to check both for a crtc link (meaning that the
13222 * encoder is active and trying to read from a pipe) and the
13223 * pipe itself being active. */
13224 bool has_active_crtc = encoder->base.crtc &&
13225 to_intel_crtc(encoder->base.crtc)->active;
13226
13227 if (encoder->connectors_active && !has_active_crtc) {
13228 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13229 encoder->base.base.id,
13230 encoder->base.name);
13231
13232 /* Connector is active, but has no active pipe. This is
13233 * fallout from our resume register restoring. Disable
13234 * the encoder manually again. */
13235 if (encoder->base.crtc) {
13236 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13237 encoder->base.base.id,
13238 encoder->base.name);
13239 encoder->disable(encoder);
13240 if (encoder->post_disable)
13241 encoder->post_disable(encoder);
13242 }
13243 encoder->base.crtc = NULL;
13244 encoder->connectors_active = false;
13245
13246 /* Inconsistent output/port/pipe state happens presumably due to
13247 * a bug in one of the get_hw_state functions. Or someplace else
13248 * in our code, like the register restore mess on resume. Clamp
13249 * things to off as a safer default. */
13250 list_for_each_entry(connector,
13251 &dev->mode_config.connector_list,
13252 base.head) {
13253 if (connector->encoder != encoder)
13254 continue;
13255 connector->base.dpms = DRM_MODE_DPMS_OFF;
13256 connector->base.encoder = NULL;
13257 }
13258 }
13259 /* Enabled encoders without active connectors will be fixed in
13260 * the crtc fixup. */
13261 }
13262
13263 void i915_redisable_vga_power_on(struct drm_device *dev)
13264 {
13265 struct drm_i915_private *dev_priv = dev->dev_private;
13266 u32 vga_reg = i915_vgacntrl_reg(dev);
13267
13268 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13269 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13270 i915_disable_vga(dev);
13271 }
13272 }
13273
13274 void i915_redisable_vga(struct drm_device *dev)
13275 {
13276 struct drm_i915_private *dev_priv = dev->dev_private;
13277
13278 /* This function can be called both from intel_modeset_setup_hw_state or
13279 * at a very early point in our resume sequence, where the power well
13280 * structures are not yet restored. Since this function is at a very
13281 * paranoid "someone might have enabled VGA while we were not looking"
13282 * level, just check if the power well is enabled instead of trying to
13283 * follow the "don't touch the power well if we don't need it" policy
13284 * the rest of the driver uses. */
13285 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13286 return;
13287
13288 i915_redisable_vga_power_on(dev);
13289 }
13290
13291 static bool primary_get_hw_state(struct intel_crtc *crtc)
13292 {
13293 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13294
13295 if (!crtc->active)
13296 return false;
13297
13298 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13299 }
13300
13301 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13302 {
13303 struct drm_i915_private *dev_priv = dev->dev_private;
13304 enum pipe pipe;
13305 struct intel_crtc *crtc;
13306 struct intel_encoder *encoder;
13307 struct intel_connector *connector;
13308 int i;
13309
13310 for_each_intel_crtc(dev, crtc) {
13311 memset(&crtc->config, 0, sizeof(crtc->config));
13312
13313 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13314
13315 crtc->active = dev_priv->display.get_pipe_config(crtc,
13316 &crtc->config);
13317
13318 crtc->base.enabled = crtc->active;
13319 crtc->primary_enabled = primary_get_hw_state(crtc);
13320
13321 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13322 crtc->base.base.id,
13323 crtc->active ? "enabled" : "disabled");
13324 }
13325
13326 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13327 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13328
13329 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13330 pll->active = 0;
13331 for_each_intel_crtc(dev, crtc) {
13332 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13333 pll->active++;
13334 }
13335 pll->refcount = pll->active;
13336
13337 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13338 pll->name, pll->refcount, pll->on);
13339
13340 if (pll->refcount)
13341 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13342 }
13343
13344 for_each_intel_encoder(dev, encoder) {
13345 pipe = 0;
13346
13347 if (encoder->get_hw_state(encoder, &pipe)) {
13348 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13349 encoder->base.crtc = &crtc->base;
13350 encoder->get_config(encoder, &crtc->config);
13351 } else {
13352 encoder->base.crtc = NULL;
13353 }
13354
13355 encoder->connectors_active = false;
13356 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13357 encoder->base.base.id,
13358 encoder->base.name,
13359 encoder->base.crtc ? "enabled" : "disabled",
13360 pipe_name(pipe));
13361 }
13362
13363 list_for_each_entry(connector, &dev->mode_config.connector_list,
13364 base.head) {
13365 if (connector->get_hw_state(connector)) {
13366 connector->base.dpms = DRM_MODE_DPMS_ON;
13367 connector->encoder->connectors_active = true;
13368 connector->base.encoder = &connector->encoder->base;
13369 } else {
13370 connector->base.dpms = DRM_MODE_DPMS_OFF;
13371 connector->base.encoder = NULL;
13372 }
13373 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13374 connector->base.base.id,
13375 connector->base.name,
13376 connector->base.encoder ? "enabled" : "disabled");
13377 }
13378 }
13379
13380 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13381 * and i915 state tracking structures. */
13382 void intel_modeset_setup_hw_state(struct drm_device *dev,
13383 bool force_restore)
13384 {
13385 struct drm_i915_private *dev_priv = dev->dev_private;
13386 enum pipe pipe;
13387 struct intel_crtc *crtc;
13388 struct intel_encoder *encoder;
13389 int i;
13390
13391 intel_modeset_readout_hw_state(dev);
13392
13393 /*
13394 * Now that we have the config, copy it to each CRTC struct
13395 * Note that this could go away if we move to using crtc_config
13396 * checking everywhere.
13397 */
13398 for_each_intel_crtc(dev, crtc) {
13399 if (crtc->active && i915.fastboot) {
13400 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13401 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13402 crtc->base.base.id);
13403 drm_mode_debug_printmodeline(&crtc->base.mode);
13404 }
13405 }
13406
13407 /* HW state is read out, now we need to sanitize this mess. */
13408 for_each_intel_encoder(dev, encoder) {
13409 intel_sanitize_encoder(encoder);
13410 }
13411
13412 for_each_pipe(dev_priv, pipe) {
13413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13414 intel_sanitize_crtc(crtc);
13415 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13416 }
13417
13418 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13419 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13420
13421 if (!pll->on || pll->active)
13422 continue;
13423
13424 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13425
13426 pll->disable(dev_priv, pll);
13427 pll->on = false;
13428 }
13429
13430 if (HAS_PCH_SPLIT(dev))
13431 ilk_wm_get_hw_state(dev);
13432
13433 if (force_restore) {
13434 i915_redisable_vga(dev);
13435
13436 /*
13437 * We need to use raw interfaces for restoring state to avoid
13438 * checking (bogus) intermediate states.
13439 */
13440 for_each_pipe(dev_priv, pipe) {
13441 struct drm_crtc *crtc =
13442 dev_priv->pipe_to_crtc_mapping[pipe];
13443
13444 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13445 crtc->primary->fb);
13446 }
13447 } else {
13448 intel_modeset_update_staged_output_state(dev);
13449 }
13450
13451 intel_modeset_check_state(dev);
13452 }
13453
13454 void intel_modeset_gem_init(struct drm_device *dev)
13455 {
13456 struct drm_crtc *c;
13457 struct drm_i915_gem_object *obj;
13458
13459 mutex_lock(&dev->struct_mutex);
13460 intel_init_gt_powersave(dev);
13461 mutex_unlock(&dev->struct_mutex);
13462
13463 intel_modeset_init_hw(dev);
13464
13465 intel_setup_overlay(dev);
13466
13467 /*
13468 * Make sure any fbs we allocated at startup are properly
13469 * pinned & fenced. When we do the allocation it's too early
13470 * for this.
13471 */
13472 mutex_lock(&dev->struct_mutex);
13473 for_each_crtc(dev, c) {
13474 obj = intel_fb_obj(c->primary->fb);
13475 if (obj == NULL)
13476 continue;
13477
13478 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13479 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13480 to_intel_crtc(c)->pipe);
13481 drm_framebuffer_unreference(c->primary->fb);
13482 c->primary->fb = NULL;
13483 }
13484 }
13485 mutex_unlock(&dev->struct_mutex);
13486 }
13487
13488 void intel_connector_unregister(struct intel_connector *intel_connector)
13489 {
13490 struct drm_connector *connector = &intel_connector->base;
13491
13492 intel_panel_destroy_backlight(connector);
13493 drm_connector_unregister(connector);
13494 }
13495
13496 void intel_modeset_cleanup(struct drm_device *dev)
13497 {
13498 struct drm_i915_private *dev_priv = dev->dev_private;
13499 struct drm_connector *connector;
13500
13501 /*
13502 * Interrupts and polling as the first thing to avoid creating havoc.
13503 * Too much stuff here (turning of rps, connectors, ...) would
13504 * experience fancy races otherwise.
13505 */
13506 drm_irq_uninstall(dev);
13507 intel_hpd_cancel_work(dev_priv);
13508 dev_priv->pm._irqs_disabled = true;
13509
13510 /*
13511 * Due to the hpd irq storm handling the hotplug work can re-arm the
13512 * poll handlers. Hence disable polling after hpd handling is shut down.
13513 */
13514 drm_kms_helper_poll_fini(dev);
13515
13516 mutex_lock(&dev->struct_mutex);
13517
13518 intel_unregister_dsm_handler();
13519
13520 intel_disable_fbc(dev);
13521
13522 intel_disable_gt_powersave(dev);
13523
13524 ironlake_teardown_rc6(dev);
13525
13526 mutex_unlock(&dev->struct_mutex);
13527
13528 /* flush any delayed tasks or pending work */
13529 flush_scheduled_work();
13530
13531 /* destroy the backlight and sysfs files before encoders/connectors */
13532 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13533 struct intel_connector *intel_connector;
13534
13535 intel_connector = to_intel_connector(connector);
13536 intel_connector->unregister(intel_connector);
13537 }
13538
13539 drm_mode_config_cleanup(dev);
13540
13541 intel_cleanup_overlay(dev);
13542
13543 mutex_lock(&dev->struct_mutex);
13544 intel_cleanup_gt_powersave(dev);
13545 mutex_unlock(&dev->struct_mutex);
13546 }
13547
13548 /*
13549 * Return which encoder is currently attached for connector.
13550 */
13551 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13552 {
13553 return &intel_attached_encoder(connector)->base;
13554 }
13555
13556 void intel_connector_attach_encoder(struct intel_connector *connector,
13557 struct intel_encoder *encoder)
13558 {
13559 connector->encoder = encoder;
13560 drm_mode_connector_attach_encoder(&connector->base,
13561 &encoder->base);
13562 }
13563
13564 /*
13565 * set vga decode state - true == enable VGA decode
13566 */
13567 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13568 {
13569 struct drm_i915_private *dev_priv = dev->dev_private;
13570 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13571 u16 gmch_ctrl;
13572
13573 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13574 DRM_ERROR("failed to read control word\n");
13575 return -EIO;
13576 }
13577
13578 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13579 return 0;
13580
13581 if (state)
13582 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13583 else
13584 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13585
13586 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13587 DRM_ERROR("failed to write control word\n");
13588 return -EIO;
13589 }
13590
13591 return 0;
13592 }
13593
13594 struct intel_display_error_state {
13595
13596 u32 power_well_driver;
13597
13598 int num_transcoders;
13599
13600 struct intel_cursor_error_state {
13601 u32 control;
13602 u32 position;
13603 u32 base;
13604 u32 size;
13605 } cursor[I915_MAX_PIPES];
13606
13607 struct intel_pipe_error_state {
13608 bool power_domain_on;
13609 u32 source;
13610 u32 stat;
13611 } pipe[I915_MAX_PIPES];
13612
13613 struct intel_plane_error_state {
13614 u32 control;
13615 u32 stride;
13616 u32 size;
13617 u32 pos;
13618 u32 addr;
13619 u32 surface;
13620 u32 tile_offset;
13621 } plane[I915_MAX_PIPES];
13622
13623 struct intel_transcoder_error_state {
13624 bool power_domain_on;
13625 enum transcoder cpu_transcoder;
13626
13627 u32 conf;
13628
13629 u32 htotal;
13630 u32 hblank;
13631 u32 hsync;
13632 u32 vtotal;
13633 u32 vblank;
13634 u32 vsync;
13635 } transcoder[4];
13636 };
13637
13638 struct intel_display_error_state *
13639 intel_display_capture_error_state(struct drm_device *dev)
13640 {
13641 struct drm_i915_private *dev_priv = dev->dev_private;
13642 struct intel_display_error_state *error;
13643 int transcoders[] = {
13644 TRANSCODER_A,
13645 TRANSCODER_B,
13646 TRANSCODER_C,
13647 TRANSCODER_EDP,
13648 };
13649 int i;
13650
13651 if (INTEL_INFO(dev)->num_pipes == 0)
13652 return NULL;
13653
13654 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13655 if (error == NULL)
13656 return NULL;
13657
13658 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13659 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13660
13661 for_each_pipe(dev_priv, i) {
13662 error->pipe[i].power_domain_on =
13663 intel_display_power_enabled_unlocked(dev_priv,
13664 POWER_DOMAIN_PIPE(i));
13665 if (!error->pipe[i].power_domain_on)
13666 continue;
13667
13668 error->cursor[i].control = I915_READ(CURCNTR(i));
13669 error->cursor[i].position = I915_READ(CURPOS(i));
13670 error->cursor[i].base = I915_READ(CURBASE(i));
13671
13672 error->plane[i].control = I915_READ(DSPCNTR(i));
13673 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13674 if (INTEL_INFO(dev)->gen <= 3) {
13675 error->plane[i].size = I915_READ(DSPSIZE(i));
13676 error->plane[i].pos = I915_READ(DSPPOS(i));
13677 }
13678 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13679 error->plane[i].addr = I915_READ(DSPADDR(i));
13680 if (INTEL_INFO(dev)->gen >= 4) {
13681 error->plane[i].surface = I915_READ(DSPSURF(i));
13682 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13683 }
13684
13685 error->pipe[i].source = I915_READ(PIPESRC(i));
13686
13687 if (HAS_GMCH_DISPLAY(dev))
13688 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13689 }
13690
13691 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13692 if (HAS_DDI(dev_priv->dev))
13693 error->num_transcoders++; /* Account for eDP. */
13694
13695 for (i = 0; i < error->num_transcoders; i++) {
13696 enum transcoder cpu_transcoder = transcoders[i];
13697
13698 error->transcoder[i].power_domain_on =
13699 intel_display_power_enabled_unlocked(dev_priv,
13700 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13701 if (!error->transcoder[i].power_domain_on)
13702 continue;
13703
13704 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13705
13706 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13707 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13708 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13709 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13710 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13711 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13712 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13713 }
13714
13715 return error;
13716 }
13717
13718 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13719
13720 void
13721 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13722 struct drm_device *dev,
13723 struct intel_display_error_state *error)
13724 {
13725 struct drm_i915_private *dev_priv = dev->dev_private;
13726 int i;
13727
13728 if (!error)
13729 return;
13730
13731 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13732 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13733 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13734 error->power_well_driver);
13735 for_each_pipe(dev_priv, i) {
13736 err_printf(m, "Pipe [%d]:\n", i);
13737 err_printf(m, " Power: %s\n",
13738 error->pipe[i].power_domain_on ? "on" : "off");
13739 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13740 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13741
13742 err_printf(m, "Plane [%d]:\n", i);
13743 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13744 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13745 if (INTEL_INFO(dev)->gen <= 3) {
13746 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13747 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13748 }
13749 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13750 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13751 if (INTEL_INFO(dev)->gen >= 4) {
13752 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13753 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13754 }
13755
13756 err_printf(m, "Cursor [%d]:\n", i);
13757 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13758 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13759 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13760 }
13761
13762 for (i = 0; i < error->num_transcoders; i++) {
13763 err_printf(m, "CPU transcoder: %c\n",
13764 transcoder_name(error->transcoder[i].cpu_transcoder));
13765 err_printf(m, " Power: %s\n",
13766 error->transcoder[i].power_domain_on ? "on" : "off");
13767 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13768 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13769 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13770 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13771 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13772 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13773 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13774 }
13775 }
13776
13777 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13778 {
13779 struct intel_crtc *crtc;
13780
13781 for_each_intel_crtc(dev, crtc) {
13782 struct intel_unpin_work *work;
13783 unsigned long irqflags;
13784
13785 spin_lock_irqsave(&dev->event_lock, irqflags);
13786
13787 work = crtc->unpin_work;
13788
13789 if (work && work->event &&
13790 work->event->base.file_priv == file) {
13791 kfree(work->event);
13792 work->event = NULL;
13793 }
13794
13795 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13796 }
13797 }
Linux kernel - Deliverables
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