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drm/i915: Handle error to get connector state when staging config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
88 static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
92 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
97 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
98 static void haswell_set_pipeconf(struct drm_crtc *crtc);
99 static void intel_set_pipe_csc(struct drm_crtc *crtc);
100 static void vlv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void chv_prepare_pll(struct intel_crtc *crtc,
103 const struct intel_crtc_state *pipe_config);
104 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
106
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108 {
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113 }
114
115 typedef struct {
116 int min, max;
117 } intel_range_t;
118
119 typedef struct {
120 int dot_limit;
121 int p2_slow, p2_fast;
122 } intel_p2_t;
123
124 typedef struct intel_limit intel_limit_t;
125 struct intel_limit {
126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
128 };
129
130 int
131 intel_pch_rawclk(struct drm_device *dev)
132 {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138 }
139
140 static inline u32 /* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device *dev)
142 {
143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
148 }
149
150 static const intel_limit_t intel_limits_i8xx_dac = {
151 .dot = { .min = 25000, .max = 350000 },
152 .vco = { .min = 908000, .max = 1512000 },
153 .n = { .min = 2, .max = 16 },
154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
161 };
162
163 static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
165 .vco = { .min = 908000, .max = 1512000 },
166 .n = { .min = 2, .max = 16 },
167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174 };
175
176 static const intel_limit_t intel_limits_i8xx_lvds = {
177 .dot = { .min = 25000, .max = 350000 },
178 .vco = { .min = 908000, .max = 1512000 },
179 .n = { .min = 2, .max = 16 },
180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
187 };
188
189 static const intel_limit_t intel_limits_i9xx_sdvo = {
190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
200 };
201
202 static const intel_limit_t intel_limits_i9xx_lvds = {
203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
213 };
214
215
216 static const intel_limit_t intel_limits_g4x_sdvo = {
217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
228 },
229 };
230
231 static const intel_limit_t intel_limits_g4x_hdmi = {
232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
242 };
243
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
255 },
256 };
257
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
269 },
270 };
271
272 static const intel_limit_t intel_limits_pineview_sdvo = {
273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 };
299
300 /* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
305 static const intel_limit_t intel_limits_ironlake_dac = {
306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
316 };
317
318 static const intel_limit_t intel_limits_ironlake_single_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 };
330
331 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 };
343
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
353 .p1 = { .min = 2, .max = 8 },
354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
356 };
357
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
366 .p1 = { .min = 2, .max = 6 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
369 };
370
371 static const intel_limit_t intel_limits_vlv = {
372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
385 };
386
387 static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
395 .vco = { .min = 4800000, .max = 6480000 },
396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401 };
402
403 static void vlv_clock(int refclk, intel_clock_t *clock)
404 {
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
411 }
412
413 /**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
416 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
417 {
418 struct drm_device *dev = crtc->base.dev;
419 struct intel_encoder *encoder;
420
421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
422 if (encoder->type == type)
423 return true;
424
425 return false;
426 }
427
428 /**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
436 {
437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
439 struct intel_encoder *encoder;
440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
451
452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
454 return true;
455 }
456
457 WARN_ON(num_connectors == 0);
458
459 return false;
460 }
461
462 static const intel_limit_t *
463 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
464 {
465 struct drm_device *dev = crtc_state->base.crtc->dev;
466 const intel_limit_t *limit;
467
468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
469 if (intel_is_dual_link_lvds(dev)) {
470 if (refclk == 100000)
471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
475 if (refclk == 100000)
476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
480 } else
481 limit = &intel_limits_ironlake_dac;
482
483 return limit;
484 }
485
486 static const intel_limit_t *
487 intel_g4x_limit(struct intel_crtc_state *crtc_state)
488 {
489 struct drm_device *dev = crtc_state->base.crtc->dev;
490 const intel_limit_t *limit;
491
492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
493 if (intel_is_dual_link_lvds(dev))
494 limit = &intel_limits_g4x_dual_channel_lvds;
495 else
496 limit = &intel_limits_g4x_single_channel_lvds;
497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
499 limit = &intel_limits_g4x_hdmi;
500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
501 limit = &intel_limits_g4x_sdvo;
502 } else /* The option is for other outputs */
503 limit = &intel_limits_i9xx_sdvo;
504
505 return limit;
506 }
507
508 static const intel_limit_t *
509 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
510 {
511 struct drm_device *dev = crtc_state->base.crtc->dev;
512 const intel_limit_t *limit;
513
514 if (HAS_PCH_SPLIT(dev))
515 limit = intel_ironlake_limit(crtc_state, refclk);
516 else if (IS_G4X(dev)) {
517 limit = intel_g4x_limit(crtc_state);
518 } else if (IS_PINEVIEW(dev)) {
519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
520 limit = &intel_limits_pineview_lvds;
521 else
522 limit = &intel_limits_pineview_sdvo;
523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
525 } else if (IS_VALLEYVIEW(dev)) {
526 limit = &intel_limits_vlv;
527 } else if (!IS_GEN2(dev)) {
528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
532 } else {
533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_i8xx_lvds;
535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
536 limit = &intel_limits_i8xx_dvo;
537 else
538 limit = &intel_limits_i8xx_dac;
539 }
540 return limit;
541 }
542
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk, intel_clock_t *clock)
545 {
546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
552 }
553
554 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555 {
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557 }
558
559 static void i9xx_clock(int refclk, intel_clock_t *clock)
560 {
561 clock->m = i9xx_dpll_compute_m(clock);
562 clock->p = clock->p1 * clock->p2;
563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
567 }
568
569 static void chv_clock(int refclk, intel_clock_t *clock)
570 {
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578 }
579
580 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
581 /**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
586 static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
589 {
590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
593 INTELPllInvalid("p1 out of range\n");
594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
595 INTELPllInvalid("m2 out of range\n");
596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
597 INTELPllInvalid("m1 out of range\n");
598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
616 INTELPllInvalid("dot out of range\n");
617
618 return true;
619 }
620
621 static bool
622 i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
626 {
627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
628 struct drm_device *dev = crtc->base.dev;
629 intel_clock_t clock;
630 int err = target;
631
632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
633 /*
634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
637 */
638 if (intel_is_dual_link_lvds(dev))
639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
649 memset(best_clock, 0, sizeof(*best_clock));
650
651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
655 if (clock.m2 >= clock.m1)
656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
661 int this_err;
662
663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682 }
683
684 static bool
685 pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
689 {
690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
691 struct drm_device *dev = crtc->base.dev;
692 intel_clock_t clock;
693 int err = target;
694
695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
696 /*
697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
700 */
701 if (intel_is_dual_link_lvds(dev))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
722 int this_err;
723
724 pineview_clock(refclk, &clock);
725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
727 continue;
728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743 }
744
745 static bool
746 g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
750 {
751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
752 struct drm_device *dev = crtc->base.dev;
753 intel_clock_t clock;
754 int max_n;
755 bool found;
756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
758 found = false;
759
760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
761 if (intel_is_dual_link_lvds(dev))
762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
774 /* based on hardware requirement, prefer smaller n to precision */
775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
776 /* based on hardware requirement, prefere larger m1,m2 */
777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
785 i9xx_clock(refclk, &clock);
786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
788 continue;
789
790 this_err = abs(clock.dot - target);
791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
801 return found;
802 }
803
804 /*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813 {
814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842 }
843
844 static bool
845 vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
849 {
850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
851 struct drm_device *dev = crtc->base.dev;
852 intel_clock_t clock;
853 unsigned int bestppm = 1000000;
854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
856 bool found = false;
857
858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
861
862 /* based on hardware requirement, prefer smaller n to precision */
863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
867 clock.p = clock.p1 * clock.p2;
868 /* based on hardware requirement, prefer bigger m1,m2 values */
869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
870 unsigned int ppm;
871
872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
876
877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
879 continue;
880
881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
886
887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
890 }
891 }
892 }
893 }
894
895 return found;
896 }
897
898 static bool
899 chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903 {
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
905 struct drm_device *dev = crtc->base.dev;
906 unsigned int best_error_ppm;
907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
912 best_error_ppm = 1000000;
913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
926 unsigned int error_ppm;
927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
950 }
951 }
952
953 return found;
954 }
955
956 bool intel_crtc_active(struct drm_crtc *crtc)
957 {
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
963 * We can ditch the adjusted_mode.crtc_clock check as soon
964 * as Haswell has gained clock readout/fastboot support.
965 *
966 * We can ditch the crtc->primary->fb check as soon as we can
967 * properly reconstruct framebuffers.
968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
972 */
973 return intel_crtc->active && crtc->primary->state->fb &&
974 intel_crtc->config->base.adjusted_mode.crtc_clock;
975 }
976
977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979 {
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
983 return intel_crtc->config->cpu_transcoder;
984 }
985
986 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987 {
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003 }
1004
1005 /*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
1007 * @crtc: crtc whose pipe to wait for
1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
1019 *
1020 */
1021 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1022 {
1023 struct drm_device *dev = crtc->base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1026 enum pipe pipe = crtc->pipe;
1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
1029 int reg = PIPECONF(cpu_transcoder);
1030
1031 /* Wait for the Pipe State to go off */
1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
1034 WARN(1, "pipe_off wait timed out\n");
1035 } else {
1036 /* Wait for the display line to settle */
1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1038 WARN(1, "pipe_off wait timed out\n");
1039 }
1040 }
1041
1042 /*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051 {
1052 u32 bit;
1053
1054 if (HAS_PCH_IBX(dev_priv->dev)) {
1055 switch (port->port) {
1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
1069 switch (port->port) {
1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085 }
1086
1087 static const char *state_string(bool enabled)
1088 {
1089 return enabled ? "on" : "off";
1090 }
1091
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
1095 {
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
1103 I915_STATE_WARN(cur_state != state,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106 }
1107
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110 {
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
1119 I915_STATE_WARN(cur_state != state,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122 }
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
1126 struct intel_shared_dpll *
1127 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128 {
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
1131 if (crtc->config->shared_dpll < 0)
1132 return NULL;
1133
1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1135 }
1136
1137 /* For ILK+ */
1138 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
1141 {
1142 bool cur_state;
1143 struct intel_dpll_hw_state hw_state;
1144
1145 if (WARN (!pll,
1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
1147 return;
1148
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1150 I915_STATE_WARN(cur_state != state,
1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
1153 }
1154
1155 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157 {
1158 int reg;
1159 u32 val;
1160 bool cur_state;
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
1163
1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1167 val = I915_READ(reg);
1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
1174 I915_STATE_WARN(cur_state != state,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177 }
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183 {
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
1191 I915_STATE_WARN(cur_state != state,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194 }
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200 {
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1206 return;
1207
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv->dev))
1210 return;
1211
1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 int reg;
1221 u32 val;
1222 bool cur_state;
1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1227 I915_STATE_WARN(cur_state != state,
1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
1230 }
1231
1232 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234 {
1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
1239 bool locked = true;
1240
1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
1247 pp_reg = PCH_PP_CONTROL;
1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
1258 } else {
1259 pp_reg = PP_CONTROL;
1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1267 locked = false;
1268
1269 I915_STATE_WARN(panel_pipe == pipe && locked,
1270 "panel assertion failure, pipe %c regs locked\n",
1271 pipe_name(pipe));
1272 }
1273
1274 static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276 {
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
1280 if (IS_845G(dev) || IS_I865G(dev))
1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1282 else
1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1284
1285 I915_STATE_WARN(cur_state != state,
1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288 }
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
1292 void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
1294 {
1295 int reg;
1296 u32 val;
1297 bool cur_state;
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
1300
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1304 state = true;
1305
1306 if (!intel_display_power_is_enabled(dev_priv,
1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
1315 I915_STATE_WARN(cur_state != state,
1316 "pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe), state_string(state), state_string(cur_state));
1318 }
1319
1320 static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
1322 {
1323 int reg;
1324 u32 val;
1325 bool cur_state;
1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1330 I915_STATE_WARN(cur_state != state,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
1333 }
1334
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340 {
1341 struct drm_device *dev = dev_priv->dev;
1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
1353 return;
1354 }
1355
1356 /* Need to check both planes against the pipe */
1357 for_each_pipe(dev_priv, i) {
1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
1365 }
1366 }
1367
1368 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370 {
1371 struct drm_device *dev = dev_priv->dev;
1372 int reg, sprite;
1373 u32 val;
1374
1375 if (INTEL_INFO(dev)->gen >= 9) {
1376 for_each_sprite(dev_priv, pipe, sprite) {
1377 val = I915_READ(PLANE_CTL(pipe, sprite));
1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
1383 for_each_sprite(dev_priv, pipe, sprite) {
1384 reg = SPCNTR(pipe, sprite);
1385 val = I915_READ(reg);
1386 I915_STATE_WARN(val & SP_ENABLE,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 sprite_name(pipe, sprite), pipe_name(pipe));
1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
1392 val = I915_READ(reg);
1393 I915_STATE_WARN(val & SPRITE_ENABLE,
1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
1398 val = I915_READ(reg);
1399 I915_STATE_WARN(val & DVS_ENABLE,
1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401 plane_name(pipe), pipe_name(pipe));
1402 }
1403 }
1404
1405 static void assert_vblank_disabled(struct drm_crtc *crtc)
1406 {
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1408 drm_crtc_vblank_put(crtc);
1409 }
1410
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1412 {
1413 u32 val;
1414 bool enabled;
1415
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1417
1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1422 }
1423
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
1426 {
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
1431 reg = PCH_TRANSCONF(pipe);
1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
1434 I915_STATE_WARN(enabled,
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
1437 }
1438
1439 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
1441 {
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458 }
1459
1460 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462 {
1463 if ((val & SDVO_ENABLE) == 0)
1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1468 return false;
1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1472 } else {
1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1474 return false;
1475 }
1476 return true;
1477 }
1478
1479 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481 {
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493 }
1494
1495 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497 {
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508 }
1509
1510 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1511 enum pipe pipe, int reg, u32 port_sel)
1512 {
1513 u32 val = I915_READ(reg);
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516 reg, pipe_name(pipe));
1517
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1519 && (val & DP_PIPEB_SELECT),
1520 "IBX PCH dp port still using transcoder B\n");
1521 }
1522
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525 {
1526 u32 val = I915_READ(reg);
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529 reg, pipe_name(pipe));
1530
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1532 && (val & SDVO_PIPE_B_SELECT),
1533 "IBX PCH hdmi port still using transcoder B\n");
1534 }
1535
1536 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538 {
1539 int reg;
1540 u32 val;
1541
1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
1550 pipe_name(pipe));
1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1556 pipe_name(pipe));
1557
1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1561 }
1562
1563 static void intel_init_dpio(struct drm_device *dev)
1564 {
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
1581 }
1582
1583 static void vlv_enable_pll(struct intel_crtc *crtc,
1584 const struct intel_crtc_state *pipe_config)
1585 {
1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
1590
1591 assert_pipe_disabled(dev_priv, crtc->pipe);
1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
1597 if (IS_MOBILE(dev_priv->dev))
1598 assert_panel_unlocked(dev_priv, crtc->pipe);
1599
1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1608 POSTING_READ(DPLL_MD(crtc->pipe));
1609
1610 /* We do this three times for luck */
1611 I915_WRITE(reg, dpll);
1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
1617 I915_WRITE(reg, dpll);
1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620 }
1621
1622 static void chv_enable_pll(struct intel_crtc *crtc,
1623 const struct intel_crtc_state *pipe_config)
1624 {
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1649
1650 /* Check PLL is locked */
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
1654 /* not sure when this should be written */
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1656 POSTING_READ(DPLL_MD(pipe));
1657
1658 mutex_unlock(&dev_priv->dpio_lock);
1659 }
1660
1661 static int intel_num_dvo_pipes(struct drm_device *dev)
1662 {
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1669
1670 return count;
1671 }
1672
1673 static void i9xx_enable_pll(struct intel_crtc *crtc)
1674 {
1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
1679
1680 assert_pipe_disabled(dev_priv, crtc->pipe);
1681
1682 /* No really, not for ILK+ */
1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1684
1685 /* PLL is protected by panel, make sure we can write it */
1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
1688
1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
1708 crtc->config->dpll_hw_state.dpll_md);
1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
1717
1718 /* We do this three times for luck */
1719 I915_WRITE(reg, dpll);
1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg, dpll);
1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
1725 I915_WRITE(reg, dpll);
1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728 }
1729
1730 /**
1731 * i9xx_disable_pll - disable a PLL
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1739 static void i9xx_disable_pll(struct intel_crtc *crtc)
1740 {
1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
1765 }
1766
1767 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768 {
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
1778 if (pipe == PIPE_B)
1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
1782
1783 }
1784
1785 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786 {
1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1788 u32 val;
1789
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
1792
1793 /* Set PLL en = 0 */
1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
1818 mutex_unlock(&dev_priv->dpio_lock);
1819 }
1820
1821 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
1823 {
1824 u32 port_mask;
1825 int dpll_reg;
1826
1827 switch (dport->port) {
1828 case PORT_B:
1829 port_mask = DPLL_PORTB_READY_MASK;
1830 dpll_reg = DPLL(0);
1831 break;
1832 case PORT_C:
1833 port_mask = DPLL_PORTC_READY_MASK;
1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
1839 break;
1840 default:
1841 BUG();
1842 }
1843
1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846 port_name(dport->port), I915_READ(dpll_reg));
1847 }
1848
1849 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850 {
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
1855 if (WARN_ON(pll == NULL))
1856 return;
1857
1858 WARN_ON(!pll->config.crtc_mask);
1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866 }
1867
1868 /**
1869 * intel_enable_shared_dpll - enable PCH PLL
1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
1876 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 if (WARN_ON(pll->config.crtc_mask == 0))
1886 return;
1887
1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889 pll->name, pll->active, pll->on,
1890 crtc->base.base.id);
1891
1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
1894 assert_shared_dpll_enabled(dev_priv, pll);
1895 return;
1896 }
1897 WARN_ON(pll->on);
1898
1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1902 pll->enable(dev_priv, pll);
1903 pll->on = true;
1904 }
1905
1906 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1907 {
1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1911
1912 /* PCH only available on ILK+ */
1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
1914 if (WARN_ON(pll == NULL))
1915 return;
1916
1917 if (WARN_ON(pll->config.crtc_mask == 0))
1918 return;
1919
1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
1922 crtc->base.base.id);
1923
1924 if (WARN_ON(pll->active == 0)) {
1925 assert_shared_dpll_disabled(dev_priv, pll);
1926 return;
1927 }
1928
1929 assert_shared_dpll_enabled(dev_priv, pll);
1930 WARN_ON(!pll->on);
1931 if (--pll->active)
1932 return;
1933
1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1935 pll->disable(dev_priv, pll);
1936 pll->on = false;
1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1939 }
1940
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
1943 {
1944 struct drm_device *dev = dev_priv->dev;
1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1947 uint32_t reg, val, pipeconf_val;
1948
1949 /* PCH only available on ILK+ */
1950 BUG_ON(!HAS_PCH_SPLIT(dev));
1951
1952 /* Make sure PCH DPLL is enabled */
1953 assert_shared_dpll_enabled(dev_priv,
1954 intel_crtc_to_shared_dpll(intel_crtc));
1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
1967 }
1968
1969 reg = PCH_TRANSCONF(pipe);
1970 val = I915_READ(reg);
1971 pipeconf_val = I915_READ(PIPECONF(pipe));
1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
1980 }
1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1984 if (HAS_PCH_IBX(dev_priv->dev) &&
1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1995 }
1996
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1998 enum transcoder cpu_transcoder)
1999 {
2000 u32 val, pipeconf_val;
2001
2002 /* PCH only available on ILK+ */
2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2004
2005 /* FDI must be feeding us bits for PCH ports */
2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2008
2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
2014 val = TRANS_ENABLE;
2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2016
2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("Failed to enable PCH transcoder\n");
2026 }
2027
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
2030 {
2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
2041 reg = PCH_TRANSCONF(pipe);
2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
2056 }
2057
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2059 {
2060 u32 val;
2061
2062 val = I915_READ(LPT_TRANSCONF);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(LPT_TRANSCONF, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2067 DRM_ERROR("Failed to disable PCH transcoder\n");
2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2072 I915_WRITE(_TRANSA_CHICKEN2, val);
2073 }
2074
2075 /**
2076 * intel_enable_pipe - enable a pipe, asserting requirements
2077 * @crtc: crtc responsible for the pipe
2078 *
2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2081 */
2082 static void intel_enable_pipe(struct intel_crtc *crtc)
2083 {
2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
2089 enum pipe pch_transcoder;
2090 int reg;
2091 u32 val;
2092
2093 assert_planes_disabled(dev_priv, pipe);
2094 assert_cursor_disabled(dev_priv, pipe);
2095 assert_sprites_disabled(dev_priv, pipe);
2096
2097 if (HAS_PCH_LPT(dev_priv->dev))
2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
2112 else {
2113 if (crtc->config->has_pch_encoder) {
2114 /* if driving the PCH, we need FDI enabled */
2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
2121
2122 reg = PIPECONF(cpu_transcoder);
2123 val = I915_READ(reg);
2124 if (val & PIPECONF_ENABLE) {
2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2127 return;
2128 }
2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
2131 POSTING_READ(reg);
2132 }
2133
2134 /**
2135 * intel_disable_pipe - disable a pipe, asserting requirements
2136 * @crtc: crtc whose pipes is to be disabled
2137 *
2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
2144 static void intel_disable_pipe(struct intel_crtc *crtc)
2145 {
2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2148 enum pipe pipe = crtc->pipe;
2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
2157 assert_cursor_disabled(dev_priv, pipe);
2158 assert_sprites_disabled(dev_priv, pipe);
2159
2160 reg = PIPECONF(cpu_transcoder);
2161 val = I915_READ(reg);
2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
2169 if (crtc->config->double_wide)
2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
2180 }
2181
2182 /*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
2186 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
2188 {
2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
2194 }
2195
2196 /**
2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
2200 *
2201 * Enable @plane on @crtc, making sure that the pipe is running first.
2202 */
2203 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
2205 {
2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2212
2213 if (intel_crtc->primary_enabled)
2214 return;
2215
2216 intel_crtc->primary_enabled = true;
2217
2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
2228 }
2229
2230 /**
2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
2234 *
2235 * Disable @plane on @crtc, making sure that the pipe is running first.
2236 */
2237 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
2239 {
2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
2244 if (WARN_ON(!intel_crtc->active))
2245 return;
2246
2247 if (!intel_crtc->primary_enabled)
2248 return;
2249
2250 intel_crtc->primary_enabled = false;
2251
2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
2254 }
2255
2256 static bool need_vtd_wa(struct drm_device *dev)
2257 {
2258 #ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261 #endif
2262 return false;
2263 }
2264
2265 unsigned int
2266 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
2268 {
2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
2271
2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
2285 default:
2286 case 1:
2287 tile_height = 64;
2288 break;
2289 case 2:
2290 case 4:
2291 tile_height = 32;
2292 break;
2293 case 8:
2294 tile_height = 16;
2295 break;
2296 case 16:
2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
2308
2309 return tile_height;
2310 }
2311
2312 unsigned int
2313 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315 {
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
2318 }
2319
2320 static int
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323 {
2324 struct intel_rotation_info *info = &view->rotation_info;
2325
2326 *view = i915_ggtt_view_normal;
2327
2328 if (!plane_state)
2329 return 0;
2330
2331 if (!intel_rotation_90_or_270(plane_state->rotation))
2332 return 0;
2333
2334 *view = i915_ggtt_view_rotated;
2335
2336 info->height = fb->height;
2337 info->pixel_format = fb->pixel_format;
2338 info->pitch = fb->pitches[0];
2339 info->fb_modifier = fb->modifier[0];
2340
2341 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2342 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2343 DRM_DEBUG_KMS(
2344 "Y or Yf tiling is needed for 90/270 rotation!\n");
2345 return -EINVAL;
2346 }
2347
2348 return 0;
2349 }
2350
2351 int
2352 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2353 struct drm_framebuffer *fb,
2354 const struct drm_plane_state *plane_state,
2355 struct intel_engine_cs *pipelined)
2356 {
2357 struct drm_device *dev = fb->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2360 struct i915_ggtt_view view;
2361 u32 alignment;
2362 int ret;
2363
2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
2368 if (INTEL_INFO(dev)->gen >= 9)
2369 alignment = 256 * 1024;
2370 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2371 alignment = 128 * 1024;
2372 else if (INTEL_INFO(dev)->gen >= 4)
2373 alignment = 4 * 1024;
2374 else
2375 alignment = 64 * 1024;
2376 break;
2377 case I915_FORMAT_MOD_X_TILED:
2378 if (INTEL_INFO(dev)->gen >= 9)
2379 alignment = 256 * 1024;
2380 else {
2381 /* pin() will align the object as required by fence */
2382 alignment = 0;
2383 }
2384 break;
2385 case I915_FORMAT_MOD_Y_TILED:
2386 case I915_FORMAT_MOD_Yf_TILED:
2387 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2388 "Y tiling bo slipped through, driver bug!\n"))
2389 return -EINVAL;
2390 alignment = 1 * 1024 * 1024;
2391 break;
2392 default:
2393 MISSING_CASE(fb->modifier[0]);
2394 return -EINVAL;
2395 }
2396
2397 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2398 if (ret)
2399 return ret;
2400
2401 /* Note that the w/a also requires 64 PTE of padding following the
2402 * bo. We currently fill all unused PTE with the shadow page and so
2403 * we should always have valid PTE following the scanout preventing
2404 * the VT-d warning.
2405 */
2406 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2407 alignment = 256 * 1024;
2408
2409 /*
2410 * Global gtt pte registers are special registers which actually forward
2411 * writes to a chunk of system memory. Which means that there is no risk
2412 * that the register values disappear as soon as we call
2413 * intel_runtime_pm_put(), so it is correct to wrap only the
2414 * pin/unpin/fence and not more.
2415 */
2416 intel_runtime_pm_get(dev_priv);
2417
2418 dev_priv->mm.interruptible = false;
2419 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2420 &view);
2421 if (ret)
2422 goto err_interruptible;
2423
2424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425 * fence, whereas 965+ only requires a fence if using
2426 * framebuffer compression. For simplicity, we always install
2427 * a fence as the cost is not that onerous.
2428 */
2429 ret = i915_gem_object_get_fence(obj);
2430 if (ret)
2431 goto err_unpin;
2432
2433 i915_gem_object_pin_fence(obj);
2434
2435 dev_priv->mm.interruptible = true;
2436 intel_runtime_pm_put(dev_priv);
2437 return 0;
2438
2439 err_unpin:
2440 i915_gem_object_unpin_from_display_plane(obj, &view);
2441 err_interruptible:
2442 dev_priv->mm.interruptible = true;
2443 intel_runtime_pm_put(dev_priv);
2444 return ret;
2445 }
2446
2447 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2448 const struct drm_plane_state *plane_state)
2449 {
2450 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2451 struct i915_ggtt_view view;
2452 int ret;
2453
2454 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2455
2456 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2457 WARN_ONCE(ret, "Couldn't get view from plane state!");
2458
2459 i915_gem_object_unpin_fence(obj);
2460 i915_gem_object_unpin_from_display_plane(obj, &view);
2461 }
2462
2463 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464 * is assumed to be a power-of-two. */
2465 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2466 unsigned int tiling_mode,
2467 unsigned int cpp,
2468 unsigned int pitch)
2469 {
2470 if (tiling_mode != I915_TILING_NONE) {
2471 unsigned int tile_rows, tiles;
2472
2473 tile_rows = *y / 8;
2474 *y %= 8;
2475
2476 tiles = *x / (512/cpp);
2477 *x %= 512/cpp;
2478
2479 return tile_rows * pitch * 8 + tiles * 4096;
2480 } else {
2481 unsigned int offset;
2482
2483 offset = *y * pitch + *x * cpp;
2484 *y = 0;
2485 *x = (offset & 4095) / cpp;
2486 return offset & -4096;
2487 }
2488 }
2489
2490 static int i9xx_format_to_fourcc(int format)
2491 {
2492 switch (format) {
2493 case DISPPLANE_8BPP:
2494 return DRM_FORMAT_C8;
2495 case DISPPLANE_BGRX555:
2496 return DRM_FORMAT_XRGB1555;
2497 case DISPPLANE_BGRX565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case DISPPLANE_BGRX888:
2501 return DRM_FORMAT_XRGB8888;
2502 case DISPPLANE_RGBX888:
2503 return DRM_FORMAT_XBGR8888;
2504 case DISPPLANE_BGRX101010:
2505 return DRM_FORMAT_XRGB2101010;
2506 case DISPPLANE_RGBX101010:
2507 return DRM_FORMAT_XBGR2101010;
2508 }
2509 }
2510
2511 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2512 {
2513 switch (format) {
2514 case PLANE_CTL_FORMAT_RGB_565:
2515 return DRM_FORMAT_RGB565;
2516 default:
2517 case PLANE_CTL_FORMAT_XRGB_8888:
2518 if (rgb_order) {
2519 if (alpha)
2520 return DRM_FORMAT_ABGR8888;
2521 else
2522 return DRM_FORMAT_XBGR8888;
2523 } else {
2524 if (alpha)
2525 return DRM_FORMAT_ARGB8888;
2526 else
2527 return DRM_FORMAT_XRGB8888;
2528 }
2529 case PLANE_CTL_FORMAT_XRGB_2101010:
2530 if (rgb_order)
2531 return DRM_FORMAT_XBGR2101010;
2532 else
2533 return DRM_FORMAT_XRGB2101010;
2534 }
2535 }
2536
2537 static bool
2538 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2539 struct intel_initial_plane_config *plane_config)
2540 {
2541 struct drm_device *dev = crtc->base.dev;
2542 struct drm_i915_gem_object *obj = NULL;
2543 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2544 struct drm_framebuffer *fb = &plane_config->fb->base;
2545 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2546 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2547 PAGE_SIZE);
2548
2549 size_aligned -= base_aligned;
2550
2551 if (plane_config->size == 0)
2552 return false;
2553
2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
2558 if (!obj)
2559 return false;
2560
2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
2563 obj->stride = fb->pitches[0];
2564
2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572 mutex_lock(&dev->struct_mutex);
2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574 &mode_cmd, obj)) {
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
2578 mutex_unlock(&dev->struct_mutex);
2579
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581 return true;
2582
2583 out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
2586 return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
2606 {
2607 struct drm_device *dev = intel_crtc->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2611 struct drm_i915_gem_object *obj;
2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_framebuffer *fb;
2614
2615 if (!plane_config->fb)
2616 return;
2617
2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2619 fb = &plane_config->fb->base;
2620 goto valid_fb;
2621 }
2622
2623 kfree(plane_config->fb);
2624
2625 /*
2626 * Failed to alloc the obj, check to see if we should share
2627 * an fb with another CRTC instead
2628 */
2629 for_each_crtc(dev, c) {
2630 i = to_intel_crtc(c);
2631
2632 if (c == &intel_crtc->base)
2633 continue;
2634
2635 if (!i->active)
2636 continue;
2637
2638 fb = c->primary->fb;
2639 if (!fb)
2640 continue;
2641
2642 obj = intel_fb_obj(fb);
2643 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2644 drm_framebuffer_reference(fb);
2645 goto valid_fb;
2646 }
2647 }
2648
2649 return;
2650
2651 valid_fb:
2652 obj = intel_fb_obj(fb);
2653 if (obj->tiling_mode != I915_TILING_NONE)
2654 dev_priv->preserve_bios_swizzle = true;
2655
2656 primary->fb = fb;
2657 primary->state->crtc = &intel_crtc->base;
2658 primary->crtc = &intel_crtc->base;
2659 update_state_fb(primary);
2660 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2661 }
2662
2663 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2664 struct drm_framebuffer *fb,
2665 int x, int y)
2666 {
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2670 struct drm_i915_gem_object *obj;
2671 int plane = intel_crtc->plane;
2672 unsigned long linear_offset;
2673 u32 dspcntr;
2674 u32 reg = DSPCNTR(plane);
2675 int pixel_size;
2676
2677 if (!intel_crtc->primary_enabled) {
2678 I915_WRITE(reg, 0);
2679 if (INTEL_INFO(dev)->gen >= 4)
2680 I915_WRITE(DSPSURF(plane), 0);
2681 else
2682 I915_WRITE(DSPADDR(plane), 0);
2683 POSTING_READ(reg);
2684 return;
2685 }
2686
2687 obj = intel_fb_obj(fb);
2688 if (WARN_ON(obj == NULL))
2689 return;
2690
2691 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2692
2693 dspcntr = DISPPLANE_GAMMA_ENABLE;
2694
2695 dspcntr |= DISPLAY_PLANE_ENABLE;
2696
2697 if (INTEL_INFO(dev)->gen < 4) {
2698 if (intel_crtc->pipe == PIPE_B)
2699 dspcntr |= DISPPLANE_SEL_PIPE_B;
2700
2701 /* pipesrc and dspsize control the size that is scaled from,
2702 * which should always be the user's requested size.
2703 */
2704 I915_WRITE(DSPSIZE(plane),
2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
2707 I915_WRITE(DSPPOS(plane), 0);
2708 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2709 I915_WRITE(PRIMSIZE(plane),
2710 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2711 (intel_crtc->config->pipe_src_w - 1));
2712 I915_WRITE(PRIMPOS(plane), 0);
2713 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2714 }
2715
2716 switch (fb->pixel_format) {
2717 case DRM_FORMAT_C8:
2718 dspcntr |= DISPPLANE_8BPP;
2719 break;
2720 case DRM_FORMAT_XRGB1555:
2721 case DRM_FORMAT_ARGB1555:
2722 dspcntr |= DISPPLANE_BGRX555;
2723 break;
2724 case DRM_FORMAT_RGB565:
2725 dspcntr |= DISPPLANE_BGRX565;
2726 break;
2727 case DRM_FORMAT_XRGB8888:
2728 case DRM_FORMAT_ARGB8888:
2729 dspcntr |= DISPPLANE_BGRX888;
2730 break;
2731 case DRM_FORMAT_XBGR8888:
2732 case DRM_FORMAT_ABGR8888:
2733 dspcntr |= DISPPLANE_RGBX888;
2734 break;
2735 case DRM_FORMAT_XRGB2101010:
2736 case DRM_FORMAT_ARGB2101010:
2737 dspcntr |= DISPPLANE_BGRX101010;
2738 break;
2739 case DRM_FORMAT_XBGR2101010:
2740 case DRM_FORMAT_ABGR2101010:
2741 dspcntr |= DISPPLANE_RGBX101010;
2742 break;
2743 default:
2744 BUG();
2745 }
2746
2747 if (INTEL_INFO(dev)->gen >= 4 &&
2748 obj->tiling_mode != I915_TILING_NONE)
2749 dspcntr |= DISPPLANE_TILED;
2750
2751 if (IS_G4X(dev))
2752 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2753
2754 linear_offset = y * fb->pitches[0] + x * pixel_size;
2755
2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 intel_crtc->dspaddr_offset =
2758 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2759 pixel_size,
2760 fb->pitches[0]);
2761 linear_offset -= intel_crtc->dspaddr_offset;
2762 } else {
2763 intel_crtc->dspaddr_offset = linear_offset;
2764 }
2765
2766 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2767 dspcntr |= DISPPLANE_ROTATE_180;
2768
2769 x += (intel_crtc->config->pipe_src_w - 1);
2770 y += (intel_crtc->config->pipe_src_h - 1);
2771
2772 /* Finding the last pixel of the last line of the display
2773 data and adding to linear_offset*/
2774 linear_offset +=
2775 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2776 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2777 }
2778
2779 I915_WRITE(reg, dspcntr);
2780
2781 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2782 if (INTEL_INFO(dev)->gen >= 4) {
2783 I915_WRITE(DSPSURF(plane),
2784 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2785 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2786 I915_WRITE(DSPLINOFF(plane), linear_offset);
2787 } else
2788 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2789 POSTING_READ(reg);
2790 }
2791
2792 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793 struct drm_framebuffer *fb,
2794 int x, int y)
2795 {
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2799 struct drm_i915_gem_object *obj;
2800 int plane = intel_crtc->plane;
2801 unsigned long linear_offset;
2802 u32 dspcntr;
2803 u32 reg = DSPCNTR(plane);
2804 int pixel_size;
2805
2806 if (!intel_crtc->primary_enabled) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821 dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
2832 break;
2833 case DRM_FORMAT_XRGB8888:
2834 case DRM_FORMAT_ARGB8888:
2835 dspcntr |= DISPPLANE_BGRX888;
2836 break;
2837 case DRM_FORMAT_XBGR8888:
2838 case DRM_FORMAT_ABGR8888:
2839 dspcntr |= DISPPLANE_RGBX888;
2840 break;
2841 case DRM_FORMAT_XRGB2101010:
2842 case DRM_FORMAT_ARGB2101010:
2843 dspcntr |= DISPPLANE_BGRX101010;
2844 break;
2845 case DRM_FORMAT_XBGR2101010:
2846 case DRM_FORMAT_ABGR2101010:
2847 dspcntr |= DISPPLANE_RGBX101010;
2848 break;
2849 default:
2850 BUG();
2851 }
2852
2853 if (obj->tiling_mode != I915_TILING_NONE)
2854 dspcntr |= DISPPLANE_TILED;
2855
2856 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2857 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2858
2859 linear_offset = y * fb->pitches[0] + x * pixel_size;
2860 intel_crtc->dspaddr_offset =
2861 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2862 pixel_size,
2863 fb->pitches[0]);
2864 linear_offset -= intel_crtc->dspaddr_offset;
2865 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2866 dspcntr |= DISPPLANE_ROTATE_180;
2867
2868 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2869 x += (intel_crtc->config->pipe_src_w - 1);
2870 y += (intel_crtc->config->pipe_src_h - 1);
2871
2872 /* Finding the last pixel of the last line of the display
2873 data and adding to linear_offset*/
2874 linear_offset +=
2875 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2876 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2877 }
2878 }
2879
2880 I915_WRITE(reg, dspcntr);
2881
2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
2891 POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896 {
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926 }
2927
2928 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj)
2930 {
2931 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2932
2933 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2934 view = &i915_ggtt_view_rotated;
2935
2936 return i915_gem_obj_ggtt_offset_view(obj, view);
2937 }
2938
2939 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2940 struct drm_framebuffer *fb,
2941 int x, int y)
2942 {
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2946 struct drm_i915_gem_object *obj;
2947 int pipe = intel_crtc->pipe;
2948 u32 plane_ctl, stride_div;
2949 unsigned long surf_addr;
2950
2951 if (!intel_crtc->primary_enabled) {
2952 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2953 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2954 POSTING_READ(PLANE_CTL(pipe, 0));
2955 return;
2956 }
2957
2958 plane_ctl = PLANE_CTL_ENABLE |
2959 PLANE_CTL_PIPE_GAMMA_ENABLE |
2960 PLANE_CTL_PIPE_CSC_ENABLE;
2961
2962 switch (fb->pixel_format) {
2963 case DRM_FORMAT_RGB565:
2964 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2965 break;
2966 case DRM_FORMAT_XRGB8888:
2967 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2968 break;
2969 case DRM_FORMAT_ARGB8888:
2970 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2971 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972 break;
2973 case DRM_FORMAT_XBGR8888:
2974 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2975 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2976 break;
2977 case DRM_FORMAT_ABGR8888:
2978 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2979 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2980 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981 break;
2982 case DRM_FORMAT_XRGB2101010:
2983 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_XBGR2101010:
2986 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2987 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2988 break;
2989 default:
2990 BUG();
2991 }
2992
2993 switch (fb->modifier[0]) {
2994 case DRM_FORMAT_MOD_NONE:
2995 break;
2996 case I915_FORMAT_MOD_X_TILED:
2997 plane_ctl |= PLANE_CTL_TILED_X;
2998 break;
2999 case I915_FORMAT_MOD_Y_TILED:
3000 plane_ctl |= PLANE_CTL_TILED_Y;
3001 break;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 plane_ctl |= PLANE_CTL_TILED_YF;
3004 break;
3005 default:
3006 MISSING_CASE(fb->modifier[0]);
3007 }
3008
3009 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3010 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
3011 plane_ctl |= PLANE_CTL_ROTATE_180;
3012
3013 obj = intel_fb_obj(fb);
3014 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3015 fb->pixel_format);
3016 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
3017
3018 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3019 I915_WRITE(PLANE_POS(pipe, 0), 0);
3020 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3021 I915_WRITE(PLANE_SIZE(pipe, 0),
3022 (intel_crtc->config->pipe_src_h - 1) << 16 |
3023 (intel_crtc->config->pipe_src_w - 1));
3024 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
3025 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3026
3027 POSTING_READ(PLANE_SURF(pipe, 0));
3028 }
3029
3030 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3031 static int
3032 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3033 int x, int y, enum mode_set_atomic state)
3034 {
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037
3038 if (dev_priv->display.disable_fbc)
3039 dev_priv->display.disable_fbc(dev);
3040
3041 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3042
3043 return 0;
3044 }
3045
3046 static void intel_complete_page_flips(struct drm_device *dev)
3047 {
3048 struct drm_crtc *crtc;
3049
3050 for_each_crtc(dev, crtc) {
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 enum plane plane = intel_crtc->plane;
3053
3054 intel_prepare_page_flip(dev, plane);
3055 intel_finish_page_flip_plane(dev, plane);
3056 }
3057 }
3058
3059 static void intel_update_primary_planes(struct drm_device *dev)
3060 {
3061 struct drm_i915_private *dev_priv = dev->dev_private;
3062 struct drm_crtc *crtc;
3063
3064 for_each_crtc(dev, crtc) {
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066
3067 drm_modeset_lock(&crtc->mutex, NULL);
3068 /*
3069 * FIXME: Once we have proper support for primary planes (and
3070 * disabling them without disabling the entire crtc) allow again
3071 * a NULL crtc->primary->fb.
3072 */
3073 if (intel_crtc->active && crtc->primary->fb)
3074 dev_priv->display.update_primary_plane(crtc,
3075 crtc->primary->fb,
3076 crtc->x,
3077 crtc->y);
3078 drm_modeset_unlock(&crtc->mutex);
3079 }
3080 }
3081
3082 void intel_prepare_reset(struct drm_device *dev)
3083 {
3084 struct drm_i915_private *dev_priv = to_i915(dev);
3085 struct intel_crtc *crtc;
3086
3087 /* no reset support for gen2 */
3088 if (IS_GEN2(dev))
3089 return;
3090
3091 /* reset doesn't touch the display */
3092 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3093 return;
3094
3095 drm_modeset_lock_all(dev);
3096
3097 /*
3098 * Disabling the crtcs gracefully seems nicer. Also the
3099 * g33 docs say we should at least disable all the planes.
3100 */
3101 for_each_intel_crtc(dev, crtc) {
3102 if (crtc->active)
3103 dev_priv->display.crtc_disable(&crtc->base);
3104 }
3105 }
3106
3107 void intel_finish_reset(struct drm_device *dev)
3108 {
3109 struct drm_i915_private *dev_priv = to_i915(dev);
3110
3111 /*
3112 * Flips in the rings will be nuked by the reset,
3113 * so complete all pending flips so that user space
3114 * will get its events and not get stuck.
3115 */
3116 intel_complete_page_flips(dev);
3117
3118 /* no reset support for gen2 */
3119 if (IS_GEN2(dev))
3120 return;
3121
3122 /* reset doesn't touch the display */
3123 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3124 /*
3125 * Flips in the rings have been nuked by the reset,
3126 * so update the base address of all primary
3127 * planes to the the last fb to make sure we're
3128 * showing the correct fb after a reset.
3129 */
3130 intel_update_primary_planes(dev);
3131 return;
3132 }
3133
3134 /*
3135 * The display has been reset as well,
3136 * so need a full re-initialization.
3137 */
3138 intel_runtime_pm_disable_interrupts(dev_priv);
3139 intel_runtime_pm_enable_interrupts(dev_priv);
3140
3141 intel_modeset_init_hw(dev);
3142
3143 spin_lock_irq(&dev_priv->irq_lock);
3144 if (dev_priv->display.hpd_irq_setup)
3145 dev_priv->display.hpd_irq_setup(dev);
3146 spin_unlock_irq(&dev_priv->irq_lock);
3147
3148 intel_modeset_setup_hw_state(dev, true);
3149
3150 intel_hpd_init(dev_priv);
3151
3152 drm_modeset_unlock_all(dev);
3153 }
3154
3155 static int
3156 intel_finish_fb(struct drm_framebuffer *old_fb)
3157 {
3158 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3159 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3160 bool was_interruptible = dev_priv->mm.interruptible;
3161 int ret;
3162
3163 /* Big Hammer, we also need to ensure that any pending
3164 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165 * current scanout is retired before unpinning the old
3166 * framebuffer.
3167 *
3168 * This should only fail upon a hung GPU, in which case we
3169 * can safely continue.
3170 */
3171 dev_priv->mm.interruptible = false;
3172 ret = i915_gem_object_finish_gpu(obj);
3173 dev_priv->mm.interruptible = was_interruptible;
3174
3175 return ret;
3176 }
3177
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179 {
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183 bool pending;
3184
3185 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3186 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3187 return false;
3188
3189 spin_lock_irq(&dev->event_lock);
3190 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3191 spin_unlock_irq(&dev->event_lock);
3192
3193 return pending;
3194 }
3195
3196 static void intel_update_pipe_size(struct intel_crtc *crtc)
3197 {
3198 struct drm_device *dev = crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 const struct drm_display_mode *adjusted_mode;
3201
3202 if (!i915.fastboot)
3203 return;
3204
3205 /*
3206 * Update pipe size and adjust fitter if needed: the reason for this is
3207 * that in compute_mode_changes we check the native mode (not the pfit
3208 * mode) to see if we can flip rather than do a full mode set. In the
3209 * fastboot case, we'll flip, but if we don't update the pipesrc and
3210 * pfit state, we'll end up with a big fb scanned out into the wrong
3211 * sized surface.
3212 *
3213 * To fix this properly, we need to hoist the checks up into
3214 * compute_mode_changes (or above), check the actual pfit state and
3215 * whether the platform allows pfit disable with pipe active, and only
3216 * then update the pipesrc and pfit state, even on the flip path.
3217 */
3218
3219 adjusted_mode = &crtc->config->base.adjusted_mode;
3220
3221 I915_WRITE(PIPESRC(crtc->pipe),
3222 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3223 (adjusted_mode->crtc_vdisplay - 1));
3224 if (!crtc->config->pch_pfit.enabled &&
3225 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3226 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3227 I915_WRITE(PF_CTL(crtc->pipe), 0);
3228 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3229 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3230 }
3231 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3232 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3233 }
3234
3235 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3236 {
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240 int pipe = intel_crtc->pipe;
3241 u32 reg, temp;
3242
3243 /* enable normal train */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 if (IS_IVYBRIDGE(dev)) {
3247 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3248 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3249 } else {
3250 temp &= ~FDI_LINK_TRAIN_NONE;
3251 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3252 }
3253 I915_WRITE(reg, temp);
3254
3255 reg = FDI_RX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 if (HAS_PCH_CPT(dev)) {
3258 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3259 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3260 } else {
3261 temp &= ~FDI_LINK_TRAIN_NONE;
3262 temp |= FDI_LINK_TRAIN_NONE;
3263 }
3264 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3265
3266 /* wait one idle pattern time */
3267 POSTING_READ(reg);
3268 udelay(1000);
3269
3270 /* IVB wants error correction enabled */
3271 if (IS_IVYBRIDGE(dev))
3272 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3273 FDI_FE_ERRC_ENABLE);
3274 }
3275
3276 /* The FDI link training functions for ILK/Ibexpeak. */
3277 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3278 {
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 int pipe = intel_crtc->pipe;
3283 u32 reg, temp, tries;
3284
3285 /* FDI needs bits from pipe first */
3286 assert_pipe_enabled(dev_priv, pipe);
3287
3288 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3289 for train result */
3290 reg = FDI_RX_IMR(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_RX_SYMBOL_LOCK;
3293 temp &= ~FDI_RX_BIT_LOCK;
3294 I915_WRITE(reg, temp);
3295 I915_READ(reg);
3296 udelay(150);
3297
3298 /* enable CPU FDI TX and PCH FDI RX */
3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
3301 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3302 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3303 temp &= ~FDI_LINK_TRAIN_NONE;
3304 temp |= FDI_LINK_TRAIN_PATTERN_1;
3305 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3306
3307 reg = FDI_RX_CTL(pipe);
3308 temp = I915_READ(reg);
3309 temp &= ~FDI_LINK_TRAIN_NONE;
3310 temp |= FDI_LINK_TRAIN_PATTERN_1;
3311 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3312
3313 POSTING_READ(reg);
3314 udelay(150);
3315
3316 /* Ironlake workaround, enable clock pointer after FDI enable*/
3317 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3318 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3319 FDI_RX_PHASE_SYNC_POINTER_EN);
3320
3321 reg = FDI_RX_IIR(pipe);
3322 for (tries = 0; tries < 5; tries++) {
3323 temp = I915_READ(reg);
3324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3325
3326 if ((temp & FDI_RX_BIT_LOCK)) {
3327 DRM_DEBUG_KMS("FDI train 1 done.\n");
3328 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3329 break;
3330 }
3331 }
3332 if (tries == 5)
3333 DRM_ERROR("FDI train 1 fail!\n");
3334
3335 /* Train 2 */
3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_2;
3340 I915_WRITE(reg, temp);
3341
3342 reg = FDI_RX_CTL(pipe);
3343 temp = I915_READ(reg);
3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_2;
3346 I915_WRITE(reg, temp);
3347
3348 POSTING_READ(reg);
3349 udelay(150);
3350
3351 reg = FDI_RX_IIR(pipe);
3352 for (tries = 0; tries < 5; tries++) {
3353 temp = I915_READ(reg);
3354 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3355
3356 if (temp & FDI_RX_SYMBOL_LOCK) {
3357 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3358 DRM_DEBUG_KMS("FDI train 2 done.\n");
3359 break;
3360 }
3361 }
3362 if (tries == 5)
3363 DRM_ERROR("FDI train 2 fail!\n");
3364
3365 DRM_DEBUG_KMS("FDI train done\n");
3366
3367 }
3368
3369 static const int snb_b_fdi_train_param[] = {
3370 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3371 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3373 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3374 };
3375
3376 /* The FDI link training functions for SNB/Cougarpoint. */
3377 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3378 {
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp, i, retry;
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392
3393 POSTING_READ(reg);
3394 udelay(150);
3395
3396 /* enable CPU FDI TX and PCH FDI RX */
3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
3403 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3404 /* SNB-B */
3405 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3407
3408 I915_WRITE(FDI_RX_MISC(pipe),
3409 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3410
3411 reg = FDI_RX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if (HAS_PCH_CPT(dev)) {
3414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3416 } else {
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 }
3420 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421
3422 POSTING_READ(reg);
3423 udelay(150);
3424
3425 for (i = 0; i < 4; i++) {
3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
3428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3429 temp |= snb_b_fdi_train_param[i];
3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
3433 udelay(500);
3434
3435 for (retry = 0; retry < 5; retry++) {
3436 reg = FDI_RX_IIR(pipe);
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439 if (temp & FDI_RX_BIT_LOCK) {
3440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 break;
3443 }
3444 udelay(50);
3445 }
3446 if (retry < 5)
3447 break;
3448 }
3449 if (i == 4)
3450 DRM_ERROR("FDI train 1 fail!\n");
3451
3452 /* Train 2 */
3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 if (IS_GEN6(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3459 /* SNB-B */
3460 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3461 }
3462 I915_WRITE(reg, temp);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 if (HAS_PCH_CPT(dev)) {
3467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3469 } else {
3470 temp &= ~FDI_LINK_TRAIN_NONE;
3471 temp |= FDI_LINK_TRAIN_PATTERN_2;
3472 }
3473 I915_WRITE(reg, temp);
3474
3475 POSTING_READ(reg);
3476 udelay(150);
3477
3478 for (i = 0; i < 4; i++) {
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3482 temp |= snb_b_fdi_train_param[i];
3483 I915_WRITE(reg, temp);
3484
3485 POSTING_READ(reg);
3486 udelay(500);
3487
3488 for (retry = 0; retry < 5; retry++) {
3489 reg = FDI_RX_IIR(pipe);
3490 temp = I915_READ(reg);
3491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492 if (temp & FDI_RX_SYMBOL_LOCK) {
3493 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3494 DRM_DEBUG_KMS("FDI train 2 done.\n");
3495 break;
3496 }
3497 udelay(50);
3498 }
3499 if (retry < 5)
3500 break;
3501 }
3502 if (i == 4)
3503 DRM_ERROR("FDI train 2 fail!\n");
3504
3505 DRM_DEBUG_KMS("FDI train done.\n");
3506 }
3507
3508 /* Manual link training for Ivy Bridge A0 parts */
3509 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3510 {
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 int pipe = intel_crtc->pipe;
3515 u32 reg, temp, i, j;
3516
3517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518 for train result */
3519 reg = FDI_RX_IMR(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_RX_SYMBOL_LOCK;
3522 temp &= ~FDI_RX_BIT_LOCK;
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(150);
3527
3528 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529 I915_READ(FDI_RX_IIR(pipe)));
3530
3531 /* Try each vswing and preemphasis setting twice before moving on */
3532 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3533 /* disable first in case we need to retry */
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3537 temp &= ~FDI_TX_ENABLE;
3538 I915_WRITE(reg, temp);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_AUTO;
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp &= ~FDI_RX_ENABLE;
3545 I915_WRITE(reg, temp);
3546
3547 /* enable CPU FDI TX and PCH FDI RX */
3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
3550 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3551 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3552 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554 temp |= snb_b_fdi_train_param[j/2];
3555 temp |= FDI_COMPOSITE_SYNC;
3556 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3557
3558 I915_WRITE(FDI_RX_MISC(pipe),
3559 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3560
3561 reg = FDI_RX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564 temp |= FDI_COMPOSITE_SYNC;
3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3566
3567 POSTING_READ(reg);
3568 udelay(1); /* should be 0.5us */
3569
3570 for (i = 0; i < 4; i++) {
3571 reg = FDI_RX_IIR(pipe);
3572 temp = I915_READ(reg);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3574
3575 if (temp & FDI_RX_BIT_LOCK ||
3576 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3578 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3579 i);
3580 break;
3581 }
3582 udelay(1); /* should be 0.5us */
3583 }
3584 if (i == 4) {
3585 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3586 continue;
3587 }
3588
3589 /* Train 2 */
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3594 I915_WRITE(reg, temp);
3595
3596 reg = FDI_RX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
3603 udelay(2); /* should be 1.5us */
3604
3605 for (i = 0; i < 4; i++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3609
3610 if (temp & FDI_RX_SYMBOL_LOCK ||
3611 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3612 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3614 i);
3615 goto train_done;
3616 }
3617 udelay(2); /* should be 1.5us */
3618 }
3619 if (i == 4)
3620 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3621 }
3622
3623 train_done:
3624 DRM_DEBUG_KMS("FDI train done.\n");
3625 }
3626
3627 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3628 {
3629 struct drm_device *dev = intel_crtc->base.dev;
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631 int pipe = intel_crtc->pipe;
3632 u32 reg, temp;
3633
3634
3635 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3639 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3640 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3641 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3642
3643 POSTING_READ(reg);
3644 udelay(200);
3645
3646 /* Switch from Rawclk to PCDclk */
3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp | FDI_PCDCLK);
3649
3650 POSTING_READ(reg);
3651 udelay(200);
3652
3653 /* Enable CPU FDI TX PLL, always on for Ironlake */
3654 reg = FDI_TX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3657 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3658
3659 POSTING_READ(reg);
3660 udelay(100);
3661 }
3662 }
3663
3664 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3665 {
3666 struct drm_device *dev = intel_crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 int pipe = intel_crtc->pipe;
3669 u32 reg, temp;
3670
3671 /* Switch from PCDclk to Rawclk */
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3675
3676 /* Disable CPU FDI TX PLL */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3680
3681 POSTING_READ(reg);
3682 udelay(100);
3683
3684 reg = FDI_RX_CTL(pipe);
3685 temp = I915_READ(reg);
3686 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3687
3688 /* Wait for the clocks to turn off. */
3689 POSTING_READ(reg);
3690 udelay(100);
3691 }
3692
3693 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3694 {
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 int pipe = intel_crtc->pipe;
3699 u32 reg, temp;
3700
3701 /* disable CPU FDI tx and PCH FDI rx */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3705 POSTING_READ(reg);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~(0x7 << 16);
3710 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3711 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(100);
3715
3716 /* Ironlake workaround, disable clock pointer after downing FDI */
3717 if (HAS_PCH_IBX(dev))
3718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3719
3720 /* still set train pattern 1 */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 temp &= ~FDI_LINK_TRAIN_NONE;
3724 temp |= FDI_LINK_TRAIN_PATTERN_1;
3725 I915_WRITE(reg, temp);
3726
3727 reg = FDI_RX_CTL(pipe);
3728 temp = I915_READ(reg);
3729 if (HAS_PCH_CPT(dev)) {
3730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3732 } else {
3733 temp &= ~FDI_LINK_TRAIN_NONE;
3734 temp |= FDI_LINK_TRAIN_PATTERN_1;
3735 }
3736 /* BPC in FDI rx is consistent with that in PIPECONF */
3737 temp &= ~(0x07 << 16);
3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3739 I915_WRITE(reg, temp);
3740
3741 POSTING_READ(reg);
3742 udelay(100);
3743 }
3744
3745 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3746 {
3747 struct intel_crtc *crtc;
3748
3749 /* Note that we don't need to be called with mode_config.lock here
3750 * as our list of CRTC objects is static for the lifetime of the
3751 * device and so cannot disappear as we iterate. Similarly, we can
3752 * happily treat the predicates as racy, atomic checks as userspace
3753 * cannot claim and pin a new fb without at least acquring the
3754 * struct_mutex and so serialising with us.
3755 */
3756 for_each_intel_crtc(dev, crtc) {
3757 if (atomic_read(&crtc->unpin_work_count) == 0)
3758 continue;
3759
3760 if (crtc->unpin_work)
3761 intel_wait_for_vblank(dev, crtc->pipe);
3762
3763 return true;
3764 }
3765
3766 return false;
3767 }
3768
3769 static void page_flip_completed(struct intel_crtc *intel_crtc)
3770 {
3771 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3772 struct intel_unpin_work *work = intel_crtc->unpin_work;
3773
3774 /* ensure that the unpin work is consistent wrt ->pending. */
3775 smp_rmb();
3776 intel_crtc->unpin_work = NULL;
3777
3778 if (work->event)
3779 drm_send_vblank_event(intel_crtc->base.dev,
3780 intel_crtc->pipe,
3781 work->event);
3782
3783 drm_crtc_vblank_put(&intel_crtc->base);
3784
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 queue_work(dev_priv->wq, &work->work);
3787
3788 trace_i915_flip_complete(intel_crtc->plane,
3789 work->pending_flip_obj);
3790 }
3791
3792 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3793 {
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796
3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3798 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3799 !intel_crtc_has_pending_flip(crtc),
3800 60*HZ) == 0)) {
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802
3803 spin_lock_irq(&dev->event_lock);
3804 if (intel_crtc->unpin_work) {
3805 WARN_ONCE(1, "Removing stuck page flip\n");
3806 page_flip_completed(intel_crtc);
3807 }
3808 spin_unlock_irq(&dev->event_lock);
3809 }
3810
3811 if (crtc->primary->fb) {
3812 mutex_lock(&dev->struct_mutex);
3813 intel_finish_fb(crtc->primary->fb);
3814 mutex_unlock(&dev->struct_mutex);
3815 }
3816 }
3817
3818 /* Program iCLKIP clock to the desired frequency */
3819 static void lpt_program_iclkip(struct drm_crtc *crtc)
3820 {
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3824 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3825 u32 temp;
3826
3827 mutex_lock(&dev_priv->dpio_lock);
3828
3829 /* It is necessary to ungate the pixclk gate prior to programming
3830 * the divisors, and gate it back when it is done.
3831 */
3832 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834 /* Disable SSCCTL */
3835 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3836 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3837 SBI_SSCCTL_DISABLE,
3838 SBI_ICLK);
3839
3840 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3841 if (clock == 20000) {
3842 auxdiv = 1;
3843 divsel = 0x41;
3844 phaseinc = 0x20;
3845 } else {
3846 /* The iCLK virtual clock root frequency is in MHz,
3847 * but the adjusted_mode->crtc_clock in in KHz. To get the
3848 * divisors, it is necessary to divide one by another, so we
3849 * convert the virtual clock precision to KHz here for higher
3850 * precision.
3851 */
3852 u32 iclk_virtual_root_freq = 172800 * 1000;
3853 u32 iclk_pi_range = 64;
3854 u32 desired_divisor, msb_divisor_value, pi_value;
3855
3856 desired_divisor = (iclk_virtual_root_freq / clock);
3857 msb_divisor_value = desired_divisor / iclk_pi_range;
3858 pi_value = desired_divisor % iclk_pi_range;
3859
3860 auxdiv = 0;
3861 divsel = msb_divisor_value - 2;
3862 phaseinc = pi_value;
3863 }
3864
3865 /* This should not happen with any sane values */
3866 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3867 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3869 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3870
3871 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3872 clock,
3873 auxdiv,
3874 divsel,
3875 phasedir,
3876 phaseinc);
3877
3878 /* Program SSCDIVINTPHASE6 */
3879 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3880 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3882 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3884 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3885 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3886 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3887
3888 /* Program SSCAUXDIV */
3889 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3890 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3892 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3893
3894 /* Enable modulator and associated divider */
3895 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3896 temp &= ~SBI_SSCCTL_DISABLE;
3897 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3903
3904 mutex_unlock(&dev_priv->dpio_lock);
3905 }
3906
3907 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3908 enum pipe pch_transcoder)
3909 {
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3913
3914 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3915 I915_READ(HTOTAL(cpu_transcoder)));
3916 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3917 I915_READ(HBLANK(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3919 I915_READ(HSYNC(cpu_transcoder)));
3920
3921 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3922 I915_READ(VTOTAL(cpu_transcoder)));
3923 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3924 I915_READ(VBLANK(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3926 I915_READ(VSYNC(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3928 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3929 }
3930
3931 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3932 {
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 uint32_t temp;
3935
3936 temp = I915_READ(SOUTH_CHICKEN1);
3937 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3938 return;
3939
3940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3941 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3942
3943 temp &= ~FDI_BC_BIFURCATION_SELECT;
3944 if (enable)
3945 temp |= FDI_BC_BIFURCATION_SELECT;
3946
3947 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3948 I915_WRITE(SOUTH_CHICKEN1, temp);
3949 POSTING_READ(SOUTH_CHICKEN1);
3950 }
3951
3952 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3953 {
3954 struct drm_device *dev = intel_crtc->base.dev;
3955
3956 switch (intel_crtc->pipe) {
3957 case PIPE_A:
3958 break;
3959 case PIPE_B:
3960 if (intel_crtc->config->fdi_lanes > 2)
3961 cpt_set_fdi_bc_bifurcation(dev, false);
3962 else
3963 cpt_set_fdi_bc_bifurcation(dev, true);
3964
3965 break;
3966 case PIPE_C:
3967 cpt_set_fdi_bc_bifurcation(dev, true);
3968
3969 break;
3970 default:
3971 BUG();
3972 }
3973 }
3974
3975 /*
3976 * Enable PCH resources required for PCH ports:
3977 * - PCH PLLs
3978 * - FDI training & RX/TX
3979 * - update transcoder timings
3980 * - DP transcoding bits
3981 * - transcoder
3982 */
3983 static void ironlake_pch_enable(struct drm_crtc *crtc)
3984 {
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
3989 u32 reg, temp;
3990
3991 assert_pch_transcoder_disabled(dev_priv, pipe);
3992
3993 if (IS_IVYBRIDGE(dev))
3994 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3995
3996 /* Write the TU size bits before fdi link training, so that error
3997 * detection works. */
3998 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3999 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4000
4001 /* For PCH output, training FDI link */
4002 dev_priv->display.fdi_link_train(crtc);
4003
4004 /* We need to program the right clock selection before writing the pixel
4005 * mutliplier into the DPLL. */
4006 if (HAS_PCH_CPT(dev)) {
4007 u32 sel;
4008
4009 temp = I915_READ(PCH_DPLL_SEL);
4010 temp |= TRANS_DPLL_ENABLE(pipe);
4011 sel = TRANS_DPLLB_SEL(pipe);
4012 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4013 temp |= sel;
4014 else
4015 temp &= ~sel;
4016 I915_WRITE(PCH_DPLL_SEL, temp);
4017 }
4018
4019 /* XXX: pch pll's can be enabled any time before we enable the PCH
4020 * transcoder, and we actually should do this to not upset any PCH
4021 * transcoder that already use the clock when we share it.
4022 *
4023 * Note that enable_shared_dpll tries to do the right thing, but
4024 * get_shared_dpll unconditionally resets the pll - we need that to have
4025 * the right LVDS enable sequence. */
4026 intel_enable_shared_dpll(intel_crtc);
4027
4028 /* set transcoder timing, panel must allow it */
4029 assert_panel_unlocked(dev_priv, pipe);
4030 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4031
4032 intel_fdi_normal_train(crtc);
4033
4034 /* For PCH DP, enable TRANS_DP_CTL */
4035 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4037 reg = TRANS_DP_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4040 TRANS_DP_SYNC_MASK |
4041 TRANS_DP_BPC_MASK);
4042 temp |= (TRANS_DP_OUTPUT_ENABLE |
4043 TRANS_DP_ENH_FRAMING);
4044 temp |= bpc << 9; /* same format but at 11:9 */
4045
4046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4050
4051 switch (intel_trans_dp_port_sel(crtc)) {
4052 case PCH_DP_B:
4053 temp |= TRANS_DP_PORT_SEL_B;
4054 break;
4055 case PCH_DP_C:
4056 temp |= TRANS_DP_PORT_SEL_C;
4057 break;
4058 case PCH_DP_D:
4059 temp |= TRANS_DP_PORT_SEL_D;
4060 break;
4061 default:
4062 BUG();
4063 }
4064
4065 I915_WRITE(reg, temp);
4066 }
4067
4068 ironlake_enable_pch_transcoder(dev_priv, pipe);
4069 }
4070
4071 static void lpt_pch_enable(struct drm_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4077
4078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4079
4080 lpt_program_iclkip(crtc);
4081
4082 /* Set transcoder timing. */
4083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4084
4085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4086 }
4087
4088 void intel_put_shared_dpll(struct intel_crtc *crtc)
4089 {
4090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4091
4092 if (pll == NULL)
4093 return;
4094
4095 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4096 WARN(1, "bad %s crtc mask\n", pll->name);
4097 return;
4098 }
4099
4100 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4101 if (pll->config.crtc_mask == 0) {
4102 WARN_ON(pll->on);
4103 WARN_ON(pll->active);
4104 }
4105
4106 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4107 }
4108
4109 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4110 struct intel_crtc_state *crtc_state)
4111 {
4112 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4113 struct intel_shared_dpll *pll;
4114 enum intel_dpll_id i;
4115
4116 if (HAS_PCH_IBX(dev_priv->dev)) {
4117 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4118 i = (enum intel_dpll_id) crtc->pipe;
4119 pll = &dev_priv->shared_dplls[i];
4120
4121 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122 crtc->base.base.id, pll->name);
4123
4124 WARN_ON(pll->new_config->crtc_mask);
4125
4126 goto found;
4127 }
4128
4129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130 pll = &dev_priv->shared_dplls[i];
4131
4132 /* Only want to check enabled timings first */
4133 if (pll->new_config->crtc_mask == 0)
4134 continue;
4135
4136 if (memcmp(&crtc_state->dpll_hw_state,
4137 &pll->new_config->hw_state,
4138 sizeof(pll->new_config->hw_state)) == 0) {
4139 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4140 crtc->base.base.id, pll->name,
4141 pll->new_config->crtc_mask,
4142 pll->active);
4143 goto found;
4144 }
4145 }
4146
4147 /* Ok no matching timings, maybe there's a free one? */
4148 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4149 pll = &dev_priv->shared_dplls[i];
4150 if (pll->new_config->crtc_mask == 0) {
4151 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152 crtc->base.base.id, pll->name);
4153 goto found;
4154 }
4155 }
4156
4157 return NULL;
4158
4159 found:
4160 if (pll->new_config->crtc_mask == 0)
4161 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4162
4163 crtc_state->shared_dpll = i;
4164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4165 pipe_name(crtc->pipe));
4166
4167 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4168
4169 return pll;
4170 }
4171
4172 /**
4173 * intel_shared_dpll_start_config - start a new PLL staged config
4174 * @dev_priv: DRM device
4175 * @clear_pipes: mask of pipes that will have their PLLs freed
4176 *
4177 * Starts a new PLL staged config, copying the current config but
4178 * releasing the references of pipes specified in clear_pipes.
4179 */
4180 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4181 unsigned clear_pipes)
4182 {
4183 struct intel_shared_dpll *pll;
4184 enum intel_dpll_id i;
4185
4186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4187 pll = &dev_priv->shared_dplls[i];
4188
4189 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4190 GFP_KERNEL);
4191 if (!pll->new_config)
4192 goto cleanup;
4193
4194 pll->new_config->crtc_mask &= ~clear_pipes;
4195 }
4196
4197 return 0;
4198
4199 cleanup:
4200 while (--i >= 0) {
4201 pll = &dev_priv->shared_dplls[i];
4202 kfree(pll->new_config);
4203 pll->new_config = NULL;
4204 }
4205
4206 return -ENOMEM;
4207 }
4208
4209 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4210 {
4211 struct intel_shared_dpll *pll;
4212 enum intel_dpll_id i;
4213
4214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215 pll = &dev_priv->shared_dplls[i];
4216
4217 WARN_ON(pll->new_config == &pll->config);
4218
4219 pll->config = *pll->new_config;
4220 kfree(pll->new_config);
4221 pll->new_config = NULL;
4222 }
4223 }
4224
4225 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4226 {
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
4232
4233 WARN_ON(pll->new_config == &pll->config);
4234
4235 kfree(pll->new_config);
4236 pll->new_config = NULL;
4237 }
4238 }
4239
4240 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4241 {
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 int dslreg = PIPEDSL(pipe);
4244 u32 temp;
4245
4246 temp = I915_READ(dslreg);
4247 udelay(500);
4248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4249 if (wait_for(I915_READ(dslreg) != temp, 5))
4250 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4251 }
4252 }
4253
4254 static void skylake_pfit_enable(struct intel_crtc *crtc)
4255 {
4256 struct drm_device *dev = crtc->base.dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int pipe = crtc->pipe;
4259
4260 if (crtc->config->pch_pfit.enabled) {
4261 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4262 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4263 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4264 }
4265 }
4266
4267 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4268 {
4269 struct drm_device *dev = crtc->base.dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 int pipe = crtc->pipe;
4272
4273 if (crtc->config->pch_pfit.enabled) {
4274 /* Force use of hard-coded filter coefficients
4275 * as some pre-programmed values are broken,
4276 * e.g. x201.
4277 */
4278 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4279 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4280 PF_PIPE_SEL_IVB(pipe));
4281 else
4282 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4283 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4284 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4285 }
4286 }
4287
4288 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4289 {
4290 struct drm_device *dev = crtc->dev;
4291 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4292 struct drm_plane *plane;
4293 struct intel_plane *intel_plane;
4294
4295 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4296 intel_plane = to_intel_plane(plane);
4297 if (intel_plane->pipe == pipe)
4298 intel_plane_restore(&intel_plane->base);
4299 }
4300 }
4301
4302 /*
4303 * Disable a plane internally without actually modifying the plane's state.
4304 * This will allow us to easily restore the plane later by just reprogramming
4305 * its state.
4306 */
4307 static void disable_plane_internal(struct drm_plane *plane)
4308 {
4309 struct intel_plane *intel_plane = to_intel_plane(plane);
4310 struct drm_plane_state *state =
4311 plane->funcs->atomic_duplicate_state(plane);
4312 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4313
4314 intel_state->visible = false;
4315 intel_plane->commit_plane(plane, intel_state);
4316
4317 intel_plane_destroy_state(plane, state);
4318 }
4319
4320 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4321 {
4322 struct drm_device *dev = crtc->dev;
4323 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4324 struct drm_plane *plane;
4325 struct intel_plane *intel_plane;
4326
4327 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4328 intel_plane = to_intel_plane(plane);
4329 if (plane->fb && intel_plane->pipe == pipe)
4330 disable_plane_internal(plane);
4331 }
4332 }
4333
4334 void hsw_enable_ips(struct intel_crtc *crtc)
4335 {
4336 struct drm_device *dev = crtc->base.dev;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338
4339 if (!crtc->config->ips_enabled)
4340 return;
4341
4342 /* We can only enable IPS after we enable a plane and wait for a vblank */
4343 intel_wait_for_vblank(dev, crtc->pipe);
4344
4345 assert_plane_enabled(dev_priv, crtc->plane);
4346 if (IS_BROADWELL(dev)) {
4347 mutex_lock(&dev_priv->rps.hw_lock);
4348 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4349 mutex_unlock(&dev_priv->rps.hw_lock);
4350 /* Quoting Art Runyan: "its not safe to expect any particular
4351 * value in IPS_CTL bit 31 after enabling IPS through the
4352 * mailbox." Moreover, the mailbox may return a bogus state,
4353 * so we need to just enable it and continue on.
4354 */
4355 } else {
4356 I915_WRITE(IPS_CTL, IPS_ENABLE);
4357 /* The bit only becomes 1 in the next vblank, so this wait here
4358 * is essentially intel_wait_for_vblank. If we don't have this
4359 * and don't wait for vblanks until the end of crtc_enable, then
4360 * the HW state readout code will complain that the expected
4361 * IPS_CTL value is not the one we read. */
4362 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4363 DRM_ERROR("Timed out waiting for IPS enable\n");
4364 }
4365 }
4366
4367 void hsw_disable_ips(struct intel_crtc *crtc)
4368 {
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371
4372 if (!crtc->config->ips_enabled)
4373 return;
4374
4375 assert_plane_enabled(dev_priv, crtc->plane);
4376 if (IS_BROADWELL(dev)) {
4377 mutex_lock(&dev_priv->rps.hw_lock);
4378 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4379 mutex_unlock(&dev_priv->rps.hw_lock);
4380 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4382 DRM_ERROR("Timed out waiting for IPS disable\n");
4383 } else {
4384 I915_WRITE(IPS_CTL, 0);
4385 POSTING_READ(IPS_CTL);
4386 }
4387
4388 /* We need to wait for a vblank before we can disable the plane. */
4389 intel_wait_for_vblank(dev, crtc->pipe);
4390 }
4391
4392 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4393 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4394 {
4395 struct drm_device *dev = crtc->dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 enum pipe pipe = intel_crtc->pipe;
4399 int palreg = PALETTE(pipe);
4400 int i;
4401 bool reenable_ips = false;
4402
4403 /* The clocks have to be on to load the palette. */
4404 if (!crtc->state->enable || !intel_crtc->active)
4405 return;
4406
4407 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4408 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4409 assert_dsi_pll_enabled(dev_priv);
4410 else
4411 assert_pll_enabled(dev_priv, pipe);
4412 }
4413
4414 /* use legacy palette for Ironlake */
4415 if (!HAS_GMCH_DISPLAY(dev))
4416 palreg = LGC_PALETTE(pipe);
4417
4418 /* Workaround : Do not read or write the pipe palette/gamma data while
4419 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4420 */
4421 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4422 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4423 GAMMA_MODE_MODE_SPLIT)) {
4424 hsw_disable_ips(intel_crtc);
4425 reenable_ips = true;
4426 }
4427
4428 for (i = 0; i < 256; i++) {
4429 I915_WRITE(palreg + 4 * i,
4430 (intel_crtc->lut_r[i] << 16) |
4431 (intel_crtc->lut_g[i] << 8) |
4432 intel_crtc->lut_b[i]);
4433 }
4434
4435 if (reenable_ips)
4436 hsw_enable_ips(intel_crtc);
4437 }
4438
4439 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4440 {
4441 if (!enable && intel_crtc->overlay) {
4442 struct drm_device *dev = intel_crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445 mutex_lock(&dev->struct_mutex);
4446 dev_priv->mm.interruptible = false;
4447 (void) intel_overlay_switch_off(intel_crtc->overlay);
4448 dev_priv->mm.interruptible = true;
4449 mutex_unlock(&dev->struct_mutex);
4450 }
4451
4452 /* Let userspace switch the overlay on again. In most cases userspace
4453 * has to recompute where to put it anyway.
4454 */
4455 }
4456
4457 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4458 {
4459 struct drm_device *dev = crtc->dev;
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
4462
4463 intel_enable_primary_hw_plane(crtc->primary, crtc);
4464 intel_enable_sprite_planes(crtc);
4465 intel_crtc_update_cursor(crtc, true);
4466 intel_crtc_dpms_overlay(intel_crtc, true);
4467
4468 hsw_enable_ips(intel_crtc);
4469
4470 mutex_lock(&dev->struct_mutex);
4471 intel_fbc_update(dev);
4472 mutex_unlock(&dev->struct_mutex);
4473
4474 /*
4475 * FIXME: Once we grow proper nuclear flip support out of this we need
4476 * to compute the mask of flip planes precisely. For the time being
4477 * consider this a flip from a NULL plane.
4478 */
4479 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4480 }
4481
4482 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4483 {
4484 struct drm_device *dev = crtc->dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487 int pipe = intel_crtc->pipe;
4488
4489 intel_crtc_wait_for_pending_flips(crtc);
4490
4491 if (dev_priv->fbc.crtc == intel_crtc)
4492 intel_fbc_disable(dev);
4493
4494 hsw_disable_ips(intel_crtc);
4495
4496 intel_crtc_dpms_overlay(intel_crtc, false);
4497 intel_crtc_update_cursor(crtc, false);
4498 intel_disable_sprite_planes(crtc);
4499 intel_disable_primary_hw_plane(crtc->primary, crtc);
4500
4501 /*
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip to a NULL plane.
4505 */
4506 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4507 }
4508
4509 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4510 {
4511 struct drm_device *dev = crtc->dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4514 struct intel_encoder *encoder;
4515 int pipe = intel_crtc->pipe;
4516
4517 WARN_ON(!crtc->state->enable);
4518
4519 if (intel_crtc->active)
4520 return;
4521
4522 if (intel_crtc->config->has_pch_encoder)
4523 intel_prepare_shared_dpll(intel_crtc);
4524
4525 if (intel_crtc->config->has_dp_encoder)
4526 intel_dp_set_m_n(intel_crtc, M1_N1);
4527
4528 intel_set_pipe_timings(intel_crtc);
4529
4530 if (intel_crtc->config->has_pch_encoder) {
4531 intel_cpu_transcoder_set_m_n(intel_crtc,
4532 &intel_crtc->config->fdi_m_n, NULL);
4533 }
4534
4535 ironlake_set_pipeconf(crtc);
4536
4537 intel_crtc->active = true;
4538
4539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4540 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4541
4542 for_each_encoder_on_crtc(dev, crtc, encoder)
4543 if (encoder->pre_enable)
4544 encoder->pre_enable(encoder);
4545
4546 if (intel_crtc->config->has_pch_encoder) {
4547 /* Note: FDI PLL enabling _must_ be done before we enable the
4548 * cpu pipes, hence this is separate from all the other fdi/pch
4549 * enabling. */
4550 ironlake_fdi_pll_enable(intel_crtc);
4551 } else {
4552 assert_fdi_tx_disabled(dev_priv, pipe);
4553 assert_fdi_rx_disabled(dev_priv, pipe);
4554 }
4555
4556 ironlake_pfit_enable(intel_crtc);
4557
4558 /*
4559 * On ILK+ LUT must be loaded before the pipe is running but with
4560 * clocks enabled
4561 */
4562 intel_crtc_load_lut(crtc);
4563
4564 intel_update_watermarks(crtc);
4565 intel_enable_pipe(intel_crtc);
4566
4567 if (intel_crtc->config->has_pch_encoder)
4568 ironlake_pch_enable(crtc);
4569
4570 assert_vblank_disabled(crtc);
4571 drm_crtc_vblank_on(crtc);
4572
4573 for_each_encoder_on_crtc(dev, crtc, encoder)
4574 encoder->enable(encoder);
4575
4576 if (HAS_PCH_CPT(dev))
4577 cpt_verify_modeset(dev, intel_crtc->pipe);
4578
4579 intel_crtc_enable_planes(crtc);
4580 }
4581
4582 /* IPS only exists on ULT machines and is tied to pipe A. */
4583 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4584 {
4585 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4586 }
4587
4588 /*
4589 * This implements the workaround described in the "notes" section of the mode
4590 * set sequence documentation. When going from no pipes or single pipe to
4591 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4593 */
4594 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4595 {
4596 struct drm_device *dev = crtc->base.dev;
4597 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4598
4599 /* We want to get the other_active_crtc only if there's only 1 other
4600 * active crtc. */
4601 for_each_intel_crtc(dev, crtc_it) {
4602 if (!crtc_it->active || crtc_it == crtc)
4603 continue;
4604
4605 if (other_active_crtc)
4606 return;
4607
4608 other_active_crtc = crtc_it;
4609 }
4610 if (!other_active_crtc)
4611 return;
4612
4613 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4615 }
4616
4617 static void haswell_crtc_enable(struct drm_crtc *crtc)
4618 {
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 struct intel_encoder *encoder;
4623 int pipe = intel_crtc->pipe;
4624
4625 WARN_ON(!crtc->state->enable);
4626
4627 if (intel_crtc->active)
4628 return;
4629
4630 if (intel_crtc_to_shared_dpll(intel_crtc))
4631 intel_enable_shared_dpll(intel_crtc);
4632
4633 if (intel_crtc->config->has_dp_encoder)
4634 intel_dp_set_m_n(intel_crtc, M1_N1);
4635
4636 intel_set_pipe_timings(intel_crtc);
4637
4638 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4639 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4640 intel_crtc->config->pixel_multiplier - 1);
4641 }
4642
4643 if (intel_crtc->config->has_pch_encoder) {
4644 intel_cpu_transcoder_set_m_n(intel_crtc,
4645 &intel_crtc->config->fdi_m_n, NULL);
4646 }
4647
4648 haswell_set_pipeconf(crtc);
4649
4650 intel_set_pipe_csc(crtc);
4651
4652 intel_crtc->active = true;
4653
4654 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4655 for_each_encoder_on_crtc(dev, crtc, encoder)
4656 if (encoder->pre_enable)
4657 encoder->pre_enable(encoder);
4658
4659 if (intel_crtc->config->has_pch_encoder) {
4660 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4661 true);
4662 dev_priv->display.fdi_link_train(crtc);
4663 }
4664
4665 intel_ddi_enable_pipe_clock(intel_crtc);
4666
4667 if (IS_SKYLAKE(dev))
4668 skylake_pfit_enable(intel_crtc);
4669 else
4670 ironlake_pfit_enable(intel_crtc);
4671
4672 /*
4673 * On ILK+ LUT must be loaded before the pipe is running but with
4674 * clocks enabled
4675 */
4676 intel_crtc_load_lut(crtc);
4677
4678 intel_ddi_set_pipe_settings(crtc);
4679 intel_ddi_enable_transcoder_func(crtc);
4680
4681 intel_update_watermarks(crtc);
4682 intel_enable_pipe(intel_crtc);
4683
4684 if (intel_crtc->config->has_pch_encoder)
4685 lpt_pch_enable(crtc);
4686
4687 if (intel_crtc->config->dp_encoder_is_mst)
4688 intel_ddi_set_vc_payload_alloc(crtc, true);
4689
4690 assert_vblank_disabled(crtc);
4691 drm_crtc_vblank_on(crtc);
4692
4693 for_each_encoder_on_crtc(dev, crtc, encoder) {
4694 encoder->enable(encoder);
4695 intel_opregion_notify_encoder(encoder, true);
4696 }
4697
4698 /* If we change the relative order between pipe/planes enabling, we need
4699 * to change the workaround. */
4700 haswell_mode_set_planes_workaround(intel_crtc);
4701 intel_crtc_enable_planes(crtc);
4702 }
4703
4704 static void skylake_pfit_disable(struct intel_crtc *crtc)
4705 {
4706 struct drm_device *dev = crtc->base.dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 int pipe = crtc->pipe;
4709
4710 /* To avoid upsetting the power well on haswell only disable the pfit if
4711 * it's in use. The hw state code will make sure we get this right. */
4712 if (crtc->config->pch_pfit.enabled) {
4713 I915_WRITE(PS_CTL(pipe), 0);
4714 I915_WRITE(PS_WIN_POS(pipe), 0);
4715 I915_WRITE(PS_WIN_SZ(pipe), 0);
4716 }
4717 }
4718
4719 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4720 {
4721 struct drm_device *dev = crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int pipe = crtc->pipe;
4724
4725 /* To avoid upsetting the power well on haswell only disable the pfit if
4726 * it's in use. The hw state code will make sure we get this right. */
4727 if (crtc->config->pch_pfit.enabled) {
4728 I915_WRITE(PF_CTL(pipe), 0);
4729 I915_WRITE(PF_WIN_POS(pipe), 0);
4730 I915_WRITE(PF_WIN_SZ(pipe), 0);
4731 }
4732 }
4733
4734 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4735 {
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4739 struct intel_encoder *encoder;
4740 int pipe = intel_crtc->pipe;
4741 u32 reg, temp;
4742
4743 if (!intel_crtc->active)
4744 return;
4745
4746 intel_crtc_disable_planes(crtc);
4747
4748 for_each_encoder_on_crtc(dev, crtc, encoder)
4749 encoder->disable(encoder);
4750
4751 drm_crtc_vblank_off(crtc);
4752 assert_vblank_disabled(crtc);
4753
4754 if (intel_crtc->config->has_pch_encoder)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4756
4757 intel_disable_pipe(intel_crtc);
4758
4759 ironlake_pfit_disable(intel_crtc);
4760
4761 for_each_encoder_on_crtc(dev, crtc, encoder)
4762 if (encoder->post_disable)
4763 encoder->post_disable(encoder);
4764
4765 if (intel_crtc->config->has_pch_encoder) {
4766 ironlake_fdi_disable(crtc);
4767
4768 ironlake_disable_pch_transcoder(dev_priv, pipe);
4769
4770 if (HAS_PCH_CPT(dev)) {
4771 /* disable TRANS_DP_CTL */
4772 reg = TRANS_DP_CTL(pipe);
4773 temp = I915_READ(reg);
4774 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4775 TRANS_DP_PORT_SEL_MASK);
4776 temp |= TRANS_DP_PORT_SEL_NONE;
4777 I915_WRITE(reg, temp);
4778
4779 /* disable DPLL_SEL */
4780 temp = I915_READ(PCH_DPLL_SEL);
4781 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4782 I915_WRITE(PCH_DPLL_SEL, temp);
4783 }
4784
4785 /* disable PCH DPLL */
4786 intel_disable_shared_dpll(intel_crtc);
4787
4788 ironlake_fdi_pll_disable(intel_crtc);
4789 }
4790
4791 intel_crtc->active = false;
4792 intel_update_watermarks(crtc);
4793
4794 mutex_lock(&dev->struct_mutex);
4795 intel_fbc_update(dev);
4796 mutex_unlock(&dev->struct_mutex);
4797 }
4798
4799 static void haswell_crtc_disable(struct drm_crtc *crtc)
4800 {
4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4804 struct intel_encoder *encoder;
4805 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4806
4807 if (!intel_crtc->active)
4808 return;
4809
4810 intel_crtc_disable_planes(crtc);
4811
4812 for_each_encoder_on_crtc(dev, crtc, encoder) {
4813 intel_opregion_notify_encoder(encoder, false);
4814 encoder->disable(encoder);
4815 }
4816
4817 drm_crtc_vblank_off(crtc);
4818 assert_vblank_disabled(crtc);
4819
4820 if (intel_crtc->config->has_pch_encoder)
4821 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4822 false);
4823 intel_disable_pipe(intel_crtc);
4824
4825 if (intel_crtc->config->dp_encoder_is_mst)
4826 intel_ddi_set_vc_payload_alloc(crtc, false);
4827
4828 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4829
4830 if (IS_SKYLAKE(dev))
4831 skylake_pfit_disable(intel_crtc);
4832 else
4833 ironlake_pfit_disable(intel_crtc);
4834
4835 intel_ddi_disable_pipe_clock(intel_crtc);
4836
4837 if (intel_crtc->config->has_pch_encoder) {
4838 lpt_disable_pch_transcoder(dev_priv);
4839 intel_ddi_fdi_disable(crtc);
4840 }
4841
4842 for_each_encoder_on_crtc(dev, crtc, encoder)
4843 if (encoder->post_disable)
4844 encoder->post_disable(encoder);
4845
4846 intel_crtc->active = false;
4847 intel_update_watermarks(crtc);
4848
4849 mutex_lock(&dev->struct_mutex);
4850 intel_fbc_update(dev);
4851 mutex_unlock(&dev->struct_mutex);
4852
4853 if (intel_crtc_to_shared_dpll(intel_crtc))
4854 intel_disable_shared_dpll(intel_crtc);
4855 }
4856
4857 static void ironlake_crtc_off(struct drm_crtc *crtc)
4858 {
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4860 intel_put_shared_dpll(intel_crtc);
4861 }
4862
4863
4864 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4865 {
4866 struct drm_device *dev = crtc->base.dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc_state *pipe_config = crtc->config;
4869
4870 if (!pipe_config->gmch_pfit.control)
4871 return;
4872
4873 /*
4874 * The panel fitter should only be adjusted whilst the pipe is disabled,
4875 * according to register description and PRM.
4876 */
4877 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4878 assert_pipe_disabled(dev_priv, crtc->pipe);
4879
4880 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4881 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4882
4883 /* Border color in case we don't scale up to the full screen. Black by
4884 * default, change to something else for debugging. */
4885 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4886 }
4887
4888 static enum intel_display_power_domain port_to_power_domain(enum port port)
4889 {
4890 switch (port) {
4891 case PORT_A:
4892 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4893 case PORT_B:
4894 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4895 case PORT_C:
4896 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4897 case PORT_D:
4898 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4899 default:
4900 WARN_ON_ONCE(1);
4901 return POWER_DOMAIN_PORT_OTHER;
4902 }
4903 }
4904
4905 #define for_each_power_domain(domain, mask) \
4906 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4907 if ((1 << (domain)) & (mask))
4908
4909 enum intel_display_power_domain
4910 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4911 {
4912 struct drm_device *dev = intel_encoder->base.dev;
4913 struct intel_digital_port *intel_dig_port;
4914
4915 switch (intel_encoder->type) {
4916 case INTEL_OUTPUT_UNKNOWN:
4917 /* Only DDI platforms should ever use this output type */
4918 WARN_ON_ONCE(!HAS_DDI(dev));
4919 case INTEL_OUTPUT_DISPLAYPORT:
4920 case INTEL_OUTPUT_HDMI:
4921 case INTEL_OUTPUT_EDP:
4922 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4923 return port_to_power_domain(intel_dig_port->port);
4924 case INTEL_OUTPUT_DP_MST:
4925 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4926 return port_to_power_domain(intel_dig_port->port);
4927 case INTEL_OUTPUT_ANALOG:
4928 return POWER_DOMAIN_PORT_CRT;
4929 case INTEL_OUTPUT_DSI:
4930 return POWER_DOMAIN_PORT_DSI;
4931 default:
4932 return POWER_DOMAIN_PORT_OTHER;
4933 }
4934 }
4935
4936 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4937 {
4938 struct drm_device *dev = crtc->dev;
4939 struct intel_encoder *intel_encoder;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 enum pipe pipe = intel_crtc->pipe;
4942 unsigned long mask;
4943 enum transcoder transcoder;
4944
4945 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4946
4947 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4948 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4949 if (intel_crtc->config->pch_pfit.enabled ||
4950 intel_crtc->config->pch_pfit.force_thru)
4951 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4952
4953 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4954 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4955
4956 return mask;
4957 }
4958
4959 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
4960 {
4961 struct drm_device *dev = state->dev;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4964 struct intel_crtc *crtc;
4965
4966 /*
4967 * First get all needed power domains, then put all unneeded, to avoid
4968 * any unnecessary toggling of the power wells.
4969 */
4970 for_each_intel_crtc(dev, crtc) {
4971 enum intel_display_power_domain domain;
4972
4973 if (!crtc->base.state->enable)
4974 continue;
4975
4976 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4977
4978 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4979 intel_display_power_get(dev_priv, domain);
4980 }
4981
4982 if (dev_priv->display.modeset_global_resources)
4983 dev_priv->display.modeset_global_resources(state);
4984
4985 for_each_intel_crtc(dev, crtc) {
4986 enum intel_display_power_domain domain;
4987
4988 for_each_power_domain(domain, crtc->enabled_power_domains)
4989 intel_display_power_put(dev_priv, domain);
4990
4991 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4992 }
4993
4994 intel_display_set_init_power(dev_priv, false);
4995 }
4996
4997 /* returns HPLL frequency in kHz */
4998 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4999 {
5000 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5001
5002 /* Obtain SKU information */
5003 mutex_lock(&dev_priv->dpio_lock);
5004 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5005 CCK_FUSE_HPLL_FREQ_MASK;
5006 mutex_unlock(&dev_priv->dpio_lock);
5007
5008 return vco_freq[hpll_freq] * 1000;
5009 }
5010
5011 static void vlv_update_cdclk(struct drm_device *dev)
5012 {
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014
5015 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5016 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5017 dev_priv->vlv_cdclk_freq);
5018
5019 /*
5020 * Program the gmbus_freq based on the cdclk frequency.
5021 * BSpec erroneously claims we should aim for 4MHz, but
5022 * in fact 1MHz is the correct frequency.
5023 */
5024 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
5025 }
5026
5027 /* Adjust CDclk dividers to allow high res or save power if possible */
5028 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5029 {
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 u32 val, cmd;
5032
5033 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5034
5035 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5036 cmd = 2;
5037 else if (cdclk == 266667)
5038 cmd = 1;
5039 else
5040 cmd = 0;
5041
5042 mutex_lock(&dev_priv->rps.hw_lock);
5043 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5044 val &= ~DSPFREQGUAR_MASK;
5045 val |= (cmd << DSPFREQGUAR_SHIFT);
5046 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5047 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5048 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5049 50)) {
5050 DRM_ERROR("timed out waiting for CDclk change\n");
5051 }
5052 mutex_unlock(&dev_priv->rps.hw_lock);
5053
5054 if (cdclk == 400000) {
5055 u32 divider;
5056
5057 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5058
5059 mutex_lock(&dev_priv->dpio_lock);
5060 /* adjust cdclk divider */
5061 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5062 val &= ~DISPLAY_FREQUENCY_VALUES;
5063 val |= divider;
5064 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5065
5066 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5067 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5068 50))
5069 DRM_ERROR("timed out waiting for CDclk change\n");
5070 mutex_unlock(&dev_priv->dpio_lock);
5071 }
5072
5073 mutex_lock(&dev_priv->dpio_lock);
5074 /* adjust self-refresh exit latency value */
5075 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5076 val &= ~0x7f;
5077
5078 /*
5079 * For high bandwidth configs, we set a higher latency in the bunit
5080 * so that the core display fetch happens in time to avoid underruns.
5081 */
5082 if (cdclk == 400000)
5083 val |= 4500 / 250; /* 4.5 usec */
5084 else
5085 val |= 3000 / 250; /* 3.0 usec */
5086 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5087 mutex_unlock(&dev_priv->dpio_lock);
5088
5089 vlv_update_cdclk(dev);
5090 }
5091
5092 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5093 {
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 u32 val, cmd;
5096
5097 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5098
5099 switch (cdclk) {
5100 case 333333:
5101 case 320000:
5102 case 266667:
5103 case 200000:
5104 break;
5105 default:
5106 MISSING_CASE(cdclk);
5107 return;
5108 }
5109
5110 /*
5111 * Specs are full of misinformation, but testing on actual
5112 * hardware has shown that we just need to write the desired
5113 * CCK divider into the Punit register.
5114 */
5115 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5116
5117 mutex_lock(&dev_priv->rps.hw_lock);
5118 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5119 val &= ~DSPFREQGUAR_MASK_CHV;
5120 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5121 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5122 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5123 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5124 50)) {
5125 DRM_ERROR("timed out waiting for CDclk change\n");
5126 }
5127 mutex_unlock(&dev_priv->rps.hw_lock);
5128
5129 vlv_update_cdclk(dev);
5130 }
5131
5132 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5133 int max_pixclk)
5134 {
5135 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5136 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5137
5138 /*
5139 * Really only a few cases to deal with, as only 4 CDclks are supported:
5140 * 200MHz
5141 * 267MHz
5142 * 320/333MHz (depends on HPLL freq)
5143 * 400MHz (VLV only)
5144 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145 * of the lower bin and adjust if needed.
5146 *
5147 * We seem to get an unstable or solid color picture at 200MHz.
5148 * Not sure what's wrong. For now use 200MHz only when all pipes
5149 * are off.
5150 */
5151 if (!IS_CHERRYVIEW(dev_priv) &&
5152 max_pixclk > freq_320*limit/100)
5153 return 400000;
5154 else if (max_pixclk > 266667*limit/100)
5155 return freq_320;
5156 else if (max_pixclk > 0)
5157 return 266667;
5158 else
5159 return 200000;
5160 }
5161
5162 /* compute the max pixel clock for new configuration */
5163 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5164 {
5165 struct drm_device *dev = dev_priv->dev;
5166 struct intel_crtc *intel_crtc;
5167 int max_pixclk = 0;
5168
5169 for_each_intel_crtc(dev, intel_crtc) {
5170 if (intel_crtc->new_enabled)
5171 max_pixclk = max(max_pixclk,
5172 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5173 }
5174
5175 return max_pixclk;
5176 }
5177
5178 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5179 unsigned *prepare_pipes)
5180 {
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *intel_crtc;
5183 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5184
5185 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5186 dev_priv->vlv_cdclk_freq)
5187 return;
5188
5189 /* disable/enable all currently active pipes while we change cdclk */
5190 for_each_intel_crtc(dev, intel_crtc)
5191 if (intel_crtc->base.state->enable)
5192 *prepare_pipes |= (1 << intel_crtc->pipe);
5193 }
5194
5195 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5196 {
5197 unsigned int credits, default_credits;
5198
5199 if (IS_CHERRYVIEW(dev_priv))
5200 default_credits = PFI_CREDIT(12);
5201 else
5202 default_credits = PFI_CREDIT(8);
5203
5204 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5205 /* CHV suggested value is 31 or 63 */
5206 if (IS_CHERRYVIEW(dev_priv))
5207 credits = PFI_CREDIT_31;
5208 else
5209 credits = PFI_CREDIT(15);
5210 } else {
5211 credits = default_credits;
5212 }
5213
5214 /*
5215 * WA - write default credits before re-programming
5216 * FIXME: should we also set the resend bit here?
5217 */
5218 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5219 default_credits);
5220
5221 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5222 credits | PFI_CREDIT_RESEND);
5223
5224 /*
5225 * FIXME is this guaranteed to clear
5226 * immediately or should we poll for it?
5227 */
5228 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5229 }
5230
5231 static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
5232 {
5233 struct drm_device *dev = state->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5236 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5237
5238 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5239 /*
5240 * FIXME: We can end up here with all power domains off, yet
5241 * with a CDCLK frequency other than the minimum. To account
5242 * for this take the PIPE-A power domain, which covers the HW
5243 * blocks needed for the following programming. This can be
5244 * removed once it's guaranteed that we get here either with
5245 * the minimum CDCLK set, or the required power domains
5246 * enabled.
5247 */
5248 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5249
5250 if (IS_CHERRYVIEW(dev))
5251 cherryview_set_cdclk(dev, req_cdclk);
5252 else
5253 valleyview_set_cdclk(dev, req_cdclk);
5254
5255 vlv_program_pfi_credits(dev_priv);
5256
5257 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5258 }
5259 }
5260
5261 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5262 {
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = to_i915(dev);
5265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5266 struct intel_encoder *encoder;
5267 int pipe = intel_crtc->pipe;
5268 bool is_dsi;
5269
5270 WARN_ON(!crtc->state->enable);
5271
5272 if (intel_crtc->active)
5273 return;
5274
5275 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5276
5277 if (!is_dsi) {
5278 if (IS_CHERRYVIEW(dev))
5279 chv_prepare_pll(intel_crtc, intel_crtc->config);
5280 else
5281 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5282 }
5283
5284 if (intel_crtc->config->has_dp_encoder)
5285 intel_dp_set_m_n(intel_crtc, M1_N1);
5286
5287 intel_set_pipe_timings(intel_crtc);
5288
5289 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5290 struct drm_i915_private *dev_priv = dev->dev_private;
5291
5292 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5293 I915_WRITE(CHV_CANVAS(pipe), 0);
5294 }
5295
5296 i9xx_set_pipeconf(intel_crtc);
5297
5298 intel_crtc->active = true;
5299
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5301
5302 for_each_encoder_on_crtc(dev, crtc, encoder)
5303 if (encoder->pre_pll_enable)
5304 encoder->pre_pll_enable(encoder);
5305
5306 if (!is_dsi) {
5307 if (IS_CHERRYVIEW(dev))
5308 chv_enable_pll(intel_crtc, intel_crtc->config);
5309 else
5310 vlv_enable_pll(intel_crtc, intel_crtc->config);
5311 }
5312
5313 for_each_encoder_on_crtc(dev, crtc, encoder)
5314 if (encoder->pre_enable)
5315 encoder->pre_enable(encoder);
5316
5317 i9xx_pfit_enable(intel_crtc);
5318
5319 intel_crtc_load_lut(crtc);
5320
5321 intel_update_watermarks(crtc);
5322 intel_enable_pipe(intel_crtc);
5323
5324 assert_vblank_disabled(crtc);
5325 drm_crtc_vblank_on(crtc);
5326
5327 for_each_encoder_on_crtc(dev, crtc, encoder)
5328 encoder->enable(encoder);
5329
5330 intel_crtc_enable_planes(crtc);
5331
5332 /* Underruns don't raise interrupts, so check manually. */
5333 i9xx_check_fifo_underruns(dev_priv);
5334 }
5335
5336 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5337 {
5338 struct drm_device *dev = crtc->base.dev;
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340
5341 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5342 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5343 }
5344
5345 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5346 {
5347 struct drm_device *dev = crtc->dev;
5348 struct drm_i915_private *dev_priv = to_i915(dev);
5349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350 struct intel_encoder *encoder;
5351 int pipe = intel_crtc->pipe;
5352
5353 WARN_ON(!crtc->state->enable);
5354
5355 if (intel_crtc->active)
5356 return;
5357
5358 i9xx_set_pll_dividers(intel_crtc);
5359
5360 if (intel_crtc->config->has_dp_encoder)
5361 intel_dp_set_m_n(intel_crtc, M1_N1);
5362
5363 intel_set_pipe_timings(intel_crtc);
5364
5365 i9xx_set_pipeconf(intel_crtc);
5366
5367 intel_crtc->active = true;
5368
5369 if (!IS_GEN2(dev))
5370 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5371
5372 for_each_encoder_on_crtc(dev, crtc, encoder)
5373 if (encoder->pre_enable)
5374 encoder->pre_enable(encoder);
5375
5376 i9xx_enable_pll(intel_crtc);
5377
5378 i9xx_pfit_enable(intel_crtc);
5379
5380 intel_crtc_load_lut(crtc);
5381
5382 intel_update_watermarks(crtc);
5383 intel_enable_pipe(intel_crtc);
5384
5385 assert_vblank_disabled(crtc);
5386 drm_crtc_vblank_on(crtc);
5387
5388 for_each_encoder_on_crtc(dev, crtc, encoder)
5389 encoder->enable(encoder);
5390
5391 intel_crtc_enable_planes(crtc);
5392
5393 /*
5394 * Gen2 reports pipe underruns whenever all planes are disabled.
5395 * So don't enable underrun reporting before at least some planes
5396 * are enabled.
5397 * FIXME: Need to fix the logic to work when we turn off all planes
5398 * but leave the pipe running.
5399 */
5400 if (IS_GEN2(dev))
5401 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5402
5403 /* Underruns don't raise interrupts, so check manually. */
5404 i9xx_check_fifo_underruns(dev_priv);
5405 }
5406
5407 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5408 {
5409 struct drm_device *dev = crtc->base.dev;
5410 struct drm_i915_private *dev_priv = dev->dev_private;
5411
5412 if (!crtc->config->gmch_pfit.control)
5413 return;
5414
5415 assert_pipe_disabled(dev_priv, crtc->pipe);
5416
5417 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5418 I915_READ(PFIT_CONTROL));
5419 I915_WRITE(PFIT_CONTROL, 0);
5420 }
5421
5422 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5423 {
5424 struct drm_device *dev = crtc->dev;
5425 struct drm_i915_private *dev_priv = dev->dev_private;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427 struct intel_encoder *encoder;
5428 int pipe = intel_crtc->pipe;
5429
5430 if (!intel_crtc->active)
5431 return;
5432
5433 /*
5434 * Gen2 reports pipe underruns whenever all planes are disabled.
5435 * So diasble underrun reporting before all the planes get disabled.
5436 * FIXME: Need to fix the logic to work when we turn off all planes
5437 * but leave the pipe running.
5438 */
5439 if (IS_GEN2(dev))
5440 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5441
5442 /*
5443 * Vblank time updates from the shadow to live plane control register
5444 * are blocked if the memory self-refresh mode is active at that
5445 * moment. So to make sure the plane gets truly disabled, disable
5446 * first the self-refresh mode. The self-refresh enable bit in turn
5447 * will be checked/applied by the HW only at the next frame start
5448 * event which is after the vblank start event, so we need to have a
5449 * wait-for-vblank between disabling the plane and the pipe.
5450 */
5451 intel_set_memory_cxsr(dev_priv, false);
5452 intel_crtc_disable_planes(crtc);
5453
5454 /*
5455 * On gen2 planes are double buffered but the pipe isn't, so we must
5456 * wait for planes to fully turn off before disabling the pipe.
5457 * We also need to wait on all gmch platforms because of the
5458 * self-refresh mode constraint explained above.
5459 */
5460 intel_wait_for_vblank(dev, pipe);
5461
5462 for_each_encoder_on_crtc(dev, crtc, encoder)
5463 encoder->disable(encoder);
5464
5465 drm_crtc_vblank_off(crtc);
5466 assert_vblank_disabled(crtc);
5467
5468 intel_disable_pipe(intel_crtc);
5469
5470 i9xx_pfit_disable(intel_crtc);
5471
5472 for_each_encoder_on_crtc(dev, crtc, encoder)
5473 if (encoder->post_disable)
5474 encoder->post_disable(encoder);
5475
5476 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5477 if (IS_CHERRYVIEW(dev))
5478 chv_disable_pll(dev_priv, pipe);
5479 else if (IS_VALLEYVIEW(dev))
5480 vlv_disable_pll(dev_priv, pipe);
5481 else
5482 i9xx_disable_pll(intel_crtc);
5483 }
5484
5485 if (!IS_GEN2(dev))
5486 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5487
5488 intel_crtc->active = false;
5489 intel_update_watermarks(crtc);
5490
5491 mutex_lock(&dev->struct_mutex);
5492 intel_fbc_update(dev);
5493 mutex_unlock(&dev->struct_mutex);
5494 }
5495
5496 static void i9xx_crtc_off(struct drm_crtc *crtc)
5497 {
5498 }
5499
5500 /* Master function to enable/disable CRTC and corresponding power wells */
5501 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5502 {
5503 struct drm_device *dev = crtc->dev;
5504 struct drm_i915_private *dev_priv = dev->dev_private;
5505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5506 enum intel_display_power_domain domain;
5507 unsigned long domains;
5508
5509 if (enable) {
5510 if (!intel_crtc->active) {
5511 domains = get_crtc_power_domains(crtc);
5512 for_each_power_domain(domain, domains)
5513 intel_display_power_get(dev_priv, domain);
5514 intel_crtc->enabled_power_domains = domains;
5515
5516 dev_priv->display.crtc_enable(crtc);
5517 }
5518 } else {
5519 if (intel_crtc->active) {
5520 dev_priv->display.crtc_disable(crtc);
5521
5522 domains = intel_crtc->enabled_power_domains;
5523 for_each_power_domain(domain, domains)
5524 intel_display_power_put(dev_priv, domain);
5525 intel_crtc->enabled_power_domains = 0;
5526 }
5527 }
5528 }
5529
5530 /**
5531 * Sets the power management mode of the pipe and plane.
5532 */
5533 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5534 {
5535 struct drm_device *dev = crtc->dev;
5536 struct intel_encoder *intel_encoder;
5537 bool enable = false;
5538
5539 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5540 enable |= intel_encoder->connectors_active;
5541
5542 intel_crtc_control(crtc, enable);
5543 }
5544
5545 static void intel_crtc_disable(struct drm_crtc *crtc)
5546 {
5547 struct drm_device *dev = crtc->dev;
5548 struct drm_connector *connector;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551 /* crtc should still be enabled when we disable it. */
5552 WARN_ON(!crtc->state->enable);
5553
5554 dev_priv->display.crtc_disable(crtc);
5555 dev_priv->display.off(crtc);
5556
5557 crtc->primary->funcs->disable_plane(crtc->primary);
5558
5559 /* Update computed state. */
5560 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5561 if (!connector->encoder || !connector->encoder->crtc)
5562 continue;
5563
5564 if (connector->encoder->crtc != crtc)
5565 continue;
5566
5567 connector->dpms = DRM_MODE_DPMS_OFF;
5568 to_intel_encoder(connector->encoder)->connectors_active = false;
5569 }
5570 }
5571
5572 void intel_encoder_destroy(struct drm_encoder *encoder)
5573 {
5574 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5575
5576 drm_encoder_cleanup(encoder);
5577 kfree(intel_encoder);
5578 }
5579
5580 /* Simple dpms helper for encoders with just one connector, no cloning and only
5581 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5582 * state of the entire output pipe. */
5583 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5584 {
5585 if (mode == DRM_MODE_DPMS_ON) {
5586 encoder->connectors_active = true;
5587
5588 intel_crtc_update_dpms(encoder->base.crtc);
5589 } else {
5590 encoder->connectors_active = false;
5591
5592 intel_crtc_update_dpms(encoder->base.crtc);
5593 }
5594 }
5595
5596 /* Cross check the actual hw state with our own modeset state tracking (and it's
5597 * internal consistency). */
5598 static void intel_connector_check_state(struct intel_connector *connector)
5599 {
5600 if (connector->get_hw_state(connector)) {
5601 struct intel_encoder *encoder = connector->encoder;
5602 struct drm_crtc *crtc;
5603 bool encoder_enabled;
5604 enum pipe pipe;
5605
5606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5607 connector->base.base.id,
5608 connector->base.name);
5609
5610 /* there is no real hw state for MST connectors */
5611 if (connector->mst_port)
5612 return;
5613
5614 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5615 "wrong connector dpms state\n");
5616 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5617 "active connector not linked to encoder\n");
5618
5619 if (encoder) {
5620 I915_STATE_WARN(!encoder->connectors_active,
5621 "encoder->connectors_active not set\n");
5622
5623 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5624 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5625 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5626 return;
5627
5628 crtc = encoder->base.crtc;
5629
5630 I915_STATE_WARN(!crtc->state->enable,
5631 "crtc not enabled\n");
5632 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5633 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5634 "encoder active on the wrong pipe\n");
5635 }
5636 }
5637 }
5638
5639 /* Even simpler default implementation, if there's really no special case to
5640 * consider. */
5641 void intel_connector_dpms(struct drm_connector *connector, int mode)
5642 {
5643 /* All the simple cases only support two dpms states. */
5644 if (mode != DRM_MODE_DPMS_ON)
5645 mode = DRM_MODE_DPMS_OFF;
5646
5647 if (mode == connector->dpms)
5648 return;
5649
5650 connector->dpms = mode;
5651
5652 /* Only need to change hw state when actually enabled */
5653 if (connector->encoder)
5654 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5655
5656 intel_modeset_check_state(connector->dev);
5657 }
5658
5659 /* Simple connector->get_hw_state implementation for encoders that support only
5660 * one connector and no cloning and hence the encoder state determines the state
5661 * of the connector. */
5662 bool intel_connector_get_hw_state(struct intel_connector *connector)
5663 {
5664 enum pipe pipe = 0;
5665 struct intel_encoder *encoder = connector->encoder;
5666
5667 return encoder->get_hw_state(encoder, &pipe);
5668 }
5669
5670 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5671 {
5672 struct intel_crtc *crtc =
5673 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5674
5675 if (crtc->base.state->enable &&
5676 crtc->config->has_pch_encoder)
5677 return crtc->config->fdi_lanes;
5678
5679 return 0;
5680 }
5681
5682 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5683 struct intel_crtc_state *pipe_config)
5684 {
5685 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5687 if (pipe_config->fdi_lanes > 4) {
5688 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5689 pipe_name(pipe), pipe_config->fdi_lanes);
5690 return false;
5691 }
5692
5693 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5694 if (pipe_config->fdi_lanes > 2) {
5695 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5696 pipe_config->fdi_lanes);
5697 return false;
5698 } else {
5699 return true;
5700 }
5701 }
5702
5703 if (INTEL_INFO(dev)->num_pipes == 2)
5704 return true;
5705
5706 /* Ivybridge 3 pipe is really complicated */
5707 switch (pipe) {
5708 case PIPE_A:
5709 return true;
5710 case PIPE_B:
5711 if (pipe_config->fdi_lanes > 2 &&
5712 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5713 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5714 pipe_name(pipe), pipe_config->fdi_lanes);
5715 return false;
5716 }
5717 return true;
5718 case PIPE_C:
5719 if (pipe_config->fdi_lanes > 2) {
5720 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5721 pipe_name(pipe), pipe_config->fdi_lanes);
5722 return false;
5723 }
5724 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5725 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5726 return false;
5727 }
5728 return true;
5729 default:
5730 BUG();
5731 }
5732 }
5733
5734 #define RETRY 1
5735 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5736 struct intel_crtc_state *pipe_config)
5737 {
5738 struct drm_device *dev = intel_crtc->base.dev;
5739 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5740 int lane, link_bw, fdi_dotclock;
5741 bool setup_ok, needs_recompute = false;
5742
5743 retry:
5744 /* FDI is a binary signal running at ~2.7GHz, encoding
5745 * each output octet as 10 bits. The actual frequency
5746 * is stored as a divider into a 100MHz clock, and the
5747 * mode pixel clock is stored in units of 1KHz.
5748 * Hence the bw of each lane in terms of the mode signal
5749 * is:
5750 */
5751 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5752
5753 fdi_dotclock = adjusted_mode->crtc_clock;
5754
5755 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5756 pipe_config->pipe_bpp);
5757
5758 pipe_config->fdi_lanes = lane;
5759
5760 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5761 link_bw, &pipe_config->fdi_m_n);
5762
5763 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5764 intel_crtc->pipe, pipe_config);
5765 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5766 pipe_config->pipe_bpp -= 2*3;
5767 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5768 pipe_config->pipe_bpp);
5769 needs_recompute = true;
5770 pipe_config->bw_constrained = true;
5771
5772 goto retry;
5773 }
5774
5775 if (needs_recompute)
5776 return RETRY;
5777
5778 return setup_ok ? 0 : -EINVAL;
5779 }
5780
5781 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5782 struct intel_crtc_state *pipe_config)
5783 {
5784 pipe_config->ips_enabled = i915.enable_ips &&
5785 hsw_crtc_supports_ips(crtc) &&
5786 pipe_config->pipe_bpp <= 24;
5787 }
5788
5789 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5790 struct intel_crtc_state *pipe_config)
5791 {
5792 struct drm_device *dev = crtc->base.dev;
5793 struct drm_i915_private *dev_priv = dev->dev_private;
5794 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5795
5796 /* FIXME should check pixel clock limits on all platforms */
5797 if (INTEL_INFO(dev)->gen < 4) {
5798 int clock_limit =
5799 dev_priv->display.get_display_clock_speed(dev);
5800
5801 /*
5802 * Enable pixel doubling when the dot clock
5803 * is > 90% of the (display) core speed.
5804 *
5805 * GDG double wide on either pipe,
5806 * otherwise pipe A only.
5807 */
5808 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5809 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5810 clock_limit *= 2;
5811 pipe_config->double_wide = true;
5812 }
5813
5814 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5815 return -EINVAL;
5816 }
5817
5818 /*
5819 * Pipe horizontal size must be even in:
5820 * - DVO ganged mode
5821 * - LVDS dual channel mode
5822 * - Double wide pipe
5823 */
5824 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
5825 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5826 pipe_config->pipe_src_w &= ~1;
5827
5828 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5829 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5830 */
5831 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5832 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5833 return -EINVAL;
5834
5835 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5836 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5837 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5838 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5839 * for lvds. */
5840 pipe_config->pipe_bpp = 8*3;
5841 }
5842
5843 if (HAS_IPS(dev))
5844 hsw_compute_ips_config(crtc, pipe_config);
5845
5846 if (pipe_config->has_pch_encoder)
5847 return ironlake_fdi_compute_config(crtc, pipe_config);
5848
5849 return 0;
5850 }
5851
5852 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5853 {
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 u32 val;
5856 int divider;
5857
5858 if (dev_priv->hpll_freq == 0)
5859 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5860
5861 mutex_lock(&dev_priv->dpio_lock);
5862 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5863 mutex_unlock(&dev_priv->dpio_lock);
5864
5865 divider = val & DISPLAY_FREQUENCY_VALUES;
5866
5867 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5868 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5869 "cdclk change in progress\n");
5870
5871 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5872 }
5873
5874 static int i945_get_display_clock_speed(struct drm_device *dev)
5875 {
5876 return 400000;
5877 }
5878
5879 static int i915_get_display_clock_speed(struct drm_device *dev)
5880 {
5881 return 333000;
5882 }
5883
5884 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5885 {
5886 return 200000;
5887 }
5888
5889 static int pnv_get_display_clock_speed(struct drm_device *dev)
5890 {
5891 u16 gcfgc = 0;
5892
5893 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5894
5895 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5896 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5897 return 267000;
5898 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5899 return 333000;
5900 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5901 return 444000;
5902 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5903 return 200000;
5904 default:
5905 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5906 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5907 return 133000;
5908 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5909 return 167000;
5910 }
5911 }
5912
5913 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5914 {
5915 u16 gcfgc = 0;
5916
5917 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5918
5919 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5920 return 133000;
5921 else {
5922 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5923 case GC_DISPLAY_CLOCK_333_MHZ:
5924 return 333000;
5925 default:
5926 case GC_DISPLAY_CLOCK_190_200_MHZ:
5927 return 190000;
5928 }
5929 }
5930 }
5931
5932 static int i865_get_display_clock_speed(struct drm_device *dev)
5933 {
5934 return 266000;
5935 }
5936
5937 static int i855_get_display_clock_speed(struct drm_device *dev)
5938 {
5939 u16 hpllcc = 0;
5940 /* Assume that the hardware is in the high speed state. This
5941 * should be the default.
5942 */
5943 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5944 case GC_CLOCK_133_200:
5945 case GC_CLOCK_100_200:
5946 return 200000;
5947 case GC_CLOCK_166_250:
5948 return 250000;
5949 case GC_CLOCK_100_133:
5950 return 133000;
5951 }
5952
5953 /* Shouldn't happen */
5954 return 0;
5955 }
5956
5957 static int i830_get_display_clock_speed(struct drm_device *dev)
5958 {
5959 return 133000;
5960 }
5961
5962 static void
5963 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5964 {
5965 while (*num > DATA_LINK_M_N_MASK ||
5966 *den > DATA_LINK_M_N_MASK) {
5967 *num >>= 1;
5968 *den >>= 1;
5969 }
5970 }
5971
5972 static void compute_m_n(unsigned int m, unsigned int n,
5973 uint32_t *ret_m, uint32_t *ret_n)
5974 {
5975 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5976 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5977 intel_reduce_m_n_ratio(ret_m, ret_n);
5978 }
5979
5980 void
5981 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5982 int pixel_clock, int link_clock,
5983 struct intel_link_m_n *m_n)
5984 {
5985 m_n->tu = 64;
5986
5987 compute_m_n(bits_per_pixel * pixel_clock,
5988 link_clock * nlanes * 8,
5989 &m_n->gmch_m, &m_n->gmch_n);
5990
5991 compute_m_n(pixel_clock, link_clock,
5992 &m_n->link_m, &m_n->link_n);
5993 }
5994
5995 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5996 {
5997 if (i915.panel_use_ssc >= 0)
5998 return i915.panel_use_ssc != 0;
5999 return dev_priv->vbt.lvds_use_ssc
6000 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6001 }
6002
6003 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6004 int num_connectors)
6005 {
6006 struct drm_device *dev = crtc_state->base.crtc->dev;
6007 struct drm_i915_private *dev_priv = dev->dev_private;
6008 int refclk;
6009
6010 WARN_ON(!crtc_state->base.state);
6011
6012 if (IS_VALLEYVIEW(dev)) {
6013 refclk = 100000;
6014 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6015 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6016 refclk = dev_priv->vbt.lvds_ssc_freq;
6017 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6018 } else if (!IS_GEN2(dev)) {
6019 refclk = 96000;
6020 } else {
6021 refclk = 48000;
6022 }
6023
6024 return refclk;
6025 }
6026
6027 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6028 {
6029 return (1 << dpll->n) << 16 | dpll->m2;
6030 }
6031
6032 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6033 {
6034 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6035 }
6036
6037 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6038 struct intel_crtc_state *crtc_state,
6039 intel_clock_t *reduced_clock)
6040 {
6041 struct drm_device *dev = crtc->base.dev;
6042 u32 fp, fp2 = 0;
6043
6044 if (IS_PINEVIEW(dev)) {
6045 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6046 if (reduced_clock)
6047 fp2 = pnv_dpll_compute_fp(reduced_clock);
6048 } else {
6049 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6050 if (reduced_clock)
6051 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6052 }
6053
6054 crtc_state->dpll_hw_state.fp0 = fp;
6055
6056 crtc->lowfreq_avail = false;
6057 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6058 reduced_clock) {
6059 crtc_state->dpll_hw_state.fp1 = fp2;
6060 crtc->lowfreq_avail = true;
6061 } else {
6062 crtc_state->dpll_hw_state.fp1 = fp;
6063 }
6064 }
6065
6066 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6067 pipe)
6068 {
6069 u32 reg_val;
6070
6071 /*
6072 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6073 * and set it to a reasonable value instead.
6074 */
6075 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6076 reg_val &= 0xffffff00;
6077 reg_val |= 0x00000030;
6078 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6079
6080 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6081 reg_val &= 0x8cffffff;
6082 reg_val = 0x8c000000;
6083 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6084
6085 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6086 reg_val &= 0xffffff00;
6087 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6088
6089 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6090 reg_val &= 0x00ffffff;
6091 reg_val |= 0xb0000000;
6092 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6093 }
6094
6095 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6096 struct intel_link_m_n *m_n)
6097 {
6098 struct drm_device *dev = crtc->base.dev;
6099 struct drm_i915_private *dev_priv = dev->dev_private;
6100 int pipe = crtc->pipe;
6101
6102 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6103 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6104 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6105 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6106 }
6107
6108 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6109 struct intel_link_m_n *m_n,
6110 struct intel_link_m_n *m2_n2)
6111 {
6112 struct drm_device *dev = crtc->base.dev;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114 int pipe = crtc->pipe;
6115 enum transcoder transcoder = crtc->config->cpu_transcoder;
6116
6117 if (INTEL_INFO(dev)->gen >= 5) {
6118 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6119 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6120 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6121 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6122 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6123 * for gen < 8) and if DRRS is supported (to make sure the
6124 * registers are not unnecessarily accessed).
6125 */
6126 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6127 crtc->config->has_drrs) {
6128 I915_WRITE(PIPE_DATA_M2(transcoder),
6129 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6130 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6131 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6132 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6133 }
6134 } else {
6135 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6136 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6137 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6138 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6139 }
6140 }
6141
6142 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6143 {
6144 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6145
6146 if (m_n == M1_N1) {
6147 dp_m_n = &crtc->config->dp_m_n;
6148 dp_m2_n2 = &crtc->config->dp_m2_n2;
6149 } else if (m_n == M2_N2) {
6150
6151 /*
6152 * M2_N2 registers are not supported. Hence m2_n2 divider value
6153 * needs to be programmed into M1_N1.
6154 */
6155 dp_m_n = &crtc->config->dp_m2_n2;
6156 } else {
6157 DRM_ERROR("Unsupported divider value\n");
6158 return;
6159 }
6160
6161 if (crtc->config->has_pch_encoder)
6162 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6163 else
6164 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6165 }
6166
6167 static void vlv_update_pll(struct intel_crtc *crtc,
6168 struct intel_crtc_state *pipe_config)
6169 {
6170 u32 dpll, dpll_md;
6171
6172 /*
6173 * Enable DPIO clock input. We should never disable the reference
6174 * clock for pipe B, since VGA hotplug / manual detection depends
6175 * on it.
6176 */
6177 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6178 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6179 /* We should never disable this, set it here for state tracking */
6180 if (crtc->pipe == PIPE_B)
6181 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6182 dpll |= DPLL_VCO_ENABLE;
6183 pipe_config->dpll_hw_state.dpll = dpll;
6184
6185 dpll_md = (pipe_config->pixel_multiplier - 1)
6186 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6187 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6188 }
6189
6190 static void vlv_prepare_pll(struct intel_crtc *crtc,
6191 const struct intel_crtc_state *pipe_config)
6192 {
6193 struct drm_device *dev = crtc->base.dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 int pipe = crtc->pipe;
6196 u32 mdiv;
6197 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6198 u32 coreclk, reg_val;
6199
6200 mutex_lock(&dev_priv->dpio_lock);
6201
6202 bestn = pipe_config->dpll.n;
6203 bestm1 = pipe_config->dpll.m1;
6204 bestm2 = pipe_config->dpll.m2;
6205 bestp1 = pipe_config->dpll.p1;
6206 bestp2 = pipe_config->dpll.p2;
6207
6208 /* See eDP HDMI DPIO driver vbios notes doc */
6209
6210 /* PLL B needs special handling */
6211 if (pipe == PIPE_B)
6212 vlv_pllb_recal_opamp(dev_priv, pipe);
6213
6214 /* Set up Tx target for periodic Rcomp update */
6215 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6216
6217 /* Disable target IRef on PLL */
6218 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6219 reg_val &= 0x00ffffff;
6220 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6221
6222 /* Disable fast lock */
6223 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6224
6225 /* Set idtafcrecal before PLL is enabled */
6226 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6227 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6228 mdiv |= ((bestn << DPIO_N_SHIFT));
6229 mdiv |= (1 << DPIO_K_SHIFT);
6230
6231 /*
6232 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6233 * but we don't support that).
6234 * Note: don't use the DAC post divider as it seems unstable.
6235 */
6236 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6237 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6238
6239 mdiv |= DPIO_ENABLE_CALIBRATION;
6240 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6241
6242 /* Set HBR and RBR LPF coefficients */
6243 if (pipe_config->port_clock == 162000 ||
6244 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6245 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6247 0x009f0003);
6248 else
6249 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6250 0x00d0000f);
6251
6252 if (pipe_config->has_dp_encoder) {
6253 /* Use SSC source */
6254 if (pipe == PIPE_A)
6255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6256 0x0df40000);
6257 else
6258 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6259 0x0df70000);
6260 } else { /* HDMI or VGA */
6261 /* Use bend source */
6262 if (pipe == PIPE_A)
6263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6264 0x0df70000);
6265 else
6266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6267 0x0df40000);
6268 }
6269
6270 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6271 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6273 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6274 coreclk |= 0x01000000;
6275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6276
6277 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6278 mutex_unlock(&dev_priv->dpio_lock);
6279 }
6280
6281 static void chv_update_pll(struct intel_crtc *crtc,
6282 struct intel_crtc_state *pipe_config)
6283 {
6284 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6285 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6286 DPLL_VCO_ENABLE;
6287 if (crtc->pipe != PIPE_A)
6288 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6289
6290 pipe_config->dpll_hw_state.dpll_md =
6291 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6292 }
6293
6294 static void chv_prepare_pll(struct intel_crtc *crtc,
6295 const struct intel_crtc_state *pipe_config)
6296 {
6297 struct drm_device *dev = crtc->base.dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299 int pipe = crtc->pipe;
6300 int dpll_reg = DPLL(crtc->pipe);
6301 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6302 u32 loopfilter, tribuf_calcntr;
6303 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6304 u32 dpio_val;
6305 int vco;
6306
6307 bestn = pipe_config->dpll.n;
6308 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6309 bestm1 = pipe_config->dpll.m1;
6310 bestm2 = pipe_config->dpll.m2 >> 22;
6311 bestp1 = pipe_config->dpll.p1;
6312 bestp2 = pipe_config->dpll.p2;
6313 vco = pipe_config->dpll.vco;
6314 dpio_val = 0;
6315 loopfilter = 0;
6316
6317 /*
6318 * Enable Refclk and SSC
6319 */
6320 I915_WRITE(dpll_reg,
6321 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6322
6323 mutex_lock(&dev_priv->dpio_lock);
6324
6325 /* p1 and p2 divider */
6326 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6327 5 << DPIO_CHV_S1_DIV_SHIFT |
6328 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6329 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6330 1 << DPIO_CHV_K_DIV_SHIFT);
6331
6332 /* Feedback post-divider - m2 */
6333 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6334
6335 /* Feedback refclk divider - n and m1 */
6336 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6337 DPIO_CHV_M1_DIV_BY_2 |
6338 1 << DPIO_CHV_N_DIV_SHIFT);
6339
6340 /* M2 fraction division */
6341 if (bestm2_frac)
6342 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6343
6344 /* M2 fraction division enable */
6345 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6346 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6347 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6348 if (bestm2_frac)
6349 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6350 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6351
6352 /* Program digital lock detect threshold */
6353 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6354 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6355 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6356 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6357 if (!bestm2_frac)
6358 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6360
6361 /* Loop filter */
6362 if (vco == 5400000) {
6363 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6364 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6365 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6366 tribuf_calcntr = 0x9;
6367 } else if (vco <= 6200000) {
6368 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6369 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6370 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6371 tribuf_calcntr = 0x9;
6372 } else if (vco <= 6480000) {
6373 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6374 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6375 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6376 tribuf_calcntr = 0x8;
6377 } else {
6378 /* Not supported. Apply the same limits as in the max case */
6379 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6380 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6381 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6382 tribuf_calcntr = 0;
6383 }
6384 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6385
6386 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6387 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6388 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6389 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6390
6391 /* AFC Recal */
6392 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6393 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6394 DPIO_AFC_RECAL);
6395
6396 mutex_unlock(&dev_priv->dpio_lock);
6397 }
6398
6399 /**
6400 * vlv_force_pll_on - forcibly enable just the PLL
6401 * @dev_priv: i915 private structure
6402 * @pipe: pipe PLL to enable
6403 * @dpll: PLL configuration
6404 *
6405 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6406 * in cases where we need the PLL enabled even when @pipe is not going to
6407 * be enabled.
6408 */
6409 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6410 const struct dpll *dpll)
6411 {
6412 struct intel_crtc *crtc =
6413 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6414 struct intel_crtc_state pipe_config = {
6415 .base.crtc = &crtc->base,
6416 .pixel_multiplier = 1,
6417 .dpll = *dpll,
6418 };
6419
6420 if (IS_CHERRYVIEW(dev)) {
6421 chv_update_pll(crtc, &pipe_config);
6422 chv_prepare_pll(crtc, &pipe_config);
6423 chv_enable_pll(crtc, &pipe_config);
6424 } else {
6425 vlv_update_pll(crtc, &pipe_config);
6426 vlv_prepare_pll(crtc, &pipe_config);
6427 vlv_enable_pll(crtc, &pipe_config);
6428 }
6429 }
6430
6431 /**
6432 * vlv_force_pll_off - forcibly disable just the PLL
6433 * @dev_priv: i915 private structure
6434 * @pipe: pipe PLL to disable
6435 *
6436 * Disable the PLL for @pipe. To be used in cases where we need
6437 * the PLL enabled even when @pipe is not going to be enabled.
6438 */
6439 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6440 {
6441 if (IS_CHERRYVIEW(dev))
6442 chv_disable_pll(to_i915(dev), pipe);
6443 else
6444 vlv_disable_pll(to_i915(dev), pipe);
6445 }
6446
6447 static void i9xx_update_pll(struct intel_crtc *crtc,
6448 struct intel_crtc_state *crtc_state,
6449 intel_clock_t *reduced_clock,
6450 int num_connectors)
6451 {
6452 struct drm_device *dev = crtc->base.dev;
6453 struct drm_i915_private *dev_priv = dev->dev_private;
6454 u32 dpll;
6455 bool is_sdvo;
6456 struct dpll *clock = &crtc_state->dpll;
6457
6458 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6459
6460 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6461 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
6462
6463 dpll = DPLL_VGA_MODE_DIS;
6464
6465 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
6466 dpll |= DPLLB_MODE_LVDS;
6467 else
6468 dpll |= DPLLB_MODE_DAC_SERIAL;
6469
6470 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6471 dpll |= (crtc_state->pixel_multiplier - 1)
6472 << SDVO_MULTIPLIER_SHIFT_HIRES;
6473 }
6474
6475 if (is_sdvo)
6476 dpll |= DPLL_SDVO_HIGH_SPEED;
6477
6478 if (crtc_state->has_dp_encoder)
6479 dpll |= DPLL_SDVO_HIGH_SPEED;
6480
6481 /* compute bitmask from p1 value */
6482 if (IS_PINEVIEW(dev))
6483 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6484 else {
6485 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6486 if (IS_G4X(dev) && reduced_clock)
6487 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6488 }
6489 switch (clock->p2) {
6490 case 5:
6491 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6492 break;
6493 case 7:
6494 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6495 break;
6496 case 10:
6497 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6498 break;
6499 case 14:
6500 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6501 break;
6502 }
6503 if (INTEL_INFO(dev)->gen >= 4)
6504 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6505
6506 if (crtc_state->sdvo_tv_clock)
6507 dpll |= PLL_REF_INPUT_TVCLKINBC;
6508 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6509 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6510 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6511 else
6512 dpll |= PLL_REF_INPUT_DREFCLK;
6513
6514 dpll |= DPLL_VCO_ENABLE;
6515 crtc_state->dpll_hw_state.dpll = dpll;
6516
6517 if (INTEL_INFO(dev)->gen >= 4) {
6518 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6519 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6520 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6521 }
6522 }
6523
6524 static void i8xx_update_pll(struct intel_crtc *crtc,
6525 struct intel_crtc_state *crtc_state,
6526 intel_clock_t *reduced_clock,
6527 int num_connectors)
6528 {
6529 struct drm_device *dev = crtc->base.dev;
6530 struct drm_i915_private *dev_priv = dev->dev_private;
6531 u32 dpll;
6532 struct dpll *clock = &crtc_state->dpll;
6533
6534 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6535
6536 dpll = DPLL_VGA_MODE_DIS;
6537
6538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6539 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6540 } else {
6541 if (clock->p1 == 2)
6542 dpll |= PLL_P1_DIVIDE_BY_TWO;
6543 else
6544 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6545 if (clock->p2 == 4)
6546 dpll |= PLL_P2_DIVIDE_BY_4;
6547 }
6548
6549 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
6550 dpll |= DPLL_DVO_2X_MODE;
6551
6552 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6553 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6554 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6555 else
6556 dpll |= PLL_REF_INPUT_DREFCLK;
6557
6558 dpll |= DPLL_VCO_ENABLE;
6559 crtc_state->dpll_hw_state.dpll = dpll;
6560 }
6561
6562 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6563 {
6564 struct drm_device *dev = intel_crtc->base.dev;
6565 struct drm_i915_private *dev_priv = dev->dev_private;
6566 enum pipe pipe = intel_crtc->pipe;
6567 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6568 struct drm_display_mode *adjusted_mode =
6569 &intel_crtc->config->base.adjusted_mode;
6570 uint32_t crtc_vtotal, crtc_vblank_end;
6571 int vsyncshift = 0;
6572
6573 /* We need to be careful not to changed the adjusted mode, for otherwise
6574 * the hw state checker will get angry at the mismatch. */
6575 crtc_vtotal = adjusted_mode->crtc_vtotal;
6576 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6577
6578 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6579 /* the chip adds 2 halflines automatically */
6580 crtc_vtotal -= 1;
6581 crtc_vblank_end -= 1;
6582
6583 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6584 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6585 else
6586 vsyncshift = adjusted_mode->crtc_hsync_start -
6587 adjusted_mode->crtc_htotal / 2;
6588 if (vsyncshift < 0)
6589 vsyncshift += adjusted_mode->crtc_htotal;
6590 }
6591
6592 if (INTEL_INFO(dev)->gen > 3)
6593 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6594
6595 I915_WRITE(HTOTAL(cpu_transcoder),
6596 (adjusted_mode->crtc_hdisplay - 1) |
6597 ((adjusted_mode->crtc_htotal - 1) << 16));
6598 I915_WRITE(HBLANK(cpu_transcoder),
6599 (adjusted_mode->crtc_hblank_start - 1) |
6600 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6601 I915_WRITE(HSYNC(cpu_transcoder),
6602 (adjusted_mode->crtc_hsync_start - 1) |
6603 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6604
6605 I915_WRITE(VTOTAL(cpu_transcoder),
6606 (adjusted_mode->crtc_vdisplay - 1) |
6607 ((crtc_vtotal - 1) << 16));
6608 I915_WRITE(VBLANK(cpu_transcoder),
6609 (adjusted_mode->crtc_vblank_start - 1) |
6610 ((crtc_vblank_end - 1) << 16));
6611 I915_WRITE(VSYNC(cpu_transcoder),
6612 (adjusted_mode->crtc_vsync_start - 1) |
6613 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6614
6615 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6616 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6617 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6618 * bits. */
6619 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6620 (pipe == PIPE_B || pipe == PIPE_C))
6621 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6622
6623 /* pipesrc controls the size that is scaled from, which should
6624 * always be the user's requested size.
6625 */
6626 I915_WRITE(PIPESRC(pipe),
6627 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6628 (intel_crtc->config->pipe_src_h - 1));
6629 }
6630
6631 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6632 struct intel_crtc_state *pipe_config)
6633 {
6634 struct drm_device *dev = crtc->base.dev;
6635 struct drm_i915_private *dev_priv = dev->dev_private;
6636 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6637 uint32_t tmp;
6638
6639 tmp = I915_READ(HTOTAL(cpu_transcoder));
6640 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6641 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6642 tmp = I915_READ(HBLANK(cpu_transcoder));
6643 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6644 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6645 tmp = I915_READ(HSYNC(cpu_transcoder));
6646 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6647 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6648
6649 tmp = I915_READ(VTOTAL(cpu_transcoder));
6650 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6651 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6652 tmp = I915_READ(VBLANK(cpu_transcoder));
6653 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6654 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6655 tmp = I915_READ(VSYNC(cpu_transcoder));
6656 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6657 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6658
6659 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6660 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6661 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6662 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6663 }
6664
6665 tmp = I915_READ(PIPESRC(crtc->pipe));
6666 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6667 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6668
6669 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6670 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6671 }
6672
6673 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6674 struct intel_crtc_state *pipe_config)
6675 {
6676 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6677 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6678 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6679 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6680
6681 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6682 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6683 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6684 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6685
6686 mode->flags = pipe_config->base.adjusted_mode.flags;
6687
6688 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6689 mode->flags |= pipe_config->base.adjusted_mode.flags;
6690 }
6691
6692 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6693 {
6694 struct drm_device *dev = intel_crtc->base.dev;
6695 struct drm_i915_private *dev_priv = dev->dev_private;
6696 uint32_t pipeconf;
6697
6698 pipeconf = 0;
6699
6700 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6701 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6702 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6703
6704 if (intel_crtc->config->double_wide)
6705 pipeconf |= PIPECONF_DOUBLE_WIDE;
6706
6707 /* only g4x and later have fancy bpc/dither controls */
6708 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6709 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6710 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6711 pipeconf |= PIPECONF_DITHER_EN |
6712 PIPECONF_DITHER_TYPE_SP;
6713
6714 switch (intel_crtc->config->pipe_bpp) {
6715 case 18:
6716 pipeconf |= PIPECONF_6BPC;
6717 break;
6718 case 24:
6719 pipeconf |= PIPECONF_8BPC;
6720 break;
6721 case 30:
6722 pipeconf |= PIPECONF_10BPC;
6723 break;
6724 default:
6725 /* Case prevented by intel_choose_pipe_bpp_dither. */
6726 BUG();
6727 }
6728 }
6729
6730 if (HAS_PIPE_CXSR(dev)) {
6731 if (intel_crtc->lowfreq_avail) {
6732 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6733 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6734 } else {
6735 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6736 }
6737 }
6738
6739 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6740 if (INTEL_INFO(dev)->gen < 4 ||
6741 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6742 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6743 else
6744 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6745 } else
6746 pipeconf |= PIPECONF_PROGRESSIVE;
6747
6748 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6749 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6750
6751 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6752 POSTING_READ(PIPECONF(intel_crtc->pipe));
6753 }
6754
6755 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6756 struct intel_crtc_state *crtc_state)
6757 {
6758 struct drm_device *dev = crtc->base.dev;
6759 struct drm_i915_private *dev_priv = dev->dev_private;
6760 int refclk, num_connectors = 0;
6761 intel_clock_t clock, reduced_clock;
6762 bool ok, has_reduced_clock = false;
6763 bool is_lvds = false, is_dsi = false;
6764 struct intel_encoder *encoder;
6765 const intel_limit_t *limit;
6766 struct drm_atomic_state *state = crtc_state->base.state;
6767 struct drm_connector_state *connector_state;
6768 int i;
6769
6770 for (i = 0; i < state->num_connector; i++) {
6771 if (!state->connectors[i])
6772 continue;
6773
6774 connector_state = state->connector_states[i];
6775 if (connector_state->crtc != &crtc->base)
6776 continue;
6777
6778 encoder = to_intel_encoder(connector_state->best_encoder);
6779
6780 switch (encoder->type) {
6781 case INTEL_OUTPUT_LVDS:
6782 is_lvds = true;
6783 break;
6784 case INTEL_OUTPUT_DSI:
6785 is_dsi = true;
6786 break;
6787 default:
6788 break;
6789 }
6790
6791 num_connectors++;
6792 }
6793
6794 if (is_dsi)
6795 return 0;
6796
6797 if (!crtc_state->clock_set) {
6798 refclk = i9xx_get_refclk(crtc_state, num_connectors);
6799
6800 /*
6801 * Returns a set of divisors for the desired target clock with
6802 * the given refclk, or FALSE. The returned values represent
6803 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6804 * 2) / p1 / p2.
6805 */
6806 limit = intel_limit(crtc_state, refclk);
6807 ok = dev_priv->display.find_dpll(limit, crtc_state,
6808 crtc_state->port_clock,
6809 refclk, NULL, &clock);
6810 if (!ok) {
6811 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6812 return -EINVAL;
6813 }
6814
6815 if (is_lvds && dev_priv->lvds_downclock_avail) {
6816 /*
6817 * Ensure we match the reduced clock's P to the target
6818 * clock. If the clocks don't match, we can't switch
6819 * the display clock by using the FP0/FP1. In such case
6820 * we will disable the LVDS downclock feature.
6821 */
6822 has_reduced_clock =
6823 dev_priv->display.find_dpll(limit, crtc_state,
6824 dev_priv->lvds_downclock,
6825 refclk, &clock,
6826 &reduced_clock);
6827 }
6828 /* Compat-code for transition, will disappear. */
6829 crtc_state->dpll.n = clock.n;
6830 crtc_state->dpll.m1 = clock.m1;
6831 crtc_state->dpll.m2 = clock.m2;
6832 crtc_state->dpll.p1 = clock.p1;
6833 crtc_state->dpll.p2 = clock.p2;
6834 }
6835
6836 if (IS_GEN2(dev)) {
6837 i8xx_update_pll(crtc, crtc_state,
6838 has_reduced_clock ? &reduced_clock : NULL,
6839 num_connectors);
6840 } else if (IS_CHERRYVIEW(dev)) {
6841 chv_update_pll(crtc, crtc_state);
6842 } else if (IS_VALLEYVIEW(dev)) {
6843 vlv_update_pll(crtc, crtc_state);
6844 } else {
6845 i9xx_update_pll(crtc, crtc_state,
6846 has_reduced_clock ? &reduced_clock : NULL,
6847 num_connectors);
6848 }
6849
6850 return 0;
6851 }
6852
6853 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6854 struct intel_crtc_state *pipe_config)
6855 {
6856 struct drm_device *dev = crtc->base.dev;
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 uint32_t tmp;
6859
6860 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6861 return;
6862
6863 tmp = I915_READ(PFIT_CONTROL);
6864 if (!(tmp & PFIT_ENABLE))
6865 return;
6866
6867 /* Check whether the pfit is attached to our pipe. */
6868 if (INTEL_INFO(dev)->gen < 4) {
6869 if (crtc->pipe != PIPE_B)
6870 return;
6871 } else {
6872 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6873 return;
6874 }
6875
6876 pipe_config->gmch_pfit.control = tmp;
6877 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6878 if (INTEL_INFO(dev)->gen < 5)
6879 pipe_config->gmch_pfit.lvds_border_bits =
6880 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6881 }
6882
6883 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6884 struct intel_crtc_state *pipe_config)
6885 {
6886 struct drm_device *dev = crtc->base.dev;
6887 struct drm_i915_private *dev_priv = dev->dev_private;
6888 int pipe = pipe_config->cpu_transcoder;
6889 intel_clock_t clock;
6890 u32 mdiv;
6891 int refclk = 100000;
6892
6893 /* In case of MIPI DPLL will not even be used */
6894 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6895 return;
6896
6897 mutex_lock(&dev_priv->dpio_lock);
6898 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6899 mutex_unlock(&dev_priv->dpio_lock);
6900
6901 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6902 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6903 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6904 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6905 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6906
6907 vlv_clock(refclk, &clock);
6908
6909 /* clock.dot is the fast clock */
6910 pipe_config->port_clock = clock.dot / 5;
6911 }
6912
6913 static void
6914 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6915 struct intel_initial_plane_config *plane_config)
6916 {
6917 struct drm_device *dev = crtc->base.dev;
6918 struct drm_i915_private *dev_priv = dev->dev_private;
6919 u32 val, base, offset;
6920 int pipe = crtc->pipe, plane = crtc->plane;
6921 int fourcc, pixel_format;
6922 unsigned int aligned_height;
6923 struct drm_framebuffer *fb;
6924 struct intel_framebuffer *intel_fb;
6925
6926 val = I915_READ(DSPCNTR(plane));
6927 if (!(val & DISPLAY_PLANE_ENABLE))
6928 return;
6929
6930 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6931 if (!intel_fb) {
6932 DRM_DEBUG_KMS("failed to alloc fb\n");
6933 return;
6934 }
6935
6936 fb = &intel_fb->base;
6937
6938 if (INTEL_INFO(dev)->gen >= 4) {
6939 if (val & DISPPLANE_TILED) {
6940 plane_config->tiling = I915_TILING_X;
6941 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6942 }
6943 }
6944
6945 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6946 fourcc = i9xx_format_to_fourcc(pixel_format);
6947 fb->pixel_format = fourcc;
6948 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6949
6950 if (INTEL_INFO(dev)->gen >= 4) {
6951 if (plane_config->tiling)
6952 offset = I915_READ(DSPTILEOFF(plane));
6953 else
6954 offset = I915_READ(DSPLINOFF(plane));
6955 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6956 } else {
6957 base = I915_READ(DSPADDR(plane));
6958 }
6959 plane_config->base = base;
6960
6961 val = I915_READ(PIPESRC(pipe));
6962 fb->width = ((val >> 16) & 0xfff) + 1;
6963 fb->height = ((val >> 0) & 0xfff) + 1;
6964
6965 val = I915_READ(DSPSTRIDE(pipe));
6966 fb->pitches[0] = val & 0xffffffc0;
6967
6968 aligned_height = intel_fb_align_height(dev, fb->height,
6969 fb->pixel_format,
6970 fb->modifier[0]);
6971
6972 plane_config->size = fb->pitches[0] * aligned_height;
6973
6974 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6975 pipe_name(pipe), plane, fb->width, fb->height,
6976 fb->bits_per_pixel, base, fb->pitches[0],
6977 plane_config->size);
6978
6979 plane_config->fb = intel_fb;
6980 }
6981
6982 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6983 struct intel_crtc_state *pipe_config)
6984 {
6985 struct drm_device *dev = crtc->base.dev;
6986 struct drm_i915_private *dev_priv = dev->dev_private;
6987 int pipe = pipe_config->cpu_transcoder;
6988 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6989 intel_clock_t clock;
6990 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6991 int refclk = 100000;
6992
6993 mutex_lock(&dev_priv->dpio_lock);
6994 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6995 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6996 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6997 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6998 mutex_unlock(&dev_priv->dpio_lock);
6999
7000 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7001 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7002 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7003 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7004 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7005
7006 chv_clock(refclk, &clock);
7007
7008 /* clock.dot is the fast clock */
7009 pipe_config->port_clock = clock.dot / 5;
7010 }
7011
7012 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7013 struct intel_crtc_state *pipe_config)
7014 {
7015 struct drm_device *dev = crtc->base.dev;
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 uint32_t tmp;
7018
7019 if (!intel_display_power_is_enabled(dev_priv,
7020 POWER_DOMAIN_PIPE(crtc->pipe)))
7021 return false;
7022
7023 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7024 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7025
7026 tmp = I915_READ(PIPECONF(crtc->pipe));
7027 if (!(tmp & PIPECONF_ENABLE))
7028 return false;
7029
7030 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7031 switch (tmp & PIPECONF_BPC_MASK) {
7032 case PIPECONF_6BPC:
7033 pipe_config->pipe_bpp = 18;
7034 break;
7035 case PIPECONF_8BPC:
7036 pipe_config->pipe_bpp = 24;
7037 break;
7038 case PIPECONF_10BPC:
7039 pipe_config->pipe_bpp = 30;
7040 break;
7041 default:
7042 break;
7043 }
7044 }
7045
7046 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7047 pipe_config->limited_color_range = true;
7048
7049 if (INTEL_INFO(dev)->gen < 4)
7050 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7051
7052 intel_get_pipe_timings(crtc, pipe_config);
7053
7054 i9xx_get_pfit_config(crtc, pipe_config);
7055
7056 if (INTEL_INFO(dev)->gen >= 4) {
7057 tmp = I915_READ(DPLL_MD(crtc->pipe));
7058 pipe_config->pixel_multiplier =
7059 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7060 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7061 pipe_config->dpll_hw_state.dpll_md = tmp;
7062 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7063 tmp = I915_READ(DPLL(crtc->pipe));
7064 pipe_config->pixel_multiplier =
7065 ((tmp & SDVO_MULTIPLIER_MASK)
7066 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7067 } else {
7068 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7069 * port and will be fixed up in the encoder->get_config
7070 * function. */
7071 pipe_config->pixel_multiplier = 1;
7072 }
7073 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7074 if (!IS_VALLEYVIEW(dev)) {
7075 /*
7076 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7077 * on 830. Filter it out here so that we don't
7078 * report errors due to that.
7079 */
7080 if (IS_I830(dev))
7081 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7082
7083 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7084 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7085 } else {
7086 /* Mask out read-only status bits. */
7087 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7088 DPLL_PORTC_READY_MASK |
7089 DPLL_PORTB_READY_MASK);
7090 }
7091
7092 if (IS_CHERRYVIEW(dev))
7093 chv_crtc_clock_get(crtc, pipe_config);
7094 else if (IS_VALLEYVIEW(dev))
7095 vlv_crtc_clock_get(crtc, pipe_config);
7096 else
7097 i9xx_crtc_clock_get(crtc, pipe_config);
7098
7099 return true;
7100 }
7101
7102 static void ironlake_init_pch_refclk(struct drm_device *dev)
7103 {
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 struct intel_encoder *encoder;
7106 u32 val, final;
7107 bool has_lvds = false;
7108 bool has_cpu_edp = false;
7109 bool has_panel = false;
7110 bool has_ck505 = false;
7111 bool can_ssc = false;
7112
7113 /* We need to take the global config into account */
7114 for_each_intel_encoder(dev, encoder) {
7115 switch (encoder->type) {
7116 case INTEL_OUTPUT_LVDS:
7117 has_panel = true;
7118 has_lvds = true;
7119 break;
7120 case INTEL_OUTPUT_EDP:
7121 has_panel = true;
7122 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7123 has_cpu_edp = true;
7124 break;
7125 default:
7126 break;
7127 }
7128 }
7129
7130 if (HAS_PCH_IBX(dev)) {
7131 has_ck505 = dev_priv->vbt.display_clock_mode;
7132 can_ssc = has_ck505;
7133 } else {
7134 has_ck505 = false;
7135 can_ssc = true;
7136 }
7137
7138 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7139 has_panel, has_lvds, has_ck505);
7140
7141 /* Ironlake: try to setup display ref clock before DPLL
7142 * enabling. This is only under driver's control after
7143 * PCH B stepping, previous chipset stepping should be
7144 * ignoring this setting.
7145 */
7146 val = I915_READ(PCH_DREF_CONTROL);
7147
7148 /* As we must carefully and slowly disable/enable each source in turn,
7149 * compute the final state we want first and check if we need to
7150 * make any changes at all.
7151 */
7152 final = val;
7153 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7154 if (has_ck505)
7155 final |= DREF_NONSPREAD_CK505_ENABLE;
7156 else
7157 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7158
7159 final &= ~DREF_SSC_SOURCE_MASK;
7160 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7161 final &= ~DREF_SSC1_ENABLE;
7162
7163 if (has_panel) {
7164 final |= DREF_SSC_SOURCE_ENABLE;
7165
7166 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7167 final |= DREF_SSC1_ENABLE;
7168
7169 if (has_cpu_edp) {
7170 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7171 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7172 else
7173 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7174 } else
7175 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7176 } else {
7177 final |= DREF_SSC_SOURCE_DISABLE;
7178 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7179 }
7180
7181 if (final == val)
7182 return;
7183
7184 /* Always enable nonspread source */
7185 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7186
7187 if (has_ck505)
7188 val |= DREF_NONSPREAD_CK505_ENABLE;
7189 else
7190 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7191
7192 if (has_panel) {
7193 val &= ~DREF_SSC_SOURCE_MASK;
7194 val |= DREF_SSC_SOURCE_ENABLE;
7195
7196 /* SSC must be turned on before enabling the CPU output */
7197 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7198 DRM_DEBUG_KMS("Using SSC on panel\n");
7199 val |= DREF_SSC1_ENABLE;
7200 } else
7201 val &= ~DREF_SSC1_ENABLE;
7202
7203 /* Get SSC going before enabling the outputs */
7204 I915_WRITE(PCH_DREF_CONTROL, val);
7205 POSTING_READ(PCH_DREF_CONTROL);
7206 udelay(200);
7207
7208 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7209
7210 /* Enable CPU source on CPU attached eDP */
7211 if (has_cpu_edp) {
7212 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7213 DRM_DEBUG_KMS("Using SSC on eDP\n");
7214 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7215 } else
7216 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7217 } else
7218 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7219
7220 I915_WRITE(PCH_DREF_CONTROL, val);
7221 POSTING_READ(PCH_DREF_CONTROL);
7222 udelay(200);
7223 } else {
7224 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7225
7226 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7227
7228 /* Turn off CPU output */
7229 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7230
7231 I915_WRITE(PCH_DREF_CONTROL, val);
7232 POSTING_READ(PCH_DREF_CONTROL);
7233 udelay(200);
7234
7235 /* Turn off the SSC source */
7236 val &= ~DREF_SSC_SOURCE_MASK;
7237 val |= DREF_SSC_SOURCE_DISABLE;
7238
7239 /* Turn off SSC1 */
7240 val &= ~DREF_SSC1_ENABLE;
7241
7242 I915_WRITE(PCH_DREF_CONTROL, val);
7243 POSTING_READ(PCH_DREF_CONTROL);
7244 udelay(200);
7245 }
7246
7247 BUG_ON(val != final);
7248 }
7249
7250 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7251 {
7252 uint32_t tmp;
7253
7254 tmp = I915_READ(SOUTH_CHICKEN2);
7255 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7256 I915_WRITE(SOUTH_CHICKEN2, tmp);
7257
7258 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7259 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7260 DRM_ERROR("FDI mPHY reset assert timeout\n");
7261
7262 tmp = I915_READ(SOUTH_CHICKEN2);
7263 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7264 I915_WRITE(SOUTH_CHICKEN2, tmp);
7265
7266 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7267 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7268 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7269 }
7270
7271 /* WaMPhyProgramming:hsw */
7272 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7273 {
7274 uint32_t tmp;
7275
7276 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7277 tmp &= ~(0xFF << 24);
7278 tmp |= (0x12 << 24);
7279 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7280
7281 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7282 tmp |= (1 << 11);
7283 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7284
7285 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7286 tmp |= (1 << 11);
7287 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7288
7289 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7290 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7291 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7292
7293 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7294 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7295 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7296
7297 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7298 tmp &= ~(7 << 13);
7299 tmp |= (5 << 13);
7300 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7301
7302 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7303 tmp &= ~(7 << 13);
7304 tmp |= (5 << 13);
7305 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7306
7307 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7308 tmp &= ~0xFF;
7309 tmp |= 0x1C;
7310 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7311
7312 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7313 tmp &= ~0xFF;
7314 tmp |= 0x1C;
7315 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7316
7317 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7318 tmp &= ~(0xFF << 16);
7319 tmp |= (0x1C << 16);
7320 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7321
7322 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7323 tmp &= ~(0xFF << 16);
7324 tmp |= (0x1C << 16);
7325 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7326
7327 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7328 tmp |= (1 << 27);
7329 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7330
7331 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7332 tmp |= (1 << 27);
7333 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7334
7335 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7336 tmp &= ~(0xF << 28);
7337 tmp |= (4 << 28);
7338 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7339
7340 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7341 tmp &= ~(0xF << 28);
7342 tmp |= (4 << 28);
7343 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7344 }
7345
7346 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7347 * Programming" based on the parameters passed:
7348 * - Sequence to enable CLKOUT_DP
7349 * - Sequence to enable CLKOUT_DP without spread
7350 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7351 */
7352 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7353 bool with_fdi)
7354 {
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 uint32_t reg, tmp;
7357
7358 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7359 with_spread = true;
7360 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7361 with_fdi, "LP PCH doesn't have FDI\n"))
7362 with_fdi = false;
7363
7364 mutex_lock(&dev_priv->dpio_lock);
7365
7366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7367 tmp &= ~SBI_SSCCTL_DISABLE;
7368 tmp |= SBI_SSCCTL_PATHALT;
7369 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7370
7371 udelay(24);
7372
7373 if (with_spread) {
7374 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7375 tmp &= ~SBI_SSCCTL_PATHALT;
7376 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7377
7378 if (with_fdi) {
7379 lpt_reset_fdi_mphy(dev_priv);
7380 lpt_program_fdi_mphy(dev_priv);
7381 }
7382 }
7383
7384 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7385 SBI_GEN0 : SBI_DBUFF0;
7386 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7387 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7388 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7389
7390 mutex_unlock(&dev_priv->dpio_lock);
7391 }
7392
7393 /* Sequence to disable CLKOUT_DP */
7394 static void lpt_disable_clkout_dp(struct drm_device *dev)
7395 {
7396 struct drm_i915_private *dev_priv = dev->dev_private;
7397 uint32_t reg, tmp;
7398
7399 mutex_lock(&dev_priv->dpio_lock);
7400
7401 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7402 SBI_GEN0 : SBI_DBUFF0;
7403 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7404 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7405 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7406
7407 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7408 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7409 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7410 tmp |= SBI_SSCCTL_PATHALT;
7411 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7412 udelay(32);
7413 }
7414 tmp |= SBI_SSCCTL_DISABLE;
7415 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7416 }
7417
7418 mutex_unlock(&dev_priv->dpio_lock);
7419 }
7420
7421 static void lpt_init_pch_refclk(struct drm_device *dev)
7422 {
7423 struct intel_encoder *encoder;
7424 bool has_vga = false;
7425
7426 for_each_intel_encoder(dev, encoder) {
7427 switch (encoder->type) {
7428 case INTEL_OUTPUT_ANALOG:
7429 has_vga = true;
7430 break;
7431 default:
7432 break;
7433 }
7434 }
7435
7436 if (has_vga)
7437 lpt_enable_clkout_dp(dev, true, true);
7438 else
7439 lpt_disable_clkout_dp(dev);
7440 }
7441
7442 /*
7443 * Initialize reference clocks when the driver loads
7444 */
7445 void intel_init_pch_refclk(struct drm_device *dev)
7446 {
7447 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7448 ironlake_init_pch_refclk(dev);
7449 else if (HAS_PCH_LPT(dev))
7450 lpt_init_pch_refclk(dev);
7451 }
7452
7453 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
7454 {
7455 struct drm_device *dev = crtc_state->base.crtc->dev;
7456 struct drm_i915_private *dev_priv = dev->dev_private;
7457 struct drm_atomic_state *state = crtc_state->base.state;
7458 struct drm_connector_state *connector_state;
7459 struct intel_encoder *encoder;
7460 int num_connectors = 0, i;
7461 bool is_lvds = false;
7462
7463 for (i = 0; i < state->num_connector; i++) {
7464 if (!state->connectors[i])
7465 continue;
7466
7467 connector_state = state->connector_states[i];
7468 if (connector_state->crtc != crtc_state->base.crtc)
7469 continue;
7470
7471 encoder = to_intel_encoder(connector_state->best_encoder);
7472
7473 switch (encoder->type) {
7474 case INTEL_OUTPUT_LVDS:
7475 is_lvds = true;
7476 break;
7477 default:
7478 break;
7479 }
7480 num_connectors++;
7481 }
7482
7483 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7484 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7485 dev_priv->vbt.lvds_ssc_freq);
7486 return dev_priv->vbt.lvds_ssc_freq;
7487 }
7488
7489 return 120000;
7490 }
7491
7492 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7493 {
7494 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7496 int pipe = intel_crtc->pipe;
7497 uint32_t val;
7498
7499 val = 0;
7500
7501 switch (intel_crtc->config->pipe_bpp) {
7502 case 18:
7503 val |= PIPECONF_6BPC;
7504 break;
7505 case 24:
7506 val |= PIPECONF_8BPC;
7507 break;
7508 case 30:
7509 val |= PIPECONF_10BPC;
7510 break;
7511 case 36:
7512 val |= PIPECONF_12BPC;
7513 break;
7514 default:
7515 /* Case prevented by intel_choose_pipe_bpp_dither. */
7516 BUG();
7517 }
7518
7519 if (intel_crtc->config->dither)
7520 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7521
7522 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7523 val |= PIPECONF_INTERLACED_ILK;
7524 else
7525 val |= PIPECONF_PROGRESSIVE;
7526
7527 if (intel_crtc->config->limited_color_range)
7528 val |= PIPECONF_COLOR_RANGE_SELECT;
7529
7530 I915_WRITE(PIPECONF(pipe), val);
7531 POSTING_READ(PIPECONF(pipe));
7532 }
7533
7534 /*
7535 * Set up the pipe CSC unit.
7536 *
7537 * Currently only full range RGB to limited range RGB conversion
7538 * is supported, but eventually this should handle various
7539 * RGB<->YCbCr scenarios as well.
7540 */
7541 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7542 {
7543 struct drm_device *dev = crtc->dev;
7544 struct drm_i915_private *dev_priv = dev->dev_private;
7545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7546 int pipe = intel_crtc->pipe;
7547 uint16_t coeff = 0x7800; /* 1.0 */
7548
7549 /*
7550 * TODO: Check what kind of values actually come out of the pipe
7551 * with these coeff/postoff values and adjust to get the best
7552 * accuracy. Perhaps we even need to take the bpc value into
7553 * consideration.
7554 */
7555
7556 if (intel_crtc->config->limited_color_range)
7557 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7558
7559 /*
7560 * GY/GU and RY/RU should be the other way around according
7561 * to BSpec, but reality doesn't agree. Just set them up in
7562 * a way that results in the correct picture.
7563 */
7564 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7565 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7566
7567 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7568 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7569
7570 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7571 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7572
7573 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7574 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7575 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7576
7577 if (INTEL_INFO(dev)->gen > 6) {
7578 uint16_t postoff = 0;
7579
7580 if (intel_crtc->config->limited_color_range)
7581 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7582
7583 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7584 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7585 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7586
7587 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7588 } else {
7589 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7590
7591 if (intel_crtc->config->limited_color_range)
7592 mode |= CSC_BLACK_SCREEN_OFFSET;
7593
7594 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7595 }
7596 }
7597
7598 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7599 {
7600 struct drm_device *dev = crtc->dev;
7601 struct drm_i915_private *dev_priv = dev->dev_private;
7602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7603 enum pipe pipe = intel_crtc->pipe;
7604 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7605 uint32_t val;
7606
7607 val = 0;
7608
7609 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7610 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7611
7612 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7613 val |= PIPECONF_INTERLACED_ILK;
7614 else
7615 val |= PIPECONF_PROGRESSIVE;
7616
7617 I915_WRITE(PIPECONF(cpu_transcoder), val);
7618 POSTING_READ(PIPECONF(cpu_transcoder));
7619
7620 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7621 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7622
7623 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7624 val = 0;
7625
7626 switch (intel_crtc->config->pipe_bpp) {
7627 case 18:
7628 val |= PIPEMISC_DITHER_6_BPC;
7629 break;
7630 case 24:
7631 val |= PIPEMISC_DITHER_8_BPC;
7632 break;
7633 case 30:
7634 val |= PIPEMISC_DITHER_10_BPC;
7635 break;
7636 case 36:
7637 val |= PIPEMISC_DITHER_12_BPC;
7638 break;
7639 default:
7640 /* Case prevented by pipe_config_set_bpp. */
7641 BUG();
7642 }
7643
7644 if (intel_crtc->config->dither)
7645 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7646
7647 I915_WRITE(PIPEMISC(pipe), val);
7648 }
7649 }
7650
7651 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7652 struct intel_crtc_state *crtc_state,
7653 intel_clock_t *clock,
7654 bool *has_reduced_clock,
7655 intel_clock_t *reduced_clock)
7656 {
7657 struct drm_device *dev = crtc->dev;
7658 struct drm_i915_private *dev_priv = dev->dev_private;
7659 int refclk;
7660 const intel_limit_t *limit;
7661 bool ret, is_lvds = false;
7662
7663 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
7664
7665 refclk = ironlake_get_refclk(crtc_state);
7666
7667 /*
7668 * Returns a set of divisors for the desired target clock with the given
7669 * refclk, or FALSE. The returned values represent the clock equation:
7670 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7671 */
7672 limit = intel_limit(crtc_state, refclk);
7673 ret = dev_priv->display.find_dpll(limit, crtc_state,
7674 crtc_state->port_clock,
7675 refclk, NULL, clock);
7676 if (!ret)
7677 return false;
7678
7679 if (is_lvds && dev_priv->lvds_downclock_avail) {
7680 /*
7681 * Ensure we match the reduced clock's P to the target clock.
7682 * If the clocks don't match, we can't switch the display clock
7683 * by using the FP0/FP1. In such case we will disable the LVDS
7684 * downclock feature.
7685 */
7686 *has_reduced_clock =
7687 dev_priv->display.find_dpll(limit, crtc_state,
7688 dev_priv->lvds_downclock,
7689 refclk, clock,
7690 reduced_clock);
7691 }
7692
7693 return true;
7694 }
7695
7696 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7697 {
7698 /*
7699 * Account for spread spectrum to avoid
7700 * oversubscribing the link. Max center spread
7701 * is 2.5%; use 5% for safety's sake.
7702 */
7703 u32 bps = target_clock * bpp * 21 / 20;
7704 return DIV_ROUND_UP(bps, link_bw * 8);
7705 }
7706
7707 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7708 {
7709 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7710 }
7711
7712 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7713 struct intel_crtc_state *crtc_state,
7714 u32 *fp,
7715 intel_clock_t *reduced_clock, u32 *fp2)
7716 {
7717 struct drm_crtc *crtc = &intel_crtc->base;
7718 struct drm_device *dev = crtc->dev;
7719 struct drm_i915_private *dev_priv = dev->dev_private;
7720 struct drm_atomic_state *state = crtc_state->base.state;
7721 struct drm_connector_state *connector_state;
7722 struct intel_encoder *encoder;
7723 uint32_t dpll;
7724 int factor, num_connectors = 0, i;
7725 bool is_lvds = false, is_sdvo = false;
7726
7727 for (i = 0; i < state->num_connector; i++) {
7728 if (!state->connectors[i])
7729 continue;
7730
7731 connector_state = state->connector_states[i];
7732 if (connector_state->crtc != crtc_state->base.crtc)
7733 continue;
7734
7735 encoder = to_intel_encoder(connector_state->best_encoder);
7736
7737 switch (encoder->type) {
7738 case INTEL_OUTPUT_LVDS:
7739 is_lvds = true;
7740 break;
7741 case INTEL_OUTPUT_SDVO:
7742 case INTEL_OUTPUT_HDMI:
7743 is_sdvo = true;
7744 break;
7745 default:
7746 break;
7747 }
7748
7749 num_connectors++;
7750 }
7751
7752 /* Enable autotuning of the PLL clock (if permissible) */
7753 factor = 21;
7754 if (is_lvds) {
7755 if ((intel_panel_use_ssc(dev_priv) &&
7756 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7757 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7758 factor = 25;
7759 } else if (crtc_state->sdvo_tv_clock)
7760 factor = 20;
7761
7762 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7763 *fp |= FP_CB_TUNE;
7764
7765 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7766 *fp2 |= FP_CB_TUNE;
7767
7768 dpll = 0;
7769
7770 if (is_lvds)
7771 dpll |= DPLLB_MODE_LVDS;
7772 else
7773 dpll |= DPLLB_MODE_DAC_SERIAL;
7774
7775 dpll |= (crtc_state->pixel_multiplier - 1)
7776 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7777
7778 if (is_sdvo)
7779 dpll |= DPLL_SDVO_HIGH_SPEED;
7780 if (crtc_state->has_dp_encoder)
7781 dpll |= DPLL_SDVO_HIGH_SPEED;
7782
7783 /* compute bitmask from p1 value */
7784 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7785 /* also FPA1 */
7786 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7787
7788 switch (crtc_state->dpll.p2) {
7789 case 5:
7790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7791 break;
7792 case 7:
7793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7794 break;
7795 case 10:
7796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7797 break;
7798 case 14:
7799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7800 break;
7801 }
7802
7803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7805 else
7806 dpll |= PLL_REF_INPUT_DREFCLK;
7807
7808 return dpll | DPLL_VCO_ENABLE;
7809 }
7810
7811 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7812 struct intel_crtc_state *crtc_state)
7813 {
7814 struct drm_device *dev = crtc->base.dev;
7815 intel_clock_t clock, reduced_clock;
7816 u32 dpll = 0, fp = 0, fp2 = 0;
7817 bool ok, has_reduced_clock = false;
7818 bool is_lvds = false;
7819 struct intel_shared_dpll *pll;
7820
7821 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7822
7823 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7824 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7825
7826 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7827 &has_reduced_clock, &reduced_clock);
7828 if (!ok && !crtc_state->clock_set) {
7829 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7830 return -EINVAL;
7831 }
7832 /* Compat-code for transition, will disappear. */
7833 if (!crtc_state->clock_set) {
7834 crtc_state->dpll.n = clock.n;
7835 crtc_state->dpll.m1 = clock.m1;
7836 crtc_state->dpll.m2 = clock.m2;
7837 crtc_state->dpll.p1 = clock.p1;
7838 crtc_state->dpll.p2 = clock.p2;
7839 }
7840
7841 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7842 if (crtc_state->has_pch_encoder) {
7843 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7844 if (has_reduced_clock)
7845 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7846
7847 dpll = ironlake_compute_dpll(crtc, crtc_state,
7848 &fp, &reduced_clock,
7849 has_reduced_clock ? &fp2 : NULL);
7850
7851 crtc_state->dpll_hw_state.dpll = dpll;
7852 crtc_state->dpll_hw_state.fp0 = fp;
7853 if (has_reduced_clock)
7854 crtc_state->dpll_hw_state.fp1 = fp2;
7855 else
7856 crtc_state->dpll_hw_state.fp1 = fp;
7857
7858 pll = intel_get_shared_dpll(crtc, crtc_state);
7859 if (pll == NULL) {
7860 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7861 pipe_name(crtc->pipe));
7862 return -EINVAL;
7863 }
7864 }
7865
7866 if (is_lvds && has_reduced_clock)
7867 crtc->lowfreq_avail = true;
7868 else
7869 crtc->lowfreq_avail = false;
7870
7871 return 0;
7872 }
7873
7874 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7875 struct intel_link_m_n *m_n)
7876 {
7877 struct drm_device *dev = crtc->base.dev;
7878 struct drm_i915_private *dev_priv = dev->dev_private;
7879 enum pipe pipe = crtc->pipe;
7880
7881 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7882 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7883 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7884 & ~TU_SIZE_MASK;
7885 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7886 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7887 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7888 }
7889
7890 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7891 enum transcoder transcoder,
7892 struct intel_link_m_n *m_n,
7893 struct intel_link_m_n *m2_n2)
7894 {
7895 struct drm_device *dev = crtc->base.dev;
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 enum pipe pipe = crtc->pipe;
7898
7899 if (INTEL_INFO(dev)->gen >= 5) {
7900 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7901 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7902 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7903 & ~TU_SIZE_MASK;
7904 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7905 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7906 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7907 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7908 * gen < 8) and if DRRS is supported (to make sure the
7909 * registers are not unnecessarily read).
7910 */
7911 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7912 crtc->config->has_drrs) {
7913 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7914 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7915 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7916 & ~TU_SIZE_MASK;
7917 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7918 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7919 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7920 }
7921 } else {
7922 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7923 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7924 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7925 & ~TU_SIZE_MASK;
7926 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7927 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7928 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7929 }
7930 }
7931
7932 void intel_dp_get_m_n(struct intel_crtc *crtc,
7933 struct intel_crtc_state *pipe_config)
7934 {
7935 if (pipe_config->has_pch_encoder)
7936 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7937 else
7938 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7939 &pipe_config->dp_m_n,
7940 &pipe_config->dp_m2_n2);
7941 }
7942
7943 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7944 struct intel_crtc_state *pipe_config)
7945 {
7946 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7947 &pipe_config->fdi_m_n, NULL);
7948 }
7949
7950 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7951 struct intel_crtc_state *pipe_config)
7952 {
7953 struct drm_device *dev = crtc->base.dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 uint32_t tmp;
7956
7957 tmp = I915_READ(PS_CTL(crtc->pipe));
7958
7959 if (tmp & PS_ENABLE) {
7960 pipe_config->pch_pfit.enabled = true;
7961 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7962 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7963 }
7964 }
7965
7966 static void
7967 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7968 struct intel_initial_plane_config *plane_config)
7969 {
7970 struct drm_device *dev = crtc->base.dev;
7971 struct drm_i915_private *dev_priv = dev->dev_private;
7972 u32 val, base, offset, stride_mult, tiling;
7973 int pipe = crtc->pipe;
7974 int fourcc, pixel_format;
7975 unsigned int aligned_height;
7976 struct drm_framebuffer *fb;
7977 struct intel_framebuffer *intel_fb;
7978
7979 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7980 if (!intel_fb) {
7981 DRM_DEBUG_KMS("failed to alloc fb\n");
7982 return;
7983 }
7984
7985 fb = &intel_fb->base;
7986
7987 val = I915_READ(PLANE_CTL(pipe, 0));
7988 if (!(val & PLANE_CTL_ENABLE))
7989 goto error;
7990
7991 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7992 fourcc = skl_format_to_fourcc(pixel_format,
7993 val & PLANE_CTL_ORDER_RGBX,
7994 val & PLANE_CTL_ALPHA_MASK);
7995 fb->pixel_format = fourcc;
7996 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7997
7998 tiling = val & PLANE_CTL_TILED_MASK;
7999 switch (tiling) {
8000 case PLANE_CTL_TILED_LINEAR:
8001 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8002 break;
8003 case PLANE_CTL_TILED_X:
8004 plane_config->tiling = I915_TILING_X;
8005 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8006 break;
8007 case PLANE_CTL_TILED_Y:
8008 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8009 break;
8010 case PLANE_CTL_TILED_YF:
8011 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8012 break;
8013 default:
8014 MISSING_CASE(tiling);
8015 goto error;
8016 }
8017
8018 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8019 plane_config->base = base;
8020
8021 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8022
8023 val = I915_READ(PLANE_SIZE(pipe, 0));
8024 fb->height = ((val >> 16) & 0xfff) + 1;
8025 fb->width = ((val >> 0) & 0x1fff) + 1;
8026
8027 val = I915_READ(PLANE_STRIDE(pipe, 0));
8028 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8029 fb->pixel_format);
8030 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8031
8032 aligned_height = intel_fb_align_height(dev, fb->height,
8033 fb->pixel_format,
8034 fb->modifier[0]);
8035
8036 plane_config->size = fb->pitches[0] * aligned_height;
8037
8038 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8039 pipe_name(pipe), fb->width, fb->height,
8040 fb->bits_per_pixel, base, fb->pitches[0],
8041 plane_config->size);
8042
8043 plane_config->fb = intel_fb;
8044 return;
8045
8046 error:
8047 kfree(fb);
8048 }
8049
8050 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8051 struct intel_crtc_state *pipe_config)
8052 {
8053 struct drm_device *dev = crtc->base.dev;
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 uint32_t tmp;
8056
8057 tmp = I915_READ(PF_CTL(crtc->pipe));
8058
8059 if (tmp & PF_ENABLE) {
8060 pipe_config->pch_pfit.enabled = true;
8061 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8062 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8063
8064 /* We currently do not free assignements of panel fitters on
8065 * ivb/hsw (since we don't use the higher upscaling modes which
8066 * differentiates them) so just WARN about this case for now. */
8067 if (IS_GEN7(dev)) {
8068 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8069 PF_PIPE_SEL_IVB(crtc->pipe));
8070 }
8071 }
8072 }
8073
8074 static void
8075 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8076 struct intel_initial_plane_config *plane_config)
8077 {
8078 struct drm_device *dev = crtc->base.dev;
8079 struct drm_i915_private *dev_priv = dev->dev_private;
8080 u32 val, base, offset;
8081 int pipe = crtc->pipe;
8082 int fourcc, pixel_format;
8083 unsigned int aligned_height;
8084 struct drm_framebuffer *fb;
8085 struct intel_framebuffer *intel_fb;
8086
8087 val = I915_READ(DSPCNTR(pipe));
8088 if (!(val & DISPLAY_PLANE_ENABLE))
8089 return;
8090
8091 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8092 if (!intel_fb) {
8093 DRM_DEBUG_KMS("failed to alloc fb\n");
8094 return;
8095 }
8096
8097 fb = &intel_fb->base;
8098
8099 if (INTEL_INFO(dev)->gen >= 4) {
8100 if (val & DISPPLANE_TILED) {
8101 plane_config->tiling = I915_TILING_X;
8102 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8103 }
8104 }
8105
8106 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8107 fourcc = i9xx_format_to_fourcc(pixel_format);
8108 fb->pixel_format = fourcc;
8109 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8110
8111 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8112 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8113 offset = I915_READ(DSPOFFSET(pipe));
8114 } else {
8115 if (plane_config->tiling)
8116 offset = I915_READ(DSPTILEOFF(pipe));
8117 else
8118 offset = I915_READ(DSPLINOFF(pipe));
8119 }
8120 plane_config->base = base;
8121
8122 val = I915_READ(PIPESRC(pipe));
8123 fb->width = ((val >> 16) & 0xfff) + 1;
8124 fb->height = ((val >> 0) & 0xfff) + 1;
8125
8126 val = I915_READ(DSPSTRIDE(pipe));
8127 fb->pitches[0] = val & 0xffffffc0;
8128
8129 aligned_height = intel_fb_align_height(dev, fb->height,
8130 fb->pixel_format,
8131 fb->modifier[0]);
8132
8133 plane_config->size = fb->pitches[0] * aligned_height;
8134
8135 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8136 pipe_name(pipe), fb->width, fb->height,
8137 fb->bits_per_pixel, base, fb->pitches[0],
8138 plane_config->size);
8139
8140 plane_config->fb = intel_fb;
8141 }
8142
8143 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8144 struct intel_crtc_state *pipe_config)
8145 {
8146 struct drm_device *dev = crtc->base.dev;
8147 struct drm_i915_private *dev_priv = dev->dev_private;
8148 uint32_t tmp;
8149
8150 if (!intel_display_power_is_enabled(dev_priv,
8151 POWER_DOMAIN_PIPE(crtc->pipe)))
8152 return false;
8153
8154 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8155 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8156
8157 tmp = I915_READ(PIPECONF(crtc->pipe));
8158 if (!(tmp & PIPECONF_ENABLE))
8159 return false;
8160
8161 switch (tmp & PIPECONF_BPC_MASK) {
8162 case PIPECONF_6BPC:
8163 pipe_config->pipe_bpp = 18;
8164 break;
8165 case PIPECONF_8BPC:
8166 pipe_config->pipe_bpp = 24;
8167 break;
8168 case PIPECONF_10BPC:
8169 pipe_config->pipe_bpp = 30;
8170 break;
8171 case PIPECONF_12BPC:
8172 pipe_config->pipe_bpp = 36;
8173 break;
8174 default:
8175 break;
8176 }
8177
8178 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8179 pipe_config->limited_color_range = true;
8180
8181 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8182 struct intel_shared_dpll *pll;
8183
8184 pipe_config->has_pch_encoder = true;
8185
8186 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8187 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8188 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8189
8190 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8191
8192 if (HAS_PCH_IBX(dev_priv->dev)) {
8193 pipe_config->shared_dpll =
8194 (enum intel_dpll_id) crtc->pipe;
8195 } else {
8196 tmp = I915_READ(PCH_DPLL_SEL);
8197 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8198 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8199 else
8200 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8201 }
8202
8203 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8204
8205 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8206 &pipe_config->dpll_hw_state));
8207
8208 tmp = pipe_config->dpll_hw_state.dpll;
8209 pipe_config->pixel_multiplier =
8210 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8211 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8212
8213 ironlake_pch_clock_get(crtc, pipe_config);
8214 } else {
8215 pipe_config->pixel_multiplier = 1;
8216 }
8217
8218 intel_get_pipe_timings(crtc, pipe_config);
8219
8220 ironlake_get_pfit_config(crtc, pipe_config);
8221
8222 return true;
8223 }
8224
8225 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8226 {
8227 struct drm_device *dev = dev_priv->dev;
8228 struct intel_crtc *crtc;
8229
8230 for_each_intel_crtc(dev, crtc)
8231 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8232 pipe_name(crtc->pipe));
8233
8234 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8235 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8236 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8237 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8238 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8239 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8240 "CPU PWM1 enabled\n");
8241 if (IS_HASWELL(dev))
8242 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8243 "CPU PWM2 enabled\n");
8244 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8245 "PCH PWM1 enabled\n");
8246 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8247 "Utility pin enabled\n");
8248 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8249
8250 /*
8251 * In theory we can still leave IRQs enabled, as long as only the HPD
8252 * interrupts remain enabled. We used to check for that, but since it's
8253 * gen-specific and since we only disable LCPLL after we fully disable
8254 * the interrupts, the check below should be enough.
8255 */
8256 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8257 }
8258
8259 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8260 {
8261 struct drm_device *dev = dev_priv->dev;
8262
8263 if (IS_HASWELL(dev))
8264 return I915_READ(D_COMP_HSW);
8265 else
8266 return I915_READ(D_COMP_BDW);
8267 }
8268
8269 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8270 {
8271 struct drm_device *dev = dev_priv->dev;
8272
8273 if (IS_HASWELL(dev)) {
8274 mutex_lock(&dev_priv->rps.hw_lock);
8275 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8276 val))
8277 DRM_ERROR("Failed to write to D_COMP\n");
8278 mutex_unlock(&dev_priv->rps.hw_lock);
8279 } else {
8280 I915_WRITE(D_COMP_BDW, val);
8281 POSTING_READ(D_COMP_BDW);
8282 }
8283 }
8284
8285 /*
8286 * This function implements pieces of two sequences from BSpec:
8287 * - Sequence for display software to disable LCPLL
8288 * - Sequence for display software to allow package C8+
8289 * The steps implemented here are just the steps that actually touch the LCPLL
8290 * register. Callers should take care of disabling all the display engine
8291 * functions, doing the mode unset, fixing interrupts, etc.
8292 */
8293 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8294 bool switch_to_fclk, bool allow_power_down)
8295 {
8296 uint32_t val;
8297
8298 assert_can_disable_lcpll(dev_priv);
8299
8300 val = I915_READ(LCPLL_CTL);
8301
8302 if (switch_to_fclk) {
8303 val |= LCPLL_CD_SOURCE_FCLK;
8304 I915_WRITE(LCPLL_CTL, val);
8305
8306 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8307 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8308 DRM_ERROR("Switching to FCLK failed\n");
8309
8310 val = I915_READ(LCPLL_CTL);
8311 }
8312
8313 val |= LCPLL_PLL_DISABLE;
8314 I915_WRITE(LCPLL_CTL, val);
8315 POSTING_READ(LCPLL_CTL);
8316
8317 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8318 DRM_ERROR("LCPLL still locked\n");
8319
8320 val = hsw_read_dcomp(dev_priv);
8321 val |= D_COMP_COMP_DISABLE;
8322 hsw_write_dcomp(dev_priv, val);
8323 ndelay(100);
8324
8325 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8326 1))
8327 DRM_ERROR("D_COMP RCOMP still in progress\n");
8328
8329 if (allow_power_down) {
8330 val = I915_READ(LCPLL_CTL);
8331 val |= LCPLL_POWER_DOWN_ALLOW;
8332 I915_WRITE(LCPLL_CTL, val);
8333 POSTING_READ(LCPLL_CTL);
8334 }
8335 }
8336
8337 /*
8338 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8339 * source.
8340 */
8341 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8342 {
8343 uint32_t val;
8344
8345 val = I915_READ(LCPLL_CTL);
8346
8347 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8348 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8349 return;
8350
8351 /*
8352 * Make sure we're not on PC8 state before disabling PC8, otherwise
8353 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8354 */
8355 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8356
8357 if (val & LCPLL_POWER_DOWN_ALLOW) {
8358 val &= ~LCPLL_POWER_DOWN_ALLOW;
8359 I915_WRITE(LCPLL_CTL, val);
8360 POSTING_READ(LCPLL_CTL);
8361 }
8362
8363 val = hsw_read_dcomp(dev_priv);
8364 val |= D_COMP_COMP_FORCE;
8365 val &= ~D_COMP_COMP_DISABLE;
8366 hsw_write_dcomp(dev_priv, val);
8367
8368 val = I915_READ(LCPLL_CTL);
8369 val &= ~LCPLL_PLL_DISABLE;
8370 I915_WRITE(LCPLL_CTL, val);
8371
8372 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8373 DRM_ERROR("LCPLL not locked yet\n");
8374
8375 if (val & LCPLL_CD_SOURCE_FCLK) {
8376 val = I915_READ(LCPLL_CTL);
8377 val &= ~LCPLL_CD_SOURCE_FCLK;
8378 I915_WRITE(LCPLL_CTL, val);
8379
8380 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8381 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8382 DRM_ERROR("Switching back to LCPLL failed\n");
8383 }
8384
8385 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8386 }
8387
8388 /*
8389 * Package states C8 and deeper are really deep PC states that can only be
8390 * reached when all the devices on the system allow it, so even if the graphics
8391 * device allows PC8+, it doesn't mean the system will actually get to these
8392 * states. Our driver only allows PC8+ when going into runtime PM.
8393 *
8394 * The requirements for PC8+ are that all the outputs are disabled, the power
8395 * well is disabled and most interrupts are disabled, and these are also
8396 * requirements for runtime PM. When these conditions are met, we manually do
8397 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8398 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8399 * hang the machine.
8400 *
8401 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8402 * the state of some registers, so when we come back from PC8+ we need to
8403 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8404 * need to take care of the registers kept by RC6. Notice that this happens even
8405 * if we don't put the device in PCI D3 state (which is what currently happens
8406 * because of the runtime PM support).
8407 *
8408 * For more, read "Display Sequences for Package C8" on the hardware
8409 * documentation.
8410 */
8411 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8412 {
8413 struct drm_device *dev = dev_priv->dev;
8414 uint32_t val;
8415
8416 DRM_DEBUG_KMS("Enabling package C8+\n");
8417
8418 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8419 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8420 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8421 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8422 }
8423
8424 lpt_disable_clkout_dp(dev);
8425 hsw_disable_lcpll(dev_priv, true, true);
8426 }
8427
8428 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8429 {
8430 struct drm_device *dev = dev_priv->dev;
8431 uint32_t val;
8432
8433 DRM_DEBUG_KMS("Disabling package C8+\n");
8434
8435 hsw_restore_lcpll(dev_priv);
8436 lpt_init_pch_refclk(dev);
8437
8438 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8439 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8440 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8441 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8442 }
8443
8444 intel_prepare_ddi(dev);
8445 }
8446
8447 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8448 struct intel_crtc_state *crtc_state)
8449 {
8450 if (!intel_ddi_pll_select(crtc, crtc_state))
8451 return -EINVAL;
8452
8453 crtc->lowfreq_avail = false;
8454
8455 return 0;
8456 }
8457
8458 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8459 enum port port,
8460 struct intel_crtc_state *pipe_config)
8461 {
8462 u32 temp, dpll_ctl1;
8463
8464 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8465 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8466
8467 switch (pipe_config->ddi_pll_sel) {
8468 case SKL_DPLL0:
8469 /*
8470 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8471 * of the shared DPLL framework and thus needs to be read out
8472 * separately
8473 */
8474 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8475 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8476 break;
8477 case SKL_DPLL1:
8478 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8479 break;
8480 case SKL_DPLL2:
8481 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8482 break;
8483 case SKL_DPLL3:
8484 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8485 break;
8486 }
8487 }
8488
8489 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8490 enum port port,
8491 struct intel_crtc_state *pipe_config)
8492 {
8493 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8494
8495 switch (pipe_config->ddi_pll_sel) {
8496 case PORT_CLK_SEL_WRPLL1:
8497 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8498 break;
8499 case PORT_CLK_SEL_WRPLL2:
8500 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8501 break;
8502 }
8503 }
8504
8505 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8506 struct intel_crtc_state *pipe_config)
8507 {
8508 struct drm_device *dev = crtc->base.dev;
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8510 struct intel_shared_dpll *pll;
8511 enum port port;
8512 uint32_t tmp;
8513
8514 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8515
8516 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8517
8518 if (IS_SKYLAKE(dev))
8519 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8520 else
8521 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8522
8523 if (pipe_config->shared_dpll >= 0) {
8524 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8525
8526 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8527 &pipe_config->dpll_hw_state));
8528 }
8529
8530 /*
8531 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8532 * DDI E. So just check whether this pipe is wired to DDI E and whether
8533 * the PCH transcoder is on.
8534 */
8535 if (INTEL_INFO(dev)->gen < 9 &&
8536 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8537 pipe_config->has_pch_encoder = true;
8538
8539 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8540 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8541 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8542
8543 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8544 }
8545 }
8546
8547 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8548 struct intel_crtc_state *pipe_config)
8549 {
8550 struct drm_device *dev = crtc->base.dev;
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8552 enum intel_display_power_domain pfit_domain;
8553 uint32_t tmp;
8554
8555 if (!intel_display_power_is_enabled(dev_priv,
8556 POWER_DOMAIN_PIPE(crtc->pipe)))
8557 return false;
8558
8559 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8560 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8561
8562 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8563 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8564 enum pipe trans_edp_pipe;
8565 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8566 default:
8567 WARN(1, "unknown pipe linked to edp transcoder\n");
8568 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8569 case TRANS_DDI_EDP_INPUT_A_ON:
8570 trans_edp_pipe = PIPE_A;
8571 break;
8572 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8573 trans_edp_pipe = PIPE_B;
8574 break;
8575 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8576 trans_edp_pipe = PIPE_C;
8577 break;
8578 }
8579
8580 if (trans_edp_pipe == crtc->pipe)
8581 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8582 }
8583
8584 if (!intel_display_power_is_enabled(dev_priv,
8585 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8586 return false;
8587
8588 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8589 if (!(tmp & PIPECONF_ENABLE))
8590 return false;
8591
8592 haswell_get_ddi_port_state(crtc, pipe_config);
8593
8594 intel_get_pipe_timings(crtc, pipe_config);
8595
8596 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8597 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8598 if (IS_SKYLAKE(dev))
8599 skylake_get_pfit_config(crtc, pipe_config);
8600 else
8601 ironlake_get_pfit_config(crtc, pipe_config);
8602 }
8603
8604 if (IS_HASWELL(dev))
8605 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8606 (I915_READ(IPS_CTL) & IPS_ENABLE);
8607
8608 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8609 pipe_config->pixel_multiplier =
8610 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8611 } else {
8612 pipe_config->pixel_multiplier = 1;
8613 }
8614
8615 return true;
8616 }
8617
8618 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8619 {
8620 struct drm_device *dev = crtc->dev;
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8623 uint32_t cntl = 0, size = 0;
8624
8625 if (base) {
8626 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8627 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8628 unsigned int stride = roundup_pow_of_two(width) * 4;
8629
8630 switch (stride) {
8631 default:
8632 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8633 width, stride);
8634 stride = 256;
8635 /* fallthrough */
8636 case 256:
8637 case 512:
8638 case 1024:
8639 case 2048:
8640 break;
8641 }
8642
8643 cntl |= CURSOR_ENABLE |
8644 CURSOR_GAMMA_ENABLE |
8645 CURSOR_FORMAT_ARGB |
8646 CURSOR_STRIDE(stride);
8647
8648 size = (height << 12) | width;
8649 }
8650
8651 if (intel_crtc->cursor_cntl != 0 &&
8652 (intel_crtc->cursor_base != base ||
8653 intel_crtc->cursor_size != size ||
8654 intel_crtc->cursor_cntl != cntl)) {
8655 /* On these chipsets we can only modify the base/size/stride
8656 * whilst the cursor is disabled.
8657 */
8658 I915_WRITE(_CURACNTR, 0);
8659 POSTING_READ(_CURACNTR);
8660 intel_crtc->cursor_cntl = 0;
8661 }
8662
8663 if (intel_crtc->cursor_base != base) {
8664 I915_WRITE(_CURABASE, base);
8665 intel_crtc->cursor_base = base;
8666 }
8667
8668 if (intel_crtc->cursor_size != size) {
8669 I915_WRITE(CURSIZE, size);
8670 intel_crtc->cursor_size = size;
8671 }
8672
8673 if (intel_crtc->cursor_cntl != cntl) {
8674 I915_WRITE(_CURACNTR, cntl);
8675 POSTING_READ(_CURACNTR);
8676 intel_crtc->cursor_cntl = cntl;
8677 }
8678 }
8679
8680 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8681 {
8682 struct drm_device *dev = crtc->dev;
8683 struct drm_i915_private *dev_priv = dev->dev_private;
8684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8685 int pipe = intel_crtc->pipe;
8686 uint32_t cntl;
8687
8688 cntl = 0;
8689 if (base) {
8690 cntl = MCURSOR_GAMMA_ENABLE;
8691 switch (intel_crtc->base.cursor->state->crtc_w) {
8692 case 64:
8693 cntl |= CURSOR_MODE_64_ARGB_AX;
8694 break;
8695 case 128:
8696 cntl |= CURSOR_MODE_128_ARGB_AX;
8697 break;
8698 case 256:
8699 cntl |= CURSOR_MODE_256_ARGB_AX;
8700 break;
8701 default:
8702 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8703 return;
8704 }
8705 cntl |= pipe << 28; /* Connect to correct pipe */
8706
8707 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8708 cntl |= CURSOR_PIPE_CSC_ENABLE;
8709 }
8710
8711 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8712 cntl |= CURSOR_ROTATE_180;
8713
8714 if (intel_crtc->cursor_cntl != cntl) {
8715 I915_WRITE(CURCNTR(pipe), cntl);
8716 POSTING_READ(CURCNTR(pipe));
8717 intel_crtc->cursor_cntl = cntl;
8718 }
8719
8720 /* and commit changes on next vblank */
8721 I915_WRITE(CURBASE(pipe), base);
8722 POSTING_READ(CURBASE(pipe));
8723
8724 intel_crtc->cursor_base = base;
8725 }
8726
8727 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8728 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8729 bool on)
8730 {
8731 struct drm_device *dev = crtc->dev;
8732 struct drm_i915_private *dev_priv = dev->dev_private;
8733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8734 int pipe = intel_crtc->pipe;
8735 int x = crtc->cursor_x;
8736 int y = crtc->cursor_y;
8737 u32 base = 0, pos = 0;
8738
8739 if (on)
8740 base = intel_crtc->cursor_addr;
8741
8742 if (x >= intel_crtc->config->pipe_src_w)
8743 base = 0;
8744
8745 if (y >= intel_crtc->config->pipe_src_h)
8746 base = 0;
8747
8748 if (x < 0) {
8749 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8750 base = 0;
8751
8752 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8753 x = -x;
8754 }
8755 pos |= x << CURSOR_X_SHIFT;
8756
8757 if (y < 0) {
8758 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8759 base = 0;
8760
8761 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8762 y = -y;
8763 }
8764 pos |= y << CURSOR_Y_SHIFT;
8765
8766 if (base == 0 && intel_crtc->cursor_base == 0)
8767 return;
8768
8769 I915_WRITE(CURPOS(pipe), pos);
8770
8771 /* ILK+ do this automagically */
8772 if (HAS_GMCH_DISPLAY(dev) &&
8773 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8774 base += (intel_crtc->base.cursor->state->crtc_h *
8775 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8776 }
8777
8778 if (IS_845G(dev) || IS_I865G(dev))
8779 i845_update_cursor(crtc, base);
8780 else
8781 i9xx_update_cursor(crtc, base);
8782 }
8783
8784 static bool cursor_size_ok(struct drm_device *dev,
8785 uint32_t width, uint32_t height)
8786 {
8787 if (width == 0 || height == 0)
8788 return false;
8789
8790 /*
8791 * 845g/865g are special in that they are only limited by
8792 * the width of their cursors, the height is arbitrary up to
8793 * the precision of the register. Everything else requires
8794 * square cursors, limited to a few power-of-two sizes.
8795 */
8796 if (IS_845G(dev) || IS_I865G(dev)) {
8797 if ((width & 63) != 0)
8798 return false;
8799
8800 if (width > (IS_845G(dev) ? 64 : 512))
8801 return false;
8802
8803 if (height > 1023)
8804 return false;
8805 } else {
8806 switch (width | height) {
8807 case 256:
8808 case 128:
8809 if (IS_GEN2(dev))
8810 return false;
8811 case 64:
8812 break;
8813 default:
8814 return false;
8815 }
8816 }
8817
8818 return true;
8819 }
8820
8821 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8822 u16 *blue, uint32_t start, uint32_t size)
8823 {
8824 int end = (start + size > 256) ? 256 : start + size, i;
8825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8826
8827 for (i = start; i < end; i++) {
8828 intel_crtc->lut_r[i] = red[i] >> 8;
8829 intel_crtc->lut_g[i] = green[i] >> 8;
8830 intel_crtc->lut_b[i] = blue[i] >> 8;
8831 }
8832
8833 intel_crtc_load_lut(crtc);
8834 }
8835
8836 /* VESA 640x480x72Hz mode to set on the pipe */
8837 static struct drm_display_mode load_detect_mode = {
8838 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8839 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8840 };
8841
8842 struct drm_framebuffer *
8843 __intel_framebuffer_create(struct drm_device *dev,
8844 struct drm_mode_fb_cmd2 *mode_cmd,
8845 struct drm_i915_gem_object *obj)
8846 {
8847 struct intel_framebuffer *intel_fb;
8848 int ret;
8849
8850 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8851 if (!intel_fb) {
8852 drm_gem_object_unreference(&obj->base);
8853 return ERR_PTR(-ENOMEM);
8854 }
8855
8856 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8857 if (ret)
8858 goto err;
8859
8860 return &intel_fb->base;
8861 err:
8862 drm_gem_object_unreference(&obj->base);
8863 kfree(intel_fb);
8864
8865 return ERR_PTR(ret);
8866 }
8867
8868 static struct drm_framebuffer *
8869 intel_framebuffer_create(struct drm_device *dev,
8870 struct drm_mode_fb_cmd2 *mode_cmd,
8871 struct drm_i915_gem_object *obj)
8872 {
8873 struct drm_framebuffer *fb;
8874 int ret;
8875
8876 ret = i915_mutex_lock_interruptible(dev);
8877 if (ret)
8878 return ERR_PTR(ret);
8879 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8880 mutex_unlock(&dev->struct_mutex);
8881
8882 return fb;
8883 }
8884
8885 static u32
8886 intel_framebuffer_pitch_for_width(int width, int bpp)
8887 {
8888 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8889 return ALIGN(pitch, 64);
8890 }
8891
8892 static u32
8893 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8894 {
8895 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8896 return PAGE_ALIGN(pitch * mode->vdisplay);
8897 }
8898
8899 static struct drm_framebuffer *
8900 intel_framebuffer_create_for_mode(struct drm_device *dev,
8901 struct drm_display_mode *mode,
8902 int depth, int bpp)
8903 {
8904 struct drm_i915_gem_object *obj;
8905 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8906
8907 obj = i915_gem_alloc_object(dev,
8908 intel_framebuffer_size_for_mode(mode, bpp));
8909 if (obj == NULL)
8910 return ERR_PTR(-ENOMEM);
8911
8912 mode_cmd.width = mode->hdisplay;
8913 mode_cmd.height = mode->vdisplay;
8914 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8915 bpp);
8916 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8917
8918 return intel_framebuffer_create(dev, &mode_cmd, obj);
8919 }
8920
8921 static struct drm_framebuffer *
8922 mode_fits_in_fbdev(struct drm_device *dev,
8923 struct drm_display_mode *mode)
8924 {
8925 #ifdef CONFIG_DRM_I915_FBDEV
8926 struct drm_i915_private *dev_priv = dev->dev_private;
8927 struct drm_i915_gem_object *obj;
8928 struct drm_framebuffer *fb;
8929
8930 if (!dev_priv->fbdev)
8931 return NULL;
8932
8933 if (!dev_priv->fbdev->fb)
8934 return NULL;
8935
8936 obj = dev_priv->fbdev->fb->obj;
8937 BUG_ON(!obj);
8938
8939 fb = &dev_priv->fbdev->fb->base;
8940 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8941 fb->bits_per_pixel))
8942 return NULL;
8943
8944 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8945 return NULL;
8946
8947 return fb;
8948 #else
8949 return NULL;
8950 #endif
8951 }
8952
8953 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8954 struct drm_display_mode *mode,
8955 struct intel_load_detect_pipe *old,
8956 struct drm_modeset_acquire_ctx *ctx)
8957 {
8958 struct intel_crtc *intel_crtc;
8959 struct intel_encoder *intel_encoder =
8960 intel_attached_encoder(connector);
8961 struct drm_crtc *possible_crtc;
8962 struct drm_encoder *encoder = &intel_encoder->base;
8963 struct drm_crtc *crtc = NULL;
8964 struct drm_device *dev = encoder->dev;
8965 struct drm_framebuffer *fb;
8966 struct drm_mode_config *config = &dev->mode_config;
8967 struct drm_atomic_state *state = NULL;
8968 struct drm_connector_state *connector_state;
8969 int ret, i = -1;
8970
8971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8972 connector->base.id, connector->name,
8973 encoder->base.id, encoder->name);
8974
8975 retry:
8976 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8977 if (ret)
8978 goto fail_unlock;
8979
8980 /*
8981 * Algorithm gets a little messy:
8982 *
8983 * - if the connector already has an assigned crtc, use it (but make
8984 * sure it's on first)
8985 *
8986 * - try to find the first unused crtc that can drive this connector,
8987 * and use that if we find one
8988 */
8989
8990 /* See if we already have a CRTC for this connector */
8991 if (encoder->crtc) {
8992 crtc = encoder->crtc;
8993
8994 ret = drm_modeset_lock(&crtc->mutex, ctx);
8995 if (ret)
8996 goto fail_unlock;
8997 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8998 if (ret)
8999 goto fail_unlock;
9000
9001 old->dpms_mode = connector->dpms;
9002 old->load_detect_temp = false;
9003
9004 /* Make sure the crtc and connector are running */
9005 if (connector->dpms != DRM_MODE_DPMS_ON)
9006 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9007
9008 return true;
9009 }
9010
9011 /* Find an unused one (if possible) */
9012 for_each_crtc(dev, possible_crtc) {
9013 i++;
9014 if (!(encoder->possible_crtcs & (1 << i)))
9015 continue;
9016 if (possible_crtc->state->enable)
9017 continue;
9018 /* This can occur when applying the pipe A quirk on resume. */
9019 if (to_intel_crtc(possible_crtc)->new_enabled)
9020 continue;
9021
9022 crtc = possible_crtc;
9023 break;
9024 }
9025
9026 /*
9027 * If we didn't find an unused CRTC, don't use any.
9028 */
9029 if (!crtc) {
9030 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9031 goto fail_unlock;
9032 }
9033
9034 ret = drm_modeset_lock(&crtc->mutex, ctx);
9035 if (ret)
9036 goto fail_unlock;
9037 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9038 if (ret)
9039 goto fail_unlock;
9040 intel_encoder->new_crtc = to_intel_crtc(crtc);
9041 to_intel_connector(connector)->new_encoder = intel_encoder;
9042
9043 intel_crtc = to_intel_crtc(crtc);
9044 intel_crtc->new_enabled = true;
9045 intel_crtc->new_config = intel_crtc->config;
9046 old->dpms_mode = connector->dpms;
9047 old->load_detect_temp = true;
9048 old->release_fb = NULL;
9049
9050 state = drm_atomic_state_alloc(dev);
9051 if (!state)
9052 return false;
9053
9054 state->acquire_ctx = ctx;
9055
9056 connector_state = drm_atomic_get_connector_state(state, connector);
9057 if (IS_ERR(connector_state)) {
9058 ret = PTR_ERR(connector_state);
9059 goto fail;
9060 }
9061
9062 connector_state->crtc = crtc;
9063 connector_state->best_encoder = &intel_encoder->base;
9064
9065 if (!mode)
9066 mode = &load_detect_mode;
9067
9068 /* We need a framebuffer large enough to accommodate all accesses
9069 * that the plane may generate whilst we perform load detection.
9070 * We can not rely on the fbcon either being present (we get called
9071 * during its initialisation to detect all boot displays, or it may
9072 * not even exist) or that it is large enough to satisfy the
9073 * requested mode.
9074 */
9075 fb = mode_fits_in_fbdev(dev, mode);
9076 if (fb == NULL) {
9077 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9078 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9079 old->release_fb = fb;
9080 } else
9081 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9082 if (IS_ERR(fb)) {
9083 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9084 goto fail;
9085 }
9086
9087 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
9088 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9089 if (old->release_fb)
9090 old->release_fb->funcs->destroy(old->release_fb);
9091 goto fail;
9092 }
9093 crtc->primary->crtc = crtc;
9094
9095 /* let the connector get through one full cycle before testing */
9096 intel_wait_for_vblank(dev, intel_crtc->pipe);
9097 return true;
9098
9099 fail:
9100 intel_crtc->new_enabled = crtc->state->enable;
9101 if (intel_crtc->new_enabled)
9102 intel_crtc->new_config = intel_crtc->config;
9103 else
9104 intel_crtc->new_config = NULL;
9105 fail_unlock:
9106 if (state) {
9107 drm_atomic_state_free(state);
9108 state = NULL;
9109 }
9110
9111 if (ret == -EDEADLK) {
9112 drm_modeset_backoff(ctx);
9113 goto retry;
9114 }
9115
9116 return false;
9117 }
9118
9119 void intel_release_load_detect_pipe(struct drm_connector *connector,
9120 struct intel_load_detect_pipe *old,
9121 struct drm_modeset_acquire_ctx *ctx)
9122 {
9123 struct drm_device *dev = connector->dev;
9124 struct intel_encoder *intel_encoder =
9125 intel_attached_encoder(connector);
9126 struct drm_encoder *encoder = &intel_encoder->base;
9127 struct drm_crtc *crtc = encoder->crtc;
9128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9129 struct drm_atomic_state *state;
9130 struct drm_connector_state *connector_state;
9131
9132 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9133 connector->base.id, connector->name,
9134 encoder->base.id, encoder->name);
9135
9136 if (old->load_detect_temp) {
9137 state = drm_atomic_state_alloc(dev);
9138 if (!state)
9139 goto fail;
9140
9141 state->acquire_ctx = ctx;
9142
9143 connector_state = drm_atomic_get_connector_state(state, connector);
9144 if (IS_ERR(connector_state))
9145 goto fail;
9146
9147 to_intel_connector(connector)->new_encoder = NULL;
9148 intel_encoder->new_crtc = NULL;
9149 intel_crtc->new_enabled = false;
9150 intel_crtc->new_config = NULL;
9151
9152 connector_state->best_encoder = NULL;
9153 connector_state->crtc = NULL;
9154
9155 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9156
9157 drm_atomic_state_free(state);
9158
9159 if (old->release_fb) {
9160 drm_framebuffer_unregister_private(old->release_fb);
9161 drm_framebuffer_unreference(old->release_fb);
9162 }
9163
9164 return;
9165 }
9166
9167 /* Switch crtc and encoder back off if necessary */
9168 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9169 connector->funcs->dpms(connector, old->dpms_mode);
9170
9171 return;
9172 fail:
9173 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9174 drm_atomic_state_free(state);
9175 }
9176
9177 static int i9xx_pll_refclk(struct drm_device *dev,
9178 const struct intel_crtc_state *pipe_config)
9179 {
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 u32 dpll = pipe_config->dpll_hw_state.dpll;
9182
9183 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9184 return dev_priv->vbt.lvds_ssc_freq;
9185 else if (HAS_PCH_SPLIT(dev))
9186 return 120000;
9187 else if (!IS_GEN2(dev))
9188 return 96000;
9189 else
9190 return 48000;
9191 }
9192
9193 /* Returns the clock of the currently programmed mode of the given pipe. */
9194 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9195 struct intel_crtc_state *pipe_config)
9196 {
9197 struct drm_device *dev = crtc->base.dev;
9198 struct drm_i915_private *dev_priv = dev->dev_private;
9199 int pipe = pipe_config->cpu_transcoder;
9200 u32 dpll = pipe_config->dpll_hw_state.dpll;
9201 u32 fp;
9202 intel_clock_t clock;
9203 int refclk = i9xx_pll_refclk(dev, pipe_config);
9204
9205 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9206 fp = pipe_config->dpll_hw_state.fp0;
9207 else
9208 fp = pipe_config->dpll_hw_state.fp1;
9209
9210 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9211 if (IS_PINEVIEW(dev)) {
9212 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9213 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9214 } else {
9215 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9216 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9217 }
9218
9219 if (!IS_GEN2(dev)) {
9220 if (IS_PINEVIEW(dev))
9221 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9222 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9223 else
9224 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9225 DPLL_FPA01_P1_POST_DIV_SHIFT);
9226
9227 switch (dpll & DPLL_MODE_MASK) {
9228 case DPLLB_MODE_DAC_SERIAL:
9229 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9230 5 : 10;
9231 break;
9232 case DPLLB_MODE_LVDS:
9233 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9234 7 : 14;
9235 break;
9236 default:
9237 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9238 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9239 return;
9240 }
9241
9242 if (IS_PINEVIEW(dev))
9243 pineview_clock(refclk, &clock);
9244 else
9245 i9xx_clock(refclk, &clock);
9246 } else {
9247 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9248 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9249
9250 if (is_lvds) {
9251 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9252 DPLL_FPA01_P1_POST_DIV_SHIFT);
9253
9254 if (lvds & LVDS_CLKB_POWER_UP)
9255 clock.p2 = 7;
9256 else
9257 clock.p2 = 14;
9258 } else {
9259 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9260 clock.p1 = 2;
9261 else {
9262 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9263 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9264 }
9265 if (dpll & PLL_P2_DIVIDE_BY_4)
9266 clock.p2 = 4;
9267 else
9268 clock.p2 = 2;
9269 }
9270
9271 i9xx_clock(refclk, &clock);
9272 }
9273
9274 /*
9275 * This value includes pixel_multiplier. We will use
9276 * port_clock to compute adjusted_mode.crtc_clock in the
9277 * encoder's get_config() function.
9278 */
9279 pipe_config->port_clock = clock.dot;
9280 }
9281
9282 int intel_dotclock_calculate(int link_freq,
9283 const struct intel_link_m_n *m_n)
9284 {
9285 /*
9286 * The calculation for the data clock is:
9287 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9288 * But we want to avoid losing precison if possible, so:
9289 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9290 *
9291 * and the link clock is simpler:
9292 * link_clock = (m * link_clock) / n
9293 */
9294
9295 if (!m_n->link_n)
9296 return 0;
9297
9298 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9299 }
9300
9301 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9302 struct intel_crtc_state *pipe_config)
9303 {
9304 struct drm_device *dev = crtc->base.dev;
9305
9306 /* read out port_clock from the DPLL */
9307 i9xx_crtc_clock_get(crtc, pipe_config);
9308
9309 /*
9310 * This value does not include pixel_multiplier.
9311 * We will check that port_clock and adjusted_mode.crtc_clock
9312 * agree once we know their relationship in the encoder's
9313 * get_config() function.
9314 */
9315 pipe_config->base.adjusted_mode.crtc_clock =
9316 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9317 &pipe_config->fdi_m_n);
9318 }
9319
9320 /** Returns the currently programmed mode of the given pipe. */
9321 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9322 struct drm_crtc *crtc)
9323 {
9324 struct drm_i915_private *dev_priv = dev->dev_private;
9325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9326 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9327 struct drm_display_mode *mode;
9328 struct intel_crtc_state pipe_config;
9329 int htot = I915_READ(HTOTAL(cpu_transcoder));
9330 int hsync = I915_READ(HSYNC(cpu_transcoder));
9331 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9332 int vsync = I915_READ(VSYNC(cpu_transcoder));
9333 enum pipe pipe = intel_crtc->pipe;
9334
9335 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9336 if (!mode)
9337 return NULL;
9338
9339 /*
9340 * Construct a pipe_config sufficient for getting the clock info
9341 * back out of crtc_clock_get.
9342 *
9343 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9344 * to use a real value here instead.
9345 */
9346 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9347 pipe_config.pixel_multiplier = 1;
9348 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9349 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9350 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9351 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9352
9353 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9354 mode->hdisplay = (htot & 0xffff) + 1;
9355 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9356 mode->hsync_start = (hsync & 0xffff) + 1;
9357 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9358 mode->vdisplay = (vtot & 0xffff) + 1;
9359 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9360 mode->vsync_start = (vsync & 0xffff) + 1;
9361 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9362
9363 drm_mode_set_name(mode);
9364
9365 return mode;
9366 }
9367
9368 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9369 {
9370 struct drm_device *dev = crtc->dev;
9371 struct drm_i915_private *dev_priv = dev->dev_private;
9372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9373
9374 if (!HAS_GMCH_DISPLAY(dev))
9375 return;
9376
9377 if (!dev_priv->lvds_downclock_avail)
9378 return;
9379
9380 /*
9381 * Since this is called by a timer, we should never get here in
9382 * the manual case.
9383 */
9384 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9385 int pipe = intel_crtc->pipe;
9386 int dpll_reg = DPLL(pipe);
9387 int dpll;
9388
9389 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9390
9391 assert_panel_unlocked(dev_priv, pipe);
9392
9393 dpll = I915_READ(dpll_reg);
9394 dpll |= DISPLAY_RATE_SELECT_FPA1;
9395 I915_WRITE(dpll_reg, dpll);
9396 intel_wait_for_vblank(dev, pipe);
9397 dpll = I915_READ(dpll_reg);
9398 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9399 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9400 }
9401
9402 }
9403
9404 void intel_mark_busy(struct drm_device *dev)
9405 {
9406 struct drm_i915_private *dev_priv = dev->dev_private;
9407
9408 if (dev_priv->mm.busy)
9409 return;
9410
9411 intel_runtime_pm_get(dev_priv);
9412 i915_update_gfx_val(dev_priv);
9413 if (INTEL_INFO(dev)->gen >= 6)
9414 gen6_rps_busy(dev_priv);
9415 dev_priv->mm.busy = true;
9416 }
9417
9418 void intel_mark_idle(struct drm_device *dev)
9419 {
9420 struct drm_i915_private *dev_priv = dev->dev_private;
9421 struct drm_crtc *crtc;
9422
9423 if (!dev_priv->mm.busy)
9424 return;
9425
9426 dev_priv->mm.busy = false;
9427
9428 for_each_crtc(dev, crtc) {
9429 if (!crtc->primary->fb)
9430 continue;
9431
9432 intel_decrease_pllclock(crtc);
9433 }
9434
9435 if (INTEL_INFO(dev)->gen >= 6)
9436 gen6_rps_idle(dev->dev_private);
9437
9438 intel_runtime_pm_put(dev_priv);
9439 }
9440
9441 static void intel_crtc_set_state(struct intel_crtc *crtc,
9442 struct intel_crtc_state *crtc_state)
9443 {
9444 kfree(crtc->config);
9445 crtc->config = crtc_state;
9446 crtc->base.state = &crtc_state->base;
9447 }
9448
9449 static void intel_crtc_destroy(struct drm_crtc *crtc)
9450 {
9451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9452 struct drm_device *dev = crtc->dev;
9453 struct intel_unpin_work *work;
9454
9455 spin_lock_irq(&dev->event_lock);
9456 work = intel_crtc->unpin_work;
9457 intel_crtc->unpin_work = NULL;
9458 spin_unlock_irq(&dev->event_lock);
9459
9460 if (work) {
9461 cancel_work_sync(&work->work);
9462 kfree(work);
9463 }
9464
9465 intel_crtc_set_state(intel_crtc, NULL);
9466 drm_crtc_cleanup(crtc);
9467
9468 kfree(intel_crtc);
9469 }
9470
9471 static void intel_unpin_work_fn(struct work_struct *__work)
9472 {
9473 struct intel_unpin_work *work =
9474 container_of(__work, struct intel_unpin_work, work);
9475 struct drm_device *dev = work->crtc->dev;
9476 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9477
9478 mutex_lock(&dev->struct_mutex);
9479 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
9480 drm_gem_object_unreference(&work->pending_flip_obj->base);
9481
9482 intel_fbc_update(dev);
9483
9484 if (work->flip_queued_req)
9485 i915_gem_request_assign(&work->flip_queued_req, NULL);
9486 mutex_unlock(&dev->struct_mutex);
9487
9488 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9489 drm_framebuffer_unreference(work->old_fb);
9490
9491 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9492 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9493
9494 kfree(work);
9495 }
9496
9497 static void do_intel_finish_page_flip(struct drm_device *dev,
9498 struct drm_crtc *crtc)
9499 {
9500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9501 struct intel_unpin_work *work;
9502 unsigned long flags;
9503
9504 /* Ignore early vblank irqs */
9505 if (intel_crtc == NULL)
9506 return;
9507
9508 /*
9509 * This is called both by irq handlers and the reset code (to complete
9510 * lost pageflips) so needs the full irqsave spinlocks.
9511 */
9512 spin_lock_irqsave(&dev->event_lock, flags);
9513 work = intel_crtc->unpin_work;
9514
9515 /* Ensure we don't miss a work->pending update ... */
9516 smp_rmb();
9517
9518 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9519 spin_unlock_irqrestore(&dev->event_lock, flags);
9520 return;
9521 }
9522
9523 page_flip_completed(intel_crtc);
9524
9525 spin_unlock_irqrestore(&dev->event_lock, flags);
9526 }
9527
9528 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9529 {
9530 struct drm_i915_private *dev_priv = dev->dev_private;
9531 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9532
9533 do_intel_finish_page_flip(dev, crtc);
9534 }
9535
9536 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9537 {
9538 struct drm_i915_private *dev_priv = dev->dev_private;
9539 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9540
9541 do_intel_finish_page_flip(dev, crtc);
9542 }
9543
9544 /* Is 'a' after or equal to 'b'? */
9545 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9546 {
9547 return !((a - b) & 0x80000000);
9548 }
9549
9550 static bool page_flip_finished(struct intel_crtc *crtc)
9551 {
9552 struct drm_device *dev = crtc->base.dev;
9553 struct drm_i915_private *dev_priv = dev->dev_private;
9554
9555 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9556 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9557 return true;
9558
9559 /*
9560 * The relevant registers doen't exist on pre-ctg.
9561 * As the flip done interrupt doesn't trigger for mmio
9562 * flips on gmch platforms, a flip count check isn't
9563 * really needed there. But since ctg has the registers,
9564 * include it in the check anyway.
9565 */
9566 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9567 return true;
9568
9569 /*
9570 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9571 * used the same base address. In that case the mmio flip might
9572 * have completed, but the CS hasn't even executed the flip yet.
9573 *
9574 * A flip count check isn't enough as the CS might have updated
9575 * the base address just after start of vblank, but before we
9576 * managed to process the interrupt. This means we'd complete the
9577 * CS flip too soon.
9578 *
9579 * Combining both checks should get us a good enough result. It may
9580 * still happen that the CS flip has been executed, but has not
9581 * yet actually completed. But in case the base address is the same
9582 * anyway, we don't really care.
9583 */
9584 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9585 crtc->unpin_work->gtt_offset &&
9586 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9587 crtc->unpin_work->flip_count);
9588 }
9589
9590 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9591 {
9592 struct drm_i915_private *dev_priv = dev->dev_private;
9593 struct intel_crtc *intel_crtc =
9594 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9595 unsigned long flags;
9596
9597
9598 /*
9599 * This is called both by irq handlers and the reset code (to complete
9600 * lost pageflips) so needs the full irqsave spinlocks.
9601 *
9602 * NB: An MMIO update of the plane base pointer will also
9603 * generate a page-flip completion irq, i.e. every modeset
9604 * is also accompanied by a spurious intel_prepare_page_flip().
9605 */
9606 spin_lock_irqsave(&dev->event_lock, flags);
9607 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9608 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9609 spin_unlock_irqrestore(&dev->event_lock, flags);
9610 }
9611
9612 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9613 {
9614 /* Ensure that the work item is consistent when activating it ... */
9615 smp_wmb();
9616 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9617 /* and that it is marked active as soon as the irq could fire. */
9618 smp_wmb();
9619 }
9620
9621 static int intel_gen2_queue_flip(struct drm_device *dev,
9622 struct drm_crtc *crtc,
9623 struct drm_framebuffer *fb,
9624 struct drm_i915_gem_object *obj,
9625 struct intel_engine_cs *ring,
9626 uint32_t flags)
9627 {
9628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9629 u32 flip_mask;
9630 int ret;
9631
9632 ret = intel_ring_begin(ring, 6);
9633 if (ret)
9634 return ret;
9635
9636 /* Can't queue multiple flips, so wait for the previous
9637 * one to finish before executing the next.
9638 */
9639 if (intel_crtc->plane)
9640 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9641 else
9642 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9643 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9644 intel_ring_emit(ring, MI_NOOP);
9645 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9646 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9647 intel_ring_emit(ring, fb->pitches[0]);
9648 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9649 intel_ring_emit(ring, 0); /* aux display base address, unused */
9650
9651 intel_mark_page_flip_active(intel_crtc);
9652 __intel_ring_advance(ring);
9653 return 0;
9654 }
9655
9656 static int intel_gen3_queue_flip(struct drm_device *dev,
9657 struct drm_crtc *crtc,
9658 struct drm_framebuffer *fb,
9659 struct drm_i915_gem_object *obj,
9660 struct intel_engine_cs *ring,
9661 uint32_t flags)
9662 {
9663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9664 u32 flip_mask;
9665 int ret;
9666
9667 ret = intel_ring_begin(ring, 6);
9668 if (ret)
9669 return ret;
9670
9671 if (intel_crtc->plane)
9672 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9673 else
9674 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9675 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9676 intel_ring_emit(ring, MI_NOOP);
9677 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9678 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9679 intel_ring_emit(ring, fb->pitches[0]);
9680 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9681 intel_ring_emit(ring, MI_NOOP);
9682
9683 intel_mark_page_flip_active(intel_crtc);
9684 __intel_ring_advance(ring);
9685 return 0;
9686 }
9687
9688 static int intel_gen4_queue_flip(struct drm_device *dev,
9689 struct drm_crtc *crtc,
9690 struct drm_framebuffer *fb,
9691 struct drm_i915_gem_object *obj,
9692 struct intel_engine_cs *ring,
9693 uint32_t flags)
9694 {
9695 struct drm_i915_private *dev_priv = dev->dev_private;
9696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9697 uint32_t pf, pipesrc;
9698 int ret;
9699
9700 ret = intel_ring_begin(ring, 4);
9701 if (ret)
9702 return ret;
9703
9704 /* i965+ uses the linear or tiled offsets from the
9705 * Display Registers (which do not change across a page-flip)
9706 * so we need only reprogram the base address.
9707 */
9708 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9709 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9710 intel_ring_emit(ring, fb->pitches[0]);
9711 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9712 obj->tiling_mode);
9713
9714 /* XXX Enabling the panel-fitter across page-flip is so far
9715 * untested on non-native modes, so ignore it for now.
9716 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9717 */
9718 pf = 0;
9719 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9720 intel_ring_emit(ring, pf | pipesrc);
9721
9722 intel_mark_page_flip_active(intel_crtc);
9723 __intel_ring_advance(ring);
9724 return 0;
9725 }
9726
9727 static int intel_gen6_queue_flip(struct drm_device *dev,
9728 struct drm_crtc *crtc,
9729 struct drm_framebuffer *fb,
9730 struct drm_i915_gem_object *obj,
9731 struct intel_engine_cs *ring,
9732 uint32_t flags)
9733 {
9734 struct drm_i915_private *dev_priv = dev->dev_private;
9735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9736 uint32_t pf, pipesrc;
9737 int ret;
9738
9739 ret = intel_ring_begin(ring, 4);
9740 if (ret)
9741 return ret;
9742
9743 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9744 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9745 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9746 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9747
9748 /* Contrary to the suggestions in the documentation,
9749 * "Enable Panel Fitter" does not seem to be required when page
9750 * flipping with a non-native mode, and worse causes a normal
9751 * modeset to fail.
9752 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9753 */
9754 pf = 0;
9755 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9756 intel_ring_emit(ring, pf | pipesrc);
9757
9758 intel_mark_page_flip_active(intel_crtc);
9759 __intel_ring_advance(ring);
9760 return 0;
9761 }
9762
9763 static int intel_gen7_queue_flip(struct drm_device *dev,
9764 struct drm_crtc *crtc,
9765 struct drm_framebuffer *fb,
9766 struct drm_i915_gem_object *obj,
9767 struct intel_engine_cs *ring,
9768 uint32_t flags)
9769 {
9770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9771 uint32_t plane_bit = 0;
9772 int len, ret;
9773
9774 switch (intel_crtc->plane) {
9775 case PLANE_A:
9776 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9777 break;
9778 case PLANE_B:
9779 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9780 break;
9781 case PLANE_C:
9782 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9783 break;
9784 default:
9785 WARN_ONCE(1, "unknown plane in flip command\n");
9786 return -ENODEV;
9787 }
9788
9789 len = 4;
9790 if (ring->id == RCS) {
9791 len += 6;
9792 /*
9793 * On Gen 8, SRM is now taking an extra dword to accommodate
9794 * 48bits addresses, and we need a NOOP for the batch size to
9795 * stay even.
9796 */
9797 if (IS_GEN8(dev))
9798 len += 2;
9799 }
9800
9801 /*
9802 * BSpec MI_DISPLAY_FLIP for IVB:
9803 * "The full packet must be contained within the same cache line."
9804 *
9805 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9806 * cacheline, if we ever start emitting more commands before
9807 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9808 * then do the cacheline alignment, and finally emit the
9809 * MI_DISPLAY_FLIP.
9810 */
9811 ret = intel_ring_cacheline_align(ring);
9812 if (ret)
9813 return ret;
9814
9815 ret = intel_ring_begin(ring, len);
9816 if (ret)
9817 return ret;
9818
9819 /* Unmask the flip-done completion message. Note that the bspec says that
9820 * we should do this for both the BCS and RCS, and that we must not unmask
9821 * more than one flip event at any time (or ensure that one flip message
9822 * can be sent by waiting for flip-done prior to queueing new flips).
9823 * Experimentation says that BCS works despite DERRMR masking all
9824 * flip-done completion events and that unmasking all planes at once
9825 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9826 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9827 */
9828 if (ring->id == RCS) {
9829 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9830 intel_ring_emit(ring, DERRMR);
9831 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9832 DERRMR_PIPEB_PRI_FLIP_DONE |
9833 DERRMR_PIPEC_PRI_FLIP_DONE));
9834 if (IS_GEN8(dev))
9835 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9836 MI_SRM_LRM_GLOBAL_GTT);
9837 else
9838 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9839 MI_SRM_LRM_GLOBAL_GTT);
9840 intel_ring_emit(ring, DERRMR);
9841 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9842 if (IS_GEN8(dev)) {
9843 intel_ring_emit(ring, 0);
9844 intel_ring_emit(ring, MI_NOOP);
9845 }
9846 }
9847
9848 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9849 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9850 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9851 intel_ring_emit(ring, (MI_NOOP));
9852
9853 intel_mark_page_flip_active(intel_crtc);
9854 __intel_ring_advance(ring);
9855 return 0;
9856 }
9857
9858 static bool use_mmio_flip(struct intel_engine_cs *ring,
9859 struct drm_i915_gem_object *obj)
9860 {
9861 /*
9862 * This is not being used for older platforms, because
9863 * non-availability of flip done interrupt forces us to use
9864 * CS flips. Older platforms derive flip done using some clever
9865 * tricks involving the flip_pending status bits and vblank irqs.
9866 * So using MMIO flips there would disrupt this mechanism.
9867 */
9868
9869 if (ring == NULL)
9870 return true;
9871
9872 if (INTEL_INFO(ring->dev)->gen < 5)
9873 return false;
9874
9875 if (i915.use_mmio_flip < 0)
9876 return false;
9877 else if (i915.use_mmio_flip > 0)
9878 return true;
9879 else if (i915.enable_execlists)
9880 return true;
9881 else
9882 return ring != i915_gem_request_get_ring(obj->last_read_req);
9883 }
9884
9885 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9886 {
9887 struct drm_device *dev = intel_crtc->base.dev;
9888 struct drm_i915_private *dev_priv = dev->dev_private;
9889 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9890 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9891 struct drm_i915_gem_object *obj = intel_fb->obj;
9892 const enum pipe pipe = intel_crtc->pipe;
9893 u32 ctl, stride;
9894
9895 ctl = I915_READ(PLANE_CTL(pipe, 0));
9896 ctl &= ~PLANE_CTL_TILED_MASK;
9897 if (obj->tiling_mode == I915_TILING_X)
9898 ctl |= PLANE_CTL_TILED_X;
9899
9900 /*
9901 * The stride is either expressed as a multiple of 64 bytes chunks for
9902 * linear buffers or in number of tiles for tiled buffers.
9903 */
9904 stride = fb->pitches[0] >> 6;
9905 if (obj->tiling_mode == I915_TILING_X)
9906 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9907
9908 /*
9909 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9910 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9911 */
9912 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9913 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9914
9915 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9916 POSTING_READ(PLANE_SURF(pipe, 0));
9917 }
9918
9919 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9920 {
9921 struct drm_device *dev = intel_crtc->base.dev;
9922 struct drm_i915_private *dev_priv = dev->dev_private;
9923 struct intel_framebuffer *intel_fb =
9924 to_intel_framebuffer(intel_crtc->base.primary->fb);
9925 struct drm_i915_gem_object *obj = intel_fb->obj;
9926 u32 dspcntr;
9927 u32 reg;
9928
9929 reg = DSPCNTR(intel_crtc->plane);
9930 dspcntr = I915_READ(reg);
9931
9932 if (obj->tiling_mode != I915_TILING_NONE)
9933 dspcntr |= DISPPLANE_TILED;
9934 else
9935 dspcntr &= ~DISPPLANE_TILED;
9936
9937 I915_WRITE(reg, dspcntr);
9938
9939 I915_WRITE(DSPSURF(intel_crtc->plane),
9940 intel_crtc->unpin_work->gtt_offset);
9941 POSTING_READ(DSPSURF(intel_crtc->plane));
9942
9943 }
9944
9945 /*
9946 * XXX: This is the temporary way to update the plane registers until we get
9947 * around to using the usual plane update functions for MMIO flips
9948 */
9949 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9950 {
9951 struct drm_device *dev = intel_crtc->base.dev;
9952 bool atomic_update;
9953 u32 start_vbl_count;
9954
9955 intel_mark_page_flip_active(intel_crtc);
9956
9957 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9958
9959 if (INTEL_INFO(dev)->gen >= 9)
9960 skl_do_mmio_flip(intel_crtc);
9961 else
9962 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9963 ilk_do_mmio_flip(intel_crtc);
9964
9965 if (atomic_update)
9966 intel_pipe_update_end(intel_crtc, start_vbl_count);
9967 }
9968
9969 static void intel_mmio_flip_work_func(struct work_struct *work)
9970 {
9971 struct intel_crtc *crtc =
9972 container_of(work, struct intel_crtc, mmio_flip.work);
9973 struct intel_mmio_flip *mmio_flip;
9974
9975 mmio_flip = &crtc->mmio_flip;
9976 if (mmio_flip->req)
9977 WARN_ON(__i915_wait_request(mmio_flip->req,
9978 crtc->reset_counter,
9979 false, NULL, NULL) != 0);
9980
9981 intel_do_mmio_flip(crtc);
9982 if (mmio_flip->req) {
9983 mutex_lock(&crtc->base.dev->struct_mutex);
9984 i915_gem_request_assign(&mmio_flip->req, NULL);
9985 mutex_unlock(&crtc->base.dev->struct_mutex);
9986 }
9987 }
9988
9989 static int intel_queue_mmio_flip(struct drm_device *dev,
9990 struct drm_crtc *crtc,
9991 struct drm_framebuffer *fb,
9992 struct drm_i915_gem_object *obj,
9993 struct intel_engine_cs *ring,
9994 uint32_t flags)
9995 {
9996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9997
9998 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9999 obj->last_write_req);
10000
10001 schedule_work(&intel_crtc->mmio_flip.work);
10002
10003 return 0;
10004 }
10005
10006 static int intel_default_queue_flip(struct drm_device *dev,
10007 struct drm_crtc *crtc,
10008 struct drm_framebuffer *fb,
10009 struct drm_i915_gem_object *obj,
10010 struct intel_engine_cs *ring,
10011 uint32_t flags)
10012 {
10013 return -ENODEV;
10014 }
10015
10016 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10017 struct drm_crtc *crtc)
10018 {
10019 struct drm_i915_private *dev_priv = dev->dev_private;
10020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10021 struct intel_unpin_work *work = intel_crtc->unpin_work;
10022 u32 addr;
10023
10024 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10025 return true;
10026
10027 if (!work->enable_stall_check)
10028 return false;
10029
10030 if (work->flip_ready_vblank == 0) {
10031 if (work->flip_queued_req &&
10032 !i915_gem_request_completed(work->flip_queued_req, true))
10033 return false;
10034
10035 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10036 }
10037
10038 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10039 return false;
10040
10041 /* Potential stall - if we see that the flip has happened,
10042 * assume a missed interrupt. */
10043 if (INTEL_INFO(dev)->gen >= 4)
10044 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10045 else
10046 addr = I915_READ(DSPADDR(intel_crtc->plane));
10047
10048 /* There is a potential issue here with a false positive after a flip
10049 * to the same address. We could address this by checking for a
10050 * non-incrementing frame counter.
10051 */
10052 return addr == work->gtt_offset;
10053 }
10054
10055 void intel_check_page_flip(struct drm_device *dev, int pipe)
10056 {
10057 struct drm_i915_private *dev_priv = dev->dev_private;
10058 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10060
10061 WARN_ON(!in_interrupt());
10062
10063 if (crtc == NULL)
10064 return;
10065
10066 spin_lock(&dev->event_lock);
10067 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10068 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10069 intel_crtc->unpin_work->flip_queued_vblank,
10070 drm_vblank_count(dev, pipe));
10071 page_flip_completed(intel_crtc);
10072 }
10073 spin_unlock(&dev->event_lock);
10074 }
10075
10076 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10077 struct drm_framebuffer *fb,
10078 struct drm_pending_vblank_event *event,
10079 uint32_t page_flip_flags)
10080 {
10081 struct drm_device *dev = crtc->dev;
10082 struct drm_i915_private *dev_priv = dev->dev_private;
10083 struct drm_framebuffer *old_fb = crtc->primary->fb;
10084 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10086 struct drm_plane *primary = crtc->primary;
10087 enum pipe pipe = intel_crtc->pipe;
10088 struct intel_unpin_work *work;
10089 struct intel_engine_cs *ring;
10090 int ret;
10091
10092 /*
10093 * drm_mode_page_flip_ioctl() should already catch this, but double
10094 * check to be safe. In the future we may enable pageflipping from
10095 * a disabled primary plane.
10096 */
10097 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10098 return -EBUSY;
10099
10100 /* Can't change pixel format via MI display flips. */
10101 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10102 return -EINVAL;
10103
10104 /*
10105 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10106 * Note that pitch changes could also affect these register.
10107 */
10108 if (INTEL_INFO(dev)->gen > 3 &&
10109 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10110 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10111 return -EINVAL;
10112
10113 if (i915_terminally_wedged(&dev_priv->gpu_error))
10114 goto out_hang;
10115
10116 work = kzalloc(sizeof(*work), GFP_KERNEL);
10117 if (work == NULL)
10118 return -ENOMEM;
10119
10120 work->event = event;
10121 work->crtc = crtc;
10122 work->old_fb = old_fb;
10123 INIT_WORK(&work->work, intel_unpin_work_fn);
10124
10125 ret = drm_crtc_vblank_get(crtc);
10126 if (ret)
10127 goto free_work;
10128
10129 /* We borrow the event spin lock for protecting unpin_work */
10130 spin_lock_irq(&dev->event_lock);
10131 if (intel_crtc->unpin_work) {
10132 /* Before declaring the flip queue wedged, check if
10133 * the hardware completed the operation behind our backs.
10134 */
10135 if (__intel_pageflip_stall_check(dev, crtc)) {
10136 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10137 page_flip_completed(intel_crtc);
10138 } else {
10139 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10140 spin_unlock_irq(&dev->event_lock);
10141
10142 drm_crtc_vblank_put(crtc);
10143 kfree(work);
10144 return -EBUSY;
10145 }
10146 }
10147 intel_crtc->unpin_work = work;
10148 spin_unlock_irq(&dev->event_lock);
10149
10150 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10151 flush_workqueue(dev_priv->wq);
10152
10153 /* Reference the objects for the scheduled work. */
10154 drm_framebuffer_reference(work->old_fb);
10155 drm_gem_object_reference(&obj->base);
10156
10157 crtc->primary->fb = fb;
10158 update_state_fb(crtc->primary);
10159
10160 work->pending_flip_obj = obj;
10161
10162 ret = i915_mutex_lock_interruptible(dev);
10163 if (ret)
10164 goto cleanup;
10165
10166 atomic_inc(&intel_crtc->unpin_work_count);
10167 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10168
10169 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10170 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10171
10172 if (IS_VALLEYVIEW(dev)) {
10173 ring = &dev_priv->ring[BCS];
10174 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10175 /* vlv: DISPLAY_FLIP fails to change tiling */
10176 ring = NULL;
10177 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10178 ring = &dev_priv->ring[BCS];
10179 } else if (INTEL_INFO(dev)->gen >= 7) {
10180 ring = i915_gem_request_get_ring(obj->last_read_req);
10181 if (ring == NULL || ring->id != RCS)
10182 ring = &dev_priv->ring[BCS];
10183 } else {
10184 ring = &dev_priv->ring[RCS];
10185 }
10186
10187 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10188 crtc->primary->state, ring);
10189 if (ret)
10190 goto cleanup_pending;
10191
10192 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10193 + intel_crtc->dspaddr_offset;
10194
10195 if (use_mmio_flip(ring, obj)) {
10196 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10197 page_flip_flags);
10198 if (ret)
10199 goto cleanup_unpin;
10200
10201 i915_gem_request_assign(&work->flip_queued_req,
10202 obj->last_write_req);
10203 } else {
10204 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10205 page_flip_flags);
10206 if (ret)
10207 goto cleanup_unpin;
10208
10209 i915_gem_request_assign(&work->flip_queued_req,
10210 intel_ring_get_request(ring));
10211 }
10212
10213 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10214 work->enable_stall_check = true;
10215
10216 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10217 INTEL_FRONTBUFFER_PRIMARY(pipe));
10218
10219 intel_fbc_disable(dev);
10220 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10221 mutex_unlock(&dev->struct_mutex);
10222
10223 trace_i915_flip_request(intel_crtc->plane, obj);
10224
10225 return 0;
10226
10227 cleanup_unpin:
10228 intel_unpin_fb_obj(fb, crtc->primary->state);
10229 cleanup_pending:
10230 atomic_dec(&intel_crtc->unpin_work_count);
10231 mutex_unlock(&dev->struct_mutex);
10232 cleanup:
10233 crtc->primary->fb = old_fb;
10234 update_state_fb(crtc->primary);
10235
10236 drm_gem_object_unreference_unlocked(&obj->base);
10237 drm_framebuffer_unreference(work->old_fb);
10238
10239 spin_lock_irq(&dev->event_lock);
10240 intel_crtc->unpin_work = NULL;
10241 spin_unlock_irq(&dev->event_lock);
10242
10243 drm_crtc_vblank_put(crtc);
10244 free_work:
10245 kfree(work);
10246
10247 if (ret == -EIO) {
10248 out_hang:
10249 ret = intel_plane_restore(primary);
10250 if (ret == 0 && event) {
10251 spin_lock_irq(&dev->event_lock);
10252 drm_send_vblank_event(dev, pipe, event);
10253 spin_unlock_irq(&dev->event_lock);
10254 }
10255 }
10256 return ret;
10257 }
10258
10259 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10260 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10261 .load_lut = intel_crtc_load_lut,
10262 .atomic_begin = intel_begin_crtc_commit,
10263 .atomic_flush = intel_finish_crtc_commit,
10264 };
10265
10266 /**
10267 * intel_modeset_update_staged_output_state
10268 *
10269 * Updates the staged output configuration state, e.g. after we've read out the
10270 * current hw state.
10271 */
10272 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10273 {
10274 struct intel_crtc *crtc;
10275 struct intel_encoder *encoder;
10276 struct intel_connector *connector;
10277
10278 for_each_intel_connector(dev, connector) {
10279 connector->new_encoder =
10280 to_intel_encoder(connector->base.encoder);
10281 }
10282
10283 for_each_intel_encoder(dev, encoder) {
10284 encoder->new_crtc =
10285 to_intel_crtc(encoder->base.crtc);
10286 }
10287
10288 for_each_intel_crtc(dev, crtc) {
10289 crtc->new_enabled = crtc->base.state->enable;
10290
10291 if (crtc->new_enabled)
10292 crtc->new_config = crtc->config;
10293 else
10294 crtc->new_config = NULL;
10295 }
10296 }
10297
10298 /* Transitional helper to copy current connector/encoder state to
10299 * connector->state. This is needed so that code that is partially
10300 * converted to atomic does the right thing.
10301 */
10302 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10303 {
10304 struct intel_connector *connector;
10305
10306 for_each_intel_connector(dev, connector) {
10307 if (connector->base.encoder) {
10308 connector->base.state->best_encoder =
10309 connector->base.encoder;
10310 connector->base.state->crtc =
10311 connector->base.encoder->crtc;
10312 } else {
10313 connector->base.state->best_encoder = NULL;
10314 connector->base.state->crtc = NULL;
10315 }
10316 }
10317 }
10318
10319 /**
10320 * intel_modeset_commit_output_state
10321 *
10322 * This function copies the stage display pipe configuration to the real one.
10323 */
10324 static void intel_modeset_commit_output_state(struct drm_device *dev)
10325 {
10326 struct intel_crtc *crtc;
10327 struct intel_encoder *encoder;
10328 struct intel_connector *connector;
10329
10330 for_each_intel_connector(dev, connector) {
10331 connector->base.encoder = &connector->new_encoder->base;
10332 }
10333
10334 for_each_intel_encoder(dev, encoder) {
10335 encoder->base.crtc = &encoder->new_crtc->base;
10336 }
10337
10338 for_each_intel_crtc(dev, crtc) {
10339 crtc->base.state->enable = crtc->new_enabled;
10340 crtc->base.enabled = crtc->new_enabled;
10341 }
10342
10343 intel_modeset_update_connector_atomic_state(dev);
10344 }
10345
10346 static void
10347 connected_sink_compute_bpp(struct intel_connector *connector,
10348 struct intel_crtc_state *pipe_config)
10349 {
10350 int bpp = pipe_config->pipe_bpp;
10351
10352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10353 connector->base.base.id,
10354 connector->base.name);
10355
10356 /* Don't use an invalid EDID bpc value */
10357 if (connector->base.display_info.bpc &&
10358 connector->base.display_info.bpc * 3 < bpp) {
10359 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10360 bpp, connector->base.display_info.bpc*3);
10361 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10362 }
10363
10364 /* Clamp bpp to 8 on screens without EDID 1.4 */
10365 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10366 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10367 bpp);
10368 pipe_config->pipe_bpp = 24;
10369 }
10370 }
10371
10372 static int
10373 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10374 struct drm_framebuffer *fb,
10375 struct intel_crtc_state *pipe_config)
10376 {
10377 struct drm_device *dev = crtc->base.dev;
10378 struct drm_atomic_state *state;
10379 struct intel_connector *connector;
10380 int bpp, i;
10381
10382 switch (fb->pixel_format) {
10383 case DRM_FORMAT_C8:
10384 bpp = 8*3; /* since we go through a colormap */
10385 break;
10386 case DRM_FORMAT_XRGB1555:
10387 case DRM_FORMAT_ARGB1555:
10388 /* checked in intel_framebuffer_init already */
10389 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10390 return -EINVAL;
10391 case DRM_FORMAT_RGB565:
10392 bpp = 6*3; /* min is 18bpp */
10393 break;
10394 case DRM_FORMAT_XBGR8888:
10395 case DRM_FORMAT_ABGR8888:
10396 /* checked in intel_framebuffer_init already */
10397 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10398 return -EINVAL;
10399 case DRM_FORMAT_XRGB8888:
10400 case DRM_FORMAT_ARGB8888:
10401 bpp = 8*3;
10402 break;
10403 case DRM_FORMAT_XRGB2101010:
10404 case DRM_FORMAT_ARGB2101010:
10405 case DRM_FORMAT_XBGR2101010:
10406 case DRM_FORMAT_ABGR2101010:
10407 /* checked in intel_framebuffer_init already */
10408 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10409 return -EINVAL;
10410 bpp = 10*3;
10411 break;
10412 /* TODO: gen4+ supports 16 bpc floating point, too. */
10413 default:
10414 DRM_DEBUG_KMS("unsupported depth\n");
10415 return -EINVAL;
10416 }
10417
10418 pipe_config->pipe_bpp = bpp;
10419
10420 state = pipe_config->base.state;
10421
10422 /* Clamp display bpp to EDID value */
10423 for (i = 0; i < state->num_connector; i++) {
10424 if (!state->connectors[i])
10425 continue;
10426
10427 connector = to_intel_connector(state->connectors[i]);
10428 if (state->connector_states[i]->crtc != &crtc->base)
10429 continue;
10430
10431 connected_sink_compute_bpp(connector, pipe_config);
10432 }
10433
10434 return bpp;
10435 }
10436
10437 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10438 {
10439 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10440 "type: 0x%x flags: 0x%x\n",
10441 mode->crtc_clock,
10442 mode->crtc_hdisplay, mode->crtc_hsync_start,
10443 mode->crtc_hsync_end, mode->crtc_htotal,
10444 mode->crtc_vdisplay, mode->crtc_vsync_start,
10445 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10446 }
10447
10448 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10449 struct intel_crtc_state *pipe_config,
10450 const char *context)
10451 {
10452 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10453 context, pipe_name(crtc->pipe));
10454
10455 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10456 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10457 pipe_config->pipe_bpp, pipe_config->dither);
10458 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10459 pipe_config->has_pch_encoder,
10460 pipe_config->fdi_lanes,
10461 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10462 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10463 pipe_config->fdi_m_n.tu);
10464 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10465 pipe_config->has_dp_encoder,
10466 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10467 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10468 pipe_config->dp_m_n.tu);
10469
10470 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10471 pipe_config->has_dp_encoder,
10472 pipe_config->dp_m2_n2.gmch_m,
10473 pipe_config->dp_m2_n2.gmch_n,
10474 pipe_config->dp_m2_n2.link_m,
10475 pipe_config->dp_m2_n2.link_n,
10476 pipe_config->dp_m2_n2.tu);
10477
10478 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10479 pipe_config->has_audio,
10480 pipe_config->has_infoframe);
10481
10482 DRM_DEBUG_KMS("requested mode:\n");
10483 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10484 DRM_DEBUG_KMS("adjusted mode:\n");
10485 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10486 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10487 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10488 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10489 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10490 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10491 pipe_config->gmch_pfit.control,
10492 pipe_config->gmch_pfit.pgm_ratios,
10493 pipe_config->gmch_pfit.lvds_border_bits);
10494 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10495 pipe_config->pch_pfit.pos,
10496 pipe_config->pch_pfit.size,
10497 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10498 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10499 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10500 }
10501
10502 static bool encoders_cloneable(const struct intel_encoder *a,
10503 const struct intel_encoder *b)
10504 {
10505 /* masks could be asymmetric, so check both ways */
10506 return a == b || (a->cloneable & (1 << b->type) &&
10507 b->cloneable & (1 << a->type));
10508 }
10509
10510 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10511 struct intel_encoder *encoder)
10512 {
10513 struct drm_device *dev = crtc->base.dev;
10514 struct intel_encoder *source_encoder;
10515
10516 for_each_intel_encoder(dev, source_encoder) {
10517 if (source_encoder->new_crtc != crtc)
10518 continue;
10519
10520 if (!encoders_cloneable(encoder, source_encoder))
10521 return false;
10522 }
10523
10524 return true;
10525 }
10526
10527 static bool check_encoder_cloning(struct intel_crtc *crtc)
10528 {
10529 struct drm_device *dev = crtc->base.dev;
10530 struct intel_encoder *encoder;
10531
10532 for_each_intel_encoder(dev, encoder) {
10533 if (encoder->new_crtc != crtc)
10534 continue;
10535
10536 if (!check_single_encoder_cloning(crtc, encoder))
10537 return false;
10538 }
10539
10540 return true;
10541 }
10542
10543 static bool check_digital_port_conflicts(struct drm_device *dev)
10544 {
10545 struct intel_connector *connector;
10546 unsigned int used_ports = 0;
10547
10548 /*
10549 * Walk the connector list instead of the encoder
10550 * list to detect the problem on ddi platforms
10551 * where there's just one encoder per digital port.
10552 */
10553 for_each_intel_connector(dev, connector) {
10554 struct intel_encoder *encoder = connector->new_encoder;
10555
10556 if (!encoder)
10557 continue;
10558
10559 WARN_ON(!encoder->new_crtc);
10560
10561 switch (encoder->type) {
10562 unsigned int port_mask;
10563 case INTEL_OUTPUT_UNKNOWN:
10564 if (WARN_ON(!HAS_DDI(dev)))
10565 break;
10566 case INTEL_OUTPUT_DISPLAYPORT:
10567 case INTEL_OUTPUT_HDMI:
10568 case INTEL_OUTPUT_EDP:
10569 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10570
10571 /* the same port mustn't appear more than once */
10572 if (used_ports & port_mask)
10573 return false;
10574
10575 used_ports |= port_mask;
10576 default:
10577 break;
10578 }
10579 }
10580
10581 return true;
10582 }
10583
10584 static void
10585 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10586 {
10587 struct drm_crtc_state tmp_state;
10588
10589 /* Clear only the intel specific part of the crtc state */
10590 tmp_state = crtc_state->base;
10591 memset(crtc_state, 0, sizeof *crtc_state);
10592 crtc_state->base = tmp_state;
10593 }
10594
10595 static struct intel_crtc_state *
10596 intel_modeset_pipe_config(struct drm_crtc *crtc,
10597 struct drm_framebuffer *fb,
10598 struct drm_display_mode *mode,
10599 struct drm_atomic_state *state)
10600 {
10601 struct drm_device *dev = crtc->dev;
10602 struct intel_encoder *encoder;
10603 struct intel_connector *connector;
10604 struct drm_connector_state *connector_state;
10605 struct intel_crtc_state *pipe_config;
10606 int plane_bpp, ret = -EINVAL;
10607 int i;
10608 bool retry = true;
10609
10610 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10611 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10612 return ERR_PTR(-EINVAL);
10613 }
10614
10615 if (!check_digital_port_conflicts(dev)) {
10616 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10617 return ERR_PTR(-EINVAL);
10618 }
10619
10620 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10621 if (IS_ERR(pipe_config))
10622 return pipe_config;
10623
10624 clear_intel_crtc_state(pipe_config);
10625
10626 pipe_config->base.crtc = crtc;
10627 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10628 drm_mode_copy(&pipe_config->base.mode, mode);
10629
10630 pipe_config->cpu_transcoder =
10631 (enum transcoder) to_intel_crtc(crtc)->pipe;
10632 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10633
10634 /*
10635 * Sanitize sync polarity flags based on requested ones. If neither
10636 * positive or negative polarity is requested, treat this as meaning
10637 * negative polarity.
10638 */
10639 if (!(pipe_config->base.adjusted_mode.flags &
10640 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10641 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10642
10643 if (!(pipe_config->base.adjusted_mode.flags &
10644 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10645 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10646
10647 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10648 * plane pixel format and any sink constraints into account. Returns the
10649 * source plane bpp so that dithering can be selected on mismatches
10650 * after encoders and crtc also have had their say. */
10651 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10652 fb, pipe_config);
10653 if (plane_bpp < 0)
10654 goto fail;
10655
10656 /*
10657 * Determine the real pipe dimensions. Note that stereo modes can
10658 * increase the actual pipe size due to the frame doubling and
10659 * insertion of additional space for blanks between the frame. This
10660 * is stored in the crtc timings. We use the requested mode to do this
10661 * computation to clearly distinguish it from the adjusted mode, which
10662 * can be changed by the connectors in the below retry loop.
10663 */
10664 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10665 &pipe_config->pipe_src_w,
10666 &pipe_config->pipe_src_h);
10667
10668 encoder_retry:
10669 /* Ensure the port clock defaults are reset when retrying. */
10670 pipe_config->port_clock = 0;
10671 pipe_config->pixel_multiplier = 1;
10672
10673 /* Fill in default crtc timings, allow encoders to overwrite them. */
10674 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10675 CRTC_STEREO_DOUBLE);
10676
10677 /* Pass our mode to the connectors and the CRTC to give them a chance to
10678 * adjust it according to limitations or connector properties, and also
10679 * a chance to reject the mode entirely.
10680 */
10681 for (i = 0; i < state->num_connector; i++) {
10682 connector = to_intel_connector(state->connectors[i]);
10683 if (!connector)
10684 continue;
10685
10686 connector_state = state->connector_states[i];
10687 if (connector_state->crtc != crtc)
10688 continue;
10689
10690 encoder = to_intel_encoder(connector_state->best_encoder);
10691
10692 if (!(encoder->compute_config(encoder, pipe_config))) {
10693 DRM_DEBUG_KMS("Encoder config failure\n");
10694 goto fail;
10695 }
10696 }
10697
10698 /* Set default port clock if not overwritten by the encoder. Needs to be
10699 * done afterwards in case the encoder adjusts the mode. */
10700 if (!pipe_config->port_clock)
10701 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10702 * pipe_config->pixel_multiplier;
10703
10704 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10705 if (ret < 0) {
10706 DRM_DEBUG_KMS("CRTC fixup failed\n");
10707 goto fail;
10708 }
10709
10710 if (ret == RETRY) {
10711 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10712 ret = -EINVAL;
10713 goto fail;
10714 }
10715
10716 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10717 retry = false;
10718 goto encoder_retry;
10719 }
10720
10721 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10722 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10723 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10724
10725 return pipe_config;
10726 fail:
10727 return ERR_PTR(ret);
10728 }
10729
10730 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10731 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10732 static void
10733 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10734 unsigned *prepare_pipes, unsigned *disable_pipes)
10735 {
10736 struct intel_crtc *intel_crtc;
10737 struct drm_device *dev = crtc->dev;
10738 struct intel_encoder *encoder;
10739 struct intel_connector *connector;
10740 struct drm_crtc *tmp_crtc;
10741
10742 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10743
10744 /* Check which crtcs have changed outputs connected to them, these need
10745 * to be part of the prepare_pipes mask. We don't (yet) support global
10746 * modeset across multiple crtcs, so modeset_pipes will only have one
10747 * bit set at most. */
10748 for_each_intel_connector(dev, connector) {
10749 if (connector->base.encoder == &connector->new_encoder->base)
10750 continue;
10751
10752 if (connector->base.encoder) {
10753 tmp_crtc = connector->base.encoder->crtc;
10754
10755 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10756 }
10757
10758 if (connector->new_encoder)
10759 *prepare_pipes |=
10760 1 << connector->new_encoder->new_crtc->pipe;
10761 }
10762
10763 for_each_intel_encoder(dev, encoder) {
10764 if (encoder->base.crtc == &encoder->new_crtc->base)
10765 continue;
10766
10767 if (encoder->base.crtc) {
10768 tmp_crtc = encoder->base.crtc;
10769
10770 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10771 }
10772
10773 if (encoder->new_crtc)
10774 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10775 }
10776
10777 /* Check for pipes that will be enabled/disabled ... */
10778 for_each_intel_crtc(dev, intel_crtc) {
10779 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10780 continue;
10781
10782 if (!intel_crtc->new_enabled)
10783 *disable_pipes |= 1 << intel_crtc->pipe;
10784 else
10785 *prepare_pipes |= 1 << intel_crtc->pipe;
10786 }
10787
10788
10789 /* set_mode is also used to update properties on life display pipes. */
10790 intel_crtc = to_intel_crtc(crtc);
10791 if (intel_crtc->new_enabled)
10792 *prepare_pipes |= 1 << intel_crtc->pipe;
10793
10794 /*
10795 * For simplicity do a full modeset on any pipe where the output routing
10796 * changed. We could be more clever, but that would require us to be
10797 * more careful with calling the relevant encoder->mode_set functions.
10798 */
10799 if (*prepare_pipes)
10800 *modeset_pipes = *prepare_pipes;
10801
10802 /* ... and mask these out. */
10803 *modeset_pipes &= ~(*disable_pipes);
10804 *prepare_pipes &= ~(*disable_pipes);
10805
10806 /*
10807 * HACK: We don't (yet) fully support global modesets. intel_set_config
10808 * obies this rule, but the modeset restore mode of
10809 * intel_modeset_setup_hw_state does not.
10810 */
10811 *modeset_pipes &= 1 << intel_crtc->pipe;
10812 *prepare_pipes &= 1 << intel_crtc->pipe;
10813
10814 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10815 *modeset_pipes, *prepare_pipes, *disable_pipes);
10816 }
10817
10818 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10819 {
10820 struct drm_encoder *encoder;
10821 struct drm_device *dev = crtc->dev;
10822
10823 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10824 if (encoder->crtc == crtc)
10825 return true;
10826
10827 return false;
10828 }
10829
10830 static void
10831 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10832 {
10833 struct drm_i915_private *dev_priv = dev->dev_private;
10834 struct intel_encoder *intel_encoder;
10835 struct intel_crtc *intel_crtc;
10836 struct drm_connector *connector;
10837
10838 intel_shared_dpll_commit(dev_priv);
10839
10840 for_each_intel_encoder(dev, intel_encoder) {
10841 if (!intel_encoder->base.crtc)
10842 continue;
10843
10844 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10845
10846 if (prepare_pipes & (1 << intel_crtc->pipe))
10847 intel_encoder->connectors_active = false;
10848 }
10849
10850 intel_modeset_commit_output_state(dev);
10851
10852 /* Double check state. */
10853 for_each_intel_crtc(dev, intel_crtc) {
10854 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10855 WARN_ON(intel_crtc->new_config &&
10856 intel_crtc->new_config != intel_crtc->config);
10857 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10858 }
10859
10860 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10861 if (!connector->encoder || !connector->encoder->crtc)
10862 continue;
10863
10864 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10865
10866 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10867 struct drm_property *dpms_property =
10868 dev->mode_config.dpms_property;
10869
10870 connector->dpms = DRM_MODE_DPMS_ON;
10871 drm_object_property_set_value(&connector->base,
10872 dpms_property,
10873 DRM_MODE_DPMS_ON);
10874
10875 intel_encoder = to_intel_encoder(connector->encoder);
10876 intel_encoder->connectors_active = true;
10877 }
10878 }
10879
10880 }
10881
10882 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10883 {
10884 int diff;
10885
10886 if (clock1 == clock2)
10887 return true;
10888
10889 if (!clock1 || !clock2)
10890 return false;
10891
10892 diff = abs(clock1 - clock2);
10893
10894 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10895 return true;
10896
10897 return false;
10898 }
10899
10900 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10901 list_for_each_entry((intel_crtc), \
10902 &(dev)->mode_config.crtc_list, \
10903 base.head) \
10904 if (mask & (1 <<(intel_crtc)->pipe))
10905
10906 static bool
10907 intel_pipe_config_compare(struct drm_device *dev,
10908 struct intel_crtc_state *current_config,
10909 struct intel_crtc_state *pipe_config)
10910 {
10911 #define PIPE_CONF_CHECK_X(name) \
10912 if (current_config->name != pipe_config->name) { \
10913 DRM_ERROR("mismatch in " #name " " \
10914 "(expected 0x%08x, found 0x%08x)\n", \
10915 current_config->name, \
10916 pipe_config->name); \
10917 return false; \
10918 }
10919
10920 #define PIPE_CONF_CHECK_I(name) \
10921 if (current_config->name != pipe_config->name) { \
10922 DRM_ERROR("mismatch in " #name " " \
10923 "(expected %i, found %i)\n", \
10924 current_config->name, \
10925 pipe_config->name); \
10926 return false; \
10927 }
10928
10929 /* This is required for BDW+ where there is only one set of registers for
10930 * switching between high and low RR.
10931 * This macro can be used whenever a comparison has to be made between one
10932 * hw state and multiple sw state variables.
10933 */
10934 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10935 if ((current_config->name != pipe_config->name) && \
10936 (current_config->alt_name != pipe_config->name)) { \
10937 DRM_ERROR("mismatch in " #name " " \
10938 "(expected %i or %i, found %i)\n", \
10939 current_config->name, \
10940 current_config->alt_name, \
10941 pipe_config->name); \
10942 return false; \
10943 }
10944
10945 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10946 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10947 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10948 "(expected %i, found %i)\n", \
10949 current_config->name & (mask), \
10950 pipe_config->name & (mask)); \
10951 return false; \
10952 }
10953
10954 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10955 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10956 DRM_ERROR("mismatch in " #name " " \
10957 "(expected %i, found %i)\n", \
10958 current_config->name, \
10959 pipe_config->name); \
10960 return false; \
10961 }
10962
10963 #define PIPE_CONF_QUIRK(quirk) \
10964 ((current_config->quirks | pipe_config->quirks) & (quirk))
10965
10966 PIPE_CONF_CHECK_I(cpu_transcoder);
10967
10968 PIPE_CONF_CHECK_I(has_pch_encoder);
10969 PIPE_CONF_CHECK_I(fdi_lanes);
10970 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10971 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10972 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10973 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10974 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10975
10976 PIPE_CONF_CHECK_I(has_dp_encoder);
10977
10978 if (INTEL_INFO(dev)->gen < 8) {
10979 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10980 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10981 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10982 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10983 PIPE_CONF_CHECK_I(dp_m_n.tu);
10984
10985 if (current_config->has_drrs) {
10986 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10987 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10988 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10989 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10990 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10991 }
10992 } else {
10993 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10994 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10995 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10996 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10997 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10998 }
10999
11000 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11001 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11002 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11003 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11004 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11005 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11006
11007 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11008 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11009 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11010 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11011 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11012 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11013
11014 PIPE_CONF_CHECK_I(pixel_multiplier);
11015 PIPE_CONF_CHECK_I(has_hdmi_sink);
11016 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11017 IS_VALLEYVIEW(dev))
11018 PIPE_CONF_CHECK_I(limited_color_range);
11019 PIPE_CONF_CHECK_I(has_infoframe);
11020
11021 PIPE_CONF_CHECK_I(has_audio);
11022
11023 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11024 DRM_MODE_FLAG_INTERLACE);
11025
11026 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11027 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11028 DRM_MODE_FLAG_PHSYNC);
11029 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11030 DRM_MODE_FLAG_NHSYNC);
11031 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11032 DRM_MODE_FLAG_PVSYNC);
11033 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11034 DRM_MODE_FLAG_NVSYNC);
11035 }
11036
11037 PIPE_CONF_CHECK_I(pipe_src_w);
11038 PIPE_CONF_CHECK_I(pipe_src_h);
11039
11040 /*
11041 * FIXME: BIOS likes to set up a cloned config with lvds+external
11042 * screen. Since we don't yet re-compute the pipe config when moving
11043 * just the lvds port away to another pipe the sw tracking won't match.
11044 *
11045 * Proper atomic modesets with recomputed global state will fix this.
11046 * Until then just don't check gmch state for inherited modes.
11047 */
11048 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11049 PIPE_CONF_CHECK_I(gmch_pfit.control);
11050 /* pfit ratios are autocomputed by the hw on gen4+ */
11051 if (INTEL_INFO(dev)->gen < 4)
11052 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11053 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11054 }
11055
11056 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11057 if (current_config->pch_pfit.enabled) {
11058 PIPE_CONF_CHECK_I(pch_pfit.pos);
11059 PIPE_CONF_CHECK_I(pch_pfit.size);
11060 }
11061
11062 /* BDW+ don't expose a synchronous way to read the state */
11063 if (IS_HASWELL(dev))
11064 PIPE_CONF_CHECK_I(ips_enabled);
11065
11066 PIPE_CONF_CHECK_I(double_wide);
11067
11068 PIPE_CONF_CHECK_X(ddi_pll_sel);
11069
11070 PIPE_CONF_CHECK_I(shared_dpll);
11071 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11072 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11073 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11074 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11075 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11076 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11077 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11078 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11079
11080 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11081 PIPE_CONF_CHECK_I(pipe_bpp);
11082
11083 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11084 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11085
11086 #undef PIPE_CONF_CHECK_X
11087 #undef PIPE_CONF_CHECK_I
11088 #undef PIPE_CONF_CHECK_I_ALT
11089 #undef PIPE_CONF_CHECK_FLAGS
11090 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11091 #undef PIPE_CONF_QUIRK
11092
11093 return true;
11094 }
11095
11096 static void check_wm_state(struct drm_device *dev)
11097 {
11098 struct drm_i915_private *dev_priv = dev->dev_private;
11099 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11100 struct intel_crtc *intel_crtc;
11101 int plane;
11102
11103 if (INTEL_INFO(dev)->gen < 9)
11104 return;
11105
11106 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11107 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11108
11109 for_each_intel_crtc(dev, intel_crtc) {
11110 struct skl_ddb_entry *hw_entry, *sw_entry;
11111 const enum pipe pipe = intel_crtc->pipe;
11112
11113 if (!intel_crtc->active)
11114 continue;
11115
11116 /* planes */
11117 for_each_plane(dev_priv, pipe, plane) {
11118 hw_entry = &hw_ddb.plane[pipe][plane];
11119 sw_entry = &sw_ddb->plane[pipe][plane];
11120
11121 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11122 continue;
11123
11124 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11125 "(expected (%u,%u), found (%u,%u))\n",
11126 pipe_name(pipe), plane + 1,
11127 sw_entry->start, sw_entry->end,
11128 hw_entry->start, hw_entry->end);
11129 }
11130
11131 /* cursor */
11132 hw_entry = &hw_ddb.cursor[pipe];
11133 sw_entry = &sw_ddb->cursor[pipe];
11134
11135 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11136 continue;
11137
11138 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11139 "(expected (%u,%u), found (%u,%u))\n",
11140 pipe_name(pipe),
11141 sw_entry->start, sw_entry->end,
11142 hw_entry->start, hw_entry->end);
11143 }
11144 }
11145
11146 static void
11147 check_connector_state(struct drm_device *dev)
11148 {
11149 struct intel_connector *connector;
11150
11151 for_each_intel_connector(dev, connector) {
11152 /* This also checks the encoder/connector hw state with the
11153 * ->get_hw_state callbacks. */
11154 intel_connector_check_state(connector);
11155
11156 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11157 "connector's staged encoder doesn't match current encoder\n");
11158 }
11159 }
11160
11161 static void
11162 check_encoder_state(struct drm_device *dev)
11163 {
11164 struct intel_encoder *encoder;
11165 struct intel_connector *connector;
11166
11167 for_each_intel_encoder(dev, encoder) {
11168 bool enabled = false;
11169 bool active = false;
11170 enum pipe pipe, tracked_pipe;
11171
11172 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11173 encoder->base.base.id,
11174 encoder->base.name);
11175
11176 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11177 "encoder's stage crtc doesn't match current crtc\n");
11178 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11179 "encoder's active_connectors set, but no crtc\n");
11180
11181 for_each_intel_connector(dev, connector) {
11182 if (connector->base.encoder != &encoder->base)
11183 continue;
11184 enabled = true;
11185 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11186 active = true;
11187 }
11188 /*
11189 * for MST connectors if we unplug the connector is gone
11190 * away but the encoder is still connected to a crtc
11191 * until a modeset happens in response to the hotplug.
11192 */
11193 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11194 continue;
11195
11196 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11197 "encoder's enabled state mismatch "
11198 "(expected %i, found %i)\n",
11199 !!encoder->base.crtc, enabled);
11200 I915_STATE_WARN(active && !encoder->base.crtc,
11201 "active encoder with no crtc\n");
11202
11203 I915_STATE_WARN(encoder->connectors_active != active,
11204 "encoder's computed active state doesn't match tracked active state "
11205 "(expected %i, found %i)\n", active, encoder->connectors_active);
11206
11207 active = encoder->get_hw_state(encoder, &pipe);
11208 I915_STATE_WARN(active != encoder->connectors_active,
11209 "encoder's hw state doesn't match sw tracking "
11210 "(expected %i, found %i)\n",
11211 encoder->connectors_active, active);
11212
11213 if (!encoder->base.crtc)
11214 continue;
11215
11216 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
11217 I915_STATE_WARN(active && pipe != tracked_pipe,
11218 "active encoder's pipe doesn't match"
11219 "(expected %i, found %i)\n",
11220 tracked_pipe, pipe);
11221
11222 }
11223 }
11224
11225 static void
11226 check_crtc_state(struct drm_device *dev)
11227 {
11228 struct drm_i915_private *dev_priv = dev->dev_private;
11229 struct intel_crtc *crtc;
11230 struct intel_encoder *encoder;
11231 struct intel_crtc_state pipe_config;
11232
11233 for_each_intel_crtc(dev, crtc) {
11234 bool enabled = false;
11235 bool active = false;
11236
11237 memset(&pipe_config, 0, sizeof(pipe_config));
11238
11239 DRM_DEBUG_KMS("[CRTC:%d]\n",
11240 crtc->base.base.id);
11241
11242 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11243 "active crtc, but not enabled in sw tracking\n");
11244
11245 for_each_intel_encoder(dev, encoder) {
11246 if (encoder->base.crtc != &crtc->base)
11247 continue;
11248 enabled = true;
11249 if (encoder->connectors_active)
11250 active = true;
11251 }
11252
11253 I915_STATE_WARN(active != crtc->active,
11254 "crtc's computed active state doesn't match tracked active state "
11255 "(expected %i, found %i)\n", active, crtc->active);
11256 I915_STATE_WARN(enabled != crtc->base.state->enable,
11257 "crtc's computed enabled state doesn't match tracked enabled state "
11258 "(expected %i, found %i)\n", enabled,
11259 crtc->base.state->enable);
11260
11261 active = dev_priv->display.get_pipe_config(crtc,
11262 &pipe_config);
11263
11264 /* hw state is inconsistent with the pipe quirk */
11265 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11266 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11267 active = crtc->active;
11268
11269 for_each_intel_encoder(dev, encoder) {
11270 enum pipe pipe;
11271 if (encoder->base.crtc != &crtc->base)
11272 continue;
11273 if (encoder->get_hw_state(encoder, &pipe))
11274 encoder->get_config(encoder, &pipe_config);
11275 }
11276
11277 I915_STATE_WARN(crtc->active != active,
11278 "crtc active state doesn't match with hw state "
11279 "(expected %i, found %i)\n", crtc->active, active);
11280
11281 if (active &&
11282 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11283 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11284 intel_dump_pipe_config(crtc, &pipe_config,
11285 "[hw state]");
11286 intel_dump_pipe_config(crtc, crtc->config,
11287 "[sw state]");
11288 }
11289 }
11290 }
11291
11292 static void
11293 check_shared_dpll_state(struct drm_device *dev)
11294 {
11295 struct drm_i915_private *dev_priv = dev->dev_private;
11296 struct intel_crtc *crtc;
11297 struct intel_dpll_hw_state dpll_hw_state;
11298 int i;
11299
11300 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11301 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11302 int enabled_crtcs = 0, active_crtcs = 0;
11303 bool active;
11304
11305 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11306
11307 DRM_DEBUG_KMS("%s\n", pll->name);
11308
11309 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11310
11311 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11312 "more active pll users than references: %i vs %i\n",
11313 pll->active, hweight32(pll->config.crtc_mask));
11314 I915_STATE_WARN(pll->active && !pll->on,
11315 "pll in active use but not on in sw tracking\n");
11316 I915_STATE_WARN(pll->on && !pll->active,
11317 "pll in on but not on in use in sw tracking\n");
11318 I915_STATE_WARN(pll->on != active,
11319 "pll on state mismatch (expected %i, found %i)\n",
11320 pll->on, active);
11321
11322 for_each_intel_crtc(dev, crtc) {
11323 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11324 enabled_crtcs++;
11325 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11326 active_crtcs++;
11327 }
11328 I915_STATE_WARN(pll->active != active_crtcs,
11329 "pll active crtcs mismatch (expected %i, found %i)\n",
11330 pll->active, active_crtcs);
11331 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11332 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11333 hweight32(pll->config.crtc_mask), enabled_crtcs);
11334
11335 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11336 sizeof(dpll_hw_state)),
11337 "pll hw state mismatch\n");
11338 }
11339 }
11340
11341 void
11342 intel_modeset_check_state(struct drm_device *dev)
11343 {
11344 check_wm_state(dev);
11345 check_connector_state(dev);
11346 check_encoder_state(dev);
11347 check_crtc_state(dev);
11348 check_shared_dpll_state(dev);
11349 }
11350
11351 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11352 int dotclock)
11353 {
11354 /*
11355 * FDI already provided one idea for the dotclock.
11356 * Yell if the encoder disagrees.
11357 */
11358 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11359 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11360 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11361 }
11362
11363 static void update_scanline_offset(struct intel_crtc *crtc)
11364 {
11365 struct drm_device *dev = crtc->base.dev;
11366
11367 /*
11368 * The scanline counter increments at the leading edge of hsync.
11369 *
11370 * On most platforms it starts counting from vtotal-1 on the
11371 * first active line. That means the scanline counter value is
11372 * always one less than what we would expect. Ie. just after
11373 * start of vblank, which also occurs at start of hsync (on the
11374 * last active line), the scanline counter will read vblank_start-1.
11375 *
11376 * On gen2 the scanline counter starts counting from 1 instead
11377 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11378 * to keep the value positive), instead of adding one.
11379 *
11380 * On HSW+ the behaviour of the scanline counter depends on the output
11381 * type. For DP ports it behaves like most other platforms, but on HDMI
11382 * there's an extra 1 line difference. So we need to add two instead of
11383 * one to the value.
11384 */
11385 if (IS_GEN2(dev)) {
11386 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11387 int vtotal;
11388
11389 vtotal = mode->crtc_vtotal;
11390 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11391 vtotal /= 2;
11392
11393 crtc->scanline_offset = vtotal - 1;
11394 } else if (HAS_DDI(dev) &&
11395 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11396 crtc->scanline_offset = 2;
11397 } else
11398 crtc->scanline_offset = 1;
11399 }
11400
11401 static struct intel_crtc_state *
11402 intel_modeset_compute_config(struct drm_crtc *crtc,
11403 struct drm_display_mode *mode,
11404 struct drm_framebuffer *fb,
11405 struct drm_atomic_state *state,
11406 unsigned *modeset_pipes,
11407 unsigned *prepare_pipes,
11408 unsigned *disable_pipes)
11409 {
11410 struct drm_device *dev = crtc->dev;
11411 struct intel_crtc_state *pipe_config = NULL;
11412 struct intel_crtc *intel_crtc;
11413 int ret = 0;
11414
11415 ret = drm_atomic_add_affected_connectors(state, crtc);
11416 if (ret)
11417 return ERR_PTR(ret);
11418
11419 intel_modeset_affected_pipes(crtc, modeset_pipes,
11420 prepare_pipes, disable_pipes);
11421
11422 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11423 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11424 if (IS_ERR(pipe_config))
11425 return pipe_config;
11426
11427 pipe_config->base.enable = false;
11428 }
11429
11430 /*
11431 * Note this needs changes when we start tracking multiple modes
11432 * and crtcs. At that point we'll need to compute the whole config
11433 * (i.e. one pipe_config for each crtc) rather than just the one
11434 * for this crtc.
11435 */
11436 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11437 /* FIXME: For now we still expect modeset_pipes has at most
11438 * one bit set. */
11439 if (WARN_ON(&intel_crtc->base != crtc))
11440 continue;
11441
11442 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11443 if (IS_ERR(pipe_config))
11444 return pipe_config;
11445
11446 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11447 "[modeset]");
11448 }
11449
11450 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
11451 }
11452
11453 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11454 unsigned modeset_pipes,
11455 unsigned disable_pipes)
11456 {
11457 struct drm_i915_private *dev_priv = to_i915(dev);
11458 unsigned clear_pipes = modeset_pipes | disable_pipes;
11459 struct intel_crtc *intel_crtc;
11460 int ret = 0;
11461
11462 if (!dev_priv->display.crtc_compute_clock)
11463 return 0;
11464
11465 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11466 if (ret)
11467 goto done;
11468
11469 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11470 struct intel_crtc_state *state = intel_crtc->new_config;
11471 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11472 state);
11473 if (ret) {
11474 intel_shared_dpll_abort_config(dev_priv);
11475 goto done;
11476 }
11477 }
11478
11479 done:
11480 return ret;
11481 }
11482
11483 static int __intel_set_mode(struct drm_crtc *crtc,
11484 struct drm_display_mode *mode,
11485 int x, int y, struct drm_framebuffer *fb,
11486 struct intel_crtc_state *pipe_config,
11487 unsigned modeset_pipes,
11488 unsigned prepare_pipes,
11489 unsigned disable_pipes)
11490 {
11491 struct drm_device *dev = crtc->dev;
11492 struct drm_i915_private *dev_priv = dev->dev_private;
11493 struct drm_display_mode *saved_mode;
11494 struct intel_crtc_state *crtc_state_copy = NULL;
11495 struct intel_crtc *intel_crtc;
11496 int ret = 0;
11497
11498 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11499 if (!saved_mode)
11500 return -ENOMEM;
11501
11502 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11503 if (!crtc_state_copy) {
11504 ret = -ENOMEM;
11505 goto done;
11506 }
11507
11508 *saved_mode = crtc->mode;
11509
11510 if (modeset_pipes)
11511 to_intel_crtc(crtc)->new_config = pipe_config;
11512
11513 /*
11514 * See if the config requires any additional preparation, e.g.
11515 * to adjust global state with pipes off. We need to do this
11516 * here so we can get the modeset_pipe updated config for the new
11517 * mode set on this crtc. For other crtcs we need to use the
11518 * adjusted_mode bits in the crtc directly.
11519 */
11520 if (IS_VALLEYVIEW(dev)) {
11521 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11522
11523 /* may have added more to prepare_pipes than we should */
11524 prepare_pipes &= ~disable_pipes;
11525 }
11526
11527 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11528 if (ret)
11529 goto done;
11530
11531 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11532 intel_crtc_disable(&intel_crtc->base);
11533
11534 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11535 if (intel_crtc->base.state->enable)
11536 dev_priv->display.crtc_disable(&intel_crtc->base);
11537 }
11538
11539 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11540 * to set it here already despite that we pass it down the callchain.
11541 *
11542 * Note we'll need to fix this up when we start tracking multiple
11543 * pipes; here we assume a single modeset_pipe and only track the
11544 * single crtc and mode.
11545 */
11546 if (modeset_pipes) {
11547 crtc->mode = *mode;
11548 /* mode_set/enable/disable functions rely on a correct pipe
11549 * config. */
11550 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11551
11552 /*
11553 * Calculate and store various constants which
11554 * are later needed by vblank and swap-completion
11555 * timestamping. They are derived from true hwmode.
11556 */
11557 drm_calc_timestamping_constants(crtc,
11558 &pipe_config->base.adjusted_mode);
11559 }
11560
11561 /* Only after disabling all output pipelines that will be changed can we
11562 * update the the output configuration. */
11563 intel_modeset_update_state(dev, prepare_pipes);
11564
11565 modeset_update_crtc_power_domains(pipe_config->base.state);
11566
11567 /* Set up the DPLL and any encoders state that needs to adjust or depend
11568 * on the DPLL.
11569 */
11570 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11571 struct drm_plane *primary = intel_crtc->base.primary;
11572 int vdisplay, hdisplay;
11573
11574 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11575 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11576 fb, 0, 0,
11577 hdisplay, vdisplay,
11578 x << 16, y << 16,
11579 hdisplay << 16, vdisplay << 16);
11580 }
11581
11582 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11583 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11584 update_scanline_offset(intel_crtc);
11585
11586 dev_priv->display.crtc_enable(&intel_crtc->base);
11587 }
11588
11589 /* FIXME: add subpixel order */
11590 done:
11591 if (ret && crtc->state->enable)
11592 crtc->mode = *saved_mode;
11593
11594 if (ret == 0 && pipe_config) {
11595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11596
11597 /* The pipe_config will be freed with the atomic state, so
11598 * make a copy. */
11599 memcpy(crtc_state_copy, intel_crtc->config,
11600 sizeof *crtc_state_copy);
11601 intel_crtc->config = crtc_state_copy;
11602 intel_crtc->base.state = &crtc_state_copy->base;
11603
11604 if (modeset_pipes)
11605 intel_crtc->new_config = intel_crtc->config;
11606 } else {
11607 kfree(crtc_state_copy);
11608 }
11609
11610 kfree(saved_mode);
11611 return ret;
11612 }
11613
11614 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11615 struct drm_display_mode *mode,
11616 int x, int y, struct drm_framebuffer *fb,
11617 struct intel_crtc_state *pipe_config,
11618 unsigned modeset_pipes,
11619 unsigned prepare_pipes,
11620 unsigned disable_pipes)
11621 {
11622 int ret;
11623
11624 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11625 prepare_pipes, disable_pipes);
11626
11627 if (ret == 0)
11628 intel_modeset_check_state(crtc->dev);
11629
11630 return ret;
11631 }
11632
11633 static int intel_set_mode(struct drm_crtc *crtc,
11634 struct drm_display_mode *mode,
11635 int x, int y, struct drm_framebuffer *fb,
11636 struct drm_atomic_state *state)
11637 {
11638 struct intel_crtc_state *pipe_config;
11639 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11640 int ret = 0;
11641
11642 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
11643 &modeset_pipes,
11644 &prepare_pipes,
11645 &disable_pipes);
11646
11647 if (IS_ERR(pipe_config)) {
11648 ret = PTR_ERR(pipe_config);
11649 goto out;
11650 }
11651
11652 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11653 modeset_pipes, prepare_pipes,
11654 disable_pipes);
11655 if (ret)
11656 goto out;
11657
11658 out:
11659 return ret;
11660 }
11661
11662 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11663 {
11664 struct drm_device *dev = crtc->dev;
11665 struct drm_atomic_state *state;
11666 struct intel_encoder *encoder;
11667 struct intel_connector *connector;
11668 struct drm_connector_state *connector_state;
11669
11670 state = drm_atomic_state_alloc(dev);
11671 if (!state) {
11672 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11673 crtc->base.id);
11674 return;
11675 }
11676
11677 state->acquire_ctx = dev->mode_config.acquire_ctx;
11678
11679 /* The force restore path in the HW readout code relies on the staged
11680 * config still keeping the user requested config while the actual
11681 * state has been overwritten by the configuration read from HW. We
11682 * need to copy the staged config to the atomic state, otherwise the
11683 * mode set will just reapply the state the HW is already in. */
11684 for_each_intel_encoder(dev, encoder) {
11685 if (&encoder->new_crtc->base != crtc)
11686 continue;
11687
11688 for_each_intel_connector(dev, connector) {
11689 if (connector->new_encoder != encoder)
11690 continue;
11691
11692 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11693 if (IS_ERR(connector_state)) {
11694 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11695 connector->base.base.id,
11696 connector->base.name,
11697 PTR_ERR(connector_state));
11698 continue;
11699 }
11700
11701 connector_state->crtc = crtc;
11702 connector_state->best_encoder = &encoder->base;
11703 }
11704 }
11705
11706 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11707 state);
11708
11709 drm_atomic_state_free(state);
11710 }
11711
11712 #undef for_each_intel_crtc_masked
11713
11714 static void intel_set_config_free(struct intel_set_config *config)
11715 {
11716 if (!config)
11717 return;
11718
11719 kfree(config->save_connector_encoders);
11720 kfree(config->save_encoder_crtcs);
11721 kfree(config->save_crtc_enabled);
11722 kfree(config);
11723 }
11724
11725 static int intel_set_config_save_state(struct drm_device *dev,
11726 struct intel_set_config *config)
11727 {
11728 struct drm_crtc *crtc;
11729 struct drm_encoder *encoder;
11730 struct drm_connector *connector;
11731 int count;
11732
11733 config->save_crtc_enabled =
11734 kcalloc(dev->mode_config.num_crtc,
11735 sizeof(bool), GFP_KERNEL);
11736 if (!config->save_crtc_enabled)
11737 return -ENOMEM;
11738
11739 config->save_encoder_crtcs =
11740 kcalloc(dev->mode_config.num_encoder,
11741 sizeof(struct drm_crtc *), GFP_KERNEL);
11742 if (!config->save_encoder_crtcs)
11743 return -ENOMEM;
11744
11745 config->save_connector_encoders =
11746 kcalloc(dev->mode_config.num_connector,
11747 sizeof(struct drm_encoder *), GFP_KERNEL);
11748 if (!config->save_connector_encoders)
11749 return -ENOMEM;
11750
11751 /* Copy data. Note that driver private data is not affected.
11752 * Should anything bad happen only the expected state is
11753 * restored, not the drivers personal bookkeeping.
11754 */
11755 count = 0;
11756 for_each_crtc(dev, crtc) {
11757 config->save_crtc_enabled[count++] = crtc->state->enable;
11758 }
11759
11760 count = 0;
11761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11762 config->save_encoder_crtcs[count++] = encoder->crtc;
11763 }
11764
11765 count = 0;
11766 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11767 config->save_connector_encoders[count++] = connector->encoder;
11768 }
11769
11770 return 0;
11771 }
11772
11773 static void intel_set_config_restore_state(struct drm_device *dev,
11774 struct intel_set_config *config)
11775 {
11776 struct intel_crtc *crtc;
11777 struct intel_encoder *encoder;
11778 struct intel_connector *connector;
11779 int count;
11780
11781 count = 0;
11782 for_each_intel_crtc(dev, crtc) {
11783 crtc->new_enabled = config->save_crtc_enabled[count++];
11784
11785 if (crtc->new_enabled)
11786 crtc->new_config = crtc->config;
11787 else
11788 crtc->new_config = NULL;
11789 }
11790
11791 count = 0;
11792 for_each_intel_encoder(dev, encoder) {
11793 encoder->new_crtc =
11794 to_intel_crtc(config->save_encoder_crtcs[count++]);
11795 }
11796
11797 count = 0;
11798 for_each_intel_connector(dev, connector) {
11799 connector->new_encoder =
11800 to_intel_encoder(config->save_connector_encoders[count++]);
11801 }
11802 }
11803
11804 static bool
11805 is_crtc_connector_off(struct drm_mode_set *set)
11806 {
11807 int i;
11808
11809 if (set->num_connectors == 0)
11810 return false;
11811
11812 if (WARN_ON(set->connectors == NULL))
11813 return false;
11814
11815 for (i = 0; i < set->num_connectors; i++)
11816 if (set->connectors[i]->encoder &&
11817 set->connectors[i]->encoder->crtc == set->crtc &&
11818 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11819 return true;
11820
11821 return false;
11822 }
11823
11824 static void
11825 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11826 struct intel_set_config *config)
11827 {
11828
11829 /* We should be able to check here if the fb has the same properties
11830 * and then just flip_or_move it */
11831 if (is_crtc_connector_off(set)) {
11832 config->mode_changed = true;
11833 } else if (set->crtc->primary->fb != set->fb) {
11834 /*
11835 * If we have no fb, we can only flip as long as the crtc is
11836 * active, otherwise we need a full mode set. The crtc may
11837 * be active if we've only disabled the primary plane, or
11838 * in fastboot situations.
11839 */
11840 if (set->crtc->primary->fb == NULL) {
11841 struct intel_crtc *intel_crtc =
11842 to_intel_crtc(set->crtc);
11843
11844 if (intel_crtc->active) {
11845 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11846 config->fb_changed = true;
11847 } else {
11848 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11849 config->mode_changed = true;
11850 }
11851 } else if (set->fb == NULL) {
11852 config->mode_changed = true;
11853 } else if (set->fb->pixel_format !=
11854 set->crtc->primary->fb->pixel_format) {
11855 config->mode_changed = true;
11856 } else {
11857 config->fb_changed = true;
11858 }
11859 }
11860
11861 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11862 config->fb_changed = true;
11863
11864 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11865 DRM_DEBUG_KMS("modes are different, full mode set\n");
11866 drm_mode_debug_printmodeline(&set->crtc->mode);
11867 drm_mode_debug_printmodeline(set->mode);
11868 config->mode_changed = true;
11869 }
11870
11871 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11872 set->crtc->base.id, config->mode_changed, config->fb_changed);
11873 }
11874
11875 static int
11876 intel_modeset_stage_output_state(struct drm_device *dev,
11877 struct drm_mode_set *set,
11878 struct intel_set_config *config,
11879 struct drm_atomic_state *state)
11880 {
11881 struct intel_connector *connector;
11882 struct drm_connector_state *connector_state;
11883 struct intel_encoder *encoder;
11884 struct intel_crtc *crtc;
11885 int ro;
11886
11887 /* The upper layers ensure that we either disable a crtc or have a list
11888 * of connectors. For paranoia, double-check this. */
11889 WARN_ON(!set->fb && (set->num_connectors != 0));
11890 WARN_ON(set->fb && (set->num_connectors == 0));
11891
11892 for_each_intel_connector(dev, connector) {
11893 /* Otherwise traverse passed in connector list and get encoders
11894 * for them. */
11895 for (ro = 0; ro < set->num_connectors; ro++) {
11896 if (set->connectors[ro] == &connector->base) {
11897 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11898 break;
11899 }
11900 }
11901
11902 /* If we disable the crtc, disable all its connectors. Also, if
11903 * the connector is on the changing crtc but not on the new
11904 * connector list, disable it. */
11905 if ((!set->fb || ro == set->num_connectors) &&
11906 connector->base.encoder &&
11907 connector->base.encoder->crtc == set->crtc) {
11908 connector->new_encoder = NULL;
11909
11910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11911 connector->base.base.id,
11912 connector->base.name);
11913 }
11914
11915
11916 if (&connector->new_encoder->base != connector->base.encoder) {
11917 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11918 connector->base.base.id,
11919 connector->base.name);
11920 config->mode_changed = true;
11921 }
11922 }
11923 /* connector->new_encoder is now updated for all connectors. */
11924
11925 /* Update crtc of enabled connectors. */
11926 for_each_intel_connector(dev, connector) {
11927 struct drm_crtc *new_crtc;
11928
11929 if (!connector->new_encoder)
11930 continue;
11931
11932 new_crtc = connector->new_encoder->base.crtc;
11933
11934 for (ro = 0; ro < set->num_connectors; ro++) {
11935 if (set->connectors[ro] == &connector->base)
11936 new_crtc = set->crtc;
11937 }
11938
11939 /* Make sure the new CRTC will work with the encoder */
11940 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11941 new_crtc)) {
11942 return -EINVAL;
11943 }
11944 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11945
11946 connector_state =
11947 drm_atomic_get_connector_state(state, &connector->base);
11948 if (IS_ERR(connector_state))
11949 return PTR_ERR(connector_state);
11950
11951 connector_state->crtc = new_crtc;
11952 connector_state->best_encoder = &connector->new_encoder->base;
11953
11954 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11955 connector->base.base.id,
11956 connector->base.name,
11957 new_crtc->base.id);
11958 }
11959
11960 /* Check for any encoders that needs to be disabled. */
11961 for_each_intel_encoder(dev, encoder) {
11962 int num_connectors = 0;
11963 for_each_intel_connector(dev, connector) {
11964 if (connector->new_encoder == encoder) {
11965 WARN_ON(!connector->new_encoder->new_crtc);
11966 num_connectors++;
11967 }
11968 }
11969
11970 if (num_connectors == 0)
11971 encoder->new_crtc = NULL;
11972 else if (num_connectors > 1)
11973 return -EINVAL;
11974
11975 /* Only now check for crtc changes so we don't miss encoders
11976 * that will be disabled. */
11977 if (&encoder->new_crtc->base != encoder->base.crtc) {
11978 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11979 encoder->base.base.id,
11980 encoder->base.name);
11981 config->mode_changed = true;
11982 }
11983 }
11984 /* Now we've also updated encoder->new_crtc for all encoders. */
11985 for_each_intel_connector(dev, connector) {
11986 connector_state =
11987 drm_atomic_get_connector_state(state, &connector->base);
11988 if (IS_ERR(connector_state))
11989 return PTR_ERR(connector_state);
11990
11991 if (connector->new_encoder) {
11992 if (connector->new_encoder != connector->encoder)
11993 connector->encoder = connector->new_encoder;
11994 } else {
11995 connector_state->crtc = NULL;
11996 }
11997 }
11998 for_each_intel_crtc(dev, crtc) {
11999 crtc->new_enabled = false;
12000
12001 for_each_intel_encoder(dev, encoder) {
12002 if (encoder->new_crtc == crtc) {
12003 crtc->new_enabled = true;
12004 break;
12005 }
12006 }
12007
12008 if (crtc->new_enabled != crtc->base.state->enable) {
12009 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12010 crtc->base.base.id,
12011 crtc->new_enabled ? "en" : "dis");
12012 config->mode_changed = true;
12013 }
12014
12015 if (crtc->new_enabled)
12016 crtc->new_config = crtc->config;
12017 else
12018 crtc->new_config = NULL;
12019 }
12020
12021 return 0;
12022 }
12023
12024 static void disable_crtc_nofb(struct intel_crtc *crtc)
12025 {
12026 struct drm_device *dev = crtc->base.dev;
12027 struct intel_encoder *encoder;
12028 struct intel_connector *connector;
12029
12030 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12031 pipe_name(crtc->pipe));
12032
12033 for_each_intel_connector(dev, connector) {
12034 if (connector->new_encoder &&
12035 connector->new_encoder->new_crtc == crtc)
12036 connector->new_encoder = NULL;
12037 }
12038
12039 for_each_intel_encoder(dev, encoder) {
12040 if (encoder->new_crtc == crtc)
12041 encoder->new_crtc = NULL;
12042 }
12043
12044 crtc->new_enabled = false;
12045 crtc->new_config = NULL;
12046 }
12047
12048 static int intel_crtc_set_config(struct drm_mode_set *set)
12049 {
12050 struct drm_device *dev;
12051 struct drm_mode_set save_set;
12052 struct drm_atomic_state *state = NULL;
12053 struct intel_set_config *config;
12054 struct intel_crtc_state *pipe_config;
12055 unsigned modeset_pipes, prepare_pipes, disable_pipes;
12056 int ret;
12057
12058 BUG_ON(!set);
12059 BUG_ON(!set->crtc);
12060 BUG_ON(!set->crtc->helper_private);
12061
12062 /* Enforce sane interface api - has been abused by the fb helper. */
12063 BUG_ON(!set->mode && set->fb);
12064 BUG_ON(set->fb && set->num_connectors == 0);
12065
12066 if (set->fb) {
12067 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12068 set->crtc->base.id, set->fb->base.id,
12069 (int)set->num_connectors, set->x, set->y);
12070 } else {
12071 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12072 }
12073
12074 dev = set->crtc->dev;
12075
12076 ret = -ENOMEM;
12077 config = kzalloc(sizeof(*config), GFP_KERNEL);
12078 if (!config)
12079 goto out_config;
12080
12081 ret = intel_set_config_save_state(dev, config);
12082 if (ret)
12083 goto out_config;
12084
12085 save_set.crtc = set->crtc;
12086 save_set.mode = &set->crtc->mode;
12087 save_set.x = set->crtc->x;
12088 save_set.y = set->crtc->y;
12089 save_set.fb = set->crtc->primary->fb;
12090
12091 /* Compute whether we need a full modeset, only an fb base update or no
12092 * change at all. In the future we might also check whether only the
12093 * mode changed, e.g. for LVDS where we only change the panel fitter in
12094 * such cases. */
12095 intel_set_config_compute_mode_changes(set, config);
12096
12097 state = drm_atomic_state_alloc(dev);
12098 if (!state) {
12099 ret = -ENOMEM;
12100 goto out_config;
12101 }
12102
12103 state->acquire_ctx = dev->mode_config.acquire_ctx;
12104
12105 ret = intel_modeset_stage_output_state(dev, set, config, state);
12106 if (ret)
12107 goto fail;
12108
12109 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
12110 set->fb, state,
12111 &modeset_pipes,
12112 &prepare_pipes,
12113 &disable_pipes);
12114 if (IS_ERR(pipe_config)) {
12115 ret = PTR_ERR(pipe_config);
12116 goto fail;
12117 } else if (pipe_config) {
12118 if (pipe_config->has_audio !=
12119 to_intel_crtc(set->crtc)->config->has_audio)
12120 config->mode_changed = true;
12121
12122 /*
12123 * Note we have an issue here with infoframes: current code
12124 * only updates them on the full mode set path per hw
12125 * requirements. So here we should be checking for any
12126 * required changes and forcing a mode set.
12127 */
12128 }
12129
12130 intel_update_pipe_size(to_intel_crtc(set->crtc));
12131
12132 if (config->mode_changed) {
12133 ret = intel_set_mode_pipes(set->crtc, set->mode,
12134 set->x, set->y, set->fb, pipe_config,
12135 modeset_pipes, prepare_pipes,
12136 disable_pipes);
12137 } else if (config->fb_changed) {
12138 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12139 struct drm_plane *primary = set->crtc->primary;
12140 int vdisplay, hdisplay;
12141
12142 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12143 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12144 0, 0, hdisplay, vdisplay,
12145 set->x << 16, set->y << 16,
12146 hdisplay << 16, vdisplay << 16);
12147
12148 /*
12149 * We need to make sure the primary plane is re-enabled if it
12150 * has previously been turned off.
12151 */
12152 if (!intel_crtc->primary_enabled && ret == 0) {
12153 WARN_ON(!intel_crtc->active);
12154 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
12155 }
12156
12157 /*
12158 * In the fastboot case this may be our only check of the
12159 * state after boot. It would be better to only do it on
12160 * the first update, but we don't have a nice way of doing that
12161 * (and really, set_config isn't used much for high freq page
12162 * flipping, so increasing its cost here shouldn't be a big
12163 * deal).
12164 */
12165 if (i915.fastboot && ret == 0)
12166 intel_modeset_check_state(set->crtc->dev);
12167 }
12168
12169 if (ret) {
12170 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12171 set->crtc->base.id, ret);
12172 fail:
12173 intel_set_config_restore_state(dev, config);
12174
12175 drm_atomic_state_clear(state);
12176
12177 /*
12178 * HACK: if the pipe was on, but we didn't have a framebuffer,
12179 * force the pipe off to avoid oopsing in the modeset code
12180 * due to fb==NULL. This should only happen during boot since
12181 * we don't yet reconstruct the FB from the hardware state.
12182 */
12183 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12184 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12185
12186 /* Try to restore the config */
12187 if (config->mode_changed &&
12188 intel_set_mode(save_set.crtc, save_set.mode,
12189 save_set.x, save_set.y, save_set.fb,
12190 state))
12191 DRM_ERROR("failed to restore config after modeset failure\n");
12192 }
12193
12194 out_config:
12195 if (state)
12196 drm_atomic_state_free(state);
12197
12198 intel_set_config_free(config);
12199 return ret;
12200 }
12201
12202 static const struct drm_crtc_funcs intel_crtc_funcs = {
12203 .gamma_set = intel_crtc_gamma_set,
12204 .set_config = intel_crtc_set_config,
12205 .destroy = intel_crtc_destroy,
12206 .page_flip = intel_crtc_page_flip,
12207 .atomic_duplicate_state = intel_crtc_duplicate_state,
12208 .atomic_destroy_state = intel_crtc_destroy_state,
12209 };
12210
12211 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12212 struct intel_shared_dpll *pll,
12213 struct intel_dpll_hw_state *hw_state)
12214 {
12215 uint32_t val;
12216
12217 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12218 return false;
12219
12220 val = I915_READ(PCH_DPLL(pll->id));
12221 hw_state->dpll = val;
12222 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12223 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12224
12225 return val & DPLL_VCO_ENABLE;
12226 }
12227
12228 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12229 struct intel_shared_dpll *pll)
12230 {
12231 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12232 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12233 }
12234
12235 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12236 struct intel_shared_dpll *pll)
12237 {
12238 /* PCH refclock must be enabled first */
12239 ibx_assert_pch_refclk_enabled(dev_priv);
12240
12241 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12242
12243 /* Wait for the clocks to stabilize. */
12244 POSTING_READ(PCH_DPLL(pll->id));
12245 udelay(150);
12246
12247 /* The pixel multiplier can only be updated once the
12248 * DPLL is enabled and the clocks are stable.
12249 *
12250 * So write it again.
12251 */
12252 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12253 POSTING_READ(PCH_DPLL(pll->id));
12254 udelay(200);
12255 }
12256
12257 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12258 struct intel_shared_dpll *pll)
12259 {
12260 struct drm_device *dev = dev_priv->dev;
12261 struct intel_crtc *crtc;
12262
12263 /* Make sure no transcoder isn't still depending on us. */
12264 for_each_intel_crtc(dev, crtc) {
12265 if (intel_crtc_to_shared_dpll(crtc) == pll)
12266 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12267 }
12268
12269 I915_WRITE(PCH_DPLL(pll->id), 0);
12270 POSTING_READ(PCH_DPLL(pll->id));
12271 udelay(200);
12272 }
12273
12274 static char *ibx_pch_dpll_names[] = {
12275 "PCH DPLL A",
12276 "PCH DPLL B",
12277 };
12278
12279 static void ibx_pch_dpll_init(struct drm_device *dev)
12280 {
12281 struct drm_i915_private *dev_priv = dev->dev_private;
12282 int i;
12283
12284 dev_priv->num_shared_dpll = 2;
12285
12286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12287 dev_priv->shared_dplls[i].id = i;
12288 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12289 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12290 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12291 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12292 dev_priv->shared_dplls[i].get_hw_state =
12293 ibx_pch_dpll_get_hw_state;
12294 }
12295 }
12296
12297 static void intel_shared_dpll_init(struct drm_device *dev)
12298 {
12299 struct drm_i915_private *dev_priv = dev->dev_private;
12300
12301 if (HAS_DDI(dev))
12302 intel_ddi_pll_init(dev);
12303 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12304 ibx_pch_dpll_init(dev);
12305 else
12306 dev_priv->num_shared_dpll = 0;
12307
12308 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12309 }
12310
12311 /**
12312 * intel_wm_need_update - Check whether watermarks need updating
12313 * @plane: drm plane
12314 * @state: new plane state
12315 *
12316 * Check current plane state versus the new one to determine whether
12317 * watermarks need to be recalculated.
12318 *
12319 * Returns true or false.
12320 */
12321 bool intel_wm_need_update(struct drm_plane *plane,
12322 struct drm_plane_state *state)
12323 {
12324 /* Update watermarks on tiling changes. */
12325 if (!plane->state->fb || !state->fb ||
12326 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12327 plane->state->rotation != state->rotation)
12328 return true;
12329
12330 return false;
12331 }
12332
12333 /**
12334 * intel_prepare_plane_fb - Prepare fb for usage on plane
12335 * @plane: drm plane to prepare for
12336 * @fb: framebuffer to prepare for presentation
12337 *
12338 * Prepares a framebuffer for usage on a display plane. Generally this
12339 * involves pinning the underlying object and updating the frontbuffer tracking
12340 * bits. Some older platforms need special physical address handling for
12341 * cursor planes.
12342 *
12343 * Returns 0 on success, negative error code on failure.
12344 */
12345 int
12346 intel_prepare_plane_fb(struct drm_plane *plane,
12347 struct drm_framebuffer *fb,
12348 const struct drm_plane_state *new_state)
12349 {
12350 struct drm_device *dev = plane->dev;
12351 struct intel_plane *intel_plane = to_intel_plane(plane);
12352 enum pipe pipe = intel_plane->pipe;
12353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12354 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12355 unsigned frontbuffer_bits = 0;
12356 int ret = 0;
12357
12358 if (!obj)
12359 return 0;
12360
12361 switch (plane->type) {
12362 case DRM_PLANE_TYPE_PRIMARY:
12363 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12364 break;
12365 case DRM_PLANE_TYPE_CURSOR:
12366 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12367 break;
12368 case DRM_PLANE_TYPE_OVERLAY:
12369 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12370 break;
12371 }
12372
12373 mutex_lock(&dev->struct_mutex);
12374
12375 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12376 INTEL_INFO(dev)->cursor_needs_physical) {
12377 int align = IS_I830(dev) ? 16 * 1024 : 256;
12378 ret = i915_gem_object_attach_phys(obj, align);
12379 if (ret)
12380 DRM_DEBUG_KMS("failed to attach phys object\n");
12381 } else {
12382 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12383 }
12384
12385 if (ret == 0)
12386 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12387
12388 mutex_unlock(&dev->struct_mutex);
12389
12390 return ret;
12391 }
12392
12393 /**
12394 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12395 * @plane: drm plane to clean up for
12396 * @fb: old framebuffer that was on plane
12397 *
12398 * Cleans up a framebuffer that has just been removed from a plane.
12399 */
12400 void
12401 intel_cleanup_plane_fb(struct drm_plane *plane,
12402 struct drm_framebuffer *fb,
12403 const struct drm_plane_state *old_state)
12404 {
12405 struct drm_device *dev = plane->dev;
12406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12407
12408 if (WARN_ON(!obj))
12409 return;
12410
12411 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12412 !INTEL_INFO(dev)->cursor_needs_physical) {
12413 mutex_lock(&dev->struct_mutex);
12414 intel_unpin_fb_obj(fb, old_state);
12415 mutex_unlock(&dev->struct_mutex);
12416 }
12417 }
12418
12419 static int
12420 intel_check_primary_plane(struct drm_plane *plane,
12421 struct intel_plane_state *state)
12422 {
12423 struct drm_device *dev = plane->dev;
12424 struct drm_i915_private *dev_priv = dev->dev_private;
12425 struct drm_crtc *crtc = state->base.crtc;
12426 struct intel_crtc *intel_crtc;
12427 struct drm_framebuffer *fb = state->base.fb;
12428 struct drm_rect *dest = &state->dst;
12429 struct drm_rect *src = &state->src;
12430 const struct drm_rect *clip = &state->clip;
12431 int ret;
12432
12433 crtc = crtc ? crtc : plane->crtc;
12434 intel_crtc = to_intel_crtc(crtc);
12435
12436 ret = drm_plane_helper_check_update(plane, crtc, fb,
12437 src, dest, clip,
12438 DRM_PLANE_HELPER_NO_SCALING,
12439 DRM_PLANE_HELPER_NO_SCALING,
12440 false, true, &state->visible);
12441 if (ret)
12442 return ret;
12443
12444 if (intel_crtc->active) {
12445 intel_crtc->atomic.wait_for_flips = true;
12446
12447 /*
12448 * FBC does not work on some platforms for rotated
12449 * planes, so disable it when rotation is not 0 and
12450 * update it when rotation is set back to 0.
12451 *
12452 * FIXME: This is redundant with the fbc update done in
12453 * the primary plane enable function except that that
12454 * one is done too late. We eventually need to unify
12455 * this.
12456 */
12457 if (intel_crtc->primary_enabled &&
12458 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12459 dev_priv->fbc.crtc == intel_crtc &&
12460 state->base.rotation != BIT(DRM_ROTATE_0)) {
12461 intel_crtc->atomic.disable_fbc = true;
12462 }
12463
12464 if (state->visible) {
12465 /*
12466 * BDW signals flip done immediately if the plane
12467 * is disabled, even if the plane enable is already
12468 * armed to occur at the next vblank :(
12469 */
12470 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12471 intel_crtc->atomic.wait_vblank = true;
12472 }
12473
12474 intel_crtc->atomic.fb_bits |=
12475 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12476
12477 intel_crtc->atomic.update_fbc = true;
12478
12479 if (intel_wm_need_update(plane, &state->base))
12480 intel_crtc->atomic.update_wm = true;
12481 }
12482
12483 return 0;
12484 }
12485
12486 static void
12487 intel_commit_primary_plane(struct drm_plane *plane,
12488 struct intel_plane_state *state)
12489 {
12490 struct drm_crtc *crtc = state->base.crtc;
12491 struct drm_framebuffer *fb = state->base.fb;
12492 struct drm_device *dev = plane->dev;
12493 struct drm_i915_private *dev_priv = dev->dev_private;
12494 struct intel_crtc *intel_crtc;
12495 struct drm_rect *src = &state->src;
12496
12497 crtc = crtc ? crtc : plane->crtc;
12498 intel_crtc = to_intel_crtc(crtc);
12499
12500 plane->fb = fb;
12501 crtc->x = src->x1 >> 16;
12502 crtc->y = src->y1 >> 16;
12503
12504 if (intel_crtc->active) {
12505 if (state->visible) {
12506 /* FIXME: kill this fastboot hack */
12507 intel_update_pipe_size(intel_crtc);
12508
12509 intel_crtc->primary_enabled = true;
12510
12511 dev_priv->display.update_primary_plane(crtc, plane->fb,
12512 crtc->x, crtc->y);
12513 } else {
12514 /*
12515 * If clipping results in a non-visible primary plane,
12516 * we'll disable the primary plane. Note that this is
12517 * a bit different than what happens if userspace
12518 * explicitly disables the plane by passing fb=0
12519 * because plane->fb still gets set and pinned.
12520 */
12521 intel_disable_primary_hw_plane(plane, crtc);
12522 }
12523 }
12524 }
12525
12526 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12527 {
12528 struct drm_device *dev = crtc->dev;
12529 struct drm_i915_private *dev_priv = dev->dev_private;
12530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12531 struct intel_plane *intel_plane;
12532 struct drm_plane *p;
12533 unsigned fb_bits = 0;
12534
12535 /* Track fb's for any planes being disabled */
12536 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12537 intel_plane = to_intel_plane(p);
12538
12539 if (intel_crtc->atomic.disabled_planes &
12540 (1 << drm_plane_index(p))) {
12541 switch (p->type) {
12542 case DRM_PLANE_TYPE_PRIMARY:
12543 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12544 break;
12545 case DRM_PLANE_TYPE_CURSOR:
12546 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12547 break;
12548 case DRM_PLANE_TYPE_OVERLAY:
12549 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12550 break;
12551 }
12552
12553 mutex_lock(&dev->struct_mutex);
12554 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12555 mutex_unlock(&dev->struct_mutex);
12556 }
12557 }
12558
12559 if (intel_crtc->atomic.wait_for_flips)
12560 intel_crtc_wait_for_pending_flips(crtc);
12561
12562 if (intel_crtc->atomic.disable_fbc)
12563 intel_fbc_disable(dev);
12564
12565 if (intel_crtc->atomic.pre_disable_primary)
12566 intel_pre_disable_primary(crtc);
12567
12568 if (intel_crtc->atomic.update_wm)
12569 intel_update_watermarks(crtc);
12570
12571 intel_runtime_pm_get(dev_priv);
12572
12573 /* Perform vblank evasion around commit operation */
12574 if (intel_crtc->active)
12575 intel_crtc->atomic.evade =
12576 intel_pipe_update_start(intel_crtc,
12577 &intel_crtc->atomic.start_vbl_count);
12578 }
12579
12580 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12581 {
12582 struct drm_device *dev = crtc->dev;
12583 struct drm_i915_private *dev_priv = dev->dev_private;
12584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12585 struct drm_plane *p;
12586
12587 if (intel_crtc->atomic.evade)
12588 intel_pipe_update_end(intel_crtc,
12589 intel_crtc->atomic.start_vbl_count);
12590
12591 intel_runtime_pm_put(dev_priv);
12592
12593 if (intel_crtc->atomic.wait_vblank)
12594 intel_wait_for_vblank(dev, intel_crtc->pipe);
12595
12596 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12597
12598 if (intel_crtc->atomic.update_fbc) {
12599 mutex_lock(&dev->struct_mutex);
12600 intel_fbc_update(dev);
12601 mutex_unlock(&dev->struct_mutex);
12602 }
12603
12604 if (intel_crtc->atomic.post_enable_primary)
12605 intel_post_enable_primary(crtc);
12606
12607 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12608 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12609 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12610 false, false);
12611
12612 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12613 }
12614
12615 /**
12616 * intel_plane_destroy - destroy a plane
12617 * @plane: plane to destroy
12618 *
12619 * Common destruction function for all types of planes (primary, cursor,
12620 * sprite).
12621 */
12622 void intel_plane_destroy(struct drm_plane *plane)
12623 {
12624 struct intel_plane *intel_plane = to_intel_plane(plane);
12625 drm_plane_cleanup(plane);
12626 kfree(intel_plane);
12627 }
12628
12629 const struct drm_plane_funcs intel_plane_funcs = {
12630 .update_plane = drm_plane_helper_update,
12631 .disable_plane = drm_plane_helper_disable,
12632 .destroy = intel_plane_destroy,
12633 .set_property = drm_atomic_helper_plane_set_property,
12634 .atomic_get_property = intel_plane_atomic_get_property,
12635 .atomic_set_property = intel_plane_atomic_set_property,
12636 .atomic_duplicate_state = intel_plane_duplicate_state,
12637 .atomic_destroy_state = intel_plane_destroy_state,
12638
12639 };
12640
12641 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12642 int pipe)
12643 {
12644 struct intel_plane *primary;
12645 struct intel_plane_state *state;
12646 const uint32_t *intel_primary_formats;
12647 int num_formats;
12648
12649 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12650 if (primary == NULL)
12651 return NULL;
12652
12653 state = intel_create_plane_state(&primary->base);
12654 if (!state) {
12655 kfree(primary);
12656 return NULL;
12657 }
12658 primary->base.state = &state->base;
12659
12660 primary->can_scale = false;
12661 primary->max_downscale = 1;
12662 primary->pipe = pipe;
12663 primary->plane = pipe;
12664 primary->check_plane = intel_check_primary_plane;
12665 primary->commit_plane = intel_commit_primary_plane;
12666 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12667 primary->plane = !pipe;
12668
12669 if (INTEL_INFO(dev)->gen <= 3) {
12670 intel_primary_formats = intel_primary_formats_gen2;
12671 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12672 } else {
12673 intel_primary_formats = intel_primary_formats_gen4;
12674 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12675 }
12676
12677 drm_universal_plane_init(dev, &primary->base, 0,
12678 &intel_plane_funcs,
12679 intel_primary_formats, num_formats,
12680 DRM_PLANE_TYPE_PRIMARY);
12681
12682 if (INTEL_INFO(dev)->gen >= 4) {
12683 if (!dev->mode_config.rotation_property)
12684 dev->mode_config.rotation_property =
12685 drm_mode_create_rotation_property(dev,
12686 BIT(DRM_ROTATE_0) |
12687 BIT(DRM_ROTATE_180));
12688 if (dev->mode_config.rotation_property)
12689 drm_object_attach_property(&primary->base.base,
12690 dev->mode_config.rotation_property,
12691 state->base.rotation);
12692 }
12693
12694 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12695
12696 return &primary->base;
12697 }
12698
12699 static int
12700 intel_check_cursor_plane(struct drm_plane *plane,
12701 struct intel_plane_state *state)
12702 {
12703 struct drm_crtc *crtc = state->base.crtc;
12704 struct drm_device *dev = plane->dev;
12705 struct drm_framebuffer *fb = state->base.fb;
12706 struct drm_rect *dest = &state->dst;
12707 struct drm_rect *src = &state->src;
12708 const struct drm_rect *clip = &state->clip;
12709 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12710 struct intel_crtc *intel_crtc;
12711 unsigned stride;
12712 int ret;
12713
12714 crtc = crtc ? crtc : plane->crtc;
12715 intel_crtc = to_intel_crtc(crtc);
12716
12717 ret = drm_plane_helper_check_update(plane, crtc, fb,
12718 src, dest, clip,
12719 DRM_PLANE_HELPER_NO_SCALING,
12720 DRM_PLANE_HELPER_NO_SCALING,
12721 true, true, &state->visible);
12722 if (ret)
12723 return ret;
12724
12725
12726 /* if we want to turn off the cursor ignore width and height */
12727 if (!obj)
12728 goto finish;
12729
12730 /* Check for which cursor types we support */
12731 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12732 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12733 state->base.crtc_w, state->base.crtc_h);
12734 return -EINVAL;
12735 }
12736
12737 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12738 if (obj->base.size < stride * state->base.crtc_h) {
12739 DRM_DEBUG_KMS("buffer is too small\n");
12740 return -ENOMEM;
12741 }
12742
12743 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12744 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12745 ret = -EINVAL;
12746 }
12747
12748 finish:
12749 if (intel_crtc->active) {
12750 if (plane->state->crtc_w != state->base.crtc_w)
12751 intel_crtc->atomic.update_wm = true;
12752
12753 intel_crtc->atomic.fb_bits |=
12754 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12755 }
12756
12757 return ret;
12758 }
12759
12760 static void
12761 intel_commit_cursor_plane(struct drm_plane *plane,
12762 struct intel_plane_state *state)
12763 {
12764 struct drm_crtc *crtc = state->base.crtc;
12765 struct drm_device *dev = plane->dev;
12766 struct intel_crtc *intel_crtc;
12767 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12768 uint32_t addr;
12769
12770 crtc = crtc ? crtc : plane->crtc;
12771 intel_crtc = to_intel_crtc(crtc);
12772
12773 plane->fb = state->base.fb;
12774 crtc->cursor_x = state->base.crtc_x;
12775 crtc->cursor_y = state->base.crtc_y;
12776
12777 if (intel_crtc->cursor_bo == obj)
12778 goto update;
12779
12780 if (!obj)
12781 addr = 0;
12782 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12783 addr = i915_gem_obj_ggtt_offset(obj);
12784 else
12785 addr = obj->phys_handle->busaddr;
12786
12787 intel_crtc->cursor_addr = addr;
12788 intel_crtc->cursor_bo = obj;
12789 update:
12790
12791 if (intel_crtc->active)
12792 intel_crtc_update_cursor(crtc, state->visible);
12793 }
12794
12795 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12796 int pipe)
12797 {
12798 struct intel_plane *cursor;
12799 struct intel_plane_state *state;
12800
12801 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12802 if (cursor == NULL)
12803 return NULL;
12804
12805 state = intel_create_plane_state(&cursor->base);
12806 if (!state) {
12807 kfree(cursor);
12808 return NULL;
12809 }
12810 cursor->base.state = &state->base;
12811
12812 cursor->can_scale = false;
12813 cursor->max_downscale = 1;
12814 cursor->pipe = pipe;
12815 cursor->plane = pipe;
12816 cursor->check_plane = intel_check_cursor_plane;
12817 cursor->commit_plane = intel_commit_cursor_plane;
12818
12819 drm_universal_plane_init(dev, &cursor->base, 0,
12820 &intel_plane_funcs,
12821 intel_cursor_formats,
12822 ARRAY_SIZE(intel_cursor_formats),
12823 DRM_PLANE_TYPE_CURSOR);
12824
12825 if (INTEL_INFO(dev)->gen >= 4) {
12826 if (!dev->mode_config.rotation_property)
12827 dev->mode_config.rotation_property =
12828 drm_mode_create_rotation_property(dev,
12829 BIT(DRM_ROTATE_0) |
12830 BIT(DRM_ROTATE_180));
12831 if (dev->mode_config.rotation_property)
12832 drm_object_attach_property(&cursor->base.base,
12833 dev->mode_config.rotation_property,
12834 state->base.rotation);
12835 }
12836
12837 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12838
12839 return &cursor->base;
12840 }
12841
12842 static void intel_crtc_init(struct drm_device *dev, int pipe)
12843 {
12844 struct drm_i915_private *dev_priv = dev->dev_private;
12845 struct intel_crtc *intel_crtc;
12846 struct intel_crtc_state *crtc_state = NULL;
12847 struct drm_plane *primary = NULL;
12848 struct drm_plane *cursor = NULL;
12849 int i, ret;
12850
12851 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12852 if (intel_crtc == NULL)
12853 return;
12854
12855 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12856 if (!crtc_state)
12857 goto fail;
12858 intel_crtc_set_state(intel_crtc, crtc_state);
12859 crtc_state->base.crtc = &intel_crtc->base;
12860
12861 primary = intel_primary_plane_create(dev, pipe);
12862 if (!primary)
12863 goto fail;
12864
12865 cursor = intel_cursor_plane_create(dev, pipe);
12866 if (!cursor)
12867 goto fail;
12868
12869 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12870 cursor, &intel_crtc_funcs);
12871 if (ret)
12872 goto fail;
12873
12874 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12875 for (i = 0; i < 256; i++) {
12876 intel_crtc->lut_r[i] = i;
12877 intel_crtc->lut_g[i] = i;
12878 intel_crtc->lut_b[i] = i;
12879 }
12880
12881 /*
12882 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12883 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12884 */
12885 intel_crtc->pipe = pipe;
12886 intel_crtc->plane = pipe;
12887 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12888 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12889 intel_crtc->plane = !pipe;
12890 }
12891
12892 intel_crtc->cursor_base = ~0;
12893 intel_crtc->cursor_cntl = ~0;
12894 intel_crtc->cursor_size = ~0;
12895
12896 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12897 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12898 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12899 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12900
12901 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12902
12903 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12904
12905 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12906 return;
12907
12908 fail:
12909 if (primary)
12910 drm_plane_cleanup(primary);
12911 if (cursor)
12912 drm_plane_cleanup(cursor);
12913 kfree(crtc_state);
12914 kfree(intel_crtc);
12915 }
12916
12917 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12918 {
12919 struct drm_encoder *encoder = connector->base.encoder;
12920 struct drm_device *dev = connector->base.dev;
12921
12922 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12923
12924 if (!encoder || WARN_ON(!encoder->crtc))
12925 return INVALID_PIPE;
12926
12927 return to_intel_crtc(encoder->crtc)->pipe;
12928 }
12929
12930 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12931 struct drm_file *file)
12932 {
12933 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12934 struct drm_crtc *drmmode_crtc;
12935 struct intel_crtc *crtc;
12936
12937 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12938
12939 if (!drmmode_crtc) {
12940 DRM_ERROR("no such CRTC id\n");
12941 return -ENOENT;
12942 }
12943
12944 crtc = to_intel_crtc(drmmode_crtc);
12945 pipe_from_crtc_id->pipe = crtc->pipe;
12946
12947 return 0;
12948 }
12949
12950 static int intel_encoder_clones(struct intel_encoder *encoder)
12951 {
12952 struct drm_device *dev = encoder->base.dev;
12953 struct intel_encoder *source_encoder;
12954 int index_mask = 0;
12955 int entry = 0;
12956
12957 for_each_intel_encoder(dev, source_encoder) {
12958 if (encoders_cloneable(encoder, source_encoder))
12959 index_mask |= (1 << entry);
12960
12961 entry++;
12962 }
12963
12964 return index_mask;
12965 }
12966
12967 static bool has_edp_a(struct drm_device *dev)
12968 {
12969 struct drm_i915_private *dev_priv = dev->dev_private;
12970
12971 if (!IS_MOBILE(dev))
12972 return false;
12973
12974 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12975 return false;
12976
12977 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12978 return false;
12979
12980 return true;
12981 }
12982
12983 static bool intel_crt_present(struct drm_device *dev)
12984 {
12985 struct drm_i915_private *dev_priv = dev->dev_private;
12986
12987 if (INTEL_INFO(dev)->gen >= 9)
12988 return false;
12989
12990 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12991 return false;
12992
12993 if (IS_CHERRYVIEW(dev))
12994 return false;
12995
12996 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12997 return false;
12998
12999 return true;
13000 }
13001
13002 static void intel_setup_outputs(struct drm_device *dev)
13003 {
13004 struct drm_i915_private *dev_priv = dev->dev_private;
13005 struct intel_encoder *encoder;
13006 struct drm_connector *connector;
13007 bool dpd_is_edp = false;
13008
13009 intel_lvds_init(dev);
13010
13011 if (intel_crt_present(dev))
13012 intel_crt_init(dev);
13013
13014 if (HAS_DDI(dev)) {
13015 int found;
13016
13017 /*
13018 * Haswell uses DDI functions to detect digital outputs.
13019 * On SKL pre-D0 the strap isn't connected, so we assume
13020 * it's there.
13021 */
13022 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13023 /* WaIgnoreDDIAStrap: skl */
13024 if (found ||
13025 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13026 intel_ddi_init(dev, PORT_A);
13027
13028 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13029 * register */
13030 found = I915_READ(SFUSE_STRAP);
13031
13032 if (found & SFUSE_STRAP_DDIB_DETECTED)
13033 intel_ddi_init(dev, PORT_B);
13034 if (found & SFUSE_STRAP_DDIC_DETECTED)
13035 intel_ddi_init(dev, PORT_C);
13036 if (found & SFUSE_STRAP_DDID_DETECTED)
13037 intel_ddi_init(dev, PORT_D);
13038 } else if (HAS_PCH_SPLIT(dev)) {
13039 int found;
13040 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13041
13042 if (has_edp_a(dev))
13043 intel_dp_init(dev, DP_A, PORT_A);
13044
13045 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13046 /* PCH SDVOB multiplex with HDMIB */
13047 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13048 if (!found)
13049 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13050 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13051 intel_dp_init(dev, PCH_DP_B, PORT_B);
13052 }
13053
13054 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13055 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13056
13057 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13058 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13059
13060 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13061 intel_dp_init(dev, PCH_DP_C, PORT_C);
13062
13063 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13064 intel_dp_init(dev, PCH_DP_D, PORT_D);
13065 } else if (IS_VALLEYVIEW(dev)) {
13066 /*
13067 * The DP_DETECTED bit is the latched state of the DDC
13068 * SDA pin at boot. However since eDP doesn't require DDC
13069 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13070 * eDP ports may have been muxed to an alternate function.
13071 * Thus we can't rely on the DP_DETECTED bit alone to detect
13072 * eDP ports. Consult the VBT as well as DP_DETECTED to
13073 * detect eDP ports.
13074 */
13075 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13076 !intel_dp_is_edp(dev, PORT_B))
13077 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13078 PORT_B);
13079 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13080 intel_dp_is_edp(dev, PORT_B))
13081 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13082
13083 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13084 !intel_dp_is_edp(dev, PORT_C))
13085 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13086 PORT_C);
13087 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13088 intel_dp_is_edp(dev, PORT_C))
13089 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13090
13091 if (IS_CHERRYVIEW(dev)) {
13092 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13093 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13094 PORT_D);
13095 /* eDP not supported on port D, so don't check VBT */
13096 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13097 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13098 }
13099
13100 intel_dsi_init(dev);
13101 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13102 bool found = false;
13103
13104 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13105 DRM_DEBUG_KMS("probing SDVOB\n");
13106 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13107 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13108 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13109 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13110 }
13111
13112 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13113 intel_dp_init(dev, DP_B, PORT_B);
13114 }
13115
13116 /* Before G4X SDVOC doesn't have its own detect register */
13117
13118 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13119 DRM_DEBUG_KMS("probing SDVOC\n");
13120 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13121 }
13122
13123 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13124
13125 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13126 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13127 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13128 }
13129 if (SUPPORTS_INTEGRATED_DP(dev))
13130 intel_dp_init(dev, DP_C, PORT_C);
13131 }
13132
13133 if (SUPPORTS_INTEGRATED_DP(dev) &&
13134 (I915_READ(DP_D) & DP_DETECTED))
13135 intel_dp_init(dev, DP_D, PORT_D);
13136 } else if (IS_GEN2(dev))
13137 intel_dvo_init(dev);
13138
13139 if (SUPPORTS_TV(dev))
13140 intel_tv_init(dev);
13141
13142 /*
13143 * FIXME: We don't have full atomic support yet, but we want to be
13144 * able to enable/test plane updates via the atomic interface in the
13145 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13146 * will take some atomic codepaths to lookup properties during
13147 * drmModeGetConnector() that unconditionally dereference
13148 * connector->state.
13149 *
13150 * We create a dummy connector state here for each connector to ensure
13151 * the DRM core doesn't try to dereference a NULL connector->state.
13152 * The actual connector properties will never be updated or contain
13153 * useful information, but since we're doing this specifically for
13154 * testing/debug of the plane operations (and only when a specific
13155 * kernel module option is given), that shouldn't really matter.
13156 *
13157 * We are also relying on these states to convert the legacy mode set
13158 * to use a drm_atomic_state struct. The states are kept consistent
13159 * with actual state, so that it is safe to rely on that instead of
13160 * the staged config.
13161 *
13162 * Once atomic support for crtc's + connectors lands, this loop should
13163 * be removed since we'll be setting up real connector state, which
13164 * will contain Intel-specific properties.
13165 */
13166 list_for_each_entry(connector,
13167 &dev->mode_config.connector_list,
13168 head) {
13169 if (!WARN_ON(connector->state)) {
13170 connector->state = kzalloc(sizeof(*connector->state),
13171 GFP_KERNEL);
13172 }
13173 }
13174
13175 intel_psr_init(dev);
13176
13177 for_each_intel_encoder(dev, encoder) {
13178 encoder->base.possible_crtcs = encoder->crtc_mask;
13179 encoder->base.possible_clones =
13180 intel_encoder_clones(encoder);
13181 }
13182
13183 intel_init_pch_refclk(dev);
13184
13185 drm_helper_move_panel_connectors_to_head(dev);
13186 }
13187
13188 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13189 {
13190 struct drm_device *dev = fb->dev;
13191 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13192
13193 drm_framebuffer_cleanup(fb);
13194 mutex_lock(&dev->struct_mutex);
13195 WARN_ON(!intel_fb->obj->framebuffer_references--);
13196 drm_gem_object_unreference(&intel_fb->obj->base);
13197 mutex_unlock(&dev->struct_mutex);
13198 kfree(intel_fb);
13199 }
13200
13201 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13202 struct drm_file *file,
13203 unsigned int *handle)
13204 {
13205 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13206 struct drm_i915_gem_object *obj = intel_fb->obj;
13207
13208 return drm_gem_handle_create(file, &obj->base, handle);
13209 }
13210
13211 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13212 .destroy = intel_user_framebuffer_destroy,
13213 .create_handle = intel_user_framebuffer_create_handle,
13214 };
13215
13216 static
13217 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13218 uint32_t pixel_format)
13219 {
13220 u32 gen = INTEL_INFO(dev)->gen;
13221
13222 if (gen >= 9) {
13223 /* "The stride in bytes must not exceed the of the size of 8K
13224 * pixels and 32K bytes."
13225 */
13226 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13227 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13228 return 32*1024;
13229 } else if (gen >= 4) {
13230 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13231 return 16*1024;
13232 else
13233 return 32*1024;
13234 } else if (gen >= 3) {
13235 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13236 return 8*1024;
13237 else
13238 return 16*1024;
13239 } else {
13240 /* XXX DSPC is limited to 4k tiled */
13241 return 8*1024;
13242 }
13243 }
13244
13245 static int intel_framebuffer_init(struct drm_device *dev,
13246 struct intel_framebuffer *intel_fb,
13247 struct drm_mode_fb_cmd2 *mode_cmd,
13248 struct drm_i915_gem_object *obj)
13249 {
13250 unsigned int aligned_height;
13251 int ret;
13252 u32 pitch_limit, stride_alignment;
13253
13254 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13255
13256 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13257 /* Enforce that fb modifier and tiling mode match, but only for
13258 * X-tiled. This is needed for FBC. */
13259 if (!!(obj->tiling_mode == I915_TILING_X) !=
13260 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13261 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13262 return -EINVAL;
13263 }
13264 } else {
13265 if (obj->tiling_mode == I915_TILING_X)
13266 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13267 else if (obj->tiling_mode == I915_TILING_Y) {
13268 DRM_DEBUG("No Y tiling for legacy addfb\n");
13269 return -EINVAL;
13270 }
13271 }
13272
13273 /* Passed in modifier sanity checking. */
13274 switch (mode_cmd->modifier[0]) {
13275 case I915_FORMAT_MOD_Y_TILED:
13276 case I915_FORMAT_MOD_Yf_TILED:
13277 if (INTEL_INFO(dev)->gen < 9) {
13278 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13279 mode_cmd->modifier[0]);
13280 return -EINVAL;
13281 }
13282 case DRM_FORMAT_MOD_NONE:
13283 case I915_FORMAT_MOD_X_TILED:
13284 break;
13285 default:
13286 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13287 mode_cmd->modifier[0]);
13288 return -EINVAL;
13289 }
13290
13291 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13292 mode_cmd->pixel_format);
13293 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13294 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13295 mode_cmd->pitches[0], stride_alignment);
13296 return -EINVAL;
13297 }
13298
13299 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13300 mode_cmd->pixel_format);
13301 if (mode_cmd->pitches[0] > pitch_limit) {
13302 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13303 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13304 "tiled" : "linear",
13305 mode_cmd->pitches[0], pitch_limit);
13306 return -EINVAL;
13307 }
13308
13309 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13310 mode_cmd->pitches[0] != obj->stride) {
13311 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13312 mode_cmd->pitches[0], obj->stride);
13313 return -EINVAL;
13314 }
13315
13316 /* Reject formats not supported by any plane early. */
13317 switch (mode_cmd->pixel_format) {
13318 case DRM_FORMAT_C8:
13319 case DRM_FORMAT_RGB565:
13320 case DRM_FORMAT_XRGB8888:
13321 case DRM_FORMAT_ARGB8888:
13322 break;
13323 case DRM_FORMAT_XRGB1555:
13324 case DRM_FORMAT_ARGB1555:
13325 if (INTEL_INFO(dev)->gen > 3) {
13326 DRM_DEBUG("unsupported pixel format: %s\n",
13327 drm_get_format_name(mode_cmd->pixel_format));
13328 return -EINVAL;
13329 }
13330 break;
13331 case DRM_FORMAT_XBGR8888:
13332 case DRM_FORMAT_ABGR8888:
13333 case DRM_FORMAT_XRGB2101010:
13334 case DRM_FORMAT_ARGB2101010:
13335 case DRM_FORMAT_XBGR2101010:
13336 case DRM_FORMAT_ABGR2101010:
13337 if (INTEL_INFO(dev)->gen < 4) {
13338 DRM_DEBUG("unsupported pixel format: %s\n",
13339 drm_get_format_name(mode_cmd->pixel_format));
13340 return -EINVAL;
13341 }
13342 break;
13343 case DRM_FORMAT_YUYV:
13344 case DRM_FORMAT_UYVY:
13345 case DRM_FORMAT_YVYU:
13346 case DRM_FORMAT_VYUY:
13347 if (INTEL_INFO(dev)->gen < 5) {
13348 DRM_DEBUG("unsupported pixel format: %s\n",
13349 drm_get_format_name(mode_cmd->pixel_format));
13350 return -EINVAL;
13351 }
13352 break;
13353 default:
13354 DRM_DEBUG("unsupported pixel format: %s\n",
13355 drm_get_format_name(mode_cmd->pixel_format));
13356 return -EINVAL;
13357 }
13358
13359 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13360 if (mode_cmd->offsets[0] != 0)
13361 return -EINVAL;
13362
13363 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13364 mode_cmd->pixel_format,
13365 mode_cmd->modifier[0]);
13366 /* FIXME drm helper for size checks (especially planar formats)? */
13367 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13368 return -EINVAL;
13369
13370 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13371 intel_fb->obj = obj;
13372 intel_fb->obj->framebuffer_references++;
13373
13374 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13375 if (ret) {
13376 DRM_ERROR("framebuffer init failed %d\n", ret);
13377 return ret;
13378 }
13379
13380 return 0;
13381 }
13382
13383 static struct drm_framebuffer *
13384 intel_user_framebuffer_create(struct drm_device *dev,
13385 struct drm_file *filp,
13386 struct drm_mode_fb_cmd2 *mode_cmd)
13387 {
13388 struct drm_i915_gem_object *obj;
13389
13390 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13391 mode_cmd->handles[0]));
13392 if (&obj->base == NULL)
13393 return ERR_PTR(-ENOENT);
13394
13395 return intel_framebuffer_create(dev, mode_cmd, obj);
13396 }
13397
13398 #ifndef CONFIG_DRM_I915_FBDEV
13399 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13400 {
13401 }
13402 #endif
13403
13404 static const struct drm_mode_config_funcs intel_mode_funcs = {
13405 .fb_create = intel_user_framebuffer_create,
13406 .output_poll_changed = intel_fbdev_output_poll_changed,
13407 .atomic_check = intel_atomic_check,
13408 .atomic_commit = intel_atomic_commit,
13409 };
13410
13411 /* Set up chip specific display functions */
13412 static void intel_init_display(struct drm_device *dev)
13413 {
13414 struct drm_i915_private *dev_priv = dev->dev_private;
13415
13416 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13417 dev_priv->display.find_dpll = g4x_find_best_dpll;
13418 else if (IS_CHERRYVIEW(dev))
13419 dev_priv->display.find_dpll = chv_find_best_dpll;
13420 else if (IS_VALLEYVIEW(dev))
13421 dev_priv->display.find_dpll = vlv_find_best_dpll;
13422 else if (IS_PINEVIEW(dev))
13423 dev_priv->display.find_dpll = pnv_find_best_dpll;
13424 else
13425 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13426
13427 if (INTEL_INFO(dev)->gen >= 9) {
13428 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13429 dev_priv->display.get_initial_plane_config =
13430 skylake_get_initial_plane_config;
13431 dev_priv->display.crtc_compute_clock =
13432 haswell_crtc_compute_clock;
13433 dev_priv->display.crtc_enable = haswell_crtc_enable;
13434 dev_priv->display.crtc_disable = haswell_crtc_disable;
13435 dev_priv->display.off = ironlake_crtc_off;
13436 dev_priv->display.update_primary_plane =
13437 skylake_update_primary_plane;
13438 } else if (HAS_DDI(dev)) {
13439 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13440 dev_priv->display.get_initial_plane_config =
13441 ironlake_get_initial_plane_config;
13442 dev_priv->display.crtc_compute_clock =
13443 haswell_crtc_compute_clock;
13444 dev_priv->display.crtc_enable = haswell_crtc_enable;
13445 dev_priv->display.crtc_disable = haswell_crtc_disable;
13446 dev_priv->display.off = ironlake_crtc_off;
13447 dev_priv->display.update_primary_plane =
13448 ironlake_update_primary_plane;
13449 } else if (HAS_PCH_SPLIT(dev)) {
13450 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13451 dev_priv->display.get_initial_plane_config =
13452 ironlake_get_initial_plane_config;
13453 dev_priv->display.crtc_compute_clock =
13454 ironlake_crtc_compute_clock;
13455 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13456 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13457 dev_priv->display.off = ironlake_crtc_off;
13458 dev_priv->display.update_primary_plane =
13459 ironlake_update_primary_plane;
13460 } else if (IS_VALLEYVIEW(dev)) {
13461 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13462 dev_priv->display.get_initial_plane_config =
13463 i9xx_get_initial_plane_config;
13464 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13465 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13466 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13467 dev_priv->display.off = i9xx_crtc_off;
13468 dev_priv->display.update_primary_plane =
13469 i9xx_update_primary_plane;
13470 } else {
13471 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13472 dev_priv->display.get_initial_plane_config =
13473 i9xx_get_initial_plane_config;
13474 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13475 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13476 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13477 dev_priv->display.off = i9xx_crtc_off;
13478 dev_priv->display.update_primary_plane =
13479 i9xx_update_primary_plane;
13480 }
13481
13482 /* Returns the core display clock speed */
13483 if (IS_VALLEYVIEW(dev))
13484 dev_priv->display.get_display_clock_speed =
13485 valleyview_get_display_clock_speed;
13486 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13487 dev_priv->display.get_display_clock_speed =
13488 i945_get_display_clock_speed;
13489 else if (IS_I915G(dev))
13490 dev_priv->display.get_display_clock_speed =
13491 i915_get_display_clock_speed;
13492 else if (IS_I945GM(dev) || IS_845G(dev))
13493 dev_priv->display.get_display_clock_speed =
13494 i9xx_misc_get_display_clock_speed;
13495 else if (IS_PINEVIEW(dev))
13496 dev_priv->display.get_display_clock_speed =
13497 pnv_get_display_clock_speed;
13498 else if (IS_I915GM(dev))
13499 dev_priv->display.get_display_clock_speed =
13500 i915gm_get_display_clock_speed;
13501 else if (IS_I865G(dev))
13502 dev_priv->display.get_display_clock_speed =
13503 i865_get_display_clock_speed;
13504 else if (IS_I85X(dev))
13505 dev_priv->display.get_display_clock_speed =
13506 i855_get_display_clock_speed;
13507 else /* 852, 830 */
13508 dev_priv->display.get_display_clock_speed =
13509 i830_get_display_clock_speed;
13510
13511 if (IS_GEN5(dev)) {
13512 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13513 } else if (IS_GEN6(dev)) {
13514 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13515 } else if (IS_IVYBRIDGE(dev)) {
13516 /* FIXME: detect B0+ stepping and use auto training */
13517 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13518 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13519 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13520 } else if (IS_VALLEYVIEW(dev)) {
13521 dev_priv->display.modeset_global_resources =
13522 valleyview_modeset_global_resources;
13523 }
13524
13525 switch (INTEL_INFO(dev)->gen) {
13526 case 2:
13527 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13528 break;
13529
13530 case 3:
13531 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13532 break;
13533
13534 case 4:
13535 case 5:
13536 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13537 break;
13538
13539 case 6:
13540 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13541 break;
13542 case 7:
13543 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13544 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13545 break;
13546 case 9:
13547 /* Drop through - unsupported since execlist only. */
13548 default:
13549 /* Default just returns -ENODEV to indicate unsupported */
13550 dev_priv->display.queue_flip = intel_default_queue_flip;
13551 }
13552
13553 intel_panel_init_backlight_funcs(dev);
13554
13555 mutex_init(&dev_priv->pps_mutex);
13556 }
13557
13558 /*
13559 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13560 * resume, or other times. This quirk makes sure that's the case for
13561 * affected systems.
13562 */
13563 static void quirk_pipea_force(struct drm_device *dev)
13564 {
13565 struct drm_i915_private *dev_priv = dev->dev_private;
13566
13567 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13568 DRM_INFO("applying pipe a force quirk\n");
13569 }
13570
13571 static void quirk_pipeb_force(struct drm_device *dev)
13572 {
13573 struct drm_i915_private *dev_priv = dev->dev_private;
13574
13575 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13576 DRM_INFO("applying pipe b force quirk\n");
13577 }
13578
13579 /*
13580 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13581 */
13582 static void quirk_ssc_force_disable(struct drm_device *dev)
13583 {
13584 struct drm_i915_private *dev_priv = dev->dev_private;
13585 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13586 DRM_INFO("applying lvds SSC disable quirk\n");
13587 }
13588
13589 /*
13590 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13591 * brightness value
13592 */
13593 static void quirk_invert_brightness(struct drm_device *dev)
13594 {
13595 struct drm_i915_private *dev_priv = dev->dev_private;
13596 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13597 DRM_INFO("applying inverted panel brightness quirk\n");
13598 }
13599
13600 /* Some VBT's incorrectly indicate no backlight is present */
13601 static void quirk_backlight_present(struct drm_device *dev)
13602 {
13603 struct drm_i915_private *dev_priv = dev->dev_private;
13604 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13605 DRM_INFO("applying backlight present quirk\n");
13606 }
13607
13608 struct intel_quirk {
13609 int device;
13610 int subsystem_vendor;
13611 int subsystem_device;
13612 void (*hook)(struct drm_device *dev);
13613 };
13614
13615 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13616 struct intel_dmi_quirk {
13617 void (*hook)(struct drm_device *dev);
13618 const struct dmi_system_id (*dmi_id_list)[];
13619 };
13620
13621 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13622 {
13623 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13624 return 1;
13625 }
13626
13627 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13628 {
13629 .dmi_id_list = &(const struct dmi_system_id[]) {
13630 {
13631 .callback = intel_dmi_reverse_brightness,
13632 .ident = "NCR Corporation",
13633 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13634 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13635 },
13636 },
13637 { } /* terminating entry */
13638 },
13639 .hook = quirk_invert_brightness,
13640 },
13641 };
13642
13643 static struct intel_quirk intel_quirks[] = {
13644 /* HP Mini needs pipe A force quirk (LP: #322104) */
13645 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13646
13647 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13648 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13649
13650 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13651 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13652
13653 /* 830 needs to leave pipe A & dpll A up */
13654 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13655
13656 /* 830 needs to leave pipe B & dpll B up */
13657 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13658
13659 /* Lenovo U160 cannot use SSC on LVDS */
13660 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13661
13662 /* Sony Vaio Y cannot use SSC on LVDS */
13663 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13664
13665 /* Acer Aspire 5734Z must invert backlight brightness */
13666 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13667
13668 /* Acer/eMachines G725 */
13669 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13670
13671 /* Acer/eMachines e725 */
13672 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13673
13674 /* Acer/Packard Bell NCL20 */
13675 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13676
13677 /* Acer Aspire 4736Z */
13678 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13679
13680 /* Acer Aspire 5336 */
13681 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13682
13683 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13684 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13685
13686 /* Acer C720 Chromebook (Core i3 4005U) */
13687 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13688
13689 /* Apple Macbook 2,1 (Core 2 T7400) */
13690 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13691
13692 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13693 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13694
13695 /* HP Chromebook 14 (Celeron 2955U) */
13696 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13697
13698 /* Dell Chromebook 11 */
13699 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13700 };
13701
13702 static void intel_init_quirks(struct drm_device *dev)
13703 {
13704 struct pci_dev *d = dev->pdev;
13705 int i;
13706
13707 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13708 struct intel_quirk *q = &intel_quirks[i];
13709
13710 if (d->device == q->device &&
13711 (d->subsystem_vendor == q->subsystem_vendor ||
13712 q->subsystem_vendor == PCI_ANY_ID) &&
13713 (d->subsystem_device == q->subsystem_device ||
13714 q->subsystem_device == PCI_ANY_ID))
13715 q->hook(dev);
13716 }
13717 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13718 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13719 intel_dmi_quirks[i].hook(dev);
13720 }
13721 }
13722
13723 /* Disable the VGA plane that we never use */
13724 static void i915_disable_vga(struct drm_device *dev)
13725 {
13726 struct drm_i915_private *dev_priv = dev->dev_private;
13727 u8 sr1;
13728 u32 vga_reg = i915_vgacntrl_reg(dev);
13729
13730 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13731 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13732 outb(SR01, VGA_SR_INDEX);
13733 sr1 = inb(VGA_SR_DATA);
13734 outb(sr1 | 1<<5, VGA_SR_DATA);
13735 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13736 udelay(300);
13737
13738 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13739 POSTING_READ(vga_reg);
13740 }
13741
13742 void intel_modeset_init_hw(struct drm_device *dev)
13743 {
13744 intel_prepare_ddi(dev);
13745
13746 if (IS_VALLEYVIEW(dev))
13747 vlv_update_cdclk(dev);
13748
13749 intel_init_clock_gating(dev);
13750
13751 intel_enable_gt_powersave(dev);
13752 }
13753
13754 void intel_modeset_init(struct drm_device *dev)
13755 {
13756 struct drm_i915_private *dev_priv = dev->dev_private;
13757 int sprite, ret;
13758 enum pipe pipe;
13759 struct intel_crtc *crtc;
13760
13761 drm_mode_config_init(dev);
13762
13763 dev->mode_config.min_width = 0;
13764 dev->mode_config.min_height = 0;
13765
13766 dev->mode_config.preferred_depth = 24;
13767 dev->mode_config.prefer_shadow = 1;
13768
13769 dev->mode_config.allow_fb_modifiers = true;
13770
13771 dev->mode_config.funcs = &intel_mode_funcs;
13772
13773 intel_init_quirks(dev);
13774
13775 intel_init_pm(dev);
13776
13777 if (INTEL_INFO(dev)->num_pipes == 0)
13778 return;
13779
13780 intel_init_display(dev);
13781 intel_init_audio(dev);
13782
13783 if (IS_GEN2(dev)) {
13784 dev->mode_config.max_width = 2048;
13785 dev->mode_config.max_height = 2048;
13786 } else if (IS_GEN3(dev)) {
13787 dev->mode_config.max_width = 4096;
13788 dev->mode_config.max_height = 4096;
13789 } else {
13790 dev->mode_config.max_width = 8192;
13791 dev->mode_config.max_height = 8192;
13792 }
13793
13794 if (IS_845G(dev) || IS_I865G(dev)) {
13795 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13796 dev->mode_config.cursor_height = 1023;
13797 } else if (IS_GEN2(dev)) {
13798 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13799 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13800 } else {
13801 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13802 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13803 }
13804
13805 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13806
13807 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13808 INTEL_INFO(dev)->num_pipes,
13809 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13810
13811 for_each_pipe(dev_priv, pipe) {
13812 intel_crtc_init(dev, pipe);
13813 for_each_sprite(dev_priv, pipe, sprite) {
13814 ret = intel_plane_init(dev, pipe, sprite);
13815 if (ret)
13816 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13817 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13818 }
13819 }
13820
13821 intel_init_dpio(dev);
13822
13823 intel_shared_dpll_init(dev);
13824
13825 /* Just disable it once at startup */
13826 i915_disable_vga(dev);
13827 intel_setup_outputs(dev);
13828
13829 /* Just in case the BIOS is doing something questionable. */
13830 intel_fbc_disable(dev);
13831
13832 drm_modeset_lock_all(dev);
13833 intel_modeset_setup_hw_state(dev, false);
13834 drm_modeset_unlock_all(dev);
13835
13836 for_each_intel_crtc(dev, crtc) {
13837 if (!crtc->active)
13838 continue;
13839
13840 /*
13841 * Note that reserving the BIOS fb up front prevents us
13842 * from stuffing other stolen allocations like the ring
13843 * on top. This prevents some ugliness at boot time, and
13844 * can even allow for smooth boot transitions if the BIOS
13845 * fb is large enough for the active pipe configuration.
13846 */
13847 if (dev_priv->display.get_initial_plane_config) {
13848 dev_priv->display.get_initial_plane_config(crtc,
13849 &crtc->plane_config);
13850 /*
13851 * If the fb is shared between multiple heads, we'll
13852 * just get the first one.
13853 */
13854 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
13855 }
13856 }
13857 }
13858
13859 static void intel_enable_pipe_a(struct drm_device *dev)
13860 {
13861 struct intel_connector *connector;
13862 struct drm_connector *crt = NULL;
13863 struct intel_load_detect_pipe load_detect_temp;
13864 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13865
13866 /* We can't just switch on the pipe A, we need to set things up with a
13867 * proper mode and output configuration. As a gross hack, enable pipe A
13868 * by enabling the load detect pipe once. */
13869 for_each_intel_connector(dev, connector) {
13870 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13871 crt = &connector->base;
13872 break;
13873 }
13874 }
13875
13876 if (!crt)
13877 return;
13878
13879 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13880 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
13881 }
13882
13883 static bool
13884 intel_check_plane_mapping(struct intel_crtc *crtc)
13885 {
13886 struct drm_device *dev = crtc->base.dev;
13887 struct drm_i915_private *dev_priv = dev->dev_private;
13888 u32 reg, val;
13889
13890 if (INTEL_INFO(dev)->num_pipes == 1)
13891 return true;
13892
13893 reg = DSPCNTR(!crtc->plane);
13894 val = I915_READ(reg);
13895
13896 if ((val & DISPLAY_PLANE_ENABLE) &&
13897 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13898 return false;
13899
13900 return true;
13901 }
13902
13903 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13904 {
13905 struct drm_device *dev = crtc->base.dev;
13906 struct drm_i915_private *dev_priv = dev->dev_private;
13907 u32 reg;
13908
13909 /* Clear any frame start delays used for debugging left by the BIOS */
13910 reg = PIPECONF(crtc->config->cpu_transcoder);
13911 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13912
13913 /* restore vblank interrupts to correct state */
13914 drm_crtc_vblank_reset(&crtc->base);
13915 if (crtc->active) {
13916 update_scanline_offset(crtc);
13917 drm_crtc_vblank_on(&crtc->base);
13918 }
13919
13920 /* We need to sanitize the plane -> pipe mapping first because this will
13921 * disable the crtc (and hence change the state) if it is wrong. Note
13922 * that gen4+ has a fixed plane -> pipe mapping. */
13923 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13924 struct intel_connector *connector;
13925 bool plane;
13926
13927 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13928 crtc->base.base.id);
13929
13930 /* Pipe has the wrong plane attached and the plane is active.
13931 * Temporarily change the plane mapping and disable everything
13932 * ... */
13933 plane = crtc->plane;
13934 crtc->plane = !plane;
13935 crtc->primary_enabled = true;
13936 dev_priv->display.crtc_disable(&crtc->base);
13937 crtc->plane = plane;
13938
13939 /* ... and break all links. */
13940 for_each_intel_connector(dev, connector) {
13941 if (connector->encoder->base.crtc != &crtc->base)
13942 continue;
13943
13944 connector->base.dpms = DRM_MODE_DPMS_OFF;
13945 connector->base.encoder = NULL;
13946 }
13947 /* multiple connectors may have the same encoder:
13948 * handle them and break crtc link separately */
13949 for_each_intel_connector(dev, connector)
13950 if (connector->encoder->base.crtc == &crtc->base) {
13951 connector->encoder->base.crtc = NULL;
13952 connector->encoder->connectors_active = false;
13953 }
13954
13955 WARN_ON(crtc->active);
13956 crtc->base.state->enable = false;
13957 crtc->base.enabled = false;
13958 }
13959
13960 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13961 crtc->pipe == PIPE_A && !crtc->active) {
13962 /* BIOS forgot to enable pipe A, this mostly happens after
13963 * resume. Force-enable the pipe to fix this, the update_dpms
13964 * call below we restore the pipe to the right state, but leave
13965 * the required bits on. */
13966 intel_enable_pipe_a(dev);
13967 }
13968
13969 /* Adjust the state of the output pipe according to whether we
13970 * have active connectors/encoders. */
13971 intel_crtc_update_dpms(&crtc->base);
13972
13973 if (crtc->active != crtc->base.state->enable) {
13974 struct intel_encoder *encoder;
13975
13976 /* This can happen either due to bugs in the get_hw_state
13977 * functions or because the pipe is force-enabled due to the
13978 * pipe A quirk. */
13979 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13980 crtc->base.base.id,
13981 crtc->base.state->enable ? "enabled" : "disabled",
13982 crtc->active ? "enabled" : "disabled");
13983
13984 crtc->base.state->enable = crtc->active;
13985 crtc->base.enabled = crtc->active;
13986
13987 /* Because we only establish the connector -> encoder ->
13988 * crtc links if something is active, this means the
13989 * crtc is now deactivated. Break the links. connector
13990 * -> encoder links are only establish when things are
13991 * actually up, hence no need to break them. */
13992 WARN_ON(crtc->active);
13993
13994 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13995 WARN_ON(encoder->connectors_active);
13996 encoder->base.crtc = NULL;
13997 }
13998 }
13999
14000 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14001 /*
14002 * We start out with underrun reporting disabled to avoid races.
14003 * For correct bookkeeping mark this on active crtcs.
14004 *
14005 * Also on gmch platforms we dont have any hardware bits to
14006 * disable the underrun reporting. Which means we need to start
14007 * out with underrun reporting disabled also on inactive pipes,
14008 * since otherwise we'll complain about the garbage we read when
14009 * e.g. coming up after runtime pm.
14010 *
14011 * No protection against concurrent access is required - at
14012 * worst a fifo underrun happens which also sets this to false.
14013 */
14014 crtc->cpu_fifo_underrun_disabled = true;
14015 crtc->pch_fifo_underrun_disabled = true;
14016 }
14017 }
14018
14019 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14020 {
14021 struct intel_connector *connector;
14022 struct drm_device *dev = encoder->base.dev;
14023
14024 /* We need to check both for a crtc link (meaning that the
14025 * encoder is active and trying to read from a pipe) and the
14026 * pipe itself being active. */
14027 bool has_active_crtc = encoder->base.crtc &&
14028 to_intel_crtc(encoder->base.crtc)->active;
14029
14030 if (encoder->connectors_active && !has_active_crtc) {
14031 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14032 encoder->base.base.id,
14033 encoder->base.name);
14034
14035 /* Connector is active, but has no active pipe. This is
14036 * fallout from our resume register restoring. Disable
14037 * the encoder manually again. */
14038 if (encoder->base.crtc) {
14039 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14040 encoder->base.base.id,
14041 encoder->base.name);
14042 encoder->disable(encoder);
14043 if (encoder->post_disable)
14044 encoder->post_disable(encoder);
14045 }
14046 encoder->base.crtc = NULL;
14047 encoder->connectors_active = false;
14048
14049 /* Inconsistent output/port/pipe state happens presumably due to
14050 * a bug in one of the get_hw_state functions. Or someplace else
14051 * in our code, like the register restore mess on resume. Clamp
14052 * things to off as a safer default. */
14053 for_each_intel_connector(dev, connector) {
14054 if (connector->encoder != encoder)
14055 continue;
14056 connector->base.dpms = DRM_MODE_DPMS_OFF;
14057 connector->base.encoder = NULL;
14058 }
14059 }
14060 /* Enabled encoders without active connectors will be fixed in
14061 * the crtc fixup. */
14062 }
14063
14064 void i915_redisable_vga_power_on(struct drm_device *dev)
14065 {
14066 struct drm_i915_private *dev_priv = dev->dev_private;
14067 u32 vga_reg = i915_vgacntrl_reg(dev);
14068
14069 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14070 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14071 i915_disable_vga(dev);
14072 }
14073 }
14074
14075 void i915_redisable_vga(struct drm_device *dev)
14076 {
14077 struct drm_i915_private *dev_priv = dev->dev_private;
14078
14079 /* This function can be called both from intel_modeset_setup_hw_state or
14080 * at a very early point in our resume sequence, where the power well
14081 * structures are not yet restored. Since this function is at a very
14082 * paranoid "someone might have enabled VGA while we were not looking"
14083 * level, just check if the power well is enabled instead of trying to
14084 * follow the "don't touch the power well if we don't need it" policy
14085 * the rest of the driver uses. */
14086 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14087 return;
14088
14089 i915_redisable_vga_power_on(dev);
14090 }
14091
14092 static bool primary_get_hw_state(struct intel_crtc *crtc)
14093 {
14094 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14095
14096 if (!crtc->active)
14097 return false;
14098
14099 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14100 }
14101
14102 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14103 {
14104 struct drm_i915_private *dev_priv = dev->dev_private;
14105 enum pipe pipe;
14106 struct intel_crtc *crtc;
14107 struct intel_encoder *encoder;
14108 struct intel_connector *connector;
14109 int i;
14110
14111 for_each_intel_crtc(dev, crtc) {
14112 memset(crtc->config, 0, sizeof(*crtc->config));
14113
14114 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14115
14116 crtc->active = dev_priv->display.get_pipe_config(crtc,
14117 crtc->config);
14118
14119 crtc->base.state->enable = crtc->active;
14120 crtc->base.enabled = crtc->active;
14121 crtc->primary_enabled = primary_get_hw_state(crtc);
14122
14123 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14124 crtc->base.base.id,
14125 crtc->active ? "enabled" : "disabled");
14126 }
14127
14128 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14129 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14130
14131 pll->on = pll->get_hw_state(dev_priv, pll,
14132 &pll->config.hw_state);
14133 pll->active = 0;
14134 pll->config.crtc_mask = 0;
14135 for_each_intel_crtc(dev, crtc) {
14136 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14137 pll->active++;
14138 pll->config.crtc_mask |= 1 << crtc->pipe;
14139 }
14140 }
14141
14142 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14143 pll->name, pll->config.crtc_mask, pll->on);
14144
14145 if (pll->config.crtc_mask)
14146 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14147 }
14148
14149 for_each_intel_encoder(dev, encoder) {
14150 pipe = 0;
14151
14152 if (encoder->get_hw_state(encoder, &pipe)) {
14153 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14154 encoder->base.crtc = &crtc->base;
14155 encoder->get_config(encoder, crtc->config);
14156 } else {
14157 encoder->base.crtc = NULL;
14158 }
14159
14160 encoder->connectors_active = false;
14161 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14162 encoder->base.base.id,
14163 encoder->base.name,
14164 encoder->base.crtc ? "enabled" : "disabled",
14165 pipe_name(pipe));
14166 }
14167
14168 for_each_intel_connector(dev, connector) {
14169 if (connector->get_hw_state(connector)) {
14170 connector->base.dpms = DRM_MODE_DPMS_ON;
14171 connector->encoder->connectors_active = true;
14172 connector->base.encoder = &connector->encoder->base;
14173 } else {
14174 connector->base.dpms = DRM_MODE_DPMS_OFF;
14175 connector->base.encoder = NULL;
14176 }
14177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14178 connector->base.base.id,
14179 connector->base.name,
14180 connector->base.encoder ? "enabled" : "disabled");
14181 }
14182 }
14183
14184 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14185 * and i915 state tracking structures. */
14186 void intel_modeset_setup_hw_state(struct drm_device *dev,
14187 bool force_restore)
14188 {
14189 struct drm_i915_private *dev_priv = dev->dev_private;
14190 enum pipe pipe;
14191 struct intel_crtc *crtc;
14192 struct intel_encoder *encoder;
14193 int i;
14194
14195 intel_modeset_readout_hw_state(dev);
14196
14197 /*
14198 * Now that we have the config, copy it to each CRTC struct
14199 * Note that this could go away if we move to using crtc_config
14200 * checking everywhere.
14201 */
14202 for_each_intel_crtc(dev, crtc) {
14203 if (crtc->active && i915.fastboot) {
14204 intel_mode_from_pipe_config(&crtc->base.mode,
14205 crtc->config);
14206 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14207 crtc->base.base.id);
14208 drm_mode_debug_printmodeline(&crtc->base.mode);
14209 }
14210 }
14211
14212 /* HW state is read out, now we need to sanitize this mess. */
14213 for_each_intel_encoder(dev, encoder) {
14214 intel_sanitize_encoder(encoder);
14215 }
14216
14217 for_each_pipe(dev_priv, pipe) {
14218 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14219 intel_sanitize_crtc(crtc);
14220 intel_dump_pipe_config(crtc, crtc->config,
14221 "[setup_hw_state]");
14222 }
14223
14224 intel_modeset_update_connector_atomic_state(dev);
14225
14226 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14227 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14228
14229 if (!pll->on || pll->active)
14230 continue;
14231
14232 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14233
14234 pll->disable(dev_priv, pll);
14235 pll->on = false;
14236 }
14237
14238 if (IS_GEN9(dev))
14239 skl_wm_get_hw_state(dev);
14240 else if (HAS_PCH_SPLIT(dev))
14241 ilk_wm_get_hw_state(dev);
14242
14243 if (force_restore) {
14244 i915_redisable_vga(dev);
14245
14246 /*
14247 * We need to use raw interfaces for restoring state to avoid
14248 * checking (bogus) intermediate states.
14249 */
14250 for_each_pipe(dev_priv, pipe) {
14251 struct drm_crtc *crtc =
14252 dev_priv->pipe_to_crtc_mapping[pipe];
14253
14254 intel_crtc_restore_mode(crtc);
14255 }
14256 } else {
14257 intel_modeset_update_staged_output_state(dev);
14258 }
14259
14260 intel_modeset_check_state(dev);
14261 }
14262
14263 void intel_modeset_gem_init(struct drm_device *dev)
14264 {
14265 struct drm_i915_private *dev_priv = dev->dev_private;
14266 struct drm_crtc *c;
14267 struct drm_i915_gem_object *obj;
14268
14269 mutex_lock(&dev->struct_mutex);
14270 intel_init_gt_powersave(dev);
14271 mutex_unlock(&dev->struct_mutex);
14272
14273 /*
14274 * There may be no VBT; and if the BIOS enabled SSC we can
14275 * just keep using it to avoid unnecessary flicker. Whereas if the
14276 * BIOS isn't using it, don't assume it will work even if the VBT
14277 * indicates as much.
14278 */
14279 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14280 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14281 DREF_SSC1_ENABLE);
14282
14283 intel_modeset_init_hw(dev);
14284
14285 intel_setup_overlay(dev);
14286
14287 /*
14288 * Make sure any fbs we allocated at startup are properly
14289 * pinned & fenced. When we do the allocation it's too early
14290 * for this.
14291 */
14292 mutex_lock(&dev->struct_mutex);
14293 for_each_crtc(dev, c) {
14294 obj = intel_fb_obj(c->primary->fb);
14295 if (obj == NULL)
14296 continue;
14297
14298 if (intel_pin_and_fence_fb_obj(c->primary,
14299 c->primary->fb,
14300 c->primary->state,
14301 NULL)) {
14302 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14303 to_intel_crtc(c)->pipe);
14304 drm_framebuffer_unreference(c->primary->fb);
14305 c->primary->fb = NULL;
14306 update_state_fb(c->primary);
14307 }
14308 }
14309 mutex_unlock(&dev->struct_mutex);
14310
14311 intel_backlight_register(dev);
14312 }
14313
14314 void intel_connector_unregister(struct intel_connector *intel_connector)
14315 {
14316 struct drm_connector *connector = &intel_connector->base;
14317
14318 intel_panel_destroy_backlight(connector);
14319 drm_connector_unregister(connector);
14320 }
14321
14322 void intel_modeset_cleanup(struct drm_device *dev)
14323 {
14324 struct drm_i915_private *dev_priv = dev->dev_private;
14325 struct drm_connector *connector;
14326
14327 intel_disable_gt_powersave(dev);
14328
14329 intel_backlight_unregister(dev);
14330
14331 /*
14332 * Interrupts and polling as the first thing to avoid creating havoc.
14333 * Too much stuff here (turning of connectors, ...) would
14334 * experience fancy races otherwise.
14335 */
14336 intel_irq_uninstall(dev_priv);
14337
14338 /*
14339 * Due to the hpd irq storm handling the hotplug work can re-arm the
14340 * poll handlers. Hence disable polling after hpd handling is shut down.
14341 */
14342 drm_kms_helper_poll_fini(dev);
14343
14344 mutex_lock(&dev->struct_mutex);
14345
14346 intel_unregister_dsm_handler();
14347
14348 intel_fbc_disable(dev);
14349
14350 mutex_unlock(&dev->struct_mutex);
14351
14352 /* flush any delayed tasks or pending work */
14353 flush_scheduled_work();
14354
14355 /* destroy the backlight and sysfs files before encoders/connectors */
14356 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
14357 struct intel_connector *intel_connector;
14358
14359 intel_connector = to_intel_connector(connector);
14360 intel_connector->unregister(intel_connector);
14361 }
14362
14363 drm_mode_config_cleanup(dev);
14364
14365 intel_cleanup_overlay(dev);
14366
14367 mutex_lock(&dev->struct_mutex);
14368 intel_cleanup_gt_powersave(dev);
14369 mutex_unlock(&dev->struct_mutex);
14370 }
14371
14372 /*
14373 * Return which encoder is currently attached for connector.
14374 */
14375 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14376 {
14377 return &intel_attached_encoder(connector)->base;
14378 }
14379
14380 void intel_connector_attach_encoder(struct intel_connector *connector,
14381 struct intel_encoder *encoder)
14382 {
14383 connector->encoder = encoder;
14384 drm_mode_connector_attach_encoder(&connector->base,
14385 &encoder->base);
14386 }
14387
14388 /*
14389 * set vga decode state - true == enable VGA decode
14390 */
14391 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14392 {
14393 struct drm_i915_private *dev_priv = dev->dev_private;
14394 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14395 u16 gmch_ctrl;
14396
14397 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14398 DRM_ERROR("failed to read control word\n");
14399 return -EIO;
14400 }
14401
14402 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14403 return 0;
14404
14405 if (state)
14406 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14407 else
14408 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14409
14410 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14411 DRM_ERROR("failed to write control word\n");
14412 return -EIO;
14413 }
14414
14415 return 0;
14416 }
14417
14418 struct intel_display_error_state {
14419
14420 u32 power_well_driver;
14421
14422 int num_transcoders;
14423
14424 struct intel_cursor_error_state {
14425 u32 control;
14426 u32 position;
14427 u32 base;
14428 u32 size;
14429 } cursor[I915_MAX_PIPES];
14430
14431 struct intel_pipe_error_state {
14432 bool power_domain_on;
14433 u32 source;
14434 u32 stat;
14435 } pipe[I915_MAX_PIPES];
14436
14437 struct intel_plane_error_state {
14438 u32 control;
14439 u32 stride;
14440 u32 size;
14441 u32 pos;
14442 u32 addr;
14443 u32 surface;
14444 u32 tile_offset;
14445 } plane[I915_MAX_PIPES];
14446
14447 struct intel_transcoder_error_state {
14448 bool power_domain_on;
14449 enum transcoder cpu_transcoder;
14450
14451 u32 conf;
14452
14453 u32 htotal;
14454 u32 hblank;
14455 u32 hsync;
14456 u32 vtotal;
14457 u32 vblank;
14458 u32 vsync;
14459 } transcoder[4];
14460 };
14461
14462 struct intel_display_error_state *
14463 intel_display_capture_error_state(struct drm_device *dev)
14464 {
14465 struct drm_i915_private *dev_priv = dev->dev_private;
14466 struct intel_display_error_state *error;
14467 int transcoders[] = {
14468 TRANSCODER_A,
14469 TRANSCODER_B,
14470 TRANSCODER_C,
14471 TRANSCODER_EDP,
14472 };
14473 int i;
14474
14475 if (INTEL_INFO(dev)->num_pipes == 0)
14476 return NULL;
14477
14478 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14479 if (error == NULL)
14480 return NULL;
14481
14482 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14483 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14484
14485 for_each_pipe(dev_priv, i) {
14486 error->pipe[i].power_domain_on =
14487 __intel_display_power_is_enabled(dev_priv,
14488 POWER_DOMAIN_PIPE(i));
14489 if (!error->pipe[i].power_domain_on)
14490 continue;
14491
14492 error->cursor[i].control = I915_READ(CURCNTR(i));
14493 error->cursor[i].position = I915_READ(CURPOS(i));
14494 error->cursor[i].base = I915_READ(CURBASE(i));
14495
14496 error->plane[i].control = I915_READ(DSPCNTR(i));
14497 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14498 if (INTEL_INFO(dev)->gen <= 3) {
14499 error->plane[i].size = I915_READ(DSPSIZE(i));
14500 error->plane[i].pos = I915_READ(DSPPOS(i));
14501 }
14502 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14503 error->plane[i].addr = I915_READ(DSPADDR(i));
14504 if (INTEL_INFO(dev)->gen >= 4) {
14505 error->plane[i].surface = I915_READ(DSPSURF(i));
14506 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14507 }
14508
14509 error->pipe[i].source = I915_READ(PIPESRC(i));
14510
14511 if (HAS_GMCH_DISPLAY(dev))
14512 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14513 }
14514
14515 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14516 if (HAS_DDI(dev_priv->dev))
14517 error->num_transcoders++; /* Account for eDP. */
14518
14519 for (i = 0; i < error->num_transcoders; i++) {
14520 enum transcoder cpu_transcoder = transcoders[i];
14521
14522 error->transcoder[i].power_domain_on =
14523 __intel_display_power_is_enabled(dev_priv,
14524 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14525 if (!error->transcoder[i].power_domain_on)
14526 continue;
14527
14528 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14529
14530 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14531 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14532 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14533 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14534 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14535 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14536 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14537 }
14538
14539 return error;
14540 }
14541
14542 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14543
14544 void
14545 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14546 struct drm_device *dev,
14547 struct intel_display_error_state *error)
14548 {
14549 struct drm_i915_private *dev_priv = dev->dev_private;
14550 int i;
14551
14552 if (!error)
14553 return;
14554
14555 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14556 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14557 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14558 error->power_well_driver);
14559 for_each_pipe(dev_priv, i) {
14560 err_printf(m, "Pipe [%d]:\n", i);
14561 err_printf(m, " Power: %s\n",
14562 error->pipe[i].power_domain_on ? "on" : "off");
14563 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14564 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14565
14566 err_printf(m, "Plane [%d]:\n", i);
14567 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14568 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14569 if (INTEL_INFO(dev)->gen <= 3) {
14570 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14571 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14572 }
14573 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14574 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14575 if (INTEL_INFO(dev)->gen >= 4) {
14576 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14577 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14578 }
14579
14580 err_printf(m, "Cursor [%d]:\n", i);
14581 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14582 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14583 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14584 }
14585
14586 for (i = 0; i < error->num_transcoders; i++) {
14587 err_printf(m, "CPU transcoder: %c\n",
14588 transcoder_name(error->transcoder[i].cpu_transcoder));
14589 err_printf(m, " Power: %s\n",
14590 error->transcoder[i].power_domain_on ? "on" : "off");
14591 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14592 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14593 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14594 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14595 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14596 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14597 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14598 }
14599 }
14600
14601 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14602 {
14603 struct intel_crtc *crtc;
14604
14605 for_each_intel_crtc(dev, crtc) {
14606 struct intel_unpin_work *work;
14607
14608 spin_lock_irq(&dev->event_lock);
14609
14610 work = crtc->unpin_work;
14611
14612 if (work && work->event &&
14613 work->event->base.file_priv == file) {
14614 kfree(work->event);
14615 work->event = NULL;
14616 }
14617
14618 spin_unlock_irq(&dev->event_lock);
14619 }
14620 }
Linux kernel - Deliverables
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