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drm/i915: s/intel_ring_buffer/intel_engine_cs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
54
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
69 static void vlv_prepare_pll(struct intel_crtc *crtc);
70
71 typedef struct {
72 int min, max;
73 } intel_range_t;
74
75 typedef struct {
76 int dot_limit;
77 int p2_slow, p2_fast;
78 } intel_p2_t;
79
80 typedef struct intel_limit intel_limit_t;
81 struct intel_limit {
82 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
84 };
85
86 int
87 intel_pch_rawclk(struct drm_device *dev)
88 {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 }
95
96 static inline u32 /* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device *dev)
98 {
99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
104 }
105
106 static const intel_limit_t intel_limits_i8xx_dac = {
107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 908000, .max = 1512000 },
109 .n = { .min = 2, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
117 };
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 908000, .max = 1512000 },
122 .n = { .min = 2, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130 };
131
132 static const intel_limit_t intel_limits_i8xx_lvds = {
133 .dot = { .min = 25000, .max = 350000 },
134 .vco = { .min = 908000, .max = 1512000 },
135 .n = { .min = 2, .max = 16 },
136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
143 };
144
145 static const intel_limit_t intel_limits_i9xx_sdvo = {
146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 };
170
171
172 static const intel_limit_t intel_limits_g4x_sdvo = {
173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
184 },
185 };
186
187 static const intel_limit_t intel_limits_g4x_hdmi = {
188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
211 },
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_sdvo = {
229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
231 /* Pineview's Ncounter is a ring counter */
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 /* Pineview only has one combined m divider, which we treat as m2. */
235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_pineview_lvds = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
254 };
255
256 /* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
261 static const intel_limit_t intel_limits_ironlake_dac = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
272 };
273
274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
285 };
286
287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
298 };
299
300 /* LVDS 100mhz refclk limits. */
301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
312 };
313
314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
322 .p1 = { .min = 2, .max = 6 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
325 };
326
327 static const intel_limit_t intel_limits_vlv = {
328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
335 .vco = { .min = 4000000, .max = 6000000 },
336 .n = { .min = 1, .max = 7 },
337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
339 .p1 = { .min = 2, .max = 3 },
340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
341 };
342
343 static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357 };
358
359 static void vlv_clock(int refclk, intel_clock_t *clock)
360 {
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
367 }
368
369 /**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373 {
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382 }
383
384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
386 {
387 struct drm_device *dev = crtc->dev;
388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
391 if (intel_is_dual_link_lvds(dev)) {
392 if (refclk == 100000)
393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
397 if (refclk == 100000)
398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
402 } else
403 limit = &intel_limits_ironlake_dac;
404
405 return limit;
406 }
407
408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409 {
410 struct drm_device *dev = crtc->dev;
411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
414 if (intel_is_dual_link_lvds(dev))
415 limit = &intel_limits_g4x_dual_channel_lvds;
416 else
417 limit = &intel_limits_g4x_single_channel_lvds;
418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
420 limit = &intel_limits_g4x_hdmi;
421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
422 limit = &intel_limits_g4x_sdvo;
423 } else /* The option is for other outputs */
424 limit = &intel_limits_i9xx_sdvo;
425
426 return limit;
427 }
428
429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 {
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
434 if (HAS_PCH_SPLIT(dev))
435 limit = intel_ironlake_limit(crtc, refclk);
436 else if (IS_G4X(dev)) {
437 limit = intel_g4x_limit(crtc);
438 } else if (IS_PINEVIEW(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_pineview_lvds;
441 else
442 limit = &intel_limits_pineview_sdvo;
443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
445 } else if (IS_VALLEYVIEW(dev)) {
446 limit = &intel_limits_vlv;
447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
454 limit = &intel_limits_i8xx_lvds;
455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
456 limit = &intel_limits_i8xx_dvo;
457 else
458 limit = &intel_limits_i8xx_dac;
459 }
460 return limit;
461 }
462
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk, intel_clock_t *clock)
465 {
466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
472 }
473
474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475 {
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477 }
478
479 static void i9xx_clock(int refclk, intel_clock_t *clock)
480 {
481 clock->m = i9xx_dpll_compute_m(clock);
482 clock->p = clock->p1 * clock->p2;
483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487 }
488
489 static void chv_clock(int refclk, intel_clock_t *clock)
490 {
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498 }
499
500 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
501 /**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
506 static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
509 {
510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
513 INTELPllInvalid("p1 out of range\n");
514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
515 INTELPllInvalid("m2 out of range\n");
516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
517 INTELPllInvalid("m1 out of range\n");
518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
531 INTELPllInvalid("vco out of range\n");
532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
536 INTELPllInvalid("dot out of range\n");
537
538 return true;
539 }
540
541 static bool
542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
545 {
546 struct drm_device *dev = crtc->dev;
547 intel_clock_t clock;
548 int err = target;
549
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551 /*
552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
555 */
556 if (intel_is_dual_link_lvds(dev))
557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
567 memset(best_clock, 0, sizeof(*best_clock));
568
569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
573 if (clock.m2 >= clock.m1)
574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
579 int this_err;
580
581 i9xx_clock(refclk, &clock);
582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
584 continue;
585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600 }
601
602 static bool
603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->dev;
667 intel_clock_t clock;
668 int max_n;
669 bool found;
670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if (intel_is_dual_link_lvds(dev))
676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
690 /* based on hardware requirement, prefere larger m1,m2 */
691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
699 i9xx_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703
704 this_err = abs(clock.dot - target);
705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
715 return found;
716 }
717
718 static bool
719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->dev;
724 intel_clock_t clock;
725 unsigned int bestppm = 1000000;
726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
728 bool found = false;
729
730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
739 clock.p = clock.p1 * clock.p2;
740 /* based on hardware requirement, prefer bigger m1,m2 values */
741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
742 unsigned int ppm, diff;
743
744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
746
747 vlv_clock(refclk, &clock);
748
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752
753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
757 bestppm = 0;
758 *best_clock = clock;
759 found = true;
760 }
761
762 if (bestppm >= 10 && ppm < bestppm - 10) {
763 bestppm = ppm;
764 *best_clock = clock;
765 found = true;
766 }
767 }
768 }
769 }
770 }
771
772 return found;
773 }
774
775 static bool
776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825 }
826
827 bool intel_crtc_active(struct drm_crtc *crtc)
828 {
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
834 * We can ditch the adjusted_mode.crtc_clock check as soon
835 * as Haswell has gained clock readout/fastboot support.
836 *
837 * We can ditch the crtc->primary->fb check as soon as we can
838 * properly reconstruct framebuffers.
839 */
840 return intel_crtc->active && crtc->primary->fb &&
841 intel_crtc->config.adjusted_mode.crtc_clock;
842 }
843
844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846 {
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
850 return intel_crtc->config.cpu_transcoder;
851 }
852
853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
861 WARN(1, "vblank wait timed out\n");
862 }
863
864 /**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
873 {
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 int pipestat_reg = PIPESTAT(pipe);
876
877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
879 return;
880 }
881
882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
898 /* Wait for vblank interrupt bit to set */
899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
902 DRM_DEBUG_KMS("vblank wait timed out\n");
903 }
904
905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922 }
923
924 /*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
939 *
940 */
941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
942 {
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
946
947 if (INTEL_INFO(dev)->gen >= 4) {
948 int reg = PIPECONF(cpu_transcoder);
949
950 /* Wait for the Pipe State to go off */
951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
953 WARN(1, "pipe_off wait timed out\n");
954 } else {
955 /* Wait for the display line to settle */
956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
957 WARN(1, "pipe_off wait timed out\n");
958 }
959 }
960
961 /*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970 {
971 u32 bit;
972
973 if (HAS_PCH_IBX(dev_priv->dev)) {
974 switch (port->port) {
975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
988 switch (port->port) {
989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
1001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008 return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050 if (crtc->config.shared_dpll < 0)
1051 return NULL;
1052
1053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
1060 {
1061 bool cur_state;
1062 struct intel_dpll_hw_state hw_state;
1063
1064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
1162 bool locked = true;
1163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
1182 pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
1191 if (IS_845G(dev) || IS_I865G(dev))
1192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193 else
1194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
1211
1212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
1216 if (!intel_display_power_enabled(dev_priv,
1217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
1225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
1227 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
1232 {
1233 int reg;
1234 u32 val;
1235 bool cur_state;
1236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250 {
1251 struct drm_device *dev = dev_priv->dev;
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
1256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN(val & DISPLAY_PLANE_ENABLE,
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
1263 return;
1264 }
1265
1266 /* Need to check both planes against the pipe */
1267 for_each_pipe(i) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1275 }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280 {
1281 struct drm_device *dev = dev_priv->dev;
1282 int reg, sprite;
1283 u32 val;
1284
1285 if (IS_VALLEYVIEW(dev)) {
1286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
1288 val = I915_READ(reg);
1289 WARN(val & SP_ENABLE,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 sprite_name(pipe, sprite), pipe_name(pipe));
1292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & SPRITE_ENABLE,
1297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
1302 WARN(val & DVS_ENABLE,
1303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
1305 }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310 u32 val;
1311 bool enabled;
1312
1313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
1323 {
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
1328 reg = PCH_TRANSCONF(pipe);
1329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
1331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
1347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
1350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359 {
1360 if ((val & SDVO_ENABLE) == 0)
1361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
1364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365 return false;
1366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
1369 } else {
1370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371 return false;
1372 }
1373 return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378 {
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg, u32 port_sel)
1409 {
1410 u32 val = I915_READ(reg);
1411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1414
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
1417 "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422 {
1423 u32 val = I915_READ(reg);
1424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426 reg, pipe_name(pipe));
1427
1428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429 && (val & SDVO_PIPE_B_SELECT),
1430 "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435 {
1436 int reg;
1437 u32 val;
1438
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
1445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446 "PCH VGA enabled on transcoder %c, should be disabled\n",
1447 pipe_name(pipe));
1448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
1451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453 pipe_name(pipe));
1454
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
1467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
1487 /*
1488 * Enable the CRI clock source so we can get at the display and the
1489 * reference clock for VGA hotplug / manual detection.
1490 */
1491 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1492 DPLL_REFA_CLK_ENABLE_VLV |
1493 DPLL_INTEGRATED_CRI_CLK_VLV);
1494
1495 if (IS_CHERRYVIEW(dev)) {
1496 enum dpio_phy phy;
1497 u32 val;
1498
1499 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1500 /* Poll for phypwrgood signal */
1501 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1502 PHY_POWERGOOD(phy), 1))
1503 DRM_ERROR("Display PHY %d is not power up\n", phy);
1504
1505 /*
1506 * Deassert common lane reset for PHY.
1507 *
1508 * This should only be done on init and resume from S3
1509 * with both PLLs disabled, or we risk losing DPIO and
1510 * PLL synchronization.
1511 */
1512 val = I915_READ(DISPLAY_PHY_CONTROL);
1513 I915_WRITE(DISPLAY_PHY_CONTROL,
1514 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1515 }
1516
1517 } else {
1518 /*
1519 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1520 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1521 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1522 * b. The other bits such as sfr settings / modesel may all
1523 * be set to 0.
1524 *
1525 * This should only be done on init and resume from S3 with
1526 * both PLLs disabled, or we risk losing DPIO and PLL
1527 * synchronization.
1528 */
1529 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1530 }
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc)
1534 {
1535 struct drm_device *dev = crtc->base.dev;
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537 int reg = DPLL(crtc->pipe);
1538 u32 dpll = crtc->config.dpll_hw_state.dpll;
1539
1540 assert_pipe_disabled(dev_priv, crtc->pipe);
1541
1542 /* No really, not for ILK+ */
1543 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1544
1545 /* PLL is protected by panel, make sure we can write it */
1546 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1547 assert_panel_unlocked(dev_priv, crtc->pipe);
1548
1549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150);
1552
1553 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1554 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1555
1556 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1557 POSTING_READ(DPLL_MD(crtc->pipe));
1558
1559 /* We do this three times for luck */
1560 I915_WRITE(reg, dpll);
1561 POSTING_READ(reg);
1562 udelay(150); /* wait for warmup */
1563 I915_WRITE(reg, dpll);
1564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 }
1570
1571 static void chv_enable_pll(struct intel_crtc *crtc)
1572 {
1573 struct drm_device *dev = crtc->base.dev;
1574 struct drm_i915_private *dev_priv = dev->dev_private;
1575 int pipe = crtc->pipe;
1576 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1577 u32 tmp;
1578
1579 assert_pipe_disabled(dev_priv, crtc->pipe);
1580
1581 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1582
1583 mutex_lock(&dev_priv->dpio_lock);
1584
1585 /* Enable back the 10bit clock to display controller */
1586 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1587 tmp |= DPIO_DCLKP_EN;
1588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1589
1590 /*
1591 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1592 */
1593 udelay(1);
1594
1595 /* Enable PLL */
1596 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1597
1598 /* Check PLL is locked */
1599 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1600 DRM_ERROR("PLL %d failed to lock\n", pipe);
1601
1602 /* not sure when this should be written */
1603 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1604 POSTING_READ(DPLL_MD(pipe));
1605
1606 mutex_unlock(&dev_priv->dpio_lock);
1607 }
1608
1609 static void i9xx_enable_pll(struct intel_crtc *crtc)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = crtc->config.dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626
1627 /* Wait for the clocks to stabilize. */
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (INTEL_INFO(dev)->gen >= 4) {
1632 I915_WRITE(DPLL_MD(crtc->pipe),
1633 crtc->config.dpll_hw_state.dpll_md);
1634 } else {
1635 /* The pixel multiplier can only be updated once the
1636 * DPLL is enabled and the clocks are stable.
1637 *
1638 * So write it again.
1639 */
1640 I915_WRITE(reg, dpll);
1641 }
1642
1643 /* We do this three times for luck */
1644 I915_WRITE(reg, dpll);
1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 }
1654
1655 /**
1656 * i9xx_disable_pll - disable a PLL
1657 * @dev_priv: i915 private structure
1658 * @pipe: pipe PLL to disable
1659 *
1660 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 *
1662 * Note! This is for pre-ILK only.
1663 */
1664 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1665 {
1666 /* Don't disable pipe A or pipe A PLLs if needed */
1667 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1668 return;
1669
1670 /* Make sure the pipe isn't still relying on us */
1671 assert_pipe_disabled(dev_priv, pipe);
1672
1673 I915_WRITE(DPLL(pipe), 0);
1674 POSTING_READ(DPLL(pipe));
1675 }
1676
1677 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1678 {
1679 u32 val = 0;
1680
1681 /* Make sure the pipe isn't still relying on us */
1682 assert_pipe_disabled(dev_priv, pipe);
1683
1684 /*
1685 * Leave integrated clock source and reference clock enabled for pipe B.
1686 * The latter is needed for VGA hotplug / manual detection.
1687 */
1688 if (pipe == PIPE_B)
1689 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1690 I915_WRITE(DPLL(pipe), val);
1691 POSTING_READ(DPLL(pipe));
1692
1693 }
1694
1695 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1696 {
1697 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1698 u32 val;
1699
1700 /* Make sure the pipe isn't still relying on us */
1701 assert_pipe_disabled(dev_priv, pipe);
1702
1703 /* Set PLL en = 0 */
1704 val = DPLL_SSC_REF_CLOCK_CHV;
1705 if (pipe != PIPE_A)
1706 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1707 I915_WRITE(DPLL(pipe), val);
1708 POSTING_READ(DPLL(pipe));
1709
1710 mutex_lock(&dev_priv->dpio_lock);
1711
1712 /* Disable 10bit clock to display controller */
1713 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1714 val &= ~DPIO_DCLKP_EN;
1715 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1716
1717 mutex_unlock(&dev_priv->dpio_lock);
1718 }
1719
1720 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1721 struct intel_digital_port *dport)
1722 {
1723 u32 port_mask;
1724 int dpll_reg;
1725
1726 switch (dport->port) {
1727 case PORT_B:
1728 port_mask = DPLL_PORTB_READY_MASK;
1729 dpll_reg = DPLL(0);
1730 break;
1731 case PORT_C:
1732 port_mask = DPLL_PORTC_READY_MASK;
1733 dpll_reg = DPLL(0);
1734 break;
1735 case PORT_D:
1736 port_mask = DPLL_PORTD_READY_MASK;
1737 dpll_reg = DPIO_PHY_STATUS;
1738 break;
1739 default:
1740 BUG();
1741 }
1742
1743 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1744 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1745 port_name(dport->port), I915_READ(dpll_reg));
1746 }
1747
1748 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1749 {
1750 struct drm_device *dev = crtc->base.dev;
1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1753
1754 WARN_ON(!pll->refcount);
1755 if (pll->active == 0) {
1756 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1757 WARN_ON(pll->on);
1758 assert_shared_dpll_disabled(dev_priv, pll);
1759
1760 pll->mode_set(dev_priv, pll);
1761 }
1762 }
1763
1764 /**
1765 * intel_enable_shared_dpll - enable PCH PLL
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to enable
1768 *
1769 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1770 * drives the transcoder clock.
1771 */
1772 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1773 {
1774 struct drm_device *dev = crtc->base.dev;
1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1777
1778 if (WARN_ON(pll == NULL))
1779 return;
1780
1781 if (WARN_ON(pll->refcount == 0))
1782 return;
1783
1784 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1785 pll->name, pll->active, pll->on,
1786 crtc->base.base.id);
1787
1788 if (pll->active++) {
1789 WARN_ON(!pll->on);
1790 assert_shared_dpll_enabled(dev_priv, pll);
1791 return;
1792 }
1793 WARN_ON(pll->on);
1794
1795 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1796 pll->enable(dev_priv, pll);
1797 pll->on = true;
1798 }
1799
1800 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 /* PCH only available on ILK+ */
1807 BUG_ON(INTEL_INFO(dev)->gen < 5);
1808 if (WARN_ON(pll == NULL))
1809 return;
1810
1811 if (WARN_ON(pll->refcount == 0))
1812 return;
1813
1814 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
1816 crtc->base.base.id);
1817
1818 if (WARN_ON(pll->active == 0)) {
1819 assert_shared_dpll_disabled(dev_priv, pll);
1820 return;
1821 }
1822
1823 assert_shared_dpll_enabled(dev_priv, pll);
1824 WARN_ON(!pll->on);
1825 if (--pll->active)
1826 return;
1827
1828 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1829 pll->disable(dev_priv, pll);
1830 pll->on = false;
1831 }
1832
1833 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1834 enum pipe pipe)
1835 {
1836 struct drm_device *dev = dev_priv->dev;
1837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1839 uint32_t reg, val, pipeconf_val;
1840
1841 /* PCH only available on ILK+ */
1842 BUG_ON(INTEL_INFO(dev)->gen < 5);
1843
1844 /* Make sure PCH DPLL is enabled */
1845 assert_shared_dpll_enabled(dev_priv,
1846 intel_crtc_to_shared_dpll(intel_crtc));
1847
1848 /* FDI must be feeding us bits for PCH ports */
1849 assert_fdi_tx_enabled(dev_priv, pipe);
1850 assert_fdi_rx_enabled(dev_priv, pipe);
1851
1852 if (HAS_PCH_CPT(dev)) {
1853 /* Workaround: Set the timing override bit before enabling the
1854 * pch transcoder. */
1855 reg = TRANS_CHICKEN2(pipe);
1856 val = I915_READ(reg);
1857 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1858 I915_WRITE(reg, val);
1859 }
1860
1861 reg = PCH_TRANSCONF(pipe);
1862 val = I915_READ(reg);
1863 pipeconf_val = I915_READ(PIPECONF(pipe));
1864
1865 if (HAS_PCH_IBX(dev_priv->dev)) {
1866 /*
1867 * make the BPC in transcoder be consistent with
1868 * that in pipeconf reg.
1869 */
1870 val &= ~PIPECONF_BPC_MASK;
1871 val |= pipeconf_val & PIPECONF_BPC_MASK;
1872 }
1873
1874 val &= ~TRANS_INTERLACE_MASK;
1875 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1876 if (HAS_PCH_IBX(dev_priv->dev) &&
1877 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1878 val |= TRANS_LEGACY_INTERLACED_ILK;
1879 else
1880 val |= TRANS_INTERLACED;
1881 else
1882 val |= TRANS_PROGRESSIVE;
1883
1884 I915_WRITE(reg, val | TRANS_ENABLE);
1885 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1886 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1887 }
1888
1889 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1890 enum transcoder cpu_transcoder)
1891 {
1892 u32 val, pipeconf_val;
1893
1894 /* PCH only available on ILK+ */
1895 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1896
1897 /* FDI must be feeding us bits for PCH ports */
1898 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1899 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1900
1901 /* Workaround: set timing override bit. */
1902 val = I915_READ(_TRANSA_CHICKEN2);
1903 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1904 I915_WRITE(_TRANSA_CHICKEN2, val);
1905
1906 val = TRANS_ENABLE;
1907 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1908
1909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1910 PIPECONF_INTERLACED_ILK)
1911 val |= TRANS_INTERLACED;
1912 else
1913 val |= TRANS_PROGRESSIVE;
1914
1915 I915_WRITE(LPT_TRANSCONF, val);
1916 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1917 DRM_ERROR("Failed to enable PCH transcoder\n");
1918 }
1919
1920 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1921 enum pipe pipe)
1922 {
1923 struct drm_device *dev = dev_priv->dev;
1924 uint32_t reg, val;
1925
1926 /* FDI relies on the transcoder */
1927 assert_fdi_tx_disabled(dev_priv, pipe);
1928 assert_fdi_rx_disabled(dev_priv, pipe);
1929
1930 /* Ports must be off as well */
1931 assert_pch_ports_disabled(dev_priv, pipe);
1932
1933 reg = PCH_TRANSCONF(pipe);
1934 val = I915_READ(reg);
1935 val &= ~TRANS_ENABLE;
1936 I915_WRITE(reg, val);
1937 /* wait for PCH transcoder off, transcoder state */
1938 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1939 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1940
1941 if (!HAS_PCH_IBX(dev)) {
1942 /* Workaround: Clear the timing override chicken bit again. */
1943 reg = TRANS_CHICKEN2(pipe);
1944 val = I915_READ(reg);
1945 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1946 I915_WRITE(reg, val);
1947 }
1948 }
1949
1950 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1951 {
1952 u32 val;
1953
1954 val = I915_READ(LPT_TRANSCONF);
1955 val &= ~TRANS_ENABLE;
1956 I915_WRITE(LPT_TRANSCONF, val);
1957 /* wait for PCH transcoder off, transcoder state */
1958 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1959 DRM_ERROR("Failed to disable PCH transcoder\n");
1960
1961 /* Workaround: clear timing override bit. */
1962 val = I915_READ(_TRANSA_CHICKEN2);
1963 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1964 I915_WRITE(_TRANSA_CHICKEN2, val);
1965 }
1966
1967 /**
1968 * intel_enable_pipe - enable a pipe, asserting requirements
1969 * @crtc: crtc responsible for the pipe
1970 *
1971 * Enable @crtc's pipe, making sure that various hardware specific requirements
1972 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1973 */
1974 static void intel_enable_pipe(struct intel_crtc *crtc)
1975 {
1976 struct drm_device *dev = crtc->base.dev;
1977 struct drm_i915_private *dev_priv = dev->dev_private;
1978 enum pipe pipe = crtc->pipe;
1979 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1980 pipe);
1981 enum pipe pch_transcoder;
1982 int reg;
1983 u32 val;
1984
1985 assert_planes_disabled(dev_priv, pipe);
1986 assert_cursor_disabled(dev_priv, pipe);
1987 assert_sprites_disabled(dev_priv, pipe);
1988
1989 if (HAS_PCH_LPT(dev_priv->dev))
1990 pch_transcoder = TRANSCODER_A;
1991 else
1992 pch_transcoder = pipe;
1993
1994 /*
1995 * A pipe without a PLL won't actually be able to drive bits from
1996 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1997 * need the check.
1998 */
1999 if (!HAS_PCH_SPLIT(dev_priv->dev))
2000 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2001 assert_dsi_pll_enabled(dev_priv);
2002 else
2003 assert_pll_enabled(dev_priv, pipe);
2004 else {
2005 if (crtc->config.has_pch_encoder) {
2006 /* if driving the PCH, we need FDI enabled */
2007 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2008 assert_fdi_tx_pll_enabled(dev_priv,
2009 (enum pipe) cpu_transcoder);
2010 }
2011 /* FIXME: assert CPU port conditions for SNB+ */
2012 }
2013
2014 reg = PIPECONF(cpu_transcoder);
2015 val = I915_READ(reg);
2016 if (val & PIPECONF_ENABLE) {
2017 WARN_ON(!(pipe == PIPE_A &&
2018 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2019 return;
2020 }
2021
2022 I915_WRITE(reg, val | PIPECONF_ENABLE);
2023 POSTING_READ(reg);
2024 }
2025
2026 /**
2027 * intel_disable_pipe - disable a pipe, asserting requirements
2028 * @dev_priv: i915 private structure
2029 * @pipe: pipe to disable
2030 *
2031 * Disable @pipe, making sure that various hardware specific requirements
2032 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2033 *
2034 * @pipe should be %PIPE_A or %PIPE_B.
2035 *
2036 * Will wait until the pipe has shut down before returning.
2037 */
2038 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2039 enum pipe pipe)
2040 {
2041 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2042 pipe);
2043 int reg;
2044 u32 val;
2045
2046 /*
2047 * Make sure planes won't keep trying to pump pixels to us,
2048 * or we might hang the display.
2049 */
2050 assert_planes_disabled(dev_priv, pipe);
2051 assert_cursor_disabled(dev_priv, pipe);
2052 assert_sprites_disabled(dev_priv, pipe);
2053
2054 /* Don't disable pipe A or pipe A PLLs if needed */
2055 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2056 return;
2057
2058 reg = PIPECONF(cpu_transcoder);
2059 val = I915_READ(reg);
2060 if ((val & PIPECONF_ENABLE) == 0)
2061 return;
2062
2063 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2064 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2065 }
2066
2067 /*
2068 * Plane regs are double buffered, going from enabled->disabled needs a
2069 * trigger in order to latch. The display address reg provides this.
2070 */
2071 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2072 enum plane plane)
2073 {
2074 struct drm_device *dev = dev_priv->dev;
2075 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2076
2077 I915_WRITE(reg, I915_READ(reg));
2078 POSTING_READ(reg);
2079 }
2080
2081 /**
2082 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2083 * @dev_priv: i915 private structure
2084 * @plane: plane to enable
2085 * @pipe: pipe being fed
2086 *
2087 * Enable @plane on @pipe, making sure that @pipe is running first.
2088 */
2089 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2090 enum plane plane, enum pipe pipe)
2091 {
2092 struct intel_crtc *intel_crtc =
2093 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2094 int reg;
2095 u32 val;
2096
2097 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2098 assert_pipe_enabled(dev_priv, pipe);
2099
2100 if (intel_crtc->primary_enabled)
2101 return;
2102
2103 intel_crtc->primary_enabled = true;
2104
2105 reg = DSPCNTR(plane);
2106 val = I915_READ(reg);
2107 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2108
2109 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2110 intel_flush_primary_plane(dev_priv, plane);
2111 }
2112
2113 /**
2114 * intel_disable_primary_hw_plane - disable the primary hardware plane
2115 * @dev_priv: i915 private structure
2116 * @plane: plane to disable
2117 * @pipe: pipe consuming the data
2118 *
2119 * Disable @plane; should be an independent operation.
2120 */
2121 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2122 enum plane plane, enum pipe pipe)
2123 {
2124 struct intel_crtc *intel_crtc =
2125 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2126 int reg;
2127 u32 val;
2128
2129 if (!intel_crtc->primary_enabled)
2130 return;
2131
2132 intel_crtc->primary_enabled = false;
2133
2134 reg = DSPCNTR(plane);
2135 val = I915_READ(reg);
2136 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2137
2138 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2139 intel_flush_primary_plane(dev_priv, plane);
2140 }
2141
2142 static bool need_vtd_wa(struct drm_device *dev)
2143 {
2144 #ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147 #endif
2148 return false;
2149 }
2150
2151 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2152 {
2153 int tile_height;
2154
2155 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2156 return ALIGN(height, tile_height);
2157 }
2158
2159 int
2160 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2161 struct drm_i915_gem_object *obj,
2162 struct intel_engine_cs *pipelined)
2163 {
2164 struct drm_i915_private *dev_priv = dev->dev_private;
2165 u32 alignment;
2166 int ret;
2167
2168 switch (obj->tiling_mode) {
2169 case I915_TILING_NONE:
2170 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2171 alignment = 128 * 1024;
2172 else if (INTEL_INFO(dev)->gen >= 4)
2173 alignment = 4 * 1024;
2174 else
2175 alignment = 64 * 1024;
2176 break;
2177 case I915_TILING_X:
2178 /* pin() will align the object as required by fence */
2179 alignment = 0;
2180 break;
2181 case I915_TILING_Y:
2182 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2183 return -EINVAL;
2184 default:
2185 BUG();
2186 }
2187
2188 /* Note that the w/a also requires 64 PTE of padding following the
2189 * bo. We currently fill all unused PTE with the shadow page and so
2190 * we should always have valid PTE following the scanout preventing
2191 * the VT-d warning.
2192 */
2193 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2194 alignment = 256 * 1024;
2195
2196 dev_priv->mm.interruptible = false;
2197 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2198 if (ret)
2199 goto err_interruptible;
2200
2201 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2202 * fence, whereas 965+ only requires a fence if using
2203 * framebuffer compression. For simplicity, we always install
2204 * a fence as the cost is not that onerous.
2205 */
2206 ret = i915_gem_object_get_fence(obj);
2207 if (ret)
2208 goto err_unpin;
2209
2210 i915_gem_object_pin_fence(obj);
2211
2212 dev_priv->mm.interruptible = true;
2213 return 0;
2214
2215 err_unpin:
2216 i915_gem_object_unpin_from_display_plane(obj);
2217 err_interruptible:
2218 dev_priv->mm.interruptible = true;
2219 return ret;
2220 }
2221
2222 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2223 {
2224 i915_gem_object_unpin_fence(obj);
2225 i915_gem_object_unpin_from_display_plane(obj);
2226 }
2227
2228 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2229 * is assumed to be a power-of-two. */
2230 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2231 unsigned int tiling_mode,
2232 unsigned int cpp,
2233 unsigned int pitch)
2234 {
2235 if (tiling_mode != I915_TILING_NONE) {
2236 unsigned int tile_rows, tiles;
2237
2238 tile_rows = *y / 8;
2239 *y %= 8;
2240
2241 tiles = *x / (512/cpp);
2242 *x %= 512/cpp;
2243
2244 return tile_rows * pitch * 8 + tiles * 4096;
2245 } else {
2246 unsigned int offset;
2247
2248 offset = *y * pitch + *x * cpp;
2249 *y = 0;
2250 *x = (offset & 4095) / cpp;
2251 return offset & -4096;
2252 }
2253 }
2254
2255 int intel_format_to_fourcc(int format)
2256 {
2257 switch (format) {
2258 case DISPPLANE_8BPP:
2259 return DRM_FORMAT_C8;
2260 case DISPPLANE_BGRX555:
2261 return DRM_FORMAT_XRGB1555;
2262 case DISPPLANE_BGRX565:
2263 return DRM_FORMAT_RGB565;
2264 default:
2265 case DISPPLANE_BGRX888:
2266 return DRM_FORMAT_XRGB8888;
2267 case DISPPLANE_RGBX888:
2268 return DRM_FORMAT_XBGR8888;
2269 case DISPPLANE_BGRX101010:
2270 return DRM_FORMAT_XRGB2101010;
2271 case DISPPLANE_RGBX101010:
2272 return DRM_FORMAT_XBGR2101010;
2273 }
2274 }
2275
2276 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2277 struct intel_plane_config *plane_config)
2278 {
2279 struct drm_device *dev = crtc->base.dev;
2280 struct drm_i915_gem_object *obj = NULL;
2281 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2282 u32 base = plane_config->base;
2283
2284 if (plane_config->size == 0)
2285 return false;
2286
2287 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2288 plane_config->size);
2289 if (!obj)
2290 return false;
2291
2292 if (plane_config->tiled) {
2293 obj->tiling_mode = I915_TILING_X;
2294 obj->stride = crtc->base.primary->fb->pitches[0];
2295 }
2296
2297 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2298 mode_cmd.width = crtc->base.primary->fb->width;
2299 mode_cmd.height = crtc->base.primary->fb->height;
2300 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2301
2302 mutex_lock(&dev->struct_mutex);
2303
2304 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2305 &mode_cmd, obj)) {
2306 DRM_DEBUG_KMS("intel fb init failed\n");
2307 goto out_unref_obj;
2308 }
2309
2310 mutex_unlock(&dev->struct_mutex);
2311
2312 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2313 return true;
2314
2315 out_unref_obj:
2316 drm_gem_object_unreference(&obj->base);
2317 mutex_unlock(&dev->struct_mutex);
2318 return false;
2319 }
2320
2321 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2322 struct intel_plane_config *plane_config)
2323 {
2324 struct drm_device *dev = intel_crtc->base.dev;
2325 struct drm_crtc *c;
2326 struct intel_crtc *i;
2327 struct intel_framebuffer *fb;
2328
2329 if (!intel_crtc->base.primary->fb)
2330 return;
2331
2332 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2333 return;
2334
2335 kfree(intel_crtc->base.primary->fb);
2336 intel_crtc->base.primary->fb = NULL;
2337
2338 /*
2339 * Failed to alloc the obj, check to see if we should share
2340 * an fb with another CRTC instead
2341 */
2342 for_each_crtc(dev, c) {
2343 i = to_intel_crtc(c);
2344
2345 if (c == &intel_crtc->base)
2346 continue;
2347
2348 if (!i->active || !c->primary->fb)
2349 continue;
2350
2351 fb = to_intel_framebuffer(c->primary->fb);
2352 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2353 drm_framebuffer_reference(c->primary->fb);
2354 intel_crtc->base.primary->fb = c->primary->fb;
2355 break;
2356 }
2357 }
2358 }
2359
2360 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2361 struct drm_framebuffer *fb,
2362 int x, int y)
2363 {
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 struct intel_framebuffer *intel_fb;
2368 struct drm_i915_gem_object *obj;
2369 int plane = intel_crtc->plane;
2370 unsigned long linear_offset;
2371 u32 dspcntr;
2372 u32 reg;
2373
2374 intel_fb = to_intel_framebuffer(fb);
2375 obj = intel_fb->obj;
2376
2377 reg = DSPCNTR(plane);
2378 dspcntr = I915_READ(reg);
2379 /* Mask out pixel format bits in case we change it */
2380 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2381 switch (fb->pixel_format) {
2382 case DRM_FORMAT_C8:
2383 dspcntr |= DISPPLANE_8BPP;
2384 break;
2385 case DRM_FORMAT_XRGB1555:
2386 case DRM_FORMAT_ARGB1555:
2387 dspcntr |= DISPPLANE_BGRX555;
2388 break;
2389 case DRM_FORMAT_RGB565:
2390 dspcntr |= DISPPLANE_BGRX565;
2391 break;
2392 case DRM_FORMAT_XRGB8888:
2393 case DRM_FORMAT_ARGB8888:
2394 dspcntr |= DISPPLANE_BGRX888;
2395 break;
2396 case DRM_FORMAT_XBGR8888:
2397 case DRM_FORMAT_ABGR8888:
2398 dspcntr |= DISPPLANE_RGBX888;
2399 break;
2400 case DRM_FORMAT_XRGB2101010:
2401 case DRM_FORMAT_ARGB2101010:
2402 dspcntr |= DISPPLANE_BGRX101010;
2403 break;
2404 case DRM_FORMAT_XBGR2101010:
2405 case DRM_FORMAT_ABGR2101010:
2406 dspcntr |= DISPPLANE_RGBX101010;
2407 break;
2408 default:
2409 BUG();
2410 }
2411
2412 if (INTEL_INFO(dev)->gen >= 4) {
2413 if (obj->tiling_mode != I915_TILING_NONE)
2414 dspcntr |= DISPPLANE_TILED;
2415 else
2416 dspcntr &= ~DISPPLANE_TILED;
2417 }
2418
2419 if (IS_G4X(dev))
2420 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2421
2422 I915_WRITE(reg, dspcntr);
2423
2424 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2425
2426 if (INTEL_INFO(dev)->gen >= 4) {
2427 intel_crtc->dspaddr_offset =
2428 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2429 fb->bits_per_pixel / 8,
2430 fb->pitches[0]);
2431 linear_offset -= intel_crtc->dspaddr_offset;
2432 } else {
2433 intel_crtc->dspaddr_offset = linear_offset;
2434 }
2435
2436 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2437 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2438 fb->pitches[0]);
2439 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2440 if (INTEL_INFO(dev)->gen >= 4) {
2441 I915_WRITE(DSPSURF(plane),
2442 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2443 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2444 I915_WRITE(DSPLINOFF(plane), linear_offset);
2445 } else
2446 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2447 POSTING_READ(reg);
2448 }
2449
2450 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2451 struct drm_framebuffer *fb,
2452 int x, int y)
2453 {
2454 struct drm_device *dev = crtc->dev;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2457 struct intel_framebuffer *intel_fb;
2458 struct drm_i915_gem_object *obj;
2459 int plane = intel_crtc->plane;
2460 unsigned long linear_offset;
2461 u32 dspcntr;
2462 u32 reg;
2463
2464 intel_fb = to_intel_framebuffer(fb);
2465 obj = intel_fb->obj;
2466
2467 reg = DSPCNTR(plane);
2468 dspcntr = I915_READ(reg);
2469 /* Mask out pixel format bits in case we change it */
2470 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2471 switch (fb->pixel_format) {
2472 case DRM_FORMAT_C8:
2473 dspcntr |= DISPPLANE_8BPP;
2474 break;
2475 case DRM_FORMAT_RGB565:
2476 dspcntr |= DISPPLANE_BGRX565;
2477 break;
2478 case DRM_FORMAT_XRGB8888:
2479 case DRM_FORMAT_ARGB8888:
2480 dspcntr |= DISPPLANE_BGRX888;
2481 break;
2482 case DRM_FORMAT_XBGR8888:
2483 case DRM_FORMAT_ABGR8888:
2484 dspcntr |= DISPPLANE_RGBX888;
2485 break;
2486 case DRM_FORMAT_XRGB2101010:
2487 case DRM_FORMAT_ARGB2101010:
2488 dspcntr |= DISPPLANE_BGRX101010;
2489 break;
2490 case DRM_FORMAT_XBGR2101010:
2491 case DRM_FORMAT_ABGR2101010:
2492 dspcntr |= DISPPLANE_RGBX101010;
2493 break;
2494 default:
2495 BUG();
2496 }
2497
2498 if (obj->tiling_mode != I915_TILING_NONE)
2499 dspcntr |= DISPPLANE_TILED;
2500 else
2501 dspcntr &= ~DISPPLANE_TILED;
2502
2503 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2504 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2505 else
2506 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2507
2508 I915_WRITE(reg, dspcntr);
2509
2510 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2511 intel_crtc->dspaddr_offset =
2512 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2513 fb->bits_per_pixel / 8,
2514 fb->pitches[0]);
2515 linear_offset -= intel_crtc->dspaddr_offset;
2516
2517 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2518 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2519 fb->pitches[0]);
2520 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2521 I915_WRITE(DSPSURF(plane),
2522 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2523 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2524 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2525 } else {
2526 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2527 I915_WRITE(DSPLINOFF(plane), linear_offset);
2528 }
2529 POSTING_READ(reg);
2530 }
2531
2532 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2533 static int
2534 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2535 int x, int y, enum mode_set_atomic state)
2536 {
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539
2540 if (dev_priv->display.disable_fbc)
2541 dev_priv->display.disable_fbc(dev);
2542 intel_increase_pllclock(crtc);
2543
2544 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2545
2546 return 0;
2547 }
2548
2549 void intel_display_handle_reset(struct drm_device *dev)
2550 {
2551 struct drm_i915_private *dev_priv = dev->dev_private;
2552 struct drm_crtc *crtc;
2553
2554 /*
2555 * Flips in the rings have been nuked by the reset,
2556 * so complete all pending flips so that user space
2557 * will get its events and not get stuck.
2558 *
2559 * Also update the base address of all primary
2560 * planes to the the last fb to make sure we're
2561 * showing the correct fb after a reset.
2562 *
2563 * Need to make two loops over the crtcs so that we
2564 * don't try to grab a crtc mutex before the
2565 * pending_flip_queue really got woken up.
2566 */
2567
2568 for_each_crtc(dev, crtc) {
2569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2570 enum plane plane = intel_crtc->plane;
2571
2572 intel_prepare_page_flip(dev, plane);
2573 intel_finish_page_flip_plane(dev, plane);
2574 }
2575
2576 for_each_crtc(dev, crtc) {
2577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2578
2579 mutex_lock(&crtc->mutex);
2580 /*
2581 * FIXME: Once we have proper support for primary planes (and
2582 * disabling them without disabling the entire crtc) allow again
2583 * a NULL crtc->primary->fb.
2584 */
2585 if (intel_crtc->active && crtc->primary->fb)
2586 dev_priv->display.update_primary_plane(crtc,
2587 crtc->primary->fb,
2588 crtc->x,
2589 crtc->y);
2590 mutex_unlock(&crtc->mutex);
2591 }
2592 }
2593
2594 static int
2595 intel_finish_fb(struct drm_framebuffer *old_fb)
2596 {
2597 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2598 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2599 bool was_interruptible = dev_priv->mm.interruptible;
2600 int ret;
2601
2602 /* Big Hammer, we also need to ensure that any pending
2603 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2604 * current scanout is retired before unpinning the old
2605 * framebuffer.
2606 *
2607 * This should only fail upon a hung GPU, in which case we
2608 * can safely continue.
2609 */
2610 dev_priv->mm.interruptible = false;
2611 ret = i915_gem_object_finish_gpu(obj);
2612 dev_priv->mm.interruptible = was_interruptible;
2613
2614 return ret;
2615 }
2616
2617 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2618 {
2619 struct drm_device *dev = crtc->dev;
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622 unsigned long flags;
2623 bool pending;
2624
2625 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2626 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2627 return false;
2628
2629 spin_lock_irqsave(&dev->event_lock, flags);
2630 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2631 spin_unlock_irqrestore(&dev->event_lock, flags);
2632
2633 return pending;
2634 }
2635
2636 static int
2637 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2638 struct drm_framebuffer *fb)
2639 {
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 struct drm_framebuffer *old_fb;
2644 int ret;
2645
2646 if (intel_crtc_has_pending_flip(crtc)) {
2647 DRM_ERROR("pipe is still busy with an old pageflip\n");
2648 return -EBUSY;
2649 }
2650
2651 /* no fb bound */
2652 if (!fb) {
2653 DRM_ERROR("No FB bound\n");
2654 return 0;
2655 }
2656
2657 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2658 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2659 plane_name(intel_crtc->plane),
2660 INTEL_INFO(dev)->num_pipes);
2661 return -EINVAL;
2662 }
2663
2664 mutex_lock(&dev->struct_mutex);
2665 ret = intel_pin_and_fence_fb_obj(dev,
2666 to_intel_framebuffer(fb)->obj,
2667 NULL);
2668 mutex_unlock(&dev->struct_mutex);
2669 if (ret != 0) {
2670 DRM_ERROR("pin & fence failed\n");
2671 return ret;
2672 }
2673
2674 /*
2675 * Update pipe size and adjust fitter if needed: the reason for this is
2676 * that in compute_mode_changes we check the native mode (not the pfit
2677 * mode) to see if we can flip rather than do a full mode set. In the
2678 * fastboot case, we'll flip, but if we don't update the pipesrc and
2679 * pfit state, we'll end up with a big fb scanned out into the wrong
2680 * sized surface.
2681 *
2682 * To fix this properly, we need to hoist the checks up into
2683 * compute_mode_changes (or above), check the actual pfit state and
2684 * whether the platform allows pfit disable with pipe active, and only
2685 * then update the pipesrc and pfit state, even on the flip path.
2686 */
2687 if (i915.fastboot) {
2688 const struct drm_display_mode *adjusted_mode =
2689 &intel_crtc->config.adjusted_mode;
2690
2691 I915_WRITE(PIPESRC(intel_crtc->pipe),
2692 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2693 (adjusted_mode->crtc_vdisplay - 1));
2694 if (!intel_crtc->config.pch_pfit.enabled &&
2695 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2696 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2697 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2698 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2699 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2700 }
2701 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2702 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2703 }
2704
2705 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2706
2707 old_fb = crtc->primary->fb;
2708 crtc->primary->fb = fb;
2709 crtc->x = x;
2710 crtc->y = y;
2711
2712 if (old_fb) {
2713 if (intel_crtc->active && old_fb != fb)
2714 intel_wait_for_vblank(dev, intel_crtc->pipe);
2715 mutex_lock(&dev->struct_mutex);
2716 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2717 mutex_unlock(&dev->struct_mutex);
2718 }
2719
2720 mutex_lock(&dev->struct_mutex);
2721 intel_update_fbc(dev);
2722 intel_edp_psr_update(dev);
2723 mutex_unlock(&dev->struct_mutex);
2724
2725 return 0;
2726 }
2727
2728 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2729 {
2730 struct drm_device *dev = crtc->dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2733 int pipe = intel_crtc->pipe;
2734 u32 reg, temp;
2735
2736 /* enable normal train */
2737 reg = FDI_TX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (IS_IVYBRIDGE(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2741 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2745 }
2746 I915_WRITE(reg, temp);
2747
2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 if (HAS_PCH_CPT(dev)) {
2751 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2752 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2753 } else {
2754 temp &= ~FDI_LINK_TRAIN_NONE;
2755 temp |= FDI_LINK_TRAIN_NONE;
2756 }
2757 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2758
2759 /* wait one idle pattern time */
2760 POSTING_READ(reg);
2761 udelay(1000);
2762
2763 /* IVB wants error correction enabled */
2764 if (IS_IVYBRIDGE(dev))
2765 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2766 FDI_FE_ERRC_ENABLE);
2767 }
2768
2769 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2770 {
2771 return crtc->base.enabled && crtc->active &&
2772 crtc->config.has_pch_encoder;
2773 }
2774
2775 static void ivb_modeset_global_resources(struct drm_device *dev)
2776 {
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_crtc *pipe_B_crtc =
2779 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2780 struct intel_crtc *pipe_C_crtc =
2781 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2782 uint32_t temp;
2783
2784 /*
2785 * When everything is off disable fdi C so that we could enable fdi B
2786 * with all lanes. Note that we don't care about enabled pipes without
2787 * an enabled pch encoder.
2788 */
2789 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2790 !pipe_has_enabled_pch(pipe_C_crtc)) {
2791 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2792 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2793
2794 temp = I915_READ(SOUTH_CHICKEN1);
2795 temp &= ~FDI_BC_BIFURCATION_SELECT;
2796 DRM_DEBUG_KMS("disabling fdi C rx\n");
2797 I915_WRITE(SOUTH_CHICKEN1, temp);
2798 }
2799 }
2800
2801 /* The FDI link training functions for ILK/Ibexpeak. */
2802 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2803 {
2804 struct drm_device *dev = crtc->dev;
2805 struct drm_i915_private *dev_priv = dev->dev_private;
2806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2807 int pipe = intel_crtc->pipe;
2808 u32 reg, temp, tries;
2809
2810 /* FDI needs bits from pipe first */
2811 assert_pipe_enabled(dev_priv, pipe);
2812
2813 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2814 for train result */
2815 reg = FDI_RX_IMR(pipe);
2816 temp = I915_READ(reg);
2817 temp &= ~FDI_RX_SYMBOL_LOCK;
2818 temp &= ~FDI_RX_BIT_LOCK;
2819 I915_WRITE(reg, temp);
2820 I915_READ(reg);
2821 udelay(150);
2822
2823 /* enable CPU FDI TX and PCH FDI RX */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2827 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2828 temp &= ~FDI_LINK_TRAIN_NONE;
2829 temp |= FDI_LINK_TRAIN_PATTERN_1;
2830 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2831
2832 reg = FDI_RX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
2836 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2837
2838 POSTING_READ(reg);
2839 udelay(150);
2840
2841 /* Ironlake workaround, enable clock pointer after FDI enable*/
2842 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2843 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2844 FDI_RX_PHASE_SYNC_POINTER_EN);
2845
2846 reg = FDI_RX_IIR(pipe);
2847 for (tries = 0; tries < 5; tries++) {
2848 temp = I915_READ(reg);
2849 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2850
2851 if ((temp & FDI_RX_BIT_LOCK)) {
2852 DRM_DEBUG_KMS("FDI train 1 done.\n");
2853 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2854 break;
2855 }
2856 }
2857 if (tries == 5)
2858 DRM_ERROR("FDI train 1 fail!\n");
2859
2860 /* Train 2 */
2861 reg = FDI_TX_CTL(pipe);
2862 temp = I915_READ(reg);
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_2;
2865 I915_WRITE(reg, temp);
2866
2867 reg = FDI_RX_CTL(pipe);
2868 temp = I915_READ(reg);
2869 temp &= ~FDI_LINK_TRAIN_NONE;
2870 temp |= FDI_LINK_TRAIN_PATTERN_2;
2871 I915_WRITE(reg, temp);
2872
2873 POSTING_READ(reg);
2874 udelay(150);
2875
2876 reg = FDI_RX_IIR(pipe);
2877 for (tries = 0; tries < 5; tries++) {
2878 temp = I915_READ(reg);
2879 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2880
2881 if (temp & FDI_RX_SYMBOL_LOCK) {
2882 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2883 DRM_DEBUG_KMS("FDI train 2 done.\n");
2884 break;
2885 }
2886 }
2887 if (tries == 5)
2888 DRM_ERROR("FDI train 2 fail!\n");
2889
2890 DRM_DEBUG_KMS("FDI train done\n");
2891
2892 }
2893
2894 static const int snb_b_fdi_train_param[] = {
2895 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2896 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2897 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2898 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2899 };
2900
2901 /* The FDI link training functions for SNB/Cougarpoint. */
2902 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2903 {
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_i915_private *dev_priv = dev->dev_private;
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 int pipe = intel_crtc->pipe;
2908 u32 reg, temp, i, retry;
2909
2910 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2911 for train result */
2912 reg = FDI_RX_IMR(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~FDI_RX_SYMBOL_LOCK;
2915 temp &= ~FDI_RX_BIT_LOCK;
2916 I915_WRITE(reg, temp);
2917
2918 POSTING_READ(reg);
2919 udelay(150);
2920
2921 /* enable CPU FDI TX and PCH FDI RX */
2922 reg = FDI_TX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2925 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2926 temp &= ~FDI_LINK_TRAIN_NONE;
2927 temp |= FDI_LINK_TRAIN_PATTERN_1;
2928 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2929 /* SNB-B */
2930 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2931 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2932
2933 I915_WRITE(FDI_RX_MISC(pipe),
2934 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2935
2936 reg = FDI_RX_CTL(pipe);
2937 temp = I915_READ(reg);
2938 if (HAS_PCH_CPT(dev)) {
2939 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2941 } else {
2942 temp &= ~FDI_LINK_TRAIN_NONE;
2943 temp |= FDI_LINK_TRAIN_PATTERN_1;
2944 }
2945 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2946
2947 POSTING_READ(reg);
2948 udelay(150);
2949
2950 for (i = 0; i < 4; i++) {
2951 reg = FDI_TX_CTL(pipe);
2952 temp = I915_READ(reg);
2953 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2954 temp |= snb_b_fdi_train_param[i];
2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(500);
2959
2960 for (retry = 0; retry < 5; retry++) {
2961 reg = FDI_RX_IIR(pipe);
2962 temp = I915_READ(reg);
2963 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2964 if (temp & FDI_RX_BIT_LOCK) {
2965 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2966 DRM_DEBUG_KMS("FDI train 1 done.\n");
2967 break;
2968 }
2969 udelay(50);
2970 }
2971 if (retry < 5)
2972 break;
2973 }
2974 if (i == 4)
2975 DRM_ERROR("FDI train 1 fail!\n");
2976
2977 /* Train 2 */
2978 reg = FDI_TX_CTL(pipe);
2979 temp = I915_READ(reg);
2980 temp &= ~FDI_LINK_TRAIN_NONE;
2981 temp |= FDI_LINK_TRAIN_PATTERN_2;
2982 if (IS_GEN6(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2984 /* SNB-B */
2985 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2986 }
2987 I915_WRITE(reg, temp);
2988
2989 reg = FDI_RX_CTL(pipe);
2990 temp = I915_READ(reg);
2991 if (HAS_PCH_CPT(dev)) {
2992 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2993 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2994 } else {
2995 temp &= ~FDI_LINK_TRAIN_NONE;
2996 temp |= FDI_LINK_TRAIN_PATTERN_2;
2997 }
2998 I915_WRITE(reg, temp);
2999
3000 POSTING_READ(reg);
3001 udelay(150);
3002
3003 for (i = 0; i < 4; i++) {
3004 reg = FDI_TX_CTL(pipe);
3005 temp = I915_READ(reg);
3006 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3007 temp |= snb_b_fdi_train_param[i];
3008 I915_WRITE(reg, temp);
3009
3010 POSTING_READ(reg);
3011 udelay(500);
3012
3013 for (retry = 0; retry < 5; retry++) {
3014 reg = FDI_RX_IIR(pipe);
3015 temp = I915_READ(reg);
3016 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3017 if (temp & FDI_RX_SYMBOL_LOCK) {
3018 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3019 DRM_DEBUG_KMS("FDI train 2 done.\n");
3020 break;
3021 }
3022 udelay(50);
3023 }
3024 if (retry < 5)
3025 break;
3026 }
3027 if (i == 4)
3028 DRM_ERROR("FDI train 2 fail!\n");
3029
3030 DRM_DEBUG_KMS("FDI train done.\n");
3031 }
3032
3033 /* Manual link training for Ivy Bridge A0 parts */
3034 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
3040 u32 reg, temp, i, j;
3041
3042 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3043 for train result */
3044 reg = FDI_RX_IMR(pipe);
3045 temp = I915_READ(reg);
3046 temp &= ~FDI_RX_SYMBOL_LOCK;
3047 temp &= ~FDI_RX_BIT_LOCK;
3048 I915_WRITE(reg, temp);
3049
3050 POSTING_READ(reg);
3051 udelay(150);
3052
3053 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3054 I915_READ(FDI_RX_IIR(pipe)));
3055
3056 /* Try each vswing and preemphasis setting twice before moving on */
3057 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3058 /* disable first in case we need to retry */
3059 reg = FDI_TX_CTL(pipe);
3060 temp = I915_READ(reg);
3061 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3062 temp &= ~FDI_TX_ENABLE;
3063 I915_WRITE(reg, temp);
3064
3065 reg = FDI_RX_CTL(pipe);
3066 temp = I915_READ(reg);
3067 temp &= ~FDI_LINK_TRAIN_AUTO;
3068 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3069 temp &= ~FDI_RX_ENABLE;
3070 I915_WRITE(reg, temp);
3071
3072 /* enable CPU FDI TX and PCH FDI RX */
3073 reg = FDI_TX_CTL(pipe);
3074 temp = I915_READ(reg);
3075 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3076 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3077 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3078 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3079 temp |= snb_b_fdi_train_param[j/2];
3080 temp |= FDI_COMPOSITE_SYNC;
3081 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3082
3083 I915_WRITE(FDI_RX_MISC(pipe),
3084 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3085
3086 reg = FDI_RX_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3089 temp |= FDI_COMPOSITE_SYNC;
3090 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3091
3092 POSTING_READ(reg);
3093 udelay(1); /* should be 0.5us */
3094
3095 for (i = 0; i < 4; i++) {
3096 reg = FDI_RX_IIR(pipe);
3097 temp = I915_READ(reg);
3098 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3099
3100 if (temp & FDI_RX_BIT_LOCK ||
3101 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3102 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3103 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3104 i);
3105 break;
3106 }
3107 udelay(1); /* should be 0.5us */
3108 }
3109 if (i == 4) {
3110 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3111 continue;
3112 }
3113
3114 /* Train 2 */
3115 reg = FDI_TX_CTL(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3118 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3119 I915_WRITE(reg, temp);
3120
3121 reg = FDI_RX_CTL(pipe);
3122 temp = I915_READ(reg);
3123 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3124 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3125 I915_WRITE(reg, temp);
3126
3127 POSTING_READ(reg);
3128 udelay(2); /* should be 1.5us */
3129
3130 for (i = 0; i < 4; i++) {
3131 reg = FDI_RX_IIR(pipe);
3132 temp = I915_READ(reg);
3133 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3134
3135 if (temp & FDI_RX_SYMBOL_LOCK ||
3136 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3137 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3138 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3139 i);
3140 goto train_done;
3141 }
3142 udelay(2); /* should be 1.5us */
3143 }
3144 if (i == 4)
3145 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3146 }
3147
3148 train_done:
3149 DRM_DEBUG_KMS("FDI train done.\n");
3150 }
3151
3152 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3153 {
3154 struct drm_device *dev = intel_crtc->base.dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 int pipe = intel_crtc->pipe;
3157 u32 reg, temp;
3158
3159
3160 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3161 reg = FDI_RX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3164 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3165 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3166 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3167
3168 POSTING_READ(reg);
3169 udelay(200);
3170
3171 /* Switch from Rawclk to PCDclk */
3172 temp = I915_READ(reg);
3173 I915_WRITE(reg, temp | FDI_PCDCLK);
3174
3175 POSTING_READ(reg);
3176 udelay(200);
3177
3178 /* Enable CPU FDI TX PLL, always on for Ironlake */
3179 reg = FDI_TX_CTL(pipe);
3180 temp = I915_READ(reg);
3181 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3182 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3183
3184 POSTING_READ(reg);
3185 udelay(100);
3186 }
3187 }
3188
3189 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3190 {
3191 struct drm_device *dev = intel_crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp;
3195
3196 /* Switch from PCDclk to Rawclk */
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3200
3201 /* Disable CPU FDI TX PLL */
3202 reg = FDI_TX_CTL(pipe);
3203 temp = I915_READ(reg);
3204 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3205
3206 POSTING_READ(reg);
3207 udelay(100);
3208
3209 reg = FDI_RX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3212
3213 /* Wait for the clocks to turn off. */
3214 POSTING_READ(reg);
3215 udelay(100);
3216 }
3217
3218 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3219 {
3220 struct drm_device *dev = crtc->dev;
3221 struct drm_i915_private *dev_priv = dev->dev_private;
3222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3223 int pipe = intel_crtc->pipe;
3224 u32 reg, temp;
3225
3226 /* disable CPU FDI tx and PCH FDI rx */
3227 reg = FDI_TX_CTL(pipe);
3228 temp = I915_READ(reg);
3229 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3230 POSTING_READ(reg);
3231
3232 reg = FDI_RX_CTL(pipe);
3233 temp = I915_READ(reg);
3234 temp &= ~(0x7 << 16);
3235 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3236 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3237
3238 POSTING_READ(reg);
3239 udelay(100);
3240
3241 /* Ironlake workaround, disable clock pointer after downing FDI */
3242 if (HAS_PCH_IBX(dev))
3243 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3244
3245 /* still set train pattern 1 */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 temp &= ~FDI_LINK_TRAIN_NONE;
3249 temp |= FDI_LINK_TRAIN_PATTERN_1;
3250 I915_WRITE(reg, temp);
3251
3252 reg = FDI_RX_CTL(pipe);
3253 temp = I915_READ(reg);
3254 if (HAS_PCH_CPT(dev)) {
3255 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3256 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3257 } else {
3258 temp &= ~FDI_LINK_TRAIN_NONE;
3259 temp |= FDI_LINK_TRAIN_PATTERN_1;
3260 }
3261 /* BPC in FDI rx is consistent with that in PIPECONF */
3262 temp &= ~(0x07 << 16);
3263 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3264 I915_WRITE(reg, temp);
3265
3266 POSTING_READ(reg);
3267 udelay(100);
3268 }
3269
3270 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3271 {
3272 struct intel_crtc *crtc;
3273
3274 /* Note that we don't need to be called with mode_config.lock here
3275 * as our list of CRTC objects is static for the lifetime of the
3276 * device and so cannot disappear as we iterate. Similarly, we can
3277 * happily treat the predicates as racy, atomic checks as userspace
3278 * cannot claim and pin a new fb without at least acquring the
3279 * struct_mutex and so serialising with us.
3280 */
3281 for_each_intel_crtc(dev, crtc) {
3282 if (atomic_read(&crtc->unpin_work_count) == 0)
3283 continue;
3284
3285 if (crtc->unpin_work)
3286 intel_wait_for_vblank(dev, crtc->pipe);
3287
3288 return true;
3289 }
3290
3291 return false;
3292 }
3293
3294 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3295 {
3296 struct drm_device *dev = crtc->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298
3299 if (crtc->primary->fb == NULL)
3300 return;
3301
3302 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3303
3304 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3305 !intel_crtc_has_pending_flip(crtc),
3306 60*HZ) == 0);
3307
3308 mutex_lock(&dev->struct_mutex);
3309 intel_finish_fb(crtc->primary->fb);
3310 mutex_unlock(&dev->struct_mutex);
3311 }
3312
3313 /* Program iCLKIP clock to the desired frequency */
3314 static void lpt_program_iclkip(struct drm_crtc *crtc)
3315 {
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3319 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3320 u32 temp;
3321
3322 mutex_lock(&dev_priv->dpio_lock);
3323
3324 /* It is necessary to ungate the pixclk gate prior to programming
3325 * the divisors, and gate it back when it is done.
3326 */
3327 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3328
3329 /* Disable SSCCTL */
3330 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3331 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3332 SBI_SSCCTL_DISABLE,
3333 SBI_ICLK);
3334
3335 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3336 if (clock == 20000) {
3337 auxdiv = 1;
3338 divsel = 0x41;
3339 phaseinc = 0x20;
3340 } else {
3341 /* The iCLK virtual clock root frequency is in MHz,
3342 * but the adjusted_mode->crtc_clock in in KHz. To get the
3343 * divisors, it is necessary to divide one by another, so we
3344 * convert the virtual clock precision to KHz here for higher
3345 * precision.
3346 */
3347 u32 iclk_virtual_root_freq = 172800 * 1000;
3348 u32 iclk_pi_range = 64;
3349 u32 desired_divisor, msb_divisor_value, pi_value;
3350
3351 desired_divisor = (iclk_virtual_root_freq / clock);
3352 msb_divisor_value = desired_divisor / iclk_pi_range;
3353 pi_value = desired_divisor % iclk_pi_range;
3354
3355 auxdiv = 0;
3356 divsel = msb_divisor_value - 2;
3357 phaseinc = pi_value;
3358 }
3359
3360 /* This should not happen with any sane values */
3361 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3362 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3363 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3364 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3365
3366 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3367 clock,
3368 auxdiv,
3369 divsel,
3370 phasedir,
3371 phaseinc);
3372
3373 /* Program SSCDIVINTPHASE6 */
3374 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3375 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3376 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3377 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3378 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3379 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3380 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3381 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3382
3383 /* Program SSCAUXDIV */
3384 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3385 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3386 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3387 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3388
3389 /* Enable modulator and associated divider */
3390 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3391 temp &= ~SBI_SSCCTL_DISABLE;
3392 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3393
3394 /* Wait for initialization time */
3395 udelay(24);
3396
3397 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3398
3399 mutex_unlock(&dev_priv->dpio_lock);
3400 }
3401
3402 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3403 enum pipe pch_transcoder)
3404 {
3405 struct drm_device *dev = crtc->base.dev;
3406 struct drm_i915_private *dev_priv = dev->dev_private;
3407 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3408
3409 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3410 I915_READ(HTOTAL(cpu_transcoder)));
3411 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3412 I915_READ(HBLANK(cpu_transcoder)));
3413 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3414 I915_READ(HSYNC(cpu_transcoder)));
3415
3416 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3417 I915_READ(VTOTAL(cpu_transcoder)));
3418 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3419 I915_READ(VBLANK(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3421 I915_READ(VSYNC(cpu_transcoder)));
3422 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3423 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3424 }
3425
3426 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3427 {
3428 struct drm_i915_private *dev_priv = dev->dev_private;
3429 uint32_t temp;
3430
3431 temp = I915_READ(SOUTH_CHICKEN1);
3432 if (temp & FDI_BC_BIFURCATION_SELECT)
3433 return;
3434
3435 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3436 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3437
3438 temp |= FDI_BC_BIFURCATION_SELECT;
3439 DRM_DEBUG_KMS("enabling fdi C rx\n");
3440 I915_WRITE(SOUTH_CHICKEN1, temp);
3441 POSTING_READ(SOUTH_CHICKEN1);
3442 }
3443
3444 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3445 {
3446 struct drm_device *dev = intel_crtc->base.dev;
3447 struct drm_i915_private *dev_priv = dev->dev_private;
3448
3449 switch (intel_crtc->pipe) {
3450 case PIPE_A:
3451 break;
3452 case PIPE_B:
3453 if (intel_crtc->config.fdi_lanes > 2)
3454 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3455 else
3456 cpt_enable_fdi_bc_bifurcation(dev);
3457
3458 break;
3459 case PIPE_C:
3460 cpt_enable_fdi_bc_bifurcation(dev);
3461
3462 break;
3463 default:
3464 BUG();
3465 }
3466 }
3467
3468 /*
3469 * Enable PCH resources required for PCH ports:
3470 * - PCH PLLs
3471 * - FDI training & RX/TX
3472 * - update transcoder timings
3473 * - DP transcoding bits
3474 * - transcoder
3475 */
3476 static void ironlake_pch_enable(struct drm_crtc *crtc)
3477 {
3478 struct drm_device *dev = crtc->dev;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481 int pipe = intel_crtc->pipe;
3482 u32 reg, temp;
3483
3484 assert_pch_transcoder_disabled(dev_priv, pipe);
3485
3486 if (IS_IVYBRIDGE(dev))
3487 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3488
3489 /* Write the TU size bits before fdi link training, so that error
3490 * detection works. */
3491 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3492 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3493
3494 /* For PCH output, training FDI link */
3495 dev_priv->display.fdi_link_train(crtc);
3496
3497 /* We need to program the right clock selection before writing the pixel
3498 * mutliplier into the DPLL. */
3499 if (HAS_PCH_CPT(dev)) {
3500 u32 sel;
3501
3502 temp = I915_READ(PCH_DPLL_SEL);
3503 temp |= TRANS_DPLL_ENABLE(pipe);
3504 sel = TRANS_DPLLB_SEL(pipe);
3505 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3506 temp |= sel;
3507 else
3508 temp &= ~sel;
3509 I915_WRITE(PCH_DPLL_SEL, temp);
3510 }
3511
3512 /* XXX: pch pll's can be enabled any time before we enable the PCH
3513 * transcoder, and we actually should do this to not upset any PCH
3514 * transcoder that already use the clock when we share it.
3515 *
3516 * Note that enable_shared_dpll tries to do the right thing, but
3517 * get_shared_dpll unconditionally resets the pll - we need that to have
3518 * the right LVDS enable sequence. */
3519 intel_enable_shared_dpll(intel_crtc);
3520
3521 /* set transcoder timing, panel must allow it */
3522 assert_panel_unlocked(dev_priv, pipe);
3523 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3524
3525 intel_fdi_normal_train(crtc);
3526
3527 /* For PCH DP, enable TRANS_DP_CTL */
3528 if (HAS_PCH_CPT(dev) &&
3529 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3530 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3531 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3532 reg = TRANS_DP_CTL(pipe);
3533 temp = I915_READ(reg);
3534 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3535 TRANS_DP_SYNC_MASK |
3536 TRANS_DP_BPC_MASK);
3537 temp |= (TRANS_DP_OUTPUT_ENABLE |
3538 TRANS_DP_ENH_FRAMING);
3539 temp |= bpc << 9; /* same format but at 11:9 */
3540
3541 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3542 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3543 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3544 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3545
3546 switch (intel_trans_dp_port_sel(crtc)) {
3547 case PCH_DP_B:
3548 temp |= TRANS_DP_PORT_SEL_B;
3549 break;
3550 case PCH_DP_C:
3551 temp |= TRANS_DP_PORT_SEL_C;
3552 break;
3553 case PCH_DP_D:
3554 temp |= TRANS_DP_PORT_SEL_D;
3555 break;
3556 default:
3557 BUG();
3558 }
3559
3560 I915_WRITE(reg, temp);
3561 }
3562
3563 ironlake_enable_pch_transcoder(dev_priv, pipe);
3564 }
3565
3566 static void lpt_pch_enable(struct drm_crtc *crtc)
3567 {
3568 struct drm_device *dev = crtc->dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3572
3573 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3574
3575 lpt_program_iclkip(crtc);
3576
3577 /* Set transcoder timing. */
3578 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3579
3580 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3581 }
3582
3583 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3584 {
3585 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3586
3587 if (pll == NULL)
3588 return;
3589
3590 if (pll->refcount == 0) {
3591 WARN(1, "bad %s refcount\n", pll->name);
3592 return;
3593 }
3594
3595 if (--pll->refcount == 0) {
3596 WARN_ON(pll->on);
3597 WARN_ON(pll->active);
3598 }
3599
3600 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3601 }
3602
3603 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3604 {
3605 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3606 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3607 enum intel_dpll_id i;
3608
3609 if (pll) {
3610 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3611 crtc->base.base.id, pll->name);
3612 intel_put_shared_dpll(crtc);
3613 }
3614
3615 if (HAS_PCH_IBX(dev_priv->dev)) {
3616 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3617 i = (enum intel_dpll_id) crtc->pipe;
3618 pll = &dev_priv->shared_dplls[i];
3619
3620 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3621 crtc->base.base.id, pll->name);
3622
3623 WARN_ON(pll->refcount);
3624
3625 goto found;
3626 }
3627
3628 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3629 pll = &dev_priv->shared_dplls[i];
3630
3631 /* Only want to check enabled timings first */
3632 if (pll->refcount == 0)
3633 continue;
3634
3635 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3636 sizeof(pll->hw_state)) == 0) {
3637 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3638 crtc->base.base.id,
3639 pll->name, pll->refcount, pll->active);
3640
3641 goto found;
3642 }
3643 }
3644
3645 /* Ok no matching timings, maybe there's a free one? */
3646 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3647 pll = &dev_priv->shared_dplls[i];
3648 if (pll->refcount == 0) {
3649 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3650 crtc->base.base.id, pll->name);
3651 goto found;
3652 }
3653 }
3654
3655 return NULL;
3656
3657 found:
3658 if (pll->refcount == 0)
3659 pll->hw_state = crtc->config.dpll_hw_state;
3660
3661 crtc->config.shared_dpll = i;
3662 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3663 pipe_name(crtc->pipe));
3664
3665 pll->refcount++;
3666
3667 return pll;
3668 }
3669
3670 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3671 {
3672 struct drm_i915_private *dev_priv = dev->dev_private;
3673 int dslreg = PIPEDSL(pipe);
3674 u32 temp;
3675
3676 temp = I915_READ(dslreg);
3677 udelay(500);
3678 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3679 if (wait_for(I915_READ(dslreg) != temp, 5))
3680 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3681 }
3682 }
3683
3684 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3685 {
3686 struct drm_device *dev = crtc->base.dev;
3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 int pipe = crtc->pipe;
3689
3690 if (crtc->config.pch_pfit.enabled) {
3691 /* Force use of hard-coded filter coefficients
3692 * as some pre-programmed values are broken,
3693 * e.g. x201.
3694 */
3695 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3696 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3697 PF_PIPE_SEL_IVB(pipe));
3698 else
3699 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3700 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3701 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3702 }
3703 }
3704
3705 static void intel_enable_planes(struct drm_crtc *crtc)
3706 {
3707 struct drm_device *dev = crtc->dev;
3708 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3709 struct drm_plane *plane;
3710 struct intel_plane *intel_plane;
3711
3712 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3713 intel_plane = to_intel_plane(plane);
3714 if (intel_plane->pipe == pipe)
3715 intel_plane_restore(&intel_plane->base);
3716 }
3717 }
3718
3719 static void intel_disable_planes(struct drm_crtc *crtc)
3720 {
3721 struct drm_device *dev = crtc->dev;
3722 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3723 struct drm_plane *plane;
3724 struct intel_plane *intel_plane;
3725
3726 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3727 intel_plane = to_intel_plane(plane);
3728 if (intel_plane->pipe == pipe)
3729 intel_plane_disable(&intel_plane->base);
3730 }
3731 }
3732
3733 void hsw_enable_ips(struct intel_crtc *crtc)
3734 {
3735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737
3738 if (!crtc->config.ips_enabled)
3739 return;
3740
3741 /* We can only enable IPS after we enable a plane and wait for a vblank */
3742 intel_wait_for_vblank(dev, crtc->pipe);
3743
3744 assert_plane_enabled(dev_priv, crtc->plane);
3745 if (IS_BROADWELL(dev)) {
3746 mutex_lock(&dev_priv->rps.hw_lock);
3747 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3748 mutex_unlock(&dev_priv->rps.hw_lock);
3749 /* Quoting Art Runyan: "its not safe to expect any particular
3750 * value in IPS_CTL bit 31 after enabling IPS through the
3751 * mailbox." Moreover, the mailbox may return a bogus state,
3752 * so we need to just enable it and continue on.
3753 */
3754 } else {
3755 I915_WRITE(IPS_CTL, IPS_ENABLE);
3756 /* The bit only becomes 1 in the next vblank, so this wait here
3757 * is essentially intel_wait_for_vblank. If we don't have this
3758 * and don't wait for vblanks until the end of crtc_enable, then
3759 * the HW state readout code will complain that the expected
3760 * IPS_CTL value is not the one we read. */
3761 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3762 DRM_ERROR("Timed out waiting for IPS enable\n");
3763 }
3764 }
3765
3766 void hsw_disable_ips(struct intel_crtc *crtc)
3767 {
3768 struct drm_device *dev = crtc->base.dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770
3771 if (!crtc->config.ips_enabled)
3772 return;
3773
3774 assert_plane_enabled(dev_priv, crtc->plane);
3775 if (IS_BROADWELL(dev)) {
3776 mutex_lock(&dev_priv->rps.hw_lock);
3777 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3778 mutex_unlock(&dev_priv->rps.hw_lock);
3779 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3780 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3781 DRM_ERROR("Timed out waiting for IPS disable\n");
3782 } else {
3783 I915_WRITE(IPS_CTL, 0);
3784 POSTING_READ(IPS_CTL);
3785 }
3786
3787 /* We need to wait for a vblank before we can disable the plane. */
3788 intel_wait_for_vblank(dev, crtc->pipe);
3789 }
3790
3791 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3792 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3793 {
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 enum pipe pipe = intel_crtc->pipe;
3798 int palreg = PALETTE(pipe);
3799 int i;
3800 bool reenable_ips = false;
3801
3802 /* The clocks have to be on to load the palette. */
3803 if (!crtc->enabled || !intel_crtc->active)
3804 return;
3805
3806 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3808 assert_dsi_pll_enabled(dev_priv);
3809 else
3810 assert_pll_enabled(dev_priv, pipe);
3811 }
3812
3813 /* use legacy palette for Ironlake */
3814 if (HAS_PCH_SPLIT(dev))
3815 palreg = LGC_PALETTE(pipe);
3816
3817 /* Workaround : Do not read or write the pipe palette/gamma data while
3818 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3819 */
3820 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3821 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3822 GAMMA_MODE_MODE_SPLIT)) {
3823 hsw_disable_ips(intel_crtc);
3824 reenable_ips = true;
3825 }
3826
3827 for (i = 0; i < 256; i++) {
3828 I915_WRITE(palreg + 4 * i,
3829 (intel_crtc->lut_r[i] << 16) |
3830 (intel_crtc->lut_g[i] << 8) |
3831 intel_crtc->lut_b[i]);
3832 }
3833
3834 if (reenable_ips)
3835 hsw_enable_ips(intel_crtc);
3836 }
3837
3838 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3839 {
3840 if (!enable && intel_crtc->overlay) {
3841 struct drm_device *dev = intel_crtc->base.dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843
3844 mutex_lock(&dev->struct_mutex);
3845 dev_priv->mm.interruptible = false;
3846 (void) intel_overlay_switch_off(intel_crtc->overlay);
3847 dev_priv->mm.interruptible = true;
3848 mutex_unlock(&dev->struct_mutex);
3849 }
3850
3851 /* Let userspace switch the overlay on again. In most cases userspace
3852 * has to recompute where to put it anyway.
3853 */
3854 }
3855
3856 /**
3857 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3858 * cursor plane briefly if not already running after enabling the display
3859 * plane.
3860 * This workaround avoids occasional blank screens when self refresh is
3861 * enabled.
3862 */
3863 static void
3864 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3865 {
3866 u32 cntl = I915_READ(CURCNTR(pipe));
3867
3868 if ((cntl & CURSOR_MODE) == 0) {
3869 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3870
3871 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3872 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3873 intel_wait_for_vblank(dev_priv->dev, pipe);
3874 I915_WRITE(CURCNTR(pipe), cntl);
3875 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3876 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3877 }
3878 }
3879
3880 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3881 {
3882 struct drm_device *dev = crtc->dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3885 int pipe = intel_crtc->pipe;
3886 int plane = intel_crtc->plane;
3887
3888 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3889 intel_enable_planes(crtc);
3890 /* The fixup needs to happen before cursor is enabled */
3891 if (IS_G4X(dev))
3892 g4x_fixup_plane(dev_priv, pipe);
3893 intel_crtc_update_cursor(crtc, true);
3894 intel_crtc_dpms_overlay(intel_crtc, true);
3895
3896 hsw_enable_ips(intel_crtc);
3897
3898 mutex_lock(&dev->struct_mutex);
3899 intel_update_fbc(dev);
3900 intel_edp_psr_update(dev);
3901 mutex_unlock(&dev->struct_mutex);
3902 }
3903
3904 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3905 {
3906 struct drm_device *dev = crtc->dev;
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3910 int plane = intel_crtc->plane;
3911
3912 intel_crtc_wait_for_pending_flips(crtc);
3913 drm_crtc_vblank_off(crtc);
3914
3915 if (dev_priv->fbc.plane == plane)
3916 intel_disable_fbc(dev);
3917
3918 hsw_disable_ips(intel_crtc);
3919
3920 intel_crtc_dpms_overlay(intel_crtc, false);
3921 intel_crtc_update_cursor(crtc, false);
3922 intel_disable_planes(crtc);
3923 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3924 }
3925
3926 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3927 {
3928 struct drm_device *dev = crtc->dev;
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931 struct intel_encoder *encoder;
3932 int pipe = intel_crtc->pipe;
3933 enum plane plane = intel_crtc->plane;
3934
3935 WARN_ON(!crtc->enabled);
3936
3937 if (intel_crtc->active)
3938 return;
3939
3940 if (intel_crtc->config.has_pch_encoder)
3941 intel_prepare_shared_dpll(intel_crtc);
3942
3943 if (intel_crtc->config.has_dp_encoder)
3944 intel_dp_set_m_n(intel_crtc);
3945
3946 intel_set_pipe_timings(intel_crtc);
3947
3948 if (intel_crtc->config.has_pch_encoder) {
3949 intel_cpu_transcoder_set_m_n(intel_crtc,
3950 &intel_crtc->config.fdi_m_n);
3951 }
3952
3953 ironlake_set_pipeconf(crtc);
3954
3955 /* Set up the display plane register */
3956 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3957 POSTING_READ(DSPCNTR(plane));
3958
3959 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3960 crtc->x, crtc->y);
3961
3962 intel_crtc->active = true;
3963
3964 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3965 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3966
3967 for_each_encoder_on_crtc(dev, crtc, encoder)
3968 if (encoder->pre_enable)
3969 encoder->pre_enable(encoder);
3970
3971 if (intel_crtc->config.has_pch_encoder) {
3972 /* Note: FDI PLL enabling _must_ be done before we enable the
3973 * cpu pipes, hence this is separate from all the other fdi/pch
3974 * enabling. */
3975 ironlake_fdi_pll_enable(intel_crtc);
3976 } else {
3977 assert_fdi_tx_disabled(dev_priv, pipe);
3978 assert_fdi_rx_disabled(dev_priv, pipe);
3979 }
3980
3981 ironlake_pfit_enable(intel_crtc);
3982
3983 /*
3984 * On ILK+ LUT must be loaded before the pipe is running but with
3985 * clocks enabled
3986 */
3987 intel_crtc_load_lut(crtc);
3988
3989 intel_update_watermarks(crtc);
3990 intel_enable_pipe(intel_crtc);
3991
3992 if (intel_crtc->config.has_pch_encoder)
3993 ironlake_pch_enable(crtc);
3994
3995 for_each_encoder_on_crtc(dev, crtc, encoder)
3996 encoder->enable(encoder);
3997
3998 if (HAS_PCH_CPT(dev))
3999 cpt_verify_modeset(dev, intel_crtc->pipe);
4000
4001 intel_crtc_enable_planes(crtc);
4002
4003 drm_crtc_vblank_on(crtc);
4004 }
4005
4006 /* IPS only exists on ULT machines and is tied to pipe A. */
4007 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4008 {
4009 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4010 }
4011
4012 /*
4013 * This implements the workaround described in the "notes" section of the mode
4014 * set sequence documentation. When going from no pipes or single pipe to
4015 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4016 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4017 */
4018 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4019 {
4020 struct drm_device *dev = crtc->base.dev;
4021 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4022
4023 /* We want to get the other_active_crtc only if there's only 1 other
4024 * active crtc. */
4025 for_each_intel_crtc(dev, crtc_it) {
4026 if (!crtc_it->active || crtc_it == crtc)
4027 continue;
4028
4029 if (other_active_crtc)
4030 return;
4031
4032 other_active_crtc = crtc_it;
4033 }
4034 if (!other_active_crtc)
4035 return;
4036
4037 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4038 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4039 }
4040
4041 static void haswell_crtc_enable(struct drm_crtc *crtc)
4042 {
4043 struct drm_device *dev = crtc->dev;
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4046 struct intel_encoder *encoder;
4047 int pipe = intel_crtc->pipe;
4048 enum plane plane = intel_crtc->plane;
4049
4050 WARN_ON(!crtc->enabled);
4051
4052 if (intel_crtc->active)
4053 return;
4054
4055 if (intel_crtc->config.has_dp_encoder)
4056 intel_dp_set_m_n(intel_crtc);
4057
4058 intel_set_pipe_timings(intel_crtc);
4059
4060 if (intel_crtc->config.has_pch_encoder) {
4061 intel_cpu_transcoder_set_m_n(intel_crtc,
4062 &intel_crtc->config.fdi_m_n);
4063 }
4064
4065 haswell_set_pipeconf(crtc);
4066
4067 intel_set_pipe_csc(crtc);
4068
4069 /* Set up the display plane register */
4070 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4071 POSTING_READ(DSPCNTR(plane));
4072
4073 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4074 crtc->x, crtc->y);
4075
4076 intel_crtc->active = true;
4077
4078 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4079 if (intel_crtc->config.has_pch_encoder)
4080 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4081
4082 if (intel_crtc->config.has_pch_encoder)
4083 dev_priv->display.fdi_link_train(crtc);
4084
4085 for_each_encoder_on_crtc(dev, crtc, encoder)
4086 if (encoder->pre_enable)
4087 encoder->pre_enable(encoder);
4088
4089 intel_ddi_enable_pipe_clock(intel_crtc);
4090
4091 ironlake_pfit_enable(intel_crtc);
4092
4093 /*
4094 * On ILK+ LUT must be loaded before the pipe is running but with
4095 * clocks enabled
4096 */
4097 intel_crtc_load_lut(crtc);
4098
4099 intel_ddi_set_pipe_settings(crtc);
4100 intel_ddi_enable_transcoder_func(crtc);
4101
4102 intel_update_watermarks(crtc);
4103 intel_enable_pipe(intel_crtc);
4104
4105 if (intel_crtc->config.has_pch_encoder)
4106 lpt_pch_enable(crtc);
4107
4108 for_each_encoder_on_crtc(dev, crtc, encoder) {
4109 encoder->enable(encoder);
4110 intel_opregion_notify_encoder(encoder, true);
4111 }
4112
4113 /* If we change the relative order between pipe/planes enabling, we need
4114 * to change the workaround. */
4115 haswell_mode_set_planes_workaround(intel_crtc);
4116 intel_crtc_enable_planes(crtc);
4117
4118 drm_crtc_vblank_on(crtc);
4119 }
4120
4121 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4122 {
4123 struct drm_device *dev = crtc->base.dev;
4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 int pipe = crtc->pipe;
4126
4127 /* To avoid upsetting the power well on haswell only disable the pfit if
4128 * it's in use. The hw state code will make sure we get this right. */
4129 if (crtc->config.pch_pfit.enabled) {
4130 I915_WRITE(PF_CTL(pipe), 0);
4131 I915_WRITE(PF_WIN_POS(pipe), 0);
4132 I915_WRITE(PF_WIN_SZ(pipe), 0);
4133 }
4134 }
4135
4136 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4137 {
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4141 struct intel_encoder *encoder;
4142 int pipe = intel_crtc->pipe;
4143 u32 reg, temp;
4144
4145 if (!intel_crtc->active)
4146 return;
4147
4148 intel_crtc_disable_planes(crtc);
4149
4150 for_each_encoder_on_crtc(dev, crtc, encoder)
4151 encoder->disable(encoder);
4152
4153 if (intel_crtc->config.has_pch_encoder)
4154 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4155
4156 intel_disable_pipe(dev_priv, pipe);
4157
4158 ironlake_pfit_disable(intel_crtc);
4159
4160 for_each_encoder_on_crtc(dev, crtc, encoder)
4161 if (encoder->post_disable)
4162 encoder->post_disable(encoder);
4163
4164 if (intel_crtc->config.has_pch_encoder) {
4165 ironlake_fdi_disable(crtc);
4166
4167 ironlake_disable_pch_transcoder(dev_priv, pipe);
4168 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4169
4170 if (HAS_PCH_CPT(dev)) {
4171 /* disable TRANS_DP_CTL */
4172 reg = TRANS_DP_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4175 TRANS_DP_PORT_SEL_MASK);
4176 temp |= TRANS_DP_PORT_SEL_NONE;
4177 I915_WRITE(reg, temp);
4178
4179 /* disable DPLL_SEL */
4180 temp = I915_READ(PCH_DPLL_SEL);
4181 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4182 I915_WRITE(PCH_DPLL_SEL, temp);
4183 }
4184
4185 /* disable PCH DPLL */
4186 intel_disable_shared_dpll(intel_crtc);
4187
4188 ironlake_fdi_pll_disable(intel_crtc);
4189 }
4190
4191 intel_crtc->active = false;
4192 intel_update_watermarks(crtc);
4193
4194 mutex_lock(&dev->struct_mutex);
4195 intel_update_fbc(dev);
4196 intel_edp_psr_update(dev);
4197 mutex_unlock(&dev->struct_mutex);
4198 }
4199
4200 static void haswell_crtc_disable(struct drm_crtc *crtc)
4201 {
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 struct intel_encoder *encoder;
4206 int pipe = intel_crtc->pipe;
4207 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4208
4209 if (!intel_crtc->active)
4210 return;
4211
4212 intel_crtc_disable_planes(crtc);
4213
4214 for_each_encoder_on_crtc(dev, crtc, encoder) {
4215 intel_opregion_notify_encoder(encoder, false);
4216 encoder->disable(encoder);
4217 }
4218
4219 if (intel_crtc->config.has_pch_encoder)
4220 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4221 intel_disable_pipe(dev_priv, pipe);
4222
4223 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4224
4225 ironlake_pfit_disable(intel_crtc);
4226
4227 intel_ddi_disable_pipe_clock(intel_crtc);
4228
4229 for_each_encoder_on_crtc(dev, crtc, encoder)
4230 if (encoder->post_disable)
4231 encoder->post_disable(encoder);
4232
4233 if (intel_crtc->config.has_pch_encoder) {
4234 lpt_disable_pch_transcoder(dev_priv);
4235 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4236 intel_ddi_fdi_disable(crtc);
4237 }
4238
4239 intel_crtc->active = false;
4240 intel_update_watermarks(crtc);
4241
4242 mutex_lock(&dev->struct_mutex);
4243 intel_update_fbc(dev);
4244 intel_edp_psr_update(dev);
4245 mutex_unlock(&dev->struct_mutex);
4246 }
4247
4248 static void ironlake_crtc_off(struct drm_crtc *crtc)
4249 {
4250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4251 intel_put_shared_dpll(intel_crtc);
4252 }
4253
4254 static void haswell_crtc_off(struct drm_crtc *crtc)
4255 {
4256 intel_ddi_put_crtc_pll(crtc);
4257 }
4258
4259 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4260 {
4261 struct drm_device *dev = crtc->base.dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_crtc_config *pipe_config = &crtc->config;
4264
4265 if (!crtc->config.gmch_pfit.control)
4266 return;
4267
4268 /*
4269 * The panel fitter should only be adjusted whilst the pipe is disabled,
4270 * according to register description and PRM.
4271 */
4272 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4273 assert_pipe_disabled(dev_priv, crtc->pipe);
4274
4275 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4276 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4277
4278 /* Border color in case we don't scale up to the full screen. Black by
4279 * default, change to something else for debugging. */
4280 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4281 }
4282
4283 #define for_each_power_domain(domain, mask) \
4284 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4285 if ((1 << (domain)) & (mask))
4286
4287 enum intel_display_power_domain
4288 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4289 {
4290 struct drm_device *dev = intel_encoder->base.dev;
4291 struct intel_digital_port *intel_dig_port;
4292
4293 switch (intel_encoder->type) {
4294 case INTEL_OUTPUT_UNKNOWN:
4295 /* Only DDI platforms should ever use this output type */
4296 WARN_ON_ONCE(!HAS_DDI(dev));
4297 case INTEL_OUTPUT_DISPLAYPORT:
4298 case INTEL_OUTPUT_HDMI:
4299 case INTEL_OUTPUT_EDP:
4300 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4301 switch (intel_dig_port->port) {
4302 case PORT_A:
4303 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4304 case PORT_B:
4305 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4306 case PORT_C:
4307 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4308 case PORT_D:
4309 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4310 default:
4311 WARN_ON_ONCE(1);
4312 return POWER_DOMAIN_PORT_OTHER;
4313 }
4314 case INTEL_OUTPUT_ANALOG:
4315 return POWER_DOMAIN_PORT_CRT;
4316 case INTEL_OUTPUT_DSI:
4317 return POWER_DOMAIN_PORT_DSI;
4318 default:
4319 return POWER_DOMAIN_PORT_OTHER;
4320 }
4321 }
4322
4323 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4324 {
4325 struct drm_device *dev = crtc->dev;
4326 struct intel_encoder *intel_encoder;
4327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4328 enum pipe pipe = intel_crtc->pipe;
4329 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4330 unsigned long mask;
4331 enum transcoder transcoder;
4332
4333 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4334
4335 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4336 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4337 if (pfit_enabled)
4338 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4339
4340 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4341 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4342
4343 return mask;
4344 }
4345
4346 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4347 bool enable)
4348 {
4349 if (dev_priv->power_domains.init_power_on == enable)
4350 return;
4351
4352 if (enable)
4353 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4354 else
4355 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4356
4357 dev_priv->power_domains.init_power_on = enable;
4358 }
4359
4360 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4361 {
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4364 struct intel_crtc *crtc;
4365
4366 /*
4367 * First get all needed power domains, then put all unneeded, to avoid
4368 * any unnecessary toggling of the power wells.
4369 */
4370 for_each_intel_crtc(dev, crtc) {
4371 enum intel_display_power_domain domain;
4372
4373 if (!crtc->base.enabled)
4374 continue;
4375
4376 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4377
4378 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4379 intel_display_power_get(dev_priv, domain);
4380 }
4381
4382 for_each_intel_crtc(dev, crtc) {
4383 enum intel_display_power_domain domain;
4384
4385 for_each_power_domain(domain, crtc->enabled_power_domains)
4386 intel_display_power_put(dev_priv, domain);
4387
4388 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4389 }
4390
4391 intel_display_set_init_power(dev_priv, false);
4392 }
4393
4394 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4395 {
4396 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4397
4398 /* Obtain SKU information */
4399 mutex_lock(&dev_priv->dpio_lock);
4400 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4401 CCK_FUSE_HPLL_FREQ_MASK;
4402 mutex_unlock(&dev_priv->dpio_lock);
4403
4404 return vco_freq[hpll_freq];
4405 }
4406
4407 /* Adjust CDclk dividers to allow high res or save power if possible */
4408 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4409 {
4410 struct drm_i915_private *dev_priv = dev->dev_private;
4411 u32 val, cmd;
4412
4413 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4414 dev_priv->vlv_cdclk_freq = cdclk;
4415
4416 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4417 cmd = 2;
4418 else if (cdclk == 266)
4419 cmd = 1;
4420 else
4421 cmd = 0;
4422
4423 mutex_lock(&dev_priv->rps.hw_lock);
4424 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4425 val &= ~DSPFREQGUAR_MASK;
4426 val |= (cmd << DSPFREQGUAR_SHIFT);
4427 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4428 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4429 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4430 50)) {
4431 DRM_ERROR("timed out waiting for CDclk change\n");
4432 }
4433 mutex_unlock(&dev_priv->rps.hw_lock);
4434
4435 if (cdclk == 400) {
4436 u32 divider, vco;
4437
4438 vco = valleyview_get_vco(dev_priv);
4439 divider = ((vco << 1) / cdclk) - 1;
4440
4441 mutex_lock(&dev_priv->dpio_lock);
4442 /* adjust cdclk divider */
4443 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4444 val &= ~0xf;
4445 val |= divider;
4446 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4447 mutex_unlock(&dev_priv->dpio_lock);
4448 }
4449
4450 mutex_lock(&dev_priv->dpio_lock);
4451 /* adjust self-refresh exit latency value */
4452 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4453 val &= ~0x7f;
4454
4455 /*
4456 * For high bandwidth configs, we set a higher latency in the bunit
4457 * so that the core display fetch happens in time to avoid underruns.
4458 */
4459 if (cdclk == 400)
4460 val |= 4500 / 250; /* 4.5 usec */
4461 else
4462 val |= 3000 / 250; /* 3.0 usec */
4463 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4464 mutex_unlock(&dev_priv->dpio_lock);
4465
4466 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4467 intel_i2c_reset(dev);
4468 }
4469
4470 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4471 {
4472 int cur_cdclk, vco;
4473 int divider;
4474
4475 vco = valleyview_get_vco(dev_priv);
4476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4479 mutex_unlock(&dev_priv->dpio_lock);
4480
4481 divider &= 0xf;
4482
4483 cur_cdclk = (vco << 1) / (divider + 1);
4484
4485 return cur_cdclk;
4486 }
4487
4488 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4489 int max_pixclk)
4490 {
4491 /*
4492 * Really only a few cases to deal with, as only 4 CDclks are supported:
4493 * 200MHz
4494 * 267MHz
4495 * 320MHz
4496 * 400MHz
4497 * So we check to see whether we're above 90% of the lower bin and
4498 * adjust if needed.
4499 */
4500 if (max_pixclk > 288000) {
4501 return 400;
4502 } else if (max_pixclk > 240000) {
4503 return 320;
4504 } else
4505 return 266;
4506 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4507 }
4508
4509 /* compute the max pixel clock for new configuration */
4510 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4511 {
4512 struct drm_device *dev = dev_priv->dev;
4513 struct intel_crtc *intel_crtc;
4514 int max_pixclk = 0;
4515
4516 for_each_intel_crtc(dev, intel_crtc) {
4517 if (intel_crtc->new_enabled)
4518 max_pixclk = max(max_pixclk,
4519 intel_crtc->new_config->adjusted_mode.crtc_clock);
4520 }
4521
4522 return max_pixclk;
4523 }
4524
4525 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4526 unsigned *prepare_pipes)
4527 {
4528 struct drm_i915_private *dev_priv = dev->dev_private;
4529 struct intel_crtc *intel_crtc;
4530 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4531
4532 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4533 dev_priv->vlv_cdclk_freq)
4534 return;
4535
4536 /* disable/enable all currently active pipes while we change cdclk */
4537 for_each_intel_crtc(dev, intel_crtc)
4538 if (intel_crtc->base.enabled)
4539 *prepare_pipes |= (1 << intel_crtc->pipe);
4540 }
4541
4542 static void valleyview_modeset_global_resources(struct drm_device *dev)
4543 {
4544 struct drm_i915_private *dev_priv = dev->dev_private;
4545 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4546 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4547
4548 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4549 valleyview_set_cdclk(dev, req_cdclk);
4550 modeset_update_crtc_power_domains(dev);
4551 }
4552
4553 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4554 {
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 struct intel_encoder *encoder;
4559 int pipe = intel_crtc->pipe;
4560 int plane = intel_crtc->plane;
4561 bool is_dsi;
4562 u32 dspcntr;
4563
4564 WARN_ON(!crtc->enabled);
4565
4566 if (intel_crtc->active)
4567 return;
4568
4569 vlv_prepare_pll(intel_crtc);
4570
4571 /* Set up the display plane register */
4572 dspcntr = DISPPLANE_GAMMA_ENABLE;
4573
4574 if (intel_crtc->config.has_dp_encoder)
4575 intel_dp_set_m_n(intel_crtc);
4576
4577 intel_set_pipe_timings(intel_crtc);
4578
4579 /* pipesrc and dspsize control the size that is scaled from,
4580 * which should always be the user's requested size.
4581 */
4582 I915_WRITE(DSPSIZE(plane),
4583 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4584 (intel_crtc->config.pipe_src_w - 1));
4585 I915_WRITE(DSPPOS(plane), 0);
4586
4587 i9xx_set_pipeconf(intel_crtc);
4588
4589 I915_WRITE(DSPCNTR(plane), dspcntr);
4590 POSTING_READ(DSPCNTR(plane));
4591
4592 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4593 crtc->x, crtc->y);
4594
4595 intel_crtc->active = true;
4596
4597 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4598
4599 for_each_encoder_on_crtc(dev, crtc, encoder)
4600 if (encoder->pre_pll_enable)
4601 encoder->pre_pll_enable(encoder);
4602
4603 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4604
4605 if (!is_dsi) {
4606 if (IS_CHERRYVIEW(dev))
4607 chv_enable_pll(intel_crtc);
4608 else
4609 vlv_enable_pll(intel_crtc);
4610 }
4611
4612 for_each_encoder_on_crtc(dev, crtc, encoder)
4613 if (encoder->pre_enable)
4614 encoder->pre_enable(encoder);
4615
4616 i9xx_pfit_enable(intel_crtc);
4617
4618 intel_crtc_load_lut(crtc);
4619
4620 intel_update_watermarks(crtc);
4621 intel_enable_pipe(intel_crtc);
4622
4623 for_each_encoder_on_crtc(dev, crtc, encoder)
4624 encoder->enable(encoder);
4625
4626 intel_crtc_enable_planes(crtc);
4627
4628 drm_crtc_vblank_on(crtc);
4629
4630 /* Underruns don't raise interrupts, so check manually. */
4631 i9xx_check_fifo_underruns(dev);
4632 }
4633
4634 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4635 {
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4640 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4641 }
4642
4643 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4644 {
4645 struct drm_device *dev = crtc->dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4648 struct intel_encoder *encoder;
4649 int pipe = intel_crtc->pipe;
4650 int plane = intel_crtc->plane;
4651 u32 dspcntr;
4652
4653 WARN_ON(!crtc->enabled);
4654
4655 if (intel_crtc->active)
4656 return;
4657
4658 i9xx_set_pll_dividers(intel_crtc);
4659
4660 /* Set up the display plane register */
4661 dspcntr = DISPPLANE_GAMMA_ENABLE;
4662
4663 if (pipe == 0)
4664 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4665 else
4666 dspcntr |= DISPPLANE_SEL_PIPE_B;
4667
4668 if (intel_crtc->config.has_dp_encoder)
4669 intel_dp_set_m_n(intel_crtc);
4670
4671 intel_set_pipe_timings(intel_crtc);
4672
4673 /* pipesrc and dspsize control the size that is scaled from,
4674 * which should always be the user's requested size.
4675 */
4676 I915_WRITE(DSPSIZE(plane),
4677 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4678 (intel_crtc->config.pipe_src_w - 1));
4679 I915_WRITE(DSPPOS(plane), 0);
4680
4681 i9xx_set_pipeconf(intel_crtc);
4682
4683 I915_WRITE(DSPCNTR(plane), dspcntr);
4684 POSTING_READ(DSPCNTR(plane));
4685
4686 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4687 crtc->x, crtc->y);
4688
4689 intel_crtc->active = true;
4690
4691 if (!IS_GEN2(dev))
4692 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4693
4694 for_each_encoder_on_crtc(dev, crtc, encoder)
4695 if (encoder->pre_enable)
4696 encoder->pre_enable(encoder);
4697
4698 i9xx_enable_pll(intel_crtc);
4699
4700 i9xx_pfit_enable(intel_crtc);
4701
4702 intel_crtc_load_lut(crtc);
4703
4704 intel_update_watermarks(crtc);
4705 intel_enable_pipe(intel_crtc);
4706
4707 for_each_encoder_on_crtc(dev, crtc, encoder)
4708 encoder->enable(encoder);
4709
4710 intel_crtc_enable_planes(crtc);
4711
4712 /*
4713 * Gen2 reports pipe underruns whenever all planes are disabled.
4714 * So don't enable underrun reporting before at least some planes
4715 * are enabled.
4716 * FIXME: Need to fix the logic to work when we turn off all planes
4717 * but leave the pipe running.
4718 */
4719 if (IS_GEN2(dev))
4720 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4721
4722 drm_crtc_vblank_on(crtc);
4723
4724 /* Underruns don't raise interrupts, so check manually. */
4725 i9xx_check_fifo_underruns(dev);
4726 }
4727
4728 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4729 {
4730 struct drm_device *dev = crtc->base.dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732
4733 if (!crtc->config.gmch_pfit.control)
4734 return;
4735
4736 assert_pipe_disabled(dev_priv, crtc->pipe);
4737
4738 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4739 I915_READ(PFIT_CONTROL));
4740 I915_WRITE(PFIT_CONTROL, 0);
4741 }
4742
4743 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4748 struct intel_encoder *encoder;
4749 int pipe = intel_crtc->pipe;
4750
4751 if (!intel_crtc->active)
4752 return;
4753
4754 /*
4755 * Gen2 reports pipe underruns whenever all planes are disabled.
4756 * So diasble underrun reporting before all the planes get disabled.
4757 * FIXME: Need to fix the logic to work when we turn off all planes
4758 * but leave the pipe running.
4759 */
4760 if (IS_GEN2(dev))
4761 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4762
4763 intel_crtc_disable_planes(crtc);
4764
4765 for_each_encoder_on_crtc(dev, crtc, encoder)
4766 encoder->disable(encoder);
4767
4768 /*
4769 * On gen2 planes are double buffered but the pipe isn't, so we must
4770 * wait for planes to fully turn off before disabling the pipe.
4771 */
4772 if (IS_GEN2(dev))
4773 intel_wait_for_vblank(dev, pipe);
4774
4775 intel_disable_pipe(dev_priv, pipe);
4776
4777 i9xx_pfit_disable(intel_crtc);
4778
4779 for_each_encoder_on_crtc(dev, crtc, encoder)
4780 if (encoder->post_disable)
4781 encoder->post_disable(encoder);
4782
4783 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4784 if (IS_CHERRYVIEW(dev))
4785 chv_disable_pll(dev_priv, pipe);
4786 else if (IS_VALLEYVIEW(dev))
4787 vlv_disable_pll(dev_priv, pipe);
4788 else
4789 i9xx_disable_pll(dev_priv, pipe);
4790 }
4791
4792 if (!IS_GEN2(dev))
4793 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4794
4795 intel_crtc->active = false;
4796 intel_update_watermarks(crtc);
4797
4798 mutex_lock(&dev->struct_mutex);
4799 intel_update_fbc(dev);
4800 intel_edp_psr_update(dev);
4801 mutex_unlock(&dev->struct_mutex);
4802 }
4803
4804 static void i9xx_crtc_off(struct drm_crtc *crtc)
4805 {
4806 }
4807
4808 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4809 bool enabled)
4810 {
4811 struct drm_device *dev = crtc->dev;
4812 struct drm_i915_master_private *master_priv;
4813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4814 int pipe = intel_crtc->pipe;
4815
4816 if (!dev->primary->master)
4817 return;
4818
4819 master_priv = dev->primary->master->driver_priv;
4820 if (!master_priv->sarea_priv)
4821 return;
4822
4823 switch (pipe) {
4824 case 0:
4825 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4826 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4827 break;
4828 case 1:
4829 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4830 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4831 break;
4832 default:
4833 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4834 break;
4835 }
4836 }
4837
4838 /**
4839 * Sets the power management mode of the pipe and plane.
4840 */
4841 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4842 {
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_encoder *intel_encoder;
4846 bool enable = false;
4847
4848 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4849 enable |= intel_encoder->connectors_active;
4850
4851 if (enable)
4852 dev_priv->display.crtc_enable(crtc);
4853 else
4854 dev_priv->display.crtc_disable(crtc);
4855
4856 intel_crtc_update_sarea(crtc, enable);
4857 }
4858
4859 static void intel_crtc_disable(struct drm_crtc *crtc)
4860 {
4861 struct drm_device *dev = crtc->dev;
4862 struct drm_connector *connector;
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864
4865 /* crtc should still be enabled when we disable it. */
4866 WARN_ON(!crtc->enabled);
4867
4868 dev_priv->display.crtc_disable(crtc);
4869 intel_crtc_update_sarea(crtc, false);
4870 dev_priv->display.off(crtc);
4871
4872 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4873 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4874 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4875
4876 if (crtc->primary->fb) {
4877 mutex_lock(&dev->struct_mutex);
4878 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4879 mutex_unlock(&dev->struct_mutex);
4880 crtc->primary->fb = NULL;
4881 }
4882
4883 /* Update computed state. */
4884 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4885 if (!connector->encoder || !connector->encoder->crtc)
4886 continue;
4887
4888 if (connector->encoder->crtc != crtc)
4889 continue;
4890
4891 connector->dpms = DRM_MODE_DPMS_OFF;
4892 to_intel_encoder(connector->encoder)->connectors_active = false;
4893 }
4894 }
4895
4896 void intel_encoder_destroy(struct drm_encoder *encoder)
4897 {
4898 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4899
4900 drm_encoder_cleanup(encoder);
4901 kfree(intel_encoder);
4902 }
4903
4904 /* Simple dpms helper for encoders with just one connector, no cloning and only
4905 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4906 * state of the entire output pipe. */
4907 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4908 {
4909 if (mode == DRM_MODE_DPMS_ON) {
4910 encoder->connectors_active = true;
4911
4912 intel_crtc_update_dpms(encoder->base.crtc);
4913 } else {
4914 encoder->connectors_active = false;
4915
4916 intel_crtc_update_dpms(encoder->base.crtc);
4917 }
4918 }
4919
4920 /* Cross check the actual hw state with our own modeset state tracking (and it's
4921 * internal consistency). */
4922 static void intel_connector_check_state(struct intel_connector *connector)
4923 {
4924 if (connector->get_hw_state(connector)) {
4925 struct intel_encoder *encoder = connector->encoder;
4926 struct drm_crtc *crtc;
4927 bool encoder_enabled;
4928 enum pipe pipe;
4929
4930 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4931 connector->base.base.id,
4932 drm_get_connector_name(&connector->base));
4933
4934 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4935 "wrong connector dpms state\n");
4936 WARN(connector->base.encoder != &encoder->base,
4937 "active connector not linked to encoder\n");
4938 WARN(!encoder->connectors_active,
4939 "encoder->connectors_active not set\n");
4940
4941 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4942 WARN(!encoder_enabled, "encoder not enabled\n");
4943 if (WARN_ON(!encoder->base.crtc))
4944 return;
4945
4946 crtc = encoder->base.crtc;
4947
4948 WARN(!crtc->enabled, "crtc not enabled\n");
4949 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4950 WARN(pipe != to_intel_crtc(crtc)->pipe,
4951 "encoder active on the wrong pipe\n");
4952 }
4953 }
4954
4955 /* Even simpler default implementation, if there's really no special case to
4956 * consider. */
4957 void intel_connector_dpms(struct drm_connector *connector, int mode)
4958 {
4959 /* All the simple cases only support two dpms states. */
4960 if (mode != DRM_MODE_DPMS_ON)
4961 mode = DRM_MODE_DPMS_OFF;
4962
4963 if (mode == connector->dpms)
4964 return;
4965
4966 connector->dpms = mode;
4967
4968 /* Only need to change hw state when actually enabled */
4969 if (connector->encoder)
4970 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4971
4972 intel_modeset_check_state(connector->dev);
4973 }
4974
4975 /* Simple connector->get_hw_state implementation for encoders that support only
4976 * one connector and no cloning and hence the encoder state determines the state
4977 * of the connector. */
4978 bool intel_connector_get_hw_state(struct intel_connector *connector)
4979 {
4980 enum pipe pipe = 0;
4981 struct intel_encoder *encoder = connector->encoder;
4982
4983 return encoder->get_hw_state(encoder, &pipe);
4984 }
4985
4986 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4987 struct intel_crtc_config *pipe_config)
4988 {
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 struct intel_crtc *pipe_B_crtc =
4991 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4992
4993 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4994 pipe_name(pipe), pipe_config->fdi_lanes);
4995 if (pipe_config->fdi_lanes > 4) {
4996 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4997 pipe_name(pipe), pipe_config->fdi_lanes);
4998 return false;
4999 }
5000
5001 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5002 if (pipe_config->fdi_lanes > 2) {
5003 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5004 pipe_config->fdi_lanes);
5005 return false;
5006 } else {
5007 return true;
5008 }
5009 }
5010
5011 if (INTEL_INFO(dev)->num_pipes == 2)
5012 return true;
5013
5014 /* Ivybridge 3 pipe is really complicated */
5015 switch (pipe) {
5016 case PIPE_A:
5017 return true;
5018 case PIPE_B:
5019 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5020 pipe_config->fdi_lanes > 2) {
5021 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5022 pipe_name(pipe), pipe_config->fdi_lanes);
5023 return false;
5024 }
5025 return true;
5026 case PIPE_C:
5027 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5028 pipe_B_crtc->config.fdi_lanes <= 2) {
5029 if (pipe_config->fdi_lanes > 2) {
5030 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5031 pipe_name(pipe), pipe_config->fdi_lanes);
5032 return false;
5033 }
5034 } else {
5035 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5036 return false;
5037 }
5038 return true;
5039 default:
5040 BUG();
5041 }
5042 }
5043
5044 #define RETRY 1
5045 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5046 struct intel_crtc_config *pipe_config)
5047 {
5048 struct drm_device *dev = intel_crtc->base.dev;
5049 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5050 int lane, link_bw, fdi_dotclock;
5051 bool setup_ok, needs_recompute = false;
5052
5053 retry:
5054 /* FDI is a binary signal running at ~2.7GHz, encoding
5055 * each output octet as 10 bits. The actual frequency
5056 * is stored as a divider into a 100MHz clock, and the
5057 * mode pixel clock is stored in units of 1KHz.
5058 * Hence the bw of each lane in terms of the mode signal
5059 * is:
5060 */
5061 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5062
5063 fdi_dotclock = adjusted_mode->crtc_clock;
5064
5065 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5066 pipe_config->pipe_bpp);
5067
5068 pipe_config->fdi_lanes = lane;
5069
5070 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5071 link_bw, &pipe_config->fdi_m_n);
5072
5073 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5074 intel_crtc->pipe, pipe_config);
5075 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5076 pipe_config->pipe_bpp -= 2*3;
5077 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5078 pipe_config->pipe_bpp);
5079 needs_recompute = true;
5080 pipe_config->bw_constrained = true;
5081
5082 goto retry;
5083 }
5084
5085 if (needs_recompute)
5086 return RETRY;
5087
5088 return setup_ok ? 0 : -EINVAL;
5089 }
5090
5091 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5092 struct intel_crtc_config *pipe_config)
5093 {
5094 pipe_config->ips_enabled = i915.enable_ips &&
5095 hsw_crtc_supports_ips(crtc) &&
5096 pipe_config->pipe_bpp <= 24;
5097 }
5098
5099 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5100 struct intel_crtc_config *pipe_config)
5101 {
5102 struct drm_device *dev = crtc->base.dev;
5103 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5104
5105 /* FIXME should check pixel clock limits on all platforms */
5106 if (INTEL_INFO(dev)->gen < 4) {
5107 struct drm_i915_private *dev_priv = dev->dev_private;
5108 int clock_limit =
5109 dev_priv->display.get_display_clock_speed(dev);
5110
5111 /*
5112 * Enable pixel doubling when the dot clock
5113 * is > 90% of the (display) core speed.
5114 *
5115 * GDG double wide on either pipe,
5116 * otherwise pipe A only.
5117 */
5118 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5119 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5120 clock_limit *= 2;
5121 pipe_config->double_wide = true;
5122 }
5123
5124 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5125 return -EINVAL;
5126 }
5127
5128 /*
5129 * Pipe horizontal size must be even in:
5130 * - DVO ganged mode
5131 * - LVDS dual channel mode
5132 * - Double wide pipe
5133 */
5134 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5135 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5136 pipe_config->pipe_src_w &= ~1;
5137
5138 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5139 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5140 */
5141 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5142 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5143 return -EINVAL;
5144
5145 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5146 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5147 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5148 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5149 * for lvds. */
5150 pipe_config->pipe_bpp = 8*3;
5151 }
5152
5153 if (HAS_IPS(dev))
5154 hsw_compute_ips_config(crtc, pipe_config);
5155
5156 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5157 * clock survives for now. */
5158 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5159 pipe_config->shared_dpll = crtc->config.shared_dpll;
5160
5161 if (pipe_config->has_pch_encoder)
5162 return ironlake_fdi_compute_config(crtc, pipe_config);
5163
5164 return 0;
5165 }
5166
5167 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5168 {
5169 return 400000; /* FIXME */
5170 }
5171
5172 static int i945_get_display_clock_speed(struct drm_device *dev)
5173 {
5174 return 400000;
5175 }
5176
5177 static int i915_get_display_clock_speed(struct drm_device *dev)
5178 {
5179 return 333000;
5180 }
5181
5182 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5183 {
5184 return 200000;
5185 }
5186
5187 static int pnv_get_display_clock_speed(struct drm_device *dev)
5188 {
5189 u16 gcfgc = 0;
5190
5191 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5192
5193 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5194 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5195 return 267000;
5196 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5197 return 333000;
5198 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5199 return 444000;
5200 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5201 return 200000;
5202 default:
5203 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5204 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5205 return 133000;
5206 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5207 return 167000;
5208 }
5209 }
5210
5211 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5212 {
5213 u16 gcfgc = 0;
5214
5215 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5216
5217 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5218 return 133000;
5219 else {
5220 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5221 case GC_DISPLAY_CLOCK_333_MHZ:
5222 return 333000;
5223 default:
5224 case GC_DISPLAY_CLOCK_190_200_MHZ:
5225 return 190000;
5226 }
5227 }
5228 }
5229
5230 static int i865_get_display_clock_speed(struct drm_device *dev)
5231 {
5232 return 266000;
5233 }
5234
5235 static int i855_get_display_clock_speed(struct drm_device *dev)
5236 {
5237 u16 hpllcc = 0;
5238 /* Assume that the hardware is in the high speed state. This
5239 * should be the default.
5240 */
5241 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5242 case GC_CLOCK_133_200:
5243 case GC_CLOCK_100_200:
5244 return 200000;
5245 case GC_CLOCK_166_250:
5246 return 250000;
5247 case GC_CLOCK_100_133:
5248 return 133000;
5249 }
5250
5251 /* Shouldn't happen */
5252 return 0;
5253 }
5254
5255 static int i830_get_display_clock_speed(struct drm_device *dev)
5256 {
5257 return 133000;
5258 }
5259
5260 static void
5261 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5262 {
5263 while (*num > DATA_LINK_M_N_MASK ||
5264 *den > DATA_LINK_M_N_MASK) {
5265 *num >>= 1;
5266 *den >>= 1;
5267 }
5268 }
5269
5270 static void compute_m_n(unsigned int m, unsigned int n,
5271 uint32_t *ret_m, uint32_t *ret_n)
5272 {
5273 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5274 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5275 intel_reduce_m_n_ratio(ret_m, ret_n);
5276 }
5277
5278 void
5279 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5280 int pixel_clock, int link_clock,
5281 struct intel_link_m_n *m_n)
5282 {
5283 m_n->tu = 64;
5284
5285 compute_m_n(bits_per_pixel * pixel_clock,
5286 link_clock * nlanes * 8,
5287 &m_n->gmch_m, &m_n->gmch_n);
5288
5289 compute_m_n(pixel_clock, link_clock,
5290 &m_n->link_m, &m_n->link_n);
5291 }
5292
5293 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5294 {
5295 if (i915.panel_use_ssc >= 0)
5296 return i915.panel_use_ssc != 0;
5297 return dev_priv->vbt.lvds_use_ssc
5298 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5299 }
5300
5301 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5302 {
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 int refclk;
5306
5307 if (IS_VALLEYVIEW(dev)) {
5308 refclk = 100000;
5309 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5310 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5311 refclk = dev_priv->vbt.lvds_ssc_freq;
5312 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5313 } else if (!IS_GEN2(dev)) {
5314 refclk = 96000;
5315 } else {
5316 refclk = 48000;
5317 }
5318
5319 return refclk;
5320 }
5321
5322 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5323 {
5324 return (1 << dpll->n) << 16 | dpll->m2;
5325 }
5326
5327 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5328 {
5329 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5330 }
5331
5332 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5333 intel_clock_t *reduced_clock)
5334 {
5335 struct drm_device *dev = crtc->base.dev;
5336 u32 fp, fp2 = 0;
5337
5338 if (IS_PINEVIEW(dev)) {
5339 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5340 if (reduced_clock)
5341 fp2 = pnv_dpll_compute_fp(reduced_clock);
5342 } else {
5343 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5344 if (reduced_clock)
5345 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5346 }
5347
5348 crtc->config.dpll_hw_state.fp0 = fp;
5349
5350 crtc->lowfreq_avail = false;
5351 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5352 reduced_clock && i915.powersave) {
5353 crtc->config.dpll_hw_state.fp1 = fp2;
5354 crtc->lowfreq_avail = true;
5355 } else {
5356 crtc->config.dpll_hw_state.fp1 = fp;
5357 }
5358 }
5359
5360 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5361 pipe)
5362 {
5363 u32 reg_val;
5364
5365 /*
5366 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5367 * and set it to a reasonable value instead.
5368 */
5369 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5370 reg_val &= 0xffffff00;
5371 reg_val |= 0x00000030;
5372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5373
5374 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5375 reg_val &= 0x8cffffff;
5376 reg_val = 0x8c000000;
5377 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5378
5379 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5380 reg_val &= 0xffffff00;
5381 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5382
5383 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5384 reg_val &= 0x00ffffff;
5385 reg_val |= 0xb0000000;
5386 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5387 }
5388
5389 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5390 struct intel_link_m_n *m_n)
5391 {
5392 struct drm_device *dev = crtc->base.dev;
5393 struct drm_i915_private *dev_priv = dev->dev_private;
5394 int pipe = crtc->pipe;
5395
5396 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5397 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5398 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5399 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5400 }
5401
5402 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5403 struct intel_link_m_n *m_n)
5404 {
5405 struct drm_device *dev = crtc->base.dev;
5406 struct drm_i915_private *dev_priv = dev->dev_private;
5407 int pipe = crtc->pipe;
5408 enum transcoder transcoder = crtc->config.cpu_transcoder;
5409
5410 if (INTEL_INFO(dev)->gen >= 5) {
5411 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5412 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5413 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5414 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5415 } else {
5416 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5417 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5418 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5419 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5420 }
5421 }
5422
5423 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5424 {
5425 if (crtc->config.has_pch_encoder)
5426 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5427 else
5428 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5429 }
5430
5431 static void vlv_update_pll(struct intel_crtc *crtc)
5432 {
5433 u32 dpll, dpll_md;
5434
5435 /*
5436 * Enable DPIO clock input. We should never disable the reference
5437 * clock for pipe B, since VGA hotplug / manual detection depends
5438 * on it.
5439 */
5440 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5441 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5442 /* We should never disable this, set it here for state tracking */
5443 if (crtc->pipe == PIPE_B)
5444 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5445 dpll |= DPLL_VCO_ENABLE;
5446 crtc->config.dpll_hw_state.dpll = dpll;
5447
5448 dpll_md = (crtc->config.pixel_multiplier - 1)
5449 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5450 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5451 }
5452
5453 static void vlv_prepare_pll(struct intel_crtc *crtc)
5454 {
5455 struct drm_device *dev = crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 int pipe = crtc->pipe;
5458 u32 mdiv;
5459 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5460 u32 coreclk, reg_val;
5461
5462 mutex_lock(&dev_priv->dpio_lock);
5463
5464 bestn = crtc->config.dpll.n;
5465 bestm1 = crtc->config.dpll.m1;
5466 bestm2 = crtc->config.dpll.m2;
5467 bestp1 = crtc->config.dpll.p1;
5468 bestp2 = crtc->config.dpll.p2;
5469
5470 /* See eDP HDMI DPIO driver vbios notes doc */
5471
5472 /* PLL B needs special handling */
5473 if (pipe == PIPE_B)
5474 vlv_pllb_recal_opamp(dev_priv, pipe);
5475
5476 /* Set up Tx target for periodic Rcomp update */
5477 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5478
5479 /* Disable target IRef on PLL */
5480 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5481 reg_val &= 0x00ffffff;
5482 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5483
5484 /* Disable fast lock */
5485 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5486
5487 /* Set idtafcrecal before PLL is enabled */
5488 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5489 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5490 mdiv |= ((bestn << DPIO_N_SHIFT));
5491 mdiv |= (1 << DPIO_K_SHIFT);
5492
5493 /*
5494 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5495 * but we don't support that).
5496 * Note: don't use the DAC post divider as it seems unstable.
5497 */
5498 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5499 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5500
5501 mdiv |= DPIO_ENABLE_CALIBRATION;
5502 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5503
5504 /* Set HBR and RBR LPF coefficients */
5505 if (crtc->config.port_clock == 162000 ||
5506 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5507 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5509 0x009f0003);
5510 else
5511 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5512 0x00d0000f);
5513
5514 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5515 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5516 /* Use SSC source */
5517 if (pipe == PIPE_A)
5518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5519 0x0df40000);
5520 else
5521 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5522 0x0df70000);
5523 } else { /* HDMI or VGA */
5524 /* Use bend source */
5525 if (pipe == PIPE_A)
5526 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5527 0x0df70000);
5528 else
5529 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5530 0x0df40000);
5531 }
5532
5533 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5534 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5535 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5536 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5537 coreclk |= 0x01000000;
5538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5539
5540 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5541 mutex_unlock(&dev_priv->dpio_lock);
5542 }
5543
5544 static void chv_update_pll(struct intel_crtc *crtc)
5545 {
5546 struct drm_device *dev = crtc->base.dev;
5547 struct drm_i915_private *dev_priv = dev->dev_private;
5548 int pipe = crtc->pipe;
5549 int dpll_reg = DPLL(crtc->pipe);
5550 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5551 u32 loopfilter, intcoeff;
5552 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5553 int refclk;
5554
5555 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5556 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5557 DPLL_VCO_ENABLE;
5558 if (pipe != PIPE_A)
5559 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5560
5561 crtc->config.dpll_hw_state.dpll_md =
5562 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5563
5564 bestn = crtc->config.dpll.n;
5565 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5566 bestm1 = crtc->config.dpll.m1;
5567 bestm2 = crtc->config.dpll.m2 >> 22;
5568 bestp1 = crtc->config.dpll.p1;
5569 bestp2 = crtc->config.dpll.p2;
5570
5571 /*
5572 * Enable Refclk and SSC
5573 */
5574 I915_WRITE(dpll_reg,
5575 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5576
5577 mutex_lock(&dev_priv->dpio_lock);
5578
5579 /* p1 and p2 divider */
5580 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5581 5 << DPIO_CHV_S1_DIV_SHIFT |
5582 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5583 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5584 1 << DPIO_CHV_K_DIV_SHIFT);
5585
5586 /* Feedback post-divider - m2 */
5587 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5588
5589 /* Feedback refclk divider - n and m1 */
5590 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5591 DPIO_CHV_M1_DIV_BY_2 |
5592 1 << DPIO_CHV_N_DIV_SHIFT);
5593
5594 /* M2 fraction division */
5595 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5596
5597 /* M2 fraction division enable */
5598 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5599 DPIO_CHV_FRAC_DIV_EN |
5600 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5601
5602 /* Loop filter */
5603 refclk = i9xx_get_refclk(&crtc->base, 0);
5604 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5605 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5606 if (refclk == 100000)
5607 intcoeff = 11;
5608 else if (refclk == 38400)
5609 intcoeff = 10;
5610 else
5611 intcoeff = 9;
5612 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5613 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5614
5615 /* AFC Recal */
5616 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5617 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5618 DPIO_AFC_RECAL);
5619
5620 mutex_unlock(&dev_priv->dpio_lock);
5621 }
5622
5623 static void i9xx_update_pll(struct intel_crtc *crtc,
5624 intel_clock_t *reduced_clock,
5625 int num_connectors)
5626 {
5627 struct drm_device *dev = crtc->base.dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 u32 dpll;
5630 bool is_sdvo;
5631 struct dpll *clock = &crtc->config.dpll;
5632
5633 i9xx_update_pll_dividers(crtc, reduced_clock);
5634
5635 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5636 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5637
5638 dpll = DPLL_VGA_MODE_DIS;
5639
5640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5641 dpll |= DPLLB_MODE_LVDS;
5642 else
5643 dpll |= DPLLB_MODE_DAC_SERIAL;
5644
5645 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5646 dpll |= (crtc->config.pixel_multiplier - 1)
5647 << SDVO_MULTIPLIER_SHIFT_HIRES;
5648 }
5649
5650 if (is_sdvo)
5651 dpll |= DPLL_SDVO_HIGH_SPEED;
5652
5653 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5654 dpll |= DPLL_SDVO_HIGH_SPEED;
5655
5656 /* compute bitmask from p1 value */
5657 if (IS_PINEVIEW(dev))
5658 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5659 else {
5660 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5661 if (IS_G4X(dev) && reduced_clock)
5662 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5663 }
5664 switch (clock->p2) {
5665 case 5:
5666 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5667 break;
5668 case 7:
5669 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5670 break;
5671 case 10:
5672 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5673 break;
5674 case 14:
5675 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5676 break;
5677 }
5678 if (INTEL_INFO(dev)->gen >= 4)
5679 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5680
5681 if (crtc->config.sdvo_tv_clock)
5682 dpll |= PLL_REF_INPUT_TVCLKINBC;
5683 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5684 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5685 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5686 else
5687 dpll |= PLL_REF_INPUT_DREFCLK;
5688
5689 dpll |= DPLL_VCO_ENABLE;
5690 crtc->config.dpll_hw_state.dpll = dpll;
5691
5692 if (INTEL_INFO(dev)->gen >= 4) {
5693 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5694 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5695 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5696 }
5697 }
5698
5699 static void i8xx_update_pll(struct intel_crtc *crtc,
5700 intel_clock_t *reduced_clock,
5701 int num_connectors)
5702 {
5703 struct drm_device *dev = crtc->base.dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
5705 u32 dpll;
5706 struct dpll *clock = &crtc->config.dpll;
5707
5708 i9xx_update_pll_dividers(crtc, reduced_clock);
5709
5710 dpll = DPLL_VGA_MODE_DIS;
5711
5712 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5713 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5714 } else {
5715 if (clock->p1 == 2)
5716 dpll |= PLL_P1_DIVIDE_BY_TWO;
5717 else
5718 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5719 if (clock->p2 == 4)
5720 dpll |= PLL_P2_DIVIDE_BY_4;
5721 }
5722
5723 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5724 dpll |= DPLL_DVO_2X_MODE;
5725
5726 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5727 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5728 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5729 else
5730 dpll |= PLL_REF_INPUT_DREFCLK;
5731
5732 dpll |= DPLL_VCO_ENABLE;
5733 crtc->config.dpll_hw_state.dpll = dpll;
5734 }
5735
5736 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5737 {
5738 struct drm_device *dev = intel_crtc->base.dev;
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740 enum pipe pipe = intel_crtc->pipe;
5741 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5742 struct drm_display_mode *adjusted_mode =
5743 &intel_crtc->config.adjusted_mode;
5744 uint32_t crtc_vtotal, crtc_vblank_end;
5745 int vsyncshift = 0;
5746
5747 /* We need to be careful not to changed the adjusted mode, for otherwise
5748 * the hw state checker will get angry at the mismatch. */
5749 crtc_vtotal = adjusted_mode->crtc_vtotal;
5750 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5751
5752 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5753 /* the chip adds 2 halflines automatically */
5754 crtc_vtotal -= 1;
5755 crtc_vblank_end -= 1;
5756
5757 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5758 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5759 else
5760 vsyncshift = adjusted_mode->crtc_hsync_start -
5761 adjusted_mode->crtc_htotal / 2;
5762 if (vsyncshift < 0)
5763 vsyncshift += adjusted_mode->crtc_htotal;
5764 }
5765
5766 if (INTEL_INFO(dev)->gen > 3)
5767 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5768
5769 I915_WRITE(HTOTAL(cpu_transcoder),
5770 (adjusted_mode->crtc_hdisplay - 1) |
5771 ((adjusted_mode->crtc_htotal - 1) << 16));
5772 I915_WRITE(HBLANK(cpu_transcoder),
5773 (adjusted_mode->crtc_hblank_start - 1) |
5774 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5775 I915_WRITE(HSYNC(cpu_transcoder),
5776 (adjusted_mode->crtc_hsync_start - 1) |
5777 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5778
5779 I915_WRITE(VTOTAL(cpu_transcoder),
5780 (adjusted_mode->crtc_vdisplay - 1) |
5781 ((crtc_vtotal - 1) << 16));
5782 I915_WRITE(VBLANK(cpu_transcoder),
5783 (adjusted_mode->crtc_vblank_start - 1) |
5784 ((crtc_vblank_end - 1) << 16));
5785 I915_WRITE(VSYNC(cpu_transcoder),
5786 (adjusted_mode->crtc_vsync_start - 1) |
5787 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5788
5789 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5790 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5791 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5792 * bits. */
5793 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5794 (pipe == PIPE_B || pipe == PIPE_C))
5795 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5796
5797 /* pipesrc controls the size that is scaled from, which should
5798 * always be the user's requested size.
5799 */
5800 I915_WRITE(PIPESRC(pipe),
5801 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5802 (intel_crtc->config.pipe_src_h - 1));
5803 }
5804
5805 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5806 struct intel_crtc_config *pipe_config)
5807 {
5808 struct drm_device *dev = crtc->base.dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5811 uint32_t tmp;
5812
5813 tmp = I915_READ(HTOTAL(cpu_transcoder));
5814 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5815 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5816 tmp = I915_READ(HBLANK(cpu_transcoder));
5817 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5818 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5819 tmp = I915_READ(HSYNC(cpu_transcoder));
5820 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5821 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5822
5823 tmp = I915_READ(VTOTAL(cpu_transcoder));
5824 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5825 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5826 tmp = I915_READ(VBLANK(cpu_transcoder));
5827 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5828 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5829 tmp = I915_READ(VSYNC(cpu_transcoder));
5830 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5831 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5832
5833 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5834 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5835 pipe_config->adjusted_mode.crtc_vtotal += 1;
5836 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5837 }
5838
5839 tmp = I915_READ(PIPESRC(crtc->pipe));
5840 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5841 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5842
5843 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5844 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5845 }
5846
5847 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5848 struct intel_crtc_config *pipe_config)
5849 {
5850 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5851 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5852 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5853 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5854
5855 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5856 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5857 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5858 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5859
5860 mode->flags = pipe_config->adjusted_mode.flags;
5861
5862 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5863 mode->flags |= pipe_config->adjusted_mode.flags;
5864 }
5865
5866 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5867 {
5868 struct drm_device *dev = intel_crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 uint32_t pipeconf;
5871
5872 pipeconf = 0;
5873
5874 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5875 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5876 pipeconf |= PIPECONF_ENABLE;
5877
5878 if (intel_crtc->config.double_wide)
5879 pipeconf |= PIPECONF_DOUBLE_WIDE;
5880
5881 /* only g4x and later have fancy bpc/dither controls */
5882 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5883 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5884 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5885 pipeconf |= PIPECONF_DITHER_EN |
5886 PIPECONF_DITHER_TYPE_SP;
5887
5888 switch (intel_crtc->config.pipe_bpp) {
5889 case 18:
5890 pipeconf |= PIPECONF_6BPC;
5891 break;
5892 case 24:
5893 pipeconf |= PIPECONF_8BPC;
5894 break;
5895 case 30:
5896 pipeconf |= PIPECONF_10BPC;
5897 break;
5898 default:
5899 /* Case prevented by intel_choose_pipe_bpp_dither. */
5900 BUG();
5901 }
5902 }
5903
5904 if (HAS_PIPE_CXSR(dev)) {
5905 if (intel_crtc->lowfreq_avail) {
5906 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5907 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5908 } else {
5909 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5910 }
5911 }
5912
5913 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5914 if (INTEL_INFO(dev)->gen < 4 ||
5915 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5916 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5917 else
5918 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5919 } else
5920 pipeconf |= PIPECONF_PROGRESSIVE;
5921
5922 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5923 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5924
5925 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5926 POSTING_READ(PIPECONF(intel_crtc->pipe));
5927 }
5928
5929 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5930 int x, int y,
5931 struct drm_framebuffer *fb)
5932 {
5933 struct drm_device *dev = crtc->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936 int refclk, num_connectors = 0;
5937 intel_clock_t clock, reduced_clock;
5938 bool ok, has_reduced_clock = false;
5939 bool is_lvds = false, is_dsi = false;
5940 struct intel_encoder *encoder;
5941 const intel_limit_t *limit;
5942
5943 for_each_encoder_on_crtc(dev, crtc, encoder) {
5944 switch (encoder->type) {
5945 case INTEL_OUTPUT_LVDS:
5946 is_lvds = true;
5947 break;
5948 case INTEL_OUTPUT_DSI:
5949 is_dsi = true;
5950 break;
5951 }
5952
5953 num_connectors++;
5954 }
5955
5956 if (is_dsi)
5957 return 0;
5958
5959 if (!intel_crtc->config.clock_set) {
5960 refclk = i9xx_get_refclk(crtc, num_connectors);
5961
5962 /*
5963 * Returns a set of divisors for the desired target clock with
5964 * the given refclk, or FALSE. The returned values represent
5965 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5966 * 2) / p1 / p2.
5967 */
5968 limit = intel_limit(crtc, refclk);
5969 ok = dev_priv->display.find_dpll(limit, crtc,
5970 intel_crtc->config.port_clock,
5971 refclk, NULL, &clock);
5972 if (!ok) {
5973 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5974 return -EINVAL;
5975 }
5976
5977 if (is_lvds && dev_priv->lvds_downclock_avail) {
5978 /*
5979 * Ensure we match the reduced clock's P to the target
5980 * clock. If the clocks don't match, we can't switch
5981 * the display clock by using the FP0/FP1. In such case
5982 * we will disable the LVDS downclock feature.
5983 */
5984 has_reduced_clock =
5985 dev_priv->display.find_dpll(limit, crtc,
5986 dev_priv->lvds_downclock,
5987 refclk, &clock,
5988 &reduced_clock);
5989 }
5990 /* Compat-code for transition, will disappear. */
5991 intel_crtc->config.dpll.n = clock.n;
5992 intel_crtc->config.dpll.m1 = clock.m1;
5993 intel_crtc->config.dpll.m2 = clock.m2;
5994 intel_crtc->config.dpll.p1 = clock.p1;
5995 intel_crtc->config.dpll.p2 = clock.p2;
5996 }
5997
5998 if (IS_GEN2(dev)) {
5999 i8xx_update_pll(intel_crtc,
6000 has_reduced_clock ? &reduced_clock : NULL,
6001 num_connectors);
6002 } else if (IS_CHERRYVIEW(dev)) {
6003 chv_update_pll(intel_crtc);
6004 } else if (IS_VALLEYVIEW(dev)) {
6005 vlv_update_pll(intel_crtc);
6006 } else {
6007 i9xx_update_pll(intel_crtc,
6008 has_reduced_clock ? &reduced_clock : NULL,
6009 num_connectors);
6010 }
6011
6012 return 0;
6013 }
6014
6015 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6016 struct intel_crtc_config *pipe_config)
6017 {
6018 struct drm_device *dev = crtc->base.dev;
6019 struct drm_i915_private *dev_priv = dev->dev_private;
6020 uint32_t tmp;
6021
6022 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6023 return;
6024
6025 tmp = I915_READ(PFIT_CONTROL);
6026 if (!(tmp & PFIT_ENABLE))
6027 return;
6028
6029 /* Check whether the pfit is attached to our pipe. */
6030 if (INTEL_INFO(dev)->gen < 4) {
6031 if (crtc->pipe != PIPE_B)
6032 return;
6033 } else {
6034 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6035 return;
6036 }
6037
6038 pipe_config->gmch_pfit.control = tmp;
6039 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6040 if (INTEL_INFO(dev)->gen < 5)
6041 pipe_config->gmch_pfit.lvds_border_bits =
6042 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6043 }
6044
6045 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6046 struct intel_crtc_config *pipe_config)
6047 {
6048 struct drm_device *dev = crtc->base.dev;
6049 struct drm_i915_private *dev_priv = dev->dev_private;
6050 int pipe = pipe_config->cpu_transcoder;
6051 intel_clock_t clock;
6052 u32 mdiv;
6053 int refclk = 100000;
6054
6055 mutex_lock(&dev_priv->dpio_lock);
6056 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6057 mutex_unlock(&dev_priv->dpio_lock);
6058
6059 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6060 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6061 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6062 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6063 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6064
6065 vlv_clock(refclk, &clock);
6066
6067 /* clock.dot is the fast clock */
6068 pipe_config->port_clock = clock.dot / 5;
6069 }
6070
6071 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6072 struct intel_plane_config *plane_config)
6073 {
6074 struct drm_device *dev = crtc->base.dev;
6075 struct drm_i915_private *dev_priv = dev->dev_private;
6076 u32 val, base, offset;
6077 int pipe = crtc->pipe, plane = crtc->plane;
6078 int fourcc, pixel_format;
6079 int aligned_height;
6080
6081 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6082 if (!crtc->base.primary->fb) {
6083 DRM_DEBUG_KMS("failed to alloc fb\n");
6084 return;
6085 }
6086
6087 val = I915_READ(DSPCNTR(plane));
6088
6089 if (INTEL_INFO(dev)->gen >= 4)
6090 if (val & DISPPLANE_TILED)
6091 plane_config->tiled = true;
6092
6093 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6094 fourcc = intel_format_to_fourcc(pixel_format);
6095 crtc->base.primary->fb->pixel_format = fourcc;
6096 crtc->base.primary->fb->bits_per_pixel =
6097 drm_format_plane_cpp(fourcc, 0) * 8;
6098
6099 if (INTEL_INFO(dev)->gen >= 4) {
6100 if (plane_config->tiled)
6101 offset = I915_READ(DSPTILEOFF(plane));
6102 else
6103 offset = I915_READ(DSPLINOFF(plane));
6104 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6105 } else {
6106 base = I915_READ(DSPADDR(plane));
6107 }
6108 plane_config->base = base;
6109
6110 val = I915_READ(PIPESRC(pipe));
6111 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6112 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6113
6114 val = I915_READ(DSPSTRIDE(pipe));
6115 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6116
6117 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6118 plane_config->tiled);
6119
6120 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6121 aligned_height, PAGE_SIZE);
6122
6123 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6124 pipe, plane, crtc->base.primary->fb->width,
6125 crtc->base.primary->fb->height,
6126 crtc->base.primary->fb->bits_per_pixel, base,
6127 crtc->base.primary->fb->pitches[0],
6128 plane_config->size);
6129
6130 }
6131
6132 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6133 struct intel_crtc_config *pipe_config)
6134 {
6135 struct drm_device *dev = crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 int pipe = pipe_config->cpu_transcoder;
6138 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6139 intel_clock_t clock;
6140 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6141 int refclk = 100000;
6142
6143 mutex_lock(&dev_priv->dpio_lock);
6144 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6145 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6146 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6147 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6148 mutex_unlock(&dev_priv->dpio_lock);
6149
6150 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6151 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6152 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6153 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6154 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6155
6156 chv_clock(refclk, &clock);
6157
6158 /* clock.dot is the fast clock */
6159 pipe_config->port_clock = clock.dot / 5;
6160 }
6161
6162 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6163 struct intel_crtc_config *pipe_config)
6164 {
6165 struct drm_device *dev = crtc->base.dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 uint32_t tmp;
6168
6169 if (!intel_display_power_enabled(dev_priv,
6170 POWER_DOMAIN_PIPE(crtc->pipe)))
6171 return false;
6172
6173 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6174 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6175
6176 tmp = I915_READ(PIPECONF(crtc->pipe));
6177 if (!(tmp & PIPECONF_ENABLE))
6178 return false;
6179
6180 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6181 switch (tmp & PIPECONF_BPC_MASK) {
6182 case PIPECONF_6BPC:
6183 pipe_config->pipe_bpp = 18;
6184 break;
6185 case PIPECONF_8BPC:
6186 pipe_config->pipe_bpp = 24;
6187 break;
6188 case PIPECONF_10BPC:
6189 pipe_config->pipe_bpp = 30;
6190 break;
6191 default:
6192 break;
6193 }
6194 }
6195
6196 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6197 pipe_config->limited_color_range = true;
6198
6199 if (INTEL_INFO(dev)->gen < 4)
6200 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6201
6202 intel_get_pipe_timings(crtc, pipe_config);
6203
6204 i9xx_get_pfit_config(crtc, pipe_config);
6205
6206 if (INTEL_INFO(dev)->gen >= 4) {
6207 tmp = I915_READ(DPLL_MD(crtc->pipe));
6208 pipe_config->pixel_multiplier =
6209 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6210 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6211 pipe_config->dpll_hw_state.dpll_md = tmp;
6212 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6213 tmp = I915_READ(DPLL(crtc->pipe));
6214 pipe_config->pixel_multiplier =
6215 ((tmp & SDVO_MULTIPLIER_MASK)
6216 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6217 } else {
6218 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6219 * port and will be fixed up in the encoder->get_config
6220 * function. */
6221 pipe_config->pixel_multiplier = 1;
6222 }
6223 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6224 if (!IS_VALLEYVIEW(dev)) {
6225 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6226 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6227 } else {
6228 /* Mask out read-only status bits. */
6229 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6230 DPLL_PORTC_READY_MASK |
6231 DPLL_PORTB_READY_MASK);
6232 }
6233
6234 if (IS_CHERRYVIEW(dev))
6235 chv_crtc_clock_get(crtc, pipe_config);
6236 else if (IS_VALLEYVIEW(dev))
6237 vlv_crtc_clock_get(crtc, pipe_config);
6238 else
6239 i9xx_crtc_clock_get(crtc, pipe_config);
6240
6241 return true;
6242 }
6243
6244 static void ironlake_init_pch_refclk(struct drm_device *dev)
6245 {
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 struct drm_mode_config *mode_config = &dev->mode_config;
6248 struct intel_encoder *encoder;
6249 u32 val, final;
6250 bool has_lvds = false;
6251 bool has_cpu_edp = false;
6252 bool has_panel = false;
6253 bool has_ck505 = false;
6254 bool can_ssc = false;
6255
6256 /* We need to take the global config into account */
6257 list_for_each_entry(encoder, &mode_config->encoder_list,
6258 base.head) {
6259 switch (encoder->type) {
6260 case INTEL_OUTPUT_LVDS:
6261 has_panel = true;
6262 has_lvds = true;
6263 break;
6264 case INTEL_OUTPUT_EDP:
6265 has_panel = true;
6266 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6267 has_cpu_edp = true;
6268 break;
6269 }
6270 }
6271
6272 if (HAS_PCH_IBX(dev)) {
6273 has_ck505 = dev_priv->vbt.display_clock_mode;
6274 can_ssc = has_ck505;
6275 } else {
6276 has_ck505 = false;
6277 can_ssc = true;
6278 }
6279
6280 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6281 has_panel, has_lvds, has_ck505);
6282
6283 /* Ironlake: try to setup display ref clock before DPLL
6284 * enabling. This is only under driver's control after
6285 * PCH B stepping, previous chipset stepping should be
6286 * ignoring this setting.
6287 */
6288 val = I915_READ(PCH_DREF_CONTROL);
6289
6290 /* As we must carefully and slowly disable/enable each source in turn,
6291 * compute the final state we want first and check if we need to
6292 * make any changes at all.
6293 */
6294 final = val;
6295 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6296 if (has_ck505)
6297 final |= DREF_NONSPREAD_CK505_ENABLE;
6298 else
6299 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6300
6301 final &= ~DREF_SSC_SOURCE_MASK;
6302 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6303 final &= ~DREF_SSC1_ENABLE;
6304
6305 if (has_panel) {
6306 final |= DREF_SSC_SOURCE_ENABLE;
6307
6308 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6309 final |= DREF_SSC1_ENABLE;
6310
6311 if (has_cpu_edp) {
6312 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6313 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6314 else
6315 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6316 } else
6317 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6318 } else {
6319 final |= DREF_SSC_SOURCE_DISABLE;
6320 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6321 }
6322
6323 if (final == val)
6324 return;
6325
6326 /* Always enable nonspread source */
6327 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6328
6329 if (has_ck505)
6330 val |= DREF_NONSPREAD_CK505_ENABLE;
6331 else
6332 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6333
6334 if (has_panel) {
6335 val &= ~DREF_SSC_SOURCE_MASK;
6336 val |= DREF_SSC_SOURCE_ENABLE;
6337
6338 /* SSC must be turned on before enabling the CPU output */
6339 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6340 DRM_DEBUG_KMS("Using SSC on panel\n");
6341 val |= DREF_SSC1_ENABLE;
6342 } else
6343 val &= ~DREF_SSC1_ENABLE;
6344
6345 /* Get SSC going before enabling the outputs */
6346 I915_WRITE(PCH_DREF_CONTROL, val);
6347 POSTING_READ(PCH_DREF_CONTROL);
6348 udelay(200);
6349
6350 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6351
6352 /* Enable CPU source on CPU attached eDP */
6353 if (has_cpu_edp) {
6354 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6355 DRM_DEBUG_KMS("Using SSC on eDP\n");
6356 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6357 } else
6358 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6359 } else
6360 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6361
6362 I915_WRITE(PCH_DREF_CONTROL, val);
6363 POSTING_READ(PCH_DREF_CONTROL);
6364 udelay(200);
6365 } else {
6366 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6367
6368 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6369
6370 /* Turn off CPU output */
6371 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6372
6373 I915_WRITE(PCH_DREF_CONTROL, val);
6374 POSTING_READ(PCH_DREF_CONTROL);
6375 udelay(200);
6376
6377 /* Turn off the SSC source */
6378 val &= ~DREF_SSC_SOURCE_MASK;
6379 val |= DREF_SSC_SOURCE_DISABLE;
6380
6381 /* Turn off SSC1 */
6382 val &= ~DREF_SSC1_ENABLE;
6383
6384 I915_WRITE(PCH_DREF_CONTROL, val);
6385 POSTING_READ(PCH_DREF_CONTROL);
6386 udelay(200);
6387 }
6388
6389 BUG_ON(val != final);
6390 }
6391
6392 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6393 {
6394 uint32_t tmp;
6395
6396 tmp = I915_READ(SOUTH_CHICKEN2);
6397 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6398 I915_WRITE(SOUTH_CHICKEN2, tmp);
6399
6400 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6401 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6402 DRM_ERROR("FDI mPHY reset assert timeout\n");
6403
6404 tmp = I915_READ(SOUTH_CHICKEN2);
6405 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6406 I915_WRITE(SOUTH_CHICKEN2, tmp);
6407
6408 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6409 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6410 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6411 }
6412
6413 /* WaMPhyProgramming:hsw */
6414 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6415 {
6416 uint32_t tmp;
6417
6418 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6419 tmp &= ~(0xFF << 24);
6420 tmp |= (0x12 << 24);
6421 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6422
6423 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6424 tmp |= (1 << 11);
6425 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6426
6427 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6428 tmp |= (1 << 11);
6429 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6430
6431 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6432 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6433 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6434
6435 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6436 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6437 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6438
6439 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6440 tmp &= ~(7 << 13);
6441 tmp |= (5 << 13);
6442 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6443
6444 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6445 tmp &= ~(7 << 13);
6446 tmp |= (5 << 13);
6447 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6448
6449 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6450 tmp &= ~0xFF;
6451 tmp |= 0x1C;
6452 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6453
6454 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6455 tmp &= ~0xFF;
6456 tmp |= 0x1C;
6457 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6458
6459 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6460 tmp &= ~(0xFF << 16);
6461 tmp |= (0x1C << 16);
6462 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6463
6464 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6465 tmp &= ~(0xFF << 16);
6466 tmp |= (0x1C << 16);
6467 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6468
6469 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6470 tmp |= (1 << 27);
6471 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6472
6473 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6474 tmp |= (1 << 27);
6475 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6476
6477 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6478 tmp &= ~(0xF << 28);
6479 tmp |= (4 << 28);
6480 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6481
6482 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6483 tmp &= ~(0xF << 28);
6484 tmp |= (4 << 28);
6485 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6486 }
6487
6488 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6489 * Programming" based on the parameters passed:
6490 * - Sequence to enable CLKOUT_DP
6491 * - Sequence to enable CLKOUT_DP without spread
6492 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6493 */
6494 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6495 bool with_fdi)
6496 {
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 uint32_t reg, tmp;
6499
6500 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6501 with_spread = true;
6502 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6503 with_fdi, "LP PCH doesn't have FDI\n"))
6504 with_fdi = false;
6505
6506 mutex_lock(&dev_priv->dpio_lock);
6507
6508 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6509 tmp &= ~SBI_SSCCTL_DISABLE;
6510 tmp |= SBI_SSCCTL_PATHALT;
6511 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6512
6513 udelay(24);
6514
6515 if (with_spread) {
6516 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6517 tmp &= ~SBI_SSCCTL_PATHALT;
6518 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6519
6520 if (with_fdi) {
6521 lpt_reset_fdi_mphy(dev_priv);
6522 lpt_program_fdi_mphy(dev_priv);
6523 }
6524 }
6525
6526 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6527 SBI_GEN0 : SBI_DBUFF0;
6528 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6529 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6530 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6531
6532 mutex_unlock(&dev_priv->dpio_lock);
6533 }
6534
6535 /* Sequence to disable CLKOUT_DP */
6536 static void lpt_disable_clkout_dp(struct drm_device *dev)
6537 {
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539 uint32_t reg, tmp;
6540
6541 mutex_lock(&dev_priv->dpio_lock);
6542
6543 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6544 SBI_GEN0 : SBI_DBUFF0;
6545 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6546 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6547 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6548
6549 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6550 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6551 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6552 tmp |= SBI_SSCCTL_PATHALT;
6553 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6554 udelay(32);
6555 }
6556 tmp |= SBI_SSCCTL_DISABLE;
6557 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6558 }
6559
6560 mutex_unlock(&dev_priv->dpio_lock);
6561 }
6562
6563 static void lpt_init_pch_refclk(struct drm_device *dev)
6564 {
6565 struct drm_mode_config *mode_config = &dev->mode_config;
6566 struct intel_encoder *encoder;
6567 bool has_vga = false;
6568
6569 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6570 switch (encoder->type) {
6571 case INTEL_OUTPUT_ANALOG:
6572 has_vga = true;
6573 break;
6574 }
6575 }
6576
6577 if (has_vga)
6578 lpt_enable_clkout_dp(dev, true, true);
6579 else
6580 lpt_disable_clkout_dp(dev);
6581 }
6582
6583 /*
6584 * Initialize reference clocks when the driver loads
6585 */
6586 void intel_init_pch_refclk(struct drm_device *dev)
6587 {
6588 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6589 ironlake_init_pch_refclk(dev);
6590 else if (HAS_PCH_LPT(dev))
6591 lpt_init_pch_refclk(dev);
6592 }
6593
6594 static int ironlake_get_refclk(struct drm_crtc *crtc)
6595 {
6596 struct drm_device *dev = crtc->dev;
6597 struct drm_i915_private *dev_priv = dev->dev_private;
6598 struct intel_encoder *encoder;
6599 int num_connectors = 0;
6600 bool is_lvds = false;
6601
6602 for_each_encoder_on_crtc(dev, crtc, encoder) {
6603 switch (encoder->type) {
6604 case INTEL_OUTPUT_LVDS:
6605 is_lvds = true;
6606 break;
6607 }
6608 num_connectors++;
6609 }
6610
6611 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6612 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6613 dev_priv->vbt.lvds_ssc_freq);
6614 return dev_priv->vbt.lvds_ssc_freq;
6615 }
6616
6617 return 120000;
6618 }
6619
6620 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6621 {
6622 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6624 int pipe = intel_crtc->pipe;
6625 uint32_t val;
6626
6627 val = 0;
6628
6629 switch (intel_crtc->config.pipe_bpp) {
6630 case 18:
6631 val |= PIPECONF_6BPC;
6632 break;
6633 case 24:
6634 val |= PIPECONF_8BPC;
6635 break;
6636 case 30:
6637 val |= PIPECONF_10BPC;
6638 break;
6639 case 36:
6640 val |= PIPECONF_12BPC;
6641 break;
6642 default:
6643 /* Case prevented by intel_choose_pipe_bpp_dither. */
6644 BUG();
6645 }
6646
6647 if (intel_crtc->config.dither)
6648 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6649
6650 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6651 val |= PIPECONF_INTERLACED_ILK;
6652 else
6653 val |= PIPECONF_PROGRESSIVE;
6654
6655 if (intel_crtc->config.limited_color_range)
6656 val |= PIPECONF_COLOR_RANGE_SELECT;
6657
6658 I915_WRITE(PIPECONF(pipe), val);
6659 POSTING_READ(PIPECONF(pipe));
6660 }
6661
6662 /*
6663 * Set up the pipe CSC unit.
6664 *
6665 * Currently only full range RGB to limited range RGB conversion
6666 * is supported, but eventually this should handle various
6667 * RGB<->YCbCr scenarios as well.
6668 */
6669 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6670 {
6671 struct drm_device *dev = crtc->dev;
6672 struct drm_i915_private *dev_priv = dev->dev_private;
6673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6674 int pipe = intel_crtc->pipe;
6675 uint16_t coeff = 0x7800; /* 1.0 */
6676
6677 /*
6678 * TODO: Check what kind of values actually come out of the pipe
6679 * with these coeff/postoff values and adjust to get the best
6680 * accuracy. Perhaps we even need to take the bpc value into
6681 * consideration.
6682 */
6683
6684 if (intel_crtc->config.limited_color_range)
6685 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6686
6687 /*
6688 * GY/GU and RY/RU should be the other way around according
6689 * to BSpec, but reality doesn't agree. Just set them up in
6690 * a way that results in the correct picture.
6691 */
6692 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6693 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6694
6695 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6696 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6697
6698 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6699 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6700
6701 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6702 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6703 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6704
6705 if (INTEL_INFO(dev)->gen > 6) {
6706 uint16_t postoff = 0;
6707
6708 if (intel_crtc->config.limited_color_range)
6709 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6710
6711 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6712 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6713 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6714
6715 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6716 } else {
6717 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6718
6719 if (intel_crtc->config.limited_color_range)
6720 mode |= CSC_BLACK_SCREEN_OFFSET;
6721
6722 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6723 }
6724 }
6725
6726 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6727 {
6728 struct drm_device *dev = crtc->dev;
6729 struct drm_i915_private *dev_priv = dev->dev_private;
6730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6731 enum pipe pipe = intel_crtc->pipe;
6732 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6733 uint32_t val;
6734
6735 val = 0;
6736
6737 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6738 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6739
6740 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6741 val |= PIPECONF_INTERLACED_ILK;
6742 else
6743 val |= PIPECONF_PROGRESSIVE;
6744
6745 I915_WRITE(PIPECONF(cpu_transcoder), val);
6746 POSTING_READ(PIPECONF(cpu_transcoder));
6747
6748 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6749 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6750
6751 if (IS_BROADWELL(dev)) {
6752 val = 0;
6753
6754 switch (intel_crtc->config.pipe_bpp) {
6755 case 18:
6756 val |= PIPEMISC_DITHER_6_BPC;
6757 break;
6758 case 24:
6759 val |= PIPEMISC_DITHER_8_BPC;
6760 break;
6761 case 30:
6762 val |= PIPEMISC_DITHER_10_BPC;
6763 break;
6764 case 36:
6765 val |= PIPEMISC_DITHER_12_BPC;
6766 break;
6767 default:
6768 /* Case prevented by pipe_config_set_bpp. */
6769 BUG();
6770 }
6771
6772 if (intel_crtc->config.dither)
6773 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6774
6775 I915_WRITE(PIPEMISC(pipe), val);
6776 }
6777 }
6778
6779 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6780 intel_clock_t *clock,
6781 bool *has_reduced_clock,
6782 intel_clock_t *reduced_clock)
6783 {
6784 struct drm_device *dev = crtc->dev;
6785 struct drm_i915_private *dev_priv = dev->dev_private;
6786 struct intel_encoder *intel_encoder;
6787 int refclk;
6788 const intel_limit_t *limit;
6789 bool ret, is_lvds = false;
6790
6791 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6792 switch (intel_encoder->type) {
6793 case INTEL_OUTPUT_LVDS:
6794 is_lvds = true;
6795 break;
6796 }
6797 }
6798
6799 refclk = ironlake_get_refclk(crtc);
6800
6801 /*
6802 * Returns a set of divisors for the desired target clock with the given
6803 * refclk, or FALSE. The returned values represent the clock equation:
6804 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6805 */
6806 limit = intel_limit(crtc, refclk);
6807 ret = dev_priv->display.find_dpll(limit, crtc,
6808 to_intel_crtc(crtc)->config.port_clock,
6809 refclk, NULL, clock);
6810 if (!ret)
6811 return false;
6812
6813 if (is_lvds && dev_priv->lvds_downclock_avail) {
6814 /*
6815 * Ensure we match the reduced clock's P to the target clock.
6816 * If the clocks don't match, we can't switch the display clock
6817 * by using the FP0/FP1. In such case we will disable the LVDS
6818 * downclock feature.
6819 */
6820 *has_reduced_clock =
6821 dev_priv->display.find_dpll(limit, crtc,
6822 dev_priv->lvds_downclock,
6823 refclk, clock,
6824 reduced_clock);
6825 }
6826
6827 return true;
6828 }
6829
6830 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6831 {
6832 /*
6833 * Account for spread spectrum to avoid
6834 * oversubscribing the link. Max center spread
6835 * is 2.5%; use 5% for safety's sake.
6836 */
6837 u32 bps = target_clock * bpp * 21 / 20;
6838 return DIV_ROUND_UP(bps, link_bw * 8);
6839 }
6840
6841 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6842 {
6843 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6844 }
6845
6846 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6847 u32 *fp,
6848 intel_clock_t *reduced_clock, u32 *fp2)
6849 {
6850 struct drm_crtc *crtc = &intel_crtc->base;
6851 struct drm_device *dev = crtc->dev;
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 struct intel_encoder *intel_encoder;
6854 uint32_t dpll;
6855 int factor, num_connectors = 0;
6856 bool is_lvds = false, is_sdvo = false;
6857
6858 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6859 switch (intel_encoder->type) {
6860 case INTEL_OUTPUT_LVDS:
6861 is_lvds = true;
6862 break;
6863 case INTEL_OUTPUT_SDVO:
6864 case INTEL_OUTPUT_HDMI:
6865 is_sdvo = true;
6866 break;
6867 }
6868
6869 num_connectors++;
6870 }
6871
6872 /* Enable autotuning of the PLL clock (if permissible) */
6873 factor = 21;
6874 if (is_lvds) {
6875 if ((intel_panel_use_ssc(dev_priv) &&
6876 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6877 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6878 factor = 25;
6879 } else if (intel_crtc->config.sdvo_tv_clock)
6880 factor = 20;
6881
6882 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6883 *fp |= FP_CB_TUNE;
6884
6885 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6886 *fp2 |= FP_CB_TUNE;
6887
6888 dpll = 0;
6889
6890 if (is_lvds)
6891 dpll |= DPLLB_MODE_LVDS;
6892 else
6893 dpll |= DPLLB_MODE_DAC_SERIAL;
6894
6895 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6896 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6897
6898 if (is_sdvo)
6899 dpll |= DPLL_SDVO_HIGH_SPEED;
6900 if (intel_crtc->config.has_dp_encoder)
6901 dpll |= DPLL_SDVO_HIGH_SPEED;
6902
6903 /* compute bitmask from p1 value */
6904 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6905 /* also FPA1 */
6906 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6907
6908 switch (intel_crtc->config.dpll.p2) {
6909 case 5:
6910 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6911 break;
6912 case 7:
6913 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6914 break;
6915 case 10:
6916 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6917 break;
6918 case 14:
6919 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6920 break;
6921 }
6922
6923 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6924 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6925 else
6926 dpll |= PLL_REF_INPUT_DREFCLK;
6927
6928 return dpll | DPLL_VCO_ENABLE;
6929 }
6930
6931 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6932 int x, int y,
6933 struct drm_framebuffer *fb)
6934 {
6935 struct drm_device *dev = crtc->dev;
6936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6937 int num_connectors = 0;
6938 intel_clock_t clock, reduced_clock;
6939 u32 dpll = 0, fp = 0, fp2 = 0;
6940 bool ok, has_reduced_clock = false;
6941 bool is_lvds = false;
6942 struct intel_encoder *encoder;
6943 struct intel_shared_dpll *pll;
6944
6945 for_each_encoder_on_crtc(dev, crtc, encoder) {
6946 switch (encoder->type) {
6947 case INTEL_OUTPUT_LVDS:
6948 is_lvds = true;
6949 break;
6950 }
6951
6952 num_connectors++;
6953 }
6954
6955 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6956 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6957
6958 ok = ironlake_compute_clocks(crtc, &clock,
6959 &has_reduced_clock, &reduced_clock);
6960 if (!ok && !intel_crtc->config.clock_set) {
6961 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6962 return -EINVAL;
6963 }
6964 /* Compat-code for transition, will disappear. */
6965 if (!intel_crtc->config.clock_set) {
6966 intel_crtc->config.dpll.n = clock.n;
6967 intel_crtc->config.dpll.m1 = clock.m1;
6968 intel_crtc->config.dpll.m2 = clock.m2;
6969 intel_crtc->config.dpll.p1 = clock.p1;
6970 intel_crtc->config.dpll.p2 = clock.p2;
6971 }
6972
6973 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6974 if (intel_crtc->config.has_pch_encoder) {
6975 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6976 if (has_reduced_clock)
6977 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6978
6979 dpll = ironlake_compute_dpll(intel_crtc,
6980 &fp, &reduced_clock,
6981 has_reduced_clock ? &fp2 : NULL);
6982
6983 intel_crtc->config.dpll_hw_state.dpll = dpll;
6984 intel_crtc->config.dpll_hw_state.fp0 = fp;
6985 if (has_reduced_clock)
6986 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6987 else
6988 intel_crtc->config.dpll_hw_state.fp1 = fp;
6989
6990 pll = intel_get_shared_dpll(intel_crtc);
6991 if (pll == NULL) {
6992 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6993 pipe_name(intel_crtc->pipe));
6994 return -EINVAL;
6995 }
6996 } else
6997 intel_put_shared_dpll(intel_crtc);
6998
6999 if (is_lvds && has_reduced_clock && i915.powersave)
7000 intel_crtc->lowfreq_avail = true;
7001 else
7002 intel_crtc->lowfreq_avail = false;
7003
7004 return 0;
7005 }
7006
7007 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7008 struct intel_link_m_n *m_n)
7009 {
7010 struct drm_device *dev = crtc->base.dev;
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012 enum pipe pipe = crtc->pipe;
7013
7014 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7015 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7016 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7017 & ~TU_SIZE_MASK;
7018 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7019 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7020 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7021 }
7022
7023 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7024 enum transcoder transcoder,
7025 struct intel_link_m_n *m_n)
7026 {
7027 struct drm_device *dev = crtc->base.dev;
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7029 enum pipe pipe = crtc->pipe;
7030
7031 if (INTEL_INFO(dev)->gen >= 5) {
7032 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7033 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7034 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7035 & ~TU_SIZE_MASK;
7036 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7037 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7038 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7039 } else {
7040 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7041 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7042 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7043 & ~TU_SIZE_MASK;
7044 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7045 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7046 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7047 }
7048 }
7049
7050 void intel_dp_get_m_n(struct intel_crtc *crtc,
7051 struct intel_crtc_config *pipe_config)
7052 {
7053 if (crtc->config.has_pch_encoder)
7054 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7055 else
7056 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7057 &pipe_config->dp_m_n);
7058 }
7059
7060 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7061 struct intel_crtc_config *pipe_config)
7062 {
7063 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7064 &pipe_config->fdi_m_n);
7065 }
7066
7067 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7068 struct intel_crtc_config *pipe_config)
7069 {
7070 struct drm_device *dev = crtc->base.dev;
7071 struct drm_i915_private *dev_priv = dev->dev_private;
7072 uint32_t tmp;
7073
7074 tmp = I915_READ(PF_CTL(crtc->pipe));
7075
7076 if (tmp & PF_ENABLE) {
7077 pipe_config->pch_pfit.enabled = true;
7078 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7079 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7080
7081 /* We currently do not free assignements of panel fitters on
7082 * ivb/hsw (since we don't use the higher upscaling modes which
7083 * differentiates them) so just WARN about this case for now. */
7084 if (IS_GEN7(dev)) {
7085 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7086 PF_PIPE_SEL_IVB(crtc->pipe));
7087 }
7088 }
7089 }
7090
7091 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7092 struct intel_plane_config *plane_config)
7093 {
7094 struct drm_device *dev = crtc->base.dev;
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 u32 val, base, offset;
7097 int pipe = crtc->pipe, plane = crtc->plane;
7098 int fourcc, pixel_format;
7099 int aligned_height;
7100
7101 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7102 if (!crtc->base.primary->fb) {
7103 DRM_DEBUG_KMS("failed to alloc fb\n");
7104 return;
7105 }
7106
7107 val = I915_READ(DSPCNTR(plane));
7108
7109 if (INTEL_INFO(dev)->gen >= 4)
7110 if (val & DISPPLANE_TILED)
7111 plane_config->tiled = true;
7112
7113 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7114 fourcc = intel_format_to_fourcc(pixel_format);
7115 crtc->base.primary->fb->pixel_format = fourcc;
7116 crtc->base.primary->fb->bits_per_pixel =
7117 drm_format_plane_cpp(fourcc, 0) * 8;
7118
7119 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7120 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7121 offset = I915_READ(DSPOFFSET(plane));
7122 } else {
7123 if (plane_config->tiled)
7124 offset = I915_READ(DSPTILEOFF(plane));
7125 else
7126 offset = I915_READ(DSPLINOFF(plane));
7127 }
7128 plane_config->base = base;
7129
7130 val = I915_READ(PIPESRC(pipe));
7131 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7132 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7133
7134 val = I915_READ(DSPSTRIDE(pipe));
7135 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7136
7137 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7138 plane_config->tiled);
7139
7140 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7141 aligned_height, PAGE_SIZE);
7142
7143 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7144 pipe, plane, crtc->base.primary->fb->width,
7145 crtc->base.primary->fb->height,
7146 crtc->base.primary->fb->bits_per_pixel, base,
7147 crtc->base.primary->fb->pitches[0],
7148 plane_config->size);
7149 }
7150
7151 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7152 struct intel_crtc_config *pipe_config)
7153 {
7154 struct drm_device *dev = crtc->base.dev;
7155 struct drm_i915_private *dev_priv = dev->dev_private;
7156 uint32_t tmp;
7157
7158 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7159 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7160
7161 tmp = I915_READ(PIPECONF(crtc->pipe));
7162 if (!(tmp & PIPECONF_ENABLE))
7163 return false;
7164
7165 switch (tmp & PIPECONF_BPC_MASK) {
7166 case PIPECONF_6BPC:
7167 pipe_config->pipe_bpp = 18;
7168 break;
7169 case PIPECONF_8BPC:
7170 pipe_config->pipe_bpp = 24;
7171 break;
7172 case PIPECONF_10BPC:
7173 pipe_config->pipe_bpp = 30;
7174 break;
7175 case PIPECONF_12BPC:
7176 pipe_config->pipe_bpp = 36;
7177 break;
7178 default:
7179 break;
7180 }
7181
7182 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7183 pipe_config->limited_color_range = true;
7184
7185 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7186 struct intel_shared_dpll *pll;
7187
7188 pipe_config->has_pch_encoder = true;
7189
7190 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7191 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7192 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7193
7194 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7195
7196 if (HAS_PCH_IBX(dev_priv->dev)) {
7197 pipe_config->shared_dpll =
7198 (enum intel_dpll_id) crtc->pipe;
7199 } else {
7200 tmp = I915_READ(PCH_DPLL_SEL);
7201 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7203 else
7204 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7205 }
7206
7207 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7208
7209 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7210 &pipe_config->dpll_hw_state));
7211
7212 tmp = pipe_config->dpll_hw_state.dpll;
7213 pipe_config->pixel_multiplier =
7214 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7215 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7216
7217 ironlake_pch_clock_get(crtc, pipe_config);
7218 } else {
7219 pipe_config->pixel_multiplier = 1;
7220 }
7221
7222 intel_get_pipe_timings(crtc, pipe_config);
7223
7224 ironlake_get_pfit_config(crtc, pipe_config);
7225
7226 return true;
7227 }
7228
7229 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7230 {
7231 struct drm_device *dev = dev_priv->dev;
7232 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7233 struct intel_crtc *crtc;
7234
7235 for_each_intel_crtc(dev, crtc)
7236 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7237 pipe_name(crtc->pipe));
7238
7239 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7240 WARN(plls->spll_refcount, "SPLL enabled\n");
7241 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7242 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7243 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7244 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7245 "CPU PWM1 enabled\n");
7246 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7247 "CPU PWM2 enabled\n");
7248 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7249 "PCH PWM1 enabled\n");
7250 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7251 "Utility pin enabled\n");
7252 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7253
7254 /*
7255 * In theory we can still leave IRQs enabled, as long as only the HPD
7256 * interrupts remain enabled. We used to check for that, but since it's
7257 * gen-specific and since we only disable LCPLL after we fully disable
7258 * the interrupts, the check below should be enough.
7259 */
7260 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7261 }
7262
7263 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7264 {
7265 struct drm_device *dev = dev_priv->dev;
7266
7267 if (IS_HASWELL(dev)) {
7268 mutex_lock(&dev_priv->rps.hw_lock);
7269 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7270 val))
7271 DRM_ERROR("Failed to disable D_COMP\n");
7272 mutex_unlock(&dev_priv->rps.hw_lock);
7273 } else {
7274 I915_WRITE(D_COMP, val);
7275 }
7276 POSTING_READ(D_COMP);
7277 }
7278
7279 /*
7280 * This function implements pieces of two sequences from BSpec:
7281 * - Sequence for display software to disable LCPLL
7282 * - Sequence for display software to allow package C8+
7283 * The steps implemented here are just the steps that actually touch the LCPLL
7284 * register. Callers should take care of disabling all the display engine
7285 * functions, doing the mode unset, fixing interrupts, etc.
7286 */
7287 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7288 bool switch_to_fclk, bool allow_power_down)
7289 {
7290 uint32_t val;
7291
7292 assert_can_disable_lcpll(dev_priv);
7293
7294 val = I915_READ(LCPLL_CTL);
7295
7296 if (switch_to_fclk) {
7297 val |= LCPLL_CD_SOURCE_FCLK;
7298 I915_WRITE(LCPLL_CTL, val);
7299
7300 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7301 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7302 DRM_ERROR("Switching to FCLK failed\n");
7303
7304 val = I915_READ(LCPLL_CTL);
7305 }
7306
7307 val |= LCPLL_PLL_DISABLE;
7308 I915_WRITE(LCPLL_CTL, val);
7309 POSTING_READ(LCPLL_CTL);
7310
7311 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7312 DRM_ERROR("LCPLL still locked\n");
7313
7314 val = I915_READ(D_COMP);
7315 val |= D_COMP_COMP_DISABLE;
7316 hsw_write_dcomp(dev_priv, val);
7317 ndelay(100);
7318
7319 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7320 DRM_ERROR("D_COMP RCOMP still in progress\n");
7321
7322 if (allow_power_down) {
7323 val = I915_READ(LCPLL_CTL);
7324 val |= LCPLL_POWER_DOWN_ALLOW;
7325 I915_WRITE(LCPLL_CTL, val);
7326 POSTING_READ(LCPLL_CTL);
7327 }
7328 }
7329
7330 /*
7331 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7332 * source.
7333 */
7334 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7335 {
7336 uint32_t val;
7337 unsigned long irqflags;
7338
7339 val = I915_READ(LCPLL_CTL);
7340
7341 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7342 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7343 return;
7344
7345 /*
7346 * Make sure we're not on PC8 state before disabling PC8, otherwise
7347 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7348 *
7349 * The other problem is that hsw_restore_lcpll() is called as part of
7350 * the runtime PM resume sequence, so we can't just call
7351 * gen6_gt_force_wake_get() because that function calls
7352 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7353 * while we are on the resume sequence. So to solve this problem we have
7354 * to call special forcewake code that doesn't touch runtime PM and
7355 * doesn't enable the forcewake delayed work.
7356 */
7357 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7358 if (dev_priv->uncore.forcewake_count++ == 0)
7359 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7360 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7361
7362 if (val & LCPLL_POWER_DOWN_ALLOW) {
7363 val &= ~LCPLL_POWER_DOWN_ALLOW;
7364 I915_WRITE(LCPLL_CTL, val);
7365 POSTING_READ(LCPLL_CTL);
7366 }
7367
7368 val = I915_READ(D_COMP);
7369 val |= D_COMP_COMP_FORCE;
7370 val &= ~D_COMP_COMP_DISABLE;
7371 hsw_write_dcomp(dev_priv, val);
7372
7373 val = I915_READ(LCPLL_CTL);
7374 val &= ~LCPLL_PLL_DISABLE;
7375 I915_WRITE(LCPLL_CTL, val);
7376
7377 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7378 DRM_ERROR("LCPLL not locked yet\n");
7379
7380 if (val & LCPLL_CD_SOURCE_FCLK) {
7381 val = I915_READ(LCPLL_CTL);
7382 val &= ~LCPLL_CD_SOURCE_FCLK;
7383 I915_WRITE(LCPLL_CTL, val);
7384
7385 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7386 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7387 DRM_ERROR("Switching back to LCPLL failed\n");
7388 }
7389
7390 /* See the big comment above. */
7391 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7392 if (--dev_priv->uncore.forcewake_count == 0)
7393 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7394 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7395 }
7396
7397 /*
7398 * Package states C8 and deeper are really deep PC states that can only be
7399 * reached when all the devices on the system allow it, so even if the graphics
7400 * device allows PC8+, it doesn't mean the system will actually get to these
7401 * states. Our driver only allows PC8+ when going into runtime PM.
7402 *
7403 * The requirements for PC8+ are that all the outputs are disabled, the power
7404 * well is disabled and most interrupts are disabled, and these are also
7405 * requirements for runtime PM. When these conditions are met, we manually do
7406 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7407 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7408 * hang the machine.
7409 *
7410 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7411 * the state of some registers, so when we come back from PC8+ we need to
7412 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7413 * need to take care of the registers kept by RC6. Notice that this happens even
7414 * if we don't put the device in PCI D3 state (which is what currently happens
7415 * because of the runtime PM support).
7416 *
7417 * For more, read "Display Sequences for Package C8" on the hardware
7418 * documentation.
7419 */
7420 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7421 {
7422 struct drm_device *dev = dev_priv->dev;
7423 uint32_t val;
7424
7425 DRM_DEBUG_KMS("Enabling package C8+\n");
7426
7427 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7428 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7429 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7430 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7431 }
7432
7433 lpt_disable_clkout_dp(dev);
7434 hsw_disable_lcpll(dev_priv, true, true);
7435 }
7436
7437 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7438 {
7439 struct drm_device *dev = dev_priv->dev;
7440 uint32_t val;
7441
7442 DRM_DEBUG_KMS("Disabling package C8+\n");
7443
7444 hsw_restore_lcpll(dev_priv);
7445 lpt_init_pch_refclk(dev);
7446
7447 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7448 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7449 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7450 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7451 }
7452
7453 intel_prepare_ddi(dev);
7454 }
7455
7456 static void snb_modeset_global_resources(struct drm_device *dev)
7457 {
7458 modeset_update_crtc_power_domains(dev);
7459 }
7460
7461 static void haswell_modeset_global_resources(struct drm_device *dev)
7462 {
7463 modeset_update_crtc_power_domains(dev);
7464 }
7465
7466 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7467 int x, int y,
7468 struct drm_framebuffer *fb)
7469 {
7470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7471
7472 if (!intel_ddi_pll_select(intel_crtc))
7473 return -EINVAL;
7474 intel_ddi_pll_enable(intel_crtc);
7475
7476 intel_crtc->lowfreq_avail = false;
7477
7478 return 0;
7479 }
7480
7481 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7482 struct intel_crtc_config *pipe_config)
7483 {
7484 struct drm_device *dev = crtc->base.dev;
7485 struct drm_i915_private *dev_priv = dev->dev_private;
7486 enum intel_display_power_domain pfit_domain;
7487 uint32_t tmp;
7488
7489 if (!intel_display_power_enabled(dev_priv,
7490 POWER_DOMAIN_PIPE(crtc->pipe)))
7491 return false;
7492
7493 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7494 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7495
7496 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7497 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7498 enum pipe trans_edp_pipe;
7499 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7500 default:
7501 WARN(1, "unknown pipe linked to edp transcoder\n");
7502 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7503 case TRANS_DDI_EDP_INPUT_A_ON:
7504 trans_edp_pipe = PIPE_A;
7505 break;
7506 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7507 trans_edp_pipe = PIPE_B;
7508 break;
7509 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7510 trans_edp_pipe = PIPE_C;
7511 break;
7512 }
7513
7514 if (trans_edp_pipe == crtc->pipe)
7515 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7516 }
7517
7518 if (!intel_display_power_enabled(dev_priv,
7519 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7520 return false;
7521
7522 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7523 if (!(tmp & PIPECONF_ENABLE))
7524 return false;
7525
7526 /*
7527 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7528 * DDI E. So just check whether this pipe is wired to DDI E and whether
7529 * the PCH transcoder is on.
7530 */
7531 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7532 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7533 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7534 pipe_config->has_pch_encoder = true;
7535
7536 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7537 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7538 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7539
7540 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7541 }
7542
7543 intel_get_pipe_timings(crtc, pipe_config);
7544
7545 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7546 if (intel_display_power_enabled(dev_priv, pfit_domain))
7547 ironlake_get_pfit_config(crtc, pipe_config);
7548
7549 if (IS_HASWELL(dev))
7550 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7551 (I915_READ(IPS_CTL) & IPS_ENABLE);
7552
7553 pipe_config->pixel_multiplier = 1;
7554
7555 return true;
7556 }
7557
7558 static struct {
7559 int clock;
7560 u32 config;
7561 } hdmi_audio_clock[] = {
7562 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7563 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7564 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7565 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7566 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7567 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7568 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7569 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7570 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7571 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7572 };
7573
7574 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7575 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7576 {
7577 int i;
7578
7579 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7580 if (mode->clock == hdmi_audio_clock[i].clock)
7581 break;
7582 }
7583
7584 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7585 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7586 i = 1;
7587 }
7588
7589 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7590 hdmi_audio_clock[i].clock,
7591 hdmi_audio_clock[i].config);
7592
7593 return hdmi_audio_clock[i].config;
7594 }
7595
7596 static bool intel_eld_uptodate(struct drm_connector *connector,
7597 int reg_eldv, uint32_t bits_eldv,
7598 int reg_elda, uint32_t bits_elda,
7599 int reg_edid)
7600 {
7601 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7602 uint8_t *eld = connector->eld;
7603 uint32_t i;
7604
7605 i = I915_READ(reg_eldv);
7606 i &= bits_eldv;
7607
7608 if (!eld[0])
7609 return !i;
7610
7611 if (!i)
7612 return false;
7613
7614 i = I915_READ(reg_elda);
7615 i &= ~bits_elda;
7616 I915_WRITE(reg_elda, i);
7617
7618 for (i = 0; i < eld[2]; i++)
7619 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7620 return false;
7621
7622 return true;
7623 }
7624
7625 static void g4x_write_eld(struct drm_connector *connector,
7626 struct drm_crtc *crtc,
7627 struct drm_display_mode *mode)
7628 {
7629 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7630 uint8_t *eld = connector->eld;
7631 uint32_t eldv;
7632 uint32_t len;
7633 uint32_t i;
7634
7635 i = I915_READ(G4X_AUD_VID_DID);
7636
7637 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7638 eldv = G4X_ELDV_DEVCL_DEVBLC;
7639 else
7640 eldv = G4X_ELDV_DEVCTG;
7641
7642 if (intel_eld_uptodate(connector,
7643 G4X_AUD_CNTL_ST, eldv,
7644 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7645 G4X_HDMIW_HDMIEDID))
7646 return;
7647
7648 i = I915_READ(G4X_AUD_CNTL_ST);
7649 i &= ~(eldv | G4X_ELD_ADDR);
7650 len = (i >> 9) & 0x1f; /* ELD buffer size */
7651 I915_WRITE(G4X_AUD_CNTL_ST, i);
7652
7653 if (!eld[0])
7654 return;
7655
7656 len = min_t(uint8_t, eld[2], len);
7657 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7658 for (i = 0; i < len; i++)
7659 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7660
7661 i = I915_READ(G4X_AUD_CNTL_ST);
7662 i |= eldv;
7663 I915_WRITE(G4X_AUD_CNTL_ST, i);
7664 }
7665
7666 static void haswell_write_eld(struct drm_connector *connector,
7667 struct drm_crtc *crtc,
7668 struct drm_display_mode *mode)
7669 {
7670 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7671 uint8_t *eld = connector->eld;
7672 uint32_t eldv;
7673 uint32_t i;
7674 int len;
7675 int pipe = to_intel_crtc(crtc)->pipe;
7676 int tmp;
7677
7678 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7679 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7680 int aud_config = HSW_AUD_CFG(pipe);
7681 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7682
7683 /* Audio output enable */
7684 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7685 tmp = I915_READ(aud_cntrl_st2);
7686 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7687 I915_WRITE(aud_cntrl_st2, tmp);
7688 POSTING_READ(aud_cntrl_st2);
7689
7690 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7691
7692 /* Set ELD valid state */
7693 tmp = I915_READ(aud_cntrl_st2);
7694 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7695 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7696 I915_WRITE(aud_cntrl_st2, tmp);
7697 tmp = I915_READ(aud_cntrl_st2);
7698 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7699
7700 /* Enable HDMI mode */
7701 tmp = I915_READ(aud_config);
7702 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7703 /* clear N_programing_enable and N_value_index */
7704 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7705 I915_WRITE(aud_config, tmp);
7706
7707 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7708
7709 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7710
7711 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7712 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7713 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7714 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7715 } else {
7716 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7717 }
7718
7719 if (intel_eld_uptodate(connector,
7720 aud_cntrl_st2, eldv,
7721 aud_cntl_st, IBX_ELD_ADDRESS,
7722 hdmiw_hdmiedid))
7723 return;
7724
7725 i = I915_READ(aud_cntrl_st2);
7726 i &= ~eldv;
7727 I915_WRITE(aud_cntrl_st2, i);
7728
7729 if (!eld[0])
7730 return;
7731
7732 i = I915_READ(aud_cntl_st);
7733 i &= ~IBX_ELD_ADDRESS;
7734 I915_WRITE(aud_cntl_st, i);
7735 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7736 DRM_DEBUG_DRIVER("port num:%d\n", i);
7737
7738 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7739 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7740 for (i = 0; i < len; i++)
7741 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7742
7743 i = I915_READ(aud_cntrl_st2);
7744 i |= eldv;
7745 I915_WRITE(aud_cntrl_st2, i);
7746
7747 }
7748
7749 static void ironlake_write_eld(struct drm_connector *connector,
7750 struct drm_crtc *crtc,
7751 struct drm_display_mode *mode)
7752 {
7753 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7754 uint8_t *eld = connector->eld;
7755 uint32_t eldv;
7756 uint32_t i;
7757 int len;
7758 int hdmiw_hdmiedid;
7759 int aud_config;
7760 int aud_cntl_st;
7761 int aud_cntrl_st2;
7762 int pipe = to_intel_crtc(crtc)->pipe;
7763
7764 if (HAS_PCH_IBX(connector->dev)) {
7765 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7766 aud_config = IBX_AUD_CFG(pipe);
7767 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7768 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7769 } else if (IS_VALLEYVIEW(connector->dev)) {
7770 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7771 aud_config = VLV_AUD_CFG(pipe);
7772 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7773 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7774 } else {
7775 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7776 aud_config = CPT_AUD_CFG(pipe);
7777 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7778 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7779 }
7780
7781 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7782
7783 if (IS_VALLEYVIEW(connector->dev)) {
7784 struct intel_encoder *intel_encoder;
7785 struct intel_digital_port *intel_dig_port;
7786
7787 intel_encoder = intel_attached_encoder(connector);
7788 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7789 i = intel_dig_port->port;
7790 } else {
7791 i = I915_READ(aud_cntl_st);
7792 i = (i >> 29) & DIP_PORT_SEL_MASK;
7793 /* DIP_Port_Select, 0x1 = PortB */
7794 }
7795
7796 if (!i) {
7797 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7798 /* operate blindly on all ports */
7799 eldv = IBX_ELD_VALIDB;
7800 eldv |= IBX_ELD_VALIDB << 4;
7801 eldv |= IBX_ELD_VALIDB << 8;
7802 } else {
7803 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7804 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7805 }
7806
7807 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7808 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7809 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7810 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7811 } else {
7812 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7813 }
7814
7815 if (intel_eld_uptodate(connector,
7816 aud_cntrl_st2, eldv,
7817 aud_cntl_st, IBX_ELD_ADDRESS,
7818 hdmiw_hdmiedid))
7819 return;
7820
7821 i = I915_READ(aud_cntrl_st2);
7822 i &= ~eldv;
7823 I915_WRITE(aud_cntrl_st2, i);
7824
7825 if (!eld[0])
7826 return;
7827
7828 i = I915_READ(aud_cntl_st);
7829 i &= ~IBX_ELD_ADDRESS;
7830 I915_WRITE(aud_cntl_st, i);
7831
7832 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7833 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7834 for (i = 0; i < len; i++)
7835 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7836
7837 i = I915_READ(aud_cntrl_st2);
7838 i |= eldv;
7839 I915_WRITE(aud_cntrl_st2, i);
7840 }
7841
7842 void intel_write_eld(struct drm_encoder *encoder,
7843 struct drm_display_mode *mode)
7844 {
7845 struct drm_crtc *crtc = encoder->crtc;
7846 struct drm_connector *connector;
7847 struct drm_device *dev = encoder->dev;
7848 struct drm_i915_private *dev_priv = dev->dev_private;
7849
7850 connector = drm_select_eld(encoder, mode);
7851 if (!connector)
7852 return;
7853
7854 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7855 connector->base.id,
7856 drm_get_connector_name(connector),
7857 connector->encoder->base.id,
7858 drm_get_encoder_name(connector->encoder));
7859
7860 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7861
7862 if (dev_priv->display.write_eld)
7863 dev_priv->display.write_eld(connector, crtc, mode);
7864 }
7865
7866 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7867 {
7868 struct drm_device *dev = crtc->dev;
7869 struct drm_i915_private *dev_priv = dev->dev_private;
7870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7871 bool visible = base != 0;
7872 u32 cntl;
7873
7874 if (intel_crtc->cursor_visible == visible)
7875 return;
7876
7877 cntl = I915_READ(_CURACNTR);
7878 if (visible) {
7879 /* On these chipsets we can only modify the base whilst
7880 * the cursor is disabled.
7881 */
7882 I915_WRITE(_CURABASE, base);
7883
7884 cntl &= ~(CURSOR_FORMAT_MASK);
7885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7886 cntl |= CURSOR_ENABLE |
7887 CURSOR_GAMMA_ENABLE |
7888 CURSOR_FORMAT_ARGB;
7889 } else
7890 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7891 I915_WRITE(_CURACNTR, cntl);
7892
7893 intel_crtc->cursor_visible = visible;
7894 }
7895
7896 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7897 {
7898 struct drm_device *dev = crtc->dev;
7899 struct drm_i915_private *dev_priv = dev->dev_private;
7900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7901 int pipe = intel_crtc->pipe;
7902 bool visible = base != 0;
7903
7904 if (intel_crtc->cursor_visible != visible) {
7905 int16_t width = intel_crtc->cursor_width;
7906 uint32_t cntl = I915_READ(CURCNTR(pipe));
7907 if (base) {
7908 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7909 cntl |= MCURSOR_GAMMA_ENABLE;
7910
7911 switch (width) {
7912 case 64:
7913 cntl |= CURSOR_MODE_64_ARGB_AX;
7914 break;
7915 case 128:
7916 cntl |= CURSOR_MODE_128_ARGB_AX;
7917 break;
7918 case 256:
7919 cntl |= CURSOR_MODE_256_ARGB_AX;
7920 break;
7921 default:
7922 WARN_ON(1);
7923 return;
7924 }
7925 cntl |= pipe << 28; /* Connect to correct pipe */
7926 } else {
7927 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7928 cntl |= CURSOR_MODE_DISABLE;
7929 }
7930 I915_WRITE(CURCNTR(pipe), cntl);
7931
7932 intel_crtc->cursor_visible = visible;
7933 }
7934 /* and commit changes on next vblank */
7935 POSTING_READ(CURCNTR(pipe));
7936 I915_WRITE(CURBASE(pipe), base);
7937 POSTING_READ(CURBASE(pipe));
7938 }
7939
7940 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7941 {
7942 struct drm_device *dev = crtc->dev;
7943 struct drm_i915_private *dev_priv = dev->dev_private;
7944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7945 int pipe = intel_crtc->pipe;
7946 bool visible = base != 0;
7947
7948 if (intel_crtc->cursor_visible != visible) {
7949 int16_t width = intel_crtc->cursor_width;
7950 uint32_t cntl = I915_READ(CURCNTR(pipe));
7951 if (base) {
7952 cntl &= ~CURSOR_MODE;
7953 cntl |= MCURSOR_GAMMA_ENABLE;
7954 switch (width) {
7955 case 64:
7956 cntl |= CURSOR_MODE_64_ARGB_AX;
7957 break;
7958 case 128:
7959 cntl |= CURSOR_MODE_128_ARGB_AX;
7960 break;
7961 case 256:
7962 cntl |= CURSOR_MODE_256_ARGB_AX;
7963 break;
7964 default:
7965 WARN_ON(1);
7966 return;
7967 }
7968 } else {
7969 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7970 cntl |= CURSOR_MODE_DISABLE;
7971 }
7972 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7973 cntl |= CURSOR_PIPE_CSC_ENABLE;
7974 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7975 }
7976 I915_WRITE(CURCNTR(pipe), cntl);
7977
7978 intel_crtc->cursor_visible = visible;
7979 }
7980 /* and commit changes on next vblank */
7981 POSTING_READ(CURCNTR(pipe));
7982 I915_WRITE(CURBASE(pipe), base);
7983 POSTING_READ(CURBASE(pipe));
7984 }
7985
7986 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7987 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7988 bool on)
7989 {
7990 struct drm_device *dev = crtc->dev;
7991 struct drm_i915_private *dev_priv = dev->dev_private;
7992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7993 int pipe = intel_crtc->pipe;
7994 int x = intel_crtc->cursor_x;
7995 int y = intel_crtc->cursor_y;
7996 u32 base = 0, pos = 0;
7997 bool visible;
7998
7999 if (on)
8000 base = intel_crtc->cursor_addr;
8001
8002 if (x >= intel_crtc->config.pipe_src_w)
8003 base = 0;
8004
8005 if (y >= intel_crtc->config.pipe_src_h)
8006 base = 0;
8007
8008 if (x < 0) {
8009 if (x + intel_crtc->cursor_width <= 0)
8010 base = 0;
8011
8012 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8013 x = -x;
8014 }
8015 pos |= x << CURSOR_X_SHIFT;
8016
8017 if (y < 0) {
8018 if (y + intel_crtc->cursor_height <= 0)
8019 base = 0;
8020
8021 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8022 y = -y;
8023 }
8024 pos |= y << CURSOR_Y_SHIFT;
8025
8026 visible = base != 0;
8027 if (!visible && !intel_crtc->cursor_visible)
8028 return;
8029
8030 I915_WRITE(CURPOS(pipe), pos);
8031
8032 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8033 ivb_update_cursor(crtc, base);
8034 else if (IS_845G(dev) || IS_I865G(dev))
8035 i845_update_cursor(crtc, base);
8036 else
8037 i9xx_update_cursor(crtc, base);
8038 }
8039
8040 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8041 struct drm_file *file,
8042 uint32_t handle,
8043 uint32_t width, uint32_t height)
8044 {
8045 struct drm_device *dev = crtc->dev;
8046 struct drm_i915_private *dev_priv = dev->dev_private;
8047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8048 struct drm_i915_gem_object *obj;
8049 unsigned old_width;
8050 uint32_t addr;
8051 int ret;
8052
8053 /* if we want to turn off the cursor ignore width and height */
8054 if (!handle) {
8055 DRM_DEBUG_KMS("cursor off\n");
8056 addr = 0;
8057 obj = NULL;
8058 mutex_lock(&dev->struct_mutex);
8059 goto finish;
8060 }
8061
8062 /* Check for which cursor types we support */
8063 if (!((width == 64 && height == 64) ||
8064 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8065 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8066 DRM_DEBUG("Cursor dimension not supported\n");
8067 return -EINVAL;
8068 }
8069
8070 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8071 if (&obj->base == NULL)
8072 return -ENOENT;
8073
8074 if (obj->base.size < width * height * 4) {
8075 DRM_DEBUG_KMS("buffer is to small\n");
8076 ret = -ENOMEM;
8077 goto fail;
8078 }
8079
8080 /* we only need to pin inside GTT if cursor is non-phy */
8081 mutex_lock(&dev->struct_mutex);
8082 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8083 unsigned alignment;
8084
8085 if (obj->tiling_mode) {
8086 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8087 ret = -EINVAL;
8088 goto fail_locked;
8089 }
8090
8091 /* Note that the w/a also requires 2 PTE of padding following
8092 * the bo. We currently fill all unused PTE with the shadow
8093 * page and so we should always have valid PTE following the
8094 * cursor preventing the VT-d warning.
8095 */
8096 alignment = 0;
8097 if (need_vtd_wa(dev))
8098 alignment = 64*1024;
8099
8100 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8101 if (ret) {
8102 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8103 goto fail_locked;
8104 }
8105
8106 ret = i915_gem_object_put_fence(obj);
8107 if (ret) {
8108 DRM_DEBUG_KMS("failed to release fence for cursor");
8109 goto fail_unpin;
8110 }
8111
8112 addr = i915_gem_obj_ggtt_offset(obj);
8113 } else {
8114 int align = IS_I830(dev) ? 16 * 1024 : 256;
8115 ret = i915_gem_attach_phys_object(dev, obj,
8116 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
8117 align);
8118 if (ret) {
8119 DRM_DEBUG_KMS("failed to attach phys object\n");
8120 goto fail_locked;
8121 }
8122 addr = obj->phys_obj->handle->busaddr;
8123 }
8124
8125 if (IS_GEN2(dev))
8126 I915_WRITE(CURSIZE, (height << 12) | width);
8127
8128 finish:
8129 if (intel_crtc->cursor_bo) {
8130 if (INTEL_INFO(dev)->cursor_needs_physical) {
8131 if (intel_crtc->cursor_bo != obj)
8132 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
8133 } else
8134 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8135 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8136 }
8137
8138 mutex_unlock(&dev->struct_mutex);
8139
8140 old_width = intel_crtc->cursor_width;
8141
8142 intel_crtc->cursor_addr = addr;
8143 intel_crtc->cursor_bo = obj;
8144 intel_crtc->cursor_width = width;
8145 intel_crtc->cursor_height = height;
8146
8147 if (intel_crtc->active) {
8148 if (old_width != width)
8149 intel_update_watermarks(crtc);
8150 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8151 }
8152
8153 return 0;
8154 fail_unpin:
8155 i915_gem_object_unpin_from_display_plane(obj);
8156 fail_locked:
8157 mutex_unlock(&dev->struct_mutex);
8158 fail:
8159 drm_gem_object_unreference_unlocked(&obj->base);
8160 return ret;
8161 }
8162
8163 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8164 {
8165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8166
8167 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8168 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8169
8170 if (intel_crtc->active)
8171 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8172
8173 return 0;
8174 }
8175
8176 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8177 u16 *blue, uint32_t start, uint32_t size)
8178 {
8179 int end = (start + size > 256) ? 256 : start + size, i;
8180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8181
8182 for (i = start; i < end; i++) {
8183 intel_crtc->lut_r[i] = red[i] >> 8;
8184 intel_crtc->lut_g[i] = green[i] >> 8;
8185 intel_crtc->lut_b[i] = blue[i] >> 8;
8186 }
8187
8188 intel_crtc_load_lut(crtc);
8189 }
8190
8191 /* VESA 640x480x72Hz mode to set on the pipe */
8192 static struct drm_display_mode load_detect_mode = {
8193 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8194 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8195 };
8196
8197 struct drm_framebuffer *
8198 __intel_framebuffer_create(struct drm_device *dev,
8199 struct drm_mode_fb_cmd2 *mode_cmd,
8200 struct drm_i915_gem_object *obj)
8201 {
8202 struct intel_framebuffer *intel_fb;
8203 int ret;
8204
8205 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8206 if (!intel_fb) {
8207 drm_gem_object_unreference_unlocked(&obj->base);
8208 return ERR_PTR(-ENOMEM);
8209 }
8210
8211 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8212 if (ret)
8213 goto err;
8214
8215 return &intel_fb->base;
8216 err:
8217 drm_gem_object_unreference_unlocked(&obj->base);
8218 kfree(intel_fb);
8219
8220 return ERR_PTR(ret);
8221 }
8222
8223 static struct drm_framebuffer *
8224 intel_framebuffer_create(struct drm_device *dev,
8225 struct drm_mode_fb_cmd2 *mode_cmd,
8226 struct drm_i915_gem_object *obj)
8227 {
8228 struct drm_framebuffer *fb;
8229 int ret;
8230
8231 ret = i915_mutex_lock_interruptible(dev);
8232 if (ret)
8233 return ERR_PTR(ret);
8234 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8235 mutex_unlock(&dev->struct_mutex);
8236
8237 return fb;
8238 }
8239
8240 static u32
8241 intel_framebuffer_pitch_for_width(int width, int bpp)
8242 {
8243 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8244 return ALIGN(pitch, 64);
8245 }
8246
8247 static u32
8248 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8249 {
8250 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8251 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8252 }
8253
8254 static struct drm_framebuffer *
8255 intel_framebuffer_create_for_mode(struct drm_device *dev,
8256 struct drm_display_mode *mode,
8257 int depth, int bpp)
8258 {
8259 struct drm_i915_gem_object *obj;
8260 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8261
8262 obj = i915_gem_alloc_object(dev,
8263 intel_framebuffer_size_for_mode(mode, bpp));
8264 if (obj == NULL)
8265 return ERR_PTR(-ENOMEM);
8266
8267 mode_cmd.width = mode->hdisplay;
8268 mode_cmd.height = mode->vdisplay;
8269 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8270 bpp);
8271 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8272
8273 return intel_framebuffer_create(dev, &mode_cmd, obj);
8274 }
8275
8276 static struct drm_framebuffer *
8277 mode_fits_in_fbdev(struct drm_device *dev,
8278 struct drm_display_mode *mode)
8279 {
8280 #ifdef CONFIG_DRM_I915_FBDEV
8281 struct drm_i915_private *dev_priv = dev->dev_private;
8282 struct drm_i915_gem_object *obj;
8283 struct drm_framebuffer *fb;
8284
8285 if (!dev_priv->fbdev)
8286 return NULL;
8287
8288 if (!dev_priv->fbdev->fb)
8289 return NULL;
8290
8291 obj = dev_priv->fbdev->fb->obj;
8292 BUG_ON(!obj);
8293
8294 fb = &dev_priv->fbdev->fb->base;
8295 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8296 fb->bits_per_pixel))
8297 return NULL;
8298
8299 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8300 return NULL;
8301
8302 return fb;
8303 #else
8304 return NULL;
8305 #endif
8306 }
8307
8308 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8309 struct drm_display_mode *mode,
8310 struct intel_load_detect_pipe *old)
8311 {
8312 struct intel_crtc *intel_crtc;
8313 struct intel_encoder *intel_encoder =
8314 intel_attached_encoder(connector);
8315 struct drm_crtc *possible_crtc;
8316 struct drm_encoder *encoder = &intel_encoder->base;
8317 struct drm_crtc *crtc = NULL;
8318 struct drm_device *dev = encoder->dev;
8319 struct drm_framebuffer *fb;
8320 int i = -1;
8321
8322 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8323 connector->base.id, drm_get_connector_name(connector),
8324 encoder->base.id, drm_get_encoder_name(encoder));
8325
8326 /*
8327 * Algorithm gets a little messy:
8328 *
8329 * - if the connector already has an assigned crtc, use it (but make
8330 * sure it's on first)
8331 *
8332 * - try to find the first unused crtc that can drive this connector,
8333 * and use that if we find one
8334 */
8335
8336 /* See if we already have a CRTC for this connector */
8337 if (encoder->crtc) {
8338 crtc = encoder->crtc;
8339
8340 mutex_lock(&crtc->mutex);
8341
8342 old->dpms_mode = connector->dpms;
8343 old->load_detect_temp = false;
8344
8345 /* Make sure the crtc and connector are running */
8346 if (connector->dpms != DRM_MODE_DPMS_ON)
8347 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8348
8349 return true;
8350 }
8351
8352 /* Find an unused one (if possible) */
8353 for_each_crtc(dev, possible_crtc) {
8354 i++;
8355 if (!(encoder->possible_crtcs & (1 << i)))
8356 continue;
8357 if (!possible_crtc->enabled) {
8358 crtc = possible_crtc;
8359 break;
8360 }
8361 }
8362
8363 /*
8364 * If we didn't find an unused CRTC, don't use any.
8365 */
8366 if (!crtc) {
8367 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8368 return false;
8369 }
8370
8371 mutex_lock(&crtc->mutex);
8372 intel_encoder->new_crtc = to_intel_crtc(crtc);
8373 to_intel_connector(connector)->new_encoder = intel_encoder;
8374
8375 intel_crtc = to_intel_crtc(crtc);
8376 intel_crtc->new_enabled = true;
8377 intel_crtc->new_config = &intel_crtc->config;
8378 old->dpms_mode = connector->dpms;
8379 old->load_detect_temp = true;
8380 old->release_fb = NULL;
8381
8382 if (!mode)
8383 mode = &load_detect_mode;
8384
8385 /* We need a framebuffer large enough to accommodate all accesses
8386 * that the plane may generate whilst we perform load detection.
8387 * We can not rely on the fbcon either being present (we get called
8388 * during its initialisation to detect all boot displays, or it may
8389 * not even exist) or that it is large enough to satisfy the
8390 * requested mode.
8391 */
8392 fb = mode_fits_in_fbdev(dev, mode);
8393 if (fb == NULL) {
8394 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8395 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8396 old->release_fb = fb;
8397 } else
8398 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8399 if (IS_ERR(fb)) {
8400 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8401 goto fail;
8402 }
8403
8404 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8405 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8406 if (old->release_fb)
8407 old->release_fb->funcs->destroy(old->release_fb);
8408 goto fail;
8409 }
8410
8411 /* let the connector get through one full cycle before testing */
8412 intel_wait_for_vblank(dev, intel_crtc->pipe);
8413 return true;
8414
8415 fail:
8416 intel_crtc->new_enabled = crtc->enabled;
8417 if (intel_crtc->new_enabled)
8418 intel_crtc->new_config = &intel_crtc->config;
8419 else
8420 intel_crtc->new_config = NULL;
8421 mutex_unlock(&crtc->mutex);
8422 return false;
8423 }
8424
8425 void intel_release_load_detect_pipe(struct drm_connector *connector,
8426 struct intel_load_detect_pipe *old)
8427 {
8428 struct intel_encoder *intel_encoder =
8429 intel_attached_encoder(connector);
8430 struct drm_encoder *encoder = &intel_encoder->base;
8431 struct drm_crtc *crtc = encoder->crtc;
8432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8433
8434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8435 connector->base.id, drm_get_connector_name(connector),
8436 encoder->base.id, drm_get_encoder_name(encoder));
8437
8438 if (old->load_detect_temp) {
8439 to_intel_connector(connector)->new_encoder = NULL;
8440 intel_encoder->new_crtc = NULL;
8441 intel_crtc->new_enabled = false;
8442 intel_crtc->new_config = NULL;
8443 intel_set_mode(crtc, NULL, 0, 0, NULL);
8444
8445 if (old->release_fb) {
8446 drm_framebuffer_unregister_private(old->release_fb);
8447 drm_framebuffer_unreference(old->release_fb);
8448 }
8449
8450 mutex_unlock(&crtc->mutex);
8451 return;
8452 }
8453
8454 /* Switch crtc and encoder back off if necessary */
8455 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8456 connector->funcs->dpms(connector, old->dpms_mode);
8457
8458 mutex_unlock(&crtc->mutex);
8459 }
8460
8461 static int i9xx_pll_refclk(struct drm_device *dev,
8462 const struct intel_crtc_config *pipe_config)
8463 {
8464 struct drm_i915_private *dev_priv = dev->dev_private;
8465 u32 dpll = pipe_config->dpll_hw_state.dpll;
8466
8467 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8468 return dev_priv->vbt.lvds_ssc_freq;
8469 else if (HAS_PCH_SPLIT(dev))
8470 return 120000;
8471 else if (!IS_GEN2(dev))
8472 return 96000;
8473 else
8474 return 48000;
8475 }
8476
8477 /* Returns the clock of the currently programmed mode of the given pipe. */
8478 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8479 struct intel_crtc_config *pipe_config)
8480 {
8481 struct drm_device *dev = crtc->base.dev;
8482 struct drm_i915_private *dev_priv = dev->dev_private;
8483 int pipe = pipe_config->cpu_transcoder;
8484 u32 dpll = pipe_config->dpll_hw_state.dpll;
8485 u32 fp;
8486 intel_clock_t clock;
8487 int refclk = i9xx_pll_refclk(dev, pipe_config);
8488
8489 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8490 fp = pipe_config->dpll_hw_state.fp0;
8491 else
8492 fp = pipe_config->dpll_hw_state.fp1;
8493
8494 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8495 if (IS_PINEVIEW(dev)) {
8496 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8497 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8498 } else {
8499 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8500 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8501 }
8502
8503 if (!IS_GEN2(dev)) {
8504 if (IS_PINEVIEW(dev))
8505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8506 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8507 else
8508 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8509 DPLL_FPA01_P1_POST_DIV_SHIFT);
8510
8511 switch (dpll & DPLL_MODE_MASK) {
8512 case DPLLB_MODE_DAC_SERIAL:
8513 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8514 5 : 10;
8515 break;
8516 case DPLLB_MODE_LVDS:
8517 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8518 7 : 14;
8519 break;
8520 default:
8521 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8522 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8523 return;
8524 }
8525
8526 if (IS_PINEVIEW(dev))
8527 pineview_clock(refclk, &clock);
8528 else
8529 i9xx_clock(refclk, &clock);
8530 } else {
8531 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8532 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8533
8534 if (is_lvds) {
8535 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8536 DPLL_FPA01_P1_POST_DIV_SHIFT);
8537
8538 if (lvds & LVDS_CLKB_POWER_UP)
8539 clock.p2 = 7;
8540 else
8541 clock.p2 = 14;
8542 } else {
8543 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8544 clock.p1 = 2;
8545 else {
8546 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8547 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8548 }
8549 if (dpll & PLL_P2_DIVIDE_BY_4)
8550 clock.p2 = 4;
8551 else
8552 clock.p2 = 2;
8553 }
8554
8555 i9xx_clock(refclk, &clock);
8556 }
8557
8558 /*
8559 * This value includes pixel_multiplier. We will use
8560 * port_clock to compute adjusted_mode.crtc_clock in the
8561 * encoder's get_config() function.
8562 */
8563 pipe_config->port_clock = clock.dot;
8564 }
8565
8566 int intel_dotclock_calculate(int link_freq,
8567 const struct intel_link_m_n *m_n)
8568 {
8569 /*
8570 * The calculation for the data clock is:
8571 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8572 * But we want to avoid losing precison if possible, so:
8573 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8574 *
8575 * and the link clock is simpler:
8576 * link_clock = (m * link_clock) / n
8577 */
8578
8579 if (!m_n->link_n)
8580 return 0;
8581
8582 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8583 }
8584
8585 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8586 struct intel_crtc_config *pipe_config)
8587 {
8588 struct drm_device *dev = crtc->base.dev;
8589
8590 /* read out port_clock from the DPLL */
8591 i9xx_crtc_clock_get(crtc, pipe_config);
8592
8593 /*
8594 * This value does not include pixel_multiplier.
8595 * We will check that port_clock and adjusted_mode.crtc_clock
8596 * agree once we know their relationship in the encoder's
8597 * get_config() function.
8598 */
8599 pipe_config->adjusted_mode.crtc_clock =
8600 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8601 &pipe_config->fdi_m_n);
8602 }
8603
8604 /** Returns the currently programmed mode of the given pipe. */
8605 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8606 struct drm_crtc *crtc)
8607 {
8608 struct drm_i915_private *dev_priv = dev->dev_private;
8609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8610 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8611 struct drm_display_mode *mode;
8612 struct intel_crtc_config pipe_config;
8613 int htot = I915_READ(HTOTAL(cpu_transcoder));
8614 int hsync = I915_READ(HSYNC(cpu_transcoder));
8615 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8616 int vsync = I915_READ(VSYNC(cpu_transcoder));
8617 enum pipe pipe = intel_crtc->pipe;
8618
8619 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8620 if (!mode)
8621 return NULL;
8622
8623 /*
8624 * Construct a pipe_config sufficient for getting the clock info
8625 * back out of crtc_clock_get.
8626 *
8627 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8628 * to use a real value here instead.
8629 */
8630 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8631 pipe_config.pixel_multiplier = 1;
8632 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8633 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8634 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8635 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8636
8637 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8638 mode->hdisplay = (htot & 0xffff) + 1;
8639 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8640 mode->hsync_start = (hsync & 0xffff) + 1;
8641 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8642 mode->vdisplay = (vtot & 0xffff) + 1;
8643 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8644 mode->vsync_start = (vsync & 0xffff) + 1;
8645 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8646
8647 drm_mode_set_name(mode);
8648
8649 return mode;
8650 }
8651
8652 static void intel_increase_pllclock(struct drm_crtc *crtc)
8653 {
8654 struct drm_device *dev = crtc->dev;
8655 struct drm_i915_private *dev_priv = dev->dev_private;
8656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8657 int pipe = intel_crtc->pipe;
8658 int dpll_reg = DPLL(pipe);
8659 int dpll;
8660
8661 if (HAS_PCH_SPLIT(dev))
8662 return;
8663
8664 if (!dev_priv->lvds_downclock_avail)
8665 return;
8666
8667 dpll = I915_READ(dpll_reg);
8668 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8669 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8670
8671 assert_panel_unlocked(dev_priv, pipe);
8672
8673 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8674 I915_WRITE(dpll_reg, dpll);
8675 intel_wait_for_vblank(dev, pipe);
8676
8677 dpll = I915_READ(dpll_reg);
8678 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8679 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8680 }
8681 }
8682
8683 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8684 {
8685 struct drm_device *dev = crtc->dev;
8686 struct drm_i915_private *dev_priv = dev->dev_private;
8687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8688
8689 if (HAS_PCH_SPLIT(dev))
8690 return;
8691
8692 if (!dev_priv->lvds_downclock_avail)
8693 return;
8694
8695 /*
8696 * Since this is called by a timer, we should never get here in
8697 * the manual case.
8698 */
8699 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8700 int pipe = intel_crtc->pipe;
8701 int dpll_reg = DPLL(pipe);
8702 int dpll;
8703
8704 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8705
8706 assert_panel_unlocked(dev_priv, pipe);
8707
8708 dpll = I915_READ(dpll_reg);
8709 dpll |= DISPLAY_RATE_SELECT_FPA1;
8710 I915_WRITE(dpll_reg, dpll);
8711 intel_wait_for_vblank(dev, pipe);
8712 dpll = I915_READ(dpll_reg);
8713 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8714 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8715 }
8716
8717 }
8718
8719 void intel_mark_busy(struct drm_device *dev)
8720 {
8721 struct drm_i915_private *dev_priv = dev->dev_private;
8722
8723 if (dev_priv->mm.busy)
8724 return;
8725
8726 intel_runtime_pm_get(dev_priv);
8727 i915_update_gfx_val(dev_priv);
8728 dev_priv->mm.busy = true;
8729 }
8730
8731 void intel_mark_idle(struct drm_device *dev)
8732 {
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734 struct drm_crtc *crtc;
8735
8736 if (!dev_priv->mm.busy)
8737 return;
8738
8739 dev_priv->mm.busy = false;
8740
8741 if (!i915.powersave)
8742 goto out;
8743
8744 for_each_crtc(dev, crtc) {
8745 if (!crtc->primary->fb)
8746 continue;
8747
8748 intel_decrease_pllclock(crtc);
8749 }
8750
8751 if (INTEL_INFO(dev)->gen >= 6)
8752 gen6_rps_idle(dev->dev_private);
8753
8754 out:
8755 intel_runtime_pm_put(dev_priv);
8756 }
8757
8758 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8759 struct intel_engine_cs *ring)
8760 {
8761 struct drm_device *dev = obj->base.dev;
8762 struct drm_crtc *crtc;
8763
8764 if (!i915.powersave)
8765 return;
8766
8767 for_each_crtc(dev, crtc) {
8768 if (!crtc->primary->fb)
8769 continue;
8770
8771 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8772 continue;
8773
8774 intel_increase_pllclock(crtc);
8775 if (ring && intel_fbc_enabled(dev))
8776 ring->fbc_dirty = true;
8777 }
8778 }
8779
8780 static void intel_crtc_destroy(struct drm_crtc *crtc)
8781 {
8782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8783 struct drm_device *dev = crtc->dev;
8784 struct intel_unpin_work *work;
8785 unsigned long flags;
8786
8787 spin_lock_irqsave(&dev->event_lock, flags);
8788 work = intel_crtc->unpin_work;
8789 intel_crtc->unpin_work = NULL;
8790 spin_unlock_irqrestore(&dev->event_lock, flags);
8791
8792 if (work) {
8793 cancel_work_sync(&work->work);
8794 kfree(work);
8795 }
8796
8797 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8798
8799 drm_crtc_cleanup(crtc);
8800
8801 kfree(intel_crtc);
8802 }
8803
8804 static void intel_unpin_work_fn(struct work_struct *__work)
8805 {
8806 struct intel_unpin_work *work =
8807 container_of(__work, struct intel_unpin_work, work);
8808 struct drm_device *dev = work->crtc->dev;
8809
8810 mutex_lock(&dev->struct_mutex);
8811 intel_unpin_fb_obj(work->old_fb_obj);
8812 drm_gem_object_unreference(&work->pending_flip_obj->base);
8813 drm_gem_object_unreference(&work->old_fb_obj->base);
8814
8815 intel_update_fbc(dev);
8816 mutex_unlock(&dev->struct_mutex);
8817
8818 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8819 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8820
8821 kfree(work);
8822 }
8823
8824 static void do_intel_finish_page_flip(struct drm_device *dev,
8825 struct drm_crtc *crtc)
8826 {
8827 struct drm_i915_private *dev_priv = dev->dev_private;
8828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8829 struct intel_unpin_work *work;
8830 unsigned long flags;
8831
8832 /* Ignore early vblank irqs */
8833 if (intel_crtc == NULL)
8834 return;
8835
8836 spin_lock_irqsave(&dev->event_lock, flags);
8837 work = intel_crtc->unpin_work;
8838
8839 /* Ensure we don't miss a work->pending update ... */
8840 smp_rmb();
8841
8842 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8843 spin_unlock_irqrestore(&dev->event_lock, flags);
8844 return;
8845 }
8846
8847 /* and that the unpin work is consistent wrt ->pending. */
8848 smp_rmb();
8849
8850 intel_crtc->unpin_work = NULL;
8851
8852 if (work->event)
8853 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8854
8855 drm_crtc_vblank_put(crtc);
8856
8857 spin_unlock_irqrestore(&dev->event_lock, flags);
8858
8859 wake_up_all(&dev_priv->pending_flip_queue);
8860
8861 queue_work(dev_priv->wq, &work->work);
8862
8863 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8864 }
8865
8866 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8867 {
8868 struct drm_i915_private *dev_priv = dev->dev_private;
8869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8870
8871 do_intel_finish_page_flip(dev, crtc);
8872 }
8873
8874 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8875 {
8876 struct drm_i915_private *dev_priv = dev->dev_private;
8877 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8878
8879 do_intel_finish_page_flip(dev, crtc);
8880 }
8881
8882 /* Is 'a' after or equal to 'b'? */
8883 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8884 {
8885 return !((a - b) & 0x80000000);
8886 }
8887
8888 static bool page_flip_finished(struct intel_crtc *crtc)
8889 {
8890 struct drm_device *dev = crtc->base.dev;
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892
8893 /*
8894 * The relevant registers doen't exist on pre-ctg.
8895 * As the flip done interrupt doesn't trigger for mmio
8896 * flips on gmch platforms, a flip count check isn't
8897 * really needed there. But since ctg has the registers,
8898 * include it in the check anyway.
8899 */
8900 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8901 return true;
8902
8903 /*
8904 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8905 * used the same base address. In that case the mmio flip might
8906 * have completed, but the CS hasn't even executed the flip yet.
8907 *
8908 * A flip count check isn't enough as the CS might have updated
8909 * the base address just after start of vblank, but before we
8910 * managed to process the interrupt. This means we'd complete the
8911 * CS flip too soon.
8912 *
8913 * Combining both checks should get us a good enough result. It may
8914 * still happen that the CS flip has been executed, but has not
8915 * yet actually completed. But in case the base address is the same
8916 * anyway, we don't really care.
8917 */
8918 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8919 crtc->unpin_work->gtt_offset &&
8920 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8921 crtc->unpin_work->flip_count);
8922 }
8923
8924 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8925 {
8926 struct drm_i915_private *dev_priv = dev->dev_private;
8927 struct intel_crtc *intel_crtc =
8928 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8929 unsigned long flags;
8930
8931 /* NB: An MMIO update of the plane base pointer will also
8932 * generate a page-flip completion irq, i.e. every modeset
8933 * is also accompanied by a spurious intel_prepare_page_flip().
8934 */
8935 spin_lock_irqsave(&dev->event_lock, flags);
8936 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8937 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8938 spin_unlock_irqrestore(&dev->event_lock, flags);
8939 }
8940
8941 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8942 {
8943 /* Ensure that the work item is consistent when activating it ... */
8944 smp_wmb();
8945 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8946 /* and that it is marked active as soon as the irq could fire. */
8947 smp_wmb();
8948 }
8949
8950 static int intel_gen2_queue_flip(struct drm_device *dev,
8951 struct drm_crtc *crtc,
8952 struct drm_framebuffer *fb,
8953 struct drm_i915_gem_object *obj,
8954 struct intel_engine_cs *ring,
8955 uint32_t flags)
8956 {
8957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8958 u32 flip_mask;
8959 int ret;
8960
8961 ret = intel_ring_begin(ring, 6);
8962 if (ret)
8963 return ret;
8964
8965 /* Can't queue multiple flips, so wait for the previous
8966 * one to finish before executing the next.
8967 */
8968 if (intel_crtc->plane)
8969 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8970 else
8971 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8972 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8973 intel_ring_emit(ring, MI_NOOP);
8974 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8975 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8976 intel_ring_emit(ring, fb->pitches[0]);
8977 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8978 intel_ring_emit(ring, 0); /* aux display base address, unused */
8979
8980 intel_mark_page_flip_active(intel_crtc);
8981 __intel_ring_advance(ring);
8982 return 0;
8983 }
8984
8985 static int intel_gen3_queue_flip(struct drm_device *dev,
8986 struct drm_crtc *crtc,
8987 struct drm_framebuffer *fb,
8988 struct drm_i915_gem_object *obj,
8989 struct intel_engine_cs *ring,
8990 uint32_t flags)
8991 {
8992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8993 u32 flip_mask;
8994 int ret;
8995
8996 ret = intel_ring_begin(ring, 6);
8997 if (ret)
8998 return ret;
8999
9000 if (intel_crtc->plane)
9001 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9002 else
9003 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9004 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9005 intel_ring_emit(ring, MI_NOOP);
9006 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9007 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9008 intel_ring_emit(ring, fb->pitches[0]);
9009 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9010 intel_ring_emit(ring, MI_NOOP);
9011
9012 intel_mark_page_flip_active(intel_crtc);
9013 __intel_ring_advance(ring);
9014 return 0;
9015 }
9016
9017 static int intel_gen4_queue_flip(struct drm_device *dev,
9018 struct drm_crtc *crtc,
9019 struct drm_framebuffer *fb,
9020 struct drm_i915_gem_object *obj,
9021 struct intel_engine_cs *ring,
9022 uint32_t flags)
9023 {
9024 struct drm_i915_private *dev_priv = dev->dev_private;
9025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9026 uint32_t pf, pipesrc;
9027 int ret;
9028
9029 ret = intel_ring_begin(ring, 4);
9030 if (ret)
9031 return ret;
9032
9033 /* i965+ uses the linear or tiled offsets from the
9034 * Display Registers (which do not change across a page-flip)
9035 * so we need only reprogram the base address.
9036 */
9037 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9038 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9039 intel_ring_emit(ring, fb->pitches[0]);
9040 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9041 obj->tiling_mode);
9042
9043 /* XXX Enabling the panel-fitter across page-flip is so far
9044 * untested on non-native modes, so ignore it for now.
9045 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9046 */
9047 pf = 0;
9048 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9049 intel_ring_emit(ring, pf | pipesrc);
9050
9051 intel_mark_page_flip_active(intel_crtc);
9052 __intel_ring_advance(ring);
9053 return 0;
9054 }
9055
9056 static int intel_gen6_queue_flip(struct drm_device *dev,
9057 struct drm_crtc *crtc,
9058 struct drm_framebuffer *fb,
9059 struct drm_i915_gem_object *obj,
9060 struct intel_engine_cs *ring,
9061 uint32_t flags)
9062 {
9063 struct drm_i915_private *dev_priv = dev->dev_private;
9064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9065 uint32_t pf, pipesrc;
9066 int ret;
9067
9068 ret = intel_ring_begin(ring, 4);
9069 if (ret)
9070 return ret;
9071
9072 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9073 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9074 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9075 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9076
9077 /* Contrary to the suggestions in the documentation,
9078 * "Enable Panel Fitter" does not seem to be required when page
9079 * flipping with a non-native mode, and worse causes a normal
9080 * modeset to fail.
9081 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9082 */
9083 pf = 0;
9084 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9085 intel_ring_emit(ring, pf | pipesrc);
9086
9087 intel_mark_page_flip_active(intel_crtc);
9088 __intel_ring_advance(ring);
9089 return 0;
9090 }
9091
9092 static int intel_gen7_queue_flip(struct drm_device *dev,
9093 struct drm_crtc *crtc,
9094 struct drm_framebuffer *fb,
9095 struct drm_i915_gem_object *obj,
9096 struct intel_engine_cs *ring,
9097 uint32_t flags)
9098 {
9099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9100 uint32_t plane_bit = 0;
9101 int len, ret;
9102
9103 switch (intel_crtc->plane) {
9104 case PLANE_A:
9105 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9106 break;
9107 case PLANE_B:
9108 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9109 break;
9110 case PLANE_C:
9111 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9112 break;
9113 default:
9114 WARN_ONCE(1, "unknown plane in flip command\n");
9115 return -ENODEV;
9116 }
9117
9118 len = 4;
9119 if (ring->id == RCS) {
9120 len += 6;
9121 /*
9122 * On Gen 8, SRM is now taking an extra dword to accommodate
9123 * 48bits addresses, and we need a NOOP for the batch size to
9124 * stay even.
9125 */
9126 if (IS_GEN8(dev))
9127 len += 2;
9128 }
9129
9130 /*
9131 * BSpec MI_DISPLAY_FLIP for IVB:
9132 * "The full packet must be contained within the same cache line."
9133 *
9134 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9135 * cacheline, if we ever start emitting more commands before
9136 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9137 * then do the cacheline alignment, and finally emit the
9138 * MI_DISPLAY_FLIP.
9139 */
9140 ret = intel_ring_cacheline_align(ring);
9141 if (ret)
9142 return ret;
9143
9144 ret = intel_ring_begin(ring, len);
9145 if (ret)
9146 return ret;
9147
9148 /* Unmask the flip-done completion message. Note that the bspec says that
9149 * we should do this for both the BCS and RCS, and that we must not unmask
9150 * more than one flip event at any time (or ensure that one flip message
9151 * can be sent by waiting for flip-done prior to queueing new flips).
9152 * Experimentation says that BCS works despite DERRMR masking all
9153 * flip-done completion events and that unmasking all planes at once
9154 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9155 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9156 */
9157 if (ring->id == RCS) {
9158 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9159 intel_ring_emit(ring, DERRMR);
9160 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9161 DERRMR_PIPEB_PRI_FLIP_DONE |
9162 DERRMR_PIPEC_PRI_FLIP_DONE));
9163 if (IS_GEN8(dev))
9164 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9165 MI_SRM_LRM_GLOBAL_GTT);
9166 else
9167 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9168 MI_SRM_LRM_GLOBAL_GTT);
9169 intel_ring_emit(ring, DERRMR);
9170 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9171 if (IS_GEN8(dev)) {
9172 intel_ring_emit(ring, 0);
9173 intel_ring_emit(ring, MI_NOOP);
9174 }
9175 }
9176
9177 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9178 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9179 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9180 intel_ring_emit(ring, (MI_NOOP));
9181
9182 intel_mark_page_flip_active(intel_crtc);
9183 __intel_ring_advance(ring);
9184 return 0;
9185 }
9186
9187 static int intel_default_queue_flip(struct drm_device *dev,
9188 struct drm_crtc *crtc,
9189 struct drm_framebuffer *fb,
9190 struct drm_i915_gem_object *obj,
9191 struct intel_engine_cs *ring,
9192 uint32_t flags)
9193 {
9194 return -ENODEV;
9195 }
9196
9197 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9198 struct drm_framebuffer *fb,
9199 struct drm_pending_vblank_event *event,
9200 uint32_t page_flip_flags)
9201 {
9202 struct drm_device *dev = crtc->dev;
9203 struct drm_i915_private *dev_priv = dev->dev_private;
9204 struct drm_framebuffer *old_fb = crtc->primary->fb;
9205 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9207 struct intel_unpin_work *work;
9208 struct intel_engine_cs *ring;
9209 unsigned long flags;
9210 int ret;
9211
9212 /* Can't change pixel format via MI display flips. */
9213 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9214 return -EINVAL;
9215
9216 /*
9217 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9218 * Note that pitch changes could also affect these register.
9219 */
9220 if (INTEL_INFO(dev)->gen > 3 &&
9221 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9222 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9223 return -EINVAL;
9224
9225 if (i915_terminally_wedged(&dev_priv->gpu_error))
9226 goto out_hang;
9227
9228 work = kzalloc(sizeof(*work), GFP_KERNEL);
9229 if (work == NULL)
9230 return -ENOMEM;
9231
9232 work->event = event;
9233 work->crtc = crtc;
9234 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9235 INIT_WORK(&work->work, intel_unpin_work_fn);
9236
9237 ret = drm_crtc_vblank_get(crtc);
9238 if (ret)
9239 goto free_work;
9240
9241 /* We borrow the event spin lock for protecting unpin_work */
9242 spin_lock_irqsave(&dev->event_lock, flags);
9243 if (intel_crtc->unpin_work) {
9244 spin_unlock_irqrestore(&dev->event_lock, flags);
9245 kfree(work);
9246 drm_crtc_vblank_put(crtc);
9247
9248 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9249 return -EBUSY;
9250 }
9251 intel_crtc->unpin_work = work;
9252 spin_unlock_irqrestore(&dev->event_lock, flags);
9253
9254 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9255 flush_workqueue(dev_priv->wq);
9256
9257 ret = i915_mutex_lock_interruptible(dev);
9258 if (ret)
9259 goto cleanup;
9260
9261 /* Reference the objects for the scheduled work. */
9262 drm_gem_object_reference(&work->old_fb_obj->base);
9263 drm_gem_object_reference(&obj->base);
9264
9265 crtc->primary->fb = fb;
9266
9267 work->pending_flip_obj = obj;
9268
9269 work->enable_stall_check = true;
9270
9271 atomic_inc(&intel_crtc->unpin_work_count);
9272 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9273
9274 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9275 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9276
9277 if (IS_VALLEYVIEW(dev)) {
9278 ring = &dev_priv->ring[BCS];
9279 } else if (INTEL_INFO(dev)->gen >= 7) {
9280 ring = obj->ring;
9281 if (ring == NULL || ring->id != RCS)
9282 ring = &dev_priv->ring[BCS];
9283 } else {
9284 ring = &dev_priv->ring[RCS];
9285 }
9286
9287 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9288 if (ret)
9289 goto cleanup_pending;
9290
9291 work->gtt_offset =
9292 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9293
9294 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9295 if (ret)
9296 goto cleanup_unpin;
9297
9298 intel_disable_fbc(dev);
9299 intel_mark_fb_busy(obj, NULL);
9300 mutex_unlock(&dev->struct_mutex);
9301
9302 trace_i915_flip_request(intel_crtc->plane, obj);
9303
9304 return 0;
9305
9306 cleanup_unpin:
9307 intel_unpin_fb_obj(obj);
9308 cleanup_pending:
9309 atomic_dec(&intel_crtc->unpin_work_count);
9310 crtc->primary->fb = old_fb;
9311 drm_gem_object_unreference(&work->old_fb_obj->base);
9312 drm_gem_object_unreference(&obj->base);
9313 mutex_unlock(&dev->struct_mutex);
9314
9315 cleanup:
9316 spin_lock_irqsave(&dev->event_lock, flags);
9317 intel_crtc->unpin_work = NULL;
9318 spin_unlock_irqrestore(&dev->event_lock, flags);
9319
9320 drm_crtc_vblank_put(crtc);
9321 free_work:
9322 kfree(work);
9323
9324 if (ret == -EIO) {
9325 out_hang:
9326 intel_crtc_wait_for_pending_flips(crtc);
9327 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9328 if (ret == 0 && event)
9329 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9330 }
9331 return ret;
9332 }
9333
9334 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9335 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9336 .load_lut = intel_crtc_load_lut,
9337 };
9338
9339 /**
9340 * intel_modeset_update_staged_output_state
9341 *
9342 * Updates the staged output configuration state, e.g. after we've read out the
9343 * current hw state.
9344 */
9345 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9346 {
9347 struct intel_crtc *crtc;
9348 struct intel_encoder *encoder;
9349 struct intel_connector *connector;
9350
9351 list_for_each_entry(connector, &dev->mode_config.connector_list,
9352 base.head) {
9353 connector->new_encoder =
9354 to_intel_encoder(connector->base.encoder);
9355 }
9356
9357 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9358 base.head) {
9359 encoder->new_crtc =
9360 to_intel_crtc(encoder->base.crtc);
9361 }
9362
9363 for_each_intel_crtc(dev, crtc) {
9364 crtc->new_enabled = crtc->base.enabled;
9365
9366 if (crtc->new_enabled)
9367 crtc->new_config = &crtc->config;
9368 else
9369 crtc->new_config = NULL;
9370 }
9371 }
9372
9373 /**
9374 * intel_modeset_commit_output_state
9375 *
9376 * This function copies the stage display pipe configuration to the real one.
9377 */
9378 static void intel_modeset_commit_output_state(struct drm_device *dev)
9379 {
9380 struct intel_crtc *crtc;
9381 struct intel_encoder *encoder;
9382 struct intel_connector *connector;
9383
9384 list_for_each_entry(connector, &dev->mode_config.connector_list,
9385 base.head) {
9386 connector->base.encoder = &connector->new_encoder->base;
9387 }
9388
9389 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9390 base.head) {
9391 encoder->base.crtc = &encoder->new_crtc->base;
9392 }
9393
9394 for_each_intel_crtc(dev, crtc) {
9395 crtc->base.enabled = crtc->new_enabled;
9396 }
9397 }
9398
9399 static void
9400 connected_sink_compute_bpp(struct intel_connector *connector,
9401 struct intel_crtc_config *pipe_config)
9402 {
9403 int bpp = pipe_config->pipe_bpp;
9404
9405 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9406 connector->base.base.id,
9407 drm_get_connector_name(&connector->base));
9408
9409 /* Don't use an invalid EDID bpc value */
9410 if (connector->base.display_info.bpc &&
9411 connector->base.display_info.bpc * 3 < bpp) {
9412 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9413 bpp, connector->base.display_info.bpc*3);
9414 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9415 }
9416
9417 /* Clamp bpp to 8 on screens without EDID 1.4 */
9418 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9419 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9420 bpp);
9421 pipe_config->pipe_bpp = 24;
9422 }
9423 }
9424
9425 static int
9426 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9427 struct drm_framebuffer *fb,
9428 struct intel_crtc_config *pipe_config)
9429 {
9430 struct drm_device *dev = crtc->base.dev;
9431 struct intel_connector *connector;
9432 int bpp;
9433
9434 switch (fb->pixel_format) {
9435 case DRM_FORMAT_C8:
9436 bpp = 8*3; /* since we go through a colormap */
9437 break;
9438 case DRM_FORMAT_XRGB1555:
9439 case DRM_FORMAT_ARGB1555:
9440 /* checked in intel_framebuffer_init already */
9441 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9442 return -EINVAL;
9443 case DRM_FORMAT_RGB565:
9444 bpp = 6*3; /* min is 18bpp */
9445 break;
9446 case DRM_FORMAT_XBGR8888:
9447 case DRM_FORMAT_ABGR8888:
9448 /* checked in intel_framebuffer_init already */
9449 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9450 return -EINVAL;
9451 case DRM_FORMAT_XRGB8888:
9452 case DRM_FORMAT_ARGB8888:
9453 bpp = 8*3;
9454 break;
9455 case DRM_FORMAT_XRGB2101010:
9456 case DRM_FORMAT_ARGB2101010:
9457 case DRM_FORMAT_XBGR2101010:
9458 case DRM_FORMAT_ABGR2101010:
9459 /* checked in intel_framebuffer_init already */
9460 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9461 return -EINVAL;
9462 bpp = 10*3;
9463 break;
9464 /* TODO: gen4+ supports 16 bpc floating point, too. */
9465 default:
9466 DRM_DEBUG_KMS("unsupported depth\n");
9467 return -EINVAL;
9468 }
9469
9470 pipe_config->pipe_bpp = bpp;
9471
9472 /* Clamp display bpp to EDID value */
9473 list_for_each_entry(connector, &dev->mode_config.connector_list,
9474 base.head) {
9475 if (!connector->new_encoder ||
9476 connector->new_encoder->new_crtc != crtc)
9477 continue;
9478
9479 connected_sink_compute_bpp(connector, pipe_config);
9480 }
9481
9482 return bpp;
9483 }
9484
9485 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9486 {
9487 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9488 "type: 0x%x flags: 0x%x\n",
9489 mode->crtc_clock,
9490 mode->crtc_hdisplay, mode->crtc_hsync_start,
9491 mode->crtc_hsync_end, mode->crtc_htotal,
9492 mode->crtc_vdisplay, mode->crtc_vsync_start,
9493 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9494 }
9495
9496 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9497 struct intel_crtc_config *pipe_config,
9498 const char *context)
9499 {
9500 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9501 context, pipe_name(crtc->pipe));
9502
9503 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9504 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9505 pipe_config->pipe_bpp, pipe_config->dither);
9506 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9507 pipe_config->has_pch_encoder,
9508 pipe_config->fdi_lanes,
9509 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9510 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9511 pipe_config->fdi_m_n.tu);
9512 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9513 pipe_config->has_dp_encoder,
9514 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9515 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9516 pipe_config->dp_m_n.tu);
9517 DRM_DEBUG_KMS("requested mode:\n");
9518 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9519 DRM_DEBUG_KMS("adjusted mode:\n");
9520 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9521 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9522 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9523 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9524 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9525 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9526 pipe_config->gmch_pfit.control,
9527 pipe_config->gmch_pfit.pgm_ratios,
9528 pipe_config->gmch_pfit.lvds_border_bits);
9529 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9530 pipe_config->pch_pfit.pos,
9531 pipe_config->pch_pfit.size,
9532 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9533 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9534 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9535 }
9536
9537 static bool encoders_cloneable(const struct intel_encoder *a,
9538 const struct intel_encoder *b)
9539 {
9540 /* masks could be asymmetric, so check both ways */
9541 return a == b || (a->cloneable & (1 << b->type) &&
9542 b->cloneable & (1 << a->type));
9543 }
9544
9545 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9546 struct intel_encoder *encoder)
9547 {
9548 struct drm_device *dev = crtc->base.dev;
9549 struct intel_encoder *source_encoder;
9550
9551 list_for_each_entry(source_encoder,
9552 &dev->mode_config.encoder_list, base.head) {
9553 if (source_encoder->new_crtc != crtc)
9554 continue;
9555
9556 if (!encoders_cloneable(encoder, source_encoder))
9557 return false;
9558 }
9559
9560 return true;
9561 }
9562
9563 static bool check_encoder_cloning(struct intel_crtc *crtc)
9564 {
9565 struct drm_device *dev = crtc->base.dev;
9566 struct intel_encoder *encoder;
9567
9568 list_for_each_entry(encoder,
9569 &dev->mode_config.encoder_list, base.head) {
9570 if (encoder->new_crtc != crtc)
9571 continue;
9572
9573 if (!check_single_encoder_cloning(crtc, encoder))
9574 return false;
9575 }
9576
9577 return true;
9578 }
9579
9580 static struct intel_crtc_config *
9581 intel_modeset_pipe_config(struct drm_crtc *crtc,
9582 struct drm_framebuffer *fb,
9583 struct drm_display_mode *mode)
9584 {
9585 struct drm_device *dev = crtc->dev;
9586 struct intel_encoder *encoder;
9587 struct intel_crtc_config *pipe_config;
9588 int plane_bpp, ret = -EINVAL;
9589 bool retry = true;
9590
9591 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9592 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9593 return ERR_PTR(-EINVAL);
9594 }
9595
9596 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9597 if (!pipe_config)
9598 return ERR_PTR(-ENOMEM);
9599
9600 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9601 drm_mode_copy(&pipe_config->requested_mode, mode);
9602
9603 pipe_config->cpu_transcoder =
9604 (enum transcoder) to_intel_crtc(crtc)->pipe;
9605 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9606
9607 /*
9608 * Sanitize sync polarity flags based on requested ones. If neither
9609 * positive or negative polarity is requested, treat this as meaning
9610 * negative polarity.
9611 */
9612 if (!(pipe_config->adjusted_mode.flags &
9613 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9614 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9615
9616 if (!(pipe_config->adjusted_mode.flags &
9617 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9618 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9619
9620 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9621 * plane pixel format and any sink constraints into account. Returns the
9622 * source plane bpp so that dithering can be selected on mismatches
9623 * after encoders and crtc also have had their say. */
9624 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9625 fb, pipe_config);
9626 if (plane_bpp < 0)
9627 goto fail;
9628
9629 /*
9630 * Determine the real pipe dimensions. Note that stereo modes can
9631 * increase the actual pipe size due to the frame doubling and
9632 * insertion of additional space for blanks between the frame. This
9633 * is stored in the crtc timings. We use the requested mode to do this
9634 * computation to clearly distinguish it from the adjusted mode, which
9635 * can be changed by the connectors in the below retry loop.
9636 */
9637 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9638 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9639 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9640
9641 encoder_retry:
9642 /* Ensure the port clock defaults are reset when retrying. */
9643 pipe_config->port_clock = 0;
9644 pipe_config->pixel_multiplier = 1;
9645
9646 /* Fill in default crtc timings, allow encoders to overwrite them. */
9647 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9648
9649 /* Pass our mode to the connectors and the CRTC to give them a chance to
9650 * adjust it according to limitations or connector properties, and also
9651 * a chance to reject the mode entirely.
9652 */
9653 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9654 base.head) {
9655
9656 if (&encoder->new_crtc->base != crtc)
9657 continue;
9658
9659 if (!(encoder->compute_config(encoder, pipe_config))) {
9660 DRM_DEBUG_KMS("Encoder config failure\n");
9661 goto fail;
9662 }
9663 }
9664
9665 /* Set default port clock if not overwritten by the encoder. Needs to be
9666 * done afterwards in case the encoder adjusts the mode. */
9667 if (!pipe_config->port_clock)
9668 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9669 * pipe_config->pixel_multiplier;
9670
9671 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9672 if (ret < 0) {
9673 DRM_DEBUG_KMS("CRTC fixup failed\n");
9674 goto fail;
9675 }
9676
9677 if (ret == RETRY) {
9678 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9679 ret = -EINVAL;
9680 goto fail;
9681 }
9682
9683 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9684 retry = false;
9685 goto encoder_retry;
9686 }
9687
9688 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9689 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9690 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9691
9692 return pipe_config;
9693 fail:
9694 kfree(pipe_config);
9695 return ERR_PTR(ret);
9696 }
9697
9698 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9699 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9700 static void
9701 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9702 unsigned *prepare_pipes, unsigned *disable_pipes)
9703 {
9704 struct intel_crtc *intel_crtc;
9705 struct drm_device *dev = crtc->dev;
9706 struct intel_encoder *encoder;
9707 struct intel_connector *connector;
9708 struct drm_crtc *tmp_crtc;
9709
9710 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9711
9712 /* Check which crtcs have changed outputs connected to them, these need
9713 * to be part of the prepare_pipes mask. We don't (yet) support global
9714 * modeset across multiple crtcs, so modeset_pipes will only have one
9715 * bit set at most. */
9716 list_for_each_entry(connector, &dev->mode_config.connector_list,
9717 base.head) {
9718 if (connector->base.encoder == &connector->new_encoder->base)
9719 continue;
9720
9721 if (connector->base.encoder) {
9722 tmp_crtc = connector->base.encoder->crtc;
9723
9724 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9725 }
9726
9727 if (connector->new_encoder)
9728 *prepare_pipes |=
9729 1 << connector->new_encoder->new_crtc->pipe;
9730 }
9731
9732 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9733 base.head) {
9734 if (encoder->base.crtc == &encoder->new_crtc->base)
9735 continue;
9736
9737 if (encoder->base.crtc) {
9738 tmp_crtc = encoder->base.crtc;
9739
9740 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9741 }
9742
9743 if (encoder->new_crtc)
9744 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9745 }
9746
9747 /* Check for pipes that will be enabled/disabled ... */
9748 for_each_intel_crtc(dev, intel_crtc) {
9749 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9750 continue;
9751
9752 if (!intel_crtc->new_enabled)
9753 *disable_pipes |= 1 << intel_crtc->pipe;
9754 else
9755 *prepare_pipes |= 1 << intel_crtc->pipe;
9756 }
9757
9758
9759 /* set_mode is also used to update properties on life display pipes. */
9760 intel_crtc = to_intel_crtc(crtc);
9761 if (intel_crtc->new_enabled)
9762 *prepare_pipes |= 1 << intel_crtc->pipe;
9763
9764 /*
9765 * For simplicity do a full modeset on any pipe where the output routing
9766 * changed. We could be more clever, but that would require us to be
9767 * more careful with calling the relevant encoder->mode_set functions.
9768 */
9769 if (*prepare_pipes)
9770 *modeset_pipes = *prepare_pipes;
9771
9772 /* ... and mask these out. */
9773 *modeset_pipes &= ~(*disable_pipes);
9774 *prepare_pipes &= ~(*disable_pipes);
9775
9776 /*
9777 * HACK: We don't (yet) fully support global modesets. intel_set_config
9778 * obies this rule, but the modeset restore mode of
9779 * intel_modeset_setup_hw_state does not.
9780 */
9781 *modeset_pipes &= 1 << intel_crtc->pipe;
9782 *prepare_pipes &= 1 << intel_crtc->pipe;
9783
9784 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9785 *modeset_pipes, *prepare_pipes, *disable_pipes);
9786 }
9787
9788 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9789 {
9790 struct drm_encoder *encoder;
9791 struct drm_device *dev = crtc->dev;
9792
9793 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9794 if (encoder->crtc == crtc)
9795 return true;
9796
9797 return false;
9798 }
9799
9800 static void
9801 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9802 {
9803 struct intel_encoder *intel_encoder;
9804 struct intel_crtc *intel_crtc;
9805 struct drm_connector *connector;
9806
9807 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9808 base.head) {
9809 if (!intel_encoder->base.crtc)
9810 continue;
9811
9812 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9813
9814 if (prepare_pipes & (1 << intel_crtc->pipe))
9815 intel_encoder->connectors_active = false;
9816 }
9817
9818 intel_modeset_commit_output_state(dev);
9819
9820 /* Double check state. */
9821 for_each_intel_crtc(dev, intel_crtc) {
9822 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9823 WARN_ON(intel_crtc->new_config &&
9824 intel_crtc->new_config != &intel_crtc->config);
9825 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9826 }
9827
9828 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9829 if (!connector->encoder || !connector->encoder->crtc)
9830 continue;
9831
9832 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9833
9834 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9835 struct drm_property *dpms_property =
9836 dev->mode_config.dpms_property;
9837
9838 connector->dpms = DRM_MODE_DPMS_ON;
9839 drm_object_property_set_value(&connector->base,
9840 dpms_property,
9841 DRM_MODE_DPMS_ON);
9842
9843 intel_encoder = to_intel_encoder(connector->encoder);
9844 intel_encoder->connectors_active = true;
9845 }
9846 }
9847
9848 }
9849
9850 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9851 {
9852 int diff;
9853
9854 if (clock1 == clock2)
9855 return true;
9856
9857 if (!clock1 || !clock2)
9858 return false;
9859
9860 diff = abs(clock1 - clock2);
9861
9862 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9863 return true;
9864
9865 return false;
9866 }
9867
9868 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9869 list_for_each_entry((intel_crtc), \
9870 &(dev)->mode_config.crtc_list, \
9871 base.head) \
9872 if (mask & (1 <<(intel_crtc)->pipe))
9873
9874 static bool
9875 intel_pipe_config_compare(struct drm_device *dev,
9876 struct intel_crtc_config *current_config,
9877 struct intel_crtc_config *pipe_config)
9878 {
9879 #define PIPE_CONF_CHECK_X(name) \
9880 if (current_config->name != pipe_config->name) { \
9881 DRM_ERROR("mismatch in " #name " " \
9882 "(expected 0x%08x, found 0x%08x)\n", \
9883 current_config->name, \
9884 pipe_config->name); \
9885 return false; \
9886 }
9887
9888 #define PIPE_CONF_CHECK_I(name) \
9889 if (current_config->name != pipe_config->name) { \
9890 DRM_ERROR("mismatch in " #name " " \
9891 "(expected %i, found %i)\n", \
9892 current_config->name, \
9893 pipe_config->name); \
9894 return false; \
9895 }
9896
9897 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9898 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9899 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9900 "(expected %i, found %i)\n", \
9901 current_config->name & (mask), \
9902 pipe_config->name & (mask)); \
9903 return false; \
9904 }
9905
9906 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9907 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9908 DRM_ERROR("mismatch in " #name " " \
9909 "(expected %i, found %i)\n", \
9910 current_config->name, \
9911 pipe_config->name); \
9912 return false; \
9913 }
9914
9915 #define PIPE_CONF_QUIRK(quirk) \
9916 ((current_config->quirks | pipe_config->quirks) & (quirk))
9917
9918 PIPE_CONF_CHECK_I(cpu_transcoder);
9919
9920 PIPE_CONF_CHECK_I(has_pch_encoder);
9921 PIPE_CONF_CHECK_I(fdi_lanes);
9922 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9923 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9924 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9925 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9926 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9927
9928 PIPE_CONF_CHECK_I(has_dp_encoder);
9929 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9930 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9931 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9932 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9933 PIPE_CONF_CHECK_I(dp_m_n.tu);
9934
9935 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9936 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9937 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9938 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9939 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9940 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9941
9942 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9943 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9944 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9945 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9946 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9947 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9948
9949 PIPE_CONF_CHECK_I(pixel_multiplier);
9950 PIPE_CONF_CHECK_I(has_hdmi_sink);
9951 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9952 IS_VALLEYVIEW(dev))
9953 PIPE_CONF_CHECK_I(limited_color_range);
9954
9955 PIPE_CONF_CHECK_I(has_audio);
9956
9957 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9958 DRM_MODE_FLAG_INTERLACE);
9959
9960 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9961 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9962 DRM_MODE_FLAG_PHSYNC);
9963 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9964 DRM_MODE_FLAG_NHSYNC);
9965 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9966 DRM_MODE_FLAG_PVSYNC);
9967 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9968 DRM_MODE_FLAG_NVSYNC);
9969 }
9970
9971 PIPE_CONF_CHECK_I(pipe_src_w);
9972 PIPE_CONF_CHECK_I(pipe_src_h);
9973
9974 /*
9975 * FIXME: BIOS likes to set up a cloned config with lvds+external
9976 * screen. Since we don't yet re-compute the pipe config when moving
9977 * just the lvds port away to another pipe the sw tracking won't match.
9978 *
9979 * Proper atomic modesets with recomputed global state will fix this.
9980 * Until then just don't check gmch state for inherited modes.
9981 */
9982 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9983 PIPE_CONF_CHECK_I(gmch_pfit.control);
9984 /* pfit ratios are autocomputed by the hw on gen4+ */
9985 if (INTEL_INFO(dev)->gen < 4)
9986 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9987 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9988 }
9989
9990 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9991 if (current_config->pch_pfit.enabled) {
9992 PIPE_CONF_CHECK_I(pch_pfit.pos);
9993 PIPE_CONF_CHECK_I(pch_pfit.size);
9994 }
9995
9996 /* BDW+ don't expose a synchronous way to read the state */
9997 if (IS_HASWELL(dev))
9998 PIPE_CONF_CHECK_I(ips_enabled);
9999
10000 PIPE_CONF_CHECK_I(double_wide);
10001
10002 PIPE_CONF_CHECK_I(shared_dpll);
10003 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10004 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10005 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10006 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10007
10008 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10009 PIPE_CONF_CHECK_I(pipe_bpp);
10010
10011 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10012 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10013
10014 #undef PIPE_CONF_CHECK_X
10015 #undef PIPE_CONF_CHECK_I
10016 #undef PIPE_CONF_CHECK_FLAGS
10017 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10018 #undef PIPE_CONF_QUIRK
10019
10020 return true;
10021 }
10022
10023 static void
10024 check_connector_state(struct drm_device *dev)
10025 {
10026 struct intel_connector *connector;
10027
10028 list_for_each_entry(connector, &dev->mode_config.connector_list,
10029 base.head) {
10030 /* This also checks the encoder/connector hw state with the
10031 * ->get_hw_state callbacks. */
10032 intel_connector_check_state(connector);
10033
10034 WARN(&connector->new_encoder->base != connector->base.encoder,
10035 "connector's staged encoder doesn't match current encoder\n");
10036 }
10037 }
10038
10039 static void
10040 check_encoder_state(struct drm_device *dev)
10041 {
10042 struct intel_encoder *encoder;
10043 struct intel_connector *connector;
10044
10045 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10046 base.head) {
10047 bool enabled = false;
10048 bool active = false;
10049 enum pipe pipe, tracked_pipe;
10050
10051 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10052 encoder->base.base.id,
10053 drm_get_encoder_name(&encoder->base));
10054
10055 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10056 "encoder's stage crtc doesn't match current crtc\n");
10057 WARN(encoder->connectors_active && !encoder->base.crtc,
10058 "encoder's active_connectors set, but no crtc\n");
10059
10060 list_for_each_entry(connector, &dev->mode_config.connector_list,
10061 base.head) {
10062 if (connector->base.encoder != &encoder->base)
10063 continue;
10064 enabled = true;
10065 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10066 active = true;
10067 }
10068 WARN(!!encoder->base.crtc != enabled,
10069 "encoder's enabled state mismatch "
10070 "(expected %i, found %i)\n",
10071 !!encoder->base.crtc, enabled);
10072 WARN(active && !encoder->base.crtc,
10073 "active encoder with no crtc\n");
10074
10075 WARN(encoder->connectors_active != active,
10076 "encoder's computed active state doesn't match tracked active state "
10077 "(expected %i, found %i)\n", active, encoder->connectors_active);
10078
10079 active = encoder->get_hw_state(encoder, &pipe);
10080 WARN(active != encoder->connectors_active,
10081 "encoder's hw state doesn't match sw tracking "
10082 "(expected %i, found %i)\n",
10083 encoder->connectors_active, active);
10084
10085 if (!encoder->base.crtc)
10086 continue;
10087
10088 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10089 WARN(active && pipe != tracked_pipe,
10090 "active encoder's pipe doesn't match"
10091 "(expected %i, found %i)\n",
10092 tracked_pipe, pipe);
10093
10094 }
10095 }
10096
10097 static void
10098 check_crtc_state(struct drm_device *dev)
10099 {
10100 struct drm_i915_private *dev_priv = dev->dev_private;
10101 struct intel_crtc *crtc;
10102 struct intel_encoder *encoder;
10103 struct intel_crtc_config pipe_config;
10104
10105 for_each_intel_crtc(dev, crtc) {
10106 bool enabled = false;
10107 bool active = false;
10108
10109 memset(&pipe_config, 0, sizeof(pipe_config));
10110
10111 DRM_DEBUG_KMS("[CRTC:%d]\n",
10112 crtc->base.base.id);
10113
10114 WARN(crtc->active && !crtc->base.enabled,
10115 "active crtc, but not enabled in sw tracking\n");
10116
10117 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10118 base.head) {
10119 if (encoder->base.crtc != &crtc->base)
10120 continue;
10121 enabled = true;
10122 if (encoder->connectors_active)
10123 active = true;
10124 }
10125
10126 WARN(active != crtc->active,
10127 "crtc's computed active state doesn't match tracked active state "
10128 "(expected %i, found %i)\n", active, crtc->active);
10129 WARN(enabled != crtc->base.enabled,
10130 "crtc's computed enabled state doesn't match tracked enabled state "
10131 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10132
10133 active = dev_priv->display.get_pipe_config(crtc,
10134 &pipe_config);
10135
10136 /* hw state is inconsistent with the pipe A quirk */
10137 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10138 active = crtc->active;
10139
10140 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10141 base.head) {
10142 enum pipe pipe;
10143 if (encoder->base.crtc != &crtc->base)
10144 continue;
10145 if (encoder->get_hw_state(encoder, &pipe))
10146 encoder->get_config(encoder, &pipe_config);
10147 }
10148
10149 WARN(crtc->active != active,
10150 "crtc active state doesn't match with hw state "
10151 "(expected %i, found %i)\n", crtc->active, active);
10152
10153 if (active &&
10154 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10155 WARN(1, "pipe state doesn't match!\n");
10156 intel_dump_pipe_config(crtc, &pipe_config,
10157 "[hw state]");
10158 intel_dump_pipe_config(crtc, &crtc->config,
10159 "[sw state]");
10160 }
10161 }
10162 }
10163
10164 static void
10165 check_shared_dpll_state(struct drm_device *dev)
10166 {
10167 struct drm_i915_private *dev_priv = dev->dev_private;
10168 struct intel_crtc *crtc;
10169 struct intel_dpll_hw_state dpll_hw_state;
10170 int i;
10171
10172 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10173 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10174 int enabled_crtcs = 0, active_crtcs = 0;
10175 bool active;
10176
10177 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10178
10179 DRM_DEBUG_KMS("%s\n", pll->name);
10180
10181 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10182
10183 WARN(pll->active > pll->refcount,
10184 "more active pll users than references: %i vs %i\n",
10185 pll->active, pll->refcount);
10186 WARN(pll->active && !pll->on,
10187 "pll in active use but not on in sw tracking\n");
10188 WARN(pll->on && !pll->active,
10189 "pll in on but not on in use in sw tracking\n");
10190 WARN(pll->on != active,
10191 "pll on state mismatch (expected %i, found %i)\n",
10192 pll->on, active);
10193
10194 for_each_intel_crtc(dev, crtc) {
10195 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10196 enabled_crtcs++;
10197 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10198 active_crtcs++;
10199 }
10200 WARN(pll->active != active_crtcs,
10201 "pll active crtcs mismatch (expected %i, found %i)\n",
10202 pll->active, active_crtcs);
10203 WARN(pll->refcount != enabled_crtcs,
10204 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10205 pll->refcount, enabled_crtcs);
10206
10207 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10208 sizeof(dpll_hw_state)),
10209 "pll hw state mismatch\n");
10210 }
10211 }
10212
10213 void
10214 intel_modeset_check_state(struct drm_device *dev)
10215 {
10216 check_connector_state(dev);
10217 check_encoder_state(dev);
10218 check_crtc_state(dev);
10219 check_shared_dpll_state(dev);
10220 }
10221
10222 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10223 int dotclock)
10224 {
10225 /*
10226 * FDI already provided one idea for the dotclock.
10227 * Yell if the encoder disagrees.
10228 */
10229 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10230 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10231 pipe_config->adjusted_mode.crtc_clock, dotclock);
10232 }
10233
10234 static void update_scanline_offset(struct intel_crtc *crtc)
10235 {
10236 struct drm_device *dev = crtc->base.dev;
10237
10238 /*
10239 * The scanline counter increments at the leading edge of hsync.
10240 *
10241 * On most platforms it starts counting from vtotal-1 on the
10242 * first active line. That means the scanline counter value is
10243 * always one less than what we would expect. Ie. just after
10244 * start of vblank, which also occurs at start of hsync (on the
10245 * last active line), the scanline counter will read vblank_start-1.
10246 *
10247 * On gen2 the scanline counter starts counting from 1 instead
10248 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10249 * to keep the value positive), instead of adding one.
10250 *
10251 * On HSW+ the behaviour of the scanline counter depends on the output
10252 * type. For DP ports it behaves like most other platforms, but on HDMI
10253 * there's an extra 1 line difference. So we need to add two instead of
10254 * one to the value.
10255 */
10256 if (IS_GEN2(dev)) {
10257 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10258 int vtotal;
10259
10260 vtotal = mode->crtc_vtotal;
10261 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10262 vtotal /= 2;
10263
10264 crtc->scanline_offset = vtotal - 1;
10265 } else if (HAS_DDI(dev) &&
10266 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10267 crtc->scanline_offset = 2;
10268 } else
10269 crtc->scanline_offset = 1;
10270 }
10271
10272 static int __intel_set_mode(struct drm_crtc *crtc,
10273 struct drm_display_mode *mode,
10274 int x, int y, struct drm_framebuffer *fb)
10275 {
10276 struct drm_device *dev = crtc->dev;
10277 struct drm_i915_private *dev_priv = dev->dev_private;
10278 struct drm_display_mode *saved_mode;
10279 struct intel_crtc_config *pipe_config = NULL;
10280 struct intel_crtc *intel_crtc;
10281 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10282 int ret = 0;
10283
10284 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10285 if (!saved_mode)
10286 return -ENOMEM;
10287
10288 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10289 &prepare_pipes, &disable_pipes);
10290
10291 *saved_mode = crtc->mode;
10292
10293 /* Hack: Because we don't (yet) support global modeset on multiple
10294 * crtcs, we don't keep track of the new mode for more than one crtc.
10295 * Hence simply check whether any bit is set in modeset_pipes in all the
10296 * pieces of code that are not yet converted to deal with mutliple crtcs
10297 * changing their mode at the same time. */
10298 if (modeset_pipes) {
10299 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10300 if (IS_ERR(pipe_config)) {
10301 ret = PTR_ERR(pipe_config);
10302 pipe_config = NULL;
10303
10304 goto out;
10305 }
10306 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10307 "[modeset]");
10308 to_intel_crtc(crtc)->new_config = pipe_config;
10309 }
10310
10311 /*
10312 * See if the config requires any additional preparation, e.g.
10313 * to adjust global state with pipes off. We need to do this
10314 * here so we can get the modeset_pipe updated config for the new
10315 * mode set on this crtc. For other crtcs we need to use the
10316 * adjusted_mode bits in the crtc directly.
10317 */
10318 if (IS_VALLEYVIEW(dev)) {
10319 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10320
10321 /* may have added more to prepare_pipes than we should */
10322 prepare_pipes &= ~disable_pipes;
10323 }
10324
10325 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10326 intel_crtc_disable(&intel_crtc->base);
10327
10328 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10329 if (intel_crtc->base.enabled)
10330 dev_priv->display.crtc_disable(&intel_crtc->base);
10331 }
10332
10333 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10334 * to set it here already despite that we pass it down the callchain.
10335 */
10336 if (modeset_pipes) {
10337 crtc->mode = *mode;
10338 /* mode_set/enable/disable functions rely on a correct pipe
10339 * config. */
10340 to_intel_crtc(crtc)->config = *pipe_config;
10341 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10342
10343 /*
10344 * Calculate and store various constants which
10345 * are later needed by vblank and swap-completion
10346 * timestamping. They are derived from true hwmode.
10347 */
10348 drm_calc_timestamping_constants(crtc,
10349 &pipe_config->adjusted_mode);
10350 }
10351
10352 /* Only after disabling all output pipelines that will be changed can we
10353 * update the the output configuration. */
10354 intel_modeset_update_state(dev, prepare_pipes);
10355
10356 if (dev_priv->display.modeset_global_resources)
10357 dev_priv->display.modeset_global_resources(dev);
10358
10359 /* Set up the DPLL and any encoders state that needs to adjust or depend
10360 * on the DPLL.
10361 */
10362 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10363 struct drm_framebuffer *old_fb;
10364
10365 mutex_lock(&dev->struct_mutex);
10366 ret = intel_pin_and_fence_fb_obj(dev,
10367 to_intel_framebuffer(fb)->obj,
10368 NULL);
10369 if (ret != 0) {
10370 DRM_ERROR("pin & fence failed\n");
10371 mutex_unlock(&dev->struct_mutex);
10372 goto done;
10373 }
10374 old_fb = crtc->primary->fb;
10375 if (old_fb)
10376 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10377 mutex_unlock(&dev->struct_mutex);
10378
10379 crtc->primary->fb = fb;
10380 crtc->x = x;
10381 crtc->y = y;
10382
10383 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10384 x, y, fb);
10385 if (ret)
10386 goto done;
10387 }
10388
10389 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10390 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10391 update_scanline_offset(intel_crtc);
10392
10393 dev_priv->display.crtc_enable(&intel_crtc->base);
10394 }
10395
10396 /* FIXME: add subpixel order */
10397 done:
10398 if (ret && crtc->enabled)
10399 crtc->mode = *saved_mode;
10400
10401 out:
10402 kfree(pipe_config);
10403 kfree(saved_mode);
10404 return ret;
10405 }
10406
10407 static int intel_set_mode(struct drm_crtc *crtc,
10408 struct drm_display_mode *mode,
10409 int x, int y, struct drm_framebuffer *fb)
10410 {
10411 int ret;
10412
10413 ret = __intel_set_mode(crtc, mode, x, y, fb);
10414
10415 if (ret == 0)
10416 intel_modeset_check_state(crtc->dev);
10417
10418 return ret;
10419 }
10420
10421 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10422 {
10423 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10424 }
10425
10426 #undef for_each_intel_crtc_masked
10427
10428 static void intel_set_config_free(struct intel_set_config *config)
10429 {
10430 if (!config)
10431 return;
10432
10433 kfree(config->save_connector_encoders);
10434 kfree(config->save_encoder_crtcs);
10435 kfree(config->save_crtc_enabled);
10436 kfree(config);
10437 }
10438
10439 static int intel_set_config_save_state(struct drm_device *dev,
10440 struct intel_set_config *config)
10441 {
10442 struct drm_crtc *crtc;
10443 struct drm_encoder *encoder;
10444 struct drm_connector *connector;
10445 int count;
10446
10447 config->save_crtc_enabled =
10448 kcalloc(dev->mode_config.num_crtc,
10449 sizeof(bool), GFP_KERNEL);
10450 if (!config->save_crtc_enabled)
10451 return -ENOMEM;
10452
10453 config->save_encoder_crtcs =
10454 kcalloc(dev->mode_config.num_encoder,
10455 sizeof(struct drm_crtc *), GFP_KERNEL);
10456 if (!config->save_encoder_crtcs)
10457 return -ENOMEM;
10458
10459 config->save_connector_encoders =
10460 kcalloc(dev->mode_config.num_connector,
10461 sizeof(struct drm_encoder *), GFP_KERNEL);
10462 if (!config->save_connector_encoders)
10463 return -ENOMEM;
10464
10465 /* Copy data. Note that driver private data is not affected.
10466 * Should anything bad happen only the expected state is
10467 * restored, not the drivers personal bookkeeping.
10468 */
10469 count = 0;
10470 for_each_crtc(dev, crtc) {
10471 config->save_crtc_enabled[count++] = crtc->enabled;
10472 }
10473
10474 count = 0;
10475 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10476 config->save_encoder_crtcs[count++] = encoder->crtc;
10477 }
10478
10479 count = 0;
10480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10481 config->save_connector_encoders[count++] = connector->encoder;
10482 }
10483
10484 return 0;
10485 }
10486
10487 static void intel_set_config_restore_state(struct drm_device *dev,
10488 struct intel_set_config *config)
10489 {
10490 struct intel_crtc *crtc;
10491 struct intel_encoder *encoder;
10492 struct intel_connector *connector;
10493 int count;
10494
10495 count = 0;
10496 for_each_intel_crtc(dev, crtc) {
10497 crtc->new_enabled = config->save_crtc_enabled[count++];
10498
10499 if (crtc->new_enabled)
10500 crtc->new_config = &crtc->config;
10501 else
10502 crtc->new_config = NULL;
10503 }
10504
10505 count = 0;
10506 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10507 encoder->new_crtc =
10508 to_intel_crtc(config->save_encoder_crtcs[count++]);
10509 }
10510
10511 count = 0;
10512 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10513 connector->new_encoder =
10514 to_intel_encoder(config->save_connector_encoders[count++]);
10515 }
10516 }
10517
10518 static bool
10519 is_crtc_connector_off(struct drm_mode_set *set)
10520 {
10521 int i;
10522
10523 if (set->num_connectors == 0)
10524 return false;
10525
10526 if (WARN_ON(set->connectors == NULL))
10527 return false;
10528
10529 for (i = 0; i < set->num_connectors; i++)
10530 if (set->connectors[i]->encoder &&
10531 set->connectors[i]->encoder->crtc == set->crtc &&
10532 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10533 return true;
10534
10535 return false;
10536 }
10537
10538 static void
10539 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10540 struct intel_set_config *config)
10541 {
10542
10543 /* We should be able to check here if the fb has the same properties
10544 * and then just flip_or_move it */
10545 if (is_crtc_connector_off(set)) {
10546 config->mode_changed = true;
10547 } else if (set->crtc->primary->fb != set->fb) {
10548 /* If we have no fb then treat it as a full mode set */
10549 if (set->crtc->primary->fb == NULL) {
10550 struct intel_crtc *intel_crtc =
10551 to_intel_crtc(set->crtc);
10552
10553 if (intel_crtc->active && i915.fastboot) {
10554 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10555 config->fb_changed = true;
10556 } else {
10557 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10558 config->mode_changed = true;
10559 }
10560 } else if (set->fb == NULL) {
10561 config->mode_changed = true;
10562 } else if (set->fb->pixel_format !=
10563 set->crtc->primary->fb->pixel_format) {
10564 config->mode_changed = true;
10565 } else {
10566 config->fb_changed = true;
10567 }
10568 }
10569
10570 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10571 config->fb_changed = true;
10572
10573 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10574 DRM_DEBUG_KMS("modes are different, full mode set\n");
10575 drm_mode_debug_printmodeline(&set->crtc->mode);
10576 drm_mode_debug_printmodeline(set->mode);
10577 config->mode_changed = true;
10578 }
10579
10580 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10581 set->crtc->base.id, config->mode_changed, config->fb_changed);
10582 }
10583
10584 static int
10585 intel_modeset_stage_output_state(struct drm_device *dev,
10586 struct drm_mode_set *set,
10587 struct intel_set_config *config)
10588 {
10589 struct intel_connector *connector;
10590 struct intel_encoder *encoder;
10591 struct intel_crtc *crtc;
10592 int ro;
10593
10594 /* The upper layers ensure that we either disable a crtc or have a list
10595 * of connectors. For paranoia, double-check this. */
10596 WARN_ON(!set->fb && (set->num_connectors != 0));
10597 WARN_ON(set->fb && (set->num_connectors == 0));
10598
10599 list_for_each_entry(connector, &dev->mode_config.connector_list,
10600 base.head) {
10601 /* Otherwise traverse passed in connector list and get encoders
10602 * for them. */
10603 for (ro = 0; ro < set->num_connectors; ro++) {
10604 if (set->connectors[ro] == &connector->base) {
10605 connector->new_encoder = connector->encoder;
10606 break;
10607 }
10608 }
10609
10610 /* If we disable the crtc, disable all its connectors. Also, if
10611 * the connector is on the changing crtc but not on the new
10612 * connector list, disable it. */
10613 if ((!set->fb || ro == set->num_connectors) &&
10614 connector->base.encoder &&
10615 connector->base.encoder->crtc == set->crtc) {
10616 connector->new_encoder = NULL;
10617
10618 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10619 connector->base.base.id,
10620 drm_get_connector_name(&connector->base));
10621 }
10622
10623
10624 if (&connector->new_encoder->base != connector->base.encoder) {
10625 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10626 config->mode_changed = true;
10627 }
10628 }
10629 /* connector->new_encoder is now updated for all connectors. */
10630
10631 /* Update crtc of enabled connectors. */
10632 list_for_each_entry(connector, &dev->mode_config.connector_list,
10633 base.head) {
10634 struct drm_crtc *new_crtc;
10635
10636 if (!connector->new_encoder)
10637 continue;
10638
10639 new_crtc = connector->new_encoder->base.crtc;
10640
10641 for (ro = 0; ro < set->num_connectors; ro++) {
10642 if (set->connectors[ro] == &connector->base)
10643 new_crtc = set->crtc;
10644 }
10645
10646 /* Make sure the new CRTC will work with the encoder */
10647 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10648 new_crtc)) {
10649 return -EINVAL;
10650 }
10651 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10652
10653 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10654 connector->base.base.id,
10655 drm_get_connector_name(&connector->base),
10656 new_crtc->base.id);
10657 }
10658
10659 /* Check for any encoders that needs to be disabled. */
10660 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10661 base.head) {
10662 int num_connectors = 0;
10663 list_for_each_entry(connector,
10664 &dev->mode_config.connector_list,
10665 base.head) {
10666 if (connector->new_encoder == encoder) {
10667 WARN_ON(!connector->new_encoder->new_crtc);
10668 num_connectors++;
10669 }
10670 }
10671
10672 if (num_connectors == 0)
10673 encoder->new_crtc = NULL;
10674 else if (num_connectors > 1)
10675 return -EINVAL;
10676
10677 /* Only now check for crtc changes so we don't miss encoders
10678 * that will be disabled. */
10679 if (&encoder->new_crtc->base != encoder->base.crtc) {
10680 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10681 config->mode_changed = true;
10682 }
10683 }
10684 /* Now we've also updated encoder->new_crtc for all encoders. */
10685
10686 for_each_intel_crtc(dev, crtc) {
10687 crtc->new_enabled = false;
10688
10689 list_for_each_entry(encoder,
10690 &dev->mode_config.encoder_list,
10691 base.head) {
10692 if (encoder->new_crtc == crtc) {
10693 crtc->new_enabled = true;
10694 break;
10695 }
10696 }
10697
10698 if (crtc->new_enabled != crtc->base.enabled) {
10699 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10700 crtc->new_enabled ? "en" : "dis");
10701 config->mode_changed = true;
10702 }
10703
10704 if (crtc->new_enabled)
10705 crtc->new_config = &crtc->config;
10706 else
10707 crtc->new_config = NULL;
10708 }
10709
10710 return 0;
10711 }
10712
10713 static void disable_crtc_nofb(struct intel_crtc *crtc)
10714 {
10715 struct drm_device *dev = crtc->base.dev;
10716 struct intel_encoder *encoder;
10717 struct intel_connector *connector;
10718
10719 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10720 pipe_name(crtc->pipe));
10721
10722 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10723 if (connector->new_encoder &&
10724 connector->new_encoder->new_crtc == crtc)
10725 connector->new_encoder = NULL;
10726 }
10727
10728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10729 if (encoder->new_crtc == crtc)
10730 encoder->new_crtc = NULL;
10731 }
10732
10733 crtc->new_enabled = false;
10734 crtc->new_config = NULL;
10735 }
10736
10737 static int intel_crtc_set_config(struct drm_mode_set *set)
10738 {
10739 struct drm_device *dev;
10740 struct drm_mode_set save_set;
10741 struct intel_set_config *config;
10742 int ret;
10743
10744 BUG_ON(!set);
10745 BUG_ON(!set->crtc);
10746 BUG_ON(!set->crtc->helper_private);
10747
10748 /* Enforce sane interface api - has been abused by the fb helper. */
10749 BUG_ON(!set->mode && set->fb);
10750 BUG_ON(set->fb && set->num_connectors == 0);
10751
10752 if (set->fb) {
10753 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10754 set->crtc->base.id, set->fb->base.id,
10755 (int)set->num_connectors, set->x, set->y);
10756 } else {
10757 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10758 }
10759
10760 dev = set->crtc->dev;
10761
10762 ret = -ENOMEM;
10763 config = kzalloc(sizeof(*config), GFP_KERNEL);
10764 if (!config)
10765 goto out_config;
10766
10767 ret = intel_set_config_save_state(dev, config);
10768 if (ret)
10769 goto out_config;
10770
10771 save_set.crtc = set->crtc;
10772 save_set.mode = &set->crtc->mode;
10773 save_set.x = set->crtc->x;
10774 save_set.y = set->crtc->y;
10775 save_set.fb = set->crtc->primary->fb;
10776
10777 /* Compute whether we need a full modeset, only an fb base update or no
10778 * change at all. In the future we might also check whether only the
10779 * mode changed, e.g. for LVDS where we only change the panel fitter in
10780 * such cases. */
10781 intel_set_config_compute_mode_changes(set, config);
10782
10783 ret = intel_modeset_stage_output_state(dev, set, config);
10784 if (ret)
10785 goto fail;
10786
10787 if (config->mode_changed) {
10788 ret = intel_set_mode(set->crtc, set->mode,
10789 set->x, set->y, set->fb);
10790 } else if (config->fb_changed) {
10791 intel_crtc_wait_for_pending_flips(set->crtc);
10792
10793 ret = intel_pipe_set_base(set->crtc,
10794 set->x, set->y, set->fb);
10795 /*
10796 * In the fastboot case this may be our only check of the
10797 * state after boot. It would be better to only do it on
10798 * the first update, but we don't have a nice way of doing that
10799 * (and really, set_config isn't used much for high freq page
10800 * flipping, so increasing its cost here shouldn't be a big
10801 * deal).
10802 */
10803 if (i915.fastboot && ret == 0)
10804 intel_modeset_check_state(set->crtc->dev);
10805 }
10806
10807 if (ret) {
10808 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10809 set->crtc->base.id, ret);
10810 fail:
10811 intel_set_config_restore_state(dev, config);
10812
10813 /*
10814 * HACK: if the pipe was on, but we didn't have a framebuffer,
10815 * force the pipe off to avoid oopsing in the modeset code
10816 * due to fb==NULL. This should only happen during boot since
10817 * we don't yet reconstruct the FB from the hardware state.
10818 */
10819 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10820 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10821
10822 /* Try to restore the config */
10823 if (config->mode_changed &&
10824 intel_set_mode(save_set.crtc, save_set.mode,
10825 save_set.x, save_set.y, save_set.fb))
10826 DRM_ERROR("failed to restore config after modeset failure\n");
10827 }
10828
10829 out_config:
10830 intel_set_config_free(config);
10831 return ret;
10832 }
10833
10834 static const struct drm_crtc_funcs intel_crtc_funcs = {
10835 .cursor_set = intel_crtc_cursor_set,
10836 .cursor_move = intel_crtc_cursor_move,
10837 .gamma_set = intel_crtc_gamma_set,
10838 .set_config = intel_crtc_set_config,
10839 .destroy = intel_crtc_destroy,
10840 .page_flip = intel_crtc_page_flip,
10841 };
10842
10843 static void intel_cpu_pll_init(struct drm_device *dev)
10844 {
10845 if (HAS_DDI(dev))
10846 intel_ddi_pll_init(dev);
10847 }
10848
10849 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10850 struct intel_shared_dpll *pll,
10851 struct intel_dpll_hw_state *hw_state)
10852 {
10853 uint32_t val;
10854
10855 val = I915_READ(PCH_DPLL(pll->id));
10856 hw_state->dpll = val;
10857 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10858 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10859
10860 return val & DPLL_VCO_ENABLE;
10861 }
10862
10863 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10864 struct intel_shared_dpll *pll)
10865 {
10866 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10867 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10868 }
10869
10870 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10871 struct intel_shared_dpll *pll)
10872 {
10873 /* PCH refclock must be enabled first */
10874 ibx_assert_pch_refclk_enabled(dev_priv);
10875
10876 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10877
10878 /* Wait for the clocks to stabilize. */
10879 POSTING_READ(PCH_DPLL(pll->id));
10880 udelay(150);
10881
10882 /* The pixel multiplier can only be updated once the
10883 * DPLL is enabled and the clocks are stable.
10884 *
10885 * So write it again.
10886 */
10887 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10888 POSTING_READ(PCH_DPLL(pll->id));
10889 udelay(200);
10890 }
10891
10892 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10893 struct intel_shared_dpll *pll)
10894 {
10895 struct drm_device *dev = dev_priv->dev;
10896 struct intel_crtc *crtc;
10897
10898 /* Make sure no transcoder isn't still depending on us. */
10899 for_each_intel_crtc(dev, crtc) {
10900 if (intel_crtc_to_shared_dpll(crtc) == pll)
10901 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10902 }
10903
10904 I915_WRITE(PCH_DPLL(pll->id), 0);
10905 POSTING_READ(PCH_DPLL(pll->id));
10906 udelay(200);
10907 }
10908
10909 static char *ibx_pch_dpll_names[] = {
10910 "PCH DPLL A",
10911 "PCH DPLL B",
10912 };
10913
10914 static void ibx_pch_dpll_init(struct drm_device *dev)
10915 {
10916 struct drm_i915_private *dev_priv = dev->dev_private;
10917 int i;
10918
10919 dev_priv->num_shared_dpll = 2;
10920
10921 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10922 dev_priv->shared_dplls[i].id = i;
10923 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10924 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10925 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10926 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10927 dev_priv->shared_dplls[i].get_hw_state =
10928 ibx_pch_dpll_get_hw_state;
10929 }
10930 }
10931
10932 static void intel_shared_dpll_init(struct drm_device *dev)
10933 {
10934 struct drm_i915_private *dev_priv = dev->dev_private;
10935
10936 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10937 ibx_pch_dpll_init(dev);
10938 else
10939 dev_priv->num_shared_dpll = 0;
10940
10941 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10942 }
10943
10944 static void intel_crtc_init(struct drm_device *dev, int pipe)
10945 {
10946 struct drm_i915_private *dev_priv = dev->dev_private;
10947 struct intel_crtc *intel_crtc;
10948 int i;
10949
10950 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10951 if (intel_crtc == NULL)
10952 return;
10953
10954 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10955
10956 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10957 for (i = 0; i < 256; i++) {
10958 intel_crtc->lut_r[i] = i;
10959 intel_crtc->lut_g[i] = i;
10960 intel_crtc->lut_b[i] = i;
10961 }
10962
10963 /*
10964 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10965 * is hooked to plane B. Hence we want plane A feeding pipe B.
10966 */
10967 intel_crtc->pipe = pipe;
10968 intel_crtc->plane = pipe;
10969 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10970 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10971 intel_crtc->plane = !pipe;
10972 }
10973
10974 init_waitqueue_head(&intel_crtc->vbl_wait);
10975
10976 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10977 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10978 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10979 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10980
10981 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10982
10983 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
10984 }
10985
10986 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10987 {
10988 struct drm_encoder *encoder = connector->base.encoder;
10989
10990 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10991
10992 if (!encoder)
10993 return INVALID_PIPE;
10994
10995 return to_intel_crtc(encoder->crtc)->pipe;
10996 }
10997
10998 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10999 struct drm_file *file)
11000 {
11001 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11002 struct drm_mode_object *drmmode_obj;
11003 struct intel_crtc *crtc;
11004
11005 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11006 return -ENODEV;
11007
11008 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11009 DRM_MODE_OBJECT_CRTC);
11010
11011 if (!drmmode_obj) {
11012 DRM_ERROR("no such CRTC id\n");
11013 return -ENOENT;
11014 }
11015
11016 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11017 pipe_from_crtc_id->pipe = crtc->pipe;
11018
11019 return 0;
11020 }
11021
11022 static int intel_encoder_clones(struct intel_encoder *encoder)
11023 {
11024 struct drm_device *dev = encoder->base.dev;
11025 struct intel_encoder *source_encoder;
11026 int index_mask = 0;
11027 int entry = 0;
11028
11029 list_for_each_entry(source_encoder,
11030 &dev->mode_config.encoder_list, base.head) {
11031 if (encoders_cloneable(encoder, source_encoder))
11032 index_mask |= (1 << entry);
11033
11034 entry++;
11035 }
11036
11037 return index_mask;
11038 }
11039
11040 static bool has_edp_a(struct drm_device *dev)
11041 {
11042 struct drm_i915_private *dev_priv = dev->dev_private;
11043
11044 if (!IS_MOBILE(dev))
11045 return false;
11046
11047 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11048 return false;
11049
11050 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11051 return false;
11052
11053 return true;
11054 }
11055
11056 const char *intel_output_name(int output)
11057 {
11058 static const char *names[] = {
11059 [INTEL_OUTPUT_UNUSED] = "Unused",
11060 [INTEL_OUTPUT_ANALOG] = "Analog",
11061 [INTEL_OUTPUT_DVO] = "DVO",
11062 [INTEL_OUTPUT_SDVO] = "SDVO",
11063 [INTEL_OUTPUT_LVDS] = "LVDS",
11064 [INTEL_OUTPUT_TVOUT] = "TV",
11065 [INTEL_OUTPUT_HDMI] = "HDMI",
11066 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11067 [INTEL_OUTPUT_EDP] = "eDP",
11068 [INTEL_OUTPUT_DSI] = "DSI",
11069 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11070 };
11071
11072 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11073 return "Invalid";
11074
11075 return names[output];
11076 }
11077
11078 static void intel_setup_outputs(struct drm_device *dev)
11079 {
11080 struct drm_i915_private *dev_priv = dev->dev_private;
11081 struct intel_encoder *encoder;
11082 bool dpd_is_edp = false;
11083
11084 intel_lvds_init(dev);
11085
11086 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev))
11087 intel_crt_init(dev);
11088
11089 if (HAS_DDI(dev)) {
11090 int found;
11091
11092 /* Haswell uses DDI functions to detect digital outputs */
11093 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11094 /* DDI A only supports eDP */
11095 if (found)
11096 intel_ddi_init(dev, PORT_A);
11097
11098 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11099 * register */
11100 found = I915_READ(SFUSE_STRAP);
11101
11102 if (found & SFUSE_STRAP_DDIB_DETECTED)
11103 intel_ddi_init(dev, PORT_B);
11104 if (found & SFUSE_STRAP_DDIC_DETECTED)
11105 intel_ddi_init(dev, PORT_C);
11106 if (found & SFUSE_STRAP_DDID_DETECTED)
11107 intel_ddi_init(dev, PORT_D);
11108 } else if (HAS_PCH_SPLIT(dev)) {
11109 int found;
11110 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11111
11112 if (has_edp_a(dev))
11113 intel_dp_init(dev, DP_A, PORT_A);
11114
11115 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11116 /* PCH SDVOB multiplex with HDMIB */
11117 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11118 if (!found)
11119 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11120 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11121 intel_dp_init(dev, PCH_DP_B, PORT_B);
11122 }
11123
11124 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11125 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11126
11127 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11128 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11129
11130 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11131 intel_dp_init(dev, PCH_DP_C, PORT_C);
11132
11133 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11134 intel_dp_init(dev, PCH_DP_D, PORT_D);
11135 } else if (IS_VALLEYVIEW(dev)) {
11136 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11137 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11138 PORT_B);
11139 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11140 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11141 }
11142
11143 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11144 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11145 PORT_C);
11146 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11147 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11148 }
11149
11150 if (IS_CHERRYVIEW(dev)) {
11151 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11152 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11153 PORT_D);
11154 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11155 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11156 }
11157 }
11158
11159 intel_dsi_init(dev);
11160 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11161 bool found = false;
11162
11163 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11164 DRM_DEBUG_KMS("probing SDVOB\n");
11165 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11166 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11167 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11168 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11169 }
11170
11171 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11172 intel_dp_init(dev, DP_B, PORT_B);
11173 }
11174
11175 /* Before G4X SDVOC doesn't have its own detect register */
11176
11177 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11178 DRM_DEBUG_KMS("probing SDVOC\n");
11179 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11180 }
11181
11182 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11183
11184 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11185 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11186 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11187 }
11188 if (SUPPORTS_INTEGRATED_DP(dev))
11189 intel_dp_init(dev, DP_C, PORT_C);
11190 }
11191
11192 if (SUPPORTS_INTEGRATED_DP(dev) &&
11193 (I915_READ(DP_D) & DP_DETECTED))
11194 intel_dp_init(dev, DP_D, PORT_D);
11195 } else if (IS_GEN2(dev))
11196 intel_dvo_init(dev);
11197
11198 if (SUPPORTS_TV(dev))
11199 intel_tv_init(dev);
11200
11201 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11202 encoder->base.possible_crtcs = encoder->crtc_mask;
11203 encoder->base.possible_clones =
11204 intel_encoder_clones(encoder);
11205 }
11206
11207 intel_init_pch_refclk(dev);
11208
11209 drm_helper_move_panel_connectors_to_head(dev);
11210 }
11211
11212 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11213 {
11214 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11215
11216 drm_framebuffer_cleanup(fb);
11217 WARN_ON(!intel_fb->obj->framebuffer_references--);
11218 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11219 kfree(intel_fb);
11220 }
11221
11222 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11223 struct drm_file *file,
11224 unsigned int *handle)
11225 {
11226 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11227 struct drm_i915_gem_object *obj = intel_fb->obj;
11228
11229 return drm_gem_handle_create(file, &obj->base, handle);
11230 }
11231
11232 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11233 .destroy = intel_user_framebuffer_destroy,
11234 .create_handle = intel_user_framebuffer_create_handle,
11235 };
11236
11237 static int intel_framebuffer_init(struct drm_device *dev,
11238 struct intel_framebuffer *intel_fb,
11239 struct drm_mode_fb_cmd2 *mode_cmd,
11240 struct drm_i915_gem_object *obj)
11241 {
11242 int aligned_height;
11243 int pitch_limit;
11244 int ret;
11245
11246 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11247
11248 if (obj->tiling_mode == I915_TILING_Y) {
11249 DRM_DEBUG("hardware does not support tiling Y\n");
11250 return -EINVAL;
11251 }
11252
11253 if (mode_cmd->pitches[0] & 63) {
11254 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11255 mode_cmd->pitches[0]);
11256 return -EINVAL;
11257 }
11258
11259 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11260 pitch_limit = 32*1024;
11261 } else if (INTEL_INFO(dev)->gen >= 4) {
11262 if (obj->tiling_mode)
11263 pitch_limit = 16*1024;
11264 else
11265 pitch_limit = 32*1024;
11266 } else if (INTEL_INFO(dev)->gen >= 3) {
11267 if (obj->tiling_mode)
11268 pitch_limit = 8*1024;
11269 else
11270 pitch_limit = 16*1024;
11271 } else
11272 /* XXX DSPC is limited to 4k tiled */
11273 pitch_limit = 8*1024;
11274
11275 if (mode_cmd->pitches[0] > pitch_limit) {
11276 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11277 obj->tiling_mode ? "tiled" : "linear",
11278 mode_cmd->pitches[0], pitch_limit);
11279 return -EINVAL;
11280 }
11281
11282 if (obj->tiling_mode != I915_TILING_NONE &&
11283 mode_cmd->pitches[0] != obj->stride) {
11284 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11285 mode_cmd->pitches[0], obj->stride);
11286 return -EINVAL;
11287 }
11288
11289 /* Reject formats not supported by any plane early. */
11290 switch (mode_cmd->pixel_format) {
11291 case DRM_FORMAT_C8:
11292 case DRM_FORMAT_RGB565:
11293 case DRM_FORMAT_XRGB8888:
11294 case DRM_FORMAT_ARGB8888:
11295 break;
11296 case DRM_FORMAT_XRGB1555:
11297 case DRM_FORMAT_ARGB1555:
11298 if (INTEL_INFO(dev)->gen > 3) {
11299 DRM_DEBUG("unsupported pixel format: %s\n",
11300 drm_get_format_name(mode_cmd->pixel_format));
11301 return -EINVAL;
11302 }
11303 break;
11304 case DRM_FORMAT_XBGR8888:
11305 case DRM_FORMAT_ABGR8888:
11306 case DRM_FORMAT_XRGB2101010:
11307 case DRM_FORMAT_ARGB2101010:
11308 case DRM_FORMAT_XBGR2101010:
11309 case DRM_FORMAT_ABGR2101010:
11310 if (INTEL_INFO(dev)->gen < 4) {
11311 DRM_DEBUG("unsupported pixel format: %s\n",
11312 drm_get_format_name(mode_cmd->pixel_format));
11313 return -EINVAL;
11314 }
11315 break;
11316 case DRM_FORMAT_YUYV:
11317 case DRM_FORMAT_UYVY:
11318 case DRM_FORMAT_YVYU:
11319 case DRM_FORMAT_VYUY:
11320 if (INTEL_INFO(dev)->gen < 5) {
11321 DRM_DEBUG("unsupported pixel format: %s\n",
11322 drm_get_format_name(mode_cmd->pixel_format));
11323 return -EINVAL;
11324 }
11325 break;
11326 default:
11327 DRM_DEBUG("unsupported pixel format: %s\n",
11328 drm_get_format_name(mode_cmd->pixel_format));
11329 return -EINVAL;
11330 }
11331
11332 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11333 if (mode_cmd->offsets[0] != 0)
11334 return -EINVAL;
11335
11336 aligned_height = intel_align_height(dev, mode_cmd->height,
11337 obj->tiling_mode);
11338 /* FIXME drm helper for size checks (especially planar formats)? */
11339 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11340 return -EINVAL;
11341
11342 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11343 intel_fb->obj = obj;
11344 intel_fb->obj->framebuffer_references++;
11345
11346 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11347 if (ret) {
11348 DRM_ERROR("framebuffer init failed %d\n", ret);
11349 return ret;
11350 }
11351
11352 return 0;
11353 }
11354
11355 static struct drm_framebuffer *
11356 intel_user_framebuffer_create(struct drm_device *dev,
11357 struct drm_file *filp,
11358 struct drm_mode_fb_cmd2 *mode_cmd)
11359 {
11360 struct drm_i915_gem_object *obj;
11361
11362 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11363 mode_cmd->handles[0]));
11364 if (&obj->base == NULL)
11365 return ERR_PTR(-ENOENT);
11366
11367 return intel_framebuffer_create(dev, mode_cmd, obj);
11368 }
11369
11370 #ifndef CONFIG_DRM_I915_FBDEV
11371 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11372 {
11373 }
11374 #endif
11375
11376 static const struct drm_mode_config_funcs intel_mode_funcs = {
11377 .fb_create = intel_user_framebuffer_create,
11378 .output_poll_changed = intel_fbdev_output_poll_changed,
11379 };
11380
11381 /* Set up chip specific display functions */
11382 static void intel_init_display(struct drm_device *dev)
11383 {
11384 struct drm_i915_private *dev_priv = dev->dev_private;
11385
11386 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11387 dev_priv->display.find_dpll = g4x_find_best_dpll;
11388 else if (IS_CHERRYVIEW(dev))
11389 dev_priv->display.find_dpll = chv_find_best_dpll;
11390 else if (IS_VALLEYVIEW(dev))
11391 dev_priv->display.find_dpll = vlv_find_best_dpll;
11392 else if (IS_PINEVIEW(dev))
11393 dev_priv->display.find_dpll = pnv_find_best_dpll;
11394 else
11395 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11396
11397 if (HAS_DDI(dev)) {
11398 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11399 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11400 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11401 dev_priv->display.crtc_enable = haswell_crtc_enable;
11402 dev_priv->display.crtc_disable = haswell_crtc_disable;
11403 dev_priv->display.off = haswell_crtc_off;
11404 dev_priv->display.update_primary_plane =
11405 ironlake_update_primary_plane;
11406 } else if (HAS_PCH_SPLIT(dev)) {
11407 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11408 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11409 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11410 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11411 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11412 dev_priv->display.off = ironlake_crtc_off;
11413 dev_priv->display.update_primary_plane =
11414 ironlake_update_primary_plane;
11415 } else if (IS_VALLEYVIEW(dev)) {
11416 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11417 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11418 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11419 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11420 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11421 dev_priv->display.off = i9xx_crtc_off;
11422 dev_priv->display.update_primary_plane =
11423 i9xx_update_primary_plane;
11424 } else {
11425 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11426 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11427 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11428 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11429 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11430 dev_priv->display.off = i9xx_crtc_off;
11431 dev_priv->display.update_primary_plane =
11432 i9xx_update_primary_plane;
11433 }
11434
11435 /* Returns the core display clock speed */
11436 if (IS_VALLEYVIEW(dev))
11437 dev_priv->display.get_display_clock_speed =
11438 valleyview_get_display_clock_speed;
11439 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11440 dev_priv->display.get_display_clock_speed =
11441 i945_get_display_clock_speed;
11442 else if (IS_I915G(dev))
11443 dev_priv->display.get_display_clock_speed =
11444 i915_get_display_clock_speed;
11445 else if (IS_I945GM(dev) || IS_845G(dev))
11446 dev_priv->display.get_display_clock_speed =
11447 i9xx_misc_get_display_clock_speed;
11448 else if (IS_PINEVIEW(dev))
11449 dev_priv->display.get_display_clock_speed =
11450 pnv_get_display_clock_speed;
11451 else if (IS_I915GM(dev))
11452 dev_priv->display.get_display_clock_speed =
11453 i915gm_get_display_clock_speed;
11454 else if (IS_I865G(dev))
11455 dev_priv->display.get_display_clock_speed =
11456 i865_get_display_clock_speed;
11457 else if (IS_I85X(dev))
11458 dev_priv->display.get_display_clock_speed =
11459 i855_get_display_clock_speed;
11460 else /* 852, 830 */
11461 dev_priv->display.get_display_clock_speed =
11462 i830_get_display_clock_speed;
11463
11464 if (HAS_PCH_SPLIT(dev)) {
11465 if (IS_GEN5(dev)) {
11466 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11467 dev_priv->display.write_eld = ironlake_write_eld;
11468 } else if (IS_GEN6(dev)) {
11469 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11470 dev_priv->display.write_eld = ironlake_write_eld;
11471 dev_priv->display.modeset_global_resources =
11472 snb_modeset_global_resources;
11473 } else if (IS_IVYBRIDGE(dev)) {
11474 /* FIXME: detect B0+ stepping and use auto training */
11475 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11476 dev_priv->display.write_eld = ironlake_write_eld;
11477 dev_priv->display.modeset_global_resources =
11478 ivb_modeset_global_resources;
11479 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11480 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11481 dev_priv->display.write_eld = haswell_write_eld;
11482 dev_priv->display.modeset_global_resources =
11483 haswell_modeset_global_resources;
11484 }
11485 } else if (IS_G4X(dev)) {
11486 dev_priv->display.write_eld = g4x_write_eld;
11487 } else if (IS_VALLEYVIEW(dev)) {
11488 dev_priv->display.modeset_global_resources =
11489 valleyview_modeset_global_resources;
11490 dev_priv->display.write_eld = ironlake_write_eld;
11491 }
11492
11493 /* Default just returns -ENODEV to indicate unsupported */
11494 dev_priv->display.queue_flip = intel_default_queue_flip;
11495
11496 switch (INTEL_INFO(dev)->gen) {
11497 case 2:
11498 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11499 break;
11500
11501 case 3:
11502 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11503 break;
11504
11505 case 4:
11506 case 5:
11507 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11508 break;
11509
11510 case 6:
11511 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11512 break;
11513 case 7:
11514 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11515 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11516 break;
11517 }
11518
11519 intel_panel_init_backlight_funcs(dev);
11520 }
11521
11522 /*
11523 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11524 * resume, or other times. This quirk makes sure that's the case for
11525 * affected systems.
11526 */
11527 static void quirk_pipea_force(struct drm_device *dev)
11528 {
11529 struct drm_i915_private *dev_priv = dev->dev_private;
11530
11531 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11532 DRM_INFO("applying pipe a force quirk\n");
11533 }
11534
11535 /*
11536 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11537 */
11538 static void quirk_ssc_force_disable(struct drm_device *dev)
11539 {
11540 struct drm_i915_private *dev_priv = dev->dev_private;
11541 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11542 DRM_INFO("applying lvds SSC disable quirk\n");
11543 }
11544
11545 /*
11546 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11547 * brightness value
11548 */
11549 static void quirk_invert_brightness(struct drm_device *dev)
11550 {
11551 struct drm_i915_private *dev_priv = dev->dev_private;
11552 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11553 DRM_INFO("applying inverted panel brightness quirk\n");
11554 }
11555
11556 struct intel_quirk {
11557 int device;
11558 int subsystem_vendor;
11559 int subsystem_device;
11560 void (*hook)(struct drm_device *dev);
11561 };
11562
11563 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11564 struct intel_dmi_quirk {
11565 void (*hook)(struct drm_device *dev);
11566 const struct dmi_system_id (*dmi_id_list)[];
11567 };
11568
11569 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11570 {
11571 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11572 return 1;
11573 }
11574
11575 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11576 {
11577 .dmi_id_list = &(const struct dmi_system_id[]) {
11578 {
11579 .callback = intel_dmi_reverse_brightness,
11580 .ident = "NCR Corporation",
11581 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11582 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11583 },
11584 },
11585 { } /* terminating entry */
11586 },
11587 .hook = quirk_invert_brightness,
11588 },
11589 };
11590
11591 static struct intel_quirk intel_quirks[] = {
11592 /* HP Mini needs pipe A force quirk (LP: #322104) */
11593 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11594
11595 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11596 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11597
11598 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11599 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11600
11601 /* 830 needs to leave pipe A & dpll A up */
11602 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
11603
11604 /* Lenovo U160 cannot use SSC on LVDS */
11605 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11606
11607 /* Sony Vaio Y cannot use SSC on LVDS */
11608 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11609
11610 /* Acer Aspire 5734Z must invert backlight brightness */
11611 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11612
11613 /* Acer/eMachines G725 */
11614 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11615
11616 /* Acer/eMachines e725 */
11617 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11618
11619 /* Acer/Packard Bell NCL20 */
11620 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11621
11622 /* Acer Aspire 4736Z */
11623 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11624
11625 /* Acer Aspire 5336 */
11626 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11627 };
11628
11629 static void intel_init_quirks(struct drm_device *dev)
11630 {
11631 struct pci_dev *d = dev->pdev;
11632 int i;
11633
11634 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11635 struct intel_quirk *q = &intel_quirks[i];
11636
11637 if (d->device == q->device &&
11638 (d->subsystem_vendor == q->subsystem_vendor ||
11639 q->subsystem_vendor == PCI_ANY_ID) &&
11640 (d->subsystem_device == q->subsystem_device ||
11641 q->subsystem_device == PCI_ANY_ID))
11642 q->hook(dev);
11643 }
11644 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11645 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11646 intel_dmi_quirks[i].hook(dev);
11647 }
11648 }
11649
11650 /* Disable the VGA plane that we never use */
11651 static void i915_disable_vga(struct drm_device *dev)
11652 {
11653 struct drm_i915_private *dev_priv = dev->dev_private;
11654 u8 sr1;
11655 u32 vga_reg = i915_vgacntrl_reg(dev);
11656
11657 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11658 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11659 outb(SR01, VGA_SR_INDEX);
11660 sr1 = inb(VGA_SR_DATA);
11661 outb(sr1 | 1<<5, VGA_SR_DATA);
11662 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11663 udelay(300);
11664
11665 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11666 POSTING_READ(vga_reg);
11667 }
11668
11669 void intel_modeset_init_hw(struct drm_device *dev)
11670 {
11671 intel_prepare_ddi(dev);
11672
11673 intel_init_clock_gating(dev);
11674
11675 intel_reset_dpio(dev);
11676
11677 intel_enable_gt_powersave(dev);
11678 }
11679
11680 void intel_modeset_suspend_hw(struct drm_device *dev)
11681 {
11682 intel_suspend_hw(dev);
11683 }
11684
11685 void intel_modeset_init(struct drm_device *dev)
11686 {
11687 struct drm_i915_private *dev_priv = dev->dev_private;
11688 int sprite, ret;
11689 enum pipe pipe;
11690 struct intel_crtc *crtc;
11691
11692 drm_mode_config_init(dev);
11693
11694 dev->mode_config.min_width = 0;
11695 dev->mode_config.min_height = 0;
11696
11697 dev->mode_config.preferred_depth = 24;
11698 dev->mode_config.prefer_shadow = 1;
11699
11700 dev->mode_config.funcs = &intel_mode_funcs;
11701
11702 intel_init_quirks(dev);
11703
11704 intel_init_pm(dev);
11705
11706 if (INTEL_INFO(dev)->num_pipes == 0)
11707 return;
11708
11709 intel_init_display(dev);
11710
11711 if (IS_GEN2(dev)) {
11712 dev->mode_config.max_width = 2048;
11713 dev->mode_config.max_height = 2048;
11714 } else if (IS_GEN3(dev)) {
11715 dev->mode_config.max_width = 4096;
11716 dev->mode_config.max_height = 4096;
11717 } else {
11718 dev->mode_config.max_width = 8192;
11719 dev->mode_config.max_height = 8192;
11720 }
11721
11722 if (IS_GEN2(dev)) {
11723 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11724 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11725 } else {
11726 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11727 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11728 }
11729
11730 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11731
11732 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11733 INTEL_INFO(dev)->num_pipes,
11734 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11735
11736 for_each_pipe(pipe) {
11737 intel_crtc_init(dev, pipe);
11738 for_each_sprite(pipe, sprite) {
11739 ret = intel_plane_init(dev, pipe, sprite);
11740 if (ret)
11741 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11742 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11743 }
11744 }
11745
11746 intel_init_dpio(dev);
11747 intel_reset_dpio(dev);
11748
11749 intel_cpu_pll_init(dev);
11750 intel_shared_dpll_init(dev);
11751
11752 /* Just disable it once at startup */
11753 i915_disable_vga(dev);
11754 intel_setup_outputs(dev);
11755
11756 /* Just in case the BIOS is doing something questionable. */
11757 intel_disable_fbc(dev);
11758
11759 mutex_lock(&dev->mode_config.mutex);
11760 intel_modeset_setup_hw_state(dev, false);
11761 mutex_unlock(&dev->mode_config.mutex);
11762
11763 for_each_intel_crtc(dev, crtc) {
11764 if (!crtc->active)
11765 continue;
11766
11767 /*
11768 * Note that reserving the BIOS fb up front prevents us
11769 * from stuffing other stolen allocations like the ring
11770 * on top. This prevents some ugliness at boot time, and
11771 * can even allow for smooth boot transitions if the BIOS
11772 * fb is large enough for the active pipe configuration.
11773 */
11774 if (dev_priv->display.get_plane_config) {
11775 dev_priv->display.get_plane_config(crtc,
11776 &crtc->plane_config);
11777 /*
11778 * If the fb is shared between multiple heads, we'll
11779 * just get the first one.
11780 */
11781 intel_find_plane_obj(crtc, &crtc->plane_config);
11782 }
11783 }
11784 }
11785
11786 static void
11787 intel_connector_break_all_links(struct intel_connector *connector)
11788 {
11789 connector->base.dpms = DRM_MODE_DPMS_OFF;
11790 connector->base.encoder = NULL;
11791 connector->encoder->connectors_active = false;
11792 connector->encoder->base.crtc = NULL;
11793 }
11794
11795 static void intel_enable_pipe_a(struct drm_device *dev)
11796 {
11797 struct intel_connector *connector;
11798 struct drm_connector *crt = NULL;
11799 struct intel_load_detect_pipe load_detect_temp;
11800
11801 /* We can't just switch on the pipe A, we need to set things up with a
11802 * proper mode and output configuration. As a gross hack, enable pipe A
11803 * by enabling the load detect pipe once. */
11804 list_for_each_entry(connector,
11805 &dev->mode_config.connector_list,
11806 base.head) {
11807 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11808 crt = &connector->base;
11809 break;
11810 }
11811 }
11812
11813 if (!crt)
11814 return;
11815
11816 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
11817 intel_release_load_detect_pipe(crt, &load_detect_temp);
11818
11819
11820 }
11821
11822 static bool
11823 intel_check_plane_mapping(struct intel_crtc *crtc)
11824 {
11825 struct drm_device *dev = crtc->base.dev;
11826 struct drm_i915_private *dev_priv = dev->dev_private;
11827 u32 reg, val;
11828
11829 if (INTEL_INFO(dev)->num_pipes == 1)
11830 return true;
11831
11832 reg = DSPCNTR(!crtc->plane);
11833 val = I915_READ(reg);
11834
11835 if ((val & DISPLAY_PLANE_ENABLE) &&
11836 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11837 return false;
11838
11839 return true;
11840 }
11841
11842 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11843 {
11844 struct drm_device *dev = crtc->base.dev;
11845 struct drm_i915_private *dev_priv = dev->dev_private;
11846 u32 reg;
11847
11848 /* Clear any frame start delays used for debugging left by the BIOS */
11849 reg = PIPECONF(crtc->config.cpu_transcoder);
11850 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11851
11852 /* restore vblank interrupts to correct state */
11853 if (crtc->active)
11854 drm_vblank_on(dev, crtc->pipe);
11855 else
11856 drm_vblank_off(dev, crtc->pipe);
11857
11858 /* We need to sanitize the plane -> pipe mapping first because this will
11859 * disable the crtc (and hence change the state) if it is wrong. Note
11860 * that gen4+ has a fixed plane -> pipe mapping. */
11861 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11862 struct intel_connector *connector;
11863 bool plane;
11864
11865 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11866 crtc->base.base.id);
11867
11868 /* Pipe has the wrong plane attached and the plane is active.
11869 * Temporarily change the plane mapping and disable everything
11870 * ... */
11871 plane = crtc->plane;
11872 crtc->plane = !plane;
11873 dev_priv->display.crtc_disable(&crtc->base);
11874 crtc->plane = plane;
11875
11876 /* ... and break all links. */
11877 list_for_each_entry(connector, &dev->mode_config.connector_list,
11878 base.head) {
11879 if (connector->encoder->base.crtc != &crtc->base)
11880 continue;
11881
11882 intel_connector_break_all_links(connector);
11883 }
11884
11885 WARN_ON(crtc->active);
11886 crtc->base.enabled = false;
11887 }
11888
11889 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11890 crtc->pipe == PIPE_A && !crtc->active) {
11891 /* BIOS forgot to enable pipe A, this mostly happens after
11892 * resume. Force-enable the pipe to fix this, the update_dpms
11893 * call below we restore the pipe to the right state, but leave
11894 * the required bits on. */
11895 intel_enable_pipe_a(dev);
11896 }
11897
11898 /* Adjust the state of the output pipe according to whether we
11899 * have active connectors/encoders. */
11900 intel_crtc_update_dpms(&crtc->base);
11901
11902 if (crtc->active != crtc->base.enabled) {
11903 struct intel_encoder *encoder;
11904
11905 /* This can happen either due to bugs in the get_hw_state
11906 * functions or because the pipe is force-enabled due to the
11907 * pipe A quirk. */
11908 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11909 crtc->base.base.id,
11910 crtc->base.enabled ? "enabled" : "disabled",
11911 crtc->active ? "enabled" : "disabled");
11912
11913 crtc->base.enabled = crtc->active;
11914
11915 /* Because we only establish the connector -> encoder ->
11916 * crtc links if something is active, this means the
11917 * crtc is now deactivated. Break the links. connector
11918 * -> encoder links are only establish when things are
11919 * actually up, hence no need to break them. */
11920 WARN_ON(crtc->active);
11921
11922 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11923 WARN_ON(encoder->connectors_active);
11924 encoder->base.crtc = NULL;
11925 }
11926 }
11927
11928 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
11929 /*
11930 * We start out with underrun reporting disabled to avoid races.
11931 * For correct bookkeeping mark this on active crtcs.
11932 *
11933 * Also on gmch platforms we dont have any hardware bits to
11934 * disable the underrun reporting. Which means we need to start
11935 * out with underrun reporting disabled also on inactive pipes,
11936 * since otherwise we'll complain about the garbage we read when
11937 * e.g. coming up after runtime pm.
11938 *
11939 * No protection against concurrent access is required - at
11940 * worst a fifo underrun happens which also sets this to false.
11941 */
11942 crtc->cpu_fifo_underrun_disabled = true;
11943 crtc->pch_fifo_underrun_disabled = true;
11944
11945 update_scanline_offset(crtc);
11946 }
11947 }
11948
11949 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11950 {
11951 struct intel_connector *connector;
11952 struct drm_device *dev = encoder->base.dev;
11953
11954 /* We need to check both for a crtc link (meaning that the
11955 * encoder is active and trying to read from a pipe) and the
11956 * pipe itself being active. */
11957 bool has_active_crtc = encoder->base.crtc &&
11958 to_intel_crtc(encoder->base.crtc)->active;
11959
11960 if (encoder->connectors_active && !has_active_crtc) {
11961 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11962 encoder->base.base.id,
11963 drm_get_encoder_name(&encoder->base));
11964
11965 /* Connector is active, but has no active pipe. This is
11966 * fallout from our resume register restoring. Disable
11967 * the encoder manually again. */
11968 if (encoder->base.crtc) {
11969 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11970 encoder->base.base.id,
11971 drm_get_encoder_name(&encoder->base));
11972 encoder->disable(encoder);
11973 }
11974
11975 /* Inconsistent output/port/pipe state happens presumably due to
11976 * a bug in one of the get_hw_state functions. Or someplace else
11977 * in our code, like the register restore mess on resume. Clamp
11978 * things to off as a safer default. */
11979 list_for_each_entry(connector,
11980 &dev->mode_config.connector_list,
11981 base.head) {
11982 if (connector->encoder != encoder)
11983 continue;
11984
11985 intel_connector_break_all_links(connector);
11986 }
11987 }
11988 /* Enabled encoders without active connectors will be fixed in
11989 * the crtc fixup. */
11990 }
11991
11992 void i915_redisable_vga_power_on(struct drm_device *dev)
11993 {
11994 struct drm_i915_private *dev_priv = dev->dev_private;
11995 u32 vga_reg = i915_vgacntrl_reg(dev);
11996
11997 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11998 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11999 i915_disable_vga(dev);
12000 }
12001 }
12002
12003 void i915_redisable_vga(struct drm_device *dev)
12004 {
12005 struct drm_i915_private *dev_priv = dev->dev_private;
12006
12007 /* This function can be called both from intel_modeset_setup_hw_state or
12008 * at a very early point in our resume sequence, where the power well
12009 * structures are not yet restored. Since this function is at a very
12010 * paranoid "someone might have enabled VGA while we were not looking"
12011 * level, just check if the power well is enabled instead of trying to
12012 * follow the "don't touch the power well if we don't need it" policy
12013 * the rest of the driver uses. */
12014 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12015 return;
12016
12017 i915_redisable_vga_power_on(dev);
12018 }
12019
12020 static bool primary_get_hw_state(struct intel_crtc *crtc)
12021 {
12022 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12023
12024 if (!crtc->active)
12025 return false;
12026
12027 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12028 }
12029
12030 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12031 {
12032 struct drm_i915_private *dev_priv = dev->dev_private;
12033 enum pipe pipe;
12034 struct intel_crtc *crtc;
12035 struct intel_encoder *encoder;
12036 struct intel_connector *connector;
12037 int i;
12038
12039 for_each_intel_crtc(dev, crtc) {
12040 memset(&crtc->config, 0, sizeof(crtc->config));
12041
12042 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12043
12044 crtc->active = dev_priv->display.get_pipe_config(crtc,
12045 &crtc->config);
12046
12047 crtc->base.enabled = crtc->active;
12048 crtc->primary_enabled = primary_get_hw_state(crtc);
12049
12050 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12051 crtc->base.base.id,
12052 crtc->active ? "enabled" : "disabled");
12053 }
12054
12055 /* FIXME: Smash this into the new shared dpll infrastructure. */
12056 if (HAS_DDI(dev))
12057 intel_ddi_setup_hw_pll_state(dev);
12058
12059 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12060 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12061
12062 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12063 pll->active = 0;
12064 for_each_intel_crtc(dev, crtc) {
12065 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12066 pll->active++;
12067 }
12068 pll->refcount = pll->active;
12069
12070 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12071 pll->name, pll->refcount, pll->on);
12072 }
12073
12074 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12075 base.head) {
12076 pipe = 0;
12077
12078 if (encoder->get_hw_state(encoder, &pipe)) {
12079 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12080 encoder->base.crtc = &crtc->base;
12081 encoder->get_config(encoder, &crtc->config);
12082 } else {
12083 encoder->base.crtc = NULL;
12084 }
12085
12086 encoder->connectors_active = false;
12087 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12088 encoder->base.base.id,
12089 drm_get_encoder_name(&encoder->base),
12090 encoder->base.crtc ? "enabled" : "disabled",
12091 pipe_name(pipe));
12092 }
12093
12094 list_for_each_entry(connector, &dev->mode_config.connector_list,
12095 base.head) {
12096 if (connector->get_hw_state(connector)) {
12097 connector->base.dpms = DRM_MODE_DPMS_ON;
12098 connector->encoder->connectors_active = true;
12099 connector->base.encoder = &connector->encoder->base;
12100 } else {
12101 connector->base.dpms = DRM_MODE_DPMS_OFF;
12102 connector->base.encoder = NULL;
12103 }
12104 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12105 connector->base.base.id,
12106 drm_get_connector_name(&connector->base),
12107 connector->base.encoder ? "enabled" : "disabled");
12108 }
12109 }
12110
12111 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12112 * and i915 state tracking structures. */
12113 void intel_modeset_setup_hw_state(struct drm_device *dev,
12114 bool force_restore)
12115 {
12116 struct drm_i915_private *dev_priv = dev->dev_private;
12117 enum pipe pipe;
12118 struct intel_crtc *crtc;
12119 struct intel_encoder *encoder;
12120 int i;
12121
12122 intel_modeset_readout_hw_state(dev);
12123
12124 /*
12125 * Now that we have the config, copy it to each CRTC struct
12126 * Note that this could go away if we move to using crtc_config
12127 * checking everywhere.
12128 */
12129 for_each_intel_crtc(dev, crtc) {
12130 if (crtc->active && i915.fastboot) {
12131 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12132 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12133 crtc->base.base.id);
12134 drm_mode_debug_printmodeline(&crtc->base.mode);
12135 }
12136 }
12137
12138 /* HW state is read out, now we need to sanitize this mess. */
12139 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12140 base.head) {
12141 intel_sanitize_encoder(encoder);
12142 }
12143
12144 for_each_pipe(pipe) {
12145 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12146 intel_sanitize_crtc(crtc);
12147 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12148 }
12149
12150 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12151 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12152
12153 if (!pll->on || pll->active)
12154 continue;
12155
12156 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12157
12158 pll->disable(dev_priv, pll);
12159 pll->on = false;
12160 }
12161
12162 if (HAS_PCH_SPLIT(dev))
12163 ilk_wm_get_hw_state(dev);
12164
12165 if (force_restore) {
12166 i915_redisable_vga(dev);
12167
12168 /*
12169 * We need to use raw interfaces for restoring state to avoid
12170 * checking (bogus) intermediate states.
12171 */
12172 for_each_pipe(pipe) {
12173 struct drm_crtc *crtc =
12174 dev_priv->pipe_to_crtc_mapping[pipe];
12175
12176 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12177 crtc->primary->fb);
12178 }
12179 } else {
12180 intel_modeset_update_staged_output_state(dev);
12181 }
12182
12183 intel_modeset_check_state(dev);
12184 }
12185
12186 void intel_modeset_gem_init(struct drm_device *dev)
12187 {
12188 struct drm_crtc *c;
12189 struct intel_framebuffer *fb;
12190
12191 mutex_lock(&dev->struct_mutex);
12192 intel_init_gt_powersave(dev);
12193 mutex_unlock(&dev->struct_mutex);
12194
12195 intel_modeset_init_hw(dev);
12196
12197 intel_setup_overlay(dev);
12198
12199 /*
12200 * Make sure any fbs we allocated at startup are properly
12201 * pinned & fenced. When we do the allocation it's too early
12202 * for this.
12203 */
12204 mutex_lock(&dev->struct_mutex);
12205 for_each_crtc(dev, c) {
12206 if (!c->primary->fb)
12207 continue;
12208
12209 fb = to_intel_framebuffer(c->primary->fb);
12210 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12211 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12212 to_intel_crtc(c)->pipe);
12213 drm_framebuffer_unreference(c->primary->fb);
12214 c->primary->fb = NULL;
12215 }
12216 }
12217 mutex_unlock(&dev->struct_mutex);
12218 }
12219
12220 void intel_connector_unregister(struct intel_connector *intel_connector)
12221 {
12222 struct drm_connector *connector = &intel_connector->base;
12223
12224 intel_panel_destroy_backlight(connector);
12225 drm_sysfs_connector_remove(connector);
12226 }
12227
12228 void intel_modeset_cleanup(struct drm_device *dev)
12229 {
12230 struct drm_i915_private *dev_priv = dev->dev_private;
12231 struct drm_crtc *crtc;
12232 struct drm_connector *connector;
12233
12234 /*
12235 * Interrupts and polling as the first thing to avoid creating havoc.
12236 * Too much stuff here (turning of rps, connectors, ...) would
12237 * experience fancy races otherwise.
12238 */
12239 drm_irq_uninstall(dev);
12240 cancel_work_sync(&dev_priv->hotplug_work);
12241 /*
12242 * Due to the hpd irq storm handling the hotplug work can re-arm the
12243 * poll handlers. Hence disable polling after hpd handling is shut down.
12244 */
12245 drm_kms_helper_poll_fini(dev);
12246
12247 mutex_lock(&dev->struct_mutex);
12248
12249 intel_unregister_dsm_handler();
12250
12251 for_each_crtc(dev, crtc) {
12252 /* Skip inactive CRTCs */
12253 if (!crtc->primary->fb)
12254 continue;
12255
12256 intel_increase_pllclock(crtc);
12257 }
12258
12259 intel_disable_fbc(dev);
12260
12261 intel_disable_gt_powersave(dev);
12262
12263 ironlake_teardown_rc6(dev);
12264
12265 mutex_unlock(&dev->struct_mutex);
12266
12267 /* flush any delayed tasks or pending work */
12268 flush_scheduled_work();
12269
12270 /* destroy the backlight and sysfs files before encoders/connectors */
12271 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12272 struct intel_connector *intel_connector;
12273
12274 intel_connector = to_intel_connector(connector);
12275 intel_connector->unregister(intel_connector);
12276 }
12277
12278 drm_mode_config_cleanup(dev);
12279
12280 intel_cleanup_overlay(dev);
12281
12282 mutex_lock(&dev->struct_mutex);
12283 intel_cleanup_gt_powersave(dev);
12284 mutex_unlock(&dev->struct_mutex);
12285 }
12286
12287 /*
12288 * Return which encoder is currently attached for connector.
12289 */
12290 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12291 {
12292 return &intel_attached_encoder(connector)->base;
12293 }
12294
12295 void intel_connector_attach_encoder(struct intel_connector *connector,
12296 struct intel_encoder *encoder)
12297 {
12298 connector->encoder = encoder;
12299 drm_mode_connector_attach_encoder(&connector->base,
12300 &encoder->base);
12301 }
12302
12303 /*
12304 * set vga decode state - true == enable VGA decode
12305 */
12306 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12307 {
12308 struct drm_i915_private *dev_priv = dev->dev_private;
12309 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12310 u16 gmch_ctrl;
12311
12312 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12313 DRM_ERROR("failed to read control word\n");
12314 return -EIO;
12315 }
12316
12317 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12318 return 0;
12319
12320 if (state)
12321 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12322 else
12323 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12324
12325 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12326 DRM_ERROR("failed to write control word\n");
12327 return -EIO;
12328 }
12329
12330 return 0;
12331 }
12332
12333 struct intel_display_error_state {
12334
12335 u32 power_well_driver;
12336
12337 int num_transcoders;
12338
12339 struct intel_cursor_error_state {
12340 u32 control;
12341 u32 position;
12342 u32 base;
12343 u32 size;
12344 } cursor[I915_MAX_PIPES];
12345
12346 struct intel_pipe_error_state {
12347 bool power_domain_on;
12348 u32 source;
12349 u32 stat;
12350 } pipe[I915_MAX_PIPES];
12351
12352 struct intel_plane_error_state {
12353 u32 control;
12354 u32 stride;
12355 u32 size;
12356 u32 pos;
12357 u32 addr;
12358 u32 surface;
12359 u32 tile_offset;
12360 } plane[I915_MAX_PIPES];
12361
12362 struct intel_transcoder_error_state {
12363 bool power_domain_on;
12364 enum transcoder cpu_transcoder;
12365
12366 u32 conf;
12367
12368 u32 htotal;
12369 u32 hblank;
12370 u32 hsync;
12371 u32 vtotal;
12372 u32 vblank;
12373 u32 vsync;
12374 } transcoder[4];
12375 };
12376
12377 struct intel_display_error_state *
12378 intel_display_capture_error_state(struct drm_device *dev)
12379 {
12380 struct drm_i915_private *dev_priv = dev->dev_private;
12381 struct intel_display_error_state *error;
12382 int transcoders[] = {
12383 TRANSCODER_A,
12384 TRANSCODER_B,
12385 TRANSCODER_C,
12386 TRANSCODER_EDP,
12387 };
12388 int i;
12389
12390 if (INTEL_INFO(dev)->num_pipes == 0)
12391 return NULL;
12392
12393 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12394 if (error == NULL)
12395 return NULL;
12396
12397 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12398 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12399
12400 for_each_pipe(i) {
12401 error->pipe[i].power_domain_on =
12402 intel_display_power_enabled_sw(dev_priv,
12403 POWER_DOMAIN_PIPE(i));
12404 if (!error->pipe[i].power_domain_on)
12405 continue;
12406
12407 error->cursor[i].control = I915_READ(CURCNTR(i));
12408 error->cursor[i].position = I915_READ(CURPOS(i));
12409 error->cursor[i].base = I915_READ(CURBASE(i));
12410
12411 error->plane[i].control = I915_READ(DSPCNTR(i));
12412 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12413 if (INTEL_INFO(dev)->gen <= 3) {
12414 error->plane[i].size = I915_READ(DSPSIZE(i));
12415 error->plane[i].pos = I915_READ(DSPPOS(i));
12416 }
12417 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12418 error->plane[i].addr = I915_READ(DSPADDR(i));
12419 if (INTEL_INFO(dev)->gen >= 4) {
12420 error->plane[i].surface = I915_READ(DSPSURF(i));
12421 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12422 }
12423
12424 error->pipe[i].source = I915_READ(PIPESRC(i));
12425
12426 if (!HAS_PCH_SPLIT(dev))
12427 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12428 }
12429
12430 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12431 if (HAS_DDI(dev_priv->dev))
12432 error->num_transcoders++; /* Account for eDP. */
12433
12434 for (i = 0; i < error->num_transcoders; i++) {
12435 enum transcoder cpu_transcoder = transcoders[i];
12436
12437 error->transcoder[i].power_domain_on =
12438 intel_display_power_enabled_sw(dev_priv,
12439 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12440 if (!error->transcoder[i].power_domain_on)
12441 continue;
12442
12443 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12444
12445 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12446 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12447 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12448 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12449 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12450 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12451 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12452 }
12453
12454 return error;
12455 }
12456
12457 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12458
12459 void
12460 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12461 struct drm_device *dev,
12462 struct intel_display_error_state *error)
12463 {
12464 int i;
12465
12466 if (!error)
12467 return;
12468
12469 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12470 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12471 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12472 error->power_well_driver);
12473 for_each_pipe(i) {
12474 err_printf(m, "Pipe [%d]:\n", i);
12475 err_printf(m, " Power: %s\n",
12476 error->pipe[i].power_domain_on ? "on" : "off");
12477 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12478 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12479
12480 err_printf(m, "Plane [%d]:\n", i);
12481 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12482 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12483 if (INTEL_INFO(dev)->gen <= 3) {
12484 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12485 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12486 }
12487 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12488 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12489 if (INTEL_INFO(dev)->gen >= 4) {
12490 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12491 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12492 }
12493
12494 err_printf(m, "Cursor [%d]:\n", i);
12495 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12496 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12497 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12498 }
12499
12500 for (i = 0; i < error->num_transcoders; i++) {
12501 err_printf(m, "CPU transcoder: %c\n",
12502 transcoder_name(error->transcoder[i].cpu_transcoder));
12503 err_printf(m, " Power: %s\n",
12504 error->transcoder[i].power_domain_on ? "on" : "off");
12505 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12506 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12507 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12508 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12509 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12510 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12511 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12512 }
12513 }
Linux kernel - Deliverables
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