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drm/i915: Disable M2 frac division for integer case
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 *
900 * FIXME: The intel_crtc->active here should be switched to
901 * crtc->state->active once we have proper CRTC states wired up
902 * for atomic.
903 */
904 return intel_crtc->active && crtc->primary->state->fb &&
905 intel_crtc->config->base.adjusted_mode.crtc_clock;
906 }
907
908 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
909 enum pipe pipe)
910 {
911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913
914 return intel_crtc->config->cpu_transcoder;
915 }
916
917 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 reg = PIPEDSL(pipe);
921 u32 line1, line2;
922 u32 line_mask;
923
924 if (IS_GEN2(dev))
925 line_mask = DSL_LINEMASK_GEN2;
926 else
927 line_mask = DSL_LINEMASK_GEN3;
928
929 line1 = I915_READ(reg) & line_mask;
930 mdelay(5);
931 line2 = I915_READ(reg) & line_mask;
932
933 return line1 == line2;
934 }
935
936 /*
937 * intel_wait_for_pipe_off - wait for pipe to turn off
938 * @crtc: crtc whose pipe to wait for
939 *
940 * After disabling a pipe, we can't wait for vblank in the usual way,
941 * spinning on the vblank interrupt status bit, since we won't actually
942 * see an interrupt when the pipe is disabled.
943 *
944 * On Gen4 and above:
945 * wait for the pipe register state bit to turn off
946 *
947 * Otherwise:
948 * wait for the display line value to settle (it usually
949 * ends up stopping at the start of the next frame).
950 *
951 */
952 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
953 {
954 struct drm_device *dev = crtc->base.dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
957 enum pipe pipe = crtc->pipe;
958
959 if (INTEL_INFO(dev)->gen >= 4) {
960 int reg = PIPECONF(cpu_transcoder);
961
962 /* Wait for the Pipe State to go off */
963 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
964 100))
965 WARN(1, "pipe_off wait timed out\n");
966 } else {
967 /* Wait for the display line to settle */
968 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
969 WARN(1, "pipe_off wait timed out\n");
970 }
971 }
972
973 /*
974 * ibx_digital_port_connected - is the specified port connected?
975 * @dev_priv: i915 private structure
976 * @port: the port to test
977 *
978 * Returns true if @port is connected, false otherwise.
979 */
980 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
981 struct intel_digital_port *port)
982 {
983 u32 bit;
984
985 if (HAS_PCH_IBX(dev_priv->dev)) {
986 switch (port->port) {
987 case PORT_B:
988 bit = SDE_PORTB_HOTPLUG;
989 break;
990 case PORT_C:
991 bit = SDE_PORTC_HOTPLUG;
992 break;
993 case PORT_D:
994 bit = SDE_PORTD_HOTPLUG;
995 break;
996 default:
997 return true;
998 }
999 } else {
1000 switch (port->port) {
1001 case PORT_B:
1002 bit = SDE_PORTB_HOTPLUG_CPT;
1003 break;
1004 case PORT_C:
1005 bit = SDE_PORTC_HOTPLUG_CPT;
1006 break;
1007 case PORT_D:
1008 bit = SDE_PORTD_HOTPLUG_CPT;
1009 break;
1010 default:
1011 return true;
1012 }
1013 }
1014
1015 return I915_READ(SDEISR) & bit;
1016 }
1017
1018 static const char *state_string(bool enabled)
1019 {
1020 return enabled ? "on" : "off";
1021 }
1022
1023 /* Only for pre-ILK configs */
1024 void assert_pll(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026 {
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
1031 reg = DPLL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & DPLL_VCO_ENABLE);
1034 I915_STATE_WARN(cur_state != state,
1035 "PLL state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037 }
1038
1039 /* XXX: the dsi pll is shared between MIPI DSI ports */
1040 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 {
1042 u32 val;
1043 bool cur_state;
1044
1045 mutex_lock(&dev_priv->dpio_lock);
1046 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1047 mutex_unlock(&dev_priv->dpio_lock);
1048
1049 cur_state = val & DSI_PLL_VCO_EN;
1050 I915_STATE_WARN(cur_state != state,
1051 "DSI PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1053 }
1054 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1055 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1056
1057 struct intel_shared_dpll *
1058 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1059 {
1060 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1061
1062 if (crtc->config->shared_dpll < 0)
1063 return NULL;
1064
1065 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1066 }
1067
1068 /* For ILK+ */
1069 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1070 struct intel_shared_dpll *pll,
1071 bool state)
1072 {
1073 bool cur_state;
1074 struct intel_dpll_hw_state hw_state;
1075
1076 if (WARN (!pll,
1077 "asserting DPLL %s with no DPLL\n", state_string(state)))
1078 return;
1079
1080 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1081 I915_STATE_WARN(cur_state != state,
1082 "%s assertion failure (expected %s, current %s)\n",
1083 pll->name, state_string(state), state_string(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 int reg;
1090 u32 val;
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv->dev)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1100 } else {
1101 reg = FDI_TX_CTL(pipe);
1102 val = I915_READ(reg);
1103 cur_state = !!(val & FDI_TX_ENABLE);
1104 }
1105 I915_STATE_WARN(cur_state != state,
1106 "FDI TX state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108 }
1109 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1110 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1111
1112 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118
1119 reg = FDI_RX_CTL(pipe);
1120 val = I915_READ(reg);
1121 cur_state = !!(val & FDI_RX_ENABLE);
1122 I915_STATE_WARN(cur_state != state,
1123 "FDI RX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1127 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128
1129 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1130 enum pipe pipe)
1131 {
1132 int reg;
1133 u32 val;
1134
1135 /* ILK FDI PLL is always enabled */
1136 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1137 return;
1138
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv->dev))
1141 return;
1142
1143 reg = FDI_TX_CTL(pipe);
1144 val = I915_READ(reg);
1145 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1146 }
1147
1148 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1149 enum pipe pipe, bool state)
1150 {
1151 int reg;
1152 u32 val;
1153 bool cur_state;
1154
1155 reg = FDI_RX_CTL(pipe);
1156 val = I915_READ(reg);
1157 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1158 I915_STATE_WARN(cur_state != state,
1159 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1160 state_string(state), state_string(cur_state));
1161 }
1162
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 enum pipe pipe)
1165 {
1166 struct drm_device *dev = dev_priv->dev;
1167 int pp_reg;
1168 u32 val;
1169 enum pipe panel_pipe = PIPE_A;
1170 bool locked = true;
1171
1172 if (WARN_ON(HAS_DDI(dev)))
1173 return;
1174
1175 if (HAS_PCH_SPLIT(dev)) {
1176 u32 port_sel;
1177
1178 pp_reg = PCH_PP_CONTROL;
1179 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1180
1181 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1182 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1183 panel_pipe = PIPE_B;
1184 /* XXX: else fix for eDP */
1185 } else if (IS_VALLEYVIEW(dev)) {
1186 /* presumably write lock depends on pipe, not port select */
1187 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1188 panel_pipe = pipe;
1189 } else {
1190 pp_reg = PP_CONTROL;
1191 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1192 panel_pipe = PIPE_B;
1193 }
1194
1195 val = I915_READ(pp_reg);
1196 if (!(val & PANEL_POWER_ON) ||
1197 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1198 locked = false;
1199
1200 I915_STATE_WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
1202 pipe_name(pipe));
1203 }
1204
1205 static void assert_cursor(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1207 {
1208 struct drm_device *dev = dev_priv->dev;
1209 bool cur_state;
1210
1211 if (IS_845G(dev) || IS_I865G(dev))
1212 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1213 else
1214 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1215
1216 I915_STATE_WARN(cur_state != state,
1217 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1218 pipe_name(pipe), state_string(state), state_string(cur_state));
1219 }
1220 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1221 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1222
1223 void assert_pipe(struct drm_i915_private *dev_priv,
1224 enum pipe pipe, bool state)
1225 {
1226 int reg;
1227 u32 val;
1228 bool cur_state;
1229 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230 pipe);
1231
1232 /* if we need the pipe quirk it must be always on */
1233 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1234 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1235 state = true;
1236
1237 if (!intel_display_power_is_enabled(dev_priv,
1238 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1239 cur_state = false;
1240 } else {
1241 reg = PIPECONF(cpu_transcoder);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & PIPECONF_ENABLE);
1244 }
1245
1246 I915_STATE_WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271 {
1272 struct drm_device *dev = dev_priv->dev;
1273 int reg, i;
1274 u32 val;
1275 int cur_pipe;
1276
1277 /* Primary planes are fixed to pipes on gen4+ */
1278 if (INTEL_INFO(dev)->gen >= 4) {
1279 reg = DSPCNTR(pipe);
1280 val = I915_READ(reg);
1281 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1282 "plane %c assertion failure, should be disabled but not\n",
1283 plane_name(pipe));
1284 return;
1285 }
1286
1287 /* Need to check both planes against the pipe */
1288 for_each_pipe(dev_priv, i) {
1289 reg = DSPCNTR(i);
1290 val = I915_READ(reg);
1291 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292 DISPPLANE_SEL_PIPE_SHIFT;
1293 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295 plane_name(i), pipe_name(pipe));
1296 }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 int reg, sprite;
1304 u32 val;
1305
1306 if (INTEL_INFO(dev)->gen >= 9) {
1307 for_each_sprite(dev_priv, pipe, sprite) {
1308 val = I915_READ(PLANE_CTL(pipe, sprite));
1309 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1310 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1311 sprite, pipe_name(pipe));
1312 }
1313 } else if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(dev_priv, pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 I915_STATE_WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 I915_STATE_WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 I915_STATE_WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 {
1344 u32 val;
1345 bool enabled;
1346
1347 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1348
1349 val = I915_READ(PCH_DREF_CONTROL);
1350 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1351 DREF_SUPERSPREAD_SOURCE_MASK));
1352 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1353 }
1354
1355 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360 bool enabled;
1361
1362 reg = PCH_TRANSCONF(pipe);
1363 val = I915_READ(reg);
1364 enabled = !!(val & TRANS_ENABLE);
1365 I915_STATE_WARN(enabled,
1366 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 pipe_name(pipe));
1368 }
1369
1370 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 port_sel, u32 val)
1372 {
1373 if ((val & DP_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv->dev)) {
1377 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1378 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1379 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380 return false;
1381 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1382 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383 return false;
1384 } else {
1385 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & SDVO_ENABLE) == 0)
1395 return false;
1396
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399 return false;
1400 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402 return false;
1403 } else {
1404 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405 return false;
1406 }
1407 return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 val)
1412 {
1413 if ((val & LVDS_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418 return false;
1419 } else {
1420 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421 return false;
1422 }
1423 return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, u32 val)
1428 {
1429 if ((val & ADPA_DAC_ENABLE) == 0)
1430 return false;
1431 if (HAS_PCH_CPT(dev_priv->dev)) {
1432 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433 return false;
1434 } else {
1435 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436 return false;
1437 }
1438 return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, int reg, u32 port_sel)
1443 {
1444 u32 val = I915_READ(reg);
1445 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1446 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1447 reg, pipe_name(pipe));
1448
1449 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1450 && (val & DP_PIPEB_SELECT),
1451 "IBX PCH dp port still using transcoder B\n");
1452 }
1453
1454 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, int reg)
1456 {
1457 u32 val = I915_READ(reg);
1458 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1459 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1460 reg, pipe_name(pipe));
1461
1462 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1463 && (val & SDVO_PIPE_B_SELECT),
1464 "IBX PCH hdmi port still using transcoder B\n");
1465 }
1466
1467 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
1469 {
1470 int reg;
1471 u32 val;
1472
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477 reg = PCH_ADPA;
1478 val = I915_READ(reg);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 reg = PCH_LVDS;
1484 val = I915_READ(reg);
1485 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1486 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 pipe_name(pipe));
1488
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1492 }
1493
1494 static void intel_init_dpio(struct drm_device *dev)
1495 {
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498 if (!IS_VALLEYVIEW(dev))
1499 return;
1500
1501 /*
1502 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1503 * CHV x1 PHY (DP/HDMI D)
1504 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505 */
1506 if (IS_CHERRYVIEW(dev)) {
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1509 } else {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1511 }
1512 }
1513
1514 static void vlv_enable_pll(struct intel_crtc *crtc,
1515 const struct intel_crtc_state *pipe_config)
1516 {
1517 struct drm_device *dev = crtc->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 int reg = DPLL(crtc->pipe);
1520 u32 dpll = pipe_config->dpll_hw_state.dpll;
1521
1522 assert_pipe_disabled(dev_priv, crtc->pipe);
1523
1524 /* No really, not for ILK+ */
1525 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1526
1527 /* PLL is protected by panel, make sure we can write it */
1528 if (IS_MOBILE(dev_priv->dev))
1529 assert_panel_unlocked(dev_priv, crtc->pipe);
1530
1531 I915_WRITE(reg, dpll);
1532 POSTING_READ(reg);
1533 udelay(150);
1534
1535 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1536 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1537
1538 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1539 POSTING_READ(DPLL_MD(crtc->pipe));
1540
1541 /* We do this three times for luck */
1542 I915_WRITE(reg, dpll);
1543 POSTING_READ(reg);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg, dpll);
1546 POSTING_READ(reg);
1547 udelay(150); /* wait for warmup */
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150); /* wait for warmup */
1551 }
1552
1553 static void chv_enable_pll(struct intel_crtc *crtc,
1554 const struct intel_crtc_state *pipe_config)
1555 {
1556 struct drm_device *dev = crtc->base.dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 int pipe = crtc->pipe;
1559 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1560 u32 tmp;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1565
1566 mutex_lock(&dev_priv->dpio_lock);
1567
1568 /* Enable back the 10bit clock to display controller */
1569 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1570 tmp |= DPIO_DCLKP_EN;
1571 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1572
1573 /*
1574 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 */
1576 udelay(1);
1577
1578 /* Enable PLL */
1579 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1580
1581 /* Check PLL is locked */
1582 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1583 DRM_ERROR("PLL %d failed to lock\n", pipe);
1584
1585 /* not sure when this should be written */
1586 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(pipe));
1588
1589 mutex_unlock(&dev_priv->dpio_lock);
1590 }
1591
1592 static int intel_num_dvo_pipes(struct drm_device *dev)
1593 {
1594 struct intel_crtc *crtc;
1595 int count = 0;
1596
1597 for_each_intel_crtc(dev, crtc)
1598 count += crtc->active &&
1599 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600
1601 return count;
1602 }
1603
1604 static void i9xx_enable_pll(struct intel_crtc *crtc)
1605 {
1606 struct drm_device *dev = crtc->base.dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 int reg = DPLL(crtc->pipe);
1609 u32 dpll = crtc->config->dpll_hw_state.dpll;
1610
1611 assert_pipe_disabled(dev_priv, crtc->pipe);
1612
1613 /* No really, not for ILK+ */
1614 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1615
1616 /* PLL is protected by panel, make sure we can write it */
1617 if (IS_MOBILE(dev) && !IS_I830(dev))
1618 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620 /* Enable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1622 /*
1623 * It appears to be important that we don't enable this
1624 * for the current pipe before otherwise configuring the
1625 * PLL. No idea how this should be handled if multiple
1626 * DVO outputs are enabled simultaneosly.
1627 */
1628 dpll |= DPLL_DVO_2X_MODE;
1629 I915_WRITE(DPLL(!crtc->pipe),
1630 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Wait for the clocks to stabilize. */
1634 POSTING_READ(reg);
1635 udelay(150);
1636
1637 if (INTEL_INFO(dev)->gen >= 4) {
1638 I915_WRITE(DPLL_MD(crtc->pipe),
1639 crtc->config->dpll_hw_state.dpll_md);
1640 } else {
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1643 *
1644 * So write it again.
1645 */
1646 I915_WRITE(reg, dpll);
1647 }
1648
1649 /* We do this three times for luck */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg, dpll);
1657 POSTING_READ(reg);
1658 udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1665 *
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1667 *
1668 * Note! This is for pre-ILK only.
1669 */
1670 static void i9xx_disable_pll(struct intel_crtc *crtc)
1671 {
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 enum pipe pipe = crtc->pipe;
1675
1676 /* Disable DVO 2x clock on both PLLs if necessary */
1677 if (IS_I830(dev) &&
1678 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1679 intel_num_dvo_pipes(dev) == 1) {
1680 I915_WRITE(DPLL(PIPE_B),
1681 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1682 I915_WRITE(DPLL(PIPE_A),
1683 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1684 }
1685
1686 /* Don't disable pipe or pipe PLLs if needed */
1687 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1688 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1689 return;
1690
1691 /* Make sure the pipe isn't still relying on us */
1692 assert_pipe_disabled(dev_priv, pipe);
1693
1694 I915_WRITE(DPLL(pipe), 0);
1695 POSTING_READ(DPLL(pipe));
1696 }
1697
1698 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 u32 val = 0;
1701
1702 /* Make sure the pipe isn't still relying on us */
1703 assert_pipe_disabled(dev_priv, pipe);
1704
1705 /*
1706 * Leave integrated clock source and reference clock enabled for pipe B.
1707 * The latter is needed for VGA hotplug / manual detection.
1708 */
1709 if (pipe == PIPE_B)
1710 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1711 I915_WRITE(DPLL(pipe), val);
1712 POSTING_READ(DPLL(pipe));
1713
1714 }
1715
1716 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1719 u32 val;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 /* Set PLL en = 0 */
1725 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1726 if (pipe != PIPE_A)
1727 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1728 I915_WRITE(DPLL(pipe), val);
1729 POSTING_READ(DPLL(pipe));
1730
1731 mutex_lock(&dev_priv->dpio_lock);
1732
1733 /* Disable 10bit clock to display controller */
1734 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1735 val &= ~DPIO_DCLKP_EN;
1736 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1737
1738 /* disable left/right clock distribution */
1739 if (pipe != PIPE_B) {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1741 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1743 } else {
1744 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1745 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1746 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1747 }
1748
1749 mutex_unlock(&dev_priv->dpio_lock);
1750 }
1751
1752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1753 struct intel_digital_port *dport)
1754 {
1755 u32 port_mask;
1756 int dpll_reg;
1757
1758 switch (dport->port) {
1759 case PORT_B:
1760 port_mask = DPLL_PORTB_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_C:
1764 port_mask = DPLL_PORTC_READY_MASK;
1765 dpll_reg = DPLL(0);
1766 break;
1767 case PORT_D:
1768 port_mask = DPLL_PORTD_READY_MASK;
1769 dpll_reg = DPIO_PHY_STATUS;
1770 break;
1771 default:
1772 BUG();
1773 }
1774
1775 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1776 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1777 port_name(dport->port), I915_READ(dpll_reg));
1778 }
1779
1780 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1781 {
1782 struct drm_device *dev = crtc->base.dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1785
1786 if (WARN_ON(pll == NULL))
1787 return;
1788
1789 WARN_ON(!pll->config.crtc_mask);
1790 if (pll->active == 0) {
1791 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1792 WARN_ON(pll->on);
1793 assert_shared_dpll_disabled(dev_priv, pll);
1794
1795 pll->mode_set(dev_priv, pll);
1796 }
1797 }
1798
1799 /**
1800 * intel_enable_shared_dpll - enable PCH PLL
1801 * @dev_priv: i915 private structure
1802 * @pipe: pipe PLL to enable
1803 *
1804 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1805 * drives the transcoder clock.
1806 */
1807 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1808 {
1809 struct drm_device *dev = crtc->base.dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1812
1813 if (WARN_ON(pll == NULL))
1814 return;
1815
1816 if (WARN_ON(pll->config.crtc_mask == 0))
1817 return;
1818
1819 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1820 pll->name, pll->active, pll->on,
1821 crtc->base.base.id);
1822
1823 if (pll->active++) {
1824 WARN_ON(!pll->on);
1825 assert_shared_dpll_enabled(dev_priv, pll);
1826 return;
1827 }
1828 WARN_ON(pll->on);
1829
1830 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1831
1832 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1833 pll->enable(dev_priv, pll);
1834 pll->on = true;
1835 }
1836
1837 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1838 {
1839 struct drm_device *dev = crtc->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1842
1843 /* PCH only available on ILK+ */
1844 BUG_ON(INTEL_INFO(dev)->gen < 5);
1845 if (WARN_ON(pll == NULL))
1846 return;
1847
1848 if (WARN_ON(pll->config.crtc_mask == 0))
1849 return;
1850
1851 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1852 pll->name, pll->active, pll->on,
1853 crtc->base.base.id);
1854
1855 if (WARN_ON(pll->active == 0)) {
1856 assert_shared_dpll_disabled(dev_priv, pll);
1857 return;
1858 }
1859
1860 assert_shared_dpll_enabled(dev_priv, pll);
1861 WARN_ON(!pll->on);
1862 if (--pll->active)
1863 return;
1864
1865 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1866 pll->disable(dev_priv, pll);
1867 pll->on = false;
1868
1869 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1870 }
1871
1872 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873 enum pipe pipe)
1874 {
1875 struct drm_device *dev = dev_priv->dev;
1876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1878 uint32_t reg, val, pipeconf_val;
1879
1880 /* PCH only available on ILK+ */
1881 BUG_ON(!HAS_PCH_SPLIT(dev));
1882
1883 /* Make sure PCH DPLL is enabled */
1884 assert_shared_dpll_enabled(dev_priv,
1885 intel_crtc_to_shared_dpll(intel_crtc));
1886
1887 /* FDI must be feeding us bits for PCH ports */
1888 assert_fdi_tx_enabled(dev_priv, pipe);
1889 assert_fdi_rx_enabled(dev_priv, pipe);
1890
1891 if (HAS_PCH_CPT(dev)) {
1892 /* Workaround: Set the timing override bit before enabling the
1893 * pch transcoder. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899
1900 reg = PCH_TRANSCONF(pipe);
1901 val = I915_READ(reg);
1902 pipeconf_val = I915_READ(PIPECONF(pipe));
1903
1904 if (HAS_PCH_IBX(dev_priv->dev)) {
1905 /*
1906 * make the BPC in transcoder be consistent with
1907 * that in pipeconf reg.
1908 */
1909 val &= ~PIPECONF_BPC_MASK;
1910 val |= pipeconf_val & PIPECONF_BPC_MASK;
1911 }
1912
1913 val &= ~TRANS_INTERLACE_MASK;
1914 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1915 if (HAS_PCH_IBX(dev_priv->dev) &&
1916 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1917 val |= TRANS_LEGACY_INTERLACED_ILK;
1918 else
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(reg, val | TRANS_ENABLE);
1924 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1926 }
1927
1928 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum transcoder cpu_transcoder)
1930 {
1931 u32 val, pipeconf_val;
1932
1933 /* PCH only available on ILK+ */
1934 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1935
1936 /* FDI must be feeding us bits for PCH ports */
1937 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1938 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1939
1940 /* Workaround: set timing override bit. */
1941 val = I915_READ(_TRANSA_CHICKEN2);
1942 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1943 I915_WRITE(_TRANSA_CHICKEN2, val);
1944
1945 val = TRANS_ENABLE;
1946 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1947
1948 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1949 PIPECONF_INTERLACED_ILK)
1950 val |= TRANS_INTERLACED;
1951 else
1952 val |= TRANS_PROGRESSIVE;
1953
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1956 DRM_ERROR("Failed to enable PCH transcoder\n");
1957 }
1958
1959 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 uint32_t reg, val;
1964
1965 /* FDI relies on the transcoder */
1966 assert_fdi_tx_disabled(dev_priv, pipe);
1967 assert_fdi_rx_disabled(dev_priv, pipe);
1968
1969 /* Ports must be off as well */
1970 assert_pch_ports_disabled(dev_priv, pipe);
1971
1972 reg = PCH_TRANSCONF(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_ENABLE;
1975 I915_WRITE(reg, val);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1978 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1979
1980 if (!HAS_PCH_IBX(dev)) {
1981 /* Workaround: Clear the timing override chicken bit again. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987 }
1988
1989 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1990 {
1991 u32 val;
1992
1993 val = I915_READ(LPT_TRANSCONF);
1994 val &= ~TRANS_ENABLE;
1995 I915_WRITE(LPT_TRANSCONF, val);
1996 /* wait for PCH transcoder off, transcoder state */
1997 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1998 DRM_ERROR("Failed to disable PCH transcoder\n");
1999
2000 /* Workaround: clear timing override bit. */
2001 val = I915_READ(_TRANSA_CHICKEN2);
2002 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(_TRANSA_CHICKEN2, val);
2004 }
2005
2006 /**
2007 * intel_enable_pipe - enable a pipe, asserting requirements
2008 * @crtc: crtc responsible for the pipe
2009 *
2010 * Enable @crtc's pipe, making sure that various hardware specific requirements
2011 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2012 */
2013 static void intel_enable_pipe(struct intel_crtc *crtc)
2014 {
2015 struct drm_device *dev = crtc->base.dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 enum pipe pipe = crtc->pipe;
2018 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2019 pipe);
2020 enum pipe pch_transcoder;
2021 int reg;
2022 u32 val;
2023
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 if (HAS_PCH_LPT(dev_priv->dev))
2029 pch_transcoder = TRANSCODER_A;
2030 else
2031 pch_transcoder = pipe;
2032
2033 /*
2034 * A pipe without a PLL won't actually be able to drive bits from
2035 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2036 * need the check.
2037 */
2038 if (!HAS_PCH_SPLIT(dev_priv->dev))
2039 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2040 assert_dsi_pll_enabled(dev_priv);
2041 else
2042 assert_pll_enabled(dev_priv, pipe);
2043 else {
2044 if (crtc->config->has_pch_encoder) {
2045 /* if driving the PCH, we need FDI enabled */
2046 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2047 assert_fdi_tx_pll_enabled(dev_priv,
2048 (enum pipe) cpu_transcoder);
2049 }
2050 /* FIXME: assert CPU port conditions for SNB+ */
2051 }
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if (val & PIPECONF_ENABLE) {
2056 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2057 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2058 return;
2059 }
2060
2061 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 POSTING_READ(reg);
2063 }
2064
2065 /**
2066 * intel_disable_pipe - disable a pipe, asserting requirements
2067 * @crtc: crtc whose pipes is to be disabled
2068 *
2069 * Disable the pipe of @crtc, making sure that various hardware
2070 * specific requirements are met, if applicable, e.g. plane
2071 * disabled, panel fitter off, etc.
2072 *
2073 * Will wait until the pipe has shut down before returning.
2074 */
2075 static void intel_disable_pipe(struct intel_crtc *crtc)
2076 {
2077 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2078 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2079 enum pipe pipe = crtc->pipe;
2080 int reg;
2081 u32 val;
2082
2083 /*
2084 * Make sure planes won't keep trying to pump pixels to us,
2085 * or we might hang the display.
2086 */
2087 assert_planes_disabled(dev_priv, pipe);
2088 assert_cursor_disabled(dev_priv, pipe);
2089 assert_sprites_disabled(dev_priv, pipe);
2090
2091 reg = PIPECONF(cpu_transcoder);
2092 val = I915_READ(reg);
2093 if ((val & PIPECONF_ENABLE) == 0)
2094 return;
2095
2096 /*
2097 * Double wide has implications for planes
2098 * so best keep it disabled when not needed.
2099 */
2100 if (crtc->config->double_wide)
2101 val &= ~PIPECONF_DOUBLE_WIDE;
2102
2103 /* Don't disable pipe or pipe PLLs if needed */
2104 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2105 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2106 val &= ~PIPECONF_ENABLE;
2107
2108 I915_WRITE(reg, val);
2109 if ((val & PIPECONF_ENABLE) == 0)
2110 intel_wait_for_pipe_off(crtc);
2111 }
2112
2113 /*
2114 * Plane regs are double buffered, going from enabled->disabled needs a
2115 * trigger in order to latch. The display address reg provides this.
2116 */
2117 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2118 enum plane plane)
2119 {
2120 struct drm_device *dev = dev_priv->dev;
2121 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2122
2123 I915_WRITE(reg, I915_READ(reg));
2124 POSTING_READ(reg);
2125 }
2126
2127 /**
2128 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2129 * @plane: plane to be enabled
2130 * @crtc: crtc for the plane
2131 *
2132 * Enable @plane on @crtc, making sure that the pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2135 struct drm_crtc *crtc)
2136 {
2137 struct drm_device *dev = plane->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 dev_priv->display.update_primary_plane(crtc, plane->fb,
2150 crtc->x, crtc->y);
2151
2152 /*
2153 * BDW signals flip done immediately if the plane
2154 * is disabled, even if the plane enable is already
2155 * armed to occur at the next vblank :(
2156 */
2157 if (IS_BROADWELL(dev))
2158 intel_wait_for_vblank(dev, intel_crtc->pipe);
2159 }
2160
2161 /**
2162 * intel_disable_primary_hw_plane - disable the primary hardware plane
2163 * @plane: plane to be disabled
2164 * @crtc: crtc for the plane
2165 *
2166 * Disable @plane on @crtc, making sure that the pipe is running first.
2167 */
2168 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2169 struct drm_crtc *crtc)
2170 {
2171 struct drm_device *dev = plane->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174
2175 if (WARN_ON(!intel_crtc->active))
2176 return;
2177
2178 if (!intel_crtc->primary_enabled)
2179 return;
2180
2181 intel_crtc->primary_enabled = false;
2182
2183 dev_priv->display.update_primary_plane(crtc, plane->fb,
2184 crtc->x, crtc->y);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191 return true;
2192 #endif
2193 return false;
2194 }
2195
2196 int
2197 intel_fb_align_height(struct drm_device *dev, int height,
2198 uint32_t pixel_format,
2199 uint64_t fb_format_modifier)
2200 {
2201 int tile_height;
2202 uint32_t bits_per_pixel;
2203
2204 switch (fb_format_modifier) {
2205 case DRM_FORMAT_MOD_NONE:
2206 tile_height = 1;
2207 break;
2208 case I915_FORMAT_MOD_X_TILED:
2209 tile_height = IS_GEN2(dev) ? 16 : 8;
2210 break;
2211 case I915_FORMAT_MOD_Y_TILED:
2212 tile_height = 32;
2213 break;
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2216 switch (bits_per_pixel) {
2217 default:
2218 case 8:
2219 tile_height = 64;
2220 break;
2221 case 16:
2222 case 32:
2223 tile_height = 32;
2224 break;
2225 case 64:
2226 tile_height = 16;
2227 break;
2228 case 128:
2229 WARN_ONCE(1,
2230 "128-bit pixels are not supported for display!");
2231 tile_height = 16;
2232 break;
2233 }
2234 break;
2235 default:
2236 MISSING_CASE(fb_format_modifier);
2237 tile_height = 1;
2238 break;
2239 }
2240
2241 return ALIGN(height, tile_height);
2242 }
2243
2244 int
2245 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2246 struct drm_framebuffer *fb,
2247 struct intel_engine_cs *pipelined)
2248 {
2249 struct drm_device *dev = fb->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2252 u32 alignment;
2253 int ret;
2254
2255 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2256
2257 switch (fb->modifier[0]) {
2258 case DRM_FORMAT_MOD_NONE:
2259 if (INTEL_INFO(dev)->gen >= 9)
2260 alignment = 256 * 1024;
2261 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2262 alignment = 128 * 1024;
2263 else if (INTEL_INFO(dev)->gen >= 4)
2264 alignment = 4 * 1024;
2265 else
2266 alignment = 64 * 1024;
2267 break;
2268 case I915_FORMAT_MOD_X_TILED:
2269 if (INTEL_INFO(dev)->gen >= 9)
2270 alignment = 256 * 1024;
2271 else {
2272 /* pin() will align the object as required by fence */
2273 alignment = 0;
2274 }
2275 break;
2276 case I915_FORMAT_MOD_Y_TILED:
2277 case I915_FORMAT_MOD_Yf_TILED:
2278 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2279 "Y tiling bo slipped through, driver bug!\n"))
2280 return -EINVAL;
2281 alignment = 1 * 1024 * 1024;
2282 break;
2283 default:
2284 MISSING_CASE(fb->modifier[0]);
2285 return -EINVAL;
2286 }
2287
2288 /* Note that the w/a also requires 64 PTE of padding following the
2289 * bo. We currently fill all unused PTE with the shadow page and so
2290 * we should always have valid PTE following the scanout preventing
2291 * the VT-d warning.
2292 */
2293 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2294 alignment = 256 * 1024;
2295
2296 /*
2297 * Global gtt pte registers are special registers which actually forward
2298 * writes to a chunk of system memory. Which means that there is no risk
2299 * that the register values disappear as soon as we call
2300 * intel_runtime_pm_put(), so it is correct to wrap only the
2301 * pin/unpin/fence and not more.
2302 */
2303 intel_runtime_pm_get(dev_priv);
2304
2305 dev_priv->mm.interruptible = false;
2306 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2307 if (ret)
2308 goto err_interruptible;
2309
2310 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2311 * fence, whereas 965+ only requires a fence if using
2312 * framebuffer compression. For simplicity, we always install
2313 * a fence as the cost is not that onerous.
2314 */
2315 ret = i915_gem_object_get_fence(obj);
2316 if (ret)
2317 goto err_unpin;
2318
2319 i915_gem_object_pin_fence(obj);
2320
2321 dev_priv->mm.interruptible = true;
2322 intel_runtime_pm_put(dev_priv);
2323 return 0;
2324
2325 err_unpin:
2326 i915_gem_object_unpin_from_display_plane(obj);
2327 err_interruptible:
2328 dev_priv->mm.interruptible = true;
2329 intel_runtime_pm_put(dev_priv);
2330 return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2334 {
2335 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2336
2337 i915_gem_object_unpin_fence(obj);
2338 i915_gem_object_unpin_from_display_plane(obj);
2339 }
2340
2341 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2342 * is assumed to be a power-of-two. */
2343 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2344 unsigned int tiling_mode,
2345 unsigned int cpp,
2346 unsigned int pitch)
2347 {
2348 if (tiling_mode != I915_TILING_NONE) {
2349 unsigned int tile_rows, tiles;
2350
2351 tile_rows = *y / 8;
2352 *y %= 8;
2353
2354 tiles = *x / (512/cpp);
2355 *x %= 512/cpp;
2356
2357 return tile_rows * pitch * 8 + tiles * 4096;
2358 } else {
2359 unsigned int offset;
2360
2361 offset = *y * pitch + *x * cpp;
2362 *y = 0;
2363 *x = (offset & 4095) / cpp;
2364 return offset & -4096;
2365 }
2366 }
2367
2368 static int i9xx_format_to_fourcc(int format)
2369 {
2370 switch (format) {
2371 case DISPPLANE_8BPP:
2372 return DRM_FORMAT_C8;
2373 case DISPPLANE_BGRX555:
2374 return DRM_FORMAT_XRGB1555;
2375 case DISPPLANE_BGRX565:
2376 return DRM_FORMAT_RGB565;
2377 default:
2378 case DISPPLANE_BGRX888:
2379 return DRM_FORMAT_XRGB8888;
2380 case DISPPLANE_RGBX888:
2381 return DRM_FORMAT_XBGR8888;
2382 case DISPPLANE_BGRX101010:
2383 return DRM_FORMAT_XRGB2101010;
2384 case DISPPLANE_RGBX101010:
2385 return DRM_FORMAT_XBGR2101010;
2386 }
2387 }
2388
2389 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2390 {
2391 switch (format) {
2392 case PLANE_CTL_FORMAT_RGB_565:
2393 return DRM_FORMAT_RGB565;
2394 default:
2395 case PLANE_CTL_FORMAT_XRGB_8888:
2396 if (rgb_order) {
2397 if (alpha)
2398 return DRM_FORMAT_ABGR8888;
2399 else
2400 return DRM_FORMAT_XBGR8888;
2401 } else {
2402 if (alpha)
2403 return DRM_FORMAT_ARGB8888;
2404 else
2405 return DRM_FORMAT_XRGB8888;
2406 }
2407 case PLANE_CTL_FORMAT_XRGB_2101010:
2408 if (rgb_order)
2409 return DRM_FORMAT_XBGR2101010;
2410 else
2411 return DRM_FORMAT_XRGB2101010;
2412 }
2413 }
2414
2415 static bool
2416 intel_alloc_plane_obj(struct intel_crtc *crtc,
2417 struct intel_initial_plane_config *plane_config)
2418 {
2419 struct drm_device *dev = crtc->base.dev;
2420 struct drm_i915_gem_object *obj = NULL;
2421 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2422 struct drm_framebuffer *fb = &plane_config->fb->base;
2423 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2424 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2425 PAGE_SIZE);
2426
2427 size_aligned -= base_aligned;
2428
2429 if (plane_config->size == 0)
2430 return false;
2431
2432 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2433 base_aligned,
2434 base_aligned,
2435 size_aligned);
2436 if (!obj)
2437 return false;
2438
2439 obj->tiling_mode = plane_config->tiling;
2440 if (obj->tiling_mode == I915_TILING_X)
2441 obj->stride = fb->pitches[0];
2442
2443 mode_cmd.pixel_format = fb->pixel_format;
2444 mode_cmd.width = fb->width;
2445 mode_cmd.height = fb->height;
2446 mode_cmd.pitches[0] = fb->pitches[0];
2447 mode_cmd.modifier[0] = fb->modifier[0];
2448 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2449
2450 mutex_lock(&dev->struct_mutex);
2451
2452 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2453 &mode_cmd, obj)) {
2454 DRM_DEBUG_KMS("intel fb init failed\n");
2455 goto out_unref_obj;
2456 }
2457
2458 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2459 mutex_unlock(&dev->struct_mutex);
2460
2461 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2462 return true;
2463
2464 out_unref_obj:
2465 drm_gem_object_unreference(&obj->base);
2466 mutex_unlock(&dev->struct_mutex);
2467 return false;
2468 }
2469
2470 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2471 static void
2472 update_state_fb(struct drm_plane *plane)
2473 {
2474 if (plane->fb == plane->state->fb)
2475 return;
2476
2477 if (plane->state->fb)
2478 drm_framebuffer_unreference(plane->state->fb);
2479 plane->state->fb = plane->fb;
2480 if (plane->state->fb)
2481 drm_framebuffer_reference(plane->state->fb);
2482 }
2483
2484 static void
2485 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2486 struct intel_initial_plane_config *plane_config)
2487 {
2488 struct drm_device *dev = intel_crtc->base.dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_crtc *c;
2491 struct intel_crtc *i;
2492 struct drm_i915_gem_object *obj;
2493
2494 if (!plane_config->fb)
2495 return;
2496
2497 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2498 struct drm_plane *primary = intel_crtc->base.primary;
2499
2500 primary->fb = &plane_config->fb->base;
2501 primary->state->crtc = &intel_crtc->base;
2502 update_state_fb(primary);
2503
2504 return;
2505 }
2506
2507 kfree(plane_config->fb);
2508
2509 /*
2510 * Failed to alloc the obj, check to see if we should share
2511 * an fb with another CRTC instead
2512 */
2513 for_each_crtc(dev, c) {
2514 i = to_intel_crtc(c);
2515
2516 if (c == &intel_crtc->base)
2517 continue;
2518
2519 if (!i->active)
2520 continue;
2521
2522 obj = intel_fb_obj(c->primary->fb);
2523 if (obj == NULL)
2524 continue;
2525
2526 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2527 struct drm_plane *primary = intel_crtc->base.primary;
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dev_priv->preserve_bios_swizzle = true;
2531
2532 drm_framebuffer_reference(c->primary->fb);
2533 primary->fb = c->primary->fb;
2534 primary->state->crtc = &intel_crtc->base;
2535 update_state_fb(intel_crtc->base.primary);
2536 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2537 break;
2538 }
2539 }
2540
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544 struct drm_framebuffer *fb,
2545 int x, int y)
2546 {
2547 struct drm_device *dev = crtc->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550 struct drm_i915_gem_object *obj;
2551 int plane = intel_crtc->plane;
2552 unsigned long linear_offset;
2553 u32 dspcntr;
2554 u32 reg = DSPCNTR(plane);
2555 int pixel_size;
2556
2557 if (!intel_crtc->primary_enabled) {
2558 I915_WRITE(reg, 0);
2559 if (INTEL_INFO(dev)->gen >= 4)
2560 I915_WRITE(DSPSURF(plane), 0);
2561 else
2562 I915_WRITE(DSPADDR(plane), 0);
2563 POSTING_READ(reg);
2564 return;
2565 }
2566
2567 obj = intel_fb_obj(fb);
2568 if (WARN_ON(obj == NULL))
2569 return;
2570
2571 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573 dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575 dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577 if (INTEL_INFO(dev)->gen < 4) {
2578 if (intel_crtc->pipe == PIPE_B)
2579 dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581 /* pipesrc and dspsize control the size that is scaled from,
2582 * which should always be the user's requested size.
2583 */
2584 I915_WRITE(DSPSIZE(plane),
2585 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586 (intel_crtc->config->pipe_src_w - 1));
2587 I915_WRITE(DSPPOS(plane), 0);
2588 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589 I915_WRITE(PRIMSIZE(plane),
2590 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591 (intel_crtc->config->pipe_src_w - 1));
2592 I915_WRITE(PRIMPOS(plane), 0);
2593 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594 }
2595
2596 switch (fb->pixel_format) {
2597 case DRM_FORMAT_C8:
2598 dspcntr |= DISPPLANE_8BPP;
2599 break;
2600 case DRM_FORMAT_XRGB1555:
2601 case DRM_FORMAT_ARGB1555:
2602 dspcntr |= DISPPLANE_BGRX555;
2603 break;
2604 case DRM_FORMAT_RGB565:
2605 dspcntr |= DISPPLANE_BGRX565;
2606 break;
2607 case DRM_FORMAT_XRGB8888:
2608 case DRM_FORMAT_ARGB8888:
2609 dspcntr |= DISPPLANE_BGRX888;
2610 break;
2611 case DRM_FORMAT_XBGR8888:
2612 case DRM_FORMAT_ABGR8888:
2613 dspcntr |= DISPPLANE_RGBX888;
2614 break;
2615 case DRM_FORMAT_XRGB2101010:
2616 case DRM_FORMAT_ARGB2101010:
2617 dspcntr |= DISPPLANE_BGRX101010;
2618 break;
2619 case DRM_FORMAT_XBGR2101010:
2620 case DRM_FORMAT_ABGR2101010:
2621 dspcntr |= DISPPLANE_RGBX101010;
2622 break;
2623 default:
2624 BUG();
2625 }
2626
2627 if (INTEL_INFO(dev)->gen >= 4 &&
2628 obj->tiling_mode != I915_TILING_NONE)
2629 dspcntr |= DISPPLANE_TILED;
2630
2631 if (IS_G4X(dev))
2632 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634 linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636 if (INTEL_INFO(dev)->gen >= 4) {
2637 intel_crtc->dspaddr_offset =
2638 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639 pixel_size,
2640 fb->pitches[0]);
2641 linear_offset -= intel_crtc->dspaddr_offset;
2642 } else {
2643 intel_crtc->dspaddr_offset = linear_offset;
2644 }
2645
2646 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 x += (intel_crtc->config->pipe_src_w - 1);
2650 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652 /* Finding the last pixel of the last line of the display
2653 data and adding to linear_offset*/
2654 linear_offset +=
2655 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657 }
2658
2659 I915_WRITE(reg, dspcntr);
2660
2661 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2662 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2663 fb->pitches[0]);
2664 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2665 if (INTEL_INFO(dev)->gen >= 4) {
2666 I915_WRITE(DSPSURF(plane),
2667 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2668 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2669 I915_WRITE(DSPLINOFF(plane), linear_offset);
2670 } else
2671 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2672 POSTING_READ(reg);
2673 }
2674
2675 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2676 struct drm_framebuffer *fb,
2677 int x, int y)
2678 {
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 struct drm_i915_gem_object *obj;
2683 int plane = intel_crtc->plane;
2684 unsigned long linear_offset;
2685 u32 dspcntr;
2686 u32 reg = DSPCNTR(plane);
2687 int pixel_size;
2688
2689 if (!intel_crtc->primary_enabled) {
2690 I915_WRITE(reg, 0);
2691 I915_WRITE(DSPSURF(plane), 0);
2692 POSTING_READ(reg);
2693 return;
2694 }
2695
2696 obj = intel_fb_obj(fb);
2697 if (WARN_ON(obj == NULL))
2698 return;
2699
2700 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702 dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704 dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2707 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2708
2709 switch (fb->pixel_format) {
2710 case DRM_FORMAT_C8:
2711 dspcntr |= DISPPLANE_8BPP;
2712 break;
2713 case DRM_FORMAT_RGB565:
2714 dspcntr |= DISPPLANE_BGRX565;
2715 break;
2716 case DRM_FORMAT_XRGB8888:
2717 case DRM_FORMAT_ARGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
2721 case DRM_FORMAT_ABGR8888:
2722 dspcntr |= DISPPLANE_RGBX888;
2723 break;
2724 case DRM_FORMAT_XRGB2101010:
2725 case DRM_FORMAT_ARGB2101010:
2726 dspcntr |= DISPPLANE_BGRX101010;
2727 break;
2728 case DRM_FORMAT_XBGR2101010:
2729 case DRM_FORMAT_ABGR2101010:
2730 dspcntr |= DISPPLANE_RGBX101010;
2731 break;
2732 default:
2733 BUG();
2734 }
2735
2736 if (obj->tiling_mode != I915_TILING_NONE)
2737 dspcntr |= DISPPLANE_TILED;
2738
2739 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2740 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2741
2742 linear_offset = y * fb->pitches[0] + x * pixel_size;
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2745 pixel_size,
2746 fb->pitches[0]);
2747 linear_offset -= intel_crtc->dspaddr_offset;
2748 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2749 dspcntr |= DISPPLANE_ROTATE_180;
2750
2751 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760 }
2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
2765 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2766 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2767 fb->pitches[0]);
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 I915_WRITE(DSPSURF(plane),
2770 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2772 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2773 } else {
2774 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2775 I915_WRITE(DSPLINOFF(plane), linear_offset);
2776 }
2777 POSTING_READ(reg);
2778 }
2779
2780 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2781 uint32_t pixel_format)
2782 {
2783 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2784
2785 /*
2786 * The stride is either expressed as a multiple of 64 bytes
2787 * chunks for linear buffers or in number of tiles for tiled
2788 * buffers.
2789 */
2790 switch (fb_modifier) {
2791 case DRM_FORMAT_MOD_NONE:
2792 return 64;
2793 case I915_FORMAT_MOD_X_TILED:
2794 if (INTEL_INFO(dev)->gen == 2)
2795 return 128;
2796 return 512;
2797 case I915_FORMAT_MOD_Y_TILED:
2798 /* No need to check for old gens and Y tiling since this is
2799 * about the display engine and those will be blocked before
2800 * we get here.
2801 */
2802 return 128;
2803 case I915_FORMAT_MOD_Yf_TILED:
2804 if (bits_per_pixel == 8)
2805 return 64;
2806 else
2807 return 128;
2808 default:
2809 MISSING_CASE(fb_modifier);
2810 return 64;
2811 }
2812 }
2813
2814 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2815 struct drm_framebuffer *fb,
2816 int x, int y)
2817 {
2818 struct drm_device *dev = crtc->dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 struct drm_i915_gem_object *obj;
2822 int pipe = intel_crtc->pipe;
2823 u32 plane_ctl, stride_div;
2824
2825 if (!intel_crtc->primary_enabled) {
2826 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2827 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2828 POSTING_READ(PLANE_CTL(pipe, 0));
2829 return;
2830 }
2831
2832 plane_ctl = PLANE_CTL_ENABLE |
2833 PLANE_CTL_PIPE_GAMMA_ENABLE |
2834 PLANE_CTL_PIPE_CSC_ENABLE;
2835
2836 switch (fb->pixel_format) {
2837 case DRM_FORMAT_RGB565:
2838 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2839 break;
2840 case DRM_FORMAT_XRGB8888:
2841 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2842 break;
2843 case DRM_FORMAT_ARGB8888:
2844 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2845 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2846 break;
2847 case DRM_FORMAT_XBGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 break;
2851 case DRM_FORMAT_ABGR8888:
2852 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2854 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2855 break;
2856 case DRM_FORMAT_XRGB2101010:
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858 break;
2859 case DRM_FORMAT_XBGR2101010:
2860 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2861 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2862 break;
2863 default:
2864 BUG();
2865 }
2866
2867 switch (fb->modifier[0]) {
2868 case DRM_FORMAT_MOD_NONE:
2869 break;
2870 case I915_FORMAT_MOD_X_TILED:
2871 plane_ctl |= PLANE_CTL_TILED_X;
2872 break;
2873 case I915_FORMAT_MOD_Y_TILED:
2874 plane_ctl |= PLANE_CTL_TILED_Y;
2875 break;
2876 case I915_FORMAT_MOD_Yf_TILED:
2877 plane_ctl |= PLANE_CTL_TILED_YF;
2878 break;
2879 default:
2880 MISSING_CASE(fb->modifier[0]);
2881 }
2882
2883 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2884 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2885 plane_ctl |= PLANE_CTL_ROTATE_180;
2886
2887 obj = intel_fb_obj(fb);
2888 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2889 fb->pixel_format);
2890
2891 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2892
2893 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2894 i915_gem_obj_ggtt_offset(obj),
2895 x, y, fb->width, fb->height,
2896 fb->pitches[0]);
2897
2898 I915_WRITE(PLANE_POS(pipe, 0), 0);
2899 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2900 I915_WRITE(PLANE_SIZE(pipe, 0),
2901 (intel_crtc->config->pipe_src_h - 1) << 16 |
2902 (intel_crtc->config->pipe_src_w - 1));
2903 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2904 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2905
2906 POSTING_READ(PLANE_SURF(pipe, 0));
2907 }
2908
2909 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2910 static int
2911 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2912 int x, int y, enum mode_set_atomic state)
2913 {
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916
2917 if (dev_priv->display.disable_fbc)
2918 dev_priv->display.disable_fbc(dev);
2919
2920 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2921
2922 return 0;
2923 }
2924
2925 static void intel_complete_page_flips(struct drm_device *dev)
2926 {
2927 struct drm_crtc *crtc;
2928
2929 for_each_crtc(dev, crtc) {
2930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931 enum plane plane = intel_crtc->plane;
2932
2933 intel_prepare_page_flip(dev, plane);
2934 intel_finish_page_flip_plane(dev, plane);
2935 }
2936 }
2937
2938 static void intel_update_primary_planes(struct drm_device *dev)
2939 {
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2941 struct drm_crtc *crtc;
2942
2943 for_each_crtc(dev, crtc) {
2944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945
2946 drm_modeset_lock(&crtc->mutex, NULL);
2947 /*
2948 * FIXME: Once we have proper support for primary planes (and
2949 * disabling them without disabling the entire crtc) allow again
2950 * a NULL crtc->primary->fb.
2951 */
2952 if (intel_crtc->active && crtc->primary->fb)
2953 dev_priv->display.update_primary_plane(crtc,
2954 crtc->primary->fb,
2955 crtc->x,
2956 crtc->y);
2957 drm_modeset_unlock(&crtc->mutex);
2958 }
2959 }
2960
2961 void intel_prepare_reset(struct drm_device *dev)
2962 {
2963 struct drm_i915_private *dev_priv = to_i915(dev);
2964 struct intel_crtc *crtc;
2965
2966 /* no reset support for gen2 */
2967 if (IS_GEN2(dev))
2968 return;
2969
2970 /* reset doesn't touch the display */
2971 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2972 return;
2973
2974 drm_modeset_lock_all(dev);
2975
2976 /*
2977 * Disabling the crtcs gracefully seems nicer. Also the
2978 * g33 docs say we should at least disable all the planes.
2979 */
2980 for_each_intel_crtc(dev, crtc) {
2981 if (crtc->active)
2982 dev_priv->display.crtc_disable(&crtc->base);
2983 }
2984 }
2985
2986 void intel_finish_reset(struct drm_device *dev)
2987 {
2988 struct drm_i915_private *dev_priv = to_i915(dev);
2989
2990 /*
2991 * Flips in the rings will be nuked by the reset,
2992 * so complete all pending flips so that user space
2993 * will get its events and not get stuck.
2994 */
2995 intel_complete_page_flips(dev);
2996
2997 /* no reset support for gen2 */
2998 if (IS_GEN2(dev))
2999 return;
3000
3001 /* reset doesn't touch the display */
3002 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3003 /*
3004 * Flips in the rings have been nuked by the reset,
3005 * so update the base address of all primary
3006 * planes to the the last fb to make sure we're
3007 * showing the correct fb after a reset.
3008 */
3009 intel_update_primary_planes(dev);
3010 return;
3011 }
3012
3013 /*
3014 * The display has been reset as well,
3015 * so need a full re-initialization.
3016 */
3017 intel_runtime_pm_disable_interrupts(dev_priv);
3018 intel_runtime_pm_enable_interrupts(dev_priv);
3019
3020 intel_modeset_init_hw(dev);
3021
3022 spin_lock_irq(&dev_priv->irq_lock);
3023 if (dev_priv->display.hpd_irq_setup)
3024 dev_priv->display.hpd_irq_setup(dev);
3025 spin_unlock_irq(&dev_priv->irq_lock);
3026
3027 intel_modeset_setup_hw_state(dev, true);
3028
3029 intel_hpd_init(dev_priv);
3030
3031 drm_modeset_unlock_all(dev);
3032 }
3033
3034 static int
3035 intel_finish_fb(struct drm_framebuffer *old_fb)
3036 {
3037 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3038 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3039 bool was_interruptible = dev_priv->mm.interruptible;
3040 int ret;
3041
3042 /* Big Hammer, we also need to ensure that any pending
3043 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3044 * current scanout is retired before unpinning the old
3045 * framebuffer.
3046 *
3047 * This should only fail upon a hung GPU, in which case we
3048 * can safely continue.
3049 */
3050 dev_priv->mm.interruptible = false;
3051 ret = i915_gem_object_finish_gpu(obj);
3052 dev_priv->mm.interruptible = was_interruptible;
3053
3054 return ret;
3055 }
3056
3057 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3058 {
3059 struct drm_device *dev = crtc->dev;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3062 bool pending;
3063
3064 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3065 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3066 return false;
3067
3068 spin_lock_irq(&dev->event_lock);
3069 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3070 spin_unlock_irq(&dev->event_lock);
3071
3072 return pending;
3073 }
3074
3075 static void intel_update_pipe_size(struct intel_crtc *crtc)
3076 {
3077 struct drm_device *dev = crtc->base.dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 const struct drm_display_mode *adjusted_mode;
3080
3081 if (!i915.fastboot)
3082 return;
3083
3084 /*
3085 * Update pipe size and adjust fitter if needed: the reason for this is
3086 * that in compute_mode_changes we check the native mode (not the pfit
3087 * mode) to see if we can flip rather than do a full mode set. In the
3088 * fastboot case, we'll flip, but if we don't update the pipesrc and
3089 * pfit state, we'll end up with a big fb scanned out into the wrong
3090 * sized surface.
3091 *
3092 * To fix this properly, we need to hoist the checks up into
3093 * compute_mode_changes (or above), check the actual pfit state and
3094 * whether the platform allows pfit disable with pipe active, and only
3095 * then update the pipesrc and pfit state, even on the flip path.
3096 */
3097
3098 adjusted_mode = &crtc->config->base.adjusted_mode;
3099
3100 I915_WRITE(PIPESRC(crtc->pipe),
3101 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3102 (adjusted_mode->crtc_vdisplay - 1));
3103 if (!crtc->config->pch_pfit.enabled &&
3104 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3105 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3106 I915_WRITE(PF_CTL(crtc->pipe), 0);
3107 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3108 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3109 }
3110 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3111 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3112 }
3113
3114 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3115 {
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 int pipe = intel_crtc->pipe;
3120 u32 reg, temp;
3121
3122 /* enable normal train */
3123 reg = FDI_TX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 if (IS_IVYBRIDGE(dev)) {
3126 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3127 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3128 } else {
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3131 }
3132 I915_WRITE(reg, temp);
3133
3134 reg = FDI_RX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 if (HAS_PCH_CPT(dev)) {
3137 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3138 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3139 } else {
3140 temp &= ~FDI_LINK_TRAIN_NONE;
3141 temp |= FDI_LINK_TRAIN_NONE;
3142 }
3143 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3144
3145 /* wait one idle pattern time */
3146 POSTING_READ(reg);
3147 udelay(1000);
3148
3149 /* IVB wants error correction enabled */
3150 if (IS_IVYBRIDGE(dev))
3151 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3152 FDI_FE_ERRC_ENABLE);
3153 }
3154
3155 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3156 {
3157 return crtc->base.state->enable && crtc->active &&
3158 crtc->config->has_pch_encoder;
3159 }
3160
3161 static void ivb_modeset_global_resources(struct drm_device *dev)
3162 {
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *pipe_B_crtc =
3165 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3166 struct intel_crtc *pipe_C_crtc =
3167 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3168 uint32_t temp;
3169
3170 /*
3171 * When everything is off disable fdi C so that we could enable fdi B
3172 * with all lanes. Note that we don't care about enabled pipes without
3173 * an enabled pch encoder.
3174 */
3175 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3176 !pipe_has_enabled_pch(pipe_C_crtc)) {
3177 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3178 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3179
3180 temp = I915_READ(SOUTH_CHICKEN1);
3181 temp &= ~FDI_BC_BIFURCATION_SELECT;
3182 DRM_DEBUG_KMS("disabling fdi C rx\n");
3183 I915_WRITE(SOUTH_CHICKEN1, temp);
3184 }
3185 }
3186
3187 /* The FDI link training functions for ILK/Ibexpeak. */
3188 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3189 {
3190 struct drm_device *dev = crtc->dev;
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp, tries;
3195
3196 /* FDI needs bits from pipe first */
3197 assert_pipe_enabled(dev_priv, pipe);
3198
3199 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3200 for train result */
3201 reg = FDI_RX_IMR(pipe);
3202 temp = I915_READ(reg);
3203 temp &= ~FDI_RX_SYMBOL_LOCK;
3204 temp &= ~FDI_RX_BIT_LOCK;
3205 I915_WRITE(reg, temp);
3206 I915_READ(reg);
3207 udelay(150);
3208
3209 /* enable CPU FDI TX and PCH FDI RX */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3213 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3214 temp &= ~FDI_LINK_TRAIN_NONE;
3215 temp |= FDI_LINK_TRAIN_PATTERN_1;
3216 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3217
3218 reg = FDI_RX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 temp &= ~FDI_LINK_TRAIN_NONE;
3221 temp |= FDI_LINK_TRAIN_PATTERN_1;
3222 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3223
3224 POSTING_READ(reg);
3225 udelay(150);
3226
3227 /* Ironlake workaround, enable clock pointer after FDI enable*/
3228 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3229 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3230 FDI_RX_PHASE_SYNC_POINTER_EN);
3231
3232 reg = FDI_RX_IIR(pipe);
3233 for (tries = 0; tries < 5; tries++) {
3234 temp = I915_READ(reg);
3235 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3236
3237 if ((temp & FDI_RX_BIT_LOCK)) {
3238 DRM_DEBUG_KMS("FDI train 1 done.\n");
3239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3240 break;
3241 }
3242 }
3243 if (tries == 5)
3244 DRM_ERROR("FDI train 1 fail!\n");
3245
3246 /* Train 2 */
3247 reg = FDI_TX_CTL(pipe);
3248 temp = I915_READ(reg);
3249 temp &= ~FDI_LINK_TRAIN_NONE;
3250 temp |= FDI_LINK_TRAIN_PATTERN_2;
3251 I915_WRITE(reg, temp);
3252
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 temp &= ~FDI_LINK_TRAIN_NONE;
3256 temp |= FDI_LINK_TRAIN_PATTERN_2;
3257 I915_WRITE(reg, temp);
3258
3259 POSTING_READ(reg);
3260 udelay(150);
3261
3262 reg = FDI_RX_IIR(pipe);
3263 for (tries = 0; tries < 5; tries++) {
3264 temp = I915_READ(reg);
3265 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3266
3267 if (temp & FDI_RX_SYMBOL_LOCK) {
3268 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3269 DRM_DEBUG_KMS("FDI train 2 done.\n");
3270 break;
3271 }
3272 }
3273 if (tries == 5)
3274 DRM_ERROR("FDI train 2 fail!\n");
3275
3276 DRM_DEBUG_KMS("FDI train done\n");
3277
3278 }
3279
3280 static const int snb_b_fdi_train_param[] = {
3281 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3282 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3283 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3284 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3285 };
3286
3287 /* The FDI link training functions for SNB/Cougarpoint. */
3288 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3289 {
3290 struct drm_device *dev = crtc->dev;
3291 struct drm_i915_private *dev_priv = dev->dev_private;
3292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293 int pipe = intel_crtc->pipe;
3294 u32 reg, temp, i, retry;
3295
3296 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3297 for train result */
3298 reg = FDI_RX_IMR(pipe);
3299 temp = I915_READ(reg);
3300 temp &= ~FDI_RX_SYMBOL_LOCK;
3301 temp &= ~FDI_RX_BIT_LOCK;
3302 I915_WRITE(reg, temp);
3303
3304 POSTING_READ(reg);
3305 udelay(150);
3306
3307 /* enable CPU FDI TX and PCH FDI RX */
3308 reg = FDI_TX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3311 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3312 temp &= ~FDI_LINK_TRAIN_NONE;
3313 temp |= FDI_LINK_TRAIN_PATTERN_1;
3314 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3315 /* SNB-B */
3316 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3317 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3318
3319 I915_WRITE(FDI_RX_MISC(pipe),
3320 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3321
3322 reg = FDI_RX_CTL(pipe);
3323 temp = I915_READ(reg);
3324 if (HAS_PCH_CPT(dev)) {
3325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3326 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3327 } else {
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330 }
3331 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3332
3333 POSTING_READ(reg);
3334 udelay(150);
3335
3336 for (i = 0; i < 4; i++) {
3337 reg = FDI_TX_CTL(pipe);
3338 temp = I915_READ(reg);
3339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3340 temp |= snb_b_fdi_train_param[i];
3341 I915_WRITE(reg, temp);
3342
3343 POSTING_READ(reg);
3344 udelay(500);
3345
3346 for (retry = 0; retry < 5; retry++) {
3347 reg = FDI_RX_IIR(pipe);
3348 temp = I915_READ(reg);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350 if (temp & FDI_RX_BIT_LOCK) {
3351 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 break;
3354 }
3355 udelay(50);
3356 }
3357 if (retry < 5)
3358 break;
3359 }
3360 if (i == 4)
3361 DRM_ERROR("FDI train 1 fail!\n");
3362
3363 /* Train 2 */
3364 reg = FDI_TX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 temp &= ~FDI_LINK_TRAIN_NONE;
3367 temp |= FDI_LINK_TRAIN_PATTERN_2;
3368 if (IS_GEN6(dev)) {
3369 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3370 /* SNB-B */
3371 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3372 }
3373 I915_WRITE(reg, temp);
3374
3375 reg = FDI_RX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 if (HAS_PCH_CPT(dev)) {
3378 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3379 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3380 } else {
3381 temp &= ~FDI_LINK_TRAIN_NONE;
3382 temp |= FDI_LINK_TRAIN_PATTERN_2;
3383 }
3384 I915_WRITE(reg, temp);
3385
3386 POSTING_READ(reg);
3387 udelay(150);
3388
3389 for (i = 0; i < 4; i++) {
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3393 temp |= snb_b_fdi_train_param[i];
3394 I915_WRITE(reg, temp);
3395
3396 POSTING_READ(reg);
3397 udelay(500);
3398
3399 for (retry = 0; retry < 5; retry++) {
3400 reg = FDI_RX_IIR(pipe);
3401 temp = I915_READ(reg);
3402 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3403 if (temp & FDI_RX_SYMBOL_LOCK) {
3404 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3405 DRM_DEBUG_KMS("FDI train 2 done.\n");
3406 break;
3407 }
3408 udelay(50);
3409 }
3410 if (retry < 5)
3411 break;
3412 }
3413 if (i == 4)
3414 DRM_ERROR("FDI train 2 fail!\n");
3415
3416 DRM_DEBUG_KMS("FDI train done.\n");
3417 }
3418
3419 /* Manual link training for Ivy Bridge A0 parts */
3420 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3421 {
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp, i, j;
3427
3428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429 for train result */
3430 reg = FDI_RX_IMR(pipe);
3431 temp = I915_READ(reg);
3432 temp &= ~FDI_RX_SYMBOL_LOCK;
3433 temp &= ~FDI_RX_BIT_LOCK;
3434 I915_WRITE(reg, temp);
3435
3436 POSTING_READ(reg);
3437 udelay(150);
3438
3439 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3440 I915_READ(FDI_RX_IIR(pipe)));
3441
3442 /* Try each vswing and preemphasis setting twice before moving on */
3443 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3444 /* disable first in case we need to retry */
3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3448 temp &= ~FDI_TX_ENABLE;
3449 I915_WRITE(reg, temp);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_AUTO;
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp &= ~FDI_RX_ENABLE;
3456 I915_WRITE(reg, temp);
3457
3458 /* enable CPU FDI TX and PCH FDI RX */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3462 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3463 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3464 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3465 temp |= snb_b_fdi_train_param[j/2];
3466 temp |= FDI_COMPOSITE_SYNC;
3467 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3468
3469 I915_WRITE(FDI_RX_MISC(pipe),
3470 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3471
3472 reg = FDI_RX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3475 temp |= FDI_COMPOSITE_SYNC;
3476 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3477
3478 POSTING_READ(reg);
3479 udelay(1); /* should be 0.5us */
3480
3481 for (i = 0; i < 4; i++) {
3482 reg = FDI_RX_IIR(pipe);
3483 temp = I915_READ(reg);
3484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485
3486 if (temp & FDI_RX_BIT_LOCK ||
3487 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3488 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3489 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3490 i);
3491 break;
3492 }
3493 udelay(1); /* should be 0.5us */
3494 }
3495 if (i == 4) {
3496 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3497 continue;
3498 }
3499
3500 /* Train 2 */
3501 reg = FDI_TX_CTL(pipe);
3502 temp = I915_READ(reg);
3503 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3504 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3505 I915_WRITE(reg, temp);
3506
3507 reg = FDI_RX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3511 I915_WRITE(reg, temp);
3512
3513 POSTING_READ(reg);
3514 udelay(2); /* should be 1.5us */
3515
3516 for (i = 0; i < 4; i++) {
3517 reg = FDI_RX_IIR(pipe);
3518 temp = I915_READ(reg);
3519 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3520
3521 if (temp & FDI_RX_SYMBOL_LOCK ||
3522 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3523 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3524 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3525 i);
3526 goto train_done;
3527 }
3528 udelay(2); /* should be 1.5us */
3529 }
3530 if (i == 4)
3531 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3532 }
3533
3534 train_done:
3535 DRM_DEBUG_KMS("FDI train done.\n");
3536 }
3537
3538 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3539 {
3540 struct drm_device *dev = intel_crtc->base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 int pipe = intel_crtc->pipe;
3543 u32 reg, temp;
3544
3545
3546 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3547 reg = FDI_RX_CTL(pipe);
3548 temp = I915_READ(reg);
3549 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3550 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3551 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3552 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3553
3554 POSTING_READ(reg);
3555 udelay(200);
3556
3557 /* Switch from Rawclk to PCDclk */
3558 temp = I915_READ(reg);
3559 I915_WRITE(reg, temp | FDI_PCDCLK);
3560
3561 POSTING_READ(reg);
3562 udelay(200);
3563
3564 /* Enable CPU FDI TX PLL, always on for Ironlake */
3565 reg = FDI_TX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3568 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3569
3570 POSTING_READ(reg);
3571 udelay(100);
3572 }
3573 }
3574
3575 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3576 {
3577 struct drm_device *dev = intel_crtc->base.dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 int pipe = intel_crtc->pipe;
3580 u32 reg, temp;
3581
3582 /* Switch from PCDclk to Rawclk */
3583 reg = FDI_RX_CTL(pipe);
3584 temp = I915_READ(reg);
3585 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3586
3587 /* Disable CPU FDI TX PLL */
3588 reg = FDI_TX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3591
3592 POSTING_READ(reg);
3593 udelay(100);
3594
3595 reg = FDI_RX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3598
3599 /* Wait for the clocks to turn off. */
3600 POSTING_READ(reg);
3601 udelay(100);
3602 }
3603
3604 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3605 {
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 int pipe = intel_crtc->pipe;
3610 u32 reg, temp;
3611
3612 /* disable CPU FDI tx and PCH FDI rx */
3613 reg = FDI_TX_CTL(pipe);
3614 temp = I915_READ(reg);
3615 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3616 POSTING_READ(reg);
3617
3618 reg = FDI_RX_CTL(pipe);
3619 temp = I915_READ(reg);
3620 temp &= ~(0x7 << 16);
3621 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3622 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3623
3624 POSTING_READ(reg);
3625 udelay(100);
3626
3627 /* Ironlake workaround, disable clock pointer after downing FDI */
3628 if (HAS_PCH_IBX(dev))
3629 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3630
3631 /* still set train pattern 1 */
3632 reg = FDI_TX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~FDI_LINK_TRAIN_NONE;
3635 temp |= FDI_LINK_TRAIN_PATTERN_1;
3636 I915_WRITE(reg, temp);
3637
3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
3640 if (HAS_PCH_CPT(dev)) {
3641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3643 } else {
3644 temp &= ~FDI_LINK_TRAIN_NONE;
3645 temp |= FDI_LINK_TRAIN_PATTERN_1;
3646 }
3647 /* BPC in FDI rx is consistent with that in PIPECONF */
3648 temp &= ~(0x07 << 16);
3649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3650 I915_WRITE(reg, temp);
3651
3652 POSTING_READ(reg);
3653 udelay(100);
3654 }
3655
3656 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3657 {
3658 struct intel_crtc *crtc;
3659
3660 /* Note that we don't need to be called with mode_config.lock here
3661 * as our list of CRTC objects is static for the lifetime of the
3662 * device and so cannot disappear as we iterate. Similarly, we can
3663 * happily treat the predicates as racy, atomic checks as userspace
3664 * cannot claim and pin a new fb without at least acquring the
3665 * struct_mutex and so serialising with us.
3666 */
3667 for_each_intel_crtc(dev, crtc) {
3668 if (atomic_read(&crtc->unpin_work_count) == 0)
3669 continue;
3670
3671 if (crtc->unpin_work)
3672 intel_wait_for_vblank(dev, crtc->pipe);
3673
3674 return true;
3675 }
3676
3677 return false;
3678 }
3679
3680 static void page_flip_completed(struct intel_crtc *intel_crtc)
3681 {
3682 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3683 struct intel_unpin_work *work = intel_crtc->unpin_work;
3684
3685 /* ensure that the unpin work is consistent wrt ->pending. */
3686 smp_rmb();
3687 intel_crtc->unpin_work = NULL;
3688
3689 if (work->event)
3690 drm_send_vblank_event(intel_crtc->base.dev,
3691 intel_crtc->pipe,
3692 work->event);
3693
3694 drm_crtc_vblank_put(&intel_crtc->base);
3695
3696 wake_up_all(&dev_priv->pending_flip_queue);
3697 queue_work(dev_priv->wq, &work->work);
3698
3699 trace_i915_flip_complete(intel_crtc->plane,
3700 work->pending_flip_obj);
3701 }
3702
3703 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3704 {
3705 struct drm_device *dev = crtc->dev;
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3709 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3710 !intel_crtc_has_pending_flip(crtc),
3711 60*HZ) == 0)) {
3712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3713
3714 spin_lock_irq(&dev->event_lock);
3715 if (intel_crtc->unpin_work) {
3716 WARN_ONCE(1, "Removing stuck page flip\n");
3717 page_flip_completed(intel_crtc);
3718 }
3719 spin_unlock_irq(&dev->event_lock);
3720 }
3721
3722 if (crtc->primary->fb) {
3723 mutex_lock(&dev->struct_mutex);
3724 intel_finish_fb(crtc->primary->fb);
3725 mutex_unlock(&dev->struct_mutex);
3726 }
3727 }
3728
3729 /* Program iCLKIP clock to the desired frequency */
3730 static void lpt_program_iclkip(struct drm_crtc *crtc)
3731 {
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3735 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3736 u32 temp;
3737
3738 mutex_lock(&dev_priv->dpio_lock);
3739
3740 /* It is necessary to ungate the pixclk gate prior to programming
3741 * the divisors, and gate it back when it is done.
3742 */
3743 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3744
3745 /* Disable SSCCTL */
3746 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3747 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3748 SBI_SSCCTL_DISABLE,
3749 SBI_ICLK);
3750
3751 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3752 if (clock == 20000) {
3753 auxdiv = 1;
3754 divsel = 0x41;
3755 phaseinc = 0x20;
3756 } else {
3757 /* The iCLK virtual clock root frequency is in MHz,
3758 * but the adjusted_mode->crtc_clock in in KHz. To get the
3759 * divisors, it is necessary to divide one by another, so we
3760 * convert the virtual clock precision to KHz here for higher
3761 * precision.
3762 */
3763 u32 iclk_virtual_root_freq = 172800 * 1000;
3764 u32 iclk_pi_range = 64;
3765 u32 desired_divisor, msb_divisor_value, pi_value;
3766
3767 desired_divisor = (iclk_virtual_root_freq / clock);
3768 msb_divisor_value = desired_divisor / iclk_pi_range;
3769 pi_value = desired_divisor % iclk_pi_range;
3770
3771 auxdiv = 0;
3772 divsel = msb_divisor_value - 2;
3773 phaseinc = pi_value;
3774 }
3775
3776 /* This should not happen with any sane values */
3777 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3778 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3779 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3780 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3781
3782 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3783 clock,
3784 auxdiv,
3785 divsel,
3786 phasedir,
3787 phaseinc);
3788
3789 /* Program SSCDIVINTPHASE6 */
3790 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3791 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3792 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3793 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3794 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3795 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3796 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3797 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3798
3799 /* Program SSCAUXDIV */
3800 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3801 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3802 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3803 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3804
3805 /* Enable modulator and associated divider */
3806 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3807 temp &= ~SBI_SSCCTL_DISABLE;
3808 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3809
3810 /* Wait for initialization time */
3811 udelay(24);
3812
3813 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3814
3815 mutex_unlock(&dev_priv->dpio_lock);
3816 }
3817
3818 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3819 enum pipe pch_transcoder)
3820 {
3821 struct drm_device *dev = crtc->base.dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3824
3825 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3826 I915_READ(HTOTAL(cpu_transcoder)));
3827 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3828 I915_READ(HBLANK(cpu_transcoder)));
3829 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3830 I915_READ(HSYNC(cpu_transcoder)));
3831
3832 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3833 I915_READ(VTOTAL(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3835 I915_READ(VBLANK(cpu_transcoder)));
3836 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3837 I915_READ(VSYNC(cpu_transcoder)));
3838 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3839 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3840 }
3841
3842 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3843 {
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 uint32_t temp;
3846
3847 temp = I915_READ(SOUTH_CHICKEN1);
3848 if (temp & FDI_BC_BIFURCATION_SELECT)
3849 return;
3850
3851 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3852 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3853
3854 temp |= FDI_BC_BIFURCATION_SELECT;
3855 DRM_DEBUG_KMS("enabling fdi C rx\n");
3856 I915_WRITE(SOUTH_CHICKEN1, temp);
3857 POSTING_READ(SOUTH_CHICKEN1);
3858 }
3859
3860 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3861 {
3862 struct drm_device *dev = intel_crtc->base.dev;
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864
3865 switch (intel_crtc->pipe) {
3866 case PIPE_A:
3867 break;
3868 case PIPE_B:
3869 if (intel_crtc->config->fdi_lanes > 2)
3870 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3871 else
3872 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874 break;
3875 case PIPE_C:
3876 cpt_enable_fdi_bc_bifurcation(dev);
3877
3878 break;
3879 default:
3880 BUG();
3881 }
3882 }
3883
3884 /*
3885 * Enable PCH resources required for PCH ports:
3886 * - PCH PLLs
3887 * - FDI training & RX/TX
3888 * - update transcoder timings
3889 * - DP transcoding bits
3890 * - transcoder
3891 */
3892 static void ironlake_pch_enable(struct drm_crtc *crtc)
3893 {
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
3898 u32 reg, temp;
3899
3900 assert_pch_transcoder_disabled(dev_priv, pipe);
3901
3902 if (IS_IVYBRIDGE(dev))
3903 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3904
3905 /* Write the TU size bits before fdi link training, so that error
3906 * detection works. */
3907 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3908 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3909
3910 /* For PCH output, training FDI link */
3911 dev_priv->display.fdi_link_train(crtc);
3912
3913 /* We need to program the right clock selection before writing the pixel
3914 * mutliplier into the DPLL. */
3915 if (HAS_PCH_CPT(dev)) {
3916 u32 sel;
3917
3918 temp = I915_READ(PCH_DPLL_SEL);
3919 temp |= TRANS_DPLL_ENABLE(pipe);
3920 sel = TRANS_DPLLB_SEL(pipe);
3921 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3922 temp |= sel;
3923 else
3924 temp &= ~sel;
3925 I915_WRITE(PCH_DPLL_SEL, temp);
3926 }
3927
3928 /* XXX: pch pll's can be enabled any time before we enable the PCH
3929 * transcoder, and we actually should do this to not upset any PCH
3930 * transcoder that already use the clock when we share it.
3931 *
3932 * Note that enable_shared_dpll tries to do the right thing, but
3933 * get_shared_dpll unconditionally resets the pll - we need that to have
3934 * the right LVDS enable sequence. */
3935 intel_enable_shared_dpll(intel_crtc);
3936
3937 /* set transcoder timing, panel must allow it */
3938 assert_panel_unlocked(dev_priv, pipe);
3939 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3940
3941 intel_fdi_normal_train(crtc);
3942
3943 /* For PCH DP, enable TRANS_DP_CTL */
3944 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3945 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3946 reg = TRANS_DP_CTL(pipe);
3947 temp = I915_READ(reg);
3948 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3949 TRANS_DP_SYNC_MASK |
3950 TRANS_DP_BPC_MASK);
3951 temp |= (TRANS_DP_OUTPUT_ENABLE |
3952 TRANS_DP_ENH_FRAMING);
3953 temp |= bpc << 9; /* same format but at 11:9 */
3954
3955 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3956 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3957 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3958 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3959
3960 switch (intel_trans_dp_port_sel(crtc)) {
3961 case PCH_DP_B:
3962 temp |= TRANS_DP_PORT_SEL_B;
3963 break;
3964 case PCH_DP_C:
3965 temp |= TRANS_DP_PORT_SEL_C;
3966 break;
3967 case PCH_DP_D:
3968 temp |= TRANS_DP_PORT_SEL_D;
3969 break;
3970 default:
3971 BUG();
3972 }
3973
3974 I915_WRITE(reg, temp);
3975 }
3976
3977 ironlake_enable_pch_transcoder(dev_priv, pipe);
3978 }
3979
3980 static void lpt_pch_enable(struct drm_crtc *crtc)
3981 {
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3986
3987 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3988
3989 lpt_program_iclkip(crtc);
3990
3991 /* Set transcoder timing. */
3992 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3993
3994 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3995 }
3996
3997 void intel_put_shared_dpll(struct intel_crtc *crtc)
3998 {
3999 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4000
4001 if (pll == NULL)
4002 return;
4003
4004 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4005 WARN(1, "bad %s crtc mask\n", pll->name);
4006 return;
4007 }
4008
4009 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4010 if (pll->config.crtc_mask == 0) {
4011 WARN_ON(pll->on);
4012 WARN_ON(pll->active);
4013 }
4014
4015 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4016 }
4017
4018 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4019 struct intel_crtc_state *crtc_state)
4020 {
4021 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4022 struct intel_shared_dpll *pll;
4023 enum intel_dpll_id i;
4024
4025 if (HAS_PCH_IBX(dev_priv->dev)) {
4026 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4027 i = (enum intel_dpll_id) crtc->pipe;
4028 pll = &dev_priv->shared_dplls[i];
4029
4030 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4031 crtc->base.base.id, pll->name);
4032
4033 WARN_ON(pll->new_config->crtc_mask);
4034
4035 goto found;
4036 }
4037
4038 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4039 pll = &dev_priv->shared_dplls[i];
4040
4041 /* Only want to check enabled timings first */
4042 if (pll->new_config->crtc_mask == 0)
4043 continue;
4044
4045 if (memcmp(&crtc_state->dpll_hw_state,
4046 &pll->new_config->hw_state,
4047 sizeof(pll->new_config->hw_state)) == 0) {
4048 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4049 crtc->base.base.id, pll->name,
4050 pll->new_config->crtc_mask,
4051 pll->active);
4052 goto found;
4053 }
4054 }
4055
4056 /* Ok no matching timings, maybe there's a free one? */
4057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4058 pll = &dev_priv->shared_dplls[i];
4059 if (pll->new_config->crtc_mask == 0) {
4060 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4061 crtc->base.base.id, pll->name);
4062 goto found;
4063 }
4064 }
4065
4066 return NULL;
4067
4068 found:
4069 if (pll->new_config->crtc_mask == 0)
4070 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4071
4072 crtc_state->shared_dpll = i;
4073 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4074 pipe_name(crtc->pipe));
4075
4076 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4077
4078 return pll;
4079 }
4080
4081 /**
4082 * intel_shared_dpll_start_config - start a new PLL staged config
4083 * @dev_priv: DRM device
4084 * @clear_pipes: mask of pipes that will have their PLLs freed
4085 *
4086 * Starts a new PLL staged config, copying the current config but
4087 * releasing the references of pipes specified in clear_pipes.
4088 */
4089 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4090 unsigned clear_pipes)
4091 {
4092 struct intel_shared_dpll *pll;
4093 enum intel_dpll_id i;
4094
4095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4096 pll = &dev_priv->shared_dplls[i];
4097
4098 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4099 GFP_KERNEL);
4100 if (!pll->new_config)
4101 goto cleanup;
4102
4103 pll->new_config->crtc_mask &= ~clear_pipes;
4104 }
4105
4106 return 0;
4107
4108 cleanup:
4109 while (--i >= 0) {
4110 pll = &dev_priv->shared_dplls[i];
4111 kfree(pll->new_config);
4112 pll->new_config = NULL;
4113 }
4114
4115 return -ENOMEM;
4116 }
4117
4118 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4119 {
4120 struct intel_shared_dpll *pll;
4121 enum intel_dpll_id i;
4122
4123 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4124 pll = &dev_priv->shared_dplls[i];
4125
4126 WARN_ON(pll->new_config == &pll->config);
4127
4128 pll->config = *pll->new_config;
4129 kfree(pll->new_config);
4130 pll->new_config = NULL;
4131 }
4132 }
4133
4134 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4135 {
4136 struct intel_shared_dpll *pll;
4137 enum intel_dpll_id i;
4138
4139 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4140 pll = &dev_priv->shared_dplls[i];
4141
4142 WARN_ON(pll->new_config == &pll->config);
4143
4144 kfree(pll->new_config);
4145 pll->new_config = NULL;
4146 }
4147 }
4148
4149 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4150 {
4151 struct drm_i915_private *dev_priv = dev->dev_private;
4152 int dslreg = PIPEDSL(pipe);
4153 u32 temp;
4154
4155 temp = I915_READ(dslreg);
4156 udelay(500);
4157 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4158 if (wait_for(I915_READ(dslreg) != temp, 5))
4159 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4160 }
4161 }
4162
4163 static void skylake_pfit_enable(struct intel_crtc *crtc)
4164 {
4165 struct drm_device *dev = crtc->base.dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int pipe = crtc->pipe;
4168
4169 if (crtc->config->pch_pfit.enabled) {
4170 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4171 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4172 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4173 }
4174 }
4175
4176 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4177 {
4178 struct drm_device *dev = crtc->base.dev;
4179 struct drm_i915_private *dev_priv = dev->dev_private;
4180 int pipe = crtc->pipe;
4181
4182 if (crtc->config->pch_pfit.enabled) {
4183 /* Force use of hard-coded filter coefficients
4184 * as some pre-programmed values are broken,
4185 * e.g. x201.
4186 */
4187 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4188 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4189 PF_PIPE_SEL_IVB(pipe));
4190 else
4191 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4192 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4193 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4194 }
4195 }
4196
4197 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4198 {
4199 struct drm_device *dev = crtc->dev;
4200 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4201 struct drm_plane *plane;
4202 struct intel_plane *intel_plane;
4203
4204 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4205 intel_plane = to_intel_plane(plane);
4206 if (intel_plane->pipe == pipe)
4207 intel_plane_restore(&intel_plane->base);
4208 }
4209 }
4210
4211 /*
4212 * Disable a plane internally without actually modifying the plane's state.
4213 * This will allow us to easily restore the plane later by just reprogramming
4214 * its state.
4215 */
4216 static void disable_plane_internal(struct drm_plane *plane)
4217 {
4218 struct intel_plane *intel_plane = to_intel_plane(plane);
4219 struct drm_plane_state *state =
4220 plane->funcs->atomic_duplicate_state(plane);
4221 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4222
4223 intel_state->visible = false;
4224 intel_plane->commit_plane(plane, intel_state);
4225
4226 intel_plane_destroy_state(plane, state);
4227 }
4228
4229 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4230 {
4231 struct drm_device *dev = crtc->dev;
4232 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4233 struct drm_plane *plane;
4234 struct intel_plane *intel_plane;
4235
4236 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4237 intel_plane = to_intel_plane(plane);
4238 if (plane->fb && intel_plane->pipe == pipe)
4239 disable_plane_internal(plane);
4240 }
4241 }
4242
4243 void hsw_enable_ips(struct intel_crtc *crtc)
4244 {
4245 struct drm_device *dev = crtc->base.dev;
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247
4248 if (!crtc->config->ips_enabled)
4249 return;
4250
4251 /* We can only enable IPS after we enable a plane and wait for a vblank */
4252 intel_wait_for_vblank(dev, crtc->pipe);
4253
4254 assert_plane_enabled(dev_priv, crtc->plane);
4255 if (IS_BROADWELL(dev)) {
4256 mutex_lock(&dev_priv->rps.hw_lock);
4257 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4258 mutex_unlock(&dev_priv->rps.hw_lock);
4259 /* Quoting Art Runyan: "its not safe to expect any particular
4260 * value in IPS_CTL bit 31 after enabling IPS through the
4261 * mailbox." Moreover, the mailbox may return a bogus state,
4262 * so we need to just enable it and continue on.
4263 */
4264 } else {
4265 I915_WRITE(IPS_CTL, IPS_ENABLE);
4266 /* The bit only becomes 1 in the next vblank, so this wait here
4267 * is essentially intel_wait_for_vblank. If we don't have this
4268 * and don't wait for vblanks until the end of crtc_enable, then
4269 * the HW state readout code will complain that the expected
4270 * IPS_CTL value is not the one we read. */
4271 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4272 DRM_ERROR("Timed out waiting for IPS enable\n");
4273 }
4274 }
4275
4276 void hsw_disable_ips(struct intel_crtc *crtc)
4277 {
4278 struct drm_device *dev = crtc->base.dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280
4281 if (!crtc->config->ips_enabled)
4282 return;
4283
4284 assert_plane_enabled(dev_priv, crtc->plane);
4285 if (IS_BROADWELL(dev)) {
4286 mutex_lock(&dev_priv->rps.hw_lock);
4287 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4288 mutex_unlock(&dev_priv->rps.hw_lock);
4289 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4290 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4291 DRM_ERROR("Timed out waiting for IPS disable\n");
4292 } else {
4293 I915_WRITE(IPS_CTL, 0);
4294 POSTING_READ(IPS_CTL);
4295 }
4296
4297 /* We need to wait for a vblank before we can disable the plane. */
4298 intel_wait_for_vblank(dev, crtc->pipe);
4299 }
4300
4301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4302 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4303 {
4304 struct drm_device *dev = crtc->dev;
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307 enum pipe pipe = intel_crtc->pipe;
4308 int palreg = PALETTE(pipe);
4309 int i;
4310 bool reenable_ips = false;
4311
4312 /* The clocks have to be on to load the palette. */
4313 if (!crtc->state->enable || !intel_crtc->active)
4314 return;
4315
4316 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4317 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4318 assert_dsi_pll_enabled(dev_priv);
4319 else
4320 assert_pll_enabled(dev_priv, pipe);
4321 }
4322
4323 /* use legacy palette for Ironlake */
4324 if (!HAS_GMCH_DISPLAY(dev))
4325 palreg = LGC_PALETTE(pipe);
4326
4327 /* Workaround : Do not read or write the pipe palette/gamma data while
4328 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4329 */
4330 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4331 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4332 GAMMA_MODE_MODE_SPLIT)) {
4333 hsw_disable_ips(intel_crtc);
4334 reenable_ips = true;
4335 }
4336
4337 for (i = 0; i < 256; i++) {
4338 I915_WRITE(palreg + 4 * i,
4339 (intel_crtc->lut_r[i] << 16) |
4340 (intel_crtc->lut_g[i] << 8) |
4341 intel_crtc->lut_b[i]);
4342 }
4343
4344 if (reenable_ips)
4345 hsw_enable_ips(intel_crtc);
4346 }
4347
4348 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4349 {
4350 if (!enable && intel_crtc->overlay) {
4351 struct drm_device *dev = intel_crtc->base.dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353
4354 mutex_lock(&dev->struct_mutex);
4355 dev_priv->mm.interruptible = false;
4356 (void) intel_overlay_switch_off(intel_crtc->overlay);
4357 dev_priv->mm.interruptible = true;
4358 mutex_unlock(&dev->struct_mutex);
4359 }
4360
4361 /* Let userspace switch the overlay on again. In most cases userspace
4362 * has to recompute where to put it anyway.
4363 */
4364 }
4365
4366 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4367 {
4368 struct drm_device *dev = crtc->dev;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 int pipe = intel_crtc->pipe;
4371
4372 intel_enable_primary_hw_plane(crtc->primary, crtc);
4373 intel_enable_sprite_planes(crtc);
4374 intel_crtc_update_cursor(crtc, true);
4375 intel_crtc_dpms_overlay(intel_crtc, true);
4376
4377 hsw_enable_ips(intel_crtc);
4378
4379 mutex_lock(&dev->struct_mutex);
4380 intel_fbc_update(dev);
4381 mutex_unlock(&dev->struct_mutex);
4382
4383 /*
4384 * FIXME: Once we grow proper nuclear flip support out of this we need
4385 * to compute the mask of flip planes precisely. For the time being
4386 * consider this a flip from a NULL plane.
4387 */
4388 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4389 }
4390
4391 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4392 {
4393 struct drm_device *dev = crtc->dev;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396 int pipe = intel_crtc->pipe;
4397
4398 intel_crtc_wait_for_pending_flips(crtc);
4399
4400 if (dev_priv->fbc.crtc == intel_crtc)
4401 intel_fbc_disable(dev);
4402
4403 hsw_disable_ips(intel_crtc);
4404
4405 intel_crtc_dpms_overlay(intel_crtc, false);
4406 intel_crtc_update_cursor(crtc, false);
4407 intel_disable_sprite_planes(crtc);
4408 intel_disable_primary_hw_plane(crtc->primary, crtc);
4409
4410 /*
4411 * FIXME: Once we grow proper nuclear flip support out of this we need
4412 * to compute the mask of flip planes precisely. For the time being
4413 * consider this a flip to a NULL plane.
4414 */
4415 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4416 }
4417
4418 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423 struct intel_encoder *encoder;
4424 int pipe = intel_crtc->pipe;
4425
4426 WARN_ON(!crtc->state->enable);
4427
4428 if (intel_crtc->active)
4429 return;
4430
4431 if (intel_crtc->config->has_pch_encoder)
4432 intel_prepare_shared_dpll(intel_crtc);
4433
4434 if (intel_crtc->config->has_dp_encoder)
4435 intel_dp_set_m_n(intel_crtc, M1_N1);
4436
4437 intel_set_pipe_timings(intel_crtc);
4438
4439 if (intel_crtc->config->has_pch_encoder) {
4440 intel_cpu_transcoder_set_m_n(intel_crtc,
4441 &intel_crtc->config->fdi_m_n, NULL);
4442 }
4443
4444 ironlake_set_pipeconf(crtc);
4445
4446 intel_crtc->active = true;
4447
4448 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4449 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4450
4451 for_each_encoder_on_crtc(dev, crtc, encoder)
4452 if (encoder->pre_enable)
4453 encoder->pre_enable(encoder);
4454
4455 if (intel_crtc->config->has_pch_encoder) {
4456 /* Note: FDI PLL enabling _must_ be done before we enable the
4457 * cpu pipes, hence this is separate from all the other fdi/pch
4458 * enabling. */
4459 ironlake_fdi_pll_enable(intel_crtc);
4460 } else {
4461 assert_fdi_tx_disabled(dev_priv, pipe);
4462 assert_fdi_rx_disabled(dev_priv, pipe);
4463 }
4464
4465 ironlake_pfit_enable(intel_crtc);
4466
4467 /*
4468 * On ILK+ LUT must be loaded before the pipe is running but with
4469 * clocks enabled
4470 */
4471 intel_crtc_load_lut(crtc);
4472
4473 intel_update_watermarks(crtc);
4474 intel_enable_pipe(intel_crtc);
4475
4476 if (intel_crtc->config->has_pch_encoder)
4477 ironlake_pch_enable(crtc);
4478
4479 assert_vblank_disabled(crtc);
4480 drm_crtc_vblank_on(crtc);
4481
4482 for_each_encoder_on_crtc(dev, crtc, encoder)
4483 encoder->enable(encoder);
4484
4485 if (HAS_PCH_CPT(dev))
4486 cpt_verify_modeset(dev, intel_crtc->pipe);
4487
4488 intel_crtc_enable_planes(crtc);
4489 }
4490
4491 /* IPS only exists on ULT machines and is tied to pipe A. */
4492 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4493 {
4494 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4495 }
4496
4497 /*
4498 * This implements the workaround described in the "notes" section of the mode
4499 * set sequence documentation. When going from no pipes or single pipe to
4500 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4501 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4502 */
4503 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->base.dev;
4506 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4507
4508 /* We want to get the other_active_crtc only if there's only 1 other
4509 * active crtc. */
4510 for_each_intel_crtc(dev, crtc_it) {
4511 if (!crtc_it->active || crtc_it == crtc)
4512 continue;
4513
4514 if (other_active_crtc)
4515 return;
4516
4517 other_active_crtc = crtc_it;
4518 }
4519 if (!other_active_crtc)
4520 return;
4521
4522 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4523 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4524 }
4525
4526 static void haswell_crtc_enable(struct drm_crtc *crtc)
4527 {
4528 struct drm_device *dev = crtc->dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531 struct intel_encoder *encoder;
4532 int pipe = intel_crtc->pipe;
4533
4534 WARN_ON(!crtc->state->enable);
4535
4536 if (intel_crtc->active)
4537 return;
4538
4539 if (intel_crtc_to_shared_dpll(intel_crtc))
4540 intel_enable_shared_dpll(intel_crtc);
4541
4542 if (intel_crtc->config->has_dp_encoder)
4543 intel_dp_set_m_n(intel_crtc, M1_N1);
4544
4545 intel_set_pipe_timings(intel_crtc);
4546
4547 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4548 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4549 intel_crtc->config->pixel_multiplier - 1);
4550 }
4551
4552 if (intel_crtc->config->has_pch_encoder) {
4553 intel_cpu_transcoder_set_m_n(intel_crtc,
4554 &intel_crtc->config->fdi_m_n, NULL);
4555 }
4556
4557 haswell_set_pipeconf(crtc);
4558
4559 intel_set_pipe_csc(crtc);
4560
4561 intel_crtc->active = true;
4562
4563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4564 for_each_encoder_on_crtc(dev, crtc, encoder)
4565 if (encoder->pre_enable)
4566 encoder->pre_enable(encoder);
4567
4568 if (intel_crtc->config->has_pch_encoder) {
4569 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4570 true);
4571 dev_priv->display.fdi_link_train(crtc);
4572 }
4573
4574 intel_ddi_enable_pipe_clock(intel_crtc);
4575
4576 if (IS_SKYLAKE(dev))
4577 skylake_pfit_enable(intel_crtc);
4578 else
4579 ironlake_pfit_enable(intel_crtc);
4580
4581 /*
4582 * On ILK+ LUT must be loaded before the pipe is running but with
4583 * clocks enabled
4584 */
4585 intel_crtc_load_lut(crtc);
4586
4587 intel_ddi_set_pipe_settings(crtc);
4588 intel_ddi_enable_transcoder_func(crtc);
4589
4590 intel_update_watermarks(crtc);
4591 intel_enable_pipe(intel_crtc);
4592
4593 if (intel_crtc->config->has_pch_encoder)
4594 lpt_pch_enable(crtc);
4595
4596 if (intel_crtc->config->dp_encoder_is_mst)
4597 intel_ddi_set_vc_payload_alloc(crtc, true);
4598
4599 assert_vblank_disabled(crtc);
4600 drm_crtc_vblank_on(crtc);
4601
4602 for_each_encoder_on_crtc(dev, crtc, encoder) {
4603 encoder->enable(encoder);
4604 intel_opregion_notify_encoder(encoder, true);
4605 }
4606
4607 /* If we change the relative order between pipe/planes enabling, we need
4608 * to change the workaround. */
4609 haswell_mode_set_planes_workaround(intel_crtc);
4610 intel_crtc_enable_planes(crtc);
4611 }
4612
4613 static void skylake_pfit_disable(struct intel_crtc *crtc)
4614 {
4615 struct drm_device *dev = crtc->base.dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 int pipe = crtc->pipe;
4618
4619 /* To avoid upsetting the power well on haswell only disable the pfit if
4620 * it's in use. The hw state code will make sure we get this right. */
4621 if (crtc->config->pch_pfit.enabled) {
4622 I915_WRITE(PS_CTL(pipe), 0);
4623 I915_WRITE(PS_WIN_POS(pipe), 0);
4624 I915_WRITE(PS_WIN_SZ(pipe), 0);
4625 }
4626 }
4627
4628 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4629 {
4630 struct drm_device *dev = crtc->base.dev;
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632 int pipe = crtc->pipe;
4633
4634 /* To avoid upsetting the power well on haswell only disable the pfit if
4635 * it's in use. The hw state code will make sure we get this right. */
4636 if (crtc->config->pch_pfit.enabled) {
4637 I915_WRITE(PF_CTL(pipe), 0);
4638 I915_WRITE(PF_WIN_POS(pipe), 0);
4639 I915_WRITE(PF_WIN_SZ(pipe), 0);
4640 }
4641 }
4642
4643 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4644 {
4645 struct drm_device *dev = crtc->dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4648 struct intel_encoder *encoder;
4649 int pipe = intel_crtc->pipe;
4650 u32 reg, temp;
4651
4652 if (!intel_crtc->active)
4653 return;
4654
4655 intel_crtc_disable_planes(crtc);
4656
4657 for_each_encoder_on_crtc(dev, crtc, encoder)
4658 encoder->disable(encoder);
4659
4660 drm_crtc_vblank_off(crtc);
4661 assert_vblank_disabled(crtc);
4662
4663 if (intel_crtc->config->has_pch_encoder)
4664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4665
4666 intel_disable_pipe(intel_crtc);
4667
4668 ironlake_pfit_disable(intel_crtc);
4669
4670 for_each_encoder_on_crtc(dev, crtc, encoder)
4671 if (encoder->post_disable)
4672 encoder->post_disable(encoder);
4673
4674 if (intel_crtc->config->has_pch_encoder) {
4675 ironlake_fdi_disable(crtc);
4676
4677 ironlake_disable_pch_transcoder(dev_priv, pipe);
4678
4679 if (HAS_PCH_CPT(dev)) {
4680 /* disable TRANS_DP_CTL */
4681 reg = TRANS_DP_CTL(pipe);
4682 temp = I915_READ(reg);
4683 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4684 TRANS_DP_PORT_SEL_MASK);
4685 temp |= TRANS_DP_PORT_SEL_NONE;
4686 I915_WRITE(reg, temp);
4687
4688 /* disable DPLL_SEL */
4689 temp = I915_READ(PCH_DPLL_SEL);
4690 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4691 I915_WRITE(PCH_DPLL_SEL, temp);
4692 }
4693
4694 /* disable PCH DPLL */
4695 intel_disable_shared_dpll(intel_crtc);
4696
4697 ironlake_fdi_pll_disable(intel_crtc);
4698 }
4699
4700 intel_crtc->active = false;
4701 intel_update_watermarks(crtc);
4702
4703 mutex_lock(&dev->struct_mutex);
4704 intel_fbc_update(dev);
4705 mutex_unlock(&dev->struct_mutex);
4706 }
4707
4708 static void haswell_crtc_disable(struct drm_crtc *crtc)
4709 {
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct intel_encoder *encoder;
4714 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4715
4716 if (!intel_crtc->active)
4717 return;
4718
4719 intel_crtc_disable_planes(crtc);
4720
4721 for_each_encoder_on_crtc(dev, crtc, encoder) {
4722 intel_opregion_notify_encoder(encoder, false);
4723 encoder->disable(encoder);
4724 }
4725
4726 drm_crtc_vblank_off(crtc);
4727 assert_vblank_disabled(crtc);
4728
4729 if (intel_crtc->config->has_pch_encoder)
4730 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4731 false);
4732 intel_disable_pipe(intel_crtc);
4733
4734 if (intel_crtc->config->dp_encoder_is_mst)
4735 intel_ddi_set_vc_payload_alloc(crtc, false);
4736
4737 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4738
4739 if (IS_SKYLAKE(dev))
4740 skylake_pfit_disable(intel_crtc);
4741 else
4742 ironlake_pfit_disable(intel_crtc);
4743
4744 intel_ddi_disable_pipe_clock(intel_crtc);
4745
4746 if (intel_crtc->config->has_pch_encoder) {
4747 lpt_disable_pch_transcoder(dev_priv);
4748 intel_ddi_fdi_disable(crtc);
4749 }
4750
4751 for_each_encoder_on_crtc(dev, crtc, encoder)
4752 if (encoder->post_disable)
4753 encoder->post_disable(encoder);
4754
4755 intel_crtc->active = false;
4756 intel_update_watermarks(crtc);
4757
4758 mutex_lock(&dev->struct_mutex);
4759 intel_fbc_update(dev);
4760 mutex_unlock(&dev->struct_mutex);
4761
4762 if (intel_crtc_to_shared_dpll(intel_crtc))
4763 intel_disable_shared_dpll(intel_crtc);
4764 }
4765
4766 static void ironlake_crtc_off(struct drm_crtc *crtc)
4767 {
4768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769 intel_put_shared_dpll(intel_crtc);
4770 }
4771
4772
4773 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->base.dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc_state *pipe_config = crtc->config;
4778
4779 if (!pipe_config->gmch_pfit.control)
4780 return;
4781
4782 /*
4783 * The panel fitter should only be adjusted whilst the pipe is disabled,
4784 * according to register description and PRM.
4785 */
4786 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4787 assert_pipe_disabled(dev_priv, crtc->pipe);
4788
4789 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4790 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4791
4792 /* Border color in case we don't scale up to the full screen. Black by
4793 * default, change to something else for debugging. */
4794 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4795 }
4796
4797 static enum intel_display_power_domain port_to_power_domain(enum port port)
4798 {
4799 switch (port) {
4800 case PORT_A:
4801 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4802 case PORT_B:
4803 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4804 case PORT_C:
4805 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4806 case PORT_D:
4807 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4808 default:
4809 WARN_ON_ONCE(1);
4810 return POWER_DOMAIN_PORT_OTHER;
4811 }
4812 }
4813
4814 #define for_each_power_domain(domain, mask) \
4815 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4816 if ((1 << (domain)) & (mask))
4817
4818 enum intel_display_power_domain
4819 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4820 {
4821 struct drm_device *dev = intel_encoder->base.dev;
4822 struct intel_digital_port *intel_dig_port;
4823
4824 switch (intel_encoder->type) {
4825 case INTEL_OUTPUT_UNKNOWN:
4826 /* Only DDI platforms should ever use this output type */
4827 WARN_ON_ONCE(!HAS_DDI(dev));
4828 case INTEL_OUTPUT_DISPLAYPORT:
4829 case INTEL_OUTPUT_HDMI:
4830 case INTEL_OUTPUT_EDP:
4831 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4832 return port_to_power_domain(intel_dig_port->port);
4833 case INTEL_OUTPUT_DP_MST:
4834 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4835 return port_to_power_domain(intel_dig_port->port);
4836 case INTEL_OUTPUT_ANALOG:
4837 return POWER_DOMAIN_PORT_CRT;
4838 case INTEL_OUTPUT_DSI:
4839 return POWER_DOMAIN_PORT_DSI;
4840 default:
4841 return POWER_DOMAIN_PORT_OTHER;
4842 }
4843 }
4844
4845 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4846 {
4847 struct drm_device *dev = crtc->dev;
4848 struct intel_encoder *intel_encoder;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850 enum pipe pipe = intel_crtc->pipe;
4851 unsigned long mask;
4852 enum transcoder transcoder;
4853
4854 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4855
4856 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4857 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4858 if (intel_crtc->config->pch_pfit.enabled ||
4859 intel_crtc->config->pch_pfit.force_thru)
4860 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4861
4862 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4863 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4864
4865 return mask;
4866 }
4867
4868 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4869 {
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4872 struct intel_crtc *crtc;
4873
4874 /*
4875 * First get all needed power domains, then put all unneeded, to avoid
4876 * any unnecessary toggling of the power wells.
4877 */
4878 for_each_intel_crtc(dev, crtc) {
4879 enum intel_display_power_domain domain;
4880
4881 if (!crtc->base.state->enable)
4882 continue;
4883
4884 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4885
4886 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4887 intel_display_power_get(dev_priv, domain);
4888 }
4889
4890 if (dev_priv->display.modeset_global_resources)
4891 dev_priv->display.modeset_global_resources(dev);
4892
4893 for_each_intel_crtc(dev, crtc) {
4894 enum intel_display_power_domain domain;
4895
4896 for_each_power_domain(domain, crtc->enabled_power_domains)
4897 intel_display_power_put(dev_priv, domain);
4898
4899 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4900 }
4901
4902 intel_display_set_init_power(dev_priv, false);
4903 }
4904
4905 /* returns HPLL frequency in kHz */
4906 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4907 {
4908 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4909
4910 /* Obtain SKU information */
4911 mutex_lock(&dev_priv->dpio_lock);
4912 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4913 CCK_FUSE_HPLL_FREQ_MASK;
4914 mutex_unlock(&dev_priv->dpio_lock);
4915
4916 return vco_freq[hpll_freq] * 1000;
4917 }
4918
4919 static void vlv_update_cdclk(struct drm_device *dev)
4920 {
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922
4923 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4924 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4925 dev_priv->vlv_cdclk_freq);
4926
4927 /*
4928 * Program the gmbus_freq based on the cdclk frequency.
4929 * BSpec erroneously claims we should aim for 4MHz, but
4930 * in fact 1MHz is the correct frequency.
4931 */
4932 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4933 }
4934
4935 /* Adjust CDclk dividers to allow high res or save power if possible */
4936 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4937 {
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 u32 val, cmd;
4940
4941 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4942
4943 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4944 cmd = 2;
4945 else if (cdclk == 266667)
4946 cmd = 1;
4947 else
4948 cmd = 0;
4949
4950 mutex_lock(&dev_priv->rps.hw_lock);
4951 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4952 val &= ~DSPFREQGUAR_MASK;
4953 val |= (cmd << DSPFREQGUAR_SHIFT);
4954 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4955 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4956 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4957 50)) {
4958 DRM_ERROR("timed out waiting for CDclk change\n");
4959 }
4960 mutex_unlock(&dev_priv->rps.hw_lock);
4961
4962 if (cdclk == 400000) {
4963 u32 divider;
4964
4965 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4966
4967 mutex_lock(&dev_priv->dpio_lock);
4968 /* adjust cdclk divider */
4969 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4970 val &= ~DISPLAY_FREQUENCY_VALUES;
4971 val |= divider;
4972 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4973
4974 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4975 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4976 50))
4977 DRM_ERROR("timed out waiting for CDclk change\n");
4978 mutex_unlock(&dev_priv->dpio_lock);
4979 }
4980
4981 mutex_lock(&dev_priv->dpio_lock);
4982 /* adjust self-refresh exit latency value */
4983 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4984 val &= ~0x7f;
4985
4986 /*
4987 * For high bandwidth configs, we set a higher latency in the bunit
4988 * so that the core display fetch happens in time to avoid underruns.
4989 */
4990 if (cdclk == 400000)
4991 val |= 4500 / 250; /* 4.5 usec */
4992 else
4993 val |= 3000 / 250; /* 3.0 usec */
4994 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4995 mutex_unlock(&dev_priv->dpio_lock);
4996
4997 vlv_update_cdclk(dev);
4998 }
4999
5000 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5001 {
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 u32 val, cmd;
5004
5005 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5006
5007 switch (cdclk) {
5008 case 333333:
5009 case 320000:
5010 case 266667:
5011 case 200000:
5012 break;
5013 default:
5014 MISSING_CASE(cdclk);
5015 return;
5016 }
5017
5018 /*
5019 * Specs are full of misinformation, but testing on actual
5020 * hardware has shown that we just need to write the desired
5021 * CCK divider into the Punit register.
5022 */
5023 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5024
5025 mutex_lock(&dev_priv->rps.hw_lock);
5026 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5027 val &= ~DSPFREQGUAR_MASK_CHV;
5028 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5029 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5030 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5031 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5032 50)) {
5033 DRM_ERROR("timed out waiting for CDclk change\n");
5034 }
5035 mutex_unlock(&dev_priv->rps.hw_lock);
5036
5037 vlv_update_cdclk(dev);
5038 }
5039
5040 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5041 int max_pixclk)
5042 {
5043 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5044 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5045
5046 /*
5047 * Really only a few cases to deal with, as only 4 CDclks are supported:
5048 * 200MHz
5049 * 267MHz
5050 * 320/333MHz (depends on HPLL freq)
5051 * 400MHz (VLV only)
5052 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5053 * of the lower bin and adjust if needed.
5054 *
5055 * We seem to get an unstable or solid color picture at 200MHz.
5056 * Not sure what's wrong. For now use 200MHz only when all pipes
5057 * are off.
5058 */
5059 if (!IS_CHERRYVIEW(dev_priv) &&
5060 max_pixclk > freq_320*limit/100)
5061 return 400000;
5062 else if (max_pixclk > 266667*limit/100)
5063 return freq_320;
5064 else if (max_pixclk > 0)
5065 return 266667;
5066 else
5067 return 200000;
5068 }
5069
5070 /* compute the max pixel clock for new configuration */
5071 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5072 {
5073 struct drm_device *dev = dev_priv->dev;
5074 struct intel_crtc *intel_crtc;
5075 int max_pixclk = 0;
5076
5077 for_each_intel_crtc(dev, intel_crtc) {
5078 if (intel_crtc->new_enabled)
5079 max_pixclk = max(max_pixclk,
5080 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5081 }
5082
5083 return max_pixclk;
5084 }
5085
5086 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5087 unsigned *prepare_pipes)
5088 {
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_crtc *intel_crtc;
5091 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5092
5093 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5094 dev_priv->vlv_cdclk_freq)
5095 return;
5096
5097 /* disable/enable all currently active pipes while we change cdclk */
5098 for_each_intel_crtc(dev, intel_crtc)
5099 if (intel_crtc->base.state->enable)
5100 *prepare_pipes |= (1 << intel_crtc->pipe);
5101 }
5102
5103 static void valleyview_modeset_global_resources(struct drm_device *dev)
5104 {
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5107 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5108
5109 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5110 /*
5111 * FIXME: We can end up here with all power domains off, yet
5112 * with a CDCLK frequency other than the minimum. To account
5113 * for this take the PIPE-A power domain, which covers the HW
5114 * blocks needed for the following programming. This can be
5115 * removed once it's guaranteed that we get here either with
5116 * the minimum CDCLK set, or the required power domains
5117 * enabled.
5118 */
5119 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5120
5121 if (IS_CHERRYVIEW(dev))
5122 cherryview_set_cdclk(dev, req_cdclk);
5123 else
5124 valleyview_set_cdclk(dev, req_cdclk);
5125
5126 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5127 }
5128 }
5129
5130 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5131 {
5132 struct drm_device *dev = crtc->dev;
5133 struct drm_i915_private *dev_priv = to_i915(dev);
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135 struct intel_encoder *encoder;
5136 int pipe = intel_crtc->pipe;
5137 bool is_dsi;
5138
5139 WARN_ON(!crtc->state->enable);
5140
5141 if (intel_crtc->active)
5142 return;
5143
5144 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5145
5146 if (!is_dsi) {
5147 if (IS_CHERRYVIEW(dev))
5148 chv_prepare_pll(intel_crtc, intel_crtc->config);
5149 else
5150 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5151 }
5152
5153 if (intel_crtc->config->has_dp_encoder)
5154 intel_dp_set_m_n(intel_crtc, M1_N1);
5155
5156 intel_set_pipe_timings(intel_crtc);
5157
5158 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160
5161 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5162 I915_WRITE(CHV_CANVAS(pipe), 0);
5163 }
5164
5165 i9xx_set_pipeconf(intel_crtc);
5166
5167 intel_crtc->active = true;
5168
5169 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5170
5171 for_each_encoder_on_crtc(dev, crtc, encoder)
5172 if (encoder->pre_pll_enable)
5173 encoder->pre_pll_enable(encoder);
5174
5175 if (!is_dsi) {
5176 if (IS_CHERRYVIEW(dev))
5177 chv_enable_pll(intel_crtc, intel_crtc->config);
5178 else
5179 vlv_enable_pll(intel_crtc, intel_crtc->config);
5180 }
5181
5182 for_each_encoder_on_crtc(dev, crtc, encoder)
5183 if (encoder->pre_enable)
5184 encoder->pre_enable(encoder);
5185
5186 i9xx_pfit_enable(intel_crtc);
5187
5188 intel_crtc_load_lut(crtc);
5189
5190 intel_update_watermarks(crtc);
5191 intel_enable_pipe(intel_crtc);
5192
5193 assert_vblank_disabled(crtc);
5194 drm_crtc_vblank_on(crtc);
5195
5196 for_each_encoder_on_crtc(dev, crtc, encoder)
5197 encoder->enable(encoder);
5198
5199 intel_crtc_enable_planes(crtc);
5200
5201 /* Underruns don't raise interrupts, so check manually. */
5202 i9xx_check_fifo_underruns(dev_priv);
5203 }
5204
5205 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5206 {
5207 struct drm_device *dev = crtc->base.dev;
5208 struct drm_i915_private *dev_priv = dev->dev_private;
5209
5210 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5211 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5212 }
5213
5214 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5215 {
5216 struct drm_device *dev = crtc->dev;
5217 struct drm_i915_private *dev_priv = to_i915(dev);
5218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5219 struct intel_encoder *encoder;
5220 int pipe = intel_crtc->pipe;
5221
5222 WARN_ON(!crtc->state->enable);
5223
5224 if (intel_crtc->active)
5225 return;
5226
5227 i9xx_set_pll_dividers(intel_crtc);
5228
5229 if (intel_crtc->config->has_dp_encoder)
5230 intel_dp_set_m_n(intel_crtc, M1_N1);
5231
5232 intel_set_pipe_timings(intel_crtc);
5233
5234 i9xx_set_pipeconf(intel_crtc);
5235
5236 intel_crtc->active = true;
5237
5238 if (!IS_GEN2(dev))
5239 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5240
5241 for_each_encoder_on_crtc(dev, crtc, encoder)
5242 if (encoder->pre_enable)
5243 encoder->pre_enable(encoder);
5244
5245 i9xx_enable_pll(intel_crtc);
5246
5247 i9xx_pfit_enable(intel_crtc);
5248
5249 intel_crtc_load_lut(crtc);
5250
5251 intel_update_watermarks(crtc);
5252 intel_enable_pipe(intel_crtc);
5253
5254 assert_vblank_disabled(crtc);
5255 drm_crtc_vblank_on(crtc);
5256
5257 for_each_encoder_on_crtc(dev, crtc, encoder)
5258 encoder->enable(encoder);
5259
5260 intel_crtc_enable_planes(crtc);
5261
5262 /*
5263 * Gen2 reports pipe underruns whenever all planes are disabled.
5264 * So don't enable underrun reporting before at least some planes
5265 * are enabled.
5266 * FIXME: Need to fix the logic to work when we turn off all planes
5267 * but leave the pipe running.
5268 */
5269 if (IS_GEN2(dev))
5270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5271
5272 /* Underruns don't raise interrupts, so check manually. */
5273 i9xx_check_fifo_underruns(dev_priv);
5274 }
5275
5276 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5277 {
5278 struct drm_device *dev = crtc->base.dev;
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5280
5281 if (!crtc->config->gmch_pfit.control)
5282 return;
5283
5284 assert_pipe_disabled(dev_priv, crtc->pipe);
5285
5286 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5287 I915_READ(PFIT_CONTROL));
5288 I915_WRITE(PFIT_CONTROL, 0);
5289 }
5290
5291 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5292 {
5293 struct drm_device *dev = crtc->dev;
5294 struct drm_i915_private *dev_priv = dev->dev_private;
5295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5296 struct intel_encoder *encoder;
5297 int pipe = intel_crtc->pipe;
5298
5299 if (!intel_crtc->active)
5300 return;
5301
5302 /*
5303 * Gen2 reports pipe underruns whenever all planes are disabled.
5304 * So diasble underrun reporting before all the planes get disabled.
5305 * FIXME: Need to fix the logic to work when we turn off all planes
5306 * but leave the pipe running.
5307 */
5308 if (IS_GEN2(dev))
5309 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5310
5311 /*
5312 * Vblank time updates from the shadow to live plane control register
5313 * are blocked if the memory self-refresh mode is active at that
5314 * moment. So to make sure the plane gets truly disabled, disable
5315 * first the self-refresh mode. The self-refresh enable bit in turn
5316 * will be checked/applied by the HW only at the next frame start
5317 * event which is after the vblank start event, so we need to have a
5318 * wait-for-vblank between disabling the plane and the pipe.
5319 */
5320 intel_set_memory_cxsr(dev_priv, false);
5321 intel_crtc_disable_planes(crtc);
5322
5323 /*
5324 * On gen2 planes are double buffered but the pipe isn't, so we must
5325 * wait for planes to fully turn off before disabling the pipe.
5326 * We also need to wait on all gmch platforms because of the
5327 * self-refresh mode constraint explained above.
5328 */
5329 intel_wait_for_vblank(dev, pipe);
5330
5331 for_each_encoder_on_crtc(dev, crtc, encoder)
5332 encoder->disable(encoder);
5333
5334 drm_crtc_vblank_off(crtc);
5335 assert_vblank_disabled(crtc);
5336
5337 intel_disable_pipe(intel_crtc);
5338
5339 i9xx_pfit_disable(intel_crtc);
5340
5341 for_each_encoder_on_crtc(dev, crtc, encoder)
5342 if (encoder->post_disable)
5343 encoder->post_disable(encoder);
5344
5345 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5346 if (IS_CHERRYVIEW(dev))
5347 chv_disable_pll(dev_priv, pipe);
5348 else if (IS_VALLEYVIEW(dev))
5349 vlv_disable_pll(dev_priv, pipe);
5350 else
5351 i9xx_disable_pll(intel_crtc);
5352 }
5353
5354 if (!IS_GEN2(dev))
5355 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5356
5357 intel_crtc->active = false;
5358 intel_update_watermarks(crtc);
5359
5360 mutex_lock(&dev->struct_mutex);
5361 intel_fbc_update(dev);
5362 mutex_unlock(&dev->struct_mutex);
5363 }
5364
5365 static void i9xx_crtc_off(struct drm_crtc *crtc)
5366 {
5367 }
5368
5369 /* Master function to enable/disable CRTC and corresponding power wells */
5370 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5371 {
5372 struct drm_device *dev = crtc->dev;
5373 struct drm_i915_private *dev_priv = dev->dev_private;
5374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5375 enum intel_display_power_domain domain;
5376 unsigned long domains;
5377
5378 if (enable) {
5379 if (!intel_crtc->active) {
5380 domains = get_crtc_power_domains(crtc);
5381 for_each_power_domain(domain, domains)
5382 intel_display_power_get(dev_priv, domain);
5383 intel_crtc->enabled_power_domains = domains;
5384
5385 dev_priv->display.crtc_enable(crtc);
5386 }
5387 } else {
5388 if (intel_crtc->active) {
5389 dev_priv->display.crtc_disable(crtc);
5390
5391 domains = intel_crtc->enabled_power_domains;
5392 for_each_power_domain(domain, domains)
5393 intel_display_power_put(dev_priv, domain);
5394 intel_crtc->enabled_power_domains = 0;
5395 }
5396 }
5397 }
5398
5399 /**
5400 * Sets the power management mode of the pipe and plane.
5401 */
5402 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5403 {
5404 struct drm_device *dev = crtc->dev;
5405 struct intel_encoder *intel_encoder;
5406 bool enable = false;
5407
5408 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5409 enable |= intel_encoder->connectors_active;
5410
5411 intel_crtc_control(crtc, enable);
5412 }
5413
5414 static void intel_crtc_disable(struct drm_crtc *crtc)
5415 {
5416 struct drm_device *dev = crtc->dev;
5417 struct drm_connector *connector;
5418 struct drm_i915_private *dev_priv = dev->dev_private;
5419
5420 /* crtc should still be enabled when we disable it. */
5421 WARN_ON(!crtc->state->enable);
5422
5423 dev_priv->display.crtc_disable(crtc);
5424 dev_priv->display.off(crtc);
5425
5426 crtc->primary->funcs->disable_plane(crtc->primary);
5427
5428 /* Update computed state. */
5429 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5430 if (!connector->encoder || !connector->encoder->crtc)
5431 continue;
5432
5433 if (connector->encoder->crtc != crtc)
5434 continue;
5435
5436 connector->dpms = DRM_MODE_DPMS_OFF;
5437 to_intel_encoder(connector->encoder)->connectors_active = false;
5438 }
5439 }
5440
5441 void intel_encoder_destroy(struct drm_encoder *encoder)
5442 {
5443 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5444
5445 drm_encoder_cleanup(encoder);
5446 kfree(intel_encoder);
5447 }
5448
5449 /* Simple dpms helper for encoders with just one connector, no cloning and only
5450 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5451 * state of the entire output pipe. */
5452 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5453 {
5454 if (mode == DRM_MODE_DPMS_ON) {
5455 encoder->connectors_active = true;
5456
5457 intel_crtc_update_dpms(encoder->base.crtc);
5458 } else {
5459 encoder->connectors_active = false;
5460
5461 intel_crtc_update_dpms(encoder->base.crtc);
5462 }
5463 }
5464
5465 /* Cross check the actual hw state with our own modeset state tracking (and it's
5466 * internal consistency). */
5467 static void intel_connector_check_state(struct intel_connector *connector)
5468 {
5469 if (connector->get_hw_state(connector)) {
5470 struct intel_encoder *encoder = connector->encoder;
5471 struct drm_crtc *crtc;
5472 bool encoder_enabled;
5473 enum pipe pipe;
5474
5475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5476 connector->base.base.id,
5477 connector->base.name);
5478
5479 /* there is no real hw state for MST connectors */
5480 if (connector->mst_port)
5481 return;
5482
5483 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5484 "wrong connector dpms state\n");
5485 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5486 "active connector not linked to encoder\n");
5487
5488 if (encoder) {
5489 I915_STATE_WARN(!encoder->connectors_active,
5490 "encoder->connectors_active not set\n");
5491
5492 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5493 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5494 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5495 return;
5496
5497 crtc = encoder->base.crtc;
5498
5499 I915_STATE_WARN(!crtc->state->enable,
5500 "crtc not enabled\n");
5501 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5502 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5503 "encoder active on the wrong pipe\n");
5504 }
5505 }
5506 }
5507
5508 /* Even simpler default implementation, if there's really no special case to
5509 * consider. */
5510 void intel_connector_dpms(struct drm_connector *connector, int mode)
5511 {
5512 /* All the simple cases only support two dpms states. */
5513 if (mode != DRM_MODE_DPMS_ON)
5514 mode = DRM_MODE_DPMS_OFF;
5515
5516 if (mode == connector->dpms)
5517 return;
5518
5519 connector->dpms = mode;
5520
5521 /* Only need to change hw state when actually enabled */
5522 if (connector->encoder)
5523 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5524
5525 intel_modeset_check_state(connector->dev);
5526 }
5527
5528 /* Simple connector->get_hw_state implementation for encoders that support only
5529 * one connector and no cloning and hence the encoder state determines the state
5530 * of the connector. */
5531 bool intel_connector_get_hw_state(struct intel_connector *connector)
5532 {
5533 enum pipe pipe = 0;
5534 struct intel_encoder *encoder = connector->encoder;
5535
5536 return encoder->get_hw_state(encoder, &pipe);
5537 }
5538
5539 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5540 struct intel_crtc_state *pipe_config)
5541 {
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543 struct intel_crtc *pipe_B_crtc =
5544 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5545
5546 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5547 pipe_name(pipe), pipe_config->fdi_lanes);
5548 if (pipe_config->fdi_lanes > 4) {
5549 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5550 pipe_name(pipe), pipe_config->fdi_lanes);
5551 return false;
5552 }
5553
5554 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5555 if (pipe_config->fdi_lanes > 2) {
5556 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5557 pipe_config->fdi_lanes);
5558 return false;
5559 } else {
5560 return true;
5561 }
5562 }
5563
5564 if (INTEL_INFO(dev)->num_pipes == 2)
5565 return true;
5566
5567 /* Ivybridge 3 pipe is really complicated */
5568 switch (pipe) {
5569 case PIPE_A:
5570 return true;
5571 case PIPE_B:
5572 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5573 pipe_config->fdi_lanes > 2) {
5574 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5575 pipe_name(pipe), pipe_config->fdi_lanes);
5576 return false;
5577 }
5578 return true;
5579 case PIPE_C:
5580 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5581 pipe_B_crtc->config->fdi_lanes <= 2) {
5582 if (pipe_config->fdi_lanes > 2) {
5583 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5584 pipe_name(pipe), pipe_config->fdi_lanes);
5585 return false;
5586 }
5587 } else {
5588 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5589 return false;
5590 }
5591 return true;
5592 default:
5593 BUG();
5594 }
5595 }
5596
5597 #define RETRY 1
5598 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5599 struct intel_crtc_state *pipe_config)
5600 {
5601 struct drm_device *dev = intel_crtc->base.dev;
5602 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5603 int lane, link_bw, fdi_dotclock;
5604 bool setup_ok, needs_recompute = false;
5605
5606 retry:
5607 /* FDI is a binary signal running at ~2.7GHz, encoding
5608 * each output octet as 10 bits. The actual frequency
5609 * is stored as a divider into a 100MHz clock, and the
5610 * mode pixel clock is stored in units of 1KHz.
5611 * Hence the bw of each lane in terms of the mode signal
5612 * is:
5613 */
5614 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5615
5616 fdi_dotclock = adjusted_mode->crtc_clock;
5617
5618 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5619 pipe_config->pipe_bpp);
5620
5621 pipe_config->fdi_lanes = lane;
5622
5623 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5624 link_bw, &pipe_config->fdi_m_n);
5625
5626 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5627 intel_crtc->pipe, pipe_config);
5628 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5629 pipe_config->pipe_bpp -= 2*3;
5630 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5631 pipe_config->pipe_bpp);
5632 needs_recompute = true;
5633 pipe_config->bw_constrained = true;
5634
5635 goto retry;
5636 }
5637
5638 if (needs_recompute)
5639 return RETRY;
5640
5641 return setup_ok ? 0 : -EINVAL;
5642 }
5643
5644 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5645 struct intel_crtc_state *pipe_config)
5646 {
5647 pipe_config->ips_enabled = i915.enable_ips &&
5648 hsw_crtc_supports_ips(crtc) &&
5649 pipe_config->pipe_bpp <= 24;
5650 }
5651
5652 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5653 struct intel_crtc_state *pipe_config)
5654 {
5655 struct drm_device *dev = crtc->base.dev;
5656 struct drm_i915_private *dev_priv = dev->dev_private;
5657 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5658
5659 /* FIXME should check pixel clock limits on all platforms */
5660 if (INTEL_INFO(dev)->gen < 4) {
5661 int clock_limit =
5662 dev_priv->display.get_display_clock_speed(dev);
5663
5664 /*
5665 * Enable pixel doubling when the dot clock
5666 * is > 90% of the (display) core speed.
5667 *
5668 * GDG double wide on either pipe,
5669 * otherwise pipe A only.
5670 */
5671 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5672 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5673 clock_limit *= 2;
5674 pipe_config->double_wide = true;
5675 }
5676
5677 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5678 return -EINVAL;
5679 }
5680
5681 /*
5682 * Pipe horizontal size must be even in:
5683 * - DVO ganged mode
5684 * - LVDS dual channel mode
5685 * - Double wide pipe
5686 */
5687 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5688 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5689 pipe_config->pipe_src_w &= ~1;
5690
5691 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5692 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5693 */
5694 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5695 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5696 return -EINVAL;
5697
5698 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5699 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5700 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5701 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5702 * for lvds. */
5703 pipe_config->pipe_bpp = 8*3;
5704 }
5705
5706 if (HAS_IPS(dev))
5707 hsw_compute_ips_config(crtc, pipe_config);
5708
5709 if (pipe_config->has_pch_encoder)
5710 return ironlake_fdi_compute_config(crtc, pipe_config);
5711
5712 return 0;
5713 }
5714
5715 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5716 {
5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 u32 val;
5719 int divider;
5720
5721 if (dev_priv->hpll_freq == 0)
5722 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5723
5724 mutex_lock(&dev_priv->dpio_lock);
5725 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5726 mutex_unlock(&dev_priv->dpio_lock);
5727
5728 divider = val & DISPLAY_FREQUENCY_VALUES;
5729
5730 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5731 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5732 "cdclk change in progress\n");
5733
5734 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5735 }
5736
5737 static int i945_get_display_clock_speed(struct drm_device *dev)
5738 {
5739 return 400000;
5740 }
5741
5742 static int i915_get_display_clock_speed(struct drm_device *dev)
5743 {
5744 return 333000;
5745 }
5746
5747 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5748 {
5749 return 200000;
5750 }
5751
5752 static int pnv_get_display_clock_speed(struct drm_device *dev)
5753 {
5754 u16 gcfgc = 0;
5755
5756 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5757
5758 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5759 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5760 return 267000;
5761 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5762 return 333000;
5763 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5764 return 444000;
5765 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5766 return 200000;
5767 default:
5768 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5769 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5770 return 133000;
5771 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5772 return 167000;
5773 }
5774 }
5775
5776 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5777 {
5778 u16 gcfgc = 0;
5779
5780 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5781
5782 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5783 return 133000;
5784 else {
5785 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5786 case GC_DISPLAY_CLOCK_333_MHZ:
5787 return 333000;
5788 default:
5789 case GC_DISPLAY_CLOCK_190_200_MHZ:
5790 return 190000;
5791 }
5792 }
5793 }
5794
5795 static int i865_get_display_clock_speed(struct drm_device *dev)
5796 {
5797 return 266000;
5798 }
5799
5800 static int i855_get_display_clock_speed(struct drm_device *dev)
5801 {
5802 u16 hpllcc = 0;
5803 /* Assume that the hardware is in the high speed state. This
5804 * should be the default.
5805 */
5806 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5807 case GC_CLOCK_133_200:
5808 case GC_CLOCK_100_200:
5809 return 200000;
5810 case GC_CLOCK_166_250:
5811 return 250000;
5812 case GC_CLOCK_100_133:
5813 return 133000;
5814 }
5815
5816 /* Shouldn't happen */
5817 return 0;
5818 }
5819
5820 static int i830_get_display_clock_speed(struct drm_device *dev)
5821 {
5822 return 133000;
5823 }
5824
5825 static void
5826 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5827 {
5828 while (*num > DATA_LINK_M_N_MASK ||
5829 *den > DATA_LINK_M_N_MASK) {
5830 *num >>= 1;
5831 *den >>= 1;
5832 }
5833 }
5834
5835 static void compute_m_n(unsigned int m, unsigned int n,
5836 uint32_t *ret_m, uint32_t *ret_n)
5837 {
5838 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5839 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5840 intel_reduce_m_n_ratio(ret_m, ret_n);
5841 }
5842
5843 void
5844 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5845 int pixel_clock, int link_clock,
5846 struct intel_link_m_n *m_n)
5847 {
5848 m_n->tu = 64;
5849
5850 compute_m_n(bits_per_pixel * pixel_clock,
5851 link_clock * nlanes * 8,
5852 &m_n->gmch_m, &m_n->gmch_n);
5853
5854 compute_m_n(pixel_clock, link_clock,
5855 &m_n->link_m, &m_n->link_n);
5856 }
5857
5858 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5859 {
5860 if (i915.panel_use_ssc >= 0)
5861 return i915.panel_use_ssc != 0;
5862 return dev_priv->vbt.lvds_use_ssc
5863 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5864 }
5865
5866 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5867 {
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 int refclk;
5871
5872 if (IS_VALLEYVIEW(dev)) {
5873 refclk = 100000;
5874 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5875 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5876 refclk = dev_priv->vbt.lvds_ssc_freq;
5877 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5878 } else if (!IS_GEN2(dev)) {
5879 refclk = 96000;
5880 } else {
5881 refclk = 48000;
5882 }
5883
5884 return refclk;
5885 }
5886
5887 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5888 {
5889 return (1 << dpll->n) << 16 | dpll->m2;
5890 }
5891
5892 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5893 {
5894 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5895 }
5896
5897 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5898 struct intel_crtc_state *crtc_state,
5899 intel_clock_t *reduced_clock)
5900 {
5901 struct drm_device *dev = crtc->base.dev;
5902 u32 fp, fp2 = 0;
5903
5904 if (IS_PINEVIEW(dev)) {
5905 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5906 if (reduced_clock)
5907 fp2 = pnv_dpll_compute_fp(reduced_clock);
5908 } else {
5909 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5910 if (reduced_clock)
5911 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5912 }
5913
5914 crtc_state->dpll_hw_state.fp0 = fp;
5915
5916 crtc->lowfreq_avail = false;
5917 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5918 reduced_clock && i915.powersave) {
5919 crtc_state->dpll_hw_state.fp1 = fp2;
5920 crtc->lowfreq_avail = true;
5921 } else {
5922 crtc_state->dpll_hw_state.fp1 = fp;
5923 }
5924 }
5925
5926 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5927 pipe)
5928 {
5929 u32 reg_val;
5930
5931 /*
5932 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5933 * and set it to a reasonable value instead.
5934 */
5935 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5936 reg_val &= 0xffffff00;
5937 reg_val |= 0x00000030;
5938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5939
5940 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5941 reg_val &= 0x8cffffff;
5942 reg_val = 0x8c000000;
5943 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5944
5945 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5946 reg_val &= 0xffffff00;
5947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5948
5949 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5950 reg_val &= 0x00ffffff;
5951 reg_val |= 0xb0000000;
5952 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5953 }
5954
5955 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5956 struct intel_link_m_n *m_n)
5957 {
5958 struct drm_device *dev = crtc->base.dev;
5959 struct drm_i915_private *dev_priv = dev->dev_private;
5960 int pipe = crtc->pipe;
5961
5962 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5963 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5964 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5965 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5966 }
5967
5968 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5969 struct intel_link_m_n *m_n,
5970 struct intel_link_m_n *m2_n2)
5971 {
5972 struct drm_device *dev = crtc->base.dev;
5973 struct drm_i915_private *dev_priv = dev->dev_private;
5974 int pipe = crtc->pipe;
5975 enum transcoder transcoder = crtc->config->cpu_transcoder;
5976
5977 if (INTEL_INFO(dev)->gen >= 5) {
5978 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5979 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5980 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5981 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5982 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5983 * for gen < 8) and if DRRS is supported (to make sure the
5984 * registers are not unnecessarily accessed).
5985 */
5986 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5987 crtc->config->has_drrs) {
5988 I915_WRITE(PIPE_DATA_M2(transcoder),
5989 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5990 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5991 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5992 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5993 }
5994 } else {
5995 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5996 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5997 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5998 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5999 }
6000 }
6001
6002 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6003 {
6004 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6005
6006 if (m_n == M1_N1) {
6007 dp_m_n = &crtc->config->dp_m_n;
6008 dp_m2_n2 = &crtc->config->dp_m2_n2;
6009 } else if (m_n == M2_N2) {
6010
6011 /*
6012 * M2_N2 registers are not supported. Hence m2_n2 divider value
6013 * needs to be programmed into M1_N1.
6014 */
6015 dp_m_n = &crtc->config->dp_m2_n2;
6016 } else {
6017 DRM_ERROR("Unsupported divider value\n");
6018 return;
6019 }
6020
6021 if (crtc->config->has_pch_encoder)
6022 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6023 else
6024 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6025 }
6026
6027 static void vlv_update_pll(struct intel_crtc *crtc,
6028 struct intel_crtc_state *pipe_config)
6029 {
6030 u32 dpll, dpll_md;
6031
6032 /*
6033 * Enable DPIO clock input. We should never disable the reference
6034 * clock for pipe B, since VGA hotplug / manual detection depends
6035 * on it.
6036 */
6037 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6038 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6039 /* We should never disable this, set it here for state tracking */
6040 if (crtc->pipe == PIPE_B)
6041 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6042 dpll |= DPLL_VCO_ENABLE;
6043 pipe_config->dpll_hw_state.dpll = dpll;
6044
6045 dpll_md = (pipe_config->pixel_multiplier - 1)
6046 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6047 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6048 }
6049
6050 static void vlv_prepare_pll(struct intel_crtc *crtc,
6051 const struct intel_crtc_state *pipe_config)
6052 {
6053 struct drm_device *dev = crtc->base.dev;
6054 struct drm_i915_private *dev_priv = dev->dev_private;
6055 int pipe = crtc->pipe;
6056 u32 mdiv;
6057 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6058 u32 coreclk, reg_val;
6059
6060 mutex_lock(&dev_priv->dpio_lock);
6061
6062 bestn = pipe_config->dpll.n;
6063 bestm1 = pipe_config->dpll.m1;
6064 bestm2 = pipe_config->dpll.m2;
6065 bestp1 = pipe_config->dpll.p1;
6066 bestp2 = pipe_config->dpll.p2;
6067
6068 /* See eDP HDMI DPIO driver vbios notes doc */
6069
6070 /* PLL B needs special handling */
6071 if (pipe == PIPE_B)
6072 vlv_pllb_recal_opamp(dev_priv, pipe);
6073
6074 /* Set up Tx target for periodic Rcomp update */
6075 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6076
6077 /* Disable target IRef on PLL */
6078 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6079 reg_val &= 0x00ffffff;
6080 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6081
6082 /* Disable fast lock */
6083 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6084
6085 /* Set idtafcrecal before PLL is enabled */
6086 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6087 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6088 mdiv |= ((bestn << DPIO_N_SHIFT));
6089 mdiv |= (1 << DPIO_K_SHIFT);
6090
6091 /*
6092 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6093 * but we don't support that).
6094 * Note: don't use the DAC post divider as it seems unstable.
6095 */
6096 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6097 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6098
6099 mdiv |= DPIO_ENABLE_CALIBRATION;
6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6101
6102 /* Set HBR and RBR LPF coefficients */
6103 if (pipe_config->port_clock == 162000 ||
6104 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6105 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6106 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6107 0x009f0003);
6108 else
6109 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6110 0x00d0000f);
6111
6112 if (pipe_config->has_dp_encoder) {
6113 /* Use SSC source */
6114 if (pipe == PIPE_A)
6115 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6116 0x0df40000);
6117 else
6118 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6119 0x0df70000);
6120 } else { /* HDMI or VGA */
6121 /* Use bend source */
6122 if (pipe == PIPE_A)
6123 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6124 0x0df70000);
6125 else
6126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6127 0x0df40000);
6128 }
6129
6130 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6131 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6132 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6133 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6134 coreclk |= 0x01000000;
6135 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6136
6137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6138 mutex_unlock(&dev_priv->dpio_lock);
6139 }
6140
6141 static void chv_update_pll(struct intel_crtc *crtc,
6142 struct intel_crtc_state *pipe_config)
6143 {
6144 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6145 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6146 DPLL_VCO_ENABLE;
6147 if (crtc->pipe != PIPE_A)
6148 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6149
6150 pipe_config->dpll_hw_state.dpll_md =
6151 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6152 }
6153
6154 static void chv_prepare_pll(struct intel_crtc *crtc,
6155 const struct intel_crtc_state *pipe_config)
6156 {
6157 struct drm_device *dev = crtc->base.dev;
6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 int pipe = crtc->pipe;
6160 int dpll_reg = DPLL(crtc->pipe);
6161 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6162 u32 loopfilter, intcoeff;
6163 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6164 u32 dpio_val;
6165 int refclk;
6166
6167 bestn = pipe_config->dpll.n;
6168 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6169 bestm1 = pipe_config->dpll.m1;
6170 bestm2 = pipe_config->dpll.m2 >> 22;
6171 bestp1 = pipe_config->dpll.p1;
6172 bestp2 = pipe_config->dpll.p2;
6173 dpio_val = 0;
6174
6175 /*
6176 * Enable Refclk and SSC
6177 */
6178 I915_WRITE(dpll_reg,
6179 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6180
6181 mutex_lock(&dev_priv->dpio_lock);
6182
6183 /* p1 and p2 divider */
6184 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6185 5 << DPIO_CHV_S1_DIV_SHIFT |
6186 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6187 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6188 1 << DPIO_CHV_K_DIV_SHIFT);
6189
6190 /* Feedback post-divider - m2 */
6191 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6192
6193 /* Feedback refclk divider - n and m1 */
6194 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6195 DPIO_CHV_M1_DIV_BY_2 |
6196 1 << DPIO_CHV_N_DIV_SHIFT);
6197
6198 /* M2 fraction division */
6199 if (bestm2_frac)
6200 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6201
6202 /* M2 fraction division enable */
6203 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6204 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6205 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6206 if (bestm2_frac)
6207 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6208 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6209
6210 /* Loop filter */
6211 refclk = i9xx_get_refclk(crtc, 0);
6212 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6213 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6214 if (refclk == 100000)
6215 intcoeff = 11;
6216 else if (refclk == 38400)
6217 intcoeff = 10;
6218 else
6219 intcoeff = 9;
6220 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6221 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6222
6223 /* AFC Recal */
6224 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6225 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6226 DPIO_AFC_RECAL);
6227
6228 mutex_unlock(&dev_priv->dpio_lock);
6229 }
6230
6231 /**
6232 * vlv_force_pll_on - forcibly enable just the PLL
6233 * @dev_priv: i915 private structure
6234 * @pipe: pipe PLL to enable
6235 * @dpll: PLL configuration
6236 *
6237 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6238 * in cases where we need the PLL enabled even when @pipe is not going to
6239 * be enabled.
6240 */
6241 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6242 const struct dpll *dpll)
6243 {
6244 struct intel_crtc *crtc =
6245 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6246 struct intel_crtc_state pipe_config = {
6247 .pixel_multiplier = 1,
6248 .dpll = *dpll,
6249 };
6250
6251 if (IS_CHERRYVIEW(dev)) {
6252 chv_update_pll(crtc, &pipe_config);
6253 chv_prepare_pll(crtc, &pipe_config);
6254 chv_enable_pll(crtc, &pipe_config);
6255 } else {
6256 vlv_update_pll(crtc, &pipe_config);
6257 vlv_prepare_pll(crtc, &pipe_config);
6258 vlv_enable_pll(crtc, &pipe_config);
6259 }
6260 }
6261
6262 /**
6263 * vlv_force_pll_off - forcibly disable just the PLL
6264 * @dev_priv: i915 private structure
6265 * @pipe: pipe PLL to disable
6266 *
6267 * Disable the PLL for @pipe. To be used in cases where we need
6268 * the PLL enabled even when @pipe is not going to be enabled.
6269 */
6270 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6271 {
6272 if (IS_CHERRYVIEW(dev))
6273 chv_disable_pll(to_i915(dev), pipe);
6274 else
6275 vlv_disable_pll(to_i915(dev), pipe);
6276 }
6277
6278 static void i9xx_update_pll(struct intel_crtc *crtc,
6279 struct intel_crtc_state *crtc_state,
6280 intel_clock_t *reduced_clock,
6281 int num_connectors)
6282 {
6283 struct drm_device *dev = crtc->base.dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 u32 dpll;
6286 bool is_sdvo;
6287 struct dpll *clock = &crtc_state->dpll;
6288
6289 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6290
6291 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6292 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6293
6294 dpll = DPLL_VGA_MODE_DIS;
6295
6296 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6297 dpll |= DPLLB_MODE_LVDS;
6298 else
6299 dpll |= DPLLB_MODE_DAC_SERIAL;
6300
6301 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6302 dpll |= (crtc_state->pixel_multiplier - 1)
6303 << SDVO_MULTIPLIER_SHIFT_HIRES;
6304 }
6305
6306 if (is_sdvo)
6307 dpll |= DPLL_SDVO_HIGH_SPEED;
6308
6309 if (crtc_state->has_dp_encoder)
6310 dpll |= DPLL_SDVO_HIGH_SPEED;
6311
6312 /* compute bitmask from p1 value */
6313 if (IS_PINEVIEW(dev))
6314 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6315 else {
6316 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6317 if (IS_G4X(dev) && reduced_clock)
6318 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6319 }
6320 switch (clock->p2) {
6321 case 5:
6322 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6323 break;
6324 case 7:
6325 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6326 break;
6327 case 10:
6328 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6329 break;
6330 case 14:
6331 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6332 break;
6333 }
6334 if (INTEL_INFO(dev)->gen >= 4)
6335 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6336
6337 if (crtc_state->sdvo_tv_clock)
6338 dpll |= PLL_REF_INPUT_TVCLKINBC;
6339 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6340 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6341 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6342 else
6343 dpll |= PLL_REF_INPUT_DREFCLK;
6344
6345 dpll |= DPLL_VCO_ENABLE;
6346 crtc_state->dpll_hw_state.dpll = dpll;
6347
6348 if (INTEL_INFO(dev)->gen >= 4) {
6349 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6350 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6351 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6352 }
6353 }
6354
6355 static void i8xx_update_pll(struct intel_crtc *crtc,
6356 struct intel_crtc_state *crtc_state,
6357 intel_clock_t *reduced_clock,
6358 int num_connectors)
6359 {
6360 struct drm_device *dev = crtc->base.dev;
6361 struct drm_i915_private *dev_priv = dev->dev_private;
6362 u32 dpll;
6363 struct dpll *clock = &crtc_state->dpll;
6364
6365 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6366
6367 dpll = DPLL_VGA_MODE_DIS;
6368
6369 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6370 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6371 } else {
6372 if (clock->p1 == 2)
6373 dpll |= PLL_P1_DIVIDE_BY_TWO;
6374 else
6375 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6376 if (clock->p2 == 4)
6377 dpll |= PLL_P2_DIVIDE_BY_4;
6378 }
6379
6380 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6381 dpll |= DPLL_DVO_2X_MODE;
6382
6383 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6384 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6385 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6386 else
6387 dpll |= PLL_REF_INPUT_DREFCLK;
6388
6389 dpll |= DPLL_VCO_ENABLE;
6390 crtc_state->dpll_hw_state.dpll = dpll;
6391 }
6392
6393 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6394 {
6395 struct drm_device *dev = intel_crtc->base.dev;
6396 struct drm_i915_private *dev_priv = dev->dev_private;
6397 enum pipe pipe = intel_crtc->pipe;
6398 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6399 struct drm_display_mode *adjusted_mode =
6400 &intel_crtc->config->base.adjusted_mode;
6401 uint32_t crtc_vtotal, crtc_vblank_end;
6402 int vsyncshift = 0;
6403
6404 /* We need to be careful not to changed the adjusted mode, for otherwise
6405 * the hw state checker will get angry at the mismatch. */
6406 crtc_vtotal = adjusted_mode->crtc_vtotal;
6407 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6408
6409 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6410 /* the chip adds 2 halflines automatically */
6411 crtc_vtotal -= 1;
6412 crtc_vblank_end -= 1;
6413
6414 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6415 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6416 else
6417 vsyncshift = adjusted_mode->crtc_hsync_start -
6418 adjusted_mode->crtc_htotal / 2;
6419 if (vsyncshift < 0)
6420 vsyncshift += adjusted_mode->crtc_htotal;
6421 }
6422
6423 if (INTEL_INFO(dev)->gen > 3)
6424 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6425
6426 I915_WRITE(HTOTAL(cpu_transcoder),
6427 (adjusted_mode->crtc_hdisplay - 1) |
6428 ((adjusted_mode->crtc_htotal - 1) << 16));
6429 I915_WRITE(HBLANK(cpu_transcoder),
6430 (adjusted_mode->crtc_hblank_start - 1) |
6431 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6432 I915_WRITE(HSYNC(cpu_transcoder),
6433 (adjusted_mode->crtc_hsync_start - 1) |
6434 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6435
6436 I915_WRITE(VTOTAL(cpu_transcoder),
6437 (adjusted_mode->crtc_vdisplay - 1) |
6438 ((crtc_vtotal - 1) << 16));
6439 I915_WRITE(VBLANK(cpu_transcoder),
6440 (adjusted_mode->crtc_vblank_start - 1) |
6441 ((crtc_vblank_end - 1) << 16));
6442 I915_WRITE(VSYNC(cpu_transcoder),
6443 (adjusted_mode->crtc_vsync_start - 1) |
6444 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6445
6446 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6447 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6448 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6449 * bits. */
6450 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6451 (pipe == PIPE_B || pipe == PIPE_C))
6452 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6453
6454 /* pipesrc controls the size that is scaled from, which should
6455 * always be the user's requested size.
6456 */
6457 I915_WRITE(PIPESRC(pipe),
6458 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6459 (intel_crtc->config->pipe_src_h - 1));
6460 }
6461
6462 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6463 struct intel_crtc_state *pipe_config)
6464 {
6465 struct drm_device *dev = crtc->base.dev;
6466 struct drm_i915_private *dev_priv = dev->dev_private;
6467 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6468 uint32_t tmp;
6469
6470 tmp = I915_READ(HTOTAL(cpu_transcoder));
6471 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6472 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6473 tmp = I915_READ(HBLANK(cpu_transcoder));
6474 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6475 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6476 tmp = I915_READ(HSYNC(cpu_transcoder));
6477 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6478 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6479
6480 tmp = I915_READ(VTOTAL(cpu_transcoder));
6481 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6482 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6483 tmp = I915_READ(VBLANK(cpu_transcoder));
6484 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6485 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6486 tmp = I915_READ(VSYNC(cpu_transcoder));
6487 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6488 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6489
6490 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6491 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6492 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6493 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6494 }
6495
6496 tmp = I915_READ(PIPESRC(crtc->pipe));
6497 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6498 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6499
6500 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6501 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6502 }
6503
6504 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6505 struct intel_crtc_state *pipe_config)
6506 {
6507 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6508 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6509 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6510 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6511
6512 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6513 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6514 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6515 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6516
6517 mode->flags = pipe_config->base.adjusted_mode.flags;
6518
6519 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6520 mode->flags |= pipe_config->base.adjusted_mode.flags;
6521 }
6522
6523 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6524 {
6525 struct drm_device *dev = intel_crtc->base.dev;
6526 struct drm_i915_private *dev_priv = dev->dev_private;
6527 uint32_t pipeconf;
6528
6529 pipeconf = 0;
6530
6531 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6532 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6533 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6534
6535 if (intel_crtc->config->double_wide)
6536 pipeconf |= PIPECONF_DOUBLE_WIDE;
6537
6538 /* only g4x and later have fancy bpc/dither controls */
6539 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6540 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6541 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6542 pipeconf |= PIPECONF_DITHER_EN |
6543 PIPECONF_DITHER_TYPE_SP;
6544
6545 switch (intel_crtc->config->pipe_bpp) {
6546 case 18:
6547 pipeconf |= PIPECONF_6BPC;
6548 break;
6549 case 24:
6550 pipeconf |= PIPECONF_8BPC;
6551 break;
6552 case 30:
6553 pipeconf |= PIPECONF_10BPC;
6554 break;
6555 default:
6556 /* Case prevented by intel_choose_pipe_bpp_dither. */
6557 BUG();
6558 }
6559 }
6560
6561 if (HAS_PIPE_CXSR(dev)) {
6562 if (intel_crtc->lowfreq_avail) {
6563 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6564 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6565 } else {
6566 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6567 }
6568 }
6569
6570 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6571 if (INTEL_INFO(dev)->gen < 4 ||
6572 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6573 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6574 else
6575 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6576 } else
6577 pipeconf |= PIPECONF_PROGRESSIVE;
6578
6579 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6580 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6581
6582 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6583 POSTING_READ(PIPECONF(intel_crtc->pipe));
6584 }
6585
6586 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6587 struct intel_crtc_state *crtc_state)
6588 {
6589 struct drm_device *dev = crtc->base.dev;
6590 struct drm_i915_private *dev_priv = dev->dev_private;
6591 int refclk, num_connectors = 0;
6592 intel_clock_t clock, reduced_clock;
6593 bool ok, has_reduced_clock = false;
6594 bool is_lvds = false, is_dsi = false;
6595 struct intel_encoder *encoder;
6596 const intel_limit_t *limit;
6597
6598 for_each_intel_encoder(dev, encoder) {
6599 if (encoder->new_crtc != crtc)
6600 continue;
6601
6602 switch (encoder->type) {
6603 case INTEL_OUTPUT_LVDS:
6604 is_lvds = true;
6605 break;
6606 case INTEL_OUTPUT_DSI:
6607 is_dsi = true;
6608 break;
6609 default:
6610 break;
6611 }
6612
6613 num_connectors++;
6614 }
6615
6616 if (is_dsi)
6617 return 0;
6618
6619 if (!crtc_state->clock_set) {
6620 refclk = i9xx_get_refclk(crtc, num_connectors);
6621
6622 /*
6623 * Returns a set of divisors for the desired target clock with
6624 * the given refclk, or FALSE. The returned values represent
6625 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6626 * 2) / p1 / p2.
6627 */
6628 limit = intel_limit(crtc, refclk);
6629 ok = dev_priv->display.find_dpll(limit, crtc,
6630 crtc_state->port_clock,
6631 refclk, NULL, &clock);
6632 if (!ok) {
6633 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6634 return -EINVAL;
6635 }
6636
6637 if (is_lvds && dev_priv->lvds_downclock_avail) {
6638 /*
6639 * Ensure we match the reduced clock's P to the target
6640 * clock. If the clocks don't match, we can't switch
6641 * the display clock by using the FP0/FP1. In such case
6642 * we will disable the LVDS downclock feature.
6643 */
6644 has_reduced_clock =
6645 dev_priv->display.find_dpll(limit, crtc,
6646 dev_priv->lvds_downclock,
6647 refclk, &clock,
6648 &reduced_clock);
6649 }
6650 /* Compat-code for transition, will disappear. */
6651 crtc_state->dpll.n = clock.n;
6652 crtc_state->dpll.m1 = clock.m1;
6653 crtc_state->dpll.m2 = clock.m2;
6654 crtc_state->dpll.p1 = clock.p1;
6655 crtc_state->dpll.p2 = clock.p2;
6656 }
6657
6658 if (IS_GEN2(dev)) {
6659 i8xx_update_pll(crtc, crtc_state,
6660 has_reduced_clock ? &reduced_clock : NULL,
6661 num_connectors);
6662 } else if (IS_CHERRYVIEW(dev)) {
6663 chv_update_pll(crtc, crtc_state);
6664 } else if (IS_VALLEYVIEW(dev)) {
6665 vlv_update_pll(crtc, crtc_state);
6666 } else {
6667 i9xx_update_pll(crtc, crtc_state,
6668 has_reduced_clock ? &reduced_clock : NULL,
6669 num_connectors);
6670 }
6671
6672 return 0;
6673 }
6674
6675 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6676 struct intel_crtc_state *pipe_config)
6677 {
6678 struct drm_device *dev = crtc->base.dev;
6679 struct drm_i915_private *dev_priv = dev->dev_private;
6680 uint32_t tmp;
6681
6682 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6683 return;
6684
6685 tmp = I915_READ(PFIT_CONTROL);
6686 if (!(tmp & PFIT_ENABLE))
6687 return;
6688
6689 /* Check whether the pfit is attached to our pipe. */
6690 if (INTEL_INFO(dev)->gen < 4) {
6691 if (crtc->pipe != PIPE_B)
6692 return;
6693 } else {
6694 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6695 return;
6696 }
6697
6698 pipe_config->gmch_pfit.control = tmp;
6699 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6700 if (INTEL_INFO(dev)->gen < 5)
6701 pipe_config->gmch_pfit.lvds_border_bits =
6702 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6703 }
6704
6705 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6706 struct intel_crtc_state *pipe_config)
6707 {
6708 struct drm_device *dev = crtc->base.dev;
6709 struct drm_i915_private *dev_priv = dev->dev_private;
6710 int pipe = pipe_config->cpu_transcoder;
6711 intel_clock_t clock;
6712 u32 mdiv;
6713 int refclk = 100000;
6714
6715 /* In case of MIPI DPLL will not even be used */
6716 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6717 return;
6718
6719 mutex_lock(&dev_priv->dpio_lock);
6720 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6721 mutex_unlock(&dev_priv->dpio_lock);
6722
6723 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6724 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6725 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6726 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6727 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6728
6729 vlv_clock(refclk, &clock);
6730
6731 /* clock.dot is the fast clock */
6732 pipe_config->port_clock = clock.dot / 5;
6733 }
6734
6735 static void
6736 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6737 struct intel_initial_plane_config *plane_config)
6738 {
6739 struct drm_device *dev = crtc->base.dev;
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 u32 val, base, offset;
6742 int pipe = crtc->pipe, plane = crtc->plane;
6743 int fourcc, pixel_format;
6744 int aligned_height;
6745 struct drm_framebuffer *fb;
6746 struct intel_framebuffer *intel_fb;
6747
6748 val = I915_READ(DSPCNTR(plane));
6749 if (!(val & DISPLAY_PLANE_ENABLE))
6750 return;
6751
6752 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6753 if (!intel_fb) {
6754 DRM_DEBUG_KMS("failed to alloc fb\n");
6755 return;
6756 }
6757
6758 fb = &intel_fb->base;
6759
6760 if (INTEL_INFO(dev)->gen >= 4) {
6761 if (val & DISPPLANE_TILED) {
6762 plane_config->tiling = I915_TILING_X;
6763 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6764 }
6765 }
6766
6767 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6768 fourcc = i9xx_format_to_fourcc(pixel_format);
6769 fb->pixel_format = fourcc;
6770 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6771
6772 if (INTEL_INFO(dev)->gen >= 4) {
6773 if (plane_config->tiling)
6774 offset = I915_READ(DSPTILEOFF(plane));
6775 else
6776 offset = I915_READ(DSPLINOFF(plane));
6777 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6778 } else {
6779 base = I915_READ(DSPADDR(plane));
6780 }
6781 plane_config->base = base;
6782
6783 val = I915_READ(PIPESRC(pipe));
6784 fb->width = ((val >> 16) & 0xfff) + 1;
6785 fb->height = ((val >> 0) & 0xfff) + 1;
6786
6787 val = I915_READ(DSPSTRIDE(pipe));
6788 fb->pitches[0] = val & 0xffffffc0;
6789
6790 aligned_height = intel_fb_align_height(dev, fb->height,
6791 fb->pixel_format,
6792 fb->modifier[0]);
6793
6794 plane_config->size = fb->pitches[0] * aligned_height;
6795
6796 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6797 pipe_name(pipe), plane, fb->width, fb->height,
6798 fb->bits_per_pixel, base, fb->pitches[0],
6799 plane_config->size);
6800
6801 plane_config->fb = intel_fb;
6802 }
6803
6804 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6805 struct intel_crtc_state *pipe_config)
6806 {
6807 struct drm_device *dev = crtc->base.dev;
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 int pipe = pipe_config->cpu_transcoder;
6810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6811 intel_clock_t clock;
6812 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6813 int refclk = 100000;
6814
6815 mutex_lock(&dev_priv->dpio_lock);
6816 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6817 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6818 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6819 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6820 mutex_unlock(&dev_priv->dpio_lock);
6821
6822 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6823 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6824 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6825 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6826 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6827
6828 chv_clock(refclk, &clock);
6829
6830 /* clock.dot is the fast clock */
6831 pipe_config->port_clock = clock.dot / 5;
6832 }
6833
6834 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6835 struct intel_crtc_state *pipe_config)
6836 {
6837 struct drm_device *dev = crtc->base.dev;
6838 struct drm_i915_private *dev_priv = dev->dev_private;
6839 uint32_t tmp;
6840
6841 if (!intel_display_power_is_enabled(dev_priv,
6842 POWER_DOMAIN_PIPE(crtc->pipe)))
6843 return false;
6844
6845 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6846 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6847
6848 tmp = I915_READ(PIPECONF(crtc->pipe));
6849 if (!(tmp & PIPECONF_ENABLE))
6850 return false;
6851
6852 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6853 switch (tmp & PIPECONF_BPC_MASK) {
6854 case PIPECONF_6BPC:
6855 pipe_config->pipe_bpp = 18;
6856 break;
6857 case PIPECONF_8BPC:
6858 pipe_config->pipe_bpp = 24;
6859 break;
6860 case PIPECONF_10BPC:
6861 pipe_config->pipe_bpp = 30;
6862 break;
6863 default:
6864 break;
6865 }
6866 }
6867
6868 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6869 pipe_config->limited_color_range = true;
6870
6871 if (INTEL_INFO(dev)->gen < 4)
6872 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6873
6874 intel_get_pipe_timings(crtc, pipe_config);
6875
6876 i9xx_get_pfit_config(crtc, pipe_config);
6877
6878 if (INTEL_INFO(dev)->gen >= 4) {
6879 tmp = I915_READ(DPLL_MD(crtc->pipe));
6880 pipe_config->pixel_multiplier =
6881 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6882 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6883 pipe_config->dpll_hw_state.dpll_md = tmp;
6884 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6885 tmp = I915_READ(DPLL(crtc->pipe));
6886 pipe_config->pixel_multiplier =
6887 ((tmp & SDVO_MULTIPLIER_MASK)
6888 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6889 } else {
6890 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6891 * port and will be fixed up in the encoder->get_config
6892 * function. */
6893 pipe_config->pixel_multiplier = 1;
6894 }
6895 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6896 if (!IS_VALLEYVIEW(dev)) {
6897 /*
6898 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6899 * on 830. Filter it out here so that we don't
6900 * report errors due to that.
6901 */
6902 if (IS_I830(dev))
6903 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6904
6905 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6906 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6907 } else {
6908 /* Mask out read-only status bits. */
6909 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6910 DPLL_PORTC_READY_MASK |
6911 DPLL_PORTB_READY_MASK);
6912 }
6913
6914 if (IS_CHERRYVIEW(dev))
6915 chv_crtc_clock_get(crtc, pipe_config);
6916 else if (IS_VALLEYVIEW(dev))
6917 vlv_crtc_clock_get(crtc, pipe_config);
6918 else
6919 i9xx_crtc_clock_get(crtc, pipe_config);
6920
6921 return true;
6922 }
6923
6924 static void ironlake_init_pch_refclk(struct drm_device *dev)
6925 {
6926 struct drm_i915_private *dev_priv = dev->dev_private;
6927 struct intel_encoder *encoder;
6928 u32 val, final;
6929 bool has_lvds = false;
6930 bool has_cpu_edp = false;
6931 bool has_panel = false;
6932 bool has_ck505 = false;
6933 bool can_ssc = false;
6934
6935 /* We need to take the global config into account */
6936 for_each_intel_encoder(dev, encoder) {
6937 switch (encoder->type) {
6938 case INTEL_OUTPUT_LVDS:
6939 has_panel = true;
6940 has_lvds = true;
6941 break;
6942 case INTEL_OUTPUT_EDP:
6943 has_panel = true;
6944 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6945 has_cpu_edp = true;
6946 break;
6947 default:
6948 break;
6949 }
6950 }
6951
6952 if (HAS_PCH_IBX(dev)) {
6953 has_ck505 = dev_priv->vbt.display_clock_mode;
6954 can_ssc = has_ck505;
6955 } else {
6956 has_ck505 = false;
6957 can_ssc = true;
6958 }
6959
6960 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6961 has_panel, has_lvds, has_ck505);
6962
6963 /* Ironlake: try to setup display ref clock before DPLL
6964 * enabling. This is only under driver's control after
6965 * PCH B stepping, previous chipset stepping should be
6966 * ignoring this setting.
6967 */
6968 val = I915_READ(PCH_DREF_CONTROL);
6969
6970 /* As we must carefully and slowly disable/enable each source in turn,
6971 * compute the final state we want first and check if we need to
6972 * make any changes at all.
6973 */
6974 final = val;
6975 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6976 if (has_ck505)
6977 final |= DREF_NONSPREAD_CK505_ENABLE;
6978 else
6979 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6980
6981 final &= ~DREF_SSC_SOURCE_MASK;
6982 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6983 final &= ~DREF_SSC1_ENABLE;
6984
6985 if (has_panel) {
6986 final |= DREF_SSC_SOURCE_ENABLE;
6987
6988 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6989 final |= DREF_SSC1_ENABLE;
6990
6991 if (has_cpu_edp) {
6992 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6993 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6994 else
6995 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6996 } else
6997 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6998 } else {
6999 final |= DREF_SSC_SOURCE_DISABLE;
7000 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7001 }
7002
7003 if (final == val)
7004 return;
7005
7006 /* Always enable nonspread source */
7007 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7008
7009 if (has_ck505)
7010 val |= DREF_NONSPREAD_CK505_ENABLE;
7011 else
7012 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7013
7014 if (has_panel) {
7015 val &= ~DREF_SSC_SOURCE_MASK;
7016 val |= DREF_SSC_SOURCE_ENABLE;
7017
7018 /* SSC must be turned on before enabling the CPU output */
7019 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7020 DRM_DEBUG_KMS("Using SSC on panel\n");
7021 val |= DREF_SSC1_ENABLE;
7022 } else
7023 val &= ~DREF_SSC1_ENABLE;
7024
7025 /* Get SSC going before enabling the outputs */
7026 I915_WRITE(PCH_DREF_CONTROL, val);
7027 POSTING_READ(PCH_DREF_CONTROL);
7028 udelay(200);
7029
7030 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7031
7032 /* Enable CPU source on CPU attached eDP */
7033 if (has_cpu_edp) {
7034 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7035 DRM_DEBUG_KMS("Using SSC on eDP\n");
7036 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7037 } else
7038 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7039 } else
7040 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7041
7042 I915_WRITE(PCH_DREF_CONTROL, val);
7043 POSTING_READ(PCH_DREF_CONTROL);
7044 udelay(200);
7045 } else {
7046 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7047
7048 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7049
7050 /* Turn off CPU output */
7051 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7052
7053 I915_WRITE(PCH_DREF_CONTROL, val);
7054 POSTING_READ(PCH_DREF_CONTROL);
7055 udelay(200);
7056
7057 /* Turn off the SSC source */
7058 val &= ~DREF_SSC_SOURCE_MASK;
7059 val |= DREF_SSC_SOURCE_DISABLE;
7060
7061 /* Turn off SSC1 */
7062 val &= ~DREF_SSC1_ENABLE;
7063
7064 I915_WRITE(PCH_DREF_CONTROL, val);
7065 POSTING_READ(PCH_DREF_CONTROL);
7066 udelay(200);
7067 }
7068
7069 BUG_ON(val != final);
7070 }
7071
7072 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7073 {
7074 uint32_t tmp;
7075
7076 tmp = I915_READ(SOUTH_CHICKEN2);
7077 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7078 I915_WRITE(SOUTH_CHICKEN2, tmp);
7079
7080 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7081 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7082 DRM_ERROR("FDI mPHY reset assert timeout\n");
7083
7084 tmp = I915_READ(SOUTH_CHICKEN2);
7085 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7086 I915_WRITE(SOUTH_CHICKEN2, tmp);
7087
7088 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7089 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7090 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7091 }
7092
7093 /* WaMPhyProgramming:hsw */
7094 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7095 {
7096 uint32_t tmp;
7097
7098 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7099 tmp &= ~(0xFF << 24);
7100 tmp |= (0x12 << 24);
7101 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7102
7103 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7104 tmp |= (1 << 11);
7105 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7106
7107 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7108 tmp |= (1 << 11);
7109 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7110
7111 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7112 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7113 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7114
7115 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7116 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7117 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7118
7119 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7120 tmp &= ~(7 << 13);
7121 tmp |= (5 << 13);
7122 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7123
7124 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7125 tmp &= ~(7 << 13);
7126 tmp |= (5 << 13);
7127 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7128
7129 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7130 tmp &= ~0xFF;
7131 tmp |= 0x1C;
7132 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7133
7134 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7135 tmp &= ~0xFF;
7136 tmp |= 0x1C;
7137 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7138
7139 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7140 tmp &= ~(0xFF << 16);
7141 tmp |= (0x1C << 16);
7142 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7143
7144 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7145 tmp &= ~(0xFF << 16);
7146 tmp |= (0x1C << 16);
7147 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7148
7149 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7150 tmp |= (1 << 27);
7151 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7152
7153 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7154 tmp |= (1 << 27);
7155 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7156
7157 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7158 tmp &= ~(0xF << 28);
7159 tmp |= (4 << 28);
7160 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7161
7162 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7163 tmp &= ~(0xF << 28);
7164 tmp |= (4 << 28);
7165 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7166 }
7167
7168 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7169 * Programming" based on the parameters passed:
7170 * - Sequence to enable CLKOUT_DP
7171 * - Sequence to enable CLKOUT_DP without spread
7172 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7173 */
7174 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7175 bool with_fdi)
7176 {
7177 struct drm_i915_private *dev_priv = dev->dev_private;
7178 uint32_t reg, tmp;
7179
7180 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7181 with_spread = true;
7182 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7183 with_fdi, "LP PCH doesn't have FDI\n"))
7184 with_fdi = false;
7185
7186 mutex_lock(&dev_priv->dpio_lock);
7187
7188 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7189 tmp &= ~SBI_SSCCTL_DISABLE;
7190 tmp |= SBI_SSCCTL_PATHALT;
7191 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7192
7193 udelay(24);
7194
7195 if (with_spread) {
7196 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7197 tmp &= ~SBI_SSCCTL_PATHALT;
7198 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7199
7200 if (with_fdi) {
7201 lpt_reset_fdi_mphy(dev_priv);
7202 lpt_program_fdi_mphy(dev_priv);
7203 }
7204 }
7205
7206 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7207 SBI_GEN0 : SBI_DBUFF0;
7208 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7209 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7210 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7211
7212 mutex_unlock(&dev_priv->dpio_lock);
7213 }
7214
7215 /* Sequence to disable CLKOUT_DP */
7216 static void lpt_disable_clkout_dp(struct drm_device *dev)
7217 {
7218 struct drm_i915_private *dev_priv = dev->dev_private;
7219 uint32_t reg, tmp;
7220
7221 mutex_lock(&dev_priv->dpio_lock);
7222
7223 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7224 SBI_GEN0 : SBI_DBUFF0;
7225 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7226 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7227 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7228
7229 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7230 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7231 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7232 tmp |= SBI_SSCCTL_PATHALT;
7233 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7234 udelay(32);
7235 }
7236 tmp |= SBI_SSCCTL_DISABLE;
7237 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7238 }
7239
7240 mutex_unlock(&dev_priv->dpio_lock);
7241 }
7242
7243 static void lpt_init_pch_refclk(struct drm_device *dev)
7244 {
7245 struct intel_encoder *encoder;
7246 bool has_vga = false;
7247
7248 for_each_intel_encoder(dev, encoder) {
7249 switch (encoder->type) {
7250 case INTEL_OUTPUT_ANALOG:
7251 has_vga = true;
7252 break;
7253 default:
7254 break;
7255 }
7256 }
7257
7258 if (has_vga)
7259 lpt_enable_clkout_dp(dev, true, true);
7260 else
7261 lpt_disable_clkout_dp(dev);
7262 }
7263
7264 /*
7265 * Initialize reference clocks when the driver loads
7266 */
7267 void intel_init_pch_refclk(struct drm_device *dev)
7268 {
7269 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7270 ironlake_init_pch_refclk(dev);
7271 else if (HAS_PCH_LPT(dev))
7272 lpt_init_pch_refclk(dev);
7273 }
7274
7275 static int ironlake_get_refclk(struct drm_crtc *crtc)
7276 {
7277 struct drm_device *dev = crtc->dev;
7278 struct drm_i915_private *dev_priv = dev->dev_private;
7279 struct intel_encoder *encoder;
7280 int num_connectors = 0;
7281 bool is_lvds = false;
7282
7283 for_each_intel_encoder(dev, encoder) {
7284 if (encoder->new_crtc != to_intel_crtc(crtc))
7285 continue;
7286
7287 switch (encoder->type) {
7288 case INTEL_OUTPUT_LVDS:
7289 is_lvds = true;
7290 break;
7291 default:
7292 break;
7293 }
7294 num_connectors++;
7295 }
7296
7297 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7298 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7299 dev_priv->vbt.lvds_ssc_freq);
7300 return dev_priv->vbt.lvds_ssc_freq;
7301 }
7302
7303 return 120000;
7304 }
7305
7306 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7307 {
7308 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7310 int pipe = intel_crtc->pipe;
7311 uint32_t val;
7312
7313 val = 0;
7314
7315 switch (intel_crtc->config->pipe_bpp) {
7316 case 18:
7317 val |= PIPECONF_6BPC;
7318 break;
7319 case 24:
7320 val |= PIPECONF_8BPC;
7321 break;
7322 case 30:
7323 val |= PIPECONF_10BPC;
7324 break;
7325 case 36:
7326 val |= PIPECONF_12BPC;
7327 break;
7328 default:
7329 /* Case prevented by intel_choose_pipe_bpp_dither. */
7330 BUG();
7331 }
7332
7333 if (intel_crtc->config->dither)
7334 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7335
7336 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7337 val |= PIPECONF_INTERLACED_ILK;
7338 else
7339 val |= PIPECONF_PROGRESSIVE;
7340
7341 if (intel_crtc->config->limited_color_range)
7342 val |= PIPECONF_COLOR_RANGE_SELECT;
7343
7344 I915_WRITE(PIPECONF(pipe), val);
7345 POSTING_READ(PIPECONF(pipe));
7346 }
7347
7348 /*
7349 * Set up the pipe CSC unit.
7350 *
7351 * Currently only full range RGB to limited range RGB conversion
7352 * is supported, but eventually this should handle various
7353 * RGB<->YCbCr scenarios as well.
7354 */
7355 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7356 {
7357 struct drm_device *dev = crtc->dev;
7358 struct drm_i915_private *dev_priv = dev->dev_private;
7359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7360 int pipe = intel_crtc->pipe;
7361 uint16_t coeff = 0x7800; /* 1.0 */
7362
7363 /*
7364 * TODO: Check what kind of values actually come out of the pipe
7365 * with these coeff/postoff values and adjust to get the best
7366 * accuracy. Perhaps we even need to take the bpc value into
7367 * consideration.
7368 */
7369
7370 if (intel_crtc->config->limited_color_range)
7371 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7372
7373 /*
7374 * GY/GU and RY/RU should be the other way around according
7375 * to BSpec, but reality doesn't agree. Just set them up in
7376 * a way that results in the correct picture.
7377 */
7378 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7379 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7380
7381 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7382 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7383
7384 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7385 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7386
7387 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7388 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7389 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7390
7391 if (INTEL_INFO(dev)->gen > 6) {
7392 uint16_t postoff = 0;
7393
7394 if (intel_crtc->config->limited_color_range)
7395 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7396
7397 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7398 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7399 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7400
7401 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7402 } else {
7403 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7404
7405 if (intel_crtc->config->limited_color_range)
7406 mode |= CSC_BLACK_SCREEN_OFFSET;
7407
7408 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7409 }
7410 }
7411
7412 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7413 {
7414 struct drm_device *dev = crtc->dev;
7415 struct drm_i915_private *dev_priv = dev->dev_private;
7416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7417 enum pipe pipe = intel_crtc->pipe;
7418 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7419 uint32_t val;
7420
7421 val = 0;
7422
7423 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7424 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7425
7426 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7427 val |= PIPECONF_INTERLACED_ILK;
7428 else
7429 val |= PIPECONF_PROGRESSIVE;
7430
7431 I915_WRITE(PIPECONF(cpu_transcoder), val);
7432 POSTING_READ(PIPECONF(cpu_transcoder));
7433
7434 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7435 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7436
7437 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7438 val = 0;
7439
7440 switch (intel_crtc->config->pipe_bpp) {
7441 case 18:
7442 val |= PIPEMISC_DITHER_6_BPC;
7443 break;
7444 case 24:
7445 val |= PIPEMISC_DITHER_8_BPC;
7446 break;
7447 case 30:
7448 val |= PIPEMISC_DITHER_10_BPC;
7449 break;
7450 case 36:
7451 val |= PIPEMISC_DITHER_12_BPC;
7452 break;
7453 default:
7454 /* Case prevented by pipe_config_set_bpp. */
7455 BUG();
7456 }
7457
7458 if (intel_crtc->config->dither)
7459 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7460
7461 I915_WRITE(PIPEMISC(pipe), val);
7462 }
7463 }
7464
7465 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7466 struct intel_crtc_state *crtc_state,
7467 intel_clock_t *clock,
7468 bool *has_reduced_clock,
7469 intel_clock_t *reduced_clock)
7470 {
7471 struct drm_device *dev = crtc->dev;
7472 struct drm_i915_private *dev_priv = dev->dev_private;
7473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7474 int refclk;
7475 const intel_limit_t *limit;
7476 bool ret, is_lvds = false;
7477
7478 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7479
7480 refclk = ironlake_get_refclk(crtc);
7481
7482 /*
7483 * Returns a set of divisors for the desired target clock with the given
7484 * refclk, or FALSE. The returned values represent the clock equation:
7485 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7486 */
7487 limit = intel_limit(intel_crtc, refclk);
7488 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7489 crtc_state->port_clock,
7490 refclk, NULL, clock);
7491 if (!ret)
7492 return false;
7493
7494 if (is_lvds && dev_priv->lvds_downclock_avail) {
7495 /*
7496 * Ensure we match the reduced clock's P to the target clock.
7497 * If the clocks don't match, we can't switch the display clock
7498 * by using the FP0/FP1. In such case we will disable the LVDS
7499 * downclock feature.
7500 */
7501 *has_reduced_clock =
7502 dev_priv->display.find_dpll(limit, intel_crtc,
7503 dev_priv->lvds_downclock,
7504 refclk, clock,
7505 reduced_clock);
7506 }
7507
7508 return true;
7509 }
7510
7511 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7512 {
7513 /*
7514 * Account for spread spectrum to avoid
7515 * oversubscribing the link. Max center spread
7516 * is 2.5%; use 5% for safety's sake.
7517 */
7518 u32 bps = target_clock * bpp * 21 / 20;
7519 return DIV_ROUND_UP(bps, link_bw * 8);
7520 }
7521
7522 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7523 {
7524 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7525 }
7526
7527 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7528 struct intel_crtc_state *crtc_state,
7529 u32 *fp,
7530 intel_clock_t *reduced_clock, u32 *fp2)
7531 {
7532 struct drm_crtc *crtc = &intel_crtc->base;
7533 struct drm_device *dev = crtc->dev;
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 struct intel_encoder *intel_encoder;
7536 uint32_t dpll;
7537 int factor, num_connectors = 0;
7538 bool is_lvds = false, is_sdvo = false;
7539
7540 for_each_intel_encoder(dev, intel_encoder) {
7541 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7542 continue;
7543
7544 switch (intel_encoder->type) {
7545 case INTEL_OUTPUT_LVDS:
7546 is_lvds = true;
7547 break;
7548 case INTEL_OUTPUT_SDVO:
7549 case INTEL_OUTPUT_HDMI:
7550 is_sdvo = true;
7551 break;
7552 default:
7553 break;
7554 }
7555
7556 num_connectors++;
7557 }
7558
7559 /* Enable autotuning of the PLL clock (if permissible) */
7560 factor = 21;
7561 if (is_lvds) {
7562 if ((intel_panel_use_ssc(dev_priv) &&
7563 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7564 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7565 factor = 25;
7566 } else if (crtc_state->sdvo_tv_clock)
7567 factor = 20;
7568
7569 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7570 *fp |= FP_CB_TUNE;
7571
7572 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7573 *fp2 |= FP_CB_TUNE;
7574
7575 dpll = 0;
7576
7577 if (is_lvds)
7578 dpll |= DPLLB_MODE_LVDS;
7579 else
7580 dpll |= DPLLB_MODE_DAC_SERIAL;
7581
7582 dpll |= (crtc_state->pixel_multiplier - 1)
7583 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7584
7585 if (is_sdvo)
7586 dpll |= DPLL_SDVO_HIGH_SPEED;
7587 if (crtc_state->has_dp_encoder)
7588 dpll |= DPLL_SDVO_HIGH_SPEED;
7589
7590 /* compute bitmask from p1 value */
7591 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7592 /* also FPA1 */
7593 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7594
7595 switch (crtc_state->dpll.p2) {
7596 case 5:
7597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7598 break;
7599 case 7:
7600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7601 break;
7602 case 10:
7603 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7604 break;
7605 case 14:
7606 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7607 break;
7608 }
7609
7610 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7611 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7612 else
7613 dpll |= PLL_REF_INPUT_DREFCLK;
7614
7615 return dpll | DPLL_VCO_ENABLE;
7616 }
7617
7618 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7619 struct intel_crtc_state *crtc_state)
7620 {
7621 struct drm_device *dev = crtc->base.dev;
7622 intel_clock_t clock, reduced_clock;
7623 u32 dpll = 0, fp = 0, fp2 = 0;
7624 bool ok, has_reduced_clock = false;
7625 bool is_lvds = false;
7626 struct intel_shared_dpll *pll;
7627
7628 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7629
7630 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7631 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7632
7633 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7634 &has_reduced_clock, &reduced_clock);
7635 if (!ok && !crtc_state->clock_set) {
7636 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7637 return -EINVAL;
7638 }
7639 /* Compat-code for transition, will disappear. */
7640 if (!crtc_state->clock_set) {
7641 crtc_state->dpll.n = clock.n;
7642 crtc_state->dpll.m1 = clock.m1;
7643 crtc_state->dpll.m2 = clock.m2;
7644 crtc_state->dpll.p1 = clock.p1;
7645 crtc_state->dpll.p2 = clock.p2;
7646 }
7647
7648 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7649 if (crtc_state->has_pch_encoder) {
7650 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7651 if (has_reduced_clock)
7652 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7653
7654 dpll = ironlake_compute_dpll(crtc, crtc_state,
7655 &fp, &reduced_clock,
7656 has_reduced_clock ? &fp2 : NULL);
7657
7658 crtc_state->dpll_hw_state.dpll = dpll;
7659 crtc_state->dpll_hw_state.fp0 = fp;
7660 if (has_reduced_clock)
7661 crtc_state->dpll_hw_state.fp1 = fp2;
7662 else
7663 crtc_state->dpll_hw_state.fp1 = fp;
7664
7665 pll = intel_get_shared_dpll(crtc, crtc_state);
7666 if (pll == NULL) {
7667 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7668 pipe_name(crtc->pipe));
7669 return -EINVAL;
7670 }
7671 }
7672
7673 if (is_lvds && has_reduced_clock && i915.powersave)
7674 crtc->lowfreq_avail = true;
7675 else
7676 crtc->lowfreq_avail = false;
7677
7678 return 0;
7679 }
7680
7681 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7682 struct intel_link_m_n *m_n)
7683 {
7684 struct drm_device *dev = crtc->base.dev;
7685 struct drm_i915_private *dev_priv = dev->dev_private;
7686 enum pipe pipe = crtc->pipe;
7687
7688 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7689 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7690 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7691 & ~TU_SIZE_MASK;
7692 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7693 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7694 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7695 }
7696
7697 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7698 enum transcoder transcoder,
7699 struct intel_link_m_n *m_n,
7700 struct intel_link_m_n *m2_n2)
7701 {
7702 struct drm_device *dev = crtc->base.dev;
7703 struct drm_i915_private *dev_priv = dev->dev_private;
7704 enum pipe pipe = crtc->pipe;
7705
7706 if (INTEL_INFO(dev)->gen >= 5) {
7707 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7708 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7709 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7710 & ~TU_SIZE_MASK;
7711 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7712 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7713 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7714 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7715 * gen < 8) and if DRRS is supported (to make sure the
7716 * registers are not unnecessarily read).
7717 */
7718 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7719 crtc->config->has_drrs) {
7720 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7721 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7722 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7723 & ~TU_SIZE_MASK;
7724 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7725 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7726 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7727 }
7728 } else {
7729 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7730 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7731 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7732 & ~TU_SIZE_MASK;
7733 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7734 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7735 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7736 }
7737 }
7738
7739 void intel_dp_get_m_n(struct intel_crtc *crtc,
7740 struct intel_crtc_state *pipe_config)
7741 {
7742 if (pipe_config->has_pch_encoder)
7743 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7744 else
7745 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7746 &pipe_config->dp_m_n,
7747 &pipe_config->dp_m2_n2);
7748 }
7749
7750 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7751 struct intel_crtc_state *pipe_config)
7752 {
7753 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7754 &pipe_config->fdi_m_n, NULL);
7755 }
7756
7757 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7758 struct intel_crtc_state *pipe_config)
7759 {
7760 struct drm_device *dev = crtc->base.dev;
7761 struct drm_i915_private *dev_priv = dev->dev_private;
7762 uint32_t tmp;
7763
7764 tmp = I915_READ(PS_CTL(crtc->pipe));
7765
7766 if (tmp & PS_ENABLE) {
7767 pipe_config->pch_pfit.enabled = true;
7768 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7769 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7770 }
7771 }
7772
7773 static void
7774 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7775 struct intel_initial_plane_config *plane_config)
7776 {
7777 struct drm_device *dev = crtc->base.dev;
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 u32 val, base, offset, stride_mult, tiling;
7780 int pipe = crtc->pipe;
7781 int fourcc, pixel_format;
7782 int aligned_height;
7783 struct drm_framebuffer *fb;
7784 struct intel_framebuffer *intel_fb;
7785
7786 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7787 if (!intel_fb) {
7788 DRM_DEBUG_KMS("failed to alloc fb\n");
7789 return;
7790 }
7791
7792 fb = &intel_fb->base;
7793
7794 val = I915_READ(PLANE_CTL(pipe, 0));
7795 if (!(val & PLANE_CTL_ENABLE))
7796 goto error;
7797
7798 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7799 fourcc = skl_format_to_fourcc(pixel_format,
7800 val & PLANE_CTL_ORDER_RGBX,
7801 val & PLANE_CTL_ALPHA_MASK);
7802 fb->pixel_format = fourcc;
7803 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7804
7805 tiling = val & PLANE_CTL_TILED_MASK;
7806 switch (tiling) {
7807 case PLANE_CTL_TILED_LINEAR:
7808 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7809 break;
7810 case PLANE_CTL_TILED_X:
7811 plane_config->tiling = I915_TILING_X;
7812 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7813 break;
7814 case PLANE_CTL_TILED_Y:
7815 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7816 break;
7817 case PLANE_CTL_TILED_YF:
7818 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7819 break;
7820 default:
7821 MISSING_CASE(tiling);
7822 goto error;
7823 }
7824
7825 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7826 plane_config->base = base;
7827
7828 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7829
7830 val = I915_READ(PLANE_SIZE(pipe, 0));
7831 fb->height = ((val >> 16) & 0xfff) + 1;
7832 fb->width = ((val >> 0) & 0x1fff) + 1;
7833
7834 val = I915_READ(PLANE_STRIDE(pipe, 0));
7835 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7836 fb->pixel_format);
7837 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7838
7839 aligned_height = intel_fb_align_height(dev, fb->height,
7840 fb->pixel_format,
7841 fb->modifier[0]);
7842
7843 plane_config->size = fb->pitches[0] * aligned_height;
7844
7845 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7846 pipe_name(pipe), fb->width, fb->height,
7847 fb->bits_per_pixel, base, fb->pitches[0],
7848 plane_config->size);
7849
7850 plane_config->fb = intel_fb;
7851 return;
7852
7853 error:
7854 kfree(fb);
7855 }
7856
7857 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7858 struct intel_crtc_state *pipe_config)
7859 {
7860 struct drm_device *dev = crtc->base.dev;
7861 struct drm_i915_private *dev_priv = dev->dev_private;
7862 uint32_t tmp;
7863
7864 tmp = I915_READ(PF_CTL(crtc->pipe));
7865
7866 if (tmp & PF_ENABLE) {
7867 pipe_config->pch_pfit.enabled = true;
7868 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7869 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7870
7871 /* We currently do not free assignements of panel fitters on
7872 * ivb/hsw (since we don't use the higher upscaling modes which
7873 * differentiates them) so just WARN about this case for now. */
7874 if (IS_GEN7(dev)) {
7875 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7876 PF_PIPE_SEL_IVB(crtc->pipe));
7877 }
7878 }
7879 }
7880
7881 static void
7882 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7883 struct intel_initial_plane_config *plane_config)
7884 {
7885 struct drm_device *dev = crtc->base.dev;
7886 struct drm_i915_private *dev_priv = dev->dev_private;
7887 u32 val, base, offset;
7888 int pipe = crtc->pipe;
7889 int fourcc, pixel_format;
7890 int aligned_height;
7891 struct drm_framebuffer *fb;
7892 struct intel_framebuffer *intel_fb;
7893
7894 val = I915_READ(DSPCNTR(pipe));
7895 if (!(val & DISPLAY_PLANE_ENABLE))
7896 return;
7897
7898 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7899 if (!intel_fb) {
7900 DRM_DEBUG_KMS("failed to alloc fb\n");
7901 return;
7902 }
7903
7904 fb = &intel_fb->base;
7905
7906 if (INTEL_INFO(dev)->gen >= 4) {
7907 if (val & DISPPLANE_TILED) {
7908 plane_config->tiling = I915_TILING_X;
7909 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7910 }
7911 }
7912
7913 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7914 fourcc = i9xx_format_to_fourcc(pixel_format);
7915 fb->pixel_format = fourcc;
7916 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7917
7918 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7919 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7920 offset = I915_READ(DSPOFFSET(pipe));
7921 } else {
7922 if (plane_config->tiling)
7923 offset = I915_READ(DSPTILEOFF(pipe));
7924 else
7925 offset = I915_READ(DSPLINOFF(pipe));
7926 }
7927 plane_config->base = base;
7928
7929 val = I915_READ(PIPESRC(pipe));
7930 fb->width = ((val >> 16) & 0xfff) + 1;
7931 fb->height = ((val >> 0) & 0xfff) + 1;
7932
7933 val = I915_READ(DSPSTRIDE(pipe));
7934 fb->pitches[0] = val & 0xffffffc0;
7935
7936 aligned_height = intel_fb_align_height(dev, fb->height,
7937 fb->pixel_format,
7938 fb->modifier[0]);
7939
7940 plane_config->size = fb->pitches[0] * aligned_height;
7941
7942 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7943 pipe_name(pipe), fb->width, fb->height,
7944 fb->bits_per_pixel, base, fb->pitches[0],
7945 plane_config->size);
7946
7947 plane_config->fb = intel_fb;
7948 }
7949
7950 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7951 struct intel_crtc_state *pipe_config)
7952 {
7953 struct drm_device *dev = crtc->base.dev;
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 uint32_t tmp;
7956
7957 if (!intel_display_power_is_enabled(dev_priv,
7958 POWER_DOMAIN_PIPE(crtc->pipe)))
7959 return false;
7960
7961 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7962 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7963
7964 tmp = I915_READ(PIPECONF(crtc->pipe));
7965 if (!(tmp & PIPECONF_ENABLE))
7966 return false;
7967
7968 switch (tmp & PIPECONF_BPC_MASK) {
7969 case PIPECONF_6BPC:
7970 pipe_config->pipe_bpp = 18;
7971 break;
7972 case PIPECONF_8BPC:
7973 pipe_config->pipe_bpp = 24;
7974 break;
7975 case PIPECONF_10BPC:
7976 pipe_config->pipe_bpp = 30;
7977 break;
7978 case PIPECONF_12BPC:
7979 pipe_config->pipe_bpp = 36;
7980 break;
7981 default:
7982 break;
7983 }
7984
7985 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7986 pipe_config->limited_color_range = true;
7987
7988 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7989 struct intel_shared_dpll *pll;
7990
7991 pipe_config->has_pch_encoder = true;
7992
7993 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7994 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7995 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7996
7997 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7998
7999 if (HAS_PCH_IBX(dev_priv->dev)) {
8000 pipe_config->shared_dpll =
8001 (enum intel_dpll_id) crtc->pipe;
8002 } else {
8003 tmp = I915_READ(PCH_DPLL_SEL);
8004 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8005 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8006 else
8007 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8008 }
8009
8010 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8011
8012 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8013 &pipe_config->dpll_hw_state));
8014
8015 tmp = pipe_config->dpll_hw_state.dpll;
8016 pipe_config->pixel_multiplier =
8017 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8018 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8019
8020 ironlake_pch_clock_get(crtc, pipe_config);
8021 } else {
8022 pipe_config->pixel_multiplier = 1;
8023 }
8024
8025 intel_get_pipe_timings(crtc, pipe_config);
8026
8027 ironlake_get_pfit_config(crtc, pipe_config);
8028
8029 return true;
8030 }
8031
8032 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8033 {
8034 struct drm_device *dev = dev_priv->dev;
8035 struct intel_crtc *crtc;
8036
8037 for_each_intel_crtc(dev, crtc)
8038 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8039 pipe_name(crtc->pipe));
8040
8041 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8042 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8043 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8044 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8045 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8046 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8047 "CPU PWM1 enabled\n");
8048 if (IS_HASWELL(dev))
8049 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8050 "CPU PWM2 enabled\n");
8051 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8052 "PCH PWM1 enabled\n");
8053 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8054 "Utility pin enabled\n");
8055 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8056
8057 /*
8058 * In theory we can still leave IRQs enabled, as long as only the HPD
8059 * interrupts remain enabled. We used to check for that, but since it's
8060 * gen-specific and since we only disable LCPLL after we fully disable
8061 * the interrupts, the check below should be enough.
8062 */
8063 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8064 }
8065
8066 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8067 {
8068 struct drm_device *dev = dev_priv->dev;
8069
8070 if (IS_HASWELL(dev))
8071 return I915_READ(D_COMP_HSW);
8072 else
8073 return I915_READ(D_COMP_BDW);
8074 }
8075
8076 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8077 {
8078 struct drm_device *dev = dev_priv->dev;
8079
8080 if (IS_HASWELL(dev)) {
8081 mutex_lock(&dev_priv->rps.hw_lock);
8082 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8083 val))
8084 DRM_ERROR("Failed to write to D_COMP\n");
8085 mutex_unlock(&dev_priv->rps.hw_lock);
8086 } else {
8087 I915_WRITE(D_COMP_BDW, val);
8088 POSTING_READ(D_COMP_BDW);
8089 }
8090 }
8091
8092 /*
8093 * This function implements pieces of two sequences from BSpec:
8094 * - Sequence for display software to disable LCPLL
8095 * - Sequence for display software to allow package C8+
8096 * The steps implemented here are just the steps that actually touch the LCPLL
8097 * register. Callers should take care of disabling all the display engine
8098 * functions, doing the mode unset, fixing interrupts, etc.
8099 */
8100 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8101 bool switch_to_fclk, bool allow_power_down)
8102 {
8103 uint32_t val;
8104
8105 assert_can_disable_lcpll(dev_priv);
8106
8107 val = I915_READ(LCPLL_CTL);
8108
8109 if (switch_to_fclk) {
8110 val |= LCPLL_CD_SOURCE_FCLK;
8111 I915_WRITE(LCPLL_CTL, val);
8112
8113 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8114 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8115 DRM_ERROR("Switching to FCLK failed\n");
8116
8117 val = I915_READ(LCPLL_CTL);
8118 }
8119
8120 val |= LCPLL_PLL_DISABLE;
8121 I915_WRITE(LCPLL_CTL, val);
8122 POSTING_READ(LCPLL_CTL);
8123
8124 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8125 DRM_ERROR("LCPLL still locked\n");
8126
8127 val = hsw_read_dcomp(dev_priv);
8128 val |= D_COMP_COMP_DISABLE;
8129 hsw_write_dcomp(dev_priv, val);
8130 ndelay(100);
8131
8132 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8133 1))
8134 DRM_ERROR("D_COMP RCOMP still in progress\n");
8135
8136 if (allow_power_down) {
8137 val = I915_READ(LCPLL_CTL);
8138 val |= LCPLL_POWER_DOWN_ALLOW;
8139 I915_WRITE(LCPLL_CTL, val);
8140 POSTING_READ(LCPLL_CTL);
8141 }
8142 }
8143
8144 /*
8145 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8146 * source.
8147 */
8148 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8149 {
8150 uint32_t val;
8151
8152 val = I915_READ(LCPLL_CTL);
8153
8154 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8155 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8156 return;
8157
8158 /*
8159 * Make sure we're not on PC8 state before disabling PC8, otherwise
8160 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8161 */
8162 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8163
8164 if (val & LCPLL_POWER_DOWN_ALLOW) {
8165 val &= ~LCPLL_POWER_DOWN_ALLOW;
8166 I915_WRITE(LCPLL_CTL, val);
8167 POSTING_READ(LCPLL_CTL);
8168 }
8169
8170 val = hsw_read_dcomp(dev_priv);
8171 val |= D_COMP_COMP_FORCE;
8172 val &= ~D_COMP_COMP_DISABLE;
8173 hsw_write_dcomp(dev_priv, val);
8174
8175 val = I915_READ(LCPLL_CTL);
8176 val &= ~LCPLL_PLL_DISABLE;
8177 I915_WRITE(LCPLL_CTL, val);
8178
8179 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8180 DRM_ERROR("LCPLL not locked yet\n");
8181
8182 if (val & LCPLL_CD_SOURCE_FCLK) {
8183 val = I915_READ(LCPLL_CTL);
8184 val &= ~LCPLL_CD_SOURCE_FCLK;
8185 I915_WRITE(LCPLL_CTL, val);
8186
8187 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8188 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8189 DRM_ERROR("Switching back to LCPLL failed\n");
8190 }
8191
8192 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8193 }
8194
8195 /*
8196 * Package states C8 and deeper are really deep PC states that can only be
8197 * reached when all the devices on the system allow it, so even if the graphics
8198 * device allows PC8+, it doesn't mean the system will actually get to these
8199 * states. Our driver only allows PC8+ when going into runtime PM.
8200 *
8201 * The requirements for PC8+ are that all the outputs are disabled, the power
8202 * well is disabled and most interrupts are disabled, and these are also
8203 * requirements for runtime PM. When these conditions are met, we manually do
8204 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8205 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8206 * hang the machine.
8207 *
8208 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8209 * the state of some registers, so when we come back from PC8+ we need to
8210 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8211 * need to take care of the registers kept by RC6. Notice that this happens even
8212 * if we don't put the device in PCI D3 state (which is what currently happens
8213 * because of the runtime PM support).
8214 *
8215 * For more, read "Display Sequences for Package C8" on the hardware
8216 * documentation.
8217 */
8218 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8219 {
8220 struct drm_device *dev = dev_priv->dev;
8221 uint32_t val;
8222
8223 DRM_DEBUG_KMS("Enabling package C8+\n");
8224
8225 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8226 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8227 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8228 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8229 }
8230
8231 lpt_disable_clkout_dp(dev);
8232 hsw_disable_lcpll(dev_priv, true, true);
8233 }
8234
8235 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8236 {
8237 struct drm_device *dev = dev_priv->dev;
8238 uint32_t val;
8239
8240 DRM_DEBUG_KMS("Disabling package C8+\n");
8241
8242 hsw_restore_lcpll(dev_priv);
8243 lpt_init_pch_refclk(dev);
8244
8245 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8246 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8247 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8248 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8249 }
8250
8251 intel_prepare_ddi(dev);
8252 }
8253
8254 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8255 struct intel_crtc_state *crtc_state)
8256 {
8257 if (!intel_ddi_pll_select(crtc, crtc_state))
8258 return -EINVAL;
8259
8260 crtc->lowfreq_avail = false;
8261
8262 return 0;
8263 }
8264
8265 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8266 enum port port,
8267 struct intel_crtc_state *pipe_config)
8268 {
8269 u32 temp, dpll_ctl1;
8270
8271 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8272 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8273
8274 switch (pipe_config->ddi_pll_sel) {
8275 case SKL_DPLL0:
8276 /*
8277 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8278 * of the shared DPLL framework and thus needs to be read out
8279 * separately
8280 */
8281 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8282 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8283 break;
8284 case SKL_DPLL1:
8285 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8286 break;
8287 case SKL_DPLL2:
8288 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8289 break;
8290 case SKL_DPLL3:
8291 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8292 break;
8293 }
8294 }
8295
8296 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8297 enum port port,
8298 struct intel_crtc_state *pipe_config)
8299 {
8300 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8301
8302 switch (pipe_config->ddi_pll_sel) {
8303 case PORT_CLK_SEL_WRPLL1:
8304 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8305 break;
8306 case PORT_CLK_SEL_WRPLL2:
8307 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8308 break;
8309 }
8310 }
8311
8312 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8313 struct intel_crtc_state *pipe_config)
8314 {
8315 struct drm_device *dev = crtc->base.dev;
8316 struct drm_i915_private *dev_priv = dev->dev_private;
8317 struct intel_shared_dpll *pll;
8318 enum port port;
8319 uint32_t tmp;
8320
8321 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8322
8323 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8324
8325 if (IS_SKYLAKE(dev))
8326 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8327 else
8328 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8329
8330 if (pipe_config->shared_dpll >= 0) {
8331 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8332
8333 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8334 &pipe_config->dpll_hw_state));
8335 }
8336
8337 /*
8338 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8339 * DDI E. So just check whether this pipe is wired to DDI E and whether
8340 * the PCH transcoder is on.
8341 */
8342 if (INTEL_INFO(dev)->gen < 9 &&
8343 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8344 pipe_config->has_pch_encoder = true;
8345
8346 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8347 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8348 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8349
8350 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8351 }
8352 }
8353
8354 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8355 struct intel_crtc_state *pipe_config)
8356 {
8357 struct drm_device *dev = crtc->base.dev;
8358 struct drm_i915_private *dev_priv = dev->dev_private;
8359 enum intel_display_power_domain pfit_domain;
8360 uint32_t tmp;
8361
8362 if (!intel_display_power_is_enabled(dev_priv,
8363 POWER_DOMAIN_PIPE(crtc->pipe)))
8364 return false;
8365
8366 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8367 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8368
8369 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8370 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8371 enum pipe trans_edp_pipe;
8372 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8373 default:
8374 WARN(1, "unknown pipe linked to edp transcoder\n");
8375 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8376 case TRANS_DDI_EDP_INPUT_A_ON:
8377 trans_edp_pipe = PIPE_A;
8378 break;
8379 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8380 trans_edp_pipe = PIPE_B;
8381 break;
8382 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8383 trans_edp_pipe = PIPE_C;
8384 break;
8385 }
8386
8387 if (trans_edp_pipe == crtc->pipe)
8388 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8389 }
8390
8391 if (!intel_display_power_is_enabled(dev_priv,
8392 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8393 return false;
8394
8395 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8396 if (!(tmp & PIPECONF_ENABLE))
8397 return false;
8398
8399 haswell_get_ddi_port_state(crtc, pipe_config);
8400
8401 intel_get_pipe_timings(crtc, pipe_config);
8402
8403 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8404 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8405 if (IS_SKYLAKE(dev))
8406 skylake_get_pfit_config(crtc, pipe_config);
8407 else
8408 ironlake_get_pfit_config(crtc, pipe_config);
8409 }
8410
8411 if (IS_HASWELL(dev))
8412 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8413 (I915_READ(IPS_CTL) & IPS_ENABLE);
8414
8415 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8416 pipe_config->pixel_multiplier =
8417 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8418 } else {
8419 pipe_config->pixel_multiplier = 1;
8420 }
8421
8422 return true;
8423 }
8424
8425 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8426 {
8427 struct drm_device *dev = crtc->dev;
8428 struct drm_i915_private *dev_priv = dev->dev_private;
8429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8430 uint32_t cntl = 0, size = 0;
8431
8432 if (base) {
8433 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8434 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8435 unsigned int stride = roundup_pow_of_two(width) * 4;
8436
8437 switch (stride) {
8438 default:
8439 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8440 width, stride);
8441 stride = 256;
8442 /* fallthrough */
8443 case 256:
8444 case 512:
8445 case 1024:
8446 case 2048:
8447 break;
8448 }
8449
8450 cntl |= CURSOR_ENABLE |
8451 CURSOR_GAMMA_ENABLE |
8452 CURSOR_FORMAT_ARGB |
8453 CURSOR_STRIDE(stride);
8454
8455 size = (height << 12) | width;
8456 }
8457
8458 if (intel_crtc->cursor_cntl != 0 &&
8459 (intel_crtc->cursor_base != base ||
8460 intel_crtc->cursor_size != size ||
8461 intel_crtc->cursor_cntl != cntl)) {
8462 /* On these chipsets we can only modify the base/size/stride
8463 * whilst the cursor is disabled.
8464 */
8465 I915_WRITE(_CURACNTR, 0);
8466 POSTING_READ(_CURACNTR);
8467 intel_crtc->cursor_cntl = 0;
8468 }
8469
8470 if (intel_crtc->cursor_base != base) {
8471 I915_WRITE(_CURABASE, base);
8472 intel_crtc->cursor_base = base;
8473 }
8474
8475 if (intel_crtc->cursor_size != size) {
8476 I915_WRITE(CURSIZE, size);
8477 intel_crtc->cursor_size = size;
8478 }
8479
8480 if (intel_crtc->cursor_cntl != cntl) {
8481 I915_WRITE(_CURACNTR, cntl);
8482 POSTING_READ(_CURACNTR);
8483 intel_crtc->cursor_cntl = cntl;
8484 }
8485 }
8486
8487 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8488 {
8489 struct drm_device *dev = crtc->dev;
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8492 int pipe = intel_crtc->pipe;
8493 uint32_t cntl;
8494
8495 cntl = 0;
8496 if (base) {
8497 cntl = MCURSOR_GAMMA_ENABLE;
8498 switch (intel_crtc->base.cursor->state->crtc_w) {
8499 case 64:
8500 cntl |= CURSOR_MODE_64_ARGB_AX;
8501 break;
8502 case 128:
8503 cntl |= CURSOR_MODE_128_ARGB_AX;
8504 break;
8505 case 256:
8506 cntl |= CURSOR_MODE_256_ARGB_AX;
8507 break;
8508 default:
8509 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8510 return;
8511 }
8512 cntl |= pipe << 28; /* Connect to correct pipe */
8513
8514 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8515 cntl |= CURSOR_PIPE_CSC_ENABLE;
8516 }
8517
8518 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8519 cntl |= CURSOR_ROTATE_180;
8520
8521 if (intel_crtc->cursor_cntl != cntl) {
8522 I915_WRITE(CURCNTR(pipe), cntl);
8523 POSTING_READ(CURCNTR(pipe));
8524 intel_crtc->cursor_cntl = cntl;
8525 }
8526
8527 /* and commit changes on next vblank */
8528 I915_WRITE(CURBASE(pipe), base);
8529 POSTING_READ(CURBASE(pipe));
8530
8531 intel_crtc->cursor_base = base;
8532 }
8533
8534 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8535 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8536 bool on)
8537 {
8538 struct drm_device *dev = crtc->dev;
8539 struct drm_i915_private *dev_priv = dev->dev_private;
8540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8541 int pipe = intel_crtc->pipe;
8542 int x = crtc->cursor_x;
8543 int y = crtc->cursor_y;
8544 u32 base = 0, pos = 0;
8545
8546 if (on)
8547 base = intel_crtc->cursor_addr;
8548
8549 if (x >= intel_crtc->config->pipe_src_w)
8550 base = 0;
8551
8552 if (y >= intel_crtc->config->pipe_src_h)
8553 base = 0;
8554
8555 if (x < 0) {
8556 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8557 base = 0;
8558
8559 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8560 x = -x;
8561 }
8562 pos |= x << CURSOR_X_SHIFT;
8563
8564 if (y < 0) {
8565 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8566 base = 0;
8567
8568 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8569 y = -y;
8570 }
8571 pos |= y << CURSOR_Y_SHIFT;
8572
8573 if (base == 0 && intel_crtc->cursor_base == 0)
8574 return;
8575
8576 I915_WRITE(CURPOS(pipe), pos);
8577
8578 /* ILK+ do this automagically */
8579 if (HAS_GMCH_DISPLAY(dev) &&
8580 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8581 base += (intel_crtc->base.cursor->state->crtc_h *
8582 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8583 }
8584
8585 if (IS_845G(dev) || IS_I865G(dev))
8586 i845_update_cursor(crtc, base);
8587 else
8588 i9xx_update_cursor(crtc, base);
8589 }
8590
8591 static bool cursor_size_ok(struct drm_device *dev,
8592 uint32_t width, uint32_t height)
8593 {
8594 if (width == 0 || height == 0)
8595 return false;
8596
8597 /*
8598 * 845g/865g are special in that they are only limited by
8599 * the width of their cursors, the height is arbitrary up to
8600 * the precision of the register. Everything else requires
8601 * square cursors, limited to a few power-of-two sizes.
8602 */
8603 if (IS_845G(dev) || IS_I865G(dev)) {
8604 if ((width & 63) != 0)
8605 return false;
8606
8607 if (width > (IS_845G(dev) ? 64 : 512))
8608 return false;
8609
8610 if (height > 1023)
8611 return false;
8612 } else {
8613 switch (width | height) {
8614 case 256:
8615 case 128:
8616 if (IS_GEN2(dev))
8617 return false;
8618 case 64:
8619 break;
8620 default:
8621 return false;
8622 }
8623 }
8624
8625 return true;
8626 }
8627
8628 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8629 u16 *blue, uint32_t start, uint32_t size)
8630 {
8631 int end = (start + size > 256) ? 256 : start + size, i;
8632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8633
8634 for (i = start; i < end; i++) {
8635 intel_crtc->lut_r[i] = red[i] >> 8;
8636 intel_crtc->lut_g[i] = green[i] >> 8;
8637 intel_crtc->lut_b[i] = blue[i] >> 8;
8638 }
8639
8640 intel_crtc_load_lut(crtc);
8641 }
8642
8643 /* VESA 640x480x72Hz mode to set on the pipe */
8644 static struct drm_display_mode load_detect_mode = {
8645 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8646 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8647 };
8648
8649 struct drm_framebuffer *
8650 __intel_framebuffer_create(struct drm_device *dev,
8651 struct drm_mode_fb_cmd2 *mode_cmd,
8652 struct drm_i915_gem_object *obj)
8653 {
8654 struct intel_framebuffer *intel_fb;
8655 int ret;
8656
8657 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8658 if (!intel_fb) {
8659 drm_gem_object_unreference(&obj->base);
8660 return ERR_PTR(-ENOMEM);
8661 }
8662
8663 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8664 if (ret)
8665 goto err;
8666
8667 return &intel_fb->base;
8668 err:
8669 drm_gem_object_unreference(&obj->base);
8670 kfree(intel_fb);
8671
8672 return ERR_PTR(ret);
8673 }
8674
8675 static struct drm_framebuffer *
8676 intel_framebuffer_create(struct drm_device *dev,
8677 struct drm_mode_fb_cmd2 *mode_cmd,
8678 struct drm_i915_gem_object *obj)
8679 {
8680 struct drm_framebuffer *fb;
8681 int ret;
8682
8683 ret = i915_mutex_lock_interruptible(dev);
8684 if (ret)
8685 return ERR_PTR(ret);
8686 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8687 mutex_unlock(&dev->struct_mutex);
8688
8689 return fb;
8690 }
8691
8692 static u32
8693 intel_framebuffer_pitch_for_width(int width, int bpp)
8694 {
8695 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8696 return ALIGN(pitch, 64);
8697 }
8698
8699 static u32
8700 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8701 {
8702 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8703 return PAGE_ALIGN(pitch * mode->vdisplay);
8704 }
8705
8706 static struct drm_framebuffer *
8707 intel_framebuffer_create_for_mode(struct drm_device *dev,
8708 struct drm_display_mode *mode,
8709 int depth, int bpp)
8710 {
8711 struct drm_i915_gem_object *obj;
8712 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8713
8714 obj = i915_gem_alloc_object(dev,
8715 intel_framebuffer_size_for_mode(mode, bpp));
8716 if (obj == NULL)
8717 return ERR_PTR(-ENOMEM);
8718
8719 mode_cmd.width = mode->hdisplay;
8720 mode_cmd.height = mode->vdisplay;
8721 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8722 bpp);
8723 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8724
8725 return intel_framebuffer_create(dev, &mode_cmd, obj);
8726 }
8727
8728 static struct drm_framebuffer *
8729 mode_fits_in_fbdev(struct drm_device *dev,
8730 struct drm_display_mode *mode)
8731 {
8732 #ifdef CONFIG_DRM_I915_FBDEV
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734 struct drm_i915_gem_object *obj;
8735 struct drm_framebuffer *fb;
8736
8737 if (!dev_priv->fbdev)
8738 return NULL;
8739
8740 if (!dev_priv->fbdev->fb)
8741 return NULL;
8742
8743 obj = dev_priv->fbdev->fb->obj;
8744 BUG_ON(!obj);
8745
8746 fb = &dev_priv->fbdev->fb->base;
8747 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8748 fb->bits_per_pixel))
8749 return NULL;
8750
8751 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8752 return NULL;
8753
8754 return fb;
8755 #else
8756 return NULL;
8757 #endif
8758 }
8759
8760 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8761 struct drm_display_mode *mode,
8762 struct intel_load_detect_pipe *old,
8763 struct drm_modeset_acquire_ctx *ctx)
8764 {
8765 struct intel_crtc *intel_crtc;
8766 struct intel_encoder *intel_encoder =
8767 intel_attached_encoder(connector);
8768 struct drm_crtc *possible_crtc;
8769 struct drm_encoder *encoder = &intel_encoder->base;
8770 struct drm_crtc *crtc = NULL;
8771 struct drm_device *dev = encoder->dev;
8772 struct drm_framebuffer *fb;
8773 struct drm_mode_config *config = &dev->mode_config;
8774 int ret, i = -1;
8775
8776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8777 connector->base.id, connector->name,
8778 encoder->base.id, encoder->name);
8779
8780 retry:
8781 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8782 if (ret)
8783 goto fail_unlock;
8784
8785 /*
8786 * Algorithm gets a little messy:
8787 *
8788 * - if the connector already has an assigned crtc, use it (but make
8789 * sure it's on first)
8790 *
8791 * - try to find the first unused crtc that can drive this connector,
8792 * and use that if we find one
8793 */
8794
8795 /* See if we already have a CRTC for this connector */
8796 if (encoder->crtc) {
8797 crtc = encoder->crtc;
8798
8799 ret = drm_modeset_lock(&crtc->mutex, ctx);
8800 if (ret)
8801 goto fail_unlock;
8802 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8803 if (ret)
8804 goto fail_unlock;
8805
8806 old->dpms_mode = connector->dpms;
8807 old->load_detect_temp = false;
8808
8809 /* Make sure the crtc and connector are running */
8810 if (connector->dpms != DRM_MODE_DPMS_ON)
8811 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8812
8813 return true;
8814 }
8815
8816 /* Find an unused one (if possible) */
8817 for_each_crtc(dev, possible_crtc) {
8818 i++;
8819 if (!(encoder->possible_crtcs & (1 << i)))
8820 continue;
8821 if (possible_crtc->state->enable)
8822 continue;
8823 /* This can occur when applying the pipe A quirk on resume. */
8824 if (to_intel_crtc(possible_crtc)->new_enabled)
8825 continue;
8826
8827 crtc = possible_crtc;
8828 break;
8829 }
8830
8831 /*
8832 * If we didn't find an unused CRTC, don't use any.
8833 */
8834 if (!crtc) {
8835 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8836 goto fail_unlock;
8837 }
8838
8839 ret = drm_modeset_lock(&crtc->mutex, ctx);
8840 if (ret)
8841 goto fail_unlock;
8842 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8843 if (ret)
8844 goto fail_unlock;
8845 intel_encoder->new_crtc = to_intel_crtc(crtc);
8846 to_intel_connector(connector)->new_encoder = intel_encoder;
8847
8848 intel_crtc = to_intel_crtc(crtc);
8849 intel_crtc->new_enabled = true;
8850 intel_crtc->new_config = intel_crtc->config;
8851 old->dpms_mode = connector->dpms;
8852 old->load_detect_temp = true;
8853 old->release_fb = NULL;
8854
8855 if (!mode)
8856 mode = &load_detect_mode;
8857
8858 /* We need a framebuffer large enough to accommodate all accesses
8859 * that the plane may generate whilst we perform load detection.
8860 * We can not rely on the fbcon either being present (we get called
8861 * during its initialisation to detect all boot displays, or it may
8862 * not even exist) or that it is large enough to satisfy the
8863 * requested mode.
8864 */
8865 fb = mode_fits_in_fbdev(dev, mode);
8866 if (fb == NULL) {
8867 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8868 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8869 old->release_fb = fb;
8870 } else
8871 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8872 if (IS_ERR(fb)) {
8873 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8874 goto fail;
8875 }
8876
8877 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8878 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8879 if (old->release_fb)
8880 old->release_fb->funcs->destroy(old->release_fb);
8881 goto fail;
8882 }
8883 crtc->primary->crtc = crtc;
8884
8885 /* let the connector get through one full cycle before testing */
8886 intel_wait_for_vblank(dev, intel_crtc->pipe);
8887 return true;
8888
8889 fail:
8890 intel_crtc->new_enabled = crtc->state->enable;
8891 if (intel_crtc->new_enabled)
8892 intel_crtc->new_config = intel_crtc->config;
8893 else
8894 intel_crtc->new_config = NULL;
8895 fail_unlock:
8896 if (ret == -EDEADLK) {
8897 drm_modeset_backoff(ctx);
8898 goto retry;
8899 }
8900
8901 return false;
8902 }
8903
8904 void intel_release_load_detect_pipe(struct drm_connector *connector,
8905 struct intel_load_detect_pipe *old)
8906 {
8907 struct intel_encoder *intel_encoder =
8908 intel_attached_encoder(connector);
8909 struct drm_encoder *encoder = &intel_encoder->base;
8910 struct drm_crtc *crtc = encoder->crtc;
8911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8912
8913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8914 connector->base.id, connector->name,
8915 encoder->base.id, encoder->name);
8916
8917 if (old->load_detect_temp) {
8918 to_intel_connector(connector)->new_encoder = NULL;
8919 intel_encoder->new_crtc = NULL;
8920 intel_crtc->new_enabled = false;
8921 intel_crtc->new_config = NULL;
8922 intel_set_mode(crtc, NULL, 0, 0, NULL);
8923
8924 if (old->release_fb) {
8925 drm_framebuffer_unregister_private(old->release_fb);
8926 drm_framebuffer_unreference(old->release_fb);
8927 }
8928
8929 return;
8930 }
8931
8932 /* Switch crtc and encoder back off if necessary */
8933 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8934 connector->funcs->dpms(connector, old->dpms_mode);
8935 }
8936
8937 static int i9xx_pll_refclk(struct drm_device *dev,
8938 const struct intel_crtc_state *pipe_config)
8939 {
8940 struct drm_i915_private *dev_priv = dev->dev_private;
8941 u32 dpll = pipe_config->dpll_hw_state.dpll;
8942
8943 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8944 return dev_priv->vbt.lvds_ssc_freq;
8945 else if (HAS_PCH_SPLIT(dev))
8946 return 120000;
8947 else if (!IS_GEN2(dev))
8948 return 96000;
8949 else
8950 return 48000;
8951 }
8952
8953 /* Returns the clock of the currently programmed mode of the given pipe. */
8954 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8955 struct intel_crtc_state *pipe_config)
8956 {
8957 struct drm_device *dev = crtc->base.dev;
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959 int pipe = pipe_config->cpu_transcoder;
8960 u32 dpll = pipe_config->dpll_hw_state.dpll;
8961 u32 fp;
8962 intel_clock_t clock;
8963 int refclk = i9xx_pll_refclk(dev, pipe_config);
8964
8965 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8966 fp = pipe_config->dpll_hw_state.fp0;
8967 else
8968 fp = pipe_config->dpll_hw_state.fp1;
8969
8970 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8971 if (IS_PINEVIEW(dev)) {
8972 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8973 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8974 } else {
8975 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8976 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8977 }
8978
8979 if (!IS_GEN2(dev)) {
8980 if (IS_PINEVIEW(dev))
8981 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8982 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8983 else
8984 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8985 DPLL_FPA01_P1_POST_DIV_SHIFT);
8986
8987 switch (dpll & DPLL_MODE_MASK) {
8988 case DPLLB_MODE_DAC_SERIAL:
8989 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8990 5 : 10;
8991 break;
8992 case DPLLB_MODE_LVDS:
8993 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8994 7 : 14;
8995 break;
8996 default:
8997 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8998 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8999 return;
9000 }
9001
9002 if (IS_PINEVIEW(dev))
9003 pineview_clock(refclk, &clock);
9004 else
9005 i9xx_clock(refclk, &clock);
9006 } else {
9007 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9008 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9009
9010 if (is_lvds) {
9011 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9012 DPLL_FPA01_P1_POST_DIV_SHIFT);
9013
9014 if (lvds & LVDS_CLKB_POWER_UP)
9015 clock.p2 = 7;
9016 else
9017 clock.p2 = 14;
9018 } else {
9019 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9020 clock.p1 = 2;
9021 else {
9022 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9023 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9024 }
9025 if (dpll & PLL_P2_DIVIDE_BY_4)
9026 clock.p2 = 4;
9027 else
9028 clock.p2 = 2;
9029 }
9030
9031 i9xx_clock(refclk, &clock);
9032 }
9033
9034 /*
9035 * This value includes pixel_multiplier. We will use
9036 * port_clock to compute adjusted_mode.crtc_clock in the
9037 * encoder's get_config() function.
9038 */
9039 pipe_config->port_clock = clock.dot;
9040 }
9041
9042 int intel_dotclock_calculate(int link_freq,
9043 const struct intel_link_m_n *m_n)
9044 {
9045 /*
9046 * The calculation for the data clock is:
9047 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9048 * But we want to avoid losing precison if possible, so:
9049 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9050 *
9051 * and the link clock is simpler:
9052 * link_clock = (m * link_clock) / n
9053 */
9054
9055 if (!m_n->link_n)
9056 return 0;
9057
9058 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9059 }
9060
9061 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9062 struct intel_crtc_state *pipe_config)
9063 {
9064 struct drm_device *dev = crtc->base.dev;
9065
9066 /* read out port_clock from the DPLL */
9067 i9xx_crtc_clock_get(crtc, pipe_config);
9068
9069 /*
9070 * This value does not include pixel_multiplier.
9071 * We will check that port_clock and adjusted_mode.crtc_clock
9072 * agree once we know their relationship in the encoder's
9073 * get_config() function.
9074 */
9075 pipe_config->base.adjusted_mode.crtc_clock =
9076 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9077 &pipe_config->fdi_m_n);
9078 }
9079
9080 /** Returns the currently programmed mode of the given pipe. */
9081 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9082 struct drm_crtc *crtc)
9083 {
9084 struct drm_i915_private *dev_priv = dev->dev_private;
9085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9086 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9087 struct drm_display_mode *mode;
9088 struct intel_crtc_state pipe_config;
9089 int htot = I915_READ(HTOTAL(cpu_transcoder));
9090 int hsync = I915_READ(HSYNC(cpu_transcoder));
9091 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9092 int vsync = I915_READ(VSYNC(cpu_transcoder));
9093 enum pipe pipe = intel_crtc->pipe;
9094
9095 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9096 if (!mode)
9097 return NULL;
9098
9099 /*
9100 * Construct a pipe_config sufficient for getting the clock info
9101 * back out of crtc_clock_get.
9102 *
9103 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9104 * to use a real value here instead.
9105 */
9106 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9107 pipe_config.pixel_multiplier = 1;
9108 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9109 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9110 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9111 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9112
9113 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9114 mode->hdisplay = (htot & 0xffff) + 1;
9115 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9116 mode->hsync_start = (hsync & 0xffff) + 1;
9117 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9118 mode->vdisplay = (vtot & 0xffff) + 1;
9119 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9120 mode->vsync_start = (vsync & 0xffff) + 1;
9121 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9122
9123 drm_mode_set_name(mode);
9124
9125 return mode;
9126 }
9127
9128 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9129 {
9130 struct drm_device *dev = crtc->dev;
9131 struct drm_i915_private *dev_priv = dev->dev_private;
9132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9133
9134 if (!HAS_GMCH_DISPLAY(dev))
9135 return;
9136
9137 if (!dev_priv->lvds_downclock_avail)
9138 return;
9139
9140 /*
9141 * Since this is called by a timer, we should never get here in
9142 * the manual case.
9143 */
9144 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9145 int pipe = intel_crtc->pipe;
9146 int dpll_reg = DPLL(pipe);
9147 int dpll;
9148
9149 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9150
9151 assert_panel_unlocked(dev_priv, pipe);
9152
9153 dpll = I915_READ(dpll_reg);
9154 dpll |= DISPLAY_RATE_SELECT_FPA1;
9155 I915_WRITE(dpll_reg, dpll);
9156 intel_wait_for_vblank(dev, pipe);
9157 dpll = I915_READ(dpll_reg);
9158 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9159 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9160 }
9161
9162 }
9163
9164 void intel_mark_busy(struct drm_device *dev)
9165 {
9166 struct drm_i915_private *dev_priv = dev->dev_private;
9167
9168 if (dev_priv->mm.busy)
9169 return;
9170
9171 intel_runtime_pm_get(dev_priv);
9172 i915_update_gfx_val(dev_priv);
9173 dev_priv->mm.busy = true;
9174 }
9175
9176 void intel_mark_idle(struct drm_device *dev)
9177 {
9178 struct drm_i915_private *dev_priv = dev->dev_private;
9179 struct drm_crtc *crtc;
9180
9181 if (!dev_priv->mm.busy)
9182 return;
9183
9184 dev_priv->mm.busy = false;
9185
9186 if (!i915.powersave)
9187 goto out;
9188
9189 for_each_crtc(dev, crtc) {
9190 if (!crtc->primary->fb)
9191 continue;
9192
9193 intel_decrease_pllclock(crtc);
9194 }
9195
9196 if (INTEL_INFO(dev)->gen >= 6)
9197 gen6_rps_idle(dev->dev_private);
9198
9199 out:
9200 intel_runtime_pm_put(dev_priv);
9201 }
9202
9203 static void intel_crtc_set_state(struct intel_crtc *crtc,
9204 struct intel_crtc_state *crtc_state)
9205 {
9206 kfree(crtc->config);
9207 crtc->config = crtc_state;
9208 crtc->base.state = &crtc_state->base;
9209 }
9210
9211 static void intel_crtc_destroy(struct drm_crtc *crtc)
9212 {
9213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9214 struct drm_device *dev = crtc->dev;
9215 struct intel_unpin_work *work;
9216
9217 spin_lock_irq(&dev->event_lock);
9218 work = intel_crtc->unpin_work;
9219 intel_crtc->unpin_work = NULL;
9220 spin_unlock_irq(&dev->event_lock);
9221
9222 if (work) {
9223 cancel_work_sync(&work->work);
9224 kfree(work);
9225 }
9226
9227 intel_crtc_set_state(intel_crtc, NULL);
9228 drm_crtc_cleanup(crtc);
9229
9230 kfree(intel_crtc);
9231 }
9232
9233 static void intel_unpin_work_fn(struct work_struct *__work)
9234 {
9235 struct intel_unpin_work *work =
9236 container_of(__work, struct intel_unpin_work, work);
9237 struct drm_device *dev = work->crtc->dev;
9238 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9239
9240 mutex_lock(&dev->struct_mutex);
9241 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9242 drm_gem_object_unreference(&work->pending_flip_obj->base);
9243 drm_framebuffer_unreference(work->old_fb);
9244
9245 intel_fbc_update(dev);
9246
9247 if (work->flip_queued_req)
9248 i915_gem_request_assign(&work->flip_queued_req, NULL);
9249 mutex_unlock(&dev->struct_mutex);
9250
9251 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9252
9253 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9254 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9255
9256 kfree(work);
9257 }
9258
9259 static void do_intel_finish_page_flip(struct drm_device *dev,
9260 struct drm_crtc *crtc)
9261 {
9262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9263 struct intel_unpin_work *work;
9264 unsigned long flags;
9265
9266 /* Ignore early vblank irqs */
9267 if (intel_crtc == NULL)
9268 return;
9269
9270 /*
9271 * This is called both by irq handlers and the reset code (to complete
9272 * lost pageflips) so needs the full irqsave spinlocks.
9273 */
9274 spin_lock_irqsave(&dev->event_lock, flags);
9275 work = intel_crtc->unpin_work;
9276
9277 /* Ensure we don't miss a work->pending update ... */
9278 smp_rmb();
9279
9280 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9281 spin_unlock_irqrestore(&dev->event_lock, flags);
9282 return;
9283 }
9284
9285 page_flip_completed(intel_crtc);
9286
9287 spin_unlock_irqrestore(&dev->event_lock, flags);
9288 }
9289
9290 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9291 {
9292 struct drm_i915_private *dev_priv = dev->dev_private;
9293 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9294
9295 do_intel_finish_page_flip(dev, crtc);
9296 }
9297
9298 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9299 {
9300 struct drm_i915_private *dev_priv = dev->dev_private;
9301 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9302
9303 do_intel_finish_page_flip(dev, crtc);
9304 }
9305
9306 /* Is 'a' after or equal to 'b'? */
9307 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9308 {
9309 return !((a - b) & 0x80000000);
9310 }
9311
9312 static bool page_flip_finished(struct intel_crtc *crtc)
9313 {
9314 struct drm_device *dev = crtc->base.dev;
9315 struct drm_i915_private *dev_priv = dev->dev_private;
9316
9317 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9318 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9319 return true;
9320
9321 /*
9322 * The relevant registers doen't exist on pre-ctg.
9323 * As the flip done interrupt doesn't trigger for mmio
9324 * flips on gmch platforms, a flip count check isn't
9325 * really needed there. But since ctg has the registers,
9326 * include it in the check anyway.
9327 */
9328 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9329 return true;
9330
9331 /*
9332 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9333 * used the same base address. In that case the mmio flip might
9334 * have completed, but the CS hasn't even executed the flip yet.
9335 *
9336 * A flip count check isn't enough as the CS might have updated
9337 * the base address just after start of vblank, but before we
9338 * managed to process the interrupt. This means we'd complete the
9339 * CS flip too soon.
9340 *
9341 * Combining both checks should get us a good enough result. It may
9342 * still happen that the CS flip has been executed, but has not
9343 * yet actually completed. But in case the base address is the same
9344 * anyway, we don't really care.
9345 */
9346 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9347 crtc->unpin_work->gtt_offset &&
9348 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9349 crtc->unpin_work->flip_count);
9350 }
9351
9352 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9353 {
9354 struct drm_i915_private *dev_priv = dev->dev_private;
9355 struct intel_crtc *intel_crtc =
9356 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9357 unsigned long flags;
9358
9359
9360 /*
9361 * This is called both by irq handlers and the reset code (to complete
9362 * lost pageflips) so needs the full irqsave spinlocks.
9363 *
9364 * NB: An MMIO update of the plane base pointer will also
9365 * generate a page-flip completion irq, i.e. every modeset
9366 * is also accompanied by a spurious intel_prepare_page_flip().
9367 */
9368 spin_lock_irqsave(&dev->event_lock, flags);
9369 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9370 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9371 spin_unlock_irqrestore(&dev->event_lock, flags);
9372 }
9373
9374 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9375 {
9376 /* Ensure that the work item is consistent when activating it ... */
9377 smp_wmb();
9378 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9379 /* and that it is marked active as soon as the irq could fire. */
9380 smp_wmb();
9381 }
9382
9383 static int intel_gen2_queue_flip(struct drm_device *dev,
9384 struct drm_crtc *crtc,
9385 struct drm_framebuffer *fb,
9386 struct drm_i915_gem_object *obj,
9387 struct intel_engine_cs *ring,
9388 uint32_t flags)
9389 {
9390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9391 u32 flip_mask;
9392 int ret;
9393
9394 ret = intel_ring_begin(ring, 6);
9395 if (ret)
9396 return ret;
9397
9398 /* Can't queue multiple flips, so wait for the previous
9399 * one to finish before executing the next.
9400 */
9401 if (intel_crtc->plane)
9402 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9403 else
9404 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9405 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9406 intel_ring_emit(ring, MI_NOOP);
9407 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9408 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9409 intel_ring_emit(ring, fb->pitches[0]);
9410 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9411 intel_ring_emit(ring, 0); /* aux display base address, unused */
9412
9413 intel_mark_page_flip_active(intel_crtc);
9414 __intel_ring_advance(ring);
9415 return 0;
9416 }
9417
9418 static int intel_gen3_queue_flip(struct drm_device *dev,
9419 struct drm_crtc *crtc,
9420 struct drm_framebuffer *fb,
9421 struct drm_i915_gem_object *obj,
9422 struct intel_engine_cs *ring,
9423 uint32_t flags)
9424 {
9425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9426 u32 flip_mask;
9427 int ret;
9428
9429 ret = intel_ring_begin(ring, 6);
9430 if (ret)
9431 return ret;
9432
9433 if (intel_crtc->plane)
9434 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9435 else
9436 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9437 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9438 intel_ring_emit(ring, MI_NOOP);
9439 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9440 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9441 intel_ring_emit(ring, fb->pitches[0]);
9442 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9443 intel_ring_emit(ring, MI_NOOP);
9444
9445 intel_mark_page_flip_active(intel_crtc);
9446 __intel_ring_advance(ring);
9447 return 0;
9448 }
9449
9450 static int intel_gen4_queue_flip(struct drm_device *dev,
9451 struct drm_crtc *crtc,
9452 struct drm_framebuffer *fb,
9453 struct drm_i915_gem_object *obj,
9454 struct intel_engine_cs *ring,
9455 uint32_t flags)
9456 {
9457 struct drm_i915_private *dev_priv = dev->dev_private;
9458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9459 uint32_t pf, pipesrc;
9460 int ret;
9461
9462 ret = intel_ring_begin(ring, 4);
9463 if (ret)
9464 return ret;
9465
9466 /* i965+ uses the linear or tiled offsets from the
9467 * Display Registers (which do not change across a page-flip)
9468 * so we need only reprogram the base address.
9469 */
9470 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9471 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9472 intel_ring_emit(ring, fb->pitches[0]);
9473 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9474 obj->tiling_mode);
9475
9476 /* XXX Enabling the panel-fitter across page-flip is so far
9477 * untested on non-native modes, so ignore it for now.
9478 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9479 */
9480 pf = 0;
9481 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9482 intel_ring_emit(ring, pf | pipesrc);
9483
9484 intel_mark_page_flip_active(intel_crtc);
9485 __intel_ring_advance(ring);
9486 return 0;
9487 }
9488
9489 static int intel_gen6_queue_flip(struct drm_device *dev,
9490 struct drm_crtc *crtc,
9491 struct drm_framebuffer *fb,
9492 struct drm_i915_gem_object *obj,
9493 struct intel_engine_cs *ring,
9494 uint32_t flags)
9495 {
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9498 uint32_t pf, pipesrc;
9499 int ret;
9500
9501 ret = intel_ring_begin(ring, 4);
9502 if (ret)
9503 return ret;
9504
9505 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9506 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9507 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9508 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9509
9510 /* Contrary to the suggestions in the documentation,
9511 * "Enable Panel Fitter" does not seem to be required when page
9512 * flipping with a non-native mode, and worse causes a normal
9513 * modeset to fail.
9514 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9515 */
9516 pf = 0;
9517 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9518 intel_ring_emit(ring, pf | pipesrc);
9519
9520 intel_mark_page_flip_active(intel_crtc);
9521 __intel_ring_advance(ring);
9522 return 0;
9523 }
9524
9525 static int intel_gen7_queue_flip(struct drm_device *dev,
9526 struct drm_crtc *crtc,
9527 struct drm_framebuffer *fb,
9528 struct drm_i915_gem_object *obj,
9529 struct intel_engine_cs *ring,
9530 uint32_t flags)
9531 {
9532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9533 uint32_t plane_bit = 0;
9534 int len, ret;
9535
9536 switch (intel_crtc->plane) {
9537 case PLANE_A:
9538 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9539 break;
9540 case PLANE_B:
9541 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9542 break;
9543 case PLANE_C:
9544 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9545 break;
9546 default:
9547 WARN_ONCE(1, "unknown plane in flip command\n");
9548 return -ENODEV;
9549 }
9550
9551 len = 4;
9552 if (ring->id == RCS) {
9553 len += 6;
9554 /*
9555 * On Gen 8, SRM is now taking an extra dword to accommodate
9556 * 48bits addresses, and we need a NOOP for the batch size to
9557 * stay even.
9558 */
9559 if (IS_GEN8(dev))
9560 len += 2;
9561 }
9562
9563 /*
9564 * BSpec MI_DISPLAY_FLIP for IVB:
9565 * "The full packet must be contained within the same cache line."
9566 *
9567 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9568 * cacheline, if we ever start emitting more commands before
9569 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9570 * then do the cacheline alignment, and finally emit the
9571 * MI_DISPLAY_FLIP.
9572 */
9573 ret = intel_ring_cacheline_align(ring);
9574 if (ret)
9575 return ret;
9576
9577 ret = intel_ring_begin(ring, len);
9578 if (ret)
9579 return ret;
9580
9581 /* Unmask the flip-done completion message. Note that the bspec says that
9582 * we should do this for both the BCS and RCS, and that we must not unmask
9583 * more than one flip event at any time (or ensure that one flip message
9584 * can be sent by waiting for flip-done prior to queueing new flips).
9585 * Experimentation says that BCS works despite DERRMR masking all
9586 * flip-done completion events and that unmasking all planes at once
9587 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9588 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9589 */
9590 if (ring->id == RCS) {
9591 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9592 intel_ring_emit(ring, DERRMR);
9593 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9594 DERRMR_PIPEB_PRI_FLIP_DONE |
9595 DERRMR_PIPEC_PRI_FLIP_DONE));
9596 if (IS_GEN8(dev))
9597 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9598 MI_SRM_LRM_GLOBAL_GTT);
9599 else
9600 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9601 MI_SRM_LRM_GLOBAL_GTT);
9602 intel_ring_emit(ring, DERRMR);
9603 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9604 if (IS_GEN8(dev)) {
9605 intel_ring_emit(ring, 0);
9606 intel_ring_emit(ring, MI_NOOP);
9607 }
9608 }
9609
9610 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9611 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9612 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9613 intel_ring_emit(ring, (MI_NOOP));
9614
9615 intel_mark_page_flip_active(intel_crtc);
9616 __intel_ring_advance(ring);
9617 return 0;
9618 }
9619
9620 static bool use_mmio_flip(struct intel_engine_cs *ring,
9621 struct drm_i915_gem_object *obj)
9622 {
9623 /*
9624 * This is not being used for older platforms, because
9625 * non-availability of flip done interrupt forces us to use
9626 * CS flips. Older platforms derive flip done using some clever
9627 * tricks involving the flip_pending status bits and vblank irqs.
9628 * So using MMIO flips there would disrupt this mechanism.
9629 */
9630
9631 if (ring == NULL)
9632 return true;
9633
9634 if (INTEL_INFO(ring->dev)->gen < 5)
9635 return false;
9636
9637 if (i915.use_mmio_flip < 0)
9638 return false;
9639 else if (i915.use_mmio_flip > 0)
9640 return true;
9641 else if (i915.enable_execlists)
9642 return true;
9643 else
9644 return ring != i915_gem_request_get_ring(obj->last_read_req);
9645 }
9646
9647 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9648 {
9649 struct drm_device *dev = intel_crtc->base.dev;
9650 struct drm_i915_private *dev_priv = dev->dev_private;
9651 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9652 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9653 struct drm_i915_gem_object *obj = intel_fb->obj;
9654 const enum pipe pipe = intel_crtc->pipe;
9655 u32 ctl, stride;
9656
9657 ctl = I915_READ(PLANE_CTL(pipe, 0));
9658 ctl &= ~PLANE_CTL_TILED_MASK;
9659 if (obj->tiling_mode == I915_TILING_X)
9660 ctl |= PLANE_CTL_TILED_X;
9661
9662 /*
9663 * The stride is either expressed as a multiple of 64 bytes chunks for
9664 * linear buffers or in number of tiles for tiled buffers.
9665 */
9666 stride = fb->pitches[0] >> 6;
9667 if (obj->tiling_mode == I915_TILING_X)
9668 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9669
9670 /*
9671 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9672 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9673 */
9674 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9675 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9676
9677 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9678 POSTING_READ(PLANE_SURF(pipe, 0));
9679 }
9680
9681 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9682 {
9683 struct drm_device *dev = intel_crtc->base.dev;
9684 struct drm_i915_private *dev_priv = dev->dev_private;
9685 struct intel_framebuffer *intel_fb =
9686 to_intel_framebuffer(intel_crtc->base.primary->fb);
9687 struct drm_i915_gem_object *obj = intel_fb->obj;
9688 u32 dspcntr;
9689 u32 reg;
9690
9691 reg = DSPCNTR(intel_crtc->plane);
9692 dspcntr = I915_READ(reg);
9693
9694 if (obj->tiling_mode != I915_TILING_NONE)
9695 dspcntr |= DISPPLANE_TILED;
9696 else
9697 dspcntr &= ~DISPPLANE_TILED;
9698
9699 I915_WRITE(reg, dspcntr);
9700
9701 I915_WRITE(DSPSURF(intel_crtc->plane),
9702 intel_crtc->unpin_work->gtt_offset);
9703 POSTING_READ(DSPSURF(intel_crtc->plane));
9704
9705 }
9706
9707 /*
9708 * XXX: This is the temporary way to update the plane registers until we get
9709 * around to using the usual plane update functions for MMIO flips
9710 */
9711 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9712 {
9713 struct drm_device *dev = intel_crtc->base.dev;
9714 bool atomic_update;
9715 u32 start_vbl_count;
9716
9717 intel_mark_page_flip_active(intel_crtc);
9718
9719 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9720
9721 if (INTEL_INFO(dev)->gen >= 9)
9722 skl_do_mmio_flip(intel_crtc);
9723 else
9724 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9725 ilk_do_mmio_flip(intel_crtc);
9726
9727 if (atomic_update)
9728 intel_pipe_update_end(intel_crtc, start_vbl_count);
9729 }
9730
9731 static void intel_mmio_flip_work_func(struct work_struct *work)
9732 {
9733 struct intel_crtc *crtc =
9734 container_of(work, struct intel_crtc, mmio_flip.work);
9735 struct intel_mmio_flip *mmio_flip;
9736
9737 mmio_flip = &crtc->mmio_flip;
9738 if (mmio_flip->req)
9739 WARN_ON(__i915_wait_request(mmio_flip->req,
9740 crtc->reset_counter,
9741 false, NULL, NULL) != 0);
9742
9743 intel_do_mmio_flip(crtc);
9744 if (mmio_flip->req) {
9745 mutex_lock(&crtc->base.dev->struct_mutex);
9746 i915_gem_request_assign(&mmio_flip->req, NULL);
9747 mutex_unlock(&crtc->base.dev->struct_mutex);
9748 }
9749 }
9750
9751 static int intel_queue_mmio_flip(struct drm_device *dev,
9752 struct drm_crtc *crtc,
9753 struct drm_framebuffer *fb,
9754 struct drm_i915_gem_object *obj,
9755 struct intel_engine_cs *ring,
9756 uint32_t flags)
9757 {
9758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9759
9760 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9761 obj->last_write_req);
9762
9763 schedule_work(&intel_crtc->mmio_flip.work);
9764
9765 return 0;
9766 }
9767
9768 static int intel_default_queue_flip(struct drm_device *dev,
9769 struct drm_crtc *crtc,
9770 struct drm_framebuffer *fb,
9771 struct drm_i915_gem_object *obj,
9772 struct intel_engine_cs *ring,
9773 uint32_t flags)
9774 {
9775 return -ENODEV;
9776 }
9777
9778 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9779 struct drm_crtc *crtc)
9780 {
9781 struct drm_i915_private *dev_priv = dev->dev_private;
9782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9783 struct intel_unpin_work *work = intel_crtc->unpin_work;
9784 u32 addr;
9785
9786 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9787 return true;
9788
9789 if (!work->enable_stall_check)
9790 return false;
9791
9792 if (work->flip_ready_vblank == 0) {
9793 if (work->flip_queued_req &&
9794 !i915_gem_request_completed(work->flip_queued_req, true))
9795 return false;
9796
9797 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9798 }
9799
9800 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9801 return false;
9802
9803 /* Potential stall - if we see that the flip has happened,
9804 * assume a missed interrupt. */
9805 if (INTEL_INFO(dev)->gen >= 4)
9806 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9807 else
9808 addr = I915_READ(DSPADDR(intel_crtc->plane));
9809
9810 /* There is a potential issue here with a false positive after a flip
9811 * to the same address. We could address this by checking for a
9812 * non-incrementing frame counter.
9813 */
9814 return addr == work->gtt_offset;
9815 }
9816
9817 void intel_check_page_flip(struct drm_device *dev, int pipe)
9818 {
9819 struct drm_i915_private *dev_priv = dev->dev_private;
9820 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9822
9823 WARN_ON(!in_irq());
9824
9825 if (crtc == NULL)
9826 return;
9827
9828 spin_lock(&dev->event_lock);
9829 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9830 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9831 intel_crtc->unpin_work->flip_queued_vblank,
9832 drm_vblank_count(dev, pipe));
9833 page_flip_completed(intel_crtc);
9834 }
9835 spin_unlock(&dev->event_lock);
9836 }
9837
9838 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9839 struct drm_framebuffer *fb,
9840 struct drm_pending_vblank_event *event,
9841 uint32_t page_flip_flags)
9842 {
9843 struct drm_device *dev = crtc->dev;
9844 struct drm_i915_private *dev_priv = dev->dev_private;
9845 struct drm_framebuffer *old_fb = crtc->primary->fb;
9846 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9848 struct drm_plane *primary = crtc->primary;
9849 enum pipe pipe = intel_crtc->pipe;
9850 struct intel_unpin_work *work;
9851 struct intel_engine_cs *ring;
9852 int ret;
9853
9854 /*
9855 * drm_mode_page_flip_ioctl() should already catch this, but double
9856 * check to be safe. In the future we may enable pageflipping from
9857 * a disabled primary plane.
9858 */
9859 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9860 return -EBUSY;
9861
9862 /* Can't change pixel format via MI display flips. */
9863 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9864 return -EINVAL;
9865
9866 /*
9867 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9868 * Note that pitch changes could also affect these register.
9869 */
9870 if (INTEL_INFO(dev)->gen > 3 &&
9871 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9872 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9873 return -EINVAL;
9874
9875 if (i915_terminally_wedged(&dev_priv->gpu_error))
9876 goto out_hang;
9877
9878 work = kzalloc(sizeof(*work), GFP_KERNEL);
9879 if (work == NULL)
9880 return -ENOMEM;
9881
9882 work->event = event;
9883 work->crtc = crtc;
9884 work->old_fb = old_fb;
9885 INIT_WORK(&work->work, intel_unpin_work_fn);
9886
9887 ret = drm_crtc_vblank_get(crtc);
9888 if (ret)
9889 goto free_work;
9890
9891 /* We borrow the event spin lock for protecting unpin_work */
9892 spin_lock_irq(&dev->event_lock);
9893 if (intel_crtc->unpin_work) {
9894 /* Before declaring the flip queue wedged, check if
9895 * the hardware completed the operation behind our backs.
9896 */
9897 if (__intel_pageflip_stall_check(dev, crtc)) {
9898 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9899 page_flip_completed(intel_crtc);
9900 } else {
9901 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9902 spin_unlock_irq(&dev->event_lock);
9903
9904 drm_crtc_vblank_put(crtc);
9905 kfree(work);
9906 return -EBUSY;
9907 }
9908 }
9909 intel_crtc->unpin_work = work;
9910 spin_unlock_irq(&dev->event_lock);
9911
9912 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9913 flush_workqueue(dev_priv->wq);
9914
9915 ret = i915_mutex_lock_interruptible(dev);
9916 if (ret)
9917 goto cleanup;
9918
9919 /* Reference the objects for the scheduled work. */
9920 drm_framebuffer_reference(work->old_fb);
9921 drm_gem_object_reference(&obj->base);
9922
9923 crtc->primary->fb = fb;
9924 update_state_fb(crtc->primary);
9925
9926 work->pending_flip_obj = obj;
9927
9928 atomic_inc(&intel_crtc->unpin_work_count);
9929 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9930
9931 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9932 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9933
9934 if (IS_VALLEYVIEW(dev)) {
9935 ring = &dev_priv->ring[BCS];
9936 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9937 /* vlv: DISPLAY_FLIP fails to change tiling */
9938 ring = NULL;
9939 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9940 ring = &dev_priv->ring[BCS];
9941 } else if (INTEL_INFO(dev)->gen >= 7) {
9942 ring = i915_gem_request_get_ring(obj->last_read_req);
9943 if (ring == NULL || ring->id != RCS)
9944 ring = &dev_priv->ring[BCS];
9945 } else {
9946 ring = &dev_priv->ring[RCS];
9947 }
9948
9949 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9950 if (ret)
9951 goto cleanup_pending;
9952
9953 work->gtt_offset =
9954 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9955
9956 if (use_mmio_flip(ring, obj)) {
9957 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9958 page_flip_flags);
9959 if (ret)
9960 goto cleanup_unpin;
9961
9962 i915_gem_request_assign(&work->flip_queued_req,
9963 obj->last_write_req);
9964 } else {
9965 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9966 page_flip_flags);
9967 if (ret)
9968 goto cleanup_unpin;
9969
9970 i915_gem_request_assign(&work->flip_queued_req,
9971 intel_ring_get_request(ring));
9972 }
9973
9974 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
9975 work->enable_stall_check = true;
9976
9977 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
9978 INTEL_FRONTBUFFER_PRIMARY(pipe));
9979
9980 intel_fbc_disable(dev);
9981 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9982 mutex_unlock(&dev->struct_mutex);
9983
9984 trace_i915_flip_request(intel_crtc->plane, obj);
9985
9986 return 0;
9987
9988 cleanup_unpin:
9989 intel_unpin_fb_obj(obj);
9990 cleanup_pending:
9991 atomic_dec(&intel_crtc->unpin_work_count);
9992 crtc->primary->fb = old_fb;
9993 update_state_fb(crtc->primary);
9994 drm_framebuffer_unreference(work->old_fb);
9995 drm_gem_object_unreference(&obj->base);
9996 mutex_unlock(&dev->struct_mutex);
9997
9998 cleanup:
9999 spin_lock_irq(&dev->event_lock);
10000 intel_crtc->unpin_work = NULL;
10001 spin_unlock_irq(&dev->event_lock);
10002
10003 drm_crtc_vblank_put(crtc);
10004 free_work:
10005 kfree(work);
10006
10007 if (ret == -EIO) {
10008 out_hang:
10009 ret = intel_plane_restore(primary);
10010 if (ret == 0 && event) {
10011 spin_lock_irq(&dev->event_lock);
10012 drm_send_vblank_event(dev, pipe, event);
10013 spin_unlock_irq(&dev->event_lock);
10014 }
10015 }
10016 return ret;
10017 }
10018
10019 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10020 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10021 .load_lut = intel_crtc_load_lut,
10022 .atomic_begin = intel_begin_crtc_commit,
10023 .atomic_flush = intel_finish_crtc_commit,
10024 };
10025
10026 /**
10027 * intel_modeset_update_staged_output_state
10028 *
10029 * Updates the staged output configuration state, e.g. after we've read out the
10030 * current hw state.
10031 */
10032 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10033 {
10034 struct intel_crtc *crtc;
10035 struct intel_encoder *encoder;
10036 struct intel_connector *connector;
10037
10038 for_each_intel_connector(dev, connector) {
10039 connector->new_encoder =
10040 to_intel_encoder(connector->base.encoder);
10041 }
10042
10043 for_each_intel_encoder(dev, encoder) {
10044 encoder->new_crtc =
10045 to_intel_crtc(encoder->base.crtc);
10046 }
10047
10048 for_each_intel_crtc(dev, crtc) {
10049 crtc->new_enabled = crtc->base.state->enable;
10050
10051 if (crtc->new_enabled)
10052 crtc->new_config = crtc->config;
10053 else
10054 crtc->new_config = NULL;
10055 }
10056 }
10057
10058 /**
10059 * intel_modeset_commit_output_state
10060 *
10061 * This function copies the stage display pipe configuration to the real one.
10062 */
10063 static void intel_modeset_commit_output_state(struct drm_device *dev)
10064 {
10065 struct intel_crtc *crtc;
10066 struct intel_encoder *encoder;
10067 struct intel_connector *connector;
10068
10069 for_each_intel_connector(dev, connector) {
10070 connector->base.encoder = &connector->new_encoder->base;
10071 }
10072
10073 for_each_intel_encoder(dev, encoder) {
10074 encoder->base.crtc = &encoder->new_crtc->base;
10075 }
10076
10077 for_each_intel_crtc(dev, crtc) {
10078 crtc->base.state->enable = crtc->new_enabled;
10079 crtc->base.enabled = crtc->new_enabled;
10080 }
10081 }
10082
10083 static void
10084 connected_sink_compute_bpp(struct intel_connector *connector,
10085 struct intel_crtc_state *pipe_config)
10086 {
10087 int bpp = pipe_config->pipe_bpp;
10088
10089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10090 connector->base.base.id,
10091 connector->base.name);
10092
10093 /* Don't use an invalid EDID bpc value */
10094 if (connector->base.display_info.bpc &&
10095 connector->base.display_info.bpc * 3 < bpp) {
10096 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10097 bpp, connector->base.display_info.bpc*3);
10098 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10099 }
10100
10101 /* Clamp bpp to 8 on screens without EDID 1.4 */
10102 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10103 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10104 bpp);
10105 pipe_config->pipe_bpp = 24;
10106 }
10107 }
10108
10109 static int
10110 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10111 struct drm_framebuffer *fb,
10112 struct intel_crtc_state *pipe_config)
10113 {
10114 struct drm_device *dev = crtc->base.dev;
10115 struct intel_connector *connector;
10116 int bpp;
10117
10118 switch (fb->pixel_format) {
10119 case DRM_FORMAT_C8:
10120 bpp = 8*3; /* since we go through a colormap */
10121 break;
10122 case DRM_FORMAT_XRGB1555:
10123 case DRM_FORMAT_ARGB1555:
10124 /* checked in intel_framebuffer_init already */
10125 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10126 return -EINVAL;
10127 case DRM_FORMAT_RGB565:
10128 bpp = 6*3; /* min is 18bpp */
10129 break;
10130 case DRM_FORMAT_XBGR8888:
10131 case DRM_FORMAT_ABGR8888:
10132 /* checked in intel_framebuffer_init already */
10133 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10134 return -EINVAL;
10135 case DRM_FORMAT_XRGB8888:
10136 case DRM_FORMAT_ARGB8888:
10137 bpp = 8*3;
10138 break;
10139 case DRM_FORMAT_XRGB2101010:
10140 case DRM_FORMAT_ARGB2101010:
10141 case DRM_FORMAT_XBGR2101010:
10142 case DRM_FORMAT_ABGR2101010:
10143 /* checked in intel_framebuffer_init already */
10144 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10145 return -EINVAL;
10146 bpp = 10*3;
10147 break;
10148 /* TODO: gen4+ supports 16 bpc floating point, too. */
10149 default:
10150 DRM_DEBUG_KMS("unsupported depth\n");
10151 return -EINVAL;
10152 }
10153
10154 pipe_config->pipe_bpp = bpp;
10155
10156 /* Clamp display bpp to EDID value */
10157 for_each_intel_connector(dev, connector) {
10158 if (!connector->new_encoder ||
10159 connector->new_encoder->new_crtc != crtc)
10160 continue;
10161
10162 connected_sink_compute_bpp(connector, pipe_config);
10163 }
10164
10165 return bpp;
10166 }
10167
10168 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10169 {
10170 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10171 "type: 0x%x flags: 0x%x\n",
10172 mode->crtc_clock,
10173 mode->crtc_hdisplay, mode->crtc_hsync_start,
10174 mode->crtc_hsync_end, mode->crtc_htotal,
10175 mode->crtc_vdisplay, mode->crtc_vsync_start,
10176 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10177 }
10178
10179 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10180 struct intel_crtc_state *pipe_config,
10181 const char *context)
10182 {
10183 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10184 context, pipe_name(crtc->pipe));
10185
10186 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10187 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10188 pipe_config->pipe_bpp, pipe_config->dither);
10189 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10190 pipe_config->has_pch_encoder,
10191 pipe_config->fdi_lanes,
10192 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10193 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10194 pipe_config->fdi_m_n.tu);
10195 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10196 pipe_config->has_dp_encoder,
10197 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10198 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10199 pipe_config->dp_m_n.tu);
10200
10201 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10202 pipe_config->has_dp_encoder,
10203 pipe_config->dp_m2_n2.gmch_m,
10204 pipe_config->dp_m2_n2.gmch_n,
10205 pipe_config->dp_m2_n2.link_m,
10206 pipe_config->dp_m2_n2.link_n,
10207 pipe_config->dp_m2_n2.tu);
10208
10209 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10210 pipe_config->has_audio,
10211 pipe_config->has_infoframe);
10212
10213 DRM_DEBUG_KMS("requested mode:\n");
10214 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10215 DRM_DEBUG_KMS("adjusted mode:\n");
10216 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10217 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10218 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10219 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10220 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10221 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10222 pipe_config->gmch_pfit.control,
10223 pipe_config->gmch_pfit.pgm_ratios,
10224 pipe_config->gmch_pfit.lvds_border_bits);
10225 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10226 pipe_config->pch_pfit.pos,
10227 pipe_config->pch_pfit.size,
10228 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10229 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10230 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10231 }
10232
10233 static bool encoders_cloneable(const struct intel_encoder *a,
10234 const struct intel_encoder *b)
10235 {
10236 /* masks could be asymmetric, so check both ways */
10237 return a == b || (a->cloneable & (1 << b->type) &&
10238 b->cloneable & (1 << a->type));
10239 }
10240
10241 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10242 struct intel_encoder *encoder)
10243 {
10244 struct drm_device *dev = crtc->base.dev;
10245 struct intel_encoder *source_encoder;
10246
10247 for_each_intel_encoder(dev, source_encoder) {
10248 if (source_encoder->new_crtc != crtc)
10249 continue;
10250
10251 if (!encoders_cloneable(encoder, source_encoder))
10252 return false;
10253 }
10254
10255 return true;
10256 }
10257
10258 static bool check_encoder_cloning(struct intel_crtc *crtc)
10259 {
10260 struct drm_device *dev = crtc->base.dev;
10261 struct intel_encoder *encoder;
10262
10263 for_each_intel_encoder(dev, encoder) {
10264 if (encoder->new_crtc != crtc)
10265 continue;
10266
10267 if (!check_single_encoder_cloning(crtc, encoder))
10268 return false;
10269 }
10270
10271 return true;
10272 }
10273
10274 static bool check_digital_port_conflicts(struct drm_device *dev)
10275 {
10276 struct intel_connector *connector;
10277 unsigned int used_ports = 0;
10278
10279 /*
10280 * Walk the connector list instead of the encoder
10281 * list to detect the problem on ddi platforms
10282 * where there's just one encoder per digital port.
10283 */
10284 for_each_intel_connector(dev, connector) {
10285 struct intel_encoder *encoder = connector->new_encoder;
10286
10287 if (!encoder)
10288 continue;
10289
10290 WARN_ON(!encoder->new_crtc);
10291
10292 switch (encoder->type) {
10293 unsigned int port_mask;
10294 case INTEL_OUTPUT_UNKNOWN:
10295 if (WARN_ON(!HAS_DDI(dev)))
10296 break;
10297 case INTEL_OUTPUT_DISPLAYPORT:
10298 case INTEL_OUTPUT_HDMI:
10299 case INTEL_OUTPUT_EDP:
10300 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10301
10302 /* the same port mustn't appear more than once */
10303 if (used_ports & port_mask)
10304 return false;
10305
10306 used_ports |= port_mask;
10307 default:
10308 break;
10309 }
10310 }
10311
10312 return true;
10313 }
10314
10315 static struct intel_crtc_state *
10316 intel_modeset_pipe_config(struct drm_crtc *crtc,
10317 struct drm_framebuffer *fb,
10318 struct drm_display_mode *mode)
10319 {
10320 struct drm_device *dev = crtc->dev;
10321 struct intel_encoder *encoder;
10322 struct intel_crtc_state *pipe_config;
10323 int plane_bpp, ret = -EINVAL;
10324 bool retry = true;
10325
10326 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10327 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10328 return ERR_PTR(-EINVAL);
10329 }
10330
10331 if (!check_digital_port_conflicts(dev)) {
10332 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10333 return ERR_PTR(-EINVAL);
10334 }
10335
10336 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10337 if (!pipe_config)
10338 return ERR_PTR(-ENOMEM);
10339
10340 pipe_config->base.crtc = crtc;
10341 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10342 drm_mode_copy(&pipe_config->base.mode, mode);
10343
10344 pipe_config->cpu_transcoder =
10345 (enum transcoder) to_intel_crtc(crtc)->pipe;
10346 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10347
10348 /*
10349 * Sanitize sync polarity flags based on requested ones. If neither
10350 * positive or negative polarity is requested, treat this as meaning
10351 * negative polarity.
10352 */
10353 if (!(pipe_config->base.adjusted_mode.flags &
10354 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10355 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10356
10357 if (!(pipe_config->base.adjusted_mode.flags &
10358 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10359 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10360
10361 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10362 * plane pixel format and any sink constraints into account. Returns the
10363 * source plane bpp so that dithering can be selected on mismatches
10364 * after encoders and crtc also have had their say. */
10365 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10366 fb, pipe_config);
10367 if (plane_bpp < 0)
10368 goto fail;
10369
10370 /*
10371 * Determine the real pipe dimensions. Note that stereo modes can
10372 * increase the actual pipe size due to the frame doubling and
10373 * insertion of additional space for blanks between the frame. This
10374 * is stored in the crtc timings. We use the requested mode to do this
10375 * computation to clearly distinguish it from the adjusted mode, which
10376 * can be changed by the connectors in the below retry loop.
10377 */
10378 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10379 &pipe_config->pipe_src_w,
10380 &pipe_config->pipe_src_h);
10381
10382 encoder_retry:
10383 /* Ensure the port clock defaults are reset when retrying. */
10384 pipe_config->port_clock = 0;
10385 pipe_config->pixel_multiplier = 1;
10386
10387 /* Fill in default crtc timings, allow encoders to overwrite them. */
10388 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10389 CRTC_STEREO_DOUBLE);
10390
10391 /* Pass our mode to the connectors and the CRTC to give them a chance to
10392 * adjust it according to limitations or connector properties, and also
10393 * a chance to reject the mode entirely.
10394 */
10395 for_each_intel_encoder(dev, encoder) {
10396
10397 if (&encoder->new_crtc->base != crtc)
10398 continue;
10399
10400 if (!(encoder->compute_config(encoder, pipe_config))) {
10401 DRM_DEBUG_KMS("Encoder config failure\n");
10402 goto fail;
10403 }
10404 }
10405
10406 /* Set default port clock if not overwritten by the encoder. Needs to be
10407 * done afterwards in case the encoder adjusts the mode. */
10408 if (!pipe_config->port_clock)
10409 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10410 * pipe_config->pixel_multiplier;
10411
10412 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10413 if (ret < 0) {
10414 DRM_DEBUG_KMS("CRTC fixup failed\n");
10415 goto fail;
10416 }
10417
10418 if (ret == RETRY) {
10419 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10420 ret = -EINVAL;
10421 goto fail;
10422 }
10423
10424 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10425 retry = false;
10426 goto encoder_retry;
10427 }
10428
10429 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10430 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10431 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10432
10433 return pipe_config;
10434 fail:
10435 kfree(pipe_config);
10436 return ERR_PTR(ret);
10437 }
10438
10439 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10440 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10441 static void
10442 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10443 unsigned *prepare_pipes, unsigned *disable_pipes)
10444 {
10445 struct intel_crtc *intel_crtc;
10446 struct drm_device *dev = crtc->dev;
10447 struct intel_encoder *encoder;
10448 struct intel_connector *connector;
10449 struct drm_crtc *tmp_crtc;
10450
10451 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10452
10453 /* Check which crtcs have changed outputs connected to them, these need
10454 * to be part of the prepare_pipes mask. We don't (yet) support global
10455 * modeset across multiple crtcs, so modeset_pipes will only have one
10456 * bit set at most. */
10457 for_each_intel_connector(dev, connector) {
10458 if (connector->base.encoder == &connector->new_encoder->base)
10459 continue;
10460
10461 if (connector->base.encoder) {
10462 tmp_crtc = connector->base.encoder->crtc;
10463
10464 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10465 }
10466
10467 if (connector->new_encoder)
10468 *prepare_pipes |=
10469 1 << connector->new_encoder->new_crtc->pipe;
10470 }
10471
10472 for_each_intel_encoder(dev, encoder) {
10473 if (encoder->base.crtc == &encoder->new_crtc->base)
10474 continue;
10475
10476 if (encoder->base.crtc) {
10477 tmp_crtc = encoder->base.crtc;
10478
10479 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10480 }
10481
10482 if (encoder->new_crtc)
10483 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10484 }
10485
10486 /* Check for pipes that will be enabled/disabled ... */
10487 for_each_intel_crtc(dev, intel_crtc) {
10488 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10489 continue;
10490
10491 if (!intel_crtc->new_enabled)
10492 *disable_pipes |= 1 << intel_crtc->pipe;
10493 else
10494 *prepare_pipes |= 1 << intel_crtc->pipe;
10495 }
10496
10497
10498 /* set_mode is also used to update properties on life display pipes. */
10499 intel_crtc = to_intel_crtc(crtc);
10500 if (intel_crtc->new_enabled)
10501 *prepare_pipes |= 1 << intel_crtc->pipe;
10502
10503 /*
10504 * For simplicity do a full modeset on any pipe where the output routing
10505 * changed. We could be more clever, but that would require us to be
10506 * more careful with calling the relevant encoder->mode_set functions.
10507 */
10508 if (*prepare_pipes)
10509 *modeset_pipes = *prepare_pipes;
10510
10511 /* ... and mask these out. */
10512 *modeset_pipes &= ~(*disable_pipes);
10513 *prepare_pipes &= ~(*disable_pipes);
10514
10515 /*
10516 * HACK: We don't (yet) fully support global modesets. intel_set_config
10517 * obies this rule, but the modeset restore mode of
10518 * intel_modeset_setup_hw_state does not.
10519 */
10520 *modeset_pipes &= 1 << intel_crtc->pipe;
10521 *prepare_pipes &= 1 << intel_crtc->pipe;
10522
10523 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10524 *modeset_pipes, *prepare_pipes, *disable_pipes);
10525 }
10526
10527 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10528 {
10529 struct drm_encoder *encoder;
10530 struct drm_device *dev = crtc->dev;
10531
10532 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10533 if (encoder->crtc == crtc)
10534 return true;
10535
10536 return false;
10537 }
10538
10539 static void
10540 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10541 {
10542 struct drm_i915_private *dev_priv = dev->dev_private;
10543 struct intel_encoder *intel_encoder;
10544 struct intel_crtc *intel_crtc;
10545 struct drm_connector *connector;
10546
10547 intel_shared_dpll_commit(dev_priv);
10548
10549 for_each_intel_encoder(dev, intel_encoder) {
10550 if (!intel_encoder->base.crtc)
10551 continue;
10552
10553 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10554
10555 if (prepare_pipes & (1 << intel_crtc->pipe))
10556 intel_encoder->connectors_active = false;
10557 }
10558
10559 intel_modeset_commit_output_state(dev);
10560
10561 /* Double check state. */
10562 for_each_intel_crtc(dev, intel_crtc) {
10563 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10564 WARN_ON(intel_crtc->new_config &&
10565 intel_crtc->new_config != intel_crtc->config);
10566 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10567 }
10568
10569 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10570 if (!connector->encoder || !connector->encoder->crtc)
10571 continue;
10572
10573 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10574
10575 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10576 struct drm_property *dpms_property =
10577 dev->mode_config.dpms_property;
10578
10579 connector->dpms = DRM_MODE_DPMS_ON;
10580 drm_object_property_set_value(&connector->base,
10581 dpms_property,
10582 DRM_MODE_DPMS_ON);
10583
10584 intel_encoder = to_intel_encoder(connector->encoder);
10585 intel_encoder->connectors_active = true;
10586 }
10587 }
10588
10589 }
10590
10591 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10592 {
10593 int diff;
10594
10595 if (clock1 == clock2)
10596 return true;
10597
10598 if (!clock1 || !clock2)
10599 return false;
10600
10601 diff = abs(clock1 - clock2);
10602
10603 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10604 return true;
10605
10606 return false;
10607 }
10608
10609 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10610 list_for_each_entry((intel_crtc), \
10611 &(dev)->mode_config.crtc_list, \
10612 base.head) \
10613 if (mask & (1 <<(intel_crtc)->pipe))
10614
10615 static bool
10616 intel_pipe_config_compare(struct drm_device *dev,
10617 struct intel_crtc_state *current_config,
10618 struct intel_crtc_state *pipe_config)
10619 {
10620 #define PIPE_CONF_CHECK_X(name) \
10621 if (current_config->name != pipe_config->name) { \
10622 DRM_ERROR("mismatch in " #name " " \
10623 "(expected 0x%08x, found 0x%08x)\n", \
10624 current_config->name, \
10625 pipe_config->name); \
10626 return false; \
10627 }
10628
10629 #define PIPE_CONF_CHECK_I(name) \
10630 if (current_config->name != pipe_config->name) { \
10631 DRM_ERROR("mismatch in " #name " " \
10632 "(expected %i, found %i)\n", \
10633 current_config->name, \
10634 pipe_config->name); \
10635 return false; \
10636 }
10637
10638 /* This is required for BDW+ where there is only one set of registers for
10639 * switching between high and low RR.
10640 * This macro can be used whenever a comparison has to be made between one
10641 * hw state and multiple sw state variables.
10642 */
10643 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10644 if ((current_config->name != pipe_config->name) && \
10645 (current_config->alt_name != pipe_config->name)) { \
10646 DRM_ERROR("mismatch in " #name " " \
10647 "(expected %i or %i, found %i)\n", \
10648 current_config->name, \
10649 current_config->alt_name, \
10650 pipe_config->name); \
10651 return false; \
10652 }
10653
10654 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10655 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10656 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10657 "(expected %i, found %i)\n", \
10658 current_config->name & (mask), \
10659 pipe_config->name & (mask)); \
10660 return false; \
10661 }
10662
10663 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10664 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10665 DRM_ERROR("mismatch in " #name " " \
10666 "(expected %i, found %i)\n", \
10667 current_config->name, \
10668 pipe_config->name); \
10669 return false; \
10670 }
10671
10672 #define PIPE_CONF_QUIRK(quirk) \
10673 ((current_config->quirks | pipe_config->quirks) & (quirk))
10674
10675 PIPE_CONF_CHECK_I(cpu_transcoder);
10676
10677 PIPE_CONF_CHECK_I(has_pch_encoder);
10678 PIPE_CONF_CHECK_I(fdi_lanes);
10679 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10680 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10681 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10682 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10683 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10684
10685 PIPE_CONF_CHECK_I(has_dp_encoder);
10686
10687 if (INTEL_INFO(dev)->gen < 8) {
10688 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10689 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10690 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10691 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10692 PIPE_CONF_CHECK_I(dp_m_n.tu);
10693
10694 if (current_config->has_drrs) {
10695 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10696 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10697 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10698 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10699 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10700 }
10701 } else {
10702 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10703 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10704 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10705 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10706 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10707 }
10708
10709 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10710 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10711 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10712 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10713 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10714 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10715
10716 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10717 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10718 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10719 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10722
10723 PIPE_CONF_CHECK_I(pixel_multiplier);
10724 PIPE_CONF_CHECK_I(has_hdmi_sink);
10725 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10726 IS_VALLEYVIEW(dev))
10727 PIPE_CONF_CHECK_I(limited_color_range);
10728 PIPE_CONF_CHECK_I(has_infoframe);
10729
10730 PIPE_CONF_CHECK_I(has_audio);
10731
10732 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10733 DRM_MODE_FLAG_INTERLACE);
10734
10735 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10736 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10737 DRM_MODE_FLAG_PHSYNC);
10738 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10739 DRM_MODE_FLAG_NHSYNC);
10740 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10741 DRM_MODE_FLAG_PVSYNC);
10742 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10743 DRM_MODE_FLAG_NVSYNC);
10744 }
10745
10746 PIPE_CONF_CHECK_I(pipe_src_w);
10747 PIPE_CONF_CHECK_I(pipe_src_h);
10748
10749 /*
10750 * FIXME: BIOS likes to set up a cloned config with lvds+external
10751 * screen. Since we don't yet re-compute the pipe config when moving
10752 * just the lvds port away to another pipe the sw tracking won't match.
10753 *
10754 * Proper atomic modesets with recomputed global state will fix this.
10755 * Until then just don't check gmch state for inherited modes.
10756 */
10757 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10758 PIPE_CONF_CHECK_I(gmch_pfit.control);
10759 /* pfit ratios are autocomputed by the hw on gen4+ */
10760 if (INTEL_INFO(dev)->gen < 4)
10761 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10762 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10763 }
10764
10765 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10766 if (current_config->pch_pfit.enabled) {
10767 PIPE_CONF_CHECK_I(pch_pfit.pos);
10768 PIPE_CONF_CHECK_I(pch_pfit.size);
10769 }
10770
10771 /* BDW+ don't expose a synchronous way to read the state */
10772 if (IS_HASWELL(dev))
10773 PIPE_CONF_CHECK_I(ips_enabled);
10774
10775 PIPE_CONF_CHECK_I(double_wide);
10776
10777 PIPE_CONF_CHECK_X(ddi_pll_sel);
10778
10779 PIPE_CONF_CHECK_I(shared_dpll);
10780 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10781 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10782 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10783 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10784 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10785 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10786 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10787 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10788
10789 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10790 PIPE_CONF_CHECK_I(pipe_bpp);
10791
10792 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10793 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10794
10795 #undef PIPE_CONF_CHECK_X
10796 #undef PIPE_CONF_CHECK_I
10797 #undef PIPE_CONF_CHECK_I_ALT
10798 #undef PIPE_CONF_CHECK_FLAGS
10799 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10800 #undef PIPE_CONF_QUIRK
10801
10802 return true;
10803 }
10804
10805 static void check_wm_state(struct drm_device *dev)
10806 {
10807 struct drm_i915_private *dev_priv = dev->dev_private;
10808 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10809 struct intel_crtc *intel_crtc;
10810 int plane;
10811
10812 if (INTEL_INFO(dev)->gen < 9)
10813 return;
10814
10815 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10816 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10817
10818 for_each_intel_crtc(dev, intel_crtc) {
10819 struct skl_ddb_entry *hw_entry, *sw_entry;
10820 const enum pipe pipe = intel_crtc->pipe;
10821
10822 if (!intel_crtc->active)
10823 continue;
10824
10825 /* planes */
10826 for_each_plane(dev_priv, pipe, plane) {
10827 hw_entry = &hw_ddb.plane[pipe][plane];
10828 sw_entry = &sw_ddb->plane[pipe][plane];
10829
10830 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10831 continue;
10832
10833 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10834 "(expected (%u,%u), found (%u,%u))\n",
10835 pipe_name(pipe), plane + 1,
10836 sw_entry->start, sw_entry->end,
10837 hw_entry->start, hw_entry->end);
10838 }
10839
10840 /* cursor */
10841 hw_entry = &hw_ddb.cursor[pipe];
10842 sw_entry = &sw_ddb->cursor[pipe];
10843
10844 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10845 continue;
10846
10847 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10848 "(expected (%u,%u), found (%u,%u))\n",
10849 pipe_name(pipe),
10850 sw_entry->start, sw_entry->end,
10851 hw_entry->start, hw_entry->end);
10852 }
10853 }
10854
10855 static void
10856 check_connector_state(struct drm_device *dev)
10857 {
10858 struct intel_connector *connector;
10859
10860 for_each_intel_connector(dev, connector) {
10861 /* This also checks the encoder/connector hw state with the
10862 * ->get_hw_state callbacks. */
10863 intel_connector_check_state(connector);
10864
10865 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10866 "connector's staged encoder doesn't match current encoder\n");
10867 }
10868 }
10869
10870 static void
10871 check_encoder_state(struct drm_device *dev)
10872 {
10873 struct intel_encoder *encoder;
10874 struct intel_connector *connector;
10875
10876 for_each_intel_encoder(dev, encoder) {
10877 bool enabled = false;
10878 bool active = false;
10879 enum pipe pipe, tracked_pipe;
10880
10881 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10882 encoder->base.base.id,
10883 encoder->base.name);
10884
10885 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10886 "encoder's stage crtc doesn't match current crtc\n");
10887 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10888 "encoder's active_connectors set, but no crtc\n");
10889
10890 for_each_intel_connector(dev, connector) {
10891 if (connector->base.encoder != &encoder->base)
10892 continue;
10893 enabled = true;
10894 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10895 active = true;
10896 }
10897 /*
10898 * for MST connectors if we unplug the connector is gone
10899 * away but the encoder is still connected to a crtc
10900 * until a modeset happens in response to the hotplug.
10901 */
10902 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10903 continue;
10904
10905 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10906 "encoder's enabled state mismatch "
10907 "(expected %i, found %i)\n",
10908 !!encoder->base.crtc, enabled);
10909 I915_STATE_WARN(active && !encoder->base.crtc,
10910 "active encoder with no crtc\n");
10911
10912 I915_STATE_WARN(encoder->connectors_active != active,
10913 "encoder's computed active state doesn't match tracked active state "
10914 "(expected %i, found %i)\n", active, encoder->connectors_active);
10915
10916 active = encoder->get_hw_state(encoder, &pipe);
10917 I915_STATE_WARN(active != encoder->connectors_active,
10918 "encoder's hw state doesn't match sw tracking "
10919 "(expected %i, found %i)\n",
10920 encoder->connectors_active, active);
10921
10922 if (!encoder->base.crtc)
10923 continue;
10924
10925 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10926 I915_STATE_WARN(active && pipe != tracked_pipe,
10927 "active encoder's pipe doesn't match"
10928 "(expected %i, found %i)\n",
10929 tracked_pipe, pipe);
10930
10931 }
10932 }
10933
10934 static void
10935 check_crtc_state(struct drm_device *dev)
10936 {
10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct intel_crtc *crtc;
10939 struct intel_encoder *encoder;
10940 struct intel_crtc_state pipe_config;
10941
10942 for_each_intel_crtc(dev, crtc) {
10943 bool enabled = false;
10944 bool active = false;
10945
10946 memset(&pipe_config, 0, sizeof(pipe_config));
10947
10948 DRM_DEBUG_KMS("[CRTC:%d]\n",
10949 crtc->base.base.id);
10950
10951 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10952 "active crtc, but not enabled in sw tracking\n");
10953
10954 for_each_intel_encoder(dev, encoder) {
10955 if (encoder->base.crtc != &crtc->base)
10956 continue;
10957 enabled = true;
10958 if (encoder->connectors_active)
10959 active = true;
10960 }
10961
10962 I915_STATE_WARN(active != crtc->active,
10963 "crtc's computed active state doesn't match tracked active state "
10964 "(expected %i, found %i)\n", active, crtc->active);
10965 I915_STATE_WARN(enabled != crtc->base.state->enable,
10966 "crtc's computed enabled state doesn't match tracked enabled state "
10967 "(expected %i, found %i)\n", enabled,
10968 crtc->base.state->enable);
10969
10970 active = dev_priv->display.get_pipe_config(crtc,
10971 &pipe_config);
10972
10973 /* hw state is inconsistent with the pipe quirk */
10974 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10975 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10976 active = crtc->active;
10977
10978 for_each_intel_encoder(dev, encoder) {
10979 enum pipe pipe;
10980 if (encoder->base.crtc != &crtc->base)
10981 continue;
10982 if (encoder->get_hw_state(encoder, &pipe))
10983 encoder->get_config(encoder, &pipe_config);
10984 }
10985
10986 I915_STATE_WARN(crtc->active != active,
10987 "crtc active state doesn't match with hw state "
10988 "(expected %i, found %i)\n", crtc->active, active);
10989
10990 if (active &&
10991 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10992 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10993 intel_dump_pipe_config(crtc, &pipe_config,
10994 "[hw state]");
10995 intel_dump_pipe_config(crtc, crtc->config,
10996 "[sw state]");
10997 }
10998 }
10999 }
11000
11001 static void
11002 check_shared_dpll_state(struct drm_device *dev)
11003 {
11004 struct drm_i915_private *dev_priv = dev->dev_private;
11005 struct intel_crtc *crtc;
11006 struct intel_dpll_hw_state dpll_hw_state;
11007 int i;
11008
11009 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11010 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11011 int enabled_crtcs = 0, active_crtcs = 0;
11012 bool active;
11013
11014 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11015
11016 DRM_DEBUG_KMS("%s\n", pll->name);
11017
11018 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11019
11020 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11021 "more active pll users than references: %i vs %i\n",
11022 pll->active, hweight32(pll->config.crtc_mask));
11023 I915_STATE_WARN(pll->active && !pll->on,
11024 "pll in active use but not on in sw tracking\n");
11025 I915_STATE_WARN(pll->on && !pll->active,
11026 "pll in on but not on in use in sw tracking\n");
11027 I915_STATE_WARN(pll->on != active,
11028 "pll on state mismatch (expected %i, found %i)\n",
11029 pll->on, active);
11030
11031 for_each_intel_crtc(dev, crtc) {
11032 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11033 enabled_crtcs++;
11034 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11035 active_crtcs++;
11036 }
11037 I915_STATE_WARN(pll->active != active_crtcs,
11038 "pll active crtcs mismatch (expected %i, found %i)\n",
11039 pll->active, active_crtcs);
11040 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11041 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11042 hweight32(pll->config.crtc_mask), enabled_crtcs);
11043
11044 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11045 sizeof(dpll_hw_state)),
11046 "pll hw state mismatch\n");
11047 }
11048 }
11049
11050 void
11051 intel_modeset_check_state(struct drm_device *dev)
11052 {
11053 check_wm_state(dev);
11054 check_connector_state(dev);
11055 check_encoder_state(dev);
11056 check_crtc_state(dev);
11057 check_shared_dpll_state(dev);
11058 }
11059
11060 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11061 int dotclock)
11062 {
11063 /*
11064 * FDI already provided one idea for the dotclock.
11065 * Yell if the encoder disagrees.
11066 */
11067 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11068 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11069 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11070 }
11071
11072 static void update_scanline_offset(struct intel_crtc *crtc)
11073 {
11074 struct drm_device *dev = crtc->base.dev;
11075
11076 /*
11077 * The scanline counter increments at the leading edge of hsync.
11078 *
11079 * On most platforms it starts counting from vtotal-1 on the
11080 * first active line. That means the scanline counter value is
11081 * always one less than what we would expect. Ie. just after
11082 * start of vblank, which also occurs at start of hsync (on the
11083 * last active line), the scanline counter will read vblank_start-1.
11084 *
11085 * On gen2 the scanline counter starts counting from 1 instead
11086 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11087 * to keep the value positive), instead of adding one.
11088 *
11089 * On HSW+ the behaviour of the scanline counter depends on the output
11090 * type. For DP ports it behaves like most other platforms, but on HDMI
11091 * there's an extra 1 line difference. So we need to add two instead of
11092 * one to the value.
11093 */
11094 if (IS_GEN2(dev)) {
11095 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11096 int vtotal;
11097
11098 vtotal = mode->crtc_vtotal;
11099 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11100 vtotal /= 2;
11101
11102 crtc->scanline_offset = vtotal - 1;
11103 } else if (HAS_DDI(dev) &&
11104 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11105 crtc->scanline_offset = 2;
11106 } else
11107 crtc->scanline_offset = 1;
11108 }
11109
11110 static struct intel_crtc_state *
11111 intel_modeset_compute_config(struct drm_crtc *crtc,
11112 struct drm_display_mode *mode,
11113 struct drm_framebuffer *fb,
11114 unsigned *modeset_pipes,
11115 unsigned *prepare_pipes,
11116 unsigned *disable_pipes)
11117 {
11118 struct intel_crtc_state *pipe_config = NULL;
11119
11120 intel_modeset_affected_pipes(crtc, modeset_pipes,
11121 prepare_pipes, disable_pipes);
11122
11123 if ((*modeset_pipes) == 0)
11124 goto out;
11125
11126 /*
11127 * Note this needs changes when we start tracking multiple modes
11128 * and crtcs. At that point we'll need to compute the whole config
11129 * (i.e. one pipe_config for each crtc) rather than just the one
11130 * for this crtc.
11131 */
11132 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11133 if (IS_ERR(pipe_config)) {
11134 goto out;
11135 }
11136 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11137 "[modeset]");
11138
11139 out:
11140 return pipe_config;
11141 }
11142
11143 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11144 unsigned modeset_pipes,
11145 unsigned disable_pipes)
11146 {
11147 struct drm_i915_private *dev_priv = to_i915(dev);
11148 unsigned clear_pipes = modeset_pipes | disable_pipes;
11149 struct intel_crtc *intel_crtc;
11150 int ret = 0;
11151
11152 if (!dev_priv->display.crtc_compute_clock)
11153 return 0;
11154
11155 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11156 if (ret)
11157 goto done;
11158
11159 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11160 struct intel_crtc_state *state = intel_crtc->new_config;
11161 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11162 state);
11163 if (ret) {
11164 intel_shared_dpll_abort_config(dev_priv);
11165 goto done;
11166 }
11167 }
11168
11169 done:
11170 return ret;
11171 }
11172
11173 static int __intel_set_mode(struct drm_crtc *crtc,
11174 struct drm_display_mode *mode,
11175 int x, int y, struct drm_framebuffer *fb,
11176 struct intel_crtc_state *pipe_config,
11177 unsigned modeset_pipes,
11178 unsigned prepare_pipes,
11179 unsigned disable_pipes)
11180 {
11181 struct drm_device *dev = crtc->dev;
11182 struct drm_i915_private *dev_priv = dev->dev_private;
11183 struct drm_display_mode *saved_mode;
11184 struct intel_crtc *intel_crtc;
11185 int ret = 0;
11186
11187 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11188 if (!saved_mode)
11189 return -ENOMEM;
11190
11191 *saved_mode = crtc->mode;
11192
11193 if (modeset_pipes)
11194 to_intel_crtc(crtc)->new_config = pipe_config;
11195
11196 /*
11197 * See if the config requires any additional preparation, e.g.
11198 * to adjust global state with pipes off. We need to do this
11199 * here so we can get the modeset_pipe updated config for the new
11200 * mode set on this crtc. For other crtcs we need to use the
11201 * adjusted_mode bits in the crtc directly.
11202 */
11203 if (IS_VALLEYVIEW(dev)) {
11204 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11205
11206 /* may have added more to prepare_pipes than we should */
11207 prepare_pipes &= ~disable_pipes;
11208 }
11209
11210 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11211 if (ret)
11212 goto done;
11213
11214 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11215 intel_crtc_disable(&intel_crtc->base);
11216
11217 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11218 if (intel_crtc->base.state->enable)
11219 dev_priv->display.crtc_disable(&intel_crtc->base);
11220 }
11221
11222 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11223 * to set it here already despite that we pass it down the callchain.
11224 *
11225 * Note we'll need to fix this up when we start tracking multiple
11226 * pipes; here we assume a single modeset_pipe and only track the
11227 * single crtc and mode.
11228 */
11229 if (modeset_pipes) {
11230 crtc->mode = *mode;
11231 /* mode_set/enable/disable functions rely on a correct pipe
11232 * config. */
11233 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11234
11235 /*
11236 * Calculate and store various constants which
11237 * are later needed by vblank and swap-completion
11238 * timestamping. They are derived from true hwmode.
11239 */
11240 drm_calc_timestamping_constants(crtc,
11241 &pipe_config->base.adjusted_mode);
11242 }
11243
11244 /* Only after disabling all output pipelines that will be changed can we
11245 * update the the output configuration. */
11246 intel_modeset_update_state(dev, prepare_pipes);
11247
11248 modeset_update_crtc_power_domains(dev);
11249
11250 /* Set up the DPLL and any encoders state that needs to adjust or depend
11251 * on the DPLL.
11252 */
11253 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11254 struct drm_plane *primary = intel_crtc->base.primary;
11255 int vdisplay, hdisplay;
11256
11257 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11258 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11259 fb, 0, 0,
11260 hdisplay, vdisplay,
11261 x << 16, y << 16,
11262 hdisplay << 16, vdisplay << 16);
11263 }
11264
11265 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11266 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11267 update_scanline_offset(intel_crtc);
11268
11269 dev_priv->display.crtc_enable(&intel_crtc->base);
11270 }
11271
11272 /* FIXME: add subpixel order */
11273 done:
11274 if (ret && crtc->state->enable)
11275 crtc->mode = *saved_mode;
11276
11277 kfree(saved_mode);
11278 return ret;
11279 }
11280
11281 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11282 struct drm_display_mode *mode,
11283 int x, int y, struct drm_framebuffer *fb,
11284 struct intel_crtc_state *pipe_config,
11285 unsigned modeset_pipes,
11286 unsigned prepare_pipes,
11287 unsigned disable_pipes)
11288 {
11289 int ret;
11290
11291 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11292 prepare_pipes, disable_pipes);
11293
11294 if (ret == 0)
11295 intel_modeset_check_state(crtc->dev);
11296
11297 return ret;
11298 }
11299
11300 static int intel_set_mode(struct drm_crtc *crtc,
11301 struct drm_display_mode *mode,
11302 int x, int y, struct drm_framebuffer *fb)
11303 {
11304 struct intel_crtc_state *pipe_config;
11305 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11306
11307 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11308 &modeset_pipes,
11309 &prepare_pipes,
11310 &disable_pipes);
11311
11312 if (IS_ERR(pipe_config))
11313 return PTR_ERR(pipe_config);
11314
11315 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11316 modeset_pipes, prepare_pipes,
11317 disable_pipes);
11318 }
11319
11320 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11321 {
11322 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11323 }
11324
11325 #undef for_each_intel_crtc_masked
11326
11327 static void intel_set_config_free(struct intel_set_config *config)
11328 {
11329 if (!config)
11330 return;
11331
11332 kfree(config->save_connector_encoders);
11333 kfree(config->save_encoder_crtcs);
11334 kfree(config->save_crtc_enabled);
11335 kfree(config);
11336 }
11337
11338 static int intel_set_config_save_state(struct drm_device *dev,
11339 struct intel_set_config *config)
11340 {
11341 struct drm_crtc *crtc;
11342 struct drm_encoder *encoder;
11343 struct drm_connector *connector;
11344 int count;
11345
11346 config->save_crtc_enabled =
11347 kcalloc(dev->mode_config.num_crtc,
11348 sizeof(bool), GFP_KERNEL);
11349 if (!config->save_crtc_enabled)
11350 return -ENOMEM;
11351
11352 config->save_encoder_crtcs =
11353 kcalloc(dev->mode_config.num_encoder,
11354 sizeof(struct drm_crtc *), GFP_KERNEL);
11355 if (!config->save_encoder_crtcs)
11356 return -ENOMEM;
11357
11358 config->save_connector_encoders =
11359 kcalloc(dev->mode_config.num_connector,
11360 sizeof(struct drm_encoder *), GFP_KERNEL);
11361 if (!config->save_connector_encoders)
11362 return -ENOMEM;
11363
11364 /* Copy data. Note that driver private data is not affected.
11365 * Should anything bad happen only the expected state is
11366 * restored, not the drivers personal bookkeeping.
11367 */
11368 count = 0;
11369 for_each_crtc(dev, crtc) {
11370 config->save_crtc_enabled[count++] = crtc->state->enable;
11371 }
11372
11373 count = 0;
11374 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11375 config->save_encoder_crtcs[count++] = encoder->crtc;
11376 }
11377
11378 count = 0;
11379 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11380 config->save_connector_encoders[count++] = connector->encoder;
11381 }
11382
11383 return 0;
11384 }
11385
11386 static void intel_set_config_restore_state(struct drm_device *dev,
11387 struct intel_set_config *config)
11388 {
11389 struct intel_crtc *crtc;
11390 struct intel_encoder *encoder;
11391 struct intel_connector *connector;
11392 int count;
11393
11394 count = 0;
11395 for_each_intel_crtc(dev, crtc) {
11396 crtc->new_enabled = config->save_crtc_enabled[count++];
11397
11398 if (crtc->new_enabled)
11399 crtc->new_config = crtc->config;
11400 else
11401 crtc->new_config = NULL;
11402 }
11403
11404 count = 0;
11405 for_each_intel_encoder(dev, encoder) {
11406 encoder->new_crtc =
11407 to_intel_crtc(config->save_encoder_crtcs[count++]);
11408 }
11409
11410 count = 0;
11411 for_each_intel_connector(dev, connector) {
11412 connector->new_encoder =
11413 to_intel_encoder(config->save_connector_encoders[count++]);
11414 }
11415 }
11416
11417 static bool
11418 is_crtc_connector_off(struct drm_mode_set *set)
11419 {
11420 int i;
11421
11422 if (set->num_connectors == 0)
11423 return false;
11424
11425 if (WARN_ON(set->connectors == NULL))
11426 return false;
11427
11428 for (i = 0; i < set->num_connectors; i++)
11429 if (set->connectors[i]->encoder &&
11430 set->connectors[i]->encoder->crtc == set->crtc &&
11431 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11432 return true;
11433
11434 return false;
11435 }
11436
11437 static void
11438 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11439 struct intel_set_config *config)
11440 {
11441
11442 /* We should be able to check here if the fb has the same properties
11443 * and then just flip_or_move it */
11444 if (is_crtc_connector_off(set)) {
11445 config->mode_changed = true;
11446 } else if (set->crtc->primary->fb != set->fb) {
11447 /*
11448 * If we have no fb, we can only flip as long as the crtc is
11449 * active, otherwise we need a full mode set. The crtc may
11450 * be active if we've only disabled the primary plane, or
11451 * in fastboot situations.
11452 */
11453 if (set->crtc->primary->fb == NULL) {
11454 struct intel_crtc *intel_crtc =
11455 to_intel_crtc(set->crtc);
11456
11457 if (intel_crtc->active) {
11458 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11459 config->fb_changed = true;
11460 } else {
11461 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11462 config->mode_changed = true;
11463 }
11464 } else if (set->fb == NULL) {
11465 config->mode_changed = true;
11466 } else if (set->fb->pixel_format !=
11467 set->crtc->primary->fb->pixel_format) {
11468 config->mode_changed = true;
11469 } else {
11470 config->fb_changed = true;
11471 }
11472 }
11473
11474 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11475 config->fb_changed = true;
11476
11477 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11478 DRM_DEBUG_KMS("modes are different, full mode set\n");
11479 drm_mode_debug_printmodeline(&set->crtc->mode);
11480 drm_mode_debug_printmodeline(set->mode);
11481 config->mode_changed = true;
11482 }
11483
11484 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11485 set->crtc->base.id, config->mode_changed, config->fb_changed);
11486 }
11487
11488 static int
11489 intel_modeset_stage_output_state(struct drm_device *dev,
11490 struct drm_mode_set *set,
11491 struct intel_set_config *config)
11492 {
11493 struct intel_connector *connector;
11494 struct intel_encoder *encoder;
11495 struct intel_crtc *crtc;
11496 int ro;
11497
11498 /* The upper layers ensure that we either disable a crtc or have a list
11499 * of connectors. For paranoia, double-check this. */
11500 WARN_ON(!set->fb && (set->num_connectors != 0));
11501 WARN_ON(set->fb && (set->num_connectors == 0));
11502
11503 for_each_intel_connector(dev, connector) {
11504 /* Otherwise traverse passed in connector list and get encoders
11505 * for them. */
11506 for (ro = 0; ro < set->num_connectors; ro++) {
11507 if (set->connectors[ro] == &connector->base) {
11508 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11509 break;
11510 }
11511 }
11512
11513 /* If we disable the crtc, disable all its connectors. Also, if
11514 * the connector is on the changing crtc but not on the new
11515 * connector list, disable it. */
11516 if ((!set->fb || ro == set->num_connectors) &&
11517 connector->base.encoder &&
11518 connector->base.encoder->crtc == set->crtc) {
11519 connector->new_encoder = NULL;
11520
11521 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11522 connector->base.base.id,
11523 connector->base.name);
11524 }
11525
11526
11527 if (&connector->new_encoder->base != connector->base.encoder) {
11528 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11529 connector->base.base.id,
11530 connector->base.name);
11531 config->mode_changed = true;
11532 }
11533 }
11534 /* connector->new_encoder is now updated for all connectors. */
11535
11536 /* Update crtc of enabled connectors. */
11537 for_each_intel_connector(dev, connector) {
11538 struct drm_crtc *new_crtc;
11539
11540 if (!connector->new_encoder)
11541 continue;
11542
11543 new_crtc = connector->new_encoder->base.crtc;
11544
11545 for (ro = 0; ro < set->num_connectors; ro++) {
11546 if (set->connectors[ro] == &connector->base)
11547 new_crtc = set->crtc;
11548 }
11549
11550 /* Make sure the new CRTC will work with the encoder */
11551 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11552 new_crtc)) {
11553 return -EINVAL;
11554 }
11555 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11556
11557 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11558 connector->base.base.id,
11559 connector->base.name,
11560 new_crtc->base.id);
11561 }
11562
11563 /* Check for any encoders that needs to be disabled. */
11564 for_each_intel_encoder(dev, encoder) {
11565 int num_connectors = 0;
11566 for_each_intel_connector(dev, connector) {
11567 if (connector->new_encoder == encoder) {
11568 WARN_ON(!connector->new_encoder->new_crtc);
11569 num_connectors++;
11570 }
11571 }
11572
11573 if (num_connectors == 0)
11574 encoder->new_crtc = NULL;
11575 else if (num_connectors > 1)
11576 return -EINVAL;
11577
11578 /* Only now check for crtc changes so we don't miss encoders
11579 * that will be disabled. */
11580 if (&encoder->new_crtc->base != encoder->base.crtc) {
11581 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11582 encoder->base.base.id,
11583 encoder->base.name);
11584 config->mode_changed = true;
11585 }
11586 }
11587 /* Now we've also updated encoder->new_crtc for all encoders. */
11588 for_each_intel_connector(dev, connector) {
11589 if (connector->new_encoder)
11590 if (connector->new_encoder != connector->encoder)
11591 connector->encoder = connector->new_encoder;
11592 }
11593 for_each_intel_crtc(dev, crtc) {
11594 crtc->new_enabled = false;
11595
11596 for_each_intel_encoder(dev, encoder) {
11597 if (encoder->new_crtc == crtc) {
11598 crtc->new_enabled = true;
11599 break;
11600 }
11601 }
11602
11603 if (crtc->new_enabled != crtc->base.state->enable) {
11604 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11605 crtc->base.base.id,
11606 crtc->new_enabled ? "en" : "dis");
11607 config->mode_changed = true;
11608 }
11609
11610 if (crtc->new_enabled)
11611 crtc->new_config = crtc->config;
11612 else
11613 crtc->new_config = NULL;
11614 }
11615
11616 return 0;
11617 }
11618
11619 static void disable_crtc_nofb(struct intel_crtc *crtc)
11620 {
11621 struct drm_device *dev = crtc->base.dev;
11622 struct intel_encoder *encoder;
11623 struct intel_connector *connector;
11624
11625 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11626 pipe_name(crtc->pipe));
11627
11628 for_each_intel_connector(dev, connector) {
11629 if (connector->new_encoder &&
11630 connector->new_encoder->new_crtc == crtc)
11631 connector->new_encoder = NULL;
11632 }
11633
11634 for_each_intel_encoder(dev, encoder) {
11635 if (encoder->new_crtc == crtc)
11636 encoder->new_crtc = NULL;
11637 }
11638
11639 crtc->new_enabled = false;
11640 crtc->new_config = NULL;
11641 }
11642
11643 static int intel_crtc_set_config(struct drm_mode_set *set)
11644 {
11645 struct drm_device *dev;
11646 struct drm_mode_set save_set;
11647 struct intel_set_config *config;
11648 struct intel_crtc_state *pipe_config;
11649 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11650 int ret;
11651
11652 BUG_ON(!set);
11653 BUG_ON(!set->crtc);
11654 BUG_ON(!set->crtc->helper_private);
11655
11656 /* Enforce sane interface api - has been abused by the fb helper. */
11657 BUG_ON(!set->mode && set->fb);
11658 BUG_ON(set->fb && set->num_connectors == 0);
11659
11660 if (set->fb) {
11661 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11662 set->crtc->base.id, set->fb->base.id,
11663 (int)set->num_connectors, set->x, set->y);
11664 } else {
11665 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11666 }
11667
11668 dev = set->crtc->dev;
11669
11670 ret = -ENOMEM;
11671 config = kzalloc(sizeof(*config), GFP_KERNEL);
11672 if (!config)
11673 goto out_config;
11674
11675 ret = intel_set_config_save_state(dev, config);
11676 if (ret)
11677 goto out_config;
11678
11679 save_set.crtc = set->crtc;
11680 save_set.mode = &set->crtc->mode;
11681 save_set.x = set->crtc->x;
11682 save_set.y = set->crtc->y;
11683 save_set.fb = set->crtc->primary->fb;
11684
11685 /* Compute whether we need a full modeset, only an fb base update or no
11686 * change at all. In the future we might also check whether only the
11687 * mode changed, e.g. for LVDS where we only change the panel fitter in
11688 * such cases. */
11689 intel_set_config_compute_mode_changes(set, config);
11690
11691 ret = intel_modeset_stage_output_state(dev, set, config);
11692 if (ret)
11693 goto fail;
11694
11695 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11696 set->fb,
11697 &modeset_pipes,
11698 &prepare_pipes,
11699 &disable_pipes);
11700 if (IS_ERR(pipe_config)) {
11701 ret = PTR_ERR(pipe_config);
11702 goto fail;
11703 } else if (pipe_config) {
11704 if (pipe_config->has_audio !=
11705 to_intel_crtc(set->crtc)->config->has_audio)
11706 config->mode_changed = true;
11707
11708 /*
11709 * Note we have an issue here with infoframes: current code
11710 * only updates them on the full mode set path per hw
11711 * requirements. So here we should be checking for any
11712 * required changes and forcing a mode set.
11713 */
11714 }
11715
11716 /* set_mode will free it in the mode_changed case */
11717 if (!config->mode_changed)
11718 kfree(pipe_config);
11719
11720 intel_update_pipe_size(to_intel_crtc(set->crtc));
11721
11722 if (config->mode_changed) {
11723 ret = intel_set_mode_pipes(set->crtc, set->mode,
11724 set->x, set->y, set->fb, pipe_config,
11725 modeset_pipes, prepare_pipes,
11726 disable_pipes);
11727 } else if (config->fb_changed) {
11728 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11729 struct drm_plane *primary = set->crtc->primary;
11730 int vdisplay, hdisplay;
11731
11732 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11733 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11734 0, 0, hdisplay, vdisplay,
11735 set->x << 16, set->y << 16,
11736 hdisplay << 16, vdisplay << 16);
11737
11738 /*
11739 * We need to make sure the primary plane is re-enabled if it
11740 * has previously been turned off.
11741 */
11742 if (!intel_crtc->primary_enabled && ret == 0) {
11743 WARN_ON(!intel_crtc->active);
11744 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11745 }
11746
11747 /*
11748 * In the fastboot case this may be our only check of the
11749 * state after boot. It would be better to only do it on
11750 * the first update, but we don't have a nice way of doing that
11751 * (and really, set_config isn't used much for high freq page
11752 * flipping, so increasing its cost here shouldn't be a big
11753 * deal).
11754 */
11755 if (i915.fastboot && ret == 0)
11756 intel_modeset_check_state(set->crtc->dev);
11757 }
11758
11759 if (ret) {
11760 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11761 set->crtc->base.id, ret);
11762 fail:
11763 intel_set_config_restore_state(dev, config);
11764
11765 /*
11766 * HACK: if the pipe was on, but we didn't have a framebuffer,
11767 * force the pipe off to avoid oopsing in the modeset code
11768 * due to fb==NULL. This should only happen during boot since
11769 * we don't yet reconstruct the FB from the hardware state.
11770 */
11771 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11772 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11773
11774 /* Try to restore the config */
11775 if (config->mode_changed &&
11776 intel_set_mode(save_set.crtc, save_set.mode,
11777 save_set.x, save_set.y, save_set.fb))
11778 DRM_ERROR("failed to restore config after modeset failure\n");
11779 }
11780
11781 out_config:
11782 intel_set_config_free(config);
11783 return ret;
11784 }
11785
11786 static const struct drm_crtc_funcs intel_crtc_funcs = {
11787 .gamma_set = intel_crtc_gamma_set,
11788 .set_config = intel_crtc_set_config,
11789 .destroy = intel_crtc_destroy,
11790 .page_flip = intel_crtc_page_flip,
11791 .atomic_duplicate_state = intel_crtc_duplicate_state,
11792 .atomic_destroy_state = intel_crtc_destroy_state,
11793 };
11794
11795 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11796 struct intel_shared_dpll *pll,
11797 struct intel_dpll_hw_state *hw_state)
11798 {
11799 uint32_t val;
11800
11801 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11802 return false;
11803
11804 val = I915_READ(PCH_DPLL(pll->id));
11805 hw_state->dpll = val;
11806 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11807 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11808
11809 return val & DPLL_VCO_ENABLE;
11810 }
11811
11812 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11813 struct intel_shared_dpll *pll)
11814 {
11815 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11816 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11817 }
11818
11819 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11820 struct intel_shared_dpll *pll)
11821 {
11822 /* PCH refclock must be enabled first */
11823 ibx_assert_pch_refclk_enabled(dev_priv);
11824
11825 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11826
11827 /* Wait for the clocks to stabilize. */
11828 POSTING_READ(PCH_DPLL(pll->id));
11829 udelay(150);
11830
11831 /* The pixel multiplier can only be updated once the
11832 * DPLL is enabled and the clocks are stable.
11833 *
11834 * So write it again.
11835 */
11836 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11837 POSTING_READ(PCH_DPLL(pll->id));
11838 udelay(200);
11839 }
11840
11841 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11842 struct intel_shared_dpll *pll)
11843 {
11844 struct drm_device *dev = dev_priv->dev;
11845 struct intel_crtc *crtc;
11846
11847 /* Make sure no transcoder isn't still depending on us. */
11848 for_each_intel_crtc(dev, crtc) {
11849 if (intel_crtc_to_shared_dpll(crtc) == pll)
11850 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11851 }
11852
11853 I915_WRITE(PCH_DPLL(pll->id), 0);
11854 POSTING_READ(PCH_DPLL(pll->id));
11855 udelay(200);
11856 }
11857
11858 static char *ibx_pch_dpll_names[] = {
11859 "PCH DPLL A",
11860 "PCH DPLL B",
11861 };
11862
11863 static void ibx_pch_dpll_init(struct drm_device *dev)
11864 {
11865 struct drm_i915_private *dev_priv = dev->dev_private;
11866 int i;
11867
11868 dev_priv->num_shared_dpll = 2;
11869
11870 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11871 dev_priv->shared_dplls[i].id = i;
11872 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11873 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11874 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11875 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11876 dev_priv->shared_dplls[i].get_hw_state =
11877 ibx_pch_dpll_get_hw_state;
11878 }
11879 }
11880
11881 static void intel_shared_dpll_init(struct drm_device *dev)
11882 {
11883 struct drm_i915_private *dev_priv = dev->dev_private;
11884
11885 if (HAS_DDI(dev))
11886 intel_ddi_pll_init(dev);
11887 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11888 ibx_pch_dpll_init(dev);
11889 else
11890 dev_priv->num_shared_dpll = 0;
11891
11892 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11893 }
11894
11895 /**
11896 * intel_prepare_plane_fb - Prepare fb for usage on plane
11897 * @plane: drm plane to prepare for
11898 * @fb: framebuffer to prepare for presentation
11899 *
11900 * Prepares a framebuffer for usage on a display plane. Generally this
11901 * involves pinning the underlying object and updating the frontbuffer tracking
11902 * bits. Some older platforms need special physical address handling for
11903 * cursor planes.
11904 *
11905 * Returns 0 on success, negative error code on failure.
11906 */
11907 int
11908 intel_prepare_plane_fb(struct drm_plane *plane,
11909 struct drm_framebuffer *fb,
11910 const struct drm_plane_state *new_state)
11911 {
11912 struct drm_device *dev = plane->dev;
11913 struct intel_plane *intel_plane = to_intel_plane(plane);
11914 enum pipe pipe = intel_plane->pipe;
11915 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11916 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11917 unsigned frontbuffer_bits = 0;
11918 int ret = 0;
11919
11920 if (!obj)
11921 return 0;
11922
11923 switch (plane->type) {
11924 case DRM_PLANE_TYPE_PRIMARY:
11925 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11926 break;
11927 case DRM_PLANE_TYPE_CURSOR:
11928 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11929 break;
11930 case DRM_PLANE_TYPE_OVERLAY:
11931 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11932 break;
11933 }
11934
11935 mutex_lock(&dev->struct_mutex);
11936
11937 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11938 INTEL_INFO(dev)->cursor_needs_physical) {
11939 int align = IS_I830(dev) ? 16 * 1024 : 256;
11940 ret = i915_gem_object_attach_phys(obj, align);
11941 if (ret)
11942 DRM_DEBUG_KMS("failed to attach phys object\n");
11943 } else {
11944 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11945 }
11946
11947 if (ret == 0)
11948 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11949
11950 mutex_unlock(&dev->struct_mutex);
11951
11952 return ret;
11953 }
11954
11955 /**
11956 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11957 * @plane: drm plane to clean up for
11958 * @fb: old framebuffer that was on plane
11959 *
11960 * Cleans up a framebuffer that has just been removed from a plane.
11961 */
11962 void
11963 intel_cleanup_plane_fb(struct drm_plane *plane,
11964 struct drm_framebuffer *fb,
11965 const struct drm_plane_state *old_state)
11966 {
11967 struct drm_device *dev = plane->dev;
11968 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11969
11970 if (WARN_ON(!obj))
11971 return;
11972
11973 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11974 !INTEL_INFO(dev)->cursor_needs_physical) {
11975 mutex_lock(&dev->struct_mutex);
11976 intel_unpin_fb_obj(obj);
11977 mutex_unlock(&dev->struct_mutex);
11978 }
11979 }
11980
11981 static int
11982 intel_check_primary_plane(struct drm_plane *plane,
11983 struct intel_plane_state *state)
11984 {
11985 struct drm_device *dev = plane->dev;
11986 struct drm_i915_private *dev_priv = dev->dev_private;
11987 struct drm_crtc *crtc = state->base.crtc;
11988 struct intel_crtc *intel_crtc;
11989 struct drm_framebuffer *fb = state->base.fb;
11990 struct drm_rect *dest = &state->dst;
11991 struct drm_rect *src = &state->src;
11992 const struct drm_rect *clip = &state->clip;
11993 int ret;
11994
11995 crtc = crtc ? crtc : plane->crtc;
11996 intel_crtc = to_intel_crtc(crtc);
11997
11998 ret = drm_plane_helper_check_update(plane, crtc, fb,
11999 src, dest, clip,
12000 DRM_PLANE_HELPER_NO_SCALING,
12001 DRM_PLANE_HELPER_NO_SCALING,
12002 false, true, &state->visible);
12003 if (ret)
12004 return ret;
12005
12006 if (intel_crtc->active) {
12007 intel_crtc->atomic.wait_for_flips = true;
12008
12009 /*
12010 * FBC does not work on some platforms for rotated
12011 * planes, so disable it when rotation is not 0 and
12012 * update it when rotation is set back to 0.
12013 *
12014 * FIXME: This is redundant with the fbc update done in
12015 * the primary plane enable function except that that
12016 * one is done too late. We eventually need to unify
12017 * this.
12018 */
12019 if (intel_crtc->primary_enabled &&
12020 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12021 dev_priv->fbc.crtc == intel_crtc &&
12022 state->base.rotation != BIT(DRM_ROTATE_0)) {
12023 intel_crtc->atomic.disable_fbc = true;
12024 }
12025
12026 if (state->visible) {
12027 /*
12028 * BDW signals flip done immediately if the plane
12029 * is disabled, even if the plane enable is already
12030 * armed to occur at the next vblank :(
12031 */
12032 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12033 intel_crtc->atomic.wait_vblank = true;
12034 }
12035
12036 intel_crtc->atomic.fb_bits |=
12037 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12038
12039 intel_crtc->atomic.update_fbc = true;
12040
12041 /* Update watermarks on tiling changes. */
12042 if (!plane->state->fb || !state->base.fb ||
12043 plane->state->fb->modifier[0] !=
12044 state->base.fb->modifier[0])
12045 intel_crtc->atomic.update_wm = true;
12046 }
12047
12048 return 0;
12049 }
12050
12051 static void
12052 intel_commit_primary_plane(struct drm_plane *plane,
12053 struct intel_plane_state *state)
12054 {
12055 struct drm_crtc *crtc = state->base.crtc;
12056 struct drm_framebuffer *fb = state->base.fb;
12057 struct drm_device *dev = plane->dev;
12058 struct drm_i915_private *dev_priv = dev->dev_private;
12059 struct intel_crtc *intel_crtc;
12060 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12061 struct intel_plane *intel_plane = to_intel_plane(plane);
12062 struct drm_rect *src = &state->src;
12063
12064 crtc = crtc ? crtc : plane->crtc;
12065 intel_crtc = to_intel_crtc(crtc);
12066
12067 plane->fb = fb;
12068 crtc->x = src->x1 >> 16;
12069 crtc->y = src->y1 >> 16;
12070
12071 intel_plane->obj = obj;
12072
12073 if (intel_crtc->active) {
12074 if (state->visible) {
12075 /* FIXME: kill this fastboot hack */
12076 intel_update_pipe_size(intel_crtc);
12077
12078 intel_crtc->primary_enabled = true;
12079
12080 dev_priv->display.update_primary_plane(crtc, plane->fb,
12081 crtc->x, crtc->y);
12082 } else {
12083 /*
12084 * If clipping results in a non-visible primary plane,
12085 * we'll disable the primary plane. Note that this is
12086 * a bit different than what happens if userspace
12087 * explicitly disables the plane by passing fb=0
12088 * because plane->fb still gets set and pinned.
12089 */
12090 intel_disable_primary_hw_plane(plane, crtc);
12091 }
12092 }
12093 }
12094
12095 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12096 {
12097 struct drm_device *dev = crtc->dev;
12098 struct drm_i915_private *dev_priv = dev->dev_private;
12099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12100 struct intel_plane *intel_plane;
12101 struct drm_plane *p;
12102 unsigned fb_bits = 0;
12103
12104 /* Track fb's for any planes being disabled */
12105 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12106 intel_plane = to_intel_plane(p);
12107
12108 if (intel_crtc->atomic.disabled_planes &
12109 (1 << drm_plane_index(p))) {
12110 switch (p->type) {
12111 case DRM_PLANE_TYPE_PRIMARY:
12112 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12113 break;
12114 case DRM_PLANE_TYPE_CURSOR:
12115 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12116 break;
12117 case DRM_PLANE_TYPE_OVERLAY:
12118 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12119 break;
12120 }
12121
12122 mutex_lock(&dev->struct_mutex);
12123 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12124 mutex_unlock(&dev->struct_mutex);
12125 }
12126 }
12127
12128 if (intel_crtc->atomic.wait_for_flips)
12129 intel_crtc_wait_for_pending_flips(crtc);
12130
12131 if (intel_crtc->atomic.disable_fbc)
12132 intel_fbc_disable(dev);
12133
12134 if (intel_crtc->atomic.pre_disable_primary)
12135 intel_pre_disable_primary(crtc);
12136
12137 if (intel_crtc->atomic.update_wm)
12138 intel_update_watermarks(crtc);
12139
12140 intel_runtime_pm_get(dev_priv);
12141
12142 /* Perform vblank evasion around commit operation */
12143 if (intel_crtc->active)
12144 intel_crtc->atomic.evade =
12145 intel_pipe_update_start(intel_crtc,
12146 &intel_crtc->atomic.start_vbl_count);
12147 }
12148
12149 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12150 {
12151 struct drm_device *dev = crtc->dev;
12152 struct drm_i915_private *dev_priv = dev->dev_private;
12153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12154 struct drm_plane *p;
12155
12156 if (intel_crtc->atomic.evade)
12157 intel_pipe_update_end(intel_crtc,
12158 intel_crtc->atomic.start_vbl_count);
12159
12160 intel_runtime_pm_put(dev_priv);
12161
12162 if (intel_crtc->atomic.wait_vblank)
12163 intel_wait_for_vblank(dev, intel_crtc->pipe);
12164
12165 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12166
12167 if (intel_crtc->atomic.update_fbc) {
12168 mutex_lock(&dev->struct_mutex);
12169 intel_fbc_update(dev);
12170 mutex_unlock(&dev->struct_mutex);
12171 }
12172
12173 if (intel_crtc->atomic.post_enable_primary)
12174 intel_post_enable_primary(crtc);
12175
12176 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12177 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12178 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12179 false, false);
12180
12181 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12182 }
12183
12184 /**
12185 * intel_plane_destroy - destroy a plane
12186 * @plane: plane to destroy
12187 *
12188 * Common destruction function for all types of planes (primary, cursor,
12189 * sprite).
12190 */
12191 void intel_plane_destroy(struct drm_plane *plane)
12192 {
12193 struct intel_plane *intel_plane = to_intel_plane(plane);
12194 drm_plane_cleanup(plane);
12195 kfree(intel_plane);
12196 }
12197
12198 const struct drm_plane_funcs intel_plane_funcs = {
12199 .update_plane = drm_plane_helper_update,
12200 .disable_plane = drm_plane_helper_disable,
12201 .destroy = intel_plane_destroy,
12202 .set_property = drm_atomic_helper_plane_set_property,
12203 .atomic_get_property = intel_plane_atomic_get_property,
12204 .atomic_set_property = intel_plane_atomic_set_property,
12205 .atomic_duplicate_state = intel_plane_duplicate_state,
12206 .atomic_destroy_state = intel_plane_destroy_state,
12207
12208 };
12209
12210 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12211 int pipe)
12212 {
12213 struct intel_plane *primary;
12214 struct intel_plane_state *state;
12215 const uint32_t *intel_primary_formats;
12216 int num_formats;
12217
12218 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12219 if (primary == NULL)
12220 return NULL;
12221
12222 state = intel_create_plane_state(&primary->base);
12223 if (!state) {
12224 kfree(primary);
12225 return NULL;
12226 }
12227 primary->base.state = &state->base;
12228
12229 primary->can_scale = false;
12230 primary->max_downscale = 1;
12231 primary->pipe = pipe;
12232 primary->plane = pipe;
12233 primary->check_plane = intel_check_primary_plane;
12234 primary->commit_plane = intel_commit_primary_plane;
12235 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12236 primary->plane = !pipe;
12237
12238 if (INTEL_INFO(dev)->gen <= 3) {
12239 intel_primary_formats = intel_primary_formats_gen2;
12240 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12241 } else {
12242 intel_primary_formats = intel_primary_formats_gen4;
12243 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12244 }
12245
12246 drm_universal_plane_init(dev, &primary->base, 0,
12247 &intel_plane_funcs,
12248 intel_primary_formats, num_formats,
12249 DRM_PLANE_TYPE_PRIMARY);
12250
12251 if (INTEL_INFO(dev)->gen >= 4) {
12252 if (!dev->mode_config.rotation_property)
12253 dev->mode_config.rotation_property =
12254 drm_mode_create_rotation_property(dev,
12255 BIT(DRM_ROTATE_0) |
12256 BIT(DRM_ROTATE_180));
12257 if (dev->mode_config.rotation_property)
12258 drm_object_attach_property(&primary->base.base,
12259 dev->mode_config.rotation_property,
12260 state->base.rotation);
12261 }
12262
12263 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12264
12265 return &primary->base;
12266 }
12267
12268 static int
12269 intel_check_cursor_plane(struct drm_plane *plane,
12270 struct intel_plane_state *state)
12271 {
12272 struct drm_crtc *crtc = state->base.crtc;
12273 struct drm_device *dev = plane->dev;
12274 struct drm_framebuffer *fb = state->base.fb;
12275 struct drm_rect *dest = &state->dst;
12276 struct drm_rect *src = &state->src;
12277 const struct drm_rect *clip = &state->clip;
12278 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12279 struct intel_crtc *intel_crtc;
12280 unsigned stride;
12281 int ret;
12282
12283 crtc = crtc ? crtc : plane->crtc;
12284 intel_crtc = to_intel_crtc(crtc);
12285
12286 ret = drm_plane_helper_check_update(plane, crtc, fb,
12287 src, dest, clip,
12288 DRM_PLANE_HELPER_NO_SCALING,
12289 DRM_PLANE_HELPER_NO_SCALING,
12290 true, true, &state->visible);
12291 if (ret)
12292 return ret;
12293
12294
12295 /* if we want to turn off the cursor ignore width and height */
12296 if (!obj)
12297 goto finish;
12298
12299 /* Check for which cursor types we support */
12300 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12301 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12302 state->base.crtc_w, state->base.crtc_h);
12303 return -EINVAL;
12304 }
12305
12306 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12307 if (obj->base.size < stride * state->base.crtc_h) {
12308 DRM_DEBUG_KMS("buffer is too small\n");
12309 return -ENOMEM;
12310 }
12311
12312 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12313 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12314 ret = -EINVAL;
12315 }
12316
12317 finish:
12318 if (intel_crtc->active) {
12319 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12320 intel_crtc->atomic.update_wm = true;
12321
12322 intel_crtc->atomic.fb_bits |=
12323 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12324 }
12325
12326 return ret;
12327 }
12328
12329 static void
12330 intel_commit_cursor_plane(struct drm_plane *plane,
12331 struct intel_plane_state *state)
12332 {
12333 struct drm_crtc *crtc = state->base.crtc;
12334 struct drm_device *dev = plane->dev;
12335 struct intel_crtc *intel_crtc;
12336 struct intel_plane *intel_plane = to_intel_plane(plane);
12337 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12338 uint32_t addr;
12339
12340 crtc = crtc ? crtc : plane->crtc;
12341 intel_crtc = to_intel_crtc(crtc);
12342
12343 plane->fb = state->base.fb;
12344 crtc->cursor_x = state->base.crtc_x;
12345 crtc->cursor_y = state->base.crtc_y;
12346
12347 intel_plane->obj = obj;
12348
12349 if (intel_crtc->cursor_bo == obj)
12350 goto update;
12351
12352 if (!obj)
12353 addr = 0;
12354 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12355 addr = i915_gem_obj_ggtt_offset(obj);
12356 else
12357 addr = obj->phys_handle->busaddr;
12358
12359 intel_crtc->cursor_addr = addr;
12360 intel_crtc->cursor_bo = obj;
12361 update:
12362
12363 if (intel_crtc->active)
12364 intel_crtc_update_cursor(crtc, state->visible);
12365 }
12366
12367 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12368 int pipe)
12369 {
12370 struct intel_plane *cursor;
12371 struct intel_plane_state *state;
12372
12373 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12374 if (cursor == NULL)
12375 return NULL;
12376
12377 state = intel_create_plane_state(&cursor->base);
12378 if (!state) {
12379 kfree(cursor);
12380 return NULL;
12381 }
12382 cursor->base.state = &state->base;
12383
12384 cursor->can_scale = false;
12385 cursor->max_downscale = 1;
12386 cursor->pipe = pipe;
12387 cursor->plane = pipe;
12388 cursor->check_plane = intel_check_cursor_plane;
12389 cursor->commit_plane = intel_commit_cursor_plane;
12390
12391 drm_universal_plane_init(dev, &cursor->base, 0,
12392 &intel_plane_funcs,
12393 intel_cursor_formats,
12394 ARRAY_SIZE(intel_cursor_formats),
12395 DRM_PLANE_TYPE_CURSOR);
12396
12397 if (INTEL_INFO(dev)->gen >= 4) {
12398 if (!dev->mode_config.rotation_property)
12399 dev->mode_config.rotation_property =
12400 drm_mode_create_rotation_property(dev,
12401 BIT(DRM_ROTATE_0) |
12402 BIT(DRM_ROTATE_180));
12403 if (dev->mode_config.rotation_property)
12404 drm_object_attach_property(&cursor->base.base,
12405 dev->mode_config.rotation_property,
12406 state->base.rotation);
12407 }
12408
12409 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12410
12411 return &cursor->base;
12412 }
12413
12414 static void intel_crtc_init(struct drm_device *dev, int pipe)
12415 {
12416 struct drm_i915_private *dev_priv = dev->dev_private;
12417 struct intel_crtc *intel_crtc;
12418 struct intel_crtc_state *crtc_state = NULL;
12419 struct drm_plane *primary = NULL;
12420 struct drm_plane *cursor = NULL;
12421 int i, ret;
12422
12423 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12424 if (intel_crtc == NULL)
12425 return;
12426
12427 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12428 if (!crtc_state)
12429 goto fail;
12430 intel_crtc_set_state(intel_crtc, crtc_state);
12431 crtc_state->base.crtc = &intel_crtc->base;
12432
12433 primary = intel_primary_plane_create(dev, pipe);
12434 if (!primary)
12435 goto fail;
12436
12437 cursor = intel_cursor_plane_create(dev, pipe);
12438 if (!cursor)
12439 goto fail;
12440
12441 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12442 cursor, &intel_crtc_funcs);
12443 if (ret)
12444 goto fail;
12445
12446 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12447 for (i = 0; i < 256; i++) {
12448 intel_crtc->lut_r[i] = i;
12449 intel_crtc->lut_g[i] = i;
12450 intel_crtc->lut_b[i] = i;
12451 }
12452
12453 /*
12454 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12455 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12456 */
12457 intel_crtc->pipe = pipe;
12458 intel_crtc->plane = pipe;
12459 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12460 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12461 intel_crtc->plane = !pipe;
12462 }
12463
12464 intel_crtc->cursor_base = ~0;
12465 intel_crtc->cursor_cntl = ~0;
12466 intel_crtc->cursor_size = ~0;
12467
12468 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12469 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12470 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12471 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12472
12473 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12474
12475 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12476
12477 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12478 return;
12479
12480 fail:
12481 if (primary)
12482 drm_plane_cleanup(primary);
12483 if (cursor)
12484 drm_plane_cleanup(cursor);
12485 kfree(crtc_state);
12486 kfree(intel_crtc);
12487 }
12488
12489 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12490 {
12491 struct drm_encoder *encoder = connector->base.encoder;
12492 struct drm_device *dev = connector->base.dev;
12493
12494 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12495
12496 if (!encoder || WARN_ON(!encoder->crtc))
12497 return INVALID_PIPE;
12498
12499 return to_intel_crtc(encoder->crtc)->pipe;
12500 }
12501
12502 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12503 struct drm_file *file)
12504 {
12505 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12506 struct drm_crtc *drmmode_crtc;
12507 struct intel_crtc *crtc;
12508
12509 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12510
12511 if (!drmmode_crtc) {
12512 DRM_ERROR("no such CRTC id\n");
12513 return -ENOENT;
12514 }
12515
12516 crtc = to_intel_crtc(drmmode_crtc);
12517 pipe_from_crtc_id->pipe = crtc->pipe;
12518
12519 return 0;
12520 }
12521
12522 static int intel_encoder_clones(struct intel_encoder *encoder)
12523 {
12524 struct drm_device *dev = encoder->base.dev;
12525 struct intel_encoder *source_encoder;
12526 int index_mask = 0;
12527 int entry = 0;
12528
12529 for_each_intel_encoder(dev, source_encoder) {
12530 if (encoders_cloneable(encoder, source_encoder))
12531 index_mask |= (1 << entry);
12532
12533 entry++;
12534 }
12535
12536 return index_mask;
12537 }
12538
12539 static bool has_edp_a(struct drm_device *dev)
12540 {
12541 struct drm_i915_private *dev_priv = dev->dev_private;
12542
12543 if (!IS_MOBILE(dev))
12544 return false;
12545
12546 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12547 return false;
12548
12549 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12550 return false;
12551
12552 return true;
12553 }
12554
12555 static bool intel_crt_present(struct drm_device *dev)
12556 {
12557 struct drm_i915_private *dev_priv = dev->dev_private;
12558
12559 if (INTEL_INFO(dev)->gen >= 9)
12560 return false;
12561
12562 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12563 return false;
12564
12565 if (IS_CHERRYVIEW(dev))
12566 return false;
12567
12568 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12569 return false;
12570
12571 return true;
12572 }
12573
12574 static void intel_setup_outputs(struct drm_device *dev)
12575 {
12576 struct drm_i915_private *dev_priv = dev->dev_private;
12577 struct intel_encoder *encoder;
12578 struct drm_connector *connector;
12579 bool dpd_is_edp = false;
12580
12581 intel_lvds_init(dev);
12582
12583 if (intel_crt_present(dev))
12584 intel_crt_init(dev);
12585
12586 if (HAS_DDI(dev)) {
12587 int found;
12588
12589 /*
12590 * Haswell uses DDI functions to detect digital outputs.
12591 * On SKL pre-D0 the strap isn't connected, so we assume
12592 * it's there.
12593 */
12594 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12595 /* WaIgnoreDDIAStrap: skl */
12596 if (found ||
12597 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12598 intel_ddi_init(dev, PORT_A);
12599
12600 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12601 * register */
12602 found = I915_READ(SFUSE_STRAP);
12603
12604 if (found & SFUSE_STRAP_DDIB_DETECTED)
12605 intel_ddi_init(dev, PORT_B);
12606 if (found & SFUSE_STRAP_DDIC_DETECTED)
12607 intel_ddi_init(dev, PORT_C);
12608 if (found & SFUSE_STRAP_DDID_DETECTED)
12609 intel_ddi_init(dev, PORT_D);
12610 } else if (HAS_PCH_SPLIT(dev)) {
12611 int found;
12612 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12613
12614 if (has_edp_a(dev))
12615 intel_dp_init(dev, DP_A, PORT_A);
12616
12617 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12618 /* PCH SDVOB multiplex with HDMIB */
12619 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12620 if (!found)
12621 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12622 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12623 intel_dp_init(dev, PCH_DP_B, PORT_B);
12624 }
12625
12626 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12627 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12628
12629 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12630 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12631
12632 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12633 intel_dp_init(dev, PCH_DP_C, PORT_C);
12634
12635 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12636 intel_dp_init(dev, PCH_DP_D, PORT_D);
12637 } else if (IS_VALLEYVIEW(dev)) {
12638 /*
12639 * The DP_DETECTED bit is the latched state of the DDC
12640 * SDA pin at boot. However since eDP doesn't require DDC
12641 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12642 * eDP ports may have been muxed to an alternate function.
12643 * Thus we can't rely on the DP_DETECTED bit alone to detect
12644 * eDP ports. Consult the VBT as well as DP_DETECTED to
12645 * detect eDP ports.
12646 */
12647 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12648 !intel_dp_is_edp(dev, PORT_B))
12649 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12650 PORT_B);
12651 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12652 intel_dp_is_edp(dev, PORT_B))
12653 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12654
12655 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12656 !intel_dp_is_edp(dev, PORT_C))
12657 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12658 PORT_C);
12659 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12660 intel_dp_is_edp(dev, PORT_C))
12661 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12662
12663 if (IS_CHERRYVIEW(dev)) {
12664 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12665 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12666 PORT_D);
12667 /* eDP not supported on port D, so don't check VBT */
12668 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12669 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12670 }
12671
12672 intel_dsi_init(dev);
12673 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12674 bool found = false;
12675
12676 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12677 DRM_DEBUG_KMS("probing SDVOB\n");
12678 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12679 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12680 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12681 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12682 }
12683
12684 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12685 intel_dp_init(dev, DP_B, PORT_B);
12686 }
12687
12688 /* Before G4X SDVOC doesn't have its own detect register */
12689
12690 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12691 DRM_DEBUG_KMS("probing SDVOC\n");
12692 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12693 }
12694
12695 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12696
12697 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12698 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12699 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12700 }
12701 if (SUPPORTS_INTEGRATED_DP(dev))
12702 intel_dp_init(dev, DP_C, PORT_C);
12703 }
12704
12705 if (SUPPORTS_INTEGRATED_DP(dev) &&
12706 (I915_READ(DP_D) & DP_DETECTED))
12707 intel_dp_init(dev, DP_D, PORT_D);
12708 } else if (IS_GEN2(dev))
12709 intel_dvo_init(dev);
12710
12711 if (SUPPORTS_TV(dev))
12712 intel_tv_init(dev);
12713
12714 /*
12715 * FIXME: We don't have full atomic support yet, but we want to be
12716 * able to enable/test plane updates via the atomic interface in the
12717 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12718 * will take some atomic codepaths to lookup properties during
12719 * drmModeGetConnector() that unconditionally dereference
12720 * connector->state.
12721 *
12722 * We create a dummy connector state here for each connector to ensure
12723 * the DRM core doesn't try to dereference a NULL connector->state.
12724 * The actual connector properties will never be updated or contain
12725 * useful information, but since we're doing this specifically for
12726 * testing/debug of the plane operations (and only when a specific
12727 * kernel module option is given), that shouldn't really matter.
12728 *
12729 * Once atomic support for crtc's + connectors lands, this loop should
12730 * be removed since we'll be setting up real connector state, which
12731 * will contain Intel-specific properties.
12732 */
12733 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12734 list_for_each_entry(connector,
12735 &dev->mode_config.connector_list,
12736 head) {
12737 if (!WARN_ON(connector->state)) {
12738 connector->state =
12739 kzalloc(sizeof(*connector->state),
12740 GFP_KERNEL);
12741 }
12742 }
12743 }
12744
12745 intel_psr_init(dev);
12746
12747 for_each_intel_encoder(dev, encoder) {
12748 encoder->base.possible_crtcs = encoder->crtc_mask;
12749 encoder->base.possible_clones =
12750 intel_encoder_clones(encoder);
12751 }
12752
12753 intel_init_pch_refclk(dev);
12754
12755 drm_helper_move_panel_connectors_to_head(dev);
12756 }
12757
12758 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12759 {
12760 struct drm_device *dev = fb->dev;
12761 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12762
12763 drm_framebuffer_cleanup(fb);
12764 mutex_lock(&dev->struct_mutex);
12765 WARN_ON(!intel_fb->obj->framebuffer_references--);
12766 drm_gem_object_unreference(&intel_fb->obj->base);
12767 mutex_unlock(&dev->struct_mutex);
12768 kfree(intel_fb);
12769 }
12770
12771 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12772 struct drm_file *file,
12773 unsigned int *handle)
12774 {
12775 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12776 struct drm_i915_gem_object *obj = intel_fb->obj;
12777
12778 return drm_gem_handle_create(file, &obj->base, handle);
12779 }
12780
12781 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12782 .destroy = intel_user_framebuffer_destroy,
12783 .create_handle = intel_user_framebuffer_create_handle,
12784 };
12785
12786 static
12787 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12788 uint32_t pixel_format)
12789 {
12790 u32 gen = INTEL_INFO(dev)->gen;
12791
12792 if (gen >= 9) {
12793 /* "The stride in bytes must not exceed the of the size of 8K
12794 * pixels and 32K bytes."
12795 */
12796 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12797 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12798 return 32*1024;
12799 } else if (gen >= 4) {
12800 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12801 return 16*1024;
12802 else
12803 return 32*1024;
12804 } else if (gen >= 3) {
12805 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12806 return 8*1024;
12807 else
12808 return 16*1024;
12809 } else {
12810 /* XXX DSPC is limited to 4k tiled */
12811 return 8*1024;
12812 }
12813 }
12814
12815 static int intel_framebuffer_init(struct drm_device *dev,
12816 struct intel_framebuffer *intel_fb,
12817 struct drm_mode_fb_cmd2 *mode_cmd,
12818 struct drm_i915_gem_object *obj)
12819 {
12820 int aligned_height;
12821 int ret;
12822 u32 pitch_limit, stride_alignment;
12823
12824 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12825
12826 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12827 /* Enforce that fb modifier and tiling mode match, but only for
12828 * X-tiled. This is needed for FBC. */
12829 if (!!(obj->tiling_mode == I915_TILING_X) !=
12830 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12831 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12832 return -EINVAL;
12833 }
12834 } else {
12835 if (obj->tiling_mode == I915_TILING_X)
12836 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12837 else if (obj->tiling_mode == I915_TILING_Y) {
12838 DRM_DEBUG("No Y tiling for legacy addfb\n");
12839 return -EINVAL;
12840 }
12841 }
12842
12843 /* Passed in modifier sanity checking. */
12844 switch (mode_cmd->modifier[0]) {
12845 case I915_FORMAT_MOD_Y_TILED:
12846 case I915_FORMAT_MOD_Yf_TILED:
12847 if (INTEL_INFO(dev)->gen < 9) {
12848 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12849 mode_cmd->modifier[0]);
12850 return -EINVAL;
12851 }
12852 case DRM_FORMAT_MOD_NONE:
12853 case I915_FORMAT_MOD_X_TILED:
12854 break;
12855 default:
12856 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12857 mode_cmd->modifier[0]);
12858 return -EINVAL;
12859 }
12860
12861 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12862 mode_cmd->pixel_format);
12863 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12864 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12865 mode_cmd->pitches[0], stride_alignment);
12866 return -EINVAL;
12867 }
12868
12869 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12870 mode_cmd->pixel_format);
12871 if (mode_cmd->pitches[0] > pitch_limit) {
12872 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12873 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12874 "tiled" : "linear",
12875 mode_cmd->pitches[0], pitch_limit);
12876 return -EINVAL;
12877 }
12878
12879 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12880 mode_cmd->pitches[0] != obj->stride) {
12881 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12882 mode_cmd->pitches[0], obj->stride);
12883 return -EINVAL;
12884 }
12885
12886 /* Reject formats not supported by any plane early. */
12887 switch (mode_cmd->pixel_format) {
12888 case DRM_FORMAT_C8:
12889 case DRM_FORMAT_RGB565:
12890 case DRM_FORMAT_XRGB8888:
12891 case DRM_FORMAT_ARGB8888:
12892 break;
12893 case DRM_FORMAT_XRGB1555:
12894 case DRM_FORMAT_ARGB1555:
12895 if (INTEL_INFO(dev)->gen > 3) {
12896 DRM_DEBUG("unsupported pixel format: %s\n",
12897 drm_get_format_name(mode_cmd->pixel_format));
12898 return -EINVAL;
12899 }
12900 break;
12901 case DRM_FORMAT_XBGR8888:
12902 case DRM_FORMAT_ABGR8888:
12903 case DRM_FORMAT_XRGB2101010:
12904 case DRM_FORMAT_ARGB2101010:
12905 case DRM_FORMAT_XBGR2101010:
12906 case DRM_FORMAT_ABGR2101010:
12907 if (INTEL_INFO(dev)->gen < 4) {
12908 DRM_DEBUG("unsupported pixel format: %s\n",
12909 drm_get_format_name(mode_cmd->pixel_format));
12910 return -EINVAL;
12911 }
12912 break;
12913 case DRM_FORMAT_YUYV:
12914 case DRM_FORMAT_UYVY:
12915 case DRM_FORMAT_YVYU:
12916 case DRM_FORMAT_VYUY:
12917 if (INTEL_INFO(dev)->gen < 5) {
12918 DRM_DEBUG("unsupported pixel format: %s\n",
12919 drm_get_format_name(mode_cmd->pixel_format));
12920 return -EINVAL;
12921 }
12922 break;
12923 default:
12924 DRM_DEBUG("unsupported pixel format: %s\n",
12925 drm_get_format_name(mode_cmd->pixel_format));
12926 return -EINVAL;
12927 }
12928
12929 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12930 if (mode_cmd->offsets[0] != 0)
12931 return -EINVAL;
12932
12933 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12934 mode_cmd->pixel_format,
12935 mode_cmd->modifier[0]);
12936 /* FIXME drm helper for size checks (especially planar formats)? */
12937 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12938 return -EINVAL;
12939
12940 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12941 intel_fb->obj = obj;
12942 intel_fb->obj->framebuffer_references++;
12943
12944 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12945 if (ret) {
12946 DRM_ERROR("framebuffer init failed %d\n", ret);
12947 return ret;
12948 }
12949
12950 return 0;
12951 }
12952
12953 static struct drm_framebuffer *
12954 intel_user_framebuffer_create(struct drm_device *dev,
12955 struct drm_file *filp,
12956 struct drm_mode_fb_cmd2 *mode_cmd)
12957 {
12958 struct drm_i915_gem_object *obj;
12959
12960 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12961 mode_cmd->handles[0]));
12962 if (&obj->base == NULL)
12963 return ERR_PTR(-ENOENT);
12964
12965 return intel_framebuffer_create(dev, mode_cmd, obj);
12966 }
12967
12968 #ifndef CONFIG_DRM_I915_FBDEV
12969 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12970 {
12971 }
12972 #endif
12973
12974 static const struct drm_mode_config_funcs intel_mode_funcs = {
12975 .fb_create = intel_user_framebuffer_create,
12976 .output_poll_changed = intel_fbdev_output_poll_changed,
12977 .atomic_check = intel_atomic_check,
12978 .atomic_commit = intel_atomic_commit,
12979 };
12980
12981 /* Set up chip specific display functions */
12982 static void intel_init_display(struct drm_device *dev)
12983 {
12984 struct drm_i915_private *dev_priv = dev->dev_private;
12985
12986 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12987 dev_priv->display.find_dpll = g4x_find_best_dpll;
12988 else if (IS_CHERRYVIEW(dev))
12989 dev_priv->display.find_dpll = chv_find_best_dpll;
12990 else if (IS_VALLEYVIEW(dev))
12991 dev_priv->display.find_dpll = vlv_find_best_dpll;
12992 else if (IS_PINEVIEW(dev))
12993 dev_priv->display.find_dpll = pnv_find_best_dpll;
12994 else
12995 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12996
12997 if (INTEL_INFO(dev)->gen >= 9) {
12998 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12999 dev_priv->display.get_initial_plane_config =
13000 skylake_get_initial_plane_config;
13001 dev_priv->display.crtc_compute_clock =
13002 haswell_crtc_compute_clock;
13003 dev_priv->display.crtc_enable = haswell_crtc_enable;
13004 dev_priv->display.crtc_disable = haswell_crtc_disable;
13005 dev_priv->display.off = ironlake_crtc_off;
13006 dev_priv->display.update_primary_plane =
13007 skylake_update_primary_plane;
13008 } else if (HAS_DDI(dev)) {
13009 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13010 dev_priv->display.get_initial_plane_config =
13011 ironlake_get_initial_plane_config;
13012 dev_priv->display.crtc_compute_clock =
13013 haswell_crtc_compute_clock;
13014 dev_priv->display.crtc_enable = haswell_crtc_enable;
13015 dev_priv->display.crtc_disable = haswell_crtc_disable;
13016 dev_priv->display.off = ironlake_crtc_off;
13017 dev_priv->display.update_primary_plane =
13018 ironlake_update_primary_plane;
13019 } else if (HAS_PCH_SPLIT(dev)) {
13020 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13021 dev_priv->display.get_initial_plane_config =
13022 ironlake_get_initial_plane_config;
13023 dev_priv->display.crtc_compute_clock =
13024 ironlake_crtc_compute_clock;
13025 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13026 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13027 dev_priv->display.off = ironlake_crtc_off;
13028 dev_priv->display.update_primary_plane =
13029 ironlake_update_primary_plane;
13030 } else if (IS_VALLEYVIEW(dev)) {
13031 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13032 dev_priv->display.get_initial_plane_config =
13033 i9xx_get_initial_plane_config;
13034 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13035 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13036 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13037 dev_priv->display.off = i9xx_crtc_off;
13038 dev_priv->display.update_primary_plane =
13039 i9xx_update_primary_plane;
13040 } else {
13041 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13042 dev_priv->display.get_initial_plane_config =
13043 i9xx_get_initial_plane_config;
13044 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13045 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13046 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13047 dev_priv->display.off = i9xx_crtc_off;
13048 dev_priv->display.update_primary_plane =
13049 i9xx_update_primary_plane;
13050 }
13051
13052 /* Returns the core display clock speed */
13053 if (IS_VALLEYVIEW(dev))
13054 dev_priv->display.get_display_clock_speed =
13055 valleyview_get_display_clock_speed;
13056 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13057 dev_priv->display.get_display_clock_speed =
13058 i945_get_display_clock_speed;
13059 else if (IS_I915G(dev))
13060 dev_priv->display.get_display_clock_speed =
13061 i915_get_display_clock_speed;
13062 else if (IS_I945GM(dev) || IS_845G(dev))
13063 dev_priv->display.get_display_clock_speed =
13064 i9xx_misc_get_display_clock_speed;
13065 else if (IS_PINEVIEW(dev))
13066 dev_priv->display.get_display_clock_speed =
13067 pnv_get_display_clock_speed;
13068 else if (IS_I915GM(dev))
13069 dev_priv->display.get_display_clock_speed =
13070 i915gm_get_display_clock_speed;
13071 else if (IS_I865G(dev))
13072 dev_priv->display.get_display_clock_speed =
13073 i865_get_display_clock_speed;
13074 else if (IS_I85X(dev))
13075 dev_priv->display.get_display_clock_speed =
13076 i855_get_display_clock_speed;
13077 else /* 852, 830 */
13078 dev_priv->display.get_display_clock_speed =
13079 i830_get_display_clock_speed;
13080
13081 if (IS_GEN5(dev)) {
13082 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13083 } else if (IS_GEN6(dev)) {
13084 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13085 } else if (IS_IVYBRIDGE(dev)) {
13086 /* FIXME: detect B0+ stepping and use auto training */
13087 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13088 dev_priv->display.modeset_global_resources =
13089 ivb_modeset_global_resources;
13090 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13091 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13092 } else if (IS_VALLEYVIEW(dev)) {
13093 dev_priv->display.modeset_global_resources =
13094 valleyview_modeset_global_resources;
13095 }
13096
13097 switch (INTEL_INFO(dev)->gen) {
13098 case 2:
13099 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13100 break;
13101
13102 case 3:
13103 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13104 break;
13105
13106 case 4:
13107 case 5:
13108 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13109 break;
13110
13111 case 6:
13112 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13113 break;
13114 case 7:
13115 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13116 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13117 break;
13118 case 9:
13119 /* Drop through - unsupported since execlist only. */
13120 default:
13121 /* Default just returns -ENODEV to indicate unsupported */
13122 dev_priv->display.queue_flip = intel_default_queue_flip;
13123 }
13124
13125 intel_panel_init_backlight_funcs(dev);
13126
13127 mutex_init(&dev_priv->pps_mutex);
13128 }
13129
13130 /*
13131 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13132 * resume, or other times. This quirk makes sure that's the case for
13133 * affected systems.
13134 */
13135 static void quirk_pipea_force(struct drm_device *dev)
13136 {
13137 struct drm_i915_private *dev_priv = dev->dev_private;
13138
13139 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13140 DRM_INFO("applying pipe a force quirk\n");
13141 }
13142
13143 static void quirk_pipeb_force(struct drm_device *dev)
13144 {
13145 struct drm_i915_private *dev_priv = dev->dev_private;
13146
13147 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13148 DRM_INFO("applying pipe b force quirk\n");
13149 }
13150
13151 /*
13152 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13153 */
13154 static void quirk_ssc_force_disable(struct drm_device *dev)
13155 {
13156 struct drm_i915_private *dev_priv = dev->dev_private;
13157 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13158 DRM_INFO("applying lvds SSC disable quirk\n");
13159 }
13160
13161 /*
13162 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13163 * brightness value
13164 */
13165 static void quirk_invert_brightness(struct drm_device *dev)
13166 {
13167 struct drm_i915_private *dev_priv = dev->dev_private;
13168 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13169 DRM_INFO("applying inverted panel brightness quirk\n");
13170 }
13171
13172 /* Some VBT's incorrectly indicate no backlight is present */
13173 static void quirk_backlight_present(struct drm_device *dev)
13174 {
13175 struct drm_i915_private *dev_priv = dev->dev_private;
13176 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13177 DRM_INFO("applying backlight present quirk\n");
13178 }
13179
13180 struct intel_quirk {
13181 int device;
13182 int subsystem_vendor;
13183 int subsystem_device;
13184 void (*hook)(struct drm_device *dev);
13185 };
13186
13187 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13188 struct intel_dmi_quirk {
13189 void (*hook)(struct drm_device *dev);
13190 const struct dmi_system_id (*dmi_id_list)[];
13191 };
13192
13193 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13194 {
13195 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13196 return 1;
13197 }
13198
13199 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13200 {
13201 .dmi_id_list = &(const struct dmi_system_id[]) {
13202 {
13203 .callback = intel_dmi_reverse_brightness,
13204 .ident = "NCR Corporation",
13205 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13206 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13207 },
13208 },
13209 { } /* terminating entry */
13210 },
13211 .hook = quirk_invert_brightness,
13212 },
13213 };
13214
13215 static struct intel_quirk intel_quirks[] = {
13216 /* HP Mini needs pipe A force quirk (LP: #322104) */
13217 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13218
13219 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13220 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13221
13222 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13223 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13224
13225 /* 830 needs to leave pipe A & dpll A up */
13226 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13227
13228 /* 830 needs to leave pipe B & dpll B up */
13229 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13230
13231 /* Lenovo U160 cannot use SSC on LVDS */
13232 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13233
13234 /* Sony Vaio Y cannot use SSC on LVDS */
13235 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13236
13237 /* Acer Aspire 5734Z must invert backlight brightness */
13238 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13239
13240 /* Acer/eMachines G725 */
13241 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13242
13243 /* Acer/eMachines e725 */
13244 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13245
13246 /* Acer/Packard Bell NCL20 */
13247 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13248
13249 /* Acer Aspire 4736Z */
13250 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13251
13252 /* Acer Aspire 5336 */
13253 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13254
13255 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13256 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13257
13258 /* Acer C720 Chromebook (Core i3 4005U) */
13259 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13260
13261 /* Apple Macbook 2,1 (Core 2 T7400) */
13262 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13263
13264 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13265 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13266
13267 /* HP Chromebook 14 (Celeron 2955U) */
13268 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13269
13270 /* Dell Chromebook 11 */
13271 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13272 };
13273
13274 static void intel_init_quirks(struct drm_device *dev)
13275 {
13276 struct pci_dev *d = dev->pdev;
13277 int i;
13278
13279 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13280 struct intel_quirk *q = &intel_quirks[i];
13281
13282 if (d->device == q->device &&
13283 (d->subsystem_vendor == q->subsystem_vendor ||
13284 q->subsystem_vendor == PCI_ANY_ID) &&
13285 (d->subsystem_device == q->subsystem_device ||
13286 q->subsystem_device == PCI_ANY_ID))
13287 q->hook(dev);
13288 }
13289 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13290 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13291 intel_dmi_quirks[i].hook(dev);
13292 }
13293 }
13294
13295 /* Disable the VGA plane that we never use */
13296 static void i915_disable_vga(struct drm_device *dev)
13297 {
13298 struct drm_i915_private *dev_priv = dev->dev_private;
13299 u8 sr1;
13300 u32 vga_reg = i915_vgacntrl_reg(dev);
13301
13302 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13303 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13304 outb(SR01, VGA_SR_INDEX);
13305 sr1 = inb(VGA_SR_DATA);
13306 outb(sr1 | 1<<5, VGA_SR_DATA);
13307 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13308 udelay(300);
13309
13310 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13311 POSTING_READ(vga_reg);
13312 }
13313
13314 void intel_modeset_init_hw(struct drm_device *dev)
13315 {
13316 intel_prepare_ddi(dev);
13317
13318 if (IS_VALLEYVIEW(dev))
13319 vlv_update_cdclk(dev);
13320
13321 intel_init_clock_gating(dev);
13322
13323 intel_enable_gt_powersave(dev);
13324 }
13325
13326 void intel_modeset_init(struct drm_device *dev)
13327 {
13328 struct drm_i915_private *dev_priv = dev->dev_private;
13329 int sprite, ret;
13330 enum pipe pipe;
13331 struct intel_crtc *crtc;
13332
13333 drm_mode_config_init(dev);
13334
13335 dev->mode_config.min_width = 0;
13336 dev->mode_config.min_height = 0;
13337
13338 dev->mode_config.preferred_depth = 24;
13339 dev->mode_config.prefer_shadow = 1;
13340
13341 dev->mode_config.allow_fb_modifiers = true;
13342
13343 dev->mode_config.funcs = &intel_mode_funcs;
13344
13345 intel_init_quirks(dev);
13346
13347 intel_init_pm(dev);
13348
13349 if (INTEL_INFO(dev)->num_pipes == 0)
13350 return;
13351
13352 intel_init_display(dev);
13353 intel_init_audio(dev);
13354
13355 if (IS_GEN2(dev)) {
13356 dev->mode_config.max_width = 2048;
13357 dev->mode_config.max_height = 2048;
13358 } else if (IS_GEN3(dev)) {
13359 dev->mode_config.max_width = 4096;
13360 dev->mode_config.max_height = 4096;
13361 } else {
13362 dev->mode_config.max_width = 8192;
13363 dev->mode_config.max_height = 8192;
13364 }
13365
13366 if (IS_845G(dev) || IS_I865G(dev)) {
13367 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13368 dev->mode_config.cursor_height = 1023;
13369 } else if (IS_GEN2(dev)) {
13370 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13371 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13372 } else {
13373 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13374 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13375 }
13376
13377 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13378
13379 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13380 INTEL_INFO(dev)->num_pipes,
13381 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13382
13383 for_each_pipe(dev_priv, pipe) {
13384 intel_crtc_init(dev, pipe);
13385 for_each_sprite(dev_priv, pipe, sprite) {
13386 ret = intel_plane_init(dev, pipe, sprite);
13387 if (ret)
13388 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13389 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13390 }
13391 }
13392
13393 intel_init_dpio(dev);
13394
13395 intel_shared_dpll_init(dev);
13396
13397 /* Just disable it once at startup */
13398 i915_disable_vga(dev);
13399 intel_setup_outputs(dev);
13400
13401 /* Just in case the BIOS is doing something questionable. */
13402 intel_fbc_disable(dev);
13403
13404 drm_modeset_lock_all(dev);
13405 intel_modeset_setup_hw_state(dev, false);
13406 drm_modeset_unlock_all(dev);
13407
13408 for_each_intel_crtc(dev, crtc) {
13409 if (!crtc->active)
13410 continue;
13411
13412 /*
13413 * Note that reserving the BIOS fb up front prevents us
13414 * from stuffing other stolen allocations like the ring
13415 * on top. This prevents some ugliness at boot time, and
13416 * can even allow for smooth boot transitions if the BIOS
13417 * fb is large enough for the active pipe configuration.
13418 */
13419 if (dev_priv->display.get_initial_plane_config) {
13420 dev_priv->display.get_initial_plane_config(crtc,
13421 &crtc->plane_config);
13422 /*
13423 * If the fb is shared between multiple heads, we'll
13424 * just get the first one.
13425 */
13426 intel_find_plane_obj(crtc, &crtc->plane_config);
13427 }
13428 }
13429 }
13430
13431 static void intel_enable_pipe_a(struct drm_device *dev)
13432 {
13433 struct intel_connector *connector;
13434 struct drm_connector *crt = NULL;
13435 struct intel_load_detect_pipe load_detect_temp;
13436 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13437
13438 /* We can't just switch on the pipe A, we need to set things up with a
13439 * proper mode and output configuration. As a gross hack, enable pipe A
13440 * by enabling the load detect pipe once. */
13441 for_each_intel_connector(dev, connector) {
13442 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13443 crt = &connector->base;
13444 break;
13445 }
13446 }
13447
13448 if (!crt)
13449 return;
13450
13451 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13452 intel_release_load_detect_pipe(crt, &load_detect_temp);
13453 }
13454
13455 static bool
13456 intel_check_plane_mapping(struct intel_crtc *crtc)
13457 {
13458 struct drm_device *dev = crtc->base.dev;
13459 struct drm_i915_private *dev_priv = dev->dev_private;
13460 u32 reg, val;
13461
13462 if (INTEL_INFO(dev)->num_pipes == 1)
13463 return true;
13464
13465 reg = DSPCNTR(!crtc->plane);
13466 val = I915_READ(reg);
13467
13468 if ((val & DISPLAY_PLANE_ENABLE) &&
13469 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13470 return false;
13471
13472 return true;
13473 }
13474
13475 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13476 {
13477 struct drm_device *dev = crtc->base.dev;
13478 struct drm_i915_private *dev_priv = dev->dev_private;
13479 u32 reg;
13480
13481 /* Clear any frame start delays used for debugging left by the BIOS */
13482 reg = PIPECONF(crtc->config->cpu_transcoder);
13483 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13484
13485 /* restore vblank interrupts to correct state */
13486 drm_crtc_vblank_reset(&crtc->base);
13487 if (crtc->active) {
13488 update_scanline_offset(crtc);
13489 drm_crtc_vblank_on(&crtc->base);
13490 }
13491
13492 /* We need to sanitize the plane -> pipe mapping first because this will
13493 * disable the crtc (and hence change the state) if it is wrong. Note
13494 * that gen4+ has a fixed plane -> pipe mapping. */
13495 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13496 struct intel_connector *connector;
13497 bool plane;
13498
13499 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13500 crtc->base.base.id);
13501
13502 /* Pipe has the wrong plane attached and the plane is active.
13503 * Temporarily change the plane mapping and disable everything
13504 * ... */
13505 plane = crtc->plane;
13506 crtc->plane = !plane;
13507 crtc->primary_enabled = true;
13508 dev_priv->display.crtc_disable(&crtc->base);
13509 crtc->plane = plane;
13510
13511 /* ... and break all links. */
13512 for_each_intel_connector(dev, connector) {
13513 if (connector->encoder->base.crtc != &crtc->base)
13514 continue;
13515
13516 connector->base.dpms = DRM_MODE_DPMS_OFF;
13517 connector->base.encoder = NULL;
13518 }
13519 /* multiple connectors may have the same encoder:
13520 * handle them and break crtc link separately */
13521 for_each_intel_connector(dev, connector)
13522 if (connector->encoder->base.crtc == &crtc->base) {
13523 connector->encoder->base.crtc = NULL;
13524 connector->encoder->connectors_active = false;
13525 }
13526
13527 WARN_ON(crtc->active);
13528 crtc->base.state->enable = false;
13529 crtc->base.enabled = false;
13530 }
13531
13532 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13533 crtc->pipe == PIPE_A && !crtc->active) {
13534 /* BIOS forgot to enable pipe A, this mostly happens after
13535 * resume. Force-enable the pipe to fix this, the update_dpms
13536 * call below we restore the pipe to the right state, but leave
13537 * the required bits on. */
13538 intel_enable_pipe_a(dev);
13539 }
13540
13541 /* Adjust the state of the output pipe according to whether we
13542 * have active connectors/encoders. */
13543 intel_crtc_update_dpms(&crtc->base);
13544
13545 if (crtc->active != crtc->base.state->enable) {
13546 struct intel_encoder *encoder;
13547
13548 /* This can happen either due to bugs in the get_hw_state
13549 * functions or because the pipe is force-enabled due to the
13550 * pipe A quirk. */
13551 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13552 crtc->base.base.id,
13553 crtc->base.state->enable ? "enabled" : "disabled",
13554 crtc->active ? "enabled" : "disabled");
13555
13556 crtc->base.state->enable = crtc->active;
13557 crtc->base.enabled = crtc->active;
13558
13559 /* Because we only establish the connector -> encoder ->
13560 * crtc links if something is active, this means the
13561 * crtc is now deactivated. Break the links. connector
13562 * -> encoder links are only establish when things are
13563 * actually up, hence no need to break them. */
13564 WARN_ON(crtc->active);
13565
13566 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13567 WARN_ON(encoder->connectors_active);
13568 encoder->base.crtc = NULL;
13569 }
13570 }
13571
13572 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13573 /*
13574 * We start out with underrun reporting disabled to avoid races.
13575 * For correct bookkeeping mark this on active crtcs.
13576 *
13577 * Also on gmch platforms we dont have any hardware bits to
13578 * disable the underrun reporting. Which means we need to start
13579 * out with underrun reporting disabled also on inactive pipes,
13580 * since otherwise we'll complain about the garbage we read when
13581 * e.g. coming up after runtime pm.
13582 *
13583 * No protection against concurrent access is required - at
13584 * worst a fifo underrun happens which also sets this to false.
13585 */
13586 crtc->cpu_fifo_underrun_disabled = true;
13587 crtc->pch_fifo_underrun_disabled = true;
13588 }
13589 }
13590
13591 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13592 {
13593 struct intel_connector *connector;
13594 struct drm_device *dev = encoder->base.dev;
13595
13596 /* We need to check both for a crtc link (meaning that the
13597 * encoder is active and trying to read from a pipe) and the
13598 * pipe itself being active. */
13599 bool has_active_crtc = encoder->base.crtc &&
13600 to_intel_crtc(encoder->base.crtc)->active;
13601
13602 if (encoder->connectors_active && !has_active_crtc) {
13603 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13604 encoder->base.base.id,
13605 encoder->base.name);
13606
13607 /* Connector is active, but has no active pipe. This is
13608 * fallout from our resume register restoring. Disable
13609 * the encoder manually again. */
13610 if (encoder->base.crtc) {
13611 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13612 encoder->base.base.id,
13613 encoder->base.name);
13614 encoder->disable(encoder);
13615 if (encoder->post_disable)
13616 encoder->post_disable(encoder);
13617 }
13618 encoder->base.crtc = NULL;
13619 encoder->connectors_active = false;
13620
13621 /* Inconsistent output/port/pipe state happens presumably due to
13622 * a bug in one of the get_hw_state functions. Or someplace else
13623 * in our code, like the register restore mess on resume. Clamp
13624 * things to off as a safer default. */
13625 for_each_intel_connector(dev, connector) {
13626 if (connector->encoder != encoder)
13627 continue;
13628 connector->base.dpms = DRM_MODE_DPMS_OFF;
13629 connector->base.encoder = NULL;
13630 }
13631 }
13632 /* Enabled encoders without active connectors will be fixed in
13633 * the crtc fixup. */
13634 }
13635
13636 void i915_redisable_vga_power_on(struct drm_device *dev)
13637 {
13638 struct drm_i915_private *dev_priv = dev->dev_private;
13639 u32 vga_reg = i915_vgacntrl_reg(dev);
13640
13641 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13642 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13643 i915_disable_vga(dev);
13644 }
13645 }
13646
13647 void i915_redisable_vga(struct drm_device *dev)
13648 {
13649 struct drm_i915_private *dev_priv = dev->dev_private;
13650
13651 /* This function can be called both from intel_modeset_setup_hw_state or
13652 * at a very early point in our resume sequence, where the power well
13653 * structures are not yet restored. Since this function is at a very
13654 * paranoid "someone might have enabled VGA while we were not looking"
13655 * level, just check if the power well is enabled instead of trying to
13656 * follow the "don't touch the power well if we don't need it" policy
13657 * the rest of the driver uses. */
13658 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13659 return;
13660
13661 i915_redisable_vga_power_on(dev);
13662 }
13663
13664 static bool primary_get_hw_state(struct intel_crtc *crtc)
13665 {
13666 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13667
13668 if (!crtc->active)
13669 return false;
13670
13671 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13672 }
13673
13674 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13675 {
13676 struct drm_i915_private *dev_priv = dev->dev_private;
13677 enum pipe pipe;
13678 struct intel_crtc *crtc;
13679 struct intel_encoder *encoder;
13680 struct intel_connector *connector;
13681 int i;
13682
13683 for_each_intel_crtc(dev, crtc) {
13684 memset(crtc->config, 0, sizeof(*crtc->config));
13685
13686 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13687
13688 crtc->active = dev_priv->display.get_pipe_config(crtc,
13689 crtc->config);
13690
13691 crtc->base.state->enable = crtc->active;
13692 crtc->base.enabled = crtc->active;
13693 crtc->primary_enabled = primary_get_hw_state(crtc);
13694
13695 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13696 crtc->base.base.id,
13697 crtc->active ? "enabled" : "disabled");
13698 }
13699
13700 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13701 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13702
13703 pll->on = pll->get_hw_state(dev_priv, pll,
13704 &pll->config.hw_state);
13705 pll->active = 0;
13706 pll->config.crtc_mask = 0;
13707 for_each_intel_crtc(dev, crtc) {
13708 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13709 pll->active++;
13710 pll->config.crtc_mask |= 1 << crtc->pipe;
13711 }
13712 }
13713
13714 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13715 pll->name, pll->config.crtc_mask, pll->on);
13716
13717 if (pll->config.crtc_mask)
13718 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13719 }
13720
13721 for_each_intel_encoder(dev, encoder) {
13722 pipe = 0;
13723
13724 if (encoder->get_hw_state(encoder, &pipe)) {
13725 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13726 encoder->base.crtc = &crtc->base;
13727 encoder->get_config(encoder, crtc->config);
13728 } else {
13729 encoder->base.crtc = NULL;
13730 }
13731
13732 encoder->connectors_active = false;
13733 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13734 encoder->base.base.id,
13735 encoder->base.name,
13736 encoder->base.crtc ? "enabled" : "disabled",
13737 pipe_name(pipe));
13738 }
13739
13740 for_each_intel_connector(dev, connector) {
13741 if (connector->get_hw_state(connector)) {
13742 connector->base.dpms = DRM_MODE_DPMS_ON;
13743 connector->encoder->connectors_active = true;
13744 connector->base.encoder = &connector->encoder->base;
13745 } else {
13746 connector->base.dpms = DRM_MODE_DPMS_OFF;
13747 connector->base.encoder = NULL;
13748 }
13749 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13750 connector->base.base.id,
13751 connector->base.name,
13752 connector->base.encoder ? "enabled" : "disabled");
13753 }
13754 }
13755
13756 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13757 * and i915 state tracking structures. */
13758 void intel_modeset_setup_hw_state(struct drm_device *dev,
13759 bool force_restore)
13760 {
13761 struct drm_i915_private *dev_priv = dev->dev_private;
13762 enum pipe pipe;
13763 struct intel_crtc *crtc;
13764 struct intel_encoder *encoder;
13765 int i;
13766
13767 intel_modeset_readout_hw_state(dev);
13768
13769 /*
13770 * Now that we have the config, copy it to each CRTC struct
13771 * Note that this could go away if we move to using crtc_config
13772 * checking everywhere.
13773 */
13774 for_each_intel_crtc(dev, crtc) {
13775 if (crtc->active && i915.fastboot) {
13776 intel_mode_from_pipe_config(&crtc->base.mode,
13777 crtc->config);
13778 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13779 crtc->base.base.id);
13780 drm_mode_debug_printmodeline(&crtc->base.mode);
13781 }
13782 }
13783
13784 /* HW state is read out, now we need to sanitize this mess. */
13785 for_each_intel_encoder(dev, encoder) {
13786 intel_sanitize_encoder(encoder);
13787 }
13788
13789 for_each_pipe(dev_priv, pipe) {
13790 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13791 intel_sanitize_crtc(crtc);
13792 intel_dump_pipe_config(crtc, crtc->config,
13793 "[setup_hw_state]");
13794 }
13795
13796 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13797 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13798
13799 if (!pll->on || pll->active)
13800 continue;
13801
13802 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13803
13804 pll->disable(dev_priv, pll);
13805 pll->on = false;
13806 }
13807
13808 if (IS_GEN9(dev))
13809 skl_wm_get_hw_state(dev);
13810 else if (HAS_PCH_SPLIT(dev))
13811 ilk_wm_get_hw_state(dev);
13812
13813 if (force_restore) {
13814 i915_redisable_vga(dev);
13815
13816 /*
13817 * We need to use raw interfaces for restoring state to avoid
13818 * checking (bogus) intermediate states.
13819 */
13820 for_each_pipe(dev_priv, pipe) {
13821 struct drm_crtc *crtc =
13822 dev_priv->pipe_to_crtc_mapping[pipe];
13823
13824 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13825 crtc->primary->fb);
13826 }
13827 } else {
13828 intel_modeset_update_staged_output_state(dev);
13829 }
13830
13831 intel_modeset_check_state(dev);
13832 }
13833
13834 void intel_modeset_gem_init(struct drm_device *dev)
13835 {
13836 struct drm_i915_private *dev_priv = dev->dev_private;
13837 struct drm_crtc *c;
13838 struct drm_i915_gem_object *obj;
13839
13840 mutex_lock(&dev->struct_mutex);
13841 intel_init_gt_powersave(dev);
13842 mutex_unlock(&dev->struct_mutex);
13843
13844 /*
13845 * There may be no VBT; and if the BIOS enabled SSC we can
13846 * just keep using it to avoid unnecessary flicker. Whereas if the
13847 * BIOS isn't using it, don't assume it will work even if the VBT
13848 * indicates as much.
13849 */
13850 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13851 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13852 DREF_SSC1_ENABLE);
13853
13854 intel_modeset_init_hw(dev);
13855
13856 intel_setup_overlay(dev);
13857
13858 /*
13859 * Make sure any fbs we allocated at startup are properly
13860 * pinned & fenced. When we do the allocation it's too early
13861 * for this.
13862 */
13863 mutex_lock(&dev->struct_mutex);
13864 for_each_crtc(dev, c) {
13865 obj = intel_fb_obj(c->primary->fb);
13866 if (obj == NULL)
13867 continue;
13868
13869 if (intel_pin_and_fence_fb_obj(c->primary,
13870 c->primary->fb,
13871 NULL)) {
13872 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13873 to_intel_crtc(c)->pipe);
13874 drm_framebuffer_unreference(c->primary->fb);
13875 c->primary->fb = NULL;
13876 update_state_fb(c->primary);
13877 }
13878 }
13879 mutex_unlock(&dev->struct_mutex);
13880
13881 intel_backlight_register(dev);
13882 }
13883
13884 void intel_connector_unregister(struct intel_connector *intel_connector)
13885 {
13886 struct drm_connector *connector = &intel_connector->base;
13887
13888 intel_panel_destroy_backlight(connector);
13889 drm_connector_unregister(connector);
13890 }
13891
13892 void intel_modeset_cleanup(struct drm_device *dev)
13893 {
13894 struct drm_i915_private *dev_priv = dev->dev_private;
13895 struct drm_connector *connector;
13896
13897 intel_disable_gt_powersave(dev);
13898
13899 intel_backlight_unregister(dev);
13900
13901 /*
13902 * Interrupts and polling as the first thing to avoid creating havoc.
13903 * Too much stuff here (turning of connectors, ...) would
13904 * experience fancy races otherwise.
13905 */
13906 intel_irq_uninstall(dev_priv);
13907
13908 /*
13909 * Due to the hpd irq storm handling the hotplug work can re-arm the
13910 * poll handlers. Hence disable polling after hpd handling is shut down.
13911 */
13912 drm_kms_helper_poll_fini(dev);
13913
13914 mutex_lock(&dev->struct_mutex);
13915
13916 intel_unregister_dsm_handler();
13917
13918 intel_fbc_disable(dev);
13919
13920 mutex_unlock(&dev->struct_mutex);
13921
13922 /* flush any delayed tasks or pending work */
13923 flush_scheduled_work();
13924
13925 /* destroy the backlight and sysfs files before encoders/connectors */
13926 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13927 struct intel_connector *intel_connector;
13928
13929 intel_connector = to_intel_connector(connector);
13930 intel_connector->unregister(intel_connector);
13931 }
13932
13933 drm_mode_config_cleanup(dev);
13934
13935 intel_cleanup_overlay(dev);
13936
13937 mutex_lock(&dev->struct_mutex);
13938 intel_cleanup_gt_powersave(dev);
13939 mutex_unlock(&dev->struct_mutex);
13940 }
13941
13942 /*
13943 * Return which encoder is currently attached for connector.
13944 */
13945 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13946 {
13947 return &intel_attached_encoder(connector)->base;
13948 }
13949
13950 void intel_connector_attach_encoder(struct intel_connector *connector,
13951 struct intel_encoder *encoder)
13952 {
13953 connector->encoder = encoder;
13954 drm_mode_connector_attach_encoder(&connector->base,
13955 &encoder->base);
13956 }
13957
13958 /*
13959 * set vga decode state - true == enable VGA decode
13960 */
13961 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13962 {
13963 struct drm_i915_private *dev_priv = dev->dev_private;
13964 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13965 u16 gmch_ctrl;
13966
13967 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13968 DRM_ERROR("failed to read control word\n");
13969 return -EIO;
13970 }
13971
13972 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13973 return 0;
13974
13975 if (state)
13976 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13977 else
13978 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13979
13980 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13981 DRM_ERROR("failed to write control word\n");
13982 return -EIO;
13983 }
13984
13985 return 0;
13986 }
13987
13988 struct intel_display_error_state {
13989
13990 u32 power_well_driver;
13991
13992 int num_transcoders;
13993
13994 struct intel_cursor_error_state {
13995 u32 control;
13996 u32 position;
13997 u32 base;
13998 u32 size;
13999 } cursor[I915_MAX_PIPES];
14000
14001 struct intel_pipe_error_state {
14002 bool power_domain_on;
14003 u32 source;
14004 u32 stat;
14005 } pipe[I915_MAX_PIPES];
14006
14007 struct intel_plane_error_state {
14008 u32 control;
14009 u32 stride;
14010 u32 size;
14011 u32 pos;
14012 u32 addr;
14013 u32 surface;
14014 u32 tile_offset;
14015 } plane[I915_MAX_PIPES];
14016
14017 struct intel_transcoder_error_state {
14018 bool power_domain_on;
14019 enum transcoder cpu_transcoder;
14020
14021 u32 conf;
14022
14023 u32 htotal;
14024 u32 hblank;
14025 u32 hsync;
14026 u32 vtotal;
14027 u32 vblank;
14028 u32 vsync;
14029 } transcoder[4];
14030 };
14031
14032 struct intel_display_error_state *
14033 intel_display_capture_error_state(struct drm_device *dev)
14034 {
14035 struct drm_i915_private *dev_priv = dev->dev_private;
14036 struct intel_display_error_state *error;
14037 int transcoders[] = {
14038 TRANSCODER_A,
14039 TRANSCODER_B,
14040 TRANSCODER_C,
14041 TRANSCODER_EDP,
14042 };
14043 int i;
14044
14045 if (INTEL_INFO(dev)->num_pipes == 0)
14046 return NULL;
14047
14048 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14049 if (error == NULL)
14050 return NULL;
14051
14052 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14053 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14054
14055 for_each_pipe(dev_priv, i) {
14056 error->pipe[i].power_domain_on =
14057 __intel_display_power_is_enabled(dev_priv,
14058 POWER_DOMAIN_PIPE(i));
14059 if (!error->pipe[i].power_domain_on)
14060 continue;
14061
14062 error->cursor[i].control = I915_READ(CURCNTR(i));
14063 error->cursor[i].position = I915_READ(CURPOS(i));
14064 error->cursor[i].base = I915_READ(CURBASE(i));
14065
14066 error->plane[i].control = I915_READ(DSPCNTR(i));
14067 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14068 if (INTEL_INFO(dev)->gen <= 3) {
14069 error->plane[i].size = I915_READ(DSPSIZE(i));
14070 error->plane[i].pos = I915_READ(DSPPOS(i));
14071 }
14072 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14073 error->plane[i].addr = I915_READ(DSPADDR(i));
14074 if (INTEL_INFO(dev)->gen >= 4) {
14075 error->plane[i].surface = I915_READ(DSPSURF(i));
14076 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14077 }
14078
14079 error->pipe[i].source = I915_READ(PIPESRC(i));
14080
14081 if (HAS_GMCH_DISPLAY(dev))
14082 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14083 }
14084
14085 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14086 if (HAS_DDI(dev_priv->dev))
14087 error->num_transcoders++; /* Account for eDP. */
14088
14089 for (i = 0; i < error->num_transcoders; i++) {
14090 enum transcoder cpu_transcoder = transcoders[i];
14091
14092 error->transcoder[i].power_domain_on =
14093 __intel_display_power_is_enabled(dev_priv,
14094 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14095 if (!error->transcoder[i].power_domain_on)
14096 continue;
14097
14098 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14099
14100 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14101 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14102 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14103 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14104 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14105 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14106 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14107 }
14108
14109 return error;
14110 }
14111
14112 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14113
14114 void
14115 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14116 struct drm_device *dev,
14117 struct intel_display_error_state *error)
14118 {
14119 struct drm_i915_private *dev_priv = dev->dev_private;
14120 int i;
14121
14122 if (!error)
14123 return;
14124
14125 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14126 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14127 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14128 error->power_well_driver);
14129 for_each_pipe(dev_priv, i) {
14130 err_printf(m, "Pipe [%d]:\n", i);
14131 err_printf(m, " Power: %s\n",
14132 error->pipe[i].power_domain_on ? "on" : "off");
14133 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14134 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14135
14136 err_printf(m, "Plane [%d]:\n", i);
14137 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14138 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14139 if (INTEL_INFO(dev)->gen <= 3) {
14140 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14141 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14142 }
14143 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14144 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14145 if (INTEL_INFO(dev)->gen >= 4) {
14146 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14147 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14148 }
14149
14150 err_printf(m, "Cursor [%d]:\n", i);
14151 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14152 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14153 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14154 }
14155
14156 for (i = 0; i < error->num_transcoders; i++) {
14157 err_printf(m, "CPU transcoder: %c\n",
14158 transcoder_name(error->transcoder[i].cpu_transcoder));
14159 err_printf(m, " Power: %s\n",
14160 error->transcoder[i].power_domain_on ? "on" : "off");
14161 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14162 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14163 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14164 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14165 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14166 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14167 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14168 }
14169 }
14170
14171 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14172 {
14173 struct intel_crtc *crtc;
14174
14175 for_each_intel_crtc(dev, crtc) {
14176 struct intel_unpin_work *work;
14177
14178 spin_lock_irq(&dev->event_lock);
14179
14180 work = crtc->unpin_work;
14181
14182 if (work && work->event &&
14183 work->event->base.file_priv == file) {
14184 kfree(work->event);
14185 work->event = NULL;
14186 }
14187
14188 spin_unlock_irq(&dev->event_lock);
14189 }
14190 }
Linux kernel - Deliverables
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