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drm/i915: Add .atomic_{get, set}_property() entrypoints to planes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_state *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_state *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
102 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
103
104 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
105 {
106 if (!connector->mst_port)
107 return connector->encoder;
108 else
109 return &connector->mst_port->mst_encoders[pipe]->base;
110 }
111
112 typedef struct {
113 int min, max;
114 } intel_range_t;
115
116 typedef struct {
117 int dot_limit;
118 int p2_slow, p2_fast;
119 } intel_p2_t;
120
121 typedef struct intel_limit intel_limit_t;
122 struct intel_limit {
123 intel_range_t dot, vco, n, m, m1, m2, p, p1;
124 intel_p2_t p2;
125 };
126
127 int
128 intel_pch_rawclk(struct drm_device *dev)
129 {
130 struct drm_i915_private *dev_priv = dev->dev_private;
131
132 WARN_ON(!HAS_PCH_SPLIT(dev));
133
134 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
135 }
136
137 static inline u32 /* units of 100MHz */
138 intel_fdi_link_freq(struct drm_device *dev)
139 {
140 if (IS_GEN5(dev)) {
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
143 } else
144 return 27;
145 }
146
147 static const intel_limit_t intel_limits_i8xx_dac = {
148 .dot = { .min = 25000, .max = 350000 },
149 .vco = { .min = 908000, .max = 1512000 },
150 .n = { .min = 2, .max = 16 },
151 .m = { .min = 96, .max = 140 },
152 .m1 = { .min = 18, .max = 26 },
153 .m2 = { .min = 6, .max = 16 },
154 .p = { .min = 4, .max = 128 },
155 .p1 = { .min = 2, .max = 33 },
156 .p2 = { .dot_limit = 165000,
157 .p2_slow = 4, .p2_fast = 2 },
158 };
159
160 static const intel_limit_t intel_limits_i8xx_dvo = {
161 .dot = { .min = 25000, .max = 350000 },
162 .vco = { .min = 908000, .max = 1512000 },
163 .n = { .min = 2, .max = 16 },
164 .m = { .min = 96, .max = 140 },
165 .m1 = { .min = 18, .max = 26 },
166 .m2 = { .min = 6, .max = 16 },
167 .p = { .min = 4, .max = 128 },
168 .p1 = { .min = 2, .max = 33 },
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 4, .p2_fast = 4 },
171 };
172
173 static const intel_limit_t intel_limits_i8xx_lvds = {
174 .dot = { .min = 25000, .max = 350000 },
175 .vco = { .min = 908000, .max = 1512000 },
176 .n = { .min = 2, .max = 16 },
177 .m = { .min = 96, .max = 140 },
178 .m1 = { .min = 18, .max = 26 },
179 .m2 = { .min = 6, .max = 16 },
180 .p = { .min = 4, .max = 128 },
181 .p1 = { .min = 1, .max = 6 },
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 14, .p2_fast = 7 },
184 };
185
186 static const intel_limit_t intel_limits_i9xx_sdvo = {
187 .dot = { .min = 20000, .max = 400000 },
188 .vco = { .min = 1400000, .max = 2800000 },
189 .n = { .min = 1, .max = 6 },
190 .m = { .min = 70, .max = 120 },
191 .m1 = { .min = 8, .max = 18 },
192 .m2 = { .min = 3, .max = 7 },
193 .p = { .min = 5, .max = 80 },
194 .p1 = { .min = 1, .max = 8 },
195 .p2 = { .dot_limit = 200000,
196 .p2_slow = 10, .p2_fast = 5 },
197 };
198
199 static const intel_limit_t intel_limits_i9xx_lvds = {
200 .dot = { .min = 20000, .max = 400000 },
201 .vco = { .min = 1400000, .max = 2800000 },
202 .n = { .min = 1, .max = 6 },
203 .m = { .min = 70, .max = 120 },
204 .m1 = { .min = 8, .max = 18 },
205 .m2 = { .min = 3, .max = 7 },
206 .p = { .min = 7, .max = 98 },
207 .p1 = { .min = 1, .max = 8 },
208 .p2 = { .dot_limit = 112000,
209 .p2_slow = 14, .p2_fast = 7 },
210 };
211
212
213 static const intel_limit_t intel_limits_g4x_sdvo = {
214 .dot = { .min = 25000, .max = 270000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 10, .max = 30 },
221 .p1 = { .min = 1, .max = 3},
222 .p2 = { .dot_limit = 270000,
223 .p2_slow = 10,
224 .p2_fast = 10
225 },
226 };
227
228 static const intel_limit_t intel_limits_g4x_hdmi = {
229 .dot = { .min = 22000, .max = 400000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 4 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 16, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 5, .max = 80 },
236 .p1 = { .min = 1, .max = 8},
237 .p2 = { .dot_limit = 165000,
238 .p2_slow = 10, .p2_fast = 5 },
239 };
240
241 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
242 .dot = { .min = 20000, .max = 115000 },
243 .vco = { .min = 1750000, .max = 3500000 },
244 .n = { .min = 1, .max = 3 },
245 .m = { .min = 104, .max = 138 },
246 .m1 = { .min = 17, .max = 23 },
247 .m2 = { .min = 5, .max = 11 },
248 .p = { .min = 28, .max = 112 },
249 .p1 = { .min = 2, .max = 8 },
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 14, .p2_fast = 14
252 },
253 };
254
255 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
256 .dot = { .min = 80000, .max = 224000 },
257 .vco = { .min = 1750000, .max = 3500000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 104, .max = 138 },
260 .m1 = { .min = 17, .max = 23 },
261 .m2 = { .min = 5, .max = 11 },
262 .p = { .min = 14, .max = 42 },
263 .p1 = { .min = 2, .max = 6 },
264 .p2 = { .dot_limit = 0,
265 .p2_slow = 7, .p2_fast = 7
266 },
267 };
268
269 static const intel_limit_t intel_limits_pineview_sdvo = {
270 .dot = { .min = 20000, .max = 400000},
271 .vco = { .min = 1700000, .max = 3500000 },
272 /* Pineview's Ncounter is a ring counter */
273 .n = { .min = 3, .max = 6 },
274 .m = { .min = 2, .max = 256 },
275 /* Pineview only has one combined m divider, which we treat as m2. */
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 200000,
281 .p2_slow = 10, .p2_fast = 5 },
282 };
283
284 static const intel_limit_t intel_limits_pineview_lvds = {
285 .dot = { .min = 20000, .max = 400000 },
286 .vco = { .min = 1700000, .max = 3500000 },
287 .n = { .min = 3, .max = 6 },
288 .m = { .min = 2, .max = 256 },
289 .m1 = { .min = 0, .max = 0 },
290 .m2 = { .min = 0, .max = 254 },
291 .p = { .min = 7, .max = 112 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 112000,
294 .p2_slow = 14, .p2_fast = 14 },
295 };
296
297 /* Ironlake / Sandybridge
298 *
299 * We calculate clock using (register_value + 2) for N/M1/M2, so here
300 * the range value for them is (actual_value - 2).
301 */
302 static const intel_limit_t intel_limits_ironlake_dac = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 5 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 10, .p2_fast = 5 },
313 };
314
315 static const intel_limit_t intel_limits_ironlake_single_lvds = {
316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 3 },
319 .m = { .min = 79, .max = 118 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2, .max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
326 };
327
328 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 127 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 56 },
336 .p1 = { .min = 2, .max = 8 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 };
340
341 /* LVDS 100mhz refclk limits. */
342 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
343 .dot = { .min = 25000, .max = 350000 },
344 .vco = { .min = 1760000, .max = 3510000 },
345 .n = { .min = 1, .max = 2 },
346 .m = { .min = 79, .max = 126 },
347 .m1 = { .min = 12, .max = 22 },
348 .m2 = { .min = 5, .max = 9 },
349 .p = { .min = 28, .max = 112 },
350 .p1 = { .min = 2, .max = 8 },
351 .p2 = { .dot_limit = 225000,
352 .p2_slow = 14, .p2_fast = 14 },
353 };
354
355 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000 },
358 .n = { .min = 1, .max = 3 },
359 .m = { .min = 79, .max = 126 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 14, .max = 42 },
363 .p1 = { .min = 2, .max = 6 },
364 .p2 = { .dot_limit = 225000,
365 .p2_slow = 7, .p2_fast = 7 },
366 };
367
368 static const intel_limit_t intel_limits_vlv = {
369 /*
370 * These are the data rate limits (measured in fast clocks)
371 * since those are the strictest limits we have. The fast
372 * clock and actual rate limits are more relaxed, so checking
373 * them would make no difference.
374 */
375 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
376 .vco = { .min = 4000000, .max = 6000000 },
377 .n = { .min = 1, .max = 7 },
378 .m1 = { .min = 2, .max = 3 },
379 .m2 = { .min = 11, .max = 156 },
380 .p1 = { .min = 2, .max = 3 },
381 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
382 };
383
384 static const intel_limit_t intel_limits_chv = {
385 /*
386 * These are the data rate limits (measured in fast clocks)
387 * since those are the strictest limits we have. The fast
388 * clock and actual rate limits are more relaxed, so checking
389 * them would make no difference.
390 */
391 .dot = { .min = 25000 * 5, .max = 540000 * 5},
392 .vco = { .min = 4860000, .max = 6700000 },
393 .n = { .min = 1, .max = 1 },
394 .m1 = { .min = 2, .max = 2 },
395 .m2 = { .min = 24 << 22, .max = 175 << 22 },
396 .p1 = { .min = 2, .max = 4 },
397 .p2 = { .p2_slow = 1, .p2_fast = 14 },
398 };
399
400 static void vlv_clock(int refclk, intel_clock_t *clock)
401 {
402 clock->m = clock->m1 * clock->m2;
403 clock->p = clock->p1 * clock->p2;
404 if (WARN_ON(clock->n == 0 || clock->p == 0))
405 return;
406 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
407 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
408 }
409
410 /**
411 * Returns whether any output on the specified pipe is of the specified type
412 */
413 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
414 {
415 struct drm_device *dev = crtc->base.dev;
416 struct intel_encoder *encoder;
417
418 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
419 if (encoder->type == type)
420 return true;
421
422 return false;
423 }
424
425 /**
426 * Returns whether any output on the specified pipe will have the specified
427 * type after a staged modeset is complete, i.e., the same as
428 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 * encoder->crtc.
430 */
431 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
432 {
433 struct drm_device *dev = crtc->base.dev;
434 struct intel_encoder *encoder;
435
436 for_each_intel_encoder(dev, encoder)
437 if (encoder->new_crtc == crtc && encoder->type == type)
438 return true;
439
440 return false;
441 }
442
443 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
444 int refclk)
445 {
446 struct drm_device *dev = crtc->base.dev;
447 const intel_limit_t *limit;
448
449 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
450 if (intel_is_dual_link_lvds(dev)) {
451 if (refclk == 100000)
452 limit = &intel_limits_ironlake_dual_lvds_100m;
453 else
454 limit = &intel_limits_ironlake_dual_lvds;
455 } else {
456 if (refclk == 100000)
457 limit = &intel_limits_ironlake_single_lvds_100m;
458 else
459 limit = &intel_limits_ironlake_single_lvds;
460 }
461 } else
462 limit = &intel_limits_ironlake_dac;
463
464 return limit;
465 }
466
467 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
468 {
469 struct drm_device *dev = crtc->base.dev;
470 const intel_limit_t *limit;
471
472 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
473 if (intel_is_dual_link_lvds(dev))
474 limit = &intel_limits_g4x_dual_channel_lvds;
475 else
476 limit = &intel_limits_g4x_single_channel_lvds;
477 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
478 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
479 limit = &intel_limits_g4x_hdmi;
480 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
481 limit = &intel_limits_g4x_sdvo;
482 } else /* The option is for other outputs */
483 limit = &intel_limits_i9xx_sdvo;
484
485 return limit;
486 }
487
488 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
489 {
490 struct drm_device *dev = crtc->base.dev;
491 const intel_limit_t *limit;
492
493 if (HAS_PCH_SPLIT(dev))
494 limit = intel_ironlake_limit(crtc, refclk);
495 else if (IS_G4X(dev)) {
496 limit = intel_g4x_limit(crtc);
497 } else if (IS_PINEVIEW(dev)) {
498 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
499 limit = &intel_limits_pineview_lvds;
500 else
501 limit = &intel_limits_pineview_sdvo;
502 } else if (IS_CHERRYVIEW(dev)) {
503 limit = &intel_limits_chv;
504 } else if (IS_VALLEYVIEW(dev)) {
505 limit = &intel_limits_vlv;
506 } else if (!IS_GEN2(dev)) {
507 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
508 limit = &intel_limits_i9xx_lvds;
509 else
510 limit = &intel_limits_i9xx_sdvo;
511 } else {
512 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
513 limit = &intel_limits_i8xx_lvds;
514 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
515 limit = &intel_limits_i8xx_dvo;
516 else
517 limit = &intel_limits_i8xx_dac;
518 }
519 return limit;
520 }
521
522 /* m1 is reserved as 0 in Pineview, n is a ring counter */
523 static void pineview_clock(int refclk, intel_clock_t *clock)
524 {
525 clock->m = clock->m2 + 2;
526 clock->p = clock->p1 * clock->p2;
527 if (WARN_ON(clock->n == 0 || clock->p == 0))
528 return;
529 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
534 {
535 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
536 }
537
538 static void i9xx_clock(int refclk, intel_clock_t *clock)
539 {
540 clock->m = i9xx_dpll_compute_m(clock);
541 clock->p = clock->p1 * clock->p2;
542 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
543 return;
544 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
545 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
546 }
547
548 static void chv_clock(int refclk, intel_clock_t *clock)
549 {
550 clock->m = clock->m1 * clock->m2;
551 clock->p = clock->p1 * clock->p2;
552 if (WARN_ON(clock->n == 0 || clock->p == 0))
553 return;
554 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
555 clock->n << 22);
556 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
557 }
558
559 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
560 /**
561 * Returns whether the given set of divisors are valid for a given refclk with
562 * the given connectors.
563 */
564
565 static bool intel_PLL_is_valid(struct drm_device *dev,
566 const intel_limit_t *limit,
567 const intel_clock_t *clock)
568 {
569 if (clock->n < limit->n.min || limit->n.max < clock->n)
570 INTELPllInvalid("n out of range\n");
571 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
572 INTELPllInvalid("p1 out of range\n");
573 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
574 INTELPllInvalid("m2 out of range\n");
575 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
576 INTELPllInvalid("m1 out of range\n");
577
578 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
579 if (clock->m1 <= clock->m2)
580 INTELPllInvalid("m1 <= m2\n");
581
582 if (!IS_VALLEYVIEW(dev)) {
583 if (clock->p < limit->p.min || limit->p.max < clock->p)
584 INTELPllInvalid("p out of range\n");
585 if (clock->m < limit->m.min || limit->m.max < clock->m)
586 INTELPllInvalid("m out of range\n");
587 }
588
589 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
590 INTELPllInvalid("vco out of range\n");
591 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
592 * connector, etc., rather than just a single range.
593 */
594 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
595 INTELPllInvalid("dot out of range\n");
596
597 return true;
598 }
599
600 static bool
601 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
602 int target, int refclk, intel_clock_t *match_clock,
603 intel_clock_t *best_clock)
604 {
605 struct drm_device *dev = crtc->base.dev;
606 intel_clock_t clock;
607 int err = target;
608
609 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
610 /*
611 * For LVDS just rely on its current settings for dual-channel.
612 * We haven't figured out how to reliably set up different
613 * single/dual channel state, if we even can.
614 */
615 if (intel_is_dual_link_lvds(dev))
616 clock.p2 = limit->p2.p2_fast;
617 else
618 clock.p2 = limit->p2.p2_slow;
619 } else {
620 if (target < limit->p2.dot_limit)
621 clock.p2 = limit->p2.p2_slow;
622 else
623 clock.p2 = limit->p2.p2_fast;
624 }
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
629 clock.m1++) {
630 for (clock.m2 = limit->m2.min;
631 clock.m2 <= limit->m2.max; clock.m2++) {
632 if (clock.m2 >= clock.m1)
633 break;
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 i9xx_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->base.dev;
667 intel_clock_t clock;
668 int err = target;
669
670 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
671 /*
672 * For LVDS just rely on its current settings for dual-channel.
673 * We haven't figured out how to reliably set up different
674 * single/dual channel state, if we even can.
675 */
676 if (intel_is_dual_link_lvds(dev))
677 clock.p2 = limit->p2.p2_fast;
678 else
679 clock.p2 = limit->p2.p2_slow;
680 } else {
681 if (target < limit->p2.dot_limit)
682 clock.p2 = limit->p2.p2_slow;
683 else
684 clock.p2 = limit->p2.p2_fast;
685 }
686
687 memset(best_clock, 0, sizeof(*best_clock));
688
689 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 clock.m1++) {
691 for (clock.m2 = limit->m2.min;
692 clock.m2 <= limit->m2.max; clock.m2++) {
693 for (clock.n = limit->n.min;
694 clock.n <= limit->n.max; clock.n++) {
695 for (clock.p1 = limit->p1.min;
696 clock.p1 <= limit->p1.max; clock.p1++) {
697 int this_err;
698
699 pineview_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718 }
719
720 static bool
721 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
722 int target, int refclk, intel_clock_t *match_clock,
723 intel_clock_t *best_clock)
724 {
725 struct drm_device *dev = crtc->base.dev;
726 intel_clock_t clock;
727 int max_n;
728 bool found;
729 /* approximately equals target * 0.00585 */
730 int err_most = (target >> 8) + (target >> 9);
731 found = false;
732
733 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
734 if (intel_is_dual_link_lvds(dev))
735 clock.p2 = limit->p2.p2_fast;
736 else
737 clock.p2 = limit->p2.p2_slow;
738 } else {
739 if (target < limit->p2.dot_limit)
740 clock.p2 = limit->p2.p2_slow;
741 else
742 clock.p2 = limit->p2.p2_fast;
743 }
744
745 memset(best_clock, 0, sizeof(*best_clock));
746 max_n = limit->n.max;
747 /* based on hardware requirement, prefer smaller n to precision */
748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
749 /* based on hardware requirement, prefere larger m1,m2 */
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
758 i9xx_clock(refclk, &clock);
759 if (!intel_PLL_is_valid(dev, limit,
760 &clock))
761 continue;
762
763 this_err = abs(clock.dot - target);
764 if (this_err < err_most) {
765 *best_clock = clock;
766 err_most = this_err;
767 max_n = clock.n;
768 found = true;
769 }
770 }
771 }
772 }
773 }
774 return found;
775 }
776
777 static bool
778 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
779 int target, int refclk, intel_clock_t *match_clock,
780 intel_clock_t *best_clock)
781 {
782 struct drm_device *dev = crtc->base.dev;
783 intel_clock_t clock;
784 unsigned int bestppm = 1000000;
785 /* min update 19.2 MHz */
786 int max_n = min(limit->n.max, refclk / 19200);
787 bool found = false;
788
789 target *= 5; /* fast clock */
790
791 memset(best_clock, 0, sizeof(*best_clock));
792
793 /* based on hardware requirement, prefer smaller n to precision */
794 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
797 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
798 clock.p = clock.p1 * clock.p2;
799 /* based on hardware requirement, prefer bigger m1,m2 values */
800 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
801 unsigned int ppm, diff;
802
803 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
804 refclk * clock.m1);
805
806 vlv_clock(refclk, &clock);
807
808 if (!intel_PLL_is_valid(dev, limit,
809 &clock))
810 continue;
811
812 diff = abs(clock.dot - target);
813 ppm = div_u64(1000000ULL * diff, target);
814
815 if (ppm < 100 && clock.p > best_clock->p) {
816 bestppm = 0;
817 *best_clock = clock;
818 found = true;
819 }
820
821 if (bestppm >= 10 && ppm < bestppm - 10) {
822 bestppm = ppm;
823 *best_clock = clock;
824 found = true;
825 }
826 }
827 }
828 }
829 }
830
831 return found;
832 }
833
834 static bool
835 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
836 int target, int refclk, intel_clock_t *match_clock,
837 intel_clock_t *best_clock)
838 {
839 struct drm_device *dev = crtc->base.dev;
840 intel_clock_t clock;
841 uint64_t m2;
842 int found = false;
843
844 memset(best_clock, 0, sizeof(*best_clock));
845
846 /*
847 * Based on hardware doc, the n always set to 1, and m1 always
848 * set to 2. If requires to support 200Mhz refclk, we need to
849 * revisit this because n may not 1 anymore.
850 */
851 clock.n = 1, clock.m1 = 2;
852 target *= 5; /* fast clock */
853
854 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
855 for (clock.p2 = limit->p2.p2_fast;
856 clock.p2 >= limit->p2.p2_slow;
857 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
858
859 clock.p = clock.p1 * clock.p2;
860
861 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
862 clock.n) << 22, refclk * clock.m1);
863
864 if (m2 > INT_MAX/clock.m1)
865 continue;
866
867 clock.m2 = m2;
868
869 chv_clock(refclk, &clock);
870
871 if (!intel_PLL_is_valid(dev, limit, &clock))
872 continue;
873
874 /* based on hardware requirement, prefer bigger p
875 */
876 if (clock.p > best_clock->p) {
877 *best_clock = clock;
878 found = true;
879 }
880 }
881 }
882
883 return found;
884 }
885
886 bool intel_crtc_active(struct drm_crtc *crtc)
887 {
888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
889
890 /* Be paranoid as we can arrive here with only partial
891 * state retrieved from the hardware during setup.
892 *
893 * We can ditch the adjusted_mode.crtc_clock check as soon
894 * as Haswell has gained clock readout/fastboot support.
895 *
896 * We can ditch the crtc->primary->fb check as soon as we can
897 * properly reconstruct framebuffers.
898 */
899 return intel_crtc->active && crtc->primary->fb &&
900 intel_crtc->config->base.adjusted_mode.crtc_clock;
901 }
902
903 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
908
909 return intel_crtc->config->cpu_transcoder;
910 }
911
912 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 u32 reg = PIPEDSL(pipe);
916 u32 line1, line2;
917 u32 line_mask;
918
919 if (IS_GEN2(dev))
920 line_mask = DSL_LINEMASK_GEN2;
921 else
922 line_mask = DSL_LINEMASK_GEN3;
923
924 line1 = I915_READ(reg) & line_mask;
925 mdelay(5);
926 line2 = I915_READ(reg) & line_mask;
927
928 return line1 == line2;
929 }
930
931 /*
932 * intel_wait_for_pipe_off - wait for pipe to turn off
933 * @crtc: crtc whose pipe to wait for
934 *
935 * After disabling a pipe, we can't wait for vblank in the usual way,
936 * spinning on the vblank interrupt status bit, since we won't actually
937 * see an interrupt when the pipe is disabled.
938 *
939 * On Gen4 and above:
940 * wait for the pipe register state bit to turn off
941 *
942 * Otherwise:
943 * wait for the display line value to settle (it usually
944 * ends up stopping at the start of the next frame).
945 *
946 */
947 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
948 {
949 struct drm_device *dev = crtc->base.dev;
950 struct drm_i915_private *dev_priv = dev->dev_private;
951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
952 enum pipe pipe = crtc->pipe;
953
954 if (INTEL_INFO(dev)->gen >= 4) {
955 int reg = PIPECONF(cpu_transcoder);
956
957 /* Wait for the Pipe State to go off */
958 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
959 100))
960 WARN(1, "pipe_off wait timed out\n");
961 } else {
962 /* Wait for the display line to settle */
963 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
964 WARN(1, "pipe_off wait timed out\n");
965 }
966 }
967
968 /*
969 * ibx_digital_port_connected - is the specified port connected?
970 * @dev_priv: i915 private structure
971 * @port: the port to test
972 *
973 * Returns true if @port is connected, false otherwise.
974 */
975 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
976 struct intel_digital_port *port)
977 {
978 u32 bit;
979
980 if (HAS_PCH_IBX(dev_priv->dev)) {
981 switch (port->port) {
982 case PORT_B:
983 bit = SDE_PORTB_HOTPLUG;
984 break;
985 case PORT_C:
986 bit = SDE_PORTC_HOTPLUG;
987 break;
988 case PORT_D:
989 bit = SDE_PORTD_HOTPLUG;
990 break;
991 default:
992 return true;
993 }
994 } else {
995 switch (port->port) {
996 case PORT_B:
997 bit = SDE_PORTB_HOTPLUG_CPT;
998 break;
999 case PORT_C:
1000 bit = SDE_PORTC_HOTPLUG_CPT;
1001 break;
1002 case PORT_D:
1003 bit = SDE_PORTD_HOTPLUG_CPT;
1004 break;
1005 default:
1006 return true;
1007 }
1008 }
1009
1010 return I915_READ(SDEISR) & bit;
1011 }
1012
1013 static const char *state_string(bool enabled)
1014 {
1015 return enabled ? "on" : "off";
1016 }
1017
1018 /* Only for pre-ILK configs */
1019 void assert_pll(struct drm_i915_private *dev_priv,
1020 enum pipe pipe, bool state)
1021 {
1022 int reg;
1023 u32 val;
1024 bool cur_state;
1025
1026 reg = DPLL(pipe);
1027 val = I915_READ(reg);
1028 cur_state = !!(val & DPLL_VCO_ENABLE);
1029 I915_STATE_WARN(cur_state != state,
1030 "PLL state assertion failure (expected %s, current %s)\n",
1031 state_string(state), state_string(cur_state));
1032 }
1033
1034 /* XXX: the dsi pll is shared between MIPI DSI ports */
1035 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1036 {
1037 u32 val;
1038 bool cur_state;
1039
1040 mutex_lock(&dev_priv->dpio_lock);
1041 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1042 mutex_unlock(&dev_priv->dpio_lock);
1043
1044 cur_state = val & DSI_PLL_VCO_EN;
1045 I915_STATE_WARN(cur_state != state,
1046 "DSI PLL state assertion failure (expected %s, current %s)\n",
1047 state_string(state), state_string(cur_state));
1048 }
1049 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1050 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1051
1052 struct intel_shared_dpll *
1053 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1054 {
1055 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1056
1057 if (crtc->config->shared_dpll < 0)
1058 return NULL;
1059
1060 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1061 }
1062
1063 /* For ILK+ */
1064 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1065 struct intel_shared_dpll *pll,
1066 bool state)
1067 {
1068 bool cur_state;
1069 struct intel_dpll_hw_state hw_state;
1070
1071 if (WARN (!pll,
1072 "asserting DPLL %s with no DPLL\n", state_string(state)))
1073 return;
1074
1075 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1076 I915_STATE_WARN(cur_state != state,
1077 "%s assertion failure (expected %s, current %s)\n",
1078 pll->name, state_string(state), state_string(cur_state));
1079 }
1080
1081 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1082 enum pipe pipe, bool state)
1083 {
1084 int reg;
1085 u32 val;
1086 bool cur_state;
1087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1088 pipe);
1089
1090 if (HAS_DDI(dev_priv->dev)) {
1091 /* DDI does not have a specific FDI_TX register */
1092 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1093 val = I915_READ(reg);
1094 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1095 } else {
1096 reg = FDI_TX_CTL(pipe);
1097 val = I915_READ(reg);
1098 cur_state = !!(val & FDI_TX_ENABLE);
1099 }
1100 I915_STATE_WARN(cur_state != state,
1101 "FDI TX state assertion failure (expected %s, current %s)\n",
1102 state_string(state), state_string(cur_state));
1103 }
1104 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1105 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1106
1107 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = FDI_RX_CTL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & FDI_RX_ENABLE);
1117 I915_STATE_WARN(cur_state != state,
1118 "FDI RX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1122 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1123
1124 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe)
1126 {
1127 int reg;
1128 u32 val;
1129
1130 /* ILK FDI PLL is always enabled */
1131 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1132 return;
1133
1134 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1135 if (HAS_DDI(dev_priv->dev))
1136 return;
1137
1138 reg = FDI_TX_CTL(pipe);
1139 val = I915_READ(reg);
1140 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 }
1142
1143 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1144 enum pipe pipe, bool state)
1145 {
1146 int reg;
1147 u32 val;
1148 bool cur_state;
1149
1150 reg = FDI_RX_CTL(pipe);
1151 val = I915_READ(reg);
1152 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156 }
1157
1158 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160 {
1161 struct drm_device *dev = dev_priv->dev;
1162 int pp_reg;
1163 u32 val;
1164 enum pipe panel_pipe = PIPE_A;
1165 bool locked = true;
1166
1167 if (WARN_ON(HAS_DDI(dev)))
1168 return;
1169
1170 if (HAS_PCH_SPLIT(dev)) {
1171 u32 port_sel;
1172
1173 pp_reg = PCH_PP_CONTROL;
1174 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1175
1176 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1177 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179 /* XXX: else fix for eDP */
1180 } else if (IS_VALLEYVIEW(dev)) {
1181 /* presumably write lock depends on pipe, not port select */
1182 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1183 panel_pipe = pipe;
1184 } else {
1185 pp_reg = PP_CONTROL;
1186 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1187 panel_pipe = PIPE_B;
1188 }
1189
1190 val = I915_READ(pp_reg);
1191 if (!(val & PANEL_POWER_ON) ||
1192 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1193 locked = false;
1194
1195 I915_STATE_WARN(panel_pipe == pipe && locked,
1196 "panel assertion failure, pipe %c regs locked\n",
1197 pipe_name(pipe));
1198 }
1199
1200 static void assert_cursor(struct drm_i915_private *dev_priv,
1201 enum pipe pipe, bool state)
1202 {
1203 struct drm_device *dev = dev_priv->dev;
1204 bool cur_state;
1205
1206 if (IS_845G(dev) || IS_I865G(dev))
1207 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1208 else
1209 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1210
1211 I915_STATE_WARN(cur_state != state,
1212 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1213 pipe_name(pipe), state_string(state), state_string(cur_state));
1214 }
1215 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1216 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1217
1218 void assert_pipe(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
1220 {
1221 int reg;
1222 u32 val;
1223 bool cur_state;
1224 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 pipe);
1226
1227 /* if we need the pipe quirk it must be always on */
1228 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1229 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1230 state = true;
1231
1232 if (!intel_display_power_is_enabled(dev_priv,
1233 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1234 cur_state = false;
1235 } else {
1236 reg = PIPECONF(cpu_transcoder);
1237 val = I915_READ(reg);
1238 cur_state = !!(val & PIPECONF_ENABLE);
1239 }
1240
1241 I915_STATE_WARN(cur_state != state,
1242 "pipe %c assertion failure (expected %s, current %s)\n",
1243 pipe_name(pipe), state_string(state), state_string(cur_state));
1244 }
1245
1246 static void assert_plane(struct drm_i915_private *dev_priv,
1247 enum plane plane, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = DSPCNTR(plane);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "plane %c assertion failure (expected %s, current %s)\n",
1258 plane_name(plane), state_string(state), state_string(cur_state));
1259 }
1260
1261 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1262 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1263
1264 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe)
1266 {
1267 struct drm_device *dev = dev_priv->dev;
1268 int reg, i;
1269 u32 val;
1270 int cur_pipe;
1271
1272 /* Primary planes are fixed to pipes on gen4+ */
1273 if (INTEL_INFO(dev)->gen >= 4) {
1274 reg = DSPCNTR(pipe);
1275 val = I915_READ(reg);
1276 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1277 "plane %c assertion failure, should be disabled but not\n",
1278 plane_name(pipe));
1279 return;
1280 }
1281
1282 /* Need to check both planes against the pipe */
1283 for_each_pipe(dev_priv, i) {
1284 reg = DSPCNTR(i);
1285 val = I915_READ(reg);
1286 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1287 DISPPLANE_SEL_PIPE_SHIFT;
1288 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1289 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1290 plane_name(i), pipe_name(pipe));
1291 }
1292 }
1293
1294 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296 {
1297 struct drm_device *dev = dev_priv->dev;
1298 int reg, sprite;
1299 u32 val;
1300
1301 if (INTEL_INFO(dev)->gen >= 9) {
1302 for_each_sprite(pipe, sprite) {
1303 val = I915_READ(PLANE_CTL(pipe, sprite));
1304 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1305 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1306 sprite, pipe_name(pipe));
1307 }
1308 } else if (IS_VALLEYVIEW(dev)) {
1309 for_each_sprite(pipe, sprite) {
1310 reg = SPCNTR(pipe, sprite);
1311 val = I915_READ(reg);
1312 I915_STATE_WARN(val & SP_ENABLE,
1313 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1314 sprite_name(pipe, sprite), pipe_name(pipe));
1315 }
1316 } else if (INTEL_INFO(dev)->gen >= 7) {
1317 reg = SPRCTL(pipe);
1318 val = I915_READ(reg);
1319 I915_STATE_WARN(val & SPRITE_ENABLE,
1320 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(pipe), pipe_name(pipe));
1322 } else if (INTEL_INFO(dev)->gen >= 5) {
1323 reg = DVSCNTR(pipe);
1324 val = I915_READ(reg);
1325 I915_STATE_WARN(val & DVS_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe), pipe_name(pipe));
1328 }
1329 }
1330
1331 static void assert_vblank_disabled(struct drm_crtc *crtc)
1332 {
1333 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1334 drm_crtc_vblank_put(crtc);
1335 }
1336
1337 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1338 {
1339 u32 val;
1340 bool enabled;
1341
1342 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1343
1344 val = I915_READ(PCH_DREF_CONTROL);
1345 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1346 DREF_SUPERSPREAD_SOURCE_MASK));
1347 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1348 }
1349
1350 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1351 enum pipe pipe)
1352 {
1353 int reg;
1354 u32 val;
1355 bool enabled;
1356
1357 reg = PCH_TRANSCONF(pipe);
1358 val = I915_READ(reg);
1359 enabled = !!(val & TRANS_ENABLE);
1360 I915_STATE_WARN(enabled,
1361 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1362 pipe_name(pipe));
1363 }
1364
1365 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 port_sel, u32 val)
1367 {
1368 if ((val & DP_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1373 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1374 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1375 return false;
1376 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1377 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1378 return false;
1379 } else {
1380 if ((val & DP_PIPE_MASK) != (pipe << 30))
1381 return false;
1382 }
1383 return true;
1384 }
1385
1386 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1387 enum pipe pipe, u32 val)
1388 {
1389 if ((val & SDVO_ENABLE) == 0)
1390 return false;
1391
1392 if (HAS_PCH_CPT(dev_priv->dev)) {
1393 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1394 return false;
1395 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1396 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1397 return false;
1398 } else {
1399 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1400 return false;
1401 }
1402 return true;
1403 }
1404
1405 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1406 enum pipe pipe, u32 val)
1407 {
1408 if ((val & LVDS_PORT_EN) == 0)
1409 return false;
1410
1411 if (HAS_PCH_CPT(dev_priv->dev)) {
1412 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1413 return false;
1414 } else {
1415 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1416 return false;
1417 }
1418 return true;
1419 }
1420
1421 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1422 enum pipe pipe, u32 val)
1423 {
1424 if ((val & ADPA_DAC_ENABLE) == 0)
1425 return false;
1426 if (HAS_PCH_CPT(dev_priv->dev)) {
1427 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1428 return false;
1429 } else {
1430 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg, u32 port_sel)
1438 {
1439 u32 val = I915_READ(reg);
1440 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1441 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1442 reg, pipe_name(pipe));
1443
1444 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1445 && (val & DP_PIPEB_SELECT),
1446 "IBX PCH dp port still using transcoder B\n");
1447 }
1448
1449 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe, int reg)
1451 {
1452 u32 val = I915_READ(reg);
1453 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1454 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1455 reg, pipe_name(pipe));
1456
1457 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1458 && (val & SDVO_PIPE_B_SELECT),
1459 "IBX PCH hdmi port still using transcoder B\n");
1460 }
1461
1462 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1463 enum pipe pipe)
1464 {
1465 int reg;
1466 u32 val;
1467
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1470 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1471
1472 reg = PCH_ADPA;
1473 val = I915_READ(reg);
1474 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1475 "PCH VGA enabled on transcoder %c, should be disabled\n",
1476 pipe_name(pipe));
1477
1478 reg = PCH_LVDS;
1479 val = I915_READ(reg);
1480 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1481 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 pipe_name(pipe));
1483
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1486 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1487 }
1488
1489 static void intel_init_dpio(struct drm_device *dev)
1490 {
1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492
1493 if (!IS_VALLEYVIEW(dev))
1494 return;
1495
1496 /*
1497 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1498 * CHV x1 PHY (DP/HDMI D)
1499 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1500 */
1501 if (IS_CHERRYVIEW(dev)) {
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1504 } else {
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1506 }
1507 }
1508
1509 static void vlv_enable_pll(struct intel_crtc *crtc,
1510 const struct intel_crtc_state *pipe_config)
1511 {
1512 struct drm_device *dev = crtc->base.dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 int reg = DPLL(crtc->pipe);
1515 u32 dpll = pipe_config->dpll_hw_state.dpll;
1516
1517 assert_pipe_disabled(dev_priv, crtc->pipe);
1518
1519 /* No really, not for ILK+ */
1520 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1521
1522 /* PLL is protected by panel, make sure we can write it */
1523 if (IS_MOBILE(dev_priv->dev))
1524 assert_panel_unlocked(dev_priv, crtc->pipe);
1525
1526 I915_WRITE(reg, dpll);
1527 POSTING_READ(reg);
1528 udelay(150);
1529
1530 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1531 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1532
1533 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1534 POSTING_READ(DPLL_MD(crtc->pipe));
1535
1536 /* We do this three times for luck */
1537 I915_WRITE(reg, dpll);
1538 POSTING_READ(reg);
1539 udelay(150); /* wait for warmup */
1540 I915_WRITE(reg, dpll);
1541 POSTING_READ(reg);
1542 udelay(150); /* wait for warmup */
1543 I915_WRITE(reg, dpll);
1544 POSTING_READ(reg);
1545 udelay(150); /* wait for warmup */
1546 }
1547
1548 static void chv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_state *pipe_config)
1550 {
1551 struct drm_device *dev = crtc->base.dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553 int pipe = crtc->pipe;
1554 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1555 u32 tmp;
1556
1557 assert_pipe_disabled(dev_priv, crtc->pipe);
1558
1559 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1560
1561 mutex_lock(&dev_priv->dpio_lock);
1562
1563 /* Enable back the 10bit clock to display controller */
1564 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1565 tmp |= DPIO_DCLKP_EN;
1566 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1567
1568 /*
1569 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1570 */
1571 udelay(1);
1572
1573 /* Enable PLL */
1574 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1575
1576 /* Check PLL is locked */
1577 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1578 DRM_ERROR("PLL %d failed to lock\n", pipe);
1579
1580 /* not sure when this should be written */
1581 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1582 POSTING_READ(DPLL_MD(pipe));
1583
1584 mutex_unlock(&dev_priv->dpio_lock);
1585 }
1586
1587 static int intel_num_dvo_pipes(struct drm_device *dev)
1588 {
1589 struct intel_crtc *crtc;
1590 int count = 0;
1591
1592 for_each_intel_crtc(dev, crtc)
1593 count += crtc->active &&
1594 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1595
1596 return count;
1597 }
1598
1599 static void i9xx_enable_pll(struct intel_crtc *crtc)
1600 {
1601 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config->dpll_hw_state.dpll;
1605
1606 assert_pipe_disabled(dev_priv, crtc->pipe);
1607
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev) && !IS_I830(dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 /* Enable DVO 2x clock on both PLLs if necessary */
1616 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1617 /*
1618 * It appears to be important that we don't enable this
1619 * for the current pipe before otherwise configuring the
1620 * PLL. No idea how this should be handled if multiple
1621 * DVO outputs are enabled simultaneosly.
1622 */
1623 dpll |= DPLL_DVO_2X_MODE;
1624 I915_WRITE(DPLL(!crtc->pipe),
1625 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1626 }
1627
1628 /* Wait for the clocks to stabilize. */
1629 POSTING_READ(reg);
1630 udelay(150);
1631
1632 if (INTEL_INFO(dev)->gen >= 4) {
1633 I915_WRITE(DPLL_MD(crtc->pipe),
1634 crtc->config->dpll_hw_state.dpll_md);
1635 } else {
1636 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable.
1638 *
1639 * So write it again.
1640 */
1641 I915_WRITE(reg, dpll);
1642 }
1643
1644 /* We do this three times for luck */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 }
1655
1656 /**
1657 * i9xx_disable_pll - disable a PLL
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe PLL to disable
1660 *
1661 * Disable the PLL for @pipe, making sure the pipe is off first.
1662 *
1663 * Note! This is for pre-ILK only.
1664 */
1665 static void i9xx_disable_pll(struct intel_crtc *crtc)
1666 {
1667 struct drm_device *dev = crtc->base.dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 enum pipe pipe = crtc->pipe;
1670
1671 /* Disable DVO 2x clock on both PLLs if necessary */
1672 if (IS_I830(dev) &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1674 intel_num_dvo_pipes(dev) == 1) {
1675 I915_WRITE(DPLL(PIPE_B),
1676 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1677 I915_WRITE(DPLL(PIPE_A),
1678 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1679 }
1680
1681 /* Don't disable pipe or pipe PLLs if needed */
1682 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1683 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1684 return;
1685
1686 /* Make sure the pipe isn't still relying on us */
1687 assert_pipe_disabled(dev_priv, pipe);
1688
1689 I915_WRITE(DPLL(pipe), 0);
1690 POSTING_READ(DPLL(pipe));
1691 }
1692
1693 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695 u32 val = 0;
1696
1697 /* Make sure the pipe isn't still relying on us */
1698 assert_pipe_disabled(dev_priv, pipe);
1699
1700 /*
1701 * Leave integrated clock source and reference clock enabled for pipe B.
1702 * The latter is needed for VGA hotplug / manual detection.
1703 */
1704 if (pipe == PIPE_B)
1705 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
1708
1709 }
1710
1711 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1712 {
1713 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1714 u32 val;
1715
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1718
1719 /* Set PLL en = 0 */
1720 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1721 if (pipe != PIPE_A)
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1723 I915_WRITE(DPLL(pipe), val);
1724 POSTING_READ(DPLL(pipe));
1725
1726 mutex_lock(&dev_priv->dpio_lock);
1727
1728 /* Disable 10bit clock to display controller */
1729 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1730 val &= ~DPIO_DCLKP_EN;
1731 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1732
1733 /* disable left/right clock distribution */
1734 if (pipe != PIPE_B) {
1735 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1736 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1737 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1738 } else {
1739 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1740 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1741 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1742 }
1743
1744 mutex_unlock(&dev_priv->dpio_lock);
1745 }
1746
1747 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1748 struct intel_digital_port *dport)
1749 {
1750 u32 port_mask;
1751 int dpll_reg;
1752
1753 switch (dport->port) {
1754 case PORT_B:
1755 port_mask = DPLL_PORTB_READY_MASK;
1756 dpll_reg = DPLL(0);
1757 break;
1758 case PORT_C:
1759 port_mask = DPLL_PORTC_READY_MASK;
1760 dpll_reg = DPLL(0);
1761 break;
1762 case PORT_D:
1763 port_mask = DPLL_PORTD_READY_MASK;
1764 dpll_reg = DPIO_PHY_STATUS;
1765 break;
1766 default:
1767 BUG();
1768 }
1769
1770 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1771 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1772 port_name(dport->port), I915_READ(dpll_reg));
1773 }
1774
1775 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1776 {
1777 struct drm_device *dev = crtc->base.dev;
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1780
1781 if (WARN_ON(pll == NULL))
1782 return;
1783
1784 WARN_ON(!pll->config.crtc_mask);
1785 if (pll->active == 0) {
1786 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1787 WARN_ON(pll->on);
1788 assert_shared_dpll_disabled(dev_priv, pll);
1789
1790 pll->mode_set(dev_priv, pll);
1791 }
1792 }
1793
1794 /**
1795 * intel_enable_shared_dpll - enable PCH PLL
1796 * @dev_priv: i915 private structure
1797 * @pipe: pipe PLL to enable
1798 *
1799 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1800 * drives the transcoder clock.
1801 */
1802 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1803 {
1804 struct drm_device *dev = crtc->base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1807
1808 if (WARN_ON(pll == NULL))
1809 return;
1810
1811 if (WARN_ON(pll->config.crtc_mask == 0))
1812 return;
1813
1814 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1815 pll->name, pll->active, pll->on,
1816 crtc->base.base.id);
1817
1818 if (pll->active++) {
1819 WARN_ON(!pll->on);
1820 assert_shared_dpll_enabled(dev_priv, pll);
1821 return;
1822 }
1823 WARN_ON(pll->on);
1824
1825 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1826
1827 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1828 pll->enable(dev_priv, pll);
1829 pll->on = true;
1830 }
1831
1832 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1833 {
1834 struct drm_device *dev = crtc->base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1837
1838 /* PCH only available on ILK+ */
1839 BUG_ON(INTEL_INFO(dev)->gen < 5);
1840 if (WARN_ON(pll == NULL))
1841 return;
1842
1843 if (WARN_ON(pll->config.crtc_mask == 0))
1844 return;
1845
1846 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1847 pll->name, pll->active, pll->on,
1848 crtc->base.base.id);
1849
1850 if (WARN_ON(pll->active == 0)) {
1851 assert_shared_dpll_disabled(dev_priv, pll);
1852 return;
1853 }
1854
1855 assert_shared_dpll_enabled(dev_priv, pll);
1856 WARN_ON(!pll->on);
1857 if (--pll->active)
1858 return;
1859
1860 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1861 pll->disable(dev_priv, pll);
1862 pll->on = false;
1863
1864 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1865 }
1866
1867 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1868 enum pipe pipe)
1869 {
1870 struct drm_device *dev = dev_priv->dev;
1871 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1873 uint32_t reg, val, pipeconf_val;
1874
1875 /* PCH only available on ILK+ */
1876 BUG_ON(!HAS_PCH_SPLIT(dev));
1877
1878 /* Make sure PCH DPLL is enabled */
1879 assert_shared_dpll_enabled(dev_priv,
1880 intel_crtc_to_shared_dpll(intel_crtc));
1881
1882 /* FDI must be feeding us bits for PCH ports */
1883 assert_fdi_tx_enabled(dev_priv, pipe);
1884 assert_fdi_rx_enabled(dev_priv, pipe);
1885
1886 if (HAS_PCH_CPT(dev)) {
1887 /* Workaround: Set the timing override bit before enabling the
1888 * pch transcoder. */
1889 reg = TRANS_CHICKEN2(pipe);
1890 val = I915_READ(reg);
1891 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1892 I915_WRITE(reg, val);
1893 }
1894
1895 reg = PCH_TRANSCONF(pipe);
1896 val = I915_READ(reg);
1897 pipeconf_val = I915_READ(PIPECONF(pipe));
1898
1899 if (HAS_PCH_IBX(dev_priv->dev)) {
1900 /*
1901 * make the BPC in transcoder be consistent with
1902 * that in pipeconf reg.
1903 */
1904 val &= ~PIPECONF_BPC_MASK;
1905 val |= pipeconf_val & PIPECONF_BPC_MASK;
1906 }
1907
1908 val &= ~TRANS_INTERLACE_MASK;
1909 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1910 if (HAS_PCH_IBX(dev_priv->dev) &&
1911 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1912 val |= TRANS_LEGACY_INTERLACED_ILK;
1913 else
1914 val |= TRANS_INTERLACED;
1915 else
1916 val |= TRANS_PROGRESSIVE;
1917
1918 I915_WRITE(reg, val | TRANS_ENABLE);
1919 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1920 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1921 }
1922
1923 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1924 enum transcoder cpu_transcoder)
1925 {
1926 u32 val, pipeconf_val;
1927
1928 /* PCH only available on ILK+ */
1929 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1930
1931 /* FDI must be feeding us bits for PCH ports */
1932 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1933 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1934
1935 /* Workaround: set timing override bit. */
1936 val = I915_READ(_TRANSA_CHICKEN2);
1937 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1938 I915_WRITE(_TRANSA_CHICKEN2, val);
1939
1940 val = TRANS_ENABLE;
1941 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1942
1943 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1944 PIPECONF_INTERLACED_ILK)
1945 val |= TRANS_INTERLACED;
1946 else
1947 val |= TRANS_PROGRESSIVE;
1948
1949 I915_WRITE(LPT_TRANSCONF, val);
1950 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1951 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 }
1953
1954 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 enum pipe pipe)
1956 {
1957 struct drm_device *dev = dev_priv->dev;
1958 uint32_t reg, val;
1959
1960 /* FDI relies on the transcoder */
1961 assert_fdi_tx_disabled(dev_priv, pipe);
1962 assert_fdi_rx_disabled(dev_priv, pipe);
1963
1964 /* Ports must be off as well */
1965 assert_pch_ports_disabled(dev_priv, pipe);
1966
1967 reg = PCH_TRANSCONF(pipe);
1968 val = I915_READ(reg);
1969 val &= ~TRANS_ENABLE;
1970 I915_WRITE(reg, val);
1971 /* wait for PCH transcoder off, transcoder state */
1972 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1973 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1974
1975 if (!HAS_PCH_IBX(dev)) {
1976 /* Workaround: Clear the timing override chicken bit again. */
1977 reg = TRANS_CHICKEN2(pipe);
1978 val = I915_READ(reg);
1979 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1980 I915_WRITE(reg, val);
1981 }
1982 }
1983
1984 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1985 {
1986 u32 val;
1987
1988 val = I915_READ(LPT_TRANSCONF);
1989 val &= ~TRANS_ENABLE;
1990 I915_WRITE(LPT_TRANSCONF, val);
1991 /* wait for PCH transcoder off, transcoder state */
1992 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1993 DRM_ERROR("Failed to disable PCH transcoder\n");
1994
1995 /* Workaround: clear timing override bit. */
1996 val = I915_READ(_TRANSA_CHICKEN2);
1997 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1998 I915_WRITE(_TRANSA_CHICKEN2, val);
1999 }
2000
2001 /**
2002 * intel_enable_pipe - enable a pipe, asserting requirements
2003 * @crtc: crtc responsible for the pipe
2004 *
2005 * Enable @crtc's pipe, making sure that various hardware specific requirements
2006 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2007 */
2008 static void intel_enable_pipe(struct intel_crtc *crtc)
2009 {
2010 struct drm_device *dev = crtc->base.dev;
2011 struct drm_i915_private *dev_priv = dev->dev_private;
2012 enum pipe pipe = crtc->pipe;
2013 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2014 pipe);
2015 enum pipe pch_transcoder;
2016 int reg;
2017 u32 val;
2018
2019 assert_planes_disabled(dev_priv, pipe);
2020 assert_cursor_disabled(dev_priv, pipe);
2021 assert_sprites_disabled(dev_priv, pipe);
2022
2023 if (HAS_PCH_LPT(dev_priv->dev))
2024 pch_transcoder = TRANSCODER_A;
2025 else
2026 pch_transcoder = pipe;
2027
2028 /*
2029 * A pipe without a PLL won't actually be able to drive bits from
2030 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 * need the check.
2032 */
2033 if (!HAS_PCH_SPLIT(dev_priv->dev))
2034 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2035 assert_dsi_pll_enabled(dev_priv);
2036 else
2037 assert_pll_enabled(dev_priv, pipe);
2038 else {
2039 if (crtc->config->has_pch_encoder) {
2040 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2042 assert_fdi_tx_pll_enabled(dev_priv,
2043 (enum pipe) cpu_transcoder);
2044 }
2045 /* FIXME: assert CPU port conditions for SNB+ */
2046 }
2047
2048 reg = PIPECONF(cpu_transcoder);
2049 val = I915_READ(reg);
2050 if (val & PIPECONF_ENABLE) {
2051 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2052 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2053 return;
2054 }
2055
2056 I915_WRITE(reg, val | PIPECONF_ENABLE);
2057 POSTING_READ(reg);
2058 }
2059
2060 /**
2061 * intel_disable_pipe - disable a pipe, asserting requirements
2062 * @crtc: crtc whose pipes is to be disabled
2063 *
2064 * Disable the pipe of @crtc, making sure that various hardware
2065 * specific requirements are met, if applicable, e.g. plane
2066 * disabled, panel fitter off, etc.
2067 *
2068 * Will wait until the pipe has shut down before returning.
2069 */
2070 static void intel_disable_pipe(struct intel_crtc *crtc)
2071 {
2072 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2073 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2074 enum pipe pipe = crtc->pipe;
2075 int reg;
2076 u32 val;
2077
2078 /*
2079 * Make sure planes won't keep trying to pump pixels to us,
2080 * or we might hang the display.
2081 */
2082 assert_planes_disabled(dev_priv, pipe);
2083 assert_cursor_disabled(dev_priv, pipe);
2084 assert_sprites_disabled(dev_priv, pipe);
2085
2086 reg = PIPECONF(cpu_transcoder);
2087 val = I915_READ(reg);
2088 if ((val & PIPECONF_ENABLE) == 0)
2089 return;
2090
2091 /*
2092 * Double wide has implications for planes
2093 * so best keep it disabled when not needed.
2094 */
2095 if (crtc->config->double_wide)
2096 val &= ~PIPECONF_DOUBLE_WIDE;
2097
2098 /* Don't disable pipe or pipe PLLs if needed */
2099 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2100 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2101 val &= ~PIPECONF_ENABLE;
2102
2103 I915_WRITE(reg, val);
2104 if ((val & PIPECONF_ENABLE) == 0)
2105 intel_wait_for_pipe_off(crtc);
2106 }
2107
2108 /*
2109 * Plane regs are double buffered, going from enabled->disabled needs a
2110 * trigger in order to latch. The display address reg provides this.
2111 */
2112 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2113 enum plane plane)
2114 {
2115 struct drm_device *dev = dev_priv->dev;
2116 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2117
2118 I915_WRITE(reg, I915_READ(reg));
2119 POSTING_READ(reg);
2120 }
2121
2122 /**
2123 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2124 * @plane: plane to be enabled
2125 * @crtc: crtc for the plane
2126 *
2127 * Enable @plane on @crtc, making sure that the pipe is running first.
2128 */
2129 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2130 struct drm_crtc *crtc)
2131 {
2132 struct drm_device *dev = plane->dev;
2133 struct drm_i915_private *dev_priv = dev->dev_private;
2134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2135
2136 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2137 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2138
2139 if (intel_crtc->primary_enabled)
2140 return;
2141
2142 intel_crtc->primary_enabled = true;
2143
2144 dev_priv->display.update_primary_plane(crtc, plane->fb,
2145 crtc->x, crtc->y);
2146
2147 /*
2148 * BDW signals flip done immediately if the plane
2149 * is disabled, even if the plane enable is already
2150 * armed to occur at the next vblank :(
2151 */
2152 if (IS_BROADWELL(dev))
2153 intel_wait_for_vblank(dev, intel_crtc->pipe);
2154 }
2155
2156 /**
2157 * intel_disable_primary_hw_plane - disable the primary hardware plane
2158 * @plane: plane to be disabled
2159 * @crtc: crtc for the plane
2160 *
2161 * Disable @plane on @crtc, making sure that the pipe is running first.
2162 */
2163 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2164 struct drm_crtc *crtc)
2165 {
2166 struct drm_device *dev = plane->dev;
2167 struct drm_i915_private *dev_priv = dev->dev_private;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (WARN_ON(!intel_crtc->active))
2171 return;
2172
2173 if (!intel_crtc->primary_enabled)
2174 return;
2175
2176 intel_crtc->primary_enabled = false;
2177
2178 dev_priv->display.update_primary_plane(crtc, plane->fb,
2179 crtc->x, crtc->y);
2180 }
2181
2182 static bool need_vtd_wa(struct drm_device *dev)
2183 {
2184 #ifdef CONFIG_INTEL_IOMMU
2185 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2186 return true;
2187 #endif
2188 return false;
2189 }
2190
2191 int
2192 intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2193 {
2194 int tile_height;
2195
2196 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2197 return ALIGN(height, tile_height);
2198 }
2199
2200 int
2201 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2202 struct drm_framebuffer *fb,
2203 struct intel_engine_cs *pipelined)
2204 {
2205 struct drm_device *dev = fb->dev;
2206 struct drm_i915_private *dev_priv = dev->dev_private;
2207 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2208 u32 alignment;
2209 int ret;
2210
2211 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2212
2213 switch (obj->tiling_mode) {
2214 case I915_TILING_NONE:
2215 if (INTEL_INFO(dev)->gen >= 9)
2216 alignment = 256 * 1024;
2217 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2218 alignment = 128 * 1024;
2219 else if (INTEL_INFO(dev)->gen >= 4)
2220 alignment = 4 * 1024;
2221 else
2222 alignment = 64 * 1024;
2223 break;
2224 case I915_TILING_X:
2225 if (INTEL_INFO(dev)->gen >= 9)
2226 alignment = 256 * 1024;
2227 else {
2228 /* pin() will align the object as required by fence */
2229 alignment = 0;
2230 }
2231 break;
2232 case I915_TILING_Y:
2233 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2234 return -EINVAL;
2235 default:
2236 BUG();
2237 }
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 intel_runtime_pm_get(dev_priv);
2255
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2258 if (ret)
2259 goto err_interruptible;
2260
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2265 */
2266 ret = i915_gem_object_get_fence(obj);
2267 if (ret)
2268 goto err_unpin;
2269
2270 i915_gem_object_pin_fence(obj);
2271
2272 dev_priv->mm.interruptible = true;
2273 intel_runtime_pm_put(dev_priv);
2274 return 0;
2275
2276 err_unpin:
2277 i915_gem_object_unpin_from_display_plane(obj);
2278 err_interruptible:
2279 dev_priv->mm.interruptible = true;
2280 intel_runtime_pm_put(dev_priv);
2281 return ret;
2282 }
2283
2284 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2285 {
2286 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2287
2288 i915_gem_object_unpin_fence(obj);
2289 i915_gem_object_unpin_from_display_plane(obj);
2290 }
2291
2292 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2293 * is assumed to be a power-of-two. */
2294 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2295 unsigned int tiling_mode,
2296 unsigned int cpp,
2297 unsigned int pitch)
2298 {
2299 if (tiling_mode != I915_TILING_NONE) {
2300 unsigned int tile_rows, tiles;
2301
2302 tile_rows = *y / 8;
2303 *y %= 8;
2304
2305 tiles = *x / (512/cpp);
2306 *x %= 512/cpp;
2307
2308 return tile_rows * pitch * 8 + tiles * 4096;
2309 } else {
2310 unsigned int offset;
2311
2312 offset = *y * pitch + *x * cpp;
2313 *y = 0;
2314 *x = (offset & 4095) / cpp;
2315 return offset & -4096;
2316 }
2317 }
2318
2319 static int i9xx_format_to_fourcc(int format)
2320 {
2321 switch (format) {
2322 case DISPPLANE_8BPP:
2323 return DRM_FORMAT_C8;
2324 case DISPPLANE_BGRX555:
2325 return DRM_FORMAT_XRGB1555;
2326 case DISPPLANE_BGRX565:
2327 return DRM_FORMAT_RGB565;
2328 default:
2329 case DISPPLANE_BGRX888:
2330 return DRM_FORMAT_XRGB8888;
2331 case DISPPLANE_RGBX888:
2332 return DRM_FORMAT_XBGR8888;
2333 case DISPPLANE_BGRX101010:
2334 return DRM_FORMAT_XRGB2101010;
2335 case DISPPLANE_RGBX101010:
2336 return DRM_FORMAT_XBGR2101010;
2337 }
2338 }
2339
2340 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2341 {
2342 switch (format) {
2343 case PLANE_CTL_FORMAT_RGB_565:
2344 return DRM_FORMAT_RGB565;
2345 default:
2346 case PLANE_CTL_FORMAT_XRGB_8888:
2347 if (rgb_order) {
2348 if (alpha)
2349 return DRM_FORMAT_ABGR8888;
2350 else
2351 return DRM_FORMAT_XBGR8888;
2352 } else {
2353 if (alpha)
2354 return DRM_FORMAT_ARGB8888;
2355 else
2356 return DRM_FORMAT_XRGB8888;
2357 }
2358 case PLANE_CTL_FORMAT_XRGB_2101010:
2359 if (rgb_order)
2360 return DRM_FORMAT_XBGR2101010;
2361 else
2362 return DRM_FORMAT_XRGB2101010;
2363 }
2364 }
2365
2366 static bool
2367 intel_alloc_plane_obj(struct intel_crtc *crtc,
2368 struct intel_initial_plane_config *plane_config)
2369 {
2370 struct drm_device *dev = crtc->base.dev;
2371 struct drm_i915_gem_object *obj = NULL;
2372 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2373 u32 base = plane_config->base;
2374
2375 if (plane_config->size == 0)
2376 return false;
2377
2378 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2379 plane_config->size);
2380 if (!obj)
2381 return false;
2382
2383 obj->tiling_mode = plane_config->tiling;
2384 if (obj->tiling_mode == I915_TILING_X)
2385 obj->stride = crtc->base.primary->fb->pitches[0];
2386
2387 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2388 mode_cmd.width = crtc->base.primary->fb->width;
2389 mode_cmd.height = crtc->base.primary->fb->height;
2390 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2391
2392 mutex_lock(&dev->struct_mutex);
2393
2394 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2395 &mode_cmd, obj)) {
2396 DRM_DEBUG_KMS("intel fb init failed\n");
2397 goto out_unref_obj;
2398 }
2399
2400 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2401 mutex_unlock(&dev->struct_mutex);
2402
2403 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2404 return true;
2405
2406 out_unref_obj:
2407 drm_gem_object_unreference(&obj->base);
2408 mutex_unlock(&dev->struct_mutex);
2409 return false;
2410 }
2411
2412 static void
2413 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2414 struct intel_initial_plane_config *plane_config)
2415 {
2416 struct drm_device *dev = intel_crtc->base.dev;
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct drm_crtc *c;
2419 struct intel_crtc *i;
2420 struct drm_i915_gem_object *obj;
2421
2422 if (!intel_crtc->base.primary->fb)
2423 return;
2424
2425 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2426 return;
2427
2428 kfree(intel_crtc->base.primary->fb);
2429 intel_crtc->base.primary->fb = NULL;
2430
2431 /*
2432 * Failed to alloc the obj, check to see if we should share
2433 * an fb with another CRTC instead
2434 */
2435 for_each_crtc(dev, c) {
2436 i = to_intel_crtc(c);
2437
2438 if (c == &intel_crtc->base)
2439 continue;
2440
2441 if (!i->active)
2442 continue;
2443
2444 obj = intel_fb_obj(c->primary->fb);
2445 if (obj == NULL)
2446 continue;
2447
2448 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2449 if (obj->tiling_mode != I915_TILING_NONE)
2450 dev_priv->preserve_bios_swizzle = true;
2451
2452 drm_framebuffer_reference(c->primary->fb);
2453 intel_crtc->base.primary->fb = c->primary->fb;
2454 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2455 break;
2456 }
2457 }
2458 }
2459
2460 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2461 struct drm_framebuffer *fb,
2462 int x, int y)
2463 {
2464 struct drm_device *dev = crtc->dev;
2465 struct drm_i915_private *dev_priv = dev->dev_private;
2466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2467 struct drm_i915_gem_object *obj;
2468 int plane = intel_crtc->plane;
2469 unsigned long linear_offset;
2470 u32 dspcntr;
2471 u32 reg = DSPCNTR(plane);
2472 int pixel_size;
2473
2474 if (!intel_crtc->primary_enabled) {
2475 I915_WRITE(reg, 0);
2476 if (INTEL_INFO(dev)->gen >= 4)
2477 I915_WRITE(DSPSURF(plane), 0);
2478 else
2479 I915_WRITE(DSPADDR(plane), 0);
2480 POSTING_READ(reg);
2481 return;
2482 }
2483
2484 obj = intel_fb_obj(fb);
2485 if (WARN_ON(obj == NULL))
2486 return;
2487
2488 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2489
2490 dspcntr = DISPPLANE_GAMMA_ENABLE;
2491
2492 dspcntr |= DISPLAY_PLANE_ENABLE;
2493
2494 if (INTEL_INFO(dev)->gen < 4) {
2495 if (intel_crtc->pipe == PIPE_B)
2496 dspcntr |= DISPPLANE_SEL_PIPE_B;
2497
2498 /* pipesrc and dspsize control the size that is scaled from,
2499 * which should always be the user's requested size.
2500 */
2501 I915_WRITE(DSPSIZE(plane),
2502 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2503 (intel_crtc->config->pipe_src_w - 1));
2504 I915_WRITE(DSPPOS(plane), 0);
2505 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2506 I915_WRITE(PRIMSIZE(plane),
2507 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2508 (intel_crtc->config->pipe_src_w - 1));
2509 I915_WRITE(PRIMPOS(plane), 0);
2510 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2511 }
2512
2513 switch (fb->pixel_format) {
2514 case DRM_FORMAT_C8:
2515 dspcntr |= DISPPLANE_8BPP;
2516 break;
2517 case DRM_FORMAT_XRGB1555:
2518 case DRM_FORMAT_ARGB1555:
2519 dspcntr |= DISPPLANE_BGRX555;
2520 break;
2521 case DRM_FORMAT_RGB565:
2522 dspcntr |= DISPPLANE_BGRX565;
2523 break;
2524 case DRM_FORMAT_XRGB8888:
2525 case DRM_FORMAT_ARGB8888:
2526 dspcntr |= DISPPLANE_BGRX888;
2527 break;
2528 case DRM_FORMAT_XBGR8888:
2529 case DRM_FORMAT_ABGR8888:
2530 dspcntr |= DISPPLANE_RGBX888;
2531 break;
2532 case DRM_FORMAT_XRGB2101010:
2533 case DRM_FORMAT_ARGB2101010:
2534 dspcntr |= DISPPLANE_BGRX101010;
2535 break;
2536 case DRM_FORMAT_XBGR2101010:
2537 case DRM_FORMAT_ABGR2101010:
2538 dspcntr |= DISPPLANE_RGBX101010;
2539 break;
2540 default:
2541 BUG();
2542 }
2543
2544 if (INTEL_INFO(dev)->gen >= 4 &&
2545 obj->tiling_mode != I915_TILING_NONE)
2546 dspcntr |= DISPPLANE_TILED;
2547
2548 if (IS_G4X(dev))
2549 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2550
2551 linear_offset = y * fb->pitches[0] + x * pixel_size;
2552
2553 if (INTEL_INFO(dev)->gen >= 4) {
2554 intel_crtc->dspaddr_offset =
2555 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2556 pixel_size,
2557 fb->pitches[0]);
2558 linear_offset -= intel_crtc->dspaddr_offset;
2559 } else {
2560 intel_crtc->dspaddr_offset = linear_offset;
2561 }
2562
2563 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2564 dspcntr |= DISPPLANE_ROTATE_180;
2565
2566 x += (intel_crtc->config->pipe_src_w - 1);
2567 y += (intel_crtc->config->pipe_src_h - 1);
2568
2569 /* Finding the last pixel of the last line of the display
2570 data and adding to linear_offset*/
2571 linear_offset +=
2572 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2573 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2574 }
2575
2576 I915_WRITE(reg, dspcntr);
2577
2578 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2579 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2580 fb->pitches[0]);
2581 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2582 if (INTEL_INFO(dev)->gen >= 4) {
2583 I915_WRITE(DSPSURF(plane),
2584 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2585 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2586 I915_WRITE(DSPLINOFF(plane), linear_offset);
2587 } else
2588 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2589 POSTING_READ(reg);
2590 }
2591
2592 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2593 struct drm_framebuffer *fb,
2594 int x, int y)
2595 {
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 struct drm_i915_gem_object *obj;
2600 int plane = intel_crtc->plane;
2601 unsigned long linear_offset;
2602 u32 dspcntr;
2603 u32 reg = DSPCNTR(plane);
2604 int pixel_size;
2605
2606 if (!intel_crtc->primary_enabled) {
2607 I915_WRITE(reg, 0);
2608 I915_WRITE(DSPSURF(plane), 0);
2609 POSTING_READ(reg);
2610 return;
2611 }
2612
2613 obj = intel_fb_obj(fb);
2614 if (WARN_ON(obj == NULL))
2615 return;
2616
2617 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2618
2619 dspcntr = DISPPLANE_GAMMA_ENABLE;
2620
2621 dspcntr |= DISPLAY_PLANE_ENABLE;
2622
2623 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2624 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2625
2626 switch (fb->pixel_format) {
2627 case DRM_FORMAT_C8:
2628 dspcntr |= DISPPLANE_8BPP;
2629 break;
2630 case DRM_FORMAT_RGB565:
2631 dspcntr |= DISPPLANE_BGRX565;
2632 break;
2633 case DRM_FORMAT_XRGB8888:
2634 case DRM_FORMAT_ARGB8888:
2635 dspcntr |= DISPPLANE_BGRX888;
2636 break;
2637 case DRM_FORMAT_XBGR8888:
2638 case DRM_FORMAT_ABGR8888:
2639 dspcntr |= DISPPLANE_RGBX888;
2640 break;
2641 case DRM_FORMAT_XRGB2101010:
2642 case DRM_FORMAT_ARGB2101010:
2643 dspcntr |= DISPPLANE_BGRX101010;
2644 break;
2645 case DRM_FORMAT_XBGR2101010:
2646 case DRM_FORMAT_ABGR2101010:
2647 dspcntr |= DISPPLANE_RGBX101010;
2648 break;
2649 default:
2650 BUG();
2651 }
2652
2653 if (obj->tiling_mode != I915_TILING_NONE)
2654 dspcntr |= DISPPLANE_TILED;
2655
2656 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2657 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2658
2659 linear_offset = y * fb->pitches[0] + x * pixel_size;
2660 intel_crtc->dspaddr_offset =
2661 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2662 pixel_size,
2663 fb->pitches[0]);
2664 linear_offset -= intel_crtc->dspaddr_offset;
2665 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2666 dspcntr |= DISPPLANE_ROTATE_180;
2667
2668 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2669 x += (intel_crtc->config->pipe_src_w - 1);
2670 y += (intel_crtc->config->pipe_src_h - 1);
2671
2672 /* Finding the last pixel of the last line of the display
2673 data and adding to linear_offset*/
2674 linear_offset +=
2675 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2676 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2677 }
2678 }
2679
2680 I915_WRITE(reg, dspcntr);
2681
2682 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2683 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2684 fb->pitches[0]);
2685 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2686 I915_WRITE(DSPSURF(plane),
2687 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2688 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2689 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2690 } else {
2691 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2692 I915_WRITE(DSPLINOFF(plane), linear_offset);
2693 }
2694 POSTING_READ(reg);
2695 }
2696
2697 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2698 struct drm_framebuffer *fb,
2699 int x, int y)
2700 {
2701 struct drm_device *dev = crtc->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 struct intel_framebuffer *intel_fb;
2705 struct drm_i915_gem_object *obj;
2706 int pipe = intel_crtc->pipe;
2707 u32 plane_ctl, stride;
2708
2709 if (!intel_crtc->primary_enabled) {
2710 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2711 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2712 POSTING_READ(PLANE_CTL(pipe, 0));
2713 return;
2714 }
2715
2716 plane_ctl = PLANE_CTL_ENABLE |
2717 PLANE_CTL_PIPE_GAMMA_ENABLE |
2718 PLANE_CTL_PIPE_CSC_ENABLE;
2719
2720 switch (fb->pixel_format) {
2721 case DRM_FORMAT_RGB565:
2722 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2723 break;
2724 case DRM_FORMAT_XRGB8888:
2725 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2726 break;
2727 case DRM_FORMAT_XBGR8888:
2728 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2729 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2730 break;
2731 case DRM_FORMAT_XRGB2101010:
2732 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2736 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2737 break;
2738 default:
2739 BUG();
2740 }
2741
2742 intel_fb = to_intel_framebuffer(fb);
2743 obj = intel_fb->obj;
2744
2745 /*
2746 * The stride is either expressed as a multiple of 64 bytes chunks for
2747 * linear buffers or in number of tiles for tiled buffers.
2748 */
2749 switch (obj->tiling_mode) {
2750 case I915_TILING_NONE:
2751 stride = fb->pitches[0] >> 6;
2752 break;
2753 case I915_TILING_X:
2754 plane_ctl |= PLANE_CTL_TILED_X;
2755 stride = fb->pitches[0] >> 9;
2756 break;
2757 default:
2758 BUG();
2759 }
2760
2761 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2762 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2763 plane_ctl |= PLANE_CTL_ROTATE_180;
2764
2765 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2766
2767 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2768 i915_gem_obj_ggtt_offset(obj),
2769 x, y, fb->width, fb->height,
2770 fb->pitches[0]);
2771
2772 I915_WRITE(PLANE_POS(pipe, 0), 0);
2773 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2774 I915_WRITE(PLANE_SIZE(pipe, 0),
2775 (intel_crtc->config->pipe_src_h - 1) << 16 |
2776 (intel_crtc->config->pipe_src_w - 1));
2777 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2778 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2779
2780 POSTING_READ(PLANE_SURF(pipe, 0));
2781 }
2782
2783 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2784 static int
2785 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2786 int x, int y, enum mode_set_atomic state)
2787 {
2788 struct drm_device *dev = crtc->dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790
2791 if (dev_priv->display.disable_fbc)
2792 dev_priv->display.disable_fbc(dev);
2793
2794 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2795
2796 return 0;
2797 }
2798
2799 static void intel_complete_page_flips(struct drm_device *dev)
2800 {
2801 struct drm_crtc *crtc;
2802
2803 for_each_crtc(dev, crtc) {
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 enum plane plane = intel_crtc->plane;
2806
2807 intel_prepare_page_flip(dev, plane);
2808 intel_finish_page_flip_plane(dev, plane);
2809 }
2810 }
2811
2812 static void intel_update_primary_planes(struct drm_device *dev)
2813 {
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct drm_crtc *crtc;
2816
2817 for_each_crtc(dev, crtc) {
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819
2820 drm_modeset_lock(&crtc->mutex, NULL);
2821 /*
2822 * FIXME: Once we have proper support for primary planes (and
2823 * disabling them without disabling the entire crtc) allow again
2824 * a NULL crtc->primary->fb.
2825 */
2826 if (intel_crtc->active && crtc->primary->fb)
2827 dev_priv->display.update_primary_plane(crtc,
2828 crtc->primary->fb,
2829 crtc->x,
2830 crtc->y);
2831 drm_modeset_unlock(&crtc->mutex);
2832 }
2833 }
2834
2835 void intel_prepare_reset(struct drm_device *dev)
2836 {
2837 struct drm_i915_private *dev_priv = to_i915(dev);
2838 struct intel_crtc *crtc;
2839
2840 /* no reset support for gen2 */
2841 if (IS_GEN2(dev))
2842 return;
2843
2844 /* reset doesn't touch the display */
2845 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2846 return;
2847
2848 drm_modeset_lock_all(dev);
2849
2850 /*
2851 * Disabling the crtcs gracefully seems nicer. Also the
2852 * g33 docs say we should at least disable all the planes.
2853 */
2854 for_each_intel_crtc(dev, crtc) {
2855 if (crtc->active)
2856 dev_priv->display.crtc_disable(&crtc->base);
2857 }
2858 }
2859
2860 void intel_finish_reset(struct drm_device *dev)
2861 {
2862 struct drm_i915_private *dev_priv = to_i915(dev);
2863
2864 /*
2865 * Flips in the rings will be nuked by the reset,
2866 * so complete all pending flips so that user space
2867 * will get its events and not get stuck.
2868 */
2869 intel_complete_page_flips(dev);
2870
2871 /* no reset support for gen2 */
2872 if (IS_GEN2(dev))
2873 return;
2874
2875 /* reset doesn't touch the display */
2876 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2877 /*
2878 * Flips in the rings have been nuked by the reset,
2879 * so update the base address of all primary
2880 * planes to the the last fb to make sure we're
2881 * showing the correct fb after a reset.
2882 */
2883 intel_update_primary_planes(dev);
2884 return;
2885 }
2886
2887 /*
2888 * The display has been reset as well,
2889 * so need a full re-initialization.
2890 */
2891 intel_runtime_pm_disable_interrupts(dev_priv);
2892 intel_runtime_pm_enable_interrupts(dev_priv);
2893
2894 intel_modeset_init_hw(dev);
2895
2896 spin_lock_irq(&dev_priv->irq_lock);
2897 if (dev_priv->display.hpd_irq_setup)
2898 dev_priv->display.hpd_irq_setup(dev);
2899 spin_unlock_irq(&dev_priv->irq_lock);
2900
2901 intel_modeset_setup_hw_state(dev, true);
2902
2903 intel_hpd_init(dev_priv);
2904
2905 drm_modeset_unlock_all(dev);
2906 }
2907
2908 static int
2909 intel_finish_fb(struct drm_framebuffer *old_fb)
2910 {
2911 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2912 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2913 bool was_interruptible = dev_priv->mm.interruptible;
2914 int ret;
2915
2916 /* Big Hammer, we also need to ensure that any pending
2917 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2918 * current scanout is retired before unpinning the old
2919 * framebuffer.
2920 *
2921 * This should only fail upon a hung GPU, in which case we
2922 * can safely continue.
2923 */
2924 dev_priv->mm.interruptible = false;
2925 ret = i915_gem_object_finish_gpu(obj);
2926 dev_priv->mm.interruptible = was_interruptible;
2927
2928 return ret;
2929 }
2930
2931 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2932 {
2933 struct drm_device *dev = crtc->dev;
2934 struct drm_i915_private *dev_priv = dev->dev_private;
2935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2936 bool pending;
2937
2938 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2939 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2940 return false;
2941
2942 spin_lock_irq(&dev->event_lock);
2943 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2944 spin_unlock_irq(&dev->event_lock);
2945
2946 return pending;
2947 }
2948
2949 static void intel_update_pipe_size(struct intel_crtc *crtc)
2950 {
2951 struct drm_device *dev = crtc->base.dev;
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2953 const struct drm_display_mode *adjusted_mode;
2954
2955 if (!i915.fastboot)
2956 return;
2957
2958 /*
2959 * Update pipe size and adjust fitter if needed: the reason for this is
2960 * that in compute_mode_changes we check the native mode (not the pfit
2961 * mode) to see if we can flip rather than do a full mode set. In the
2962 * fastboot case, we'll flip, but if we don't update the pipesrc and
2963 * pfit state, we'll end up with a big fb scanned out into the wrong
2964 * sized surface.
2965 *
2966 * To fix this properly, we need to hoist the checks up into
2967 * compute_mode_changes (or above), check the actual pfit state and
2968 * whether the platform allows pfit disable with pipe active, and only
2969 * then update the pipesrc and pfit state, even on the flip path.
2970 */
2971
2972 adjusted_mode = &crtc->config->base.adjusted_mode;
2973
2974 I915_WRITE(PIPESRC(crtc->pipe),
2975 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2976 (adjusted_mode->crtc_vdisplay - 1));
2977 if (!crtc->config->pch_pfit.enabled &&
2978 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2979 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2980 I915_WRITE(PF_CTL(crtc->pipe), 0);
2981 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2982 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2983 }
2984 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
2985 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
2986 }
2987
2988 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2989 {
2990 struct drm_device *dev = crtc->dev;
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2993 int pipe = intel_crtc->pipe;
2994 u32 reg, temp;
2995
2996 /* enable normal train */
2997 reg = FDI_TX_CTL(pipe);
2998 temp = I915_READ(reg);
2999 if (IS_IVYBRIDGE(dev)) {
3000 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3001 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3002 } else {
3003 temp &= ~FDI_LINK_TRAIN_NONE;
3004 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3005 }
3006 I915_WRITE(reg, temp);
3007
3008 reg = FDI_RX_CTL(pipe);
3009 temp = I915_READ(reg);
3010 if (HAS_PCH_CPT(dev)) {
3011 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3012 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3013 } else {
3014 temp &= ~FDI_LINK_TRAIN_NONE;
3015 temp |= FDI_LINK_TRAIN_NONE;
3016 }
3017 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3018
3019 /* wait one idle pattern time */
3020 POSTING_READ(reg);
3021 udelay(1000);
3022
3023 /* IVB wants error correction enabled */
3024 if (IS_IVYBRIDGE(dev))
3025 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3026 FDI_FE_ERRC_ENABLE);
3027 }
3028
3029 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3030 {
3031 return crtc->base.enabled && crtc->active &&
3032 crtc->config->has_pch_encoder;
3033 }
3034
3035 static void ivb_modeset_global_resources(struct drm_device *dev)
3036 {
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *pipe_B_crtc =
3039 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3040 struct intel_crtc *pipe_C_crtc =
3041 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3042 uint32_t temp;
3043
3044 /*
3045 * When everything is off disable fdi C so that we could enable fdi B
3046 * with all lanes. Note that we don't care about enabled pipes without
3047 * an enabled pch encoder.
3048 */
3049 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3050 !pipe_has_enabled_pch(pipe_C_crtc)) {
3051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3053
3054 temp = I915_READ(SOUTH_CHICKEN1);
3055 temp &= ~FDI_BC_BIFURCATION_SELECT;
3056 DRM_DEBUG_KMS("disabling fdi C rx\n");
3057 I915_WRITE(SOUTH_CHICKEN1, temp);
3058 }
3059 }
3060
3061 /* The FDI link training functions for ILK/Ibexpeak. */
3062 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3063 {
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
3068 u32 reg, temp, tries;
3069
3070 /* FDI needs bits from pipe first */
3071 assert_pipe_enabled(dev_priv, pipe);
3072
3073 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3074 for train result */
3075 reg = FDI_RX_IMR(pipe);
3076 temp = I915_READ(reg);
3077 temp &= ~FDI_RX_SYMBOL_LOCK;
3078 temp &= ~FDI_RX_BIT_LOCK;
3079 I915_WRITE(reg, temp);
3080 I915_READ(reg);
3081 udelay(150);
3082
3083 /* enable CPU FDI TX and PCH FDI RX */
3084 reg = FDI_TX_CTL(pipe);
3085 temp = I915_READ(reg);
3086 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3087 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3088 temp &= ~FDI_LINK_TRAIN_NONE;
3089 temp |= FDI_LINK_TRAIN_PATTERN_1;
3090 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3091
3092 reg = FDI_RX_CTL(pipe);
3093 temp = I915_READ(reg);
3094 temp &= ~FDI_LINK_TRAIN_NONE;
3095 temp |= FDI_LINK_TRAIN_PATTERN_1;
3096 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3097
3098 POSTING_READ(reg);
3099 udelay(150);
3100
3101 /* Ironlake workaround, enable clock pointer after FDI enable*/
3102 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3103 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3104 FDI_RX_PHASE_SYNC_POINTER_EN);
3105
3106 reg = FDI_RX_IIR(pipe);
3107 for (tries = 0; tries < 5; tries++) {
3108 temp = I915_READ(reg);
3109 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3110
3111 if ((temp & FDI_RX_BIT_LOCK)) {
3112 DRM_DEBUG_KMS("FDI train 1 done.\n");
3113 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3114 break;
3115 }
3116 }
3117 if (tries == 5)
3118 DRM_ERROR("FDI train 1 fail!\n");
3119
3120 /* Train 2 */
3121 reg = FDI_TX_CTL(pipe);
3122 temp = I915_READ(reg);
3123 temp &= ~FDI_LINK_TRAIN_NONE;
3124 temp |= FDI_LINK_TRAIN_PATTERN_2;
3125 I915_WRITE(reg, temp);
3126
3127 reg = FDI_RX_CTL(pipe);
3128 temp = I915_READ(reg);
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_PATTERN_2;
3131 I915_WRITE(reg, temp);
3132
3133 POSTING_READ(reg);
3134 udelay(150);
3135
3136 reg = FDI_RX_IIR(pipe);
3137 for (tries = 0; tries < 5; tries++) {
3138 temp = I915_READ(reg);
3139 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3140
3141 if (temp & FDI_RX_SYMBOL_LOCK) {
3142 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3143 DRM_DEBUG_KMS("FDI train 2 done.\n");
3144 break;
3145 }
3146 }
3147 if (tries == 5)
3148 DRM_ERROR("FDI train 2 fail!\n");
3149
3150 DRM_DEBUG_KMS("FDI train done\n");
3151
3152 }
3153
3154 static const int snb_b_fdi_train_param[] = {
3155 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3156 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3157 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3158 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3159 };
3160
3161 /* The FDI link training functions for SNB/Cougarpoint. */
3162 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3163 {
3164 struct drm_device *dev = crtc->dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 int pipe = intel_crtc->pipe;
3168 u32 reg, temp, i, retry;
3169
3170 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3171 for train result */
3172 reg = FDI_RX_IMR(pipe);
3173 temp = I915_READ(reg);
3174 temp &= ~FDI_RX_SYMBOL_LOCK;
3175 temp &= ~FDI_RX_BIT_LOCK;
3176 I915_WRITE(reg, temp);
3177
3178 POSTING_READ(reg);
3179 udelay(150);
3180
3181 /* enable CPU FDI TX and PCH FDI RX */
3182 reg = FDI_TX_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3185 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3186 temp &= ~FDI_LINK_TRAIN_NONE;
3187 temp |= FDI_LINK_TRAIN_PATTERN_1;
3188 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3189 /* SNB-B */
3190 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3191 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3192
3193 I915_WRITE(FDI_RX_MISC(pipe),
3194 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3195
3196 reg = FDI_RX_CTL(pipe);
3197 temp = I915_READ(reg);
3198 if (HAS_PCH_CPT(dev)) {
3199 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3200 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3201 } else {
3202 temp &= ~FDI_LINK_TRAIN_NONE;
3203 temp |= FDI_LINK_TRAIN_PATTERN_1;
3204 }
3205 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3206
3207 POSTING_READ(reg);
3208 udelay(150);
3209
3210 for (i = 0; i < 4; i++) {
3211 reg = FDI_TX_CTL(pipe);
3212 temp = I915_READ(reg);
3213 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3214 temp |= snb_b_fdi_train_param[i];
3215 I915_WRITE(reg, temp);
3216
3217 POSTING_READ(reg);
3218 udelay(500);
3219
3220 for (retry = 0; retry < 5; retry++) {
3221 reg = FDI_RX_IIR(pipe);
3222 temp = I915_READ(reg);
3223 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3224 if (temp & FDI_RX_BIT_LOCK) {
3225 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3226 DRM_DEBUG_KMS("FDI train 1 done.\n");
3227 break;
3228 }
3229 udelay(50);
3230 }
3231 if (retry < 5)
3232 break;
3233 }
3234 if (i == 4)
3235 DRM_ERROR("FDI train 1 fail!\n");
3236
3237 /* Train 2 */
3238 reg = FDI_TX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 temp &= ~FDI_LINK_TRAIN_NONE;
3241 temp |= FDI_LINK_TRAIN_PATTERN_2;
3242 if (IS_GEN6(dev)) {
3243 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3244 /* SNB-B */
3245 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3246 }
3247 I915_WRITE(reg, temp);
3248
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 if (HAS_PCH_CPT(dev)) {
3252 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3253 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3254 } else {
3255 temp &= ~FDI_LINK_TRAIN_NONE;
3256 temp |= FDI_LINK_TRAIN_PATTERN_2;
3257 }
3258 I915_WRITE(reg, temp);
3259
3260 POSTING_READ(reg);
3261 udelay(150);
3262
3263 for (i = 0; i < 4; i++) {
3264 reg = FDI_TX_CTL(pipe);
3265 temp = I915_READ(reg);
3266 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3267 temp |= snb_b_fdi_train_param[i];
3268 I915_WRITE(reg, temp);
3269
3270 POSTING_READ(reg);
3271 udelay(500);
3272
3273 for (retry = 0; retry < 5; retry++) {
3274 reg = FDI_RX_IIR(pipe);
3275 temp = I915_READ(reg);
3276 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3277 if (temp & FDI_RX_SYMBOL_LOCK) {
3278 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3279 DRM_DEBUG_KMS("FDI train 2 done.\n");
3280 break;
3281 }
3282 udelay(50);
3283 }
3284 if (retry < 5)
3285 break;
3286 }
3287 if (i == 4)
3288 DRM_ERROR("FDI train 2 fail!\n");
3289
3290 DRM_DEBUG_KMS("FDI train done.\n");
3291 }
3292
3293 /* Manual link training for Ivy Bridge A0 parts */
3294 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3295 {
3296 struct drm_device *dev = crtc->dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3299 int pipe = intel_crtc->pipe;
3300 u32 reg, temp, i, j;
3301
3302 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3303 for train result */
3304 reg = FDI_RX_IMR(pipe);
3305 temp = I915_READ(reg);
3306 temp &= ~FDI_RX_SYMBOL_LOCK;
3307 temp &= ~FDI_RX_BIT_LOCK;
3308 I915_WRITE(reg, temp);
3309
3310 POSTING_READ(reg);
3311 udelay(150);
3312
3313 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3314 I915_READ(FDI_RX_IIR(pipe)));
3315
3316 /* Try each vswing and preemphasis setting twice before moving on */
3317 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3318 /* disable first in case we need to retry */
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3322 temp &= ~FDI_TX_ENABLE;
3323 I915_WRITE(reg, temp);
3324
3325 reg = FDI_RX_CTL(pipe);
3326 temp = I915_READ(reg);
3327 temp &= ~FDI_LINK_TRAIN_AUTO;
3328 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3329 temp &= ~FDI_RX_ENABLE;
3330 I915_WRITE(reg, temp);
3331
3332 /* enable CPU FDI TX and PCH FDI RX */
3333 reg = FDI_TX_CTL(pipe);
3334 temp = I915_READ(reg);
3335 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3336 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3337 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3338 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3339 temp |= snb_b_fdi_train_param[j/2];
3340 temp |= FDI_COMPOSITE_SYNC;
3341 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3342
3343 I915_WRITE(FDI_RX_MISC(pipe),
3344 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3345
3346 reg = FDI_RX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3349 temp |= FDI_COMPOSITE_SYNC;
3350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3351
3352 POSTING_READ(reg);
3353 udelay(1); /* should be 0.5us */
3354
3355 for (i = 0; i < 4; i++) {
3356 reg = FDI_RX_IIR(pipe);
3357 temp = I915_READ(reg);
3358 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3359
3360 if (temp & FDI_RX_BIT_LOCK ||
3361 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3362 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3363 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3364 i);
3365 break;
3366 }
3367 udelay(1); /* should be 0.5us */
3368 }
3369 if (i == 4) {
3370 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3371 continue;
3372 }
3373
3374 /* Train 2 */
3375 reg = FDI_TX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3378 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3379 I915_WRITE(reg, temp);
3380
3381 reg = FDI_RX_CTL(pipe);
3382 temp = I915_READ(reg);
3383 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3384 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3385 I915_WRITE(reg, temp);
3386
3387 POSTING_READ(reg);
3388 udelay(2); /* should be 1.5us */
3389
3390 for (i = 0; i < 4; i++) {
3391 reg = FDI_RX_IIR(pipe);
3392 temp = I915_READ(reg);
3393 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3394
3395 if (temp & FDI_RX_SYMBOL_LOCK ||
3396 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3397 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3398 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3399 i);
3400 goto train_done;
3401 }
3402 udelay(2); /* should be 1.5us */
3403 }
3404 if (i == 4)
3405 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3406 }
3407
3408 train_done:
3409 DRM_DEBUG_KMS("FDI train done.\n");
3410 }
3411
3412 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3413 {
3414 struct drm_device *dev = intel_crtc->base.dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 int pipe = intel_crtc->pipe;
3417 u32 reg, temp;
3418
3419
3420 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3421 reg = FDI_RX_CTL(pipe);
3422 temp = I915_READ(reg);
3423 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3424 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3425 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3426 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(200);
3430
3431 /* Switch from Rawclk to PCDclk */
3432 temp = I915_READ(reg);
3433 I915_WRITE(reg, temp | FDI_PCDCLK);
3434
3435 POSTING_READ(reg);
3436 udelay(200);
3437
3438 /* Enable CPU FDI TX PLL, always on for Ironlake */
3439 reg = FDI_TX_CTL(pipe);
3440 temp = I915_READ(reg);
3441 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3442 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3443
3444 POSTING_READ(reg);
3445 udelay(100);
3446 }
3447 }
3448
3449 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3450 {
3451 struct drm_device *dev = intel_crtc->base.dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 int pipe = intel_crtc->pipe;
3454 u32 reg, temp;
3455
3456 /* Switch from PCDclk to Rawclk */
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3460
3461 /* Disable CPU FDI TX PLL */
3462 reg = FDI_TX_CTL(pipe);
3463 temp = I915_READ(reg);
3464 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3465
3466 POSTING_READ(reg);
3467 udelay(100);
3468
3469 reg = FDI_RX_CTL(pipe);
3470 temp = I915_READ(reg);
3471 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3472
3473 /* Wait for the clocks to turn off. */
3474 POSTING_READ(reg);
3475 udelay(100);
3476 }
3477
3478 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3479 {
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
3484 u32 reg, temp;
3485
3486 /* disable CPU FDI tx and PCH FDI rx */
3487 reg = FDI_TX_CTL(pipe);
3488 temp = I915_READ(reg);
3489 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3490 POSTING_READ(reg);
3491
3492 reg = FDI_RX_CTL(pipe);
3493 temp = I915_READ(reg);
3494 temp &= ~(0x7 << 16);
3495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500
3501 /* Ironlake workaround, disable clock pointer after downing FDI */
3502 if (HAS_PCH_IBX(dev))
3503 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3504
3505 /* still set train pattern 1 */
3506 reg = FDI_TX_CTL(pipe);
3507 temp = I915_READ(reg);
3508 temp &= ~FDI_LINK_TRAIN_NONE;
3509 temp |= FDI_LINK_TRAIN_PATTERN_1;
3510 I915_WRITE(reg, temp);
3511
3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517 } else {
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 }
3521 /* BPC in FDI rx is consistent with that in PIPECONF */
3522 temp &= ~(0x07 << 16);
3523 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3524 I915_WRITE(reg, temp);
3525
3526 POSTING_READ(reg);
3527 udelay(100);
3528 }
3529
3530 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3531 {
3532 struct intel_crtc *crtc;
3533
3534 /* Note that we don't need to be called with mode_config.lock here
3535 * as our list of CRTC objects is static for the lifetime of the
3536 * device and so cannot disappear as we iterate. Similarly, we can
3537 * happily treat the predicates as racy, atomic checks as userspace
3538 * cannot claim and pin a new fb without at least acquring the
3539 * struct_mutex and so serialising with us.
3540 */
3541 for_each_intel_crtc(dev, crtc) {
3542 if (atomic_read(&crtc->unpin_work_count) == 0)
3543 continue;
3544
3545 if (crtc->unpin_work)
3546 intel_wait_for_vblank(dev, crtc->pipe);
3547
3548 return true;
3549 }
3550
3551 return false;
3552 }
3553
3554 static void page_flip_completed(struct intel_crtc *intel_crtc)
3555 {
3556 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3557 struct intel_unpin_work *work = intel_crtc->unpin_work;
3558
3559 /* ensure that the unpin work is consistent wrt ->pending. */
3560 smp_rmb();
3561 intel_crtc->unpin_work = NULL;
3562
3563 if (work->event)
3564 drm_send_vblank_event(intel_crtc->base.dev,
3565 intel_crtc->pipe,
3566 work->event);
3567
3568 drm_crtc_vblank_put(&intel_crtc->base);
3569
3570 wake_up_all(&dev_priv->pending_flip_queue);
3571 queue_work(dev_priv->wq, &work->work);
3572
3573 trace_i915_flip_complete(intel_crtc->plane,
3574 work->pending_flip_obj);
3575 }
3576
3577 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3578 {
3579 struct drm_device *dev = crtc->dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3583 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3584 !intel_crtc_has_pending_flip(crtc),
3585 60*HZ) == 0)) {
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587
3588 spin_lock_irq(&dev->event_lock);
3589 if (intel_crtc->unpin_work) {
3590 WARN_ONCE(1, "Removing stuck page flip\n");
3591 page_flip_completed(intel_crtc);
3592 }
3593 spin_unlock_irq(&dev->event_lock);
3594 }
3595
3596 if (crtc->primary->fb) {
3597 mutex_lock(&dev->struct_mutex);
3598 intel_finish_fb(crtc->primary->fb);
3599 mutex_unlock(&dev->struct_mutex);
3600 }
3601 }
3602
3603 /* Program iCLKIP clock to the desired frequency */
3604 static void lpt_program_iclkip(struct drm_crtc *crtc)
3605 {
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3609 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3610 u32 temp;
3611
3612 mutex_lock(&dev_priv->dpio_lock);
3613
3614 /* It is necessary to ungate the pixclk gate prior to programming
3615 * the divisors, and gate it back when it is done.
3616 */
3617 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3618
3619 /* Disable SSCCTL */
3620 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3621 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3622 SBI_SSCCTL_DISABLE,
3623 SBI_ICLK);
3624
3625 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3626 if (clock == 20000) {
3627 auxdiv = 1;
3628 divsel = 0x41;
3629 phaseinc = 0x20;
3630 } else {
3631 /* The iCLK virtual clock root frequency is in MHz,
3632 * but the adjusted_mode->crtc_clock in in KHz. To get the
3633 * divisors, it is necessary to divide one by another, so we
3634 * convert the virtual clock precision to KHz here for higher
3635 * precision.
3636 */
3637 u32 iclk_virtual_root_freq = 172800 * 1000;
3638 u32 iclk_pi_range = 64;
3639 u32 desired_divisor, msb_divisor_value, pi_value;
3640
3641 desired_divisor = (iclk_virtual_root_freq / clock);
3642 msb_divisor_value = desired_divisor / iclk_pi_range;
3643 pi_value = desired_divisor % iclk_pi_range;
3644
3645 auxdiv = 0;
3646 divsel = msb_divisor_value - 2;
3647 phaseinc = pi_value;
3648 }
3649
3650 /* This should not happen with any sane values */
3651 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3652 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3653 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3654 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3655
3656 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3657 clock,
3658 auxdiv,
3659 divsel,
3660 phasedir,
3661 phaseinc);
3662
3663 /* Program SSCDIVINTPHASE6 */
3664 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3665 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3666 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3667 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3668 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3669 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3670 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3671 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3672
3673 /* Program SSCAUXDIV */
3674 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3675 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3676 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3677 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3678
3679 /* Enable modulator and associated divider */
3680 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3681 temp &= ~SBI_SSCCTL_DISABLE;
3682 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3683
3684 /* Wait for initialization time */
3685 udelay(24);
3686
3687 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3688
3689 mutex_unlock(&dev_priv->dpio_lock);
3690 }
3691
3692 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3693 enum pipe pch_transcoder)
3694 {
3695 struct drm_device *dev = crtc->base.dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3698
3699 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3700 I915_READ(HTOTAL(cpu_transcoder)));
3701 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3702 I915_READ(HBLANK(cpu_transcoder)));
3703 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3704 I915_READ(HSYNC(cpu_transcoder)));
3705
3706 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3707 I915_READ(VTOTAL(cpu_transcoder)));
3708 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3709 I915_READ(VBLANK(cpu_transcoder)));
3710 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3711 I915_READ(VSYNC(cpu_transcoder)));
3712 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3713 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3714 }
3715
3716 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3717 {
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 uint32_t temp;
3720
3721 temp = I915_READ(SOUTH_CHICKEN1);
3722 if (temp & FDI_BC_BIFURCATION_SELECT)
3723 return;
3724
3725 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3726 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3727
3728 temp |= FDI_BC_BIFURCATION_SELECT;
3729 DRM_DEBUG_KMS("enabling fdi C rx\n");
3730 I915_WRITE(SOUTH_CHICKEN1, temp);
3731 POSTING_READ(SOUTH_CHICKEN1);
3732 }
3733
3734 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3735 {
3736 struct drm_device *dev = intel_crtc->base.dev;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738
3739 switch (intel_crtc->pipe) {
3740 case PIPE_A:
3741 break;
3742 case PIPE_B:
3743 if (intel_crtc->config->fdi_lanes > 2)
3744 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3745 else
3746 cpt_enable_fdi_bc_bifurcation(dev);
3747
3748 break;
3749 case PIPE_C:
3750 cpt_enable_fdi_bc_bifurcation(dev);
3751
3752 break;
3753 default:
3754 BUG();
3755 }
3756 }
3757
3758 /*
3759 * Enable PCH resources required for PCH ports:
3760 * - PCH PLLs
3761 * - FDI training & RX/TX
3762 * - update transcoder timings
3763 * - DP transcoding bits
3764 * - transcoder
3765 */
3766 static void ironlake_pch_enable(struct drm_crtc *crtc)
3767 {
3768 struct drm_device *dev = crtc->dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
3770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3771 int pipe = intel_crtc->pipe;
3772 u32 reg, temp;
3773
3774 assert_pch_transcoder_disabled(dev_priv, pipe);
3775
3776 if (IS_IVYBRIDGE(dev))
3777 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3778
3779 /* Write the TU size bits before fdi link training, so that error
3780 * detection works. */
3781 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3782 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3783
3784 /* For PCH output, training FDI link */
3785 dev_priv->display.fdi_link_train(crtc);
3786
3787 /* We need to program the right clock selection before writing the pixel
3788 * mutliplier into the DPLL. */
3789 if (HAS_PCH_CPT(dev)) {
3790 u32 sel;
3791
3792 temp = I915_READ(PCH_DPLL_SEL);
3793 temp |= TRANS_DPLL_ENABLE(pipe);
3794 sel = TRANS_DPLLB_SEL(pipe);
3795 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3796 temp |= sel;
3797 else
3798 temp &= ~sel;
3799 I915_WRITE(PCH_DPLL_SEL, temp);
3800 }
3801
3802 /* XXX: pch pll's can be enabled any time before we enable the PCH
3803 * transcoder, and we actually should do this to not upset any PCH
3804 * transcoder that already use the clock when we share it.
3805 *
3806 * Note that enable_shared_dpll tries to do the right thing, but
3807 * get_shared_dpll unconditionally resets the pll - we need that to have
3808 * the right LVDS enable sequence. */
3809 intel_enable_shared_dpll(intel_crtc);
3810
3811 /* set transcoder timing, panel must allow it */
3812 assert_panel_unlocked(dev_priv, pipe);
3813 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3814
3815 intel_fdi_normal_train(crtc);
3816
3817 /* For PCH DP, enable TRANS_DP_CTL */
3818 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3819 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3820 reg = TRANS_DP_CTL(pipe);
3821 temp = I915_READ(reg);
3822 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3823 TRANS_DP_SYNC_MASK |
3824 TRANS_DP_BPC_MASK);
3825 temp |= (TRANS_DP_OUTPUT_ENABLE |
3826 TRANS_DP_ENH_FRAMING);
3827 temp |= bpc << 9; /* same format but at 11:9 */
3828
3829 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3830 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3831 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3832 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3833
3834 switch (intel_trans_dp_port_sel(crtc)) {
3835 case PCH_DP_B:
3836 temp |= TRANS_DP_PORT_SEL_B;
3837 break;
3838 case PCH_DP_C:
3839 temp |= TRANS_DP_PORT_SEL_C;
3840 break;
3841 case PCH_DP_D:
3842 temp |= TRANS_DP_PORT_SEL_D;
3843 break;
3844 default:
3845 BUG();
3846 }
3847
3848 I915_WRITE(reg, temp);
3849 }
3850
3851 ironlake_enable_pch_transcoder(dev_priv, pipe);
3852 }
3853
3854 static void lpt_pch_enable(struct drm_crtc *crtc)
3855 {
3856 struct drm_device *dev = crtc->dev;
3857 struct drm_i915_private *dev_priv = dev->dev_private;
3858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3860
3861 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3862
3863 lpt_program_iclkip(crtc);
3864
3865 /* Set transcoder timing. */
3866 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3867
3868 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3869 }
3870
3871 void intel_put_shared_dpll(struct intel_crtc *crtc)
3872 {
3873 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3874
3875 if (pll == NULL)
3876 return;
3877
3878 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3879 WARN(1, "bad %s crtc mask\n", pll->name);
3880 return;
3881 }
3882
3883 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3884 if (pll->config.crtc_mask == 0) {
3885 WARN_ON(pll->on);
3886 WARN_ON(pll->active);
3887 }
3888
3889 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3890 }
3891
3892 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3893 struct intel_crtc_state *crtc_state)
3894 {
3895 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3896 struct intel_shared_dpll *pll;
3897 enum intel_dpll_id i;
3898
3899 if (HAS_PCH_IBX(dev_priv->dev)) {
3900 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3901 i = (enum intel_dpll_id) crtc->pipe;
3902 pll = &dev_priv->shared_dplls[i];
3903
3904 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3905 crtc->base.base.id, pll->name);
3906
3907 WARN_ON(pll->new_config->crtc_mask);
3908
3909 goto found;
3910 }
3911
3912 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3913 pll = &dev_priv->shared_dplls[i];
3914
3915 /* Only want to check enabled timings first */
3916 if (pll->new_config->crtc_mask == 0)
3917 continue;
3918
3919 if (memcmp(&crtc_state->dpll_hw_state,
3920 &pll->new_config->hw_state,
3921 sizeof(pll->new_config->hw_state)) == 0) {
3922 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3923 crtc->base.base.id, pll->name,
3924 pll->new_config->crtc_mask,
3925 pll->active);
3926 goto found;
3927 }
3928 }
3929
3930 /* Ok no matching timings, maybe there's a free one? */
3931 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3932 pll = &dev_priv->shared_dplls[i];
3933 if (pll->new_config->crtc_mask == 0) {
3934 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3935 crtc->base.base.id, pll->name);
3936 goto found;
3937 }
3938 }
3939
3940 return NULL;
3941
3942 found:
3943 if (pll->new_config->crtc_mask == 0)
3944 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3945
3946 crtc_state->shared_dpll = i;
3947 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3948 pipe_name(crtc->pipe));
3949
3950 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3951
3952 return pll;
3953 }
3954
3955 /**
3956 * intel_shared_dpll_start_config - start a new PLL staged config
3957 * @dev_priv: DRM device
3958 * @clear_pipes: mask of pipes that will have their PLLs freed
3959 *
3960 * Starts a new PLL staged config, copying the current config but
3961 * releasing the references of pipes specified in clear_pipes.
3962 */
3963 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3964 unsigned clear_pipes)
3965 {
3966 struct intel_shared_dpll *pll;
3967 enum intel_dpll_id i;
3968
3969 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3970 pll = &dev_priv->shared_dplls[i];
3971
3972 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3973 GFP_KERNEL);
3974 if (!pll->new_config)
3975 goto cleanup;
3976
3977 pll->new_config->crtc_mask &= ~clear_pipes;
3978 }
3979
3980 return 0;
3981
3982 cleanup:
3983 while (--i >= 0) {
3984 pll = &dev_priv->shared_dplls[i];
3985 kfree(pll->new_config);
3986 pll->new_config = NULL;
3987 }
3988
3989 return -ENOMEM;
3990 }
3991
3992 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3993 {
3994 struct intel_shared_dpll *pll;
3995 enum intel_dpll_id i;
3996
3997 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3998 pll = &dev_priv->shared_dplls[i];
3999
4000 WARN_ON(pll->new_config == &pll->config);
4001
4002 pll->config = *pll->new_config;
4003 kfree(pll->new_config);
4004 pll->new_config = NULL;
4005 }
4006 }
4007
4008 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4009 {
4010 struct intel_shared_dpll *pll;
4011 enum intel_dpll_id i;
4012
4013 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4014 pll = &dev_priv->shared_dplls[i];
4015
4016 WARN_ON(pll->new_config == &pll->config);
4017
4018 kfree(pll->new_config);
4019 pll->new_config = NULL;
4020 }
4021 }
4022
4023 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4024 {
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4026 int dslreg = PIPEDSL(pipe);
4027 u32 temp;
4028
4029 temp = I915_READ(dslreg);
4030 udelay(500);
4031 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4032 if (wait_for(I915_READ(dslreg) != temp, 5))
4033 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4034 }
4035 }
4036
4037 static void skylake_pfit_enable(struct intel_crtc *crtc)
4038 {
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 int pipe = crtc->pipe;
4042
4043 if (crtc->config->pch_pfit.enabled) {
4044 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4045 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4046 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4047 }
4048 }
4049
4050 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4051 {
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
4054 int pipe = crtc->pipe;
4055
4056 if (crtc->config->pch_pfit.enabled) {
4057 /* Force use of hard-coded filter coefficients
4058 * as some pre-programmed values are broken,
4059 * e.g. x201.
4060 */
4061 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4062 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4063 PF_PIPE_SEL_IVB(pipe));
4064 else
4065 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4066 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4067 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4068 }
4069 }
4070
4071 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->dev;
4074 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4075 struct drm_plane *plane;
4076 struct intel_plane *intel_plane;
4077
4078 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4079 intel_plane = to_intel_plane(plane);
4080 if (intel_plane->pipe == pipe)
4081 intel_plane_restore(&intel_plane->base);
4082 }
4083 }
4084
4085 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4086 {
4087 struct drm_device *dev = crtc->dev;
4088 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4089 struct drm_plane *plane;
4090 struct intel_plane *intel_plane;
4091
4092 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4093 intel_plane = to_intel_plane(plane);
4094 if (intel_plane->pipe == pipe)
4095 plane->funcs->disable_plane(plane);
4096 }
4097 }
4098
4099 void hsw_enable_ips(struct intel_crtc *crtc)
4100 {
4101 struct drm_device *dev = crtc->base.dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103
4104 if (!crtc->config->ips_enabled)
4105 return;
4106
4107 /* We can only enable IPS after we enable a plane and wait for a vblank */
4108 intel_wait_for_vblank(dev, crtc->pipe);
4109
4110 assert_plane_enabled(dev_priv, crtc->plane);
4111 if (IS_BROADWELL(dev)) {
4112 mutex_lock(&dev_priv->rps.hw_lock);
4113 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4114 mutex_unlock(&dev_priv->rps.hw_lock);
4115 /* Quoting Art Runyan: "its not safe to expect any particular
4116 * value in IPS_CTL bit 31 after enabling IPS through the
4117 * mailbox." Moreover, the mailbox may return a bogus state,
4118 * so we need to just enable it and continue on.
4119 */
4120 } else {
4121 I915_WRITE(IPS_CTL, IPS_ENABLE);
4122 /* The bit only becomes 1 in the next vblank, so this wait here
4123 * is essentially intel_wait_for_vblank. If we don't have this
4124 * and don't wait for vblanks until the end of crtc_enable, then
4125 * the HW state readout code will complain that the expected
4126 * IPS_CTL value is not the one we read. */
4127 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4128 DRM_ERROR("Timed out waiting for IPS enable\n");
4129 }
4130 }
4131
4132 void hsw_disable_ips(struct intel_crtc *crtc)
4133 {
4134 struct drm_device *dev = crtc->base.dev;
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136
4137 if (!crtc->config->ips_enabled)
4138 return;
4139
4140 assert_plane_enabled(dev_priv, crtc->plane);
4141 if (IS_BROADWELL(dev)) {
4142 mutex_lock(&dev_priv->rps.hw_lock);
4143 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4144 mutex_unlock(&dev_priv->rps.hw_lock);
4145 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4146 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4147 DRM_ERROR("Timed out waiting for IPS disable\n");
4148 } else {
4149 I915_WRITE(IPS_CTL, 0);
4150 POSTING_READ(IPS_CTL);
4151 }
4152
4153 /* We need to wait for a vblank before we can disable the plane. */
4154 intel_wait_for_vblank(dev, crtc->pipe);
4155 }
4156
4157 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4158 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4159 {
4160 struct drm_device *dev = crtc->dev;
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4163 enum pipe pipe = intel_crtc->pipe;
4164 int palreg = PALETTE(pipe);
4165 int i;
4166 bool reenable_ips = false;
4167
4168 /* The clocks have to be on to load the palette. */
4169 if (!crtc->enabled || !intel_crtc->active)
4170 return;
4171
4172 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4173 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4174 assert_dsi_pll_enabled(dev_priv);
4175 else
4176 assert_pll_enabled(dev_priv, pipe);
4177 }
4178
4179 /* use legacy palette for Ironlake */
4180 if (!HAS_GMCH_DISPLAY(dev))
4181 palreg = LGC_PALETTE(pipe);
4182
4183 /* Workaround : Do not read or write the pipe palette/gamma data while
4184 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4185 */
4186 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4187 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4188 GAMMA_MODE_MODE_SPLIT)) {
4189 hsw_disable_ips(intel_crtc);
4190 reenable_ips = true;
4191 }
4192
4193 for (i = 0; i < 256; i++) {
4194 I915_WRITE(palreg + 4 * i,
4195 (intel_crtc->lut_r[i] << 16) |
4196 (intel_crtc->lut_g[i] << 8) |
4197 intel_crtc->lut_b[i]);
4198 }
4199
4200 if (reenable_ips)
4201 hsw_enable_ips(intel_crtc);
4202 }
4203
4204 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4205 {
4206 if (!enable && intel_crtc->overlay) {
4207 struct drm_device *dev = intel_crtc->base.dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209
4210 mutex_lock(&dev->struct_mutex);
4211 dev_priv->mm.interruptible = false;
4212 (void) intel_overlay_switch_off(intel_crtc->overlay);
4213 dev_priv->mm.interruptible = true;
4214 mutex_unlock(&dev->struct_mutex);
4215 }
4216
4217 /* Let userspace switch the overlay on again. In most cases userspace
4218 * has to recompute where to put it anyway.
4219 */
4220 }
4221
4222 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4223 {
4224 struct drm_device *dev = crtc->dev;
4225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4226 int pipe = intel_crtc->pipe;
4227
4228 intel_enable_primary_hw_plane(crtc->primary, crtc);
4229 intel_enable_sprite_planes(crtc);
4230 intel_crtc_update_cursor(crtc, true);
4231 intel_crtc_dpms_overlay(intel_crtc, true);
4232
4233 hsw_enable_ips(intel_crtc);
4234
4235 mutex_lock(&dev->struct_mutex);
4236 intel_fbc_update(dev);
4237 mutex_unlock(&dev->struct_mutex);
4238
4239 /*
4240 * FIXME: Once we grow proper nuclear flip support out of this we need
4241 * to compute the mask of flip planes precisely. For the time being
4242 * consider this a flip from a NULL plane.
4243 */
4244 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4245 }
4246
4247 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4248 {
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4252 int pipe = intel_crtc->pipe;
4253 int plane = intel_crtc->plane;
4254
4255 intel_crtc_wait_for_pending_flips(crtc);
4256
4257 if (dev_priv->fbc.plane == plane)
4258 intel_fbc_disable(dev);
4259
4260 hsw_disable_ips(intel_crtc);
4261
4262 intel_crtc_dpms_overlay(intel_crtc, false);
4263 intel_crtc_update_cursor(crtc, false);
4264 intel_disable_sprite_planes(crtc);
4265 intel_disable_primary_hw_plane(crtc->primary, crtc);
4266
4267 /*
4268 * FIXME: Once we grow proper nuclear flip support out of this we need
4269 * to compute the mask of flip planes precisely. For the time being
4270 * consider this a flip to a NULL plane.
4271 */
4272 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4273 }
4274
4275 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4276 {
4277 struct drm_device *dev = crtc->dev;
4278 struct drm_i915_private *dev_priv = dev->dev_private;
4279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4280 struct intel_encoder *encoder;
4281 int pipe = intel_crtc->pipe;
4282
4283 WARN_ON(!crtc->enabled);
4284
4285 if (intel_crtc->active)
4286 return;
4287
4288 if (intel_crtc->config->has_pch_encoder)
4289 intel_prepare_shared_dpll(intel_crtc);
4290
4291 if (intel_crtc->config->has_dp_encoder)
4292 intel_dp_set_m_n(intel_crtc);
4293
4294 intel_set_pipe_timings(intel_crtc);
4295
4296 if (intel_crtc->config->has_pch_encoder) {
4297 intel_cpu_transcoder_set_m_n(intel_crtc,
4298 &intel_crtc->config->fdi_m_n, NULL);
4299 }
4300
4301 ironlake_set_pipeconf(crtc);
4302
4303 intel_crtc->active = true;
4304
4305 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4306 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4307
4308 for_each_encoder_on_crtc(dev, crtc, encoder)
4309 if (encoder->pre_enable)
4310 encoder->pre_enable(encoder);
4311
4312 if (intel_crtc->config->has_pch_encoder) {
4313 /* Note: FDI PLL enabling _must_ be done before we enable the
4314 * cpu pipes, hence this is separate from all the other fdi/pch
4315 * enabling. */
4316 ironlake_fdi_pll_enable(intel_crtc);
4317 } else {
4318 assert_fdi_tx_disabled(dev_priv, pipe);
4319 assert_fdi_rx_disabled(dev_priv, pipe);
4320 }
4321
4322 ironlake_pfit_enable(intel_crtc);
4323
4324 /*
4325 * On ILK+ LUT must be loaded before the pipe is running but with
4326 * clocks enabled
4327 */
4328 intel_crtc_load_lut(crtc);
4329
4330 intel_update_watermarks(crtc);
4331 intel_enable_pipe(intel_crtc);
4332
4333 if (intel_crtc->config->has_pch_encoder)
4334 ironlake_pch_enable(crtc);
4335
4336 assert_vblank_disabled(crtc);
4337 drm_crtc_vblank_on(crtc);
4338
4339 for_each_encoder_on_crtc(dev, crtc, encoder)
4340 encoder->enable(encoder);
4341
4342 if (HAS_PCH_CPT(dev))
4343 cpt_verify_modeset(dev, intel_crtc->pipe);
4344
4345 intel_crtc_enable_planes(crtc);
4346 }
4347
4348 /* IPS only exists on ULT machines and is tied to pipe A. */
4349 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4350 {
4351 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4352 }
4353
4354 /*
4355 * This implements the workaround described in the "notes" section of the mode
4356 * set sequence documentation. When going from no pipes or single pipe to
4357 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4358 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4359 */
4360 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4361 {
4362 struct drm_device *dev = crtc->base.dev;
4363 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4364
4365 /* We want to get the other_active_crtc only if there's only 1 other
4366 * active crtc. */
4367 for_each_intel_crtc(dev, crtc_it) {
4368 if (!crtc_it->active || crtc_it == crtc)
4369 continue;
4370
4371 if (other_active_crtc)
4372 return;
4373
4374 other_active_crtc = crtc_it;
4375 }
4376 if (!other_active_crtc)
4377 return;
4378
4379 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4380 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4381 }
4382
4383 static void haswell_crtc_enable(struct drm_crtc *crtc)
4384 {
4385 struct drm_device *dev = crtc->dev;
4386 struct drm_i915_private *dev_priv = dev->dev_private;
4387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4388 struct intel_encoder *encoder;
4389 int pipe = intel_crtc->pipe;
4390
4391 WARN_ON(!crtc->enabled);
4392
4393 if (intel_crtc->active)
4394 return;
4395
4396 if (intel_crtc_to_shared_dpll(intel_crtc))
4397 intel_enable_shared_dpll(intel_crtc);
4398
4399 if (intel_crtc->config->has_dp_encoder)
4400 intel_dp_set_m_n(intel_crtc);
4401
4402 intel_set_pipe_timings(intel_crtc);
4403
4404 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4405 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4406 intel_crtc->config->pixel_multiplier - 1);
4407 }
4408
4409 if (intel_crtc->config->has_pch_encoder) {
4410 intel_cpu_transcoder_set_m_n(intel_crtc,
4411 &intel_crtc->config->fdi_m_n, NULL);
4412 }
4413
4414 haswell_set_pipeconf(crtc);
4415
4416 intel_set_pipe_csc(crtc);
4417
4418 intel_crtc->active = true;
4419
4420 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4421 for_each_encoder_on_crtc(dev, crtc, encoder)
4422 if (encoder->pre_enable)
4423 encoder->pre_enable(encoder);
4424
4425 if (intel_crtc->config->has_pch_encoder) {
4426 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4427 true);
4428 dev_priv->display.fdi_link_train(crtc);
4429 }
4430
4431 intel_ddi_enable_pipe_clock(intel_crtc);
4432
4433 if (IS_SKYLAKE(dev))
4434 skylake_pfit_enable(intel_crtc);
4435 else
4436 ironlake_pfit_enable(intel_crtc);
4437
4438 /*
4439 * On ILK+ LUT must be loaded before the pipe is running but with
4440 * clocks enabled
4441 */
4442 intel_crtc_load_lut(crtc);
4443
4444 intel_ddi_set_pipe_settings(crtc);
4445 intel_ddi_enable_transcoder_func(crtc);
4446
4447 intel_update_watermarks(crtc);
4448 intel_enable_pipe(intel_crtc);
4449
4450 if (intel_crtc->config->has_pch_encoder)
4451 lpt_pch_enable(crtc);
4452
4453 if (intel_crtc->config->dp_encoder_is_mst)
4454 intel_ddi_set_vc_payload_alloc(crtc, true);
4455
4456 assert_vblank_disabled(crtc);
4457 drm_crtc_vblank_on(crtc);
4458
4459 for_each_encoder_on_crtc(dev, crtc, encoder) {
4460 encoder->enable(encoder);
4461 intel_opregion_notify_encoder(encoder, true);
4462 }
4463
4464 /* If we change the relative order between pipe/planes enabling, we need
4465 * to change the workaround. */
4466 haswell_mode_set_planes_workaround(intel_crtc);
4467 intel_crtc_enable_planes(crtc);
4468 }
4469
4470 static void skylake_pfit_disable(struct intel_crtc *crtc)
4471 {
4472 struct drm_device *dev = crtc->base.dev;
4473 struct drm_i915_private *dev_priv = dev->dev_private;
4474 int pipe = crtc->pipe;
4475
4476 /* To avoid upsetting the power well on haswell only disable the pfit if
4477 * it's in use. The hw state code will make sure we get this right. */
4478 if (crtc->config->pch_pfit.enabled) {
4479 I915_WRITE(PS_CTL(pipe), 0);
4480 I915_WRITE(PS_WIN_POS(pipe), 0);
4481 I915_WRITE(PS_WIN_SZ(pipe), 0);
4482 }
4483 }
4484
4485 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4486 {
4487 struct drm_device *dev = crtc->base.dev;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 int pipe = crtc->pipe;
4490
4491 /* To avoid upsetting the power well on haswell only disable the pfit if
4492 * it's in use. The hw state code will make sure we get this right. */
4493 if (crtc->config->pch_pfit.enabled) {
4494 I915_WRITE(PF_CTL(pipe), 0);
4495 I915_WRITE(PF_WIN_POS(pipe), 0);
4496 I915_WRITE(PF_WIN_SZ(pipe), 0);
4497 }
4498 }
4499
4500 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4501 {
4502 struct drm_device *dev = crtc->dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4505 struct intel_encoder *encoder;
4506 int pipe = intel_crtc->pipe;
4507 u32 reg, temp;
4508
4509 if (!intel_crtc->active)
4510 return;
4511
4512 intel_crtc_disable_planes(crtc);
4513
4514 for_each_encoder_on_crtc(dev, crtc, encoder)
4515 encoder->disable(encoder);
4516
4517 drm_crtc_vblank_off(crtc);
4518 assert_vblank_disabled(crtc);
4519
4520 if (intel_crtc->config->has_pch_encoder)
4521 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4522
4523 intel_disable_pipe(intel_crtc);
4524
4525 ironlake_pfit_disable(intel_crtc);
4526
4527 for_each_encoder_on_crtc(dev, crtc, encoder)
4528 if (encoder->post_disable)
4529 encoder->post_disable(encoder);
4530
4531 if (intel_crtc->config->has_pch_encoder) {
4532 ironlake_fdi_disable(crtc);
4533
4534 ironlake_disable_pch_transcoder(dev_priv, pipe);
4535
4536 if (HAS_PCH_CPT(dev)) {
4537 /* disable TRANS_DP_CTL */
4538 reg = TRANS_DP_CTL(pipe);
4539 temp = I915_READ(reg);
4540 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4541 TRANS_DP_PORT_SEL_MASK);
4542 temp |= TRANS_DP_PORT_SEL_NONE;
4543 I915_WRITE(reg, temp);
4544
4545 /* disable DPLL_SEL */
4546 temp = I915_READ(PCH_DPLL_SEL);
4547 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4548 I915_WRITE(PCH_DPLL_SEL, temp);
4549 }
4550
4551 /* disable PCH DPLL */
4552 intel_disable_shared_dpll(intel_crtc);
4553
4554 ironlake_fdi_pll_disable(intel_crtc);
4555 }
4556
4557 intel_crtc->active = false;
4558 intel_update_watermarks(crtc);
4559
4560 mutex_lock(&dev->struct_mutex);
4561 intel_fbc_update(dev);
4562 mutex_unlock(&dev->struct_mutex);
4563 }
4564
4565 static void haswell_crtc_disable(struct drm_crtc *crtc)
4566 {
4567 struct drm_device *dev = crtc->dev;
4568 struct drm_i915_private *dev_priv = dev->dev_private;
4569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4570 struct intel_encoder *encoder;
4571 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4572
4573 if (!intel_crtc->active)
4574 return;
4575
4576 intel_crtc_disable_planes(crtc);
4577
4578 for_each_encoder_on_crtc(dev, crtc, encoder) {
4579 intel_opregion_notify_encoder(encoder, false);
4580 encoder->disable(encoder);
4581 }
4582
4583 drm_crtc_vblank_off(crtc);
4584 assert_vblank_disabled(crtc);
4585
4586 if (intel_crtc->config->has_pch_encoder)
4587 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4588 false);
4589 intel_disable_pipe(intel_crtc);
4590
4591 if (intel_crtc->config->dp_encoder_is_mst)
4592 intel_ddi_set_vc_payload_alloc(crtc, false);
4593
4594 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4595
4596 if (IS_SKYLAKE(dev))
4597 skylake_pfit_disable(intel_crtc);
4598 else
4599 ironlake_pfit_disable(intel_crtc);
4600
4601 intel_ddi_disable_pipe_clock(intel_crtc);
4602
4603 if (intel_crtc->config->has_pch_encoder) {
4604 lpt_disable_pch_transcoder(dev_priv);
4605 intel_ddi_fdi_disable(crtc);
4606 }
4607
4608 for_each_encoder_on_crtc(dev, crtc, encoder)
4609 if (encoder->post_disable)
4610 encoder->post_disable(encoder);
4611
4612 intel_crtc->active = false;
4613 intel_update_watermarks(crtc);
4614
4615 mutex_lock(&dev->struct_mutex);
4616 intel_fbc_update(dev);
4617 mutex_unlock(&dev->struct_mutex);
4618
4619 if (intel_crtc_to_shared_dpll(intel_crtc))
4620 intel_disable_shared_dpll(intel_crtc);
4621 }
4622
4623 static void ironlake_crtc_off(struct drm_crtc *crtc)
4624 {
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 intel_put_shared_dpll(intel_crtc);
4627 }
4628
4629
4630 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4631 {
4632 struct drm_device *dev = crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 struct intel_crtc_state *pipe_config = crtc->config;
4635
4636 if (!pipe_config->gmch_pfit.control)
4637 return;
4638
4639 /*
4640 * The panel fitter should only be adjusted whilst the pipe is disabled,
4641 * according to register description and PRM.
4642 */
4643 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4644 assert_pipe_disabled(dev_priv, crtc->pipe);
4645
4646 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4647 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4648
4649 /* Border color in case we don't scale up to the full screen. Black by
4650 * default, change to something else for debugging. */
4651 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4652 }
4653
4654 static enum intel_display_power_domain port_to_power_domain(enum port port)
4655 {
4656 switch (port) {
4657 case PORT_A:
4658 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4659 case PORT_B:
4660 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4661 case PORT_C:
4662 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4663 case PORT_D:
4664 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4665 default:
4666 WARN_ON_ONCE(1);
4667 return POWER_DOMAIN_PORT_OTHER;
4668 }
4669 }
4670
4671 #define for_each_power_domain(domain, mask) \
4672 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4673 if ((1 << (domain)) & (mask))
4674
4675 enum intel_display_power_domain
4676 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4677 {
4678 struct drm_device *dev = intel_encoder->base.dev;
4679 struct intel_digital_port *intel_dig_port;
4680
4681 switch (intel_encoder->type) {
4682 case INTEL_OUTPUT_UNKNOWN:
4683 /* Only DDI platforms should ever use this output type */
4684 WARN_ON_ONCE(!HAS_DDI(dev));
4685 case INTEL_OUTPUT_DISPLAYPORT:
4686 case INTEL_OUTPUT_HDMI:
4687 case INTEL_OUTPUT_EDP:
4688 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4689 return port_to_power_domain(intel_dig_port->port);
4690 case INTEL_OUTPUT_DP_MST:
4691 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4692 return port_to_power_domain(intel_dig_port->port);
4693 case INTEL_OUTPUT_ANALOG:
4694 return POWER_DOMAIN_PORT_CRT;
4695 case INTEL_OUTPUT_DSI:
4696 return POWER_DOMAIN_PORT_DSI;
4697 default:
4698 return POWER_DOMAIN_PORT_OTHER;
4699 }
4700 }
4701
4702 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4703 {
4704 struct drm_device *dev = crtc->dev;
4705 struct intel_encoder *intel_encoder;
4706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707 enum pipe pipe = intel_crtc->pipe;
4708 unsigned long mask;
4709 enum transcoder transcoder;
4710
4711 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4712
4713 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4714 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4715 if (intel_crtc->config->pch_pfit.enabled ||
4716 intel_crtc->config->pch_pfit.force_thru)
4717 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4718
4719 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4720 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4721
4722 return mask;
4723 }
4724
4725 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4726 {
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4729 struct intel_crtc *crtc;
4730
4731 /*
4732 * First get all needed power domains, then put all unneeded, to avoid
4733 * any unnecessary toggling of the power wells.
4734 */
4735 for_each_intel_crtc(dev, crtc) {
4736 enum intel_display_power_domain domain;
4737
4738 if (!crtc->base.enabled)
4739 continue;
4740
4741 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4742
4743 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4744 intel_display_power_get(dev_priv, domain);
4745 }
4746
4747 if (dev_priv->display.modeset_global_resources)
4748 dev_priv->display.modeset_global_resources(dev);
4749
4750 for_each_intel_crtc(dev, crtc) {
4751 enum intel_display_power_domain domain;
4752
4753 for_each_power_domain(domain, crtc->enabled_power_domains)
4754 intel_display_power_put(dev_priv, domain);
4755
4756 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4757 }
4758
4759 intel_display_set_init_power(dev_priv, false);
4760 }
4761
4762 /* returns HPLL frequency in kHz */
4763 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4764 {
4765 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4766
4767 /* Obtain SKU information */
4768 mutex_lock(&dev_priv->dpio_lock);
4769 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4770 CCK_FUSE_HPLL_FREQ_MASK;
4771 mutex_unlock(&dev_priv->dpio_lock);
4772
4773 return vco_freq[hpll_freq] * 1000;
4774 }
4775
4776 static void vlv_update_cdclk(struct drm_device *dev)
4777 {
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779
4780 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4781 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4782 dev_priv->vlv_cdclk_freq);
4783
4784 /*
4785 * Program the gmbus_freq based on the cdclk frequency.
4786 * BSpec erroneously claims we should aim for 4MHz, but
4787 * in fact 1MHz is the correct frequency.
4788 */
4789 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4790 }
4791
4792 /* Adjust CDclk dividers to allow high res or save power if possible */
4793 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4794 {
4795 struct drm_i915_private *dev_priv = dev->dev_private;
4796 u32 val, cmd;
4797
4798 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4799
4800 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4801 cmd = 2;
4802 else if (cdclk == 266667)
4803 cmd = 1;
4804 else
4805 cmd = 0;
4806
4807 mutex_lock(&dev_priv->rps.hw_lock);
4808 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4809 val &= ~DSPFREQGUAR_MASK;
4810 val |= (cmd << DSPFREQGUAR_SHIFT);
4811 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4812 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4813 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4814 50)) {
4815 DRM_ERROR("timed out waiting for CDclk change\n");
4816 }
4817 mutex_unlock(&dev_priv->rps.hw_lock);
4818
4819 if (cdclk == 400000) {
4820 u32 divider;
4821
4822 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4823
4824 mutex_lock(&dev_priv->dpio_lock);
4825 /* adjust cdclk divider */
4826 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4827 val &= ~DISPLAY_FREQUENCY_VALUES;
4828 val |= divider;
4829 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4830
4831 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4832 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4833 50))
4834 DRM_ERROR("timed out waiting for CDclk change\n");
4835 mutex_unlock(&dev_priv->dpio_lock);
4836 }
4837
4838 mutex_lock(&dev_priv->dpio_lock);
4839 /* adjust self-refresh exit latency value */
4840 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4841 val &= ~0x7f;
4842
4843 /*
4844 * For high bandwidth configs, we set a higher latency in the bunit
4845 * so that the core display fetch happens in time to avoid underruns.
4846 */
4847 if (cdclk == 400000)
4848 val |= 4500 / 250; /* 4.5 usec */
4849 else
4850 val |= 3000 / 250; /* 3.0 usec */
4851 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4852 mutex_unlock(&dev_priv->dpio_lock);
4853
4854 vlv_update_cdclk(dev);
4855 }
4856
4857 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4858 {
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 u32 val, cmd;
4861
4862 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4863
4864 switch (cdclk) {
4865 case 400000:
4866 cmd = 3;
4867 break;
4868 case 333333:
4869 case 320000:
4870 cmd = 2;
4871 break;
4872 case 266667:
4873 cmd = 1;
4874 break;
4875 case 200000:
4876 cmd = 0;
4877 break;
4878 default:
4879 MISSING_CASE(cdclk);
4880 return;
4881 }
4882
4883 mutex_lock(&dev_priv->rps.hw_lock);
4884 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4885 val &= ~DSPFREQGUAR_MASK_CHV;
4886 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4887 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4888 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4889 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4890 50)) {
4891 DRM_ERROR("timed out waiting for CDclk change\n");
4892 }
4893 mutex_unlock(&dev_priv->rps.hw_lock);
4894
4895 vlv_update_cdclk(dev);
4896 }
4897
4898 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4899 int max_pixclk)
4900 {
4901 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4902
4903 /* FIXME: Punit isn't quite ready yet */
4904 if (IS_CHERRYVIEW(dev_priv->dev))
4905 return 400000;
4906
4907 /*
4908 * Really only a few cases to deal with, as only 4 CDclks are supported:
4909 * 200MHz
4910 * 267MHz
4911 * 320/333MHz (depends on HPLL freq)
4912 * 400MHz
4913 * So we check to see whether we're above 90% of the lower bin and
4914 * adjust if needed.
4915 *
4916 * We seem to get an unstable or solid color picture at 200MHz.
4917 * Not sure what's wrong. For now use 200MHz only when all pipes
4918 * are off.
4919 */
4920 if (max_pixclk > freq_320*9/10)
4921 return 400000;
4922 else if (max_pixclk > 266667*9/10)
4923 return freq_320;
4924 else if (max_pixclk > 0)
4925 return 266667;
4926 else
4927 return 200000;
4928 }
4929
4930 /* compute the max pixel clock for new configuration */
4931 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4932 {
4933 struct drm_device *dev = dev_priv->dev;
4934 struct intel_crtc *intel_crtc;
4935 int max_pixclk = 0;
4936
4937 for_each_intel_crtc(dev, intel_crtc) {
4938 if (intel_crtc->new_enabled)
4939 max_pixclk = max(max_pixclk,
4940 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4941 }
4942
4943 return max_pixclk;
4944 }
4945
4946 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4947 unsigned *prepare_pipes)
4948 {
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_crtc *intel_crtc;
4951 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4952
4953 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4954 dev_priv->vlv_cdclk_freq)
4955 return;
4956
4957 /* disable/enable all currently active pipes while we change cdclk */
4958 for_each_intel_crtc(dev, intel_crtc)
4959 if (intel_crtc->base.enabled)
4960 *prepare_pipes |= (1 << intel_crtc->pipe);
4961 }
4962
4963 static void valleyview_modeset_global_resources(struct drm_device *dev)
4964 {
4965 struct drm_i915_private *dev_priv = dev->dev_private;
4966 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4967 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4968
4969 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4970 /*
4971 * FIXME: We can end up here with all power domains off, yet
4972 * with a CDCLK frequency other than the minimum. To account
4973 * for this take the PIPE-A power domain, which covers the HW
4974 * blocks needed for the following programming. This can be
4975 * removed once it's guaranteed that we get here either with
4976 * the minimum CDCLK set, or the required power domains
4977 * enabled.
4978 */
4979 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
4980
4981 if (IS_CHERRYVIEW(dev))
4982 cherryview_set_cdclk(dev, req_cdclk);
4983 else
4984 valleyview_set_cdclk(dev, req_cdclk);
4985
4986 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
4987 }
4988 }
4989
4990 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4991 {
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = to_i915(dev);
4994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995 struct intel_encoder *encoder;
4996 int pipe = intel_crtc->pipe;
4997 bool is_dsi;
4998
4999 WARN_ON(!crtc->enabled);
5000
5001 if (intel_crtc->active)
5002 return;
5003
5004 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5005
5006 if (!is_dsi) {
5007 if (IS_CHERRYVIEW(dev))
5008 chv_prepare_pll(intel_crtc, intel_crtc->config);
5009 else
5010 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5011 }
5012
5013 if (intel_crtc->config->has_dp_encoder)
5014 intel_dp_set_m_n(intel_crtc);
5015
5016 intel_set_pipe_timings(intel_crtc);
5017
5018 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020
5021 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5022 I915_WRITE(CHV_CANVAS(pipe), 0);
5023 }
5024
5025 i9xx_set_pipeconf(intel_crtc);
5026
5027 intel_crtc->active = true;
5028
5029 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5030
5031 for_each_encoder_on_crtc(dev, crtc, encoder)
5032 if (encoder->pre_pll_enable)
5033 encoder->pre_pll_enable(encoder);
5034
5035 if (!is_dsi) {
5036 if (IS_CHERRYVIEW(dev))
5037 chv_enable_pll(intel_crtc, intel_crtc->config);
5038 else
5039 vlv_enable_pll(intel_crtc, intel_crtc->config);
5040 }
5041
5042 for_each_encoder_on_crtc(dev, crtc, encoder)
5043 if (encoder->pre_enable)
5044 encoder->pre_enable(encoder);
5045
5046 i9xx_pfit_enable(intel_crtc);
5047
5048 intel_crtc_load_lut(crtc);
5049
5050 intel_update_watermarks(crtc);
5051 intel_enable_pipe(intel_crtc);
5052
5053 assert_vblank_disabled(crtc);
5054 drm_crtc_vblank_on(crtc);
5055
5056 for_each_encoder_on_crtc(dev, crtc, encoder)
5057 encoder->enable(encoder);
5058
5059 intel_crtc_enable_planes(crtc);
5060
5061 /* Underruns don't raise interrupts, so check manually. */
5062 i9xx_check_fifo_underruns(dev_priv);
5063 }
5064
5065 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5066 {
5067 struct drm_device *dev = crtc->base.dev;
5068 struct drm_i915_private *dev_priv = dev->dev_private;
5069
5070 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5071 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5072 }
5073
5074 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5075 {
5076 struct drm_device *dev = crtc->dev;
5077 struct drm_i915_private *dev_priv = to_i915(dev);
5078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5079 struct intel_encoder *encoder;
5080 int pipe = intel_crtc->pipe;
5081
5082 WARN_ON(!crtc->enabled);
5083
5084 if (intel_crtc->active)
5085 return;
5086
5087 i9xx_set_pll_dividers(intel_crtc);
5088
5089 if (intel_crtc->config->has_dp_encoder)
5090 intel_dp_set_m_n(intel_crtc);
5091
5092 intel_set_pipe_timings(intel_crtc);
5093
5094 i9xx_set_pipeconf(intel_crtc);
5095
5096 intel_crtc->active = true;
5097
5098 if (!IS_GEN2(dev))
5099 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5100
5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 if (encoder->pre_enable)
5103 encoder->pre_enable(encoder);
5104
5105 i9xx_enable_pll(intel_crtc);
5106
5107 i9xx_pfit_enable(intel_crtc);
5108
5109 intel_crtc_load_lut(crtc);
5110
5111 intel_update_watermarks(crtc);
5112 intel_enable_pipe(intel_crtc);
5113
5114 assert_vblank_disabled(crtc);
5115 drm_crtc_vblank_on(crtc);
5116
5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 encoder->enable(encoder);
5119
5120 intel_crtc_enable_planes(crtc);
5121
5122 /*
5123 * Gen2 reports pipe underruns whenever all planes are disabled.
5124 * So don't enable underrun reporting before at least some planes
5125 * are enabled.
5126 * FIXME: Need to fix the logic to work when we turn off all planes
5127 * but leave the pipe running.
5128 */
5129 if (IS_GEN2(dev))
5130 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5131
5132 /* Underruns don't raise interrupts, so check manually. */
5133 i9xx_check_fifo_underruns(dev_priv);
5134 }
5135
5136 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5137 {
5138 struct drm_device *dev = crtc->base.dev;
5139 struct drm_i915_private *dev_priv = dev->dev_private;
5140
5141 if (!crtc->config->gmch_pfit.control)
5142 return;
5143
5144 assert_pipe_disabled(dev_priv, crtc->pipe);
5145
5146 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5147 I915_READ(PFIT_CONTROL));
5148 I915_WRITE(PFIT_CONTROL, 0);
5149 }
5150
5151 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5152 {
5153 struct drm_device *dev = crtc->dev;
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5156 struct intel_encoder *encoder;
5157 int pipe = intel_crtc->pipe;
5158
5159 if (!intel_crtc->active)
5160 return;
5161
5162 /*
5163 * Gen2 reports pipe underruns whenever all planes are disabled.
5164 * So diasble underrun reporting before all the planes get disabled.
5165 * FIXME: Need to fix the logic to work when we turn off all planes
5166 * but leave the pipe running.
5167 */
5168 if (IS_GEN2(dev))
5169 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5170
5171 /*
5172 * Vblank time updates from the shadow to live plane control register
5173 * are blocked if the memory self-refresh mode is active at that
5174 * moment. So to make sure the plane gets truly disabled, disable
5175 * first the self-refresh mode. The self-refresh enable bit in turn
5176 * will be checked/applied by the HW only at the next frame start
5177 * event which is after the vblank start event, so we need to have a
5178 * wait-for-vblank between disabling the plane and the pipe.
5179 */
5180 intel_set_memory_cxsr(dev_priv, false);
5181 intel_crtc_disable_planes(crtc);
5182
5183 /*
5184 * On gen2 planes are double buffered but the pipe isn't, so we must
5185 * wait for planes to fully turn off before disabling the pipe.
5186 * We also need to wait on all gmch platforms because of the
5187 * self-refresh mode constraint explained above.
5188 */
5189 intel_wait_for_vblank(dev, pipe);
5190
5191 for_each_encoder_on_crtc(dev, crtc, encoder)
5192 encoder->disable(encoder);
5193
5194 drm_crtc_vblank_off(crtc);
5195 assert_vblank_disabled(crtc);
5196
5197 intel_disable_pipe(intel_crtc);
5198
5199 i9xx_pfit_disable(intel_crtc);
5200
5201 for_each_encoder_on_crtc(dev, crtc, encoder)
5202 if (encoder->post_disable)
5203 encoder->post_disable(encoder);
5204
5205 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5206 if (IS_CHERRYVIEW(dev))
5207 chv_disable_pll(dev_priv, pipe);
5208 else if (IS_VALLEYVIEW(dev))
5209 vlv_disable_pll(dev_priv, pipe);
5210 else
5211 i9xx_disable_pll(intel_crtc);
5212 }
5213
5214 if (!IS_GEN2(dev))
5215 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5216
5217 intel_crtc->active = false;
5218 intel_update_watermarks(crtc);
5219
5220 mutex_lock(&dev->struct_mutex);
5221 intel_fbc_update(dev);
5222 mutex_unlock(&dev->struct_mutex);
5223 }
5224
5225 static void i9xx_crtc_off(struct drm_crtc *crtc)
5226 {
5227 }
5228
5229 /* Master function to enable/disable CRTC and corresponding power wells */
5230 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5231 {
5232 struct drm_device *dev = crtc->dev;
5233 struct drm_i915_private *dev_priv = dev->dev_private;
5234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5235 enum intel_display_power_domain domain;
5236 unsigned long domains;
5237
5238 if (enable) {
5239 if (!intel_crtc->active) {
5240 domains = get_crtc_power_domains(crtc);
5241 for_each_power_domain(domain, domains)
5242 intel_display_power_get(dev_priv, domain);
5243 intel_crtc->enabled_power_domains = domains;
5244
5245 dev_priv->display.crtc_enable(crtc);
5246 }
5247 } else {
5248 if (intel_crtc->active) {
5249 dev_priv->display.crtc_disable(crtc);
5250
5251 domains = intel_crtc->enabled_power_domains;
5252 for_each_power_domain(domain, domains)
5253 intel_display_power_put(dev_priv, domain);
5254 intel_crtc->enabled_power_domains = 0;
5255 }
5256 }
5257 }
5258
5259 /**
5260 * Sets the power management mode of the pipe and plane.
5261 */
5262 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5263 {
5264 struct drm_device *dev = crtc->dev;
5265 struct intel_encoder *intel_encoder;
5266 bool enable = false;
5267
5268 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5269 enable |= intel_encoder->connectors_active;
5270
5271 intel_crtc_control(crtc, enable);
5272 }
5273
5274 static void intel_crtc_disable(struct drm_crtc *crtc)
5275 {
5276 struct drm_device *dev = crtc->dev;
5277 struct drm_connector *connector;
5278 struct drm_i915_private *dev_priv = dev->dev_private;
5279
5280 /* crtc should still be enabled when we disable it. */
5281 WARN_ON(!crtc->enabled);
5282
5283 dev_priv->display.crtc_disable(crtc);
5284 dev_priv->display.off(crtc);
5285
5286 crtc->primary->funcs->disable_plane(crtc->primary);
5287
5288 /* Update computed state. */
5289 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5290 if (!connector->encoder || !connector->encoder->crtc)
5291 continue;
5292
5293 if (connector->encoder->crtc != crtc)
5294 continue;
5295
5296 connector->dpms = DRM_MODE_DPMS_OFF;
5297 to_intel_encoder(connector->encoder)->connectors_active = false;
5298 }
5299 }
5300
5301 void intel_encoder_destroy(struct drm_encoder *encoder)
5302 {
5303 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5304
5305 drm_encoder_cleanup(encoder);
5306 kfree(intel_encoder);
5307 }
5308
5309 /* Simple dpms helper for encoders with just one connector, no cloning and only
5310 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5311 * state of the entire output pipe. */
5312 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5313 {
5314 if (mode == DRM_MODE_DPMS_ON) {
5315 encoder->connectors_active = true;
5316
5317 intel_crtc_update_dpms(encoder->base.crtc);
5318 } else {
5319 encoder->connectors_active = false;
5320
5321 intel_crtc_update_dpms(encoder->base.crtc);
5322 }
5323 }
5324
5325 /* Cross check the actual hw state with our own modeset state tracking (and it's
5326 * internal consistency). */
5327 static void intel_connector_check_state(struct intel_connector *connector)
5328 {
5329 if (connector->get_hw_state(connector)) {
5330 struct intel_encoder *encoder = connector->encoder;
5331 struct drm_crtc *crtc;
5332 bool encoder_enabled;
5333 enum pipe pipe;
5334
5335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5336 connector->base.base.id,
5337 connector->base.name);
5338
5339 /* there is no real hw state for MST connectors */
5340 if (connector->mst_port)
5341 return;
5342
5343 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5344 "wrong connector dpms state\n");
5345 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5346 "active connector not linked to encoder\n");
5347
5348 if (encoder) {
5349 I915_STATE_WARN(!encoder->connectors_active,
5350 "encoder->connectors_active not set\n");
5351
5352 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5353 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5354 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5355 return;
5356
5357 crtc = encoder->base.crtc;
5358
5359 I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
5360 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5361 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5362 "encoder active on the wrong pipe\n");
5363 }
5364 }
5365 }
5366
5367 /* Even simpler default implementation, if there's really no special case to
5368 * consider. */
5369 void intel_connector_dpms(struct drm_connector *connector, int mode)
5370 {
5371 /* All the simple cases only support two dpms states. */
5372 if (mode != DRM_MODE_DPMS_ON)
5373 mode = DRM_MODE_DPMS_OFF;
5374
5375 if (mode == connector->dpms)
5376 return;
5377
5378 connector->dpms = mode;
5379
5380 /* Only need to change hw state when actually enabled */
5381 if (connector->encoder)
5382 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5383
5384 intel_modeset_check_state(connector->dev);
5385 }
5386
5387 /* Simple connector->get_hw_state implementation for encoders that support only
5388 * one connector and no cloning and hence the encoder state determines the state
5389 * of the connector. */
5390 bool intel_connector_get_hw_state(struct intel_connector *connector)
5391 {
5392 enum pipe pipe = 0;
5393 struct intel_encoder *encoder = connector->encoder;
5394
5395 return encoder->get_hw_state(encoder, &pipe);
5396 }
5397
5398 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5399 struct intel_crtc_state *pipe_config)
5400 {
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402 struct intel_crtc *pipe_B_crtc =
5403 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5404
5405 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5406 pipe_name(pipe), pipe_config->fdi_lanes);
5407 if (pipe_config->fdi_lanes > 4) {
5408 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5409 pipe_name(pipe), pipe_config->fdi_lanes);
5410 return false;
5411 }
5412
5413 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5414 if (pipe_config->fdi_lanes > 2) {
5415 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5416 pipe_config->fdi_lanes);
5417 return false;
5418 } else {
5419 return true;
5420 }
5421 }
5422
5423 if (INTEL_INFO(dev)->num_pipes == 2)
5424 return true;
5425
5426 /* Ivybridge 3 pipe is really complicated */
5427 switch (pipe) {
5428 case PIPE_A:
5429 return true;
5430 case PIPE_B:
5431 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5432 pipe_config->fdi_lanes > 2) {
5433 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5434 pipe_name(pipe), pipe_config->fdi_lanes);
5435 return false;
5436 }
5437 return true;
5438 case PIPE_C:
5439 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5440 pipe_B_crtc->config->fdi_lanes <= 2) {
5441 if (pipe_config->fdi_lanes > 2) {
5442 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5443 pipe_name(pipe), pipe_config->fdi_lanes);
5444 return false;
5445 }
5446 } else {
5447 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5448 return false;
5449 }
5450 return true;
5451 default:
5452 BUG();
5453 }
5454 }
5455
5456 #define RETRY 1
5457 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5458 struct intel_crtc_state *pipe_config)
5459 {
5460 struct drm_device *dev = intel_crtc->base.dev;
5461 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5462 int lane, link_bw, fdi_dotclock;
5463 bool setup_ok, needs_recompute = false;
5464
5465 retry:
5466 /* FDI is a binary signal running at ~2.7GHz, encoding
5467 * each output octet as 10 bits. The actual frequency
5468 * is stored as a divider into a 100MHz clock, and the
5469 * mode pixel clock is stored in units of 1KHz.
5470 * Hence the bw of each lane in terms of the mode signal
5471 * is:
5472 */
5473 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5474
5475 fdi_dotclock = adjusted_mode->crtc_clock;
5476
5477 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5478 pipe_config->pipe_bpp);
5479
5480 pipe_config->fdi_lanes = lane;
5481
5482 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5483 link_bw, &pipe_config->fdi_m_n);
5484
5485 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5486 intel_crtc->pipe, pipe_config);
5487 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5488 pipe_config->pipe_bpp -= 2*3;
5489 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5490 pipe_config->pipe_bpp);
5491 needs_recompute = true;
5492 pipe_config->bw_constrained = true;
5493
5494 goto retry;
5495 }
5496
5497 if (needs_recompute)
5498 return RETRY;
5499
5500 return setup_ok ? 0 : -EINVAL;
5501 }
5502
5503 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5504 struct intel_crtc_state *pipe_config)
5505 {
5506 pipe_config->ips_enabled = i915.enable_ips &&
5507 hsw_crtc_supports_ips(crtc) &&
5508 pipe_config->pipe_bpp <= 24;
5509 }
5510
5511 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5512 struct intel_crtc_state *pipe_config)
5513 {
5514 struct drm_device *dev = crtc->base.dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5517
5518 /* FIXME should check pixel clock limits on all platforms */
5519 if (INTEL_INFO(dev)->gen < 4) {
5520 int clock_limit =
5521 dev_priv->display.get_display_clock_speed(dev);
5522
5523 /*
5524 * Enable pixel doubling when the dot clock
5525 * is > 90% of the (display) core speed.
5526 *
5527 * GDG double wide on either pipe,
5528 * otherwise pipe A only.
5529 */
5530 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5531 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5532 clock_limit *= 2;
5533 pipe_config->double_wide = true;
5534 }
5535
5536 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5537 return -EINVAL;
5538 }
5539
5540 /*
5541 * Pipe horizontal size must be even in:
5542 * - DVO ganged mode
5543 * - LVDS dual channel mode
5544 * - Double wide pipe
5545 */
5546 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5547 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5548 pipe_config->pipe_src_w &= ~1;
5549
5550 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5551 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5552 */
5553 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5554 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5555 return -EINVAL;
5556
5557 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5558 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5559 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5560 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5561 * for lvds. */
5562 pipe_config->pipe_bpp = 8*3;
5563 }
5564
5565 if (HAS_IPS(dev))
5566 hsw_compute_ips_config(crtc, pipe_config);
5567
5568 if (pipe_config->has_pch_encoder)
5569 return ironlake_fdi_compute_config(crtc, pipe_config);
5570
5571 return 0;
5572 }
5573
5574 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5575 {
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577 u32 val;
5578 int divider;
5579
5580 /* FIXME: Punit isn't quite ready yet */
5581 if (IS_CHERRYVIEW(dev))
5582 return 400000;
5583
5584 if (dev_priv->hpll_freq == 0)
5585 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5586
5587 mutex_lock(&dev_priv->dpio_lock);
5588 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5589 mutex_unlock(&dev_priv->dpio_lock);
5590
5591 divider = val & DISPLAY_FREQUENCY_VALUES;
5592
5593 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5594 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5595 "cdclk change in progress\n");
5596
5597 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5598 }
5599
5600 static int i945_get_display_clock_speed(struct drm_device *dev)
5601 {
5602 return 400000;
5603 }
5604
5605 static int i915_get_display_clock_speed(struct drm_device *dev)
5606 {
5607 return 333000;
5608 }
5609
5610 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5611 {
5612 return 200000;
5613 }
5614
5615 static int pnv_get_display_clock_speed(struct drm_device *dev)
5616 {
5617 u16 gcfgc = 0;
5618
5619 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5620
5621 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5622 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5623 return 267000;
5624 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5625 return 333000;
5626 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5627 return 444000;
5628 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5629 return 200000;
5630 default:
5631 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5632 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5633 return 133000;
5634 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5635 return 167000;
5636 }
5637 }
5638
5639 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5640 {
5641 u16 gcfgc = 0;
5642
5643 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5644
5645 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5646 return 133000;
5647 else {
5648 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5649 case GC_DISPLAY_CLOCK_333_MHZ:
5650 return 333000;
5651 default:
5652 case GC_DISPLAY_CLOCK_190_200_MHZ:
5653 return 190000;
5654 }
5655 }
5656 }
5657
5658 static int i865_get_display_clock_speed(struct drm_device *dev)
5659 {
5660 return 266000;
5661 }
5662
5663 static int i855_get_display_clock_speed(struct drm_device *dev)
5664 {
5665 u16 hpllcc = 0;
5666 /* Assume that the hardware is in the high speed state. This
5667 * should be the default.
5668 */
5669 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5670 case GC_CLOCK_133_200:
5671 case GC_CLOCK_100_200:
5672 return 200000;
5673 case GC_CLOCK_166_250:
5674 return 250000;
5675 case GC_CLOCK_100_133:
5676 return 133000;
5677 }
5678
5679 /* Shouldn't happen */
5680 return 0;
5681 }
5682
5683 static int i830_get_display_clock_speed(struct drm_device *dev)
5684 {
5685 return 133000;
5686 }
5687
5688 static void
5689 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5690 {
5691 while (*num > DATA_LINK_M_N_MASK ||
5692 *den > DATA_LINK_M_N_MASK) {
5693 *num >>= 1;
5694 *den >>= 1;
5695 }
5696 }
5697
5698 static void compute_m_n(unsigned int m, unsigned int n,
5699 uint32_t *ret_m, uint32_t *ret_n)
5700 {
5701 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5702 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5703 intel_reduce_m_n_ratio(ret_m, ret_n);
5704 }
5705
5706 void
5707 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5708 int pixel_clock, int link_clock,
5709 struct intel_link_m_n *m_n)
5710 {
5711 m_n->tu = 64;
5712
5713 compute_m_n(bits_per_pixel * pixel_clock,
5714 link_clock * nlanes * 8,
5715 &m_n->gmch_m, &m_n->gmch_n);
5716
5717 compute_m_n(pixel_clock, link_clock,
5718 &m_n->link_m, &m_n->link_n);
5719 }
5720
5721 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5722 {
5723 if (i915.panel_use_ssc >= 0)
5724 return i915.panel_use_ssc != 0;
5725 return dev_priv->vbt.lvds_use_ssc
5726 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5727 }
5728
5729 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5730 {
5731 struct drm_device *dev = crtc->base.dev;
5732 struct drm_i915_private *dev_priv = dev->dev_private;
5733 int refclk;
5734
5735 if (IS_VALLEYVIEW(dev)) {
5736 refclk = 100000;
5737 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5738 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5739 refclk = dev_priv->vbt.lvds_ssc_freq;
5740 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5741 } else if (!IS_GEN2(dev)) {
5742 refclk = 96000;
5743 } else {
5744 refclk = 48000;
5745 }
5746
5747 return refclk;
5748 }
5749
5750 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5751 {
5752 return (1 << dpll->n) << 16 | dpll->m2;
5753 }
5754
5755 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5756 {
5757 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5758 }
5759
5760 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5761 struct intel_crtc_state *crtc_state,
5762 intel_clock_t *reduced_clock)
5763 {
5764 struct drm_device *dev = crtc->base.dev;
5765 u32 fp, fp2 = 0;
5766
5767 if (IS_PINEVIEW(dev)) {
5768 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5769 if (reduced_clock)
5770 fp2 = pnv_dpll_compute_fp(reduced_clock);
5771 } else {
5772 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5773 if (reduced_clock)
5774 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5775 }
5776
5777 crtc_state->dpll_hw_state.fp0 = fp;
5778
5779 crtc->lowfreq_avail = false;
5780 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5781 reduced_clock && i915.powersave) {
5782 crtc_state->dpll_hw_state.fp1 = fp2;
5783 crtc->lowfreq_avail = true;
5784 } else {
5785 crtc_state->dpll_hw_state.fp1 = fp;
5786 }
5787 }
5788
5789 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5790 pipe)
5791 {
5792 u32 reg_val;
5793
5794 /*
5795 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5796 * and set it to a reasonable value instead.
5797 */
5798 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5799 reg_val &= 0xffffff00;
5800 reg_val |= 0x00000030;
5801 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5802
5803 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5804 reg_val &= 0x8cffffff;
5805 reg_val = 0x8c000000;
5806 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5807
5808 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5809 reg_val &= 0xffffff00;
5810 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5811
5812 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5813 reg_val &= 0x00ffffff;
5814 reg_val |= 0xb0000000;
5815 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5816 }
5817
5818 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5819 struct intel_link_m_n *m_n)
5820 {
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 int pipe = crtc->pipe;
5824
5825 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5826 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5827 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5828 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5829 }
5830
5831 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5832 struct intel_link_m_n *m_n,
5833 struct intel_link_m_n *m2_n2)
5834 {
5835 struct drm_device *dev = crtc->base.dev;
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 int pipe = crtc->pipe;
5838 enum transcoder transcoder = crtc->config->cpu_transcoder;
5839
5840 if (INTEL_INFO(dev)->gen >= 5) {
5841 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5842 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5843 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5844 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5845 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5846 * for gen < 8) and if DRRS is supported (to make sure the
5847 * registers are not unnecessarily accessed).
5848 */
5849 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5850 crtc->config->has_drrs) {
5851 I915_WRITE(PIPE_DATA_M2(transcoder),
5852 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5853 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5854 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5855 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5856 }
5857 } else {
5858 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5859 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5860 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5861 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5862 }
5863 }
5864
5865 void intel_dp_set_m_n(struct intel_crtc *crtc)
5866 {
5867 if (crtc->config->has_pch_encoder)
5868 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5869 else
5870 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5871 &crtc->config->dp_m2_n2);
5872 }
5873
5874 static void vlv_update_pll(struct intel_crtc *crtc,
5875 struct intel_crtc_state *pipe_config)
5876 {
5877 u32 dpll, dpll_md;
5878
5879 /*
5880 * Enable DPIO clock input. We should never disable the reference
5881 * clock for pipe B, since VGA hotplug / manual detection depends
5882 * on it.
5883 */
5884 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5885 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5886 /* We should never disable this, set it here for state tracking */
5887 if (crtc->pipe == PIPE_B)
5888 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5889 dpll |= DPLL_VCO_ENABLE;
5890 pipe_config->dpll_hw_state.dpll = dpll;
5891
5892 dpll_md = (pipe_config->pixel_multiplier - 1)
5893 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5894 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5895 }
5896
5897 static void vlv_prepare_pll(struct intel_crtc *crtc,
5898 const struct intel_crtc_state *pipe_config)
5899 {
5900 struct drm_device *dev = crtc->base.dev;
5901 struct drm_i915_private *dev_priv = dev->dev_private;
5902 int pipe = crtc->pipe;
5903 u32 mdiv;
5904 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5905 u32 coreclk, reg_val;
5906
5907 mutex_lock(&dev_priv->dpio_lock);
5908
5909 bestn = pipe_config->dpll.n;
5910 bestm1 = pipe_config->dpll.m1;
5911 bestm2 = pipe_config->dpll.m2;
5912 bestp1 = pipe_config->dpll.p1;
5913 bestp2 = pipe_config->dpll.p2;
5914
5915 /* See eDP HDMI DPIO driver vbios notes doc */
5916
5917 /* PLL B needs special handling */
5918 if (pipe == PIPE_B)
5919 vlv_pllb_recal_opamp(dev_priv, pipe);
5920
5921 /* Set up Tx target for periodic Rcomp update */
5922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5923
5924 /* Disable target IRef on PLL */
5925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5926 reg_val &= 0x00ffffff;
5927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5928
5929 /* Disable fast lock */
5930 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5931
5932 /* Set idtafcrecal before PLL is enabled */
5933 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5934 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5935 mdiv |= ((bestn << DPIO_N_SHIFT));
5936 mdiv |= (1 << DPIO_K_SHIFT);
5937
5938 /*
5939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5940 * but we don't support that).
5941 * Note: don't use the DAC post divider as it seems unstable.
5942 */
5943 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5945
5946 mdiv |= DPIO_ENABLE_CALIBRATION;
5947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5948
5949 /* Set HBR and RBR LPF coefficients */
5950 if (pipe_config->port_clock == 162000 ||
5951 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5952 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5954 0x009f0003);
5955 else
5956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5957 0x00d0000f);
5958
5959 if (pipe_config->has_dp_encoder) {
5960 /* Use SSC source */
5961 if (pipe == PIPE_A)
5962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5963 0x0df40000);
5964 else
5965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5966 0x0df70000);
5967 } else { /* HDMI or VGA */
5968 /* Use bend source */
5969 if (pipe == PIPE_A)
5970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5971 0x0df70000);
5972 else
5973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5974 0x0df40000);
5975 }
5976
5977 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5978 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5979 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5980 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5981 coreclk |= 0x01000000;
5982 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5983
5984 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5985 mutex_unlock(&dev_priv->dpio_lock);
5986 }
5987
5988 static void chv_update_pll(struct intel_crtc *crtc,
5989 struct intel_crtc_state *pipe_config)
5990 {
5991 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5992 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5993 DPLL_VCO_ENABLE;
5994 if (crtc->pipe != PIPE_A)
5995 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5996
5997 pipe_config->dpll_hw_state.dpll_md =
5998 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5999 }
6000
6001 static void chv_prepare_pll(struct intel_crtc *crtc,
6002 const struct intel_crtc_state *pipe_config)
6003 {
6004 struct drm_device *dev = crtc->base.dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 int pipe = crtc->pipe;
6007 int dpll_reg = DPLL(crtc->pipe);
6008 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6009 u32 loopfilter, intcoeff;
6010 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6011 int refclk;
6012
6013 bestn = pipe_config->dpll.n;
6014 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6015 bestm1 = pipe_config->dpll.m1;
6016 bestm2 = pipe_config->dpll.m2 >> 22;
6017 bestp1 = pipe_config->dpll.p1;
6018 bestp2 = pipe_config->dpll.p2;
6019
6020 /*
6021 * Enable Refclk and SSC
6022 */
6023 I915_WRITE(dpll_reg,
6024 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6025
6026 mutex_lock(&dev_priv->dpio_lock);
6027
6028 /* p1 and p2 divider */
6029 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6030 5 << DPIO_CHV_S1_DIV_SHIFT |
6031 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6032 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6033 1 << DPIO_CHV_K_DIV_SHIFT);
6034
6035 /* Feedback post-divider - m2 */
6036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6037
6038 /* Feedback refclk divider - n and m1 */
6039 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6040 DPIO_CHV_M1_DIV_BY_2 |
6041 1 << DPIO_CHV_N_DIV_SHIFT);
6042
6043 /* M2 fraction division */
6044 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6045
6046 /* M2 fraction division enable */
6047 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6048 DPIO_CHV_FRAC_DIV_EN |
6049 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6050
6051 /* Loop filter */
6052 refclk = i9xx_get_refclk(crtc, 0);
6053 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6054 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6055 if (refclk == 100000)
6056 intcoeff = 11;
6057 else if (refclk == 38400)
6058 intcoeff = 10;
6059 else
6060 intcoeff = 9;
6061 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6062 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6063
6064 /* AFC Recal */
6065 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6066 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6067 DPIO_AFC_RECAL);
6068
6069 mutex_unlock(&dev_priv->dpio_lock);
6070 }
6071
6072 /**
6073 * vlv_force_pll_on - forcibly enable just the PLL
6074 * @dev_priv: i915 private structure
6075 * @pipe: pipe PLL to enable
6076 * @dpll: PLL configuration
6077 *
6078 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6079 * in cases where we need the PLL enabled even when @pipe is not going to
6080 * be enabled.
6081 */
6082 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6083 const struct dpll *dpll)
6084 {
6085 struct intel_crtc *crtc =
6086 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6087 struct intel_crtc_state pipe_config = {
6088 .pixel_multiplier = 1,
6089 .dpll = *dpll,
6090 };
6091
6092 if (IS_CHERRYVIEW(dev)) {
6093 chv_update_pll(crtc, &pipe_config);
6094 chv_prepare_pll(crtc, &pipe_config);
6095 chv_enable_pll(crtc, &pipe_config);
6096 } else {
6097 vlv_update_pll(crtc, &pipe_config);
6098 vlv_prepare_pll(crtc, &pipe_config);
6099 vlv_enable_pll(crtc, &pipe_config);
6100 }
6101 }
6102
6103 /**
6104 * vlv_force_pll_off - forcibly disable just the PLL
6105 * @dev_priv: i915 private structure
6106 * @pipe: pipe PLL to disable
6107 *
6108 * Disable the PLL for @pipe. To be used in cases where we need
6109 * the PLL enabled even when @pipe is not going to be enabled.
6110 */
6111 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6112 {
6113 if (IS_CHERRYVIEW(dev))
6114 chv_disable_pll(to_i915(dev), pipe);
6115 else
6116 vlv_disable_pll(to_i915(dev), pipe);
6117 }
6118
6119 static void i9xx_update_pll(struct intel_crtc *crtc,
6120 struct intel_crtc_state *crtc_state,
6121 intel_clock_t *reduced_clock,
6122 int num_connectors)
6123 {
6124 struct drm_device *dev = crtc->base.dev;
6125 struct drm_i915_private *dev_priv = dev->dev_private;
6126 u32 dpll;
6127 bool is_sdvo;
6128 struct dpll *clock = &crtc_state->dpll;
6129
6130 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6131
6132 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6133 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6134
6135 dpll = DPLL_VGA_MODE_DIS;
6136
6137 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6138 dpll |= DPLLB_MODE_LVDS;
6139 else
6140 dpll |= DPLLB_MODE_DAC_SERIAL;
6141
6142 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6143 dpll |= (crtc_state->pixel_multiplier - 1)
6144 << SDVO_MULTIPLIER_SHIFT_HIRES;
6145 }
6146
6147 if (is_sdvo)
6148 dpll |= DPLL_SDVO_HIGH_SPEED;
6149
6150 if (crtc_state->has_dp_encoder)
6151 dpll |= DPLL_SDVO_HIGH_SPEED;
6152
6153 /* compute bitmask from p1 value */
6154 if (IS_PINEVIEW(dev))
6155 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6156 else {
6157 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6158 if (IS_G4X(dev) && reduced_clock)
6159 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6160 }
6161 switch (clock->p2) {
6162 case 5:
6163 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6164 break;
6165 case 7:
6166 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6167 break;
6168 case 10:
6169 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6170 break;
6171 case 14:
6172 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6173 break;
6174 }
6175 if (INTEL_INFO(dev)->gen >= 4)
6176 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6177
6178 if (crtc_state->sdvo_tv_clock)
6179 dpll |= PLL_REF_INPUT_TVCLKINBC;
6180 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6181 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6182 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6183 else
6184 dpll |= PLL_REF_INPUT_DREFCLK;
6185
6186 dpll |= DPLL_VCO_ENABLE;
6187 crtc_state->dpll_hw_state.dpll = dpll;
6188
6189 if (INTEL_INFO(dev)->gen >= 4) {
6190 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6191 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6192 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6193 }
6194 }
6195
6196 static void i8xx_update_pll(struct intel_crtc *crtc,
6197 struct intel_crtc_state *crtc_state,
6198 intel_clock_t *reduced_clock,
6199 int num_connectors)
6200 {
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 u32 dpll;
6204 struct dpll *clock = &crtc_state->dpll;
6205
6206 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6207
6208 dpll = DPLL_VGA_MODE_DIS;
6209
6210 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6211 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6212 } else {
6213 if (clock->p1 == 2)
6214 dpll |= PLL_P1_DIVIDE_BY_TWO;
6215 else
6216 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6217 if (clock->p2 == 4)
6218 dpll |= PLL_P2_DIVIDE_BY_4;
6219 }
6220
6221 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6222 dpll |= DPLL_DVO_2X_MODE;
6223
6224 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6225 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6226 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6227 else
6228 dpll |= PLL_REF_INPUT_DREFCLK;
6229
6230 dpll |= DPLL_VCO_ENABLE;
6231 crtc_state->dpll_hw_state.dpll = dpll;
6232 }
6233
6234 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6235 {
6236 struct drm_device *dev = intel_crtc->base.dev;
6237 struct drm_i915_private *dev_priv = dev->dev_private;
6238 enum pipe pipe = intel_crtc->pipe;
6239 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6240 struct drm_display_mode *adjusted_mode =
6241 &intel_crtc->config->base.adjusted_mode;
6242 uint32_t crtc_vtotal, crtc_vblank_end;
6243 int vsyncshift = 0;
6244
6245 /* We need to be careful not to changed the adjusted mode, for otherwise
6246 * the hw state checker will get angry at the mismatch. */
6247 crtc_vtotal = adjusted_mode->crtc_vtotal;
6248 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6249
6250 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6251 /* the chip adds 2 halflines automatically */
6252 crtc_vtotal -= 1;
6253 crtc_vblank_end -= 1;
6254
6255 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6256 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6257 else
6258 vsyncshift = adjusted_mode->crtc_hsync_start -
6259 adjusted_mode->crtc_htotal / 2;
6260 if (vsyncshift < 0)
6261 vsyncshift += adjusted_mode->crtc_htotal;
6262 }
6263
6264 if (INTEL_INFO(dev)->gen > 3)
6265 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6266
6267 I915_WRITE(HTOTAL(cpu_transcoder),
6268 (adjusted_mode->crtc_hdisplay - 1) |
6269 ((adjusted_mode->crtc_htotal - 1) << 16));
6270 I915_WRITE(HBLANK(cpu_transcoder),
6271 (adjusted_mode->crtc_hblank_start - 1) |
6272 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6273 I915_WRITE(HSYNC(cpu_transcoder),
6274 (adjusted_mode->crtc_hsync_start - 1) |
6275 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6276
6277 I915_WRITE(VTOTAL(cpu_transcoder),
6278 (adjusted_mode->crtc_vdisplay - 1) |
6279 ((crtc_vtotal - 1) << 16));
6280 I915_WRITE(VBLANK(cpu_transcoder),
6281 (adjusted_mode->crtc_vblank_start - 1) |
6282 ((crtc_vblank_end - 1) << 16));
6283 I915_WRITE(VSYNC(cpu_transcoder),
6284 (adjusted_mode->crtc_vsync_start - 1) |
6285 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6286
6287 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6288 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6289 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6290 * bits. */
6291 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6292 (pipe == PIPE_B || pipe == PIPE_C))
6293 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6294
6295 /* pipesrc controls the size that is scaled from, which should
6296 * always be the user's requested size.
6297 */
6298 I915_WRITE(PIPESRC(pipe),
6299 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6300 (intel_crtc->config->pipe_src_h - 1));
6301 }
6302
6303 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6304 struct intel_crtc_state *pipe_config)
6305 {
6306 struct drm_device *dev = crtc->base.dev;
6307 struct drm_i915_private *dev_priv = dev->dev_private;
6308 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6309 uint32_t tmp;
6310
6311 tmp = I915_READ(HTOTAL(cpu_transcoder));
6312 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6313 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6314 tmp = I915_READ(HBLANK(cpu_transcoder));
6315 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6316 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6317 tmp = I915_READ(HSYNC(cpu_transcoder));
6318 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6319 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6320
6321 tmp = I915_READ(VTOTAL(cpu_transcoder));
6322 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6323 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6324 tmp = I915_READ(VBLANK(cpu_transcoder));
6325 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6326 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6327 tmp = I915_READ(VSYNC(cpu_transcoder));
6328 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6329 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6330
6331 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6332 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6333 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6334 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6335 }
6336
6337 tmp = I915_READ(PIPESRC(crtc->pipe));
6338 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6339 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6340
6341 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6342 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6343 }
6344
6345 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6346 struct intel_crtc_state *pipe_config)
6347 {
6348 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6349 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6350 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6351 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6352
6353 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6354 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6355 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6356 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6357
6358 mode->flags = pipe_config->base.adjusted_mode.flags;
6359
6360 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6361 mode->flags |= pipe_config->base.adjusted_mode.flags;
6362 }
6363
6364 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6365 {
6366 struct drm_device *dev = intel_crtc->base.dev;
6367 struct drm_i915_private *dev_priv = dev->dev_private;
6368 uint32_t pipeconf;
6369
6370 pipeconf = 0;
6371
6372 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6373 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6374 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6375
6376 if (intel_crtc->config->double_wide)
6377 pipeconf |= PIPECONF_DOUBLE_WIDE;
6378
6379 /* only g4x and later have fancy bpc/dither controls */
6380 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6381 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6382 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6383 pipeconf |= PIPECONF_DITHER_EN |
6384 PIPECONF_DITHER_TYPE_SP;
6385
6386 switch (intel_crtc->config->pipe_bpp) {
6387 case 18:
6388 pipeconf |= PIPECONF_6BPC;
6389 break;
6390 case 24:
6391 pipeconf |= PIPECONF_8BPC;
6392 break;
6393 case 30:
6394 pipeconf |= PIPECONF_10BPC;
6395 break;
6396 default:
6397 /* Case prevented by intel_choose_pipe_bpp_dither. */
6398 BUG();
6399 }
6400 }
6401
6402 if (HAS_PIPE_CXSR(dev)) {
6403 if (intel_crtc->lowfreq_avail) {
6404 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6405 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6406 } else {
6407 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6408 }
6409 }
6410
6411 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6412 if (INTEL_INFO(dev)->gen < 4 ||
6413 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6414 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6415 else
6416 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6417 } else
6418 pipeconf |= PIPECONF_PROGRESSIVE;
6419
6420 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6421 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6422
6423 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6424 POSTING_READ(PIPECONF(intel_crtc->pipe));
6425 }
6426
6427 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6428 struct intel_crtc_state *crtc_state)
6429 {
6430 struct drm_device *dev = crtc->base.dev;
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 int refclk, num_connectors = 0;
6433 intel_clock_t clock, reduced_clock;
6434 bool ok, has_reduced_clock = false;
6435 bool is_lvds = false, is_dsi = false;
6436 struct intel_encoder *encoder;
6437 const intel_limit_t *limit;
6438
6439 for_each_intel_encoder(dev, encoder) {
6440 if (encoder->new_crtc != crtc)
6441 continue;
6442
6443 switch (encoder->type) {
6444 case INTEL_OUTPUT_LVDS:
6445 is_lvds = true;
6446 break;
6447 case INTEL_OUTPUT_DSI:
6448 is_dsi = true;
6449 break;
6450 default:
6451 break;
6452 }
6453
6454 num_connectors++;
6455 }
6456
6457 if (is_dsi)
6458 return 0;
6459
6460 if (!crtc_state->clock_set) {
6461 refclk = i9xx_get_refclk(crtc, num_connectors);
6462
6463 /*
6464 * Returns a set of divisors for the desired target clock with
6465 * the given refclk, or FALSE. The returned values represent
6466 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6467 * 2) / p1 / p2.
6468 */
6469 limit = intel_limit(crtc, refclk);
6470 ok = dev_priv->display.find_dpll(limit, crtc,
6471 crtc_state->port_clock,
6472 refclk, NULL, &clock);
6473 if (!ok) {
6474 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6475 return -EINVAL;
6476 }
6477
6478 if (is_lvds && dev_priv->lvds_downclock_avail) {
6479 /*
6480 * Ensure we match the reduced clock's P to the target
6481 * clock. If the clocks don't match, we can't switch
6482 * the display clock by using the FP0/FP1. In such case
6483 * we will disable the LVDS downclock feature.
6484 */
6485 has_reduced_clock =
6486 dev_priv->display.find_dpll(limit, crtc,
6487 dev_priv->lvds_downclock,
6488 refclk, &clock,
6489 &reduced_clock);
6490 }
6491 /* Compat-code for transition, will disappear. */
6492 crtc_state->dpll.n = clock.n;
6493 crtc_state->dpll.m1 = clock.m1;
6494 crtc_state->dpll.m2 = clock.m2;
6495 crtc_state->dpll.p1 = clock.p1;
6496 crtc_state->dpll.p2 = clock.p2;
6497 }
6498
6499 if (IS_GEN2(dev)) {
6500 i8xx_update_pll(crtc, crtc_state,
6501 has_reduced_clock ? &reduced_clock : NULL,
6502 num_connectors);
6503 } else if (IS_CHERRYVIEW(dev)) {
6504 chv_update_pll(crtc, crtc_state);
6505 } else if (IS_VALLEYVIEW(dev)) {
6506 vlv_update_pll(crtc, crtc_state);
6507 } else {
6508 i9xx_update_pll(crtc, crtc_state,
6509 has_reduced_clock ? &reduced_clock : NULL,
6510 num_connectors);
6511 }
6512
6513 return 0;
6514 }
6515
6516 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6517 struct intel_crtc_state *pipe_config)
6518 {
6519 struct drm_device *dev = crtc->base.dev;
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 uint32_t tmp;
6522
6523 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6524 return;
6525
6526 tmp = I915_READ(PFIT_CONTROL);
6527 if (!(tmp & PFIT_ENABLE))
6528 return;
6529
6530 /* Check whether the pfit is attached to our pipe. */
6531 if (INTEL_INFO(dev)->gen < 4) {
6532 if (crtc->pipe != PIPE_B)
6533 return;
6534 } else {
6535 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6536 return;
6537 }
6538
6539 pipe_config->gmch_pfit.control = tmp;
6540 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6541 if (INTEL_INFO(dev)->gen < 5)
6542 pipe_config->gmch_pfit.lvds_border_bits =
6543 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6544 }
6545
6546 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6547 struct intel_crtc_state *pipe_config)
6548 {
6549 struct drm_device *dev = crtc->base.dev;
6550 struct drm_i915_private *dev_priv = dev->dev_private;
6551 int pipe = pipe_config->cpu_transcoder;
6552 intel_clock_t clock;
6553 u32 mdiv;
6554 int refclk = 100000;
6555
6556 /* In case of MIPI DPLL will not even be used */
6557 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6558 return;
6559
6560 mutex_lock(&dev_priv->dpio_lock);
6561 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6562 mutex_unlock(&dev_priv->dpio_lock);
6563
6564 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6565 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6566 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6567 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6568 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6569
6570 vlv_clock(refclk, &clock);
6571
6572 /* clock.dot is the fast clock */
6573 pipe_config->port_clock = clock.dot / 5;
6574 }
6575
6576 static void
6577 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6578 struct intel_initial_plane_config *plane_config)
6579 {
6580 struct drm_device *dev = crtc->base.dev;
6581 struct drm_i915_private *dev_priv = dev->dev_private;
6582 u32 val, base, offset;
6583 int pipe = crtc->pipe, plane = crtc->plane;
6584 int fourcc, pixel_format;
6585 int aligned_height;
6586 struct drm_framebuffer *fb;
6587 struct intel_framebuffer *intel_fb;
6588
6589 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6590 if (!intel_fb) {
6591 DRM_DEBUG_KMS("failed to alloc fb\n");
6592 return;
6593 }
6594
6595 fb = &intel_fb->base;
6596
6597 val = I915_READ(DSPCNTR(plane));
6598
6599 if (INTEL_INFO(dev)->gen >= 4)
6600 if (val & DISPPLANE_TILED)
6601 plane_config->tiling = I915_TILING_X;
6602
6603 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6604 fourcc = i9xx_format_to_fourcc(pixel_format);
6605 fb->pixel_format = fourcc;
6606 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6607
6608 if (INTEL_INFO(dev)->gen >= 4) {
6609 if (plane_config->tiling)
6610 offset = I915_READ(DSPTILEOFF(plane));
6611 else
6612 offset = I915_READ(DSPLINOFF(plane));
6613 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6614 } else {
6615 base = I915_READ(DSPADDR(plane));
6616 }
6617 plane_config->base = base;
6618
6619 val = I915_READ(PIPESRC(pipe));
6620 fb->width = ((val >> 16) & 0xfff) + 1;
6621 fb->height = ((val >> 0) & 0xfff) + 1;
6622
6623 val = I915_READ(DSPSTRIDE(pipe));
6624 fb->pitches[0] = val & 0xffffffc0;
6625
6626 aligned_height = intel_fb_align_height(dev, fb->height,
6627 plane_config->tiling);
6628
6629 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6630
6631 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6632 pipe_name(pipe), plane, fb->width, fb->height,
6633 fb->bits_per_pixel, base, fb->pitches[0],
6634 plane_config->size);
6635
6636 crtc->base.primary->fb = fb;
6637 }
6638
6639 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6640 struct intel_crtc_state *pipe_config)
6641 {
6642 struct drm_device *dev = crtc->base.dev;
6643 struct drm_i915_private *dev_priv = dev->dev_private;
6644 int pipe = pipe_config->cpu_transcoder;
6645 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6646 intel_clock_t clock;
6647 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6648 int refclk = 100000;
6649
6650 mutex_lock(&dev_priv->dpio_lock);
6651 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6652 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6653 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6654 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6655 mutex_unlock(&dev_priv->dpio_lock);
6656
6657 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6658 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6659 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6660 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6661 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6662
6663 chv_clock(refclk, &clock);
6664
6665 /* clock.dot is the fast clock */
6666 pipe_config->port_clock = clock.dot / 5;
6667 }
6668
6669 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6670 struct intel_crtc_state *pipe_config)
6671 {
6672 struct drm_device *dev = crtc->base.dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 uint32_t tmp;
6675
6676 if (!intel_display_power_is_enabled(dev_priv,
6677 POWER_DOMAIN_PIPE(crtc->pipe)))
6678 return false;
6679
6680 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6681 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6682
6683 tmp = I915_READ(PIPECONF(crtc->pipe));
6684 if (!(tmp & PIPECONF_ENABLE))
6685 return false;
6686
6687 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6688 switch (tmp & PIPECONF_BPC_MASK) {
6689 case PIPECONF_6BPC:
6690 pipe_config->pipe_bpp = 18;
6691 break;
6692 case PIPECONF_8BPC:
6693 pipe_config->pipe_bpp = 24;
6694 break;
6695 case PIPECONF_10BPC:
6696 pipe_config->pipe_bpp = 30;
6697 break;
6698 default:
6699 break;
6700 }
6701 }
6702
6703 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6704 pipe_config->limited_color_range = true;
6705
6706 if (INTEL_INFO(dev)->gen < 4)
6707 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6708
6709 intel_get_pipe_timings(crtc, pipe_config);
6710
6711 i9xx_get_pfit_config(crtc, pipe_config);
6712
6713 if (INTEL_INFO(dev)->gen >= 4) {
6714 tmp = I915_READ(DPLL_MD(crtc->pipe));
6715 pipe_config->pixel_multiplier =
6716 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6717 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6718 pipe_config->dpll_hw_state.dpll_md = tmp;
6719 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6720 tmp = I915_READ(DPLL(crtc->pipe));
6721 pipe_config->pixel_multiplier =
6722 ((tmp & SDVO_MULTIPLIER_MASK)
6723 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6724 } else {
6725 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6726 * port and will be fixed up in the encoder->get_config
6727 * function. */
6728 pipe_config->pixel_multiplier = 1;
6729 }
6730 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6731 if (!IS_VALLEYVIEW(dev)) {
6732 /*
6733 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6734 * on 830. Filter it out here so that we don't
6735 * report errors due to that.
6736 */
6737 if (IS_I830(dev))
6738 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6739
6740 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6741 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6742 } else {
6743 /* Mask out read-only status bits. */
6744 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6745 DPLL_PORTC_READY_MASK |
6746 DPLL_PORTB_READY_MASK);
6747 }
6748
6749 if (IS_CHERRYVIEW(dev))
6750 chv_crtc_clock_get(crtc, pipe_config);
6751 else if (IS_VALLEYVIEW(dev))
6752 vlv_crtc_clock_get(crtc, pipe_config);
6753 else
6754 i9xx_crtc_clock_get(crtc, pipe_config);
6755
6756 return true;
6757 }
6758
6759 static void ironlake_init_pch_refclk(struct drm_device *dev)
6760 {
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 struct intel_encoder *encoder;
6763 u32 val, final;
6764 bool has_lvds = false;
6765 bool has_cpu_edp = false;
6766 bool has_panel = false;
6767 bool has_ck505 = false;
6768 bool can_ssc = false;
6769
6770 /* We need to take the global config into account */
6771 for_each_intel_encoder(dev, encoder) {
6772 switch (encoder->type) {
6773 case INTEL_OUTPUT_LVDS:
6774 has_panel = true;
6775 has_lvds = true;
6776 break;
6777 case INTEL_OUTPUT_EDP:
6778 has_panel = true;
6779 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6780 has_cpu_edp = true;
6781 break;
6782 default:
6783 break;
6784 }
6785 }
6786
6787 if (HAS_PCH_IBX(dev)) {
6788 has_ck505 = dev_priv->vbt.display_clock_mode;
6789 can_ssc = has_ck505;
6790 } else {
6791 has_ck505 = false;
6792 can_ssc = true;
6793 }
6794
6795 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6796 has_panel, has_lvds, has_ck505);
6797
6798 /* Ironlake: try to setup display ref clock before DPLL
6799 * enabling. This is only under driver's control after
6800 * PCH B stepping, previous chipset stepping should be
6801 * ignoring this setting.
6802 */
6803 val = I915_READ(PCH_DREF_CONTROL);
6804
6805 /* As we must carefully and slowly disable/enable each source in turn,
6806 * compute the final state we want first and check if we need to
6807 * make any changes at all.
6808 */
6809 final = val;
6810 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6811 if (has_ck505)
6812 final |= DREF_NONSPREAD_CK505_ENABLE;
6813 else
6814 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6815
6816 final &= ~DREF_SSC_SOURCE_MASK;
6817 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6818 final &= ~DREF_SSC1_ENABLE;
6819
6820 if (has_panel) {
6821 final |= DREF_SSC_SOURCE_ENABLE;
6822
6823 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6824 final |= DREF_SSC1_ENABLE;
6825
6826 if (has_cpu_edp) {
6827 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6828 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6829 else
6830 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6831 } else
6832 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6833 } else {
6834 final |= DREF_SSC_SOURCE_DISABLE;
6835 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6836 }
6837
6838 if (final == val)
6839 return;
6840
6841 /* Always enable nonspread source */
6842 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6843
6844 if (has_ck505)
6845 val |= DREF_NONSPREAD_CK505_ENABLE;
6846 else
6847 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6848
6849 if (has_panel) {
6850 val &= ~DREF_SSC_SOURCE_MASK;
6851 val |= DREF_SSC_SOURCE_ENABLE;
6852
6853 /* SSC must be turned on before enabling the CPU output */
6854 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6855 DRM_DEBUG_KMS("Using SSC on panel\n");
6856 val |= DREF_SSC1_ENABLE;
6857 } else
6858 val &= ~DREF_SSC1_ENABLE;
6859
6860 /* Get SSC going before enabling the outputs */
6861 I915_WRITE(PCH_DREF_CONTROL, val);
6862 POSTING_READ(PCH_DREF_CONTROL);
6863 udelay(200);
6864
6865 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6866
6867 /* Enable CPU source on CPU attached eDP */
6868 if (has_cpu_edp) {
6869 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6870 DRM_DEBUG_KMS("Using SSC on eDP\n");
6871 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6872 } else
6873 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6874 } else
6875 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6876
6877 I915_WRITE(PCH_DREF_CONTROL, val);
6878 POSTING_READ(PCH_DREF_CONTROL);
6879 udelay(200);
6880 } else {
6881 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6882
6883 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6884
6885 /* Turn off CPU output */
6886 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6887
6888 I915_WRITE(PCH_DREF_CONTROL, val);
6889 POSTING_READ(PCH_DREF_CONTROL);
6890 udelay(200);
6891
6892 /* Turn off the SSC source */
6893 val &= ~DREF_SSC_SOURCE_MASK;
6894 val |= DREF_SSC_SOURCE_DISABLE;
6895
6896 /* Turn off SSC1 */
6897 val &= ~DREF_SSC1_ENABLE;
6898
6899 I915_WRITE(PCH_DREF_CONTROL, val);
6900 POSTING_READ(PCH_DREF_CONTROL);
6901 udelay(200);
6902 }
6903
6904 BUG_ON(val != final);
6905 }
6906
6907 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6908 {
6909 uint32_t tmp;
6910
6911 tmp = I915_READ(SOUTH_CHICKEN2);
6912 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6913 I915_WRITE(SOUTH_CHICKEN2, tmp);
6914
6915 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6916 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6917 DRM_ERROR("FDI mPHY reset assert timeout\n");
6918
6919 tmp = I915_READ(SOUTH_CHICKEN2);
6920 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6921 I915_WRITE(SOUTH_CHICKEN2, tmp);
6922
6923 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6924 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6925 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6926 }
6927
6928 /* WaMPhyProgramming:hsw */
6929 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6930 {
6931 uint32_t tmp;
6932
6933 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6934 tmp &= ~(0xFF << 24);
6935 tmp |= (0x12 << 24);
6936 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6937
6938 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6939 tmp |= (1 << 11);
6940 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6941
6942 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6943 tmp |= (1 << 11);
6944 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6945
6946 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6947 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6948 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6949
6950 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6951 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6952 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6953
6954 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6955 tmp &= ~(7 << 13);
6956 tmp |= (5 << 13);
6957 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6958
6959 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6960 tmp &= ~(7 << 13);
6961 tmp |= (5 << 13);
6962 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6963
6964 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6965 tmp &= ~0xFF;
6966 tmp |= 0x1C;
6967 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6968
6969 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6970 tmp &= ~0xFF;
6971 tmp |= 0x1C;
6972 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6973
6974 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6975 tmp &= ~(0xFF << 16);
6976 tmp |= (0x1C << 16);
6977 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6978
6979 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6980 tmp &= ~(0xFF << 16);
6981 tmp |= (0x1C << 16);
6982 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6983
6984 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6985 tmp |= (1 << 27);
6986 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6987
6988 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6989 tmp |= (1 << 27);
6990 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6991
6992 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6993 tmp &= ~(0xF << 28);
6994 tmp |= (4 << 28);
6995 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6996
6997 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6998 tmp &= ~(0xF << 28);
6999 tmp |= (4 << 28);
7000 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7001 }
7002
7003 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7004 * Programming" based on the parameters passed:
7005 * - Sequence to enable CLKOUT_DP
7006 * - Sequence to enable CLKOUT_DP without spread
7007 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7008 */
7009 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7010 bool with_fdi)
7011 {
7012 struct drm_i915_private *dev_priv = dev->dev_private;
7013 uint32_t reg, tmp;
7014
7015 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7016 with_spread = true;
7017 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7018 with_fdi, "LP PCH doesn't have FDI\n"))
7019 with_fdi = false;
7020
7021 mutex_lock(&dev_priv->dpio_lock);
7022
7023 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7024 tmp &= ~SBI_SSCCTL_DISABLE;
7025 tmp |= SBI_SSCCTL_PATHALT;
7026 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7027
7028 udelay(24);
7029
7030 if (with_spread) {
7031 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7032 tmp &= ~SBI_SSCCTL_PATHALT;
7033 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7034
7035 if (with_fdi) {
7036 lpt_reset_fdi_mphy(dev_priv);
7037 lpt_program_fdi_mphy(dev_priv);
7038 }
7039 }
7040
7041 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7042 SBI_GEN0 : SBI_DBUFF0;
7043 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7044 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7045 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7046
7047 mutex_unlock(&dev_priv->dpio_lock);
7048 }
7049
7050 /* Sequence to disable CLKOUT_DP */
7051 static void lpt_disable_clkout_dp(struct drm_device *dev)
7052 {
7053 struct drm_i915_private *dev_priv = dev->dev_private;
7054 uint32_t reg, tmp;
7055
7056 mutex_lock(&dev_priv->dpio_lock);
7057
7058 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7059 SBI_GEN0 : SBI_DBUFF0;
7060 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7061 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7062 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7063
7064 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7065 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7066 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7067 tmp |= SBI_SSCCTL_PATHALT;
7068 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7069 udelay(32);
7070 }
7071 tmp |= SBI_SSCCTL_DISABLE;
7072 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7073 }
7074
7075 mutex_unlock(&dev_priv->dpio_lock);
7076 }
7077
7078 static void lpt_init_pch_refclk(struct drm_device *dev)
7079 {
7080 struct intel_encoder *encoder;
7081 bool has_vga = false;
7082
7083 for_each_intel_encoder(dev, encoder) {
7084 switch (encoder->type) {
7085 case INTEL_OUTPUT_ANALOG:
7086 has_vga = true;
7087 break;
7088 default:
7089 break;
7090 }
7091 }
7092
7093 if (has_vga)
7094 lpt_enable_clkout_dp(dev, true, true);
7095 else
7096 lpt_disable_clkout_dp(dev);
7097 }
7098
7099 /*
7100 * Initialize reference clocks when the driver loads
7101 */
7102 void intel_init_pch_refclk(struct drm_device *dev)
7103 {
7104 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7105 ironlake_init_pch_refclk(dev);
7106 else if (HAS_PCH_LPT(dev))
7107 lpt_init_pch_refclk(dev);
7108 }
7109
7110 static int ironlake_get_refclk(struct drm_crtc *crtc)
7111 {
7112 struct drm_device *dev = crtc->dev;
7113 struct drm_i915_private *dev_priv = dev->dev_private;
7114 struct intel_encoder *encoder;
7115 int num_connectors = 0;
7116 bool is_lvds = false;
7117
7118 for_each_intel_encoder(dev, encoder) {
7119 if (encoder->new_crtc != to_intel_crtc(crtc))
7120 continue;
7121
7122 switch (encoder->type) {
7123 case INTEL_OUTPUT_LVDS:
7124 is_lvds = true;
7125 break;
7126 default:
7127 break;
7128 }
7129 num_connectors++;
7130 }
7131
7132 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7133 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7134 dev_priv->vbt.lvds_ssc_freq);
7135 return dev_priv->vbt.lvds_ssc_freq;
7136 }
7137
7138 return 120000;
7139 }
7140
7141 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7142 {
7143 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7145 int pipe = intel_crtc->pipe;
7146 uint32_t val;
7147
7148 val = 0;
7149
7150 switch (intel_crtc->config->pipe_bpp) {
7151 case 18:
7152 val |= PIPECONF_6BPC;
7153 break;
7154 case 24:
7155 val |= PIPECONF_8BPC;
7156 break;
7157 case 30:
7158 val |= PIPECONF_10BPC;
7159 break;
7160 case 36:
7161 val |= PIPECONF_12BPC;
7162 break;
7163 default:
7164 /* Case prevented by intel_choose_pipe_bpp_dither. */
7165 BUG();
7166 }
7167
7168 if (intel_crtc->config->dither)
7169 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7170
7171 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7172 val |= PIPECONF_INTERLACED_ILK;
7173 else
7174 val |= PIPECONF_PROGRESSIVE;
7175
7176 if (intel_crtc->config->limited_color_range)
7177 val |= PIPECONF_COLOR_RANGE_SELECT;
7178
7179 I915_WRITE(PIPECONF(pipe), val);
7180 POSTING_READ(PIPECONF(pipe));
7181 }
7182
7183 /*
7184 * Set up the pipe CSC unit.
7185 *
7186 * Currently only full range RGB to limited range RGB conversion
7187 * is supported, but eventually this should handle various
7188 * RGB<->YCbCr scenarios as well.
7189 */
7190 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7191 {
7192 struct drm_device *dev = crtc->dev;
7193 struct drm_i915_private *dev_priv = dev->dev_private;
7194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195 int pipe = intel_crtc->pipe;
7196 uint16_t coeff = 0x7800; /* 1.0 */
7197
7198 /*
7199 * TODO: Check what kind of values actually come out of the pipe
7200 * with these coeff/postoff values and adjust to get the best
7201 * accuracy. Perhaps we even need to take the bpc value into
7202 * consideration.
7203 */
7204
7205 if (intel_crtc->config->limited_color_range)
7206 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7207
7208 /*
7209 * GY/GU and RY/RU should be the other way around according
7210 * to BSpec, but reality doesn't agree. Just set them up in
7211 * a way that results in the correct picture.
7212 */
7213 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7214 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7215
7216 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7217 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7218
7219 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7220 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7221
7222 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7223 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7224 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7225
7226 if (INTEL_INFO(dev)->gen > 6) {
7227 uint16_t postoff = 0;
7228
7229 if (intel_crtc->config->limited_color_range)
7230 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7231
7232 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7233 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7234 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7235
7236 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7237 } else {
7238 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7239
7240 if (intel_crtc->config->limited_color_range)
7241 mode |= CSC_BLACK_SCREEN_OFFSET;
7242
7243 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7244 }
7245 }
7246
7247 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7248 {
7249 struct drm_device *dev = crtc->dev;
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7252 enum pipe pipe = intel_crtc->pipe;
7253 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7254 uint32_t val;
7255
7256 val = 0;
7257
7258 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7259 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7260
7261 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7262 val |= PIPECONF_INTERLACED_ILK;
7263 else
7264 val |= PIPECONF_PROGRESSIVE;
7265
7266 I915_WRITE(PIPECONF(cpu_transcoder), val);
7267 POSTING_READ(PIPECONF(cpu_transcoder));
7268
7269 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7270 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7271
7272 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7273 val = 0;
7274
7275 switch (intel_crtc->config->pipe_bpp) {
7276 case 18:
7277 val |= PIPEMISC_DITHER_6_BPC;
7278 break;
7279 case 24:
7280 val |= PIPEMISC_DITHER_8_BPC;
7281 break;
7282 case 30:
7283 val |= PIPEMISC_DITHER_10_BPC;
7284 break;
7285 case 36:
7286 val |= PIPEMISC_DITHER_12_BPC;
7287 break;
7288 default:
7289 /* Case prevented by pipe_config_set_bpp. */
7290 BUG();
7291 }
7292
7293 if (intel_crtc->config->dither)
7294 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7295
7296 I915_WRITE(PIPEMISC(pipe), val);
7297 }
7298 }
7299
7300 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7301 struct intel_crtc_state *crtc_state,
7302 intel_clock_t *clock,
7303 bool *has_reduced_clock,
7304 intel_clock_t *reduced_clock)
7305 {
7306 struct drm_device *dev = crtc->dev;
7307 struct drm_i915_private *dev_priv = dev->dev_private;
7308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309 int refclk;
7310 const intel_limit_t *limit;
7311 bool ret, is_lvds = false;
7312
7313 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7314
7315 refclk = ironlake_get_refclk(crtc);
7316
7317 /*
7318 * Returns a set of divisors for the desired target clock with the given
7319 * refclk, or FALSE. The returned values represent the clock equation:
7320 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7321 */
7322 limit = intel_limit(intel_crtc, refclk);
7323 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7324 crtc_state->port_clock,
7325 refclk, NULL, clock);
7326 if (!ret)
7327 return false;
7328
7329 if (is_lvds && dev_priv->lvds_downclock_avail) {
7330 /*
7331 * Ensure we match the reduced clock's P to the target clock.
7332 * If the clocks don't match, we can't switch the display clock
7333 * by using the FP0/FP1. In such case we will disable the LVDS
7334 * downclock feature.
7335 */
7336 *has_reduced_clock =
7337 dev_priv->display.find_dpll(limit, intel_crtc,
7338 dev_priv->lvds_downclock,
7339 refclk, clock,
7340 reduced_clock);
7341 }
7342
7343 return true;
7344 }
7345
7346 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7347 {
7348 /*
7349 * Account for spread spectrum to avoid
7350 * oversubscribing the link. Max center spread
7351 * is 2.5%; use 5% for safety's sake.
7352 */
7353 u32 bps = target_clock * bpp * 21 / 20;
7354 return DIV_ROUND_UP(bps, link_bw * 8);
7355 }
7356
7357 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7358 {
7359 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7360 }
7361
7362 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7363 struct intel_crtc_state *crtc_state,
7364 u32 *fp,
7365 intel_clock_t *reduced_clock, u32 *fp2)
7366 {
7367 struct drm_crtc *crtc = &intel_crtc->base;
7368 struct drm_device *dev = crtc->dev;
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 struct intel_encoder *intel_encoder;
7371 uint32_t dpll;
7372 int factor, num_connectors = 0;
7373 bool is_lvds = false, is_sdvo = false;
7374
7375 for_each_intel_encoder(dev, intel_encoder) {
7376 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7377 continue;
7378
7379 switch (intel_encoder->type) {
7380 case INTEL_OUTPUT_LVDS:
7381 is_lvds = true;
7382 break;
7383 case INTEL_OUTPUT_SDVO:
7384 case INTEL_OUTPUT_HDMI:
7385 is_sdvo = true;
7386 break;
7387 default:
7388 break;
7389 }
7390
7391 num_connectors++;
7392 }
7393
7394 /* Enable autotuning of the PLL clock (if permissible) */
7395 factor = 21;
7396 if (is_lvds) {
7397 if ((intel_panel_use_ssc(dev_priv) &&
7398 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7399 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7400 factor = 25;
7401 } else if (crtc_state->sdvo_tv_clock)
7402 factor = 20;
7403
7404 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7405 *fp |= FP_CB_TUNE;
7406
7407 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7408 *fp2 |= FP_CB_TUNE;
7409
7410 dpll = 0;
7411
7412 if (is_lvds)
7413 dpll |= DPLLB_MODE_LVDS;
7414 else
7415 dpll |= DPLLB_MODE_DAC_SERIAL;
7416
7417 dpll |= (crtc_state->pixel_multiplier - 1)
7418 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7419
7420 if (is_sdvo)
7421 dpll |= DPLL_SDVO_HIGH_SPEED;
7422 if (crtc_state->has_dp_encoder)
7423 dpll |= DPLL_SDVO_HIGH_SPEED;
7424
7425 /* compute bitmask from p1 value */
7426 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7427 /* also FPA1 */
7428 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7429
7430 switch (crtc_state->dpll.p2) {
7431 case 5:
7432 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7433 break;
7434 case 7:
7435 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7436 break;
7437 case 10:
7438 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7439 break;
7440 case 14:
7441 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7442 break;
7443 }
7444
7445 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7446 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7447 else
7448 dpll |= PLL_REF_INPUT_DREFCLK;
7449
7450 return dpll | DPLL_VCO_ENABLE;
7451 }
7452
7453 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7454 struct intel_crtc_state *crtc_state)
7455 {
7456 struct drm_device *dev = crtc->base.dev;
7457 intel_clock_t clock, reduced_clock;
7458 u32 dpll = 0, fp = 0, fp2 = 0;
7459 bool ok, has_reduced_clock = false;
7460 bool is_lvds = false;
7461 struct intel_shared_dpll *pll;
7462
7463 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7464
7465 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7466 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7467
7468 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7469 &has_reduced_clock, &reduced_clock);
7470 if (!ok && !crtc_state->clock_set) {
7471 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7472 return -EINVAL;
7473 }
7474 /* Compat-code for transition, will disappear. */
7475 if (!crtc_state->clock_set) {
7476 crtc_state->dpll.n = clock.n;
7477 crtc_state->dpll.m1 = clock.m1;
7478 crtc_state->dpll.m2 = clock.m2;
7479 crtc_state->dpll.p1 = clock.p1;
7480 crtc_state->dpll.p2 = clock.p2;
7481 }
7482
7483 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7484 if (crtc_state->has_pch_encoder) {
7485 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7486 if (has_reduced_clock)
7487 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7488
7489 dpll = ironlake_compute_dpll(crtc, crtc_state,
7490 &fp, &reduced_clock,
7491 has_reduced_clock ? &fp2 : NULL);
7492
7493 crtc_state->dpll_hw_state.dpll = dpll;
7494 crtc_state->dpll_hw_state.fp0 = fp;
7495 if (has_reduced_clock)
7496 crtc_state->dpll_hw_state.fp1 = fp2;
7497 else
7498 crtc_state->dpll_hw_state.fp1 = fp;
7499
7500 pll = intel_get_shared_dpll(crtc, crtc_state);
7501 if (pll == NULL) {
7502 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7503 pipe_name(crtc->pipe));
7504 return -EINVAL;
7505 }
7506 }
7507
7508 if (is_lvds && has_reduced_clock && i915.powersave)
7509 crtc->lowfreq_avail = true;
7510 else
7511 crtc->lowfreq_avail = false;
7512
7513 return 0;
7514 }
7515
7516 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7517 struct intel_link_m_n *m_n)
7518 {
7519 struct drm_device *dev = crtc->base.dev;
7520 struct drm_i915_private *dev_priv = dev->dev_private;
7521 enum pipe pipe = crtc->pipe;
7522
7523 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7524 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7525 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7526 & ~TU_SIZE_MASK;
7527 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7528 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7529 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7530 }
7531
7532 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7533 enum transcoder transcoder,
7534 struct intel_link_m_n *m_n,
7535 struct intel_link_m_n *m2_n2)
7536 {
7537 struct drm_device *dev = crtc->base.dev;
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 enum pipe pipe = crtc->pipe;
7540
7541 if (INTEL_INFO(dev)->gen >= 5) {
7542 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7543 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7544 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7545 & ~TU_SIZE_MASK;
7546 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7547 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7548 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7549 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7550 * gen < 8) and if DRRS is supported (to make sure the
7551 * registers are not unnecessarily read).
7552 */
7553 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7554 crtc->config->has_drrs) {
7555 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7556 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7557 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7558 & ~TU_SIZE_MASK;
7559 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7560 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7561 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7562 }
7563 } else {
7564 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7565 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7566 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7567 & ~TU_SIZE_MASK;
7568 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7569 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7570 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7571 }
7572 }
7573
7574 void intel_dp_get_m_n(struct intel_crtc *crtc,
7575 struct intel_crtc_state *pipe_config)
7576 {
7577 if (pipe_config->has_pch_encoder)
7578 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7579 else
7580 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7581 &pipe_config->dp_m_n,
7582 &pipe_config->dp_m2_n2);
7583 }
7584
7585 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7586 struct intel_crtc_state *pipe_config)
7587 {
7588 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7589 &pipe_config->fdi_m_n, NULL);
7590 }
7591
7592 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7593 struct intel_crtc_state *pipe_config)
7594 {
7595 struct drm_device *dev = crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7597 uint32_t tmp;
7598
7599 tmp = I915_READ(PS_CTL(crtc->pipe));
7600
7601 if (tmp & PS_ENABLE) {
7602 pipe_config->pch_pfit.enabled = true;
7603 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7604 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7605 }
7606 }
7607
7608 static void
7609 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7610 struct intel_initial_plane_config *plane_config)
7611 {
7612 struct drm_device *dev = crtc->base.dev;
7613 struct drm_i915_private *dev_priv = dev->dev_private;
7614 u32 val, base, offset, stride_mult;
7615 int pipe = crtc->pipe;
7616 int fourcc, pixel_format;
7617 int aligned_height;
7618 struct drm_framebuffer *fb;
7619 struct intel_framebuffer *intel_fb;
7620
7621 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7622 if (!intel_fb) {
7623 DRM_DEBUG_KMS("failed to alloc fb\n");
7624 return;
7625 }
7626
7627 fb = &intel_fb->base;
7628
7629 val = I915_READ(PLANE_CTL(pipe, 0));
7630 if (val & PLANE_CTL_TILED_MASK)
7631 plane_config->tiling = I915_TILING_X;
7632
7633 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7634 fourcc = skl_format_to_fourcc(pixel_format,
7635 val & PLANE_CTL_ORDER_RGBX,
7636 val & PLANE_CTL_ALPHA_MASK);
7637 fb->pixel_format = fourcc;
7638 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7639
7640 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7641 plane_config->base = base;
7642
7643 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7644
7645 val = I915_READ(PLANE_SIZE(pipe, 0));
7646 fb->height = ((val >> 16) & 0xfff) + 1;
7647 fb->width = ((val >> 0) & 0x1fff) + 1;
7648
7649 val = I915_READ(PLANE_STRIDE(pipe, 0));
7650 switch (plane_config->tiling) {
7651 case I915_TILING_NONE:
7652 stride_mult = 64;
7653 break;
7654 case I915_TILING_X:
7655 stride_mult = 512;
7656 break;
7657 default:
7658 MISSING_CASE(plane_config->tiling);
7659 goto error;
7660 }
7661 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7662
7663 aligned_height = intel_fb_align_height(dev, fb->height,
7664 plane_config->tiling);
7665
7666 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7667
7668 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7669 pipe_name(pipe), fb->width, fb->height,
7670 fb->bits_per_pixel, base, fb->pitches[0],
7671 plane_config->size);
7672
7673 crtc->base.primary->fb = fb;
7674 return;
7675
7676 error:
7677 kfree(fb);
7678 }
7679
7680 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7681 struct intel_crtc_state *pipe_config)
7682 {
7683 struct drm_device *dev = crtc->base.dev;
7684 struct drm_i915_private *dev_priv = dev->dev_private;
7685 uint32_t tmp;
7686
7687 tmp = I915_READ(PF_CTL(crtc->pipe));
7688
7689 if (tmp & PF_ENABLE) {
7690 pipe_config->pch_pfit.enabled = true;
7691 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7692 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7693
7694 /* We currently do not free assignements of panel fitters on
7695 * ivb/hsw (since we don't use the higher upscaling modes which
7696 * differentiates them) so just WARN about this case for now. */
7697 if (IS_GEN7(dev)) {
7698 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7699 PF_PIPE_SEL_IVB(crtc->pipe));
7700 }
7701 }
7702 }
7703
7704 static void
7705 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7706 struct intel_initial_plane_config *plane_config)
7707 {
7708 struct drm_device *dev = crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 u32 val, base, offset;
7711 int pipe = crtc->pipe;
7712 int fourcc, pixel_format;
7713 int aligned_height;
7714 struct drm_framebuffer *fb;
7715 struct intel_framebuffer *intel_fb;
7716
7717 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7718 if (!intel_fb) {
7719 DRM_DEBUG_KMS("failed to alloc fb\n");
7720 return;
7721 }
7722
7723 fb = &intel_fb->base;
7724
7725 val = I915_READ(DSPCNTR(pipe));
7726
7727 if (INTEL_INFO(dev)->gen >= 4)
7728 if (val & DISPPLANE_TILED)
7729 plane_config->tiling = I915_TILING_X;
7730
7731 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7732 fourcc = i9xx_format_to_fourcc(pixel_format);
7733 fb->pixel_format = fourcc;
7734 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7735
7736 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7737 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7738 offset = I915_READ(DSPOFFSET(pipe));
7739 } else {
7740 if (plane_config->tiling)
7741 offset = I915_READ(DSPTILEOFF(pipe));
7742 else
7743 offset = I915_READ(DSPLINOFF(pipe));
7744 }
7745 plane_config->base = base;
7746
7747 val = I915_READ(PIPESRC(pipe));
7748 fb->width = ((val >> 16) & 0xfff) + 1;
7749 fb->height = ((val >> 0) & 0xfff) + 1;
7750
7751 val = I915_READ(DSPSTRIDE(pipe));
7752 fb->pitches[0] = val & 0xffffffc0;
7753
7754 aligned_height = intel_fb_align_height(dev, fb->height,
7755 plane_config->tiling);
7756
7757 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7758
7759 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7760 pipe_name(pipe), fb->width, fb->height,
7761 fb->bits_per_pixel, base, fb->pitches[0],
7762 plane_config->size);
7763
7764 crtc->base.primary->fb = fb;
7765 }
7766
7767 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7768 struct intel_crtc_state *pipe_config)
7769 {
7770 struct drm_device *dev = crtc->base.dev;
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 uint32_t tmp;
7773
7774 if (!intel_display_power_is_enabled(dev_priv,
7775 POWER_DOMAIN_PIPE(crtc->pipe)))
7776 return false;
7777
7778 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7779 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7780
7781 tmp = I915_READ(PIPECONF(crtc->pipe));
7782 if (!(tmp & PIPECONF_ENABLE))
7783 return false;
7784
7785 switch (tmp & PIPECONF_BPC_MASK) {
7786 case PIPECONF_6BPC:
7787 pipe_config->pipe_bpp = 18;
7788 break;
7789 case PIPECONF_8BPC:
7790 pipe_config->pipe_bpp = 24;
7791 break;
7792 case PIPECONF_10BPC:
7793 pipe_config->pipe_bpp = 30;
7794 break;
7795 case PIPECONF_12BPC:
7796 pipe_config->pipe_bpp = 36;
7797 break;
7798 default:
7799 break;
7800 }
7801
7802 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7803 pipe_config->limited_color_range = true;
7804
7805 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7806 struct intel_shared_dpll *pll;
7807
7808 pipe_config->has_pch_encoder = true;
7809
7810 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7811 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7812 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7813
7814 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7815
7816 if (HAS_PCH_IBX(dev_priv->dev)) {
7817 pipe_config->shared_dpll =
7818 (enum intel_dpll_id) crtc->pipe;
7819 } else {
7820 tmp = I915_READ(PCH_DPLL_SEL);
7821 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7822 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7823 else
7824 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7825 }
7826
7827 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7828
7829 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7830 &pipe_config->dpll_hw_state));
7831
7832 tmp = pipe_config->dpll_hw_state.dpll;
7833 pipe_config->pixel_multiplier =
7834 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7835 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7836
7837 ironlake_pch_clock_get(crtc, pipe_config);
7838 } else {
7839 pipe_config->pixel_multiplier = 1;
7840 }
7841
7842 intel_get_pipe_timings(crtc, pipe_config);
7843
7844 ironlake_get_pfit_config(crtc, pipe_config);
7845
7846 return true;
7847 }
7848
7849 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7850 {
7851 struct drm_device *dev = dev_priv->dev;
7852 struct intel_crtc *crtc;
7853
7854 for_each_intel_crtc(dev, crtc)
7855 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
7856 pipe_name(crtc->pipe));
7857
7858 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7859 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7860 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7861 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7862 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7863 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7864 "CPU PWM1 enabled\n");
7865 if (IS_HASWELL(dev))
7866 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7867 "CPU PWM2 enabled\n");
7868 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7869 "PCH PWM1 enabled\n");
7870 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7871 "Utility pin enabled\n");
7872 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7873
7874 /*
7875 * In theory we can still leave IRQs enabled, as long as only the HPD
7876 * interrupts remain enabled. We used to check for that, but since it's
7877 * gen-specific and since we only disable LCPLL after we fully disable
7878 * the interrupts, the check below should be enough.
7879 */
7880 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7881 }
7882
7883 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7884 {
7885 struct drm_device *dev = dev_priv->dev;
7886
7887 if (IS_HASWELL(dev))
7888 return I915_READ(D_COMP_HSW);
7889 else
7890 return I915_READ(D_COMP_BDW);
7891 }
7892
7893 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7894 {
7895 struct drm_device *dev = dev_priv->dev;
7896
7897 if (IS_HASWELL(dev)) {
7898 mutex_lock(&dev_priv->rps.hw_lock);
7899 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7900 val))
7901 DRM_ERROR("Failed to write to D_COMP\n");
7902 mutex_unlock(&dev_priv->rps.hw_lock);
7903 } else {
7904 I915_WRITE(D_COMP_BDW, val);
7905 POSTING_READ(D_COMP_BDW);
7906 }
7907 }
7908
7909 /*
7910 * This function implements pieces of two sequences from BSpec:
7911 * - Sequence for display software to disable LCPLL
7912 * - Sequence for display software to allow package C8+
7913 * The steps implemented here are just the steps that actually touch the LCPLL
7914 * register. Callers should take care of disabling all the display engine
7915 * functions, doing the mode unset, fixing interrupts, etc.
7916 */
7917 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7918 bool switch_to_fclk, bool allow_power_down)
7919 {
7920 uint32_t val;
7921
7922 assert_can_disable_lcpll(dev_priv);
7923
7924 val = I915_READ(LCPLL_CTL);
7925
7926 if (switch_to_fclk) {
7927 val |= LCPLL_CD_SOURCE_FCLK;
7928 I915_WRITE(LCPLL_CTL, val);
7929
7930 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7931 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7932 DRM_ERROR("Switching to FCLK failed\n");
7933
7934 val = I915_READ(LCPLL_CTL);
7935 }
7936
7937 val |= LCPLL_PLL_DISABLE;
7938 I915_WRITE(LCPLL_CTL, val);
7939 POSTING_READ(LCPLL_CTL);
7940
7941 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7942 DRM_ERROR("LCPLL still locked\n");
7943
7944 val = hsw_read_dcomp(dev_priv);
7945 val |= D_COMP_COMP_DISABLE;
7946 hsw_write_dcomp(dev_priv, val);
7947 ndelay(100);
7948
7949 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7950 1))
7951 DRM_ERROR("D_COMP RCOMP still in progress\n");
7952
7953 if (allow_power_down) {
7954 val = I915_READ(LCPLL_CTL);
7955 val |= LCPLL_POWER_DOWN_ALLOW;
7956 I915_WRITE(LCPLL_CTL, val);
7957 POSTING_READ(LCPLL_CTL);
7958 }
7959 }
7960
7961 /*
7962 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7963 * source.
7964 */
7965 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7966 {
7967 uint32_t val;
7968
7969 val = I915_READ(LCPLL_CTL);
7970
7971 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7972 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7973 return;
7974
7975 /*
7976 * Make sure we're not on PC8 state before disabling PC8, otherwise
7977 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7978 */
7979 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7980
7981 if (val & LCPLL_POWER_DOWN_ALLOW) {
7982 val &= ~LCPLL_POWER_DOWN_ALLOW;
7983 I915_WRITE(LCPLL_CTL, val);
7984 POSTING_READ(LCPLL_CTL);
7985 }
7986
7987 val = hsw_read_dcomp(dev_priv);
7988 val |= D_COMP_COMP_FORCE;
7989 val &= ~D_COMP_COMP_DISABLE;
7990 hsw_write_dcomp(dev_priv, val);
7991
7992 val = I915_READ(LCPLL_CTL);
7993 val &= ~LCPLL_PLL_DISABLE;
7994 I915_WRITE(LCPLL_CTL, val);
7995
7996 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7997 DRM_ERROR("LCPLL not locked yet\n");
7998
7999 if (val & LCPLL_CD_SOURCE_FCLK) {
8000 val = I915_READ(LCPLL_CTL);
8001 val &= ~LCPLL_CD_SOURCE_FCLK;
8002 I915_WRITE(LCPLL_CTL, val);
8003
8004 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8005 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8006 DRM_ERROR("Switching back to LCPLL failed\n");
8007 }
8008
8009 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8010 }
8011
8012 /*
8013 * Package states C8 and deeper are really deep PC states that can only be
8014 * reached when all the devices on the system allow it, so even if the graphics
8015 * device allows PC8+, it doesn't mean the system will actually get to these
8016 * states. Our driver only allows PC8+ when going into runtime PM.
8017 *
8018 * The requirements for PC8+ are that all the outputs are disabled, the power
8019 * well is disabled and most interrupts are disabled, and these are also
8020 * requirements for runtime PM. When these conditions are met, we manually do
8021 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8022 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8023 * hang the machine.
8024 *
8025 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8026 * the state of some registers, so when we come back from PC8+ we need to
8027 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8028 * need to take care of the registers kept by RC6. Notice that this happens even
8029 * if we don't put the device in PCI D3 state (which is what currently happens
8030 * because of the runtime PM support).
8031 *
8032 * For more, read "Display Sequences for Package C8" on the hardware
8033 * documentation.
8034 */
8035 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8036 {
8037 struct drm_device *dev = dev_priv->dev;
8038 uint32_t val;
8039
8040 DRM_DEBUG_KMS("Enabling package C8+\n");
8041
8042 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8043 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8044 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8045 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8046 }
8047
8048 lpt_disable_clkout_dp(dev);
8049 hsw_disable_lcpll(dev_priv, true, true);
8050 }
8051
8052 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8053 {
8054 struct drm_device *dev = dev_priv->dev;
8055 uint32_t val;
8056
8057 DRM_DEBUG_KMS("Disabling package C8+\n");
8058
8059 hsw_restore_lcpll(dev_priv);
8060 lpt_init_pch_refclk(dev);
8061
8062 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8063 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8064 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8065 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8066 }
8067
8068 intel_prepare_ddi(dev);
8069 }
8070
8071 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8072 struct intel_crtc_state *crtc_state)
8073 {
8074 if (!intel_ddi_pll_select(crtc, crtc_state))
8075 return -EINVAL;
8076
8077 crtc->lowfreq_avail = false;
8078
8079 return 0;
8080 }
8081
8082 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8083 enum port port,
8084 struct intel_crtc_state *pipe_config)
8085 {
8086 u32 temp, dpll_ctl1;
8087
8088 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8089 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8090
8091 switch (pipe_config->ddi_pll_sel) {
8092 case SKL_DPLL0:
8093 /*
8094 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8095 * of the shared DPLL framework and thus needs to be read out
8096 * separately
8097 */
8098 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8099 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8100 break;
8101 case SKL_DPLL1:
8102 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8103 break;
8104 case SKL_DPLL2:
8105 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8106 break;
8107 case SKL_DPLL3:
8108 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8109 break;
8110 }
8111 }
8112
8113 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8114 enum port port,
8115 struct intel_crtc_state *pipe_config)
8116 {
8117 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8118
8119 switch (pipe_config->ddi_pll_sel) {
8120 case PORT_CLK_SEL_WRPLL1:
8121 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8122 break;
8123 case PORT_CLK_SEL_WRPLL2:
8124 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8125 break;
8126 }
8127 }
8128
8129 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8130 struct intel_crtc_state *pipe_config)
8131 {
8132 struct drm_device *dev = crtc->base.dev;
8133 struct drm_i915_private *dev_priv = dev->dev_private;
8134 struct intel_shared_dpll *pll;
8135 enum port port;
8136 uint32_t tmp;
8137
8138 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8139
8140 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8141
8142 if (IS_SKYLAKE(dev))
8143 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8144 else
8145 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8146
8147 if (pipe_config->shared_dpll >= 0) {
8148 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8149
8150 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8151 &pipe_config->dpll_hw_state));
8152 }
8153
8154 /*
8155 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8156 * DDI E. So just check whether this pipe is wired to DDI E and whether
8157 * the PCH transcoder is on.
8158 */
8159 if (INTEL_INFO(dev)->gen < 9 &&
8160 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8161 pipe_config->has_pch_encoder = true;
8162
8163 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8164 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8165 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8166
8167 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8168 }
8169 }
8170
8171 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8172 struct intel_crtc_state *pipe_config)
8173 {
8174 struct drm_device *dev = crtc->base.dev;
8175 struct drm_i915_private *dev_priv = dev->dev_private;
8176 enum intel_display_power_domain pfit_domain;
8177 uint32_t tmp;
8178
8179 if (!intel_display_power_is_enabled(dev_priv,
8180 POWER_DOMAIN_PIPE(crtc->pipe)))
8181 return false;
8182
8183 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8184 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8185
8186 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8187 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8188 enum pipe trans_edp_pipe;
8189 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8190 default:
8191 WARN(1, "unknown pipe linked to edp transcoder\n");
8192 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8193 case TRANS_DDI_EDP_INPUT_A_ON:
8194 trans_edp_pipe = PIPE_A;
8195 break;
8196 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8197 trans_edp_pipe = PIPE_B;
8198 break;
8199 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8200 trans_edp_pipe = PIPE_C;
8201 break;
8202 }
8203
8204 if (trans_edp_pipe == crtc->pipe)
8205 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8206 }
8207
8208 if (!intel_display_power_is_enabled(dev_priv,
8209 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8210 return false;
8211
8212 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8213 if (!(tmp & PIPECONF_ENABLE))
8214 return false;
8215
8216 haswell_get_ddi_port_state(crtc, pipe_config);
8217
8218 intel_get_pipe_timings(crtc, pipe_config);
8219
8220 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8221 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8222 if (IS_SKYLAKE(dev))
8223 skylake_get_pfit_config(crtc, pipe_config);
8224 else
8225 ironlake_get_pfit_config(crtc, pipe_config);
8226 }
8227
8228 if (IS_HASWELL(dev))
8229 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8230 (I915_READ(IPS_CTL) & IPS_ENABLE);
8231
8232 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8233 pipe_config->pixel_multiplier =
8234 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8235 } else {
8236 pipe_config->pixel_multiplier = 1;
8237 }
8238
8239 return true;
8240 }
8241
8242 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8243 {
8244 struct drm_device *dev = crtc->dev;
8245 struct drm_i915_private *dev_priv = dev->dev_private;
8246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8247 uint32_t cntl = 0, size = 0;
8248
8249 if (base) {
8250 unsigned int width = intel_crtc->cursor_width;
8251 unsigned int height = intel_crtc->cursor_height;
8252 unsigned int stride = roundup_pow_of_two(width) * 4;
8253
8254 switch (stride) {
8255 default:
8256 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8257 width, stride);
8258 stride = 256;
8259 /* fallthrough */
8260 case 256:
8261 case 512:
8262 case 1024:
8263 case 2048:
8264 break;
8265 }
8266
8267 cntl |= CURSOR_ENABLE |
8268 CURSOR_GAMMA_ENABLE |
8269 CURSOR_FORMAT_ARGB |
8270 CURSOR_STRIDE(stride);
8271
8272 size = (height << 12) | width;
8273 }
8274
8275 if (intel_crtc->cursor_cntl != 0 &&
8276 (intel_crtc->cursor_base != base ||
8277 intel_crtc->cursor_size != size ||
8278 intel_crtc->cursor_cntl != cntl)) {
8279 /* On these chipsets we can only modify the base/size/stride
8280 * whilst the cursor is disabled.
8281 */
8282 I915_WRITE(_CURACNTR, 0);
8283 POSTING_READ(_CURACNTR);
8284 intel_crtc->cursor_cntl = 0;
8285 }
8286
8287 if (intel_crtc->cursor_base != base) {
8288 I915_WRITE(_CURABASE, base);
8289 intel_crtc->cursor_base = base;
8290 }
8291
8292 if (intel_crtc->cursor_size != size) {
8293 I915_WRITE(CURSIZE, size);
8294 intel_crtc->cursor_size = size;
8295 }
8296
8297 if (intel_crtc->cursor_cntl != cntl) {
8298 I915_WRITE(_CURACNTR, cntl);
8299 POSTING_READ(_CURACNTR);
8300 intel_crtc->cursor_cntl = cntl;
8301 }
8302 }
8303
8304 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8305 {
8306 struct drm_device *dev = crtc->dev;
8307 struct drm_i915_private *dev_priv = dev->dev_private;
8308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8309 int pipe = intel_crtc->pipe;
8310 uint32_t cntl;
8311
8312 cntl = 0;
8313 if (base) {
8314 cntl = MCURSOR_GAMMA_ENABLE;
8315 switch (intel_crtc->cursor_width) {
8316 case 64:
8317 cntl |= CURSOR_MODE_64_ARGB_AX;
8318 break;
8319 case 128:
8320 cntl |= CURSOR_MODE_128_ARGB_AX;
8321 break;
8322 case 256:
8323 cntl |= CURSOR_MODE_256_ARGB_AX;
8324 break;
8325 default:
8326 MISSING_CASE(intel_crtc->cursor_width);
8327 return;
8328 }
8329 cntl |= pipe << 28; /* Connect to correct pipe */
8330
8331 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8332 cntl |= CURSOR_PIPE_CSC_ENABLE;
8333 }
8334
8335 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8336 cntl |= CURSOR_ROTATE_180;
8337
8338 if (intel_crtc->cursor_cntl != cntl) {
8339 I915_WRITE(CURCNTR(pipe), cntl);
8340 POSTING_READ(CURCNTR(pipe));
8341 intel_crtc->cursor_cntl = cntl;
8342 }
8343
8344 /* and commit changes on next vblank */
8345 I915_WRITE(CURBASE(pipe), base);
8346 POSTING_READ(CURBASE(pipe));
8347
8348 intel_crtc->cursor_base = base;
8349 }
8350
8351 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8352 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8353 bool on)
8354 {
8355 struct drm_device *dev = crtc->dev;
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8358 int pipe = intel_crtc->pipe;
8359 int x = crtc->cursor_x;
8360 int y = crtc->cursor_y;
8361 u32 base = 0, pos = 0;
8362
8363 if (on)
8364 base = intel_crtc->cursor_addr;
8365
8366 if (x >= intel_crtc->config->pipe_src_w)
8367 base = 0;
8368
8369 if (y >= intel_crtc->config->pipe_src_h)
8370 base = 0;
8371
8372 if (x < 0) {
8373 if (x + intel_crtc->cursor_width <= 0)
8374 base = 0;
8375
8376 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8377 x = -x;
8378 }
8379 pos |= x << CURSOR_X_SHIFT;
8380
8381 if (y < 0) {
8382 if (y + intel_crtc->cursor_height <= 0)
8383 base = 0;
8384
8385 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8386 y = -y;
8387 }
8388 pos |= y << CURSOR_Y_SHIFT;
8389
8390 if (base == 0 && intel_crtc->cursor_base == 0)
8391 return;
8392
8393 I915_WRITE(CURPOS(pipe), pos);
8394
8395 /* ILK+ do this automagically */
8396 if (HAS_GMCH_DISPLAY(dev) &&
8397 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8398 base += (intel_crtc->cursor_height *
8399 intel_crtc->cursor_width - 1) * 4;
8400 }
8401
8402 if (IS_845G(dev) || IS_I865G(dev))
8403 i845_update_cursor(crtc, base);
8404 else
8405 i9xx_update_cursor(crtc, base);
8406 }
8407
8408 static bool cursor_size_ok(struct drm_device *dev,
8409 uint32_t width, uint32_t height)
8410 {
8411 if (width == 0 || height == 0)
8412 return false;
8413
8414 /*
8415 * 845g/865g are special in that they are only limited by
8416 * the width of their cursors, the height is arbitrary up to
8417 * the precision of the register. Everything else requires
8418 * square cursors, limited to a few power-of-two sizes.
8419 */
8420 if (IS_845G(dev) || IS_I865G(dev)) {
8421 if ((width & 63) != 0)
8422 return false;
8423
8424 if (width > (IS_845G(dev) ? 64 : 512))
8425 return false;
8426
8427 if (height > 1023)
8428 return false;
8429 } else {
8430 switch (width | height) {
8431 case 256:
8432 case 128:
8433 if (IS_GEN2(dev))
8434 return false;
8435 case 64:
8436 break;
8437 default:
8438 return false;
8439 }
8440 }
8441
8442 return true;
8443 }
8444
8445 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8446 u16 *blue, uint32_t start, uint32_t size)
8447 {
8448 int end = (start + size > 256) ? 256 : start + size, i;
8449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8450
8451 for (i = start; i < end; i++) {
8452 intel_crtc->lut_r[i] = red[i] >> 8;
8453 intel_crtc->lut_g[i] = green[i] >> 8;
8454 intel_crtc->lut_b[i] = blue[i] >> 8;
8455 }
8456
8457 intel_crtc_load_lut(crtc);
8458 }
8459
8460 /* VESA 640x480x72Hz mode to set on the pipe */
8461 static struct drm_display_mode load_detect_mode = {
8462 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8463 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8464 };
8465
8466 struct drm_framebuffer *
8467 __intel_framebuffer_create(struct drm_device *dev,
8468 struct drm_mode_fb_cmd2 *mode_cmd,
8469 struct drm_i915_gem_object *obj)
8470 {
8471 struct intel_framebuffer *intel_fb;
8472 int ret;
8473
8474 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8475 if (!intel_fb) {
8476 drm_gem_object_unreference(&obj->base);
8477 return ERR_PTR(-ENOMEM);
8478 }
8479
8480 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8481 if (ret)
8482 goto err;
8483
8484 return &intel_fb->base;
8485 err:
8486 drm_gem_object_unreference(&obj->base);
8487 kfree(intel_fb);
8488
8489 return ERR_PTR(ret);
8490 }
8491
8492 static struct drm_framebuffer *
8493 intel_framebuffer_create(struct drm_device *dev,
8494 struct drm_mode_fb_cmd2 *mode_cmd,
8495 struct drm_i915_gem_object *obj)
8496 {
8497 struct drm_framebuffer *fb;
8498 int ret;
8499
8500 ret = i915_mutex_lock_interruptible(dev);
8501 if (ret)
8502 return ERR_PTR(ret);
8503 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8504 mutex_unlock(&dev->struct_mutex);
8505
8506 return fb;
8507 }
8508
8509 static u32
8510 intel_framebuffer_pitch_for_width(int width, int bpp)
8511 {
8512 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8513 return ALIGN(pitch, 64);
8514 }
8515
8516 static u32
8517 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8518 {
8519 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8520 return PAGE_ALIGN(pitch * mode->vdisplay);
8521 }
8522
8523 static struct drm_framebuffer *
8524 intel_framebuffer_create_for_mode(struct drm_device *dev,
8525 struct drm_display_mode *mode,
8526 int depth, int bpp)
8527 {
8528 struct drm_i915_gem_object *obj;
8529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8530
8531 obj = i915_gem_alloc_object(dev,
8532 intel_framebuffer_size_for_mode(mode, bpp));
8533 if (obj == NULL)
8534 return ERR_PTR(-ENOMEM);
8535
8536 mode_cmd.width = mode->hdisplay;
8537 mode_cmd.height = mode->vdisplay;
8538 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8539 bpp);
8540 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8541
8542 return intel_framebuffer_create(dev, &mode_cmd, obj);
8543 }
8544
8545 static struct drm_framebuffer *
8546 mode_fits_in_fbdev(struct drm_device *dev,
8547 struct drm_display_mode *mode)
8548 {
8549 #ifdef CONFIG_DRM_I915_FBDEV
8550 struct drm_i915_private *dev_priv = dev->dev_private;
8551 struct drm_i915_gem_object *obj;
8552 struct drm_framebuffer *fb;
8553
8554 if (!dev_priv->fbdev)
8555 return NULL;
8556
8557 if (!dev_priv->fbdev->fb)
8558 return NULL;
8559
8560 obj = dev_priv->fbdev->fb->obj;
8561 BUG_ON(!obj);
8562
8563 fb = &dev_priv->fbdev->fb->base;
8564 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8565 fb->bits_per_pixel))
8566 return NULL;
8567
8568 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8569 return NULL;
8570
8571 return fb;
8572 #else
8573 return NULL;
8574 #endif
8575 }
8576
8577 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8578 struct drm_display_mode *mode,
8579 struct intel_load_detect_pipe *old,
8580 struct drm_modeset_acquire_ctx *ctx)
8581 {
8582 struct intel_crtc *intel_crtc;
8583 struct intel_encoder *intel_encoder =
8584 intel_attached_encoder(connector);
8585 struct drm_crtc *possible_crtc;
8586 struct drm_encoder *encoder = &intel_encoder->base;
8587 struct drm_crtc *crtc = NULL;
8588 struct drm_device *dev = encoder->dev;
8589 struct drm_framebuffer *fb;
8590 struct drm_mode_config *config = &dev->mode_config;
8591 int ret, i = -1;
8592
8593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8594 connector->base.id, connector->name,
8595 encoder->base.id, encoder->name);
8596
8597 retry:
8598 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8599 if (ret)
8600 goto fail_unlock;
8601
8602 /*
8603 * Algorithm gets a little messy:
8604 *
8605 * - if the connector already has an assigned crtc, use it (but make
8606 * sure it's on first)
8607 *
8608 * - try to find the first unused crtc that can drive this connector,
8609 * and use that if we find one
8610 */
8611
8612 /* See if we already have a CRTC for this connector */
8613 if (encoder->crtc) {
8614 crtc = encoder->crtc;
8615
8616 ret = drm_modeset_lock(&crtc->mutex, ctx);
8617 if (ret)
8618 goto fail_unlock;
8619 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8620 if (ret)
8621 goto fail_unlock;
8622
8623 old->dpms_mode = connector->dpms;
8624 old->load_detect_temp = false;
8625
8626 /* Make sure the crtc and connector are running */
8627 if (connector->dpms != DRM_MODE_DPMS_ON)
8628 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8629
8630 return true;
8631 }
8632
8633 /* Find an unused one (if possible) */
8634 for_each_crtc(dev, possible_crtc) {
8635 i++;
8636 if (!(encoder->possible_crtcs & (1 << i)))
8637 continue;
8638 if (possible_crtc->enabled)
8639 continue;
8640 /* This can occur when applying the pipe A quirk on resume. */
8641 if (to_intel_crtc(possible_crtc)->new_enabled)
8642 continue;
8643
8644 crtc = possible_crtc;
8645 break;
8646 }
8647
8648 /*
8649 * If we didn't find an unused CRTC, don't use any.
8650 */
8651 if (!crtc) {
8652 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8653 goto fail_unlock;
8654 }
8655
8656 ret = drm_modeset_lock(&crtc->mutex, ctx);
8657 if (ret)
8658 goto fail_unlock;
8659 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8660 if (ret)
8661 goto fail_unlock;
8662 intel_encoder->new_crtc = to_intel_crtc(crtc);
8663 to_intel_connector(connector)->new_encoder = intel_encoder;
8664
8665 intel_crtc = to_intel_crtc(crtc);
8666 intel_crtc->new_enabled = true;
8667 intel_crtc->new_config = intel_crtc->config;
8668 old->dpms_mode = connector->dpms;
8669 old->load_detect_temp = true;
8670 old->release_fb = NULL;
8671
8672 if (!mode)
8673 mode = &load_detect_mode;
8674
8675 /* We need a framebuffer large enough to accommodate all accesses
8676 * that the plane may generate whilst we perform load detection.
8677 * We can not rely on the fbcon either being present (we get called
8678 * during its initialisation to detect all boot displays, or it may
8679 * not even exist) or that it is large enough to satisfy the
8680 * requested mode.
8681 */
8682 fb = mode_fits_in_fbdev(dev, mode);
8683 if (fb == NULL) {
8684 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8685 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8686 old->release_fb = fb;
8687 } else
8688 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8689 if (IS_ERR(fb)) {
8690 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8691 goto fail;
8692 }
8693
8694 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8695 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8696 if (old->release_fb)
8697 old->release_fb->funcs->destroy(old->release_fb);
8698 goto fail;
8699 }
8700
8701 /* let the connector get through one full cycle before testing */
8702 intel_wait_for_vblank(dev, intel_crtc->pipe);
8703 return true;
8704
8705 fail:
8706 intel_crtc->new_enabled = crtc->enabled;
8707 if (intel_crtc->new_enabled)
8708 intel_crtc->new_config = intel_crtc->config;
8709 else
8710 intel_crtc->new_config = NULL;
8711 fail_unlock:
8712 if (ret == -EDEADLK) {
8713 drm_modeset_backoff(ctx);
8714 goto retry;
8715 }
8716
8717 return false;
8718 }
8719
8720 void intel_release_load_detect_pipe(struct drm_connector *connector,
8721 struct intel_load_detect_pipe *old)
8722 {
8723 struct intel_encoder *intel_encoder =
8724 intel_attached_encoder(connector);
8725 struct drm_encoder *encoder = &intel_encoder->base;
8726 struct drm_crtc *crtc = encoder->crtc;
8727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8728
8729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8730 connector->base.id, connector->name,
8731 encoder->base.id, encoder->name);
8732
8733 if (old->load_detect_temp) {
8734 to_intel_connector(connector)->new_encoder = NULL;
8735 intel_encoder->new_crtc = NULL;
8736 intel_crtc->new_enabled = false;
8737 intel_crtc->new_config = NULL;
8738 intel_set_mode(crtc, NULL, 0, 0, NULL);
8739
8740 if (old->release_fb) {
8741 drm_framebuffer_unregister_private(old->release_fb);
8742 drm_framebuffer_unreference(old->release_fb);
8743 }
8744
8745 return;
8746 }
8747
8748 /* Switch crtc and encoder back off if necessary */
8749 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8750 connector->funcs->dpms(connector, old->dpms_mode);
8751 }
8752
8753 static int i9xx_pll_refclk(struct drm_device *dev,
8754 const struct intel_crtc_state *pipe_config)
8755 {
8756 struct drm_i915_private *dev_priv = dev->dev_private;
8757 u32 dpll = pipe_config->dpll_hw_state.dpll;
8758
8759 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8760 return dev_priv->vbt.lvds_ssc_freq;
8761 else if (HAS_PCH_SPLIT(dev))
8762 return 120000;
8763 else if (!IS_GEN2(dev))
8764 return 96000;
8765 else
8766 return 48000;
8767 }
8768
8769 /* Returns the clock of the currently programmed mode of the given pipe. */
8770 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8771 struct intel_crtc_state *pipe_config)
8772 {
8773 struct drm_device *dev = crtc->base.dev;
8774 struct drm_i915_private *dev_priv = dev->dev_private;
8775 int pipe = pipe_config->cpu_transcoder;
8776 u32 dpll = pipe_config->dpll_hw_state.dpll;
8777 u32 fp;
8778 intel_clock_t clock;
8779 int refclk = i9xx_pll_refclk(dev, pipe_config);
8780
8781 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8782 fp = pipe_config->dpll_hw_state.fp0;
8783 else
8784 fp = pipe_config->dpll_hw_state.fp1;
8785
8786 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8787 if (IS_PINEVIEW(dev)) {
8788 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8789 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8790 } else {
8791 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8792 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8793 }
8794
8795 if (!IS_GEN2(dev)) {
8796 if (IS_PINEVIEW(dev))
8797 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8798 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8799 else
8800 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8801 DPLL_FPA01_P1_POST_DIV_SHIFT);
8802
8803 switch (dpll & DPLL_MODE_MASK) {
8804 case DPLLB_MODE_DAC_SERIAL:
8805 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8806 5 : 10;
8807 break;
8808 case DPLLB_MODE_LVDS:
8809 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8810 7 : 14;
8811 break;
8812 default:
8813 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8814 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8815 return;
8816 }
8817
8818 if (IS_PINEVIEW(dev))
8819 pineview_clock(refclk, &clock);
8820 else
8821 i9xx_clock(refclk, &clock);
8822 } else {
8823 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8824 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8825
8826 if (is_lvds) {
8827 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8828 DPLL_FPA01_P1_POST_DIV_SHIFT);
8829
8830 if (lvds & LVDS_CLKB_POWER_UP)
8831 clock.p2 = 7;
8832 else
8833 clock.p2 = 14;
8834 } else {
8835 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8836 clock.p1 = 2;
8837 else {
8838 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8839 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8840 }
8841 if (dpll & PLL_P2_DIVIDE_BY_4)
8842 clock.p2 = 4;
8843 else
8844 clock.p2 = 2;
8845 }
8846
8847 i9xx_clock(refclk, &clock);
8848 }
8849
8850 /*
8851 * This value includes pixel_multiplier. We will use
8852 * port_clock to compute adjusted_mode.crtc_clock in the
8853 * encoder's get_config() function.
8854 */
8855 pipe_config->port_clock = clock.dot;
8856 }
8857
8858 int intel_dotclock_calculate(int link_freq,
8859 const struct intel_link_m_n *m_n)
8860 {
8861 /*
8862 * The calculation for the data clock is:
8863 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8864 * But we want to avoid losing precison if possible, so:
8865 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8866 *
8867 * and the link clock is simpler:
8868 * link_clock = (m * link_clock) / n
8869 */
8870
8871 if (!m_n->link_n)
8872 return 0;
8873
8874 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8875 }
8876
8877 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8878 struct intel_crtc_state *pipe_config)
8879 {
8880 struct drm_device *dev = crtc->base.dev;
8881
8882 /* read out port_clock from the DPLL */
8883 i9xx_crtc_clock_get(crtc, pipe_config);
8884
8885 /*
8886 * This value does not include pixel_multiplier.
8887 * We will check that port_clock and adjusted_mode.crtc_clock
8888 * agree once we know their relationship in the encoder's
8889 * get_config() function.
8890 */
8891 pipe_config->base.adjusted_mode.crtc_clock =
8892 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8893 &pipe_config->fdi_m_n);
8894 }
8895
8896 /** Returns the currently programmed mode of the given pipe. */
8897 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8898 struct drm_crtc *crtc)
8899 {
8900 struct drm_i915_private *dev_priv = dev->dev_private;
8901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8902 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8903 struct drm_display_mode *mode;
8904 struct intel_crtc_state pipe_config;
8905 int htot = I915_READ(HTOTAL(cpu_transcoder));
8906 int hsync = I915_READ(HSYNC(cpu_transcoder));
8907 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8908 int vsync = I915_READ(VSYNC(cpu_transcoder));
8909 enum pipe pipe = intel_crtc->pipe;
8910
8911 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8912 if (!mode)
8913 return NULL;
8914
8915 /*
8916 * Construct a pipe_config sufficient for getting the clock info
8917 * back out of crtc_clock_get.
8918 *
8919 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8920 * to use a real value here instead.
8921 */
8922 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8923 pipe_config.pixel_multiplier = 1;
8924 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8925 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8926 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8927 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8928
8929 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8930 mode->hdisplay = (htot & 0xffff) + 1;
8931 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8932 mode->hsync_start = (hsync & 0xffff) + 1;
8933 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8934 mode->vdisplay = (vtot & 0xffff) + 1;
8935 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8936 mode->vsync_start = (vsync & 0xffff) + 1;
8937 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8938
8939 drm_mode_set_name(mode);
8940
8941 return mode;
8942 }
8943
8944 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8945 {
8946 struct drm_device *dev = crtc->dev;
8947 struct drm_i915_private *dev_priv = dev->dev_private;
8948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8949
8950 if (!HAS_GMCH_DISPLAY(dev))
8951 return;
8952
8953 if (!dev_priv->lvds_downclock_avail)
8954 return;
8955
8956 /*
8957 * Since this is called by a timer, we should never get here in
8958 * the manual case.
8959 */
8960 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8961 int pipe = intel_crtc->pipe;
8962 int dpll_reg = DPLL(pipe);
8963 int dpll;
8964
8965 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8966
8967 assert_panel_unlocked(dev_priv, pipe);
8968
8969 dpll = I915_READ(dpll_reg);
8970 dpll |= DISPLAY_RATE_SELECT_FPA1;
8971 I915_WRITE(dpll_reg, dpll);
8972 intel_wait_for_vblank(dev, pipe);
8973 dpll = I915_READ(dpll_reg);
8974 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8975 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8976 }
8977
8978 }
8979
8980 void intel_mark_busy(struct drm_device *dev)
8981 {
8982 struct drm_i915_private *dev_priv = dev->dev_private;
8983
8984 if (dev_priv->mm.busy)
8985 return;
8986
8987 intel_runtime_pm_get(dev_priv);
8988 i915_update_gfx_val(dev_priv);
8989 dev_priv->mm.busy = true;
8990 }
8991
8992 void intel_mark_idle(struct drm_device *dev)
8993 {
8994 struct drm_i915_private *dev_priv = dev->dev_private;
8995 struct drm_crtc *crtc;
8996
8997 if (!dev_priv->mm.busy)
8998 return;
8999
9000 dev_priv->mm.busy = false;
9001
9002 if (!i915.powersave)
9003 goto out;
9004
9005 for_each_crtc(dev, crtc) {
9006 if (!crtc->primary->fb)
9007 continue;
9008
9009 intel_decrease_pllclock(crtc);
9010 }
9011
9012 if (INTEL_INFO(dev)->gen >= 6)
9013 gen6_rps_idle(dev->dev_private);
9014
9015 out:
9016 intel_runtime_pm_put(dev_priv);
9017 }
9018
9019 static void intel_crtc_set_state(struct intel_crtc *crtc,
9020 struct intel_crtc_state *crtc_state)
9021 {
9022 kfree(crtc->config);
9023 crtc->config = crtc_state;
9024 crtc->base.state = &crtc_state->base;
9025 }
9026
9027 static void intel_crtc_destroy(struct drm_crtc *crtc)
9028 {
9029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9030 struct drm_device *dev = crtc->dev;
9031 struct intel_unpin_work *work;
9032
9033 spin_lock_irq(&dev->event_lock);
9034 work = intel_crtc->unpin_work;
9035 intel_crtc->unpin_work = NULL;
9036 spin_unlock_irq(&dev->event_lock);
9037
9038 if (work) {
9039 cancel_work_sync(&work->work);
9040 kfree(work);
9041 }
9042
9043 intel_crtc_set_state(intel_crtc, NULL);
9044 drm_crtc_cleanup(crtc);
9045
9046 kfree(intel_crtc);
9047 }
9048
9049 static void intel_unpin_work_fn(struct work_struct *__work)
9050 {
9051 struct intel_unpin_work *work =
9052 container_of(__work, struct intel_unpin_work, work);
9053 struct drm_device *dev = work->crtc->dev;
9054 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9055
9056 mutex_lock(&dev->struct_mutex);
9057 intel_unpin_fb_obj(work->old_fb_obj);
9058 drm_gem_object_unreference(&work->pending_flip_obj->base);
9059 drm_gem_object_unreference(&work->old_fb_obj->base);
9060
9061 intel_fbc_update(dev);
9062
9063 if (work->flip_queued_req)
9064 i915_gem_request_assign(&work->flip_queued_req, NULL);
9065 mutex_unlock(&dev->struct_mutex);
9066
9067 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9068
9069 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9070 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9071
9072 kfree(work);
9073 }
9074
9075 static void do_intel_finish_page_flip(struct drm_device *dev,
9076 struct drm_crtc *crtc)
9077 {
9078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9079 struct intel_unpin_work *work;
9080 unsigned long flags;
9081
9082 /* Ignore early vblank irqs */
9083 if (intel_crtc == NULL)
9084 return;
9085
9086 /*
9087 * This is called both by irq handlers and the reset code (to complete
9088 * lost pageflips) so needs the full irqsave spinlocks.
9089 */
9090 spin_lock_irqsave(&dev->event_lock, flags);
9091 work = intel_crtc->unpin_work;
9092
9093 /* Ensure we don't miss a work->pending update ... */
9094 smp_rmb();
9095
9096 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9097 spin_unlock_irqrestore(&dev->event_lock, flags);
9098 return;
9099 }
9100
9101 page_flip_completed(intel_crtc);
9102
9103 spin_unlock_irqrestore(&dev->event_lock, flags);
9104 }
9105
9106 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9107 {
9108 struct drm_i915_private *dev_priv = dev->dev_private;
9109 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9110
9111 do_intel_finish_page_flip(dev, crtc);
9112 }
9113
9114 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9115 {
9116 struct drm_i915_private *dev_priv = dev->dev_private;
9117 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9118
9119 do_intel_finish_page_flip(dev, crtc);
9120 }
9121
9122 /* Is 'a' after or equal to 'b'? */
9123 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9124 {
9125 return !((a - b) & 0x80000000);
9126 }
9127
9128 static bool page_flip_finished(struct intel_crtc *crtc)
9129 {
9130 struct drm_device *dev = crtc->base.dev;
9131 struct drm_i915_private *dev_priv = dev->dev_private;
9132
9133 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9134 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9135 return true;
9136
9137 /*
9138 * The relevant registers doen't exist on pre-ctg.
9139 * As the flip done interrupt doesn't trigger for mmio
9140 * flips on gmch platforms, a flip count check isn't
9141 * really needed there. But since ctg has the registers,
9142 * include it in the check anyway.
9143 */
9144 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9145 return true;
9146
9147 /*
9148 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9149 * used the same base address. In that case the mmio flip might
9150 * have completed, but the CS hasn't even executed the flip yet.
9151 *
9152 * A flip count check isn't enough as the CS might have updated
9153 * the base address just after start of vblank, but before we
9154 * managed to process the interrupt. This means we'd complete the
9155 * CS flip too soon.
9156 *
9157 * Combining both checks should get us a good enough result. It may
9158 * still happen that the CS flip has been executed, but has not
9159 * yet actually completed. But in case the base address is the same
9160 * anyway, we don't really care.
9161 */
9162 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9163 crtc->unpin_work->gtt_offset &&
9164 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9165 crtc->unpin_work->flip_count);
9166 }
9167
9168 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9169 {
9170 struct drm_i915_private *dev_priv = dev->dev_private;
9171 struct intel_crtc *intel_crtc =
9172 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9173 unsigned long flags;
9174
9175
9176 /*
9177 * This is called both by irq handlers and the reset code (to complete
9178 * lost pageflips) so needs the full irqsave spinlocks.
9179 *
9180 * NB: An MMIO update of the plane base pointer will also
9181 * generate a page-flip completion irq, i.e. every modeset
9182 * is also accompanied by a spurious intel_prepare_page_flip().
9183 */
9184 spin_lock_irqsave(&dev->event_lock, flags);
9185 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9186 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9187 spin_unlock_irqrestore(&dev->event_lock, flags);
9188 }
9189
9190 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9191 {
9192 /* Ensure that the work item is consistent when activating it ... */
9193 smp_wmb();
9194 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9195 /* and that it is marked active as soon as the irq could fire. */
9196 smp_wmb();
9197 }
9198
9199 static int intel_gen2_queue_flip(struct drm_device *dev,
9200 struct drm_crtc *crtc,
9201 struct drm_framebuffer *fb,
9202 struct drm_i915_gem_object *obj,
9203 struct intel_engine_cs *ring,
9204 uint32_t flags)
9205 {
9206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9207 u32 flip_mask;
9208 int ret;
9209
9210 ret = intel_ring_begin(ring, 6);
9211 if (ret)
9212 return ret;
9213
9214 /* Can't queue multiple flips, so wait for the previous
9215 * one to finish before executing the next.
9216 */
9217 if (intel_crtc->plane)
9218 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9219 else
9220 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9221 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9222 intel_ring_emit(ring, MI_NOOP);
9223 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9224 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9225 intel_ring_emit(ring, fb->pitches[0]);
9226 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9227 intel_ring_emit(ring, 0); /* aux display base address, unused */
9228
9229 intel_mark_page_flip_active(intel_crtc);
9230 __intel_ring_advance(ring);
9231 return 0;
9232 }
9233
9234 static int intel_gen3_queue_flip(struct drm_device *dev,
9235 struct drm_crtc *crtc,
9236 struct drm_framebuffer *fb,
9237 struct drm_i915_gem_object *obj,
9238 struct intel_engine_cs *ring,
9239 uint32_t flags)
9240 {
9241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9242 u32 flip_mask;
9243 int ret;
9244
9245 ret = intel_ring_begin(ring, 6);
9246 if (ret)
9247 return ret;
9248
9249 if (intel_crtc->plane)
9250 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9251 else
9252 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9253 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9254 intel_ring_emit(ring, MI_NOOP);
9255 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9256 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9257 intel_ring_emit(ring, fb->pitches[0]);
9258 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9259 intel_ring_emit(ring, MI_NOOP);
9260
9261 intel_mark_page_flip_active(intel_crtc);
9262 __intel_ring_advance(ring);
9263 return 0;
9264 }
9265
9266 static int intel_gen4_queue_flip(struct drm_device *dev,
9267 struct drm_crtc *crtc,
9268 struct drm_framebuffer *fb,
9269 struct drm_i915_gem_object *obj,
9270 struct intel_engine_cs *ring,
9271 uint32_t flags)
9272 {
9273 struct drm_i915_private *dev_priv = dev->dev_private;
9274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9275 uint32_t pf, pipesrc;
9276 int ret;
9277
9278 ret = intel_ring_begin(ring, 4);
9279 if (ret)
9280 return ret;
9281
9282 /* i965+ uses the linear or tiled offsets from the
9283 * Display Registers (which do not change across a page-flip)
9284 * so we need only reprogram the base address.
9285 */
9286 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9288 intel_ring_emit(ring, fb->pitches[0]);
9289 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9290 obj->tiling_mode);
9291
9292 /* XXX Enabling the panel-fitter across page-flip is so far
9293 * untested on non-native modes, so ignore it for now.
9294 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9295 */
9296 pf = 0;
9297 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9298 intel_ring_emit(ring, pf | pipesrc);
9299
9300 intel_mark_page_flip_active(intel_crtc);
9301 __intel_ring_advance(ring);
9302 return 0;
9303 }
9304
9305 static int intel_gen6_queue_flip(struct drm_device *dev,
9306 struct drm_crtc *crtc,
9307 struct drm_framebuffer *fb,
9308 struct drm_i915_gem_object *obj,
9309 struct intel_engine_cs *ring,
9310 uint32_t flags)
9311 {
9312 struct drm_i915_private *dev_priv = dev->dev_private;
9313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9314 uint32_t pf, pipesrc;
9315 int ret;
9316
9317 ret = intel_ring_begin(ring, 4);
9318 if (ret)
9319 return ret;
9320
9321 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9322 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9323 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9324 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9325
9326 /* Contrary to the suggestions in the documentation,
9327 * "Enable Panel Fitter" does not seem to be required when page
9328 * flipping with a non-native mode, and worse causes a normal
9329 * modeset to fail.
9330 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9331 */
9332 pf = 0;
9333 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9334 intel_ring_emit(ring, pf | pipesrc);
9335
9336 intel_mark_page_flip_active(intel_crtc);
9337 __intel_ring_advance(ring);
9338 return 0;
9339 }
9340
9341 static int intel_gen7_queue_flip(struct drm_device *dev,
9342 struct drm_crtc *crtc,
9343 struct drm_framebuffer *fb,
9344 struct drm_i915_gem_object *obj,
9345 struct intel_engine_cs *ring,
9346 uint32_t flags)
9347 {
9348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9349 uint32_t plane_bit = 0;
9350 int len, ret;
9351
9352 switch (intel_crtc->plane) {
9353 case PLANE_A:
9354 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9355 break;
9356 case PLANE_B:
9357 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9358 break;
9359 case PLANE_C:
9360 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9361 break;
9362 default:
9363 WARN_ONCE(1, "unknown plane in flip command\n");
9364 return -ENODEV;
9365 }
9366
9367 len = 4;
9368 if (ring->id == RCS) {
9369 len += 6;
9370 /*
9371 * On Gen 8, SRM is now taking an extra dword to accommodate
9372 * 48bits addresses, and we need a NOOP for the batch size to
9373 * stay even.
9374 */
9375 if (IS_GEN8(dev))
9376 len += 2;
9377 }
9378
9379 /*
9380 * BSpec MI_DISPLAY_FLIP for IVB:
9381 * "The full packet must be contained within the same cache line."
9382 *
9383 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9384 * cacheline, if we ever start emitting more commands before
9385 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9386 * then do the cacheline alignment, and finally emit the
9387 * MI_DISPLAY_FLIP.
9388 */
9389 ret = intel_ring_cacheline_align(ring);
9390 if (ret)
9391 return ret;
9392
9393 ret = intel_ring_begin(ring, len);
9394 if (ret)
9395 return ret;
9396
9397 /* Unmask the flip-done completion message. Note that the bspec says that
9398 * we should do this for both the BCS and RCS, and that we must not unmask
9399 * more than one flip event at any time (or ensure that one flip message
9400 * can be sent by waiting for flip-done prior to queueing new flips).
9401 * Experimentation says that BCS works despite DERRMR masking all
9402 * flip-done completion events and that unmasking all planes at once
9403 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9404 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9405 */
9406 if (ring->id == RCS) {
9407 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9408 intel_ring_emit(ring, DERRMR);
9409 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9410 DERRMR_PIPEB_PRI_FLIP_DONE |
9411 DERRMR_PIPEC_PRI_FLIP_DONE));
9412 if (IS_GEN8(dev))
9413 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9414 MI_SRM_LRM_GLOBAL_GTT);
9415 else
9416 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9417 MI_SRM_LRM_GLOBAL_GTT);
9418 intel_ring_emit(ring, DERRMR);
9419 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9420 if (IS_GEN8(dev)) {
9421 intel_ring_emit(ring, 0);
9422 intel_ring_emit(ring, MI_NOOP);
9423 }
9424 }
9425
9426 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9427 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9428 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9429 intel_ring_emit(ring, (MI_NOOP));
9430
9431 intel_mark_page_flip_active(intel_crtc);
9432 __intel_ring_advance(ring);
9433 return 0;
9434 }
9435
9436 static bool use_mmio_flip(struct intel_engine_cs *ring,
9437 struct drm_i915_gem_object *obj)
9438 {
9439 /*
9440 * This is not being used for older platforms, because
9441 * non-availability of flip done interrupt forces us to use
9442 * CS flips. Older platforms derive flip done using some clever
9443 * tricks involving the flip_pending status bits and vblank irqs.
9444 * So using MMIO flips there would disrupt this mechanism.
9445 */
9446
9447 if (ring == NULL)
9448 return true;
9449
9450 if (INTEL_INFO(ring->dev)->gen < 5)
9451 return false;
9452
9453 if (i915.use_mmio_flip < 0)
9454 return false;
9455 else if (i915.use_mmio_flip > 0)
9456 return true;
9457 else if (i915.enable_execlists)
9458 return true;
9459 else
9460 return ring != i915_gem_request_get_ring(obj->last_read_req);
9461 }
9462
9463 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9464 {
9465 struct drm_device *dev = intel_crtc->base.dev;
9466 struct drm_i915_private *dev_priv = dev->dev_private;
9467 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9468 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9469 struct drm_i915_gem_object *obj = intel_fb->obj;
9470 const enum pipe pipe = intel_crtc->pipe;
9471 u32 ctl, stride;
9472
9473 ctl = I915_READ(PLANE_CTL(pipe, 0));
9474 ctl &= ~PLANE_CTL_TILED_MASK;
9475 if (obj->tiling_mode == I915_TILING_X)
9476 ctl |= PLANE_CTL_TILED_X;
9477
9478 /*
9479 * The stride is either expressed as a multiple of 64 bytes chunks for
9480 * linear buffers or in number of tiles for tiled buffers.
9481 */
9482 stride = fb->pitches[0] >> 6;
9483 if (obj->tiling_mode == I915_TILING_X)
9484 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9485
9486 /*
9487 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9488 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9489 */
9490 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9491 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9492
9493 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9494 POSTING_READ(PLANE_SURF(pipe, 0));
9495 }
9496
9497 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9498 {
9499 struct drm_device *dev = intel_crtc->base.dev;
9500 struct drm_i915_private *dev_priv = dev->dev_private;
9501 struct intel_framebuffer *intel_fb =
9502 to_intel_framebuffer(intel_crtc->base.primary->fb);
9503 struct drm_i915_gem_object *obj = intel_fb->obj;
9504 u32 dspcntr;
9505 u32 reg;
9506
9507 reg = DSPCNTR(intel_crtc->plane);
9508 dspcntr = I915_READ(reg);
9509
9510 if (obj->tiling_mode != I915_TILING_NONE)
9511 dspcntr |= DISPPLANE_TILED;
9512 else
9513 dspcntr &= ~DISPPLANE_TILED;
9514
9515 I915_WRITE(reg, dspcntr);
9516
9517 I915_WRITE(DSPSURF(intel_crtc->plane),
9518 intel_crtc->unpin_work->gtt_offset);
9519 POSTING_READ(DSPSURF(intel_crtc->plane));
9520
9521 }
9522
9523 /*
9524 * XXX: This is the temporary way to update the plane registers until we get
9525 * around to using the usual plane update functions for MMIO flips
9526 */
9527 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9528 {
9529 struct drm_device *dev = intel_crtc->base.dev;
9530 bool atomic_update;
9531 u32 start_vbl_count;
9532
9533 intel_mark_page_flip_active(intel_crtc);
9534
9535 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9536
9537 if (INTEL_INFO(dev)->gen >= 9)
9538 skl_do_mmio_flip(intel_crtc);
9539 else
9540 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9541 ilk_do_mmio_flip(intel_crtc);
9542
9543 if (atomic_update)
9544 intel_pipe_update_end(intel_crtc, start_vbl_count);
9545 }
9546
9547 static void intel_mmio_flip_work_func(struct work_struct *work)
9548 {
9549 struct intel_crtc *crtc =
9550 container_of(work, struct intel_crtc, mmio_flip.work);
9551 struct intel_mmio_flip *mmio_flip;
9552
9553 mmio_flip = &crtc->mmio_flip;
9554 if (mmio_flip->req)
9555 WARN_ON(__i915_wait_request(mmio_flip->req,
9556 crtc->reset_counter,
9557 false, NULL, NULL) != 0);
9558
9559 intel_do_mmio_flip(crtc);
9560 if (mmio_flip->req) {
9561 mutex_lock(&crtc->base.dev->struct_mutex);
9562 i915_gem_request_assign(&mmio_flip->req, NULL);
9563 mutex_unlock(&crtc->base.dev->struct_mutex);
9564 }
9565 }
9566
9567 static int intel_queue_mmio_flip(struct drm_device *dev,
9568 struct drm_crtc *crtc,
9569 struct drm_framebuffer *fb,
9570 struct drm_i915_gem_object *obj,
9571 struct intel_engine_cs *ring,
9572 uint32_t flags)
9573 {
9574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9575
9576 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9577 obj->last_write_req);
9578
9579 schedule_work(&intel_crtc->mmio_flip.work);
9580
9581 return 0;
9582 }
9583
9584 static int intel_gen9_queue_flip(struct drm_device *dev,
9585 struct drm_crtc *crtc,
9586 struct drm_framebuffer *fb,
9587 struct drm_i915_gem_object *obj,
9588 struct intel_engine_cs *ring,
9589 uint32_t flags)
9590 {
9591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9592 uint32_t plane = 0, stride;
9593 int ret;
9594
9595 switch(intel_crtc->pipe) {
9596 case PIPE_A:
9597 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A;
9598 break;
9599 case PIPE_B:
9600 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B;
9601 break;
9602 case PIPE_C:
9603 plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C;
9604 break;
9605 default:
9606 WARN_ONCE(1, "unknown plane in flip command\n");
9607 return -ENODEV;
9608 }
9609
9610 switch (obj->tiling_mode) {
9611 case I915_TILING_NONE:
9612 stride = fb->pitches[0] >> 6;
9613 break;
9614 case I915_TILING_X:
9615 stride = fb->pitches[0] >> 9;
9616 break;
9617 default:
9618 WARN_ONCE(1, "unknown tiling in flip command\n");
9619 return -ENODEV;
9620 }
9621
9622 ret = intel_ring_begin(ring, 10);
9623 if (ret)
9624 return ret;
9625
9626 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9627 intel_ring_emit(ring, DERRMR);
9628 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9629 DERRMR_PIPEB_PRI_FLIP_DONE |
9630 DERRMR_PIPEC_PRI_FLIP_DONE));
9631 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9632 MI_SRM_LRM_GLOBAL_GTT);
9633 intel_ring_emit(ring, DERRMR);
9634 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9635 intel_ring_emit(ring, 0);
9636
9637 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
9638 intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
9639 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9640
9641 intel_mark_page_flip_active(intel_crtc);
9642 __intel_ring_advance(ring);
9643
9644 return 0;
9645 }
9646
9647 static int intel_default_queue_flip(struct drm_device *dev,
9648 struct drm_crtc *crtc,
9649 struct drm_framebuffer *fb,
9650 struct drm_i915_gem_object *obj,
9651 struct intel_engine_cs *ring,
9652 uint32_t flags)
9653 {
9654 return -ENODEV;
9655 }
9656
9657 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9658 struct drm_crtc *crtc)
9659 {
9660 struct drm_i915_private *dev_priv = dev->dev_private;
9661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9662 struct intel_unpin_work *work = intel_crtc->unpin_work;
9663 u32 addr;
9664
9665 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9666 return true;
9667
9668 if (!work->enable_stall_check)
9669 return false;
9670
9671 if (work->flip_ready_vblank == 0) {
9672 if (work->flip_queued_req &&
9673 !i915_gem_request_completed(work->flip_queued_req, true))
9674 return false;
9675
9676 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9677 }
9678
9679 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9680 return false;
9681
9682 /* Potential stall - if we see that the flip has happened,
9683 * assume a missed interrupt. */
9684 if (INTEL_INFO(dev)->gen >= 4)
9685 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9686 else
9687 addr = I915_READ(DSPADDR(intel_crtc->plane));
9688
9689 /* There is a potential issue here with a false positive after a flip
9690 * to the same address. We could address this by checking for a
9691 * non-incrementing frame counter.
9692 */
9693 return addr == work->gtt_offset;
9694 }
9695
9696 void intel_check_page_flip(struct drm_device *dev, int pipe)
9697 {
9698 struct drm_i915_private *dev_priv = dev->dev_private;
9699 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9701
9702 WARN_ON(!in_irq());
9703
9704 if (crtc == NULL)
9705 return;
9706
9707 spin_lock(&dev->event_lock);
9708 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9709 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9710 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9711 page_flip_completed(intel_crtc);
9712 }
9713 spin_unlock(&dev->event_lock);
9714 }
9715
9716 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9717 struct drm_framebuffer *fb,
9718 struct drm_pending_vblank_event *event,
9719 uint32_t page_flip_flags)
9720 {
9721 struct drm_device *dev = crtc->dev;
9722 struct drm_i915_private *dev_priv = dev->dev_private;
9723 struct drm_framebuffer *old_fb = crtc->primary->fb;
9724 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9726 struct drm_plane *primary = crtc->primary;
9727 enum pipe pipe = intel_crtc->pipe;
9728 struct intel_unpin_work *work;
9729 struct intel_engine_cs *ring;
9730 int ret;
9731
9732 /*
9733 * drm_mode_page_flip_ioctl() should already catch this, but double
9734 * check to be safe. In the future we may enable pageflipping from
9735 * a disabled primary plane.
9736 */
9737 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9738 return -EBUSY;
9739
9740 /* Can't change pixel format via MI display flips. */
9741 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9742 return -EINVAL;
9743
9744 /*
9745 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9746 * Note that pitch changes could also affect these register.
9747 */
9748 if (INTEL_INFO(dev)->gen > 3 &&
9749 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9750 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9751 return -EINVAL;
9752
9753 if (i915_terminally_wedged(&dev_priv->gpu_error))
9754 goto out_hang;
9755
9756 work = kzalloc(sizeof(*work), GFP_KERNEL);
9757 if (work == NULL)
9758 return -ENOMEM;
9759
9760 work->event = event;
9761 work->crtc = crtc;
9762 work->old_fb_obj = intel_fb_obj(old_fb);
9763 INIT_WORK(&work->work, intel_unpin_work_fn);
9764
9765 ret = drm_crtc_vblank_get(crtc);
9766 if (ret)
9767 goto free_work;
9768
9769 /* We borrow the event spin lock for protecting unpin_work */
9770 spin_lock_irq(&dev->event_lock);
9771 if (intel_crtc->unpin_work) {
9772 /* Before declaring the flip queue wedged, check if
9773 * the hardware completed the operation behind our backs.
9774 */
9775 if (__intel_pageflip_stall_check(dev, crtc)) {
9776 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9777 page_flip_completed(intel_crtc);
9778 } else {
9779 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9780 spin_unlock_irq(&dev->event_lock);
9781
9782 drm_crtc_vblank_put(crtc);
9783 kfree(work);
9784 return -EBUSY;
9785 }
9786 }
9787 intel_crtc->unpin_work = work;
9788 spin_unlock_irq(&dev->event_lock);
9789
9790 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9791 flush_workqueue(dev_priv->wq);
9792
9793 ret = i915_mutex_lock_interruptible(dev);
9794 if (ret)
9795 goto cleanup;
9796
9797 /* Reference the objects for the scheduled work. */
9798 drm_gem_object_reference(&work->old_fb_obj->base);
9799 drm_gem_object_reference(&obj->base);
9800
9801 crtc->primary->fb = fb;
9802
9803 work->pending_flip_obj = obj;
9804
9805 atomic_inc(&intel_crtc->unpin_work_count);
9806 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9807
9808 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9809 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9810
9811 if (IS_VALLEYVIEW(dev)) {
9812 ring = &dev_priv->ring[BCS];
9813 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9814 /* vlv: DISPLAY_FLIP fails to change tiling */
9815 ring = NULL;
9816 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9817 ring = &dev_priv->ring[BCS];
9818 } else if (INTEL_INFO(dev)->gen >= 7) {
9819 ring = i915_gem_request_get_ring(obj->last_read_req);
9820 if (ring == NULL || ring->id != RCS)
9821 ring = &dev_priv->ring[BCS];
9822 } else {
9823 ring = &dev_priv->ring[RCS];
9824 }
9825
9826 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9827 if (ret)
9828 goto cleanup_pending;
9829
9830 work->gtt_offset =
9831 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9832
9833 if (use_mmio_flip(ring, obj)) {
9834 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9835 page_flip_flags);
9836 if (ret)
9837 goto cleanup_unpin;
9838
9839 i915_gem_request_assign(&work->flip_queued_req,
9840 obj->last_write_req);
9841 } else {
9842 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9843 page_flip_flags);
9844 if (ret)
9845 goto cleanup_unpin;
9846
9847 i915_gem_request_assign(&work->flip_queued_req,
9848 intel_ring_get_request(ring));
9849 }
9850
9851 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9852 work->enable_stall_check = true;
9853
9854 i915_gem_track_fb(work->old_fb_obj, obj,
9855 INTEL_FRONTBUFFER_PRIMARY(pipe));
9856
9857 intel_fbc_disable(dev);
9858 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9859 mutex_unlock(&dev->struct_mutex);
9860
9861 trace_i915_flip_request(intel_crtc->plane, obj);
9862
9863 return 0;
9864
9865 cleanup_unpin:
9866 intel_unpin_fb_obj(obj);
9867 cleanup_pending:
9868 atomic_dec(&intel_crtc->unpin_work_count);
9869 crtc->primary->fb = old_fb;
9870 drm_gem_object_unreference(&work->old_fb_obj->base);
9871 drm_gem_object_unreference(&obj->base);
9872 mutex_unlock(&dev->struct_mutex);
9873
9874 cleanup:
9875 spin_lock_irq(&dev->event_lock);
9876 intel_crtc->unpin_work = NULL;
9877 spin_unlock_irq(&dev->event_lock);
9878
9879 drm_crtc_vblank_put(crtc);
9880 free_work:
9881 kfree(work);
9882
9883 if (ret == -EIO) {
9884 out_hang:
9885 ret = intel_plane_restore(primary);
9886 if (ret == 0 && event) {
9887 spin_lock_irq(&dev->event_lock);
9888 drm_send_vblank_event(dev, pipe, event);
9889 spin_unlock_irq(&dev->event_lock);
9890 }
9891 }
9892 return ret;
9893 }
9894
9895 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9896 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9897 .load_lut = intel_crtc_load_lut,
9898 .atomic_begin = intel_begin_crtc_commit,
9899 .atomic_flush = intel_finish_crtc_commit,
9900 };
9901
9902 /**
9903 * intel_modeset_update_staged_output_state
9904 *
9905 * Updates the staged output configuration state, e.g. after we've read out the
9906 * current hw state.
9907 */
9908 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9909 {
9910 struct intel_crtc *crtc;
9911 struct intel_encoder *encoder;
9912 struct intel_connector *connector;
9913
9914 list_for_each_entry(connector, &dev->mode_config.connector_list,
9915 base.head) {
9916 connector->new_encoder =
9917 to_intel_encoder(connector->base.encoder);
9918 }
9919
9920 for_each_intel_encoder(dev, encoder) {
9921 encoder->new_crtc =
9922 to_intel_crtc(encoder->base.crtc);
9923 }
9924
9925 for_each_intel_crtc(dev, crtc) {
9926 crtc->new_enabled = crtc->base.enabled;
9927
9928 if (crtc->new_enabled)
9929 crtc->new_config = crtc->config;
9930 else
9931 crtc->new_config = NULL;
9932 }
9933 }
9934
9935 /**
9936 * intel_modeset_commit_output_state
9937 *
9938 * This function copies the stage display pipe configuration to the real one.
9939 */
9940 static void intel_modeset_commit_output_state(struct drm_device *dev)
9941 {
9942 struct intel_crtc *crtc;
9943 struct intel_encoder *encoder;
9944 struct intel_connector *connector;
9945
9946 list_for_each_entry(connector, &dev->mode_config.connector_list,
9947 base.head) {
9948 connector->base.encoder = &connector->new_encoder->base;
9949 }
9950
9951 for_each_intel_encoder(dev, encoder) {
9952 encoder->base.crtc = &encoder->new_crtc->base;
9953 }
9954
9955 for_each_intel_crtc(dev, crtc) {
9956 crtc->base.enabled = crtc->new_enabled;
9957 }
9958 }
9959
9960 static void
9961 connected_sink_compute_bpp(struct intel_connector *connector,
9962 struct intel_crtc_state *pipe_config)
9963 {
9964 int bpp = pipe_config->pipe_bpp;
9965
9966 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9967 connector->base.base.id,
9968 connector->base.name);
9969
9970 /* Don't use an invalid EDID bpc value */
9971 if (connector->base.display_info.bpc &&
9972 connector->base.display_info.bpc * 3 < bpp) {
9973 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9974 bpp, connector->base.display_info.bpc*3);
9975 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9976 }
9977
9978 /* Clamp bpp to 8 on screens without EDID 1.4 */
9979 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9980 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9981 bpp);
9982 pipe_config->pipe_bpp = 24;
9983 }
9984 }
9985
9986 static int
9987 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9988 struct drm_framebuffer *fb,
9989 struct intel_crtc_state *pipe_config)
9990 {
9991 struct drm_device *dev = crtc->base.dev;
9992 struct intel_connector *connector;
9993 int bpp;
9994
9995 switch (fb->pixel_format) {
9996 case DRM_FORMAT_C8:
9997 bpp = 8*3; /* since we go through a colormap */
9998 break;
9999 case DRM_FORMAT_XRGB1555:
10000 case DRM_FORMAT_ARGB1555:
10001 /* checked in intel_framebuffer_init already */
10002 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10003 return -EINVAL;
10004 case DRM_FORMAT_RGB565:
10005 bpp = 6*3; /* min is 18bpp */
10006 break;
10007 case DRM_FORMAT_XBGR8888:
10008 case DRM_FORMAT_ABGR8888:
10009 /* checked in intel_framebuffer_init already */
10010 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10011 return -EINVAL;
10012 case DRM_FORMAT_XRGB8888:
10013 case DRM_FORMAT_ARGB8888:
10014 bpp = 8*3;
10015 break;
10016 case DRM_FORMAT_XRGB2101010:
10017 case DRM_FORMAT_ARGB2101010:
10018 case DRM_FORMAT_XBGR2101010:
10019 case DRM_FORMAT_ABGR2101010:
10020 /* checked in intel_framebuffer_init already */
10021 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10022 return -EINVAL;
10023 bpp = 10*3;
10024 break;
10025 /* TODO: gen4+ supports 16 bpc floating point, too. */
10026 default:
10027 DRM_DEBUG_KMS("unsupported depth\n");
10028 return -EINVAL;
10029 }
10030
10031 pipe_config->pipe_bpp = bpp;
10032
10033 /* Clamp display bpp to EDID value */
10034 list_for_each_entry(connector, &dev->mode_config.connector_list,
10035 base.head) {
10036 if (!connector->new_encoder ||
10037 connector->new_encoder->new_crtc != crtc)
10038 continue;
10039
10040 connected_sink_compute_bpp(connector, pipe_config);
10041 }
10042
10043 return bpp;
10044 }
10045
10046 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10047 {
10048 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10049 "type: 0x%x flags: 0x%x\n",
10050 mode->crtc_clock,
10051 mode->crtc_hdisplay, mode->crtc_hsync_start,
10052 mode->crtc_hsync_end, mode->crtc_htotal,
10053 mode->crtc_vdisplay, mode->crtc_vsync_start,
10054 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10055 }
10056
10057 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10058 struct intel_crtc_state *pipe_config,
10059 const char *context)
10060 {
10061 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10062 context, pipe_name(crtc->pipe));
10063
10064 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10065 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10066 pipe_config->pipe_bpp, pipe_config->dither);
10067 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10068 pipe_config->has_pch_encoder,
10069 pipe_config->fdi_lanes,
10070 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10071 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10072 pipe_config->fdi_m_n.tu);
10073 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10074 pipe_config->has_dp_encoder,
10075 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10076 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10077 pipe_config->dp_m_n.tu);
10078
10079 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10080 pipe_config->has_dp_encoder,
10081 pipe_config->dp_m2_n2.gmch_m,
10082 pipe_config->dp_m2_n2.gmch_n,
10083 pipe_config->dp_m2_n2.link_m,
10084 pipe_config->dp_m2_n2.link_n,
10085 pipe_config->dp_m2_n2.tu);
10086
10087 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10088 pipe_config->has_audio,
10089 pipe_config->has_infoframe);
10090
10091 DRM_DEBUG_KMS("requested mode:\n");
10092 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10093 DRM_DEBUG_KMS("adjusted mode:\n");
10094 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10095 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10096 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10097 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10098 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10099 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10100 pipe_config->gmch_pfit.control,
10101 pipe_config->gmch_pfit.pgm_ratios,
10102 pipe_config->gmch_pfit.lvds_border_bits);
10103 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10104 pipe_config->pch_pfit.pos,
10105 pipe_config->pch_pfit.size,
10106 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10107 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10108 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10109 }
10110
10111 static bool encoders_cloneable(const struct intel_encoder *a,
10112 const struct intel_encoder *b)
10113 {
10114 /* masks could be asymmetric, so check both ways */
10115 return a == b || (a->cloneable & (1 << b->type) &&
10116 b->cloneable & (1 << a->type));
10117 }
10118
10119 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10120 struct intel_encoder *encoder)
10121 {
10122 struct drm_device *dev = crtc->base.dev;
10123 struct intel_encoder *source_encoder;
10124
10125 for_each_intel_encoder(dev, source_encoder) {
10126 if (source_encoder->new_crtc != crtc)
10127 continue;
10128
10129 if (!encoders_cloneable(encoder, source_encoder))
10130 return false;
10131 }
10132
10133 return true;
10134 }
10135
10136 static bool check_encoder_cloning(struct intel_crtc *crtc)
10137 {
10138 struct drm_device *dev = crtc->base.dev;
10139 struct intel_encoder *encoder;
10140
10141 for_each_intel_encoder(dev, encoder) {
10142 if (encoder->new_crtc != crtc)
10143 continue;
10144
10145 if (!check_single_encoder_cloning(crtc, encoder))
10146 return false;
10147 }
10148
10149 return true;
10150 }
10151
10152 static bool check_digital_port_conflicts(struct drm_device *dev)
10153 {
10154 struct intel_connector *connector;
10155 unsigned int used_ports = 0;
10156
10157 /*
10158 * Walk the connector list instead of the encoder
10159 * list to detect the problem on ddi platforms
10160 * where there's just one encoder per digital port.
10161 */
10162 list_for_each_entry(connector,
10163 &dev->mode_config.connector_list, base.head) {
10164 struct intel_encoder *encoder = connector->new_encoder;
10165
10166 if (!encoder)
10167 continue;
10168
10169 WARN_ON(!encoder->new_crtc);
10170
10171 switch (encoder->type) {
10172 unsigned int port_mask;
10173 case INTEL_OUTPUT_UNKNOWN:
10174 if (WARN_ON(!HAS_DDI(dev)))
10175 break;
10176 case INTEL_OUTPUT_DISPLAYPORT:
10177 case INTEL_OUTPUT_HDMI:
10178 case INTEL_OUTPUT_EDP:
10179 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10180
10181 /* the same port mustn't appear more than once */
10182 if (used_ports & port_mask)
10183 return false;
10184
10185 used_ports |= port_mask;
10186 default:
10187 break;
10188 }
10189 }
10190
10191 return true;
10192 }
10193
10194 static struct intel_crtc_state *
10195 intel_modeset_pipe_config(struct drm_crtc *crtc,
10196 struct drm_framebuffer *fb,
10197 struct drm_display_mode *mode)
10198 {
10199 struct drm_device *dev = crtc->dev;
10200 struct intel_encoder *encoder;
10201 struct intel_crtc_state *pipe_config;
10202 int plane_bpp, ret = -EINVAL;
10203 bool retry = true;
10204
10205 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10206 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10207 return ERR_PTR(-EINVAL);
10208 }
10209
10210 if (!check_digital_port_conflicts(dev)) {
10211 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10212 return ERR_PTR(-EINVAL);
10213 }
10214
10215 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10216 if (!pipe_config)
10217 return ERR_PTR(-ENOMEM);
10218
10219 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10220 drm_mode_copy(&pipe_config->base.mode, mode);
10221
10222 pipe_config->cpu_transcoder =
10223 (enum transcoder) to_intel_crtc(crtc)->pipe;
10224 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10225
10226 /*
10227 * Sanitize sync polarity flags based on requested ones. If neither
10228 * positive or negative polarity is requested, treat this as meaning
10229 * negative polarity.
10230 */
10231 if (!(pipe_config->base.adjusted_mode.flags &
10232 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10233 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10234
10235 if (!(pipe_config->base.adjusted_mode.flags &
10236 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10237 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10238
10239 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10240 * plane pixel format and any sink constraints into account. Returns the
10241 * source plane bpp so that dithering can be selected on mismatches
10242 * after encoders and crtc also have had their say. */
10243 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10244 fb, pipe_config);
10245 if (plane_bpp < 0)
10246 goto fail;
10247
10248 /*
10249 * Determine the real pipe dimensions. Note that stereo modes can
10250 * increase the actual pipe size due to the frame doubling and
10251 * insertion of additional space for blanks between the frame. This
10252 * is stored in the crtc timings. We use the requested mode to do this
10253 * computation to clearly distinguish it from the adjusted mode, which
10254 * can be changed by the connectors in the below retry loop.
10255 */
10256 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10257 &pipe_config->pipe_src_w,
10258 &pipe_config->pipe_src_h);
10259
10260 encoder_retry:
10261 /* Ensure the port clock defaults are reset when retrying. */
10262 pipe_config->port_clock = 0;
10263 pipe_config->pixel_multiplier = 1;
10264
10265 /* Fill in default crtc timings, allow encoders to overwrite them. */
10266 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10267 CRTC_STEREO_DOUBLE);
10268
10269 /* Pass our mode to the connectors and the CRTC to give them a chance to
10270 * adjust it according to limitations or connector properties, and also
10271 * a chance to reject the mode entirely.
10272 */
10273 for_each_intel_encoder(dev, encoder) {
10274
10275 if (&encoder->new_crtc->base != crtc)
10276 continue;
10277
10278 if (!(encoder->compute_config(encoder, pipe_config))) {
10279 DRM_DEBUG_KMS("Encoder config failure\n");
10280 goto fail;
10281 }
10282 }
10283
10284 /* Set default port clock if not overwritten by the encoder. Needs to be
10285 * done afterwards in case the encoder adjusts the mode. */
10286 if (!pipe_config->port_clock)
10287 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10288 * pipe_config->pixel_multiplier;
10289
10290 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10291 if (ret < 0) {
10292 DRM_DEBUG_KMS("CRTC fixup failed\n");
10293 goto fail;
10294 }
10295
10296 if (ret == RETRY) {
10297 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10298 ret = -EINVAL;
10299 goto fail;
10300 }
10301
10302 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10303 retry = false;
10304 goto encoder_retry;
10305 }
10306
10307 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10308 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10309 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10310
10311 return pipe_config;
10312 fail:
10313 kfree(pipe_config);
10314 return ERR_PTR(ret);
10315 }
10316
10317 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10318 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10319 static void
10320 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10321 unsigned *prepare_pipes, unsigned *disable_pipes)
10322 {
10323 struct intel_crtc *intel_crtc;
10324 struct drm_device *dev = crtc->dev;
10325 struct intel_encoder *encoder;
10326 struct intel_connector *connector;
10327 struct drm_crtc *tmp_crtc;
10328
10329 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10330
10331 /* Check which crtcs have changed outputs connected to them, these need
10332 * to be part of the prepare_pipes mask. We don't (yet) support global
10333 * modeset across multiple crtcs, so modeset_pipes will only have one
10334 * bit set at most. */
10335 list_for_each_entry(connector, &dev->mode_config.connector_list,
10336 base.head) {
10337 if (connector->base.encoder == &connector->new_encoder->base)
10338 continue;
10339
10340 if (connector->base.encoder) {
10341 tmp_crtc = connector->base.encoder->crtc;
10342
10343 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10344 }
10345
10346 if (connector->new_encoder)
10347 *prepare_pipes |=
10348 1 << connector->new_encoder->new_crtc->pipe;
10349 }
10350
10351 for_each_intel_encoder(dev, encoder) {
10352 if (encoder->base.crtc == &encoder->new_crtc->base)
10353 continue;
10354
10355 if (encoder->base.crtc) {
10356 tmp_crtc = encoder->base.crtc;
10357
10358 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10359 }
10360
10361 if (encoder->new_crtc)
10362 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10363 }
10364
10365 /* Check for pipes that will be enabled/disabled ... */
10366 for_each_intel_crtc(dev, intel_crtc) {
10367 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10368 continue;
10369
10370 if (!intel_crtc->new_enabled)
10371 *disable_pipes |= 1 << intel_crtc->pipe;
10372 else
10373 *prepare_pipes |= 1 << intel_crtc->pipe;
10374 }
10375
10376
10377 /* set_mode is also used to update properties on life display pipes. */
10378 intel_crtc = to_intel_crtc(crtc);
10379 if (intel_crtc->new_enabled)
10380 *prepare_pipes |= 1 << intel_crtc->pipe;
10381
10382 /*
10383 * For simplicity do a full modeset on any pipe where the output routing
10384 * changed. We could be more clever, but that would require us to be
10385 * more careful with calling the relevant encoder->mode_set functions.
10386 */
10387 if (*prepare_pipes)
10388 *modeset_pipes = *prepare_pipes;
10389
10390 /* ... and mask these out. */
10391 *modeset_pipes &= ~(*disable_pipes);
10392 *prepare_pipes &= ~(*disable_pipes);
10393
10394 /*
10395 * HACK: We don't (yet) fully support global modesets. intel_set_config
10396 * obies this rule, but the modeset restore mode of
10397 * intel_modeset_setup_hw_state does not.
10398 */
10399 *modeset_pipes &= 1 << intel_crtc->pipe;
10400 *prepare_pipes &= 1 << intel_crtc->pipe;
10401
10402 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10403 *modeset_pipes, *prepare_pipes, *disable_pipes);
10404 }
10405
10406 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10407 {
10408 struct drm_encoder *encoder;
10409 struct drm_device *dev = crtc->dev;
10410
10411 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10412 if (encoder->crtc == crtc)
10413 return true;
10414
10415 return false;
10416 }
10417
10418 static void
10419 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10420 {
10421 struct drm_i915_private *dev_priv = dev->dev_private;
10422 struct intel_encoder *intel_encoder;
10423 struct intel_crtc *intel_crtc;
10424 struct drm_connector *connector;
10425
10426 intel_shared_dpll_commit(dev_priv);
10427
10428 for_each_intel_encoder(dev, intel_encoder) {
10429 if (!intel_encoder->base.crtc)
10430 continue;
10431
10432 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10433
10434 if (prepare_pipes & (1 << intel_crtc->pipe))
10435 intel_encoder->connectors_active = false;
10436 }
10437
10438 intel_modeset_commit_output_state(dev);
10439
10440 /* Double check state. */
10441 for_each_intel_crtc(dev, intel_crtc) {
10442 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10443 WARN_ON(intel_crtc->new_config &&
10444 intel_crtc->new_config != intel_crtc->config);
10445 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10446 }
10447
10448 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10449 if (!connector->encoder || !connector->encoder->crtc)
10450 continue;
10451
10452 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10453
10454 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10455 struct drm_property *dpms_property =
10456 dev->mode_config.dpms_property;
10457
10458 connector->dpms = DRM_MODE_DPMS_ON;
10459 drm_object_property_set_value(&connector->base,
10460 dpms_property,
10461 DRM_MODE_DPMS_ON);
10462
10463 intel_encoder = to_intel_encoder(connector->encoder);
10464 intel_encoder->connectors_active = true;
10465 }
10466 }
10467
10468 }
10469
10470 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10471 {
10472 int diff;
10473
10474 if (clock1 == clock2)
10475 return true;
10476
10477 if (!clock1 || !clock2)
10478 return false;
10479
10480 diff = abs(clock1 - clock2);
10481
10482 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10483 return true;
10484
10485 return false;
10486 }
10487
10488 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10489 list_for_each_entry((intel_crtc), \
10490 &(dev)->mode_config.crtc_list, \
10491 base.head) \
10492 if (mask & (1 <<(intel_crtc)->pipe))
10493
10494 static bool
10495 intel_pipe_config_compare(struct drm_device *dev,
10496 struct intel_crtc_state *current_config,
10497 struct intel_crtc_state *pipe_config)
10498 {
10499 #define PIPE_CONF_CHECK_X(name) \
10500 if (current_config->name != pipe_config->name) { \
10501 DRM_ERROR("mismatch in " #name " " \
10502 "(expected 0x%08x, found 0x%08x)\n", \
10503 current_config->name, \
10504 pipe_config->name); \
10505 return false; \
10506 }
10507
10508 #define PIPE_CONF_CHECK_I(name) \
10509 if (current_config->name != pipe_config->name) { \
10510 DRM_ERROR("mismatch in " #name " " \
10511 "(expected %i, found %i)\n", \
10512 current_config->name, \
10513 pipe_config->name); \
10514 return false; \
10515 }
10516
10517 /* This is required for BDW+ where there is only one set of registers for
10518 * switching between high and low RR.
10519 * This macro can be used whenever a comparison has to be made between one
10520 * hw state and multiple sw state variables.
10521 */
10522 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10523 if ((current_config->name != pipe_config->name) && \
10524 (current_config->alt_name != pipe_config->name)) { \
10525 DRM_ERROR("mismatch in " #name " " \
10526 "(expected %i or %i, found %i)\n", \
10527 current_config->name, \
10528 current_config->alt_name, \
10529 pipe_config->name); \
10530 return false; \
10531 }
10532
10533 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10534 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10535 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10536 "(expected %i, found %i)\n", \
10537 current_config->name & (mask), \
10538 pipe_config->name & (mask)); \
10539 return false; \
10540 }
10541
10542 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10543 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10544 DRM_ERROR("mismatch in " #name " " \
10545 "(expected %i, found %i)\n", \
10546 current_config->name, \
10547 pipe_config->name); \
10548 return false; \
10549 }
10550
10551 #define PIPE_CONF_QUIRK(quirk) \
10552 ((current_config->quirks | pipe_config->quirks) & (quirk))
10553
10554 PIPE_CONF_CHECK_I(cpu_transcoder);
10555
10556 PIPE_CONF_CHECK_I(has_pch_encoder);
10557 PIPE_CONF_CHECK_I(fdi_lanes);
10558 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10559 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10560 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10561 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10562 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10563
10564 PIPE_CONF_CHECK_I(has_dp_encoder);
10565
10566 if (INTEL_INFO(dev)->gen < 8) {
10567 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10568 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10569 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10570 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10571 PIPE_CONF_CHECK_I(dp_m_n.tu);
10572
10573 if (current_config->has_drrs) {
10574 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10575 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10576 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10577 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10578 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10579 }
10580 } else {
10581 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10582 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10583 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10584 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10585 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10586 }
10587
10588 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10589 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10590 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10591 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10592 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10593 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10594
10595 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10601
10602 PIPE_CONF_CHECK_I(pixel_multiplier);
10603 PIPE_CONF_CHECK_I(has_hdmi_sink);
10604 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10605 IS_VALLEYVIEW(dev))
10606 PIPE_CONF_CHECK_I(limited_color_range);
10607 PIPE_CONF_CHECK_I(has_infoframe);
10608
10609 PIPE_CONF_CHECK_I(has_audio);
10610
10611 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10612 DRM_MODE_FLAG_INTERLACE);
10613
10614 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10615 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10616 DRM_MODE_FLAG_PHSYNC);
10617 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10618 DRM_MODE_FLAG_NHSYNC);
10619 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10620 DRM_MODE_FLAG_PVSYNC);
10621 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10622 DRM_MODE_FLAG_NVSYNC);
10623 }
10624
10625 PIPE_CONF_CHECK_I(pipe_src_w);
10626 PIPE_CONF_CHECK_I(pipe_src_h);
10627
10628 /*
10629 * FIXME: BIOS likes to set up a cloned config with lvds+external
10630 * screen. Since we don't yet re-compute the pipe config when moving
10631 * just the lvds port away to another pipe the sw tracking won't match.
10632 *
10633 * Proper atomic modesets with recomputed global state will fix this.
10634 * Until then just don't check gmch state for inherited modes.
10635 */
10636 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10637 PIPE_CONF_CHECK_I(gmch_pfit.control);
10638 /* pfit ratios are autocomputed by the hw on gen4+ */
10639 if (INTEL_INFO(dev)->gen < 4)
10640 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10641 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10642 }
10643
10644 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10645 if (current_config->pch_pfit.enabled) {
10646 PIPE_CONF_CHECK_I(pch_pfit.pos);
10647 PIPE_CONF_CHECK_I(pch_pfit.size);
10648 }
10649
10650 /* BDW+ don't expose a synchronous way to read the state */
10651 if (IS_HASWELL(dev))
10652 PIPE_CONF_CHECK_I(ips_enabled);
10653
10654 PIPE_CONF_CHECK_I(double_wide);
10655
10656 PIPE_CONF_CHECK_X(ddi_pll_sel);
10657
10658 PIPE_CONF_CHECK_I(shared_dpll);
10659 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10660 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10661 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10662 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10663 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10664 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10665 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10666 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10667
10668 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10669 PIPE_CONF_CHECK_I(pipe_bpp);
10670
10671 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10672 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10673
10674 #undef PIPE_CONF_CHECK_X
10675 #undef PIPE_CONF_CHECK_I
10676 #undef PIPE_CONF_CHECK_I_ALT
10677 #undef PIPE_CONF_CHECK_FLAGS
10678 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10679 #undef PIPE_CONF_QUIRK
10680
10681 return true;
10682 }
10683
10684 static void check_wm_state(struct drm_device *dev)
10685 {
10686 struct drm_i915_private *dev_priv = dev->dev_private;
10687 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10688 struct intel_crtc *intel_crtc;
10689 int plane;
10690
10691 if (INTEL_INFO(dev)->gen < 9)
10692 return;
10693
10694 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10695 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10696
10697 for_each_intel_crtc(dev, intel_crtc) {
10698 struct skl_ddb_entry *hw_entry, *sw_entry;
10699 const enum pipe pipe = intel_crtc->pipe;
10700
10701 if (!intel_crtc->active)
10702 continue;
10703
10704 /* planes */
10705 for_each_plane(pipe, plane) {
10706 hw_entry = &hw_ddb.plane[pipe][plane];
10707 sw_entry = &sw_ddb->plane[pipe][plane];
10708
10709 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10710 continue;
10711
10712 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10713 "(expected (%u,%u), found (%u,%u))\n",
10714 pipe_name(pipe), plane + 1,
10715 sw_entry->start, sw_entry->end,
10716 hw_entry->start, hw_entry->end);
10717 }
10718
10719 /* cursor */
10720 hw_entry = &hw_ddb.cursor[pipe];
10721 sw_entry = &sw_ddb->cursor[pipe];
10722
10723 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10724 continue;
10725
10726 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10727 "(expected (%u,%u), found (%u,%u))\n",
10728 pipe_name(pipe),
10729 sw_entry->start, sw_entry->end,
10730 hw_entry->start, hw_entry->end);
10731 }
10732 }
10733
10734 static void
10735 check_connector_state(struct drm_device *dev)
10736 {
10737 struct intel_connector *connector;
10738
10739 list_for_each_entry(connector, &dev->mode_config.connector_list,
10740 base.head) {
10741 /* This also checks the encoder/connector hw state with the
10742 * ->get_hw_state callbacks. */
10743 intel_connector_check_state(connector);
10744
10745 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10746 "connector's staged encoder doesn't match current encoder\n");
10747 }
10748 }
10749
10750 static void
10751 check_encoder_state(struct drm_device *dev)
10752 {
10753 struct intel_encoder *encoder;
10754 struct intel_connector *connector;
10755
10756 for_each_intel_encoder(dev, encoder) {
10757 bool enabled = false;
10758 bool active = false;
10759 enum pipe pipe, tracked_pipe;
10760
10761 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10762 encoder->base.base.id,
10763 encoder->base.name);
10764
10765 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10766 "encoder's stage crtc doesn't match current crtc\n");
10767 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10768 "encoder's active_connectors set, but no crtc\n");
10769
10770 list_for_each_entry(connector, &dev->mode_config.connector_list,
10771 base.head) {
10772 if (connector->base.encoder != &encoder->base)
10773 continue;
10774 enabled = true;
10775 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10776 active = true;
10777 }
10778 /*
10779 * for MST connectors if we unplug the connector is gone
10780 * away but the encoder is still connected to a crtc
10781 * until a modeset happens in response to the hotplug.
10782 */
10783 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10784 continue;
10785
10786 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10787 "encoder's enabled state mismatch "
10788 "(expected %i, found %i)\n",
10789 !!encoder->base.crtc, enabled);
10790 I915_STATE_WARN(active && !encoder->base.crtc,
10791 "active encoder with no crtc\n");
10792
10793 I915_STATE_WARN(encoder->connectors_active != active,
10794 "encoder's computed active state doesn't match tracked active state "
10795 "(expected %i, found %i)\n", active, encoder->connectors_active);
10796
10797 active = encoder->get_hw_state(encoder, &pipe);
10798 I915_STATE_WARN(active != encoder->connectors_active,
10799 "encoder's hw state doesn't match sw tracking "
10800 "(expected %i, found %i)\n",
10801 encoder->connectors_active, active);
10802
10803 if (!encoder->base.crtc)
10804 continue;
10805
10806 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10807 I915_STATE_WARN(active && pipe != tracked_pipe,
10808 "active encoder's pipe doesn't match"
10809 "(expected %i, found %i)\n",
10810 tracked_pipe, pipe);
10811
10812 }
10813 }
10814
10815 static void
10816 check_crtc_state(struct drm_device *dev)
10817 {
10818 struct drm_i915_private *dev_priv = dev->dev_private;
10819 struct intel_crtc *crtc;
10820 struct intel_encoder *encoder;
10821 struct intel_crtc_state pipe_config;
10822
10823 for_each_intel_crtc(dev, crtc) {
10824 bool enabled = false;
10825 bool active = false;
10826
10827 memset(&pipe_config, 0, sizeof(pipe_config));
10828
10829 DRM_DEBUG_KMS("[CRTC:%d]\n",
10830 crtc->base.base.id);
10831
10832 I915_STATE_WARN(crtc->active && !crtc->base.enabled,
10833 "active crtc, but not enabled in sw tracking\n");
10834
10835 for_each_intel_encoder(dev, encoder) {
10836 if (encoder->base.crtc != &crtc->base)
10837 continue;
10838 enabled = true;
10839 if (encoder->connectors_active)
10840 active = true;
10841 }
10842
10843 I915_STATE_WARN(active != crtc->active,
10844 "crtc's computed active state doesn't match tracked active state "
10845 "(expected %i, found %i)\n", active, crtc->active);
10846 I915_STATE_WARN(enabled != crtc->base.enabled,
10847 "crtc's computed enabled state doesn't match tracked enabled state "
10848 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10849
10850 active = dev_priv->display.get_pipe_config(crtc,
10851 &pipe_config);
10852
10853 /* hw state is inconsistent with the pipe quirk */
10854 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10855 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10856 active = crtc->active;
10857
10858 for_each_intel_encoder(dev, encoder) {
10859 enum pipe pipe;
10860 if (encoder->base.crtc != &crtc->base)
10861 continue;
10862 if (encoder->get_hw_state(encoder, &pipe))
10863 encoder->get_config(encoder, &pipe_config);
10864 }
10865
10866 I915_STATE_WARN(crtc->active != active,
10867 "crtc active state doesn't match with hw state "
10868 "(expected %i, found %i)\n", crtc->active, active);
10869
10870 if (active &&
10871 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10872 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10873 intel_dump_pipe_config(crtc, &pipe_config,
10874 "[hw state]");
10875 intel_dump_pipe_config(crtc, crtc->config,
10876 "[sw state]");
10877 }
10878 }
10879 }
10880
10881 static void
10882 check_shared_dpll_state(struct drm_device *dev)
10883 {
10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct intel_crtc *crtc;
10886 struct intel_dpll_hw_state dpll_hw_state;
10887 int i;
10888
10889 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10890 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10891 int enabled_crtcs = 0, active_crtcs = 0;
10892 bool active;
10893
10894 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10895
10896 DRM_DEBUG_KMS("%s\n", pll->name);
10897
10898 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10899
10900 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
10901 "more active pll users than references: %i vs %i\n",
10902 pll->active, hweight32(pll->config.crtc_mask));
10903 I915_STATE_WARN(pll->active && !pll->on,
10904 "pll in active use but not on in sw tracking\n");
10905 I915_STATE_WARN(pll->on && !pll->active,
10906 "pll in on but not on in use in sw tracking\n");
10907 I915_STATE_WARN(pll->on != active,
10908 "pll on state mismatch (expected %i, found %i)\n",
10909 pll->on, active);
10910
10911 for_each_intel_crtc(dev, crtc) {
10912 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10913 enabled_crtcs++;
10914 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10915 active_crtcs++;
10916 }
10917 I915_STATE_WARN(pll->active != active_crtcs,
10918 "pll active crtcs mismatch (expected %i, found %i)\n",
10919 pll->active, active_crtcs);
10920 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10921 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10922 hweight32(pll->config.crtc_mask), enabled_crtcs);
10923
10924 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10925 sizeof(dpll_hw_state)),
10926 "pll hw state mismatch\n");
10927 }
10928 }
10929
10930 void
10931 intel_modeset_check_state(struct drm_device *dev)
10932 {
10933 check_wm_state(dev);
10934 check_connector_state(dev);
10935 check_encoder_state(dev);
10936 check_crtc_state(dev);
10937 check_shared_dpll_state(dev);
10938 }
10939
10940 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10941 int dotclock)
10942 {
10943 /*
10944 * FDI already provided one idea for the dotclock.
10945 * Yell if the encoder disagrees.
10946 */
10947 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10948 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10949 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10950 }
10951
10952 static void update_scanline_offset(struct intel_crtc *crtc)
10953 {
10954 struct drm_device *dev = crtc->base.dev;
10955
10956 /*
10957 * The scanline counter increments at the leading edge of hsync.
10958 *
10959 * On most platforms it starts counting from vtotal-1 on the
10960 * first active line. That means the scanline counter value is
10961 * always one less than what we would expect. Ie. just after
10962 * start of vblank, which also occurs at start of hsync (on the
10963 * last active line), the scanline counter will read vblank_start-1.
10964 *
10965 * On gen2 the scanline counter starts counting from 1 instead
10966 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10967 * to keep the value positive), instead of adding one.
10968 *
10969 * On HSW+ the behaviour of the scanline counter depends on the output
10970 * type. For DP ports it behaves like most other platforms, but on HDMI
10971 * there's an extra 1 line difference. So we need to add two instead of
10972 * one to the value.
10973 */
10974 if (IS_GEN2(dev)) {
10975 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10976 int vtotal;
10977
10978 vtotal = mode->crtc_vtotal;
10979 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10980 vtotal /= 2;
10981
10982 crtc->scanline_offset = vtotal - 1;
10983 } else if (HAS_DDI(dev) &&
10984 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10985 crtc->scanline_offset = 2;
10986 } else
10987 crtc->scanline_offset = 1;
10988 }
10989
10990 static struct intel_crtc_state *
10991 intel_modeset_compute_config(struct drm_crtc *crtc,
10992 struct drm_display_mode *mode,
10993 struct drm_framebuffer *fb,
10994 unsigned *modeset_pipes,
10995 unsigned *prepare_pipes,
10996 unsigned *disable_pipes)
10997 {
10998 struct intel_crtc_state *pipe_config = NULL;
10999
11000 intel_modeset_affected_pipes(crtc, modeset_pipes,
11001 prepare_pipes, disable_pipes);
11002
11003 if ((*modeset_pipes) == 0)
11004 goto out;
11005
11006 /*
11007 * Note this needs changes when we start tracking multiple modes
11008 * and crtcs. At that point we'll need to compute the whole config
11009 * (i.e. one pipe_config for each crtc) rather than just the one
11010 * for this crtc.
11011 */
11012 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11013 if (IS_ERR(pipe_config)) {
11014 goto out;
11015 }
11016 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11017 "[modeset]");
11018
11019 out:
11020 return pipe_config;
11021 }
11022
11023 static int __intel_set_mode(struct drm_crtc *crtc,
11024 struct drm_display_mode *mode,
11025 int x, int y, struct drm_framebuffer *fb,
11026 struct intel_crtc_state *pipe_config,
11027 unsigned modeset_pipes,
11028 unsigned prepare_pipes,
11029 unsigned disable_pipes)
11030 {
11031 struct drm_device *dev = crtc->dev;
11032 struct drm_i915_private *dev_priv = dev->dev_private;
11033 struct drm_display_mode *saved_mode;
11034 struct intel_crtc *intel_crtc;
11035 int ret = 0;
11036
11037 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11038 if (!saved_mode)
11039 return -ENOMEM;
11040
11041 *saved_mode = crtc->mode;
11042
11043 if (modeset_pipes)
11044 to_intel_crtc(crtc)->new_config = pipe_config;
11045
11046 /*
11047 * See if the config requires any additional preparation, e.g.
11048 * to adjust global state with pipes off. We need to do this
11049 * here so we can get the modeset_pipe updated config for the new
11050 * mode set on this crtc. For other crtcs we need to use the
11051 * adjusted_mode bits in the crtc directly.
11052 */
11053 if (IS_VALLEYVIEW(dev)) {
11054 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11055
11056 /* may have added more to prepare_pipes than we should */
11057 prepare_pipes &= ~disable_pipes;
11058 }
11059
11060 if (dev_priv->display.crtc_compute_clock) {
11061 unsigned clear_pipes = modeset_pipes | disable_pipes;
11062
11063 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11064 if (ret)
11065 goto done;
11066
11067 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11068 struct intel_crtc_state *state = intel_crtc->new_config;
11069 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11070 state);
11071 if (ret) {
11072 intel_shared_dpll_abort_config(dev_priv);
11073 goto done;
11074 }
11075 }
11076 }
11077
11078 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11079 intel_crtc_disable(&intel_crtc->base);
11080
11081 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11082 if (intel_crtc->base.enabled)
11083 dev_priv->display.crtc_disable(&intel_crtc->base);
11084 }
11085
11086 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11087 * to set it here already despite that we pass it down the callchain.
11088 *
11089 * Note we'll need to fix this up when we start tracking multiple
11090 * pipes; here we assume a single modeset_pipe and only track the
11091 * single crtc and mode.
11092 */
11093 if (modeset_pipes) {
11094 crtc->mode = *mode;
11095 /* mode_set/enable/disable functions rely on a correct pipe
11096 * config. */
11097 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11098
11099 /*
11100 * Calculate and store various constants which
11101 * are later needed by vblank and swap-completion
11102 * timestamping. They are derived from true hwmode.
11103 */
11104 drm_calc_timestamping_constants(crtc,
11105 &pipe_config->base.adjusted_mode);
11106 }
11107
11108 /* Only after disabling all output pipelines that will be changed can we
11109 * update the the output configuration. */
11110 intel_modeset_update_state(dev, prepare_pipes);
11111
11112 modeset_update_crtc_power_domains(dev);
11113
11114 /* Set up the DPLL and any encoders state that needs to adjust or depend
11115 * on the DPLL.
11116 */
11117 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11118 struct drm_plane *primary = intel_crtc->base.primary;
11119 int vdisplay, hdisplay;
11120
11121 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11122 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11123 fb, 0, 0,
11124 hdisplay, vdisplay,
11125 x << 16, y << 16,
11126 hdisplay << 16, vdisplay << 16);
11127 }
11128
11129 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11130 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11131 update_scanline_offset(intel_crtc);
11132
11133 dev_priv->display.crtc_enable(&intel_crtc->base);
11134 }
11135
11136 /* FIXME: add subpixel order */
11137 done:
11138 if (ret && crtc->enabled)
11139 crtc->mode = *saved_mode;
11140
11141 kfree(saved_mode);
11142 return ret;
11143 }
11144
11145 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11146 struct drm_display_mode *mode,
11147 int x, int y, struct drm_framebuffer *fb,
11148 struct intel_crtc_state *pipe_config,
11149 unsigned modeset_pipes,
11150 unsigned prepare_pipes,
11151 unsigned disable_pipes)
11152 {
11153 int ret;
11154
11155 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11156 prepare_pipes, disable_pipes);
11157
11158 if (ret == 0)
11159 intel_modeset_check_state(crtc->dev);
11160
11161 return ret;
11162 }
11163
11164 static int intel_set_mode(struct drm_crtc *crtc,
11165 struct drm_display_mode *mode,
11166 int x, int y, struct drm_framebuffer *fb)
11167 {
11168 struct intel_crtc_state *pipe_config;
11169 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11170
11171 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11172 &modeset_pipes,
11173 &prepare_pipes,
11174 &disable_pipes);
11175
11176 if (IS_ERR(pipe_config))
11177 return PTR_ERR(pipe_config);
11178
11179 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11180 modeset_pipes, prepare_pipes,
11181 disable_pipes);
11182 }
11183
11184 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11185 {
11186 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11187 }
11188
11189 #undef for_each_intel_crtc_masked
11190
11191 static void intel_set_config_free(struct intel_set_config *config)
11192 {
11193 if (!config)
11194 return;
11195
11196 kfree(config->save_connector_encoders);
11197 kfree(config->save_encoder_crtcs);
11198 kfree(config->save_crtc_enabled);
11199 kfree(config);
11200 }
11201
11202 static int intel_set_config_save_state(struct drm_device *dev,
11203 struct intel_set_config *config)
11204 {
11205 struct drm_crtc *crtc;
11206 struct drm_encoder *encoder;
11207 struct drm_connector *connector;
11208 int count;
11209
11210 config->save_crtc_enabled =
11211 kcalloc(dev->mode_config.num_crtc,
11212 sizeof(bool), GFP_KERNEL);
11213 if (!config->save_crtc_enabled)
11214 return -ENOMEM;
11215
11216 config->save_encoder_crtcs =
11217 kcalloc(dev->mode_config.num_encoder,
11218 sizeof(struct drm_crtc *), GFP_KERNEL);
11219 if (!config->save_encoder_crtcs)
11220 return -ENOMEM;
11221
11222 config->save_connector_encoders =
11223 kcalloc(dev->mode_config.num_connector,
11224 sizeof(struct drm_encoder *), GFP_KERNEL);
11225 if (!config->save_connector_encoders)
11226 return -ENOMEM;
11227
11228 /* Copy data. Note that driver private data is not affected.
11229 * Should anything bad happen only the expected state is
11230 * restored, not the drivers personal bookkeeping.
11231 */
11232 count = 0;
11233 for_each_crtc(dev, crtc) {
11234 config->save_crtc_enabled[count++] = crtc->enabled;
11235 }
11236
11237 count = 0;
11238 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11239 config->save_encoder_crtcs[count++] = encoder->crtc;
11240 }
11241
11242 count = 0;
11243 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11244 config->save_connector_encoders[count++] = connector->encoder;
11245 }
11246
11247 return 0;
11248 }
11249
11250 static void intel_set_config_restore_state(struct drm_device *dev,
11251 struct intel_set_config *config)
11252 {
11253 struct intel_crtc *crtc;
11254 struct intel_encoder *encoder;
11255 struct intel_connector *connector;
11256 int count;
11257
11258 count = 0;
11259 for_each_intel_crtc(dev, crtc) {
11260 crtc->new_enabled = config->save_crtc_enabled[count++];
11261
11262 if (crtc->new_enabled)
11263 crtc->new_config = crtc->config;
11264 else
11265 crtc->new_config = NULL;
11266 }
11267
11268 count = 0;
11269 for_each_intel_encoder(dev, encoder) {
11270 encoder->new_crtc =
11271 to_intel_crtc(config->save_encoder_crtcs[count++]);
11272 }
11273
11274 count = 0;
11275 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11276 connector->new_encoder =
11277 to_intel_encoder(config->save_connector_encoders[count++]);
11278 }
11279 }
11280
11281 static bool
11282 is_crtc_connector_off(struct drm_mode_set *set)
11283 {
11284 int i;
11285
11286 if (set->num_connectors == 0)
11287 return false;
11288
11289 if (WARN_ON(set->connectors == NULL))
11290 return false;
11291
11292 for (i = 0; i < set->num_connectors; i++)
11293 if (set->connectors[i]->encoder &&
11294 set->connectors[i]->encoder->crtc == set->crtc &&
11295 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11296 return true;
11297
11298 return false;
11299 }
11300
11301 static void
11302 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11303 struct intel_set_config *config)
11304 {
11305
11306 /* We should be able to check here if the fb has the same properties
11307 * and then just flip_or_move it */
11308 if (is_crtc_connector_off(set)) {
11309 config->mode_changed = true;
11310 } else if (set->crtc->primary->fb != set->fb) {
11311 /*
11312 * If we have no fb, we can only flip as long as the crtc is
11313 * active, otherwise we need a full mode set. The crtc may
11314 * be active if we've only disabled the primary plane, or
11315 * in fastboot situations.
11316 */
11317 if (set->crtc->primary->fb == NULL) {
11318 struct intel_crtc *intel_crtc =
11319 to_intel_crtc(set->crtc);
11320
11321 if (intel_crtc->active) {
11322 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11323 config->fb_changed = true;
11324 } else {
11325 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11326 config->mode_changed = true;
11327 }
11328 } else if (set->fb == NULL) {
11329 config->mode_changed = true;
11330 } else if (set->fb->pixel_format !=
11331 set->crtc->primary->fb->pixel_format) {
11332 config->mode_changed = true;
11333 } else {
11334 config->fb_changed = true;
11335 }
11336 }
11337
11338 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11339 config->fb_changed = true;
11340
11341 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11342 DRM_DEBUG_KMS("modes are different, full mode set\n");
11343 drm_mode_debug_printmodeline(&set->crtc->mode);
11344 drm_mode_debug_printmodeline(set->mode);
11345 config->mode_changed = true;
11346 }
11347
11348 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11349 set->crtc->base.id, config->mode_changed, config->fb_changed);
11350 }
11351
11352 static int
11353 intel_modeset_stage_output_state(struct drm_device *dev,
11354 struct drm_mode_set *set,
11355 struct intel_set_config *config)
11356 {
11357 struct intel_connector *connector;
11358 struct intel_encoder *encoder;
11359 struct intel_crtc *crtc;
11360 int ro;
11361
11362 /* The upper layers ensure that we either disable a crtc or have a list
11363 * of connectors. For paranoia, double-check this. */
11364 WARN_ON(!set->fb && (set->num_connectors != 0));
11365 WARN_ON(set->fb && (set->num_connectors == 0));
11366
11367 list_for_each_entry(connector, &dev->mode_config.connector_list,
11368 base.head) {
11369 /* Otherwise traverse passed in connector list and get encoders
11370 * for them. */
11371 for (ro = 0; ro < set->num_connectors; ro++) {
11372 if (set->connectors[ro] == &connector->base) {
11373 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11374 break;
11375 }
11376 }
11377
11378 /* If we disable the crtc, disable all its connectors. Also, if
11379 * the connector is on the changing crtc but not on the new
11380 * connector list, disable it. */
11381 if ((!set->fb || ro == set->num_connectors) &&
11382 connector->base.encoder &&
11383 connector->base.encoder->crtc == set->crtc) {
11384 connector->new_encoder = NULL;
11385
11386 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11387 connector->base.base.id,
11388 connector->base.name);
11389 }
11390
11391
11392 if (&connector->new_encoder->base != connector->base.encoder) {
11393 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11394 config->mode_changed = true;
11395 }
11396 }
11397 /* connector->new_encoder is now updated for all connectors. */
11398
11399 /* Update crtc of enabled connectors. */
11400 list_for_each_entry(connector, &dev->mode_config.connector_list,
11401 base.head) {
11402 struct drm_crtc *new_crtc;
11403
11404 if (!connector->new_encoder)
11405 continue;
11406
11407 new_crtc = connector->new_encoder->base.crtc;
11408
11409 for (ro = 0; ro < set->num_connectors; ro++) {
11410 if (set->connectors[ro] == &connector->base)
11411 new_crtc = set->crtc;
11412 }
11413
11414 /* Make sure the new CRTC will work with the encoder */
11415 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11416 new_crtc)) {
11417 return -EINVAL;
11418 }
11419 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11420
11421 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11422 connector->base.base.id,
11423 connector->base.name,
11424 new_crtc->base.id);
11425 }
11426
11427 /* Check for any encoders that needs to be disabled. */
11428 for_each_intel_encoder(dev, encoder) {
11429 int num_connectors = 0;
11430 list_for_each_entry(connector,
11431 &dev->mode_config.connector_list,
11432 base.head) {
11433 if (connector->new_encoder == encoder) {
11434 WARN_ON(!connector->new_encoder->new_crtc);
11435 num_connectors++;
11436 }
11437 }
11438
11439 if (num_connectors == 0)
11440 encoder->new_crtc = NULL;
11441 else if (num_connectors > 1)
11442 return -EINVAL;
11443
11444 /* Only now check for crtc changes so we don't miss encoders
11445 * that will be disabled. */
11446 if (&encoder->new_crtc->base != encoder->base.crtc) {
11447 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11448 config->mode_changed = true;
11449 }
11450 }
11451 /* Now we've also updated encoder->new_crtc for all encoders. */
11452 list_for_each_entry(connector, &dev->mode_config.connector_list,
11453 base.head) {
11454 if (connector->new_encoder)
11455 if (connector->new_encoder != connector->encoder)
11456 connector->encoder = connector->new_encoder;
11457 }
11458 for_each_intel_crtc(dev, crtc) {
11459 crtc->new_enabled = false;
11460
11461 for_each_intel_encoder(dev, encoder) {
11462 if (encoder->new_crtc == crtc) {
11463 crtc->new_enabled = true;
11464 break;
11465 }
11466 }
11467
11468 if (crtc->new_enabled != crtc->base.enabled) {
11469 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11470 crtc->new_enabled ? "en" : "dis");
11471 config->mode_changed = true;
11472 }
11473
11474 if (crtc->new_enabled)
11475 crtc->new_config = crtc->config;
11476 else
11477 crtc->new_config = NULL;
11478 }
11479
11480 return 0;
11481 }
11482
11483 static void disable_crtc_nofb(struct intel_crtc *crtc)
11484 {
11485 struct drm_device *dev = crtc->base.dev;
11486 struct intel_encoder *encoder;
11487 struct intel_connector *connector;
11488
11489 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11490 pipe_name(crtc->pipe));
11491
11492 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11493 if (connector->new_encoder &&
11494 connector->new_encoder->new_crtc == crtc)
11495 connector->new_encoder = NULL;
11496 }
11497
11498 for_each_intel_encoder(dev, encoder) {
11499 if (encoder->new_crtc == crtc)
11500 encoder->new_crtc = NULL;
11501 }
11502
11503 crtc->new_enabled = false;
11504 crtc->new_config = NULL;
11505 }
11506
11507 static int intel_crtc_set_config(struct drm_mode_set *set)
11508 {
11509 struct drm_device *dev;
11510 struct drm_mode_set save_set;
11511 struct intel_set_config *config;
11512 struct intel_crtc_state *pipe_config;
11513 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11514 int ret;
11515
11516 BUG_ON(!set);
11517 BUG_ON(!set->crtc);
11518 BUG_ON(!set->crtc->helper_private);
11519
11520 /* Enforce sane interface api - has been abused by the fb helper. */
11521 BUG_ON(!set->mode && set->fb);
11522 BUG_ON(set->fb && set->num_connectors == 0);
11523
11524 if (set->fb) {
11525 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11526 set->crtc->base.id, set->fb->base.id,
11527 (int)set->num_connectors, set->x, set->y);
11528 } else {
11529 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11530 }
11531
11532 dev = set->crtc->dev;
11533
11534 ret = -ENOMEM;
11535 config = kzalloc(sizeof(*config), GFP_KERNEL);
11536 if (!config)
11537 goto out_config;
11538
11539 ret = intel_set_config_save_state(dev, config);
11540 if (ret)
11541 goto out_config;
11542
11543 save_set.crtc = set->crtc;
11544 save_set.mode = &set->crtc->mode;
11545 save_set.x = set->crtc->x;
11546 save_set.y = set->crtc->y;
11547 save_set.fb = set->crtc->primary->fb;
11548
11549 /* Compute whether we need a full modeset, only an fb base update or no
11550 * change at all. In the future we might also check whether only the
11551 * mode changed, e.g. for LVDS where we only change the panel fitter in
11552 * such cases. */
11553 intel_set_config_compute_mode_changes(set, config);
11554
11555 ret = intel_modeset_stage_output_state(dev, set, config);
11556 if (ret)
11557 goto fail;
11558
11559 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11560 set->fb,
11561 &modeset_pipes,
11562 &prepare_pipes,
11563 &disable_pipes);
11564 if (IS_ERR(pipe_config)) {
11565 ret = PTR_ERR(pipe_config);
11566 goto fail;
11567 } else if (pipe_config) {
11568 if (pipe_config->has_audio !=
11569 to_intel_crtc(set->crtc)->config->has_audio)
11570 config->mode_changed = true;
11571
11572 /*
11573 * Note we have an issue here with infoframes: current code
11574 * only updates them on the full mode set path per hw
11575 * requirements. So here we should be checking for any
11576 * required changes and forcing a mode set.
11577 */
11578 }
11579
11580 /* set_mode will free it in the mode_changed case */
11581 if (!config->mode_changed)
11582 kfree(pipe_config);
11583
11584 intel_update_pipe_size(to_intel_crtc(set->crtc));
11585
11586 if (config->mode_changed) {
11587 ret = intel_set_mode_pipes(set->crtc, set->mode,
11588 set->x, set->y, set->fb, pipe_config,
11589 modeset_pipes, prepare_pipes,
11590 disable_pipes);
11591 } else if (config->fb_changed) {
11592 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11593 struct drm_plane *primary = set->crtc->primary;
11594 int vdisplay, hdisplay;
11595
11596 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11597 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11598 0, 0, hdisplay, vdisplay,
11599 set->x << 16, set->y << 16,
11600 hdisplay << 16, vdisplay << 16);
11601
11602 /*
11603 * We need to make sure the primary plane is re-enabled if it
11604 * has previously been turned off.
11605 */
11606 if (!intel_crtc->primary_enabled && ret == 0) {
11607 WARN_ON(!intel_crtc->active);
11608 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11609 }
11610
11611 /*
11612 * In the fastboot case this may be our only check of the
11613 * state after boot. It would be better to only do it on
11614 * the first update, but we don't have a nice way of doing that
11615 * (and really, set_config isn't used much for high freq page
11616 * flipping, so increasing its cost here shouldn't be a big
11617 * deal).
11618 */
11619 if (i915.fastboot && ret == 0)
11620 intel_modeset_check_state(set->crtc->dev);
11621 }
11622
11623 if (ret) {
11624 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11625 set->crtc->base.id, ret);
11626 fail:
11627 intel_set_config_restore_state(dev, config);
11628
11629 /*
11630 * HACK: if the pipe was on, but we didn't have a framebuffer,
11631 * force the pipe off to avoid oopsing in the modeset code
11632 * due to fb==NULL. This should only happen during boot since
11633 * we don't yet reconstruct the FB from the hardware state.
11634 */
11635 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11636 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11637
11638 /* Try to restore the config */
11639 if (config->mode_changed &&
11640 intel_set_mode(save_set.crtc, save_set.mode,
11641 save_set.x, save_set.y, save_set.fb))
11642 DRM_ERROR("failed to restore config after modeset failure\n");
11643 }
11644
11645 out_config:
11646 intel_set_config_free(config);
11647 return ret;
11648 }
11649
11650 static const struct drm_crtc_funcs intel_crtc_funcs = {
11651 .gamma_set = intel_crtc_gamma_set,
11652 .set_config = intel_crtc_set_config,
11653 .destroy = intel_crtc_destroy,
11654 .page_flip = intel_crtc_page_flip,
11655 };
11656
11657 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11658 struct intel_shared_dpll *pll,
11659 struct intel_dpll_hw_state *hw_state)
11660 {
11661 uint32_t val;
11662
11663 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11664 return false;
11665
11666 val = I915_READ(PCH_DPLL(pll->id));
11667 hw_state->dpll = val;
11668 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11669 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11670
11671 return val & DPLL_VCO_ENABLE;
11672 }
11673
11674 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11675 struct intel_shared_dpll *pll)
11676 {
11677 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11678 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11679 }
11680
11681 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11682 struct intel_shared_dpll *pll)
11683 {
11684 /* PCH refclock must be enabled first */
11685 ibx_assert_pch_refclk_enabled(dev_priv);
11686
11687 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11688
11689 /* Wait for the clocks to stabilize. */
11690 POSTING_READ(PCH_DPLL(pll->id));
11691 udelay(150);
11692
11693 /* The pixel multiplier can only be updated once the
11694 * DPLL is enabled and the clocks are stable.
11695 *
11696 * So write it again.
11697 */
11698 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11699 POSTING_READ(PCH_DPLL(pll->id));
11700 udelay(200);
11701 }
11702
11703 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11704 struct intel_shared_dpll *pll)
11705 {
11706 struct drm_device *dev = dev_priv->dev;
11707 struct intel_crtc *crtc;
11708
11709 /* Make sure no transcoder isn't still depending on us. */
11710 for_each_intel_crtc(dev, crtc) {
11711 if (intel_crtc_to_shared_dpll(crtc) == pll)
11712 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11713 }
11714
11715 I915_WRITE(PCH_DPLL(pll->id), 0);
11716 POSTING_READ(PCH_DPLL(pll->id));
11717 udelay(200);
11718 }
11719
11720 static char *ibx_pch_dpll_names[] = {
11721 "PCH DPLL A",
11722 "PCH DPLL B",
11723 };
11724
11725 static void ibx_pch_dpll_init(struct drm_device *dev)
11726 {
11727 struct drm_i915_private *dev_priv = dev->dev_private;
11728 int i;
11729
11730 dev_priv->num_shared_dpll = 2;
11731
11732 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11733 dev_priv->shared_dplls[i].id = i;
11734 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11735 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11736 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11737 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11738 dev_priv->shared_dplls[i].get_hw_state =
11739 ibx_pch_dpll_get_hw_state;
11740 }
11741 }
11742
11743 static void intel_shared_dpll_init(struct drm_device *dev)
11744 {
11745 struct drm_i915_private *dev_priv = dev->dev_private;
11746
11747 if (HAS_DDI(dev))
11748 intel_ddi_pll_init(dev);
11749 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11750 ibx_pch_dpll_init(dev);
11751 else
11752 dev_priv->num_shared_dpll = 0;
11753
11754 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11755 }
11756
11757 /**
11758 * intel_prepare_plane_fb - Prepare fb for usage on plane
11759 * @plane: drm plane to prepare for
11760 * @fb: framebuffer to prepare for presentation
11761 *
11762 * Prepares a framebuffer for usage on a display plane. Generally this
11763 * involves pinning the underlying object and updating the frontbuffer tracking
11764 * bits. Some older platforms need special physical address handling for
11765 * cursor planes.
11766 *
11767 * Returns 0 on success, negative error code on failure.
11768 */
11769 int
11770 intel_prepare_plane_fb(struct drm_plane *plane,
11771 struct drm_framebuffer *fb)
11772 {
11773 struct drm_device *dev = plane->dev;
11774 struct intel_plane *intel_plane = to_intel_plane(plane);
11775 enum pipe pipe = intel_plane->pipe;
11776 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11777 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11778 unsigned frontbuffer_bits = 0;
11779 int ret = 0;
11780
11781 if (!obj)
11782 return 0;
11783
11784 switch (plane->type) {
11785 case DRM_PLANE_TYPE_PRIMARY:
11786 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11787 break;
11788 case DRM_PLANE_TYPE_CURSOR:
11789 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11790 break;
11791 case DRM_PLANE_TYPE_OVERLAY:
11792 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11793 break;
11794 }
11795
11796 mutex_lock(&dev->struct_mutex);
11797
11798 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11799 INTEL_INFO(dev)->cursor_needs_physical) {
11800 int align = IS_I830(dev) ? 16 * 1024 : 256;
11801 ret = i915_gem_object_attach_phys(obj, align);
11802 if (ret)
11803 DRM_DEBUG_KMS("failed to attach phys object\n");
11804 } else {
11805 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11806 }
11807
11808 if (ret == 0)
11809 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11810
11811 mutex_unlock(&dev->struct_mutex);
11812
11813 return ret;
11814 }
11815
11816 /**
11817 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11818 * @plane: drm plane to clean up for
11819 * @fb: old framebuffer that was on plane
11820 *
11821 * Cleans up a framebuffer that has just been removed from a plane.
11822 */
11823 void
11824 intel_cleanup_plane_fb(struct drm_plane *plane,
11825 struct drm_framebuffer *fb)
11826 {
11827 struct drm_device *dev = plane->dev;
11828 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11829
11830 if (WARN_ON(!obj))
11831 return;
11832
11833 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
11834 !INTEL_INFO(dev)->cursor_needs_physical) {
11835 mutex_lock(&dev->struct_mutex);
11836 intel_unpin_fb_obj(obj);
11837 mutex_unlock(&dev->struct_mutex);
11838 }
11839 }
11840
11841 static int
11842 intel_check_primary_plane(struct drm_plane *plane,
11843 struct intel_plane_state *state)
11844 {
11845 struct drm_device *dev = plane->dev;
11846 struct drm_i915_private *dev_priv = dev->dev_private;
11847 struct drm_crtc *crtc = state->base.crtc;
11848 struct intel_crtc *intel_crtc;
11849 struct drm_framebuffer *fb = state->base.fb;
11850 struct drm_rect *dest = &state->dst;
11851 struct drm_rect *src = &state->src;
11852 const struct drm_rect *clip = &state->clip;
11853 int ret;
11854
11855 crtc = crtc ? crtc : plane->crtc;
11856 intel_crtc = to_intel_crtc(crtc);
11857
11858 ret = drm_plane_helper_check_update(plane, crtc, fb,
11859 src, dest, clip,
11860 DRM_PLANE_HELPER_NO_SCALING,
11861 DRM_PLANE_HELPER_NO_SCALING,
11862 false, true, &state->visible);
11863 if (ret)
11864 return ret;
11865
11866 if (intel_crtc->active) {
11867 intel_crtc->atomic.wait_for_flips = true;
11868
11869 /*
11870 * FBC does not work on some platforms for rotated
11871 * planes, so disable it when rotation is not 0 and
11872 * update it when rotation is set back to 0.
11873 *
11874 * FIXME: This is redundant with the fbc update done in
11875 * the primary plane enable function except that that
11876 * one is done too late. We eventually need to unify
11877 * this.
11878 */
11879 if (intel_crtc->primary_enabled &&
11880 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11881 dev_priv->fbc.plane == intel_crtc->plane &&
11882 state->base.rotation != BIT(DRM_ROTATE_0)) {
11883 intel_crtc->atomic.disable_fbc = true;
11884 }
11885
11886 if (state->visible) {
11887 /*
11888 * BDW signals flip done immediately if the plane
11889 * is disabled, even if the plane enable is already
11890 * armed to occur at the next vblank :(
11891 */
11892 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
11893 intel_crtc->atomic.wait_vblank = true;
11894 }
11895
11896 intel_crtc->atomic.fb_bits |=
11897 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
11898
11899 intel_crtc->atomic.update_fbc = true;
11900 }
11901
11902 return 0;
11903 }
11904
11905 static void
11906 intel_commit_primary_plane(struct drm_plane *plane,
11907 struct intel_plane_state *state)
11908 {
11909 struct drm_crtc *crtc = state->base.crtc;
11910 struct drm_framebuffer *fb = state->base.fb;
11911 struct drm_device *dev = plane->dev;
11912 struct drm_i915_private *dev_priv = dev->dev_private;
11913 struct intel_crtc *intel_crtc;
11914 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11915 struct intel_plane *intel_plane = to_intel_plane(plane);
11916 struct drm_rect *src = &state->src;
11917
11918 crtc = crtc ? crtc : plane->crtc;
11919 intel_crtc = to_intel_crtc(crtc);
11920
11921 plane->fb = fb;
11922 crtc->x = src->x1 >> 16;
11923 crtc->y = src->y1 >> 16;
11924
11925 intel_plane->obj = obj;
11926
11927 if (intel_crtc->active) {
11928 if (state->visible) {
11929 /* FIXME: kill this fastboot hack */
11930 intel_update_pipe_size(intel_crtc);
11931
11932 intel_crtc->primary_enabled = true;
11933
11934 dev_priv->display.update_primary_plane(crtc, plane->fb,
11935 crtc->x, crtc->y);
11936 } else {
11937 /*
11938 * If clipping results in a non-visible primary plane,
11939 * we'll disable the primary plane. Note that this is
11940 * a bit different than what happens if userspace
11941 * explicitly disables the plane by passing fb=0
11942 * because plane->fb still gets set and pinned.
11943 */
11944 intel_disable_primary_hw_plane(plane, crtc);
11945 }
11946 }
11947 }
11948
11949 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
11950 {
11951 struct drm_device *dev = crtc->dev;
11952 struct drm_i915_private *dev_priv = dev->dev_private;
11953 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11954 struct intel_plane *intel_plane;
11955 struct drm_plane *p;
11956 unsigned fb_bits = 0;
11957
11958 /* Track fb's for any planes being disabled */
11959 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
11960 intel_plane = to_intel_plane(p);
11961
11962 if (intel_crtc->atomic.disabled_planes &
11963 (1 << drm_plane_index(p))) {
11964 switch (p->type) {
11965 case DRM_PLANE_TYPE_PRIMARY:
11966 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
11967 break;
11968 case DRM_PLANE_TYPE_CURSOR:
11969 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
11970 break;
11971 case DRM_PLANE_TYPE_OVERLAY:
11972 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
11973 break;
11974 }
11975
11976 mutex_lock(&dev->struct_mutex);
11977 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
11978 mutex_unlock(&dev->struct_mutex);
11979 }
11980 }
11981
11982 if (intel_crtc->atomic.wait_for_flips)
11983 intel_crtc_wait_for_pending_flips(crtc);
11984
11985 if (intel_crtc->atomic.disable_fbc)
11986 intel_fbc_disable(dev);
11987
11988 if (intel_crtc->atomic.pre_disable_primary)
11989 intel_pre_disable_primary(crtc);
11990
11991 if (intel_crtc->atomic.update_wm)
11992 intel_update_watermarks(crtc);
11993
11994 intel_runtime_pm_get(dev_priv);
11995
11996 /* Perform vblank evasion around commit operation */
11997 if (intel_crtc->active)
11998 intel_crtc->atomic.evade =
11999 intel_pipe_update_start(intel_crtc,
12000 &intel_crtc->atomic.start_vbl_count);
12001 }
12002
12003 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12004 {
12005 struct drm_device *dev = crtc->dev;
12006 struct drm_i915_private *dev_priv = dev->dev_private;
12007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12008 struct drm_plane *p;
12009
12010 if (intel_crtc->atomic.evade)
12011 intel_pipe_update_end(intel_crtc,
12012 intel_crtc->atomic.start_vbl_count);
12013
12014 intel_runtime_pm_put(dev_priv);
12015
12016 if (intel_crtc->atomic.wait_vblank)
12017 intel_wait_for_vblank(dev, intel_crtc->pipe);
12018
12019 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12020
12021 if (intel_crtc->atomic.update_fbc) {
12022 mutex_lock(&dev->struct_mutex);
12023 intel_fbc_update(dev);
12024 mutex_unlock(&dev->struct_mutex);
12025 }
12026
12027 if (intel_crtc->atomic.post_enable_primary)
12028 intel_post_enable_primary(crtc);
12029
12030 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12031 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12032 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12033 false, false);
12034
12035 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12036 }
12037
12038 /**
12039 * intel_plane_destroy - destroy a plane
12040 * @plane: plane to destroy
12041 *
12042 * Common destruction function for all types of planes (primary, cursor,
12043 * sprite).
12044 */
12045 void intel_plane_destroy(struct drm_plane *plane)
12046 {
12047 struct intel_plane *intel_plane = to_intel_plane(plane);
12048 drm_plane_cleanup(plane);
12049 kfree(intel_plane);
12050 }
12051
12052 const struct drm_plane_funcs intel_plane_funcs = {
12053 .update_plane = drm_plane_helper_update,
12054 .disable_plane = drm_plane_helper_disable,
12055 .destroy = intel_plane_destroy,
12056 .set_property = intel_plane_set_property,
12057 .atomic_get_property = intel_plane_atomic_get_property,
12058 .atomic_set_property = intel_plane_atomic_set_property,
12059 .atomic_duplicate_state = intel_plane_duplicate_state,
12060 .atomic_destroy_state = intel_plane_destroy_state,
12061
12062 };
12063
12064 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12065 int pipe)
12066 {
12067 struct intel_plane *primary;
12068 struct intel_plane_state *state;
12069 const uint32_t *intel_primary_formats;
12070 int num_formats;
12071
12072 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12073 if (primary == NULL)
12074 return NULL;
12075
12076 state = intel_create_plane_state(&primary->base);
12077 if (!state) {
12078 kfree(primary);
12079 return NULL;
12080 }
12081 primary->base.state = &state->base;
12082
12083 primary->can_scale = false;
12084 primary->max_downscale = 1;
12085 primary->pipe = pipe;
12086 primary->plane = pipe;
12087 primary->check_plane = intel_check_primary_plane;
12088 primary->commit_plane = intel_commit_primary_plane;
12089 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12090 primary->plane = !pipe;
12091
12092 if (INTEL_INFO(dev)->gen <= 3) {
12093 intel_primary_formats = intel_primary_formats_gen2;
12094 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12095 } else {
12096 intel_primary_formats = intel_primary_formats_gen4;
12097 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12098 }
12099
12100 drm_universal_plane_init(dev, &primary->base, 0,
12101 &intel_plane_funcs,
12102 intel_primary_formats, num_formats,
12103 DRM_PLANE_TYPE_PRIMARY);
12104
12105 if (INTEL_INFO(dev)->gen >= 4) {
12106 if (!dev->mode_config.rotation_property)
12107 dev->mode_config.rotation_property =
12108 drm_mode_create_rotation_property(dev,
12109 BIT(DRM_ROTATE_0) |
12110 BIT(DRM_ROTATE_180));
12111 if (dev->mode_config.rotation_property)
12112 drm_object_attach_property(&primary->base.base,
12113 dev->mode_config.rotation_property,
12114 state->base.rotation);
12115 }
12116
12117 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12118
12119 return &primary->base;
12120 }
12121
12122 static int
12123 intel_check_cursor_plane(struct drm_plane *plane,
12124 struct intel_plane_state *state)
12125 {
12126 struct drm_crtc *crtc = state->base.crtc;
12127 struct drm_device *dev = plane->dev;
12128 struct drm_framebuffer *fb = state->base.fb;
12129 struct drm_rect *dest = &state->dst;
12130 struct drm_rect *src = &state->src;
12131 const struct drm_rect *clip = &state->clip;
12132 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12133 struct intel_crtc *intel_crtc;
12134 unsigned stride;
12135 int ret;
12136
12137 crtc = crtc ? crtc : plane->crtc;
12138 intel_crtc = to_intel_crtc(crtc);
12139
12140 ret = drm_plane_helper_check_update(plane, crtc, fb,
12141 src, dest, clip,
12142 DRM_PLANE_HELPER_NO_SCALING,
12143 DRM_PLANE_HELPER_NO_SCALING,
12144 true, true, &state->visible);
12145 if (ret)
12146 return ret;
12147
12148
12149 /* if we want to turn off the cursor ignore width and height */
12150 if (!obj)
12151 goto finish;
12152
12153 /* Check for which cursor types we support */
12154 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12155 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12156 state->base.crtc_w, state->base.crtc_h);
12157 return -EINVAL;
12158 }
12159
12160 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12161 if (obj->base.size < stride * state->base.crtc_h) {
12162 DRM_DEBUG_KMS("buffer is too small\n");
12163 return -ENOMEM;
12164 }
12165
12166 if (fb == crtc->cursor->fb)
12167 return 0;
12168
12169 /* we only need to pin inside GTT if cursor is non-phy */
12170 mutex_lock(&dev->struct_mutex);
12171 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
12172 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12173 ret = -EINVAL;
12174 }
12175 mutex_unlock(&dev->struct_mutex);
12176
12177 finish:
12178 if (intel_crtc->active) {
12179 if (intel_crtc->cursor_width != state->base.crtc_w)
12180 intel_crtc->atomic.update_wm = true;
12181
12182 intel_crtc->atomic.fb_bits |=
12183 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12184 }
12185
12186 return ret;
12187 }
12188
12189 static void
12190 intel_commit_cursor_plane(struct drm_plane *plane,
12191 struct intel_plane_state *state)
12192 {
12193 struct drm_crtc *crtc = state->base.crtc;
12194 struct drm_device *dev = plane->dev;
12195 struct intel_crtc *intel_crtc;
12196 struct intel_plane *intel_plane = to_intel_plane(plane);
12197 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12198 uint32_t addr;
12199
12200 crtc = crtc ? crtc : plane->crtc;
12201 intel_crtc = to_intel_crtc(crtc);
12202
12203 plane->fb = state->base.fb;
12204 crtc->cursor_x = state->base.crtc_x;
12205 crtc->cursor_y = state->base.crtc_y;
12206
12207 intel_plane->obj = obj;
12208
12209 if (intel_crtc->cursor_bo == obj)
12210 goto update;
12211
12212 if (!obj)
12213 addr = 0;
12214 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12215 addr = i915_gem_obj_ggtt_offset(obj);
12216 else
12217 addr = obj->phys_handle->busaddr;
12218
12219 intel_crtc->cursor_addr = addr;
12220 intel_crtc->cursor_bo = obj;
12221 update:
12222 intel_crtc->cursor_width = state->base.crtc_w;
12223 intel_crtc->cursor_height = state->base.crtc_h;
12224
12225 if (intel_crtc->active)
12226 intel_crtc_update_cursor(crtc, state->visible);
12227 }
12228
12229 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12230 int pipe)
12231 {
12232 struct intel_plane *cursor;
12233 struct intel_plane_state *state;
12234
12235 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12236 if (cursor == NULL)
12237 return NULL;
12238
12239 state = intel_create_plane_state(&cursor->base);
12240 if (!state) {
12241 kfree(cursor);
12242 return NULL;
12243 }
12244 cursor->base.state = &state->base;
12245
12246 cursor->can_scale = false;
12247 cursor->max_downscale = 1;
12248 cursor->pipe = pipe;
12249 cursor->plane = pipe;
12250 cursor->check_plane = intel_check_cursor_plane;
12251 cursor->commit_plane = intel_commit_cursor_plane;
12252
12253 drm_universal_plane_init(dev, &cursor->base, 0,
12254 &intel_plane_funcs,
12255 intel_cursor_formats,
12256 ARRAY_SIZE(intel_cursor_formats),
12257 DRM_PLANE_TYPE_CURSOR);
12258
12259 if (INTEL_INFO(dev)->gen >= 4) {
12260 if (!dev->mode_config.rotation_property)
12261 dev->mode_config.rotation_property =
12262 drm_mode_create_rotation_property(dev,
12263 BIT(DRM_ROTATE_0) |
12264 BIT(DRM_ROTATE_180));
12265 if (dev->mode_config.rotation_property)
12266 drm_object_attach_property(&cursor->base.base,
12267 dev->mode_config.rotation_property,
12268 state->base.rotation);
12269 }
12270
12271 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12272
12273 return &cursor->base;
12274 }
12275
12276 static void intel_crtc_init(struct drm_device *dev, int pipe)
12277 {
12278 struct drm_i915_private *dev_priv = dev->dev_private;
12279 struct intel_crtc *intel_crtc;
12280 struct intel_crtc_state *crtc_state = NULL;
12281 struct drm_plane *primary = NULL;
12282 struct drm_plane *cursor = NULL;
12283 int i, ret;
12284
12285 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12286 if (intel_crtc == NULL)
12287 return;
12288
12289 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12290 if (!crtc_state)
12291 goto fail;
12292 intel_crtc_set_state(intel_crtc, crtc_state);
12293
12294 primary = intel_primary_plane_create(dev, pipe);
12295 if (!primary)
12296 goto fail;
12297
12298 cursor = intel_cursor_plane_create(dev, pipe);
12299 if (!cursor)
12300 goto fail;
12301
12302 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12303 cursor, &intel_crtc_funcs);
12304 if (ret)
12305 goto fail;
12306
12307 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12308 for (i = 0; i < 256; i++) {
12309 intel_crtc->lut_r[i] = i;
12310 intel_crtc->lut_g[i] = i;
12311 intel_crtc->lut_b[i] = i;
12312 }
12313
12314 /*
12315 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12316 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12317 */
12318 intel_crtc->pipe = pipe;
12319 intel_crtc->plane = pipe;
12320 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12321 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12322 intel_crtc->plane = !pipe;
12323 }
12324
12325 intel_crtc->cursor_base = ~0;
12326 intel_crtc->cursor_cntl = ~0;
12327 intel_crtc->cursor_size = ~0;
12328
12329 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12330 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12331 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12332 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12333
12334 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12335
12336 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12337
12338 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12339 return;
12340
12341 fail:
12342 if (primary)
12343 drm_plane_cleanup(primary);
12344 if (cursor)
12345 drm_plane_cleanup(cursor);
12346 kfree(crtc_state);
12347 kfree(intel_crtc);
12348 }
12349
12350 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12351 {
12352 struct drm_encoder *encoder = connector->base.encoder;
12353 struct drm_device *dev = connector->base.dev;
12354
12355 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12356
12357 if (!encoder || WARN_ON(!encoder->crtc))
12358 return INVALID_PIPE;
12359
12360 return to_intel_crtc(encoder->crtc)->pipe;
12361 }
12362
12363 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12364 struct drm_file *file)
12365 {
12366 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12367 struct drm_crtc *drmmode_crtc;
12368 struct intel_crtc *crtc;
12369
12370 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12371 return -ENODEV;
12372
12373 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12374
12375 if (!drmmode_crtc) {
12376 DRM_ERROR("no such CRTC id\n");
12377 return -ENOENT;
12378 }
12379
12380 crtc = to_intel_crtc(drmmode_crtc);
12381 pipe_from_crtc_id->pipe = crtc->pipe;
12382
12383 return 0;
12384 }
12385
12386 static int intel_encoder_clones(struct intel_encoder *encoder)
12387 {
12388 struct drm_device *dev = encoder->base.dev;
12389 struct intel_encoder *source_encoder;
12390 int index_mask = 0;
12391 int entry = 0;
12392
12393 for_each_intel_encoder(dev, source_encoder) {
12394 if (encoders_cloneable(encoder, source_encoder))
12395 index_mask |= (1 << entry);
12396
12397 entry++;
12398 }
12399
12400 return index_mask;
12401 }
12402
12403 static bool has_edp_a(struct drm_device *dev)
12404 {
12405 struct drm_i915_private *dev_priv = dev->dev_private;
12406
12407 if (!IS_MOBILE(dev))
12408 return false;
12409
12410 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12411 return false;
12412
12413 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12414 return false;
12415
12416 return true;
12417 }
12418
12419 static bool intel_crt_present(struct drm_device *dev)
12420 {
12421 struct drm_i915_private *dev_priv = dev->dev_private;
12422
12423 if (INTEL_INFO(dev)->gen >= 9)
12424 return false;
12425
12426 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12427 return false;
12428
12429 if (IS_CHERRYVIEW(dev))
12430 return false;
12431
12432 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12433 return false;
12434
12435 return true;
12436 }
12437
12438 static void intel_setup_outputs(struct drm_device *dev)
12439 {
12440 struct drm_i915_private *dev_priv = dev->dev_private;
12441 struct intel_encoder *encoder;
12442 bool dpd_is_edp = false;
12443
12444 intel_lvds_init(dev);
12445
12446 if (intel_crt_present(dev))
12447 intel_crt_init(dev);
12448
12449 if (HAS_DDI(dev)) {
12450 int found;
12451
12452 /* Haswell uses DDI functions to detect digital outputs */
12453 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12454 /* DDI A only supports eDP */
12455 if (found)
12456 intel_ddi_init(dev, PORT_A);
12457
12458 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12459 * register */
12460 found = I915_READ(SFUSE_STRAP);
12461
12462 if (found & SFUSE_STRAP_DDIB_DETECTED)
12463 intel_ddi_init(dev, PORT_B);
12464 if (found & SFUSE_STRAP_DDIC_DETECTED)
12465 intel_ddi_init(dev, PORT_C);
12466 if (found & SFUSE_STRAP_DDID_DETECTED)
12467 intel_ddi_init(dev, PORT_D);
12468 } else if (HAS_PCH_SPLIT(dev)) {
12469 int found;
12470 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12471
12472 if (has_edp_a(dev))
12473 intel_dp_init(dev, DP_A, PORT_A);
12474
12475 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12476 /* PCH SDVOB multiplex with HDMIB */
12477 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12478 if (!found)
12479 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12480 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12481 intel_dp_init(dev, PCH_DP_B, PORT_B);
12482 }
12483
12484 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12485 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12486
12487 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12488 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12489
12490 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12491 intel_dp_init(dev, PCH_DP_C, PORT_C);
12492
12493 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12494 intel_dp_init(dev, PCH_DP_D, PORT_D);
12495 } else if (IS_VALLEYVIEW(dev)) {
12496 /*
12497 * The DP_DETECTED bit is the latched state of the DDC
12498 * SDA pin at boot. However since eDP doesn't require DDC
12499 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12500 * eDP ports may have been muxed to an alternate function.
12501 * Thus we can't rely on the DP_DETECTED bit alone to detect
12502 * eDP ports. Consult the VBT as well as DP_DETECTED to
12503 * detect eDP ports.
12504 */
12505 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12506 !intel_dp_is_edp(dev, PORT_B))
12507 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12508 PORT_B);
12509 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12510 intel_dp_is_edp(dev, PORT_B))
12511 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12512
12513 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12514 !intel_dp_is_edp(dev, PORT_C))
12515 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12516 PORT_C);
12517 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12518 intel_dp_is_edp(dev, PORT_C))
12519 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12520
12521 if (IS_CHERRYVIEW(dev)) {
12522 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12523 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12524 PORT_D);
12525 /* eDP not supported on port D, so don't check VBT */
12526 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12527 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12528 }
12529
12530 intel_dsi_init(dev);
12531 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12532 bool found = false;
12533
12534 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12535 DRM_DEBUG_KMS("probing SDVOB\n");
12536 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12537 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12538 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12539 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12540 }
12541
12542 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12543 intel_dp_init(dev, DP_B, PORT_B);
12544 }
12545
12546 /* Before G4X SDVOC doesn't have its own detect register */
12547
12548 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12549 DRM_DEBUG_KMS("probing SDVOC\n");
12550 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12551 }
12552
12553 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12554
12555 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12556 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12557 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12558 }
12559 if (SUPPORTS_INTEGRATED_DP(dev))
12560 intel_dp_init(dev, DP_C, PORT_C);
12561 }
12562
12563 if (SUPPORTS_INTEGRATED_DP(dev) &&
12564 (I915_READ(DP_D) & DP_DETECTED))
12565 intel_dp_init(dev, DP_D, PORT_D);
12566 } else if (IS_GEN2(dev))
12567 intel_dvo_init(dev);
12568
12569 if (SUPPORTS_TV(dev))
12570 intel_tv_init(dev);
12571
12572 intel_psr_init(dev);
12573
12574 for_each_intel_encoder(dev, encoder) {
12575 encoder->base.possible_crtcs = encoder->crtc_mask;
12576 encoder->base.possible_clones =
12577 intel_encoder_clones(encoder);
12578 }
12579
12580 intel_init_pch_refclk(dev);
12581
12582 drm_helper_move_panel_connectors_to_head(dev);
12583 }
12584
12585 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12586 {
12587 struct drm_device *dev = fb->dev;
12588 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12589
12590 drm_framebuffer_cleanup(fb);
12591 mutex_lock(&dev->struct_mutex);
12592 WARN_ON(!intel_fb->obj->framebuffer_references--);
12593 drm_gem_object_unreference(&intel_fb->obj->base);
12594 mutex_unlock(&dev->struct_mutex);
12595 kfree(intel_fb);
12596 }
12597
12598 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12599 struct drm_file *file,
12600 unsigned int *handle)
12601 {
12602 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12603 struct drm_i915_gem_object *obj = intel_fb->obj;
12604
12605 return drm_gem_handle_create(file, &obj->base, handle);
12606 }
12607
12608 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12609 .destroy = intel_user_framebuffer_destroy,
12610 .create_handle = intel_user_framebuffer_create_handle,
12611 };
12612
12613 static int intel_framebuffer_init(struct drm_device *dev,
12614 struct intel_framebuffer *intel_fb,
12615 struct drm_mode_fb_cmd2 *mode_cmd,
12616 struct drm_i915_gem_object *obj)
12617 {
12618 int aligned_height;
12619 int pitch_limit;
12620 int ret;
12621
12622 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12623
12624 if (obj->tiling_mode == I915_TILING_Y) {
12625 DRM_DEBUG("hardware does not support tiling Y\n");
12626 return -EINVAL;
12627 }
12628
12629 if (mode_cmd->pitches[0] & 63) {
12630 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12631 mode_cmd->pitches[0]);
12632 return -EINVAL;
12633 }
12634
12635 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12636 pitch_limit = 32*1024;
12637 } else if (INTEL_INFO(dev)->gen >= 4) {
12638 if (obj->tiling_mode)
12639 pitch_limit = 16*1024;
12640 else
12641 pitch_limit = 32*1024;
12642 } else if (INTEL_INFO(dev)->gen >= 3) {
12643 if (obj->tiling_mode)
12644 pitch_limit = 8*1024;
12645 else
12646 pitch_limit = 16*1024;
12647 } else
12648 /* XXX DSPC is limited to 4k tiled */
12649 pitch_limit = 8*1024;
12650
12651 if (mode_cmd->pitches[0] > pitch_limit) {
12652 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12653 obj->tiling_mode ? "tiled" : "linear",
12654 mode_cmd->pitches[0], pitch_limit);
12655 return -EINVAL;
12656 }
12657
12658 if (obj->tiling_mode != I915_TILING_NONE &&
12659 mode_cmd->pitches[0] != obj->stride) {
12660 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12661 mode_cmd->pitches[0], obj->stride);
12662 return -EINVAL;
12663 }
12664
12665 /* Reject formats not supported by any plane early. */
12666 switch (mode_cmd->pixel_format) {
12667 case DRM_FORMAT_C8:
12668 case DRM_FORMAT_RGB565:
12669 case DRM_FORMAT_XRGB8888:
12670 case DRM_FORMAT_ARGB8888:
12671 break;
12672 case DRM_FORMAT_XRGB1555:
12673 case DRM_FORMAT_ARGB1555:
12674 if (INTEL_INFO(dev)->gen > 3) {
12675 DRM_DEBUG("unsupported pixel format: %s\n",
12676 drm_get_format_name(mode_cmd->pixel_format));
12677 return -EINVAL;
12678 }
12679 break;
12680 case DRM_FORMAT_XBGR8888:
12681 case DRM_FORMAT_ABGR8888:
12682 case DRM_FORMAT_XRGB2101010:
12683 case DRM_FORMAT_ARGB2101010:
12684 case DRM_FORMAT_XBGR2101010:
12685 case DRM_FORMAT_ABGR2101010:
12686 if (INTEL_INFO(dev)->gen < 4) {
12687 DRM_DEBUG("unsupported pixel format: %s\n",
12688 drm_get_format_name(mode_cmd->pixel_format));
12689 return -EINVAL;
12690 }
12691 break;
12692 case DRM_FORMAT_YUYV:
12693 case DRM_FORMAT_UYVY:
12694 case DRM_FORMAT_YVYU:
12695 case DRM_FORMAT_VYUY:
12696 if (INTEL_INFO(dev)->gen < 5) {
12697 DRM_DEBUG("unsupported pixel format: %s\n",
12698 drm_get_format_name(mode_cmd->pixel_format));
12699 return -EINVAL;
12700 }
12701 break;
12702 default:
12703 DRM_DEBUG("unsupported pixel format: %s\n",
12704 drm_get_format_name(mode_cmd->pixel_format));
12705 return -EINVAL;
12706 }
12707
12708 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12709 if (mode_cmd->offsets[0] != 0)
12710 return -EINVAL;
12711
12712 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12713 obj->tiling_mode);
12714 /* FIXME drm helper for size checks (especially planar formats)? */
12715 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12716 return -EINVAL;
12717
12718 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12719 intel_fb->obj = obj;
12720 intel_fb->obj->framebuffer_references++;
12721
12722 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12723 if (ret) {
12724 DRM_ERROR("framebuffer init failed %d\n", ret);
12725 return ret;
12726 }
12727
12728 return 0;
12729 }
12730
12731 static struct drm_framebuffer *
12732 intel_user_framebuffer_create(struct drm_device *dev,
12733 struct drm_file *filp,
12734 struct drm_mode_fb_cmd2 *mode_cmd)
12735 {
12736 struct drm_i915_gem_object *obj;
12737
12738 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12739 mode_cmd->handles[0]));
12740 if (&obj->base == NULL)
12741 return ERR_PTR(-ENOENT);
12742
12743 return intel_framebuffer_create(dev, mode_cmd, obj);
12744 }
12745
12746 #ifndef CONFIG_DRM_I915_FBDEV
12747 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12748 {
12749 }
12750 #endif
12751
12752 static const struct drm_mode_config_funcs intel_mode_funcs = {
12753 .fb_create = intel_user_framebuffer_create,
12754 .output_poll_changed = intel_fbdev_output_poll_changed,
12755 };
12756
12757 /* Set up chip specific display functions */
12758 static void intel_init_display(struct drm_device *dev)
12759 {
12760 struct drm_i915_private *dev_priv = dev->dev_private;
12761
12762 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12763 dev_priv->display.find_dpll = g4x_find_best_dpll;
12764 else if (IS_CHERRYVIEW(dev))
12765 dev_priv->display.find_dpll = chv_find_best_dpll;
12766 else if (IS_VALLEYVIEW(dev))
12767 dev_priv->display.find_dpll = vlv_find_best_dpll;
12768 else if (IS_PINEVIEW(dev))
12769 dev_priv->display.find_dpll = pnv_find_best_dpll;
12770 else
12771 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12772
12773 if (INTEL_INFO(dev)->gen >= 9) {
12774 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12775 dev_priv->display.get_initial_plane_config =
12776 skylake_get_initial_plane_config;
12777 dev_priv->display.crtc_compute_clock =
12778 haswell_crtc_compute_clock;
12779 dev_priv->display.crtc_enable = haswell_crtc_enable;
12780 dev_priv->display.crtc_disable = haswell_crtc_disable;
12781 dev_priv->display.off = ironlake_crtc_off;
12782 dev_priv->display.update_primary_plane =
12783 skylake_update_primary_plane;
12784 } else if (HAS_DDI(dev)) {
12785 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12786 dev_priv->display.get_initial_plane_config =
12787 ironlake_get_initial_plane_config;
12788 dev_priv->display.crtc_compute_clock =
12789 haswell_crtc_compute_clock;
12790 dev_priv->display.crtc_enable = haswell_crtc_enable;
12791 dev_priv->display.crtc_disable = haswell_crtc_disable;
12792 dev_priv->display.off = ironlake_crtc_off;
12793 dev_priv->display.update_primary_plane =
12794 ironlake_update_primary_plane;
12795 } else if (HAS_PCH_SPLIT(dev)) {
12796 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12797 dev_priv->display.get_initial_plane_config =
12798 ironlake_get_initial_plane_config;
12799 dev_priv->display.crtc_compute_clock =
12800 ironlake_crtc_compute_clock;
12801 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12802 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12803 dev_priv->display.off = ironlake_crtc_off;
12804 dev_priv->display.update_primary_plane =
12805 ironlake_update_primary_plane;
12806 } else if (IS_VALLEYVIEW(dev)) {
12807 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12808 dev_priv->display.get_initial_plane_config =
12809 i9xx_get_initial_plane_config;
12810 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12811 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12812 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12813 dev_priv->display.off = i9xx_crtc_off;
12814 dev_priv->display.update_primary_plane =
12815 i9xx_update_primary_plane;
12816 } else {
12817 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12818 dev_priv->display.get_initial_plane_config =
12819 i9xx_get_initial_plane_config;
12820 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12821 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12822 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12823 dev_priv->display.off = i9xx_crtc_off;
12824 dev_priv->display.update_primary_plane =
12825 i9xx_update_primary_plane;
12826 }
12827
12828 /* Returns the core display clock speed */
12829 if (IS_VALLEYVIEW(dev))
12830 dev_priv->display.get_display_clock_speed =
12831 valleyview_get_display_clock_speed;
12832 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12833 dev_priv->display.get_display_clock_speed =
12834 i945_get_display_clock_speed;
12835 else if (IS_I915G(dev))
12836 dev_priv->display.get_display_clock_speed =
12837 i915_get_display_clock_speed;
12838 else if (IS_I945GM(dev) || IS_845G(dev))
12839 dev_priv->display.get_display_clock_speed =
12840 i9xx_misc_get_display_clock_speed;
12841 else if (IS_PINEVIEW(dev))
12842 dev_priv->display.get_display_clock_speed =
12843 pnv_get_display_clock_speed;
12844 else if (IS_I915GM(dev))
12845 dev_priv->display.get_display_clock_speed =
12846 i915gm_get_display_clock_speed;
12847 else if (IS_I865G(dev))
12848 dev_priv->display.get_display_clock_speed =
12849 i865_get_display_clock_speed;
12850 else if (IS_I85X(dev))
12851 dev_priv->display.get_display_clock_speed =
12852 i855_get_display_clock_speed;
12853 else /* 852, 830 */
12854 dev_priv->display.get_display_clock_speed =
12855 i830_get_display_clock_speed;
12856
12857 if (IS_GEN5(dev)) {
12858 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12859 } else if (IS_GEN6(dev)) {
12860 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12861 } else if (IS_IVYBRIDGE(dev)) {
12862 /* FIXME: detect B0+ stepping and use auto training */
12863 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12864 dev_priv->display.modeset_global_resources =
12865 ivb_modeset_global_resources;
12866 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12867 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12868 } else if (IS_VALLEYVIEW(dev)) {
12869 dev_priv->display.modeset_global_resources =
12870 valleyview_modeset_global_resources;
12871 }
12872
12873 /* Default just returns -ENODEV to indicate unsupported */
12874 dev_priv->display.queue_flip = intel_default_queue_flip;
12875
12876 switch (INTEL_INFO(dev)->gen) {
12877 case 2:
12878 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12879 break;
12880
12881 case 3:
12882 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12883 break;
12884
12885 case 4:
12886 case 5:
12887 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12888 break;
12889
12890 case 6:
12891 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12892 break;
12893 case 7:
12894 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12895 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12896 break;
12897 case 9:
12898 dev_priv->display.queue_flip = intel_gen9_queue_flip;
12899 break;
12900 }
12901
12902 intel_panel_init_backlight_funcs(dev);
12903
12904 mutex_init(&dev_priv->pps_mutex);
12905 }
12906
12907 /*
12908 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12909 * resume, or other times. This quirk makes sure that's the case for
12910 * affected systems.
12911 */
12912 static void quirk_pipea_force(struct drm_device *dev)
12913 {
12914 struct drm_i915_private *dev_priv = dev->dev_private;
12915
12916 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12917 DRM_INFO("applying pipe a force quirk\n");
12918 }
12919
12920 static void quirk_pipeb_force(struct drm_device *dev)
12921 {
12922 struct drm_i915_private *dev_priv = dev->dev_private;
12923
12924 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12925 DRM_INFO("applying pipe b force quirk\n");
12926 }
12927
12928 /*
12929 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12930 */
12931 static void quirk_ssc_force_disable(struct drm_device *dev)
12932 {
12933 struct drm_i915_private *dev_priv = dev->dev_private;
12934 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12935 DRM_INFO("applying lvds SSC disable quirk\n");
12936 }
12937
12938 /*
12939 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12940 * brightness value
12941 */
12942 static void quirk_invert_brightness(struct drm_device *dev)
12943 {
12944 struct drm_i915_private *dev_priv = dev->dev_private;
12945 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12946 DRM_INFO("applying inverted panel brightness quirk\n");
12947 }
12948
12949 /* Some VBT's incorrectly indicate no backlight is present */
12950 static void quirk_backlight_present(struct drm_device *dev)
12951 {
12952 struct drm_i915_private *dev_priv = dev->dev_private;
12953 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12954 DRM_INFO("applying backlight present quirk\n");
12955 }
12956
12957 struct intel_quirk {
12958 int device;
12959 int subsystem_vendor;
12960 int subsystem_device;
12961 void (*hook)(struct drm_device *dev);
12962 };
12963
12964 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12965 struct intel_dmi_quirk {
12966 void (*hook)(struct drm_device *dev);
12967 const struct dmi_system_id (*dmi_id_list)[];
12968 };
12969
12970 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12971 {
12972 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12973 return 1;
12974 }
12975
12976 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12977 {
12978 .dmi_id_list = &(const struct dmi_system_id[]) {
12979 {
12980 .callback = intel_dmi_reverse_brightness,
12981 .ident = "NCR Corporation",
12982 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12983 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12984 },
12985 },
12986 { } /* terminating entry */
12987 },
12988 .hook = quirk_invert_brightness,
12989 },
12990 };
12991
12992 static struct intel_quirk intel_quirks[] = {
12993 /* HP Mini needs pipe A force quirk (LP: #322104) */
12994 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12995
12996 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12997 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12998
12999 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13000 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13001
13002 /* 830 needs to leave pipe A & dpll A up */
13003 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13004
13005 /* 830 needs to leave pipe B & dpll B up */
13006 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13007
13008 /* Lenovo U160 cannot use SSC on LVDS */
13009 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13010
13011 /* Sony Vaio Y cannot use SSC on LVDS */
13012 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13013
13014 /* Acer Aspire 5734Z must invert backlight brightness */
13015 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13016
13017 /* Acer/eMachines G725 */
13018 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13019
13020 /* Acer/eMachines e725 */
13021 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13022
13023 /* Acer/Packard Bell NCL20 */
13024 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13025
13026 /* Acer Aspire 4736Z */
13027 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13028
13029 /* Acer Aspire 5336 */
13030 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13031
13032 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13033 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13034
13035 /* Acer C720 Chromebook (Core i3 4005U) */
13036 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13037
13038 /* Apple Macbook 2,1 (Core 2 T7400) */
13039 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13040
13041 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13042 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13043
13044 /* HP Chromebook 14 (Celeron 2955U) */
13045 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13046 };
13047
13048 static void intel_init_quirks(struct drm_device *dev)
13049 {
13050 struct pci_dev *d = dev->pdev;
13051 int i;
13052
13053 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13054 struct intel_quirk *q = &intel_quirks[i];
13055
13056 if (d->device == q->device &&
13057 (d->subsystem_vendor == q->subsystem_vendor ||
13058 q->subsystem_vendor == PCI_ANY_ID) &&
13059 (d->subsystem_device == q->subsystem_device ||
13060 q->subsystem_device == PCI_ANY_ID))
13061 q->hook(dev);
13062 }
13063 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13064 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13065 intel_dmi_quirks[i].hook(dev);
13066 }
13067 }
13068
13069 /* Disable the VGA plane that we never use */
13070 static void i915_disable_vga(struct drm_device *dev)
13071 {
13072 struct drm_i915_private *dev_priv = dev->dev_private;
13073 u8 sr1;
13074 u32 vga_reg = i915_vgacntrl_reg(dev);
13075
13076 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13077 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13078 outb(SR01, VGA_SR_INDEX);
13079 sr1 = inb(VGA_SR_DATA);
13080 outb(sr1 | 1<<5, VGA_SR_DATA);
13081 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13082 udelay(300);
13083
13084 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13085 POSTING_READ(vga_reg);
13086 }
13087
13088 void intel_modeset_init_hw(struct drm_device *dev)
13089 {
13090 intel_prepare_ddi(dev);
13091
13092 if (IS_VALLEYVIEW(dev))
13093 vlv_update_cdclk(dev);
13094
13095 intel_init_clock_gating(dev);
13096
13097 intel_enable_gt_powersave(dev);
13098 }
13099
13100 void intel_modeset_init(struct drm_device *dev)
13101 {
13102 struct drm_i915_private *dev_priv = dev->dev_private;
13103 int sprite, ret;
13104 enum pipe pipe;
13105 struct intel_crtc *crtc;
13106
13107 drm_mode_config_init(dev);
13108
13109 dev->mode_config.min_width = 0;
13110 dev->mode_config.min_height = 0;
13111
13112 dev->mode_config.preferred_depth = 24;
13113 dev->mode_config.prefer_shadow = 1;
13114
13115 dev->mode_config.funcs = &intel_mode_funcs;
13116
13117 intel_init_quirks(dev);
13118
13119 intel_init_pm(dev);
13120
13121 if (INTEL_INFO(dev)->num_pipes == 0)
13122 return;
13123
13124 intel_init_display(dev);
13125 intel_init_audio(dev);
13126
13127 if (IS_GEN2(dev)) {
13128 dev->mode_config.max_width = 2048;
13129 dev->mode_config.max_height = 2048;
13130 } else if (IS_GEN3(dev)) {
13131 dev->mode_config.max_width = 4096;
13132 dev->mode_config.max_height = 4096;
13133 } else {
13134 dev->mode_config.max_width = 8192;
13135 dev->mode_config.max_height = 8192;
13136 }
13137
13138 if (IS_845G(dev) || IS_I865G(dev)) {
13139 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13140 dev->mode_config.cursor_height = 1023;
13141 } else if (IS_GEN2(dev)) {
13142 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13143 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13144 } else {
13145 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13146 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13147 }
13148
13149 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13150
13151 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13152 INTEL_INFO(dev)->num_pipes,
13153 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13154
13155 for_each_pipe(dev_priv, pipe) {
13156 intel_crtc_init(dev, pipe);
13157 for_each_sprite(pipe, sprite) {
13158 ret = intel_plane_init(dev, pipe, sprite);
13159 if (ret)
13160 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13161 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13162 }
13163 }
13164
13165 intel_init_dpio(dev);
13166
13167 intel_shared_dpll_init(dev);
13168
13169 /* Just disable it once at startup */
13170 i915_disable_vga(dev);
13171 intel_setup_outputs(dev);
13172
13173 /* Just in case the BIOS is doing something questionable. */
13174 intel_fbc_disable(dev);
13175
13176 drm_modeset_lock_all(dev);
13177 intel_modeset_setup_hw_state(dev, false);
13178 drm_modeset_unlock_all(dev);
13179
13180 for_each_intel_crtc(dev, crtc) {
13181 if (!crtc->active)
13182 continue;
13183
13184 /*
13185 * Note that reserving the BIOS fb up front prevents us
13186 * from stuffing other stolen allocations like the ring
13187 * on top. This prevents some ugliness at boot time, and
13188 * can even allow for smooth boot transitions if the BIOS
13189 * fb is large enough for the active pipe configuration.
13190 */
13191 if (dev_priv->display.get_initial_plane_config) {
13192 dev_priv->display.get_initial_plane_config(crtc,
13193 &crtc->plane_config);
13194 /*
13195 * If the fb is shared between multiple heads, we'll
13196 * just get the first one.
13197 */
13198 intel_find_plane_obj(crtc, &crtc->plane_config);
13199 }
13200 }
13201 }
13202
13203 static void intel_enable_pipe_a(struct drm_device *dev)
13204 {
13205 struct intel_connector *connector;
13206 struct drm_connector *crt = NULL;
13207 struct intel_load_detect_pipe load_detect_temp;
13208 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13209
13210 /* We can't just switch on the pipe A, we need to set things up with a
13211 * proper mode and output configuration. As a gross hack, enable pipe A
13212 * by enabling the load detect pipe once. */
13213 list_for_each_entry(connector,
13214 &dev->mode_config.connector_list,
13215 base.head) {
13216 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13217 crt = &connector->base;
13218 break;
13219 }
13220 }
13221
13222 if (!crt)
13223 return;
13224
13225 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13226 intel_release_load_detect_pipe(crt, &load_detect_temp);
13227 }
13228
13229 static bool
13230 intel_check_plane_mapping(struct intel_crtc *crtc)
13231 {
13232 struct drm_device *dev = crtc->base.dev;
13233 struct drm_i915_private *dev_priv = dev->dev_private;
13234 u32 reg, val;
13235
13236 if (INTEL_INFO(dev)->num_pipes == 1)
13237 return true;
13238
13239 reg = DSPCNTR(!crtc->plane);
13240 val = I915_READ(reg);
13241
13242 if ((val & DISPLAY_PLANE_ENABLE) &&
13243 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13244 return false;
13245
13246 return true;
13247 }
13248
13249 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13250 {
13251 struct drm_device *dev = crtc->base.dev;
13252 struct drm_i915_private *dev_priv = dev->dev_private;
13253 u32 reg;
13254
13255 /* Clear any frame start delays used for debugging left by the BIOS */
13256 reg = PIPECONF(crtc->config->cpu_transcoder);
13257 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13258
13259 /* restore vblank interrupts to correct state */
13260 if (crtc->active) {
13261 update_scanline_offset(crtc);
13262 drm_vblank_on(dev, crtc->pipe);
13263 } else
13264 drm_vblank_off(dev, crtc->pipe);
13265
13266 /* We need to sanitize the plane -> pipe mapping first because this will
13267 * disable the crtc (and hence change the state) if it is wrong. Note
13268 * that gen4+ has a fixed plane -> pipe mapping. */
13269 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13270 struct intel_connector *connector;
13271 bool plane;
13272
13273 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13274 crtc->base.base.id);
13275
13276 /* Pipe has the wrong plane attached and the plane is active.
13277 * Temporarily change the plane mapping and disable everything
13278 * ... */
13279 plane = crtc->plane;
13280 crtc->plane = !plane;
13281 crtc->primary_enabled = true;
13282 dev_priv->display.crtc_disable(&crtc->base);
13283 crtc->plane = plane;
13284
13285 /* ... and break all links. */
13286 list_for_each_entry(connector, &dev->mode_config.connector_list,
13287 base.head) {
13288 if (connector->encoder->base.crtc != &crtc->base)
13289 continue;
13290
13291 connector->base.dpms = DRM_MODE_DPMS_OFF;
13292 connector->base.encoder = NULL;
13293 }
13294 /* multiple connectors may have the same encoder:
13295 * handle them and break crtc link separately */
13296 list_for_each_entry(connector, &dev->mode_config.connector_list,
13297 base.head)
13298 if (connector->encoder->base.crtc == &crtc->base) {
13299 connector->encoder->base.crtc = NULL;
13300 connector->encoder->connectors_active = false;
13301 }
13302
13303 WARN_ON(crtc->active);
13304 crtc->base.enabled = false;
13305 }
13306
13307 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13308 crtc->pipe == PIPE_A && !crtc->active) {
13309 /* BIOS forgot to enable pipe A, this mostly happens after
13310 * resume. Force-enable the pipe to fix this, the update_dpms
13311 * call below we restore the pipe to the right state, but leave
13312 * the required bits on. */
13313 intel_enable_pipe_a(dev);
13314 }
13315
13316 /* Adjust the state of the output pipe according to whether we
13317 * have active connectors/encoders. */
13318 intel_crtc_update_dpms(&crtc->base);
13319
13320 if (crtc->active != crtc->base.enabled) {
13321 struct intel_encoder *encoder;
13322
13323 /* This can happen either due to bugs in the get_hw_state
13324 * functions or because the pipe is force-enabled due to the
13325 * pipe A quirk. */
13326 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13327 crtc->base.base.id,
13328 crtc->base.enabled ? "enabled" : "disabled",
13329 crtc->active ? "enabled" : "disabled");
13330
13331 crtc->base.enabled = crtc->active;
13332
13333 /* Because we only establish the connector -> encoder ->
13334 * crtc links if something is active, this means the
13335 * crtc is now deactivated. Break the links. connector
13336 * -> encoder links are only establish when things are
13337 * actually up, hence no need to break them. */
13338 WARN_ON(crtc->active);
13339
13340 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13341 WARN_ON(encoder->connectors_active);
13342 encoder->base.crtc = NULL;
13343 }
13344 }
13345
13346 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13347 /*
13348 * We start out with underrun reporting disabled to avoid races.
13349 * For correct bookkeeping mark this on active crtcs.
13350 *
13351 * Also on gmch platforms we dont have any hardware bits to
13352 * disable the underrun reporting. Which means we need to start
13353 * out with underrun reporting disabled also on inactive pipes,
13354 * since otherwise we'll complain about the garbage we read when
13355 * e.g. coming up after runtime pm.
13356 *
13357 * No protection against concurrent access is required - at
13358 * worst a fifo underrun happens which also sets this to false.
13359 */
13360 crtc->cpu_fifo_underrun_disabled = true;
13361 crtc->pch_fifo_underrun_disabled = true;
13362 }
13363 }
13364
13365 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13366 {
13367 struct intel_connector *connector;
13368 struct drm_device *dev = encoder->base.dev;
13369
13370 /* We need to check both for a crtc link (meaning that the
13371 * encoder is active and trying to read from a pipe) and the
13372 * pipe itself being active. */
13373 bool has_active_crtc = encoder->base.crtc &&
13374 to_intel_crtc(encoder->base.crtc)->active;
13375
13376 if (encoder->connectors_active && !has_active_crtc) {
13377 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13378 encoder->base.base.id,
13379 encoder->base.name);
13380
13381 /* Connector is active, but has no active pipe. This is
13382 * fallout from our resume register restoring. Disable
13383 * the encoder manually again. */
13384 if (encoder->base.crtc) {
13385 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13386 encoder->base.base.id,
13387 encoder->base.name);
13388 encoder->disable(encoder);
13389 if (encoder->post_disable)
13390 encoder->post_disable(encoder);
13391 }
13392 encoder->base.crtc = NULL;
13393 encoder->connectors_active = false;
13394
13395 /* Inconsistent output/port/pipe state happens presumably due to
13396 * a bug in one of the get_hw_state functions. Or someplace else
13397 * in our code, like the register restore mess on resume. Clamp
13398 * things to off as a safer default. */
13399 list_for_each_entry(connector,
13400 &dev->mode_config.connector_list,
13401 base.head) {
13402 if (connector->encoder != encoder)
13403 continue;
13404 connector->base.dpms = DRM_MODE_DPMS_OFF;
13405 connector->base.encoder = NULL;
13406 }
13407 }
13408 /* Enabled encoders without active connectors will be fixed in
13409 * the crtc fixup. */
13410 }
13411
13412 void i915_redisable_vga_power_on(struct drm_device *dev)
13413 {
13414 struct drm_i915_private *dev_priv = dev->dev_private;
13415 u32 vga_reg = i915_vgacntrl_reg(dev);
13416
13417 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13418 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13419 i915_disable_vga(dev);
13420 }
13421 }
13422
13423 void i915_redisable_vga(struct drm_device *dev)
13424 {
13425 struct drm_i915_private *dev_priv = dev->dev_private;
13426
13427 /* This function can be called both from intel_modeset_setup_hw_state or
13428 * at a very early point in our resume sequence, where the power well
13429 * structures are not yet restored. Since this function is at a very
13430 * paranoid "someone might have enabled VGA while we were not looking"
13431 * level, just check if the power well is enabled instead of trying to
13432 * follow the "don't touch the power well if we don't need it" policy
13433 * the rest of the driver uses. */
13434 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13435 return;
13436
13437 i915_redisable_vga_power_on(dev);
13438 }
13439
13440 static bool primary_get_hw_state(struct intel_crtc *crtc)
13441 {
13442 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13443
13444 if (!crtc->active)
13445 return false;
13446
13447 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13448 }
13449
13450 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13451 {
13452 struct drm_i915_private *dev_priv = dev->dev_private;
13453 enum pipe pipe;
13454 struct intel_crtc *crtc;
13455 struct intel_encoder *encoder;
13456 struct intel_connector *connector;
13457 int i;
13458
13459 for_each_intel_crtc(dev, crtc) {
13460 memset(crtc->config, 0, sizeof(*crtc->config));
13461
13462 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13463
13464 crtc->active = dev_priv->display.get_pipe_config(crtc,
13465 crtc->config);
13466
13467 crtc->base.enabled = crtc->active;
13468 crtc->primary_enabled = primary_get_hw_state(crtc);
13469
13470 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13471 crtc->base.base.id,
13472 crtc->active ? "enabled" : "disabled");
13473 }
13474
13475 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13476 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13477
13478 pll->on = pll->get_hw_state(dev_priv, pll,
13479 &pll->config.hw_state);
13480 pll->active = 0;
13481 pll->config.crtc_mask = 0;
13482 for_each_intel_crtc(dev, crtc) {
13483 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13484 pll->active++;
13485 pll->config.crtc_mask |= 1 << crtc->pipe;
13486 }
13487 }
13488
13489 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13490 pll->name, pll->config.crtc_mask, pll->on);
13491
13492 if (pll->config.crtc_mask)
13493 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13494 }
13495
13496 for_each_intel_encoder(dev, encoder) {
13497 pipe = 0;
13498
13499 if (encoder->get_hw_state(encoder, &pipe)) {
13500 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13501 encoder->base.crtc = &crtc->base;
13502 encoder->get_config(encoder, crtc->config);
13503 } else {
13504 encoder->base.crtc = NULL;
13505 }
13506
13507 encoder->connectors_active = false;
13508 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13509 encoder->base.base.id,
13510 encoder->base.name,
13511 encoder->base.crtc ? "enabled" : "disabled",
13512 pipe_name(pipe));
13513 }
13514
13515 list_for_each_entry(connector, &dev->mode_config.connector_list,
13516 base.head) {
13517 if (connector->get_hw_state(connector)) {
13518 connector->base.dpms = DRM_MODE_DPMS_ON;
13519 connector->encoder->connectors_active = true;
13520 connector->base.encoder = &connector->encoder->base;
13521 } else {
13522 connector->base.dpms = DRM_MODE_DPMS_OFF;
13523 connector->base.encoder = NULL;
13524 }
13525 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13526 connector->base.base.id,
13527 connector->base.name,
13528 connector->base.encoder ? "enabled" : "disabled");
13529 }
13530 }
13531
13532 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13533 * and i915 state tracking structures. */
13534 void intel_modeset_setup_hw_state(struct drm_device *dev,
13535 bool force_restore)
13536 {
13537 struct drm_i915_private *dev_priv = dev->dev_private;
13538 enum pipe pipe;
13539 struct intel_crtc *crtc;
13540 struct intel_encoder *encoder;
13541 int i;
13542
13543 intel_modeset_readout_hw_state(dev);
13544
13545 /*
13546 * Now that we have the config, copy it to each CRTC struct
13547 * Note that this could go away if we move to using crtc_config
13548 * checking everywhere.
13549 */
13550 for_each_intel_crtc(dev, crtc) {
13551 if (crtc->active && i915.fastboot) {
13552 intel_mode_from_pipe_config(&crtc->base.mode,
13553 crtc->config);
13554 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13555 crtc->base.base.id);
13556 drm_mode_debug_printmodeline(&crtc->base.mode);
13557 }
13558 }
13559
13560 /* HW state is read out, now we need to sanitize this mess. */
13561 for_each_intel_encoder(dev, encoder) {
13562 intel_sanitize_encoder(encoder);
13563 }
13564
13565 for_each_pipe(dev_priv, pipe) {
13566 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13567 intel_sanitize_crtc(crtc);
13568 intel_dump_pipe_config(crtc, crtc->config,
13569 "[setup_hw_state]");
13570 }
13571
13572 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13573 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13574
13575 if (!pll->on || pll->active)
13576 continue;
13577
13578 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13579
13580 pll->disable(dev_priv, pll);
13581 pll->on = false;
13582 }
13583
13584 if (IS_GEN9(dev))
13585 skl_wm_get_hw_state(dev);
13586 else if (HAS_PCH_SPLIT(dev))
13587 ilk_wm_get_hw_state(dev);
13588
13589 if (force_restore) {
13590 i915_redisable_vga(dev);
13591
13592 /*
13593 * We need to use raw interfaces for restoring state to avoid
13594 * checking (bogus) intermediate states.
13595 */
13596 for_each_pipe(dev_priv, pipe) {
13597 struct drm_crtc *crtc =
13598 dev_priv->pipe_to_crtc_mapping[pipe];
13599
13600 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13601 crtc->primary->fb);
13602 }
13603 } else {
13604 intel_modeset_update_staged_output_state(dev);
13605 }
13606
13607 intel_modeset_check_state(dev);
13608 }
13609
13610 void intel_modeset_gem_init(struct drm_device *dev)
13611 {
13612 struct drm_i915_private *dev_priv = dev->dev_private;
13613 struct drm_crtc *c;
13614 struct drm_i915_gem_object *obj;
13615
13616 mutex_lock(&dev->struct_mutex);
13617 intel_init_gt_powersave(dev);
13618 mutex_unlock(&dev->struct_mutex);
13619
13620 /*
13621 * There may be no VBT; and if the BIOS enabled SSC we can
13622 * just keep using it to avoid unnecessary flicker. Whereas if the
13623 * BIOS isn't using it, don't assume it will work even if the VBT
13624 * indicates as much.
13625 */
13626 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13627 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13628 DREF_SSC1_ENABLE);
13629
13630 intel_modeset_init_hw(dev);
13631
13632 intel_setup_overlay(dev);
13633
13634 /*
13635 * Make sure any fbs we allocated at startup are properly
13636 * pinned & fenced. When we do the allocation it's too early
13637 * for this.
13638 */
13639 mutex_lock(&dev->struct_mutex);
13640 for_each_crtc(dev, c) {
13641 obj = intel_fb_obj(c->primary->fb);
13642 if (obj == NULL)
13643 continue;
13644
13645 if (intel_pin_and_fence_fb_obj(c->primary,
13646 c->primary->fb,
13647 NULL)) {
13648 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13649 to_intel_crtc(c)->pipe);
13650 drm_framebuffer_unreference(c->primary->fb);
13651 c->primary->fb = NULL;
13652 }
13653 }
13654 mutex_unlock(&dev->struct_mutex);
13655
13656 intel_backlight_register(dev);
13657 }
13658
13659 void intel_connector_unregister(struct intel_connector *intel_connector)
13660 {
13661 struct drm_connector *connector = &intel_connector->base;
13662
13663 intel_panel_destroy_backlight(connector);
13664 drm_connector_unregister(connector);
13665 }
13666
13667 void intel_modeset_cleanup(struct drm_device *dev)
13668 {
13669 struct drm_i915_private *dev_priv = dev->dev_private;
13670 struct drm_connector *connector;
13671
13672 intel_disable_gt_powersave(dev);
13673
13674 intel_backlight_unregister(dev);
13675
13676 /*
13677 * Interrupts and polling as the first thing to avoid creating havoc.
13678 * Too much stuff here (turning of connectors, ...) would
13679 * experience fancy races otherwise.
13680 */
13681 intel_irq_uninstall(dev_priv);
13682
13683 /*
13684 * Due to the hpd irq storm handling the hotplug work can re-arm the
13685 * poll handlers. Hence disable polling after hpd handling is shut down.
13686 */
13687 drm_kms_helper_poll_fini(dev);
13688
13689 mutex_lock(&dev->struct_mutex);
13690
13691 intel_unregister_dsm_handler();
13692
13693 intel_fbc_disable(dev);
13694
13695 ironlake_teardown_rc6(dev);
13696
13697 mutex_unlock(&dev->struct_mutex);
13698
13699 /* flush any delayed tasks or pending work */
13700 flush_scheduled_work();
13701
13702 /* destroy the backlight and sysfs files before encoders/connectors */
13703 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13704 struct intel_connector *intel_connector;
13705
13706 intel_connector = to_intel_connector(connector);
13707 intel_connector->unregister(intel_connector);
13708 }
13709
13710 drm_mode_config_cleanup(dev);
13711
13712 intel_cleanup_overlay(dev);
13713
13714 mutex_lock(&dev->struct_mutex);
13715 intel_cleanup_gt_powersave(dev);
13716 mutex_unlock(&dev->struct_mutex);
13717 }
13718
13719 /*
13720 * Return which encoder is currently attached for connector.
13721 */
13722 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13723 {
13724 return &intel_attached_encoder(connector)->base;
13725 }
13726
13727 void intel_connector_attach_encoder(struct intel_connector *connector,
13728 struct intel_encoder *encoder)
13729 {
13730 connector->encoder = encoder;
13731 drm_mode_connector_attach_encoder(&connector->base,
13732 &encoder->base);
13733 }
13734
13735 /*
13736 * set vga decode state - true == enable VGA decode
13737 */
13738 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13739 {
13740 struct drm_i915_private *dev_priv = dev->dev_private;
13741 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13742 u16 gmch_ctrl;
13743
13744 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13745 DRM_ERROR("failed to read control word\n");
13746 return -EIO;
13747 }
13748
13749 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13750 return 0;
13751
13752 if (state)
13753 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13754 else
13755 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13756
13757 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13758 DRM_ERROR("failed to write control word\n");
13759 return -EIO;
13760 }
13761
13762 return 0;
13763 }
13764
13765 struct intel_display_error_state {
13766
13767 u32 power_well_driver;
13768
13769 int num_transcoders;
13770
13771 struct intel_cursor_error_state {
13772 u32 control;
13773 u32 position;
13774 u32 base;
13775 u32 size;
13776 } cursor[I915_MAX_PIPES];
13777
13778 struct intel_pipe_error_state {
13779 bool power_domain_on;
13780 u32 source;
13781 u32 stat;
13782 } pipe[I915_MAX_PIPES];
13783
13784 struct intel_plane_error_state {
13785 u32 control;
13786 u32 stride;
13787 u32 size;
13788 u32 pos;
13789 u32 addr;
13790 u32 surface;
13791 u32 tile_offset;
13792 } plane[I915_MAX_PIPES];
13793
13794 struct intel_transcoder_error_state {
13795 bool power_domain_on;
13796 enum transcoder cpu_transcoder;
13797
13798 u32 conf;
13799
13800 u32 htotal;
13801 u32 hblank;
13802 u32 hsync;
13803 u32 vtotal;
13804 u32 vblank;
13805 u32 vsync;
13806 } transcoder[4];
13807 };
13808
13809 struct intel_display_error_state *
13810 intel_display_capture_error_state(struct drm_device *dev)
13811 {
13812 struct drm_i915_private *dev_priv = dev->dev_private;
13813 struct intel_display_error_state *error;
13814 int transcoders[] = {
13815 TRANSCODER_A,
13816 TRANSCODER_B,
13817 TRANSCODER_C,
13818 TRANSCODER_EDP,
13819 };
13820 int i;
13821
13822 if (INTEL_INFO(dev)->num_pipes == 0)
13823 return NULL;
13824
13825 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13826 if (error == NULL)
13827 return NULL;
13828
13829 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13830 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13831
13832 for_each_pipe(dev_priv, i) {
13833 error->pipe[i].power_domain_on =
13834 __intel_display_power_is_enabled(dev_priv,
13835 POWER_DOMAIN_PIPE(i));
13836 if (!error->pipe[i].power_domain_on)
13837 continue;
13838
13839 error->cursor[i].control = I915_READ(CURCNTR(i));
13840 error->cursor[i].position = I915_READ(CURPOS(i));
13841 error->cursor[i].base = I915_READ(CURBASE(i));
13842
13843 error->plane[i].control = I915_READ(DSPCNTR(i));
13844 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13845 if (INTEL_INFO(dev)->gen <= 3) {
13846 error->plane[i].size = I915_READ(DSPSIZE(i));
13847 error->plane[i].pos = I915_READ(DSPPOS(i));
13848 }
13849 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13850 error->plane[i].addr = I915_READ(DSPADDR(i));
13851 if (INTEL_INFO(dev)->gen >= 4) {
13852 error->plane[i].surface = I915_READ(DSPSURF(i));
13853 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13854 }
13855
13856 error->pipe[i].source = I915_READ(PIPESRC(i));
13857
13858 if (HAS_GMCH_DISPLAY(dev))
13859 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13860 }
13861
13862 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13863 if (HAS_DDI(dev_priv->dev))
13864 error->num_transcoders++; /* Account for eDP. */
13865
13866 for (i = 0; i < error->num_transcoders; i++) {
13867 enum transcoder cpu_transcoder = transcoders[i];
13868
13869 error->transcoder[i].power_domain_on =
13870 __intel_display_power_is_enabled(dev_priv,
13871 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13872 if (!error->transcoder[i].power_domain_on)
13873 continue;
13874
13875 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13876
13877 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13878 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13879 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13880 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13881 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13882 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13883 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13884 }
13885
13886 return error;
13887 }
13888
13889 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13890
13891 void
13892 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13893 struct drm_device *dev,
13894 struct intel_display_error_state *error)
13895 {
13896 struct drm_i915_private *dev_priv = dev->dev_private;
13897 int i;
13898
13899 if (!error)
13900 return;
13901
13902 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13903 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13904 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13905 error->power_well_driver);
13906 for_each_pipe(dev_priv, i) {
13907 err_printf(m, "Pipe [%d]:\n", i);
13908 err_printf(m, " Power: %s\n",
13909 error->pipe[i].power_domain_on ? "on" : "off");
13910 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13911 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13912
13913 err_printf(m, "Plane [%d]:\n", i);
13914 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13915 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13916 if (INTEL_INFO(dev)->gen <= 3) {
13917 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13918 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13919 }
13920 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13921 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13922 if (INTEL_INFO(dev)->gen >= 4) {
13923 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13924 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13925 }
13926
13927 err_printf(m, "Cursor [%d]:\n", i);
13928 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13929 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13930 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13931 }
13932
13933 for (i = 0; i < error->num_transcoders; i++) {
13934 err_printf(m, "CPU transcoder: %c\n",
13935 transcoder_name(error->transcoder[i].cpu_transcoder));
13936 err_printf(m, " Power: %s\n",
13937 error->transcoder[i].power_domain_on ? "on" : "off");
13938 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13939 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13940 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13941 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13942 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13943 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13944 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13945 }
13946 }
13947
13948 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13949 {
13950 struct intel_crtc *crtc;
13951
13952 for_each_intel_crtc(dev, crtc) {
13953 struct intel_unpin_work *work;
13954
13955 spin_lock_irq(&dev->event_lock);
13956
13957 work = crtc->unpin_work;
13958
13959 if (work && work->event &&
13960 work->event->base.file_priv == file) {
13961 kfree(work->event);
13962 work->event = NULL;
13963 }
13964
13965 spin_unlock_irq(&dev->event_lock);
13966 }
13967 }
Linux kernel - Deliverables
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