2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
78 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
79 struct intel_crtc_config
*pipe_config
);
80 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_config
*pipe_config
);
83 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
84 int x
, int y
, struct drm_framebuffer
*old_fb
);
85 static int intel_framebuffer_init(struct drm_device
*dev
,
86 struct intel_framebuffer
*ifb
,
87 struct drm_mode_fb_cmd2
*mode_cmd
,
88 struct drm_i915_gem_object
*obj
);
89 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
90 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
92 struct intel_link_m_n
*m_n
,
93 struct intel_link_m_n
*m2_n2
);
94 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
95 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
96 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
97 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
98 const struct intel_crtc_config
*pipe_config
);
99 static void chv_prepare_pll(struct intel_crtc
*crtc
,
100 const struct intel_crtc_config
*pipe_config
);
102 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
104 if (!connector
->mst_port
)
105 return connector
->encoder
;
107 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
116 int p2_slow
, p2_fast
;
119 typedef struct intel_limit intel_limit_t
;
121 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
126 intel_pch_rawclk(struct drm_device
*dev
)
128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
130 WARN_ON(!HAS_PCH_SPLIT(dev
));
132 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
135 static inline u32
/* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device
*dev
)
139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
140 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
145 static const intel_limit_t intel_limits_i8xx_dac
= {
146 .dot
= { .min
= 25000, .max
= 350000 },
147 .vco
= { .min
= 908000, .max
= 1512000 },
148 .n
= { .min
= 2, .max
= 16 },
149 .m
= { .min
= 96, .max
= 140 },
150 .m1
= { .min
= 18, .max
= 26 },
151 .m2
= { .min
= 6, .max
= 16 },
152 .p
= { .min
= 4, .max
= 128 },
153 .p1
= { .min
= 2, .max
= 33 },
154 .p2
= { .dot_limit
= 165000,
155 .p2_slow
= 4, .p2_fast
= 2 },
158 static const intel_limit_t intel_limits_i8xx_dvo
= {
159 .dot
= { .min
= 25000, .max
= 350000 },
160 .vco
= { .min
= 908000, .max
= 1512000 },
161 .n
= { .min
= 2, .max
= 16 },
162 .m
= { .min
= 96, .max
= 140 },
163 .m1
= { .min
= 18, .max
= 26 },
164 .m2
= { .min
= 6, .max
= 16 },
165 .p
= { .min
= 4, .max
= 128 },
166 .p1
= { .min
= 2, .max
= 33 },
167 .p2
= { .dot_limit
= 165000,
168 .p2_slow
= 4, .p2_fast
= 4 },
171 static const intel_limit_t intel_limits_i8xx_lvds
= {
172 .dot
= { .min
= 25000, .max
= 350000 },
173 .vco
= { .min
= 908000, .max
= 1512000 },
174 .n
= { .min
= 2, .max
= 16 },
175 .m
= { .min
= 96, .max
= 140 },
176 .m1
= { .min
= 18, .max
= 26 },
177 .m2
= { .min
= 6, .max
= 16 },
178 .p
= { .min
= 4, .max
= 128 },
179 .p1
= { .min
= 1, .max
= 6 },
180 .p2
= { .dot_limit
= 165000,
181 .p2_slow
= 14, .p2_fast
= 7 },
184 static const intel_limit_t intel_limits_i9xx_sdvo
= {
185 .dot
= { .min
= 20000, .max
= 400000 },
186 .vco
= { .min
= 1400000, .max
= 2800000 },
187 .n
= { .min
= 1, .max
= 6 },
188 .m
= { .min
= 70, .max
= 120 },
189 .m1
= { .min
= 8, .max
= 18 },
190 .m2
= { .min
= 3, .max
= 7 },
191 .p
= { .min
= 5, .max
= 80 },
192 .p1
= { .min
= 1, .max
= 8 },
193 .p2
= { .dot_limit
= 200000,
194 .p2_slow
= 10, .p2_fast
= 5 },
197 static const intel_limit_t intel_limits_i9xx_lvds
= {
198 .dot
= { .min
= 20000, .max
= 400000 },
199 .vco
= { .min
= 1400000, .max
= 2800000 },
200 .n
= { .min
= 1, .max
= 6 },
201 .m
= { .min
= 70, .max
= 120 },
202 .m1
= { .min
= 8, .max
= 18 },
203 .m2
= { .min
= 3, .max
= 7 },
204 .p
= { .min
= 7, .max
= 98 },
205 .p1
= { .min
= 1, .max
= 8 },
206 .p2
= { .dot_limit
= 112000,
207 .p2_slow
= 14, .p2_fast
= 7 },
211 static const intel_limit_t intel_limits_g4x_sdvo
= {
212 .dot
= { .min
= 25000, .max
= 270000 },
213 .vco
= { .min
= 1750000, .max
= 3500000},
214 .n
= { .min
= 1, .max
= 4 },
215 .m
= { .min
= 104, .max
= 138 },
216 .m1
= { .min
= 17, .max
= 23 },
217 .m2
= { .min
= 5, .max
= 11 },
218 .p
= { .min
= 10, .max
= 30 },
219 .p1
= { .min
= 1, .max
= 3},
220 .p2
= { .dot_limit
= 270000,
226 static const intel_limit_t intel_limits_g4x_hdmi
= {
227 .dot
= { .min
= 22000, .max
= 400000 },
228 .vco
= { .min
= 1750000, .max
= 3500000},
229 .n
= { .min
= 1, .max
= 4 },
230 .m
= { .min
= 104, .max
= 138 },
231 .m1
= { .min
= 16, .max
= 23 },
232 .m2
= { .min
= 5, .max
= 11 },
233 .p
= { .min
= 5, .max
= 80 },
234 .p1
= { .min
= 1, .max
= 8},
235 .p2
= { .dot_limit
= 165000,
236 .p2_slow
= 10, .p2_fast
= 5 },
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
240 .dot
= { .min
= 20000, .max
= 115000 },
241 .vco
= { .min
= 1750000, .max
= 3500000 },
242 .n
= { .min
= 1, .max
= 3 },
243 .m
= { .min
= 104, .max
= 138 },
244 .m1
= { .min
= 17, .max
= 23 },
245 .m2
= { .min
= 5, .max
= 11 },
246 .p
= { .min
= 28, .max
= 112 },
247 .p1
= { .min
= 2, .max
= 8 },
248 .p2
= { .dot_limit
= 0,
249 .p2_slow
= 14, .p2_fast
= 14
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
254 .dot
= { .min
= 80000, .max
= 224000 },
255 .vco
= { .min
= 1750000, .max
= 3500000 },
256 .n
= { .min
= 1, .max
= 3 },
257 .m
= { .min
= 104, .max
= 138 },
258 .m1
= { .min
= 17, .max
= 23 },
259 .m2
= { .min
= 5, .max
= 11 },
260 .p
= { .min
= 14, .max
= 42 },
261 .p1
= { .min
= 2, .max
= 6 },
262 .p2
= { .dot_limit
= 0,
263 .p2_slow
= 7, .p2_fast
= 7
267 static const intel_limit_t intel_limits_pineview_sdvo
= {
268 .dot
= { .min
= 20000, .max
= 400000},
269 .vco
= { .min
= 1700000, .max
= 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n
= { .min
= 3, .max
= 6 },
272 .m
= { .min
= 2, .max
= 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1
= { .min
= 0, .max
= 0 },
275 .m2
= { .min
= 0, .max
= 254 },
276 .p
= { .min
= 5, .max
= 80 },
277 .p1
= { .min
= 1, .max
= 8 },
278 .p2
= { .dot_limit
= 200000,
279 .p2_slow
= 10, .p2_fast
= 5 },
282 static const intel_limit_t intel_limits_pineview_lvds
= {
283 .dot
= { .min
= 20000, .max
= 400000 },
284 .vco
= { .min
= 1700000, .max
= 3500000 },
285 .n
= { .min
= 3, .max
= 6 },
286 .m
= { .min
= 2, .max
= 256 },
287 .m1
= { .min
= 0, .max
= 0 },
288 .m2
= { .min
= 0, .max
= 254 },
289 .p
= { .min
= 7, .max
= 112 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 112000,
292 .p2_slow
= 14, .p2_fast
= 14 },
295 /* Ironlake / Sandybridge
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
300 static const intel_limit_t intel_limits_ironlake_dac
= {
301 .dot
= { .min
= 25000, .max
= 350000 },
302 .vco
= { .min
= 1760000, .max
= 3510000 },
303 .n
= { .min
= 1, .max
= 5 },
304 .m
= { .min
= 79, .max
= 127 },
305 .m1
= { .min
= 12, .max
= 22 },
306 .m2
= { .min
= 5, .max
= 9 },
307 .p
= { .min
= 5, .max
= 80 },
308 .p1
= { .min
= 1, .max
= 8 },
309 .p2
= { .dot_limit
= 225000,
310 .p2_slow
= 10, .p2_fast
= 5 },
313 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
314 .dot
= { .min
= 25000, .max
= 350000 },
315 .vco
= { .min
= 1760000, .max
= 3510000 },
316 .n
= { .min
= 1, .max
= 3 },
317 .m
= { .min
= 79, .max
= 118 },
318 .m1
= { .min
= 12, .max
= 22 },
319 .m2
= { .min
= 5, .max
= 9 },
320 .p
= { .min
= 28, .max
= 112 },
321 .p1
= { .min
= 2, .max
= 8 },
322 .p2
= { .dot_limit
= 225000,
323 .p2_slow
= 14, .p2_fast
= 14 },
326 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
327 .dot
= { .min
= 25000, .max
= 350000 },
328 .vco
= { .min
= 1760000, .max
= 3510000 },
329 .n
= { .min
= 1, .max
= 3 },
330 .m
= { .min
= 79, .max
= 127 },
331 .m1
= { .min
= 12, .max
= 22 },
332 .m2
= { .min
= 5, .max
= 9 },
333 .p
= { .min
= 14, .max
= 56 },
334 .p1
= { .min
= 2, .max
= 8 },
335 .p2
= { .dot_limit
= 225000,
336 .p2_slow
= 7, .p2_fast
= 7 },
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
341 .dot
= { .min
= 25000, .max
= 350000 },
342 .vco
= { .min
= 1760000, .max
= 3510000 },
343 .n
= { .min
= 1, .max
= 2 },
344 .m
= { .min
= 79, .max
= 126 },
345 .m1
= { .min
= 12, .max
= 22 },
346 .m2
= { .min
= 5, .max
= 9 },
347 .p
= { .min
= 28, .max
= 112 },
348 .p1
= { .min
= 2, .max
= 8 },
349 .p2
= { .dot_limit
= 225000,
350 .p2_slow
= 14, .p2_fast
= 14 },
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000 },
356 .n
= { .min
= 1, .max
= 3 },
357 .m
= { .min
= 79, .max
= 126 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 14, .max
= 42 },
361 .p1
= { .min
= 2, .max
= 6 },
362 .p2
= { .dot_limit
= 225000,
363 .p2_slow
= 7, .p2_fast
= 7 },
366 static const intel_limit_t intel_limits_vlv
= {
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
373 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
374 .vco
= { .min
= 4000000, .max
= 6000000 },
375 .n
= { .min
= 1, .max
= 7 },
376 .m1
= { .min
= 2, .max
= 3 },
377 .m2
= { .min
= 11, .max
= 156 },
378 .p1
= { .min
= 2, .max
= 3 },
379 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
382 static const intel_limit_t intel_limits_chv
= {
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
389 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
390 .vco
= { .min
= 4860000, .max
= 6700000 },
391 .n
= { .min
= 1, .max
= 1 },
392 .m1
= { .min
= 2, .max
= 2 },
393 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
394 .p1
= { .min
= 2, .max
= 4 },
395 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
398 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
400 clock
->m
= clock
->m1
* clock
->m2
;
401 clock
->p
= clock
->p1
* clock
->p2
;
402 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
404 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
405 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
409 * Returns whether any output on the specified pipe is of the specified type
411 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
413 struct drm_device
*dev
= crtc
->base
.dev
;
414 struct intel_encoder
*encoder
;
416 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
417 if (encoder
->type
== type
)
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
429 static bool intel_pipe_will_have_type(struct intel_crtc
*crtc
, int type
)
431 struct drm_device
*dev
= crtc
->base
.dev
;
432 struct intel_encoder
*encoder
;
434 for_each_intel_encoder(dev
, encoder
)
435 if (encoder
->new_crtc
== crtc
&& encoder
->type
== type
)
441 static const intel_limit_t
*intel_ironlake_limit(struct intel_crtc
*crtc
,
444 struct drm_device
*dev
= crtc
->base
.dev
;
445 const intel_limit_t
*limit
;
447 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
448 if (intel_is_dual_link_lvds(dev
)) {
449 if (refclk
== 100000)
450 limit
= &intel_limits_ironlake_dual_lvds_100m
;
452 limit
= &intel_limits_ironlake_dual_lvds
;
454 if (refclk
== 100000)
455 limit
= &intel_limits_ironlake_single_lvds_100m
;
457 limit
= &intel_limits_ironlake_single_lvds
;
460 limit
= &intel_limits_ironlake_dac
;
465 static const intel_limit_t
*intel_g4x_limit(struct intel_crtc
*crtc
)
467 struct drm_device
*dev
= crtc
->base
.dev
;
468 const intel_limit_t
*limit
;
470 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
471 if (intel_is_dual_link_lvds(dev
))
472 limit
= &intel_limits_g4x_dual_channel_lvds
;
474 limit
= &intel_limits_g4x_single_channel_lvds
;
475 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
) ||
476 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
477 limit
= &intel_limits_g4x_hdmi
;
478 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
)) {
479 limit
= &intel_limits_g4x_sdvo
;
480 } else /* The option is for other outputs */
481 limit
= &intel_limits_i9xx_sdvo
;
486 static const intel_limit_t
*intel_limit(struct intel_crtc
*crtc
, int refclk
)
488 struct drm_device
*dev
= crtc
->base
.dev
;
489 const intel_limit_t
*limit
;
491 if (HAS_PCH_SPLIT(dev
))
492 limit
= intel_ironlake_limit(crtc
, refclk
);
493 else if (IS_G4X(dev
)) {
494 limit
= intel_g4x_limit(crtc
);
495 } else if (IS_PINEVIEW(dev
)) {
496 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
497 limit
= &intel_limits_pineview_lvds
;
499 limit
= &intel_limits_pineview_sdvo
;
500 } else if (IS_CHERRYVIEW(dev
)) {
501 limit
= &intel_limits_chv
;
502 } else if (IS_VALLEYVIEW(dev
)) {
503 limit
= &intel_limits_vlv
;
504 } else if (!IS_GEN2(dev
)) {
505 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
506 limit
= &intel_limits_i9xx_lvds
;
508 limit
= &intel_limits_i9xx_sdvo
;
510 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
511 limit
= &intel_limits_i8xx_lvds
;
512 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
513 limit
= &intel_limits_i8xx_dvo
;
515 limit
= &intel_limits_i8xx_dac
;
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= clock
->m2
+ 2;
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
533 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
536 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
538 clock
->m
= i9xx_dpll_compute_m(clock
);
539 clock
->p
= clock
->p1
* clock
->p2
;
540 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
542 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
543 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
546 static void chv_clock(int refclk
, intel_clock_t
*clock
)
548 clock
->m
= clock
->m1
* clock
->m2
;
549 clock
->p
= clock
->p1
* clock
->p2
;
550 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
552 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
554 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
563 static bool intel_PLL_is_valid(struct drm_device
*dev
,
564 const intel_limit_t
*limit
,
565 const intel_clock_t
*clock
)
567 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
568 INTELPllInvalid("n out of range\n");
569 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
574 INTELPllInvalid("m1 out of range\n");
576 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
577 if (clock
->m1
<= clock
->m2
)
578 INTELPllInvalid("m1 <= m2\n");
580 if (!IS_VALLEYVIEW(dev
)) {
581 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
582 INTELPllInvalid("p out of range\n");
583 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
584 INTELPllInvalid("m out of range\n");
587 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
592 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
593 INTELPllInvalid("dot out of range\n");
599 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
600 int target
, int refclk
, intel_clock_t
*match_clock
,
601 intel_clock_t
*best_clock
)
603 struct drm_device
*dev
= crtc
->base
.dev
;
607 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
613 if (intel_is_dual_link_lvds(dev
))
614 clock
.p2
= limit
->p2
.p2_fast
;
616 clock
.p2
= limit
->p2
.p2_slow
;
618 if (target
< limit
->p2
.dot_limit
)
619 clock
.p2
= limit
->p2
.p2_slow
;
621 clock
.p2
= limit
->p2
.p2_fast
;
624 memset(best_clock
, 0, sizeof(*best_clock
));
626 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
628 for (clock
.m2
= limit
->m2
.min
;
629 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
630 if (clock
.m2
>= clock
.m1
)
632 for (clock
.n
= limit
->n
.min
;
633 clock
.n
<= limit
->n
.max
; clock
.n
++) {
634 for (clock
.p1
= limit
->p1
.min
;
635 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
638 i9xx_clock(refclk
, &clock
);
639 if (!intel_PLL_is_valid(dev
, limit
,
643 clock
.p
!= match_clock
->p
)
646 this_err
= abs(clock
.dot
- target
);
647 if (this_err
< err
) {
656 return (err
!= target
);
660 pnv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
661 int target
, int refclk
, intel_clock_t
*match_clock
,
662 intel_clock_t
*best_clock
)
664 struct drm_device
*dev
= crtc
->base
.dev
;
668 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
674 if (intel_is_dual_link_lvds(dev
))
675 clock
.p2
= limit
->p2
.p2_fast
;
677 clock
.p2
= limit
->p2
.p2_slow
;
679 if (target
< limit
->p2
.dot_limit
)
680 clock
.p2
= limit
->p2
.p2_slow
;
682 clock
.p2
= limit
->p2
.p2_fast
;
685 memset(best_clock
, 0, sizeof(*best_clock
));
687 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
689 for (clock
.m2
= limit
->m2
.min
;
690 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
691 for (clock
.n
= limit
->n
.min
;
692 clock
.n
<= limit
->n
.max
; clock
.n
++) {
693 for (clock
.p1
= limit
->p1
.min
;
694 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
697 pineview_clock(refclk
, &clock
);
698 if (!intel_PLL_is_valid(dev
, limit
,
702 clock
.p
!= match_clock
->p
)
705 this_err
= abs(clock
.dot
- target
);
706 if (this_err
< err
) {
715 return (err
!= target
);
719 g4x_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
720 int target
, int refclk
, intel_clock_t
*match_clock
,
721 intel_clock_t
*best_clock
)
723 struct drm_device
*dev
= crtc
->base
.dev
;
727 /* approximately equals target * 0.00585 */
728 int err_most
= (target
>> 8) + (target
>> 9);
731 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
732 if (intel_is_dual_link_lvds(dev
))
733 clock
.p2
= limit
->p2
.p2_fast
;
735 clock
.p2
= limit
->p2
.p2_slow
;
737 if (target
< limit
->p2
.dot_limit
)
738 clock
.p2
= limit
->p2
.p2_slow
;
740 clock
.p2
= limit
->p2
.p2_fast
;
743 memset(best_clock
, 0, sizeof(*best_clock
));
744 max_n
= limit
->n
.max
;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock
.m1
= limit
->m1
.max
;
749 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
750 for (clock
.m2
= limit
->m2
.max
;
751 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
752 for (clock
.p1
= limit
->p1
.max
;
753 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
756 i9xx_clock(refclk
, &clock
);
757 if (!intel_PLL_is_valid(dev
, limit
,
761 this_err
= abs(clock
.dot
- target
);
762 if (this_err
< err_most
) {
776 vlv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
777 int target
, int refclk
, intel_clock_t
*match_clock
,
778 intel_clock_t
*best_clock
)
780 struct drm_device
*dev
= crtc
->base
.dev
;
782 unsigned int bestppm
= 1000000;
783 /* min update 19.2 MHz */
784 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
787 target
*= 5; /* fast clock */
789 memset(best_clock
, 0, sizeof(*best_clock
));
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
793 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
794 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
795 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
796 clock
.p
= clock
.p1
* clock
.p2
;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
799 unsigned int ppm
, diff
;
801 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
804 vlv_clock(refclk
, &clock
);
806 if (!intel_PLL_is_valid(dev
, limit
,
810 diff
= abs(clock
.dot
- target
);
811 ppm
= div_u64(1000000ULL * diff
, target
);
813 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
819 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
833 chv_find_best_dpll(const intel_limit_t
*limit
, struct intel_crtc
*crtc
,
834 int target
, int refclk
, intel_clock_t
*match_clock
,
835 intel_clock_t
*best_clock
)
837 struct drm_device
*dev
= crtc
->base
.dev
;
842 memset(best_clock
, 0, sizeof(*best_clock
));
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
849 clock
.n
= 1, clock
.m1
= 2;
850 target
*= 5; /* fast clock */
852 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
853 for (clock
.p2
= limit
->p2
.p2_fast
;
854 clock
.p2
>= limit
->p2
.p2_slow
;
855 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
857 clock
.p
= clock
.p1
* clock
.p2
;
859 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
860 clock
.n
) << 22, refclk
* clock
.m1
);
862 if (m2
> INT_MAX
/clock
.m1
)
867 chv_clock(refclk
, &clock
);
869 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
872 /* based on hardware requirement, prefer bigger p
874 if (clock
.p
> best_clock
->p
) {
884 bool intel_crtc_active(struct drm_crtc
*crtc
)
886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
897 return intel_crtc
->active
&& crtc
->primary
->fb
&&
898 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
901 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
904 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
907 return intel_crtc
->config
.cpu_transcoder
;
910 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
913 u32 reg
= PIPEDSL(pipe
);
918 line_mask
= DSL_LINEMASK_GEN2
;
920 line_mask
= DSL_LINEMASK_GEN3
;
922 line1
= I915_READ(reg
) & line_mask
;
924 line2
= I915_READ(reg
) & line_mask
;
926 return line1
== line2
;
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
938 * wait for the pipe register state bit to turn off
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
945 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
947 struct drm_device
*dev
= crtc
->base
.dev
;
948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
949 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
950 enum pipe pipe
= crtc
->pipe
;
952 if (INTEL_INFO(dev
)->gen
>= 4) {
953 int reg
= PIPECONF(cpu_transcoder
);
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
958 WARN(1, "pipe_off wait timed out\n");
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
962 WARN(1, "pipe_off wait timed out\n");
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
971 * Returns true if @port is connected, false otherwise.
973 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
974 struct intel_digital_port
*port
)
978 if (HAS_PCH_IBX(dev_priv
->dev
)) {
979 switch (port
->port
) {
981 bit
= SDE_PORTB_HOTPLUG
;
984 bit
= SDE_PORTC_HOTPLUG
;
987 bit
= SDE_PORTD_HOTPLUG
;
993 switch (port
->port
) {
995 bit
= SDE_PORTB_HOTPLUG_CPT
;
998 bit
= SDE_PORTC_HOTPLUG_CPT
;
1001 bit
= SDE_PORTD_HOTPLUG_CPT
;
1008 return I915_READ(SDEISR
) & bit
;
1011 static const char *state_string(bool enabled
)
1013 return enabled
? "on" : "off";
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private
*dev_priv
,
1018 enum pipe pipe
, bool state
)
1025 val
= I915_READ(reg
);
1026 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1027 WARN(cur_state
!= state
,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state
), state_string(cur_state
));
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1038 mutex_lock(&dev_priv
->dpio_lock
);
1039 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1040 mutex_unlock(&dev_priv
->dpio_lock
);
1042 cur_state
= val
& DSI_PLL_VCO_EN
;
1043 WARN(cur_state
!= state
,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state
), state_string(cur_state
));
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1050 struct intel_shared_dpll
*
1051 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1053 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1055 if (crtc
->config
.shared_dpll
< 0)
1058 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1062 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1063 struct intel_shared_dpll
*pll
,
1067 struct intel_dpll_hw_state hw_state
;
1070 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1073 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1074 WARN(cur_state
!= state
,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll
->name
, state_string(state
), state_string(cur_state
));
1079 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1080 enum pipe pipe
, bool state
)
1085 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1088 if (HAS_DDI(dev_priv
->dev
)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1091 val
= I915_READ(reg
);
1092 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1094 reg
= FDI_TX_CTL(pipe
);
1095 val
= I915_READ(reg
);
1096 cur_state
= !!(val
& FDI_TX_ENABLE
);
1098 WARN(cur_state
!= state
,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state
), state_string(cur_state
));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1106 enum pipe pipe
, bool state
)
1112 reg
= FDI_RX_CTL(pipe
);
1113 val
= I915_READ(reg
);
1114 cur_state
= !!(val
& FDI_RX_ENABLE
);
1115 WARN(cur_state
!= state
,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state
), state_string(cur_state
));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv
->dev
))
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1156 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1159 struct drm_device
*dev
= dev_priv
->dev
;
1162 enum pipe panel_pipe
= PIPE_A
;
1165 if (WARN_ON(HAS_DDI(dev
)))
1168 if (HAS_PCH_SPLIT(dev
)) {
1171 pp_reg
= PCH_PP_CONTROL
;
1172 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1174 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1175 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1176 panel_pipe
= PIPE_B
;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev
)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1183 pp_reg
= PP_CONTROL
;
1184 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1185 panel_pipe
= PIPE_B
;
1188 val
= I915_READ(pp_reg
);
1189 if (!(val
& PANEL_POWER_ON
) ||
1190 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1193 WARN(panel_pipe
== pipe
&& locked
,
1194 "panel assertion failure, pipe %c regs locked\n",
1198 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1199 enum pipe pipe
, bool state
)
1201 struct drm_device
*dev
= dev_priv
->dev
;
1204 if (IS_845G(dev
) || IS_I865G(dev
))
1205 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1207 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1209 WARN(cur_state
!= state
,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1216 void assert_pipe(struct drm_i915_private
*dev_priv
,
1217 enum pipe pipe
, bool state
)
1222 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1227 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1230 if (!intel_display_power_is_enabled(dev_priv
,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1239 WARN(cur_state
!= state
,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1244 static void assert_plane(struct drm_i915_private
*dev_priv
,
1245 enum plane plane
, bool state
)
1251 reg
= DSPCNTR(plane
);
1252 val
= I915_READ(reg
);
1253 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1254 WARN(cur_state
!= state
,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane
), state_string(state
), state_string(cur_state
));
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1262 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1265 struct drm_device
*dev
= dev_priv
->dev
;
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev
)->gen
>= 4) {
1272 reg
= DSPCNTR(pipe
);
1273 val
= I915_READ(reg
);
1274 WARN(val
& DISPLAY_PLANE_ENABLE
,
1275 "plane %c assertion failure, should be disabled but not\n",
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv
, i
) {
1283 val
= I915_READ(reg
);
1284 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1285 DISPPLANE_SEL_PIPE_SHIFT
;
1286 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i
), pipe_name(pipe
));
1292 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1295 struct drm_device
*dev
= dev_priv
->dev
;
1299 if (INTEL_INFO(dev
)->gen
>= 9) {
1300 for_each_sprite(pipe
, sprite
) {
1301 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1302 WARN(val
& PLANE_CTL_ENABLE
,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite
, pipe_name(pipe
));
1306 } else if (IS_VALLEYVIEW(dev
)) {
1307 for_each_sprite(pipe
, sprite
) {
1308 reg
= SPCNTR(pipe
, sprite
);
1309 val
= I915_READ(reg
);
1310 WARN(val
& SP_ENABLE
,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1314 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1316 val
= I915_READ(reg
);
1317 WARN(val
& SPRITE_ENABLE
,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe
), pipe_name(pipe
));
1320 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1321 reg
= DVSCNTR(pipe
);
1322 val
= I915_READ(reg
);
1323 WARN(val
& DVS_ENABLE
,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe
), pipe_name(pipe
));
1329 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1331 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1332 drm_crtc_vblank_put(crtc
);
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1342 val
= I915_READ(PCH_DREF_CONTROL
);
1343 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1344 DREF_SUPERSPREAD_SOURCE_MASK
));
1345 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1355 reg
= PCH_TRANSCONF(pipe
);
1356 val
= I915_READ(reg
);
1357 enabled
= !!(val
& TRANS_ENABLE
);
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1363 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1364 enum pipe pipe
, u32 port_sel
, u32 val
)
1366 if ((val
& DP_PORT_EN
) == 0)
1369 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1370 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1371 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1372 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1374 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1375 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1378 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1384 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1385 enum pipe pipe
, u32 val
)
1387 if ((val
& SDVO_ENABLE
) == 0)
1390 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1391 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1393 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1394 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1397 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1403 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1404 enum pipe pipe
, u32 val
)
1406 if ((val
& LVDS_PORT_EN
) == 0)
1409 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1410 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1413 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1419 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1420 enum pipe pipe
, u32 val
)
1422 if ((val
& ADPA_DAC_ENABLE
) == 0)
1424 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1425 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1428 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1434 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1435 enum pipe pipe
, int reg
, u32 port_sel
)
1437 u32 val
= I915_READ(reg
);
1438 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg
, pipe_name(pipe
));
1442 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1443 && (val
& DP_PIPEB_SELECT
),
1444 "IBX PCH dp port still using transcoder B\n");
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1448 enum pipe pipe
, int reg
)
1450 u32 val
= I915_READ(reg
);
1451 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg
, pipe_name(pipe
));
1455 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1456 && (val
& SDVO_PIPE_B_SELECT
),
1457 "IBX PCH hdmi port still using transcoder B\n");
1460 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1466 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1467 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1468 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1471 val
= I915_READ(reg
);
1472 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1477 val
= I915_READ(reg
);
1478 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1482 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1483 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1484 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1487 static void intel_init_dpio(struct drm_device
*dev
)
1489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1491 if (!IS_VALLEYVIEW(dev
))
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 if (IS_CHERRYVIEW(dev
)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1507 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1508 const struct intel_crtc_config
*pipe_config
)
1510 struct drm_device
*dev
= crtc
->base
.dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1512 int reg
= DPLL(crtc
->pipe
);
1513 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1515 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv
->dev
))
1522 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1524 I915_WRITE(reg
, dpll
);
1528 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1531 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1532 POSTING_READ(DPLL_MD(crtc
->pipe
));
1534 /* We do this three times for luck */
1535 I915_WRITE(reg
, dpll
);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg
, dpll
);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg
, dpll
);
1543 udelay(150); /* wait for warmup */
1546 static void chv_enable_pll(struct intel_crtc
*crtc
,
1547 const struct intel_crtc_config
*pipe_config
)
1549 struct drm_device
*dev
= crtc
->base
.dev
;
1550 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1551 int pipe
= crtc
->pipe
;
1552 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1555 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1559 mutex_lock(&dev_priv
->dpio_lock
);
1561 /* Enable back the 10bit clock to display controller */
1562 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1563 tmp
|= DPIO_DCLKP_EN
;
1564 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1572 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1580 POSTING_READ(DPLL_MD(pipe
));
1582 mutex_unlock(&dev_priv
->dpio_lock
);
1585 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1587 struct intel_crtc
*crtc
;
1590 for_each_intel_crtc(dev
, crtc
)
1591 count
+= crtc
->active
&&
1592 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1597 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1599 struct drm_device
*dev
= crtc
->base
.dev
;
1600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1601 int reg
= DPLL(crtc
->pipe
);
1602 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1604 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1611 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1621 dpll
|= DPLL_DVO_2X_MODE
;
1622 I915_WRITE(DPLL(!crtc
->pipe
),
1623 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev
)->gen
>= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc
->config
.dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1665 struct drm_device
*dev
= crtc
->base
.dev
;
1666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1667 enum pipe pipe
= crtc
->pipe
;
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1671 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1672 intel_num_dvo_pipes(dev
) == 1) {
1673 I915_WRITE(DPLL(PIPE_B
),
1674 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1675 I915_WRITE(DPLL(PIPE_A
),
1676 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1681 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv
, pipe
);
1687 I915_WRITE(DPLL(pipe
), 0);
1688 POSTING_READ(DPLL(pipe
));
1691 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv
, pipe
);
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1703 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1704 I915_WRITE(DPLL(pipe
), val
);
1705 POSTING_READ(DPLL(pipe
));
1709 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1711 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv
, pipe
);
1717 /* Set PLL en = 0 */
1718 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1720 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1721 I915_WRITE(DPLL(pipe
), val
);
1722 POSTING_READ(DPLL(pipe
));
1724 mutex_lock(&dev_priv
->dpio_lock
);
1726 /* Disable 10bit clock to display controller */
1727 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1728 val
&= ~DPIO_DCLKP_EN
;
1729 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1731 /* disable left/right clock distribution */
1732 if (pipe
!= PIPE_B
) {
1733 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1734 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1735 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1737 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1738 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1739 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1742 mutex_unlock(&dev_priv
->dpio_lock
);
1745 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1746 struct intel_digital_port
*dport
)
1751 switch (dport
->port
) {
1753 port_mask
= DPLL_PORTB_READY_MASK
;
1757 port_mask
= DPLL_PORTC_READY_MASK
;
1761 port_mask
= DPLL_PORTD_READY_MASK
;
1762 dpll_reg
= DPIO_PHY_STATUS
;
1768 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport
->port
), I915_READ(dpll_reg
));
1773 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1775 struct drm_device
*dev
= crtc
->base
.dev
;
1776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1777 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1779 if (WARN_ON(pll
== NULL
))
1782 WARN_ON(!pll
->config
.crtc_mask
);
1783 if (pll
->active
== 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1786 assert_shared_dpll_disabled(dev_priv
, pll
);
1788 pll
->mode_set(dev_priv
, pll
);
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1800 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1802 struct drm_device
*dev
= crtc
->base
.dev
;
1803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1804 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1806 if (WARN_ON(pll
== NULL
))
1809 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll
->name
, pll
->active
, pll
->on
,
1814 crtc
->base
.base
.id
);
1816 if (pll
->active
++) {
1818 assert_shared_dpll_enabled(dev_priv
, pll
);
1823 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1825 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1826 pll
->enable(dev_priv
, pll
);
1830 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1832 struct drm_device
*dev
= crtc
->base
.dev
;
1833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1834 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1838 if (WARN_ON(pll
== NULL
))
1841 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll
->name
, pll
->active
, pll
->on
,
1846 crtc
->base
.base
.id
);
1848 if (WARN_ON(pll
->active
== 0)) {
1849 assert_shared_dpll_disabled(dev_priv
, pll
);
1853 assert_shared_dpll_enabled(dev_priv
, pll
);
1858 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1859 pll
->disable(dev_priv
, pll
);
1862 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1868 struct drm_device
*dev
= dev_priv
->dev
;
1869 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1871 uint32_t reg
, val
, pipeconf_val
;
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev
));
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv
,
1878 intel_crtc_to_shared_dpll(intel_crtc
));
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv
, pipe
);
1882 assert_fdi_rx_enabled(dev_priv
, pipe
);
1884 if (HAS_PCH_CPT(dev
)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg
= TRANS_CHICKEN2(pipe
);
1888 val
= I915_READ(reg
);
1889 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1890 I915_WRITE(reg
, val
);
1893 reg
= PCH_TRANSCONF(pipe
);
1894 val
= I915_READ(reg
);
1895 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1897 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1902 val
&= ~PIPECONF_BPC_MASK
;
1903 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1906 val
&= ~TRANS_INTERLACE_MASK
;
1907 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1908 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1909 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1910 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1912 val
|= TRANS_INTERLACED
;
1914 val
|= TRANS_PROGRESSIVE
;
1916 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1917 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1922 enum transcoder cpu_transcoder
)
1924 u32 val
, pipeconf_val
;
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1931 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1933 /* Workaround: set timing override bit. */
1934 val
= I915_READ(_TRANSA_CHICKEN2
);
1935 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1936 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1939 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1941 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1942 PIPECONF_INTERLACED_ILK
)
1943 val
|= TRANS_INTERLACED
;
1945 val
|= TRANS_PROGRESSIVE
;
1947 I915_WRITE(LPT_TRANSCONF
, val
);
1948 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1955 struct drm_device
*dev
= dev_priv
->dev
;
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv
, pipe
);
1960 assert_fdi_rx_disabled(dev_priv
, pipe
);
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv
, pipe
);
1965 reg
= PCH_TRANSCONF(pipe
);
1966 val
= I915_READ(reg
);
1967 val
&= ~TRANS_ENABLE
;
1968 I915_WRITE(reg
, val
);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1973 if (!HAS_PCH_IBX(dev
)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg
= TRANS_CHICKEN2(pipe
);
1976 val
= I915_READ(reg
);
1977 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1978 I915_WRITE(reg
, val
);
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1986 val
= I915_READ(LPT_TRANSCONF
);
1987 val
&= ~TRANS_ENABLE
;
1988 I915_WRITE(LPT_TRANSCONF
, val
);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1993 /* Workaround: clear timing override bit. */
1994 val
= I915_READ(_TRANSA_CHICKEN2
);
1995 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1996 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2006 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2008 struct drm_device
*dev
= crtc
->base
.dev
;
2009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 enum pipe pipe
= crtc
->pipe
;
2011 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2013 enum pipe pch_transcoder
;
2017 assert_planes_disabled(dev_priv
, pipe
);
2018 assert_cursor_disabled(dev_priv
, pipe
);
2019 assert_sprites_disabled(dev_priv
, pipe
);
2021 if (HAS_PCH_LPT(dev_priv
->dev
))
2022 pch_transcoder
= TRANSCODER_A
;
2024 pch_transcoder
= pipe
;
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2031 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2032 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2033 assert_dsi_pll_enabled(dev_priv
);
2035 assert_pll_enabled(dev_priv
, pipe
);
2037 if (crtc
->config
.has_pch_encoder
) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2040 assert_fdi_tx_pll_enabled(dev_priv
,
2041 (enum pipe
) cpu_transcoder
);
2043 /* FIXME: assert CPU port conditions for SNB+ */
2046 reg
= PIPECONF(cpu_transcoder
);
2047 val
= I915_READ(reg
);
2048 if (val
& PIPECONF_ENABLE
) {
2049 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2050 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2054 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2066 * Will wait until the pipe has shut down before returning.
2068 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2070 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2071 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2072 enum pipe pipe
= crtc
->pipe
;
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2080 assert_planes_disabled(dev_priv
, pipe
);
2081 assert_cursor_disabled(dev_priv
, pipe
);
2082 assert_sprites_disabled(dev_priv
, pipe
);
2084 reg
= PIPECONF(cpu_transcoder
);
2085 val
= I915_READ(reg
);
2086 if ((val
& PIPECONF_ENABLE
) == 0)
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2093 if (crtc
->config
.double_wide
)
2094 val
&= ~PIPECONF_DOUBLE_WIDE
;
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2098 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2099 val
&= ~PIPECONF_ENABLE
;
2101 I915_WRITE(reg
, val
);
2102 if ((val
& PIPECONF_ENABLE
) == 0)
2103 intel_wait_for_pipe_off(crtc
);
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2110 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2113 struct drm_device
*dev
= dev_priv
->dev
;
2114 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2116 I915_WRITE(reg
, I915_READ(reg
));
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2127 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2128 struct drm_crtc
*crtc
)
2130 struct drm_device
*dev
= plane
->dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2137 if (intel_crtc
->primary_enabled
)
2140 intel_crtc
->primary_enabled
= true;
2142 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2150 if (IS_BROADWELL(dev
))
2151 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2161 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2162 struct drm_crtc
*crtc
)
2164 struct drm_device
*dev
= plane
->dev
;
2165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2168 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2170 if (!intel_crtc
->primary_enabled
)
2173 intel_crtc
->primary_enabled
= false;
2175 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2179 static bool need_vtd_wa(struct drm_device
*dev
)
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2188 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2192 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2193 return ALIGN(height
, tile_height
);
2197 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2198 struct drm_framebuffer
*fb
,
2199 struct intel_engine_cs
*pipelined
)
2201 struct drm_device
*dev
= fb
->dev
;
2202 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2203 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2207 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2209 switch (obj
->tiling_mode
) {
2210 case I915_TILING_NONE
:
2211 if (INTEL_INFO(dev
)->gen
>= 9)
2212 alignment
= 256 * 1024;
2213 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2214 alignment
= 128 * 1024;
2215 else if (INTEL_INFO(dev
)->gen
>= 4)
2216 alignment
= 4 * 1024;
2218 alignment
= 64 * 1024;
2221 if (INTEL_INFO(dev
)->gen
>= 9)
2222 alignment
= 256 * 1024;
2224 /* pin() will align the object as required by fence */
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2240 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2241 alignment
= 256 * 1024;
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2250 intel_runtime_pm_get(dev_priv
);
2252 dev_priv
->mm
.interruptible
= false;
2253 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2255 goto err_interruptible
;
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2262 ret
= i915_gem_object_get_fence(obj
);
2266 i915_gem_object_pin_fence(obj
);
2268 dev_priv
->mm
.interruptible
= true;
2269 intel_runtime_pm_put(dev_priv
);
2273 i915_gem_object_unpin_from_display_plane(obj
);
2275 dev_priv
->mm
.interruptible
= true;
2276 intel_runtime_pm_put(dev_priv
);
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2282 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2284 i915_gem_object_unpin_fence(obj
);
2285 i915_gem_object_unpin_from_display_plane(obj
);
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2291 unsigned int tiling_mode
,
2295 if (tiling_mode
!= I915_TILING_NONE
) {
2296 unsigned int tile_rows
, tiles
;
2301 tiles
= *x
/ (512/cpp
);
2304 return tile_rows
* pitch
* 8 + tiles
* 4096;
2306 unsigned int offset
;
2308 offset
= *y
* pitch
+ *x
* cpp
;
2310 *x
= (offset
& 4095) / cpp
;
2311 return offset
& -4096;
2315 int intel_format_to_fourcc(int format
)
2318 case DISPPLANE_8BPP
:
2319 return DRM_FORMAT_C8
;
2320 case DISPPLANE_BGRX555
:
2321 return DRM_FORMAT_XRGB1555
;
2322 case DISPPLANE_BGRX565
:
2323 return DRM_FORMAT_RGB565
;
2325 case DISPPLANE_BGRX888
:
2326 return DRM_FORMAT_XRGB8888
;
2327 case DISPPLANE_RGBX888
:
2328 return DRM_FORMAT_XBGR8888
;
2329 case DISPPLANE_BGRX101010
:
2330 return DRM_FORMAT_XRGB2101010
;
2331 case DISPPLANE_RGBX101010
:
2332 return DRM_FORMAT_XBGR2101010
;
2336 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2337 struct intel_plane_config
*plane_config
)
2339 struct drm_device
*dev
= crtc
->base
.dev
;
2340 struct drm_i915_gem_object
*obj
= NULL
;
2341 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2342 u32 base
= plane_config
->base
;
2344 if (plane_config
->size
== 0)
2347 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2348 plane_config
->size
);
2352 if (plane_config
->tiled
) {
2353 obj
->tiling_mode
= I915_TILING_X
;
2354 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2357 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2358 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2359 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2360 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2362 mutex_lock(&dev
->struct_mutex
);
2364 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2370 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2371 mutex_unlock(&dev
->struct_mutex
);
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2377 drm_gem_object_unreference(&obj
->base
);
2378 mutex_unlock(&dev
->struct_mutex
);
2382 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2383 struct intel_plane_config
*plane_config
)
2385 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2388 struct intel_crtc
*i
;
2389 struct drm_i915_gem_object
*obj
;
2391 if (!intel_crtc
->base
.primary
->fb
)
2394 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2397 kfree(intel_crtc
->base
.primary
->fb
);
2398 intel_crtc
->base
.primary
->fb
= NULL
;
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2404 for_each_crtc(dev
, c
) {
2405 i
= to_intel_crtc(c
);
2407 if (c
== &intel_crtc
->base
)
2413 obj
= intel_fb_obj(c
->primary
->fb
);
2417 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2418 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2419 dev_priv
->preserve_bios_swizzle
= true;
2421 drm_framebuffer_reference(c
->primary
->fb
);
2422 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2423 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2429 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2430 struct drm_framebuffer
*fb
,
2433 struct drm_device
*dev
= crtc
->dev
;
2434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2435 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2436 struct drm_i915_gem_object
*obj
;
2437 int plane
= intel_crtc
->plane
;
2438 unsigned long linear_offset
;
2440 u32 reg
= DSPCNTR(plane
);
2443 if (!intel_crtc
->primary_enabled
) {
2445 if (INTEL_INFO(dev
)->gen
>= 4)
2446 I915_WRITE(DSPSURF(plane
), 0);
2448 I915_WRITE(DSPADDR(plane
), 0);
2453 obj
= intel_fb_obj(fb
);
2454 if (WARN_ON(obj
== NULL
))
2457 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2459 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2461 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2463 if (INTEL_INFO(dev
)->gen
< 4) {
2464 if (intel_crtc
->pipe
== PIPE_B
)
2465 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2470 I915_WRITE(DSPSIZE(plane
),
2471 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2472 (intel_crtc
->config
.pipe_src_w
- 1));
2473 I915_WRITE(DSPPOS(plane
), 0);
2474 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2475 I915_WRITE(PRIMSIZE(plane
),
2476 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2477 (intel_crtc
->config
.pipe_src_w
- 1));
2478 I915_WRITE(PRIMPOS(plane
), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2482 switch (fb
->pixel_format
) {
2484 dspcntr
|= DISPPLANE_8BPP
;
2486 case DRM_FORMAT_XRGB1555
:
2487 case DRM_FORMAT_ARGB1555
:
2488 dspcntr
|= DISPPLANE_BGRX555
;
2490 case DRM_FORMAT_RGB565
:
2491 dspcntr
|= DISPPLANE_BGRX565
;
2493 case DRM_FORMAT_XRGB8888
:
2494 case DRM_FORMAT_ARGB8888
:
2495 dspcntr
|= DISPPLANE_BGRX888
;
2497 case DRM_FORMAT_XBGR8888
:
2498 case DRM_FORMAT_ABGR8888
:
2499 dspcntr
|= DISPPLANE_RGBX888
;
2501 case DRM_FORMAT_XRGB2101010
:
2502 case DRM_FORMAT_ARGB2101010
:
2503 dspcntr
|= DISPPLANE_BGRX101010
;
2505 case DRM_FORMAT_XBGR2101010
:
2506 case DRM_FORMAT_ABGR2101010
:
2507 dspcntr
|= DISPPLANE_RGBX101010
;
2513 if (INTEL_INFO(dev
)->gen
>= 4 &&
2514 obj
->tiling_mode
!= I915_TILING_NONE
)
2515 dspcntr
|= DISPPLANE_TILED
;
2518 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2520 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2522 if (INTEL_INFO(dev
)->gen
>= 4) {
2523 intel_crtc
->dspaddr_offset
=
2524 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2527 linear_offset
-= intel_crtc
->dspaddr_offset
;
2529 intel_crtc
->dspaddr_offset
= linear_offset
;
2532 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2533 dspcntr
|= DISPPLANE_ROTATE_180
;
2535 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2536 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2541 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2542 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2545 I915_WRITE(reg
, dspcntr
);
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2550 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2551 if (INTEL_INFO(dev
)->gen
>= 4) {
2552 I915_WRITE(DSPSURF(plane
),
2553 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2554 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2555 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2557 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2561 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2562 struct drm_framebuffer
*fb
,
2565 struct drm_device
*dev
= crtc
->dev
;
2566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2567 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2568 struct drm_i915_gem_object
*obj
;
2569 int plane
= intel_crtc
->plane
;
2570 unsigned long linear_offset
;
2572 u32 reg
= DSPCNTR(plane
);
2575 if (!intel_crtc
->primary_enabled
) {
2577 I915_WRITE(DSPSURF(plane
), 0);
2582 obj
= intel_fb_obj(fb
);
2583 if (WARN_ON(obj
== NULL
))
2586 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2588 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2590 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2592 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2593 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2595 switch (fb
->pixel_format
) {
2597 dspcntr
|= DISPPLANE_8BPP
;
2599 case DRM_FORMAT_RGB565
:
2600 dspcntr
|= DISPPLANE_BGRX565
;
2602 case DRM_FORMAT_XRGB8888
:
2603 case DRM_FORMAT_ARGB8888
:
2604 dspcntr
|= DISPPLANE_BGRX888
;
2606 case DRM_FORMAT_XBGR8888
:
2607 case DRM_FORMAT_ABGR8888
:
2608 dspcntr
|= DISPPLANE_RGBX888
;
2610 case DRM_FORMAT_XRGB2101010
:
2611 case DRM_FORMAT_ARGB2101010
:
2612 dspcntr
|= DISPPLANE_BGRX101010
;
2614 case DRM_FORMAT_XBGR2101010
:
2615 case DRM_FORMAT_ABGR2101010
:
2616 dspcntr
|= DISPPLANE_RGBX101010
;
2622 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2623 dspcntr
|= DISPPLANE_TILED
;
2625 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2626 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2628 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2629 intel_crtc
->dspaddr_offset
=
2630 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2633 linear_offset
-= intel_crtc
->dspaddr_offset
;
2634 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2635 dspcntr
|= DISPPLANE_ROTATE_180
;
2637 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2638 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2639 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2644 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2645 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2649 I915_WRITE(reg
, dspcntr
);
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2654 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2655 I915_WRITE(DSPSURF(plane
),
2656 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2657 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2658 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2660 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2661 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2666 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2667 struct drm_framebuffer
*fb
,
2670 struct drm_device
*dev
= crtc
->dev
;
2671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2673 struct intel_framebuffer
*intel_fb
;
2674 struct drm_i915_gem_object
*obj
;
2675 int pipe
= intel_crtc
->pipe
;
2676 u32 plane_ctl
, stride
;
2678 if (!intel_crtc
->primary_enabled
) {
2679 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe
, 0));
2685 plane_ctl
= PLANE_CTL_ENABLE
|
2686 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2687 PLANE_CTL_PIPE_CSC_ENABLE
;
2689 switch (fb
->pixel_format
) {
2690 case DRM_FORMAT_RGB565
:
2691 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2693 case DRM_FORMAT_XRGB8888
:
2694 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2696 case DRM_FORMAT_XBGR8888
:
2697 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2698 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2700 case DRM_FORMAT_XRGB2101010
:
2701 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2703 case DRM_FORMAT_XBGR2101010
:
2704 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2705 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2711 intel_fb
= to_intel_framebuffer(fb
);
2712 obj
= intel_fb
->obj
;
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2718 switch (obj
->tiling_mode
) {
2719 case I915_TILING_NONE
:
2720 stride
= fb
->pitches
[0] >> 6;
2723 plane_ctl
|= PLANE_CTL_TILED_X
;
2724 stride
= fb
->pitches
[0] >> 9;
2730 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
2731 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
))
2732 plane_ctl
|= PLANE_CTL_ROTATE_180
;
2734 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj
),
2738 x
, y
, fb
->width
, fb
->height
,
2741 I915_WRITE(PLANE_POS(pipe
, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
2743 I915_WRITE(PLANE_SIZE(pipe
, 0),
2744 (intel_crtc
->config
.pipe_src_h
- 1) << 16 |
2745 (intel_crtc
->config
.pipe_src_w
- 1));
2746 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
2747 I915_WRITE(PLANE_SURF(pipe
, 0), i915_gem_obj_ggtt_offset(obj
));
2749 POSTING_READ(PLANE_SURF(pipe
, 0));
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2754 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2755 int x
, int y
, enum mode_set_atomic state
)
2757 struct drm_device
*dev
= crtc
->dev
;
2758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 if (dev_priv
->display
.disable_fbc
)
2761 dev_priv
->display
.disable_fbc(dev
);
2763 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2768 void intel_display_handle_reset(struct drm_device
*dev
)
2770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2771 struct drm_crtc
*crtc
;
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2787 for_each_crtc(dev
, crtc
) {
2788 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2789 enum plane plane
= intel_crtc
->plane
;
2791 intel_prepare_page_flip(dev
, plane
);
2792 intel_finish_page_flip_plane(dev
, plane
);
2795 for_each_crtc(dev
, crtc
) {
2796 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2798 drm_modeset_lock(&crtc
->mutex
, NULL
);
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
2802 * a NULL crtc->primary->fb.
2804 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2805 dev_priv
->display
.update_primary_plane(crtc
,
2809 drm_modeset_unlock(&crtc
->mutex
);
2814 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2816 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2817 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2818 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2829 dev_priv
->mm
.interruptible
= false;
2830 ret
= i915_gem_object_finish_gpu(obj
);
2831 dev_priv
->mm
.interruptible
= was_interruptible
;
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2838 struct drm_device
*dev
= crtc
->dev
;
2839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2843 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2844 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2847 spin_lock_irq(&dev
->event_lock
);
2848 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2849 spin_unlock_irq(&dev
->event_lock
);
2854 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
2856 struct drm_device
*dev
= crtc
->base
.dev
;
2857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2858 const struct drm_display_mode
*adjusted_mode
;
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2877 adjusted_mode
= &crtc
->config
.adjusted_mode
;
2879 I915_WRITE(PIPESRC(crtc
->pipe
),
2880 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2881 (adjusted_mode
->crtc_vdisplay
- 1));
2882 if (!crtc
->config
.pch_pfit
.enabled
&&
2883 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2884 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2885 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
2886 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
2889 crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2890 crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2894 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2895 struct drm_framebuffer
*fb
)
2897 struct drm_device
*dev
= crtc
->dev
;
2898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2899 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2900 enum pipe pipe
= intel_crtc
->pipe
;
2901 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2902 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2905 if (intel_crtc_has_pending_flip(crtc
)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2912 DRM_ERROR("No FB bound\n");
2916 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc
->plane
),
2919 INTEL_INFO(dev
)->num_pipes
);
2923 mutex_lock(&dev
->struct_mutex
);
2924 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
2926 i915_gem_track_fb(old_obj
, intel_fb_obj(fb
),
2927 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2928 mutex_unlock(&dev
->struct_mutex
);
2930 DRM_ERROR("pin & fence failed\n");
2934 intel_update_pipe_size(intel_crtc
);
2936 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2938 if (intel_crtc
->active
)
2939 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2941 crtc
->primary
->fb
= fb
;
2946 if (intel_crtc
->active
&& old_fb
!= fb
)
2947 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2948 mutex_lock(&dev
->struct_mutex
);
2949 intel_unpin_fb_obj(old_obj
);
2950 mutex_unlock(&dev
->struct_mutex
);
2953 mutex_lock(&dev
->struct_mutex
);
2954 intel_update_fbc(dev
);
2955 mutex_unlock(&dev
->struct_mutex
);
2960 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2962 struct drm_device
*dev
= crtc
->dev
;
2963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2965 int pipe
= intel_crtc
->pipe
;
2968 /* enable normal train */
2969 reg
= FDI_TX_CTL(pipe
);
2970 temp
= I915_READ(reg
);
2971 if (IS_IVYBRIDGE(dev
)) {
2972 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2973 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2975 temp
&= ~FDI_LINK_TRAIN_NONE
;
2976 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2978 I915_WRITE(reg
, temp
);
2980 reg
= FDI_RX_CTL(pipe
);
2981 temp
= I915_READ(reg
);
2982 if (HAS_PCH_CPT(dev
)) {
2983 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2984 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2986 temp
&= ~FDI_LINK_TRAIN_NONE
;
2987 temp
|= FDI_LINK_TRAIN_NONE
;
2989 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2991 /* wait one idle pattern time */
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev
))
2997 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2998 FDI_FE_ERRC_ENABLE
);
3001 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
3003 return crtc
->base
.enabled
&& crtc
->active
&&
3004 crtc
->config
.has_pch_encoder
;
3007 static void ivb_modeset_global_resources(struct drm_device
*dev
)
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3010 struct intel_crtc
*pipe_B_crtc
=
3011 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
3012 struct intel_crtc
*pipe_C_crtc
=
3013 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3021 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc
)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3026 temp
= I915_READ(SOUTH_CHICKEN1
);
3027 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3036 struct drm_device
*dev
= crtc
->dev
;
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3039 int pipe
= intel_crtc
->pipe
;
3040 u32 reg
, temp
, tries
;
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv
, pipe
);
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3047 reg
= FDI_RX_IMR(pipe
);
3048 temp
= I915_READ(reg
);
3049 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3050 temp
&= ~FDI_RX_BIT_LOCK
;
3051 I915_WRITE(reg
, temp
);
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg
= FDI_TX_CTL(pipe
);
3057 temp
= I915_READ(reg
);
3058 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3059 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3060 temp
&= ~FDI_LINK_TRAIN_NONE
;
3061 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3062 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3064 reg
= FDI_RX_CTL(pipe
);
3065 temp
= I915_READ(reg
);
3066 temp
&= ~FDI_LINK_TRAIN_NONE
;
3067 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3068 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3076 FDI_RX_PHASE_SYNC_POINTER_EN
);
3078 reg
= FDI_RX_IIR(pipe
);
3079 for (tries
= 0; tries
< 5; tries
++) {
3080 temp
= I915_READ(reg
);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3083 if ((temp
& FDI_RX_BIT_LOCK
)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3090 DRM_ERROR("FDI train 1 fail!\n");
3093 reg
= FDI_TX_CTL(pipe
);
3094 temp
= I915_READ(reg
);
3095 temp
&= ~FDI_LINK_TRAIN_NONE
;
3096 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3097 I915_WRITE(reg
, temp
);
3099 reg
= FDI_RX_CTL(pipe
);
3100 temp
= I915_READ(reg
);
3101 temp
&= ~FDI_LINK_TRAIN_NONE
;
3102 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3103 I915_WRITE(reg
, temp
);
3108 reg
= FDI_RX_IIR(pipe
);
3109 for (tries
= 0; tries
< 5; tries
++) {
3110 temp
= I915_READ(reg
);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3113 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3114 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3120 DRM_ERROR("FDI train 2 fail!\n");
3122 DRM_DEBUG_KMS("FDI train done\n");
3126 static const int snb_b_fdi_train_param
[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3136 struct drm_device
*dev
= crtc
->dev
;
3137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3138 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3139 int pipe
= intel_crtc
->pipe
;
3140 u32 reg
, temp
, i
, retry
;
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3144 reg
= FDI_RX_IMR(pipe
);
3145 temp
= I915_READ(reg
);
3146 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3147 temp
&= ~FDI_RX_BIT_LOCK
;
3148 I915_WRITE(reg
, temp
);
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg
= FDI_TX_CTL(pipe
);
3155 temp
= I915_READ(reg
);
3156 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3157 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3158 temp
&= ~FDI_LINK_TRAIN_NONE
;
3159 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3160 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3162 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3163 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3165 I915_WRITE(FDI_RX_MISC(pipe
),
3166 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3168 reg
= FDI_RX_CTL(pipe
);
3169 temp
= I915_READ(reg
);
3170 if (HAS_PCH_CPT(dev
)) {
3171 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3172 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3174 temp
&= ~FDI_LINK_TRAIN_NONE
;
3175 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3177 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3182 for (i
= 0; i
< 4; i
++) {
3183 reg
= FDI_TX_CTL(pipe
);
3184 temp
= I915_READ(reg
);
3185 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3186 temp
|= snb_b_fdi_train_param
[i
];
3187 I915_WRITE(reg
, temp
);
3192 for (retry
= 0; retry
< 5; retry
++) {
3193 reg
= FDI_RX_IIR(pipe
);
3194 temp
= I915_READ(reg
);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3196 if (temp
& FDI_RX_BIT_LOCK
) {
3197 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3207 DRM_ERROR("FDI train 1 fail!\n");
3210 reg
= FDI_TX_CTL(pipe
);
3211 temp
= I915_READ(reg
);
3212 temp
&= ~FDI_LINK_TRAIN_NONE
;
3213 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3215 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3217 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3219 I915_WRITE(reg
, temp
);
3221 reg
= FDI_RX_CTL(pipe
);
3222 temp
= I915_READ(reg
);
3223 if (HAS_PCH_CPT(dev
)) {
3224 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3225 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3227 temp
&= ~FDI_LINK_TRAIN_NONE
;
3228 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3230 I915_WRITE(reg
, temp
);
3235 for (i
= 0; i
< 4; i
++) {
3236 reg
= FDI_TX_CTL(pipe
);
3237 temp
= I915_READ(reg
);
3238 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3239 temp
|= snb_b_fdi_train_param
[i
];
3240 I915_WRITE(reg
, temp
);
3245 for (retry
= 0; retry
< 5; retry
++) {
3246 reg
= FDI_RX_IIR(pipe
);
3247 temp
= I915_READ(reg
);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3249 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3250 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3260 DRM_ERROR("FDI train 2 fail!\n");
3262 DRM_DEBUG_KMS("FDI train done.\n");
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3268 struct drm_device
*dev
= crtc
->dev
;
3269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3271 int pipe
= intel_crtc
->pipe
;
3272 u32 reg
, temp
, i
, j
;
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3276 reg
= FDI_RX_IMR(pipe
);
3277 temp
= I915_READ(reg
);
3278 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3279 temp
&= ~FDI_RX_BIT_LOCK
;
3280 I915_WRITE(reg
, temp
);
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe
)));
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3290 /* disable first in case we need to retry */
3291 reg
= FDI_TX_CTL(pipe
);
3292 temp
= I915_READ(reg
);
3293 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3294 temp
&= ~FDI_TX_ENABLE
;
3295 I915_WRITE(reg
, temp
);
3297 reg
= FDI_RX_CTL(pipe
);
3298 temp
= I915_READ(reg
);
3299 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3300 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3301 temp
&= ~FDI_RX_ENABLE
;
3302 I915_WRITE(reg
, temp
);
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg
= FDI_TX_CTL(pipe
);
3306 temp
= I915_READ(reg
);
3307 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3308 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3309 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3310 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3311 temp
|= snb_b_fdi_train_param
[j
/2];
3312 temp
|= FDI_COMPOSITE_SYNC
;
3313 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3315 I915_WRITE(FDI_RX_MISC(pipe
),
3316 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3318 reg
= FDI_RX_CTL(pipe
);
3319 temp
= I915_READ(reg
);
3320 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3321 temp
|= FDI_COMPOSITE_SYNC
;
3322 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3325 udelay(1); /* should be 0.5us */
3327 for (i
= 0; i
< 4; i
++) {
3328 reg
= FDI_RX_IIR(pipe
);
3329 temp
= I915_READ(reg
);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3332 if (temp
& FDI_RX_BIT_LOCK
||
3333 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3334 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3339 udelay(1); /* should be 0.5us */
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3347 reg
= FDI_TX_CTL(pipe
);
3348 temp
= I915_READ(reg
);
3349 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3350 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3351 I915_WRITE(reg
, temp
);
3353 reg
= FDI_RX_CTL(pipe
);
3354 temp
= I915_READ(reg
);
3355 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3356 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3357 I915_WRITE(reg
, temp
);
3360 udelay(2); /* should be 1.5us */
3362 for (i
= 0; i
< 4; i
++) {
3363 reg
= FDI_RX_IIR(pipe
);
3364 temp
= I915_READ(reg
);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3367 if (temp
& FDI_RX_SYMBOL_LOCK
||
3368 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3369 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3374 udelay(2); /* should be 1.5us */
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3381 DRM_DEBUG_KMS("FDI train done.\n");
3384 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3386 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3388 int pipe
= intel_crtc
->pipe
;
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg
= FDI_RX_CTL(pipe
);
3394 temp
= I915_READ(reg
);
3395 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3396 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3397 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3398 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3403 /* Switch from Rawclk to PCDclk */
3404 temp
= I915_READ(reg
);
3405 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg
= FDI_TX_CTL(pipe
);
3412 temp
= I915_READ(reg
);
3413 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3414 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3421 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3423 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3425 int pipe
= intel_crtc
->pipe
;
3428 /* Switch from PCDclk to Rawclk */
3429 reg
= FDI_RX_CTL(pipe
);
3430 temp
= I915_READ(reg
);
3431 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3433 /* Disable CPU FDI TX PLL */
3434 reg
= FDI_TX_CTL(pipe
);
3435 temp
= I915_READ(reg
);
3436 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3441 reg
= FDI_RX_CTL(pipe
);
3442 temp
= I915_READ(reg
);
3443 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3445 /* Wait for the clocks to turn off. */
3450 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3452 struct drm_device
*dev
= crtc
->dev
;
3453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3455 int pipe
= intel_crtc
->pipe
;
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg
= FDI_TX_CTL(pipe
);
3460 temp
= I915_READ(reg
);
3461 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3464 reg
= FDI_RX_CTL(pipe
);
3465 temp
= I915_READ(reg
);
3466 temp
&= ~(0x7 << 16);
3467 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3468 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev
))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3477 /* still set train pattern 1 */
3478 reg
= FDI_TX_CTL(pipe
);
3479 temp
= I915_READ(reg
);
3480 temp
&= ~FDI_LINK_TRAIN_NONE
;
3481 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3482 I915_WRITE(reg
, temp
);
3484 reg
= FDI_RX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 if (HAS_PCH_CPT(dev
)) {
3487 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3488 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3490 temp
&= ~FDI_LINK_TRAIN_NONE
;
3491 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp
&= ~(0x07 << 16);
3495 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3496 I915_WRITE(reg
, temp
);
3502 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3504 struct intel_crtc
*crtc
;
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3513 for_each_intel_crtc(dev
, crtc
) {
3514 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3517 if (crtc
->unpin_work
)
3518 intel_wait_for_vblank(dev
, crtc
->pipe
);
3526 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3528 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3529 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3533 intel_crtc
->unpin_work
= NULL
;
3536 drm_send_vblank_event(intel_crtc
->base
.dev
,
3540 drm_crtc_vblank_put(&intel_crtc
->base
);
3542 wake_up_all(&dev_priv
->pending_flip_queue
);
3543 queue_work(dev_priv
->wq
, &work
->work
);
3545 trace_i915_flip_complete(intel_crtc
->plane
,
3546 work
->pending_flip_obj
);
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3551 struct drm_device
*dev
= crtc
->dev
;
3552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3555 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3556 !intel_crtc_has_pending_flip(crtc
),
3558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3560 spin_lock_irq(&dev
->event_lock
);
3561 if (intel_crtc
->unpin_work
) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc
);
3565 spin_unlock_irq(&dev
->event_lock
);
3568 if (crtc
->primary
->fb
) {
3569 mutex_lock(&dev
->struct_mutex
);
3570 intel_finish_fb(crtc
->primary
->fb
);
3571 mutex_unlock(&dev
->struct_mutex
);
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3578 struct drm_device
*dev
= crtc
->dev
;
3579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3580 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3581 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3584 mutex_lock(&dev_priv
->dpio_lock
);
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3589 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3593 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock
== 20000) {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3609 u32 iclk_virtual_root_freq
= 172800 * 1000;
3610 u32 iclk_pi_range
= 64;
3611 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3613 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3614 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3615 pi_value
= desired_divisor
% iclk_pi_range
;
3618 divsel
= msb_divisor_value
- 2;
3619 phaseinc
= pi_value
;
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3635 /* Program SSCDIVINTPHASE6 */
3636 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3637 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3638 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3639 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3640 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3641 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3642 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3643 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3645 /* Program SSCAUXDIV */
3646 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3647 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3649 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3651 /* Enable modulator and associated divider */
3652 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3653 temp
&= ~SBI_SSCCTL_DISABLE
;
3654 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3656 /* Wait for initialization time */
3659 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3661 mutex_unlock(&dev_priv
->dpio_lock
);
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3665 enum pipe pch_transcoder
)
3667 struct drm_device
*dev
= crtc
->base
.dev
;
3668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3669 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3672 I915_READ(HTOTAL(cpu_transcoder
)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3674 I915_READ(HBLANK(cpu_transcoder
)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3676 I915_READ(HSYNC(cpu_transcoder
)));
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3679 I915_READ(VTOTAL(cpu_transcoder
)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3681 I915_READ(VBLANK(cpu_transcoder
)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3683 I915_READ(VSYNC(cpu_transcoder
)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3693 temp
= I915_READ(SOUTH_CHICKEN1
);
3694 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3700 temp
|= FDI_BC_BIFURCATION_SELECT
;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3703 POSTING_READ(SOUTH_CHICKEN1
);
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3708 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3711 switch (intel_crtc
->pipe
) {
3715 if (intel_crtc
->config
.fdi_lanes
> 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3718 cpt_enable_fdi_bc_bifurcation(dev
);
3722 cpt_enable_fdi_bc_bifurcation(dev
);
3731 * Enable PCH resources required for PCH ports:
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3738 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3740 struct drm_device
*dev
= crtc
->dev
;
3741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3743 int pipe
= intel_crtc
->pipe
;
3746 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3748 if (IS_IVYBRIDGE(dev
))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3754 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3756 /* For PCH output, training FDI link */
3757 dev_priv
->display
.fdi_link_train(crtc
);
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev
)) {
3764 temp
= I915_READ(PCH_DPLL_SEL
);
3765 temp
|= TRANS_DPLL_ENABLE(pipe
);
3766 sel
= TRANS_DPLLB_SEL(pipe
);
3767 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3771 I915_WRITE(PCH_DPLL_SEL
, temp
);
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc
);
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv
, pipe
);
3785 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3787 intel_fdi_normal_train(crtc
);
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
.has_dp_encoder
) {
3791 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3792 reg
= TRANS_DP_CTL(pipe
);
3793 temp
= I915_READ(reg
);
3794 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3795 TRANS_DP_SYNC_MASK
|
3797 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3798 TRANS_DP_ENH_FRAMING
);
3799 temp
|= bpc
<< 9; /* same format but at 11:9 */
3801 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3802 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3803 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3804 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3806 switch (intel_trans_dp_port_sel(crtc
)) {
3808 temp
|= TRANS_DP_PORT_SEL_B
;
3811 temp
|= TRANS_DP_PORT_SEL_C
;
3814 temp
|= TRANS_DP_PORT_SEL_D
;
3820 I915_WRITE(reg
, temp
);
3823 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3826 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3828 struct drm_device
*dev
= crtc
->dev
;
3829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3831 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3833 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3835 lpt_program_iclkip(crtc
);
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3840 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3843 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3845 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3850 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
3851 WARN(1, "bad %s crtc mask\n", pll
->name
);
3855 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
3856 if (pll
->config
.crtc_mask
== 0) {
3858 WARN_ON(pll
->active
);
3861 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3864 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3866 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3867 struct intel_shared_dpll
*pll
;
3868 enum intel_dpll_id i
;
3870 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872 i
= (enum intel_dpll_id
) crtc
->pipe
;
3873 pll
= &dev_priv
->shared_dplls
[i
];
3875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc
->base
.base
.id
, pll
->name
);
3878 WARN_ON(pll
->new_config
->crtc_mask
);
3883 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3884 pll
= &dev_priv
->shared_dplls
[i
];
3886 /* Only want to check enabled timings first */
3887 if (pll
->new_config
->crtc_mask
== 0)
3890 if (memcmp(&crtc
->new_config
->dpll_hw_state
,
3891 &pll
->new_config
->hw_state
,
3892 sizeof(pll
->new_config
->hw_state
)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894 crtc
->base
.base
.id
, pll
->name
,
3895 pll
->new_config
->crtc_mask
,
3901 /* Ok no matching timings, maybe there's a free one? */
3902 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3903 pll
= &dev_priv
->shared_dplls
[i
];
3904 if (pll
->new_config
->crtc_mask
== 0) {
3905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc
->base
.base
.id
, pll
->name
);
3914 if (pll
->new_config
->crtc_mask
== 0)
3915 pll
->new_config
->hw_state
= crtc
->new_config
->dpll_hw_state
;
3917 crtc
->new_config
->shared_dpll
= i
;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3919 pipe_name(crtc
->pipe
));
3921 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3934 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
3935 unsigned clear_pipes
)
3937 struct intel_shared_dpll
*pll
;
3938 enum intel_dpll_id i
;
3940 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3941 pll
= &dev_priv
->shared_dplls
[i
];
3943 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
3945 if (!pll
->new_config
)
3948 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
3955 pll
= &dev_priv
->shared_dplls
[i
];
3956 kfree(pll
->new_config
);
3957 pll
->new_config
= NULL
;
3963 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
3965 struct intel_shared_dpll
*pll
;
3966 enum intel_dpll_id i
;
3968 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3969 pll
= &dev_priv
->shared_dplls
[i
];
3971 WARN_ON(pll
->new_config
== &pll
->config
);
3973 pll
->config
= *pll
->new_config
;
3974 kfree(pll
->new_config
);
3975 pll
->new_config
= NULL
;
3979 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
3981 struct intel_shared_dpll
*pll
;
3982 enum intel_dpll_id i
;
3984 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3985 pll
= &dev_priv
->shared_dplls
[i
];
3987 WARN_ON(pll
->new_config
== &pll
->config
);
3989 kfree(pll
->new_config
);
3990 pll
->new_config
= NULL
;
3994 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3997 int dslreg
= PIPEDSL(pipe
);
4000 temp
= I915_READ(dslreg
);
4002 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4003 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4004 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4008 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4010 struct drm_device
*dev
= crtc
->base
.dev
;
4011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4012 int pipe
= crtc
->pipe
;
4014 if (crtc
->config
.pch_pfit
.enabled
) {
4015 /* Force use of hard-coded filter coefficients
4016 * as some pre-programmed values are broken,
4019 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4020 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4021 PF_PIPE_SEL_IVB(pipe
));
4023 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4024 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
4025 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
4029 static void intel_enable_planes(struct drm_crtc
*crtc
)
4031 struct drm_device
*dev
= crtc
->dev
;
4032 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4033 struct drm_plane
*plane
;
4034 struct intel_plane
*intel_plane
;
4036 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4037 intel_plane
= to_intel_plane(plane
);
4038 if (intel_plane
->pipe
== pipe
)
4039 intel_plane_restore(&intel_plane
->base
);
4043 static void intel_disable_planes(struct drm_crtc
*crtc
)
4045 struct drm_device
*dev
= crtc
->dev
;
4046 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4047 struct drm_plane
*plane
;
4048 struct intel_plane
*intel_plane
;
4050 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4051 intel_plane
= to_intel_plane(plane
);
4052 if (intel_plane
->pipe
== pipe
)
4053 intel_plane_disable(&intel_plane
->base
);
4057 void hsw_enable_ips(struct intel_crtc
*crtc
)
4059 struct drm_device
*dev
= crtc
->base
.dev
;
4060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4062 if (!crtc
->config
.ips_enabled
)
4065 /* We can only enable IPS after we enable a plane and wait for a vblank */
4066 intel_wait_for_vblank(dev
, crtc
->pipe
);
4068 assert_plane_enabled(dev_priv
, crtc
->plane
);
4069 if (IS_BROADWELL(dev
)) {
4070 mutex_lock(&dev_priv
->rps
.hw_lock
);
4071 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4072 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4073 /* Quoting Art Runyan: "its not safe to expect any particular
4074 * value in IPS_CTL bit 31 after enabling IPS through the
4075 * mailbox." Moreover, the mailbox may return a bogus state,
4076 * so we need to just enable it and continue on.
4079 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4080 /* The bit only becomes 1 in the next vblank, so this wait here
4081 * is essentially intel_wait_for_vblank. If we don't have this
4082 * and don't wait for vblanks until the end of crtc_enable, then
4083 * the HW state readout code will complain that the expected
4084 * IPS_CTL value is not the one we read. */
4085 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4086 DRM_ERROR("Timed out waiting for IPS enable\n");
4090 void hsw_disable_ips(struct intel_crtc
*crtc
)
4092 struct drm_device
*dev
= crtc
->base
.dev
;
4093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4095 if (!crtc
->config
.ips_enabled
)
4098 assert_plane_enabled(dev_priv
, crtc
->plane
);
4099 if (IS_BROADWELL(dev
)) {
4100 mutex_lock(&dev_priv
->rps
.hw_lock
);
4101 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4102 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4103 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4104 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4105 DRM_ERROR("Timed out waiting for IPS disable\n");
4107 I915_WRITE(IPS_CTL
, 0);
4108 POSTING_READ(IPS_CTL
);
4111 /* We need to wait for a vblank before we can disable the plane. */
4112 intel_wait_for_vblank(dev
, crtc
->pipe
);
4115 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4116 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4118 struct drm_device
*dev
= crtc
->dev
;
4119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4121 enum pipe pipe
= intel_crtc
->pipe
;
4122 int palreg
= PALETTE(pipe
);
4124 bool reenable_ips
= false;
4126 /* The clocks have to be on to load the palette. */
4127 if (!crtc
->enabled
|| !intel_crtc
->active
)
4130 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4131 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4132 assert_dsi_pll_enabled(dev_priv
);
4134 assert_pll_enabled(dev_priv
, pipe
);
4137 /* use legacy palette for Ironlake */
4138 if (!HAS_GMCH_DISPLAY(dev
))
4139 palreg
= LGC_PALETTE(pipe
);
4141 /* Workaround : Do not read or write the pipe palette/gamma data while
4142 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4144 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
4145 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4146 GAMMA_MODE_MODE_SPLIT
)) {
4147 hsw_disable_ips(intel_crtc
);
4148 reenable_ips
= true;
4151 for (i
= 0; i
< 256; i
++) {
4152 I915_WRITE(palreg
+ 4 * i
,
4153 (intel_crtc
->lut_r
[i
] << 16) |
4154 (intel_crtc
->lut_g
[i
] << 8) |
4155 intel_crtc
->lut_b
[i
]);
4159 hsw_enable_ips(intel_crtc
);
4162 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4164 if (!enable
&& intel_crtc
->overlay
) {
4165 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4168 mutex_lock(&dev
->struct_mutex
);
4169 dev_priv
->mm
.interruptible
= false;
4170 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4171 dev_priv
->mm
.interruptible
= true;
4172 mutex_unlock(&dev
->struct_mutex
);
4175 /* Let userspace switch the overlay on again. In most cases userspace
4176 * has to recompute where to put it anyway.
4180 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4182 struct drm_device
*dev
= crtc
->dev
;
4183 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4184 int pipe
= intel_crtc
->pipe
;
4186 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4187 intel_enable_planes(crtc
);
4188 intel_crtc_update_cursor(crtc
, true);
4189 intel_crtc_dpms_overlay(intel_crtc
, true);
4191 hsw_enable_ips(intel_crtc
);
4193 mutex_lock(&dev
->struct_mutex
);
4194 intel_update_fbc(dev
);
4195 mutex_unlock(&dev
->struct_mutex
);
4198 * FIXME: Once we grow proper nuclear flip support out of this we need
4199 * to compute the mask of flip planes precisely. For the time being
4200 * consider this a flip from a NULL plane.
4202 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4205 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4207 struct drm_device
*dev
= crtc
->dev
;
4208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4210 int pipe
= intel_crtc
->pipe
;
4211 int plane
= intel_crtc
->plane
;
4213 intel_crtc_wait_for_pending_flips(crtc
);
4215 if (dev_priv
->fbc
.plane
== plane
)
4216 intel_disable_fbc(dev
);
4218 hsw_disable_ips(intel_crtc
);
4220 intel_crtc_dpms_overlay(intel_crtc
, false);
4221 intel_crtc_update_cursor(crtc
, false);
4222 intel_disable_planes(crtc
);
4223 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4226 * FIXME: Once we grow proper nuclear flip support out of this we need
4227 * to compute the mask of flip planes precisely. For the time being
4228 * consider this a flip to a NULL plane.
4230 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4233 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4235 struct drm_device
*dev
= crtc
->dev
;
4236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4238 struct intel_encoder
*encoder
;
4239 int pipe
= intel_crtc
->pipe
;
4241 WARN_ON(!crtc
->enabled
);
4243 if (intel_crtc
->active
)
4246 if (intel_crtc
->config
.has_pch_encoder
)
4247 intel_prepare_shared_dpll(intel_crtc
);
4249 if (intel_crtc
->config
.has_dp_encoder
)
4250 intel_dp_set_m_n(intel_crtc
);
4252 intel_set_pipe_timings(intel_crtc
);
4254 if (intel_crtc
->config
.has_pch_encoder
) {
4255 intel_cpu_transcoder_set_m_n(intel_crtc
,
4256 &intel_crtc
->config
.fdi_m_n
, NULL
);
4259 ironlake_set_pipeconf(crtc
);
4261 intel_crtc
->active
= true;
4263 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4264 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4266 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4267 if (encoder
->pre_enable
)
4268 encoder
->pre_enable(encoder
);
4270 if (intel_crtc
->config
.has_pch_encoder
) {
4271 /* Note: FDI PLL enabling _must_ be done before we enable the
4272 * cpu pipes, hence this is separate from all the other fdi/pch
4274 ironlake_fdi_pll_enable(intel_crtc
);
4276 assert_fdi_tx_disabled(dev_priv
, pipe
);
4277 assert_fdi_rx_disabled(dev_priv
, pipe
);
4280 ironlake_pfit_enable(intel_crtc
);
4283 * On ILK+ LUT must be loaded before the pipe is running but with
4286 intel_crtc_load_lut(crtc
);
4288 intel_update_watermarks(crtc
);
4289 intel_enable_pipe(intel_crtc
);
4291 if (intel_crtc
->config
.has_pch_encoder
)
4292 ironlake_pch_enable(crtc
);
4294 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4295 encoder
->enable(encoder
);
4297 if (HAS_PCH_CPT(dev
))
4298 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4300 assert_vblank_disabled(crtc
);
4301 drm_crtc_vblank_on(crtc
);
4303 intel_crtc_enable_planes(crtc
);
4306 /* IPS only exists on ULT machines and is tied to pipe A. */
4307 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4309 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4313 * This implements the workaround described in the "notes" section of the mode
4314 * set sequence documentation. When going from no pipes or single pipe to
4315 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4316 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4318 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4320 struct drm_device
*dev
= crtc
->base
.dev
;
4321 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4323 /* We want to get the other_active_crtc only if there's only 1 other
4325 for_each_intel_crtc(dev
, crtc_it
) {
4326 if (!crtc_it
->active
|| crtc_it
== crtc
)
4329 if (other_active_crtc
)
4332 other_active_crtc
= crtc_it
;
4334 if (!other_active_crtc
)
4337 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4338 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4341 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4343 struct drm_device
*dev
= crtc
->dev
;
4344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4346 struct intel_encoder
*encoder
;
4347 int pipe
= intel_crtc
->pipe
;
4349 WARN_ON(!crtc
->enabled
);
4351 if (intel_crtc
->active
)
4354 if (intel_crtc_to_shared_dpll(intel_crtc
))
4355 intel_enable_shared_dpll(intel_crtc
);
4357 if (intel_crtc
->config
.has_dp_encoder
)
4358 intel_dp_set_m_n(intel_crtc
);
4360 intel_set_pipe_timings(intel_crtc
);
4362 if (intel_crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
) {
4363 I915_WRITE(PIPE_MULT(intel_crtc
->config
.cpu_transcoder
),
4364 intel_crtc
->config
.pixel_multiplier
- 1);
4367 if (intel_crtc
->config
.has_pch_encoder
) {
4368 intel_cpu_transcoder_set_m_n(intel_crtc
,
4369 &intel_crtc
->config
.fdi_m_n
, NULL
);
4372 haswell_set_pipeconf(crtc
);
4374 intel_set_pipe_csc(crtc
);
4376 intel_crtc
->active
= true;
4378 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4379 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4380 if (encoder
->pre_enable
)
4381 encoder
->pre_enable(encoder
);
4383 if (intel_crtc
->config
.has_pch_encoder
) {
4384 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4386 dev_priv
->display
.fdi_link_train(crtc
);
4389 intel_ddi_enable_pipe_clock(intel_crtc
);
4391 ironlake_pfit_enable(intel_crtc
);
4394 * On ILK+ LUT must be loaded before the pipe is running but with
4397 intel_crtc_load_lut(crtc
);
4399 intel_ddi_set_pipe_settings(crtc
);
4400 intel_ddi_enable_transcoder_func(crtc
);
4402 intel_update_watermarks(crtc
);
4403 intel_enable_pipe(intel_crtc
);
4405 if (intel_crtc
->config
.has_pch_encoder
)
4406 lpt_pch_enable(crtc
);
4408 if (intel_crtc
->config
.dp_encoder_is_mst
)
4409 intel_ddi_set_vc_payload_alloc(crtc
, true);
4411 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4412 encoder
->enable(encoder
);
4413 intel_opregion_notify_encoder(encoder
, true);
4416 assert_vblank_disabled(crtc
);
4417 drm_crtc_vblank_on(crtc
);
4419 /* If we change the relative order between pipe/planes enabling, we need
4420 * to change the workaround. */
4421 haswell_mode_set_planes_workaround(intel_crtc
);
4422 intel_crtc_enable_planes(crtc
);
4425 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4427 struct drm_device
*dev
= crtc
->base
.dev
;
4428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 int pipe
= crtc
->pipe
;
4431 /* To avoid upsetting the power well on haswell only disable the pfit if
4432 * it's in use. The hw state code will make sure we get this right. */
4433 if (crtc
->config
.pch_pfit
.enabled
) {
4434 I915_WRITE(PF_CTL(pipe
), 0);
4435 I915_WRITE(PF_WIN_POS(pipe
), 0);
4436 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4440 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4442 struct drm_device
*dev
= crtc
->dev
;
4443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4445 struct intel_encoder
*encoder
;
4446 int pipe
= intel_crtc
->pipe
;
4449 if (!intel_crtc
->active
)
4452 intel_crtc_disable_planes(crtc
);
4454 drm_crtc_vblank_off(crtc
);
4455 assert_vblank_disabled(crtc
);
4457 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4458 encoder
->disable(encoder
);
4460 if (intel_crtc
->config
.has_pch_encoder
)
4461 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4463 intel_disable_pipe(intel_crtc
);
4465 ironlake_pfit_disable(intel_crtc
);
4467 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4468 if (encoder
->post_disable
)
4469 encoder
->post_disable(encoder
);
4471 if (intel_crtc
->config
.has_pch_encoder
) {
4472 ironlake_fdi_disable(crtc
);
4474 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4475 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4477 if (HAS_PCH_CPT(dev
)) {
4478 /* disable TRANS_DP_CTL */
4479 reg
= TRANS_DP_CTL(pipe
);
4480 temp
= I915_READ(reg
);
4481 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4482 TRANS_DP_PORT_SEL_MASK
);
4483 temp
|= TRANS_DP_PORT_SEL_NONE
;
4484 I915_WRITE(reg
, temp
);
4486 /* disable DPLL_SEL */
4487 temp
= I915_READ(PCH_DPLL_SEL
);
4488 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4489 I915_WRITE(PCH_DPLL_SEL
, temp
);
4492 /* disable PCH DPLL */
4493 intel_disable_shared_dpll(intel_crtc
);
4495 ironlake_fdi_pll_disable(intel_crtc
);
4498 intel_crtc
->active
= false;
4499 intel_update_watermarks(crtc
);
4501 mutex_lock(&dev
->struct_mutex
);
4502 intel_update_fbc(dev
);
4503 mutex_unlock(&dev
->struct_mutex
);
4506 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4508 struct drm_device
*dev
= crtc
->dev
;
4509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4511 struct intel_encoder
*encoder
;
4512 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4514 if (!intel_crtc
->active
)
4517 intel_crtc_disable_planes(crtc
);
4519 drm_crtc_vblank_off(crtc
);
4520 assert_vblank_disabled(crtc
);
4522 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4523 intel_opregion_notify_encoder(encoder
, false);
4524 encoder
->disable(encoder
);
4527 if (intel_crtc
->config
.has_pch_encoder
)
4528 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4530 intel_disable_pipe(intel_crtc
);
4532 if (intel_crtc
->config
.dp_encoder_is_mst
)
4533 intel_ddi_set_vc_payload_alloc(crtc
, false);
4535 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4537 ironlake_pfit_disable(intel_crtc
);
4539 intel_ddi_disable_pipe_clock(intel_crtc
);
4541 if (intel_crtc
->config
.has_pch_encoder
) {
4542 lpt_disable_pch_transcoder(dev_priv
);
4543 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4545 intel_ddi_fdi_disable(crtc
);
4548 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4549 if (encoder
->post_disable
)
4550 encoder
->post_disable(encoder
);
4552 intel_crtc
->active
= false;
4553 intel_update_watermarks(crtc
);
4555 mutex_lock(&dev
->struct_mutex
);
4556 intel_update_fbc(dev
);
4557 mutex_unlock(&dev
->struct_mutex
);
4559 if (intel_crtc_to_shared_dpll(intel_crtc
))
4560 intel_disable_shared_dpll(intel_crtc
);
4563 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4565 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4566 intel_put_shared_dpll(intel_crtc
);
4570 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4572 struct drm_device
*dev
= crtc
->base
.dev
;
4573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4574 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4576 if (!crtc
->config
.gmch_pfit
.control
)
4580 * The panel fitter should only be adjusted whilst the pipe is disabled,
4581 * according to register description and PRM.
4583 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4584 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4586 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4587 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4589 /* Border color in case we don't scale up to the full screen. Black by
4590 * default, change to something else for debugging. */
4591 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4594 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4598 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4600 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4602 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4604 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4607 return POWER_DOMAIN_PORT_OTHER
;
4611 #define for_each_power_domain(domain, mask) \
4612 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4613 if ((1 << (domain)) & (mask))
4615 enum intel_display_power_domain
4616 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4618 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4619 struct intel_digital_port
*intel_dig_port
;
4621 switch (intel_encoder
->type
) {
4622 case INTEL_OUTPUT_UNKNOWN
:
4623 /* Only DDI platforms should ever use this output type */
4624 WARN_ON_ONCE(!HAS_DDI(dev
));
4625 case INTEL_OUTPUT_DISPLAYPORT
:
4626 case INTEL_OUTPUT_HDMI
:
4627 case INTEL_OUTPUT_EDP
:
4628 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4629 return port_to_power_domain(intel_dig_port
->port
);
4630 case INTEL_OUTPUT_DP_MST
:
4631 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4632 return port_to_power_domain(intel_dig_port
->port
);
4633 case INTEL_OUTPUT_ANALOG
:
4634 return POWER_DOMAIN_PORT_CRT
;
4635 case INTEL_OUTPUT_DSI
:
4636 return POWER_DOMAIN_PORT_DSI
;
4638 return POWER_DOMAIN_PORT_OTHER
;
4642 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4644 struct drm_device
*dev
= crtc
->dev
;
4645 struct intel_encoder
*intel_encoder
;
4646 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4647 enum pipe pipe
= intel_crtc
->pipe
;
4649 enum transcoder transcoder
;
4651 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4653 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4654 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4655 if (intel_crtc
->config
.pch_pfit
.enabled
||
4656 intel_crtc
->config
.pch_pfit
.force_thru
)
4657 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4659 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4660 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4665 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4668 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4669 struct intel_crtc
*crtc
;
4672 * First get all needed power domains, then put all unneeded, to avoid
4673 * any unnecessary toggling of the power wells.
4675 for_each_intel_crtc(dev
, crtc
) {
4676 enum intel_display_power_domain domain
;
4678 if (!crtc
->base
.enabled
)
4681 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4683 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4684 intel_display_power_get(dev_priv
, domain
);
4687 if (dev_priv
->display
.modeset_global_resources
)
4688 dev_priv
->display
.modeset_global_resources(dev
);
4690 for_each_intel_crtc(dev
, crtc
) {
4691 enum intel_display_power_domain domain
;
4693 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4694 intel_display_power_put(dev_priv
, domain
);
4696 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4699 intel_display_set_init_power(dev_priv
, false);
4702 /* returns HPLL frequency in kHz */
4703 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4705 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4707 /* Obtain SKU information */
4708 mutex_lock(&dev_priv
->dpio_lock
);
4709 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4710 CCK_FUSE_HPLL_FREQ_MASK
;
4711 mutex_unlock(&dev_priv
->dpio_lock
);
4713 return vco_freq
[hpll_freq
] * 1000;
4716 static void vlv_update_cdclk(struct drm_device
*dev
)
4718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4720 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4721 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4722 dev_priv
->vlv_cdclk_freq
);
4725 * Program the gmbus_freq based on the cdclk frequency.
4726 * BSpec erroneously claims we should aim for 4MHz, but
4727 * in fact 1MHz is the correct frequency.
4729 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
4732 /* Adjust CDclk dividers to allow high res or save power if possible */
4733 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4740 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4742 else if (cdclk
== 266667)
4747 mutex_lock(&dev_priv
->rps
.hw_lock
);
4748 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4749 val
&= ~DSPFREQGUAR_MASK
;
4750 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4751 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4752 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4753 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4755 DRM_ERROR("timed out waiting for CDclk change\n");
4757 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4759 if (cdclk
== 400000) {
4762 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
4764 mutex_lock(&dev_priv
->dpio_lock
);
4765 /* adjust cdclk divider */
4766 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4767 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4769 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4771 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4772 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4774 DRM_ERROR("timed out waiting for CDclk change\n");
4775 mutex_unlock(&dev_priv
->dpio_lock
);
4778 mutex_lock(&dev_priv
->dpio_lock
);
4779 /* adjust self-refresh exit latency value */
4780 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4784 * For high bandwidth configs, we set a higher latency in the bunit
4785 * so that the core display fetch happens in time to avoid underruns.
4787 if (cdclk
== 400000)
4788 val
|= 4500 / 250; /* 4.5 usec */
4790 val
|= 3000 / 250; /* 3.0 usec */
4791 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4792 mutex_unlock(&dev_priv
->dpio_lock
);
4794 vlv_update_cdclk(dev
);
4797 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4802 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4823 mutex_lock(&dev_priv
->rps
.hw_lock
);
4824 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4825 val
&= ~DSPFREQGUAR_MASK_CHV
;
4826 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4827 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4828 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4829 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4831 DRM_ERROR("timed out waiting for CDclk change\n");
4833 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4835 vlv_update_cdclk(dev
);
4838 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4841 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
4843 /* FIXME: Punit isn't quite ready yet */
4844 if (IS_CHERRYVIEW(dev_priv
->dev
))
4848 * Really only a few cases to deal with, as only 4 CDclks are supported:
4851 * 320/333MHz (depends on HPLL freq)
4853 * So we check to see whether we're above 90% of the lower bin and
4856 * We seem to get an unstable or solid color picture at 200MHz.
4857 * Not sure what's wrong. For now use 200MHz only when all pipes
4860 if (max_pixclk
> freq_320
*9/10)
4862 else if (max_pixclk
> 266667*9/10)
4864 else if (max_pixclk
> 0)
4870 /* compute the max pixel clock for new configuration */
4871 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4873 struct drm_device
*dev
= dev_priv
->dev
;
4874 struct intel_crtc
*intel_crtc
;
4877 for_each_intel_crtc(dev
, intel_crtc
) {
4878 if (intel_crtc
->new_enabled
)
4879 max_pixclk
= max(max_pixclk
,
4880 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4886 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4887 unsigned *prepare_pipes
)
4889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4890 struct intel_crtc
*intel_crtc
;
4891 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4893 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4894 dev_priv
->vlv_cdclk_freq
)
4897 /* disable/enable all currently active pipes while we change cdclk */
4898 for_each_intel_crtc(dev
, intel_crtc
)
4899 if (intel_crtc
->base
.enabled
)
4900 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4903 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4906 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4907 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4909 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4910 if (IS_CHERRYVIEW(dev
))
4911 cherryview_set_cdclk(dev
, req_cdclk
);
4913 valleyview_set_cdclk(dev
, req_cdclk
);
4917 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4919 struct drm_device
*dev
= crtc
->dev
;
4920 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4922 struct intel_encoder
*encoder
;
4923 int pipe
= intel_crtc
->pipe
;
4926 WARN_ON(!crtc
->enabled
);
4928 if (intel_crtc
->active
)
4931 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
4934 if (IS_CHERRYVIEW(dev
))
4935 chv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
4937 vlv_prepare_pll(intel_crtc
, &intel_crtc
->config
);
4940 if (intel_crtc
->config
.has_dp_encoder
)
4941 intel_dp_set_m_n(intel_crtc
);
4943 intel_set_pipe_timings(intel_crtc
);
4945 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
4946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4948 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
4949 I915_WRITE(CHV_CANVAS(pipe
), 0);
4952 i9xx_set_pipeconf(intel_crtc
);
4954 intel_crtc
->active
= true;
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4958 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4959 if (encoder
->pre_pll_enable
)
4960 encoder
->pre_pll_enable(encoder
);
4963 if (IS_CHERRYVIEW(dev
))
4964 chv_enable_pll(intel_crtc
, &intel_crtc
->config
);
4966 vlv_enable_pll(intel_crtc
, &intel_crtc
->config
);
4969 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4970 if (encoder
->pre_enable
)
4971 encoder
->pre_enable(encoder
);
4973 i9xx_pfit_enable(intel_crtc
);
4975 intel_crtc_load_lut(crtc
);
4977 intel_update_watermarks(crtc
);
4978 intel_enable_pipe(intel_crtc
);
4980 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4981 encoder
->enable(encoder
);
4983 assert_vblank_disabled(crtc
);
4984 drm_crtc_vblank_on(crtc
);
4986 intel_crtc_enable_planes(crtc
);
4988 /* Underruns don't raise interrupts, so check manually. */
4989 i9xx_check_fifo_underruns(dev_priv
);
4992 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4994 struct drm_device
*dev
= crtc
->base
.dev
;
4995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4997 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4998 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
5001 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5003 struct drm_device
*dev
= crtc
->dev
;
5004 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5005 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5006 struct intel_encoder
*encoder
;
5007 int pipe
= intel_crtc
->pipe
;
5009 WARN_ON(!crtc
->enabled
);
5011 if (intel_crtc
->active
)
5014 i9xx_set_pll_dividers(intel_crtc
);
5016 if (intel_crtc
->config
.has_dp_encoder
)
5017 intel_dp_set_m_n(intel_crtc
);
5019 intel_set_pipe_timings(intel_crtc
);
5021 i9xx_set_pipeconf(intel_crtc
);
5023 intel_crtc
->active
= true;
5026 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5028 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5029 if (encoder
->pre_enable
)
5030 encoder
->pre_enable(encoder
);
5032 i9xx_enable_pll(intel_crtc
);
5034 i9xx_pfit_enable(intel_crtc
);
5036 intel_crtc_load_lut(crtc
);
5038 intel_update_watermarks(crtc
);
5039 intel_enable_pipe(intel_crtc
);
5041 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5042 encoder
->enable(encoder
);
5044 assert_vblank_disabled(crtc
);
5045 drm_crtc_vblank_on(crtc
);
5047 intel_crtc_enable_planes(crtc
);
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5059 /* Underruns don't raise interrupts, so check manually. */
5060 i9xx_check_fifo_underruns(dev_priv
);
5063 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5065 struct drm_device
*dev
= crtc
->base
.dev
;
5066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5068 if (!crtc
->config
.gmch_pfit
.control
)
5071 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5073 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074 I915_READ(PFIT_CONTROL
));
5075 I915_WRITE(PFIT_CONTROL
, 0);
5078 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5080 struct drm_device
*dev
= crtc
->dev
;
5081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5083 struct intel_encoder
*encoder
;
5084 int pipe
= intel_crtc
->pipe
;
5086 if (!intel_crtc
->active
)
5090 * Gen2 reports pipe underruns whenever all planes are disabled.
5091 * So diasble underrun reporting before all the planes get disabled.
5092 * FIXME: Need to fix the logic to work when we turn off all planes
5093 * but leave the pipe running.
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5099 * Vblank time updates from the shadow to live plane control register
5100 * are blocked if the memory self-refresh mode is active at that
5101 * moment. So to make sure the plane gets truly disabled, disable
5102 * first the self-refresh mode. The self-refresh enable bit in turn
5103 * will be checked/applied by the HW only at the next frame start
5104 * event which is after the vblank start event, so we need to have a
5105 * wait-for-vblank between disabling the plane and the pipe.
5107 intel_set_memory_cxsr(dev_priv
, false);
5108 intel_crtc_disable_planes(crtc
);
5111 * On gen2 planes are double buffered but the pipe isn't, so we must
5112 * wait for planes to fully turn off before disabling the pipe.
5113 * We also need to wait on all gmch platforms because of the
5114 * self-refresh mode constraint explained above.
5116 intel_wait_for_vblank(dev
, pipe
);
5118 drm_crtc_vblank_off(crtc
);
5119 assert_vblank_disabled(crtc
);
5121 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5122 encoder
->disable(encoder
);
5124 intel_disable_pipe(intel_crtc
);
5126 i9xx_pfit_disable(intel_crtc
);
5128 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5129 if (encoder
->post_disable
)
5130 encoder
->post_disable(encoder
);
5132 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5133 if (IS_CHERRYVIEW(dev
))
5134 chv_disable_pll(dev_priv
, pipe
);
5135 else if (IS_VALLEYVIEW(dev
))
5136 vlv_disable_pll(dev_priv
, pipe
);
5138 i9xx_disable_pll(intel_crtc
);
5142 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5144 intel_crtc
->active
= false;
5145 intel_update_watermarks(crtc
);
5147 mutex_lock(&dev
->struct_mutex
);
5148 intel_update_fbc(dev
);
5149 mutex_unlock(&dev
->struct_mutex
);
5152 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5156 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
5159 struct drm_device
*dev
= crtc
->dev
;
5160 struct drm_i915_master_private
*master_priv
;
5161 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5162 int pipe
= intel_crtc
->pipe
;
5164 if (!dev
->primary
->master
)
5167 master_priv
= dev
->primary
->master
->driver_priv
;
5168 if (!master_priv
->sarea_priv
)
5173 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5174 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5177 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
5178 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
5181 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
5186 /* Master function to enable/disable CRTC and corresponding power wells */
5187 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5189 struct drm_device
*dev
= crtc
->dev
;
5190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5191 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5192 enum intel_display_power_domain domain
;
5193 unsigned long domains
;
5196 if (!intel_crtc
->active
) {
5197 domains
= get_crtc_power_domains(crtc
);
5198 for_each_power_domain(domain
, domains
)
5199 intel_display_power_get(dev_priv
, domain
);
5200 intel_crtc
->enabled_power_domains
= domains
;
5202 dev_priv
->display
.crtc_enable(crtc
);
5205 if (intel_crtc
->active
) {
5206 dev_priv
->display
.crtc_disable(crtc
);
5208 domains
= intel_crtc
->enabled_power_domains
;
5209 for_each_power_domain(domain
, domains
)
5210 intel_display_power_put(dev_priv
, domain
);
5211 intel_crtc
->enabled_power_domains
= 0;
5217 * Sets the power management mode of the pipe and plane.
5219 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5221 struct drm_device
*dev
= crtc
->dev
;
5222 struct intel_encoder
*intel_encoder
;
5223 bool enable
= false;
5225 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5226 enable
|= intel_encoder
->connectors_active
;
5228 intel_crtc_control(crtc
, enable
);
5230 intel_crtc_update_sarea(crtc
, enable
);
5233 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5235 struct drm_device
*dev
= crtc
->dev
;
5236 struct drm_connector
*connector
;
5237 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5238 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5239 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5241 /* crtc should still be enabled when we disable it. */
5242 WARN_ON(!crtc
->enabled
);
5244 dev_priv
->display
.crtc_disable(crtc
);
5245 intel_crtc_update_sarea(crtc
, false);
5246 dev_priv
->display
.off(crtc
);
5248 if (crtc
->primary
->fb
) {
5249 mutex_lock(&dev
->struct_mutex
);
5250 intel_unpin_fb_obj(old_obj
);
5251 i915_gem_track_fb(old_obj
, NULL
,
5252 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5253 mutex_unlock(&dev
->struct_mutex
);
5254 crtc
->primary
->fb
= NULL
;
5257 /* Update computed state. */
5258 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5259 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5262 if (connector
->encoder
->crtc
!= crtc
)
5265 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5266 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5270 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5272 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5274 drm_encoder_cleanup(encoder
);
5275 kfree(intel_encoder
);
5278 /* Simple dpms helper for encoders with just one connector, no cloning and only
5279 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280 * state of the entire output pipe. */
5281 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5283 if (mode
== DRM_MODE_DPMS_ON
) {
5284 encoder
->connectors_active
= true;
5286 intel_crtc_update_dpms(encoder
->base
.crtc
);
5288 encoder
->connectors_active
= false;
5290 intel_crtc_update_dpms(encoder
->base
.crtc
);
5294 /* Cross check the actual hw state with our own modeset state tracking (and it's
5295 * internal consistency). */
5296 static void intel_connector_check_state(struct intel_connector
*connector
)
5298 if (connector
->get_hw_state(connector
)) {
5299 struct intel_encoder
*encoder
= connector
->encoder
;
5300 struct drm_crtc
*crtc
;
5301 bool encoder_enabled
;
5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305 connector
->base
.base
.id
,
5306 connector
->base
.name
);
5308 /* there is no real hw state for MST connectors */
5309 if (connector
->mst_port
)
5312 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5313 "wrong connector dpms state\n");
5314 WARN(connector
->base
.encoder
!= &encoder
->base
,
5315 "active connector not linked to encoder\n");
5318 WARN(!encoder
->connectors_active
,
5319 "encoder->connectors_active not set\n");
5321 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5322 WARN(!encoder_enabled
, "encoder not enabled\n");
5323 if (WARN_ON(!encoder
->base
.crtc
))
5326 crtc
= encoder
->base
.crtc
;
5328 WARN(!crtc
->enabled
, "crtc not enabled\n");
5329 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5330 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5331 "encoder active on the wrong pipe\n");
5336 /* Even simpler default implementation, if there's really no special case to
5338 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5340 /* All the simple cases only support two dpms states. */
5341 if (mode
!= DRM_MODE_DPMS_ON
)
5342 mode
= DRM_MODE_DPMS_OFF
;
5344 if (mode
== connector
->dpms
)
5347 connector
->dpms
= mode
;
5349 /* Only need to change hw state when actually enabled */
5350 if (connector
->encoder
)
5351 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5353 intel_modeset_check_state(connector
->dev
);
5356 /* Simple connector->get_hw_state implementation for encoders that support only
5357 * one connector and no cloning and hence the encoder state determines the state
5358 * of the connector. */
5359 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5362 struct intel_encoder
*encoder
= connector
->encoder
;
5364 return encoder
->get_hw_state(encoder
, &pipe
);
5367 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5368 struct intel_crtc_config
*pipe_config
)
5370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5371 struct intel_crtc
*pipe_B_crtc
=
5372 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5376 if (pipe_config
->fdi_lanes
> 4) {
5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5382 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5383 if (pipe_config
->fdi_lanes
> 2) {
5384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385 pipe_config
->fdi_lanes
);
5392 if (INTEL_INFO(dev
)->num_pipes
== 2)
5395 /* Ivybridge 3 pipe is really complicated */
5400 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5401 pipe_config
->fdi_lanes
> 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5408 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5409 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5410 if (pipe_config
->fdi_lanes
> 2) {
5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5426 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5427 struct intel_crtc_config
*pipe_config
)
5429 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5430 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5431 int lane
, link_bw
, fdi_dotclock
;
5432 bool setup_ok
, needs_recompute
= false;
5435 /* FDI is a binary signal running at ~2.7GHz, encoding
5436 * each output octet as 10 bits. The actual frequency
5437 * is stored as a divider into a 100MHz clock, and the
5438 * mode pixel clock is stored in units of 1KHz.
5439 * Hence the bw of each lane in terms of the mode signal
5442 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5444 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5446 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5447 pipe_config
->pipe_bpp
);
5449 pipe_config
->fdi_lanes
= lane
;
5451 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5452 link_bw
, &pipe_config
->fdi_m_n
);
5454 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5455 intel_crtc
->pipe
, pipe_config
);
5456 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5457 pipe_config
->pipe_bpp
-= 2*3;
5458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459 pipe_config
->pipe_bpp
);
5460 needs_recompute
= true;
5461 pipe_config
->bw_constrained
= true;
5466 if (needs_recompute
)
5469 return setup_ok
? 0 : -EINVAL
;
5472 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5473 struct intel_crtc_config
*pipe_config
)
5475 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5476 hsw_crtc_supports_ips(crtc
) &&
5477 pipe_config
->pipe_bpp
<= 24;
5480 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5481 struct intel_crtc_config
*pipe_config
)
5483 struct drm_device
*dev
= crtc
->base
.dev
;
5484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5485 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5487 /* FIXME should check pixel clock limits on all platforms */
5488 if (INTEL_INFO(dev
)->gen
< 4) {
5490 dev_priv
->display
.get_display_clock_speed(dev
);
5493 * Enable pixel doubling when the dot clock
5494 * is > 90% of the (display) core speed.
5496 * GDG double wide on either pipe,
5497 * otherwise pipe A only.
5499 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5500 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5502 pipe_config
->double_wide
= true;
5505 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5510 * Pipe horizontal size must be even in:
5512 * - LVDS dual channel mode
5513 * - Double wide pipe
5515 if ((intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5516 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5517 pipe_config
->pipe_src_w
&= ~1;
5519 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5522 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5523 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5526 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5527 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5528 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5529 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5531 pipe_config
->pipe_bpp
= 8*3;
5535 hsw_compute_ips_config(crtc
, pipe_config
);
5537 if (pipe_config
->has_pch_encoder
)
5538 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5543 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5549 /* FIXME: Punit isn't quite ready yet */
5550 if (IS_CHERRYVIEW(dev
))
5553 if (dev_priv
->hpll_freq
== 0)
5554 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5556 mutex_lock(&dev_priv
->dpio_lock
);
5557 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5558 mutex_unlock(&dev_priv
->dpio_lock
);
5560 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5562 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5563 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5564 "cdclk change in progress\n");
5566 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5569 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5574 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5579 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5584 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5588 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5590 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5591 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5593 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5595 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5597 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5600 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5601 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5603 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5608 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5612 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5614 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5617 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5618 case GC_DISPLAY_CLOCK_333_MHZ
:
5621 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5627 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5632 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5635 /* Assume that the hardware is in the high speed state. This
5636 * should be the default.
5638 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5639 case GC_CLOCK_133_200
:
5640 case GC_CLOCK_100_200
:
5642 case GC_CLOCK_166_250
:
5644 case GC_CLOCK_100_133
:
5648 /* Shouldn't happen */
5652 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5658 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5660 while (*num
> DATA_LINK_M_N_MASK
||
5661 *den
> DATA_LINK_M_N_MASK
) {
5667 static void compute_m_n(unsigned int m
, unsigned int n
,
5668 uint32_t *ret_m
, uint32_t *ret_n
)
5670 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5671 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5672 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5676 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5677 int pixel_clock
, int link_clock
,
5678 struct intel_link_m_n
*m_n
)
5682 compute_m_n(bits_per_pixel
* pixel_clock
,
5683 link_clock
* nlanes
* 8,
5684 &m_n
->gmch_m
, &m_n
->gmch_n
);
5686 compute_m_n(pixel_clock
, link_clock
,
5687 &m_n
->link_m
, &m_n
->link_n
);
5690 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5692 if (i915
.panel_use_ssc
>= 0)
5693 return i915
.panel_use_ssc
!= 0;
5694 return dev_priv
->vbt
.lvds_use_ssc
5695 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5698 static int i9xx_get_refclk(struct intel_crtc
*crtc
, int num_connectors
)
5700 struct drm_device
*dev
= crtc
->base
.dev
;
5701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5704 if (IS_VALLEYVIEW(dev
)) {
5706 } else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5707 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5708 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5709 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5710 } else if (!IS_GEN2(dev
)) {
5719 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5721 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5724 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5726 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5729 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5730 intel_clock_t
*reduced_clock
)
5732 struct drm_device
*dev
= crtc
->base
.dev
;
5735 if (IS_PINEVIEW(dev
)) {
5736 fp
= pnv_dpll_compute_fp(&crtc
->new_config
->dpll
);
5738 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5740 fp
= i9xx_dpll_compute_fp(&crtc
->new_config
->dpll
);
5742 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5745 crtc
->new_config
->dpll_hw_state
.fp0
= fp
;
5747 crtc
->lowfreq_avail
= false;
5748 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5749 reduced_clock
&& i915
.powersave
) {
5750 crtc
->new_config
->dpll_hw_state
.fp1
= fp2
;
5751 crtc
->lowfreq_avail
= true;
5753 crtc
->new_config
->dpll_hw_state
.fp1
= fp
;
5757 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5763 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5764 * and set it to a reasonable value instead.
5766 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5767 reg_val
&= 0xffffff00;
5768 reg_val
|= 0x00000030;
5769 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5771 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5772 reg_val
&= 0x8cffffff;
5773 reg_val
= 0x8c000000;
5774 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5776 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5777 reg_val
&= 0xffffff00;
5778 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5780 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5781 reg_val
&= 0x00ffffff;
5782 reg_val
|= 0xb0000000;
5783 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5786 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5787 struct intel_link_m_n
*m_n
)
5789 struct drm_device
*dev
= crtc
->base
.dev
;
5790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5791 int pipe
= crtc
->pipe
;
5793 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5794 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5795 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5796 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5799 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5800 struct intel_link_m_n
*m_n
,
5801 struct intel_link_m_n
*m2_n2
)
5803 struct drm_device
*dev
= crtc
->base
.dev
;
5804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5805 int pipe
= crtc
->pipe
;
5806 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5808 if (INTEL_INFO(dev
)->gen
>= 5) {
5809 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5810 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5811 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5812 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5813 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5814 * for gen < 8) and if DRRS is supported (to make sure the
5815 * registers are not unnecessarily accessed).
5817 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5818 crtc
->config
.has_drrs
) {
5819 I915_WRITE(PIPE_DATA_M2(transcoder
),
5820 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5821 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5822 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5823 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5826 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5827 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5828 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5829 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5833 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5835 if (crtc
->config
.has_pch_encoder
)
5836 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5838 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5839 &crtc
->config
.dp_m2_n2
);
5842 static void vlv_update_pll(struct intel_crtc
*crtc
,
5843 struct intel_crtc_config
*pipe_config
)
5848 * Enable DPIO clock input. We should never disable the reference
5849 * clock for pipe B, since VGA hotplug / manual detection depends
5852 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5853 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5854 /* We should never disable this, set it here for state tracking */
5855 if (crtc
->pipe
== PIPE_B
)
5856 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5857 dpll
|= DPLL_VCO_ENABLE
;
5858 pipe_config
->dpll_hw_state
.dpll
= dpll
;
5860 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
5861 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5862 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
5865 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
5866 const struct intel_crtc_config
*pipe_config
)
5868 struct drm_device
*dev
= crtc
->base
.dev
;
5869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5870 int pipe
= crtc
->pipe
;
5872 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5873 u32 coreclk
, reg_val
;
5875 mutex_lock(&dev_priv
->dpio_lock
);
5877 bestn
= pipe_config
->dpll
.n
;
5878 bestm1
= pipe_config
->dpll
.m1
;
5879 bestm2
= pipe_config
->dpll
.m2
;
5880 bestp1
= pipe_config
->dpll
.p1
;
5881 bestp2
= pipe_config
->dpll
.p2
;
5883 /* See eDP HDMI DPIO driver vbios notes doc */
5885 /* PLL B needs special handling */
5887 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5889 /* Set up Tx target for periodic Rcomp update */
5890 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5892 /* Disable target IRef on PLL */
5893 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5894 reg_val
&= 0x00ffffff;
5895 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5897 /* Disable fast lock */
5898 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5900 /* Set idtafcrecal before PLL is enabled */
5901 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5902 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5903 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5904 mdiv
|= (1 << DPIO_K_SHIFT
);
5907 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5908 * but we don't support that).
5909 * Note: don't use the DAC post divider as it seems unstable.
5911 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5912 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5914 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5915 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5917 /* Set HBR and RBR LPF coefficients */
5918 if (pipe_config
->port_clock
== 162000 ||
5919 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
5920 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
5921 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5924 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5927 if (crtc
->config
.has_dp_encoder
) {
5928 /* Use SSC source */
5930 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5933 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5935 } else { /* HDMI or VGA */
5936 /* Use bend source */
5938 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5941 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5945 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5946 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5947 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
5948 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
5949 coreclk
|= 0x01000000;
5950 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5952 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5953 mutex_unlock(&dev_priv
->dpio_lock
);
5956 static void chv_update_pll(struct intel_crtc
*crtc
,
5957 struct intel_crtc_config
*pipe_config
)
5959 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5960 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5962 if (crtc
->pipe
!= PIPE_A
)
5963 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5965 pipe_config
->dpll_hw_state
.dpll_md
=
5966 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5969 static void chv_prepare_pll(struct intel_crtc
*crtc
,
5970 const struct intel_crtc_config
*pipe_config
)
5972 struct drm_device
*dev
= crtc
->base
.dev
;
5973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5974 int pipe
= crtc
->pipe
;
5975 int dpll_reg
= DPLL(crtc
->pipe
);
5976 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5977 u32 loopfilter
, intcoeff
;
5978 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5981 bestn
= pipe_config
->dpll
.n
;
5982 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
5983 bestm1
= pipe_config
->dpll
.m1
;
5984 bestm2
= pipe_config
->dpll
.m2
>> 22;
5985 bestp1
= pipe_config
->dpll
.p1
;
5986 bestp2
= pipe_config
->dpll
.p2
;
5989 * Enable Refclk and SSC
5991 I915_WRITE(dpll_reg
,
5992 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5994 mutex_lock(&dev_priv
->dpio_lock
);
5996 /* p1 and p2 divider */
5997 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5998 5 << DPIO_CHV_S1_DIV_SHIFT
|
5999 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6000 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6001 1 << DPIO_CHV_K_DIV_SHIFT
);
6003 /* Feedback post-divider - m2 */
6004 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6006 /* Feedback refclk divider - n and m1 */
6007 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6008 DPIO_CHV_M1_DIV_BY_2
|
6009 1 << DPIO_CHV_N_DIV_SHIFT
);
6011 /* M2 fraction division */
6012 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6014 /* M2 fraction division enable */
6015 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
6016 DPIO_CHV_FRAC_DIV_EN
|
6017 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
6020 refclk
= i9xx_get_refclk(crtc
, 0);
6021 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
6022 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
6023 if (refclk
== 100000)
6025 else if (refclk
== 38400)
6029 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
6030 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6033 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6034 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6037 mutex_unlock(&dev_priv
->dpio_lock
);
6041 * vlv_force_pll_on - forcibly enable just the PLL
6042 * @dev_priv: i915 private structure
6043 * @pipe: pipe PLL to enable
6044 * @dpll: PLL configuration
6046 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6047 * in cases where we need the PLL enabled even when @pipe is not going to
6050 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6051 const struct dpll
*dpll
)
6053 struct intel_crtc
*crtc
=
6054 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6055 struct intel_crtc_config pipe_config
= {
6056 .pixel_multiplier
= 1,
6060 if (IS_CHERRYVIEW(dev
)) {
6061 chv_update_pll(crtc
, &pipe_config
);
6062 chv_prepare_pll(crtc
, &pipe_config
);
6063 chv_enable_pll(crtc
, &pipe_config
);
6065 vlv_update_pll(crtc
, &pipe_config
);
6066 vlv_prepare_pll(crtc
, &pipe_config
);
6067 vlv_enable_pll(crtc
, &pipe_config
);
6072 * vlv_force_pll_off - forcibly disable just the PLL
6073 * @dev_priv: i915 private structure
6074 * @pipe: pipe PLL to disable
6076 * Disable the PLL for @pipe. To be used in cases where we need
6077 * the PLL enabled even when @pipe is not going to be enabled.
6079 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6081 if (IS_CHERRYVIEW(dev
))
6082 chv_disable_pll(to_i915(dev
), pipe
);
6084 vlv_disable_pll(to_i915(dev
), pipe
);
6087 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6088 intel_clock_t
*reduced_clock
,
6091 struct drm_device
*dev
= crtc
->base
.dev
;
6092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6095 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6097 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6099 is_sdvo
= intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_SDVO
) ||
6100 intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_HDMI
);
6102 dpll
= DPLL_VGA_MODE_DIS
;
6104 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
))
6105 dpll
|= DPLLB_MODE_LVDS
;
6107 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6109 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6110 dpll
|= (crtc
->new_config
->pixel_multiplier
- 1)
6111 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6115 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6117 if (crtc
->new_config
->has_dp_encoder
)
6118 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6120 /* compute bitmask from p1 value */
6121 if (IS_PINEVIEW(dev
))
6122 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6124 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6125 if (IS_G4X(dev
) && reduced_clock
)
6126 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6128 switch (clock
->p2
) {
6130 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6133 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6136 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6139 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6142 if (INTEL_INFO(dev
)->gen
>= 4)
6143 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6145 if (crtc
->new_config
->sdvo_tv_clock
)
6146 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6147 else if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6148 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6149 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6151 dpll
|= PLL_REF_INPUT_DREFCLK
;
6153 dpll
|= DPLL_VCO_ENABLE
;
6154 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6156 if (INTEL_INFO(dev
)->gen
>= 4) {
6157 u32 dpll_md
= (crtc
->new_config
->pixel_multiplier
- 1)
6158 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6159 crtc
->new_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6163 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6164 intel_clock_t
*reduced_clock
,
6167 struct drm_device
*dev
= crtc
->base
.dev
;
6168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6170 struct dpll
*clock
= &crtc
->new_config
->dpll
;
6172 i9xx_update_pll_dividers(crtc
, reduced_clock
);
6174 dpll
= DPLL_VGA_MODE_DIS
;
6176 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
)) {
6177 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6180 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6182 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6184 dpll
|= PLL_P2_DIVIDE_BY_4
;
6187 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_DVO
))
6188 dpll
|= DPLL_DVO_2X_MODE
;
6190 if (intel_pipe_will_have_type(crtc
, INTEL_OUTPUT_LVDS
) &&
6191 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6192 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6194 dpll
|= PLL_REF_INPUT_DREFCLK
;
6196 dpll
|= DPLL_VCO_ENABLE
;
6197 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
6200 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6202 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6204 enum pipe pipe
= intel_crtc
->pipe
;
6205 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6206 struct drm_display_mode
*adjusted_mode
=
6207 &intel_crtc
->config
.adjusted_mode
;
6208 uint32_t crtc_vtotal
, crtc_vblank_end
;
6211 /* We need to be careful not to changed the adjusted mode, for otherwise
6212 * the hw state checker will get angry at the mismatch. */
6213 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6214 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6216 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6217 /* the chip adds 2 halflines automatically */
6219 crtc_vblank_end
-= 1;
6221 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6222 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6224 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6225 adjusted_mode
->crtc_htotal
/ 2;
6227 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6230 if (INTEL_INFO(dev
)->gen
> 3)
6231 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6233 I915_WRITE(HTOTAL(cpu_transcoder
),
6234 (adjusted_mode
->crtc_hdisplay
- 1) |
6235 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6236 I915_WRITE(HBLANK(cpu_transcoder
),
6237 (adjusted_mode
->crtc_hblank_start
- 1) |
6238 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6239 I915_WRITE(HSYNC(cpu_transcoder
),
6240 (adjusted_mode
->crtc_hsync_start
- 1) |
6241 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6243 I915_WRITE(VTOTAL(cpu_transcoder
),
6244 (adjusted_mode
->crtc_vdisplay
- 1) |
6245 ((crtc_vtotal
- 1) << 16));
6246 I915_WRITE(VBLANK(cpu_transcoder
),
6247 (adjusted_mode
->crtc_vblank_start
- 1) |
6248 ((crtc_vblank_end
- 1) << 16));
6249 I915_WRITE(VSYNC(cpu_transcoder
),
6250 (adjusted_mode
->crtc_vsync_start
- 1) |
6251 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6253 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6254 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6255 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6257 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6258 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6259 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6261 /* pipesrc controls the size that is scaled from, which should
6262 * always be the user's requested size.
6264 I915_WRITE(PIPESRC(pipe
),
6265 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6266 (intel_crtc
->config
.pipe_src_h
- 1));
6269 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6270 struct intel_crtc_config
*pipe_config
)
6272 struct drm_device
*dev
= crtc
->base
.dev
;
6273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6274 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6277 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6278 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6279 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6280 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6281 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6282 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6283 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6284 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6285 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6287 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6288 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6289 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6290 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6291 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6292 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6293 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6294 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6295 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6297 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6298 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6299 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6300 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6303 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6304 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6305 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6307 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6308 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6311 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6312 struct intel_crtc_config
*pipe_config
)
6314 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6315 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6316 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6317 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6319 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6320 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6321 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6322 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6324 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6326 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6327 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6330 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6332 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6338 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6339 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6340 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6342 if (intel_crtc
->config
.double_wide
)
6343 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6345 /* only g4x and later have fancy bpc/dither controls */
6346 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6347 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6348 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6349 pipeconf
|= PIPECONF_DITHER_EN
|
6350 PIPECONF_DITHER_TYPE_SP
;
6352 switch (intel_crtc
->config
.pipe_bpp
) {
6354 pipeconf
|= PIPECONF_6BPC
;
6357 pipeconf
|= PIPECONF_8BPC
;
6360 pipeconf
|= PIPECONF_10BPC
;
6363 /* Case prevented by intel_choose_pipe_bpp_dither. */
6368 if (HAS_PIPE_CXSR(dev
)) {
6369 if (intel_crtc
->lowfreq_avail
) {
6370 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6371 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6373 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6377 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6378 if (INTEL_INFO(dev
)->gen
< 4 ||
6379 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6380 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6382 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6384 pipeconf
|= PIPECONF_PROGRESSIVE
;
6386 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6387 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6389 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6390 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6393 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
)
6395 struct drm_device
*dev
= crtc
->base
.dev
;
6396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6397 int refclk
, num_connectors
= 0;
6398 intel_clock_t clock
, reduced_clock
;
6399 bool ok
, has_reduced_clock
= false;
6400 bool is_lvds
= false, is_dsi
= false;
6401 struct intel_encoder
*encoder
;
6402 const intel_limit_t
*limit
;
6404 for_each_intel_encoder(dev
, encoder
) {
6405 if (encoder
->new_crtc
!= crtc
)
6408 switch (encoder
->type
) {
6409 case INTEL_OUTPUT_LVDS
:
6412 case INTEL_OUTPUT_DSI
:
6425 if (!crtc
->new_config
->clock_set
) {
6426 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6429 * Returns a set of divisors for the desired target clock with
6430 * the given refclk, or FALSE. The returned values represent
6431 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6434 limit
= intel_limit(crtc
, refclk
);
6435 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6436 crtc
->new_config
->port_clock
,
6437 refclk
, NULL
, &clock
);
6439 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6443 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6445 * Ensure we match the reduced clock's P to the target
6446 * clock. If the clocks don't match, we can't switch
6447 * the display clock by using the FP0/FP1. In such case
6448 * we will disable the LVDS downclock feature.
6451 dev_priv
->display
.find_dpll(limit
, crtc
,
6452 dev_priv
->lvds_downclock
,
6456 /* Compat-code for transition, will disappear. */
6457 crtc
->new_config
->dpll
.n
= clock
.n
;
6458 crtc
->new_config
->dpll
.m1
= clock
.m1
;
6459 crtc
->new_config
->dpll
.m2
= clock
.m2
;
6460 crtc
->new_config
->dpll
.p1
= clock
.p1
;
6461 crtc
->new_config
->dpll
.p2
= clock
.p2
;
6465 i8xx_update_pll(crtc
,
6466 has_reduced_clock
? &reduced_clock
: NULL
,
6468 } else if (IS_CHERRYVIEW(dev
)) {
6469 chv_update_pll(crtc
, crtc
->new_config
);
6470 } else if (IS_VALLEYVIEW(dev
)) {
6471 vlv_update_pll(crtc
, crtc
->new_config
);
6473 i9xx_update_pll(crtc
,
6474 has_reduced_clock
? &reduced_clock
: NULL
,
6481 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6482 struct intel_crtc_config
*pipe_config
)
6484 struct drm_device
*dev
= crtc
->base
.dev
;
6485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6488 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6491 tmp
= I915_READ(PFIT_CONTROL
);
6492 if (!(tmp
& PFIT_ENABLE
))
6495 /* Check whether the pfit is attached to our pipe. */
6496 if (INTEL_INFO(dev
)->gen
< 4) {
6497 if (crtc
->pipe
!= PIPE_B
)
6500 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6504 pipe_config
->gmch_pfit
.control
= tmp
;
6505 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6506 if (INTEL_INFO(dev
)->gen
< 5)
6507 pipe_config
->gmch_pfit
.lvds_border_bits
=
6508 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6511 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6512 struct intel_crtc_config
*pipe_config
)
6514 struct drm_device
*dev
= crtc
->base
.dev
;
6515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6516 int pipe
= pipe_config
->cpu_transcoder
;
6517 intel_clock_t clock
;
6519 int refclk
= 100000;
6521 /* In case of MIPI DPLL will not even be used */
6522 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6525 mutex_lock(&dev_priv
->dpio_lock
);
6526 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6527 mutex_unlock(&dev_priv
->dpio_lock
);
6529 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6530 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6531 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6532 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6533 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6535 vlv_clock(refclk
, &clock
);
6537 /* clock.dot is the fast clock */
6538 pipe_config
->port_clock
= clock
.dot
/ 5;
6541 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6542 struct intel_plane_config
*plane_config
)
6544 struct drm_device
*dev
= crtc
->base
.dev
;
6545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6546 u32 val
, base
, offset
;
6547 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6548 int fourcc
, pixel_format
;
6551 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6552 if (!crtc
->base
.primary
->fb
) {
6553 DRM_DEBUG_KMS("failed to alloc fb\n");
6557 val
= I915_READ(DSPCNTR(plane
));
6559 if (INTEL_INFO(dev
)->gen
>= 4)
6560 if (val
& DISPPLANE_TILED
)
6561 plane_config
->tiled
= true;
6563 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6564 fourcc
= intel_format_to_fourcc(pixel_format
);
6565 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6566 crtc
->base
.primary
->fb
->bits_per_pixel
=
6567 drm_format_plane_cpp(fourcc
, 0) * 8;
6569 if (INTEL_INFO(dev
)->gen
>= 4) {
6570 if (plane_config
->tiled
)
6571 offset
= I915_READ(DSPTILEOFF(plane
));
6573 offset
= I915_READ(DSPLINOFF(plane
));
6574 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6576 base
= I915_READ(DSPADDR(plane
));
6578 plane_config
->base
= base
;
6580 val
= I915_READ(PIPESRC(pipe
));
6581 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6582 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6584 val
= I915_READ(DSPSTRIDE(pipe
));
6585 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6587 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6588 plane_config
->tiled
);
6590 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6593 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6594 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6595 crtc
->base
.primary
->fb
->height
,
6596 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6597 crtc
->base
.primary
->fb
->pitches
[0],
6598 plane_config
->size
);
6602 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6603 struct intel_crtc_config
*pipe_config
)
6605 struct drm_device
*dev
= crtc
->base
.dev
;
6606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6607 int pipe
= pipe_config
->cpu_transcoder
;
6608 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6609 intel_clock_t clock
;
6610 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6611 int refclk
= 100000;
6613 mutex_lock(&dev_priv
->dpio_lock
);
6614 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6615 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6616 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6617 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6618 mutex_unlock(&dev_priv
->dpio_lock
);
6620 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6621 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6622 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6623 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6624 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6626 chv_clock(refclk
, &clock
);
6628 /* clock.dot is the fast clock */
6629 pipe_config
->port_clock
= clock
.dot
/ 5;
6632 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6633 struct intel_crtc_config
*pipe_config
)
6635 struct drm_device
*dev
= crtc
->base
.dev
;
6636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6639 if (!intel_display_power_is_enabled(dev_priv
,
6640 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6643 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6644 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6646 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6647 if (!(tmp
& PIPECONF_ENABLE
))
6650 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6651 switch (tmp
& PIPECONF_BPC_MASK
) {
6653 pipe_config
->pipe_bpp
= 18;
6656 pipe_config
->pipe_bpp
= 24;
6658 case PIPECONF_10BPC
:
6659 pipe_config
->pipe_bpp
= 30;
6666 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6667 pipe_config
->limited_color_range
= true;
6669 if (INTEL_INFO(dev
)->gen
< 4)
6670 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6672 intel_get_pipe_timings(crtc
, pipe_config
);
6674 i9xx_get_pfit_config(crtc
, pipe_config
);
6676 if (INTEL_INFO(dev
)->gen
>= 4) {
6677 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6678 pipe_config
->pixel_multiplier
=
6679 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6680 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6681 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6682 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6683 tmp
= I915_READ(DPLL(crtc
->pipe
));
6684 pipe_config
->pixel_multiplier
=
6685 ((tmp
& SDVO_MULTIPLIER_MASK
)
6686 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6688 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6689 * port and will be fixed up in the encoder->get_config
6691 pipe_config
->pixel_multiplier
= 1;
6693 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6694 if (!IS_VALLEYVIEW(dev
)) {
6696 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6697 * on 830. Filter it out here so that we don't
6698 * report errors due to that.
6701 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
6703 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6704 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6706 /* Mask out read-only status bits. */
6707 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6708 DPLL_PORTC_READY_MASK
|
6709 DPLL_PORTB_READY_MASK
);
6712 if (IS_CHERRYVIEW(dev
))
6713 chv_crtc_clock_get(crtc
, pipe_config
);
6714 else if (IS_VALLEYVIEW(dev
))
6715 vlv_crtc_clock_get(crtc
, pipe_config
);
6717 i9xx_crtc_clock_get(crtc
, pipe_config
);
6722 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6725 struct intel_encoder
*encoder
;
6727 bool has_lvds
= false;
6728 bool has_cpu_edp
= false;
6729 bool has_panel
= false;
6730 bool has_ck505
= false;
6731 bool can_ssc
= false;
6733 /* We need to take the global config into account */
6734 for_each_intel_encoder(dev
, encoder
) {
6735 switch (encoder
->type
) {
6736 case INTEL_OUTPUT_LVDS
:
6740 case INTEL_OUTPUT_EDP
:
6742 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6750 if (HAS_PCH_IBX(dev
)) {
6751 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6752 can_ssc
= has_ck505
;
6758 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6759 has_panel
, has_lvds
, has_ck505
);
6761 /* Ironlake: try to setup display ref clock before DPLL
6762 * enabling. This is only under driver's control after
6763 * PCH B stepping, previous chipset stepping should be
6764 * ignoring this setting.
6766 val
= I915_READ(PCH_DREF_CONTROL
);
6768 /* As we must carefully and slowly disable/enable each source in turn,
6769 * compute the final state we want first and check if we need to
6770 * make any changes at all.
6773 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6775 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6777 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6779 final
&= ~DREF_SSC_SOURCE_MASK
;
6780 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6781 final
&= ~DREF_SSC1_ENABLE
;
6784 final
|= DREF_SSC_SOURCE_ENABLE
;
6786 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6787 final
|= DREF_SSC1_ENABLE
;
6790 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6791 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6793 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6795 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6797 final
|= DREF_SSC_SOURCE_DISABLE
;
6798 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6804 /* Always enable nonspread source */
6805 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6808 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6810 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6813 val
&= ~DREF_SSC_SOURCE_MASK
;
6814 val
|= DREF_SSC_SOURCE_ENABLE
;
6816 /* SSC must be turned on before enabling the CPU output */
6817 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6818 DRM_DEBUG_KMS("Using SSC on panel\n");
6819 val
|= DREF_SSC1_ENABLE
;
6821 val
&= ~DREF_SSC1_ENABLE
;
6823 /* Get SSC going before enabling the outputs */
6824 I915_WRITE(PCH_DREF_CONTROL
, val
);
6825 POSTING_READ(PCH_DREF_CONTROL
);
6828 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6830 /* Enable CPU source on CPU attached eDP */
6832 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6833 DRM_DEBUG_KMS("Using SSC on eDP\n");
6834 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6836 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6838 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6840 I915_WRITE(PCH_DREF_CONTROL
, val
);
6841 POSTING_READ(PCH_DREF_CONTROL
);
6844 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6846 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6848 /* Turn off CPU output */
6849 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6851 I915_WRITE(PCH_DREF_CONTROL
, val
);
6852 POSTING_READ(PCH_DREF_CONTROL
);
6855 /* Turn off the SSC source */
6856 val
&= ~DREF_SSC_SOURCE_MASK
;
6857 val
|= DREF_SSC_SOURCE_DISABLE
;
6860 val
&= ~DREF_SSC1_ENABLE
;
6862 I915_WRITE(PCH_DREF_CONTROL
, val
);
6863 POSTING_READ(PCH_DREF_CONTROL
);
6867 BUG_ON(val
!= final
);
6870 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6874 tmp
= I915_READ(SOUTH_CHICKEN2
);
6875 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6876 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6878 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6879 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6880 DRM_ERROR("FDI mPHY reset assert timeout\n");
6882 tmp
= I915_READ(SOUTH_CHICKEN2
);
6883 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6884 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6886 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6887 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6888 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6891 /* WaMPhyProgramming:hsw */
6892 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6896 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6897 tmp
&= ~(0xFF << 24);
6898 tmp
|= (0x12 << 24);
6899 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6901 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6903 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6905 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6907 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6909 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6910 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6911 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6913 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6914 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6915 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6917 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6920 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6922 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6925 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6927 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6930 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6932 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6935 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6937 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6938 tmp
&= ~(0xFF << 16);
6939 tmp
|= (0x1C << 16);
6940 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6942 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6943 tmp
&= ~(0xFF << 16);
6944 tmp
|= (0x1C << 16);
6945 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6947 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6949 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6951 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6953 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6955 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6956 tmp
&= ~(0xF << 28);
6958 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6960 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6961 tmp
&= ~(0xF << 28);
6963 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6966 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6967 * Programming" based on the parameters passed:
6968 * - Sequence to enable CLKOUT_DP
6969 * - Sequence to enable CLKOUT_DP without spread
6970 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6972 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6978 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6980 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6981 with_fdi
, "LP PCH doesn't have FDI\n"))
6984 mutex_lock(&dev_priv
->dpio_lock
);
6986 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6987 tmp
&= ~SBI_SSCCTL_DISABLE
;
6988 tmp
|= SBI_SSCCTL_PATHALT
;
6989 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6994 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6995 tmp
&= ~SBI_SSCCTL_PATHALT
;
6996 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6999 lpt_reset_fdi_mphy(dev_priv
);
7000 lpt_program_fdi_mphy(dev_priv
);
7004 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7005 SBI_GEN0
: SBI_DBUFF0
;
7006 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7007 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7008 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7010 mutex_unlock(&dev_priv
->dpio_lock
);
7013 /* Sequence to disable CLKOUT_DP */
7014 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7019 mutex_lock(&dev_priv
->dpio_lock
);
7021 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7022 SBI_GEN0
: SBI_DBUFF0
;
7023 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7024 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7025 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7027 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7028 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7029 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7030 tmp
|= SBI_SSCCTL_PATHALT
;
7031 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7034 tmp
|= SBI_SSCCTL_DISABLE
;
7035 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7038 mutex_unlock(&dev_priv
->dpio_lock
);
7041 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7043 struct intel_encoder
*encoder
;
7044 bool has_vga
= false;
7046 for_each_intel_encoder(dev
, encoder
) {
7047 switch (encoder
->type
) {
7048 case INTEL_OUTPUT_ANALOG
:
7057 lpt_enable_clkout_dp(dev
, true, true);
7059 lpt_disable_clkout_dp(dev
);
7063 * Initialize reference clocks when the driver loads
7065 void intel_init_pch_refclk(struct drm_device
*dev
)
7067 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7068 ironlake_init_pch_refclk(dev
);
7069 else if (HAS_PCH_LPT(dev
))
7070 lpt_init_pch_refclk(dev
);
7073 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
7075 struct drm_device
*dev
= crtc
->dev
;
7076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7077 struct intel_encoder
*encoder
;
7078 int num_connectors
= 0;
7079 bool is_lvds
= false;
7081 for_each_intel_encoder(dev
, encoder
) {
7082 if (encoder
->new_crtc
!= to_intel_crtc(crtc
))
7085 switch (encoder
->type
) {
7086 case INTEL_OUTPUT_LVDS
:
7095 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7096 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7097 dev_priv
->vbt
.lvds_ssc_freq
);
7098 return dev_priv
->vbt
.lvds_ssc_freq
;
7104 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7106 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7107 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7108 int pipe
= intel_crtc
->pipe
;
7113 switch (intel_crtc
->config
.pipe_bpp
) {
7115 val
|= PIPECONF_6BPC
;
7118 val
|= PIPECONF_8BPC
;
7121 val
|= PIPECONF_10BPC
;
7124 val
|= PIPECONF_12BPC
;
7127 /* Case prevented by intel_choose_pipe_bpp_dither. */
7131 if (intel_crtc
->config
.dither
)
7132 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7134 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7135 val
|= PIPECONF_INTERLACED_ILK
;
7137 val
|= PIPECONF_PROGRESSIVE
;
7139 if (intel_crtc
->config
.limited_color_range
)
7140 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7142 I915_WRITE(PIPECONF(pipe
), val
);
7143 POSTING_READ(PIPECONF(pipe
));
7147 * Set up the pipe CSC unit.
7149 * Currently only full range RGB to limited range RGB conversion
7150 * is supported, but eventually this should handle various
7151 * RGB<->YCbCr scenarios as well.
7153 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7155 struct drm_device
*dev
= crtc
->dev
;
7156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7158 int pipe
= intel_crtc
->pipe
;
7159 uint16_t coeff
= 0x7800; /* 1.0 */
7162 * TODO: Check what kind of values actually come out of the pipe
7163 * with these coeff/postoff values and adjust to get the best
7164 * accuracy. Perhaps we even need to take the bpc value into
7168 if (intel_crtc
->config
.limited_color_range
)
7169 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7172 * GY/GU and RY/RU should be the other way around according
7173 * to BSpec, but reality doesn't agree. Just set them up in
7174 * a way that results in the correct picture.
7176 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7177 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7179 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7180 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7182 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7183 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7185 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7186 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7187 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7189 if (INTEL_INFO(dev
)->gen
> 6) {
7190 uint16_t postoff
= 0;
7192 if (intel_crtc
->config
.limited_color_range
)
7193 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7195 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7196 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7197 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7199 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7201 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7203 if (intel_crtc
->config
.limited_color_range
)
7204 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7206 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7210 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7212 struct drm_device
*dev
= crtc
->dev
;
7213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7214 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7215 enum pipe pipe
= intel_crtc
->pipe
;
7216 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7221 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
7222 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7224 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7225 val
|= PIPECONF_INTERLACED_ILK
;
7227 val
|= PIPECONF_PROGRESSIVE
;
7229 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7230 POSTING_READ(PIPECONF(cpu_transcoder
));
7232 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7233 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7235 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7238 switch (intel_crtc
->config
.pipe_bpp
) {
7240 val
|= PIPEMISC_DITHER_6_BPC
;
7243 val
|= PIPEMISC_DITHER_8_BPC
;
7246 val
|= PIPEMISC_DITHER_10_BPC
;
7249 val
|= PIPEMISC_DITHER_12_BPC
;
7252 /* Case prevented by pipe_config_set_bpp. */
7256 if (intel_crtc
->config
.dither
)
7257 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7259 I915_WRITE(PIPEMISC(pipe
), val
);
7263 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7264 intel_clock_t
*clock
,
7265 bool *has_reduced_clock
,
7266 intel_clock_t
*reduced_clock
)
7268 struct drm_device
*dev
= crtc
->dev
;
7269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7270 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7272 const intel_limit_t
*limit
;
7273 bool ret
, is_lvds
= false;
7275 is_lvds
= intel_pipe_will_have_type(intel_crtc
, INTEL_OUTPUT_LVDS
);
7277 refclk
= ironlake_get_refclk(crtc
);
7280 * Returns a set of divisors for the desired target clock with the given
7281 * refclk, or FALSE. The returned values represent the clock equation:
7282 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7284 limit
= intel_limit(intel_crtc
, refclk
);
7285 ret
= dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7286 intel_crtc
->new_config
->port_clock
,
7287 refclk
, NULL
, clock
);
7291 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7293 * Ensure we match the reduced clock's P to the target clock.
7294 * If the clocks don't match, we can't switch the display clock
7295 * by using the FP0/FP1. In such case we will disable the LVDS
7296 * downclock feature.
7298 *has_reduced_clock
=
7299 dev_priv
->display
.find_dpll(limit
, intel_crtc
,
7300 dev_priv
->lvds_downclock
,
7308 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7311 * Account for spread spectrum to avoid
7312 * oversubscribing the link. Max center spread
7313 * is 2.5%; use 5% for safety's sake.
7315 u32 bps
= target_clock
* bpp
* 21 / 20;
7316 return DIV_ROUND_UP(bps
, link_bw
* 8);
7319 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7321 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7324 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7326 intel_clock_t
*reduced_clock
, u32
*fp2
)
7328 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7329 struct drm_device
*dev
= crtc
->dev
;
7330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7331 struct intel_encoder
*intel_encoder
;
7333 int factor
, num_connectors
= 0;
7334 bool is_lvds
= false, is_sdvo
= false;
7336 for_each_intel_encoder(dev
, intel_encoder
) {
7337 if (intel_encoder
->new_crtc
!= to_intel_crtc(crtc
))
7340 switch (intel_encoder
->type
) {
7341 case INTEL_OUTPUT_LVDS
:
7344 case INTEL_OUTPUT_SDVO
:
7345 case INTEL_OUTPUT_HDMI
:
7355 /* Enable autotuning of the PLL clock (if permissible) */
7358 if ((intel_panel_use_ssc(dev_priv
) &&
7359 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7360 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7362 } else if (intel_crtc
->new_config
->sdvo_tv_clock
)
7365 if (ironlake_needs_fb_cb_tune(&intel_crtc
->new_config
->dpll
, factor
))
7368 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7374 dpll
|= DPLLB_MODE_LVDS
;
7376 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7378 dpll
|= (intel_crtc
->new_config
->pixel_multiplier
- 1)
7379 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7382 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7383 if (intel_crtc
->new_config
->has_dp_encoder
)
7384 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7386 /* compute bitmask from p1 value */
7387 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7389 dpll
|= (1 << (intel_crtc
->new_config
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7391 switch (intel_crtc
->new_config
->dpll
.p2
) {
7393 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7396 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7399 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7402 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7406 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7407 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7409 dpll
|= PLL_REF_INPUT_DREFCLK
;
7411 return dpll
| DPLL_VCO_ENABLE
;
7414 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
)
7416 struct drm_device
*dev
= crtc
->base
.dev
;
7417 intel_clock_t clock
, reduced_clock
;
7418 u32 dpll
= 0, fp
= 0, fp2
= 0;
7419 bool ok
, has_reduced_clock
= false;
7420 bool is_lvds
= false;
7421 struct intel_shared_dpll
*pll
;
7423 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7425 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7426 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7428 ok
= ironlake_compute_clocks(&crtc
->base
, &clock
,
7429 &has_reduced_clock
, &reduced_clock
);
7430 if (!ok
&& !crtc
->new_config
->clock_set
) {
7431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7434 /* Compat-code for transition, will disappear. */
7435 if (!crtc
->new_config
->clock_set
) {
7436 crtc
->new_config
->dpll
.n
= clock
.n
;
7437 crtc
->new_config
->dpll
.m1
= clock
.m1
;
7438 crtc
->new_config
->dpll
.m2
= clock
.m2
;
7439 crtc
->new_config
->dpll
.p1
= clock
.p1
;
7440 crtc
->new_config
->dpll
.p2
= clock
.p2
;
7443 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7444 if (crtc
->new_config
->has_pch_encoder
) {
7445 fp
= i9xx_dpll_compute_fp(&crtc
->new_config
->dpll
);
7446 if (has_reduced_clock
)
7447 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7449 dpll
= ironlake_compute_dpll(crtc
,
7450 &fp
, &reduced_clock
,
7451 has_reduced_clock
? &fp2
: NULL
);
7453 crtc
->new_config
->dpll_hw_state
.dpll
= dpll
;
7454 crtc
->new_config
->dpll_hw_state
.fp0
= fp
;
7455 if (has_reduced_clock
)
7456 crtc
->new_config
->dpll_hw_state
.fp1
= fp2
;
7458 crtc
->new_config
->dpll_hw_state
.fp1
= fp
;
7460 pll
= intel_get_shared_dpll(crtc
);
7462 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7463 pipe_name(crtc
->pipe
));
7468 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7469 crtc
->lowfreq_avail
= true;
7471 crtc
->lowfreq_avail
= false;
7476 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7477 struct intel_link_m_n
*m_n
)
7479 struct drm_device
*dev
= crtc
->base
.dev
;
7480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7481 enum pipe pipe
= crtc
->pipe
;
7483 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7484 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7485 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7487 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7488 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7489 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7492 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7493 enum transcoder transcoder
,
7494 struct intel_link_m_n
*m_n
,
7495 struct intel_link_m_n
*m2_n2
)
7497 struct drm_device
*dev
= crtc
->base
.dev
;
7498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7499 enum pipe pipe
= crtc
->pipe
;
7501 if (INTEL_INFO(dev
)->gen
>= 5) {
7502 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7503 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7504 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7506 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7507 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7508 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7509 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7510 * gen < 8) and if DRRS is supported (to make sure the
7511 * registers are not unnecessarily read).
7513 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7514 crtc
->config
.has_drrs
) {
7515 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7516 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7517 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7519 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7520 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7521 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7524 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7525 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7526 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7528 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7529 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7530 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7534 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7535 struct intel_crtc_config
*pipe_config
)
7537 if (crtc
->config
.has_pch_encoder
)
7538 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7540 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7541 &pipe_config
->dp_m_n
,
7542 &pipe_config
->dp_m2_n2
);
7545 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7546 struct intel_crtc_config
*pipe_config
)
7548 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7549 &pipe_config
->fdi_m_n
, NULL
);
7552 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7553 struct intel_crtc_config
*pipe_config
)
7555 struct drm_device
*dev
= crtc
->base
.dev
;
7556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7559 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7561 if (tmp
& PF_ENABLE
) {
7562 pipe_config
->pch_pfit
.enabled
= true;
7563 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7564 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7566 /* We currently do not free assignements of panel fitters on
7567 * ivb/hsw (since we don't use the higher upscaling modes which
7568 * differentiates them) so just WARN about this case for now. */
7570 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7571 PF_PIPE_SEL_IVB(crtc
->pipe
));
7576 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7577 struct intel_plane_config
*plane_config
)
7579 struct drm_device
*dev
= crtc
->base
.dev
;
7580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7581 u32 val
, base
, offset
;
7582 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7583 int fourcc
, pixel_format
;
7586 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7587 if (!crtc
->base
.primary
->fb
) {
7588 DRM_DEBUG_KMS("failed to alloc fb\n");
7592 val
= I915_READ(DSPCNTR(plane
));
7594 if (INTEL_INFO(dev
)->gen
>= 4)
7595 if (val
& DISPPLANE_TILED
)
7596 plane_config
->tiled
= true;
7598 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7599 fourcc
= intel_format_to_fourcc(pixel_format
);
7600 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7601 crtc
->base
.primary
->fb
->bits_per_pixel
=
7602 drm_format_plane_cpp(fourcc
, 0) * 8;
7604 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7605 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7606 offset
= I915_READ(DSPOFFSET(plane
));
7608 if (plane_config
->tiled
)
7609 offset
= I915_READ(DSPTILEOFF(plane
));
7611 offset
= I915_READ(DSPLINOFF(plane
));
7613 plane_config
->base
= base
;
7615 val
= I915_READ(PIPESRC(pipe
));
7616 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7617 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7619 val
= I915_READ(DSPSTRIDE(pipe
));
7620 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7622 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7623 plane_config
->tiled
);
7625 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7628 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7629 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7630 crtc
->base
.primary
->fb
->height
,
7631 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7632 crtc
->base
.primary
->fb
->pitches
[0],
7633 plane_config
->size
);
7636 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7637 struct intel_crtc_config
*pipe_config
)
7639 struct drm_device
*dev
= crtc
->base
.dev
;
7640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7643 if (!intel_display_power_is_enabled(dev_priv
,
7644 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7647 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7648 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7650 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7651 if (!(tmp
& PIPECONF_ENABLE
))
7654 switch (tmp
& PIPECONF_BPC_MASK
) {
7656 pipe_config
->pipe_bpp
= 18;
7659 pipe_config
->pipe_bpp
= 24;
7661 case PIPECONF_10BPC
:
7662 pipe_config
->pipe_bpp
= 30;
7664 case PIPECONF_12BPC
:
7665 pipe_config
->pipe_bpp
= 36;
7671 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7672 pipe_config
->limited_color_range
= true;
7674 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7675 struct intel_shared_dpll
*pll
;
7677 pipe_config
->has_pch_encoder
= true;
7679 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7680 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7681 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7683 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7685 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7686 pipe_config
->shared_dpll
=
7687 (enum intel_dpll_id
) crtc
->pipe
;
7689 tmp
= I915_READ(PCH_DPLL_SEL
);
7690 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7691 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7693 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7696 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7698 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7699 &pipe_config
->dpll_hw_state
));
7701 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7702 pipe_config
->pixel_multiplier
=
7703 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7704 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7706 ironlake_pch_clock_get(crtc
, pipe_config
);
7708 pipe_config
->pixel_multiplier
= 1;
7711 intel_get_pipe_timings(crtc
, pipe_config
);
7713 ironlake_get_pfit_config(crtc
, pipe_config
);
7718 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7720 struct drm_device
*dev
= dev_priv
->dev
;
7721 struct intel_crtc
*crtc
;
7723 for_each_intel_crtc(dev
, crtc
)
7724 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7725 pipe_name(crtc
->pipe
));
7727 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7728 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7729 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7730 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7731 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7732 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7733 "CPU PWM1 enabled\n");
7734 if (IS_HASWELL(dev
))
7735 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7736 "CPU PWM2 enabled\n");
7737 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7738 "PCH PWM1 enabled\n");
7739 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7740 "Utility pin enabled\n");
7741 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7744 * In theory we can still leave IRQs enabled, as long as only the HPD
7745 * interrupts remain enabled. We used to check for that, but since it's
7746 * gen-specific and since we only disable LCPLL after we fully disable
7747 * the interrupts, the check below should be enough.
7749 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7752 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7754 struct drm_device
*dev
= dev_priv
->dev
;
7756 if (IS_HASWELL(dev
))
7757 return I915_READ(D_COMP_HSW
);
7759 return I915_READ(D_COMP_BDW
);
7762 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7764 struct drm_device
*dev
= dev_priv
->dev
;
7766 if (IS_HASWELL(dev
)) {
7767 mutex_lock(&dev_priv
->rps
.hw_lock
);
7768 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7770 DRM_ERROR("Failed to write to D_COMP\n");
7771 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7773 I915_WRITE(D_COMP_BDW
, val
);
7774 POSTING_READ(D_COMP_BDW
);
7779 * This function implements pieces of two sequences from BSpec:
7780 * - Sequence for display software to disable LCPLL
7781 * - Sequence for display software to allow package C8+
7782 * The steps implemented here are just the steps that actually touch the LCPLL
7783 * register. Callers should take care of disabling all the display engine
7784 * functions, doing the mode unset, fixing interrupts, etc.
7786 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7787 bool switch_to_fclk
, bool allow_power_down
)
7791 assert_can_disable_lcpll(dev_priv
);
7793 val
= I915_READ(LCPLL_CTL
);
7795 if (switch_to_fclk
) {
7796 val
|= LCPLL_CD_SOURCE_FCLK
;
7797 I915_WRITE(LCPLL_CTL
, val
);
7799 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7800 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7801 DRM_ERROR("Switching to FCLK failed\n");
7803 val
= I915_READ(LCPLL_CTL
);
7806 val
|= LCPLL_PLL_DISABLE
;
7807 I915_WRITE(LCPLL_CTL
, val
);
7808 POSTING_READ(LCPLL_CTL
);
7810 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7811 DRM_ERROR("LCPLL still locked\n");
7813 val
= hsw_read_dcomp(dev_priv
);
7814 val
|= D_COMP_COMP_DISABLE
;
7815 hsw_write_dcomp(dev_priv
, val
);
7818 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7820 DRM_ERROR("D_COMP RCOMP still in progress\n");
7822 if (allow_power_down
) {
7823 val
= I915_READ(LCPLL_CTL
);
7824 val
|= LCPLL_POWER_DOWN_ALLOW
;
7825 I915_WRITE(LCPLL_CTL
, val
);
7826 POSTING_READ(LCPLL_CTL
);
7831 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7834 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7838 val
= I915_READ(LCPLL_CTL
);
7840 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7841 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7845 * Make sure we're not on PC8 state before disabling PC8, otherwise
7846 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7848 * The other problem is that hsw_restore_lcpll() is called as part of
7849 * the runtime PM resume sequence, so we can't just call
7850 * gen6_gt_force_wake_get() because that function calls
7851 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7852 * while we are on the resume sequence. So to solve this problem we have
7853 * to call special forcewake code that doesn't touch runtime PM and
7854 * doesn't enable the forcewake delayed work.
7856 spin_lock_irq(&dev_priv
->uncore
.lock
);
7857 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7858 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7859 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7861 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7862 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7863 I915_WRITE(LCPLL_CTL
, val
);
7864 POSTING_READ(LCPLL_CTL
);
7867 val
= hsw_read_dcomp(dev_priv
);
7868 val
|= D_COMP_COMP_FORCE
;
7869 val
&= ~D_COMP_COMP_DISABLE
;
7870 hsw_write_dcomp(dev_priv
, val
);
7872 val
= I915_READ(LCPLL_CTL
);
7873 val
&= ~LCPLL_PLL_DISABLE
;
7874 I915_WRITE(LCPLL_CTL
, val
);
7876 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7877 DRM_ERROR("LCPLL not locked yet\n");
7879 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7880 val
= I915_READ(LCPLL_CTL
);
7881 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7882 I915_WRITE(LCPLL_CTL
, val
);
7884 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7885 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7886 DRM_ERROR("Switching back to LCPLL failed\n");
7889 /* See the big comment above. */
7890 spin_lock_irq(&dev_priv
->uncore
.lock
);
7891 if (--dev_priv
->uncore
.forcewake_count
== 0)
7892 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7893 spin_unlock_irq(&dev_priv
->uncore
.lock
);
7897 * Package states C8 and deeper are really deep PC states that can only be
7898 * reached when all the devices on the system allow it, so even if the graphics
7899 * device allows PC8+, it doesn't mean the system will actually get to these
7900 * states. Our driver only allows PC8+ when going into runtime PM.
7902 * The requirements for PC8+ are that all the outputs are disabled, the power
7903 * well is disabled and most interrupts are disabled, and these are also
7904 * requirements for runtime PM. When these conditions are met, we manually do
7905 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7906 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7909 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7910 * the state of some registers, so when we come back from PC8+ we need to
7911 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7912 * need to take care of the registers kept by RC6. Notice that this happens even
7913 * if we don't put the device in PCI D3 state (which is what currently happens
7914 * because of the runtime PM support).
7916 * For more, read "Display Sequences for Package C8" on the hardware
7919 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7921 struct drm_device
*dev
= dev_priv
->dev
;
7924 DRM_DEBUG_KMS("Enabling package C8+\n");
7926 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7927 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7928 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7929 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7932 lpt_disable_clkout_dp(dev
);
7933 hsw_disable_lcpll(dev_priv
, true, true);
7936 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7938 struct drm_device
*dev
= dev_priv
->dev
;
7941 DRM_DEBUG_KMS("Disabling package C8+\n");
7943 hsw_restore_lcpll(dev_priv
);
7944 lpt_init_pch_refclk(dev
);
7946 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7947 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7948 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7949 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7952 intel_prepare_ddi(dev
);
7955 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
)
7957 if (!intel_ddi_pll_select(crtc
))
7960 crtc
->lowfreq_avail
= false;
7965 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7967 struct intel_crtc_config
*pipe_config
)
7969 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7971 switch (pipe_config
->ddi_pll_sel
) {
7972 case PORT_CLK_SEL_WRPLL1
:
7973 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7975 case PORT_CLK_SEL_WRPLL2
:
7976 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7981 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7982 struct intel_crtc_config
*pipe_config
)
7984 struct drm_device
*dev
= crtc
->base
.dev
;
7985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7986 struct intel_shared_dpll
*pll
;
7990 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7992 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7994 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7996 if (pipe_config
->shared_dpll
>= 0) {
7997 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7999 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8000 &pipe_config
->dpll_hw_state
));
8004 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8005 * DDI E. So just check whether this pipe is wired to DDI E and whether
8006 * the PCH transcoder is on.
8008 if (INTEL_INFO(dev
)->gen
< 9 &&
8009 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8010 pipe_config
->has_pch_encoder
= true;
8012 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8013 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8014 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8016 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8020 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8021 struct intel_crtc_config
*pipe_config
)
8023 struct drm_device
*dev
= crtc
->base
.dev
;
8024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8025 enum intel_display_power_domain pfit_domain
;
8028 if (!intel_display_power_is_enabled(dev_priv
,
8029 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8032 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8033 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8035 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8036 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8037 enum pipe trans_edp_pipe
;
8038 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8040 WARN(1, "unknown pipe linked to edp transcoder\n");
8041 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8042 case TRANS_DDI_EDP_INPUT_A_ON
:
8043 trans_edp_pipe
= PIPE_A
;
8045 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8046 trans_edp_pipe
= PIPE_B
;
8048 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8049 trans_edp_pipe
= PIPE_C
;
8053 if (trans_edp_pipe
== crtc
->pipe
)
8054 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8057 if (!intel_display_power_is_enabled(dev_priv
,
8058 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8061 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8062 if (!(tmp
& PIPECONF_ENABLE
))
8065 haswell_get_ddi_port_state(crtc
, pipe_config
);
8067 intel_get_pipe_timings(crtc
, pipe_config
);
8069 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8070 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
))
8071 ironlake_get_pfit_config(crtc
, pipe_config
);
8073 if (IS_HASWELL(dev
))
8074 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8075 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8077 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8078 pipe_config
->pixel_multiplier
=
8079 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8081 pipe_config
->pixel_multiplier
= 1;
8087 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8089 struct drm_device
*dev
= crtc
->dev
;
8090 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8092 uint32_t cntl
= 0, size
= 0;
8095 unsigned int width
= intel_crtc
->cursor_width
;
8096 unsigned int height
= intel_crtc
->cursor_height
;
8097 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8101 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8112 cntl
|= CURSOR_ENABLE
|
8113 CURSOR_GAMMA_ENABLE
|
8114 CURSOR_FORMAT_ARGB
|
8115 CURSOR_STRIDE(stride
);
8117 size
= (height
<< 12) | width
;
8120 if (intel_crtc
->cursor_cntl
!= 0 &&
8121 (intel_crtc
->cursor_base
!= base
||
8122 intel_crtc
->cursor_size
!= size
||
8123 intel_crtc
->cursor_cntl
!= cntl
)) {
8124 /* On these chipsets we can only modify the base/size/stride
8125 * whilst the cursor is disabled.
8127 I915_WRITE(_CURACNTR
, 0);
8128 POSTING_READ(_CURACNTR
);
8129 intel_crtc
->cursor_cntl
= 0;
8132 if (intel_crtc
->cursor_base
!= base
) {
8133 I915_WRITE(_CURABASE
, base
);
8134 intel_crtc
->cursor_base
= base
;
8137 if (intel_crtc
->cursor_size
!= size
) {
8138 I915_WRITE(CURSIZE
, size
);
8139 intel_crtc
->cursor_size
= size
;
8142 if (intel_crtc
->cursor_cntl
!= cntl
) {
8143 I915_WRITE(_CURACNTR
, cntl
);
8144 POSTING_READ(_CURACNTR
);
8145 intel_crtc
->cursor_cntl
= cntl
;
8149 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8151 struct drm_device
*dev
= crtc
->dev
;
8152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8154 int pipe
= intel_crtc
->pipe
;
8159 cntl
= MCURSOR_GAMMA_ENABLE
;
8160 switch (intel_crtc
->cursor_width
) {
8162 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8165 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8168 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8174 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8176 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8177 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8180 if (to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
))
8181 cntl
|= CURSOR_ROTATE_180
;
8183 if (intel_crtc
->cursor_cntl
!= cntl
) {
8184 I915_WRITE(CURCNTR(pipe
), cntl
);
8185 POSTING_READ(CURCNTR(pipe
));
8186 intel_crtc
->cursor_cntl
= cntl
;
8189 /* and commit changes on next vblank */
8190 I915_WRITE(CURBASE(pipe
), base
);
8191 POSTING_READ(CURBASE(pipe
));
8193 intel_crtc
->cursor_base
= base
;
8196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8197 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8200 struct drm_device
*dev
= crtc
->dev
;
8201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8202 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8203 int pipe
= intel_crtc
->pipe
;
8204 int x
= crtc
->cursor_x
;
8205 int y
= crtc
->cursor_y
;
8206 u32 base
= 0, pos
= 0;
8209 base
= intel_crtc
->cursor_addr
;
8211 if (x
>= intel_crtc
->config
.pipe_src_w
)
8214 if (y
>= intel_crtc
->config
.pipe_src_h
)
8218 if (x
+ intel_crtc
->cursor_width
<= 0)
8221 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8224 pos
|= x
<< CURSOR_X_SHIFT
;
8227 if (y
+ intel_crtc
->cursor_height
<= 0)
8230 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8233 pos
|= y
<< CURSOR_Y_SHIFT
;
8235 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8238 I915_WRITE(CURPOS(pipe
), pos
);
8240 /* ILK+ do this automagically */
8241 if (HAS_GMCH_DISPLAY(dev
) &&
8242 to_intel_plane(crtc
->cursor
)->rotation
== BIT(DRM_ROTATE_180
)) {
8243 base
+= (intel_crtc
->cursor_height
*
8244 intel_crtc
->cursor_width
- 1) * 4;
8247 if (IS_845G(dev
) || IS_I865G(dev
))
8248 i845_update_cursor(crtc
, base
);
8250 i9xx_update_cursor(crtc
, base
);
8253 static bool cursor_size_ok(struct drm_device
*dev
,
8254 uint32_t width
, uint32_t height
)
8256 if (width
== 0 || height
== 0)
8260 * 845g/865g are special in that they are only limited by
8261 * the width of their cursors, the height is arbitrary up to
8262 * the precision of the register. Everything else requires
8263 * square cursors, limited to a few power-of-two sizes.
8265 if (IS_845G(dev
) || IS_I865G(dev
)) {
8266 if ((width
& 63) != 0)
8269 if (width
> (IS_845G(dev
) ? 64 : 512))
8275 switch (width
| height
) {
8290 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8291 struct drm_i915_gem_object
*obj
,
8292 uint32_t width
, uint32_t height
)
8294 struct drm_device
*dev
= crtc
->dev
;
8295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8296 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8297 enum pipe pipe
= intel_crtc
->pipe
;
8302 /* if we want to turn off the cursor ignore width and height */
8304 DRM_DEBUG_KMS("cursor off\n");
8306 mutex_lock(&dev
->struct_mutex
);
8310 /* we only need to pin inside GTT if cursor is non-phy */
8311 mutex_lock(&dev
->struct_mutex
);
8312 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8316 * Global gtt pte registers are special registers which actually
8317 * forward writes to a chunk of system memory. Which means that
8318 * there is no risk that the register values disappear as soon
8319 * as we call intel_runtime_pm_put(), so it is correct to wrap
8320 * only the pin/unpin/fence and not more.
8322 intel_runtime_pm_get(dev_priv
);
8324 /* Note that the w/a also requires 2 PTE of padding following
8325 * the bo. We currently fill all unused PTE with the shadow
8326 * page and so we should always have valid PTE following the
8327 * cursor preventing the VT-d warning.
8330 if (need_vtd_wa(dev
))
8331 alignment
= 64*1024;
8333 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8335 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8336 intel_runtime_pm_put(dev_priv
);
8340 ret
= i915_gem_object_put_fence(obj
);
8342 DRM_DEBUG_KMS("failed to release fence for cursor");
8343 intel_runtime_pm_put(dev_priv
);
8347 addr
= i915_gem_obj_ggtt_offset(obj
);
8349 intel_runtime_pm_put(dev_priv
);
8351 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8352 ret
= i915_gem_object_attach_phys(obj
, align
);
8354 DRM_DEBUG_KMS("failed to attach phys object\n");
8357 addr
= obj
->phys_handle
->busaddr
;
8361 if (intel_crtc
->cursor_bo
) {
8362 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8363 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8366 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8367 INTEL_FRONTBUFFER_CURSOR(pipe
));
8368 mutex_unlock(&dev
->struct_mutex
);
8370 old_width
= intel_crtc
->cursor_width
;
8372 intel_crtc
->cursor_addr
= addr
;
8373 intel_crtc
->cursor_bo
= obj
;
8374 intel_crtc
->cursor_width
= width
;
8375 intel_crtc
->cursor_height
= height
;
8377 if (intel_crtc
->active
) {
8378 if (old_width
!= width
)
8379 intel_update_watermarks(crtc
);
8380 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8382 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8387 i915_gem_object_unpin_from_display_plane(obj
);
8389 mutex_unlock(&dev
->struct_mutex
);
8393 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8394 u16
*blue
, uint32_t start
, uint32_t size
)
8396 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8399 for (i
= start
; i
< end
; i
++) {
8400 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8401 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8402 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8405 intel_crtc_load_lut(crtc
);
8408 /* VESA 640x480x72Hz mode to set on the pipe */
8409 static struct drm_display_mode load_detect_mode
= {
8410 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8411 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8414 struct drm_framebuffer
*
8415 __intel_framebuffer_create(struct drm_device
*dev
,
8416 struct drm_mode_fb_cmd2
*mode_cmd
,
8417 struct drm_i915_gem_object
*obj
)
8419 struct intel_framebuffer
*intel_fb
;
8422 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8424 drm_gem_object_unreference_unlocked(&obj
->base
);
8425 return ERR_PTR(-ENOMEM
);
8428 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8432 return &intel_fb
->base
;
8434 drm_gem_object_unreference_unlocked(&obj
->base
);
8437 return ERR_PTR(ret
);
8440 static struct drm_framebuffer
*
8441 intel_framebuffer_create(struct drm_device
*dev
,
8442 struct drm_mode_fb_cmd2
*mode_cmd
,
8443 struct drm_i915_gem_object
*obj
)
8445 struct drm_framebuffer
*fb
;
8448 ret
= i915_mutex_lock_interruptible(dev
);
8450 return ERR_PTR(ret
);
8451 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8452 mutex_unlock(&dev
->struct_mutex
);
8458 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8460 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8461 return ALIGN(pitch
, 64);
8465 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8467 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8468 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8471 static struct drm_framebuffer
*
8472 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8473 struct drm_display_mode
*mode
,
8476 struct drm_i915_gem_object
*obj
;
8477 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8479 obj
= i915_gem_alloc_object(dev
,
8480 intel_framebuffer_size_for_mode(mode
, bpp
));
8482 return ERR_PTR(-ENOMEM
);
8484 mode_cmd
.width
= mode
->hdisplay
;
8485 mode_cmd
.height
= mode
->vdisplay
;
8486 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8488 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8490 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8493 static struct drm_framebuffer
*
8494 mode_fits_in_fbdev(struct drm_device
*dev
,
8495 struct drm_display_mode
*mode
)
8497 #ifdef CONFIG_DRM_I915_FBDEV
8498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8499 struct drm_i915_gem_object
*obj
;
8500 struct drm_framebuffer
*fb
;
8502 if (!dev_priv
->fbdev
)
8505 if (!dev_priv
->fbdev
->fb
)
8508 obj
= dev_priv
->fbdev
->fb
->obj
;
8511 fb
= &dev_priv
->fbdev
->fb
->base
;
8512 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8513 fb
->bits_per_pixel
))
8516 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8525 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8526 struct drm_display_mode
*mode
,
8527 struct intel_load_detect_pipe
*old
,
8528 struct drm_modeset_acquire_ctx
*ctx
)
8530 struct intel_crtc
*intel_crtc
;
8531 struct intel_encoder
*intel_encoder
=
8532 intel_attached_encoder(connector
);
8533 struct drm_crtc
*possible_crtc
;
8534 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8535 struct drm_crtc
*crtc
= NULL
;
8536 struct drm_device
*dev
= encoder
->dev
;
8537 struct drm_framebuffer
*fb
;
8538 struct drm_mode_config
*config
= &dev
->mode_config
;
8541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8542 connector
->base
.id
, connector
->name
,
8543 encoder
->base
.id
, encoder
->name
);
8546 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8551 * Algorithm gets a little messy:
8553 * - if the connector already has an assigned crtc, use it (but make
8554 * sure it's on first)
8556 * - try to find the first unused crtc that can drive this connector,
8557 * and use that if we find one
8560 /* See if we already have a CRTC for this connector */
8561 if (encoder
->crtc
) {
8562 crtc
= encoder
->crtc
;
8564 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8567 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8571 old
->dpms_mode
= connector
->dpms
;
8572 old
->load_detect_temp
= false;
8574 /* Make sure the crtc and connector are running */
8575 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8576 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8581 /* Find an unused one (if possible) */
8582 for_each_crtc(dev
, possible_crtc
) {
8584 if (!(encoder
->possible_crtcs
& (1 << i
)))
8586 if (possible_crtc
->enabled
)
8588 /* This can occur when applying the pipe A quirk on resume. */
8589 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8592 crtc
= possible_crtc
;
8597 * If we didn't find an unused CRTC, don't use any.
8600 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8604 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8607 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
8610 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8611 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8613 intel_crtc
= to_intel_crtc(crtc
);
8614 intel_crtc
->new_enabled
= true;
8615 intel_crtc
->new_config
= &intel_crtc
->config
;
8616 old
->dpms_mode
= connector
->dpms
;
8617 old
->load_detect_temp
= true;
8618 old
->release_fb
= NULL
;
8621 mode
= &load_detect_mode
;
8623 /* We need a framebuffer large enough to accommodate all accesses
8624 * that the plane may generate whilst we perform load detection.
8625 * We can not rely on the fbcon either being present (we get called
8626 * during its initialisation to detect all boot displays, or it may
8627 * not even exist) or that it is large enough to satisfy the
8630 fb
= mode_fits_in_fbdev(dev
, mode
);
8632 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8633 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8634 old
->release_fb
= fb
;
8636 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8638 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8642 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8643 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8644 if (old
->release_fb
)
8645 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8649 /* let the connector get through one full cycle before testing */
8650 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8654 intel_crtc
->new_enabled
= crtc
->enabled
;
8655 if (intel_crtc
->new_enabled
)
8656 intel_crtc
->new_config
= &intel_crtc
->config
;
8658 intel_crtc
->new_config
= NULL
;
8660 if (ret
== -EDEADLK
) {
8661 drm_modeset_backoff(ctx
);
8668 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8669 struct intel_load_detect_pipe
*old
)
8671 struct intel_encoder
*intel_encoder
=
8672 intel_attached_encoder(connector
);
8673 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8674 struct drm_crtc
*crtc
= encoder
->crtc
;
8675 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8677 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8678 connector
->base
.id
, connector
->name
,
8679 encoder
->base
.id
, encoder
->name
);
8681 if (old
->load_detect_temp
) {
8682 to_intel_connector(connector
)->new_encoder
= NULL
;
8683 intel_encoder
->new_crtc
= NULL
;
8684 intel_crtc
->new_enabled
= false;
8685 intel_crtc
->new_config
= NULL
;
8686 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8688 if (old
->release_fb
) {
8689 drm_framebuffer_unregister_private(old
->release_fb
);
8690 drm_framebuffer_unreference(old
->release_fb
);
8696 /* Switch crtc and encoder back off if necessary */
8697 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8698 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8701 static int i9xx_pll_refclk(struct drm_device
*dev
,
8702 const struct intel_crtc_config
*pipe_config
)
8704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8705 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8707 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8708 return dev_priv
->vbt
.lvds_ssc_freq
;
8709 else if (HAS_PCH_SPLIT(dev
))
8711 else if (!IS_GEN2(dev
))
8717 /* Returns the clock of the currently programmed mode of the given pipe. */
8718 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8719 struct intel_crtc_config
*pipe_config
)
8721 struct drm_device
*dev
= crtc
->base
.dev
;
8722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8723 int pipe
= pipe_config
->cpu_transcoder
;
8724 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8726 intel_clock_t clock
;
8727 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8729 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8730 fp
= pipe_config
->dpll_hw_state
.fp0
;
8732 fp
= pipe_config
->dpll_hw_state
.fp1
;
8734 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8735 if (IS_PINEVIEW(dev
)) {
8736 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8737 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8739 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8740 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8743 if (!IS_GEN2(dev
)) {
8744 if (IS_PINEVIEW(dev
))
8745 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8748 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8749 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8751 switch (dpll
& DPLL_MODE_MASK
) {
8752 case DPLLB_MODE_DAC_SERIAL
:
8753 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8756 case DPLLB_MODE_LVDS
:
8757 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8762 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8766 if (IS_PINEVIEW(dev
))
8767 pineview_clock(refclk
, &clock
);
8769 i9xx_clock(refclk
, &clock
);
8771 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8772 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8775 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8776 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8778 if (lvds
& LVDS_CLKB_POWER_UP
)
8783 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8786 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8787 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8789 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8795 i9xx_clock(refclk
, &clock
);
8799 * This value includes pixel_multiplier. We will use
8800 * port_clock to compute adjusted_mode.crtc_clock in the
8801 * encoder's get_config() function.
8803 pipe_config
->port_clock
= clock
.dot
;
8806 int intel_dotclock_calculate(int link_freq
,
8807 const struct intel_link_m_n
*m_n
)
8810 * The calculation for the data clock is:
8811 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8812 * But we want to avoid losing precison if possible, so:
8813 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8815 * and the link clock is simpler:
8816 * link_clock = (m * link_clock) / n
8822 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8825 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8826 struct intel_crtc_config
*pipe_config
)
8828 struct drm_device
*dev
= crtc
->base
.dev
;
8830 /* read out port_clock from the DPLL */
8831 i9xx_crtc_clock_get(crtc
, pipe_config
);
8834 * This value does not include pixel_multiplier.
8835 * We will check that port_clock and adjusted_mode.crtc_clock
8836 * agree once we know their relationship in the encoder's
8837 * get_config() function.
8839 pipe_config
->adjusted_mode
.crtc_clock
=
8840 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8841 &pipe_config
->fdi_m_n
);
8844 /** Returns the currently programmed mode of the given pipe. */
8845 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8846 struct drm_crtc
*crtc
)
8848 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8849 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8850 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8851 struct drm_display_mode
*mode
;
8852 struct intel_crtc_config pipe_config
;
8853 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8854 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8855 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8856 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8857 enum pipe pipe
= intel_crtc
->pipe
;
8859 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8864 * Construct a pipe_config sufficient for getting the clock info
8865 * back out of crtc_clock_get.
8867 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8868 * to use a real value here instead.
8870 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8871 pipe_config
.pixel_multiplier
= 1;
8872 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8873 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8874 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8875 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8877 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8878 mode
->hdisplay
= (htot
& 0xffff) + 1;
8879 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8880 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8881 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8882 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8883 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8884 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8885 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8887 drm_mode_set_name(mode
);
8892 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8894 struct drm_device
*dev
= crtc
->dev
;
8895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8896 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8898 if (!HAS_GMCH_DISPLAY(dev
))
8901 if (!dev_priv
->lvds_downclock_avail
)
8905 * Since this is called by a timer, we should never get here in
8908 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8909 int pipe
= intel_crtc
->pipe
;
8910 int dpll_reg
= DPLL(pipe
);
8913 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8915 assert_panel_unlocked(dev_priv
, pipe
);
8917 dpll
= I915_READ(dpll_reg
);
8918 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8919 I915_WRITE(dpll_reg
, dpll
);
8920 intel_wait_for_vblank(dev
, pipe
);
8921 dpll
= I915_READ(dpll_reg
);
8922 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8923 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8928 void intel_mark_busy(struct drm_device
*dev
)
8930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8932 if (dev_priv
->mm
.busy
)
8935 intel_runtime_pm_get(dev_priv
);
8936 i915_update_gfx_val(dev_priv
);
8937 dev_priv
->mm
.busy
= true;
8940 void intel_mark_idle(struct drm_device
*dev
)
8942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8943 struct drm_crtc
*crtc
;
8945 if (!dev_priv
->mm
.busy
)
8948 dev_priv
->mm
.busy
= false;
8950 if (!i915
.powersave
)
8953 for_each_crtc(dev
, crtc
) {
8954 if (!crtc
->primary
->fb
)
8957 intel_decrease_pllclock(crtc
);
8960 if (INTEL_INFO(dev
)->gen
>= 6)
8961 gen6_rps_idle(dev
->dev_private
);
8964 intel_runtime_pm_put(dev_priv
);
8967 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8969 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8970 struct drm_device
*dev
= crtc
->dev
;
8971 struct intel_unpin_work
*work
;
8973 spin_lock_irq(&dev
->event_lock
);
8974 work
= intel_crtc
->unpin_work
;
8975 intel_crtc
->unpin_work
= NULL
;
8976 spin_unlock_irq(&dev
->event_lock
);
8979 cancel_work_sync(&work
->work
);
8983 drm_crtc_cleanup(crtc
);
8988 static void intel_unpin_work_fn(struct work_struct
*__work
)
8990 struct intel_unpin_work
*work
=
8991 container_of(__work
, struct intel_unpin_work
, work
);
8992 struct drm_device
*dev
= work
->crtc
->dev
;
8993 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
8995 mutex_lock(&dev
->struct_mutex
);
8996 intel_unpin_fb_obj(work
->old_fb_obj
);
8997 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8998 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9000 intel_update_fbc(dev
);
9001 mutex_unlock(&dev
->struct_mutex
);
9003 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9005 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9006 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9011 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9012 struct drm_crtc
*crtc
)
9014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9015 struct intel_unpin_work
*work
;
9016 unsigned long flags
;
9018 /* Ignore early vblank irqs */
9019 if (intel_crtc
== NULL
)
9023 * This is called both by irq handlers and the reset code (to complete
9024 * lost pageflips) so needs the full irqsave spinlocks.
9026 spin_lock_irqsave(&dev
->event_lock
, flags
);
9027 work
= intel_crtc
->unpin_work
;
9029 /* Ensure we don't miss a work->pending update ... */
9032 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9033 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9037 page_flip_completed(intel_crtc
);
9039 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9042 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9045 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9047 do_intel_finish_page_flip(dev
, crtc
);
9050 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9053 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9055 do_intel_finish_page_flip(dev
, crtc
);
9058 /* Is 'a' after or equal to 'b'? */
9059 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9061 return !((a
- b
) & 0x80000000);
9064 static bool page_flip_finished(struct intel_crtc
*crtc
)
9066 struct drm_device
*dev
= crtc
->base
.dev
;
9067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9070 * The relevant registers doen't exist on pre-ctg.
9071 * As the flip done interrupt doesn't trigger for mmio
9072 * flips on gmch platforms, a flip count check isn't
9073 * really needed there. But since ctg has the registers,
9074 * include it in the check anyway.
9076 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9080 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9081 * used the same base address. In that case the mmio flip might
9082 * have completed, but the CS hasn't even executed the flip yet.
9084 * A flip count check isn't enough as the CS might have updated
9085 * the base address just after start of vblank, but before we
9086 * managed to process the interrupt. This means we'd complete the
9089 * Combining both checks should get us a good enough result. It may
9090 * still happen that the CS flip has been executed, but has not
9091 * yet actually completed. But in case the base address is the same
9092 * anyway, we don't really care.
9094 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9095 crtc
->unpin_work
->gtt_offset
&&
9096 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9097 crtc
->unpin_work
->flip_count
);
9100 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9103 struct intel_crtc
*intel_crtc
=
9104 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9105 unsigned long flags
;
9109 * This is called both by irq handlers and the reset code (to complete
9110 * lost pageflips) so needs the full irqsave spinlocks.
9112 * NB: An MMIO update of the plane base pointer will also
9113 * generate a page-flip completion irq, i.e. every modeset
9114 * is also accompanied by a spurious intel_prepare_page_flip().
9116 spin_lock_irqsave(&dev
->event_lock
, flags
);
9117 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9118 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9119 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9122 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9124 /* Ensure that the work item is consistent when activating it ... */
9126 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9127 /* and that it is marked active as soon as the irq could fire. */
9131 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9132 struct drm_crtc
*crtc
,
9133 struct drm_framebuffer
*fb
,
9134 struct drm_i915_gem_object
*obj
,
9135 struct intel_engine_cs
*ring
,
9138 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9142 ret
= intel_ring_begin(ring
, 6);
9146 /* Can't queue multiple flips, so wait for the previous
9147 * one to finish before executing the next.
9149 if (intel_crtc
->plane
)
9150 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9152 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9153 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9154 intel_ring_emit(ring
, MI_NOOP
);
9155 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9156 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9157 intel_ring_emit(ring
, fb
->pitches
[0]);
9158 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9159 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9161 intel_mark_page_flip_active(intel_crtc
);
9162 __intel_ring_advance(ring
);
9166 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9167 struct drm_crtc
*crtc
,
9168 struct drm_framebuffer
*fb
,
9169 struct drm_i915_gem_object
*obj
,
9170 struct intel_engine_cs
*ring
,
9173 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9177 ret
= intel_ring_begin(ring
, 6);
9181 if (intel_crtc
->plane
)
9182 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9184 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9185 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9186 intel_ring_emit(ring
, MI_NOOP
);
9187 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9188 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9189 intel_ring_emit(ring
, fb
->pitches
[0]);
9190 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9191 intel_ring_emit(ring
, MI_NOOP
);
9193 intel_mark_page_flip_active(intel_crtc
);
9194 __intel_ring_advance(ring
);
9198 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9199 struct drm_crtc
*crtc
,
9200 struct drm_framebuffer
*fb
,
9201 struct drm_i915_gem_object
*obj
,
9202 struct intel_engine_cs
*ring
,
9205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9207 uint32_t pf
, pipesrc
;
9210 ret
= intel_ring_begin(ring
, 4);
9214 /* i965+ uses the linear or tiled offsets from the
9215 * Display Registers (which do not change across a page-flip)
9216 * so we need only reprogram the base address.
9218 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9219 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9220 intel_ring_emit(ring
, fb
->pitches
[0]);
9221 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9224 /* XXX Enabling the panel-fitter across page-flip is so far
9225 * untested on non-native modes, so ignore it for now.
9226 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9229 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9230 intel_ring_emit(ring
, pf
| pipesrc
);
9232 intel_mark_page_flip_active(intel_crtc
);
9233 __intel_ring_advance(ring
);
9237 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9238 struct drm_crtc
*crtc
,
9239 struct drm_framebuffer
*fb
,
9240 struct drm_i915_gem_object
*obj
,
9241 struct intel_engine_cs
*ring
,
9244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9245 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9246 uint32_t pf
, pipesrc
;
9249 ret
= intel_ring_begin(ring
, 4);
9253 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9254 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9255 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9256 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9258 /* Contrary to the suggestions in the documentation,
9259 * "Enable Panel Fitter" does not seem to be required when page
9260 * flipping with a non-native mode, and worse causes a normal
9262 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9265 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9266 intel_ring_emit(ring
, pf
| pipesrc
);
9268 intel_mark_page_flip_active(intel_crtc
);
9269 __intel_ring_advance(ring
);
9273 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9274 struct drm_crtc
*crtc
,
9275 struct drm_framebuffer
*fb
,
9276 struct drm_i915_gem_object
*obj
,
9277 struct intel_engine_cs
*ring
,
9280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9281 uint32_t plane_bit
= 0;
9284 switch (intel_crtc
->plane
) {
9286 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9289 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9292 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9295 WARN_ONCE(1, "unknown plane in flip command\n");
9300 if (ring
->id
== RCS
) {
9303 * On Gen 8, SRM is now taking an extra dword to accommodate
9304 * 48bits addresses, and we need a NOOP for the batch size to
9312 * BSpec MI_DISPLAY_FLIP for IVB:
9313 * "The full packet must be contained within the same cache line."
9315 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9316 * cacheline, if we ever start emitting more commands before
9317 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9318 * then do the cacheline alignment, and finally emit the
9321 ret
= intel_ring_cacheline_align(ring
);
9325 ret
= intel_ring_begin(ring
, len
);
9329 /* Unmask the flip-done completion message. Note that the bspec says that
9330 * we should do this for both the BCS and RCS, and that we must not unmask
9331 * more than one flip event at any time (or ensure that one flip message
9332 * can be sent by waiting for flip-done prior to queueing new flips).
9333 * Experimentation says that BCS works despite DERRMR masking all
9334 * flip-done completion events and that unmasking all planes at once
9335 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9336 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9338 if (ring
->id
== RCS
) {
9339 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9340 intel_ring_emit(ring
, DERRMR
);
9341 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9342 DERRMR_PIPEB_PRI_FLIP_DONE
|
9343 DERRMR_PIPEC_PRI_FLIP_DONE
));
9345 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9346 MI_SRM_LRM_GLOBAL_GTT
);
9348 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9349 MI_SRM_LRM_GLOBAL_GTT
);
9350 intel_ring_emit(ring
, DERRMR
);
9351 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9353 intel_ring_emit(ring
, 0);
9354 intel_ring_emit(ring
, MI_NOOP
);
9358 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9359 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9360 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9361 intel_ring_emit(ring
, (MI_NOOP
));
9363 intel_mark_page_flip_active(intel_crtc
);
9364 __intel_ring_advance(ring
);
9368 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9369 struct drm_i915_gem_object
*obj
)
9372 * This is not being used for older platforms, because
9373 * non-availability of flip done interrupt forces us to use
9374 * CS flips. Older platforms derive flip done using some clever
9375 * tricks involving the flip_pending status bits and vblank irqs.
9376 * So using MMIO flips there would disrupt this mechanism.
9382 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9385 if (i915
.use_mmio_flip
< 0)
9387 else if (i915
.use_mmio_flip
> 0)
9389 else if (i915
.enable_execlists
)
9392 return ring
!= obj
->ring
;
9395 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9397 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9399 struct intel_framebuffer
*intel_fb
=
9400 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9401 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9403 u32 start_vbl_count
;
9407 intel_mark_page_flip_active(intel_crtc
);
9409 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
9411 reg
= DSPCNTR(intel_crtc
->plane
);
9412 dspcntr
= I915_READ(reg
);
9414 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9415 dspcntr
|= DISPPLANE_TILED
;
9417 dspcntr
&= ~DISPPLANE_TILED
;
9419 I915_WRITE(reg
, dspcntr
);
9421 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9422 intel_crtc
->unpin_work
->gtt_offset
);
9423 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9426 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
9429 static void intel_mmio_flip_work_func(struct work_struct
*work
)
9431 struct intel_crtc
*intel_crtc
=
9432 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
9433 struct intel_engine_cs
*ring
;
9436 seqno
= intel_crtc
->mmio_flip
.seqno
;
9437 ring
= intel_crtc
->mmio_flip
.ring
;
9440 WARN_ON(__i915_wait_seqno(ring
, seqno
,
9441 intel_crtc
->reset_counter
,
9442 false, NULL
, NULL
) != 0);
9444 intel_do_mmio_flip(intel_crtc
);
9447 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9448 struct drm_crtc
*crtc
,
9449 struct drm_framebuffer
*fb
,
9450 struct drm_i915_gem_object
*obj
,
9451 struct intel_engine_cs
*ring
,
9454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9456 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9457 intel_crtc
->mmio_flip
.ring
= obj
->ring
;
9459 schedule_work(&intel_crtc
->mmio_flip
.work
);
9464 static int intel_default_queue_flip(struct drm_device
*dev
,
9465 struct drm_crtc
*crtc
,
9466 struct drm_framebuffer
*fb
,
9467 struct drm_i915_gem_object
*obj
,
9468 struct intel_engine_cs
*ring
,
9474 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9475 struct drm_crtc
*crtc
)
9477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9479 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9482 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9485 if (!work
->enable_stall_check
)
9488 if (work
->flip_ready_vblank
== 0) {
9489 if (work
->flip_queued_ring
&&
9490 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9491 work
->flip_queued_seqno
))
9494 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9497 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9500 /* Potential stall - if we see that the flip has happened,
9501 * assume a missed interrupt. */
9502 if (INTEL_INFO(dev
)->gen
>= 4)
9503 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9505 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9507 /* There is a potential issue here with a false positive after a flip
9508 * to the same address. We could address this by checking for a
9509 * non-incrementing frame counter.
9511 return addr
== work
->gtt_offset
;
9514 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9517 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9518 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9525 spin_lock(&dev
->event_lock
);
9526 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9527 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9528 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9529 page_flip_completed(intel_crtc
);
9531 spin_unlock(&dev
->event_lock
);
9534 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9535 struct drm_framebuffer
*fb
,
9536 struct drm_pending_vblank_event
*event
,
9537 uint32_t page_flip_flags
)
9539 struct drm_device
*dev
= crtc
->dev
;
9540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9541 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9542 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9543 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9544 enum pipe pipe
= intel_crtc
->pipe
;
9545 struct intel_unpin_work
*work
;
9546 struct intel_engine_cs
*ring
;
9550 * drm_mode_page_flip_ioctl() should already catch this, but double
9551 * check to be safe. In the future we may enable pageflipping from
9552 * a disabled primary plane.
9554 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9557 /* Can't change pixel format via MI display flips. */
9558 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9562 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9563 * Note that pitch changes could also affect these register.
9565 if (INTEL_INFO(dev
)->gen
> 3 &&
9566 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9567 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9570 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9573 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9577 work
->event
= event
;
9579 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9580 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9582 ret
= drm_crtc_vblank_get(crtc
);
9586 /* We borrow the event spin lock for protecting unpin_work */
9587 spin_lock_irq(&dev
->event_lock
);
9588 if (intel_crtc
->unpin_work
) {
9589 /* Before declaring the flip queue wedged, check if
9590 * the hardware completed the operation behind our backs.
9592 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9593 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9594 page_flip_completed(intel_crtc
);
9596 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9597 spin_unlock_irq(&dev
->event_lock
);
9599 drm_crtc_vblank_put(crtc
);
9604 intel_crtc
->unpin_work
= work
;
9605 spin_unlock_irq(&dev
->event_lock
);
9607 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9608 flush_workqueue(dev_priv
->wq
);
9610 ret
= i915_mutex_lock_interruptible(dev
);
9614 /* Reference the objects for the scheduled work. */
9615 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9616 drm_gem_object_reference(&obj
->base
);
9618 crtc
->primary
->fb
= fb
;
9620 work
->pending_flip_obj
= obj
;
9622 atomic_inc(&intel_crtc
->unpin_work_count
);
9623 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9625 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9626 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9628 if (IS_VALLEYVIEW(dev
)) {
9629 ring
= &dev_priv
->ring
[BCS
];
9630 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9631 /* vlv: DISPLAY_FLIP fails to change tiling */
9633 } else if (IS_IVYBRIDGE(dev
)) {
9634 ring
= &dev_priv
->ring
[BCS
];
9635 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9637 if (ring
== NULL
|| ring
->id
!= RCS
)
9638 ring
= &dev_priv
->ring
[BCS
];
9640 ring
= &dev_priv
->ring
[RCS
];
9643 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, ring
);
9645 goto cleanup_pending
;
9648 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9650 if (use_mmio_flip(ring
, obj
)) {
9651 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9656 work
->flip_queued_seqno
= obj
->last_write_seqno
;
9657 work
->flip_queued_ring
= obj
->ring
;
9659 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9664 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
9665 work
->flip_queued_ring
= ring
;
9668 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9669 work
->enable_stall_check
= true;
9671 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9672 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9674 intel_disable_fbc(dev
);
9675 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9676 mutex_unlock(&dev
->struct_mutex
);
9678 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9683 intel_unpin_fb_obj(obj
);
9685 atomic_dec(&intel_crtc
->unpin_work_count
);
9686 crtc
->primary
->fb
= old_fb
;
9687 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9688 drm_gem_object_unreference(&obj
->base
);
9689 mutex_unlock(&dev
->struct_mutex
);
9692 spin_lock_irq(&dev
->event_lock
);
9693 intel_crtc
->unpin_work
= NULL
;
9694 spin_unlock_irq(&dev
->event_lock
);
9696 drm_crtc_vblank_put(crtc
);
9702 intel_crtc_wait_for_pending_flips(crtc
);
9703 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9704 if (ret
== 0 && event
) {
9705 spin_lock_irq(&dev
->event_lock
);
9706 drm_send_vblank_event(dev
, pipe
, event
);
9707 spin_unlock_irq(&dev
->event_lock
);
9713 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9714 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9715 .load_lut
= intel_crtc_load_lut
,
9719 * intel_modeset_update_staged_output_state
9721 * Updates the staged output configuration state, e.g. after we've read out the
9724 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9726 struct intel_crtc
*crtc
;
9727 struct intel_encoder
*encoder
;
9728 struct intel_connector
*connector
;
9730 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9732 connector
->new_encoder
=
9733 to_intel_encoder(connector
->base
.encoder
);
9736 for_each_intel_encoder(dev
, encoder
) {
9738 to_intel_crtc(encoder
->base
.crtc
);
9741 for_each_intel_crtc(dev
, crtc
) {
9742 crtc
->new_enabled
= crtc
->base
.enabled
;
9744 if (crtc
->new_enabled
)
9745 crtc
->new_config
= &crtc
->config
;
9747 crtc
->new_config
= NULL
;
9752 * intel_modeset_commit_output_state
9754 * This function copies the stage display pipe configuration to the real one.
9756 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9758 struct intel_crtc
*crtc
;
9759 struct intel_encoder
*encoder
;
9760 struct intel_connector
*connector
;
9762 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9764 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9767 for_each_intel_encoder(dev
, encoder
) {
9768 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9771 for_each_intel_crtc(dev
, crtc
) {
9772 crtc
->base
.enabled
= crtc
->new_enabled
;
9777 connected_sink_compute_bpp(struct intel_connector
*connector
,
9778 struct intel_crtc_config
*pipe_config
)
9780 int bpp
= pipe_config
->pipe_bpp
;
9782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9783 connector
->base
.base
.id
,
9784 connector
->base
.name
);
9786 /* Don't use an invalid EDID bpc value */
9787 if (connector
->base
.display_info
.bpc
&&
9788 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9789 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9790 bpp
, connector
->base
.display_info
.bpc
*3);
9791 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9794 /* Clamp bpp to 8 on screens without EDID 1.4 */
9795 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9796 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9798 pipe_config
->pipe_bpp
= 24;
9803 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9804 struct drm_framebuffer
*fb
,
9805 struct intel_crtc_config
*pipe_config
)
9807 struct drm_device
*dev
= crtc
->base
.dev
;
9808 struct intel_connector
*connector
;
9811 switch (fb
->pixel_format
) {
9813 bpp
= 8*3; /* since we go through a colormap */
9815 case DRM_FORMAT_XRGB1555
:
9816 case DRM_FORMAT_ARGB1555
:
9817 /* checked in intel_framebuffer_init already */
9818 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9820 case DRM_FORMAT_RGB565
:
9821 bpp
= 6*3; /* min is 18bpp */
9823 case DRM_FORMAT_XBGR8888
:
9824 case DRM_FORMAT_ABGR8888
:
9825 /* checked in intel_framebuffer_init already */
9826 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9828 case DRM_FORMAT_XRGB8888
:
9829 case DRM_FORMAT_ARGB8888
:
9832 case DRM_FORMAT_XRGB2101010
:
9833 case DRM_FORMAT_ARGB2101010
:
9834 case DRM_FORMAT_XBGR2101010
:
9835 case DRM_FORMAT_ABGR2101010
:
9836 /* checked in intel_framebuffer_init already */
9837 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9841 /* TODO: gen4+ supports 16 bpc floating point, too. */
9843 DRM_DEBUG_KMS("unsupported depth\n");
9847 pipe_config
->pipe_bpp
= bpp
;
9849 /* Clamp display bpp to EDID value */
9850 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9852 if (!connector
->new_encoder
||
9853 connector
->new_encoder
->new_crtc
!= crtc
)
9856 connected_sink_compute_bpp(connector
, pipe_config
);
9862 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9864 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9865 "type: 0x%x flags: 0x%x\n",
9867 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9868 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9869 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9870 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9873 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9874 struct intel_crtc_config
*pipe_config
,
9875 const char *context
)
9877 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9878 context
, pipe_name(crtc
->pipe
));
9880 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9881 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9882 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9883 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9884 pipe_config
->has_pch_encoder
,
9885 pipe_config
->fdi_lanes
,
9886 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
9887 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
9888 pipe_config
->fdi_m_n
.tu
);
9889 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9890 pipe_config
->has_dp_encoder
,
9891 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
9892 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
9893 pipe_config
->dp_m_n
.tu
);
9895 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9896 pipe_config
->has_dp_encoder
,
9897 pipe_config
->dp_m2_n2
.gmch_m
,
9898 pipe_config
->dp_m2_n2
.gmch_n
,
9899 pipe_config
->dp_m2_n2
.link_m
,
9900 pipe_config
->dp_m2_n2
.link_n
,
9901 pipe_config
->dp_m2_n2
.tu
);
9903 DRM_DEBUG_KMS("requested mode:\n");
9904 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
9905 DRM_DEBUG_KMS("adjusted mode:\n");
9906 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
9907 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
9908 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
9909 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9910 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
9911 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9912 pipe_config
->gmch_pfit
.control
,
9913 pipe_config
->gmch_pfit
.pgm_ratios
,
9914 pipe_config
->gmch_pfit
.lvds_border_bits
);
9915 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9916 pipe_config
->pch_pfit
.pos
,
9917 pipe_config
->pch_pfit
.size
,
9918 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
9919 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
9920 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
9923 static bool encoders_cloneable(const struct intel_encoder
*a
,
9924 const struct intel_encoder
*b
)
9926 /* masks could be asymmetric, so check both ways */
9927 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
9928 b
->cloneable
& (1 << a
->type
));
9931 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
9932 struct intel_encoder
*encoder
)
9934 struct drm_device
*dev
= crtc
->base
.dev
;
9935 struct intel_encoder
*source_encoder
;
9937 for_each_intel_encoder(dev
, source_encoder
) {
9938 if (source_encoder
->new_crtc
!= crtc
)
9941 if (!encoders_cloneable(encoder
, source_encoder
))
9948 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
9950 struct drm_device
*dev
= crtc
->base
.dev
;
9951 struct intel_encoder
*encoder
;
9953 for_each_intel_encoder(dev
, encoder
) {
9954 if (encoder
->new_crtc
!= crtc
)
9957 if (!check_single_encoder_cloning(crtc
, encoder
))
9964 static struct intel_crtc_config
*
9965 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
9966 struct drm_framebuffer
*fb
,
9967 struct drm_display_mode
*mode
)
9969 struct drm_device
*dev
= crtc
->dev
;
9970 struct intel_encoder
*encoder
;
9971 struct intel_crtc_config
*pipe_config
;
9972 int plane_bpp
, ret
= -EINVAL
;
9975 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
9976 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9977 return ERR_PTR(-EINVAL
);
9980 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
9982 return ERR_PTR(-ENOMEM
);
9984 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
9985 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
9987 pipe_config
->cpu_transcoder
=
9988 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
9989 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9992 * Sanitize sync polarity flags based on requested ones. If neither
9993 * positive or negative polarity is requested, treat this as meaning
9994 * negative polarity.
9996 if (!(pipe_config
->adjusted_mode
.flags
&
9997 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
9998 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10000 if (!(pipe_config
->adjusted_mode
.flags
&
10001 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10002 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10004 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10005 * plane pixel format and any sink constraints into account. Returns the
10006 * source plane bpp so that dithering can be selected on mismatches
10007 * after encoders and crtc also have had their say. */
10008 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10014 * Determine the real pipe dimensions. Note that stereo modes can
10015 * increase the actual pipe size due to the frame doubling and
10016 * insertion of additional space for blanks between the frame. This
10017 * is stored in the crtc timings. We use the requested mode to do this
10018 * computation to clearly distinguish it from the adjusted mode, which
10019 * can be changed by the connectors in the below retry loop.
10021 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10022 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10023 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10026 /* Ensure the port clock defaults are reset when retrying. */
10027 pipe_config
->port_clock
= 0;
10028 pipe_config
->pixel_multiplier
= 1;
10030 /* Fill in default crtc timings, allow encoders to overwrite them. */
10031 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10033 /* Pass our mode to the connectors and the CRTC to give them a chance to
10034 * adjust it according to limitations or connector properties, and also
10035 * a chance to reject the mode entirely.
10037 for_each_intel_encoder(dev
, encoder
) {
10039 if (&encoder
->new_crtc
->base
!= crtc
)
10042 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10043 DRM_DEBUG_KMS("Encoder config failure\n");
10048 /* Set default port clock if not overwritten by the encoder. Needs to be
10049 * done afterwards in case the encoder adjusts the mode. */
10050 if (!pipe_config
->port_clock
)
10051 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10052 * pipe_config
->pixel_multiplier
;
10054 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10056 DRM_DEBUG_KMS("CRTC fixup failed\n");
10060 if (ret
== RETRY
) {
10061 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10066 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10068 goto encoder_retry
;
10071 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10072 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10073 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10075 return pipe_config
;
10077 kfree(pipe_config
);
10078 return ERR_PTR(ret
);
10081 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10082 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10084 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10085 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10087 struct intel_crtc
*intel_crtc
;
10088 struct drm_device
*dev
= crtc
->dev
;
10089 struct intel_encoder
*encoder
;
10090 struct intel_connector
*connector
;
10091 struct drm_crtc
*tmp_crtc
;
10093 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10095 /* Check which crtcs have changed outputs connected to them, these need
10096 * to be part of the prepare_pipes mask. We don't (yet) support global
10097 * modeset across multiple crtcs, so modeset_pipes will only have one
10098 * bit set at most. */
10099 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10101 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10104 if (connector
->base
.encoder
) {
10105 tmp_crtc
= connector
->base
.encoder
->crtc
;
10107 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10110 if (connector
->new_encoder
)
10112 1 << connector
->new_encoder
->new_crtc
->pipe
;
10115 for_each_intel_encoder(dev
, encoder
) {
10116 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10119 if (encoder
->base
.crtc
) {
10120 tmp_crtc
= encoder
->base
.crtc
;
10122 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10125 if (encoder
->new_crtc
)
10126 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10129 /* Check for pipes that will be enabled/disabled ... */
10130 for_each_intel_crtc(dev
, intel_crtc
) {
10131 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10134 if (!intel_crtc
->new_enabled
)
10135 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10137 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10141 /* set_mode is also used to update properties on life display pipes. */
10142 intel_crtc
= to_intel_crtc(crtc
);
10143 if (intel_crtc
->new_enabled
)
10144 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10147 * For simplicity do a full modeset on any pipe where the output routing
10148 * changed. We could be more clever, but that would require us to be
10149 * more careful with calling the relevant encoder->mode_set functions.
10151 if (*prepare_pipes
)
10152 *modeset_pipes
= *prepare_pipes
;
10154 /* ... and mask these out. */
10155 *modeset_pipes
&= ~(*disable_pipes
);
10156 *prepare_pipes
&= ~(*disable_pipes
);
10159 * HACK: We don't (yet) fully support global modesets. intel_set_config
10160 * obies this rule, but the modeset restore mode of
10161 * intel_modeset_setup_hw_state does not.
10163 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10164 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10166 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10167 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10170 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10172 struct drm_encoder
*encoder
;
10173 struct drm_device
*dev
= crtc
->dev
;
10175 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10176 if (encoder
->crtc
== crtc
)
10183 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10186 struct intel_encoder
*intel_encoder
;
10187 struct intel_crtc
*intel_crtc
;
10188 struct drm_connector
*connector
;
10190 intel_shared_dpll_commit(dev_priv
);
10192 for_each_intel_encoder(dev
, intel_encoder
) {
10193 if (!intel_encoder
->base
.crtc
)
10196 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10198 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10199 intel_encoder
->connectors_active
= false;
10202 intel_modeset_commit_output_state(dev
);
10204 /* Double check state. */
10205 for_each_intel_crtc(dev
, intel_crtc
) {
10206 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10207 WARN_ON(intel_crtc
->new_config
&&
10208 intel_crtc
->new_config
!= &intel_crtc
->config
);
10209 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10212 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10213 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10216 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10218 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10219 struct drm_property
*dpms_property
=
10220 dev
->mode_config
.dpms_property
;
10222 connector
->dpms
= DRM_MODE_DPMS_ON
;
10223 drm_object_property_set_value(&connector
->base
,
10227 intel_encoder
= to_intel_encoder(connector
->encoder
);
10228 intel_encoder
->connectors_active
= true;
10234 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10238 if (clock1
== clock2
)
10241 if (!clock1
|| !clock2
)
10244 diff
= abs(clock1
- clock2
);
10246 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10252 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10253 list_for_each_entry((intel_crtc), \
10254 &(dev)->mode_config.crtc_list, \
10256 if (mask & (1 <<(intel_crtc)->pipe))
10259 intel_pipe_config_compare(struct drm_device
*dev
,
10260 struct intel_crtc_config
*current_config
,
10261 struct intel_crtc_config
*pipe_config
)
10263 #define PIPE_CONF_CHECK_X(name) \
10264 if (current_config->name != pipe_config->name) { \
10265 DRM_ERROR("mismatch in " #name " " \
10266 "(expected 0x%08x, found 0x%08x)\n", \
10267 current_config->name, \
10268 pipe_config->name); \
10272 #define PIPE_CONF_CHECK_I(name) \
10273 if (current_config->name != pipe_config->name) { \
10274 DRM_ERROR("mismatch in " #name " " \
10275 "(expected %i, found %i)\n", \
10276 current_config->name, \
10277 pipe_config->name); \
10281 /* This is required for BDW+ where there is only one set of registers for
10282 * switching between high and low RR.
10283 * This macro can be used whenever a comparison has to be made between one
10284 * hw state and multiple sw state variables.
10286 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10287 if ((current_config->name != pipe_config->name) && \
10288 (current_config->alt_name != pipe_config->name)) { \
10289 DRM_ERROR("mismatch in " #name " " \
10290 "(expected %i or %i, found %i)\n", \
10291 current_config->name, \
10292 current_config->alt_name, \
10293 pipe_config->name); \
10297 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10298 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10299 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10300 "(expected %i, found %i)\n", \
10301 current_config->name & (mask), \
10302 pipe_config->name & (mask)); \
10306 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10307 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10308 DRM_ERROR("mismatch in " #name " " \
10309 "(expected %i, found %i)\n", \
10310 current_config->name, \
10311 pipe_config->name); \
10315 #define PIPE_CONF_QUIRK(quirk) \
10316 ((current_config->quirks | pipe_config->quirks) & (quirk))
10318 PIPE_CONF_CHECK_I(cpu_transcoder
);
10320 PIPE_CONF_CHECK_I(has_pch_encoder
);
10321 PIPE_CONF_CHECK_I(fdi_lanes
);
10322 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10323 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10324 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10325 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10326 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10328 PIPE_CONF_CHECK_I(has_dp_encoder
);
10330 if (INTEL_INFO(dev
)->gen
< 8) {
10331 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10332 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10333 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10334 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10335 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10337 if (current_config
->has_drrs
) {
10338 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10339 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10340 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10341 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10342 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10345 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10346 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10347 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10348 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10349 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10352 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10353 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10354 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10355 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10356 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10357 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10359 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10360 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10361 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10362 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10363 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10364 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10366 PIPE_CONF_CHECK_I(pixel_multiplier
);
10367 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10368 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10369 IS_VALLEYVIEW(dev
))
10370 PIPE_CONF_CHECK_I(limited_color_range
);
10372 PIPE_CONF_CHECK_I(has_audio
);
10374 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10375 DRM_MODE_FLAG_INTERLACE
);
10377 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10378 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10379 DRM_MODE_FLAG_PHSYNC
);
10380 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10381 DRM_MODE_FLAG_NHSYNC
);
10382 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10383 DRM_MODE_FLAG_PVSYNC
);
10384 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10385 DRM_MODE_FLAG_NVSYNC
);
10388 PIPE_CONF_CHECK_I(pipe_src_w
);
10389 PIPE_CONF_CHECK_I(pipe_src_h
);
10392 * FIXME: BIOS likes to set up a cloned config with lvds+external
10393 * screen. Since we don't yet re-compute the pipe config when moving
10394 * just the lvds port away to another pipe the sw tracking won't match.
10396 * Proper atomic modesets with recomputed global state will fix this.
10397 * Until then just don't check gmch state for inherited modes.
10399 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10400 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10401 /* pfit ratios are autocomputed by the hw on gen4+ */
10402 if (INTEL_INFO(dev
)->gen
< 4)
10403 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10404 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10407 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10408 if (current_config
->pch_pfit
.enabled
) {
10409 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10410 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10413 /* BDW+ don't expose a synchronous way to read the state */
10414 if (IS_HASWELL(dev
))
10415 PIPE_CONF_CHECK_I(ips_enabled
);
10417 PIPE_CONF_CHECK_I(double_wide
);
10419 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10421 PIPE_CONF_CHECK_I(shared_dpll
);
10422 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10423 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10424 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10425 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10426 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10428 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10429 PIPE_CONF_CHECK_I(pipe_bpp
);
10431 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10432 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10434 #undef PIPE_CONF_CHECK_X
10435 #undef PIPE_CONF_CHECK_I
10436 #undef PIPE_CONF_CHECK_I_ALT
10437 #undef PIPE_CONF_CHECK_FLAGS
10438 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10439 #undef PIPE_CONF_QUIRK
10444 static void check_wm_state(struct drm_device
*dev
)
10446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10447 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
10448 struct intel_crtc
*intel_crtc
;
10451 if (INTEL_INFO(dev
)->gen
< 9)
10454 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
10455 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
10457 for_each_intel_crtc(dev
, intel_crtc
) {
10458 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
10459 const enum pipe pipe
= intel_crtc
->pipe
;
10461 if (!intel_crtc
->active
)
10465 for_each_plane(pipe
, plane
) {
10466 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
10467 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
10469 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10472 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10473 "(expected (%u,%u), found (%u,%u))\n",
10474 pipe_name(pipe
), plane
+ 1,
10475 sw_entry
->start
, sw_entry
->end
,
10476 hw_entry
->start
, hw_entry
->end
);
10480 hw_entry
= &hw_ddb
.cursor
[pipe
];
10481 sw_entry
= &sw_ddb
->cursor
[pipe
];
10483 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
10486 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10487 "(expected (%u,%u), found (%u,%u))\n",
10489 sw_entry
->start
, sw_entry
->end
,
10490 hw_entry
->start
, hw_entry
->end
);
10495 check_connector_state(struct drm_device
*dev
)
10497 struct intel_connector
*connector
;
10499 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10501 /* This also checks the encoder/connector hw state with the
10502 * ->get_hw_state callbacks. */
10503 intel_connector_check_state(connector
);
10505 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10506 "connector's staged encoder doesn't match current encoder\n");
10511 check_encoder_state(struct drm_device
*dev
)
10513 struct intel_encoder
*encoder
;
10514 struct intel_connector
*connector
;
10516 for_each_intel_encoder(dev
, encoder
) {
10517 bool enabled
= false;
10518 bool active
= false;
10519 enum pipe pipe
, tracked_pipe
;
10521 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10522 encoder
->base
.base
.id
,
10523 encoder
->base
.name
);
10525 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10526 "encoder's stage crtc doesn't match current crtc\n");
10527 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10528 "encoder's active_connectors set, but no crtc\n");
10530 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10532 if (connector
->base
.encoder
!= &encoder
->base
)
10535 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10539 * for MST connectors if we unplug the connector is gone
10540 * away but the encoder is still connected to a crtc
10541 * until a modeset happens in response to the hotplug.
10543 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10546 WARN(!!encoder
->base
.crtc
!= enabled
,
10547 "encoder's enabled state mismatch "
10548 "(expected %i, found %i)\n",
10549 !!encoder
->base
.crtc
, enabled
);
10550 WARN(active
&& !encoder
->base
.crtc
,
10551 "active encoder with no crtc\n");
10553 WARN(encoder
->connectors_active
!= active
,
10554 "encoder's computed active state doesn't match tracked active state "
10555 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10557 active
= encoder
->get_hw_state(encoder
, &pipe
);
10558 WARN(active
!= encoder
->connectors_active
,
10559 "encoder's hw state doesn't match sw tracking "
10560 "(expected %i, found %i)\n",
10561 encoder
->connectors_active
, active
);
10563 if (!encoder
->base
.crtc
)
10566 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10567 WARN(active
&& pipe
!= tracked_pipe
,
10568 "active encoder's pipe doesn't match"
10569 "(expected %i, found %i)\n",
10570 tracked_pipe
, pipe
);
10576 check_crtc_state(struct drm_device
*dev
)
10578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10579 struct intel_crtc
*crtc
;
10580 struct intel_encoder
*encoder
;
10581 struct intel_crtc_config pipe_config
;
10583 for_each_intel_crtc(dev
, crtc
) {
10584 bool enabled
= false;
10585 bool active
= false;
10587 memset(&pipe_config
, 0, sizeof(pipe_config
));
10589 DRM_DEBUG_KMS("[CRTC:%d]\n",
10590 crtc
->base
.base
.id
);
10592 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10593 "active crtc, but not enabled in sw tracking\n");
10595 for_each_intel_encoder(dev
, encoder
) {
10596 if (encoder
->base
.crtc
!= &crtc
->base
)
10599 if (encoder
->connectors_active
)
10603 WARN(active
!= crtc
->active
,
10604 "crtc's computed active state doesn't match tracked active state "
10605 "(expected %i, found %i)\n", active
, crtc
->active
);
10606 WARN(enabled
!= crtc
->base
.enabled
,
10607 "crtc's computed enabled state doesn't match tracked enabled state "
10608 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10610 active
= dev_priv
->display
.get_pipe_config(crtc
,
10613 /* hw state is inconsistent with the pipe quirk */
10614 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10615 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10616 active
= crtc
->active
;
10618 for_each_intel_encoder(dev
, encoder
) {
10620 if (encoder
->base
.crtc
!= &crtc
->base
)
10622 if (encoder
->get_hw_state(encoder
, &pipe
))
10623 encoder
->get_config(encoder
, &pipe_config
);
10626 WARN(crtc
->active
!= active
,
10627 "crtc active state doesn't match with hw state "
10628 "(expected %i, found %i)\n", crtc
->active
, active
);
10631 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10632 WARN(1, "pipe state doesn't match!\n");
10633 intel_dump_pipe_config(crtc
, &pipe_config
,
10635 intel_dump_pipe_config(crtc
, &crtc
->config
,
10642 check_shared_dpll_state(struct drm_device
*dev
)
10644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10645 struct intel_crtc
*crtc
;
10646 struct intel_dpll_hw_state dpll_hw_state
;
10649 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10650 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10651 int enabled_crtcs
= 0, active_crtcs
= 0;
10654 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10656 DRM_DEBUG_KMS("%s\n", pll
->name
);
10658 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10660 WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
10661 "more active pll users than references: %i vs %i\n",
10662 pll
->active
, hweight32(pll
->config
.crtc_mask
));
10663 WARN(pll
->active
&& !pll
->on
,
10664 "pll in active use but not on in sw tracking\n");
10665 WARN(pll
->on
&& !pll
->active
,
10666 "pll in on but not on in use in sw tracking\n");
10667 WARN(pll
->on
!= active
,
10668 "pll on state mismatch (expected %i, found %i)\n",
10671 for_each_intel_crtc(dev
, crtc
) {
10672 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10674 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10677 WARN(pll
->active
!= active_crtcs
,
10678 "pll active crtcs mismatch (expected %i, found %i)\n",
10679 pll
->active
, active_crtcs
);
10680 WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
10681 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10682 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
10684 WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
10685 sizeof(dpll_hw_state
)),
10686 "pll hw state mismatch\n");
10691 intel_modeset_check_state(struct drm_device
*dev
)
10693 check_wm_state(dev
);
10694 check_connector_state(dev
);
10695 check_encoder_state(dev
);
10696 check_crtc_state(dev
);
10697 check_shared_dpll_state(dev
);
10700 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10704 * FDI already provided one idea for the dotclock.
10705 * Yell if the encoder disagrees.
10707 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10708 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10709 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10712 static void update_scanline_offset(struct intel_crtc
*crtc
)
10714 struct drm_device
*dev
= crtc
->base
.dev
;
10717 * The scanline counter increments at the leading edge of hsync.
10719 * On most platforms it starts counting from vtotal-1 on the
10720 * first active line. That means the scanline counter value is
10721 * always one less than what we would expect. Ie. just after
10722 * start of vblank, which also occurs at start of hsync (on the
10723 * last active line), the scanline counter will read vblank_start-1.
10725 * On gen2 the scanline counter starts counting from 1 instead
10726 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10727 * to keep the value positive), instead of adding one.
10729 * On HSW+ the behaviour of the scanline counter depends on the output
10730 * type. For DP ports it behaves like most other platforms, but on HDMI
10731 * there's an extra 1 line difference. So we need to add two instead of
10732 * one to the value.
10734 if (IS_GEN2(dev
)) {
10735 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10738 vtotal
= mode
->crtc_vtotal
;
10739 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10742 crtc
->scanline_offset
= vtotal
- 1;
10743 } else if (HAS_DDI(dev
) &&
10744 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
10745 crtc
->scanline_offset
= 2;
10747 crtc
->scanline_offset
= 1;
10750 static int __intel_set_mode(struct drm_crtc
*crtc
,
10751 struct drm_display_mode
*mode
,
10752 int x
, int y
, struct drm_framebuffer
*fb
)
10754 struct drm_device
*dev
= crtc
->dev
;
10755 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10756 struct drm_display_mode
*saved_mode
;
10757 struct intel_crtc_config
*pipe_config
= NULL
;
10758 struct intel_crtc
*intel_crtc
;
10759 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10762 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10766 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10767 &prepare_pipes
, &disable_pipes
);
10769 *saved_mode
= crtc
->mode
;
10771 /* Hack: Because we don't (yet) support global modeset on multiple
10772 * crtcs, we don't keep track of the new mode for more than one crtc.
10773 * Hence simply check whether any bit is set in modeset_pipes in all the
10774 * pieces of code that are not yet converted to deal with mutliple crtcs
10775 * changing their mode at the same time. */
10776 if (modeset_pipes
) {
10777 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10778 if (IS_ERR(pipe_config
)) {
10779 ret
= PTR_ERR(pipe_config
);
10780 pipe_config
= NULL
;
10784 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10786 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10790 * See if the config requires any additional preparation, e.g.
10791 * to adjust global state with pipes off. We need to do this
10792 * here so we can get the modeset_pipe updated config for the new
10793 * mode set on this crtc. For other crtcs we need to use the
10794 * adjusted_mode bits in the crtc directly.
10796 if (IS_VALLEYVIEW(dev
)) {
10797 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10799 /* may have added more to prepare_pipes than we should */
10800 prepare_pipes
&= ~disable_pipes
;
10803 if (dev_priv
->display
.crtc_compute_clock
) {
10804 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
10806 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
10810 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10811 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
);
10813 intel_shared_dpll_abort_config(dev_priv
);
10819 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10820 intel_crtc_disable(&intel_crtc
->base
);
10822 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10823 if (intel_crtc
->base
.enabled
)
10824 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10827 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10828 * to set it here already despite that we pass it down the callchain.
10830 if (modeset_pipes
) {
10831 crtc
->mode
= *mode
;
10832 /* mode_set/enable/disable functions rely on a correct pipe
10834 to_intel_crtc(crtc
)->config
= *pipe_config
;
10835 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10838 * Calculate and store various constants which
10839 * are later needed by vblank and swap-completion
10840 * timestamping. They are derived from true hwmode.
10842 drm_calc_timestamping_constants(crtc
,
10843 &pipe_config
->adjusted_mode
);
10846 /* Only after disabling all output pipelines that will be changed can we
10847 * update the the output configuration. */
10848 intel_modeset_update_state(dev
, prepare_pipes
);
10850 modeset_update_crtc_power_domains(dev
);
10852 /* Set up the DPLL and any encoders state that needs to adjust or depend
10855 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10856 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10857 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10858 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10860 mutex_lock(&dev
->struct_mutex
);
10861 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
, NULL
);
10863 DRM_ERROR("pin & fence failed\n");
10864 mutex_unlock(&dev
->struct_mutex
);
10868 intel_unpin_fb_obj(old_obj
);
10869 i915_gem_track_fb(old_obj
, obj
,
10870 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
10871 mutex_unlock(&dev
->struct_mutex
);
10873 crtc
->primary
->fb
= fb
;
10878 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10879 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10880 update_scanline_offset(intel_crtc
);
10882 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
10885 /* FIXME: add subpixel order */
10887 if (ret
&& crtc
->enabled
)
10888 crtc
->mode
= *saved_mode
;
10891 kfree(pipe_config
);
10896 static int intel_set_mode(struct drm_crtc
*crtc
,
10897 struct drm_display_mode
*mode
,
10898 int x
, int y
, struct drm_framebuffer
*fb
)
10902 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
10905 intel_modeset_check_state(crtc
->dev
);
10910 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
10912 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
10915 #undef for_each_intel_crtc_masked
10917 static void intel_set_config_free(struct intel_set_config
*config
)
10922 kfree(config
->save_connector_encoders
);
10923 kfree(config
->save_encoder_crtcs
);
10924 kfree(config
->save_crtc_enabled
);
10928 static int intel_set_config_save_state(struct drm_device
*dev
,
10929 struct intel_set_config
*config
)
10931 struct drm_crtc
*crtc
;
10932 struct drm_encoder
*encoder
;
10933 struct drm_connector
*connector
;
10936 config
->save_crtc_enabled
=
10937 kcalloc(dev
->mode_config
.num_crtc
,
10938 sizeof(bool), GFP_KERNEL
);
10939 if (!config
->save_crtc_enabled
)
10942 config
->save_encoder_crtcs
=
10943 kcalloc(dev
->mode_config
.num_encoder
,
10944 sizeof(struct drm_crtc
*), GFP_KERNEL
);
10945 if (!config
->save_encoder_crtcs
)
10948 config
->save_connector_encoders
=
10949 kcalloc(dev
->mode_config
.num_connector
,
10950 sizeof(struct drm_encoder
*), GFP_KERNEL
);
10951 if (!config
->save_connector_encoders
)
10954 /* Copy data. Note that driver private data is not affected.
10955 * Should anything bad happen only the expected state is
10956 * restored, not the drivers personal bookkeeping.
10959 for_each_crtc(dev
, crtc
) {
10960 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
10964 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
10965 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
10969 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10970 config
->save_connector_encoders
[count
++] = connector
->encoder
;
10976 static void intel_set_config_restore_state(struct drm_device
*dev
,
10977 struct intel_set_config
*config
)
10979 struct intel_crtc
*crtc
;
10980 struct intel_encoder
*encoder
;
10981 struct intel_connector
*connector
;
10985 for_each_intel_crtc(dev
, crtc
) {
10986 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
10988 if (crtc
->new_enabled
)
10989 crtc
->new_config
= &crtc
->config
;
10991 crtc
->new_config
= NULL
;
10995 for_each_intel_encoder(dev
, encoder
) {
10996 encoder
->new_crtc
=
10997 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11001 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11002 connector
->new_encoder
=
11003 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11008 is_crtc_connector_off(struct drm_mode_set
*set
)
11012 if (set
->num_connectors
== 0)
11015 if (WARN_ON(set
->connectors
== NULL
))
11018 for (i
= 0; i
< set
->num_connectors
; i
++)
11019 if (set
->connectors
[i
]->encoder
&&
11020 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11021 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11028 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11029 struct intel_set_config
*config
)
11032 /* We should be able to check here if the fb has the same properties
11033 * and then just flip_or_move it */
11034 if (is_crtc_connector_off(set
)) {
11035 config
->mode_changed
= true;
11036 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11038 * If we have no fb, we can only flip as long as the crtc is
11039 * active, otherwise we need a full mode set. The crtc may
11040 * be active if we've only disabled the primary plane, or
11041 * in fastboot situations.
11043 if (set
->crtc
->primary
->fb
== NULL
) {
11044 struct intel_crtc
*intel_crtc
=
11045 to_intel_crtc(set
->crtc
);
11047 if (intel_crtc
->active
) {
11048 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11049 config
->fb_changed
= true;
11051 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11052 config
->mode_changed
= true;
11054 } else if (set
->fb
== NULL
) {
11055 config
->mode_changed
= true;
11056 } else if (set
->fb
->pixel_format
!=
11057 set
->crtc
->primary
->fb
->pixel_format
) {
11058 config
->mode_changed
= true;
11060 config
->fb_changed
= true;
11064 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11065 config
->fb_changed
= true;
11067 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11068 DRM_DEBUG_KMS("modes are different, full mode set\n");
11069 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11070 drm_mode_debug_printmodeline(set
->mode
);
11071 config
->mode_changed
= true;
11074 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11075 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11079 intel_modeset_stage_output_state(struct drm_device
*dev
,
11080 struct drm_mode_set
*set
,
11081 struct intel_set_config
*config
)
11083 struct intel_connector
*connector
;
11084 struct intel_encoder
*encoder
;
11085 struct intel_crtc
*crtc
;
11088 /* The upper layers ensure that we either disable a crtc or have a list
11089 * of connectors. For paranoia, double-check this. */
11090 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11091 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11093 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11095 /* Otherwise traverse passed in connector list and get encoders
11097 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11098 if (set
->connectors
[ro
] == &connector
->base
) {
11099 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11104 /* If we disable the crtc, disable all its connectors. Also, if
11105 * the connector is on the changing crtc but not on the new
11106 * connector list, disable it. */
11107 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11108 connector
->base
.encoder
&&
11109 connector
->base
.encoder
->crtc
== set
->crtc
) {
11110 connector
->new_encoder
= NULL
;
11112 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11113 connector
->base
.base
.id
,
11114 connector
->base
.name
);
11118 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11119 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11120 config
->mode_changed
= true;
11123 /* connector->new_encoder is now updated for all connectors. */
11125 /* Update crtc of enabled connectors. */
11126 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11128 struct drm_crtc
*new_crtc
;
11130 if (!connector
->new_encoder
)
11133 new_crtc
= connector
->new_encoder
->base
.crtc
;
11135 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11136 if (set
->connectors
[ro
] == &connector
->base
)
11137 new_crtc
= set
->crtc
;
11140 /* Make sure the new CRTC will work with the encoder */
11141 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11145 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11147 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11148 connector
->base
.base
.id
,
11149 connector
->base
.name
,
11150 new_crtc
->base
.id
);
11153 /* Check for any encoders that needs to be disabled. */
11154 for_each_intel_encoder(dev
, encoder
) {
11155 int num_connectors
= 0;
11156 list_for_each_entry(connector
,
11157 &dev
->mode_config
.connector_list
,
11159 if (connector
->new_encoder
== encoder
) {
11160 WARN_ON(!connector
->new_encoder
->new_crtc
);
11165 if (num_connectors
== 0)
11166 encoder
->new_crtc
= NULL
;
11167 else if (num_connectors
> 1)
11170 /* Only now check for crtc changes so we don't miss encoders
11171 * that will be disabled. */
11172 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11173 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11174 config
->mode_changed
= true;
11177 /* Now we've also updated encoder->new_crtc for all encoders. */
11178 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11180 if (connector
->new_encoder
)
11181 if (connector
->new_encoder
!= connector
->encoder
)
11182 connector
->encoder
= connector
->new_encoder
;
11184 for_each_intel_crtc(dev
, crtc
) {
11185 crtc
->new_enabled
= false;
11187 for_each_intel_encoder(dev
, encoder
) {
11188 if (encoder
->new_crtc
== crtc
) {
11189 crtc
->new_enabled
= true;
11194 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11195 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11196 crtc
->new_enabled
? "en" : "dis");
11197 config
->mode_changed
= true;
11200 if (crtc
->new_enabled
)
11201 crtc
->new_config
= &crtc
->config
;
11203 crtc
->new_config
= NULL
;
11209 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11211 struct drm_device
*dev
= crtc
->base
.dev
;
11212 struct intel_encoder
*encoder
;
11213 struct intel_connector
*connector
;
11215 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11216 pipe_name(crtc
->pipe
));
11218 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11219 if (connector
->new_encoder
&&
11220 connector
->new_encoder
->new_crtc
== crtc
)
11221 connector
->new_encoder
= NULL
;
11224 for_each_intel_encoder(dev
, encoder
) {
11225 if (encoder
->new_crtc
== crtc
)
11226 encoder
->new_crtc
= NULL
;
11229 crtc
->new_enabled
= false;
11230 crtc
->new_config
= NULL
;
11233 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11235 struct drm_device
*dev
;
11236 struct drm_mode_set save_set
;
11237 struct intel_set_config
*config
;
11241 BUG_ON(!set
->crtc
);
11242 BUG_ON(!set
->crtc
->helper_private
);
11244 /* Enforce sane interface api - has been abused by the fb helper. */
11245 BUG_ON(!set
->mode
&& set
->fb
);
11246 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11249 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11250 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11251 (int)set
->num_connectors
, set
->x
, set
->y
);
11253 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11256 dev
= set
->crtc
->dev
;
11259 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11263 ret
= intel_set_config_save_state(dev
, config
);
11267 save_set
.crtc
= set
->crtc
;
11268 save_set
.mode
= &set
->crtc
->mode
;
11269 save_set
.x
= set
->crtc
->x
;
11270 save_set
.y
= set
->crtc
->y
;
11271 save_set
.fb
= set
->crtc
->primary
->fb
;
11273 /* Compute whether we need a full modeset, only an fb base update or no
11274 * change at all. In the future we might also check whether only the
11275 * mode changed, e.g. for LVDS where we only change the panel fitter in
11277 intel_set_config_compute_mode_changes(set
, config
);
11279 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11283 if (config
->mode_changed
) {
11284 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11285 set
->x
, set
->y
, set
->fb
);
11286 } else if (config
->fb_changed
) {
11287 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11289 intel_crtc_wait_for_pending_flips(set
->crtc
);
11291 ret
= intel_pipe_set_base(set
->crtc
,
11292 set
->x
, set
->y
, set
->fb
);
11295 * We need to make sure the primary plane is re-enabled if it
11296 * has previously been turned off.
11298 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11299 WARN_ON(!intel_crtc
->active
);
11300 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11304 * In the fastboot case this may be our only check of the
11305 * state after boot. It would be better to only do it on
11306 * the first update, but we don't have a nice way of doing that
11307 * (and really, set_config isn't used much for high freq page
11308 * flipping, so increasing its cost here shouldn't be a big
11311 if (i915
.fastboot
&& ret
== 0)
11312 intel_modeset_check_state(set
->crtc
->dev
);
11316 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11317 set
->crtc
->base
.id
, ret
);
11319 intel_set_config_restore_state(dev
, config
);
11322 * HACK: if the pipe was on, but we didn't have a framebuffer,
11323 * force the pipe off to avoid oopsing in the modeset code
11324 * due to fb==NULL. This should only happen during boot since
11325 * we don't yet reconstruct the FB from the hardware state.
11327 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11328 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11330 /* Try to restore the config */
11331 if (config
->mode_changed
&&
11332 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11333 save_set
.x
, save_set
.y
, save_set
.fb
))
11334 DRM_ERROR("failed to restore config after modeset failure\n");
11338 intel_set_config_free(config
);
11342 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11343 .gamma_set
= intel_crtc_gamma_set
,
11344 .set_config
= intel_crtc_set_config
,
11345 .destroy
= intel_crtc_destroy
,
11346 .page_flip
= intel_crtc_page_flip
,
11349 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11350 struct intel_shared_dpll
*pll
,
11351 struct intel_dpll_hw_state
*hw_state
)
11355 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11358 val
= I915_READ(PCH_DPLL(pll
->id
));
11359 hw_state
->dpll
= val
;
11360 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11361 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11363 return val
& DPLL_VCO_ENABLE
;
11366 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11367 struct intel_shared_dpll
*pll
)
11369 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
11370 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
11373 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11374 struct intel_shared_dpll
*pll
)
11376 /* PCH refclock must be enabled first */
11377 ibx_assert_pch_refclk_enabled(dev_priv
);
11379 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11381 /* Wait for the clocks to stabilize. */
11382 POSTING_READ(PCH_DPLL(pll
->id
));
11385 /* The pixel multiplier can only be updated once the
11386 * DPLL is enabled and the clocks are stable.
11388 * So write it again.
11390 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
11391 POSTING_READ(PCH_DPLL(pll
->id
));
11395 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11396 struct intel_shared_dpll
*pll
)
11398 struct drm_device
*dev
= dev_priv
->dev
;
11399 struct intel_crtc
*crtc
;
11401 /* Make sure no transcoder isn't still depending on us. */
11402 for_each_intel_crtc(dev
, crtc
) {
11403 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11404 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11407 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11408 POSTING_READ(PCH_DPLL(pll
->id
));
11412 static char *ibx_pch_dpll_names
[] = {
11417 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11422 dev_priv
->num_shared_dpll
= 2;
11424 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11425 dev_priv
->shared_dplls
[i
].id
= i
;
11426 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11427 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11428 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11429 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11430 dev_priv
->shared_dplls
[i
].get_hw_state
=
11431 ibx_pch_dpll_get_hw_state
;
11435 static void intel_shared_dpll_init(struct drm_device
*dev
)
11437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11440 intel_ddi_pll_init(dev
);
11441 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11442 ibx_pch_dpll_init(dev
);
11444 dev_priv
->num_shared_dpll
= 0;
11446 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11450 intel_primary_plane_disable(struct drm_plane
*plane
)
11452 struct drm_device
*dev
= plane
->dev
;
11453 struct intel_crtc
*intel_crtc
;
11458 BUG_ON(!plane
->crtc
);
11460 intel_crtc
= to_intel_crtc(plane
->crtc
);
11463 * Even though we checked plane->fb above, it's still possible that
11464 * the primary plane has been implicitly disabled because the crtc
11465 * coordinates given weren't visible, or because we detected
11466 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11467 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11468 * In either case, we need to unpin the FB and let the fb pointer get
11469 * updated, but otherwise we don't need to touch the hardware.
11471 if (!intel_crtc
->primary_enabled
)
11472 goto disable_unpin
;
11474 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11475 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11478 mutex_lock(&dev
->struct_mutex
);
11479 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11480 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11481 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11482 mutex_unlock(&dev
->struct_mutex
);
11489 intel_check_primary_plane(struct drm_plane
*plane
,
11490 struct intel_plane_state
*state
)
11492 struct drm_crtc
*crtc
= state
->crtc
;
11493 struct drm_framebuffer
*fb
= state
->fb
;
11494 struct drm_rect
*dest
= &state
->dst
;
11495 struct drm_rect
*src
= &state
->src
;
11496 const struct drm_rect
*clip
= &state
->clip
;
11498 return drm_plane_helper_check_update(plane
, crtc
, fb
,
11500 DRM_PLANE_HELPER_NO_SCALING
,
11501 DRM_PLANE_HELPER_NO_SCALING
,
11502 false, true, &state
->visible
);
11506 intel_prepare_primary_plane(struct drm_plane
*plane
,
11507 struct intel_plane_state
*state
)
11509 struct drm_crtc
*crtc
= state
->crtc
;
11510 struct drm_framebuffer
*fb
= state
->fb
;
11511 struct drm_device
*dev
= crtc
->dev
;
11512 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11513 enum pipe pipe
= intel_crtc
->pipe
;
11514 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11515 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11518 intel_crtc_wait_for_pending_flips(crtc
);
11520 if (intel_crtc_has_pending_flip(crtc
)) {
11521 DRM_ERROR("pipe is still busy with an old pageflip\n");
11525 if (old_obj
!= obj
) {
11526 mutex_lock(&dev
->struct_mutex
);
11527 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, NULL
);
11529 i915_gem_track_fb(old_obj
, obj
,
11530 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11531 mutex_unlock(&dev
->struct_mutex
);
11533 DRM_DEBUG_KMS("pin & fence failed\n");
11542 intel_commit_primary_plane(struct drm_plane
*plane
,
11543 struct intel_plane_state
*state
)
11545 struct drm_crtc
*crtc
= state
->crtc
;
11546 struct drm_framebuffer
*fb
= state
->fb
;
11547 struct drm_device
*dev
= crtc
->dev
;
11548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11549 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11550 enum pipe pipe
= intel_crtc
->pipe
;
11551 struct drm_framebuffer
*old_fb
= plane
->fb
;
11552 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11553 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11554 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11555 struct drm_rect
*src
= &state
->src
;
11557 crtc
->primary
->fb
= fb
;
11561 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11562 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11563 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11564 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11565 intel_plane
->src_x
= state
->orig_src
.x1
;
11566 intel_plane
->src_y
= state
->orig_src
.y1
;
11567 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11568 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11569 intel_plane
->obj
= obj
;
11571 if (intel_crtc
->active
) {
11573 * FBC does not work on some platforms for rotated
11574 * planes, so disable it when rotation is not 0 and
11575 * update it when rotation is set back to 0.
11577 * FIXME: This is redundant with the fbc update done in
11578 * the primary plane enable function except that that
11579 * one is done too late. We eventually need to unify
11582 if (intel_crtc
->primary_enabled
&&
11583 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11584 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11585 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11586 intel_disable_fbc(dev
);
11589 if (state
->visible
) {
11590 bool was_enabled
= intel_crtc
->primary_enabled
;
11592 /* FIXME: kill this fastboot hack */
11593 intel_update_pipe_size(intel_crtc
);
11595 intel_crtc
->primary_enabled
= true;
11597 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
11601 * BDW signals flip done immediately if the plane
11602 * is disabled, even if the plane enable is already
11603 * armed to occur at the next vblank :(
11605 if (IS_BROADWELL(dev
) && !was_enabled
)
11606 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11609 * If clipping results in a non-visible primary plane,
11610 * we'll disable the primary plane. Note that this is
11611 * a bit different than what happens if userspace
11612 * explicitly disables the plane by passing fb=0
11613 * because plane->fb still gets set and pinned.
11615 intel_disable_primary_hw_plane(plane
, crtc
);
11618 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11620 mutex_lock(&dev
->struct_mutex
);
11621 intel_update_fbc(dev
);
11622 mutex_unlock(&dev
->struct_mutex
);
11625 if (old_fb
&& old_fb
!= fb
) {
11626 if (intel_crtc
->active
)
11627 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
11629 mutex_lock(&dev
->struct_mutex
);
11630 intel_unpin_fb_obj(old_obj
);
11631 mutex_unlock(&dev
->struct_mutex
);
11636 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11637 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11638 unsigned int crtc_w
, unsigned int crtc_h
,
11639 uint32_t src_x
, uint32_t src_y
,
11640 uint32_t src_w
, uint32_t src_h
)
11642 struct intel_plane_state state
;
11643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11649 /* sample coordinates in 16.16 fixed point */
11650 state
.src
.x1
= src_x
;
11651 state
.src
.x2
= src_x
+ src_w
;
11652 state
.src
.y1
= src_y
;
11653 state
.src
.y2
= src_y
+ src_h
;
11655 /* integer pixels */
11656 state
.dst
.x1
= crtc_x
;
11657 state
.dst
.x2
= crtc_x
+ crtc_w
;
11658 state
.dst
.y1
= crtc_y
;
11659 state
.dst
.y2
= crtc_y
+ crtc_h
;
11663 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11664 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11666 state
.orig_src
= state
.src
;
11667 state
.orig_dst
= state
.dst
;
11669 ret
= intel_check_primary_plane(plane
, &state
);
11673 ret
= intel_prepare_primary_plane(plane
, &state
);
11677 intel_commit_primary_plane(plane
, &state
);
11682 /* Common destruction function for both primary and cursor planes */
11683 static void intel_plane_destroy(struct drm_plane
*plane
)
11685 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11686 drm_plane_cleanup(plane
);
11687 kfree(intel_plane
);
11690 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11691 .update_plane
= intel_primary_plane_setplane
,
11692 .disable_plane
= intel_primary_plane_disable
,
11693 .destroy
= intel_plane_destroy
,
11694 .set_property
= intel_plane_set_property
11697 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11700 struct intel_plane
*primary
;
11701 const uint32_t *intel_primary_formats
;
11704 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11705 if (primary
== NULL
)
11708 primary
->can_scale
= false;
11709 primary
->max_downscale
= 1;
11710 primary
->pipe
= pipe
;
11711 primary
->plane
= pipe
;
11712 primary
->rotation
= BIT(DRM_ROTATE_0
);
11713 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11714 primary
->plane
= !pipe
;
11716 if (INTEL_INFO(dev
)->gen
<= 3) {
11717 intel_primary_formats
= intel_primary_formats_gen2
;
11718 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11720 intel_primary_formats
= intel_primary_formats_gen4
;
11721 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11724 drm_universal_plane_init(dev
, &primary
->base
, 0,
11725 &intel_primary_plane_funcs
,
11726 intel_primary_formats
, num_formats
,
11727 DRM_PLANE_TYPE_PRIMARY
);
11729 if (INTEL_INFO(dev
)->gen
>= 4) {
11730 if (!dev
->mode_config
.rotation_property
)
11731 dev
->mode_config
.rotation_property
=
11732 drm_mode_create_rotation_property(dev
,
11733 BIT(DRM_ROTATE_0
) |
11734 BIT(DRM_ROTATE_180
));
11735 if (dev
->mode_config
.rotation_property
)
11736 drm_object_attach_property(&primary
->base
.base
,
11737 dev
->mode_config
.rotation_property
,
11738 primary
->rotation
);
11741 return &primary
->base
;
11745 intel_cursor_plane_disable(struct drm_plane
*plane
)
11750 BUG_ON(!plane
->crtc
);
11752 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11756 intel_check_cursor_plane(struct drm_plane
*plane
,
11757 struct intel_plane_state
*state
)
11759 struct drm_crtc
*crtc
= state
->crtc
;
11760 struct drm_device
*dev
= crtc
->dev
;
11761 struct drm_framebuffer
*fb
= state
->fb
;
11762 struct drm_rect
*dest
= &state
->dst
;
11763 struct drm_rect
*src
= &state
->src
;
11764 const struct drm_rect
*clip
= &state
->clip
;
11765 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11766 int crtc_w
, crtc_h
;
11770 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11772 DRM_PLANE_HELPER_NO_SCALING
,
11773 DRM_PLANE_HELPER_NO_SCALING
,
11774 true, true, &state
->visible
);
11779 /* if we want to turn off the cursor ignore width and height */
11783 /* Check for which cursor types we support */
11784 crtc_w
= drm_rect_width(&state
->orig_dst
);
11785 crtc_h
= drm_rect_height(&state
->orig_dst
);
11786 if (!cursor_size_ok(dev
, crtc_w
, crtc_h
)) {
11787 DRM_DEBUG("Cursor dimension not supported\n");
11791 stride
= roundup_pow_of_two(crtc_w
) * 4;
11792 if (obj
->base
.size
< stride
* crtc_h
) {
11793 DRM_DEBUG_KMS("buffer is too small\n");
11797 if (fb
== crtc
->cursor
->fb
)
11800 /* we only need to pin inside GTT if cursor is non-phy */
11801 mutex_lock(&dev
->struct_mutex
);
11802 if (!INTEL_INFO(dev
)->cursor_needs_physical
&& obj
->tiling_mode
) {
11803 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11806 mutex_unlock(&dev
->struct_mutex
);
11812 intel_commit_cursor_plane(struct drm_plane
*plane
,
11813 struct intel_plane_state
*state
)
11815 struct drm_crtc
*crtc
= state
->crtc
;
11816 struct drm_framebuffer
*fb
= state
->fb
;
11817 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11818 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11819 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11820 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11821 int crtc_w
, crtc_h
;
11823 crtc
->cursor_x
= state
->orig_dst
.x1
;
11824 crtc
->cursor_y
= state
->orig_dst
.y1
;
11826 intel_plane
->crtc_x
= state
->orig_dst
.x1
;
11827 intel_plane
->crtc_y
= state
->orig_dst
.y1
;
11828 intel_plane
->crtc_w
= drm_rect_width(&state
->orig_dst
);
11829 intel_plane
->crtc_h
= drm_rect_height(&state
->orig_dst
);
11830 intel_plane
->src_x
= state
->orig_src
.x1
;
11831 intel_plane
->src_y
= state
->orig_src
.y1
;
11832 intel_plane
->src_w
= drm_rect_width(&state
->orig_src
);
11833 intel_plane
->src_h
= drm_rect_height(&state
->orig_src
);
11834 intel_plane
->obj
= obj
;
11836 if (fb
!= crtc
->cursor
->fb
) {
11837 crtc_w
= drm_rect_width(&state
->orig_dst
);
11838 crtc_h
= drm_rect_height(&state
->orig_dst
);
11839 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11841 intel_crtc_update_cursor(crtc
, state
->visible
);
11843 intel_frontbuffer_flip(crtc
->dev
,
11844 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
11851 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11852 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11853 unsigned int crtc_w
, unsigned int crtc_h
,
11854 uint32_t src_x
, uint32_t src_y
,
11855 uint32_t src_w
, uint32_t src_h
)
11857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11858 struct intel_plane_state state
;
11864 /* sample coordinates in 16.16 fixed point */
11865 state
.src
.x1
= src_x
;
11866 state
.src
.x2
= src_x
+ src_w
;
11867 state
.src
.y1
= src_y
;
11868 state
.src
.y2
= src_y
+ src_h
;
11870 /* integer pixels */
11871 state
.dst
.x1
= crtc_x
;
11872 state
.dst
.x2
= crtc_x
+ crtc_w
;
11873 state
.dst
.y1
= crtc_y
;
11874 state
.dst
.y2
= crtc_y
+ crtc_h
;
11878 state
.clip
.x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0;
11879 state
.clip
.y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0;
11881 state
.orig_src
= state
.src
;
11882 state
.orig_dst
= state
.dst
;
11884 ret
= intel_check_cursor_plane(plane
, &state
);
11888 return intel_commit_cursor_plane(plane
, &state
);
11891 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11892 .update_plane
= intel_cursor_plane_update
,
11893 .disable_plane
= intel_cursor_plane_disable
,
11894 .destroy
= intel_plane_destroy
,
11895 .set_property
= intel_plane_set_property
,
11898 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11901 struct intel_plane
*cursor
;
11903 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11904 if (cursor
== NULL
)
11907 cursor
->can_scale
= false;
11908 cursor
->max_downscale
= 1;
11909 cursor
->pipe
= pipe
;
11910 cursor
->plane
= pipe
;
11911 cursor
->rotation
= BIT(DRM_ROTATE_0
);
11913 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11914 &intel_cursor_plane_funcs
,
11915 intel_cursor_formats
,
11916 ARRAY_SIZE(intel_cursor_formats
),
11917 DRM_PLANE_TYPE_CURSOR
);
11919 if (INTEL_INFO(dev
)->gen
>= 4) {
11920 if (!dev
->mode_config
.rotation_property
)
11921 dev
->mode_config
.rotation_property
=
11922 drm_mode_create_rotation_property(dev
,
11923 BIT(DRM_ROTATE_0
) |
11924 BIT(DRM_ROTATE_180
));
11925 if (dev
->mode_config
.rotation_property
)
11926 drm_object_attach_property(&cursor
->base
.base
,
11927 dev
->mode_config
.rotation_property
,
11931 return &cursor
->base
;
11934 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11937 struct intel_crtc
*intel_crtc
;
11938 struct drm_plane
*primary
= NULL
;
11939 struct drm_plane
*cursor
= NULL
;
11942 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11943 if (intel_crtc
== NULL
)
11946 primary
= intel_primary_plane_create(dev
, pipe
);
11950 cursor
= intel_cursor_plane_create(dev
, pipe
);
11954 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11955 cursor
, &intel_crtc_funcs
);
11959 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11960 for (i
= 0; i
< 256; i
++) {
11961 intel_crtc
->lut_r
[i
] = i
;
11962 intel_crtc
->lut_g
[i
] = i
;
11963 intel_crtc
->lut_b
[i
] = i
;
11967 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11968 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11970 intel_crtc
->pipe
= pipe
;
11971 intel_crtc
->plane
= pipe
;
11972 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11973 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11974 intel_crtc
->plane
= !pipe
;
11977 intel_crtc
->cursor_base
= ~0;
11978 intel_crtc
->cursor_cntl
= ~0;
11979 intel_crtc
->cursor_size
= ~0;
11981 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11982 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11983 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11984 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11986 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
11988 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11990 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11995 drm_plane_cleanup(primary
);
11997 drm_plane_cleanup(cursor
);
12001 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12003 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12004 struct drm_device
*dev
= connector
->base
.dev
;
12006 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12009 return INVALID_PIPE
;
12011 return to_intel_crtc(encoder
->crtc
)->pipe
;
12014 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12015 struct drm_file
*file
)
12017 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12018 struct drm_crtc
*drmmode_crtc
;
12019 struct intel_crtc
*crtc
;
12021 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12024 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12026 if (!drmmode_crtc
) {
12027 DRM_ERROR("no such CRTC id\n");
12031 crtc
= to_intel_crtc(drmmode_crtc
);
12032 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12037 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12039 struct drm_device
*dev
= encoder
->base
.dev
;
12040 struct intel_encoder
*source_encoder
;
12041 int index_mask
= 0;
12044 for_each_intel_encoder(dev
, source_encoder
) {
12045 if (encoders_cloneable(encoder
, source_encoder
))
12046 index_mask
|= (1 << entry
);
12054 static bool has_edp_a(struct drm_device
*dev
)
12056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12058 if (!IS_MOBILE(dev
))
12061 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12064 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12070 const char *intel_output_name(int output
)
12072 static const char *names
[] = {
12073 [INTEL_OUTPUT_UNUSED
] = "Unused",
12074 [INTEL_OUTPUT_ANALOG
] = "Analog",
12075 [INTEL_OUTPUT_DVO
] = "DVO",
12076 [INTEL_OUTPUT_SDVO
] = "SDVO",
12077 [INTEL_OUTPUT_LVDS
] = "LVDS",
12078 [INTEL_OUTPUT_TVOUT
] = "TV",
12079 [INTEL_OUTPUT_HDMI
] = "HDMI",
12080 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12081 [INTEL_OUTPUT_EDP
] = "eDP",
12082 [INTEL_OUTPUT_DSI
] = "DSI",
12083 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12086 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12089 return names
[output
];
12092 static bool intel_crt_present(struct drm_device
*dev
)
12094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12096 if (INTEL_INFO(dev
)->gen
>= 9)
12099 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
12102 if (IS_CHERRYVIEW(dev
))
12105 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12111 static void intel_setup_outputs(struct drm_device
*dev
)
12113 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12114 struct intel_encoder
*encoder
;
12115 bool dpd_is_edp
= false;
12117 intel_lvds_init(dev
);
12119 if (intel_crt_present(dev
))
12120 intel_crt_init(dev
);
12122 if (HAS_DDI(dev
)) {
12125 /* Haswell uses DDI functions to detect digital outputs */
12126 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12127 /* DDI A only supports eDP */
12129 intel_ddi_init(dev
, PORT_A
);
12131 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12133 found
= I915_READ(SFUSE_STRAP
);
12135 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12136 intel_ddi_init(dev
, PORT_B
);
12137 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12138 intel_ddi_init(dev
, PORT_C
);
12139 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12140 intel_ddi_init(dev
, PORT_D
);
12141 } else if (HAS_PCH_SPLIT(dev
)) {
12143 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12145 if (has_edp_a(dev
))
12146 intel_dp_init(dev
, DP_A
, PORT_A
);
12148 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12149 /* PCH SDVOB multiplex with HDMIB */
12150 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12152 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12153 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12154 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12157 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12158 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12160 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12161 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12163 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12164 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12166 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12167 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12168 } else if (IS_VALLEYVIEW(dev
)) {
12170 * The DP_DETECTED bit is the latched state of the DDC
12171 * SDA pin at boot. However since eDP doesn't require DDC
12172 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12173 * eDP ports may have been muxed to an alternate function.
12174 * Thus we can't rely on the DP_DETECTED bit alone to detect
12175 * eDP ports. Consult the VBT as well as DP_DETECTED to
12176 * detect eDP ports.
12178 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
)
12179 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12181 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
12182 intel_dp_is_edp(dev
, PORT_B
))
12183 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12185 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
)
12186 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12188 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
12189 intel_dp_is_edp(dev
, PORT_C
))
12190 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12192 if (IS_CHERRYVIEW(dev
)) {
12193 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
12194 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12196 /* eDP not supported on port D, so don't check VBT */
12197 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12198 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12201 intel_dsi_init(dev
);
12202 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12203 bool found
= false;
12205 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12206 DRM_DEBUG_KMS("probing SDVOB\n");
12207 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12208 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12209 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12210 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12213 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12214 intel_dp_init(dev
, DP_B
, PORT_B
);
12217 /* Before G4X SDVOC doesn't have its own detect register */
12219 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12220 DRM_DEBUG_KMS("probing SDVOC\n");
12221 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12224 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12226 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12227 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12228 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12230 if (SUPPORTS_INTEGRATED_DP(dev
))
12231 intel_dp_init(dev
, DP_C
, PORT_C
);
12234 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12235 (I915_READ(DP_D
) & DP_DETECTED
))
12236 intel_dp_init(dev
, DP_D
, PORT_D
);
12237 } else if (IS_GEN2(dev
))
12238 intel_dvo_init(dev
);
12240 if (SUPPORTS_TV(dev
))
12241 intel_tv_init(dev
);
12243 intel_edp_psr_init(dev
);
12245 for_each_intel_encoder(dev
, encoder
) {
12246 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12247 encoder
->base
.possible_clones
=
12248 intel_encoder_clones(encoder
);
12251 intel_init_pch_refclk(dev
);
12253 drm_helper_move_panel_connectors_to_head(dev
);
12256 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12258 struct drm_device
*dev
= fb
->dev
;
12259 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12261 drm_framebuffer_cleanup(fb
);
12262 mutex_lock(&dev
->struct_mutex
);
12263 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12264 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12265 mutex_unlock(&dev
->struct_mutex
);
12269 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12270 struct drm_file
*file
,
12271 unsigned int *handle
)
12273 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12274 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12276 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12279 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12280 .destroy
= intel_user_framebuffer_destroy
,
12281 .create_handle
= intel_user_framebuffer_create_handle
,
12284 static int intel_framebuffer_init(struct drm_device
*dev
,
12285 struct intel_framebuffer
*intel_fb
,
12286 struct drm_mode_fb_cmd2
*mode_cmd
,
12287 struct drm_i915_gem_object
*obj
)
12289 int aligned_height
;
12293 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12295 if (obj
->tiling_mode
== I915_TILING_Y
) {
12296 DRM_DEBUG("hardware does not support tiling Y\n");
12300 if (mode_cmd
->pitches
[0] & 63) {
12301 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12302 mode_cmd
->pitches
[0]);
12306 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12307 pitch_limit
= 32*1024;
12308 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12309 if (obj
->tiling_mode
)
12310 pitch_limit
= 16*1024;
12312 pitch_limit
= 32*1024;
12313 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12314 if (obj
->tiling_mode
)
12315 pitch_limit
= 8*1024;
12317 pitch_limit
= 16*1024;
12319 /* XXX DSPC is limited to 4k tiled */
12320 pitch_limit
= 8*1024;
12322 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12323 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12324 obj
->tiling_mode
? "tiled" : "linear",
12325 mode_cmd
->pitches
[0], pitch_limit
);
12329 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12330 mode_cmd
->pitches
[0] != obj
->stride
) {
12331 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12332 mode_cmd
->pitches
[0], obj
->stride
);
12336 /* Reject formats not supported by any plane early. */
12337 switch (mode_cmd
->pixel_format
) {
12338 case DRM_FORMAT_C8
:
12339 case DRM_FORMAT_RGB565
:
12340 case DRM_FORMAT_XRGB8888
:
12341 case DRM_FORMAT_ARGB8888
:
12343 case DRM_FORMAT_XRGB1555
:
12344 case DRM_FORMAT_ARGB1555
:
12345 if (INTEL_INFO(dev
)->gen
> 3) {
12346 DRM_DEBUG("unsupported pixel format: %s\n",
12347 drm_get_format_name(mode_cmd
->pixel_format
));
12351 case DRM_FORMAT_XBGR8888
:
12352 case DRM_FORMAT_ABGR8888
:
12353 case DRM_FORMAT_XRGB2101010
:
12354 case DRM_FORMAT_ARGB2101010
:
12355 case DRM_FORMAT_XBGR2101010
:
12356 case DRM_FORMAT_ABGR2101010
:
12357 if (INTEL_INFO(dev
)->gen
< 4) {
12358 DRM_DEBUG("unsupported pixel format: %s\n",
12359 drm_get_format_name(mode_cmd
->pixel_format
));
12363 case DRM_FORMAT_YUYV
:
12364 case DRM_FORMAT_UYVY
:
12365 case DRM_FORMAT_YVYU
:
12366 case DRM_FORMAT_VYUY
:
12367 if (INTEL_INFO(dev
)->gen
< 5) {
12368 DRM_DEBUG("unsupported pixel format: %s\n",
12369 drm_get_format_name(mode_cmd
->pixel_format
));
12374 DRM_DEBUG("unsupported pixel format: %s\n",
12375 drm_get_format_name(mode_cmd
->pixel_format
));
12379 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12380 if (mode_cmd
->offsets
[0] != 0)
12383 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12385 /* FIXME drm helper for size checks (especially planar formats)? */
12386 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12389 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12390 intel_fb
->obj
= obj
;
12391 intel_fb
->obj
->framebuffer_references
++;
12393 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12395 DRM_ERROR("framebuffer init failed %d\n", ret
);
12402 static struct drm_framebuffer
*
12403 intel_user_framebuffer_create(struct drm_device
*dev
,
12404 struct drm_file
*filp
,
12405 struct drm_mode_fb_cmd2
*mode_cmd
)
12407 struct drm_i915_gem_object
*obj
;
12409 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12410 mode_cmd
->handles
[0]));
12411 if (&obj
->base
== NULL
)
12412 return ERR_PTR(-ENOENT
);
12414 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12417 #ifndef CONFIG_DRM_I915_FBDEV
12418 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12423 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12424 .fb_create
= intel_user_framebuffer_create
,
12425 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12428 /* Set up chip specific display functions */
12429 static void intel_init_display(struct drm_device
*dev
)
12431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12433 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12434 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12435 else if (IS_CHERRYVIEW(dev
))
12436 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12437 else if (IS_VALLEYVIEW(dev
))
12438 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12439 else if (IS_PINEVIEW(dev
))
12440 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12442 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12444 if (HAS_DDI(dev
)) {
12445 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12446 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12447 dev_priv
->display
.crtc_compute_clock
=
12448 haswell_crtc_compute_clock
;
12449 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12450 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12451 dev_priv
->display
.off
= ironlake_crtc_off
;
12452 if (INTEL_INFO(dev
)->gen
>= 9)
12453 dev_priv
->display
.update_primary_plane
=
12454 skylake_update_primary_plane
;
12456 dev_priv
->display
.update_primary_plane
=
12457 ironlake_update_primary_plane
;
12458 } else if (HAS_PCH_SPLIT(dev
)) {
12459 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12460 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12461 dev_priv
->display
.crtc_compute_clock
=
12462 ironlake_crtc_compute_clock
;
12463 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12464 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12465 dev_priv
->display
.off
= ironlake_crtc_off
;
12466 dev_priv
->display
.update_primary_plane
=
12467 ironlake_update_primary_plane
;
12468 } else if (IS_VALLEYVIEW(dev
)) {
12469 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12470 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12471 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12472 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12473 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12474 dev_priv
->display
.off
= i9xx_crtc_off
;
12475 dev_priv
->display
.update_primary_plane
=
12476 i9xx_update_primary_plane
;
12478 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12479 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12480 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
12481 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12482 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12483 dev_priv
->display
.off
= i9xx_crtc_off
;
12484 dev_priv
->display
.update_primary_plane
=
12485 i9xx_update_primary_plane
;
12488 /* Returns the core display clock speed */
12489 if (IS_VALLEYVIEW(dev
))
12490 dev_priv
->display
.get_display_clock_speed
=
12491 valleyview_get_display_clock_speed
;
12492 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12493 dev_priv
->display
.get_display_clock_speed
=
12494 i945_get_display_clock_speed
;
12495 else if (IS_I915G(dev
))
12496 dev_priv
->display
.get_display_clock_speed
=
12497 i915_get_display_clock_speed
;
12498 else if (IS_I945GM(dev
) || IS_845G(dev
))
12499 dev_priv
->display
.get_display_clock_speed
=
12500 i9xx_misc_get_display_clock_speed
;
12501 else if (IS_PINEVIEW(dev
))
12502 dev_priv
->display
.get_display_clock_speed
=
12503 pnv_get_display_clock_speed
;
12504 else if (IS_I915GM(dev
))
12505 dev_priv
->display
.get_display_clock_speed
=
12506 i915gm_get_display_clock_speed
;
12507 else if (IS_I865G(dev
))
12508 dev_priv
->display
.get_display_clock_speed
=
12509 i865_get_display_clock_speed
;
12510 else if (IS_I85X(dev
))
12511 dev_priv
->display
.get_display_clock_speed
=
12512 i855_get_display_clock_speed
;
12513 else /* 852, 830 */
12514 dev_priv
->display
.get_display_clock_speed
=
12515 i830_get_display_clock_speed
;
12517 if (IS_GEN5(dev
)) {
12518 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12519 } else if (IS_GEN6(dev
)) {
12520 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12521 } else if (IS_IVYBRIDGE(dev
)) {
12522 /* FIXME: detect B0+ stepping and use auto training */
12523 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12524 dev_priv
->display
.modeset_global_resources
=
12525 ivb_modeset_global_resources
;
12526 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12527 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12528 } else if (IS_VALLEYVIEW(dev
)) {
12529 dev_priv
->display
.modeset_global_resources
=
12530 valleyview_modeset_global_resources
;
12533 /* Default just returns -ENODEV to indicate unsupported */
12534 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12536 switch (INTEL_INFO(dev
)->gen
) {
12538 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12542 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12547 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12551 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12554 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12555 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12559 intel_panel_init_backlight_funcs(dev
);
12561 mutex_init(&dev_priv
->pps_mutex
);
12565 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12566 * resume, or other times. This quirk makes sure that's the case for
12567 * affected systems.
12569 static void quirk_pipea_force(struct drm_device
*dev
)
12571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12573 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12574 DRM_INFO("applying pipe a force quirk\n");
12577 static void quirk_pipeb_force(struct drm_device
*dev
)
12579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12581 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12582 DRM_INFO("applying pipe b force quirk\n");
12586 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12588 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12590 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12591 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12592 DRM_INFO("applying lvds SSC disable quirk\n");
12596 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12599 static void quirk_invert_brightness(struct drm_device
*dev
)
12601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12602 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12603 DRM_INFO("applying inverted panel brightness quirk\n");
12606 /* Some VBT's incorrectly indicate no backlight is present */
12607 static void quirk_backlight_present(struct drm_device
*dev
)
12609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12610 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12611 DRM_INFO("applying backlight present quirk\n");
12614 struct intel_quirk
{
12616 int subsystem_vendor
;
12617 int subsystem_device
;
12618 void (*hook
)(struct drm_device
*dev
);
12621 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12622 struct intel_dmi_quirk
{
12623 void (*hook
)(struct drm_device
*dev
);
12624 const struct dmi_system_id (*dmi_id_list
)[];
12627 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12629 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12633 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12635 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12637 .callback
= intel_dmi_reverse_brightness
,
12638 .ident
= "NCR Corporation",
12639 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12640 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12643 { } /* terminating entry */
12645 .hook
= quirk_invert_brightness
,
12649 static struct intel_quirk intel_quirks
[] = {
12650 /* HP Mini needs pipe A force quirk (LP: #322104) */
12651 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12653 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12654 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12656 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12657 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12659 /* 830 needs to leave pipe A & dpll A up */
12660 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12662 /* 830 needs to leave pipe B & dpll B up */
12663 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12665 /* Lenovo U160 cannot use SSC on LVDS */
12666 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12668 /* Sony Vaio Y cannot use SSC on LVDS */
12669 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12671 /* Acer Aspire 5734Z must invert backlight brightness */
12672 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12674 /* Acer/eMachines G725 */
12675 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12677 /* Acer/eMachines e725 */
12678 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12680 /* Acer/Packard Bell NCL20 */
12681 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12683 /* Acer Aspire 4736Z */
12684 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12686 /* Acer Aspire 5336 */
12687 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12689 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12690 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12692 /* Acer C720 Chromebook (Core i3 4005U) */
12693 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12695 /* Apple Macbook 2,1 (Core 2 T7400) */
12696 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
12698 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12699 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12701 /* HP Chromebook 14 (Celeron 2955U) */
12702 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12705 static void intel_init_quirks(struct drm_device
*dev
)
12707 struct pci_dev
*d
= dev
->pdev
;
12710 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12711 struct intel_quirk
*q
= &intel_quirks
[i
];
12713 if (d
->device
== q
->device
&&
12714 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12715 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12716 (d
->subsystem_device
== q
->subsystem_device
||
12717 q
->subsystem_device
== PCI_ANY_ID
))
12720 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12721 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12722 intel_dmi_quirks
[i
].hook(dev
);
12726 /* Disable the VGA plane that we never use */
12727 static void i915_disable_vga(struct drm_device
*dev
)
12729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12731 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12733 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12734 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12735 outb(SR01
, VGA_SR_INDEX
);
12736 sr1
= inb(VGA_SR_DATA
);
12737 outb(sr1
| 1<<5, VGA_SR_DATA
);
12738 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12742 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12743 * from S3 without preserving (some of?) the other bits.
12745 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12746 POSTING_READ(vga_reg
);
12749 void intel_modeset_init_hw(struct drm_device
*dev
)
12751 intel_prepare_ddi(dev
);
12753 if (IS_VALLEYVIEW(dev
))
12754 vlv_update_cdclk(dev
);
12756 intel_init_clock_gating(dev
);
12758 intel_enable_gt_powersave(dev
);
12761 void intel_modeset_init(struct drm_device
*dev
)
12763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12766 struct intel_crtc
*crtc
;
12768 drm_mode_config_init(dev
);
12770 dev
->mode_config
.min_width
= 0;
12771 dev
->mode_config
.min_height
= 0;
12773 dev
->mode_config
.preferred_depth
= 24;
12774 dev
->mode_config
.prefer_shadow
= 1;
12776 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12778 intel_init_quirks(dev
);
12780 intel_init_pm(dev
);
12782 if (INTEL_INFO(dev
)->num_pipes
== 0)
12785 intel_init_display(dev
);
12786 intel_init_audio(dev
);
12788 if (IS_GEN2(dev
)) {
12789 dev
->mode_config
.max_width
= 2048;
12790 dev
->mode_config
.max_height
= 2048;
12791 } else if (IS_GEN3(dev
)) {
12792 dev
->mode_config
.max_width
= 4096;
12793 dev
->mode_config
.max_height
= 4096;
12795 dev
->mode_config
.max_width
= 8192;
12796 dev
->mode_config
.max_height
= 8192;
12799 if (IS_845G(dev
) || IS_I865G(dev
)) {
12800 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12801 dev
->mode_config
.cursor_height
= 1023;
12802 } else if (IS_GEN2(dev
)) {
12803 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12804 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12806 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12807 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12810 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12812 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12813 INTEL_INFO(dev
)->num_pipes
,
12814 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12816 for_each_pipe(dev_priv
, pipe
) {
12817 intel_crtc_init(dev
, pipe
);
12818 for_each_sprite(pipe
, sprite
) {
12819 ret
= intel_plane_init(dev
, pipe
, sprite
);
12821 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12822 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12826 intel_init_dpio(dev
);
12828 intel_shared_dpll_init(dev
);
12830 /* save the BIOS value before clobbering it */
12831 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
12832 /* Just disable it once at startup */
12833 i915_disable_vga(dev
);
12834 intel_setup_outputs(dev
);
12836 /* Just in case the BIOS is doing something questionable. */
12837 intel_disable_fbc(dev
);
12839 drm_modeset_lock_all(dev
);
12840 intel_modeset_setup_hw_state(dev
, false);
12841 drm_modeset_unlock_all(dev
);
12843 for_each_intel_crtc(dev
, crtc
) {
12848 * Note that reserving the BIOS fb up front prevents us
12849 * from stuffing other stolen allocations like the ring
12850 * on top. This prevents some ugliness at boot time, and
12851 * can even allow for smooth boot transitions if the BIOS
12852 * fb is large enough for the active pipe configuration.
12854 if (dev_priv
->display
.get_plane_config
) {
12855 dev_priv
->display
.get_plane_config(crtc
,
12856 &crtc
->plane_config
);
12858 * If the fb is shared between multiple heads, we'll
12859 * just get the first one.
12861 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12866 static void intel_enable_pipe_a(struct drm_device
*dev
)
12868 struct intel_connector
*connector
;
12869 struct drm_connector
*crt
= NULL
;
12870 struct intel_load_detect_pipe load_detect_temp
;
12871 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12873 /* We can't just switch on the pipe A, we need to set things up with a
12874 * proper mode and output configuration. As a gross hack, enable pipe A
12875 * by enabling the load detect pipe once. */
12876 list_for_each_entry(connector
,
12877 &dev
->mode_config
.connector_list
,
12879 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12880 crt
= &connector
->base
;
12888 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12889 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12893 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12895 struct drm_device
*dev
= crtc
->base
.dev
;
12896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12899 if (INTEL_INFO(dev
)->num_pipes
== 1)
12902 reg
= DSPCNTR(!crtc
->plane
);
12903 val
= I915_READ(reg
);
12905 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12906 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12912 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12914 struct drm_device
*dev
= crtc
->base
.dev
;
12915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12918 /* Clear any frame start delays used for debugging left by the BIOS */
12919 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12920 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12922 /* restore vblank interrupts to correct state */
12923 if (crtc
->active
) {
12924 update_scanline_offset(crtc
);
12925 drm_vblank_on(dev
, crtc
->pipe
);
12927 drm_vblank_off(dev
, crtc
->pipe
);
12929 /* We need to sanitize the plane -> pipe mapping first because this will
12930 * disable the crtc (and hence change the state) if it is wrong. Note
12931 * that gen4+ has a fixed plane -> pipe mapping. */
12932 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12933 struct intel_connector
*connector
;
12936 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12937 crtc
->base
.base
.id
);
12939 /* Pipe has the wrong plane attached and the plane is active.
12940 * Temporarily change the plane mapping and disable everything
12942 plane
= crtc
->plane
;
12943 crtc
->plane
= !plane
;
12944 crtc
->primary_enabled
= true;
12945 dev_priv
->display
.crtc_disable(&crtc
->base
);
12946 crtc
->plane
= plane
;
12948 /* ... and break all links. */
12949 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12951 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12954 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12955 connector
->base
.encoder
= NULL
;
12957 /* multiple connectors may have the same encoder:
12958 * handle them and break crtc link separately */
12959 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12961 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12962 connector
->encoder
->base
.crtc
= NULL
;
12963 connector
->encoder
->connectors_active
= false;
12966 WARN_ON(crtc
->active
);
12967 crtc
->base
.enabled
= false;
12970 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12971 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12972 /* BIOS forgot to enable pipe A, this mostly happens after
12973 * resume. Force-enable the pipe to fix this, the update_dpms
12974 * call below we restore the pipe to the right state, but leave
12975 * the required bits on. */
12976 intel_enable_pipe_a(dev
);
12979 /* Adjust the state of the output pipe according to whether we
12980 * have active connectors/encoders. */
12981 intel_crtc_update_dpms(&crtc
->base
);
12983 if (crtc
->active
!= crtc
->base
.enabled
) {
12984 struct intel_encoder
*encoder
;
12986 /* This can happen either due to bugs in the get_hw_state
12987 * functions or because the pipe is force-enabled due to the
12989 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12990 crtc
->base
.base
.id
,
12991 crtc
->base
.enabled
? "enabled" : "disabled",
12992 crtc
->active
? "enabled" : "disabled");
12994 crtc
->base
.enabled
= crtc
->active
;
12996 /* Because we only establish the connector -> encoder ->
12997 * crtc links if something is active, this means the
12998 * crtc is now deactivated. Break the links. connector
12999 * -> encoder links are only establish when things are
13000 * actually up, hence no need to break them. */
13001 WARN_ON(crtc
->active
);
13003 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13004 WARN_ON(encoder
->connectors_active
);
13005 encoder
->base
.crtc
= NULL
;
13009 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13011 * We start out with underrun reporting disabled to avoid races.
13012 * For correct bookkeeping mark this on active crtcs.
13014 * Also on gmch platforms we dont have any hardware bits to
13015 * disable the underrun reporting. Which means we need to start
13016 * out with underrun reporting disabled also on inactive pipes,
13017 * since otherwise we'll complain about the garbage we read when
13018 * e.g. coming up after runtime pm.
13020 * No protection against concurrent access is required - at
13021 * worst a fifo underrun happens which also sets this to false.
13023 crtc
->cpu_fifo_underrun_disabled
= true;
13024 crtc
->pch_fifo_underrun_disabled
= true;
13028 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13030 struct intel_connector
*connector
;
13031 struct drm_device
*dev
= encoder
->base
.dev
;
13033 /* We need to check both for a crtc link (meaning that the
13034 * encoder is active and trying to read from a pipe) and the
13035 * pipe itself being active. */
13036 bool has_active_crtc
= encoder
->base
.crtc
&&
13037 to_intel_crtc(encoder
->base
.crtc
)->active
;
13039 if (encoder
->connectors_active
&& !has_active_crtc
) {
13040 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13041 encoder
->base
.base
.id
,
13042 encoder
->base
.name
);
13044 /* Connector is active, but has no active pipe. This is
13045 * fallout from our resume register restoring. Disable
13046 * the encoder manually again. */
13047 if (encoder
->base
.crtc
) {
13048 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13049 encoder
->base
.base
.id
,
13050 encoder
->base
.name
);
13051 encoder
->disable(encoder
);
13052 if (encoder
->post_disable
)
13053 encoder
->post_disable(encoder
);
13055 encoder
->base
.crtc
= NULL
;
13056 encoder
->connectors_active
= false;
13058 /* Inconsistent output/port/pipe state happens presumably due to
13059 * a bug in one of the get_hw_state functions. Or someplace else
13060 * in our code, like the register restore mess on resume. Clamp
13061 * things to off as a safer default. */
13062 list_for_each_entry(connector
,
13063 &dev
->mode_config
.connector_list
,
13065 if (connector
->encoder
!= encoder
)
13067 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13068 connector
->base
.encoder
= NULL
;
13071 /* Enabled encoders without active connectors will be fixed in
13072 * the crtc fixup. */
13075 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13078 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13080 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13081 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13082 i915_disable_vga(dev
);
13086 void i915_redisable_vga(struct drm_device
*dev
)
13088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13090 /* This function can be called both from intel_modeset_setup_hw_state or
13091 * at a very early point in our resume sequence, where the power well
13092 * structures are not yet restored. Since this function is at a very
13093 * paranoid "someone might have enabled VGA while we were not looking"
13094 * level, just check if the power well is enabled instead of trying to
13095 * follow the "don't touch the power well if we don't need it" policy
13096 * the rest of the driver uses. */
13097 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13100 i915_redisable_vga_power_on(dev
);
13103 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13105 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13110 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13113 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13117 struct intel_crtc
*crtc
;
13118 struct intel_encoder
*encoder
;
13119 struct intel_connector
*connector
;
13122 for_each_intel_crtc(dev
, crtc
) {
13123 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13125 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13127 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13130 crtc
->base
.enabled
= crtc
->active
;
13131 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13133 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13134 crtc
->base
.base
.id
,
13135 crtc
->active
? "enabled" : "disabled");
13138 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13139 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13141 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
13142 &pll
->config
.hw_state
);
13144 pll
->config
.crtc_mask
= 0;
13145 for_each_intel_crtc(dev
, crtc
) {
13146 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
13148 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
13152 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13153 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
13155 if (pll
->config
.crtc_mask
)
13156 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13159 for_each_intel_encoder(dev
, encoder
) {
13162 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13163 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13164 encoder
->base
.crtc
= &crtc
->base
;
13165 encoder
->get_config(encoder
, &crtc
->config
);
13167 encoder
->base
.crtc
= NULL
;
13170 encoder
->connectors_active
= false;
13171 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13172 encoder
->base
.base
.id
,
13173 encoder
->base
.name
,
13174 encoder
->base
.crtc
? "enabled" : "disabled",
13178 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13180 if (connector
->get_hw_state(connector
)) {
13181 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13182 connector
->encoder
->connectors_active
= true;
13183 connector
->base
.encoder
= &connector
->encoder
->base
;
13185 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13186 connector
->base
.encoder
= NULL
;
13188 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13189 connector
->base
.base
.id
,
13190 connector
->base
.name
,
13191 connector
->base
.encoder
? "enabled" : "disabled");
13195 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13196 * and i915 state tracking structures. */
13197 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13198 bool force_restore
)
13200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13202 struct intel_crtc
*crtc
;
13203 struct intel_encoder
*encoder
;
13206 intel_modeset_readout_hw_state(dev
);
13209 * Now that we have the config, copy it to each CRTC struct
13210 * Note that this could go away if we move to using crtc_config
13211 * checking everywhere.
13213 for_each_intel_crtc(dev
, crtc
) {
13214 if (crtc
->active
&& i915
.fastboot
) {
13215 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13216 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13217 crtc
->base
.base
.id
);
13218 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13222 /* HW state is read out, now we need to sanitize this mess. */
13223 for_each_intel_encoder(dev
, encoder
) {
13224 intel_sanitize_encoder(encoder
);
13227 for_each_pipe(dev_priv
, pipe
) {
13228 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13229 intel_sanitize_crtc(crtc
);
13230 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13233 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13234 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13236 if (!pll
->on
|| pll
->active
)
13239 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13241 pll
->disable(dev_priv
, pll
);
13246 skl_wm_get_hw_state(dev
);
13247 else if (HAS_PCH_SPLIT(dev
))
13248 ilk_wm_get_hw_state(dev
);
13250 if (force_restore
) {
13251 i915_redisable_vga(dev
);
13254 * We need to use raw interfaces for restoring state to avoid
13255 * checking (bogus) intermediate states.
13257 for_each_pipe(dev_priv
, pipe
) {
13258 struct drm_crtc
*crtc
=
13259 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13261 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13262 crtc
->primary
->fb
);
13265 intel_modeset_update_staged_output_state(dev
);
13268 intel_modeset_check_state(dev
);
13271 void intel_modeset_gem_init(struct drm_device
*dev
)
13273 struct drm_crtc
*c
;
13274 struct drm_i915_gem_object
*obj
;
13276 mutex_lock(&dev
->struct_mutex
);
13277 intel_init_gt_powersave(dev
);
13278 mutex_unlock(&dev
->struct_mutex
);
13280 intel_modeset_init_hw(dev
);
13282 intel_setup_overlay(dev
);
13285 * Make sure any fbs we allocated at startup are properly
13286 * pinned & fenced. When we do the allocation it's too early
13289 mutex_lock(&dev
->struct_mutex
);
13290 for_each_crtc(dev
, c
) {
13291 obj
= intel_fb_obj(c
->primary
->fb
);
13295 if (intel_pin_and_fence_fb_obj(c
->primary
,
13298 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13299 to_intel_crtc(c
)->pipe
);
13300 drm_framebuffer_unreference(c
->primary
->fb
);
13301 c
->primary
->fb
= NULL
;
13304 mutex_unlock(&dev
->struct_mutex
);
13307 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13309 struct drm_connector
*connector
= &intel_connector
->base
;
13311 intel_panel_destroy_backlight(connector
);
13312 drm_connector_unregister(connector
);
13315 void intel_modeset_cleanup(struct drm_device
*dev
)
13317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13318 struct drm_connector
*connector
;
13321 * Interrupts and polling as the first thing to avoid creating havoc.
13322 * Too much stuff here (turning of rps, connectors, ...) would
13323 * experience fancy races otherwise.
13325 intel_irq_uninstall(dev_priv
);
13328 * Due to the hpd irq storm handling the hotplug work can re-arm the
13329 * poll handlers. Hence disable polling after hpd handling is shut down.
13331 drm_kms_helper_poll_fini(dev
);
13333 mutex_lock(&dev
->struct_mutex
);
13335 intel_unregister_dsm_handler();
13337 intel_disable_fbc(dev
);
13339 intel_disable_gt_powersave(dev
);
13341 ironlake_teardown_rc6(dev
);
13343 mutex_unlock(&dev
->struct_mutex
);
13345 /* flush any delayed tasks or pending work */
13346 flush_scheduled_work();
13348 /* destroy the backlight and sysfs files before encoders/connectors */
13349 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13350 struct intel_connector
*intel_connector
;
13352 intel_connector
= to_intel_connector(connector
);
13353 intel_connector
->unregister(intel_connector
);
13356 drm_mode_config_cleanup(dev
);
13358 intel_cleanup_overlay(dev
);
13360 mutex_lock(&dev
->struct_mutex
);
13361 intel_cleanup_gt_powersave(dev
);
13362 mutex_unlock(&dev
->struct_mutex
);
13366 * Return which encoder is currently attached for connector.
13368 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13370 return &intel_attached_encoder(connector
)->base
;
13373 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13374 struct intel_encoder
*encoder
)
13376 connector
->encoder
= encoder
;
13377 drm_mode_connector_attach_encoder(&connector
->base
,
13382 * set vga decode state - true == enable VGA decode
13384 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13387 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13390 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13391 DRM_ERROR("failed to read control word\n");
13395 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13399 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13401 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13403 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13404 DRM_ERROR("failed to write control word\n");
13411 struct intel_display_error_state
{
13413 u32 power_well_driver
;
13415 int num_transcoders
;
13417 struct intel_cursor_error_state
{
13422 } cursor
[I915_MAX_PIPES
];
13424 struct intel_pipe_error_state
{
13425 bool power_domain_on
;
13428 } pipe
[I915_MAX_PIPES
];
13430 struct intel_plane_error_state
{
13438 } plane
[I915_MAX_PIPES
];
13440 struct intel_transcoder_error_state
{
13441 bool power_domain_on
;
13442 enum transcoder cpu_transcoder
;
13455 struct intel_display_error_state
*
13456 intel_display_capture_error_state(struct drm_device
*dev
)
13458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13459 struct intel_display_error_state
*error
;
13460 int transcoders
[] = {
13468 if (INTEL_INFO(dev
)->num_pipes
== 0)
13471 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13475 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13476 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13478 for_each_pipe(dev_priv
, i
) {
13479 error
->pipe
[i
].power_domain_on
=
13480 __intel_display_power_is_enabled(dev_priv
,
13481 POWER_DOMAIN_PIPE(i
));
13482 if (!error
->pipe
[i
].power_domain_on
)
13485 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13486 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13487 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13489 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13490 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13491 if (INTEL_INFO(dev
)->gen
<= 3) {
13492 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13493 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13495 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13496 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13497 if (INTEL_INFO(dev
)->gen
>= 4) {
13498 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13499 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13502 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13504 if (HAS_GMCH_DISPLAY(dev
))
13505 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13508 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13509 if (HAS_DDI(dev_priv
->dev
))
13510 error
->num_transcoders
++; /* Account for eDP. */
13512 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13513 enum transcoder cpu_transcoder
= transcoders
[i
];
13515 error
->transcoder
[i
].power_domain_on
=
13516 __intel_display_power_is_enabled(dev_priv
,
13517 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13518 if (!error
->transcoder
[i
].power_domain_on
)
13521 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13523 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13524 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13525 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13526 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13527 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13528 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13529 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13535 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13538 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13539 struct drm_device
*dev
,
13540 struct intel_display_error_state
*error
)
13542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13548 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13549 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13550 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13551 error
->power_well_driver
);
13552 for_each_pipe(dev_priv
, i
) {
13553 err_printf(m
, "Pipe [%d]:\n", i
);
13554 err_printf(m
, " Power: %s\n",
13555 error
->pipe
[i
].power_domain_on
? "on" : "off");
13556 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13557 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13559 err_printf(m
, "Plane [%d]:\n", i
);
13560 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13561 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13562 if (INTEL_INFO(dev
)->gen
<= 3) {
13563 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13564 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13566 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13567 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13568 if (INTEL_INFO(dev
)->gen
>= 4) {
13569 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13570 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13573 err_printf(m
, "Cursor [%d]:\n", i
);
13574 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13575 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13576 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13579 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13580 err_printf(m
, "CPU transcoder: %c\n",
13581 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13582 err_printf(m
, " Power: %s\n",
13583 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13584 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13585 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13586 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13587 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13588 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13589 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13590 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13594 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13596 struct intel_crtc
*crtc
;
13598 for_each_intel_crtc(dev
, crtc
) {
13599 struct intel_unpin_work
*work
;
13601 spin_lock_irq(&dev
->event_lock
);
13603 work
= crtc
->unpin_work
;
13605 if (work
&& work
->event
&&
13606 work
->event
->base
.file_priv
== file
) {
13607 kfree(work
->event
);
13608 work
->event
= NULL
;
13611 spin_unlock_irq(&dev
->event_lock
);