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drm: backmerge tag 'v3.17-rc5' into drm-next
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait timed out\n");
904 }
905
906 /**
907 * intel_wait_for_vblank - wait for vblank on a given pipe
908 * @dev: drm device
909 * @pipe: pipe to wait for
910 *
911 * Wait for vblank to occur on a given pipe. Needed for various bits of
912 * mode setting code.
913 */
914 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
915 {
916 struct drm_i915_private *dev_priv = dev->dev_private;
917 int pipestat_reg = PIPESTAT(pipe);
918
919 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
920 g4x_wait_for_vblank(dev, pipe);
921 return;
922 }
923
924 /* Clear existing vblank status. Note this will clear any other
925 * sticky status fields as well.
926 *
927 * This races with i915_driver_irq_handler() with the result
928 * that either function could miss a vblank event. Here it is not
929 * fatal, as we will either wait upon the next vblank interrupt or
930 * timeout. Generally speaking intel_wait_for_vblank() is only
931 * called during modeset at which time the GPU should be idle and
932 * should *not* be performing page flips and thus not waiting on
933 * vblanks...
934 * Currently, the result of us stealing a vblank from the irq
935 * handler is that a single frame will be skipped during swapbuffers.
936 */
937 I915_WRITE(pipestat_reg,
938 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
939
940 /* Wait for vblank interrupt bit to set */
941 if (wait_for(I915_READ(pipestat_reg) &
942 PIPE_VBLANK_INTERRUPT_STATUS,
943 50))
944 DRM_DEBUG_KMS("vblank wait timed out\n");
945 }
946
947 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 reg = PIPEDSL(pipe);
951 u32 line1, line2;
952 u32 line_mask;
953
954 if (IS_GEN2(dev))
955 line_mask = DSL_LINEMASK_GEN2;
956 else
957 line_mask = DSL_LINEMASK_GEN3;
958
959 line1 = I915_READ(reg) & line_mask;
960 mdelay(5);
961 line2 = I915_READ(reg) & line_mask;
962
963 return line1 == line2;
964 }
965
966 /*
967 * intel_wait_for_pipe_off - wait for pipe to turn off
968 * @dev: drm device
969 * @pipe: pipe to wait for
970 *
971 * After disabling a pipe, we can't wait for vblank in the usual way,
972 * spinning on the vblank interrupt status bit, since we won't actually
973 * see an interrupt when the pipe is disabled.
974 *
975 * On Gen4 and above:
976 * wait for the pipe register state bit to turn off
977 *
978 * Otherwise:
979 * wait for the display line value to settle (it usually
980 * ends up stopping at the start of the next frame).
981 *
982 */
983 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
984 {
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
987 pipe);
988
989 if (INTEL_INFO(dev)->gen >= 4) {
990 int reg = PIPECONF(cpu_transcoder);
991
992 /* Wait for the Pipe State to go off */
993 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
994 100))
995 WARN(1, "pipe_off wait timed out\n");
996 } else {
997 /* Wait for the display line to settle */
998 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
999 WARN(1, "pipe_off wait timed out\n");
1000 }
1001 }
1002
1003 /*
1004 * ibx_digital_port_connected - is the specified port connected?
1005 * @dev_priv: i915 private structure
1006 * @port: the port to test
1007 *
1008 * Returns true if @port is connected, false otherwise.
1009 */
1010 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1011 struct intel_digital_port *port)
1012 {
1013 u32 bit;
1014
1015 if (HAS_PCH_IBX(dev_priv->dev)) {
1016 switch (port->port) {
1017 case PORT_B:
1018 bit = SDE_PORTB_HOTPLUG;
1019 break;
1020 case PORT_C:
1021 bit = SDE_PORTC_HOTPLUG;
1022 break;
1023 case PORT_D:
1024 bit = SDE_PORTD_HOTPLUG;
1025 break;
1026 default:
1027 return true;
1028 }
1029 } else {
1030 switch (port->port) {
1031 case PORT_B:
1032 bit = SDE_PORTB_HOTPLUG_CPT;
1033 break;
1034 case PORT_C:
1035 bit = SDE_PORTC_HOTPLUG_CPT;
1036 break;
1037 case PORT_D:
1038 bit = SDE_PORTD_HOTPLUG_CPT;
1039 break;
1040 default:
1041 return true;
1042 }
1043 }
1044
1045 return I915_READ(SDEISR) & bit;
1046 }
1047
1048 static const char *state_string(bool enabled)
1049 {
1050 return enabled ? "on" : "off";
1051 }
1052
1053 /* Only for pre-ILK configs */
1054 void assert_pll(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, bool state)
1056 {
1057 int reg;
1058 u32 val;
1059 bool cur_state;
1060
1061 reg = DPLL(pipe);
1062 val = I915_READ(reg);
1063 cur_state = !!(val & DPLL_VCO_ENABLE);
1064 WARN(cur_state != state,
1065 "PLL state assertion failure (expected %s, current %s)\n",
1066 state_string(state), state_string(cur_state));
1067 }
1068
1069 /* XXX: the dsi pll is shared between MIPI DSI ports */
1070 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1071 {
1072 u32 val;
1073 bool cur_state;
1074
1075 mutex_lock(&dev_priv->dpio_lock);
1076 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1077 mutex_unlock(&dev_priv->dpio_lock);
1078
1079 cur_state = val & DSI_PLL_VCO_EN;
1080 WARN(cur_state != state,
1081 "DSI PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083 }
1084 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1085 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1086
1087 struct intel_shared_dpll *
1088 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1089 {
1090 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1091
1092 if (crtc->config.shared_dpll < 0)
1093 return NULL;
1094
1095 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1096 }
1097
1098 /* For ILK+ */
1099 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1100 struct intel_shared_dpll *pll,
1101 bool state)
1102 {
1103 bool cur_state;
1104 struct intel_dpll_hw_state hw_state;
1105
1106 if (WARN (!pll,
1107 "asserting DPLL %s with no DPLL\n", state_string(state)))
1108 return;
1109
1110 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1111 WARN(cur_state != state,
1112 "%s assertion failure (expected %s, current %s)\n",
1113 pll->name, state_string(state), state_string(cur_state));
1114 }
1115
1116 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118 {
1119 int reg;
1120 u32 val;
1121 bool cur_state;
1122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
1124
1125 if (HAS_DDI(dev_priv->dev)) {
1126 /* DDI does not have a specific FDI_TX register */
1127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
1135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138 }
1139 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144 {
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
1149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
1152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155 }
1156 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161 {
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1167 return;
1168
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv->dev))
1171 return;
1172
1173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176 }
1177
1178 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1179 enum pipe pipe, bool state)
1180 {
1181 int reg;
1182 u32 val;
1183 bool cur_state;
1184
1185 reg = FDI_RX_CTL(pipe);
1186 val = I915_READ(reg);
1187 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1188 WARN(cur_state != state,
1189 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191 }
1192
1193 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
1195 {
1196 int pp_reg, lvds_reg;
1197 u32 val;
1198 enum pipe panel_pipe = PIPE_A;
1199 bool locked = true;
1200
1201 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1202 pp_reg = PCH_PP_CONTROL;
1203 lvds_reg = PCH_LVDS;
1204 } else {
1205 pp_reg = PP_CONTROL;
1206 lvds_reg = LVDS;
1207 }
1208
1209 val = I915_READ(pp_reg);
1210 if (!(val & PANEL_POWER_ON) ||
1211 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1212 locked = false;
1213
1214 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216
1217 WARN(panel_pipe == pipe && locked,
1218 "panel assertion failure, pipe %c regs locked\n",
1219 pipe_name(pipe));
1220 }
1221
1222 static void assert_cursor(struct drm_i915_private *dev_priv,
1223 enum pipe pipe, bool state)
1224 {
1225 struct drm_device *dev = dev_priv->dev;
1226 bool cur_state;
1227
1228 if (IS_845G(dev) || IS_I865G(dev))
1229 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1230 else
1231 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1232
1233 WARN(cur_state != state,
1234 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1235 pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1238 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1239
1240 void assert_pipe(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, bool state)
1242 {
1243 int reg;
1244 u32 val;
1245 bool cur_state;
1246 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1247 pipe);
1248
1249 /* if we need the pipe A quirk it must be always on */
1250 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1251 state = true;
1252
1253 if (!intel_display_power_enabled(dev_priv,
1254 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1255 cur_state = false;
1256 } else {
1257 reg = PIPECONF(cpu_transcoder);
1258 val = I915_READ(reg);
1259 cur_state = !!(val & PIPECONF_ENABLE);
1260 }
1261
1262 WARN(cur_state != state,
1263 "pipe %c assertion failure (expected %s, current %s)\n",
1264 pipe_name(pipe), state_string(state), state_string(cur_state));
1265 }
1266
1267 static void assert_plane(struct drm_i915_private *dev_priv,
1268 enum plane plane, bool state)
1269 {
1270 int reg;
1271 u32 val;
1272 bool cur_state;
1273
1274 reg = DSPCNTR(plane);
1275 val = I915_READ(reg);
1276 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1277 WARN(cur_state != state,
1278 "plane %c assertion failure (expected %s, current %s)\n",
1279 plane_name(plane), state_string(state), state_string(cur_state));
1280 }
1281
1282 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1283 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1284
1285 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe)
1287 {
1288 struct drm_device *dev = dev_priv->dev;
1289 int reg, i;
1290 u32 val;
1291 int cur_pipe;
1292
1293 /* Primary planes are fixed to pipes on gen4+ */
1294 if (INTEL_INFO(dev)->gen >= 4) {
1295 reg = DSPCNTR(pipe);
1296 val = I915_READ(reg);
1297 WARN(val & DISPLAY_PLANE_ENABLE,
1298 "plane %c assertion failure, should be disabled but not\n",
1299 plane_name(pipe));
1300 return;
1301 }
1302
1303 /* Need to check both planes against the pipe */
1304 for_each_pipe(i) {
1305 reg = DSPCNTR(i);
1306 val = I915_READ(reg);
1307 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1308 DISPPLANE_SEL_PIPE_SHIFT;
1309 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1310 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1311 plane_name(i), pipe_name(pipe));
1312 }
1313 }
1314
1315 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317 {
1318 struct drm_device *dev = dev_priv->dev;
1319 int reg, sprite;
1320 u32 val;
1321
1322 if (IS_VALLEYVIEW(dev)) {
1323 for_each_sprite(pipe, sprite) {
1324 reg = SPCNTR(pipe, sprite);
1325 val = I915_READ(reg);
1326 WARN(val & SP_ENABLE,
1327 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1328 sprite_name(pipe, sprite), pipe_name(pipe));
1329 }
1330 } else if (INTEL_INFO(dev)->gen >= 7) {
1331 reg = SPRCTL(pipe);
1332 val = I915_READ(reg);
1333 WARN(val & SPRITE_ENABLE,
1334 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(pipe), pipe_name(pipe));
1336 } else if (INTEL_INFO(dev)->gen >= 5) {
1337 reg = DVSCNTR(pipe);
1338 val = I915_READ(reg);
1339 WARN(val & DVS_ENABLE,
1340 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(pipe), pipe_name(pipe));
1342 }
1343 }
1344
1345 static void assert_vblank_disabled(struct drm_crtc *crtc)
1346 {
1347 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1348 drm_crtc_vblank_put(crtc);
1349 }
1350
1351 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1352 {
1353 u32 val;
1354 bool enabled;
1355
1356 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1357
1358 val = I915_READ(PCH_DREF_CONTROL);
1359 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1360 DREF_SUPERSPREAD_SOURCE_MASK));
1361 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1362 }
1363
1364 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366 {
1367 int reg;
1368 u32 val;
1369 bool enabled;
1370
1371 reg = PCH_TRANSCONF(pipe);
1372 val = I915_READ(reg);
1373 enabled = !!(val & TRANS_ENABLE);
1374 WARN(enabled,
1375 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1376 pipe_name(pipe));
1377 }
1378
1379 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 port_sel, u32 val)
1381 {
1382 if ((val & DP_PORT_EN) == 0)
1383 return false;
1384
1385 if (HAS_PCH_CPT(dev_priv->dev)) {
1386 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1387 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1388 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1389 return false;
1390 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1391 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1392 return false;
1393 } else {
1394 if ((val & DP_PIPE_MASK) != (pipe << 30))
1395 return false;
1396 }
1397 return true;
1398 }
1399
1400 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe, u32 val)
1402 {
1403 if ((val & SDVO_ENABLE) == 0)
1404 return false;
1405
1406 if (HAS_PCH_CPT(dev_priv->dev)) {
1407 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1408 return false;
1409 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1410 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1411 return false;
1412 } else {
1413 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & LVDS_PORT_EN) == 0)
1423 return false;
1424
1425 if (HAS_PCH_CPT(dev_priv->dev)) {
1426 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1427 return false;
1428 } else {
1429 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, u32 val)
1437 {
1438 if ((val & ADPA_DAC_ENABLE) == 0)
1439 return false;
1440 if (HAS_PCH_CPT(dev_priv->dev)) {
1441 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1442 return false;
1443 } else {
1444 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1445 return false;
1446 }
1447 return true;
1448 }
1449
1450 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, int reg, u32 port_sel)
1452 {
1453 u32 val = I915_READ(reg);
1454 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1455 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1456 reg, pipe_name(pipe));
1457
1458 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1459 && (val & DP_PIPEB_SELECT),
1460 "IBX PCH dp port still using transcoder B\n");
1461 }
1462
1463 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe, int reg)
1465 {
1466 u32 val = I915_READ(reg);
1467 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1468 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1469 reg, pipe_name(pipe));
1470
1471 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1472 && (val & SDVO_PIPE_B_SELECT),
1473 "IBX PCH hdmi port still using transcoder B\n");
1474 }
1475
1476 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe)
1478 {
1479 int reg;
1480 u32 val;
1481
1482 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1483 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1484 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1485
1486 reg = PCH_ADPA;
1487 val = I915_READ(reg);
1488 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1489 "PCH VGA enabled on transcoder %c, should be disabled\n",
1490 pipe_name(pipe));
1491
1492 reg = PCH_LVDS;
1493 val = I915_READ(reg);
1494 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1495 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1496 pipe_name(pipe));
1497
1498 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1499 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1500 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1501 }
1502
1503 static void intel_init_dpio(struct drm_device *dev)
1504 {
1505 struct drm_i915_private *dev_priv = dev->dev_private;
1506
1507 if (!IS_VALLEYVIEW(dev))
1508 return;
1509
1510 /*
1511 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1512 * CHV x1 PHY (DP/HDMI D)
1513 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1514 */
1515 if (IS_CHERRYVIEW(dev)) {
1516 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1517 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1518 } else {
1519 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1520 }
1521 }
1522
1523 static void vlv_enable_pll(struct intel_crtc *crtc)
1524 {
1525 struct drm_device *dev = crtc->base.dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 int reg = DPLL(crtc->pipe);
1528 u32 dpll = crtc->config.dpll_hw_state.dpll;
1529
1530 assert_pipe_disabled(dev_priv, crtc->pipe);
1531
1532 /* No really, not for ILK+ */
1533 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1534
1535 /* PLL is protected by panel, make sure we can write it */
1536 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1537 assert_panel_unlocked(dev_priv, crtc->pipe);
1538
1539 I915_WRITE(reg, dpll);
1540 POSTING_READ(reg);
1541 udelay(150);
1542
1543 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1544 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1545
1546 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1547 POSTING_READ(DPLL_MD(crtc->pipe));
1548
1549 /* We do this three times for luck */
1550 I915_WRITE(reg, dpll);
1551 POSTING_READ(reg);
1552 udelay(150); /* wait for warmup */
1553 I915_WRITE(reg, dpll);
1554 POSTING_READ(reg);
1555 udelay(150); /* wait for warmup */
1556 I915_WRITE(reg, dpll);
1557 POSTING_READ(reg);
1558 udelay(150); /* wait for warmup */
1559 }
1560
1561 static void chv_enable_pll(struct intel_crtc *crtc)
1562 {
1563 struct drm_device *dev = crtc->base.dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 int pipe = crtc->pipe;
1566 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1567 u32 tmp;
1568
1569 assert_pipe_disabled(dev_priv, crtc->pipe);
1570
1571 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1572
1573 mutex_lock(&dev_priv->dpio_lock);
1574
1575 /* Enable back the 10bit clock to display controller */
1576 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1577 tmp |= DPIO_DCLKP_EN;
1578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1579
1580 /*
1581 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1582 */
1583 udelay(1);
1584
1585 /* Enable PLL */
1586 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1587
1588 /* Check PLL is locked */
1589 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1590 DRM_ERROR("PLL %d failed to lock\n", pipe);
1591
1592 /* not sure when this should be written */
1593 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1594 POSTING_READ(DPLL_MD(pipe));
1595
1596 mutex_unlock(&dev_priv->dpio_lock);
1597 }
1598
1599 static void i9xx_enable_pll(struct intel_crtc *crtc)
1600 {
1601 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config.dpll_hw_state.dpll;
1605
1606 assert_pipe_disabled(dev_priv, crtc->pipe);
1607
1608 /* No really, not for ILK+ */
1609 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1610
1611 /* PLL is protected by panel, make sure we can write it */
1612 if (IS_MOBILE(dev) && !IS_I830(dev))
1613 assert_panel_unlocked(dev_priv, crtc->pipe);
1614
1615 I915_WRITE(reg, dpll);
1616
1617 /* Wait for the clocks to stabilize. */
1618 POSTING_READ(reg);
1619 udelay(150);
1620
1621 if (INTEL_INFO(dev)->gen >= 4) {
1622 I915_WRITE(DPLL_MD(crtc->pipe),
1623 crtc->config.dpll_hw_state.dpll_md);
1624 } else {
1625 /* The pixel multiplier can only be updated once the
1626 * DPLL is enabled and the clocks are stable.
1627 *
1628 * So write it again.
1629 */
1630 I915_WRITE(reg, dpll);
1631 }
1632
1633 /* We do this three times for luck */
1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150); /* wait for warmup */
1637 I915_WRITE(reg, dpll);
1638 POSTING_READ(reg);
1639 udelay(150); /* wait for warmup */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 }
1644
1645 /**
1646 * i9xx_disable_pll - disable a PLL
1647 * @dev_priv: i915 private structure
1648 * @pipe: pipe PLL to disable
1649 *
1650 * Disable the PLL for @pipe, making sure the pipe is off first.
1651 *
1652 * Note! This is for pre-ILK only.
1653 */
1654 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1655 {
1656 /* Don't disable pipe A or pipe A PLLs if needed */
1657 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1658 return;
1659
1660 /* Make sure the pipe isn't still relying on us */
1661 assert_pipe_disabled(dev_priv, pipe);
1662
1663 I915_WRITE(DPLL(pipe), 0);
1664 POSTING_READ(DPLL(pipe));
1665 }
1666
1667 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 u32 val = 0;
1670
1671 /* Make sure the pipe isn't still relying on us */
1672 assert_pipe_disabled(dev_priv, pipe);
1673
1674 /*
1675 * Leave integrated clock source and reference clock enabled for pipe B.
1676 * The latter is needed for VGA hotplug / manual detection.
1677 */
1678 if (pipe == PIPE_B)
1679 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1680 I915_WRITE(DPLL(pipe), val);
1681 POSTING_READ(DPLL(pipe));
1682
1683 }
1684
1685 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1686 {
1687 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1688 u32 val;
1689
1690 /* Make sure the pipe isn't still relying on us */
1691 assert_pipe_disabled(dev_priv, pipe);
1692
1693 /* Set PLL en = 0 */
1694 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1695 if (pipe != PIPE_A)
1696 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1697 I915_WRITE(DPLL(pipe), val);
1698 POSTING_READ(DPLL(pipe));
1699
1700 mutex_lock(&dev_priv->dpio_lock);
1701
1702 /* Disable 10bit clock to display controller */
1703 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1704 val &= ~DPIO_DCLKP_EN;
1705 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1706
1707 /* disable left/right clock distribution */
1708 if (pipe != PIPE_B) {
1709 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1710 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1711 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1712 } else {
1713 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1714 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1715 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1716 }
1717
1718 mutex_unlock(&dev_priv->dpio_lock);
1719 }
1720
1721 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1722 struct intel_digital_port *dport)
1723 {
1724 u32 port_mask;
1725 int dpll_reg;
1726
1727 switch (dport->port) {
1728 case PORT_B:
1729 port_mask = DPLL_PORTB_READY_MASK;
1730 dpll_reg = DPLL(0);
1731 break;
1732 case PORT_C:
1733 port_mask = DPLL_PORTC_READY_MASK;
1734 dpll_reg = DPLL(0);
1735 break;
1736 case PORT_D:
1737 port_mask = DPLL_PORTD_READY_MASK;
1738 dpll_reg = DPIO_PHY_STATUS;
1739 break;
1740 default:
1741 BUG();
1742 }
1743
1744 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1745 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1746 port_name(dport->port), I915_READ(dpll_reg));
1747 }
1748
1749 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1750 {
1751 struct drm_device *dev = crtc->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1754
1755 if (WARN_ON(pll == NULL))
1756 return;
1757
1758 WARN_ON(!pll->refcount);
1759 if (pll->active == 0) {
1760 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1761 WARN_ON(pll->on);
1762 assert_shared_dpll_disabled(dev_priv, pll);
1763
1764 pll->mode_set(dev_priv, pll);
1765 }
1766 }
1767
1768 /**
1769 * intel_enable_shared_dpll - enable PCH PLL
1770 * @dev_priv: i915 private structure
1771 * @pipe: pipe PLL to enable
1772 *
1773 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1774 * drives the transcoder clock.
1775 */
1776 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1777 {
1778 struct drm_device *dev = crtc->base.dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1781
1782 if (WARN_ON(pll == NULL))
1783 return;
1784
1785 if (WARN_ON(pll->refcount == 0))
1786 return;
1787
1788 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1789 pll->name, pll->active, pll->on,
1790 crtc->base.base.id);
1791
1792 if (pll->active++) {
1793 WARN_ON(!pll->on);
1794 assert_shared_dpll_enabled(dev_priv, pll);
1795 return;
1796 }
1797 WARN_ON(pll->on);
1798
1799 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1800
1801 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1802 pll->enable(dev_priv, pll);
1803 pll->on = true;
1804 }
1805
1806 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1811
1812 /* PCH only available on ILK+ */
1813 BUG_ON(INTEL_INFO(dev)->gen < 5);
1814 if (WARN_ON(pll == NULL))
1815 return;
1816
1817 if (WARN_ON(pll->refcount == 0))
1818 return;
1819
1820 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1821 pll->name, pll->active, pll->on,
1822 crtc->base.base.id);
1823
1824 if (WARN_ON(pll->active == 0)) {
1825 assert_shared_dpll_disabled(dev_priv, pll);
1826 return;
1827 }
1828
1829 assert_shared_dpll_enabled(dev_priv, pll);
1830 WARN_ON(!pll->on);
1831 if (--pll->active)
1832 return;
1833
1834 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1835 pll->disable(dev_priv, pll);
1836 pll->on = false;
1837
1838 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1839 }
1840
1841 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1842 enum pipe pipe)
1843 {
1844 struct drm_device *dev = dev_priv->dev;
1845 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 uint32_t reg, val, pipeconf_val;
1848
1849 /* PCH only available on ILK+ */
1850 BUG_ON(INTEL_INFO(dev)->gen < 5);
1851
1852 /* Make sure PCH DPLL is enabled */
1853 assert_shared_dpll_enabled(dev_priv,
1854 intel_crtc_to_shared_dpll(intel_crtc));
1855
1856 /* FDI must be feeding us bits for PCH ports */
1857 assert_fdi_tx_enabled(dev_priv, pipe);
1858 assert_fdi_rx_enabled(dev_priv, pipe);
1859
1860 if (HAS_PCH_CPT(dev)) {
1861 /* Workaround: Set the timing override bit before enabling the
1862 * pch transcoder. */
1863 reg = TRANS_CHICKEN2(pipe);
1864 val = I915_READ(reg);
1865 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1866 I915_WRITE(reg, val);
1867 }
1868
1869 reg = PCH_TRANSCONF(pipe);
1870 val = I915_READ(reg);
1871 pipeconf_val = I915_READ(PIPECONF(pipe));
1872
1873 if (HAS_PCH_IBX(dev_priv->dev)) {
1874 /*
1875 * make the BPC in transcoder be consistent with
1876 * that in pipeconf reg.
1877 */
1878 val &= ~PIPECONF_BPC_MASK;
1879 val |= pipeconf_val & PIPECONF_BPC_MASK;
1880 }
1881
1882 val &= ~TRANS_INTERLACE_MASK;
1883 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1884 if (HAS_PCH_IBX(dev_priv->dev) &&
1885 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1886 val |= TRANS_LEGACY_INTERLACED_ILK;
1887 else
1888 val |= TRANS_INTERLACED;
1889 else
1890 val |= TRANS_PROGRESSIVE;
1891
1892 I915_WRITE(reg, val | TRANS_ENABLE);
1893 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1894 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1895 }
1896
1897 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1898 enum transcoder cpu_transcoder)
1899 {
1900 u32 val, pipeconf_val;
1901
1902 /* PCH only available on ILK+ */
1903 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1904
1905 /* FDI must be feeding us bits for PCH ports */
1906 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1907 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1908
1909 /* Workaround: set timing override bit. */
1910 val = I915_READ(_TRANSA_CHICKEN2);
1911 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(_TRANSA_CHICKEN2, val);
1913
1914 val = TRANS_ENABLE;
1915 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1916
1917 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1918 PIPECONF_INTERLACED_ILK)
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(LPT_TRANSCONF, val);
1924 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("Failed to enable PCH transcoder\n");
1926 }
1927
1928 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum pipe pipe)
1930 {
1931 struct drm_device *dev = dev_priv->dev;
1932 uint32_t reg, val;
1933
1934 /* FDI relies on the transcoder */
1935 assert_fdi_tx_disabled(dev_priv, pipe);
1936 assert_fdi_rx_disabled(dev_priv, pipe);
1937
1938 /* Ports must be off as well */
1939 assert_pch_ports_disabled(dev_priv, pipe);
1940
1941 reg = PCH_TRANSCONF(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_ENABLE;
1944 I915_WRITE(reg, val);
1945 /* wait for PCH transcoder off, transcoder state */
1946 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1947 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1948
1949 if (!HAS_PCH_IBX(dev)) {
1950 /* Workaround: Clear the timing override chicken bit again. */
1951 reg = TRANS_CHICKEN2(pipe);
1952 val = I915_READ(reg);
1953 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1954 I915_WRITE(reg, val);
1955 }
1956 }
1957
1958 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1959 {
1960 u32 val;
1961
1962 val = I915_READ(LPT_TRANSCONF);
1963 val &= ~TRANS_ENABLE;
1964 I915_WRITE(LPT_TRANSCONF, val);
1965 /* wait for PCH transcoder off, transcoder state */
1966 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1967 DRM_ERROR("Failed to disable PCH transcoder\n");
1968
1969 /* Workaround: clear timing override bit. */
1970 val = I915_READ(_TRANSA_CHICKEN2);
1971 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1972 I915_WRITE(_TRANSA_CHICKEN2, val);
1973 }
1974
1975 /**
1976 * intel_enable_pipe - enable a pipe, asserting requirements
1977 * @crtc: crtc responsible for the pipe
1978 *
1979 * Enable @crtc's pipe, making sure that various hardware specific requirements
1980 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1981 */
1982 static void intel_enable_pipe(struct intel_crtc *crtc)
1983 {
1984 struct drm_device *dev = crtc->base.dev;
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 enum pipe pipe = crtc->pipe;
1987 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1988 pipe);
1989 enum pipe pch_transcoder;
1990 int reg;
1991 u32 val;
1992
1993 assert_planes_disabled(dev_priv, pipe);
1994 assert_cursor_disabled(dev_priv, pipe);
1995 assert_sprites_disabled(dev_priv, pipe);
1996
1997 if (HAS_PCH_LPT(dev_priv->dev))
1998 pch_transcoder = TRANSCODER_A;
1999 else
2000 pch_transcoder = pipe;
2001
2002 /*
2003 * A pipe without a PLL won't actually be able to drive bits from
2004 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2005 * need the check.
2006 */
2007 if (!HAS_PCH_SPLIT(dev_priv->dev))
2008 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2009 assert_dsi_pll_enabled(dev_priv);
2010 else
2011 assert_pll_enabled(dev_priv, pipe);
2012 else {
2013 if (crtc->config.has_pch_encoder) {
2014 /* if driving the PCH, we need FDI enabled */
2015 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2016 assert_fdi_tx_pll_enabled(dev_priv,
2017 (enum pipe) cpu_transcoder);
2018 }
2019 /* FIXME: assert CPU port conditions for SNB+ */
2020 }
2021
2022 reg = PIPECONF(cpu_transcoder);
2023 val = I915_READ(reg);
2024 if (val & PIPECONF_ENABLE) {
2025 WARN_ON(!(pipe == PIPE_A &&
2026 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2027 return;
2028 }
2029
2030 I915_WRITE(reg, val | PIPECONF_ENABLE);
2031 POSTING_READ(reg);
2032 }
2033
2034 /**
2035 * intel_disable_pipe - disable a pipe, asserting requirements
2036 * @dev_priv: i915 private structure
2037 * @pipe: pipe to disable
2038 *
2039 * Disable @pipe, making sure that various hardware specific requirements
2040 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2041 *
2042 * @pipe should be %PIPE_A or %PIPE_B.
2043 *
2044 * Will wait until the pipe has shut down before returning.
2045 */
2046 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2047 enum pipe pipe)
2048 {
2049 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2050 pipe);
2051 int reg;
2052 u32 val;
2053
2054 /*
2055 * Make sure planes won't keep trying to pump pixels to us,
2056 * or we might hang the display.
2057 */
2058 assert_planes_disabled(dev_priv, pipe);
2059 assert_cursor_disabled(dev_priv, pipe);
2060 assert_sprites_disabled(dev_priv, pipe);
2061
2062 /* Don't disable pipe A or pipe A PLLs if needed */
2063 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2064 return;
2065
2066 reg = PIPECONF(cpu_transcoder);
2067 val = I915_READ(reg);
2068 if ((val & PIPECONF_ENABLE) == 0)
2069 return;
2070
2071 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2072 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2073 }
2074
2075 /*
2076 * Plane regs are double buffered, going from enabled->disabled needs a
2077 * trigger in order to latch. The display address reg provides this.
2078 */
2079 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2080 enum plane plane)
2081 {
2082 struct drm_device *dev = dev_priv->dev;
2083 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2084
2085 I915_WRITE(reg, I915_READ(reg));
2086 POSTING_READ(reg);
2087 }
2088
2089 /**
2090 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2091 * @plane: plane to be enabled
2092 * @crtc: crtc for the plane
2093 *
2094 * Enable @plane on @crtc, making sure that the pipe is running first.
2095 */
2096 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2097 struct drm_crtc *crtc)
2098 {
2099 struct drm_device *dev = plane->dev;
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2102
2103 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2104 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2105
2106 if (intel_crtc->primary_enabled)
2107 return;
2108
2109 intel_crtc->primary_enabled = true;
2110
2111 dev_priv->display.update_primary_plane(crtc, plane->fb,
2112 crtc->x, crtc->y);
2113
2114 /*
2115 * BDW signals flip done immediately if the plane
2116 * is disabled, even if the plane enable is already
2117 * armed to occur at the next vblank :(
2118 */
2119 if (IS_BROADWELL(dev))
2120 intel_wait_for_vblank(dev, intel_crtc->pipe);
2121 }
2122
2123 /**
2124 * intel_disable_primary_hw_plane - disable the primary hardware plane
2125 * @plane: plane to be disabled
2126 * @crtc: crtc for the plane
2127 *
2128 * Disable @plane on @crtc, making sure that the pipe is running first.
2129 */
2130 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2131 struct drm_crtc *crtc)
2132 {
2133 struct drm_device *dev = plane->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136
2137 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2138
2139 if (!intel_crtc->primary_enabled)
2140 return;
2141
2142 intel_crtc->primary_enabled = false;
2143
2144 dev_priv->display.update_primary_plane(crtc, plane->fb,
2145 crtc->x, crtc->y);
2146 }
2147
2148 static bool need_vtd_wa(struct drm_device *dev)
2149 {
2150 #ifdef CONFIG_INTEL_IOMMU
2151 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2152 return true;
2153 #endif
2154 return false;
2155 }
2156
2157 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2158 {
2159 int tile_height;
2160
2161 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2162 return ALIGN(height, tile_height);
2163 }
2164
2165 int
2166 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2167 struct drm_i915_gem_object *obj,
2168 struct intel_engine_cs *pipelined)
2169 {
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 u32 alignment;
2172 int ret;
2173
2174 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2175
2176 switch (obj->tiling_mode) {
2177 case I915_TILING_NONE:
2178 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2179 alignment = 128 * 1024;
2180 else if (INTEL_INFO(dev)->gen >= 4)
2181 alignment = 4 * 1024;
2182 else
2183 alignment = 64 * 1024;
2184 break;
2185 case I915_TILING_X:
2186 /* pin() will align the object as required by fence */
2187 alignment = 0;
2188 break;
2189 case I915_TILING_Y:
2190 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2191 return -EINVAL;
2192 default:
2193 BUG();
2194 }
2195
2196 /* Note that the w/a also requires 64 PTE of padding following the
2197 * bo. We currently fill all unused PTE with the shadow page and so
2198 * we should always have valid PTE following the scanout preventing
2199 * the VT-d warning.
2200 */
2201 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2202 alignment = 256 * 1024;
2203
2204 /*
2205 * Global gtt pte registers are special registers which actually forward
2206 * writes to a chunk of system memory. Which means that there is no risk
2207 * that the register values disappear as soon as we call
2208 * intel_runtime_pm_put(), so it is correct to wrap only the
2209 * pin/unpin/fence and not more.
2210 */
2211 intel_runtime_pm_get(dev_priv);
2212
2213 dev_priv->mm.interruptible = false;
2214 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2215 if (ret)
2216 goto err_interruptible;
2217
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always install
2221 * a fence as the cost is not that onerous.
2222 */
2223 ret = i915_gem_object_get_fence(obj);
2224 if (ret)
2225 goto err_unpin;
2226
2227 i915_gem_object_pin_fence(obj);
2228
2229 dev_priv->mm.interruptible = true;
2230 intel_runtime_pm_put(dev_priv);
2231 return 0;
2232
2233 err_unpin:
2234 i915_gem_object_unpin_from_display_plane(obj);
2235 err_interruptible:
2236 dev_priv->mm.interruptible = true;
2237 intel_runtime_pm_put(dev_priv);
2238 return ret;
2239 }
2240
2241 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2242 {
2243 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2244
2245 i915_gem_object_unpin_fence(obj);
2246 i915_gem_object_unpin_from_display_plane(obj);
2247 }
2248
2249 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2250 * is assumed to be a power-of-two. */
2251 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2252 unsigned int tiling_mode,
2253 unsigned int cpp,
2254 unsigned int pitch)
2255 {
2256 if (tiling_mode != I915_TILING_NONE) {
2257 unsigned int tile_rows, tiles;
2258
2259 tile_rows = *y / 8;
2260 *y %= 8;
2261
2262 tiles = *x / (512/cpp);
2263 *x %= 512/cpp;
2264
2265 return tile_rows * pitch * 8 + tiles * 4096;
2266 } else {
2267 unsigned int offset;
2268
2269 offset = *y * pitch + *x * cpp;
2270 *y = 0;
2271 *x = (offset & 4095) / cpp;
2272 return offset & -4096;
2273 }
2274 }
2275
2276 int intel_format_to_fourcc(int format)
2277 {
2278 switch (format) {
2279 case DISPPLANE_8BPP:
2280 return DRM_FORMAT_C8;
2281 case DISPPLANE_BGRX555:
2282 return DRM_FORMAT_XRGB1555;
2283 case DISPPLANE_BGRX565:
2284 return DRM_FORMAT_RGB565;
2285 default:
2286 case DISPPLANE_BGRX888:
2287 return DRM_FORMAT_XRGB8888;
2288 case DISPPLANE_RGBX888:
2289 return DRM_FORMAT_XBGR8888;
2290 case DISPPLANE_BGRX101010:
2291 return DRM_FORMAT_XRGB2101010;
2292 case DISPPLANE_RGBX101010:
2293 return DRM_FORMAT_XBGR2101010;
2294 }
2295 }
2296
2297 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2298 struct intel_plane_config *plane_config)
2299 {
2300 struct drm_device *dev = crtc->base.dev;
2301 struct drm_i915_gem_object *obj = NULL;
2302 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2303 u32 base = plane_config->base;
2304
2305 if (plane_config->size == 0)
2306 return false;
2307
2308 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2309 plane_config->size);
2310 if (!obj)
2311 return false;
2312
2313 if (plane_config->tiled) {
2314 obj->tiling_mode = I915_TILING_X;
2315 obj->stride = crtc->base.primary->fb->pitches[0];
2316 }
2317
2318 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2319 mode_cmd.width = crtc->base.primary->fb->width;
2320 mode_cmd.height = crtc->base.primary->fb->height;
2321 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2322
2323 mutex_lock(&dev->struct_mutex);
2324
2325 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2326 &mode_cmd, obj)) {
2327 DRM_DEBUG_KMS("intel fb init failed\n");
2328 goto out_unref_obj;
2329 }
2330
2331 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2332 mutex_unlock(&dev->struct_mutex);
2333
2334 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2335 return true;
2336
2337 out_unref_obj:
2338 drm_gem_object_unreference(&obj->base);
2339 mutex_unlock(&dev->struct_mutex);
2340 return false;
2341 }
2342
2343 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2344 struct intel_plane_config *plane_config)
2345 {
2346 struct drm_device *dev = intel_crtc->base.dev;
2347 struct drm_crtc *c;
2348 struct intel_crtc *i;
2349 struct drm_i915_gem_object *obj;
2350
2351 if (!intel_crtc->base.primary->fb)
2352 return;
2353
2354 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2355 return;
2356
2357 kfree(intel_crtc->base.primary->fb);
2358 intel_crtc->base.primary->fb = NULL;
2359
2360 /*
2361 * Failed to alloc the obj, check to see if we should share
2362 * an fb with another CRTC instead
2363 */
2364 for_each_crtc(dev, c) {
2365 i = to_intel_crtc(c);
2366
2367 if (c == &intel_crtc->base)
2368 continue;
2369
2370 if (!i->active)
2371 continue;
2372
2373 obj = intel_fb_obj(c->primary->fb);
2374 if (obj == NULL)
2375 continue;
2376
2377 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2378 drm_framebuffer_reference(c->primary->fb);
2379 intel_crtc->base.primary->fb = c->primary->fb;
2380 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2381 break;
2382 }
2383 }
2384 }
2385
2386 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2387 struct drm_framebuffer *fb,
2388 int x, int y)
2389 {
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2394 int plane = intel_crtc->plane;
2395 unsigned long linear_offset;
2396 u32 dspcntr;
2397 u32 reg = DSPCNTR(plane);
2398
2399 if (!intel_crtc->primary_enabled) {
2400 I915_WRITE(reg, 0);
2401 if (INTEL_INFO(dev)->gen >= 4)
2402 I915_WRITE(DSPSURF(plane), 0);
2403 else
2404 I915_WRITE(DSPADDR(plane), 0);
2405 POSTING_READ(reg);
2406 return;
2407 }
2408
2409 dspcntr = DISPPLANE_GAMMA_ENABLE;
2410
2411 dspcntr |= DISPLAY_PLANE_ENABLE;
2412
2413 if (INTEL_INFO(dev)->gen < 4) {
2414 if (intel_crtc->pipe == PIPE_B)
2415 dspcntr |= DISPPLANE_SEL_PIPE_B;
2416
2417 /* pipesrc and dspsize control the size that is scaled from,
2418 * which should always be the user's requested size.
2419 */
2420 I915_WRITE(DSPSIZE(plane),
2421 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2422 (intel_crtc->config.pipe_src_w - 1));
2423 I915_WRITE(DSPPOS(plane), 0);
2424 }
2425
2426 switch (fb->pixel_format) {
2427 case DRM_FORMAT_C8:
2428 dspcntr |= DISPPLANE_8BPP;
2429 break;
2430 case DRM_FORMAT_XRGB1555:
2431 case DRM_FORMAT_ARGB1555:
2432 dspcntr |= DISPPLANE_BGRX555;
2433 break;
2434 case DRM_FORMAT_RGB565:
2435 dspcntr |= DISPPLANE_BGRX565;
2436 break;
2437 case DRM_FORMAT_XRGB8888:
2438 case DRM_FORMAT_ARGB8888:
2439 dspcntr |= DISPPLANE_BGRX888;
2440 break;
2441 case DRM_FORMAT_XBGR8888:
2442 case DRM_FORMAT_ABGR8888:
2443 dspcntr |= DISPPLANE_RGBX888;
2444 break;
2445 case DRM_FORMAT_XRGB2101010:
2446 case DRM_FORMAT_ARGB2101010:
2447 dspcntr |= DISPPLANE_BGRX101010;
2448 break;
2449 case DRM_FORMAT_XBGR2101010:
2450 case DRM_FORMAT_ABGR2101010:
2451 dspcntr |= DISPPLANE_RGBX101010;
2452 break;
2453 default:
2454 BUG();
2455 }
2456
2457 if (INTEL_INFO(dev)->gen >= 4 &&
2458 obj->tiling_mode != I915_TILING_NONE)
2459 dspcntr |= DISPPLANE_TILED;
2460
2461 if (IS_G4X(dev))
2462 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2463
2464 I915_WRITE(reg, dspcntr);
2465
2466 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2467
2468 if (INTEL_INFO(dev)->gen >= 4) {
2469 intel_crtc->dspaddr_offset =
2470 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2471 fb->bits_per_pixel / 8,
2472 fb->pitches[0]);
2473 linear_offset -= intel_crtc->dspaddr_offset;
2474 } else {
2475 intel_crtc->dspaddr_offset = linear_offset;
2476 }
2477
2478 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2479 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2480 fb->pitches[0]);
2481 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2482 if (INTEL_INFO(dev)->gen >= 4) {
2483 I915_WRITE(DSPSURF(plane),
2484 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2485 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2486 I915_WRITE(DSPLINOFF(plane), linear_offset);
2487 } else
2488 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2489 POSTING_READ(reg);
2490 }
2491
2492 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2493 struct drm_framebuffer *fb,
2494 int x, int y)
2495 {
2496 struct drm_device *dev = crtc->dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2499 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2500 int plane = intel_crtc->plane;
2501 unsigned long linear_offset;
2502 u32 dspcntr;
2503 u32 reg = DSPCNTR(plane);
2504
2505 if (!intel_crtc->primary_enabled) {
2506 I915_WRITE(reg, 0);
2507 I915_WRITE(DSPSURF(plane), 0);
2508 POSTING_READ(reg);
2509 return;
2510 }
2511
2512 dspcntr = DISPPLANE_GAMMA_ENABLE;
2513
2514 dspcntr |= DISPLAY_PLANE_ENABLE;
2515
2516 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2517 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2518
2519 switch (fb->pixel_format) {
2520 case DRM_FORMAT_C8:
2521 dspcntr |= DISPPLANE_8BPP;
2522 break;
2523 case DRM_FORMAT_RGB565:
2524 dspcntr |= DISPPLANE_BGRX565;
2525 break;
2526 case DRM_FORMAT_XRGB8888:
2527 case DRM_FORMAT_ARGB8888:
2528 dspcntr |= DISPPLANE_BGRX888;
2529 break;
2530 case DRM_FORMAT_XBGR8888:
2531 case DRM_FORMAT_ABGR8888:
2532 dspcntr |= DISPPLANE_RGBX888;
2533 break;
2534 case DRM_FORMAT_XRGB2101010:
2535 case DRM_FORMAT_ARGB2101010:
2536 dspcntr |= DISPPLANE_BGRX101010;
2537 break;
2538 case DRM_FORMAT_XBGR2101010:
2539 case DRM_FORMAT_ABGR2101010:
2540 dspcntr |= DISPPLANE_RGBX101010;
2541 break;
2542 default:
2543 BUG();
2544 }
2545
2546 if (obj->tiling_mode != I915_TILING_NONE)
2547 dspcntr |= DISPPLANE_TILED;
2548
2549 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2550 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2551
2552 I915_WRITE(reg, dspcntr);
2553
2554 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2555 intel_crtc->dspaddr_offset =
2556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 fb->bits_per_pixel / 8,
2558 fb->pitches[0]);
2559 linear_offset -= intel_crtc->dspaddr_offset;
2560
2561 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2562 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2563 fb->pitches[0]);
2564 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2565 I915_WRITE(DSPSURF(plane),
2566 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2567 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2568 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2569 } else {
2570 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2571 I915_WRITE(DSPLINOFF(plane), linear_offset);
2572 }
2573 POSTING_READ(reg);
2574 }
2575
2576 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2577 static int
2578 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2579 int x, int y, enum mode_set_atomic state)
2580 {
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583
2584 if (dev_priv->display.disable_fbc)
2585 dev_priv->display.disable_fbc(dev);
2586 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2587
2588 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2589
2590 return 0;
2591 }
2592
2593 void intel_display_handle_reset(struct drm_device *dev)
2594 {
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct drm_crtc *crtc;
2597
2598 /*
2599 * Flips in the rings have been nuked by the reset,
2600 * so complete all pending flips so that user space
2601 * will get its events and not get stuck.
2602 *
2603 * Also update the base address of all primary
2604 * planes to the the last fb to make sure we're
2605 * showing the correct fb after a reset.
2606 *
2607 * Need to make two loops over the crtcs so that we
2608 * don't try to grab a crtc mutex before the
2609 * pending_flip_queue really got woken up.
2610 */
2611
2612 for_each_crtc(dev, crtc) {
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614 enum plane plane = intel_crtc->plane;
2615
2616 intel_prepare_page_flip(dev, plane);
2617 intel_finish_page_flip_plane(dev, plane);
2618 }
2619
2620 for_each_crtc(dev, crtc) {
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622
2623 drm_modeset_lock(&crtc->mutex, NULL);
2624 /*
2625 * FIXME: Once we have proper support for primary planes (and
2626 * disabling them without disabling the entire crtc) allow again
2627 * a NULL crtc->primary->fb.
2628 */
2629 if (intel_crtc->active && crtc->primary->fb)
2630 dev_priv->display.update_primary_plane(crtc,
2631 crtc->primary->fb,
2632 crtc->x,
2633 crtc->y);
2634 drm_modeset_unlock(&crtc->mutex);
2635 }
2636 }
2637
2638 static int
2639 intel_finish_fb(struct drm_framebuffer *old_fb)
2640 {
2641 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2642 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2643 bool was_interruptible = dev_priv->mm.interruptible;
2644 int ret;
2645
2646 /* Big Hammer, we also need to ensure that any pending
2647 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2648 * current scanout is retired before unpinning the old
2649 * framebuffer.
2650 *
2651 * This should only fail upon a hung GPU, in which case we
2652 * can safely continue.
2653 */
2654 dev_priv->mm.interruptible = false;
2655 ret = i915_gem_object_finish_gpu(obj);
2656 dev_priv->mm.interruptible = was_interruptible;
2657
2658 return ret;
2659 }
2660
2661 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2662 {
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666 unsigned long flags;
2667 bool pending;
2668
2669 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2670 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2671 return false;
2672
2673 spin_lock_irqsave(&dev->event_lock, flags);
2674 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2675 spin_unlock_irqrestore(&dev->event_lock, flags);
2676
2677 return pending;
2678 }
2679
2680 static int
2681 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2682 struct drm_framebuffer *fb)
2683 {
2684 struct drm_device *dev = crtc->dev;
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687 enum pipe pipe = intel_crtc->pipe;
2688 struct drm_framebuffer *old_fb = crtc->primary->fb;
2689 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2690 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2691 int ret;
2692
2693 if (intel_crtc_has_pending_flip(crtc)) {
2694 DRM_ERROR("pipe is still busy with an old pageflip\n");
2695 return -EBUSY;
2696 }
2697
2698 /* no fb bound */
2699 if (!fb) {
2700 DRM_ERROR("No FB bound\n");
2701 return 0;
2702 }
2703
2704 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2705 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2706 plane_name(intel_crtc->plane),
2707 INTEL_INFO(dev)->num_pipes);
2708 return -EINVAL;
2709 }
2710
2711 mutex_lock(&dev->struct_mutex);
2712 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2713 if (ret == 0)
2714 i915_gem_track_fb(old_obj, obj,
2715 INTEL_FRONTBUFFER_PRIMARY(pipe));
2716 mutex_unlock(&dev->struct_mutex);
2717 if (ret != 0) {
2718 DRM_ERROR("pin & fence failed\n");
2719 return ret;
2720 }
2721
2722 /*
2723 * Update pipe size and adjust fitter if needed: the reason for this is
2724 * that in compute_mode_changes we check the native mode (not the pfit
2725 * mode) to see if we can flip rather than do a full mode set. In the
2726 * fastboot case, we'll flip, but if we don't update the pipesrc and
2727 * pfit state, we'll end up with a big fb scanned out into the wrong
2728 * sized surface.
2729 *
2730 * To fix this properly, we need to hoist the checks up into
2731 * compute_mode_changes (or above), check the actual pfit state and
2732 * whether the platform allows pfit disable with pipe active, and only
2733 * then update the pipesrc and pfit state, even on the flip path.
2734 */
2735 if (i915.fastboot) {
2736 const struct drm_display_mode *adjusted_mode =
2737 &intel_crtc->config.adjusted_mode;
2738
2739 I915_WRITE(PIPESRC(intel_crtc->pipe),
2740 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2741 (adjusted_mode->crtc_vdisplay - 1));
2742 if (!intel_crtc->config.pch_pfit.enabled &&
2743 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2744 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2745 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2746 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2747 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2748 }
2749 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2750 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2751 }
2752
2753 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2754
2755 if (intel_crtc->active)
2756 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2757
2758 crtc->primary->fb = fb;
2759 crtc->x = x;
2760 crtc->y = y;
2761
2762 if (old_fb) {
2763 if (intel_crtc->active && old_fb != fb)
2764 intel_wait_for_vblank(dev, intel_crtc->pipe);
2765 mutex_lock(&dev->struct_mutex);
2766 intel_unpin_fb_obj(old_obj);
2767 mutex_unlock(&dev->struct_mutex);
2768 }
2769
2770 mutex_lock(&dev->struct_mutex);
2771 intel_update_fbc(dev);
2772 mutex_unlock(&dev->struct_mutex);
2773
2774 return 0;
2775 }
2776
2777 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2778 {
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 int pipe = intel_crtc->pipe;
2783 u32 reg, temp;
2784
2785 /* enable normal train */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 if (IS_IVYBRIDGE(dev)) {
2789 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2790 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2791 } else {
2792 temp &= ~FDI_LINK_TRAIN_NONE;
2793 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2794 }
2795 I915_WRITE(reg, temp);
2796
2797 reg = FDI_RX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 if (HAS_PCH_CPT(dev)) {
2800 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2801 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2802 } else {
2803 temp &= ~FDI_LINK_TRAIN_NONE;
2804 temp |= FDI_LINK_TRAIN_NONE;
2805 }
2806 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2807
2808 /* wait one idle pattern time */
2809 POSTING_READ(reg);
2810 udelay(1000);
2811
2812 /* IVB wants error correction enabled */
2813 if (IS_IVYBRIDGE(dev))
2814 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2815 FDI_FE_ERRC_ENABLE);
2816 }
2817
2818 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2819 {
2820 return crtc->base.enabled && crtc->active &&
2821 crtc->config.has_pch_encoder;
2822 }
2823
2824 static void ivb_modeset_global_resources(struct drm_device *dev)
2825 {
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_crtc *pipe_B_crtc =
2828 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2829 struct intel_crtc *pipe_C_crtc =
2830 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2831 uint32_t temp;
2832
2833 /*
2834 * When everything is off disable fdi C so that we could enable fdi B
2835 * with all lanes. Note that we don't care about enabled pipes without
2836 * an enabled pch encoder.
2837 */
2838 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2839 !pipe_has_enabled_pch(pipe_C_crtc)) {
2840 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2841 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2842
2843 temp = I915_READ(SOUTH_CHICKEN1);
2844 temp &= ~FDI_BC_BIFURCATION_SELECT;
2845 DRM_DEBUG_KMS("disabling fdi C rx\n");
2846 I915_WRITE(SOUTH_CHICKEN1, temp);
2847 }
2848 }
2849
2850 /* The FDI link training functions for ILK/Ibexpeak. */
2851 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2852 {
2853 struct drm_device *dev = crtc->dev;
2854 struct drm_i915_private *dev_priv = dev->dev_private;
2855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2856 int pipe = intel_crtc->pipe;
2857 u32 reg, temp, tries;
2858
2859 /* FDI needs bits from pipe first */
2860 assert_pipe_enabled(dev_priv, pipe);
2861
2862 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2863 for train result */
2864 reg = FDI_RX_IMR(pipe);
2865 temp = I915_READ(reg);
2866 temp &= ~FDI_RX_SYMBOL_LOCK;
2867 temp &= ~FDI_RX_BIT_LOCK;
2868 I915_WRITE(reg, temp);
2869 I915_READ(reg);
2870 udelay(150);
2871
2872 /* enable CPU FDI TX and PCH FDI RX */
2873 reg = FDI_TX_CTL(pipe);
2874 temp = I915_READ(reg);
2875 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2876 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 temp &= ~FDI_LINK_TRAIN_NONE;
2884 temp |= FDI_LINK_TRAIN_PATTERN_1;
2885 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2886
2887 POSTING_READ(reg);
2888 udelay(150);
2889
2890 /* Ironlake workaround, enable clock pointer after FDI enable*/
2891 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2892 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2893 FDI_RX_PHASE_SYNC_POINTER_EN);
2894
2895 reg = FDI_RX_IIR(pipe);
2896 for (tries = 0; tries < 5; tries++) {
2897 temp = I915_READ(reg);
2898 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2899
2900 if ((temp & FDI_RX_BIT_LOCK)) {
2901 DRM_DEBUG_KMS("FDI train 1 done.\n");
2902 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2903 break;
2904 }
2905 }
2906 if (tries == 5)
2907 DRM_ERROR("FDI train 1 fail!\n");
2908
2909 /* Train 2 */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_LINK_TRAIN_NONE;
2913 temp |= FDI_LINK_TRAIN_PATTERN_2;
2914 I915_WRITE(reg, temp);
2915
2916 reg = FDI_RX_CTL(pipe);
2917 temp = I915_READ(reg);
2918 temp &= ~FDI_LINK_TRAIN_NONE;
2919 temp |= FDI_LINK_TRAIN_PATTERN_2;
2920 I915_WRITE(reg, temp);
2921
2922 POSTING_READ(reg);
2923 udelay(150);
2924
2925 reg = FDI_RX_IIR(pipe);
2926 for (tries = 0; tries < 5; tries++) {
2927 temp = I915_READ(reg);
2928 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2929
2930 if (temp & FDI_RX_SYMBOL_LOCK) {
2931 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2932 DRM_DEBUG_KMS("FDI train 2 done.\n");
2933 break;
2934 }
2935 }
2936 if (tries == 5)
2937 DRM_ERROR("FDI train 2 fail!\n");
2938
2939 DRM_DEBUG_KMS("FDI train done\n");
2940
2941 }
2942
2943 static const int snb_b_fdi_train_param[] = {
2944 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2945 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2946 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2947 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2948 };
2949
2950 /* The FDI link training functions for SNB/Cougarpoint. */
2951 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2952 {
2953 struct drm_device *dev = crtc->dev;
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2956 int pipe = intel_crtc->pipe;
2957 u32 reg, temp, i, retry;
2958
2959 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2960 for train result */
2961 reg = FDI_RX_IMR(pipe);
2962 temp = I915_READ(reg);
2963 temp &= ~FDI_RX_SYMBOL_LOCK;
2964 temp &= ~FDI_RX_BIT_LOCK;
2965 I915_WRITE(reg, temp);
2966
2967 POSTING_READ(reg);
2968 udelay(150);
2969
2970 /* enable CPU FDI TX and PCH FDI RX */
2971 reg = FDI_TX_CTL(pipe);
2972 temp = I915_READ(reg);
2973 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2974 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_PATTERN_1;
2977 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2978 /* SNB-B */
2979 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2980 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2981
2982 I915_WRITE(FDI_RX_MISC(pipe),
2983 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2984
2985 reg = FDI_RX_CTL(pipe);
2986 temp = I915_READ(reg);
2987 if (HAS_PCH_CPT(dev)) {
2988 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2989 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2990 } else {
2991 temp &= ~FDI_LINK_TRAIN_NONE;
2992 temp |= FDI_LINK_TRAIN_PATTERN_1;
2993 }
2994 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2995
2996 POSTING_READ(reg);
2997 udelay(150);
2998
2999 for (i = 0; i < 4; i++) {
3000 reg = FDI_TX_CTL(pipe);
3001 temp = I915_READ(reg);
3002 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3003 temp |= snb_b_fdi_train_param[i];
3004 I915_WRITE(reg, temp);
3005
3006 POSTING_READ(reg);
3007 udelay(500);
3008
3009 for (retry = 0; retry < 5; retry++) {
3010 reg = FDI_RX_IIR(pipe);
3011 temp = I915_READ(reg);
3012 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3013 if (temp & FDI_RX_BIT_LOCK) {
3014 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3015 DRM_DEBUG_KMS("FDI train 1 done.\n");
3016 break;
3017 }
3018 udelay(50);
3019 }
3020 if (retry < 5)
3021 break;
3022 }
3023 if (i == 4)
3024 DRM_ERROR("FDI train 1 fail!\n");
3025
3026 /* Train 2 */
3027 reg = FDI_TX_CTL(pipe);
3028 temp = I915_READ(reg);
3029 temp &= ~FDI_LINK_TRAIN_NONE;
3030 temp |= FDI_LINK_TRAIN_PATTERN_2;
3031 if (IS_GEN6(dev)) {
3032 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3033 /* SNB-B */
3034 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3035 }
3036 I915_WRITE(reg, temp);
3037
3038 reg = FDI_RX_CTL(pipe);
3039 temp = I915_READ(reg);
3040 if (HAS_PCH_CPT(dev)) {
3041 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3042 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3043 } else {
3044 temp &= ~FDI_LINK_TRAIN_NONE;
3045 temp |= FDI_LINK_TRAIN_PATTERN_2;
3046 }
3047 I915_WRITE(reg, temp);
3048
3049 POSTING_READ(reg);
3050 udelay(150);
3051
3052 for (i = 0; i < 4; i++) {
3053 reg = FDI_TX_CTL(pipe);
3054 temp = I915_READ(reg);
3055 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3056 temp |= snb_b_fdi_train_param[i];
3057 I915_WRITE(reg, temp);
3058
3059 POSTING_READ(reg);
3060 udelay(500);
3061
3062 for (retry = 0; retry < 5; retry++) {
3063 reg = FDI_RX_IIR(pipe);
3064 temp = I915_READ(reg);
3065 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3066 if (temp & FDI_RX_SYMBOL_LOCK) {
3067 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3068 DRM_DEBUG_KMS("FDI train 2 done.\n");
3069 break;
3070 }
3071 udelay(50);
3072 }
3073 if (retry < 5)
3074 break;
3075 }
3076 if (i == 4)
3077 DRM_ERROR("FDI train 2 fail!\n");
3078
3079 DRM_DEBUG_KMS("FDI train done.\n");
3080 }
3081
3082 /* Manual link training for Ivy Bridge A0 parts */
3083 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3084 {
3085 struct drm_device *dev = crtc->dev;
3086 struct drm_i915_private *dev_priv = dev->dev_private;
3087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3088 int pipe = intel_crtc->pipe;
3089 u32 reg, temp, i, j;
3090
3091 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3092 for train result */
3093 reg = FDI_RX_IMR(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_RX_SYMBOL_LOCK;
3096 temp &= ~FDI_RX_BIT_LOCK;
3097 I915_WRITE(reg, temp);
3098
3099 POSTING_READ(reg);
3100 udelay(150);
3101
3102 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3103 I915_READ(FDI_RX_IIR(pipe)));
3104
3105 /* Try each vswing and preemphasis setting twice before moving on */
3106 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3107 /* disable first in case we need to retry */
3108 reg = FDI_TX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3111 temp &= ~FDI_TX_ENABLE;
3112 I915_WRITE(reg, temp);
3113
3114 reg = FDI_RX_CTL(pipe);
3115 temp = I915_READ(reg);
3116 temp &= ~FDI_LINK_TRAIN_AUTO;
3117 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3118 temp &= ~FDI_RX_ENABLE;
3119 I915_WRITE(reg, temp);
3120
3121 /* enable CPU FDI TX and PCH FDI RX */
3122 reg = FDI_TX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3125 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3126 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3127 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3128 temp |= snb_b_fdi_train_param[j/2];
3129 temp |= FDI_COMPOSITE_SYNC;
3130 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3131
3132 I915_WRITE(FDI_RX_MISC(pipe),
3133 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3134
3135 reg = FDI_RX_CTL(pipe);
3136 temp = I915_READ(reg);
3137 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3138 temp |= FDI_COMPOSITE_SYNC;
3139 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3140
3141 POSTING_READ(reg);
3142 udelay(1); /* should be 0.5us */
3143
3144 for (i = 0; i < 4; i++) {
3145 reg = FDI_RX_IIR(pipe);
3146 temp = I915_READ(reg);
3147 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3148
3149 if (temp & FDI_RX_BIT_LOCK ||
3150 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3151 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3152 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3153 i);
3154 break;
3155 }
3156 udelay(1); /* should be 0.5us */
3157 }
3158 if (i == 4) {
3159 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3160 continue;
3161 }
3162
3163 /* Train 2 */
3164 reg = FDI_TX_CTL(pipe);
3165 temp = I915_READ(reg);
3166 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3167 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3168 I915_WRITE(reg, temp);
3169
3170 reg = FDI_RX_CTL(pipe);
3171 temp = I915_READ(reg);
3172 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3173 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3174 I915_WRITE(reg, temp);
3175
3176 POSTING_READ(reg);
3177 udelay(2); /* should be 1.5us */
3178
3179 for (i = 0; i < 4; i++) {
3180 reg = FDI_RX_IIR(pipe);
3181 temp = I915_READ(reg);
3182 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3183
3184 if (temp & FDI_RX_SYMBOL_LOCK ||
3185 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3186 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3187 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3188 i);
3189 goto train_done;
3190 }
3191 udelay(2); /* should be 1.5us */
3192 }
3193 if (i == 4)
3194 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3195 }
3196
3197 train_done:
3198 DRM_DEBUG_KMS("FDI train done.\n");
3199 }
3200
3201 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3202 {
3203 struct drm_device *dev = intel_crtc->base.dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 int pipe = intel_crtc->pipe;
3206 u32 reg, temp;
3207
3208
3209 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3210 reg = FDI_RX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3213 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3214 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3215 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3216
3217 POSTING_READ(reg);
3218 udelay(200);
3219
3220 /* Switch from Rawclk to PCDclk */
3221 temp = I915_READ(reg);
3222 I915_WRITE(reg, temp | FDI_PCDCLK);
3223
3224 POSTING_READ(reg);
3225 udelay(200);
3226
3227 /* Enable CPU FDI TX PLL, always on for Ironlake */
3228 reg = FDI_TX_CTL(pipe);
3229 temp = I915_READ(reg);
3230 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3231 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3232
3233 POSTING_READ(reg);
3234 udelay(100);
3235 }
3236 }
3237
3238 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3239 {
3240 struct drm_device *dev = intel_crtc->base.dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 int pipe = intel_crtc->pipe;
3243 u32 reg, temp;
3244
3245 /* Switch from PCDclk to Rawclk */
3246 reg = FDI_RX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3249
3250 /* Disable CPU FDI TX PLL */
3251 reg = FDI_TX_CTL(pipe);
3252 temp = I915_READ(reg);
3253 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3254
3255 POSTING_READ(reg);
3256 udelay(100);
3257
3258 reg = FDI_RX_CTL(pipe);
3259 temp = I915_READ(reg);
3260 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3261
3262 /* Wait for the clocks to turn off. */
3263 POSTING_READ(reg);
3264 udelay(100);
3265 }
3266
3267 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3268 {
3269 struct drm_device *dev = crtc->dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3272 int pipe = intel_crtc->pipe;
3273 u32 reg, temp;
3274
3275 /* disable CPU FDI tx and PCH FDI rx */
3276 reg = FDI_TX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3279 POSTING_READ(reg);
3280
3281 reg = FDI_RX_CTL(pipe);
3282 temp = I915_READ(reg);
3283 temp &= ~(0x7 << 16);
3284 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3285 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3286
3287 POSTING_READ(reg);
3288 udelay(100);
3289
3290 /* Ironlake workaround, disable clock pointer after downing FDI */
3291 if (HAS_PCH_IBX(dev))
3292 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3293
3294 /* still set train pattern 1 */
3295 reg = FDI_TX_CTL(pipe);
3296 temp = I915_READ(reg);
3297 temp &= ~FDI_LINK_TRAIN_NONE;
3298 temp |= FDI_LINK_TRAIN_PATTERN_1;
3299 I915_WRITE(reg, temp);
3300
3301 reg = FDI_RX_CTL(pipe);
3302 temp = I915_READ(reg);
3303 if (HAS_PCH_CPT(dev)) {
3304 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3305 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3306 } else {
3307 temp &= ~FDI_LINK_TRAIN_NONE;
3308 temp |= FDI_LINK_TRAIN_PATTERN_1;
3309 }
3310 /* BPC in FDI rx is consistent with that in PIPECONF */
3311 temp &= ~(0x07 << 16);
3312 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3313 I915_WRITE(reg, temp);
3314
3315 POSTING_READ(reg);
3316 udelay(100);
3317 }
3318
3319 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3320 {
3321 struct intel_crtc *crtc;
3322
3323 /* Note that we don't need to be called with mode_config.lock here
3324 * as our list of CRTC objects is static for the lifetime of the
3325 * device and so cannot disappear as we iterate. Similarly, we can
3326 * happily treat the predicates as racy, atomic checks as userspace
3327 * cannot claim and pin a new fb without at least acquring the
3328 * struct_mutex and so serialising with us.
3329 */
3330 for_each_intel_crtc(dev, crtc) {
3331 if (atomic_read(&crtc->unpin_work_count) == 0)
3332 continue;
3333
3334 if (crtc->unpin_work)
3335 intel_wait_for_vblank(dev, crtc->pipe);
3336
3337 return true;
3338 }
3339
3340 return false;
3341 }
3342
3343 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347
3348 if (crtc->primary->fb == NULL)
3349 return;
3350
3351 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3352
3353 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3354 !intel_crtc_has_pending_flip(crtc),
3355 60*HZ) == 0);
3356
3357 mutex_lock(&dev->struct_mutex);
3358 intel_finish_fb(crtc->primary->fb);
3359 mutex_unlock(&dev->struct_mutex);
3360 }
3361
3362 /* Program iCLKIP clock to the desired frequency */
3363 static void lpt_program_iclkip(struct drm_crtc *crtc)
3364 {
3365 struct drm_device *dev = crtc->dev;
3366 struct drm_i915_private *dev_priv = dev->dev_private;
3367 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3368 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3369 u32 temp;
3370
3371 mutex_lock(&dev_priv->dpio_lock);
3372
3373 /* It is necessary to ungate the pixclk gate prior to programming
3374 * the divisors, and gate it back when it is done.
3375 */
3376 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3377
3378 /* Disable SSCCTL */
3379 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3380 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3381 SBI_SSCCTL_DISABLE,
3382 SBI_ICLK);
3383
3384 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3385 if (clock == 20000) {
3386 auxdiv = 1;
3387 divsel = 0x41;
3388 phaseinc = 0x20;
3389 } else {
3390 /* The iCLK virtual clock root frequency is in MHz,
3391 * but the adjusted_mode->crtc_clock in in KHz. To get the
3392 * divisors, it is necessary to divide one by another, so we
3393 * convert the virtual clock precision to KHz here for higher
3394 * precision.
3395 */
3396 u32 iclk_virtual_root_freq = 172800 * 1000;
3397 u32 iclk_pi_range = 64;
3398 u32 desired_divisor, msb_divisor_value, pi_value;
3399
3400 desired_divisor = (iclk_virtual_root_freq / clock);
3401 msb_divisor_value = desired_divisor / iclk_pi_range;
3402 pi_value = desired_divisor % iclk_pi_range;
3403
3404 auxdiv = 0;
3405 divsel = msb_divisor_value - 2;
3406 phaseinc = pi_value;
3407 }
3408
3409 /* This should not happen with any sane values */
3410 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3411 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3412 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3413 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3414
3415 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3416 clock,
3417 auxdiv,
3418 divsel,
3419 phasedir,
3420 phaseinc);
3421
3422 /* Program SSCDIVINTPHASE6 */
3423 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3424 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3425 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3426 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3427 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3428 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3429 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3430 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3431
3432 /* Program SSCAUXDIV */
3433 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3434 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3435 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3436 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3437
3438 /* Enable modulator and associated divider */
3439 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3440 temp &= ~SBI_SSCCTL_DISABLE;
3441 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3442
3443 /* Wait for initialization time */
3444 udelay(24);
3445
3446 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3447
3448 mutex_unlock(&dev_priv->dpio_lock);
3449 }
3450
3451 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3452 enum pipe pch_transcoder)
3453 {
3454 struct drm_device *dev = crtc->base.dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3457
3458 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3459 I915_READ(HTOTAL(cpu_transcoder)));
3460 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3461 I915_READ(HBLANK(cpu_transcoder)));
3462 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3463 I915_READ(HSYNC(cpu_transcoder)));
3464
3465 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3466 I915_READ(VTOTAL(cpu_transcoder)));
3467 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3468 I915_READ(VBLANK(cpu_transcoder)));
3469 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3470 I915_READ(VSYNC(cpu_transcoder)));
3471 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3472 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3473 }
3474
3475 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3476 {
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 uint32_t temp;
3479
3480 temp = I915_READ(SOUTH_CHICKEN1);
3481 if (temp & FDI_BC_BIFURCATION_SELECT)
3482 return;
3483
3484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3486
3487 temp |= FDI_BC_BIFURCATION_SELECT;
3488 DRM_DEBUG_KMS("enabling fdi C rx\n");
3489 I915_WRITE(SOUTH_CHICKEN1, temp);
3490 POSTING_READ(SOUTH_CHICKEN1);
3491 }
3492
3493 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3494 {
3495 struct drm_device *dev = intel_crtc->base.dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497
3498 switch (intel_crtc->pipe) {
3499 case PIPE_A:
3500 break;
3501 case PIPE_B:
3502 if (intel_crtc->config.fdi_lanes > 2)
3503 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3504 else
3505 cpt_enable_fdi_bc_bifurcation(dev);
3506
3507 break;
3508 case PIPE_C:
3509 cpt_enable_fdi_bc_bifurcation(dev);
3510
3511 break;
3512 default:
3513 BUG();
3514 }
3515 }
3516
3517 /*
3518 * Enable PCH resources required for PCH ports:
3519 * - PCH PLLs
3520 * - FDI training & RX/TX
3521 * - update transcoder timings
3522 * - DP transcoding bits
3523 * - transcoder
3524 */
3525 static void ironlake_pch_enable(struct drm_crtc *crtc)
3526 {
3527 struct drm_device *dev = crtc->dev;
3528 struct drm_i915_private *dev_priv = dev->dev_private;
3529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3530 int pipe = intel_crtc->pipe;
3531 u32 reg, temp;
3532
3533 assert_pch_transcoder_disabled(dev_priv, pipe);
3534
3535 if (IS_IVYBRIDGE(dev))
3536 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3537
3538 /* Write the TU size bits before fdi link training, so that error
3539 * detection works. */
3540 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3541 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3542
3543 /* For PCH output, training FDI link */
3544 dev_priv->display.fdi_link_train(crtc);
3545
3546 /* We need to program the right clock selection before writing the pixel
3547 * mutliplier into the DPLL. */
3548 if (HAS_PCH_CPT(dev)) {
3549 u32 sel;
3550
3551 temp = I915_READ(PCH_DPLL_SEL);
3552 temp |= TRANS_DPLL_ENABLE(pipe);
3553 sel = TRANS_DPLLB_SEL(pipe);
3554 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3555 temp |= sel;
3556 else
3557 temp &= ~sel;
3558 I915_WRITE(PCH_DPLL_SEL, temp);
3559 }
3560
3561 /* XXX: pch pll's can be enabled any time before we enable the PCH
3562 * transcoder, and we actually should do this to not upset any PCH
3563 * transcoder that already use the clock when we share it.
3564 *
3565 * Note that enable_shared_dpll tries to do the right thing, but
3566 * get_shared_dpll unconditionally resets the pll - we need that to have
3567 * the right LVDS enable sequence. */
3568 intel_enable_shared_dpll(intel_crtc);
3569
3570 /* set transcoder timing, panel must allow it */
3571 assert_panel_unlocked(dev_priv, pipe);
3572 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3573
3574 intel_fdi_normal_train(crtc);
3575
3576 /* For PCH DP, enable TRANS_DP_CTL */
3577 if (HAS_PCH_CPT(dev) &&
3578 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3579 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3580 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3581 reg = TRANS_DP_CTL(pipe);
3582 temp = I915_READ(reg);
3583 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3584 TRANS_DP_SYNC_MASK |
3585 TRANS_DP_BPC_MASK);
3586 temp |= (TRANS_DP_OUTPUT_ENABLE |
3587 TRANS_DP_ENH_FRAMING);
3588 temp |= bpc << 9; /* same format but at 11:9 */
3589
3590 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3591 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3592 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3593 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3594
3595 switch (intel_trans_dp_port_sel(crtc)) {
3596 case PCH_DP_B:
3597 temp |= TRANS_DP_PORT_SEL_B;
3598 break;
3599 case PCH_DP_C:
3600 temp |= TRANS_DP_PORT_SEL_C;
3601 break;
3602 case PCH_DP_D:
3603 temp |= TRANS_DP_PORT_SEL_D;
3604 break;
3605 default:
3606 BUG();
3607 }
3608
3609 I915_WRITE(reg, temp);
3610 }
3611
3612 ironlake_enable_pch_transcoder(dev_priv, pipe);
3613 }
3614
3615 static void lpt_pch_enable(struct drm_crtc *crtc)
3616 {
3617 struct drm_device *dev = crtc->dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3621
3622 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3623
3624 lpt_program_iclkip(crtc);
3625
3626 /* Set transcoder timing. */
3627 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3628
3629 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3630 }
3631
3632 void intel_put_shared_dpll(struct intel_crtc *crtc)
3633 {
3634 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3635
3636 if (pll == NULL)
3637 return;
3638
3639 if (pll->refcount == 0) {
3640 WARN(1, "bad %s refcount\n", pll->name);
3641 return;
3642 }
3643
3644 if (--pll->refcount == 0) {
3645 WARN_ON(pll->on);
3646 WARN_ON(pll->active);
3647 }
3648
3649 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3650 }
3651
3652 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3653 {
3654 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3655 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3656 enum intel_dpll_id i;
3657
3658 if (pll) {
3659 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3660 crtc->base.base.id, pll->name);
3661 intel_put_shared_dpll(crtc);
3662 }
3663
3664 if (HAS_PCH_IBX(dev_priv->dev)) {
3665 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3666 i = (enum intel_dpll_id) crtc->pipe;
3667 pll = &dev_priv->shared_dplls[i];
3668
3669 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3670 crtc->base.base.id, pll->name);
3671
3672 WARN_ON(pll->refcount);
3673
3674 goto found;
3675 }
3676
3677 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3678 pll = &dev_priv->shared_dplls[i];
3679
3680 /* Only want to check enabled timings first */
3681 if (pll->refcount == 0)
3682 continue;
3683
3684 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3685 sizeof(pll->hw_state)) == 0) {
3686 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3687 crtc->base.base.id,
3688 pll->name, pll->refcount, pll->active);
3689
3690 goto found;
3691 }
3692 }
3693
3694 /* Ok no matching timings, maybe there's a free one? */
3695 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3696 pll = &dev_priv->shared_dplls[i];
3697 if (pll->refcount == 0) {
3698 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3699 crtc->base.base.id, pll->name);
3700 goto found;
3701 }
3702 }
3703
3704 return NULL;
3705
3706 found:
3707 if (pll->refcount == 0)
3708 pll->hw_state = crtc->config.dpll_hw_state;
3709
3710 crtc->config.shared_dpll = i;
3711 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3712 pipe_name(crtc->pipe));
3713
3714 pll->refcount++;
3715
3716 return pll;
3717 }
3718
3719 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3720 {
3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 int dslreg = PIPEDSL(pipe);
3723 u32 temp;
3724
3725 temp = I915_READ(dslreg);
3726 udelay(500);
3727 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3728 if (wait_for(I915_READ(dslreg) != temp, 5))
3729 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3730 }
3731 }
3732
3733 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3734 {
3735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int pipe = crtc->pipe;
3738
3739 if (crtc->config.pch_pfit.enabled) {
3740 /* Force use of hard-coded filter coefficients
3741 * as some pre-programmed values are broken,
3742 * e.g. x201.
3743 */
3744 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3745 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3746 PF_PIPE_SEL_IVB(pipe));
3747 else
3748 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3749 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3750 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3751 }
3752 }
3753
3754 static void intel_enable_planes(struct drm_crtc *crtc)
3755 {
3756 struct drm_device *dev = crtc->dev;
3757 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3758 struct drm_plane *plane;
3759 struct intel_plane *intel_plane;
3760
3761 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3762 intel_plane = to_intel_plane(plane);
3763 if (intel_plane->pipe == pipe)
3764 intel_plane_restore(&intel_plane->base);
3765 }
3766 }
3767
3768 static void intel_disable_planes(struct drm_crtc *crtc)
3769 {
3770 struct drm_device *dev = crtc->dev;
3771 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3772 struct drm_plane *plane;
3773 struct intel_plane *intel_plane;
3774
3775 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3776 intel_plane = to_intel_plane(plane);
3777 if (intel_plane->pipe == pipe)
3778 intel_plane_disable(&intel_plane->base);
3779 }
3780 }
3781
3782 void hsw_enable_ips(struct intel_crtc *crtc)
3783 {
3784 struct drm_device *dev = crtc->base.dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786
3787 if (!crtc->config.ips_enabled)
3788 return;
3789
3790 /* We can only enable IPS after we enable a plane and wait for a vblank */
3791 intel_wait_for_vblank(dev, crtc->pipe);
3792
3793 assert_plane_enabled(dev_priv, crtc->plane);
3794 if (IS_BROADWELL(dev)) {
3795 mutex_lock(&dev_priv->rps.hw_lock);
3796 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3797 mutex_unlock(&dev_priv->rps.hw_lock);
3798 /* Quoting Art Runyan: "its not safe to expect any particular
3799 * value in IPS_CTL bit 31 after enabling IPS through the
3800 * mailbox." Moreover, the mailbox may return a bogus state,
3801 * so we need to just enable it and continue on.
3802 */
3803 } else {
3804 I915_WRITE(IPS_CTL, IPS_ENABLE);
3805 /* The bit only becomes 1 in the next vblank, so this wait here
3806 * is essentially intel_wait_for_vblank. If we don't have this
3807 * and don't wait for vblanks until the end of crtc_enable, then
3808 * the HW state readout code will complain that the expected
3809 * IPS_CTL value is not the one we read. */
3810 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3811 DRM_ERROR("Timed out waiting for IPS enable\n");
3812 }
3813 }
3814
3815 void hsw_disable_ips(struct intel_crtc *crtc)
3816 {
3817 struct drm_device *dev = crtc->base.dev;
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819
3820 if (!crtc->config.ips_enabled)
3821 return;
3822
3823 assert_plane_enabled(dev_priv, crtc->plane);
3824 if (IS_BROADWELL(dev)) {
3825 mutex_lock(&dev_priv->rps.hw_lock);
3826 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3827 mutex_unlock(&dev_priv->rps.hw_lock);
3828 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3829 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3830 DRM_ERROR("Timed out waiting for IPS disable\n");
3831 } else {
3832 I915_WRITE(IPS_CTL, 0);
3833 POSTING_READ(IPS_CTL);
3834 }
3835
3836 /* We need to wait for a vblank before we can disable the plane. */
3837 intel_wait_for_vblank(dev, crtc->pipe);
3838 }
3839
3840 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3841 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3842 {
3843 struct drm_device *dev = crtc->dev;
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3846 enum pipe pipe = intel_crtc->pipe;
3847 int palreg = PALETTE(pipe);
3848 int i;
3849 bool reenable_ips = false;
3850
3851 /* The clocks have to be on to load the palette. */
3852 if (!crtc->enabled || !intel_crtc->active)
3853 return;
3854
3855 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3856 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3857 assert_dsi_pll_enabled(dev_priv);
3858 else
3859 assert_pll_enabled(dev_priv, pipe);
3860 }
3861
3862 /* use legacy palette for Ironlake */
3863 if (!HAS_GMCH_DISPLAY(dev))
3864 palreg = LGC_PALETTE(pipe);
3865
3866 /* Workaround : Do not read or write the pipe palette/gamma data while
3867 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3868 */
3869 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3870 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3871 GAMMA_MODE_MODE_SPLIT)) {
3872 hsw_disable_ips(intel_crtc);
3873 reenable_ips = true;
3874 }
3875
3876 for (i = 0; i < 256; i++) {
3877 I915_WRITE(palreg + 4 * i,
3878 (intel_crtc->lut_r[i] << 16) |
3879 (intel_crtc->lut_g[i] << 8) |
3880 intel_crtc->lut_b[i]);
3881 }
3882
3883 if (reenable_ips)
3884 hsw_enable_ips(intel_crtc);
3885 }
3886
3887 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3888 {
3889 if (!enable && intel_crtc->overlay) {
3890 struct drm_device *dev = intel_crtc->base.dev;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3892
3893 mutex_lock(&dev->struct_mutex);
3894 dev_priv->mm.interruptible = false;
3895 (void) intel_overlay_switch_off(intel_crtc->overlay);
3896 dev_priv->mm.interruptible = true;
3897 mutex_unlock(&dev->struct_mutex);
3898 }
3899
3900 /* Let userspace switch the overlay on again. In most cases userspace
3901 * has to recompute where to put it anyway.
3902 */
3903 }
3904
3905 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3906 {
3907 struct drm_device *dev = crtc->dev;
3908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3909 int pipe = intel_crtc->pipe;
3910
3911 assert_vblank_disabled(crtc);
3912
3913 drm_vblank_on(dev, pipe);
3914
3915 intel_enable_primary_hw_plane(crtc->primary, crtc);
3916 intel_enable_planes(crtc);
3917 intel_crtc_update_cursor(crtc, true);
3918 intel_crtc_dpms_overlay(intel_crtc, true);
3919
3920 hsw_enable_ips(intel_crtc);
3921
3922 mutex_lock(&dev->struct_mutex);
3923 intel_update_fbc(dev);
3924 mutex_unlock(&dev->struct_mutex);
3925
3926 /*
3927 * FIXME: Once we grow proper nuclear flip support out of this we need
3928 * to compute the mask of flip planes precisely. For the time being
3929 * consider this a flip from a NULL plane.
3930 */
3931 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3932 }
3933
3934 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3935 {
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939 int pipe = intel_crtc->pipe;
3940 int plane = intel_crtc->plane;
3941
3942 intel_crtc_wait_for_pending_flips(crtc);
3943
3944 if (dev_priv->fbc.plane == plane)
3945 intel_disable_fbc(dev);
3946
3947 hsw_disable_ips(intel_crtc);
3948
3949 intel_crtc_dpms_overlay(intel_crtc, false);
3950 intel_crtc_update_cursor(crtc, false);
3951 intel_disable_planes(crtc);
3952 intel_disable_primary_hw_plane(crtc->primary, crtc);
3953
3954 /*
3955 * FIXME: Once we grow proper nuclear flip support out of this we need
3956 * to compute the mask of flip planes precisely. For the time being
3957 * consider this a flip to a NULL plane.
3958 */
3959 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3960
3961 drm_vblank_off(dev, pipe);
3962
3963 assert_vblank_disabled(crtc);
3964 }
3965
3966 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3967 {
3968 struct drm_device *dev = crtc->dev;
3969 struct drm_i915_private *dev_priv = dev->dev_private;
3970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3971 struct intel_encoder *encoder;
3972 int pipe = intel_crtc->pipe;
3973
3974 WARN_ON(!crtc->enabled);
3975
3976 if (intel_crtc->active)
3977 return;
3978
3979 if (intel_crtc->config.has_pch_encoder)
3980 intel_prepare_shared_dpll(intel_crtc);
3981
3982 if (intel_crtc->config.has_dp_encoder)
3983 intel_dp_set_m_n(intel_crtc);
3984
3985 intel_set_pipe_timings(intel_crtc);
3986
3987 if (intel_crtc->config.has_pch_encoder) {
3988 intel_cpu_transcoder_set_m_n(intel_crtc,
3989 &intel_crtc->config.fdi_m_n, NULL);
3990 }
3991
3992 ironlake_set_pipeconf(crtc);
3993
3994 intel_crtc->active = true;
3995
3996 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3997 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3998
3999 for_each_encoder_on_crtc(dev, crtc, encoder)
4000 if (encoder->pre_enable)
4001 encoder->pre_enable(encoder);
4002
4003 if (intel_crtc->config.has_pch_encoder) {
4004 /* Note: FDI PLL enabling _must_ be done before we enable the
4005 * cpu pipes, hence this is separate from all the other fdi/pch
4006 * enabling. */
4007 ironlake_fdi_pll_enable(intel_crtc);
4008 } else {
4009 assert_fdi_tx_disabled(dev_priv, pipe);
4010 assert_fdi_rx_disabled(dev_priv, pipe);
4011 }
4012
4013 ironlake_pfit_enable(intel_crtc);
4014
4015 /*
4016 * On ILK+ LUT must be loaded before the pipe is running but with
4017 * clocks enabled
4018 */
4019 intel_crtc_load_lut(crtc);
4020
4021 intel_update_watermarks(crtc);
4022 intel_enable_pipe(intel_crtc);
4023
4024 if (intel_crtc->config.has_pch_encoder)
4025 ironlake_pch_enable(crtc);
4026
4027 for_each_encoder_on_crtc(dev, crtc, encoder)
4028 encoder->enable(encoder);
4029
4030 if (HAS_PCH_CPT(dev))
4031 cpt_verify_modeset(dev, intel_crtc->pipe);
4032
4033 intel_crtc_enable_planes(crtc);
4034 }
4035
4036 /* IPS only exists on ULT machines and is tied to pipe A. */
4037 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4038 {
4039 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4040 }
4041
4042 /*
4043 * This implements the workaround described in the "notes" section of the mode
4044 * set sequence documentation. When going from no pipes or single pipe to
4045 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4046 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4047 */
4048 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4049 {
4050 struct drm_device *dev = crtc->base.dev;
4051 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4052
4053 /* We want to get the other_active_crtc only if there's only 1 other
4054 * active crtc. */
4055 for_each_intel_crtc(dev, crtc_it) {
4056 if (!crtc_it->active || crtc_it == crtc)
4057 continue;
4058
4059 if (other_active_crtc)
4060 return;
4061
4062 other_active_crtc = crtc_it;
4063 }
4064 if (!other_active_crtc)
4065 return;
4066
4067 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4068 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4069 }
4070
4071 static void haswell_crtc_enable(struct drm_crtc *crtc)
4072 {
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4076 struct intel_encoder *encoder;
4077 int pipe = intel_crtc->pipe;
4078
4079 WARN_ON(!crtc->enabled);
4080
4081 if (intel_crtc->active)
4082 return;
4083
4084 if (intel_crtc_to_shared_dpll(intel_crtc))
4085 intel_enable_shared_dpll(intel_crtc);
4086
4087 if (intel_crtc->config.has_dp_encoder)
4088 intel_dp_set_m_n(intel_crtc);
4089
4090 intel_set_pipe_timings(intel_crtc);
4091
4092 if (intel_crtc->config.has_pch_encoder) {
4093 intel_cpu_transcoder_set_m_n(intel_crtc,
4094 &intel_crtc->config.fdi_m_n, NULL);
4095 }
4096
4097 haswell_set_pipeconf(crtc);
4098
4099 intel_set_pipe_csc(crtc);
4100
4101 intel_crtc->active = true;
4102
4103 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4104 for_each_encoder_on_crtc(dev, crtc, encoder)
4105 if (encoder->pre_enable)
4106 encoder->pre_enable(encoder);
4107
4108 if (intel_crtc->config.has_pch_encoder) {
4109 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4110 dev_priv->display.fdi_link_train(crtc);
4111 }
4112
4113 intel_ddi_enable_pipe_clock(intel_crtc);
4114
4115 ironlake_pfit_enable(intel_crtc);
4116
4117 /*
4118 * On ILK+ LUT must be loaded before the pipe is running but with
4119 * clocks enabled
4120 */
4121 intel_crtc_load_lut(crtc);
4122
4123 intel_ddi_set_pipe_settings(crtc);
4124 intel_ddi_enable_transcoder_func(crtc);
4125
4126 intel_update_watermarks(crtc);
4127 intel_enable_pipe(intel_crtc);
4128
4129 if (intel_crtc->config.has_pch_encoder)
4130 lpt_pch_enable(crtc);
4131
4132 if (intel_crtc->config.dp_encoder_is_mst)
4133 intel_ddi_set_vc_payload_alloc(crtc, true);
4134
4135 for_each_encoder_on_crtc(dev, crtc, encoder) {
4136 encoder->enable(encoder);
4137 intel_opregion_notify_encoder(encoder, true);
4138 }
4139
4140 /* If we change the relative order between pipe/planes enabling, we need
4141 * to change the workaround. */
4142 haswell_mode_set_planes_workaround(intel_crtc);
4143 intel_crtc_enable_planes(crtc);
4144 }
4145
4146 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4147 {
4148 struct drm_device *dev = crtc->base.dev;
4149 struct drm_i915_private *dev_priv = dev->dev_private;
4150 int pipe = crtc->pipe;
4151
4152 /* To avoid upsetting the power well on haswell only disable the pfit if
4153 * it's in use. The hw state code will make sure we get this right. */
4154 if (crtc->config.pch_pfit.enabled) {
4155 I915_WRITE(PF_CTL(pipe), 0);
4156 I915_WRITE(PF_WIN_POS(pipe), 0);
4157 I915_WRITE(PF_WIN_SZ(pipe), 0);
4158 }
4159 }
4160
4161 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4162 {
4163 struct drm_device *dev = crtc->dev;
4164 struct drm_i915_private *dev_priv = dev->dev_private;
4165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4166 struct intel_encoder *encoder;
4167 int pipe = intel_crtc->pipe;
4168 u32 reg, temp;
4169
4170 if (!intel_crtc->active)
4171 return;
4172
4173 intel_crtc_disable_planes(crtc);
4174
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 encoder->disable(encoder);
4177
4178 if (intel_crtc->config.has_pch_encoder)
4179 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4180
4181 intel_disable_pipe(dev_priv, pipe);
4182 ironlake_pfit_disable(intel_crtc);
4183
4184 for_each_encoder_on_crtc(dev, crtc, encoder)
4185 if (encoder->post_disable)
4186 encoder->post_disable(encoder);
4187
4188 if (intel_crtc->config.has_pch_encoder) {
4189 ironlake_fdi_disable(crtc);
4190
4191 ironlake_disable_pch_transcoder(dev_priv, pipe);
4192 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4193
4194 if (HAS_PCH_CPT(dev)) {
4195 /* disable TRANS_DP_CTL */
4196 reg = TRANS_DP_CTL(pipe);
4197 temp = I915_READ(reg);
4198 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4199 TRANS_DP_PORT_SEL_MASK);
4200 temp |= TRANS_DP_PORT_SEL_NONE;
4201 I915_WRITE(reg, temp);
4202
4203 /* disable DPLL_SEL */
4204 temp = I915_READ(PCH_DPLL_SEL);
4205 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4206 I915_WRITE(PCH_DPLL_SEL, temp);
4207 }
4208
4209 /* disable PCH DPLL */
4210 intel_disable_shared_dpll(intel_crtc);
4211
4212 ironlake_fdi_pll_disable(intel_crtc);
4213 }
4214
4215 intel_crtc->active = false;
4216 intel_update_watermarks(crtc);
4217
4218 mutex_lock(&dev->struct_mutex);
4219 intel_update_fbc(dev);
4220 mutex_unlock(&dev->struct_mutex);
4221 }
4222
4223 static void haswell_crtc_disable(struct drm_crtc *crtc)
4224 {
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4228 struct intel_encoder *encoder;
4229 int pipe = intel_crtc->pipe;
4230 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4231
4232 if (!intel_crtc->active)
4233 return;
4234
4235 intel_crtc_disable_planes(crtc);
4236
4237 for_each_encoder_on_crtc(dev, crtc, encoder) {
4238 intel_opregion_notify_encoder(encoder, false);
4239 encoder->disable(encoder);
4240 }
4241
4242 if (intel_crtc->config.has_pch_encoder)
4243 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4244 intel_disable_pipe(dev_priv, pipe);
4245
4246 if (intel_crtc->config.dp_encoder_is_mst)
4247 intel_ddi_set_vc_payload_alloc(crtc, false);
4248
4249 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4250
4251 ironlake_pfit_disable(intel_crtc);
4252
4253 intel_ddi_disable_pipe_clock(intel_crtc);
4254
4255 if (intel_crtc->config.has_pch_encoder) {
4256 lpt_disable_pch_transcoder(dev_priv);
4257 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4258 intel_ddi_fdi_disable(crtc);
4259 }
4260
4261 for_each_encoder_on_crtc(dev, crtc, encoder)
4262 if (encoder->post_disable)
4263 encoder->post_disable(encoder);
4264
4265 intel_crtc->active = false;
4266 intel_update_watermarks(crtc);
4267
4268 mutex_lock(&dev->struct_mutex);
4269 intel_update_fbc(dev);
4270 mutex_unlock(&dev->struct_mutex);
4271
4272 if (intel_crtc_to_shared_dpll(intel_crtc))
4273 intel_disable_shared_dpll(intel_crtc);
4274 }
4275
4276 static void ironlake_crtc_off(struct drm_crtc *crtc)
4277 {
4278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4279 intel_put_shared_dpll(intel_crtc);
4280 }
4281
4282
4283 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4284 {
4285 struct drm_device *dev = crtc->base.dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 struct intel_crtc_config *pipe_config = &crtc->config;
4288
4289 if (!crtc->config.gmch_pfit.control)
4290 return;
4291
4292 /*
4293 * The panel fitter should only be adjusted whilst the pipe is disabled,
4294 * according to register description and PRM.
4295 */
4296 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4297 assert_pipe_disabled(dev_priv, crtc->pipe);
4298
4299 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4300 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4301
4302 /* Border color in case we don't scale up to the full screen. Black by
4303 * default, change to something else for debugging. */
4304 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4305 }
4306
4307 static enum intel_display_power_domain port_to_power_domain(enum port port)
4308 {
4309 switch (port) {
4310 case PORT_A:
4311 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4312 case PORT_B:
4313 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4314 case PORT_C:
4315 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4316 case PORT_D:
4317 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4318 default:
4319 WARN_ON_ONCE(1);
4320 return POWER_DOMAIN_PORT_OTHER;
4321 }
4322 }
4323
4324 #define for_each_power_domain(domain, mask) \
4325 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4326 if ((1 << (domain)) & (mask))
4327
4328 enum intel_display_power_domain
4329 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4330 {
4331 struct drm_device *dev = intel_encoder->base.dev;
4332 struct intel_digital_port *intel_dig_port;
4333
4334 switch (intel_encoder->type) {
4335 case INTEL_OUTPUT_UNKNOWN:
4336 /* Only DDI platforms should ever use this output type */
4337 WARN_ON_ONCE(!HAS_DDI(dev));
4338 case INTEL_OUTPUT_DISPLAYPORT:
4339 case INTEL_OUTPUT_HDMI:
4340 case INTEL_OUTPUT_EDP:
4341 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4342 return port_to_power_domain(intel_dig_port->port);
4343 case INTEL_OUTPUT_DP_MST:
4344 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4345 return port_to_power_domain(intel_dig_port->port);
4346 case INTEL_OUTPUT_ANALOG:
4347 return POWER_DOMAIN_PORT_CRT;
4348 case INTEL_OUTPUT_DSI:
4349 return POWER_DOMAIN_PORT_DSI;
4350 default:
4351 return POWER_DOMAIN_PORT_OTHER;
4352 }
4353 }
4354
4355 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4356 {
4357 struct drm_device *dev = crtc->dev;
4358 struct intel_encoder *intel_encoder;
4359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4360 enum pipe pipe = intel_crtc->pipe;
4361 unsigned long mask;
4362 enum transcoder transcoder;
4363
4364 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4365
4366 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4367 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4368 if (intel_crtc->config.pch_pfit.enabled ||
4369 intel_crtc->config.pch_pfit.force_thru)
4370 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4371
4372 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4373 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4374
4375 return mask;
4376 }
4377
4378 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4379 bool enable)
4380 {
4381 if (dev_priv->power_domains.init_power_on == enable)
4382 return;
4383
4384 if (enable)
4385 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4386 else
4387 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4388
4389 dev_priv->power_domains.init_power_on = enable;
4390 }
4391
4392 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4393 {
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4396 struct intel_crtc *crtc;
4397
4398 /*
4399 * First get all needed power domains, then put all unneeded, to avoid
4400 * any unnecessary toggling of the power wells.
4401 */
4402 for_each_intel_crtc(dev, crtc) {
4403 enum intel_display_power_domain domain;
4404
4405 if (!crtc->base.enabled)
4406 continue;
4407
4408 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4409
4410 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4411 intel_display_power_get(dev_priv, domain);
4412 }
4413
4414 for_each_intel_crtc(dev, crtc) {
4415 enum intel_display_power_domain domain;
4416
4417 for_each_power_domain(domain, crtc->enabled_power_domains)
4418 intel_display_power_put(dev_priv, domain);
4419
4420 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4421 }
4422
4423 intel_display_set_init_power(dev_priv, false);
4424 }
4425
4426 /* returns HPLL frequency in kHz */
4427 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4428 {
4429 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4430
4431 /* Obtain SKU information */
4432 mutex_lock(&dev_priv->dpio_lock);
4433 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4434 CCK_FUSE_HPLL_FREQ_MASK;
4435 mutex_unlock(&dev_priv->dpio_lock);
4436
4437 return vco_freq[hpll_freq] * 1000;
4438 }
4439
4440 static void vlv_update_cdclk(struct drm_device *dev)
4441 {
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443
4444 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4445 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4446 dev_priv->vlv_cdclk_freq);
4447
4448 /*
4449 * Program the gmbus_freq based on the cdclk frequency.
4450 * BSpec erroneously claims we should aim for 4MHz, but
4451 * in fact 1MHz is the correct frequency.
4452 */
4453 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4454 }
4455
4456 /* Adjust CDclk dividers to allow high res or save power if possible */
4457 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4458 {
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 u32 val, cmd;
4461
4462 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4463
4464 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4465 cmd = 2;
4466 else if (cdclk == 266667)
4467 cmd = 1;
4468 else
4469 cmd = 0;
4470
4471 mutex_lock(&dev_priv->rps.hw_lock);
4472 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4473 val &= ~DSPFREQGUAR_MASK;
4474 val |= (cmd << DSPFREQGUAR_SHIFT);
4475 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4476 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4477 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4478 50)) {
4479 DRM_ERROR("timed out waiting for CDclk change\n");
4480 }
4481 mutex_unlock(&dev_priv->rps.hw_lock);
4482
4483 if (cdclk == 400000) {
4484 u32 divider, vco;
4485
4486 vco = valleyview_get_vco(dev_priv);
4487 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4488
4489 mutex_lock(&dev_priv->dpio_lock);
4490 /* adjust cdclk divider */
4491 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4492 val &= ~DISPLAY_FREQUENCY_VALUES;
4493 val |= divider;
4494 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4495
4496 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4497 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4498 50))
4499 DRM_ERROR("timed out waiting for CDclk change\n");
4500 mutex_unlock(&dev_priv->dpio_lock);
4501 }
4502
4503 mutex_lock(&dev_priv->dpio_lock);
4504 /* adjust self-refresh exit latency value */
4505 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4506 val &= ~0x7f;
4507
4508 /*
4509 * For high bandwidth configs, we set a higher latency in the bunit
4510 * so that the core display fetch happens in time to avoid underruns.
4511 */
4512 if (cdclk == 400000)
4513 val |= 4500 / 250; /* 4.5 usec */
4514 else
4515 val |= 3000 / 250; /* 3.0 usec */
4516 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4517 mutex_unlock(&dev_priv->dpio_lock);
4518
4519 vlv_update_cdclk(dev);
4520 }
4521
4522 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4523 {
4524 struct drm_i915_private *dev_priv = dev->dev_private;
4525 u32 val, cmd;
4526
4527 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4528
4529 switch (cdclk) {
4530 case 400000:
4531 cmd = 3;
4532 break;
4533 case 333333:
4534 case 320000:
4535 cmd = 2;
4536 break;
4537 case 266667:
4538 cmd = 1;
4539 break;
4540 case 200000:
4541 cmd = 0;
4542 break;
4543 default:
4544 WARN_ON(1);
4545 return;
4546 }
4547
4548 mutex_lock(&dev_priv->rps.hw_lock);
4549 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4550 val &= ~DSPFREQGUAR_MASK_CHV;
4551 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4552 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4553 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4554 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4555 50)) {
4556 DRM_ERROR("timed out waiting for CDclk change\n");
4557 }
4558 mutex_unlock(&dev_priv->rps.hw_lock);
4559
4560 vlv_update_cdclk(dev);
4561 }
4562
4563 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4564 int max_pixclk)
4565 {
4566 int vco = valleyview_get_vco(dev_priv);
4567 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4568
4569 /* FIXME: Punit isn't quite ready yet */
4570 if (IS_CHERRYVIEW(dev_priv->dev))
4571 return 400000;
4572
4573 /*
4574 * Really only a few cases to deal with, as only 4 CDclks are supported:
4575 * 200MHz
4576 * 267MHz
4577 * 320/333MHz (depends on HPLL freq)
4578 * 400MHz
4579 * So we check to see whether we're above 90% of the lower bin and
4580 * adjust if needed.
4581 *
4582 * We seem to get an unstable or solid color picture at 200MHz.
4583 * Not sure what's wrong. For now use 200MHz only when all pipes
4584 * are off.
4585 */
4586 if (max_pixclk > freq_320*9/10)
4587 return 400000;
4588 else if (max_pixclk > 266667*9/10)
4589 return freq_320;
4590 else if (max_pixclk > 0)
4591 return 266667;
4592 else
4593 return 200000;
4594 }
4595
4596 /* compute the max pixel clock for new configuration */
4597 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4598 {
4599 struct drm_device *dev = dev_priv->dev;
4600 struct intel_crtc *intel_crtc;
4601 int max_pixclk = 0;
4602
4603 for_each_intel_crtc(dev, intel_crtc) {
4604 if (intel_crtc->new_enabled)
4605 max_pixclk = max(max_pixclk,
4606 intel_crtc->new_config->adjusted_mode.crtc_clock);
4607 }
4608
4609 return max_pixclk;
4610 }
4611
4612 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4613 unsigned *prepare_pipes)
4614 {
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 struct intel_crtc *intel_crtc;
4617 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4618
4619 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4620 dev_priv->vlv_cdclk_freq)
4621 return;
4622
4623 /* disable/enable all currently active pipes while we change cdclk */
4624 for_each_intel_crtc(dev, intel_crtc)
4625 if (intel_crtc->base.enabled)
4626 *prepare_pipes |= (1 << intel_crtc->pipe);
4627 }
4628
4629 static void valleyview_modeset_global_resources(struct drm_device *dev)
4630 {
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4633 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4634
4635 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4636 if (IS_CHERRYVIEW(dev))
4637 cherryview_set_cdclk(dev, req_cdclk);
4638 else
4639 valleyview_set_cdclk(dev, req_cdclk);
4640 }
4641
4642 modeset_update_crtc_power_domains(dev);
4643 }
4644
4645 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4646 {
4647 struct drm_device *dev = crtc->dev;
4648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4649 struct intel_encoder *encoder;
4650 int pipe = intel_crtc->pipe;
4651 bool is_dsi;
4652
4653 WARN_ON(!crtc->enabled);
4654
4655 if (intel_crtc->active)
4656 return;
4657
4658 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4659
4660 if (!is_dsi) {
4661 if (IS_CHERRYVIEW(dev))
4662 chv_prepare_pll(intel_crtc);
4663 else
4664 vlv_prepare_pll(intel_crtc);
4665 }
4666
4667 if (intel_crtc->config.has_dp_encoder)
4668 intel_dp_set_m_n(intel_crtc);
4669
4670 intel_set_pipe_timings(intel_crtc);
4671
4672 i9xx_set_pipeconf(intel_crtc);
4673
4674 intel_crtc->active = true;
4675
4676 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4677
4678 for_each_encoder_on_crtc(dev, crtc, encoder)
4679 if (encoder->pre_pll_enable)
4680 encoder->pre_pll_enable(encoder);
4681
4682 if (!is_dsi) {
4683 if (IS_CHERRYVIEW(dev))
4684 chv_enable_pll(intel_crtc);
4685 else
4686 vlv_enable_pll(intel_crtc);
4687 }
4688
4689 for_each_encoder_on_crtc(dev, crtc, encoder)
4690 if (encoder->pre_enable)
4691 encoder->pre_enable(encoder);
4692
4693 i9xx_pfit_enable(intel_crtc);
4694
4695 intel_crtc_load_lut(crtc);
4696
4697 intel_update_watermarks(crtc);
4698 intel_enable_pipe(intel_crtc);
4699
4700 for_each_encoder_on_crtc(dev, crtc, encoder)
4701 encoder->enable(encoder);
4702
4703 intel_crtc_enable_planes(crtc);
4704
4705 /* Underruns don't raise interrupts, so check manually. */
4706 i9xx_check_fifo_underruns(dev);
4707 }
4708
4709 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4710 {
4711 struct drm_device *dev = crtc->base.dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4715 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4716 }
4717
4718 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4719 {
4720 struct drm_device *dev = crtc->dev;
4721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4722 struct intel_encoder *encoder;
4723 int pipe = intel_crtc->pipe;
4724
4725 WARN_ON(!crtc->enabled);
4726
4727 if (intel_crtc->active)
4728 return;
4729
4730 i9xx_set_pll_dividers(intel_crtc);
4731
4732 if (intel_crtc->config.has_dp_encoder)
4733 intel_dp_set_m_n(intel_crtc);
4734
4735 intel_set_pipe_timings(intel_crtc);
4736
4737 i9xx_set_pipeconf(intel_crtc);
4738
4739 intel_crtc->active = true;
4740
4741 if (!IS_GEN2(dev))
4742 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4743
4744 for_each_encoder_on_crtc(dev, crtc, encoder)
4745 if (encoder->pre_enable)
4746 encoder->pre_enable(encoder);
4747
4748 i9xx_enable_pll(intel_crtc);
4749
4750 i9xx_pfit_enable(intel_crtc);
4751
4752 intel_crtc_load_lut(crtc);
4753
4754 intel_update_watermarks(crtc);
4755 intel_enable_pipe(intel_crtc);
4756
4757 for_each_encoder_on_crtc(dev, crtc, encoder)
4758 encoder->enable(encoder);
4759
4760 intel_crtc_enable_planes(crtc);
4761
4762 /*
4763 * Gen2 reports pipe underruns whenever all planes are disabled.
4764 * So don't enable underrun reporting before at least some planes
4765 * are enabled.
4766 * FIXME: Need to fix the logic to work when we turn off all planes
4767 * but leave the pipe running.
4768 */
4769 if (IS_GEN2(dev))
4770 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4771
4772 /* Underruns don't raise interrupts, so check manually. */
4773 i9xx_check_fifo_underruns(dev);
4774 }
4775
4776 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4777 {
4778 struct drm_device *dev = crtc->base.dev;
4779 struct drm_i915_private *dev_priv = dev->dev_private;
4780
4781 if (!crtc->config.gmch_pfit.control)
4782 return;
4783
4784 assert_pipe_disabled(dev_priv, crtc->pipe);
4785
4786 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4787 I915_READ(PFIT_CONTROL));
4788 I915_WRITE(PFIT_CONTROL, 0);
4789 }
4790
4791 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4792 {
4793 struct drm_device *dev = crtc->dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4796 struct intel_encoder *encoder;
4797 int pipe = intel_crtc->pipe;
4798
4799 if (!intel_crtc->active)
4800 return;
4801
4802 /*
4803 * Gen2 reports pipe underruns whenever all planes are disabled.
4804 * So diasble underrun reporting before all the planes get disabled.
4805 * FIXME: Need to fix the logic to work when we turn off all planes
4806 * but leave the pipe running.
4807 */
4808 if (IS_GEN2(dev))
4809 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4810
4811 /*
4812 * Vblank time updates from the shadow to live plane control register
4813 * are blocked if the memory self-refresh mode is active at that
4814 * moment. So to make sure the plane gets truly disabled, disable
4815 * first the self-refresh mode. The self-refresh enable bit in turn
4816 * will be checked/applied by the HW only at the next frame start
4817 * event which is after the vblank start event, so we need to have a
4818 * wait-for-vblank between disabling the plane and the pipe.
4819 */
4820 intel_set_memory_cxsr(dev_priv, false);
4821 intel_crtc_disable_planes(crtc);
4822
4823 for_each_encoder_on_crtc(dev, crtc, encoder)
4824 encoder->disable(encoder);
4825
4826 /*
4827 * On gen2 planes are double buffered but the pipe isn't, so we must
4828 * wait for planes to fully turn off before disabling the pipe.
4829 * We also need to wait on all gmch platforms because of the
4830 * self-refresh mode constraint explained above.
4831 */
4832 intel_wait_for_vblank(dev, pipe);
4833
4834 intel_disable_pipe(dev_priv, pipe);
4835
4836 i9xx_pfit_disable(intel_crtc);
4837
4838 for_each_encoder_on_crtc(dev, crtc, encoder)
4839 if (encoder->post_disable)
4840 encoder->post_disable(encoder);
4841
4842 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4843 if (IS_CHERRYVIEW(dev))
4844 chv_disable_pll(dev_priv, pipe);
4845 else if (IS_VALLEYVIEW(dev))
4846 vlv_disable_pll(dev_priv, pipe);
4847 else
4848 i9xx_disable_pll(dev_priv, pipe);
4849 }
4850
4851 if (!IS_GEN2(dev))
4852 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4853
4854 intel_crtc->active = false;
4855 intel_update_watermarks(crtc);
4856
4857 mutex_lock(&dev->struct_mutex);
4858 intel_update_fbc(dev);
4859 mutex_unlock(&dev->struct_mutex);
4860 }
4861
4862 static void i9xx_crtc_off(struct drm_crtc *crtc)
4863 {
4864 }
4865
4866 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4867 bool enabled)
4868 {
4869 struct drm_device *dev = crtc->dev;
4870 struct drm_i915_master_private *master_priv;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4872 int pipe = intel_crtc->pipe;
4873
4874 if (!dev->primary->master)
4875 return;
4876
4877 master_priv = dev->primary->master->driver_priv;
4878 if (!master_priv->sarea_priv)
4879 return;
4880
4881 switch (pipe) {
4882 case 0:
4883 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4884 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4885 break;
4886 case 1:
4887 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4888 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4889 break;
4890 default:
4891 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4892 break;
4893 }
4894 }
4895
4896 /* Master function to enable/disable CRTC and corresponding power wells */
4897 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4898 {
4899 struct drm_device *dev = crtc->dev;
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902 enum intel_display_power_domain domain;
4903 unsigned long domains;
4904
4905 if (enable) {
4906 if (!intel_crtc->active) {
4907 domains = get_crtc_power_domains(crtc);
4908 for_each_power_domain(domain, domains)
4909 intel_display_power_get(dev_priv, domain);
4910 intel_crtc->enabled_power_domains = domains;
4911
4912 dev_priv->display.crtc_enable(crtc);
4913 }
4914 } else {
4915 if (intel_crtc->active) {
4916 dev_priv->display.crtc_disable(crtc);
4917
4918 domains = intel_crtc->enabled_power_domains;
4919 for_each_power_domain(domain, domains)
4920 intel_display_power_put(dev_priv, domain);
4921 intel_crtc->enabled_power_domains = 0;
4922 }
4923 }
4924 }
4925
4926 /**
4927 * Sets the power management mode of the pipe and plane.
4928 */
4929 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4930 {
4931 struct drm_device *dev = crtc->dev;
4932 struct intel_encoder *intel_encoder;
4933 bool enable = false;
4934
4935 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4936 enable |= intel_encoder->connectors_active;
4937
4938 intel_crtc_control(crtc, enable);
4939
4940 intel_crtc_update_sarea(crtc, enable);
4941 }
4942
4943 static void intel_crtc_disable(struct drm_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_connector *connector;
4947 struct drm_i915_private *dev_priv = dev->dev_private;
4948 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4949 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4950
4951 /* crtc should still be enabled when we disable it. */
4952 WARN_ON(!crtc->enabled);
4953
4954 dev_priv->display.crtc_disable(crtc);
4955 intel_crtc_update_sarea(crtc, false);
4956 dev_priv->display.off(crtc);
4957
4958 if (crtc->primary->fb) {
4959 mutex_lock(&dev->struct_mutex);
4960 intel_unpin_fb_obj(old_obj);
4961 i915_gem_track_fb(old_obj, NULL,
4962 INTEL_FRONTBUFFER_PRIMARY(pipe));
4963 mutex_unlock(&dev->struct_mutex);
4964 crtc->primary->fb = NULL;
4965 }
4966
4967 /* Update computed state. */
4968 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4969 if (!connector->encoder || !connector->encoder->crtc)
4970 continue;
4971
4972 if (connector->encoder->crtc != crtc)
4973 continue;
4974
4975 connector->dpms = DRM_MODE_DPMS_OFF;
4976 to_intel_encoder(connector->encoder)->connectors_active = false;
4977 }
4978 }
4979
4980 void intel_encoder_destroy(struct drm_encoder *encoder)
4981 {
4982 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4983
4984 drm_encoder_cleanup(encoder);
4985 kfree(intel_encoder);
4986 }
4987
4988 /* Simple dpms helper for encoders with just one connector, no cloning and only
4989 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4990 * state of the entire output pipe. */
4991 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4992 {
4993 if (mode == DRM_MODE_DPMS_ON) {
4994 encoder->connectors_active = true;
4995
4996 intel_crtc_update_dpms(encoder->base.crtc);
4997 } else {
4998 encoder->connectors_active = false;
4999
5000 intel_crtc_update_dpms(encoder->base.crtc);
5001 }
5002 }
5003
5004 /* Cross check the actual hw state with our own modeset state tracking (and it's
5005 * internal consistency). */
5006 static void intel_connector_check_state(struct intel_connector *connector)
5007 {
5008 if (connector->get_hw_state(connector)) {
5009 struct intel_encoder *encoder = connector->encoder;
5010 struct drm_crtc *crtc;
5011 bool encoder_enabled;
5012 enum pipe pipe;
5013
5014 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5015 connector->base.base.id,
5016 connector->base.name);
5017
5018 /* there is no real hw state for MST connectors */
5019 if (connector->mst_port)
5020 return;
5021
5022 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5023 "wrong connector dpms state\n");
5024 WARN(connector->base.encoder != &encoder->base,
5025 "active connector not linked to encoder\n");
5026
5027 if (encoder) {
5028 WARN(!encoder->connectors_active,
5029 "encoder->connectors_active not set\n");
5030
5031 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5032 WARN(!encoder_enabled, "encoder not enabled\n");
5033 if (WARN_ON(!encoder->base.crtc))
5034 return;
5035
5036 crtc = encoder->base.crtc;
5037
5038 WARN(!crtc->enabled, "crtc not enabled\n");
5039 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5040 WARN(pipe != to_intel_crtc(crtc)->pipe,
5041 "encoder active on the wrong pipe\n");
5042 }
5043 }
5044 }
5045
5046 /* Even simpler default implementation, if there's really no special case to
5047 * consider. */
5048 void intel_connector_dpms(struct drm_connector *connector, int mode)
5049 {
5050 /* All the simple cases only support two dpms states. */
5051 if (mode != DRM_MODE_DPMS_ON)
5052 mode = DRM_MODE_DPMS_OFF;
5053
5054 if (mode == connector->dpms)
5055 return;
5056
5057 connector->dpms = mode;
5058
5059 /* Only need to change hw state when actually enabled */
5060 if (connector->encoder)
5061 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5062
5063 intel_modeset_check_state(connector->dev);
5064 }
5065
5066 /* Simple connector->get_hw_state implementation for encoders that support only
5067 * one connector and no cloning and hence the encoder state determines the state
5068 * of the connector. */
5069 bool intel_connector_get_hw_state(struct intel_connector *connector)
5070 {
5071 enum pipe pipe = 0;
5072 struct intel_encoder *encoder = connector->encoder;
5073
5074 return encoder->get_hw_state(encoder, &pipe);
5075 }
5076
5077 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5078 struct intel_crtc_config *pipe_config)
5079 {
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *pipe_B_crtc =
5082 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5083
5084 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5085 pipe_name(pipe), pipe_config->fdi_lanes);
5086 if (pipe_config->fdi_lanes > 4) {
5087 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5088 pipe_name(pipe), pipe_config->fdi_lanes);
5089 return false;
5090 }
5091
5092 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5093 if (pipe_config->fdi_lanes > 2) {
5094 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5095 pipe_config->fdi_lanes);
5096 return false;
5097 } else {
5098 return true;
5099 }
5100 }
5101
5102 if (INTEL_INFO(dev)->num_pipes == 2)
5103 return true;
5104
5105 /* Ivybridge 3 pipe is really complicated */
5106 switch (pipe) {
5107 case PIPE_A:
5108 return true;
5109 case PIPE_B:
5110 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5111 pipe_config->fdi_lanes > 2) {
5112 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5113 pipe_name(pipe), pipe_config->fdi_lanes);
5114 return false;
5115 }
5116 return true;
5117 case PIPE_C:
5118 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5119 pipe_B_crtc->config.fdi_lanes <= 2) {
5120 if (pipe_config->fdi_lanes > 2) {
5121 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5122 pipe_name(pipe), pipe_config->fdi_lanes);
5123 return false;
5124 }
5125 } else {
5126 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5127 return false;
5128 }
5129 return true;
5130 default:
5131 BUG();
5132 }
5133 }
5134
5135 #define RETRY 1
5136 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5137 struct intel_crtc_config *pipe_config)
5138 {
5139 struct drm_device *dev = intel_crtc->base.dev;
5140 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5141 int lane, link_bw, fdi_dotclock;
5142 bool setup_ok, needs_recompute = false;
5143
5144 retry:
5145 /* FDI is a binary signal running at ~2.7GHz, encoding
5146 * each output octet as 10 bits. The actual frequency
5147 * is stored as a divider into a 100MHz clock, and the
5148 * mode pixel clock is stored in units of 1KHz.
5149 * Hence the bw of each lane in terms of the mode signal
5150 * is:
5151 */
5152 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5153
5154 fdi_dotclock = adjusted_mode->crtc_clock;
5155
5156 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5157 pipe_config->pipe_bpp);
5158
5159 pipe_config->fdi_lanes = lane;
5160
5161 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5162 link_bw, &pipe_config->fdi_m_n);
5163
5164 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5165 intel_crtc->pipe, pipe_config);
5166 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5167 pipe_config->pipe_bpp -= 2*3;
5168 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5169 pipe_config->pipe_bpp);
5170 needs_recompute = true;
5171 pipe_config->bw_constrained = true;
5172
5173 goto retry;
5174 }
5175
5176 if (needs_recompute)
5177 return RETRY;
5178
5179 return setup_ok ? 0 : -EINVAL;
5180 }
5181
5182 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5183 struct intel_crtc_config *pipe_config)
5184 {
5185 pipe_config->ips_enabled = i915.enable_ips &&
5186 hsw_crtc_supports_ips(crtc) &&
5187 pipe_config->pipe_bpp <= 24;
5188 }
5189
5190 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5191 struct intel_crtc_config *pipe_config)
5192 {
5193 struct drm_device *dev = crtc->base.dev;
5194 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5195
5196 /* FIXME should check pixel clock limits on all platforms */
5197 if (INTEL_INFO(dev)->gen < 4) {
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199 int clock_limit =
5200 dev_priv->display.get_display_clock_speed(dev);
5201
5202 /*
5203 * Enable pixel doubling when the dot clock
5204 * is > 90% of the (display) core speed.
5205 *
5206 * GDG double wide on either pipe,
5207 * otherwise pipe A only.
5208 */
5209 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5210 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5211 clock_limit *= 2;
5212 pipe_config->double_wide = true;
5213 }
5214
5215 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5216 return -EINVAL;
5217 }
5218
5219 /*
5220 * Pipe horizontal size must be even in:
5221 * - DVO ganged mode
5222 * - LVDS dual channel mode
5223 * - Double wide pipe
5224 */
5225 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5226 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5227 pipe_config->pipe_src_w &= ~1;
5228
5229 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5230 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5231 */
5232 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5233 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5234 return -EINVAL;
5235
5236 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5237 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5238 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5239 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5240 * for lvds. */
5241 pipe_config->pipe_bpp = 8*3;
5242 }
5243
5244 if (HAS_IPS(dev))
5245 hsw_compute_ips_config(crtc, pipe_config);
5246
5247 /*
5248 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5249 * old clock survives for now.
5250 */
5251 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5252 pipe_config->shared_dpll = crtc->config.shared_dpll;
5253
5254 if (pipe_config->has_pch_encoder)
5255 return ironlake_fdi_compute_config(crtc, pipe_config);
5256
5257 return 0;
5258 }
5259
5260 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5261 {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263 int vco = valleyview_get_vco(dev_priv);
5264 u32 val;
5265 int divider;
5266
5267 /* FIXME: Punit isn't quite ready yet */
5268 if (IS_CHERRYVIEW(dev))
5269 return 400000;
5270
5271 mutex_lock(&dev_priv->dpio_lock);
5272 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5273 mutex_unlock(&dev_priv->dpio_lock);
5274
5275 divider = val & DISPLAY_FREQUENCY_VALUES;
5276
5277 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5278 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5279 "cdclk change in progress\n");
5280
5281 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5282 }
5283
5284 static int i945_get_display_clock_speed(struct drm_device *dev)
5285 {
5286 return 400000;
5287 }
5288
5289 static int i915_get_display_clock_speed(struct drm_device *dev)
5290 {
5291 return 333000;
5292 }
5293
5294 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5295 {
5296 return 200000;
5297 }
5298
5299 static int pnv_get_display_clock_speed(struct drm_device *dev)
5300 {
5301 u16 gcfgc = 0;
5302
5303 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5304
5305 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5306 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5307 return 267000;
5308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5309 return 333000;
5310 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5311 return 444000;
5312 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5313 return 200000;
5314 default:
5315 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5316 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5317 return 133000;
5318 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5319 return 167000;
5320 }
5321 }
5322
5323 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5324 {
5325 u16 gcfgc = 0;
5326
5327 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5328
5329 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5330 return 133000;
5331 else {
5332 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5333 case GC_DISPLAY_CLOCK_333_MHZ:
5334 return 333000;
5335 default:
5336 case GC_DISPLAY_CLOCK_190_200_MHZ:
5337 return 190000;
5338 }
5339 }
5340 }
5341
5342 static int i865_get_display_clock_speed(struct drm_device *dev)
5343 {
5344 return 266000;
5345 }
5346
5347 static int i855_get_display_clock_speed(struct drm_device *dev)
5348 {
5349 u16 hpllcc = 0;
5350 /* Assume that the hardware is in the high speed state. This
5351 * should be the default.
5352 */
5353 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5354 case GC_CLOCK_133_200:
5355 case GC_CLOCK_100_200:
5356 return 200000;
5357 case GC_CLOCK_166_250:
5358 return 250000;
5359 case GC_CLOCK_100_133:
5360 return 133000;
5361 }
5362
5363 /* Shouldn't happen */
5364 return 0;
5365 }
5366
5367 static int i830_get_display_clock_speed(struct drm_device *dev)
5368 {
5369 return 133000;
5370 }
5371
5372 static void
5373 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5374 {
5375 while (*num > DATA_LINK_M_N_MASK ||
5376 *den > DATA_LINK_M_N_MASK) {
5377 *num >>= 1;
5378 *den >>= 1;
5379 }
5380 }
5381
5382 static void compute_m_n(unsigned int m, unsigned int n,
5383 uint32_t *ret_m, uint32_t *ret_n)
5384 {
5385 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5386 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5387 intel_reduce_m_n_ratio(ret_m, ret_n);
5388 }
5389
5390 void
5391 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5392 int pixel_clock, int link_clock,
5393 struct intel_link_m_n *m_n)
5394 {
5395 m_n->tu = 64;
5396
5397 compute_m_n(bits_per_pixel * pixel_clock,
5398 link_clock * nlanes * 8,
5399 &m_n->gmch_m, &m_n->gmch_n);
5400
5401 compute_m_n(pixel_clock, link_clock,
5402 &m_n->link_m, &m_n->link_n);
5403 }
5404
5405 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5406 {
5407 if (i915.panel_use_ssc >= 0)
5408 return i915.panel_use_ssc != 0;
5409 return dev_priv->vbt.lvds_use_ssc
5410 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5411 }
5412
5413 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5414 {
5415 struct drm_device *dev = crtc->dev;
5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417 int refclk;
5418
5419 if (IS_VALLEYVIEW(dev)) {
5420 refclk = 100000;
5421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5422 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5423 refclk = dev_priv->vbt.lvds_ssc_freq;
5424 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5425 } else if (!IS_GEN2(dev)) {
5426 refclk = 96000;
5427 } else {
5428 refclk = 48000;
5429 }
5430
5431 return refclk;
5432 }
5433
5434 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5435 {
5436 return (1 << dpll->n) << 16 | dpll->m2;
5437 }
5438
5439 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5440 {
5441 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5442 }
5443
5444 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5445 intel_clock_t *reduced_clock)
5446 {
5447 struct drm_device *dev = crtc->base.dev;
5448 u32 fp, fp2 = 0;
5449
5450 if (IS_PINEVIEW(dev)) {
5451 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5452 if (reduced_clock)
5453 fp2 = pnv_dpll_compute_fp(reduced_clock);
5454 } else {
5455 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5456 if (reduced_clock)
5457 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5458 }
5459
5460 crtc->config.dpll_hw_state.fp0 = fp;
5461
5462 crtc->lowfreq_avail = false;
5463 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5464 reduced_clock && i915.powersave) {
5465 crtc->config.dpll_hw_state.fp1 = fp2;
5466 crtc->lowfreq_avail = true;
5467 } else {
5468 crtc->config.dpll_hw_state.fp1 = fp;
5469 }
5470 }
5471
5472 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5473 pipe)
5474 {
5475 u32 reg_val;
5476
5477 /*
5478 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5479 * and set it to a reasonable value instead.
5480 */
5481 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5482 reg_val &= 0xffffff00;
5483 reg_val |= 0x00000030;
5484 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5485
5486 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5487 reg_val &= 0x8cffffff;
5488 reg_val = 0x8c000000;
5489 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5490
5491 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5492 reg_val &= 0xffffff00;
5493 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5494
5495 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5496 reg_val &= 0x00ffffff;
5497 reg_val |= 0xb0000000;
5498 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5499 }
5500
5501 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5502 struct intel_link_m_n *m_n)
5503 {
5504 struct drm_device *dev = crtc->base.dev;
5505 struct drm_i915_private *dev_priv = dev->dev_private;
5506 int pipe = crtc->pipe;
5507
5508 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5509 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5510 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5511 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5512 }
5513
5514 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5515 struct intel_link_m_n *m_n,
5516 struct intel_link_m_n *m2_n2)
5517 {
5518 struct drm_device *dev = crtc->base.dev;
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 int pipe = crtc->pipe;
5521 enum transcoder transcoder = crtc->config.cpu_transcoder;
5522
5523 if (INTEL_INFO(dev)->gen >= 5) {
5524 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5525 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5526 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5527 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5528 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5529 * for gen < 8) and if DRRS is supported (to make sure the
5530 * registers are not unnecessarily accessed).
5531 */
5532 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5533 crtc->config.has_drrs) {
5534 I915_WRITE(PIPE_DATA_M2(transcoder),
5535 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5536 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5537 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5538 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5539 }
5540 } else {
5541 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5542 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5543 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5544 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5545 }
5546 }
5547
5548 void intel_dp_set_m_n(struct intel_crtc *crtc)
5549 {
5550 if (crtc->config.has_pch_encoder)
5551 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5552 else
5553 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5554 &crtc->config.dp_m2_n2);
5555 }
5556
5557 static void vlv_update_pll(struct intel_crtc *crtc)
5558 {
5559 u32 dpll, dpll_md;
5560
5561 /*
5562 * Enable DPIO clock input. We should never disable the reference
5563 * clock for pipe B, since VGA hotplug / manual detection depends
5564 * on it.
5565 */
5566 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5567 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5568 /* We should never disable this, set it here for state tracking */
5569 if (crtc->pipe == PIPE_B)
5570 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5571 dpll |= DPLL_VCO_ENABLE;
5572 crtc->config.dpll_hw_state.dpll = dpll;
5573
5574 dpll_md = (crtc->config.pixel_multiplier - 1)
5575 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5576 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5577 }
5578
5579 static void vlv_prepare_pll(struct intel_crtc *crtc)
5580 {
5581 struct drm_device *dev = crtc->base.dev;
5582 struct drm_i915_private *dev_priv = dev->dev_private;
5583 int pipe = crtc->pipe;
5584 u32 mdiv;
5585 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5586 u32 coreclk, reg_val;
5587
5588 mutex_lock(&dev_priv->dpio_lock);
5589
5590 bestn = crtc->config.dpll.n;
5591 bestm1 = crtc->config.dpll.m1;
5592 bestm2 = crtc->config.dpll.m2;
5593 bestp1 = crtc->config.dpll.p1;
5594 bestp2 = crtc->config.dpll.p2;
5595
5596 /* See eDP HDMI DPIO driver vbios notes doc */
5597
5598 /* PLL B needs special handling */
5599 if (pipe == PIPE_B)
5600 vlv_pllb_recal_opamp(dev_priv, pipe);
5601
5602 /* Set up Tx target for periodic Rcomp update */
5603 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5604
5605 /* Disable target IRef on PLL */
5606 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5607 reg_val &= 0x00ffffff;
5608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5609
5610 /* Disable fast lock */
5611 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5612
5613 /* Set idtafcrecal before PLL is enabled */
5614 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5615 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5616 mdiv |= ((bestn << DPIO_N_SHIFT));
5617 mdiv |= (1 << DPIO_K_SHIFT);
5618
5619 /*
5620 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5621 * but we don't support that).
5622 * Note: don't use the DAC post divider as it seems unstable.
5623 */
5624 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5625 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5626
5627 mdiv |= DPIO_ENABLE_CALIBRATION;
5628 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5629
5630 /* Set HBR and RBR LPF coefficients */
5631 if (crtc->config.port_clock == 162000 ||
5632 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5633 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5634 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5635 0x009f0003);
5636 else
5637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5638 0x00d0000f);
5639
5640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5641 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5642 /* Use SSC source */
5643 if (pipe == PIPE_A)
5644 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5645 0x0df40000);
5646 else
5647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5648 0x0df70000);
5649 } else { /* HDMI or VGA */
5650 /* Use bend source */
5651 if (pipe == PIPE_A)
5652 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5653 0x0df70000);
5654 else
5655 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5656 0x0df40000);
5657 }
5658
5659 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5660 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5661 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5662 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5663 coreclk |= 0x01000000;
5664 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5665
5666 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5667 mutex_unlock(&dev_priv->dpio_lock);
5668 }
5669
5670 static void chv_update_pll(struct intel_crtc *crtc)
5671 {
5672 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5673 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5674 DPLL_VCO_ENABLE;
5675 if (crtc->pipe != PIPE_A)
5676 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5677
5678 crtc->config.dpll_hw_state.dpll_md =
5679 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5680 }
5681
5682 static void chv_prepare_pll(struct intel_crtc *crtc)
5683 {
5684 struct drm_device *dev = crtc->base.dev;
5685 struct drm_i915_private *dev_priv = dev->dev_private;
5686 int pipe = crtc->pipe;
5687 int dpll_reg = DPLL(crtc->pipe);
5688 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5689 u32 loopfilter, intcoeff;
5690 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5691 int refclk;
5692
5693 bestn = crtc->config.dpll.n;
5694 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5695 bestm1 = crtc->config.dpll.m1;
5696 bestm2 = crtc->config.dpll.m2 >> 22;
5697 bestp1 = crtc->config.dpll.p1;
5698 bestp2 = crtc->config.dpll.p2;
5699
5700 /*
5701 * Enable Refclk and SSC
5702 */
5703 I915_WRITE(dpll_reg,
5704 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5705
5706 mutex_lock(&dev_priv->dpio_lock);
5707
5708 /* p1 and p2 divider */
5709 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5710 5 << DPIO_CHV_S1_DIV_SHIFT |
5711 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5712 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5713 1 << DPIO_CHV_K_DIV_SHIFT);
5714
5715 /* Feedback post-divider - m2 */
5716 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5717
5718 /* Feedback refclk divider - n and m1 */
5719 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5720 DPIO_CHV_M1_DIV_BY_2 |
5721 1 << DPIO_CHV_N_DIV_SHIFT);
5722
5723 /* M2 fraction division */
5724 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5725
5726 /* M2 fraction division enable */
5727 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5728 DPIO_CHV_FRAC_DIV_EN |
5729 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5730
5731 /* Loop filter */
5732 refclk = i9xx_get_refclk(&crtc->base, 0);
5733 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5734 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5735 if (refclk == 100000)
5736 intcoeff = 11;
5737 else if (refclk == 38400)
5738 intcoeff = 10;
5739 else
5740 intcoeff = 9;
5741 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5742 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5743
5744 /* AFC Recal */
5745 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5746 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5747 DPIO_AFC_RECAL);
5748
5749 mutex_unlock(&dev_priv->dpio_lock);
5750 }
5751
5752 static void i9xx_update_pll(struct intel_crtc *crtc,
5753 intel_clock_t *reduced_clock,
5754 int num_connectors)
5755 {
5756 struct drm_device *dev = crtc->base.dev;
5757 struct drm_i915_private *dev_priv = dev->dev_private;
5758 u32 dpll;
5759 bool is_sdvo;
5760 struct dpll *clock = &crtc->config.dpll;
5761
5762 i9xx_update_pll_dividers(crtc, reduced_clock);
5763
5764 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5765 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5766
5767 dpll = DPLL_VGA_MODE_DIS;
5768
5769 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5770 dpll |= DPLLB_MODE_LVDS;
5771 else
5772 dpll |= DPLLB_MODE_DAC_SERIAL;
5773
5774 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5775 dpll |= (crtc->config.pixel_multiplier - 1)
5776 << SDVO_MULTIPLIER_SHIFT_HIRES;
5777 }
5778
5779 if (is_sdvo)
5780 dpll |= DPLL_SDVO_HIGH_SPEED;
5781
5782 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5783 dpll |= DPLL_SDVO_HIGH_SPEED;
5784
5785 /* compute bitmask from p1 value */
5786 if (IS_PINEVIEW(dev))
5787 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5788 else {
5789 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5790 if (IS_G4X(dev) && reduced_clock)
5791 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5792 }
5793 switch (clock->p2) {
5794 case 5:
5795 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5796 break;
5797 case 7:
5798 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5799 break;
5800 case 10:
5801 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5802 break;
5803 case 14:
5804 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5805 break;
5806 }
5807 if (INTEL_INFO(dev)->gen >= 4)
5808 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5809
5810 if (crtc->config.sdvo_tv_clock)
5811 dpll |= PLL_REF_INPUT_TVCLKINBC;
5812 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5813 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5814 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5815 else
5816 dpll |= PLL_REF_INPUT_DREFCLK;
5817
5818 dpll |= DPLL_VCO_ENABLE;
5819 crtc->config.dpll_hw_state.dpll = dpll;
5820
5821 if (INTEL_INFO(dev)->gen >= 4) {
5822 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5823 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5824 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5825 }
5826 }
5827
5828 static void i8xx_update_pll(struct intel_crtc *crtc,
5829 intel_clock_t *reduced_clock,
5830 int num_connectors)
5831 {
5832 struct drm_device *dev = crtc->base.dev;
5833 struct drm_i915_private *dev_priv = dev->dev_private;
5834 u32 dpll;
5835 struct dpll *clock = &crtc->config.dpll;
5836
5837 i9xx_update_pll_dividers(crtc, reduced_clock);
5838
5839 dpll = DPLL_VGA_MODE_DIS;
5840
5841 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5843 } else {
5844 if (clock->p1 == 2)
5845 dpll |= PLL_P1_DIVIDE_BY_TWO;
5846 else
5847 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5848 if (clock->p2 == 4)
5849 dpll |= PLL_P2_DIVIDE_BY_4;
5850 }
5851
5852 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5853 dpll |= DPLL_DVO_2X_MODE;
5854
5855 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5856 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5857 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5858 else
5859 dpll |= PLL_REF_INPUT_DREFCLK;
5860
5861 dpll |= DPLL_VCO_ENABLE;
5862 crtc->config.dpll_hw_state.dpll = dpll;
5863 }
5864
5865 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5866 {
5867 struct drm_device *dev = intel_crtc->base.dev;
5868 struct drm_i915_private *dev_priv = dev->dev_private;
5869 enum pipe pipe = intel_crtc->pipe;
5870 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5871 struct drm_display_mode *adjusted_mode =
5872 &intel_crtc->config.adjusted_mode;
5873 uint32_t crtc_vtotal, crtc_vblank_end;
5874 int vsyncshift = 0;
5875
5876 /* We need to be careful not to changed the adjusted mode, for otherwise
5877 * the hw state checker will get angry at the mismatch. */
5878 crtc_vtotal = adjusted_mode->crtc_vtotal;
5879 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5880
5881 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5882 /* the chip adds 2 halflines automatically */
5883 crtc_vtotal -= 1;
5884 crtc_vblank_end -= 1;
5885
5886 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5887 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5888 else
5889 vsyncshift = adjusted_mode->crtc_hsync_start -
5890 adjusted_mode->crtc_htotal / 2;
5891 if (vsyncshift < 0)
5892 vsyncshift += adjusted_mode->crtc_htotal;
5893 }
5894
5895 if (INTEL_INFO(dev)->gen > 3)
5896 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5897
5898 I915_WRITE(HTOTAL(cpu_transcoder),
5899 (adjusted_mode->crtc_hdisplay - 1) |
5900 ((adjusted_mode->crtc_htotal - 1) << 16));
5901 I915_WRITE(HBLANK(cpu_transcoder),
5902 (adjusted_mode->crtc_hblank_start - 1) |
5903 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5904 I915_WRITE(HSYNC(cpu_transcoder),
5905 (adjusted_mode->crtc_hsync_start - 1) |
5906 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5907
5908 I915_WRITE(VTOTAL(cpu_transcoder),
5909 (adjusted_mode->crtc_vdisplay - 1) |
5910 ((crtc_vtotal - 1) << 16));
5911 I915_WRITE(VBLANK(cpu_transcoder),
5912 (adjusted_mode->crtc_vblank_start - 1) |
5913 ((crtc_vblank_end - 1) << 16));
5914 I915_WRITE(VSYNC(cpu_transcoder),
5915 (adjusted_mode->crtc_vsync_start - 1) |
5916 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5917
5918 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5919 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5920 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5921 * bits. */
5922 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5923 (pipe == PIPE_B || pipe == PIPE_C))
5924 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5925
5926 /* pipesrc controls the size that is scaled from, which should
5927 * always be the user's requested size.
5928 */
5929 I915_WRITE(PIPESRC(pipe),
5930 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5931 (intel_crtc->config.pipe_src_h - 1));
5932 }
5933
5934 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5935 struct intel_crtc_config *pipe_config)
5936 {
5937 struct drm_device *dev = crtc->base.dev;
5938 struct drm_i915_private *dev_priv = dev->dev_private;
5939 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5940 uint32_t tmp;
5941
5942 tmp = I915_READ(HTOTAL(cpu_transcoder));
5943 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5944 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5945 tmp = I915_READ(HBLANK(cpu_transcoder));
5946 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5947 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5948 tmp = I915_READ(HSYNC(cpu_transcoder));
5949 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5950 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5951
5952 tmp = I915_READ(VTOTAL(cpu_transcoder));
5953 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5954 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5955 tmp = I915_READ(VBLANK(cpu_transcoder));
5956 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5957 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5958 tmp = I915_READ(VSYNC(cpu_transcoder));
5959 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5960 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5961
5962 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5963 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5964 pipe_config->adjusted_mode.crtc_vtotal += 1;
5965 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5966 }
5967
5968 tmp = I915_READ(PIPESRC(crtc->pipe));
5969 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5970 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5971
5972 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5973 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5974 }
5975
5976 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5977 struct intel_crtc_config *pipe_config)
5978 {
5979 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5980 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5981 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5982 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5983
5984 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5985 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5986 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5987 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5988
5989 mode->flags = pipe_config->adjusted_mode.flags;
5990
5991 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5992 mode->flags |= pipe_config->adjusted_mode.flags;
5993 }
5994
5995 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5996 {
5997 struct drm_device *dev = intel_crtc->base.dev;
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999 uint32_t pipeconf;
6000
6001 pipeconf = 0;
6002
6003 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6004 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6005 pipeconf |= PIPECONF_ENABLE;
6006
6007 if (intel_crtc->config.double_wide)
6008 pipeconf |= PIPECONF_DOUBLE_WIDE;
6009
6010 /* only g4x and later have fancy bpc/dither controls */
6011 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6012 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6013 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6014 pipeconf |= PIPECONF_DITHER_EN |
6015 PIPECONF_DITHER_TYPE_SP;
6016
6017 switch (intel_crtc->config.pipe_bpp) {
6018 case 18:
6019 pipeconf |= PIPECONF_6BPC;
6020 break;
6021 case 24:
6022 pipeconf |= PIPECONF_8BPC;
6023 break;
6024 case 30:
6025 pipeconf |= PIPECONF_10BPC;
6026 break;
6027 default:
6028 /* Case prevented by intel_choose_pipe_bpp_dither. */
6029 BUG();
6030 }
6031 }
6032
6033 if (HAS_PIPE_CXSR(dev)) {
6034 if (intel_crtc->lowfreq_avail) {
6035 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6036 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6037 } else {
6038 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6039 }
6040 }
6041
6042 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6043 if (INTEL_INFO(dev)->gen < 4 ||
6044 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6045 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6046 else
6047 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6048 } else
6049 pipeconf |= PIPECONF_PROGRESSIVE;
6050
6051 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6052 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6053
6054 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6055 POSTING_READ(PIPECONF(intel_crtc->pipe));
6056 }
6057
6058 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6059 int x, int y,
6060 struct drm_framebuffer *fb)
6061 {
6062 struct drm_device *dev = crtc->dev;
6063 struct drm_i915_private *dev_priv = dev->dev_private;
6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065 int refclk, num_connectors = 0;
6066 intel_clock_t clock, reduced_clock;
6067 bool ok, has_reduced_clock = false;
6068 bool is_lvds = false, is_dsi = false;
6069 struct intel_encoder *encoder;
6070 const intel_limit_t *limit;
6071
6072 for_each_encoder_on_crtc(dev, crtc, encoder) {
6073 switch (encoder->type) {
6074 case INTEL_OUTPUT_LVDS:
6075 is_lvds = true;
6076 break;
6077 case INTEL_OUTPUT_DSI:
6078 is_dsi = true;
6079 break;
6080 }
6081
6082 num_connectors++;
6083 }
6084
6085 if (is_dsi)
6086 return 0;
6087
6088 if (!intel_crtc->config.clock_set) {
6089 refclk = i9xx_get_refclk(crtc, num_connectors);
6090
6091 /*
6092 * Returns a set of divisors for the desired target clock with
6093 * the given refclk, or FALSE. The returned values represent
6094 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6095 * 2) / p1 / p2.
6096 */
6097 limit = intel_limit(crtc, refclk);
6098 ok = dev_priv->display.find_dpll(limit, crtc,
6099 intel_crtc->config.port_clock,
6100 refclk, NULL, &clock);
6101 if (!ok) {
6102 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6103 return -EINVAL;
6104 }
6105
6106 if (is_lvds && dev_priv->lvds_downclock_avail) {
6107 /*
6108 * Ensure we match the reduced clock's P to the target
6109 * clock. If the clocks don't match, we can't switch
6110 * the display clock by using the FP0/FP1. In such case
6111 * we will disable the LVDS downclock feature.
6112 */
6113 has_reduced_clock =
6114 dev_priv->display.find_dpll(limit, crtc,
6115 dev_priv->lvds_downclock,
6116 refclk, &clock,
6117 &reduced_clock);
6118 }
6119 /* Compat-code for transition, will disappear. */
6120 intel_crtc->config.dpll.n = clock.n;
6121 intel_crtc->config.dpll.m1 = clock.m1;
6122 intel_crtc->config.dpll.m2 = clock.m2;
6123 intel_crtc->config.dpll.p1 = clock.p1;
6124 intel_crtc->config.dpll.p2 = clock.p2;
6125 }
6126
6127 if (IS_GEN2(dev)) {
6128 i8xx_update_pll(intel_crtc,
6129 has_reduced_clock ? &reduced_clock : NULL,
6130 num_connectors);
6131 } else if (IS_CHERRYVIEW(dev)) {
6132 chv_update_pll(intel_crtc);
6133 } else if (IS_VALLEYVIEW(dev)) {
6134 vlv_update_pll(intel_crtc);
6135 } else {
6136 i9xx_update_pll(intel_crtc,
6137 has_reduced_clock ? &reduced_clock : NULL,
6138 num_connectors);
6139 }
6140
6141 return 0;
6142 }
6143
6144 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6145 struct intel_crtc_config *pipe_config)
6146 {
6147 struct drm_device *dev = crtc->base.dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 uint32_t tmp;
6150
6151 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6152 return;
6153
6154 tmp = I915_READ(PFIT_CONTROL);
6155 if (!(tmp & PFIT_ENABLE))
6156 return;
6157
6158 /* Check whether the pfit is attached to our pipe. */
6159 if (INTEL_INFO(dev)->gen < 4) {
6160 if (crtc->pipe != PIPE_B)
6161 return;
6162 } else {
6163 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6164 return;
6165 }
6166
6167 pipe_config->gmch_pfit.control = tmp;
6168 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6169 if (INTEL_INFO(dev)->gen < 5)
6170 pipe_config->gmch_pfit.lvds_border_bits =
6171 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6172 }
6173
6174 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6175 struct intel_crtc_config *pipe_config)
6176 {
6177 struct drm_device *dev = crtc->base.dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 int pipe = pipe_config->cpu_transcoder;
6180 intel_clock_t clock;
6181 u32 mdiv;
6182 int refclk = 100000;
6183
6184 /* In case of MIPI DPLL will not even be used */
6185 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6186 return;
6187
6188 mutex_lock(&dev_priv->dpio_lock);
6189 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6190 mutex_unlock(&dev_priv->dpio_lock);
6191
6192 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6193 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6194 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6195 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6196 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6197
6198 vlv_clock(refclk, &clock);
6199
6200 /* clock.dot is the fast clock */
6201 pipe_config->port_clock = clock.dot / 5;
6202 }
6203
6204 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6205 struct intel_plane_config *plane_config)
6206 {
6207 struct drm_device *dev = crtc->base.dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 u32 val, base, offset;
6210 int pipe = crtc->pipe, plane = crtc->plane;
6211 int fourcc, pixel_format;
6212 int aligned_height;
6213
6214 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6215 if (!crtc->base.primary->fb) {
6216 DRM_DEBUG_KMS("failed to alloc fb\n");
6217 return;
6218 }
6219
6220 val = I915_READ(DSPCNTR(plane));
6221
6222 if (INTEL_INFO(dev)->gen >= 4)
6223 if (val & DISPPLANE_TILED)
6224 plane_config->tiled = true;
6225
6226 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6227 fourcc = intel_format_to_fourcc(pixel_format);
6228 crtc->base.primary->fb->pixel_format = fourcc;
6229 crtc->base.primary->fb->bits_per_pixel =
6230 drm_format_plane_cpp(fourcc, 0) * 8;
6231
6232 if (INTEL_INFO(dev)->gen >= 4) {
6233 if (plane_config->tiled)
6234 offset = I915_READ(DSPTILEOFF(plane));
6235 else
6236 offset = I915_READ(DSPLINOFF(plane));
6237 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6238 } else {
6239 base = I915_READ(DSPADDR(plane));
6240 }
6241 plane_config->base = base;
6242
6243 val = I915_READ(PIPESRC(pipe));
6244 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6245 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6246
6247 val = I915_READ(DSPSTRIDE(pipe));
6248 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6249
6250 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6251 plane_config->tiled);
6252
6253 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6254 aligned_height);
6255
6256 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6257 pipe, plane, crtc->base.primary->fb->width,
6258 crtc->base.primary->fb->height,
6259 crtc->base.primary->fb->bits_per_pixel, base,
6260 crtc->base.primary->fb->pitches[0],
6261 plane_config->size);
6262
6263 }
6264
6265 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6266 struct intel_crtc_config *pipe_config)
6267 {
6268 struct drm_device *dev = crtc->base.dev;
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270 int pipe = pipe_config->cpu_transcoder;
6271 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6272 intel_clock_t clock;
6273 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6274 int refclk = 100000;
6275
6276 mutex_lock(&dev_priv->dpio_lock);
6277 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6278 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6279 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6280 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6281 mutex_unlock(&dev_priv->dpio_lock);
6282
6283 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6284 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6285 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6286 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6287 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6288
6289 chv_clock(refclk, &clock);
6290
6291 /* clock.dot is the fast clock */
6292 pipe_config->port_clock = clock.dot / 5;
6293 }
6294
6295 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6296 struct intel_crtc_config *pipe_config)
6297 {
6298 struct drm_device *dev = crtc->base.dev;
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300 uint32_t tmp;
6301
6302 if (!intel_display_power_enabled(dev_priv,
6303 POWER_DOMAIN_PIPE(crtc->pipe)))
6304 return false;
6305
6306 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6307 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6308
6309 tmp = I915_READ(PIPECONF(crtc->pipe));
6310 if (!(tmp & PIPECONF_ENABLE))
6311 return false;
6312
6313 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6314 switch (tmp & PIPECONF_BPC_MASK) {
6315 case PIPECONF_6BPC:
6316 pipe_config->pipe_bpp = 18;
6317 break;
6318 case PIPECONF_8BPC:
6319 pipe_config->pipe_bpp = 24;
6320 break;
6321 case PIPECONF_10BPC:
6322 pipe_config->pipe_bpp = 30;
6323 break;
6324 default:
6325 break;
6326 }
6327 }
6328
6329 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6330 pipe_config->limited_color_range = true;
6331
6332 if (INTEL_INFO(dev)->gen < 4)
6333 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6334
6335 intel_get_pipe_timings(crtc, pipe_config);
6336
6337 i9xx_get_pfit_config(crtc, pipe_config);
6338
6339 if (INTEL_INFO(dev)->gen >= 4) {
6340 tmp = I915_READ(DPLL_MD(crtc->pipe));
6341 pipe_config->pixel_multiplier =
6342 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6343 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6344 pipe_config->dpll_hw_state.dpll_md = tmp;
6345 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6346 tmp = I915_READ(DPLL(crtc->pipe));
6347 pipe_config->pixel_multiplier =
6348 ((tmp & SDVO_MULTIPLIER_MASK)
6349 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6350 } else {
6351 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6352 * port and will be fixed up in the encoder->get_config
6353 * function. */
6354 pipe_config->pixel_multiplier = 1;
6355 }
6356 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6357 if (!IS_VALLEYVIEW(dev)) {
6358 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6359 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6360 } else {
6361 /* Mask out read-only status bits. */
6362 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6363 DPLL_PORTC_READY_MASK |
6364 DPLL_PORTB_READY_MASK);
6365 }
6366
6367 if (IS_CHERRYVIEW(dev))
6368 chv_crtc_clock_get(crtc, pipe_config);
6369 else if (IS_VALLEYVIEW(dev))
6370 vlv_crtc_clock_get(crtc, pipe_config);
6371 else
6372 i9xx_crtc_clock_get(crtc, pipe_config);
6373
6374 return true;
6375 }
6376
6377 static void ironlake_init_pch_refclk(struct drm_device *dev)
6378 {
6379 struct drm_i915_private *dev_priv = dev->dev_private;
6380 struct intel_encoder *encoder;
6381 u32 val, final;
6382 bool has_lvds = false;
6383 bool has_cpu_edp = false;
6384 bool has_panel = false;
6385 bool has_ck505 = false;
6386 bool can_ssc = false;
6387
6388 /* We need to take the global config into account */
6389 for_each_intel_encoder(dev, encoder) {
6390 switch (encoder->type) {
6391 case INTEL_OUTPUT_LVDS:
6392 has_panel = true;
6393 has_lvds = true;
6394 break;
6395 case INTEL_OUTPUT_EDP:
6396 has_panel = true;
6397 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6398 has_cpu_edp = true;
6399 break;
6400 }
6401 }
6402
6403 if (HAS_PCH_IBX(dev)) {
6404 has_ck505 = dev_priv->vbt.display_clock_mode;
6405 can_ssc = has_ck505;
6406 } else {
6407 has_ck505 = false;
6408 can_ssc = true;
6409 }
6410
6411 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6412 has_panel, has_lvds, has_ck505);
6413
6414 /* Ironlake: try to setup display ref clock before DPLL
6415 * enabling. This is only under driver's control after
6416 * PCH B stepping, previous chipset stepping should be
6417 * ignoring this setting.
6418 */
6419 val = I915_READ(PCH_DREF_CONTROL);
6420
6421 /* As we must carefully and slowly disable/enable each source in turn,
6422 * compute the final state we want first and check if we need to
6423 * make any changes at all.
6424 */
6425 final = val;
6426 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6427 if (has_ck505)
6428 final |= DREF_NONSPREAD_CK505_ENABLE;
6429 else
6430 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6431
6432 final &= ~DREF_SSC_SOURCE_MASK;
6433 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6434 final &= ~DREF_SSC1_ENABLE;
6435
6436 if (has_panel) {
6437 final |= DREF_SSC_SOURCE_ENABLE;
6438
6439 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6440 final |= DREF_SSC1_ENABLE;
6441
6442 if (has_cpu_edp) {
6443 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6444 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6445 else
6446 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6447 } else
6448 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6449 } else {
6450 final |= DREF_SSC_SOURCE_DISABLE;
6451 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6452 }
6453
6454 if (final == val)
6455 return;
6456
6457 /* Always enable nonspread source */
6458 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6459
6460 if (has_ck505)
6461 val |= DREF_NONSPREAD_CK505_ENABLE;
6462 else
6463 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6464
6465 if (has_panel) {
6466 val &= ~DREF_SSC_SOURCE_MASK;
6467 val |= DREF_SSC_SOURCE_ENABLE;
6468
6469 /* SSC must be turned on before enabling the CPU output */
6470 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6471 DRM_DEBUG_KMS("Using SSC on panel\n");
6472 val |= DREF_SSC1_ENABLE;
6473 } else
6474 val &= ~DREF_SSC1_ENABLE;
6475
6476 /* Get SSC going before enabling the outputs */
6477 I915_WRITE(PCH_DREF_CONTROL, val);
6478 POSTING_READ(PCH_DREF_CONTROL);
6479 udelay(200);
6480
6481 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6482
6483 /* Enable CPU source on CPU attached eDP */
6484 if (has_cpu_edp) {
6485 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6486 DRM_DEBUG_KMS("Using SSC on eDP\n");
6487 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6488 } else
6489 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6490 } else
6491 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6492
6493 I915_WRITE(PCH_DREF_CONTROL, val);
6494 POSTING_READ(PCH_DREF_CONTROL);
6495 udelay(200);
6496 } else {
6497 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6498
6499 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6500
6501 /* Turn off CPU output */
6502 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6503
6504 I915_WRITE(PCH_DREF_CONTROL, val);
6505 POSTING_READ(PCH_DREF_CONTROL);
6506 udelay(200);
6507
6508 /* Turn off the SSC source */
6509 val &= ~DREF_SSC_SOURCE_MASK;
6510 val |= DREF_SSC_SOURCE_DISABLE;
6511
6512 /* Turn off SSC1 */
6513 val &= ~DREF_SSC1_ENABLE;
6514
6515 I915_WRITE(PCH_DREF_CONTROL, val);
6516 POSTING_READ(PCH_DREF_CONTROL);
6517 udelay(200);
6518 }
6519
6520 BUG_ON(val != final);
6521 }
6522
6523 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6524 {
6525 uint32_t tmp;
6526
6527 tmp = I915_READ(SOUTH_CHICKEN2);
6528 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6529 I915_WRITE(SOUTH_CHICKEN2, tmp);
6530
6531 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6532 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6533 DRM_ERROR("FDI mPHY reset assert timeout\n");
6534
6535 tmp = I915_READ(SOUTH_CHICKEN2);
6536 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6537 I915_WRITE(SOUTH_CHICKEN2, tmp);
6538
6539 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6540 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6541 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6542 }
6543
6544 /* WaMPhyProgramming:hsw */
6545 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6546 {
6547 uint32_t tmp;
6548
6549 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6550 tmp &= ~(0xFF << 24);
6551 tmp |= (0x12 << 24);
6552 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6553
6554 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6555 tmp |= (1 << 11);
6556 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6557
6558 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6559 tmp |= (1 << 11);
6560 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6561
6562 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6563 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6564 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6565
6566 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6567 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6568 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6569
6570 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6571 tmp &= ~(7 << 13);
6572 tmp |= (5 << 13);
6573 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6574
6575 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6576 tmp &= ~(7 << 13);
6577 tmp |= (5 << 13);
6578 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6579
6580 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6581 tmp &= ~0xFF;
6582 tmp |= 0x1C;
6583 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6584
6585 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6586 tmp &= ~0xFF;
6587 tmp |= 0x1C;
6588 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6589
6590 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6591 tmp &= ~(0xFF << 16);
6592 tmp |= (0x1C << 16);
6593 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6594
6595 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6596 tmp &= ~(0xFF << 16);
6597 tmp |= (0x1C << 16);
6598 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6599
6600 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6601 tmp |= (1 << 27);
6602 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6603
6604 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6605 tmp |= (1 << 27);
6606 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6607
6608 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6609 tmp &= ~(0xF << 28);
6610 tmp |= (4 << 28);
6611 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6612
6613 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6614 tmp &= ~(0xF << 28);
6615 tmp |= (4 << 28);
6616 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6617 }
6618
6619 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6620 * Programming" based on the parameters passed:
6621 * - Sequence to enable CLKOUT_DP
6622 * - Sequence to enable CLKOUT_DP without spread
6623 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6624 */
6625 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6626 bool with_fdi)
6627 {
6628 struct drm_i915_private *dev_priv = dev->dev_private;
6629 uint32_t reg, tmp;
6630
6631 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6632 with_spread = true;
6633 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6634 with_fdi, "LP PCH doesn't have FDI\n"))
6635 with_fdi = false;
6636
6637 mutex_lock(&dev_priv->dpio_lock);
6638
6639 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6640 tmp &= ~SBI_SSCCTL_DISABLE;
6641 tmp |= SBI_SSCCTL_PATHALT;
6642 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6643
6644 udelay(24);
6645
6646 if (with_spread) {
6647 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6648 tmp &= ~SBI_SSCCTL_PATHALT;
6649 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6650
6651 if (with_fdi) {
6652 lpt_reset_fdi_mphy(dev_priv);
6653 lpt_program_fdi_mphy(dev_priv);
6654 }
6655 }
6656
6657 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6658 SBI_GEN0 : SBI_DBUFF0;
6659 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6660 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6661 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6662
6663 mutex_unlock(&dev_priv->dpio_lock);
6664 }
6665
6666 /* Sequence to disable CLKOUT_DP */
6667 static void lpt_disable_clkout_dp(struct drm_device *dev)
6668 {
6669 struct drm_i915_private *dev_priv = dev->dev_private;
6670 uint32_t reg, tmp;
6671
6672 mutex_lock(&dev_priv->dpio_lock);
6673
6674 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6675 SBI_GEN0 : SBI_DBUFF0;
6676 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6677 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6678 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6679
6680 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6681 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6682 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6683 tmp |= SBI_SSCCTL_PATHALT;
6684 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6685 udelay(32);
6686 }
6687 tmp |= SBI_SSCCTL_DISABLE;
6688 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6689 }
6690
6691 mutex_unlock(&dev_priv->dpio_lock);
6692 }
6693
6694 static void lpt_init_pch_refclk(struct drm_device *dev)
6695 {
6696 struct intel_encoder *encoder;
6697 bool has_vga = false;
6698
6699 for_each_intel_encoder(dev, encoder) {
6700 switch (encoder->type) {
6701 case INTEL_OUTPUT_ANALOG:
6702 has_vga = true;
6703 break;
6704 }
6705 }
6706
6707 if (has_vga)
6708 lpt_enable_clkout_dp(dev, true, true);
6709 else
6710 lpt_disable_clkout_dp(dev);
6711 }
6712
6713 /*
6714 * Initialize reference clocks when the driver loads
6715 */
6716 void intel_init_pch_refclk(struct drm_device *dev)
6717 {
6718 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6719 ironlake_init_pch_refclk(dev);
6720 else if (HAS_PCH_LPT(dev))
6721 lpt_init_pch_refclk(dev);
6722 }
6723
6724 static int ironlake_get_refclk(struct drm_crtc *crtc)
6725 {
6726 struct drm_device *dev = crtc->dev;
6727 struct drm_i915_private *dev_priv = dev->dev_private;
6728 struct intel_encoder *encoder;
6729 int num_connectors = 0;
6730 bool is_lvds = false;
6731
6732 for_each_encoder_on_crtc(dev, crtc, encoder) {
6733 switch (encoder->type) {
6734 case INTEL_OUTPUT_LVDS:
6735 is_lvds = true;
6736 break;
6737 }
6738 num_connectors++;
6739 }
6740
6741 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6742 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6743 dev_priv->vbt.lvds_ssc_freq);
6744 return dev_priv->vbt.lvds_ssc_freq;
6745 }
6746
6747 return 120000;
6748 }
6749
6750 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6751 {
6752 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754 int pipe = intel_crtc->pipe;
6755 uint32_t val;
6756
6757 val = 0;
6758
6759 switch (intel_crtc->config.pipe_bpp) {
6760 case 18:
6761 val |= PIPECONF_6BPC;
6762 break;
6763 case 24:
6764 val |= PIPECONF_8BPC;
6765 break;
6766 case 30:
6767 val |= PIPECONF_10BPC;
6768 break;
6769 case 36:
6770 val |= PIPECONF_12BPC;
6771 break;
6772 default:
6773 /* Case prevented by intel_choose_pipe_bpp_dither. */
6774 BUG();
6775 }
6776
6777 if (intel_crtc->config.dither)
6778 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6779
6780 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6781 val |= PIPECONF_INTERLACED_ILK;
6782 else
6783 val |= PIPECONF_PROGRESSIVE;
6784
6785 if (intel_crtc->config.limited_color_range)
6786 val |= PIPECONF_COLOR_RANGE_SELECT;
6787
6788 I915_WRITE(PIPECONF(pipe), val);
6789 POSTING_READ(PIPECONF(pipe));
6790 }
6791
6792 /*
6793 * Set up the pipe CSC unit.
6794 *
6795 * Currently only full range RGB to limited range RGB conversion
6796 * is supported, but eventually this should handle various
6797 * RGB<->YCbCr scenarios as well.
6798 */
6799 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6800 {
6801 struct drm_device *dev = crtc->dev;
6802 struct drm_i915_private *dev_priv = dev->dev_private;
6803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6804 int pipe = intel_crtc->pipe;
6805 uint16_t coeff = 0x7800; /* 1.0 */
6806
6807 /*
6808 * TODO: Check what kind of values actually come out of the pipe
6809 * with these coeff/postoff values and adjust to get the best
6810 * accuracy. Perhaps we even need to take the bpc value into
6811 * consideration.
6812 */
6813
6814 if (intel_crtc->config.limited_color_range)
6815 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6816
6817 /*
6818 * GY/GU and RY/RU should be the other way around according
6819 * to BSpec, but reality doesn't agree. Just set them up in
6820 * a way that results in the correct picture.
6821 */
6822 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6823 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6824
6825 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6826 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6827
6828 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6829 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6830
6831 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6832 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6833 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6834
6835 if (INTEL_INFO(dev)->gen > 6) {
6836 uint16_t postoff = 0;
6837
6838 if (intel_crtc->config.limited_color_range)
6839 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6840
6841 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6842 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6843 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6844
6845 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6846 } else {
6847 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6848
6849 if (intel_crtc->config.limited_color_range)
6850 mode |= CSC_BLACK_SCREEN_OFFSET;
6851
6852 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6853 }
6854 }
6855
6856 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6857 {
6858 struct drm_device *dev = crtc->dev;
6859 struct drm_i915_private *dev_priv = dev->dev_private;
6860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6861 enum pipe pipe = intel_crtc->pipe;
6862 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6863 uint32_t val;
6864
6865 val = 0;
6866
6867 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6868 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6869
6870 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6871 val |= PIPECONF_INTERLACED_ILK;
6872 else
6873 val |= PIPECONF_PROGRESSIVE;
6874
6875 I915_WRITE(PIPECONF(cpu_transcoder), val);
6876 POSTING_READ(PIPECONF(cpu_transcoder));
6877
6878 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6879 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6880
6881 if (IS_BROADWELL(dev)) {
6882 val = 0;
6883
6884 switch (intel_crtc->config.pipe_bpp) {
6885 case 18:
6886 val |= PIPEMISC_DITHER_6_BPC;
6887 break;
6888 case 24:
6889 val |= PIPEMISC_DITHER_8_BPC;
6890 break;
6891 case 30:
6892 val |= PIPEMISC_DITHER_10_BPC;
6893 break;
6894 case 36:
6895 val |= PIPEMISC_DITHER_12_BPC;
6896 break;
6897 default:
6898 /* Case prevented by pipe_config_set_bpp. */
6899 BUG();
6900 }
6901
6902 if (intel_crtc->config.dither)
6903 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6904
6905 I915_WRITE(PIPEMISC(pipe), val);
6906 }
6907 }
6908
6909 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6910 intel_clock_t *clock,
6911 bool *has_reduced_clock,
6912 intel_clock_t *reduced_clock)
6913 {
6914 struct drm_device *dev = crtc->dev;
6915 struct drm_i915_private *dev_priv = dev->dev_private;
6916 struct intel_encoder *intel_encoder;
6917 int refclk;
6918 const intel_limit_t *limit;
6919 bool ret, is_lvds = false;
6920
6921 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6922 switch (intel_encoder->type) {
6923 case INTEL_OUTPUT_LVDS:
6924 is_lvds = true;
6925 break;
6926 }
6927 }
6928
6929 refclk = ironlake_get_refclk(crtc);
6930
6931 /*
6932 * Returns a set of divisors for the desired target clock with the given
6933 * refclk, or FALSE. The returned values represent the clock equation:
6934 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6935 */
6936 limit = intel_limit(crtc, refclk);
6937 ret = dev_priv->display.find_dpll(limit, crtc,
6938 to_intel_crtc(crtc)->config.port_clock,
6939 refclk, NULL, clock);
6940 if (!ret)
6941 return false;
6942
6943 if (is_lvds && dev_priv->lvds_downclock_avail) {
6944 /*
6945 * Ensure we match the reduced clock's P to the target clock.
6946 * If the clocks don't match, we can't switch the display clock
6947 * by using the FP0/FP1. In such case we will disable the LVDS
6948 * downclock feature.
6949 */
6950 *has_reduced_clock =
6951 dev_priv->display.find_dpll(limit, crtc,
6952 dev_priv->lvds_downclock,
6953 refclk, clock,
6954 reduced_clock);
6955 }
6956
6957 return true;
6958 }
6959
6960 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6961 {
6962 /*
6963 * Account for spread spectrum to avoid
6964 * oversubscribing the link. Max center spread
6965 * is 2.5%; use 5% for safety's sake.
6966 */
6967 u32 bps = target_clock * bpp * 21 / 20;
6968 return DIV_ROUND_UP(bps, link_bw * 8);
6969 }
6970
6971 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6972 {
6973 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6974 }
6975
6976 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6977 u32 *fp,
6978 intel_clock_t *reduced_clock, u32 *fp2)
6979 {
6980 struct drm_crtc *crtc = &intel_crtc->base;
6981 struct drm_device *dev = crtc->dev;
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983 struct intel_encoder *intel_encoder;
6984 uint32_t dpll;
6985 int factor, num_connectors = 0;
6986 bool is_lvds = false, is_sdvo = false;
6987
6988 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6989 switch (intel_encoder->type) {
6990 case INTEL_OUTPUT_LVDS:
6991 is_lvds = true;
6992 break;
6993 case INTEL_OUTPUT_SDVO:
6994 case INTEL_OUTPUT_HDMI:
6995 is_sdvo = true;
6996 break;
6997 }
6998
6999 num_connectors++;
7000 }
7001
7002 /* Enable autotuning of the PLL clock (if permissible) */
7003 factor = 21;
7004 if (is_lvds) {
7005 if ((intel_panel_use_ssc(dev_priv) &&
7006 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7007 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7008 factor = 25;
7009 } else if (intel_crtc->config.sdvo_tv_clock)
7010 factor = 20;
7011
7012 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7013 *fp |= FP_CB_TUNE;
7014
7015 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7016 *fp2 |= FP_CB_TUNE;
7017
7018 dpll = 0;
7019
7020 if (is_lvds)
7021 dpll |= DPLLB_MODE_LVDS;
7022 else
7023 dpll |= DPLLB_MODE_DAC_SERIAL;
7024
7025 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7026 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7027
7028 if (is_sdvo)
7029 dpll |= DPLL_SDVO_HIGH_SPEED;
7030 if (intel_crtc->config.has_dp_encoder)
7031 dpll |= DPLL_SDVO_HIGH_SPEED;
7032
7033 /* compute bitmask from p1 value */
7034 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7035 /* also FPA1 */
7036 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7037
7038 switch (intel_crtc->config.dpll.p2) {
7039 case 5:
7040 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7041 break;
7042 case 7:
7043 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7044 break;
7045 case 10:
7046 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7047 break;
7048 case 14:
7049 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7050 break;
7051 }
7052
7053 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7054 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7055 else
7056 dpll |= PLL_REF_INPUT_DREFCLK;
7057
7058 return dpll | DPLL_VCO_ENABLE;
7059 }
7060
7061 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7062 int x, int y,
7063 struct drm_framebuffer *fb)
7064 {
7065 struct drm_device *dev = crtc->dev;
7066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7067 int num_connectors = 0;
7068 intel_clock_t clock, reduced_clock;
7069 u32 dpll = 0, fp = 0, fp2 = 0;
7070 bool ok, has_reduced_clock = false;
7071 bool is_lvds = false;
7072 struct intel_encoder *encoder;
7073 struct intel_shared_dpll *pll;
7074
7075 for_each_encoder_on_crtc(dev, crtc, encoder) {
7076 switch (encoder->type) {
7077 case INTEL_OUTPUT_LVDS:
7078 is_lvds = true;
7079 break;
7080 }
7081
7082 num_connectors++;
7083 }
7084
7085 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7086 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7087
7088 ok = ironlake_compute_clocks(crtc, &clock,
7089 &has_reduced_clock, &reduced_clock);
7090 if (!ok && !intel_crtc->config.clock_set) {
7091 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7092 return -EINVAL;
7093 }
7094 /* Compat-code for transition, will disappear. */
7095 if (!intel_crtc->config.clock_set) {
7096 intel_crtc->config.dpll.n = clock.n;
7097 intel_crtc->config.dpll.m1 = clock.m1;
7098 intel_crtc->config.dpll.m2 = clock.m2;
7099 intel_crtc->config.dpll.p1 = clock.p1;
7100 intel_crtc->config.dpll.p2 = clock.p2;
7101 }
7102
7103 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7104 if (intel_crtc->config.has_pch_encoder) {
7105 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7106 if (has_reduced_clock)
7107 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7108
7109 dpll = ironlake_compute_dpll(intel_crtc,
7110 &fp, &reduced_clock,
7111 has_reduced_clock ? &fp2 : NULL);
7112
7113 intel_crtc->config.dpll_hw_state.dpll = dpll;
7114 intel_crtc->config.dpll_hw_state.fp0 = fp;
7115 if (has_reduced_clock)
7116 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7117 else
7118 intel_crtc->config.dpll_hw_state.fp1 = fp;
7119
7120 pll = intel_get_shared_dpll(intel_crtc);
7121 if (pll == NULL) {
7122 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7123 pipe_name(intel_crtc->pipe));
7124 return -EINVAL;
7125 }
7126 } else
7127 intel_put_shared_dpll(intel_crtc);
7128
7129 if (is_lvds && has_reduced_clock && i915.powersave)
7130 intel_crtc->lowfreq_avail = true;
7131 else
7132 intel_crtc->lowfreq_avail = false;
7133
7134 return 0;
7135 }
7136
7137 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7138 struct intel_link_m_n *m_n)
7139 {
7140 struct drm_device *dev = crtc->base.dev;
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 enum pipe pipe = crtc->pipe;
7143
7144 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7145 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7146 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7147 & ~TU_SIZE_MASK;
7148 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7149 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7150 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7151 }
7152
7153 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7154 enum transcoder transcoder,
7155 struct intel_link_m_n *m_n,
7156 struct intel_link_m_n *m2_n2)
7157 {
7158 struct drm_device *dev = crtc->base.dev;
7159 struct drm_i915_private *dev_priv = dev->dev_private;
7160 enum pipe pipe = crtc->pipe;
7161
7162 if (INTEL_INFO(dev)->gen >= 5) {
7163 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7164 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7165 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7166 & ~TU_SIZE_MASK;
7167 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7168 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7169 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7170 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7171 * gen < 8) and if DRRS is supported (to make sure the
7172 * registers are not unnecessarily read).
7173 */
7174 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7175 crtc->config.has_drrs) {
7176 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7177 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7178 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7179 & ~TU_SIZE_MASK;
7180 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7181 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7182 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7183 }
7184 } else {
7185 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7186 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7187 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7188 & ~TU_SIZE_MASK;
7189 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7190 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7191 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7192 }
7193 }
7194
7195 void intel_dp_get_m_n(struct intel_crtc *crtc,
7196 struct intel_crtc_config *pipe_config)
7197 {
7198 if (crtc->config.has_pch_encoder)
7199 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7200 else
7201 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7202 &pipe_config->dp_m_n,
7203 &pipe_config->dp_m2_n2);
7204 }
7205
7206 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7207 struct intel_crtc_config *pipe_config)
7208 {
7209 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7210 &pipe_config->fdi_m_n, NULL);
7211 }
7212
7213 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7214 struct intel_crtc_config *pipe_config)
7215 {
7216 struct drm_device *dev = crtc->base.dev;
7217 struct drm_i915_private *dev_priv = dev->dev_private;
7218 uint32_t tmp;
7219
7220 tmp = I915_READ(PF_CTL(crtc->pipe));
7221
7222 if (tmp & PF_ENABLE) {
7223 pipe_config->pch_pfit.enabled = true;
7224 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7225 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7226
7227 /* We currently do not free assignements of panel fitters on
7228 * ivb/hsw (since we don't use the higher upscaling modes which
7229 * differentiates them) so just WARN about this case for now. */
7230 if (IS_GEN7(dev)) {
7231 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7232 PF_PIPE_SEL_IVB(crtc->pipe));
7233 }
7234 }
7235 }
7236
7237 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7238 struct intel_plane_config *plane_config)
7239 {
7240 struct drm_device *dev = crtc->base.dev;
7241 struct drm_i915_private *dev_priv = dev->dev_private;
7242 u32 val, base, offset;
7243 int pipe = crtc->pipe, plane = crtc->plane;
7244 int fourcc, pixel_format;
7245 int aligned_height;
7246
7247 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7248 if (!crtc->base.primary->fb) {
7249 DRM_DEBUG_KMS("failed to alloc fb\n");
7250 return;
7251 }
7252
7253 val = I915_READ(DSPCNTR(plane));
7254
7255 if (INTEL_INFO(dev)->gen >= 4)
7256 if (val & DISPPLANE_TILED)
7257 plane_config->tiled = true;
7258
7259 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7260 fourcc = intel_format_to_fourcc(pixel_format);
7261 crtc->base.primary->fb->pixel_format = fourcc;
7262 crtc->base.primary->fb->bits_per_pixel =
7263 drm_format_plane_cpp(fourcc, 0) * 8;
7264
7265 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7266 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7267 offset = I915_READ(DSPOFFSET(plane));
7268 } else {
7269 if (plane_config->tiled)
7270 offset = I915_READ(DSPTILEOFF(plane));
7271 else
7272 offset = I915_READ(DSPLINOFF(plane));
7273 }
7274 plane_config->base = base;
7275
7276 val = I915_READ(PIPESRC(pipe));
7277 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7278 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7279
7280 val = I915_READ(DSPSTRIDE(pipe));
7281 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7282
7283 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7284 plane_config->tiled);
7285
7286 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7287 aligned_height);
7288
7289 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7290 pipe, plane, crtc->base.primary->fb->width,
7291 crtc->base.primary->fb->height,
7292 crtc->base.primary->fb->bits_per_pixel, base,
7293 crtc->base.primary->fb->pitches[0],
7294 plane_config->size);
7295 }
7296
7297 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7298 struct intel_crtc_config *pipe_config)
7299 {
7300 struct drm_device *dev = crtc->base.dev;
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 uint32_t tmp;
7303
7304 if (!intel_display_power_enabled(dev_priv,
7305 POWER_DOMAIN_PIPE(crtc->pipe)))
7306 return false;
7307
7308 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7309 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7310
7311 tmp = I915_READ(PIPECONF(crtc->pipe));
7312 if (!(tmp & PIPECONF_ENABLE))
7313 return false;
7314
7315 switch (tmp & PIPECONF_BPC_MASK) {
7316 case PIPECONF_6BPC:
7317 pipe_config->pipe_bpp = 18;
7318 break;
7319 case PIPECONF_8BPC:
7320 pipe_config->pipe_bpp = 24;
7321 break;
7322 case PIPECONF_10BPC:
7323 pipe_config->pipe_bpp = 30;
7324 break;
7325 case PIPECONF_12BPC:
7326 pipe_config->pipe_bpp = 36;
7327 break;
7328 default:
7329 break;
7330 }
7331
7332 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7333 pipe_config->limited_color_range = true;
7334
7335 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7336 struct intel_shared_dpll *pll;
7337
7338 pipe_config->has_pch_encoder = true;
7339
7340 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7341 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7342 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7343
7344 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7345
7346 if (HAS_PCH_IBX(dev_priv->dev)) {
7347 pipe_config->shared_dpll =
7348 (enum intel_dpll_id) crtc->pipe;
7349 } else {
7350 tmp = I915_READ(PCH_DPLL_SEL);
7351 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7352 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7353 else
7354 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7355 }
7356
7357 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7358
7359 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7360 &pipe_config->dpll_hw_state));
7361
7362 tmp = pipe_config->dpll_hw_state.dpll;
7363 pipe_config->pixel_multiplier =
7364 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7365 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7366
7367 ironlake_pch_clock_get(crtc, pipe_config);
7368 } else {
7369 pipe_config->pixel_multiplier = 1;
7370 }
7371
7372 intel_get_pipe_timings(crtc, pipe_config);
7373
7374 ironlake_get_pfit_config(crtc, pipe_config);
7375
7376 return true;
7377 }
7378
7379 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7380 {
7381 struct drm_device *dev = dev_priv->dev;
7382 struct intel_crtc *crtc;
7383
7384 for_each_intel_crtc(dev, crtc)
7385 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7386 pipe_name(crtc->pipe));
7387
7388 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7389 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7390 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7391 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7392 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7393 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7394 "CPU PWM1 enabled\n");
7395 if (IS_HASWELL(dev))
7396 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7397 "CPU PWM2 enabled\n");
7398 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7399 "PCH PWM1 enabled\n");
7400 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7401 "Utility pin enabled\n");
7402 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7403
7404 /*
7405 * In theory we can still leave IRQs enabled, as long as only the HPD
7406 * interrupts remain enabled. We used to check for that, but since it's
7407 * gen-specific and since we only disable LCPLL after we fully disable
7408 * the interrupts, the check below should be enough.
7409 */
7410 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7411 }
7412
7413 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7414 {
7415 struct drm_device *dev = dev_priv->dev;
7416
7417 if (IS_HASWELL(dev))
7418 return I915_READ(D_COMP_HSW);
7419 else
7420 return I915_READ(D_COMP_BDW);
7421 }
7422
7423 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7424 {
7425 struct drm_device *dev = dev_priv->dev;
7426
7427 if (IS_HASWELL(dev)) {
7428 mutex_lock(&dev_priv->rps.hw_lock);
7429 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7430 val))
7431 DRM_ERROR("Failed to write to D_COMP\n");
7432 mutex_unlock(&dev_priv->rps.hw_lock);
7433 } else {
7434 I915_WRITE(D_COMP_BDW, val);
7435 POSTING_READ(D_COMP_BDW);
7436 }
7437 }
7438
7439 /*
7440 * This function implements pieces of two sequences from BSpec:
7441 * - Sequence for display software to disable LCPLL
7442 * - Sequence for display software to allow package C8+
7443 * The steps implemented here are just the steps that actually touch the LCPLL
7444 * register. Callers should take care of disabling all the display engine
7445 * functions, doing the mode unset, fixing interrupts, etc.
7446 */
7447 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7448 bool switch_to_fclk, bool allow_power_down)
7449 {
7450 uint32_t val;
7451
7452 assert_can_disable_lcpll(dev_priv);
7453
7454 val = I915_READ(LCPLL_CTL);
7455
7456 if (switch_to_fclk) {
7457 val |= LCPLL_CD_SOURCE_FCLK;
7458 I915_WRITE(LCPLL_CTL, val);
7459
7460 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7461 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7462 DRM_ERROR("Switching to FCLK failed\n");
7463
7464 val = I915_READ(LCPLL_CTL);
7465 }
7466
7467 val |= LCPLL_PLL_DISABLE;
7468 I915_WRITE(LCPLL_CTL, val);
7469 POSTING_READ(LCPLL_CTL);
7470
7471 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7472 DRM_ERROR("LCPLL still locked\n");
7473
7474 val = hsw_read_dcomp(dev_priv);
7475 val |= D_COMP_COMP_DISABLE;
7476 hsw_write_dcomp(dev_priv, val);
7477 ndelay(100);
7478
7479 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7480 1))
7481 DRM_ERROR("D_COMP RCOMP still in progress\n");
7482
7483 if (allow_power_down) {
7484 val = I915_READ(LCPLL_CTL);
7485 val |= LCPLL_POWER_DOWN_ALLOW;
7486 I915_WRITE(LCPLL_CTL, val);
7487 POSTING_READ(LCPLL_CTL);
7488 }
7489 }
7490
7491 /*
7492 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7493 * source.
7494 */
7495 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7496 {
7497 uint32_t val;
7498 unsigned long irqflags;
7499
7500 val = I915_READ(LCPLL_CTL);
7501
7502 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7503 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7504 return;
7505
7506 /*
7507 * Make sure we're not on PC8 state before disabling PC8, otherwise
7508 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7509 *
7510 * The other problem is that hsw_restore_lcpll() is called as part of
7511 * the runtime PM resume sequence, so we can't just call
7512 * gen6_gt_force_wake_get() because that function calls
7513 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7514 * while we are on the resume sequence. So to solve this problem we have
7515 * to call special forcewake code that doesn't touch runtime PM and
7516 * doesn't enable the forcewake delayed work.
7517 */
7518 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7519 if (dev_priv->uncore.forcewake_count++ == 0)
7520 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7521 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7522
7523 if (val & LCPLL_POWER_DOWN_ALLOW) {
7524 val &= ~LCPLL_POWER_DOWN_ALLOW;
7525 I915_WRITE(LCPLL_CTL, val);
7526 POSTING_READ(LCPLL_CTL);
7527 }
7528
7529 val = hsw_read_dcomp(dev_priv);
7530 val |= D_COMP_COMP_FORCE;
7531 val &= ~D_COMP_COMP_DISABLE;
7532 hsw_write_dcomp(dev_priv, val);
7533
7534 val = I915_READ(LCPLL_CTL);
7535 val &= ~LCPLL_PLL_DISABLE;
7536 I915_WRITE(LCPLL_CTL, val);
7537
7538 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7539 DRM_ERROR("LCPLL not locked yet\n");
7540
7541 if (val & LCPLL_CD_SOURCE_FCLK) {
7542 val = I915_READ(LCPLL_CTL);
7543 val &= ~LCPLL_CD_SOURCE_FCLK;
7544 I915_WRITE(LCPLL_CTL, val);
7545
7546 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7547 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7548 DRM_ERROR("Switching back to LCPLL failed\n");
7549 }
7550
7551 /* See the big comment above. */
7552 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7553 if (--dev_priv->uncore.forcewake_count == 0)
7554 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7555 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7556 }
7557
7558 /*
7559 * Package states C8 and deeper are really deep PC states that can only be
7560 * reached when all the devices on the system allow it, so even if the graphics
7561 * device allows PC8+, it doesn't mean the system will actually get to these
7562 * states. Our driver only allows PC8+ when going into runtime PM.
7563 *
7564 * The requirements for PC8+ are that all the outputs are disabled, the power
7565 * well is disabled and most interrupts are disabled, and these are also
7566 * requirements for runtime PM. When these conditions are met, we manually do
7567 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7568 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7569 * hang the machine.
7570 *
7571 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7572 * the state of some registers, so when we come back from PC8+ we need to
7573 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7574 * need to take care of the registers kept by RC6. Notice that this happens even
7575 * if we don't put the device in PCI D3 state (which is what currently happens
7576 * because of the runtime PM support).
7577 *
7578 * For more, read "Display Sequences for Package C8" on the hardware
7579 * documentation.
7580 */
7581 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7582 {
7583 struct drm_device *dev = dev_priv->dev;
7584 uint32_t val;
7585
7586 DRM_DEBUG_KMS("Enabling package C8+\n");
7587
7588 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7589 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7590 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7591 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7592 }
7593
7594 lpt_disable_clkout_dp(dev);
7595 hsw_disable_lcpll(dev_priv, true, true);
7596 }
7597
7598 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7599 {
7600 struct drm_device *dev = dev_priv->dev;
7601 uint32_t val;
7602
7603 DRM_DEBUG_KMS("Disabling package C8+\n");
7604
7605 hsw_restore_lcpll(dev_priv);
7606 lpt_init_pch_refclk(dev);
7607
7608 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7609 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7610 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7611 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7612 }
7613
7614 intel_prepare_ddi(dev);
7615 }
7616
7617 static void snb_modeset_global_resources(struct drm_device *dev)
7618 {
7619 modeset_update_crtc_power_domains(dev);
7620 }
7621
7622 static void haswell_modeset_global_resources(struct drm_device *dev)
7623 {
7624 modeset_update_crtc_power_domains(dev);
7625 }
7626
7627 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7628 int x, int y,
7629 struct drm_framebuffer *fb)
7630 {
7631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7632
7633 if (!intel_ddi_pll_select(intel_crtc))
7634 return -EINVAL;
7635
7636 intel_crtc->lowfreq_avail = false;
7637
7638 return 0;
7639 }
7640
7641 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7642 enum port port,
7643 struct intel_crtc_config *pipe_config)
7644 {
7645 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7646
7647 switch (pipe_config->ddi_pll_sel) {
7648 case PORT_CLK_SEL_WRPLL1:
7649 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7650 break;
7651 case PORT_CLK_SEL_WRPLL2:
7652 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7653 break;
7654 }
7655 }
7656
7657 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7658 struct intel_crtc_config *pipe_config)
7659 {
7660 struct drm_device *dev = crtc->base.dev;
7661 struct drm_i915_private *dev_priv = dev->dev_private;
7662 struct intel_shared_dpll *pll;
7663 enum port port;
7664 uint32_t tmp;
7665
7666 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7667
7668 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7669
7670 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7671
7672 if (pipe_config->shared_dpll >= 0) {
7673 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7674
7675 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7676 &pipe_config->dpll_hw_state));
7677 }
7678
7679 /*
7680 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7681 * DDI E. So just check whether this pipe is wired to DDI E and whether
7682 * the PCH transcoder is on.
7683 */
7684 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7685 pipe_config->has_pch_encoder = true;
7686
7687 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7688 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7689 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7690
7691 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7692 }
7693 }
7694
7695 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7696 struct intel_crtc_config *pipe_config)
7697 {
7698 struct drm_device *dev = crtc->base.dev;
7699 struct drm_i915_private *dev_priv = dev->dev_private;
7700 enum intel_display_power_domain pfit_domain;
7701 uint32_t tmp;
7702
7703 if (!intel_display_power_enabled(dev_priv,
7704 POWER_DOMAIN_PIPE(crtc->pipe)))
7705 return false;
7706
7707 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7708 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7709
7710 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7711 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7712 enum pipe trans_edp_pipe;
7713 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7714 default:
7715 WARN(1, "unknown pipe linked to edp transcoder\n");
7716 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7717 case TRANS_DDI_EDP_INPUT_A_ON:
7718 trans_edp_pipe = PIPE_A;
7719 break;
7720 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7721 trans_edp_pipe = PIPE_B;
7722 break;
7723 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7724 trans_edp_pipe = PIPE_C;
7725 break;
7726 }
7727
7728 if (trans_edp_pipe == crtc->pipe)
7729 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7730 }
7731
7732 if (!intel_display_power_enabled(dev_priv,
7733 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7734 return false;
7735
7736 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7737 if (!(tmp & PIPECONF_ENABLE))
7738 return false;
7739
7740 haswell_get_ddi_port_state(crtc, pipe_config);
7741
7742 intel_get_pipe_timings(crtc, pipe_config);
7743
7744 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7745 if (intel_display_power_enabled(dev_priv, pfit_domain))
7746 ironlake_get_pfit_config(crtc, pipe_config);
7747
7748 if (IS_HASWELL(dev))
7749 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7750 (I915_READ(IPS_CTL) & IPS_ENABLE);
7751
7752 pipe_config->pixel_multiplier = 1;
7753
7754 return true;
7755 }
7756
7757 static struct {
7758 int clock;
7759 u32 config;
7760 } hdmi_audio_clock[] = {
7761 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7762 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7763 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7764 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7765 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7766 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7767 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7768 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7769 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7770 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7771 };
7772
7773 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7774 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7775 {
7776 int i;
7777
7778 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7779 if (mode->clock == hdmi_audio_clock[i].clock)
7780 break;
7781 }
7782
7783 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7784 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7785 i = 1;
7786 }
7787
7788 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7789 hdmi_audio_clock[i].clock,
7790 hdmi_audio_clock[i].config);
7791
7792 return hdmi_audio_clock[i].config;
7793 }
7794
7795 static bool intel_eld_uptodate(struct drm_connector *connector,
7796 int reg_eldv, uint32_t bits_eldv,
7797 int reg_elda, uint32_t bits_elda,
7798 int reg_edid)
7799 {
7800 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7801 uint8_t *eld = connector->eld;
7802 uint32_t i;
7803
7804 i = I915_READ(reg_eldv);
7805 i &= bits_eldv;
7806
7807 if (!eld[0])
7808 return !i;
7809
7810 if (!i)
7811 return false;
7812
7813 i = I915_READ(reg_elda);
7814 i &= ~bits_elda;
7815 I915_WRITE(reg_elda, i);
7816
7817 for (i = 0; i < eld[2]; i++)
7818 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7819 return false;
7820
7821 return true;
7822 }
7823
7824 static void g4x_write_eld(struct drm_connector *connector,
7825 struct drm_crtc *crtc,
7826 struct drm_display_mode *mode)
7827 {
7828 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7829 uint8_t *eld = connector->eld;
7830 uint32_t eldv;
7831 uint32_t len;
7832 uint32_t i;
7833
7834 i = I915_READ(G4X_AUD_VID_DID);
7835
7836 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7837 eldv = G4X_ELDV_DEVCL_DEVBLC;
7838 else
7839 eldv = G4X_ELDV_DEVCTG;
7840
7841 if (intel_eld_uptodate(connector,
7842 G4X_AUD_CNTL_ST, eldv,
7843 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7844 G4X_HDMIW_HDMIEDID))
7845 return;
7846
7847 i = I915_READ(G4X_AUD_CNTL_ST);
7848 i &= ~(eldv | G4X_ELD_ADDR);
7849 len = (i >> 9) & 0x1f; /* ELD buffer size */
7850 I915_WRITE(G4X_AUD_CNTL_ST, i);
7851
7852 if (!eld[0])
7853 return;
7854
7855 len = min_t(uint8_t, eld[2], len);
7856 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7857 for (i = 0; i < len; i++)
7858 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7859
7860 i = I915_READ(G4X_AUD_CNTL_ST);
7861 i |= eldv;
7862 I915_WRITE(G4X_AUD_CNTL_ST, i);
7863 }
7864
7865 static void haswell_write_eld(struct drm_connector *connector,
7866 struct drm_crtc *crtc,
7867 struct drm_display_mode *mode)
7868 {
7869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7870 uint8_t *eld = connector->eld;
7871 uint32_t eldv;
7872 uint32_t i;
7873 int len;
7874 int pipe = to_intel_crtc(crtc)->pipe;
7875 int tmp;
7876
7877 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7878 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7879 int aud_config = HSW_AUD_CFG(pipe);
7880 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7881
7882 /* Audio output enable */
7883 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7884 tmp = I915_READ(aud_cntrl_st2);
7885 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7886 I915_WRITE(aud_cntrl_st2, tmp);
7887 POSTING_READ(aud_cntrl_st2);
7888
7889 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7890
7891 /* Set ELD valid state */
7892 tmp = I915_READ(aud_cntrl_st2);
7893 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7894 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7895 I915_WRITE(aud_cntrl_st2, tmp);
7896 tmp = I915_READ(aud_cntrl_st2);
7897 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7898
7899 /* Enable HDMI mode */
7900 tmp = I915_READ(aud_config);
7901 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7902 /* clear N_programing_enable and N_value_index */
7903 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7904 I915_WRITE(aud_config, tmp);
7905
7906 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7907
7908 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7909
7910 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7911 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7912 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7913 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7914 } else {
7915 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7916 }
7917
7918 if (intel_eld_uptodate(connector,
7919 aud_cntrl_st2, eldv,
7920 aud_cntl_st, IBX_ELD_ADDRESS,
7921 hdmiw_hdmiedid))
7922 return;
7923
7924 i = I915_READ(aud_cntrl_st2);
7925 i &= ~eldv;
7926 I915_WRITE(aud_cntrl_st2, i);
7927
7928 if (!eld[0])
7929 return;
7930
7931 i = I915_READ(aud_cntl_st);
7932 i &= ~IBX_ELD_ADDRESS;
7933 I915_WRITE(aud_cntl_st, i);
7934 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7935 DRM_DEBUG_DRIVER("port num:%d\n", i);
7936
7937 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7938 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7939 for (i = 0; i < len; i++)
7940 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7941
7942 i = I915_READ(aud_cntrl_st2);
7943 i |= eldv;
7944 I915_WRITE(aud_cntrl_st2, i);
7945
7946 }
7947
7948 static void ironlake_write_eld(struct drm_connector *connector,
7949 struct drm_crtc *crtc,
7950 struct drm_display_mode *mode)
7951 {
7952 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7953 uint8_t *eld = connector->eld;
7954 uint32_t eldv;
7955 uint32_t i;
7956 int len;
7957 int hdmiw_hdmiedid;
7958 int aud_config;
7959 int aud_cntl_st;
7960 int aud_cntrl_st2;
7961 int pipe = to_intel_crtc(crtc)->pipe;
7962
7963 if (HAS_PCH_IBX(connector->dev)) {
7964 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7965 aud_config = IBX_AUD_CFG(pipe);
7966 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7967 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7968 } else if (IS_VALLEYVIEW(connector->dev)) {
7969 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7970 aud_config = VLV_AUD_CFG(pipe);
7971 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7972 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7973 } else {
7974 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7975 aud_config = CPT_AUD_CFG(pipe);
7976 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7977 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7978 }
7979
7980 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7981
7982 if (IS_VALLEYVIEW(connector->dev)) {
7983 struct intel_encoder *intel_encoder;
7984 struct intel_digital_port *intel_dig_port;
7985
7986 intel_encoder = intel_attached_encoder(connector);
7987 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7988 i = intel_dig_port->port;
7989 } else {
7990 i = I915_READ(aud_cntl_st);
7991 i = (i >> 29) & DIP_PORT_SEL_MASK;
7992 /* DIP_Port_Select, 0x1 = PortB */
7993 }
7994
7995 if (!i) {
7996 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7997 /* operate blindly on all ports */
7998 eldv = IBX_ELD_VALIDB;
7999 eldv |= IBX_ELD_VALIDB << 4;
8000 eldv |= IBX_ELD_VALIDB << 8;
8001 } else {
8002 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8003 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8004 }
8005
8006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8007 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8008 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8009 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8010 } else {
8011 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8012 }
8013
8014 if (intel_eld_uptodate(connector,
8015 aud_cntrl_st2, eldv,
8016 aud_cntl_st, IBX_ELD_ADDRESS,
8017 hdmiw_hdmiedid))
8018 return;
8019
8020 i = I915_READ(aud_cntrl_st2);
8021 i &= ~eldv;
8022 I915_WRITE(aud_cntrl_st2, i);
8023
8024 if (!eld[0])
8025 return;
8026
8027 i = I915_READ(aud_cntl_st);
8028 i &= ~IBX_ELD_ADDRESS;
8029 I915_WRITE(aud_cntl_st, i);
8030
8031 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8032 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8033 for (i = 0; i < len; i++)
8034 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8035
8036 i = I915_READ(aud_cntrl_st2);
8037 i |= eldv;
8038 I915_WRITE(aud_cntrl_st2, i);
8039 }
8040
8041 void intel_write_eld(struct drm_encoder *encoder,
8042 struct drm_display_mode *mode)
8043 {
8044 struct drm_crtc *crtc = encoder->crtc;
8045 struct drm_connector *connector;
8046 struct drm_device *dev = encoder->dev;
8047 struct drm_i915_private *dev_priv = dev->dev_private;
8048
8049 connector = drm_select_eld(encoder, mode);
8050 if (!connector)
8051 return;
8052
8053 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8054 connector->base.id,
8055 connector->name,
8056 connector->encoder->base.id,
8057 connector->encoder->name);
8058
8059 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8060
8061 if (dev_priv->display.write_eld)
8062 dev_priv->display.write_eld(connector, crtc, mode);
8063 }
8064
8065 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8066 {
8067 struct drm_device *dev = crtc->dev;
8068 struct drm_i915_private *dev_priv = dev->dev_private;
8069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8070 uint32_t cntl = 0, size = 0;
8071
8072 if (base) {
8073 unsigned int width = intel_crtc->cursor_width;
8074 unsigned int height = intel_crtc->cursor_height;
8075 unsigned int stride = roundup_pow_of_two(width) * 4;
8076
8077 switch (stride) {
8078 default:
8079 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8080 width, stride);
8081 stride = 256;
8082 /* fallthrough */
8083 case 256:
8084 case 512:
8085 case 1024:
8086 case 2048:
8087 break;
8088 }
8089
8090 cntl |= CURSOR_ENABLE |
8091 CURSOR_GAMMA_ENABLE |
8092 CURSOR_FORMAT_ARGB |
8093 CURSOR_STRIDE(stride);
8094
8095 size = (height << 12) | width;
8096 }
8097
8098 if (intel_crtc->cursor_cntl != 0 &&
8099 (intel_crtc->cursor_base != base ||
8100 intel_crtc->cursor_size != size ||
8101 intel_crtc->cursor_cntl != cntl)) {
8102 /* On these chipsets we can only modify the base/size/stride
8103 * whilst the cursor is disabled.
8104 */
8105 I915_WRITE(_CURACNTR, 0);
8106 POSTING_READ(_CURACNTR);
8107 intel_crtc->cursor_cntl = 0;
8108 }
8109
8110 if (intel_crtc->cursor_base != base)
8111 I915_WRITE(_CURABASE, base);
8112
8113 if (intel_crtc->cursor_size != size) {
8114 I915_WRITE(CURSIZE, size);
8115 intel_crtc->cursor_size = size;
8116 }
8117
8118 if (intel_crtc->cursor_cntl != cntl) {
8119 I915_WRITE(_CURACNTR, cntl);
8120 POSTING_READ(_CURACNTR);
8121 intel_crtc->cursor_cntl = cntl;
8122 }
8123 }
8124
8125 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8126 {
8127 struct drm_device *dev = crtc->dev;
8128 struct drm_i915_private *dev_priv = dev->dev_private;
8129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8130 int pipe = intel_crtc->pipe;
8131 uint32_t cntl;
8132
8133 cntl = 0;
8134 if (base) {
8135 cntl = MCURSOR_GAMMA_ENABLE;
8136 switch (intel_crtc->cursor_width) {
8137 case 64:
8138 cntl |= CURSOR_MODE_64_ARGB_AX;
8139 break;
8140 case 128:
8141 cntl |= CURSOR_MODE_128_ARGB_AX;
8142 break;
8143 case 256:
8144 cntl |= CURSOR_MODE_256_ARGB_AX;
8145 break;
8146 default:
8147 WARN_ON(1);
8148 return;
8149 }
8150 cntl |= pipe << 28; /* Connect to correct pipe */
8151 }
8152 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8153 cntl |= CURSOR_PIPE_CSC_ENABLE;
8154
8155 if (intel_crtc->cursor_cntl != cntl) {
8156 I915_WRITE(CURCNTR(pipe), cntl);
8157 POSTING_READ(CURCNTR(pipe));
8158 intel_crtc->cursor_cntl = cntl;
8159 }
8160
8161 /* and commit changes on next vblank */
8162 I915_WRITE(CURBASE(pipe), base);
8163 POSTING_READ(CURBASE(pipe));
8164 }
8165
8166 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8167 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8168 bool on)
8169 {
8170 struct drm_device *dev = crtc->dev;
8171 struct drm_i915_private *dev_priv = dev->dev_private;
8172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8173 int pipe = intel_crtc->pipe;
8174 int x = crtc->cursor_x;
8175 int y = crtc->cursor_y;
8176 u32 base = 0, pos = 0;
8177
8178 if (on)
8179 base = intel_crtc->cursor_addr;
8180
8181 if (x >= intel_crtc->config.pipe_src_w)
8182 base = 0;
8183
8184 if (y >= intel_crtc->config.pipe_src_h)
8185 base = 0;
8186
8187 if (x < 0) {
8188 if (x + intel_crtc->cursor_width <= 0)
8189 base = 0;
8190
8191 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8192 x = -x;
8193 }
8194 pos |= x << CURSOR_X_SHIFT;
8195
8196 if (y < 0) {
8197 if (y + intel_crtc->cursor_height <= 0)
8198 base = 0;
8199
8200 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8201 y = -y;
8202 }
8203 pos |= y << CURSOR_Y_SHIFT;
8204
8205 if (base == 0 && intel_crtc->cursor_base == 0)
8206 return;
8207
8208 I915_WRITE(CURPOS(pipe), pos);
8209
8210 if (IS_845G(dev) || IS_I865G(dev))
8211 i845_update_cursor(crtc, base);
8212 else
8213 i9xx_update_cursor(crtc, base);
8214 intel_crtc->cursor_base = base;
8215 }
8216
8217 static bool cursor_size_ok(struct drm_device *dev,
8218 uint32_t width, uint32_t height)
8219 {
8220 if (width == 0 || height == 0)
8221 return false;
8222
8223 /*
8224 * 845g/865g are special in that they are only limited by
8225 * the width of their cursors, the height is arbitrary up to
8226 * the precision of the register. Everything else requires
8227 * square cursors, limited to a few power-of-two sizes.
8228 */
8229 if (IS_845G(dev) || IS_I865G(dev)) {
8230 if ((width & 63) != 0)
8231 return false;
8232
8233 if (width > (IS_845G(dev) ? 64 : 512))
8234 return false;
8235
8236 if (height > 1023)
8237 return false;
8238 } else {
8239 switch (width | height) {
8240 case 256:
8241 case 128:
8242 if (IS_GEN2(dev))
8243 return false;
8244 case 64:
8245 break;
8246 default:
8247 return false;
8248 }
8249 }
8250
8251 return true;
8252 }
8253
8254 /*
8255 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8256 *
8257 * Note that the object's reference will be consumed if the update fails. If
8258 * the update succeeds, the reference of the old object (if any) will be
8259 * consumed.
8260 */
8261 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8262 struct drm_i915_gem_object *obj,
8263 uint32_t width, uint32_t height)
8264 {
8265 struct drm_device *dev = crtc->dev;
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8268 enum pipe pipe = intel_crtc->pipe;
8269 unsigned old_width, stride;
8270 uint32_t addr;
8271 int ret;
8272
8273 /* if we want to turn off the cursor ignore width and height */
8274 if (!obj) {
8275 DRM_DEBUG_KMS("cursor off\n");
8276 addr = 0;
8277 obj = NULL;
8278 mutex_lock(&dev->struct_mutex);
8279 goto finish;
8280 }
8281
8282 /* Check for which cursor types we support */
8283 if (!cursor_size_ok(dev, width, height)) {
8284 DRM_DEBUG("Cursor dimension not supported\n");
8285 return -EINVAL;
8286 }
8287
8288 stride = roundup_pow_of_two(width) * 4;
8289 if (obj->base.size < stride * height) {
8290 DRM_DEBUG_KMS("buffer is too small\n");
8291 ret = -ENOMEM;
8292 goto fail;
8293 }
8294
8295 /* we only need to pin inside GTT if cursor is non-phy */
8296 mutex_lock(&dev->struct_mutex);
8297 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8298 unsigned alignment;
8299
8300 if (obj->tiling_mode) {
8301 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8302 ret = -EINVAL;
8303 goto fail_locked;
8304 }
8305
8306 /*
8307 * Global gtt pte registers are special registers which actually
8308 * forward writes to a chunk of system memory. Which means that
8309 * there is no risk that the register values disappear as soon
8310 * as we call intel_runtime_pm_put(), so it is correct to wrap
8311 * only the pin/unpin/fence and not more.
8312 */
8313 intel_runtime_pm_get(dev_priv);
8314
8315 /* Note that the w/a also requires 2 PTE of padding following
8316 * the bo. We currently fill all unused PTE with the shadow
8317 * page and so we should always have valid PTE following the
8318 * cursor preventing the VT-d warning.
8319 */
8320 alignment = 0;
8321 if (need_vtd_wa(dev))
8322 alignment = 64*1024;
8323
8324 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8325 if (ret) {
8326 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8327 intel_runtime_pm_put(dev_priv);
8328 goto fail_locked;
8329 }
8330
8331 ret = i915_gem_object_put_fence(obj);
8332 if (ret) {
8333 DRM_DEBUG_KMS("failed to release fence for cursor");
8334 intel_runtime_pm_put(dev_priv);
8335 goto fail_unpin;
8336 }
8337
8338 addr = i915_gem_obj_ggtt_offset(obj);
8339
8340 intel_runtime_pm_put(dev_priv);
8341 } else {
8342 int align = IS_I830(dev) ? 16 * 1024 : 256;
8343 ret = i915_gem_object_attach_phys(obj, align);
8344 if (ret) {
8345 DRM_DEBUG_KMS("failed to attach phys object\n");
8346 goto fail_locked;
8347 }
8348 addr = obj->phys_handle->busaddr;
8349 }
8350
8351 finish:
8352 if (intel_crtc->cursor_bo) {
8353 if (!INTEL_INFO(dev)->cursor_needs_physical)
8354 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8355 }
8356
8357 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8358 INTEL_FRONTBUFFER_CURSOR(pipe));
8359 mutex_unlock(&dev->struct_mutex);
8360
8361 old_width = intel_crtc->cursor_width;
8362
8363 intel_crtc->cursor_addr = addr;
8364 intel_crtc->cursor_bo = obj;
8365 intel_crtc->cursor_width = width;
8366 intel_crtc->cursor_height = height;
8367
8368 if (intel_crtc->active) {
8369 if (old_width != width)
8370 intel_update_watermarks(crtc);
8371 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8372 }
8373
8374 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8375
8376 return 0;
8377 fail_unpin:
8378 i915_gem_object_unpin_from_display_plane(obj);
8379 fail_locked:
8380 mutex_unlock(&dev->struct_mutex);
8381 fail:
8382 drm_gem_object_unreference_unlocked(&obj->base);
8383 return ret;
8384 }
8385
8386 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8387 u16 *blue, uint32_t start, uint32_t size)
8388 {
8389 int end = (start + size > 256) ? 256 : start + size, i;
8390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8391
8392 for (i = start; i < end; i++) {
8393 intel_crtc->lut_r[i] = red[i] >> 8;
8394 intel_crtc->lut_g[i] = green[i] >> 8;
8395 intel_crtc->lut_b[i] = blue[i] >> 8;
8396 }
8397
8398 intel_crtc_load_lut(crtc);
8399 }
8400
8401 /* VESA 640x480x72Hz mode to set on the pipe */
8402 static struct drm_display_mode load_detect_mode = {
8403 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8404 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8405 };
8406
8407 struct drm_framebuffer *
8408 __intel_framebuffer_create(struct drm_device *dev,
8409 struct drm_mode_fb_cmd2 *mode_cmd,
8410 struct drm_i915_gem_object *obj)
8411 {
8412 struct intel_framebuffer *intel_fb;
8413 int ret;
8414
8415 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8416 if (!intel_fb) {
8417 drm_gem_object_unreference_unlocked(&obj->base);
8418 return ERR_PTR(-ENOMEM);
8419 }
8420
8421 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8422 if (ret)
8423 goto err;
8424
8425 return &intel_fb->base;
8426 err:
8427 drm_gem_object_unreference_unlocked(&obj->base);
8428 kfree(intel_fb);
8429
8430 return ERR_PTR(ret);
8431 }
8432
8433 static struct drm_framebuffer *
8434 intel_framebuffer_create(struct drm_device *dev,
8435 struct drm_mode_fb_cmd2 *mode_cmd,
8436 struct drm_i915_gem_object *obj)
8437 {
8438 struct drm_framebuffer *fb;
8439 int ret;
8440
8441 ret = i915_mutex_lock_interruptible(dev);
8442 if (ret)
8443 return ERR_PTR(ret);
8444 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8445 mutex_unlock(&dev->struct_mutex);
8446
8447 return fb;
8448 }
8449
8450 static u32
8451 intel_framebuffer_pitch_for_width(int width, int bpp)
8452 {
8453 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8454 return ALIGN(pitch, 64);
8455 }
8456
8457 static u32
8458 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8459 {
8460 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8461 return PAGE_ALIGN(pitch * mode->vdisplay);
8462 }
8463
8464 static struct drm_framebuffer *
8465 intel_framebuffer_create_for_mode(struct drm_device *dev,
8466 struct drm_display_mode *mode,
8467 int depth, int bpp)
8468 {
8469 struct drm_i915_gem_object *obj;
8470 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8471
8472 obj = i915_gem_alloc_object(dev,
8473 intel_framebuffer_size_for_mode(mode, bpp));
8474 if (obj == NULL)
8475 return ERR_PTR(-ENOMEM);
8476
8477 mode_cmd.width = mode->hdisplay;
8478 mode_cmd.height = mode->vdisplay;
8479 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8480 bpp);
8481 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8482
8483 return intel_framebuffer_create(dev, &mode_cmd, obj);
8484 }
8485
8486 static struct drm_framebuffer *
8487 mode_fits_in_fbdev(struct drm_device *dev,
8488 struct drm_display_mode *mode)
8489 {
8490 #ifdef CONFIG_DRM_I915_FBDEV
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 struct drm_i915_gem_object *obj;
8493 struct drm_framebuffer *fb;
8494
8495 if (!dev_priv->fbdev)
8496 return NULL;
8497
8498 if (!dev_priv->fbdev->fb)
8499 return NULL;
8500
8501 obj = dev_priv->fbdev->fb->obj;
8502 BUG_ON(!obj);
8503
8504 fb = &dev_priv->fbdev->fb->base;
8505 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8506 fb->bits_per_pixel))
8507 return NULL;
8508
8509 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8510 return NULL;
8511
8512 return fb;
8513 #else
8514 return NULL;
8515 #endif
8516 }
8517
8518 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8519 struct drm_display_mode *mode,
8520 struct intel_load_detect_pipe *old,
8521 struct drm_modeset_acquire_ctx *ctx)
8522 {
8523 struct intel_crtc *intel_crtc;
8524 struct intel_encoder *intel_encoder =
8525 intel_attached_encoder(connector);
8526 struct drm_crtc *possible_crtc;
8527 struct drm_encoder *encoder = &intel_encoder->base;
8528 struct drm_crtc *crtc = NULL;
8529 struct drm_device *dev = encoder->dev;
8530 struct drm_framebuffer *fb;
8531 struct drm_mode_config *config = &dev->mode_config;
8532 int ret, i = -1;
8533
8534 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8535 connector->base.id, connector->name,
8536 encoder->base.id, encoder->name);
8537
8538 retry:
8539 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8540 if (ret)
8541 goto fail_unlock;
8542
8543 /*
8544 * Algorithm gets a little messy:
8545 *
8546 * - if the connector already has an assigned crtc, use it (but make
8547 * sure it's on first)
8548 *
8549 * - try to find the first unused crtc that can drive this connector,
8550 * and use that if we find one
8551 */
8552
8553 /* See if we already have a CRTC for this connector */
8554 if (encoder->crtc) {
8555 crtc = encoder->crtc;
8556
8557 ret = drm_modeset_lock(&crtc->mutex, ctx);
8558 if (ret)
8559 goto fail_unlock;
8560
8561 old->dpms_mode = connector->dpms;
8562 old->load_detect_temp = false;
8563
8564 /* Make sure the crtc and connector are running */
8565 if (connector->dpms != DRM_MODE_DPMS_ON)
8566 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8567
8568 return true;
8569 }
8570
8571 /* Find an unused one (if possible) */
8572 for_each_crtc(dev, possible_crtc) {
8573 i++;
8574 if (!(encoder->possible_crtcs & (1 << i)))
8575 continue;
8576 if (possible_crtc->enabled)
8577 continue;
8578 /* This can occur when applying the pipe A quirk on resume. */
8579 if (to_intel_crtc(possible_crtc)->new_enabled)
8580 continue;
8581
8582 crtc = possible_crtc;
8583 break;
8584 }
8585
8586 /*
8587 * If we didn't find an unused CRTC, don't use any.
8588 */
8589 if (!crtc) {
8590 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8591 goto fail_unlock;
8592 }
8593
8594 ret = drm_modeset_lock(&crtc->mutex, ctx);
8595 if (ret)
8596 goto fail_unlock;
8597 intel_encoder->new_crtc = to_intel_crtc(crtc);
8598 to_intel_connector(connector)->new_encoder = intel_encoder;
8599
8600 intel_crtc = to_intel_crtc(crtc);
8601 intel_crtc->new_enabled = true;
8602 intel_crtc->new_config = &intel_crtc->config;
8603 old->dpms_mode = connector->dpms;
8604 old->load_detect_temp = true;
8605 old->release_fb = NULL;
8606
8607 if (!mode)
8608 mode = &load_detect_mode;
8609
8610 /* We need a framebuffer large enough to accommodate all accesses
8611 * that the plane may generate whilst we perform load detection.
8612 * We can not rely on the fbcon either being present (we get called
8613 * during its initialisation to detect all boot displays, or it may
8614 * not even exist) or that it is large enough to satisfy the
8615 * requested mode.
8616 */
8617 fb = mode_fits_in_fbdev(dev, mode);
8618 if (fb == NULL) {
8619 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8620 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8621 old->release_fb = fb;
8622 } else
8623 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8624 if (IS_ERR(fb)) {
8625 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8626 goto fail;
8627 }
8628
8629 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8630 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8631 if (old->release_fb)
8632 old->release_fb->funcs->destroy(old->release_fb);
8633 goto fail;
8634 }
8635
8636 /* let the connector get through one full cycle before testing */
8637 intel_wait_for_vblank(dev, intel_crtc->pipe);
8638 return true;
8639
8640 fail:
8641 intel_crtc->new_enabled = crtc->enabled;
8642 if (intel_crtc->new_enabled)
8643 intel_crtc->new_config = &intel_crtc->config;
8644 else
8645 intel_crtc->new_config = NULL;
8646 fail_unlock:
8647 if (ret == -EDEADLK) {
8648 drm_modeset_backoff(ctx);
8649 goto retry;
8650 }
8651
8652 return false;
8653 }
8654
8655 void intel_release_load_detect_pipe(struct drm_connector *connector,
8656 struct intel_load_detect_pipe *old)
8657 {
8658 struct intel_encoder *intel_encoder =
8659 intel_attached_encoder(connector);
8660 struct drm_encoder *encoder = &intel_encoder->base;
8661 struct drm_crtc *crtc = encoder->crtc;
8662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8663
8664 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8665 connector->base.id, connector->name,
8666 encoder->base.id, encoder->name);
8667
8668 if (old->load_detect_temp) {
8669 to_intel_connector(connector)->new_encoder = NULL;
8670 intel_encoder->new_crtc = NULL;
8671 intel_crtc->new_enabled = false;
8672 intel_crtc->new_config = NULL;
8673 intel_set_mode(crtc, NULL, 0, 0, NULL);
8674
8675 if (old->release_fb) {
8676 drm_framebuffer_unregister_private(old->release_fb);
8677 drm_framebuffer_unreference(old->release_fb);
8678 }
8679
8680 return;
8681 }
8682
8683 /* Switch crtc and encoder back off if necessary */
8684 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8685 connector->funcs->dpms(connector, old->dpms_mode);
8686 }
8687
8688 static int i9xx_pll_refclk(struct drm_device *dev,
8689 const struct intel_crtc_config *pipe_config)
8690 {
8691 struct drm_i915_private *dev_priv = dev->dev_private;
8692 u32 dpll = pipe_config->dpll_hw_state.dpll;
8693
8694 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8695 return dev_priv->vbt.lvds_ssc_freq;
8696 else if (HAS_PCH_SPLIT(dev))
8697 return 120000;
8698 else if (!IS_GEN2(dev))
8699 return 96000;
8700 else
8701 return 48000;
8702 }
8703
8704 /* Returns the clock of the currently programmed mode of the given pipe. */
8705 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8706 struct intel_crtc_config *pipe_config)
8707 {
8708 struct drm_device *dev = crtc->base.dev;
8709 struct drm_i915_private *dev_priv = dev->dev_private;
8710 int pipe = pipe_config->cpu_transcoder;
8711 u32 dpll = pipe_config->dpll_hw_state.dpll;
8712 u32 fp;
8713 intel_clock_t clock;
8714 int refclk = i9xx_pll_refclk(dev, pipe_config);
8715
8716 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8717 fp = pipe_config->dpll_hw_state.fp0;
8718 else
8719 fp = pipe_config->dpll_hw_state.fp1;
8720
8721 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8722 if (IS_PINEVIEW(dev)) {
8723 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8724 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8725 } else {
8726 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8727 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8728 }
8729
8730 if (!IS_GEN2(dev)) {
8731 if (IS_PINEVIEW(dev))
8732 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8733 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8734 else
8735 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8736 DPLL_FPA01_P1_POST_DIV_SHIFT);
8737
8738 switch (dpll & DPLL_MODE_MASK) {
8739 case DPLLB_MODE_DAC_SERIAL:
8740 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8741 5 : 10;
8742 break;
8743 case DPLLB_MODE_LVDS:
8744 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8745 7 : 14;
8746 break;
8747 default:
8748 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8749 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8750 return;
8751 }
8752
8753 if (IS_PINEVIEW(dev))
8754 pineview_clock(refclk, &clock);
8755 else
8756 i9xx_clock(refclk, &clock);
8757 } else {
8758 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8759 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8760
8761 if (is_lvds) {
8762 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8763 DPLL_FPA01_P1_POST_DIV_SHIFT);
8764
8765 if (lvds & LVDS_CLKB_POWER_UP)
8766 clock.p2 = 7;
8767 else
8768 clock.p2 = 14;
8769 } else {
8770 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8771 clock.p1 = 2;
8772 else {
8773 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8774 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8775 }
8776 if (dpll & PLL_P2_DIVIDE_BY_4)
8777 clock.p2 = 4;
8778 else
8779 clock.p2 = 2;
8780 }
8781
8782 i9xx_clock(refclk, &clock);
8783 }
8784
8785 /*
8786 * This value includes pixel_multiplier. We will use
8787 * port_clock to compute adjusted_mode.crtc_clock in the
8788 * encoder's get_config() function.
8789 */
8790 pipe_config->port_clock = clock.dot;
8791 }
8792
8793 int intel_dotclock_calculate(int link_freq,
8794 const struct intel_link_m_n *m_n)
8795 {
8796 /*
8797 * The calculation for the data clock is:
8798 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8799 * But we want to avoid losing precison if possible, so:
8800 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8801 *
8802 * and the link clock is simpler:
8803 * link_clock = (m * link_clock) / n
8804 */
8805
8806 if (!m_n->link_n)
8807 return 0;
8808
8809 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8810 }
8811
8812 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8813 struct intel_crtc_config *pipe_config)
8814 {
8815 struct drm_device *dev = crtc->base.dev;
8816
8817 /* read out port_clock from the DPLL */
8818 i9xx_crtc_clock_get(crtc, pipe_config);
8819
8820 /*
8821 * This value does not include pixel_multiplier.
8822 * We will check that port_clock and adjusted_mode.crtc_clock
8823 * agree once we know their relationship in the encoder's
8824 * get_config() function.
8825 */
8826 pipe_config->adjusted_mode.crtc_clock =
8827 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8828 &pipe_config->fdi_m_n);
8829 }
8830
8831 /** Returns the currently programmed mode of the given pipe. */
8832 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8833 struct drm_crtc *crtc)
8834 {
8835 struct drm_i915_private *dev_priv = dev->dev_private;
8836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8837 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8838 struct drm_display_mode *mode;
8839 struct intel_crtc_config pipe_config;
8840 int htot = I915_READ(HTOTAL(cpu_transcoder));
8841 int hsync = I915_READ(HSYNC(cpu_transcoder));
8842 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8843 int vsync = I915_READ(VSYNC(cpu_transcoder));
8844 enum pipe pipe = intel_crtc->pipe;
8845
8846 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8847 if (!mode)
8848 return NULL;
8849
8850 /*
8851 * Construct a pipe_config sufficient for getting the clock info
8852 * back out of crtc_clock_get.
8853 *
8854 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8855 * to use a real value here instead.
8856 */
8857 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8858 pipe_config.pixel_multiplier = 1;
8859 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8860 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8861 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8862 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8863
8864 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8865 mode->hdisplay = (htot & 0xffff) + 1;
8866 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8867 mode->hsync_start = (hsync & 0xffff) + 1;
8868 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8869 mode->vdisplay = (vtot & 0xffff) + 1;
8870 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8871 mode->vsync_start = (vsync & 0xffff) + 1;
8872 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8873
8874 drm_mode_set_name(mode);
8875
8876 return mode;
8877 }
8878
8879 static void intel_increase_pllclock(struct drm_device *dev,
8880 enum pipe pipe)
8881 {
8882 struct drm_i915_private *dev_priv = dev->dev_private;
8883 int dpll_reg = DPLL(pipe);
8884 int dpll;
8885
8886 if (!HAS_GMCH_DISPLAY(dev))
8887 return;
8888
8889 if (!dev_priv->lvds_downclock_avail)
8890 return;
8891
8892 dpll = I915_READ(dpll_reg);
8893 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8894 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8895
8896 assert_panel_unlocked(dev_priv, pipe);
8897
8898 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8899 I915_WRITE(dpll_reg, dpll);
8900 intel_wait_for_vblank(dev, pipe);
8901
8902 dpll = I915_READ(dpll_reg);
8903 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8904 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8905 }
8906 }
8907
8908 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8909 {
8910 struct drm_device *dev = crtc->dev;
8911 struct drm_i915_private *dev_priv = dev->dev_private;
8912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8913
8914 if (!HAS_GMCH_DISPLAY(dev))
8915 return;
8916
8917 if (!dev_priv->lvds_downclock_avail)
8918 return;
8919
8920 /*
8921 * Since this is called by a timer, we should never get here in
8922 * the manual case.
8923 */
8924 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8925 int pipe = intel_crtc->pipe;
8926 int dpll_reg = DPLL(pipe);
8927 int dpll;
8928
8929 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8930
8931 assert_panel_unlocked(dev_priv, pipe);
8932
8933 dpll = I915_READ(dpll_reg);
8934 dpll |= DISPLAY_RATE_SELECT_FPA1;
8935 I915_WRITE(dpll_reg, dpll);
8936 intel_wait_for_vblank(dev, pipe);
8937 dpll = I915_READ(dpll_reg);
8938 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8939 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8940 }
8941
8942 }
8943
8944 void intel_mark_busy(struct drm_device *dev)
8945 {
8946 struct drm_i915_private *dev_priv = dev->dev_private;
8947
8948 if (dev_priv->mm.busy)
8949 return;
8950
8951 intel_runtime_pm_get(dev_priv);
8952 i915_update_gfx_val(dev_priv);
8953 dev_priv->mm.busy = true;
8954 }
8955
8956 void intel_mark_idle(struct drm_device *dev)
8957 {
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959 struct drm_crtc *crtc;
8960
8961 if (!dev_priv->mm.busy)
8962 return;
8963
8964 dev_priv->mm.busy = false;
8965
8966 if (!i915.powersave)
8967 goto out;
8968
8969 for_each_crtc(dev, crtc) {
8970 if (!crtc->primary->fb)
8971 continue;
8972
8973 intel_decrease_pllclock(crtc);
8974 }
8975
8976 if (INTEL_INFO(dev)->gen >= 6)
8977 gen6_rps_idle(dev->dev_private);
8978
8979 out:
8980 intel_runtime_pm_put(dev_priv);
8981 }
8982
8983
8984 /**
8985 * intel_mark_fb_busy - mark given planes as busy
8986 * @dev: DRM device
8987 * @frontbuffer_bits: bits for the affected planes
8988 * @ring: optional ring for asynchronous commands
8989 *
8990 * This function gets called every time the screen contents change. It can be
8991 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8992 */
8993 static void intel_mark_fb_busy(struct drm_device *dev,
8994 unsigned frontbuffer_bits,
8995 struct intel_engine_cs *ring)
8996 {
8997 enum pipe pipe;
8998
8999 if (!i915.powersave)
9000 return;
9001
9002 for_each_pipe(pipe) {
9003 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9004 continue;
9005
9006 intel_increase_pllclock(dev, pipe);
9007 if (ring && intel_fbc_enabled(dev))
9008 ring->fbc_dirty = true;
9009 }
9010 }
9011
9012 /**
9013 * intel_fb_obj_invalidate - invalidate frontbuffer object
9014 * @obj: GEM object to invalidate
9015 * @ring: set for asynchronous rendering
9016 *
9017 * This function gets called every time rendering on the given object starts and
9018 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9019 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9020 * until the rendering completes or a flip on this frontbuffer plane is
9021 * scheduled.
9022 */
9023 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9024 struct intel_engine_cs *ring)
9025 {
9026 struct drm_device *dev = obj->base.dev;
9027 struct drm_i915_private *dev_priv = dev->dev_private;
9028
9029 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9030
9031 if (!obj->frontbuffer_bits)
9032 return;
9033
9034 if (ring) {
9035 mutex_lock(&dev_priv->fb_tracking.lock);
9036 dev_priv->fb_tracking.busy_bits
9037 |= obj->frontbuffer_bits;
9038 dev_priv->fb_tracking.flip_bits
9039 &= ~obj->frontbuffer_bits;
9040 mutex_unlock(&dev_priv->fb_tracking.lock);
9041 }
9042
9043 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9044
9045 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9046 }
9047
9048 /**
9049 * intel_frontbuffer_flush - flush frontbuffer
9050 * @dev: DRM device
9051 * @frontbuffer_bits: frontbuffer plane tracking bits
9052 *
9053 * This function gets called every time rendering on the given planes has
9054 * completed and frontbuffer caching can be started again. Flushes will get
9055 * delayed if they're blocked by some oustanding asynchronous rendering.
9056 *
9057 * Can be called without any locks held.
9058 */
9059 void intel_frontbuffer_flush(struct drm_device *dev,
9060 unsigned frontbuffer_bits)
9061 {
9062 struct drm_i915_private *dev_priv = dev->dev_private;
9063
9064 /* Delay flushing when rings are still busy.*/
9065 mutex_lock(&dev_priv->fb_tracking.lock);
9066 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9067 mutex_unlock(&dev_priv->fb_tracking.lock);
9068
9069 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9070
9071 intel_edp_psr_flush(dev, frontbuffer_bits);
9072 }
9073
9074 /**
9075 * intel_fb_obj_flush - flush frontbuffer object
9076 * @obj: GEM object to flush
9077 * @retire: set when retiring asynchronous rendering
9078 *
9079 * This function gets called every time rendering on the given object has
9080 * completed and frontbuffer caching can be started again. If @retire is true
9081 * then any delayed flushes will be unblocked.
9082 */
9083 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9084 bool retire)
9085 {
9086 struct drm_device *dev = obj->base.dev;
9087 struct drm_i915_private *dev_priv = dev->dev_private;
9088 unsigned frontbuffer_bits;
9089
9090 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9091
9092 if (!obj->frontbuffer_bits)
9093 return;
9094
9095 frontbuffer_bits = obj->frontbuffer_bits;
9096
9097 if (retire) {
9098 mutex_lock(&dev_priv->fb_tracking.lock);
9099 /* Filter out new bits since rendering started. */
9100 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9101
9102 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9103 mutex_unlock(&dev_priv->fb_tracking.lock);
9104 }
9105
9106 intel_frontbuffer_flush(dev, frontbuffer_bits);
9107 }
9108
9109 /**
9110 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9111 * @dev: DRM device
9112 * @frontbuffer_bits: frontbuffer plane tracking bits
9113 *
9114 * This function gets called after scheduling a flip on @obj. The actual
9115 * frontbuffer flushing will be delayed until completion is signalled with
9116 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9117 * flush will be cancelled.
9118 *
9119 * Can be called without any locks held.
9120 */
9121 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9122 unsigned frontbuffer_bits)
9123 {
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125
9126 mutex_lock(&dev_priv->fb_tracking.lock);
9127 dev_priv->fb_tracking.flip_bits
9128 |= frontbuffer_bits;
9129 mutex_unlock(&dev_priv->fb_tracking.lock);
9130 }
9131
9132 /**
9133 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9134 * @dev: DRM device
9135 * @frontbuffer_bits: frontbuffer plane tracking bits
9136 *
9137 * This function gets called after the flip has been latched and will complete
9138 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9139 *
9140 * Can be called without any locks held.
9141 */
9142 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9143 unsigned frontbuffer_bits)
9144 {
9145 struct drm_i915_private *dev_priv = dev->dev_private;
9146
9147 mutex_lock(&dev_priv->fb_tracking.lock);
9148 /* Mask any cancelled flips. */
9149 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9150 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9151 mutex_unlock(&dev_priv->fb_tracking.lock);
9152
9153 intel_frontbuffer_flush(dev, frontbuffer_bits);
9154 }
9155
9156 static void intel_crtc_destroy(struct drm_crtc *crtc)
9157 {
9158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9159 struct drm_device *dev = crtc->dev;
9160 struct intel_unpin_work *work;
9161 unsigned long flags;
9162
9163 spin_lock_irqsave(&dev->event_lock, flags);
9164 work = intel_crtc->unpin_work;
9165 intel_crtc->unpin_work = NULL;
9166 spin_unlock_irqrestore(&dev->event_lock, flags);
9167
9168 if (work) {
9169 cancel_work_sync(&work->work);
9170 kfree(work);
9171 }
9172
9173 drm_crtc_cleanup(crtc);
9174
9175 kfree(intel_crtc);
9176 }
9177
9178 static void intel_unpin_work_fn(struct work_struct *__work)
9179 {
9180 struct intel_unpin_work *work =
9181 container_of(__work, struct intel_unpin_work, work);
9182 struct drm_device *dev = work->crtc->dev;
9183 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9184
9185 mutex_lock(&dev->struct_mutex);
9186 intel_unpin_fb_obj(work->old_fb_obj);
9187 drm_gem_object_unreference(&work->pending_flip_obj->base);
9188 drm_gem_object_unreference(&work->old_fb_obj->base);
9189
9190 intel_update_fbc(dev);
9191 mutex_unlock(&dev->struct_mutex);
9192
9193 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9194
9195 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9196 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9197
9198 kfree(work);
9199 }
9200
9201 static void do_intel_finish_page_flip(struct drm_device *dev,
9202 struct drm_crtc *crtc)
9203 {
9204 struct drm_i915_private *dev_priv = dev->dev_private;
9205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9206 struct intel_unpin_work *work;
9207 unsigned long flags;
9208
9209 /* Ignore early vblank irqs */
9210 if (intel_crtc == NULL)
9211 return;
9212
9213 spin_lock_irqsave(&dev->event_lock, flags);
9214 work = intel_crtc->unpin_work;
9215
9216 /* Ensure we don't miss a work->pending update ... */
9217 smp_rmb();
9218
9219 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9220 spin_unlock_irqrestore(&dev->event_lock, flags);
9221 return;
9222 }
9223
9224 /* and that the unpin work is consistent wrt ->pending. */
9225 smp_rmb();
9226
9227 intel_crtc->unpin_work = NULL;
9228
9229 if (work->event)
9230 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9231
9232 drm_crtc_vblank_put(crtc);
9233
9234 spin_unlock_irqrestore(&dev->event_lock, flags);
9235
9236 wake_up_all(&dev_priv->pending_flip_queue);
9237
9238 queue_work(dev_priv->wq, &work->work);
9239
9240 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9241 }
9242
9243 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9244 {
9245 struct drm_i915_private *dev_priv = dev->dev_private;
9246 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9247
9248 do_intel_finish_page_flip(dev, crtc);
9249 }
9250
9251 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9252 {
9253 struct drm_i915_private *dev_priv = dev->dev_private;
9254 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9255
9256 do_intel_finish_page_flip(dev, crtc);
9257 }
9258
9259 /* Is 'a' after or equal to 'b'? */
9260 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9261 {
9262 return !((a - b) & 0x80000000);
9263 }
9264
9265 static bool page_flip_finished(struct intel_crtc *crtc)
9266 {
9267 struct drm_device *dev = crtc->base.dev;
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269
9270 /*
9271 * The relevant registers doen't exist on pre-ctg.
9272 * As the flip done interrupt doesn't trigger for mmio
9273 * flips on gmch platforms, a flip count check isn't
9274 * really needed there. But since ctg has the registers,
9275 * include it in the check anyway.
9276 */
9277 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9278 return true;
9279
9280 /*
9281 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9282 * used the same base address. In that case the mmio flip might
9283 * have completed, but the CS hasn't even executed the flip yet.
9284 *
9285 * A flip count check isn't enough as the CS might have updated
9286 * the base address just after start of vblank, but before we
9287 * managed to process the interrupt. This means we'd complete the
9288 * CS flip too soon.
9289 *
9290 * Combining both checks should get us a good enough result. It may
9291 * still happen that the CS flip has been executed, but has not
9292 * yet actually completed. But in case the base address is the same
9293 * anyway, we don't really care.
9294 */
9295 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9296 crtc->unpin_work->gtt_offset &&
9297 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9298 crtc->unpin_work->flip_count);
9299 }
9300
9301 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9302 {
9303 struct drm_i915_private *dev_priv = dev->dev_private;
9304 struct intel_crtc *intel_crtc =
9305 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9306 unsigned long flags;
9307
9308 /* NB: An MMIO update of the plane base pointer will also
9309 * generate a page-flip completion irq, i.e. every modeset
9310 * is also accompanied by a spurious intel_prepare_page_flip().
9311 */
9312 spin_lock_irqsave(&dev->event_lock, flags);
9313 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9314 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9315 spin_unlock_irqrestore(&dev->event_lock, flags);
9316 }
9317
9318 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9319 {
9320 /* Ensure that the work item is consistent when activating it ... */
9321 smp_wmb();
9322 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9323 /* and that it is marked active as soon as the irq could fire. */
9324 smp_wmb();
9325 }
9326
9327 static int intel_gen2_queue_flip(struct drm_device *dev,
9328 struct drm_crtc *crtc,
9329 struct drm_framebuffer *fb,
9330 struct drm_i915_gem_object *obj,
9331 struct intel_engine_cs *ring,
9332 uint32_t flags)
9333 {
9334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9335 u32 flip_mask;
9336 int ret;
9337
9338 ret = intel_ring_begin(ring, 6);
9339 if (ret)
9340 return ret;
9341
9342 /* Can't queue multiple flips, so wait for the previous
9343 * one to finish before executing the next.
9344 */
9345 if (intel_crtc->plane)
9346 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9347 else
9348 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9349 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9350 intel_ring_emit(ring, MI_NOOP);
9351 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9352 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9353 intel_ring_emit(ring, fb->pitches[0]);
9354 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9355 intel_ring_emit(ring, 0); /* aux display base address, unused */
9356
9357 intel_mark_page_flip_active(intel_crtc);
9358 __intel_ring_advance(ring);
9359 return 0;
9360 }
9361
9362 static int intel_gen3_queue_flip(struct drm_device *dev,
9363 struct drm_crtc *crtc,
9364 struct drm_framebuffer *fb,
9365 struct drm_i915_gem_object *obj,
9366 struct intel_engine_cs *ring,
9367 uint32_t flags)
9368 {
9369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9370 u32 flip_mask;
9371 int ret;
9372
9373 ret = intel_ring_begin(ring, 6);
9374 if (ret)
9375 return ret;
9376
9377 if (intel_crtc->plane)
9378 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9379 else
9380 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9381 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9382 intel_ring_emit(ring, MI_NOOP);
9383 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9385 intel_ring_emit(ring, fb->pitches[0]);
9386 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9387 intel_ring_emit(ring, MI_NOOP);
9388
9389 intel_mark_page_flip_active(intel_crtc);
9390 __intel_ring_advance(ring);
9391 return 0;
9392 }
9393
9394 static int intel_gen4_queue_flip(struct drm_device *dev,
9395 struct drm_crtc *crtc,
9396 struct drm_framebuffer *fb,
9397 struct drm_i915_gem_object *obj,
9398 struct intel_engine_cs *ring,
9399 uint32_t flags)
9400 {
9401 struct drm_i915_private *dev_priv = dev->dev_private;
9402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9403 uint32_t pf, pipesrc;
9404 int ret;
9405
9406 ret = intel_ring_begin(ring, 4);
9407 if (ret)
9408 return ret;
9409
9410 /* i965+ uses the linear or tiled offsets from the
9411 * Display Registers (which do not change across a page-flip)
9412 * so we need only reprogram the base address.
9413 */
9414 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9415 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9416 intel_ring_emit(ring, fb->pitches[0]);
9417 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9418 obj->tiling_mode);
9419
9420 /* XXX Enabling the panel-fitter across page-flip is so far
9421 * untested on non-native modes, so ignore it for now.
9422 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9423 */
9424 pf = 0;
9425 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9426 intel_ring_emit(ring, pf | pipesrc);
9427
9428 intel_mark_page_flip_active(intel_crtc);
9429 __intel_ring_advance(ring);
9430 return 0;
9431 }
9432
9433 static int intel_gen6_queue_flip(struct drm_device *dev,
9434 struct drm_crtc *crtc,
9435 struct drm_framebuffer *fb,
9436 struct drm_i915_gem_object *obj,
9437 struct intel_engine_cs *ring,
9438 uint32_t flags)
9439 {
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 uint32_t pf, pipesrc;
9443 int ret;
9444
9445 ret = intel_ring_begin(ring, 4);
9446 if (ret)
9447 return ret;
9448
9449 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9450 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9451 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9453
9454 /* Contrary to the suggestions in the documentation,
9455 * "Enable Panel Fitter" does not seem to be required when page
9456 * flipping with a non-native mode, and worse causes a normal
9457 * modeset to fail.
9458 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9459 */
9460 pf = 0;
9461 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9462 intel_ring_emit(ring, pf | pipesrc);
9463
9464 intel_mark_page_flip_active(intel_crtc);
9465 __intel_ring_advance(ring);
9466 return 0;
9467 }
9468
9469 static int intel_gen7_queue_flip(struct drm_device *dev,
9470 struct drm_crtc *crtc,
9471 struct drm_framebuffer *fb,
9472 struct drm_i915_gem_object *obj,
9473 struct intel_engine_cs *ring,
9474 uint32_t flags)
9475 {
9476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9477 uint32_t plane_bit = 0;
9478 int len, ret;
9479
9480 switch (intel_crtc->plane) {
9481 case PLANE_A:
9482 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9483 break;
9484 case PLANE_B:
9485 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9486 break;
9487 case PLANE_C:
9488 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9489 break;
9490 default:
9491 WARN_ONCE(1, "unknown plane in flip command\n");
9492 return -ENODEV;
9493 }
9494
9495 len = 4;
9496 if (ring->id == RCS) {
9497 len += 6;
9498 /*
9499 * On Gen 8, SRM is now taking an extra dword to accommodate
9500 * 48bits addresses, and we need a NOOP for the batch size to
9501 * stay even.
9502 */
9503 if (IS_GEN8(dev))
9504 len += 2;
9505 }
9506
9507 /*
9508 * BSpec MI_DISPLAY_FLIP for IVB:
9509 * "The full packet must be contained within the same cache line."
9510 *
9511 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9512 * cacheline, if we ever start emitting more commands before
9513 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9514 * then do the cacheline alignment, and finally emit the
9515 * MI_DISPLAY_FLIP.
9516 */
9517 ret = intel_ring_cacheline_align(ring);
9518 if (ret)
9519 return ret;
9520
9521 ret = intel_ring_begin(ring, len);
9522 if (ret)
9523 return ret;
9524
9525 /* Unmask the flip-done completion message. Note that the bspec says that
9526 * we should do this for both the BCS and RCS, and that we must not unmask
9527 * more than one flip event at any time (or ensure that one flip message
9528 * can be sent by waiting for flip-done prior to queueing new flips).
9529 * Experimentation says that BCS works despite DERRMR masking all
9530 * flip-done completion events and that unmasking all planes at once
9531 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9532 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9533 */
9534 if (ring->id == RCS) {
9535 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9536 intel_ring_emit(ring, DERRMR);
9537 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9538 DERRMR_PIPEB_PRI_FLIP_DONE |
9539 DERRMR_PIPEC_PRI_FLIP_DONE));
9540 if (IS_GEN8(dev))
9541 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9542 MI_SRM_LRM_GLOBAL_GTT);
9543 else
9544 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9545 MI_SRM_LRM_GLOBAL_GTT);
9546 intel_ring_emit(ring, DERRMR);
9547 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9548 if (IS_GEN8(dev)) {
9549 intel_ring_emit(ring, 0);
9550 intel_ring_emit(ring, MI_NOOP);
9551 }
9552 }
9553
9554 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9555 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9556 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9557 intel_ring_emit(ring, (MI_NOOP));
9558
9559 intel_mark_page_flip_active(intel_crtc);
9560 __intel_ring_advance(ring);
9561 return 0;
9562 }
9563
9564 static bool use_mmio_flip(struct intel_engine_cs *ring,
9565 struct drm_i915_gem_object *obj)
9566 {
9567 /*
9568 * This is not being used for older platforms, because
9569 * non-availability of flip done interrupt forces us to use
9570 * CS flips. Older platforms derive flip done using some clever
9571 * tricks involving the flip_pending status bits and vblank irqs.
9572 * So using MMIO flips there would disrupt this mechanism.
9573 */
9574
9575 if (ring == NULL)
9576 return true;
9577
9578 if (INTEL_INFO(ring->dev)->gen < 5)
9579 return false;
9580
9581 if (i915.use_mmio_flip < 0)
9582 return false;
9583 else if (i915.use_mmio_flip > 0)
9584 return true;
9585 else if (i915.enable_execlists)
9586 return true;
9587 else
9588 return ring != obj->ring;
9589 }
9590
9591 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9592 {
9593 struct drm_device *dev = intel_crtc->base.dev;
9594 struct drm_i915_private *dev_priv = dev->dev_private;
9595 struct intel_framebuffer *intel_fb =
9596 to_intel_framebuffer(intel_crtc->base.primary->fb);
9597 struct drm_i915_gem_object *obj = intel_fb->obj;
9598 u32 dspcntr;
9599 u32 reg;
9600
9601 intel_mark_page_flip_active(intel_crtc);
9602
9603 reg = DSPCNTR(intel_crtc->plane);
9604 dspcntr = I915_READ(reg);
9605
9606 if (INTEL_INFO(dev)->gen >= 4) {
9607 if (obj->tiling_mode != I915_TILING_NONE)
9608 dspcntr |= DISPPLANE_TILED;
9609 else
9610 dspcntr &= ~DISPPLANE_TILED;
9611 }
9612 I915_WRITE(reg, dspcntr);
9613
9614 I915_WRITE(DSPSURF(intel_crtc->plane),
9615 intel_crtc->unpin_work->gtt_offset);
9616 POSTING_READ(DSPSURF(intel_crtc->plane));
9617 }
9618
9619 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9620 {
9621 struct intel_engine_cs *ring;
9622 int ret;
9623
9624 lockdep_assert_held(&obj->base.dev->struct_mutex);
9625
9626 if (!obj->last_write_seqno)
9627 return 0;
9628
9629 ring = obj->ring;
9630
9631 if (i915_seqno_passed(ring->get_seqno(ring, true),
9632 obj->last_write_seqno))
9633 return 0;
9634
9635 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9636 if (ret)
9637 return ret;
9638
9639 if (WARN_ON(!ring->irq_get(ring)))
9640 return 0;
9641
9642 return 1;
9643 }
9644
9645 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9646 {
9647 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9648 struct intel_crtc *intel_crtc;
9649 unsigned long irq_flags;
9650 u32 seqno;
9651
9652 seqno = ring->get_seqno(ring, false);
9653
9654 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9655 for_each_intel_crtc(ring->dev, intel_crtc) {
9656 struct intel_mmio_flip *mmio_flip;
9657
9658 mmio_flip = &intel_crtc->mmio_flip;
9659 if (mmio_flip->seqno == 0)
9660 continue;
9661
9662 if (ring->id != mmio_flip->ring_id)
9663 continue;
9664
9665 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9666 intel_do_mmio_flip(intel_crtc);
9667 mmio_flip->seqno = 0;
9668 ring->irq_put(ring);
9669 }
9670 }
9671 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9672 }
9673
9674 static int intel_queue_mmio_flip(struct drm_device *dev,
9675 struct drm_crtc *crtc,
9676 struct drm_framebuffer *fb,
9677 struct drm_i915_gem_object *obj,
9678 struct intel_engine_cs *ring,
9679 uint32_t flags)
9680 {
9681 struct drm_i915_private *dev_priv = dev->dev_private;
9682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9683 unsigned long irq_flags;
9684 int ret;
9685
9686 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9687 return -EBUSY;
9688
9689 ret = intel_postpone_flip(obj);
9690 if (ret < 0)
9691 return ret;
9692 if (ret == 0) {
9693 intel_do_mmio_flip(intel_crtc);
9694 return 0;
9695 }
9696
9697 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9698 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9699 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9700 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9701
9702 /*
9703 * Double check to catch cases where irq fired before
9704 * mmio flip data was ready
9705 */
9706 intel_notify_mmio_flip(obj->ring);
9707 return 0;
9708 }
9709
9710 static int intel_default_queue_flip(struct drm_device *dev,
9711 struct drm_crtc *crtc,
9712 struct drm_framebuffer *fb,
9713 struct drm_i915_gem_object *obj,
9714 struct intel_engine_cs *ring,
9715 uint32_t flags)
9716 {
9717 return -ENODEV;
9718 }
9719
9720 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9721 struct drm_framebuffer *fb,
9722 struct drm_pending_vblank_event *event,
9723 uint32_t page_flip_flags)
9724 {
9725 struct drm_device *dev = crtc->dev;
9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 struct drm_framebuffer *old_fb = crtc->primary->fb;
9728 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9730 enum pipe pipe = intel_crtc->pipe;
9731 struct intel_unpin_work *work;
9732 struct intel_engine_cs *ring;
9733 unsigned long flags;
9734 int ret;
9735
9736 /*
9737 * drm_mode_page_flip_ioctl() should already catch this, but double
9738 * check to be safe. In the future we may enable pageflipping from
9739 * a disabled primary plane.
9740 */
9741 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9742 return -EBUSY;
9743
9744 /* Can't change pixel format via MI display flips. */
9745 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9746 return -EINVAL;
9747
9748 /*
9749 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9750 * Note that pitch changes could also affect these register.
9751 */
9752 if (INTEL_INFO(dev)->gen > 3 &&
9753 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9754 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9755 return -EINVAL;
9756
9757 if (i915_terminally_wedged(&dev_priv->gpu_error))
9758 goto out_hang;
9759
9760 work = kzalloc(sizeof(*work), GFP_KERNEL);
9761 if (work == NULL)
9762 return -ENOMEM;
9763
9764 work->event = event;
9765 work->crtc = crtc;
9766 work->old_fb_obj = intel_fb_obj(old_fb);
9767 INIT_WORK(&work->work, intel_unpin_work_fn);
9768
9769 ret = drm_crtc_vblank_get(crtc);
9770 if (ret)
9771 goto free_work;
9772
9773 /* We borrow the event spin lock for protecting unpin_work */
9774 spin_lock_irqsave(&dev->event_lock, flags);
9775 if (intel_crtc->unpin_work) {
9776 spin_unlock_irqrestore(&dev->event_lock, flags);
9777 kfree(work);
9778 drm_crtc_vblank_put(crtc);
9779
9780 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9781 return -EBUSY;
9782 }
9783 intel_crtc->unpin_work = work;
9784 spin_unlock_irqrestore(&dev->event_lock, flags);
9785
9786 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9787 flush_workqueue(dev_priv->wq);
9788
9789 ret = i915_mutex_lock_interruptible(dev);
9790 if (ret)
9791 goto cleanup;
9792
9793 /* Reference the objects for the scheduled work. */
9794 drm_gem_object_reference(&work->old_fb_obj->base);
9795 drm_gem_object_reference(&obj->base);
9796
9797 crtc->primary->fb = fb;
9798
9799 work->pending_flip_obj = obj;
9800
9801 work->enable_stall_check = true;
9802
9803 atomic_inc(&intel_crtc->unpin_work_count);
9804 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9805
9806 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9807 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9808
9809 if (IS_VALLEYVIEW(dev)) {
9810 ring = &dev_priv->ring[BCS];
9811 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9812 /* vlv: DISPLAY_FLIP fails to change tiling */
9813 ring = NULL;
9814 } else if (IS_IVYBRIDGE(dev)) {
9815 ring = &dev_priv->ring[BCS];
9816 } else if (INTEL_INFO(dev)->gen >= 7) {
9817 ring = obj->ring;
9818 if (ring == NULL || ring->id != RCS)
9819 ring = &dev_priv->ring[BCS];
9820 } else {
9821 ring = &dev_priv->ring[RCS];
9822 }
9823
9824 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9825 if (ret)
9826 goto cleanup_pending;
9827
9828 work->gtt_offset =
9829 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9830
9831 if (use_mmio_flip(ring, obj))
9832 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9833 page_flip_flags);
9834 else
9835 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9836 page_flip_flags);
9837 if (ret)
9838 goto cleanup_unpin;
9839
9840 i915_gem_track_fb(work->old_fb_obj, obj,
9841 INTEL_FRONTBUFFER_PRIMARY(pipe));
9842
9843 intel_disable_fbc(dev);
9844 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9845 mutex_unlock(&dev->struct_mutex);
9846
9847 trace_i915_flip_request(intel_crtc->plane, obj);
9848
9849 return 0;
9850
9851 cleanup_unpin:
9852 intel_unpin_fb_obj(obj);
9853 cleanup_pending:
9854 atomic_dec(&intel_crtc->unpin_work_count);
9855 crtc->primary->fb = old_fb;
9856 drm_gem_object_unreference(&work->old_fb_obj->base);
9857 drm_gem_object_unreference(&obj->base);
9858 mutex_unlock(&dev->struct_mutex);
9859
9860 cleanup:
9861 spin_lock_irqsave(&dev->event_lock, flags);
9862 intel_crtc->unpin_work = NULL;
9863 spin_unlock_irqrestore(&dev->event_lock, flags);
9864
9865 drm_crtc_vblank_put(crtc);
9866 free_work:
9867 kfree(work);
9868
9869 if (ret == -EIO) {
9870 out_hang:
9871 intel_crtc_wait_for_pending_flips(crtc);
9872 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9873 if (ret == 0 && event)
9874 drm_send_vblank_event(dev, pipe, event);
9875 }
9876 return ret;
9877 }
9878
9879 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9880 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9881 .load_lut = intel_crtc_load_lut,
9882 };
9883
9884 /**
9885 * intel_modeset_update_staged_output_state
9886 *
9887 * Updates the staged output configuration state, e.g. after we've read out the
9888 * current hw state.
9889 */
9890 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9891 {
9892 struct intel_crtc *crtc;
9893 struct intel_encoder *encoder;
9894 struct intel_connector *connector;
9895
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9897 base.head) {
9898 connector->new_encoder =
9899 to_intel_encoder(connector->base.encoder);
9900 }
9901
9902 for_each_intel_encoder(dev, encoder) {
9903 encoder->new_crtc =
9904 to_intel_crtc(encoder->base.crtc);
9905 }
9906
9907 for_each_intel_crtc(dev, crtc) {
9908 crtc->new_enabled = crtc->base.enabled;
9909
9910 if (crtc->new_enabled)
9911 crtc->new_config = &crtc->config;
9912 else
9913 crtc->new_config = NULL;
9914 }
9915 }
9916
9917 /**
9918 * intel_modeset_commit_output_state
9919 *
9920 * This function copies the stage display pipe configuration to the real one.
9921 */
9922 static void intel_modeset_commit_output_state(struct drm_device *dev)
9923 {
9924 struct intel_crtc *crtc;
9925 struct intel_encoder *encoder;
9926 struct intel_connector *connector;
9927
9928 list_for_each_entry(connector, &dev->mode_config.connector_list,
9929 base.head) {
9930 connector->base.encoder = &connector->new_encoder->base;
9931 }
9932
9933 for_each_intel_encoder(dev, encoder) {
9934 encoder->base.crtc = &encoder->new_crtc->base;
9935 }
9936
9937 for_each_intel_crtc(dev, crtc) {
9938 crtc->base.enabled = crtc->new_enabled;
9939 }
9940 }
9941
9942 static void
9943 connected_sink_compute_bpp(struct intel_connector *connector,
9944 struct intel_crtc_config *pipe_config)
9945 {
9946 int bpp = pipe_config->pipe_bpp;
9947
9948 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9949 connector->base.base.id,
9950 connector->base.name);
9951
9952 /* Don't use an invalid EDID bpc value */
9953 if (connector->base.display_info.bpc &&
9954 connector->base.display_info.bpc * 3 < bpp) {
9955 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9956 bpp, connector->base.display_info.bpc*3);
9957 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9958 }
9959
9960 /* Clamp bpp to 8 on screens without EDID 1.4 */
9961 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9962 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9963 bpp);
9964 pipe_config->pipe_bpp = 24;
9965 }
9966 }
9967
9968 static int
9969 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9970 struct drm_framebuffer *fb,
9971 struct intel_crtc_config *pipe_config)
9972 {
9973 struct drm_device *dev = crtc->base.dev;
9974 struct intel_connector *connector;
9975 int bpp;
9976
9977 switch (fb->pixel_format) {
9978 case DRM_FORMAT_C8:
9979 bpp = 8*3; /* since we go through a colormap */
9980 break;
9981 case DRM_FORMAT_XRGB1555:
9982 case DRM_FORMAT_ARGB1555:
9983 /* checked in intel_framebuffer_init already */
9984 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9985 return -EINVAL;
9986 case DRM_FORMAT_RGB565:
9987 bpp = 6*3; /* min is 18bpp */
9988 break;
9989 case DRM_FORMAT_XBGR8888:
9990 case DRM_FORMAT_ABGR8888:
9991 /* checked in intel_framebuffer_init already */
9992 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9993 return -EINVAL;
9994 case DRM_FORMAT_XRGB8888:
9995 case DRM_FORMAT_ARGB8888:
9996 bpp = 8*3;
9997 break;
9998 case DRM_FORMAT_XRGB2101010:
9999 case DRM_FORMAT_ARGB2101010:
10000 case DRM_FORMAT_XBGR2101010:
10001 case DRM_FORMAT_ABGR2101010:
10002 /* checked in intel_framebuffer_init already */
10003 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10004 return -EINVAL;
10005 bpp = 10*3;
10006 break;
10007 /* TODO: gen4+ supports 16 bpc floating point, too. */
10008 default:
10009 DRM_DEBUG_KMS("unsupported depth\n");
10010 return -EINVAL;
10011 }
10012
10013 pipe_config->pipe_bpp = bpp;
10014
10015 /* Clamp display bpp to EDID value */
10016 list_for_each_entry(connector, &dev->mode_config.connector_list,
10017 base.head) {
10018 if (!connector->new_encoder ||
10019 connector->new_encoder->new_crtc != crtc)
10020 continue;
10021
10022 connected_sink_compute_bpp(connector, pipe_config);
10023 }
10024
10025 return bpp;
10026 }
10027
10028 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10029 {
10030 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10031 "type: 0x%x flags: 0x%x\n",
10032 mode->crtc_clock,
10033 mode->crtc_hdisplay, mode->crtc_hsync_start,
10034 mode->crtc_hsync_end, mode->crtc_htotal,
10035 mode->crtc_vdisplay, mode->crtc_vsync_start,
10036 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10037 }
10038
10039 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10040 struct intel_crtc_config *pipe_config,
10041 const char *context)
10042 {
10043 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10044 context, pipe_name(crtc->pipe));
10045
10046 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10047 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10048 pipe_config->pipe_bpp, pipe_config->dither);
10049 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10050 pipe_config->has_pch_encoder,
10051 pipe_config->fdi_lanes,
10052 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10053 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10054 pipe_config->fdi_m_n.tu);
10055 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10056 pipe_config->has_dp_encoder,
10057 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10058 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10059 pipe_config->dp_m_n.tu);
10060
10061 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10062 pipe_config->has_dp_encoder,
10063 pipe_config->dp_m2_n2.gmch_m,
10064 pipe_config->dp_m2_n2.gmch_n,
10065 pipe_config->dp_m2_n2.link_m,
10066 pipe_config->dp_m2_n2.link_n,
10067 pipe_config->dp_m2_n2.tu);
10068
10069 DRM_DEBUG_KMS("requested mode:\n");
10070 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10071 DRM_DEBUG_KMS("adjusted mode:\n");
10072 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10073 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10074 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10075 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10076 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10077 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10078 pipe_config->gmch_pfit.control,
10079 pipe_config->gmch_pfit.pgm_ratios,
10080 pipe_config->gmch_pfit.lvds_border_bits);
10081 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10082 pipe_config->pch_pfit.pos,
10083 pipe_config->pch_pfit.size,
10084 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10085 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10086 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10087 }
10088
10089 static bool encoders_cloneable(const struct intel_encoder *a,
10090 const struct intel_encoder *b)
10091 {
10092 /* masks could be asymmetric, so check both ways */
10093 return a == b || (a->cloneable & (1 << b->type) &&
10094 b->cloneable & (1 << a->type));
10095 }
10096
10097 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10098 struct intel_encoder *encoder)
10099 {
10100 struct drm_device *dev = crtc->base.dev;
10101 struct intel_encoder *source_encoder;
10102
10103 for_each_intel_encoder(dev, source_encoder) {
10104 if (source_encoder->new_crtc != crtc)
10105 continue;
10106
10107 if (!encoders_cloneable(encoder, source_encoder))
10108 return false;
10109 }
10110
10111 return true;
10112 }
10113
10114 static bool check_encoder_cloning(struct intel_crtc *crtc)
10115 {
10116 struct drm_device *dev = crtc->base.dev;
10117 struct intel_encoder *encoder;
10118
10119 for_each_intel_encoder(dev, encoder) {
10120 if (encoder->new_crtc != crtc)
10121 continue;
10122
10123 if (!check_single_encoder_cloning(crtc, encoder))
10124 return false;
10125 }
10126
10127 return true;
10128 }
10129
10130 static struct intel_crtc_config *
10131 intel_modeset_pipe_config(struct drm_crtc *crtc,
10132 struct drm_framebuffer *fb,
10133 struct drm_display_mode *mode)
10134 {
10135 struct drm_device *dev = crtc->dev;
10136 struct intel_encoder *encoder;
10137 struct intel_crtc_config *pipe_config;
10138 int plane_bpp, ret = -EINVAL;
10139 bool retry = true;
10140
10141 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10142 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10143 return ERR_PTR(-EINVAL);
10144 }
10145
10146 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10147 if (!pipe_config)
10148 return ERR_PTR(-ENOMEM);
10149
10150 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10151 drm_mode_copy(&pipe_config->requested_mode, mode);
10152
10153 pipe_config->cpu_transcoder =
10154 (enum transcoder) to_intel_crtc(crtc)->pipe;
10155 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10156
10157 /*
10158 * Sanitize sync polarity flags based on requested ones. If neither
10159 * positive or negative polarity is requested, treat this as meaning
10160 * negative polarity.
10161 */
10162 if (!(pipe_config->adjusted_mode.flags &
10163 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10164 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10165
10166 if (!(pipe_config->adjusted_mode.flags &
10167 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10168 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10169
10170 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10171 * plane pixel format and any sink constraints into account. Returns the
10172 * source plane bpp so that dithering can be selected on mismatches
10173 * after encoders and crtc also have had their say. */
10174 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10175 fb, pipe_config);
10176 if (plane_bpp < 0)
10177 goto fail;
10178
10179 /*
10180 * Determine the real pipe dimensions. Note that stereo modes can
10181 * increase the actual pipe size due to the frame doubling and
10182 * insertion of additional space for blanks between the frame. This
10183 * is stored in the crtc timings. We use the requested mode to do this
10184 * computation to clearly distinguish it from the adjusted mode, which
10185 * can be changed by the connectors in the below retry loop.
10186 */
10187 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10188 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10189 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10190
10191 encoder_retry:
10192 /* Ensure the port clock defaults are reset when retrying. */
10193 pipe_config->port_clock = 0;
10194 pipe_config->pixel_multiplier = 1;
10195
10196 /* Fill in default crtc timings, allow encoders to overwrite them. */
10197 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10198
10199 /* Pass our mode to the connectors and the CRTC to give them a chance to
10200 * adjust it according to limitations or connector properties, and also
10201 * a chance to reject the mode entirely.
10202 */
10203 for_each_intel_encoder(dev, encoder) {
10204
10205 if (&encoder->new_crtc->base != crtc)
10206 continue;
10207
10208 if (!(encoder->compute_config(encoder, pipe_config))) {
10209 DRM_DEBUG_KMS("Encoder config failure\n");
10210 goto fail;
10211 }
10212 }
10213
10214 /* Set default port clock if not overwritten by the encoder. Needs to be
10215 * done afterwards in case the encoder adjusts the mode. */
10216 if (!pipe_config->port_clock)
10217 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10218 * pipe_config->pixel_multiplier;
10219
10220 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10221 if (ret < 0) {
10222 DRM_DEBUG_KMS("CRTC fixup failed\n");
10223 goto fail;
10224 }
10225
10226 if (ret == RETRY) {
10227 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10228 ret = -EINVAL;
10229 goto fail;
10230 }
10231
10232 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10233 retry = false;
10234 goto encoder_retry;
10235 }
10236
10237 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10238 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10239 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10240
10241 return pipe_config;
10242 fail:
10243 kfree(pipe_config);
10244 return ERR_PTR(ret);
10245 }
10246
10247 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10248 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10249 static void
10250 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10251 unsigned *prepare_pipes, unsigned *disable_pipes)
10252 {
10253 struct intel_crtc *intel_crtc;
10254 struct drm_device *dev = crtc->dev;
10255 struct intel_encoder *encoder;
10256 struct intel_connector *connector;
10257 struct drm_crtc *tmp_crtc;
10258
10259 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10260
10261 /* Check which crtcs have changed outputs connected to them, these need
10262 * to be part of the prepare_pipes mask. We don't (yet) support global
10263 * modeset across multiple crtcs, so modeset_pipes will only have one
10264 * bit set at most. */
10265 list_for_each_entry(connector, &dev->mode_config.connector_list,
10266 base.head) {
10267 if (connector->base.encoder == &connector->new_encoder->base)
10268 continue;
10269
10270 if (connector->base.encoder) {
10271 tmp_crtc = connector->base.encoder->crtc;
10272
10273 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10274 }
10275
10276 if (connector->new_encoder)
10277 *prepare_pipes |=
10278 1 << connector->new_encoder->new_crtc->pipe;
10279 }
10280
10281 for_each_intel_encoder(dev, encoder) {
10282 if (encoder->base.crtc == &encoder->new_crtc->base)
10283 continue;
10284
10285 if (encoder->base.crtc) {
10286 tmp_crtc = encoder->base.crtc;
10287
10288 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10289 }
10290
10291 if (encoder->new_crtc)
10292 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10293 }
10294
10295 /* Check for pipes that will be enabled/disabled ... */
10296 for_each_intel_crtc(dev, intel_crtc) {
10297 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10298 continue;
10299
10300 if (!intel_crtc->new_enabled)
10301 *disable_pipes |= 1 << intel_crtc->pipe;
10302 else
10303 *prepare_pipes |= 1 << intel_crtc->pipe;
10304 }
10305
10306
10307 /* set_mode is also used to update properties on life display pipes. */
10308 intel_crtc = to_intel_crtc(crtc);
10309 if (intel_crtc->new_enabled)
10310 *prepare_pipes |= 1 << intel_crtc->pipe;
10311
10312 /*
10313 * For simplicity do a full modeset on any pipe where the output routing
10314 * changed. We could be more clever, but that would require us to be
10315 * more careful with calling the relevant encoder->mode_set functions.
10316 */
10317 if (*prepare_pipes)
10318 *modeset_pipes = *prepare_pipes;
10319
10320 /* ... and mask these out. */
10321 *modeset_pipes &= ~(*disable_pipes);
10322 *prepare_pipes &= ~(*disable_pipes);
10323
10324 /*
10325 * HACK: We don't (yet) fully support global modesets. intel_set_config
10326 * obies this rule, but the modeset restore mode of
10327 * intel_modeset_setup_hw_state does not.
10328 */
10329 *modeset_pipes &= 1 << intel_crtc->pipe;
10330 *prepare_pipes &= 1 << intel_crtc->pipe;
10331
10332 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10333 *modeset_pipes, *prepare_pipes, *disable_pipes);
10334 }
10335
10336 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10337 {
10338 struct drm_encoder *encoder;
10339 struct drm_device *dev = crtc->dev;
10340
10341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10342 if (encoder->crtc == crtc)
10343 return true;
10344
10345 return false;
10346 }
10347
10348 static void
10349 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10350 {
10351 struct intel_encoder *intel_encoder;
10352 struct intel_crtc *intel_crtc;
10353 struct drm_connector *connector;
10354
10355 for_each_intel_encoder(dev, intel_encoder) {
10356 if (!intel_encoder->base.crtc)
10357 continue;
10358
10359 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10360
10361 if (prepare_pipes & (1 << intel_crtc->pipe))
10362 intel_encoder->connectors_active = false;
10363 }
10364
10365 intel_modeset_commit_output_state(dev);
10366
10367 /* Double check state. */
10368 for_each_intel_crtc(dev, intel_crtc) {
10369 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10370 WARN_ON(intel_crtc->new_config &&
10371 intel_crtc->new_config != &intel_crtc->config);
10372 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10373 }
10374
10375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10376 if (!connector->encoder || !connector->encoder->crtc)
10377 continue;
10378
10379 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10380
10381 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10382 struct drm_property *dpms_property =
10383 dev->mode_config.dpms_property;
10384
10385 connector->dpms = DRM_MODE_DPMS_ON;
10386 drm_object_property_set_value(&connector->base,
10387 dpms_property,
10388 DRM_MODE_DPMS_ON);
10389
10390 intel_encoder = to_intel_encoder(connector->encoder);
10391 intel_encoder->connectors_active = true;
10392 }
10393 }
10394
10395 }
10396
10397 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10398 {
10399 int diff;
10400
10401 if (clock1 == clock2)
10402 return true;
10403
10404 if (!clock1 || !clock2)
10405 return false;
10406
10407 diff = abs(clock1 - clock2);
10408
10409 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10410 return true;
10411
10412 return false;
10413 }
10414
10415 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10416 list_for_each_entry((intel_crtc), \
10417 &(dev)->mode_config.crtc_list, \
10418 base.head) \
10419 if (mask & (1 <<(intel_crtc)->pipe))
10420
10421 static bool
10422 intel_pipe_config_compare(struct drm_device *dev,
10423 struct intel_crtc_config *current_config,
10424 struct intel_crtc_config *pipe_config)
10425 {
10426 #define PIPE_CONF_CHECK_X(name) \
10427 if (current_config->name != pipe_config->name) { \
10428 DRM_ERROR("mismatch in " #name " " \
10429 "(expected 0x%08x, found 0x%08x)\n", \
10430 current_config->name, \
10431 pipe_config->name); \
10432 return false; \
10433 }
10434
10435 #define PIPE_CONF_CHECK_I(name) \
10436 if (current_config->name != pipe_config->name) { \
10437 DRM_ERROR("mismatch in " #name " " \
10438 "(expected %i, found %i)\n", \
10439 current_config->name, \
10440 pipe_config->name); \
10441 return false; \
10442 }
10443
10444 /* This is required for BDW+ where there is only one set of registers for
10445 * switching between high and low RR.
10446 * This macro can be used whenever a comparison has to be made between one
10447 * hw state and multiple sw state variables.
10448 */
10449 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10450 if ((current_config->name != pipe_config->name) && \
10451 (current_config->alt_name != pipe_config->name)) { \
10452 DRM_ERROR("mismatch in " #name " " \
10453 "(expected %i or %i, found %i)\n", \
10454 current_config->name, \
10455 current_config->alt_name, \
10456 pipe_config->name); \
10457 return false; \
10458 }
10459
10460 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10461 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10462 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10463 "(expected %i, found %i)\n", \
10464 current_config->name & (mask), \
10465 pipe_config->name & (mask)); \
10466 return false; \
10467 }
10468
10469 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10470 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10471 DRM_ERROR("mismatch in " #name " " \
10472 "(expected %i, found %i)\n", \
10473 current_config->name, \
10474 pipe_config->name); \
10475 return false; \
10476 }
10477
10478 #define PIPE_CONF_QUIRK(quirk) \
10479 ((current_config->quirks | pipe_config->quirks) & (quirk))
10480
10481 PIPE_CONF_CHECK_I(cpu_transcoder);
10482
10483 PIPE_CONF_CHECK_I(has_pch_encoder);
10484 PIPE_CONF_CHECK_I(fdi_lanes);
10485 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10486 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10487 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10488 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10489 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10490
10491 PIPE_CONF_CHECK_I(has_dp_encoder);
10492
10493 if (INTEL_INFO(dev)->gen < 8) {
10494 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10495 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10496 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10497 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10498 PIPE_CONF_CHECK_I(dp_m_n.tu);
10499
10500 if (current_config->has_drrs) {
10501 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10502 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10503 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10504 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10505 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10506 }
10507 } else {
10508 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10509 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10510 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10511 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10512 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10513 }
10514
10515 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10516 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10517 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10518 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10519 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10520 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10521
10522 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10523 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10524 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10525 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10526 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10527 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10528
10529 PIPE_CONF_CHECK_I(pixel_multiplier);
10530 PIPE_CONF_CHECK_I(has_hdmi_sink);
10531 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10532 IS_VALLEYVIEW(dev))
10533 PIPE_CONF_CHECK_I(limited_color_range);
10534
10535 PIPE_CONF_CHECK_I(has_audio);
10536
10537 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10538 DRM_MODE_FLAG_INTERLACE);
10539
10540 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10541 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10542 DRM_MODE_FLAG_PHSYNC);
10543 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10544 DRM_MODE_FLAG_NHSYNC);
10545 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10546 DRM_MODE_FLAG_PVSYNC);
10547 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10548 DRM_MODE_FLAG_NVSYNC);
10549 }
10550
10551 PIPE_CONF_CHECK_I(pipe_src_w);
10552 PIPE_CONF_CHECK_I(pipe_src_h);
10553
10554 /*
10555 * FIXME: BIOS likes to set up a cloned config with lvds+external
10556 * screen. Since we don't yet re-compute the pipe config when moving
10557 * just the lvds port away to another pipe the sw tracking won't match.
10558 *
10559 * Proper atomic modesets with recomputed global state will fix this.
10560 * Until then just don't check gmch state for inherited modes.
10561 */
10562 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10563 PIPE_CONF_CHECK_I(gmch_pfit.control);
10564 /* pfit ratios are autocomputed by the hw on gen4+ */
10565 if (INTEL_INFO(dev)->gen < 4)
10566 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10567 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10568 }
10569
10570 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10571 if (current_config->pch_pfit.enabled) {
10572 PIPE_CONF_CHECK_I(pch_pfit.pos);
10573 PIPE_CONF_CHECK_I(pch_pfit.size);
10574 }
10575
10576 /* BDW+ don't expose a synchronous way to read the state */
10577 if (IS_HASWELL(dev))
10578 PIPE_CONF_CHECK_I(ips_enabled);
10579
10580 PIPE_CONF_CHECK_I(double_wide);
10581
10582 PIPE_CONF_CHECK_X(ddi_pll_sel);
10583
10584 PIPE_CONF_CHECK_I(shared_dpll);
10585 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10586 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10587 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10588 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10589 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10590
10591 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10592 PIPE_CONF_CHECK_I(pipe_bpp);
10593
10594 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10595 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10596
10597 #undef PIPE_CONF_CHECK_X
10598 #undef PIPE_CONF_CHECK_I
10599 #undef PIPE_CONF_CHECK_I_ALT
10600 #undef PIPE_CONF_CHECK_FLAGS
10601 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10602 #undef PIPE_CONF_QUIRK
10603
10604 return true;
10605 }
10606
10607 static void
10608 check_connector_state(struct drm_device *dev)
10609 {
10610 struct intel_connector *connector;
10611
10612 list_for_each_entry(connector, &dev->mode_config.connector_list,
10613 base.head) {
10614 /* This also checks the encoder/connector hw state with the
10615 * ->get_hw_state callbacks. */
10616 intel_connector_check_state(connector);
10617
10618 WARN(&connector->new_encoder->base != connector->base.encoder,
10619 "connector's staged encoder doesn't match current encoder\n");
10620 }
10621 }
10622
10623 static void
10624 check_encoder_state(struct drm_device *dev)
10625 {
10626 struct intel_encoder *encoder;
10627 struct intel_connector *connector;
10628
10629 for_each_intel_encoder(dev, encoder) {
10630 bool enabled = false;
10631 bool active = false;
10632 enum pipe pipe, tracked_pipe;
10633
10634 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10635 encoder->base.base.id,
10636 encoder->base.name);
10637
10638 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10639 "encoder's stage crtc doesn't match current crtc\n");
10640 WARN(encoder->connectors_active && !encoder->base.crtc,
10641 "encoder's active_connectors set, but no crtc\n");
10642
10643 list_for_each_entry(connector, &dev->mode_config.connector_list,
10644 base.head) {
10645 if (connector->base.encoder != &encoder->base)
10646 continue;
10647 enabled = true;
10648 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10649 active = true;
10650 }
10651 /*
10652 * for MST connectors if we unplug the connector is gone
10653 * away but the encoder is still connected to a crtc
10654 * until a modeset happens in response to the hotplug.
10655 */
10656 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10657 continue;
10658
10659 WARN(!!encoder->base.crtc != enabled,
10660 "encoder's enabled state mismatch "
10661 "(expected %i, found %i)\n",
10662 !!encoder->base.crtc, enabled);
10663 WARN(active && !encoder->base.crtc,
10664 "active encoder with no crtc\n");
10665
10666 WARN(encoder->connectors_active != active,
10667 "encoder's computed active state doesn't match tracked active state "
10668 "(expected %i, found %i)\n", active, encoder->connectors_active);
10669
10670 active = encoder->get_hw_state(encoder, &pipe);
10671 WARN(active != encoder->connectors_active,
10672 "encoder's hw state doesn't match sw tracking "
10673 "(expected %i, found %i)\n",
10674 encoder->connectors_active, active);
10675
10676 if (!encoder->base.crtc)
10677 continue;
10678
10679 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10680 WARN(active && pipe != tracked_pipe,
10681 "active encoder's pipe doesn't match"
10682 "(expected %i, found %i)\n",
10683 tracked_pipe, pipe);
10684
10685 }
10686 }
10687
10688 static void
10689 check_crtc_state(struct drm_device *dev)
10690 {
10691 struct drm_i915_private *dev_priv = dev->dev_private;
10692 struct intel_crtc *crtc;
10693 struct intel_encoder *encoder;
10694 struct intel_crtc_config pipe_config;
10695
10696 for_each_intel_crtc(dev, crtc) {
10697 bool enabled = false;
10698 bool active = false;
10699
10700 memset(&pipe_config, 0, sizeof(pipe_config));
10701
10702 DRM_DEBUG_KMS("[CRTC:%d]\n",
10703 crtc->base.base.id);
10704
10705 WARN(crtc->active && !crtc->base.enabled,
10706 "active crtc, but not enabled in sw tracking\n");
10707
10708 for_each_intel_encoder(dev, encoder) {
10709 if (encoder->base.crtc != &crtc->base)
10710 continue;
10711 enabled = true;
10712 if (encoder->connectors_active)
10713 active = true;
10714 }
10715
10716 WARN(active != crtc->active,
10717 "crtc's computed active state doesn't match tracked active state "
10718 "(expected %i, found %i)\n", active, crtc->active);
10719 WARN(enabled != crtc->base.enabled,
10720 "crtc's computed enabled state doesn't match tracked enabled state "
10721 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10722
10723 active = dev_priv->display.get_pipe_config(crtc,
10724 &pipe_config);
10725
10726 /* hw state is inconsistent with the pipe A quirk */
10727 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10728 active = crtc->active;
10729
10730 for_each_intel_encoder(dev, encoder) {
10731 enum pipe pipe;
10732 if (encoder->base.crtc != &crtc->base)
10733 continue;
10734 if (encoder->get_hw_state(encoder, &pipe))
10735 encoder->get_config(encoder, &pipe_config);
10736 }
10737
10738 WARN(crtc->active != active,
10739 "crtc active state doesn't match with hw state "
10740 "(expected %i, found %i)\n", crtc->active, active);
10741
10742 if (active &&
10743 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10744 WARN(1, "pipe state doesn't match!\n");
10745 intel_dump_pipe_config(crtc, &pipe_config,
10746 "[hw state]");
10747 intel_dump_pipe_config(crtc, &crtc->config,
10748 "[sw state]");
10749 }
10750 }
10751 }
10752
10753 static void
10754 check_shared_dpll_state(struct drm_device *dev)
10755 {
10756 struct drm_i915_private *dev_priv = dev->dev_private;
10757 struct intel_crtc *crtc;
10758 struct intel_dpll_hw_state dpll_hw_state;
10759 int i;
10760
10761 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10762 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10763 int enabled_crtcs = 0, active_crtcs = 0;
10764 bool active;
10765
10766 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10767
10768 DRM_DEBUG_KMS("%s\n", pll->name);
10769
10770 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10771
10772 WARN(pll->active > pll->refcount,
10773 "more active pll users than references: %i vs %i\n",
10774 pll->active, pll->refcount);
10775 WARN(pll->active && !pll->on,
10776 "pll in active use but not on in sw tracking\n");
10777 WARN(pll->on && !pll->active,
10778 "pll in on but not on in use in sw tracking\n");
10779 WARN(pll->on != active,
10780 "pll on state mismatch (expected %i, found %i)\n",
10781 pll->on, active);
10782
10783 for_each_intel_crtc(dev, crtc) {
10784 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10785 enabled_crtcs++;
10786 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10787 active_crtcs++;
10788 }
10789 WARN(pll->active != active_crtcs,
10790 "pll active crtcs mismatch (expected %i, found %i)\n",
10791 pll->active, active_crtcs);
10792 WARN(pll->refcount != enabled_crtcs,
10793 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10794 pll->refcount, enabled_crtcs);
10795
10796 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10797 sizeof(dpll_hw_state)),
10798 "pll hw state mismatch\n");
10799 }
10800 }
10801
10802 void
10803 intel_modeset_check_state(struct drm_device *dev)
10804 {
10805 check_connector_state(dev);
10806 check_encoder_state(dev);
10807 check_crtc_state(dev);
10808 check_shared_dpll_state(dev);
10809 }
10810
10811 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10812 int dotclock)
10813 {
10814 /*
10815 * FDI already provided one idea for the dotclock.
10816 * Yell if the encoder disagrees.
10817 */
10818 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10819 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10820 pipe_config->adjusted_mode.crtc_clock, dotclock);
10821 }
10822
10823 static void update_scanline_offset(struct intel_crtc *crtc)
10824 {
10825 struct drm_device *dev = crtc->base.dev;
10826
10827 /*
10828 * The scanline counter increments at the leading edge of hsync.
10829 *
10830 * On most platforms it starts counting from vtotal-1 on the
10831 * first active line. That means the scanline counter value is
10832 * always one less than what we would expect. Ie. just after
10833 * start of vblank, which also occurs at start of hsync (on the
10834 * last active line), the scanline counter will read vblank_start-1.
10835 *
10836 * On gen2 the scanline counter starts counting from 1 instead
10837 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10838 * to keep the value positive), instead of adding one.
10839 *
10840 * On HSW+ the behaviour of the scanline counter depends on the output
10841 * type. For DP ports it behaves like most other platforms, but on HDMI
10842 * there's an extra 1 line difference. So we need to add two instead of
10843 * one to the value.
10844 */
10845 if (IS_GEN2(dev)) {
10846 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10847 int vtotal;
10848
10849 vtotal = mode->crtc_vtotal;
10850 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10851 vtotal /= 2;
10852
10853 crtc->scanline_offset = vtotal - 1;
10854 } else if (HAS_DDI(dev) &&
10855 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10856 crtc->scanline_offset = 2;
10857 } else
10858 crtc->scanline_offset = 1;
10859 }
10860
10861 static int __intel_set_mode(struct drm_crtc *crtc,
10862 struct drm_display_mode *mode,
10863 int x, int y, struct drm_framebuffer *fb)
10864 {
10865 struct drm_device *dev = crtc->dev;
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867 struct drm_display_mode *saved_mode;
10868 struct intel_crtc_config *pipe_config = NULL;
10869 struct intel_crtc *intel_crtc;
10870 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10871 int ret = 0;
10872
10873 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10874 if (!saved_mode)
10875 return -ENOMEM;
10876
10877 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10878 &prepare_pipes, &disable_pipes);
10879
10880 *saved_mode = crtc->mode;
10881
10882 /* Hack: Because we don't (yet) support global modeset on multiple
10883 * crtcs, we don't keep track of the new mode for more than one crtc.
10884 * Hence simply check whether any bit is set in modeset_pipes in all the
10885 * pieces of code that are not yet converted to deal with mutliple crtcs
10886 * changing their mode at the same time. */
10887 if (modeset_pipes) {
10888 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10889 if (IS_ERR(pipe_config)) {
10890 ret = PTR_ERR(pipe_config);
10891 pipe_config = NULL;
10892
10893 goto out;
10894 }
10895 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10896 "[modeset]");
10897 to_intel_crtc(crtc)->new_config = pipe_config;
10898 }
10899
10900 /*
10901 * See if the config requires any additional preparation, e.g.
10902 * to adjust global state with pipes off. We need to do this
10903 * here so we can get the modeset_pipe updated config for the new
10904 * mode set on this crtc. For other crtcs we need to use the
10905 * adjusted_mode bits in the crtc directly.
10906 */
10907 if (IS_VALLEYVIEW(dev)) {
10908 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10909
10910 /* may have added more to prepare_pipes than we should */
10911 prepare_pipes &= ~disable_pipes;
10912 }
10913
10914 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10915 intel_crtc_disable(&intel_crtc->base);
10916
10917 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10918 if (intel_crtc->base.enabled)
10919 dev_priv->display.crtc_disable(&intel_crtc->base);
10920 }
10921
10922 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10923 * to set it here already despite that we pass it down the callchain.
10924 */
10925 if (modeset_pipes) {
10926 crtc->mode = *mode;
10927 /* mode_set/enable/disable functions rely on a correct pipe
10928 * config. */
10929 to_intel_crtc(crtc)->config = *pipe_config;
10930 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10931
10932 /*
10933 * Calculate and store various constants which
10934 * are later needed by vblank and swap-completion
10935 * timestamping. They are derived from true hwmode.
10936 */
10937 drm_calc_timestamping_constants(crtc,
10938 &pipe_config->adjusted_mode);
10939 }
10940
10941 /* Only after disabling all output pipelines that will be changed can we
10942 * update the the output configuration. */
10943 intel_modeset_update_state(dev, prepare_pipes);
10944
10945 if (dev_priv->display.modeset_global_resources)
10946 dev_priv->display.modeset_global_resources(dev);
10947
10948 /* Set up the DPLL and any encoders state that needs to adjust or depend
10949 * on the DPLL.
10950 */
10951 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10952 struct drm_framebuffer *old_fb = crtc->primary->fb;
10953 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10954 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10955
10956 mutex_lock(&dev->struct_mutex);
10957 ret = intel_pin_and_fence_fb_obj(dev,
10958 obj,
10959 NULL);
10960 if (ret != 0) {
10961 DRM_ERROR("pin & fence failed\n");
10962 mutex_unlock(&dev->struct_mutex);
10963 goto done;
10964 }
10965 if (old_fb)
10966 intel_unpin_fb_obj(old_obj);
10967 i915_gem_track_fb(old_obj, obj,
10968 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10969 mutex_unlock(&dev->struct_mutex);
10970
10971 crtc->primary->fb = fb;
10972 crtc->x = x;
10973 crtc->y = y;
10974
10975 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10976 x, y, fb);
10977 if (ret)
10978 goto done;
10979 }
10980
10981 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10982 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10983 update_scanline_offset(intel_crtc);
10984
10985 dev_priv->display.crtc_enable(&intel_crtc->base);
10986 }
10987
10988 /* FIXME: add subpixel order */
10989 done:
10990 if (ret && crtc->enabled)
10991 crtc->mode = *saved_mode;
10992
10993 out:
10994 kfree(pipe_config);
10995 kfree(saved_mode);
10996 return ret;
10997 }
10998
10999 static int intel_set_mode(struct drm_crtc *crtc,
11000 struct drm_display_mode *mode,
11001 int x, int y, struct drm_framebuffer *fb)
11002 {
11003 int ret;
11004
11005 ret = __intel_set_mode(crtc, mode, x, y, fb);
11006
11007 if (ret == 0)
11008 intel_modeset_check_state(crtc->dev);
11009
11010 return ret;
11011 }
11012
11013 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11014 {
11015 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11016 }
11017
11018 #undef for_each_intel_crtc_masked
11019
11020 static void intel_set_config_free(struct intel_set_config *config)
11021 {
11022 if (!config)
11023 return;
11024
11025 kfree(config->save_connector_encoders);
11026 kfree(config->save_encoder_crtcs);
11027 kfree(config->save_crtc_enabled);
11028 kfree(config);
11029 }
11030
11031 static int intel_set_config_save_state(struct drm_device *dev,
11032 struct intel_set_config *config)
11033 {
11034 struct drm_crtc *crtc;
11035 struct drm_encoder *encoder;
11036 struct drm_connector *connector;
11037 int count;
11038
11039 config->save_crtc_enabled =
11040 kcalloc(dev->mode_config.num_crtc,
11041 sizeof(bool), GFP_KERNEL);
11042 if (!config->save_crtc_enabled)
11043 return -ENOMEM;
11044
11045 config->save_encoder_crtcs =
11046 kcalloc(dev->mode_config.num_encoder,
11047 sizeof(struct drm_crtc *), GFP_KERNEL);
11048 if (!config->save_encoder_crtcs)
11049 return -ENOMEM;
11050
11051 config->save_connector_encoders =
11052 kcalloc(dev->mode_config.num_connector,
11053 sizeof(struct drm_encoder *), GFP_KERNEL);
11054 if (!config->save_connector_encoders)
11055 return -ENOMEM;
11056
11057 /* Copy data. Note that driver private data is not affected.
11058 * Should anything bad happen only the expected state is
11059 * restored, not the drivers personal bookkeeping.
11060 */
11061 count = 0;
11062 for_each_crtc(dev, crtc) {
11063 config->save_crtc_enabled[count++] = crtc->enabled;
11064 }
11065
11066 count = 0;
11067 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11068 config->save_encoder_crtcs[count++] = encoder->crtc;
11069 }
11070
11071 count = 0;
11072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11073 config->save_connector_encoders[count++] = connector->encoder;
11074 }
11075
11076 return 0;
11077 }
11078
11079 static void intel_set_config_restore_state(struct drm_device *dev,
11080 struct intel_set_config *config)
11081 {
11082 struct intel_crtc *crtc;
11083 struct intel_encoder *encoder;
11084 struct intel_connector *connector;
11085 int count;
11086
11087 count = 0;
11088 for_each_intel_crtc(dev, crtc) {
11089 crtc->new_enabled = config->save_crtc_enabled[count++];
11090
11091 if (crtc->new_enabled)
11092 crtc->new_config = &crtc->config;
11093 else
11094 crtc->new_config = NULL;
11095 }
11096
11097 count = 0;
11098 for_each_intel_encoder(dev, encoder) {
11099 encoder->new_crtc =
11100 to_intel_crtc(config->save_encoder_crtcs[count++]);
11101 }
11102
11103 count = 0;
11104 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11105 connector->new_encoder =
11106 to_intel_encoder(config->save_connector_encoders[count++]);
11107 }
11108 }
11109
11110 static bool
11111 is_crtc_connector_off(struct drm_mode_set *set)
11112 {
11113 int i;
11114
11115 if (set->num_connectors == 0)
11116 return false;
11117
11118 if (WARN_ON(set->connectors == NULL))
11119 return false;
11120
11121 for (i = 0; i < set->num_connectors; i++)
11122 if (set->connectors[i]->encoder &&
11123 set->connectors[i]->encoder->crtc == set->crtc &&
11124 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11125 return true;
11126
11127 return false;
11128 }
11129
11130 static void
11131 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11132 struct intel_set_config *config)
11133 {
11134
11135 /* We should be able to check here if the fb has the same properties
11136 * and then just flip_or_move it */
11137 if (is_crtc_connector_off(set)) {
11138 config->mode_changed = true;
11139 } else if (set->crtc->primary->fb != set->fb) {
11140 /*
11141 * If we have no fb, we can only flip as long as the crtc is
11142 * active, otherwise we need a full mode set. The crtc may
11143 * be active if we've only disabled the primary plane, or
11144 * in fastboot situations.
11145 */
11146 if (set->crtc->primary->fb == NULL) {
11147 struct intel_crtc *intel_crtc =
11148 to_intel_crtc(set->crtc);
11149
11150 if (intel_crtc->active) {
11151 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11152 config->fb_changed = true;
11153 } else {
11154 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11155 config->mode_changed = true;
11156 }
11157 } else if (set->fb == NULL) {
11158 config->mode_changed = true;
11159 } else if (set->fb->pixel_format !=
11160 set->crtc->primary->fb->pixel_format) {
11161 config->mode_changed = true;
11162 } else {
11163 config->fb_changed = true;
11164 }
11165 }
11166
11167 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11168 config->fb_changed = true;
11169
11170 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11171 DRM_DEBUG_KMS("modes are different, full mode set\n");
11172 drm_mode_debug_printmodeline(&set->crtc->mode);
11173 drm_mode_debug_printmodeline(set->mode);
11174 config->mode_changed = true;
11175 }
11176
11177 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11178 set->crtc->base.id, config->mode_changed, config->fb_changed);
11179 }
11180
11181 static int
11182 intel_modeset_stage_output_state(struct drm_device *dev,
11183 struct drm_mode_set *set,
11184 struct intel_set_config *config)
11185 {
11186 struct intel_connector *connector;
11187 struct intel_encoder *encoder;
11188 struct intel_crtc *crtc;
11189 int ro;
11190
11191 /* The upper layers ensure that we either disable a crtc or have a list
11192 * of connectors. For paranoia, double-check this. */
11193 WARN_ON(!set->fb && (set->num_connectors != 0));
11194 WARN_ON(set->fb && (set->num_connectors == 0));
11195
11196 list_for_each_entry(connector, &dev->mode_config.connector_list,
11197 base.head) {
11198 /* Otherwise traverse passed in connector list and get encoders
11199 * for them. */
11200 for (ro = 0; ro < set->num_connectors; ro++) {
11201 if (set->connectors[ro] == &connector->base) {
11202 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11203 break;
11204 }
11205 }
11206
11207 /* If we disable the crtc, disable all its connectors. Also, if
11208 * the connector is on the changing crtc but not on the new
11209 * connector list, disable it. */
11210 if ((!set->fb || ro == set->num_connectors) &&
11211 connector->base.encoder &&
11212 connector->base.encoder->crtc == set->crtc) {
11213 connector->new_encoder = NULL;
11214
11215 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11216 connector->base.base.id,
11217 connector->base.name);
11218 }
11219
11220
11221 if (&connector->new_encoder->base != connector->base.encoder) {
11222 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11223 config->mode_changed = true;
11224 }
11225 }
11226 /* connector->new_encoder is now updated for all connectors. */
11227
11228 /* Update crtc of enabled connectors. */
11229 list_for_each_entry(connector, &dev->mode_config.connector_list,
11230 base.head) {
11231 struct drm_crtc *new_crtc;
11232
11233 if (!connector->new_encoder)
11234 continue;
11235
11236 new_crtc = connector->new_encoder->base.crtc;
11237
11238 for (ro = 0; ro < set->num_connectors; ro++) {
11239 if (set->connectors[ro] == &connector->base)
11240 new_crtc = set->crtc;
11241 }
11242
11243 /* Make sure the new CRTC will work with the encoder */
11244 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11245 new_crtc)) {
11246 return -EINVAL;
11247 }
11248 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11249
11250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11251 connector->base.base.id,
11252 connector->base.name,
11253 new_crtc->base.id);
11254 }
11255
11256 /* Check for any encoders that needs to be disabled. */
11257 for_each_intel_encoder(dev, encoder) {
11258 int num_connectors = 0;
11259 list_for_each_entry(connector,
11260 &dev->mode_config.connector_list,
11261 base.head) {
11262 if (connector->new_encoder == encoder) {
11263 WARN_ON(!connector->new_encoder->new_crtc);
11264 num_connectors++;
11265 }
11266 }
11267
11268 if (num_connectors == 0)
11269 encoder->new_crtc = NULL;
11270 else if (num_connectors > 1)
11271 return -EINVAL;
11272
11273 /* Only now check for crtc changes so we don't miss encoders
11274 * that will be disabled. */
11275 if (&encoder->new_crtc->base != encoder->base.crtc) {
11276 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11277 config->mode_changed = true;
11278 }
11279 }
11280 /* Now we've also updated encoder->new_crtc for all encoders. */
11281 list_for_each_entry(connector, &dev->mode_config.connector_list,
11282 base.head) {
11283 if (connector->new_encoder)
11284 if (connector->new_encoder != connector->encoder)
11285 connector->encoder = connector->new_encoder;
11286 }
11287 for_each_intel_crtc(dev, crtc) {
11288 crtc->new_enabled = false;
11289
11290 for_each_intel_encoder(dev, encoder) {
11291 if (encoder->new_crtc == crtc) {
11292 crtc->new_enabled = true;
11293 break;
11294 }
11295 }
11296
11297 if (crtc->new_enabled != crtc->base.enabled) {
11298 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11299 crtc->new_enabled ? "en" : "dis");
11300 config->mode_changed = true;
11301 }
11302
11303 if (crtc->new_enabled)
11304 crtc->new_config = &crtc->config;
11305 else
11306 crtc->new_config = NULL;
11307 }
11308
11309 return 0;
11310 }
11311
11312 static void disable_crtc_nofb(struct intel_crtc *crtc)
11313 {
11314 struct drm_device *dev = crtc->base.dev;
11315 struct intel_encoder *encoder;
11316 struct intel_connector *connector;
11317
11318 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11319 pipe_name(crtc->pipe));
11320
11321 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11322 if (connector->new_encoder &&
11323 connector->new_encoder->new_crtc == crtc)
11324 connector->new_encoder = NULL;
11325 }
11326
11327 for_each_intel_encoder(dev, encoder) {
11328 if (encoder->new_crtc == crtc)
11329 encoder->new_crtc = NULL;
11330 }
11331
11332 crtc->new_enabled = false;
11333 crtc->new_config = NULL;
11334 }
11335
11336 static int intel_crtc_set_config(struct drm_mode_set *set)
11337 {
11338 struct drm_device *dev;
11339 struct drm_mode_set save_set;
11340 struct intel_set_config *config;
11341 int ret;
11342
11343 BUG_ON(!set);
11344 BUG_ON(!set->crtc);
11345 BUG_ON(!set->crtc->helper_private);
11346
11347 /* Enforce sane interface api - has been abused by the fb helper. */
11348 BUG_ON(!set->mode && set->fb);
11349 BUG_ON(set->fb && set->num_connectors == 0);
11350
11351 if (set->fb) {
11352 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11353 set->crtc->base.id, set->fb->base.id,
11354 (int)set->num_connectors, set->x, set->y);
11355 } else {
11356 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11357 }
11358
11359 dev = set->crtc->dev;
11360
11361 ret = -ENOMEM;
11362 config = kzalloc(sizeof(*config), GFP_KERNEL);
11363 if (!config)
11364 goto out_config;
11365
11366 ret = intel_set_config_save_state(dev, config);
11367 if (ret)
11368 goto out_config;
11369
11370 save_set.crtc = set->crtc;
11371 save_set.mode = &set->crtc->mode;
11372 save_set.x = set->crtc->x;
11373 save_set.y = set->crtc->y;
11374 save_set.fb = set->crtc->primary->fb;
11375
11376 /* Compute whether we need a full modeset, only an fb base update or no
11377 * change at all. In the future we might also check whether only the
11378 * mode changed, e.g. for LVDS where we only change the panel fitter in
11379 * such cases. */
11380 intel_set_config_compute_mode_changes(set, config);
11381
11382 ret = intel_modeset_stage_output_state(dev, set, config);
11383 if (ret)
11384 goto fail;
11385
11386 if (config->mode_changed) {
11387 ret = intel_set_mode(set->crtc, set->mode,
11388 set->x, set->y, set->fb);
11389 } else if (config->fb_changed) {
11390 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11391
11392 intel_crtc_wait_for_pending_flips(set->crtc);
11393
11394 ret = intel_pipe_set_base(set->crtc,
11395 set->x, set->y, set->fb);
11396
11397 /*
11398 * We need to make sure the primary plane is re-enabled if it
11399 * has previously been turned off.
11400 */
11401 if (!intel_crtc->primary_enabled && ret == 0) {
11402 WARN_ON(!intel_crtc->active);
11403 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11404 }
11405
11406 /*
11407 * In the fastboot case this may be our only check of the
11408 * state after boot. It would be better to only do it on
11409 * the first update, but we don't have a nice way of doing that
11410 * (and really, set_config isn't used much for high freq page
11411 * flipping, so increasing its cost here shouldn't be a big
11412 * deal).
11413 */
11414 if (i915.fastboot && ret == 0)
11415 intel_modeset_check_state(set->crtc->dev);
11416 }
11417
11418 if (ret) {
11419 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11420 set->crtc->base.id, ret);
11421 fail:
11422 intel_set_config_restore_state(dev, config);
11423
11424 /*
11425 * HACK: if the pipe was on, but we didn't have a framebuffer,
11426 * force the pipe off to avoid oopsing in the modeset code
11427 * due to fb==NULL. This should only happen during boot since
11428 * we don't yet reconstruct the FB from the hardware state.
11429 */
11430 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11431 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11432
11433 /* Try to restore the config */
11434 if (config->mode_changed &&
11435 intel_set_mode(save_set.crtc, save_set.mode,
11436 save_set.x, save_set.y, save_set.fb))
11437 DRM_ERROR("failed to restore config after modeset failure\n");
11438 }
11439
11440 out_config:
11441 intel_set_config_free(config);
11442 return ret;
11443 }
11444
11445 static const struct drm_crtc_funcs intel_crtc_funcs = {
11446 .gamma_set = intel_crtc_gamma_set,
11447 .set_config = intel_crtc_set_config,
11448 .destroy = intel_crtc_destroy,
11449 .page_flip = intel_crtc_page_flip,
11450 };
11451
11452 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11453 struct intel_shared_dpll *pll,
11454 struct intel_dpll_hw_state *hw_state)
11455 {
11456 uint32_t val;
11457
11458 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11459 return false;
11460
11461 val = I915_READ(PCH_DPLL(pll->id));
11462 hw_state->dpll = val;
11463 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11464 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11465
11466 return val & DPLL_VCO_ENABLE;
11467 }
11468
11469 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11470 struct intel_shared_dpll *pll)
11471 {
11472 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11473 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11474 }
11475
11476 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11477 struct intel_shared_dpll *pll)
11478 {
11479 /* PCH refclock must be enabled first */
11480 ibx_assert_pch_refclk_enabled(dev_priv);
11481
11482 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11483
11484 /* Wait for the clocks to stabilize. */
11485 POSTING_READ(PCH_DPLL(pll->id));
11486 udelay(150);
11487
11488 /* The pixel multiplier can only be updated once the
11489 * DPLL is enabled and the clocks are stable.
11490 *
11491 * So write it again.
11492 */
11493 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11494 POSTING_READ(PCH_DPLL(pll->id));
11495 udelay(200);
11496 }
11497
11498 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11499 struct intel_shared_dpll *pll)
11500 {
11501 struct drm_device *dev = dev_priv->dev;
11502 struct intel_crtc *crtc;
11503
11504 /* Make sure no transcoder isn't still depending on us. */
11505 for_each_intel_crtc(dev, crtc) {
11506 if (intel_crtc_to_shared_dpll(crtc) == pll)
11507 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11508 }
11509
11510 I915_WRITE(PCH_DPLL(pll->id), 0);
11511 POSTING_READ(PCH_DPLL(pll->id));
11512 udelay(200);
11513 }
11514
11515 static char *ibx_pch_dpll_names[] = {
11516 "PCH DPLL A",
11517 "PCH DPLL B",
11518 };
11519
11520 static void ibx_pch_dpll_init(struct drm_device *dev)
11521 {
11522 struct drm_i915_private *dev_priv = dev->dev_private;
11523 int i;
11524
11525 dev_priv->num_shared_dpll = 2;
11526
11527 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11528 dev_priv->shared_dplls[i].id = i;
11529 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11530 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11531 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11532 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11533 dev_priv->shared_dplls[i].get_hw_state =
11534 ibx_pch_dpll_get_hw_state;
11535 }
11536 }
11537
11538 static void intel_shared_dpll_init(struct drm_device *dev)
11539 {
11540 struct drm_i915_private *dev_priv = dev->dev_private;
11541
11542 if (HAS_DDI(dev))
11543 intel_ddi_pll_init(dev);
11544 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11545 ibx_pch_dpll_init(dev);
11546 else
11547 dev_priv->num_shared_dpll = 0;
11548
11549 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11550 }
11551
11552 static int
11553 intel_primary_plane_disable(struct drm_plane *plane)
11554 {
11555 struct drm_device *dev = plane->dev;
11556 struct intel_crtc *intel_crtc;
11557
11558 if (!plane->fb)
11559 return 0;
11560
11561 BUG_ON(!plane->crtc);
11562
11563 intel_crtc = to_intel_crtc(plane->crtc);
11564
11565 /*
11566 * Even though we checked plane->fb above, it's still possible that
11567 * the primary plane has been implicitly disabled because the crtc
11568 * coordinates given weren't visible, or because we detected
11569 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11570 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11571 * In either case, we need to unpin the FB and let the fb pointer get
11572 * updated, but otherwise we don't need to touch the hardware.
11573 */
11574 if (!intel_crtc->primary_enabled)
11575 goto disable_unpin;
11576
11577 intel_crtc_wait_for_pending_flips(plane->crtc);
11578 intel_disable_primary_hw_plane(plane, plane->crtc);
11579
11580 disable_unpin:
11581 mutex_lock(&dev->struct_mutex);
11582 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11583 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11584 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11585 mutex_unlock(&dev->struct_mutex);
11586 plane->fb = NULL;
11587
11588 return 0;
11589 }
11590
11591 static int
11592 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11593 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11594 unsigned int crtc_w, unsigned int crtc_h,
11595 uint32_t src_x, uint32_t src_y,
11596 uint32_t src_w, uint32_t src_h)
11597 {
11598 struct drm_device *dev = crtc->dev;
11599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11600 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11601 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11602 struct drm_rect dest = {
11603 /* integer pixels */
11604 .x1 = crtc_x,
11605 .y1 = crtc_y,
11606 .x2 = crtc_x + crtc_w,
11607 .y2 = crtc_y + crtc_h,
11608 };
11609 struct drm_rect src = {
11610 /* 16.16 fixed point */
11611 .x1 = src_x,
11612 .y1 = src_y,
11613 .x2 = src_x + src_w,
11614 .y2 = src_y + src_h,
11615 };
11616 const struct drm_rect clip = {
11617 /* integer pixels */
11618 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11619 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11620 };
11621 bool visible;
11622 int ret;
11623
11624 ret = drm_plane_helper_check_update(plane, crtc, fb,
11625 &src, &dest, &clip,
11626 DRM_PLANE_HELPER_NO_SCALING,
11627 DRM_PLANE_HELPER_NO_SCALING,
11628 false, true, &visible);
11629
11630 if (ret)
11631 return ret;
11632
11633 /*
11634 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11635 * updating the fb pointer, and returning without touching the
11636 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11637 * turn on the display with all planes setup as desired.
11638 */
11639 if (!crtc->enabled) {
11640 mutex_lock(&dev->struct_mutex);
11641
11642 /*
11643 * If we already called setplane while the crtc was disabled,
11644 * we may have an fb pinned; unpin it.
11645 */
11646 if (plane->fb)
11647 intel_unpin_fb_obj(old_obj);
11648
11649 i915_gem_track_fb(old_obj, obj,
11650 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11651
11652 /* Pin and return without programming hardware */
11653 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11654 mutex_unlock(&dev->struct_mutex);
11655
11656 return ret;
11657 }
11658
11659 intel_crtc_wait_for_pending_flips(crtc);
11660
11661 /*
11662 * If clipping results in a non-visible primary plane, we'll disable
11663 * the primary plane. Note that this is a bit different than what
11664 * happens if userspace explicitly disables the plane by passing fb=0
11665 * because plane->fb still gets set and pinned.
11666 */
11667 if (!visible) {
11668 mutex_lock(&dev->struct_mutex);
11669
11670 /*
11671 * Try to pin the new fb first so that we can bail out if we
11672 * fail.
11673 */
11674 if (plane->fb != fb) {
11675 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11676 if (ret) {
11677 mutex_unlock(&dev->struct_mutex);
11678 return ret;
11679 }
11680 }
11681
11682 i915_gem_track_fb(old_obj, obj,
11683 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11684
11685 if (intel_crtc->primary_enabled)
11686 intel_disable_primary_hw_plane(plane, crtc);
11687
11688
11689 if (plane->fb != fb)
11690 if (plane->fb)
11691 intel_unpin_fb_obj(old_obj);
11692
11693 mutex_unlock(&dev->struct_mutex);
11694
11695 return 0;
11696 }
11697
11698 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11699 if (ret)
11700 return ret;
11701
11702 if (!intel_crtc->primary_enabled)
11703 intel_enable_primary_hw_plane(plane, crtc);
11704
11705 return 0;
11706 }
11707
11708 /* Common destruction function for both primary and cursor planes */
11709 static void intel_plane_destroy(struct drm_plane *plane)
11710 {
11711 struct intel_plane *intel_plane = to_intel_plane(plane);
11712 drm_plane_cleanup(plane);
11713 kfree(intel_plane);
11714 }
11715
11716 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11717 .update_plane = intel_primary_plane_setplane,
11718 .disable_plane = intel_primary_plane_disable,
11719 .destroy = intel_plane_destroy,
11720 };
11721
11722 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11723 int pipe)
11724 {
11725 struct intel_plane *primary;
11726 const uint32_t *intel_primary_formats;
11727 int num_formats;
11728
11729 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11730 if (primary == NULL)
11731 return NULL;
11732
11733 primary->can_scale = false;
11734 primary->max_downscale = 1;
11735 primary->pipe = pipe;
11736 primary->plane = pipe;
11737 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11738 primary->plane = !pipe;
11739
11740 if (INTEL_INFO(dev)->gen <= 3) {
11741 intel_primary_formats = intel_primary_formats_gen2;
11742 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11743 } else {
11744 intel_primary_formats = intel_primary_formats_gen4;
11745 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11746 }
11747
11748 drm_universal_plane_init(dev, &primary->base, 0,
11749 &intel_primary_plane_funcs,
11750 intel_primary_formats, num_formats,
11751 DRM_PLANE_TYPE_PRIMARY);
11752 return &primary->base;
11753 }
11754
11755 static int
11756 intel_cursor_plane_disable(struct drm_plane *plane)
11757 {
11758 if (!plane->fb)
11759 return 0;
11760
11761 BUG_ON(!plane->crtc);
11762
11763 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11764 }
11765
11766 static int
11767 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11768 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11769 unsigned int crtc_w, unsigned int crtc_h,
11770 uint32_t src_x, uint32_t src_y,
11771 uint32_t src_w, uint32_t src_h)
11772 {
11773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11774 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11775 struct drm_i915_gem_object *obj = intel_fb->obj;
11776 struct drm_rect dest = {
11777 /* integer pixels */
11778 .x1 = crtc_x,
11779 .y1 = crtc_y,
11780 .x2 = crtc_x + crtc_w,
11781 .y2 = crtc_y + crtc_h,
11782 };
11783 struct drm_rect src = {
11784 /* 16.16 fixed point */
11785 .x1 = src_x,
11786 .y1 = src_y,
11787 .x2 = src_x + src_w,
11788 .y2 = src_y + src_h,
11789 };
11790 const struct drm_rect clip = {
11791 /* integer pixels */
11792 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11793 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11794 };
11795 bool visible;
11796 int ret;
11797
11798 ret = drm_plane_helper_check_update(plane, crtc, fb,
11799 &src, &dest, &clip,
11800 DRM_PLANE_HELPER_NO_SCALING,
11801 DRM_PLANE_HELPER_NO_SCALING,
11802 true, true, &visible);
11803 if (ret)
11804 return ret;
11805
11806 crtc->cursor_x = crtc_x;
11807 crtc->cursor_y = crtc_y;
11808 if (fb != crtc->cursor->fb) {
11809 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11810 } else {
11811 intel_crtc_update_cursor(crtc, visible);
11812
11813 intel_frontbuffer_flip(crtc->dev,
11814 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11815
11816 return 0;
11817 }
11818 }
11819 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11820 .update_plane = intel_cursor_plane_update,
11821 .disable_plane = intel_cursor_plane_disable,
11822 .destroy = intel_plane_destroy,
11823 };
11824
11825 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11826 int pipe)
11827 {
11828 struct intel_plane *cursor;
11829
11830 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11831 if (cursor == NULL)
11832 return NULL;
11833
11834 cursor->can_scale = false;
11835 cursor->max_downscale = 1;
11836 cursor->pipe = pipe;
11837 cursor->plane = pipe;
11838
11839 drm_universal_plane_init(dev, &cursor->base, 0,
11840 &intel_cursor_plane_funcs,
11841 intel_cursor_formats,
11842 ARRAY_SIZE(intel_cursor_formats),
11843 DRM_PLANE_TYPE_CURSOR);
11844 return &cursor->base;
11845 }
11846
11847 static void intel_crtc_init(struct drm_device *dev, int pipe)
11848 {
11849 struct drm_i915_private *dev_priv = dev->dev_private;
11850 struct intel_crtc *intel_crtc;
11851 struct drm_plane *primary = NULL;
11852 struct drm_plane *cursor = NULL;
11853 int i, ret;
11854
11855 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11856 if (intel_crtc == NULL)
11857 return;
11858
11859 primary = intel_primary_plane_create(dev, pipe);
11860 if (!primary)
11861 goto fail;
11862
11863 cursor = intel_cursor_plane_create(dev, pipe);
11864 if (!cursor)
11865 goto fail;
11866
11867 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11868 cursor, &intel_crtc_funcs);
11869 if (ret)
11870 goto fail;
11871
11872 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11873 for (i = 0; i < 256; i++) {
11874 intel_crtc->lut_r[i] = i;
11875 intel_crtc->lut_g[i] = i;
11876 intel_crtc->lut_b[i] = i;
11877 }
11878
11879 /*
11880 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11881 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11882 */
11883 intel_crtc->pipe = pipe;
11884 intel_crtc->plane = pipe;
11885 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11886 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11887 intel_crtc->plane = !pipe;
11888 }
11889
11890 intel_crtc->cursor_base = ~0;
11891 intel_crtc->cursor_cntl = ~0;
11892 intel_crtc->cursor_size = ~0;
11893
11894 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11895 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11896 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11897 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11898
11899 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11900
11901 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11902 return;
11903
11904 fail:
11905 if (primary)
11906 drm_plane_cleanup(primary);
11907 if (cursor)
11908 drm_plane_cleanup(cursor);
11909 kfree(intel_crtc);
11910 }
11911
11912 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11913 {
11914 struct drm_encoder *encoder = connector->base.encoder;
11915 struct drm_device *dev = connector->base.dev;
11916
11917 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11918
11919 if (!encoder)
11920 return INVALID_PIPE;
11921
11922 return to_intel_crtc(encoder->crtc)->pipe;
11923 }
11924
11925 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11926 struct drm_file *file)
11927 {
11928 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11929 struct drm_crtc *drmmode_crtc;
11930 struct intel_crtc *crtc;
11931
11932 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11933 return -ENODEV;
11934
11935 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
11936
11937 if (!drmmode_crtc) {
11938 DRM_ERROR("no such CRTC id\n");
11939 return -ENOENT;
11940 }
11941
11942 crtc = to_intel_crtc(drmmode_crtc);
11943 pipe_from_crtc_id->pipe = crtc->pipe;
11944
11945 return 0;
11946 }
11947
11948 static int intel_encoder_clones(struct intel_encoder *encoder)
11949 {
11950 struct drm_device *dev = encoder->base.dev;
11951 struct intel_encoder *source_encoder;
11952 int index_mask = 0;
11953 int entry = 0;
11954
11955 for_each_intel_encoder(dev, source_encoder) {
11956 if (encoders_cloneable(encoder, source_encoder))
11957 index_mask |= (1 << entry);
11958
11959 entry++;
11960 }
11961
11962 return index_mask;
11963 }
11964
11965 static bool has_edp_a(struct drm_device *dev)
11966 {
11967 struct drm_i915_private *dev_priv = dev->dev_private;
11968
11969 if (!IS_MOBILE(dev))
11970 return false;
11971
11972 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11973 return false;
11974
11975 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11976 return false;
11977
11978 return true;
11979 }
11980
11981 const char *intel_output_name(int output)
11982 {
11983 static const char *names[] = {
11984 [INTEL_OUTPUT_UNUSED] = "Unused",
11985 [INTEL_OUTPUT_ANALOG] = "Analog",
11986 [INTEL_OUTPUT_DVO] = "DVO",
11987 [INTEL_OUTPUT_SDVO] = "SDVO",
11988 [INTEL_OUTPUT_LVDS] = "LVDS",
11989 [INTEL_OUTPUT_TVOUT] = "TV",
11990 [INTEL_OUTPUT_HDMI] = "HDMI",
11991 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11992 [INTEL_OUTPUT_EDP] = "eDP",
11993 [INTEL_OUTPUT_DSI] = "DSI",
11994 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11995 };
11996
11997 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11998 return "Invalid";
11999
12000 return names[output];
12001 }
12002
12003 static bool intel_crt_present(struct drm_device *dev)
12004 {
12005 struct drm_i915_private *dev_priv = dev->dev_private;
12006
12007 if (IS_ULT(dev))
12008 return false;
12009
12010 if (IS_CHERRYVIEW(dev))
12011 return false;
12012
12013 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12014 return false;
12015
12016 return true;
12017 }
12018
12019 static void intel_setup_outputs(struct drm_device *dev)
12020 {
12021 struct drm_i915_private *dev_priv = dev->dev_private;
12022 struct intel_encoder *encoder;
12023 bool dpd_is_edp = false;
12024
12025 intel_lvds_init(dev);
12026
12027 if (intel_crt_present(dev))
12028 intel_crt_init(dev);
12029
12030 if (HAS_DDI(dev)) {
12031 int found;
12032
12033 /* Haswell uses DDI functions to detect digital outputs */
12034 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12035 /* DDI A only supports eDP */
12036 if (found)
12037 intel_ddi_init(dev, PORT_A);
12038
12039 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12040 * register */
12041 found = I915_READ(SFUSE_STRAP);
12042
12043 if (found & SFUSE_STRAP_DDIB_DETECTED)
12044 intel_ddi_init(dev, PORT_B);
12045 if (found & SFUSE_STRAP_DDIC_DETECTED)
12046 intel_ddi_init(dev, PORT_C);
12047 if (found & SFUSE_STRAP_DDID_DETECTED)
12048 intel_ddi_init(dev, PORT_D);
12049 } else if (HAS_PCH_SPLIT(dev)) {
12050 int found;
12051 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12052
12053 if (has_edp_a(dev))
12054 intel_dp_init(dev, DP_A, PORT_A);
12055
12056 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12057 /* PCH SDVOB multiplex with HDMIB */
12058 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12059 if (!found)
12060 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12061 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12062 intel_dp_init(dev, PCH_DP_B, PORT_B);
12063 }
12064
12065 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12066 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12067
12068 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12069 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12070
12071 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12072 intel_dp_init(dev, PCH_DP_C, PORT_C);
12073
12074 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12075 intel_dp_init(dev, PCH_DP_D, PORT_D);
12076 } else if (IS_VALLEYVIEW(dev)) {
12077 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12078 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12079 PORT_B);
12080 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12081 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12082 }
12083
12084 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12085 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12086 PORT_C);
12087 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12088 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12089 }
12090
12091 if (IS_CHERRYVIEW(dev)) {
12092 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12093 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12094 PORT_D);
12095 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12096 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12097 }
12098 }
12099
12100 intel_dsi_init(dev);
12101 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12102 bool found = false;
12103
12104 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12105 DRM_DEBUG_KMS("probing SDVOB\n");
12106 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12107 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12108 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12109 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12110 }
12111
12112 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12113 intel_dp_init(dev, DP_B, PORT_B);
12114 }
12115
12116 /* Before G4X SDVOC doesn't have its own detect register */
12117
12118 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12119 DRM_DEBUG_KMS("probing SDVOC\n");
12120 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12121 }
12122
12123 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12124
12125 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12126 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12127 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12128 }
12129 if (SUPPORTS_INTEGRATED_DP(dev))
12130 intel_dp_init(dev, DP_C, PORT_C);
12131 }
12132
12133 if (SUPPORTS_INTEGRATED_DP(dev) &&
12134 (I915_READ(DP_D) & DP_DETECTED))
12135 intel_dp_init(dev, DP_D, PORT_D);
12136 } else if (IS_GEN2(dev))
12137 intel_dvo_init(dev);
12138
12139 if (SUPPORTS_TV(dev))
12140 intel_tv_init(dev);
12141
12142 intel_edp_psr_init(dev);
12143
12144 for_each_intel_encoder(dev, encoder) {
12145 encoder->base.possible_crtcs = encoder->crtc_mask;
12146 encoder->base.possible_clones =
12147 intel_encoder_clones(encoder);
12148 }
12149
12150 intel_init_pch_refclk(dev);
12151
12152 drm_helper_move_panel_connectors_to_head(dev);
12153 }
12154
12155 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12156 {
12157 struct drm_device *dev = fb->dev;
12158 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12159
12160 drm_framebuffer_cleanup(fb);
12161 mutex_lock(&dev->struct_mutex);
12162 WARN_ON(!intel_fb->obj->framebuffer_references--);
12163 drm_gem_object_unreference(&intel_fb->obj->base);
12164 mutex_unlock(&dev->struct_mutex);
12165 kfree(intel_fb);
12166 }
12167
12168 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12169 struct drm_file *file,
12170 unsigned int *handle)
12171 {
12172 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12173 struct drm_i915_gem_object *obj = intel_fb->obj;
12174
12175 return drm_gem_handle_create(file, &obj->base, handle);
12176 }
12177
12178 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12179 .destroy = intel_user_framebuffer_destroy,
12180 .create_handle = intel_user_framebuffer_create_handle,
12181 };
12182
12183 static int intel_framebuffer_init(struct drm_device *dev,
12184 struct intel_framebuffer *intel_fb,
12185 struct drm_mode_fb_cmd2 *mode_cmd,
12186 struct drm_i915_gem_object *obj)
12187 {
12188 int aligned_height;
12189 int pitch_limit;
12190 int ret;
12191
12192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12193
12194 if (obj->tiling_mode == I915_TILING_Y) {
12195 DRM_DEBUG("hardware does not support tiling Y\n");
12196 return -EINVAL;
12197 }
12198
12199 if (mode_cmd->pitches[0] & 63) {
12200 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12201 mode_cmd->pitches[0]);
12202 return -EINVAL;
12203 }
12204
12205 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12206 pitch_limit = 32*1024;
12207 } else if (INTEL_INFO(dev)->gen >= 4) {
12208 if (obj->tiling_mode)
12209 pitch_limit = 16*1024;
12210 else
12211 pitch_limit = 32*1024;
12212 } else if (INTEL_INFO(dev)->gen >= 3) {
12213 if (obj->tiling_mode)
12214 pitch_limit = 8*1024;
12215 else
12216 pitch_limit = 16*1024;
12217 } else
12218 /* XXX DSPC is limited to 4k tiled */
12219 pitch_limit = 8*1024;
12220
12221 if (mode_cmd->pitches[0] > pitch_limit) {
12222 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12223 obj->tiling_mode ? "tiled" : "linear",
12224 mode_cmd->pitches[0], pitch_limit);
12225 return -EINVAL;
12226 }
12227
12228 if (obj->tiling_mode != I915_TILING_NONE &&
12229 mode_cmd->pitches[0] != obj->stride) {
12230 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12231 mode_cmd->pitches[0], obj->stride);
12232 return -EINVAL;
12233 }
12234
12235 /* Reject formats not supported by any plane early. */
12236 switch (mode_cmd->pixel_format) {
12237 case DRM_FORMAT_C8:
12238 case DRM_FORMAT_RGB565:
12239 case DRM_FORMAT_XRGB8888:
12240 case DRM_FORMAT_ARGB8888:
12241 break;
12242 case DRM_FORMAT_XRGB1555:
12243 case DRM_FORMAT_ARGB1555:
12244 if (INTEL_INFO(dev)->gen > 3) {
12245 DRM_DEBUG("unsupported pixel format: %s\n",
12246 drm_get_format_name(mode_cmd->pixel_format));
12247 return -EINVAL;
12248 }
12249 break;
12250 case DRM_FORMAT_XBGR8888:
12251 case DRM_FORMAT_ABGR8888:
12252 case DRM_FORMAT_XRGB2101010:
12253 case DRM_FORMAT_ARGB2101010:
12254 case DRM_FORMAT_XBGR2101010:
12255 case DRM_FORMAT_ABGR2101010:
12256 if (INTEL_INFO(dev)->gen < 4) {
12257 DRM_DEBUG("unsupported pixel format: %s\n",
12258 drm_get_format_name(mode_cmd->pixel_format));
12259 return -EINVAL;
12260 }
12261 break;
12262 case DRM_FORMAT_YUYV:
12263 case DRM_FORMAT_UYVY:
12264 case DRM_FORMAT_YVYU:
12265 case DRM_FORMAT_VYUY:
12266 if (INTEL_INFO(dev)->gen < 5) {
12267 DRM_DEBUG("unsupported pixel format: %s\n",
12268 drm_get_format_name(mode_cmd->pixel_format));
12269 return -EINVAL;
12270 }
12271 break;
12272 default:
12273 DRM_DEBUG("unsupported pixel format: %s\n",
12274 drm_get_format_name(mode_cmd->pixel_format));
12275 return -EINVAL;
12276 }
12277
12278 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12279 if (mode_cmd->offsets[0] != 0)
12280 return -EINVAL;
12281
12282 aligned_height = intel_align_height(dev, mode_cmd->height,
12283 obj->tiling_mode);
12284 /* FIXME drm helper for size checks (especially planar formats)? */
12285 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12286 return -EINVAL;
12287
12288 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12289 intel_fb->obj = obj;
12290 intel_fb->obj->framebuffer_references++;
12291
12292 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12293 if (ret) {
12294 DRM_ERROR("framebuffer init failed %d\n", ret);
12295 return ret;
12296 }
12297
12298 return 0;
12299 }
12300
12301 static struct drm_framebuffer *
12302 intel_user_framebuffer_create(struct drm_device *dev,
12303 struct drm_file *filp,
12304 struct drm_mode_fb_cmd2 *mode_cmd)
12305 {
12306 struct drm_i915_gem_object *obj;
12307
12308 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12309 mode_cmd->handles[0]));
12310 if (&obj->base == NULL)
12311 return ERR_PTR(-ENOENT);
12312
12313 return intel_framebuffer_create(dev, mode_cmd, obj);
12314 }
12315
12316 #ifndef CONFIG_DRM_I915_FBDEV
12317 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12318 {
12319 }
12320 #endif
12321
12322 static const struct drm_mode_config_funcs intel_mode_funcs = {
12323 .fb_create = intel_user_framebuffer_create,
12324 .output_poll_changed = intel_fbdev_output_poll_changed,
12325 };
12326
12327 /* Set up chip specific display functions */
12328 static void intel_init_display(struct drm_device *dev)
12329 {
12330 struct drm_i915_private *dev_priv = dev->dev_private;
12331
12332 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12333 dev_priv->display.find_dpll = g4x_find_best_dpll;
12334 else if (IS_CHERRYVIEW(dev))
12335 dev_priv->display.find_dpll = chv_find_best_dpll;
12336 else if (IS_VALLEYVIEW(dev))
12337 dev_priv->display.find_dpll = vlv_find_best_dpll;
12338 else if (IS_PINEVIEW(dev))
12339 dev_priv->display.find_dpll = pnv_find_best_dpll;
12340 else
12341 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12342
12343 if (HAS_DDI(dev)) {
12344 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12345 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12346 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12347 dev_priv->display.crtc_enable = haswell_crtc_enable;
12348 dev_priv->display.crtc_disable = haswell_crtc_disable;
12349 dev_priv->display.off = ironlake_crtc_off;
12350 dev_priv->display.update_primary_plane =
12351 ironlake_update_primary_plane;
12352 } else if (HAS_PCH_SPLIT(dev)) {
12353 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12354 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12355 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12356 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12357 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12358 dev_priv->display.off = ironlake_crtc_off;
12359 dev_priv->display.update_primary_plane =
12360 ironlake_update_primary_plane;
12361 } else if (IS_VALLEYVIEW(dev)) {
12362 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12363 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12364 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12365 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12366 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12367 dev_priv->display.off = i9xx_crtc_off;
12368 dev_priv->display.update_primary_plane =
12369 i9xx_update_primary_plane;
12370 } else {
12371 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12372 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12373 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12374 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12375 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12376 dev_priv->display.off = i9xx_crtc_off;
12377 dev_priv->display.update_primary_plane =
12378 i9xx_update_primary_plane;
12379 }
12380
12381 /* Returns the core display clock speed */
12382 if (IS_VALLEYVIEW(dev))
12383 dev_priv->display.get_display_clock_speed =
12384 valleyview_get_display_clock_speed;
12385 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12386 dev_priv->display.get_display_clock_speed =
12387 i945_get_display_clock_speed;
12388 else if (IS_I915G(dev))
12389 dev_priv->display.get_display_clock_speed =
12390 i915_get_display_clock_speed;
12391 else if (IS_I945GM(dev) || IS_845G(dev))
12392 dev_priv->display.get_display_clock_speed =
12393 i9xx_misc_get_display_clock_speed;
12394 else if (IS_PINEVIEW(dev))
12395 dev_priv->display.get_display_clock_speed =
12396 pnv_get_display_clock_speed;
12397 else if (IS_I915GM(dev))
12398 dev_priv->display.get_display_clock_speed =
12399 i915gm_get_display_clock_speed;
12400 else if (IS_I865G(dev))
12401 dev_priv->display.get_display_clock_speed =
12402 i865_get_display_clock_speed;
12403 else if (IS_I85X(dev))
12404 dev_priv->display.get_display_clock_speed =
12405 i855_get_display_clock_speed;
12406 else /* 852, 830 */
12407 dev_priv->display.get_display_clock_speed =
12408 i830_get_display_clock_speed;
12409
12410 if (IS_G4X(dev)) {
12411 dev_priv->display.write_eld = g4x_write_eld;
12412 } else if (IS_GEN5(dev)) {
12413 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12414 dev_priv->display.write_eld = ironlake_write_eld;
12415 } else if (IS_GEN6(dev)) {
12416 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12417 dev_priv->display.write_eld = ironlake_write_eld;
12418 dev_priv->display.modeset_global_resources =
12419 snb_modeset_global_resources;
12420 } else if (IS_IVYBRIDGE(dev)) {
12421 /* FIXME: detect B0+ stepping and use auto training */
12422 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12423 dev_priv->display.write_eld = ironlake_write_eld;
12424 dev_priv->display.modeset_global_resources =
12425 ivb_modeset_global_resources;
12426 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12427 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12428 dev_priv->display.write_eld = haswell_write_eld;
12429 dev_priv->display.modeset_global_resources =
12430 haswell_modeset_global_resources;
12431 } else if (IS_VALLEYVIEW(dev)) {
12432 dev_priv->display.modeset_global_resources =
12433 valleyview_modeset_global_resources;
12434 dev_priv->display.write_eld = ironlake_write_eld;
12435 }
12436
12437 /* Default just returns -ENODEV to indicate unsupported */
12438 dev_priv->display.queue_flip = intel_default_queue_flip;
12439
12440 switch (INTEL_INFO(dev)->gen) {
12441 case 2:
12442 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12443 break;
12444
12445 case 3:
12446 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12447 break;
12448
12449 case 4:
12450 case 5:
12451 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12452 break;
12453
12454 case 6:
12455 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12456 break;
12457 case 7:
12458 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12459 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12460 break;
12461 }
12462
12463 intel_panel_init_backlight_funcs(dev);
12464 }
12465
12466 /*
12467 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12468 * resume, or other times. This quirk makes sure that's the case for
12469 * affected systems.
12470 */
12471 static void quirk_pipea_force(struct drm_device *dev)
12472 {
12473 struct drm_i915_private *dev_priv = dev->dev_private;
12474
12475 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12476 DRM_INFO("applying pipe a force quirk\n");
12477 }
12478
12479 /*
12480 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12481 */
12482 static void quirk_ssc_force_disable(struct drm_device *dev)
12483 {
12484 struct drm_i915_private *dev_priv = dev->dev_private;
12485 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12486 DRM_INFO("applying lvds SSC disable quirk\n");
12487 }
12488
12489 /*
12490 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12491 * brightness value
12492 */
12493 static void quirk_invert_brightness(struct drm_device *dev)
12494 {
12495 struct drm_i915_private *dev_priv = dev->dev_private;
12496 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12497 DRM_INFO("applying inverted panel brightness quirk\n");
12498 }
12499
12500 /* Some VBT's incorrectly indicate no backlight is present */
12501 static void quirk_backlight_present(struct drm_device *dev)
12502 {
12503 struct drm_i915_private *dev_priv = dev->dev_private;
12504 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12505 DRM_INFO("applying backlight present quirk\n");
12506 }
12507
12508 struct intel_quirk {
12509 int device;
12510 int subsystem_vendor;
12511 int subsystem_device;
12512 void (*hook)(struct drm_device *dev);
12513 };
12514
12515 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12516 struct intel_dmi_quirk {
12517 void (*hook)(struct drm_device *dev);
12518 const struct dmi_system_id (*dmi_id_list)[];
12519 };
12520
12521 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12522 {
12523 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12524 return 1;
12525 }
12526
12527 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12528 {
12529 .dmi_id_list = &(const struct dmi_system_id[]) {
12530 {
12531 .callback = intel_dmi_reverse_brightness,
12532 .ident = "NCR Corporation",
12533 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12534 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12535 },
12536 },
12537 { } /* terminating entry */
12538 },
12539 .hook = quirk_invert_brightness,
12540 },
12541 };
12542
12543 static struct intel_quirk intel_quirks[] = {
12544 /* HP Mini needs pipe A force quirk (LP: #322104) */
12545 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12546
12547 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12548 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12549
12550 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12551 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12552
12553 /* Lenovo U160 cannot use SSC on LVDS */
12554 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12555
12556 /* Sony Vaio Y cannot use SSC on LVDS */
12557 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12558
12559 /* Acer Aspire 5734Z must invert backlight brightness */
12560 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12561
12562 /* Acer/eMachines G725 */
12563 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12564
12565 /* Acer/eMachines e725 */
12566 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12567
12568 /* Acer/Packard Bell NCL20 */
12569 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12570
12571 /* Acer Aspire 4736Z */
12572 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12573
12574 /* Acer Aspire 5336 */
12575 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12576
12577 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12578 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12579
12580 /* Acer C720 Chromebook (Core i3 4005U) */
12581 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12582
12583 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12584 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12585
12586 /* HP Chromebook 14 (Celeron 2955U) */
12587 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12588 };
12589
12590 static void intel_init_quirks(struct drm_device *dev)
12591 {
12592 struct pci_dev *d = dev->pdev;
12593 int i;
12594
12595 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12596 struct intel_quirk *q = &intel_quirks[i];
12597
12598 if (d->device == q->device &&
12599 (d->subsystem_vendor == q->subsystem_vendor ||
12600 q->subsystem_vendor == PCI_ANY_ID) &&
12601 (d->subsystem_device == q->subsystem_device ||
12602 q->subsystem_device == PCI_ANY_ID))
12603 q->hook(dev);
12604 }
12605 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12606 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12607 intel_dmi_quirks[i].hook(dev);
12608 }
12609 }
12610
12611 /* Disable the VGA plane that we never use */
12612 static void i915_disable_vga(struct drm_device *dev)
12613 {
12614 struct drm_i915_private *dev_priv = dev->dev_private;
12615 u8 sr1;
12616 u32 vga_reg = i915_vgacntrl_reg(dev);
12617
12618 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12619 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12620 outb(SR01, VGA_SR_INDEX);
12621 sr1 = inb(VGA_SR_DATA);
12622 outb(sr1 | 1<<5, VGA_SR_DATA);
12623 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12624 udelay(300);
12625
12626 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12627 POSTING_READ(vga_reg);
12628 }
12629
12630 void intel_modeset_init_hw(struct drm_device *dev)
12631 {
12632 intel_prepare_ddi(dev);
12633
12634 if (IS_VALLEYVIEW(dev))
12635 vlv_update_cdclk(dev);
12636
12637 intel_init_clock_gating(dev);
12638
12639 intel_enable_gt_powersave(dev);
12640 }
12641
12642 void intel_modeset_suspend_hw(struct drm_device *dev)
12643 {
12644 intel_suspend_hw(dev);
12645 }
12646
12647 void intel_modeset_init(struct drm_device *dev)
12648 {
12649 struct drm_i915_private *dev_priv = dev->dev_private;
12650 int sprite, ret;
12651 enum pipe pipe;
12652 struct intel_crtc *crtc;
12653
12654 drm_mode_config_init(dev);
12655
12656 dev->mode_config.min_width = 0;
12657 dev->mode_config.min_height = 0;
12658
12659 dev->mode_config.preferred_depth = 24;
12660 dev->mode_config.prefer_shadow = 1;
12661
12662 dev->mode_config.funcs = &intel_mode_funcs;
12663
12664 intel_init_quirks(dev);
12665
12666 intel_init_pm(dev);
12667
12668 if (INTEL_INFO(dev)->num_pipes == 0)
12669 return;
12670
12671 intel_init_display(dev);
12672
12673 if (IS_GEN2(dev)) {
12674 dev->mode_config.max_width = 2048;
12675 dev->mode_config.max_height = 2048;
12676 } else if (IS_GEN3(dev)) {
12677 dev->mode_config.max_width = 4096;
12678 dev->mode_config.max_height = 4096;
12679 } else {
12680 dev->mode_config.max_width = 8192;
12681 dev->mode_config.max_height = 8192;
12682 }
12683
12684 if (IS_845G(dev) || IS_I865G(dev)) {
12685 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12686 dev->mode_config.cursor_height = 1023;
12687 } else if (IS_GEN2(dev)) {
12688 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12689 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12690 } else {
12691 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12692 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12693 }
12694
12695 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12696
12697 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12698 INTEL_INFO(dev)->num_pipes,
12699 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12700
12701 for_each_pipe(pipe) {
12702 intel_crtc_init(dev, pipe);
12703 for_each_sprite(pipe, sprite) {
12704 ret = intel_plane_init(dev, pipe, sprite);
12705 if (ret)
12706 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12707 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12708 }
12709 }
12710
12711 intel_init_dpio(dev);
12712
12713 intel_shared_dpll_init(dev);
12714
12715 /* Just disable it once at startup */
12716 i915_disable_vga(dev);
12717 intel_setup_outputs(dev);
12718
12719 /* Just in case the BIOS is doing something questionable. */
12720 intel_disable_fbc(dev);
12721
12722 drm_modeset_lock_all(dev);
12723 intel_modeset_setup_hw_state(dev, false);
12724 drm_modeset_unlock_all(dev);
12725
12726 for_each_intel_crtc(dev, crtc) {
12727 if (!crtc->active)
12728 continue;
12729
12730 /*
12731 * Note that reserving the BIOS fb up front prevents us
12732 * from stuffing other stolen allocations like the ring
12733 * on top. This prevents some ugliness at boot time, and
12734 * can even allow for smooth boot transitions if the BIOS
12735 * fb is large enough for the active pipe configuration.
12736 */
12737 if (dev_priv->display.get_plane_config) {
12738 dev_priv->display.get_plane_config(crtc,
12739 &crtc->plane_config);
12740 /*
12741 * If the fb is shared between multiple heads, we'll
12742 * just get the first one.
12743 */
12744 intel_find_plane_obj(crtc, &crtc->plane_config);
12745 }
12746 }
12747 }
12748
12749 static void intel_enable_pipe_a(struct drm_device *dev)
12750 {
12751 struct intel_connector *connector;
12752 struct drm_connector *crt = NULL;
12753 struct intel_load_detect_pipe load_detect_temp;
12754 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12755
12756 /* We can't just switch on the pipe A, we need to set things up with a
12757 * proper mode and output configuration. As a gross hack, enable pipe A
12758 * by enabling the load detect pipe once. */
12759 list_for_each_entry(connector,
12760 &dev->mode_config.connector_list,
12761 base.head) {
12762 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12763 crt = &connector->base;
12764 break;
12765 }
12766 }
12767
12768 if (!crt)
12769 return;
12770
12771 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12772 intel_release_load_detect_pipe(crt, &load_detect_temp);
12773 }
12774
12775 static bool
12776 intel_check_plane_mapping(struct intel_crtc *crtc)
12777 {
12778 struct drm_device *dev = crtc->base.dev;
12779 struct drm_i915_private *dev_priv = dev->dev_private;
12780 u32 reg, val;
12781
12782 if (INTEL_INFO(dev)->num_pipes == 1)
12783 return true;
12784
12785 reg = DSPCNTR(!crtc->plane);
12786 val = I915_READ(reg);
12787
12788 if ((val & DISPLAY_PLANE_ENABLE) &&
12789 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12790 return false;
12791
12792 return true;
12793 }
12794
12795 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12796 {
12797 struct drm_device *dev = crtc->base.dev;
12798 struct drm_i915_private *dev_priv = dev->dev_private;
12799 u32 reg;
12800
12801 /* Clear any frame start delays used for debugging left by the BIOS */
12802 reg = PIPECONF(crtc->config.cpu_transcoder);
12803 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12804
12805 /* restore vblank interrupts to correct state */
12806 if (crtc->active) {
12807 update_scanline_offset(crtc);
12808 drm_vblank_on(dev, crtc->pipe);
12809 } else
12810 drm_vblank_off(dev, crtc->pipe);
12811
12812 /* We need to sanitize the plane -> pipe mapping first because this will
12813 * disable the crtc (and hence change the state) if it is wrong. Note
12814 * that gen4+ has a fixed plane -> pipe mapping. */
12815 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12816 struct intel_connector *connector;
12817 bool plane;
12818
12819 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12820 crtc->base.base.id);
12821
12822 /* Pipe has the wrong plane attached and the plane is active.
12823 * Temporarily change the plane mapping and disable everything
12824 * ... */
12825 plane = crtc->plane;
12826 crtc->plane = !plane;
12827 crtc->primary_enabled = true;
12828 dev_priv->display.crtc_disable(&crtc->base);
12829 crtc->plane = plane;
12830
12831 /* ... and break all links. */
12832 list_for_each_entry(connector, &dev->mode_config.connector_list,
12833 base.head) {
12834 if (connector->encoder->base.crtc != &crtc->base)
12835 continue;
12836
12837 connector->base.dpms = DRM_MODE_DPMS_OFF;
12838 connector->base.encoder = NULL;
12839 }
12840 /* multiple connectors may have the same encoder:
12841 * handle them and break crtc link separately */
12842 list_for_each_entry(connector, &dev->mode_config.connector_list,
12843 base.head)
12844 if (connector->encoder->base.crtc == &crtc->base) {
12845 connector->encoder->base.crtc = NULL;
12846 connector->encoder->connectors_active = false;
12847 }
12848
12849 WARN_ON(crtc->active);
12850 crtc->base.enabled = false;
12851 }
12852
12853 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12854 crtc->pipe == PIPE_A && !crtc->active) {
12855 /* BIOS forgot to enable pipe A, this mostly happens after
12856 * resume. Force-enable the pipe to fix this, the update_dpms
12857 * call below we restore the pipe to the right state, but leave
12858 * the required bits on. */
12859 intel_enable_pipe_a(dev);
12860 }
12861
12862 /* Adjust the state of the output pipe according to whether we
12863 * have active connectors/encoders. */
12864 intel_crtc_update_dpms(&crtc->base);
12865
12866 if (crtc->active != crtc->base.enabled) {
12867 struct intel_encoder *encoder;
12868
12869 /* This can happen either due to bugs in the get_hw_state
12870 * functions or because the pipe is force-enabled due to the
12871 * pipe A quirk. */
12872 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12873 crtc->base.base.id,
12874 crtc->base.enabled ? "enabled" : "disabled",
12875 crtc->active ? "enabled" : "disabled");
12876
12877 crtc->base.enabled = crtc->active;
12878
12879 /* Because we only establish the connector -> encoder ->
12880 * crtc links if something is active, this means the
12881 * crtc is now deactivated. Break the links. connector
12882 * -> encoder links are only establish when things are
12883 * actually up, hence no need to break them. */
12884 WARN_ON(crtc->active);
12885
12886 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12887 WARN_ON(encoder->connectors_active);
12888 encoder->base.crtc = NULL;
12889 }
12890 }
12891
12892 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12893 /*
12894 * We start out with underrun reporting disabled to avoid races.
12895 * For correct bookkeeping mark this on active crtcs.
12896 *
12897 * Also on gmch platforms we dont have any hardware bits to
12898 * disable the underrun reporting. Which means we need to start
12899 * out with underrun reporting disabled also on inactive pipes,
12900 * since otherwise we'll complain about the garbage we read when
12901 * e.g. coming up after runtime pm.
12902 *
12903 * No protection against concurrent access is required - at
12904 * worst a fifo underrun happens which also sets this to false.
12905 */
12906 crtc->cpu_fifo_underrun_disabled = true;
12907 crtc->pch_fifo_underrun_disabled = true;
12908 }
12909 }
12910
12911 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12912 {
12913 struct intel_connector *connector;
12914 struct drm_device *dev = encoder->base.dev;
12915
12916 /* We need to check both for a crtc link (meaning that the
12917 * encoder is active and trying to read from a pipe) and the
12918 * pipe itself being active. */
12919 bool has_active_crtc = encoder->base.crtc &&
12920 to_intel_crtc(encoder->base.crtc)->active;
12921
12922 if (encoder->connectors_active && !has_active_crtc) {
12923 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12924 encoder->base.base.id,
12925 encoder->base.name);
12926
12927 /* Connector is active, but has no active pipe. This is
12928 * fallout from our resume register restoring. Disable
12929 * the encoder manually again. */
12930 if (encoder->base.crtc) {
12931 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12932 encoder->base.base.id,
12933 encoder->base.name);
12934 encoder->disable(encoder);
12935 if (encoder->post_disable)
12936 encoder->post_disable(encoder);
12937 }
12938 encoder->base.crtc = NULL;
12939 encoder->connectors_active = false;
12940
12941 /* Inconsistent output/port/pipe state happens presumably due to
12942 * a bug in one of the get_hw_state functions. Or someplace else
12943 * in our code, like the register restore mess on resume. Clamp
12944 * things to off as a safer default. */
12945 list_for_each_entry(connector,
12946 &dev->mode_config.connector_list,
12947 base.head) {
12948 if (connector->encoder != encoder)
12949 continue;
12950 connector->base.dpms = DRM_MODE_DPMS_OFF;
12951 connector->base.encoder = NULL;
12952 }
12953 }
12954 /* Enabled encoders without active connectors will be fixed in
12955 * the crtc fixup. */
12956 }
12957
12958 void i915_redisable_vga_power_on(struct drm_device *dev)
12959 {
12960 struct drm_i915_private *dev_priv = dev->dev_private;
12961 u32 vga_reg = i915_vgacntrl_reg(dev);
12962
12963 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12964 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12965 i915_disable_vga(dev);
12966 }
12967 }
12968
12969 void i915_redisable_vga(struct drm_device *dev)
12970 {
12971 struct drm_i915_private *dev_priv = dev->dev_private;
12972
12973 /* This function can be called both from intel_modeset_setup_hw_state or
12974 * at a very early point in our resume sequence, where the power well
12975 * structures are not yet restored. Since this function is at a very
12976 * paranoid "someone might have enabled VGA while we were not looking"
12977 * level, just check if the power well is enabled instead of trying to
12978 * follow the "don't touch the power well if we don't need it" policy
12979 * the rest of the driver uses. */
12980 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12981 return;
12982
12983 i915_redisable_vga_power_on(dev);
12984 }
12985
12986 static bool primary_get_hw_state(struct intel_crtc *crtc)
12987 {
12988 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12989
12990 if (!crtc->active)
12991 return false;
12992
12993 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12994 }
12995
12996 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12997 {
12998 struct drm_i915_private *dev_priv = dev->dev_private;
12999 enum pipe pipe;
13000 struct intel_crtc *crtc;
13001 struct intel_encoder *encoder;
13002 struct intel_connector *connector;
13003 int i;
13004
13005 for_each_intel_crtc(dev, crtc) {
13006 memset(&crtc->config, 0, sizeof(crtc->config));
13007
13008 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13009
13010 crtc->active = dev_priv->display.get_pipe_config(crtc,
13011 &crtc->config);
13012
13013 crtc->base.enabled = crtc->active;
13014 crtc->primary_enabled = primary_get_hw_state(crtc);
13015
13016 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13017 crtc->base.base.id,
13018 crtc->active ? "enabled" : "disabled");
13019 }
13020
13021 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13022 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13023
13024 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13025 pll->active = 0;
13026 for_each_intel_crtc(dev, crtc) {
13027 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13028 pll->active++;
13029 }
13030 pll->refcount = pll->active;
13031
13032 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13033 pll->name, pll->refcount, pll->on);
13034
13035 if (pll->refcount)
13036 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13037 }
13038
13039 for_each_intel_encoder(dev, encoder) {
13040 pipe = 0;
13041
13042 if (encoder->get_hw_state(encoder, &pipe)) {
13043 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13044 encoder->base.crtc = &crtc->base;
13045 encoder->get_config(encoder, &crtc->config);
13046 } else {
13047 encoder->base.crtc = NULL;
13048 }
13049
13050 encoder->connectors_active = false;
13051 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13052 encoder->base.base.id,
13053 encoder->base.name,
13054 encoder->base.crtc ? "enabled" : "disabled",
13055 pipe_name(pipe));
13056 }
13057
13058 list_for_each_entry(connector, &dev->mode_config.connector_list,
13059 base.head) {
13060 if (connector->get_hw_state(connector)) {
13061 connector->base.dpms = DRM_MODE_DPMS_ON;
13062 connector->encoder->connectors_active = true;
13063 connector->base.encoder = &connector->encoder->base;
13064 } else {
13065 connector->base.dpms = DRM_MODE_DPMS_OFF;
13066 connector->base.encoder = NULL;
13067 }
13068 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13069 connector->base.base.id,
13070 connector->base.name,
13071 connector->base.encoder ? "enabled" : "disabled");
13072 }
13073 }
13074
13075 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13076 * and i915 state tracking structures. */
13077 void intel_modeset_setup_hw_state(struct drm_device *dev,
13078 bool force_restore)
13079 {
13080 struct drm_i915_private *dev_priv = dev->dev_private;
13081 enum pipe pipe;
13082 struct intel_crtc *crtc;
13083 struct intel_encoder *encoder;
13084 int i;
13085
13086 intel_modeset_readout_hw_state(dev);
13087
13088 /*
13089 * Now that we have the config, copy it to each CRTC struct
13090 * Note that this could go away if we move to using crtc_config
13091 * checking everywhere.
13092 */
13093 for_each_intel_crtc(dev, crtc) {
13094 if (crtc->active && i915.fastboot) {
13095 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13096 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13097 crtc->base.base.id);
13098 drm_mode_debug_printmodeline(&crtc->base.mode);
13099 }
13100 }
13101
13102 /* HW state is read out, now we need to sanitize this mess. */
13103 for_each_intel_encoder(dev, encoder) {
13104 intel_sanitize_encoder(encoder);
13105 }
13106
13107 for_each_pipe(pipe) {
13108 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13109 intel_sanitize_crtc(crtc);
13110 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13111 }
13112
13113 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13114 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13115
13116 if (!pll->on || pll->active)
13117 continue;
13118
13119 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13120
13121 pll->disable(dev_priv, pll);
13122 pll->on = false;
13123 }
13124
13125 if (HAS_PCH_SPLIT(dev))
13126 ilk_wm_get_hw_state(dev);
13127
13128 if (force_restore) {
13129 i915_redisable_vga(dev);
13130
13131 /*
13132 * We need to use raw interfaces for restoring state to avoid
13133 * checking (bogus) intermediate states.
13134 */
13135 for_each_pipe(pipe) {
13136 struct drm_crtc *crtc =
13137 dev_priv->pipe_to_crtc_mapping[pipe];
13138
13139 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13140 crtc->primary->fb);
13141 }
13142 } else {
13143 intel_modeset_update_staged_output_state(dev);
13144 }
13145
13146 intel_modeset_check_state(dev);
13147 }
13148
13149 void intel_modeset_gem_init(struct drm_device *dev)
13150 {
13151 struct drm_crtc *c;
13152 struct drm_i915_gem_object *obj;
13153
13154 mutex_lock(&dev->struct_mutex);
13155 intel_init_gt_powersave(dev);
13156 mutex_unlock(&dev->struct_mutex);
13157
13158 intel_modeset_init_hw(dev);
13159
13160 intel_setup_overlay(dev);
13161
13162 /*
13163 * Make sure any fbs we allocated at startup are properly
13164 * pinned & fenced. When we do the allocation it's too early
13165 * for this.
13166 */
13167 mutex_lock(&dev->struct_mutex);
13168 for_each_crtc(dev, c) {
13169 obj = intel_fb_obj(c->primary->fb);
13170 if (obj == NULL)
13171 continue;
13172
13173 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13174 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13175 to_intel_crtc(c)->pipe);
13176 drm_framebuffer_unreference(c->primary->fb);
13177 c->primary->fb = NULL;
13178 }
13179 }
13180 mutex_unlock(&dev->struct_mutex);
13181 }
13182
13183 void intel_connector_unregister(struct intel_connector *intel_connector)
13184 {
13185 struct drm_connector *connector = &intel_connector->base;
13186
13187 intel_panel_destroy_backlight(connector);
13188 drm_connector_unregister(connector);
13189 }
13190
13191 void intel_modeset_cleanup(struct drm_device *dev)
13192 {
13193 struct drm_i915_private *dev_priv = dev->dev_private;
13194 struct drm_connector *connector;
13195
13196 /*
13197 * Interrupts and polling as the first thing to avoid creating havoc.
13198 * Too much stuff here (turning of rps, connectors, ...) would
13199 * experience fancy races otherwise.
13200 */
13201 drm_irq_uninstall(dev);
13202 intel_hpd_cancel_work(dev_priv);
13203 dev_priv->pm._irqs_disabled = true;
13204
13205 /*
13206 * Due to the hpd irq storm handling the hotplug work can re-arm the
13207 * poll handlers. Hence disable polling after hpd handling is shut down.
13208 */
13209 drm_kms_helper_poll_fini(dev);
13210
13211 mutex_lock(&dev->struct_mutex);
13212
13213 intel_unregister_dsm_handler();
13214
13215 intel_disable_fbc(dev);
13216
13217 intel_disable_gt_powersave(dev);
13218
13219 ironlake_teardown_rc6(dev);
13220
13221 mutex_unlock(&dev->struct_mutex);
13222
13223 /* flush any delayed tasks or pending work */
13224 flush_scheduled_work();
13225
13226 /* destroy the backlight and sysfs files before encoders/connectors */
13227 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13228 struct intel_connector *intel_connector;
13229
13230 intel_connector = to_intel_connector(connector);
13231 intel_connector->unregister(intel_connector);
13232 }
13233
13234 drm_mode_config_cleanup(dev);
13235
13236 intel_cleanup_overlay(dev);
13237
13238 mutex_lock(&dev->struct_mutex);
13239 intel_cleanup_gt_powersave(dev);
13240 mutex_unlock(&dev->struct_mutex);
13241 }
13242
13243 /*
13244 * Return which encoder is currently attached for connector.
13245 */
13246 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13247 {
13248 return &intel_attached_encoder(connector)->base;
13249 }
13250
13251 void intel_connector_attach_encoder(struct intel_connector *connector,
13252 struct intel_encoder *encoder)
13253 {
13254 connector->encoder = encoder;
13255 drm_mode_connector_attach_encoder(&connector->base,
13256 &encoder->base);
13257 }
13258
13259 /*
13260 * set vga decode state - true == enable VGA decode
13261 */
13262 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13263 {
13264 struct drm_i915_private *dev_priv = dev->dev_private;
13265 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13266 u16 gmch_ctrl;
13267
13268 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13269 DRM_ERROR("failed to read control word\n");
13270 return -EIO;
13271 }
13272
13273 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13274 return 0;
13275
13276 if (state)
13277 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13278 else
13279 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13280
13281 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13282 DRM_ERROR("failed to write control word\n");
13283 return -EIO;
13284 }
13285
13286 return 0;
13287 }
13288
13289 struct intel_display_error_state {
13290
13291 u32 power_well_driver;
13292
13293 int num_transcoders;
13294
13295 struct intel_cursor_error_state {
13296 u32 control;
13297 u32 position;
13298 u32 base;
13299 u32 size;
13300 } cursor[I915_MAX_PIPES];
13301
13302 struct intel_pipe_error_state {
13303 bool power_domain_on;
13304 u32 source;
13305 u32 stat;
13306 } pipe[I915_MAX_PIPES];
13307
13308 struct intel_plane_error_state {
13309 u32 control;
13310 u32 stride;
13311 u32 size;
13312 u32 pos;
13313 u32 addr;
13314 u32 surface;
13315 u32 tile_offset;
13316 } plane[I915_MAX_PIPES];
13317
13318 struct intel_transcoder_error_state {
13319 bool power_domain_on;
13320 enum transcoder cpu_transcoder;
13321
13322 u32 conf;
13323
13324 u32 htotal;
13325 u32 hblank;
13326 u32 hsync;
13327 u32 vtotal;
13328 u32 vblank;
13329 u32 vsync;
13330 } transcoder[4];
13331 };
13332
13333 struct intel_display_error_state *
13334 intel_display_capture_error_state(struct drm_device *dev)
13335 {
13336 struct drm_i915_private *dev_priv = dev->dev_private;
13337 struct intel_display_error_state *error;
13338 int transcoders[] = {
13339 TRANSCODER_A,
13340 TRANSCODER_B,
13341 TRANSCODER_C,
13342 TRANSCODER_EDP,
13343 };
13344 int i;
13345
13346 if (INTEL_INFO(dev)->num_pipes == 0)
13347 return NULL;
13348
13349 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13350 if (error == NULL)
13351 return NULL;
13352
13353 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13354 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13355
13356 for_each_pipe(i) {
13357 error->pipe[i].power_domain_on =
13358 intel_display_power_enabled_unlocked(dev_priv,
13359 POWER_DOMAIN_PIPE(i));
13360 if (!error->pipe[i].power_domain_on)
13361 continue;
13362
13363 error->cursor[i].control = I915_READ(CURCNTR(i));
13364 error->cursor[i].position = I915_READ(CURPOS(i));
13365 error->cursor[i].base = I915_READ(CURBASE(i));
13366
13367 error->plane[i].control = I915_READ(DSPCNTR(i));
13368 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13369 if (INTEL_INFO(dev)->gen <= 3) {
13370 error->plane[i].size = I915_READ(DSPSIZE(i));
13371 error->plane[i].pos = I915_READ(DSPPOS(i));
13372 }
13373 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13374 error->plane[i].addr = I915_READ(DSPADDR(i));
13375 if (INTEL_INFO(dev)->gen >= 4) {
13376 error->plane[i].surface = I915_READ(DSPSURF(i));
13377 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13378 }
13379
13380 error->pipe[i].source = I915_READ(PIPESRC(i));
13381
13382 if (HAS_GMCH_DISPLAY(dev))
13383 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13384 }
13385
13386 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13387 if (HAS_DDI(dev_priv->dev))
13388 error->num_transcoders++; /* Account for eDP. */
13389
13390 for (i = 0; i < error->num_transcoders; i++) {
13391 enum transcoder cpu_transcoder = transcoders[i];
13392
13393 error->transcoder[i].power_domain_on =
13394 intel_display_power_enabled_unlocked(dev_priv,
13395 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13396 if (!error->transcoder[i].power_domain_on)
13397 continue;
13398
13399 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13400
13401 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13402 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13403 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13404 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13405 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13406 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13407 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13408 }
13409
13410 return error;
13411 }
13412
13413 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13414
13415 void
13416 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13417 struct drm_device *dev,
13418 struct intel_display_error_state *error)
13419 {
13420 int i;
13421
13422 if (!error)
13423 return;
13424
13425 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13426 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13427 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13428 error->power_well_driver);
13429 for_each_pipe(i) {
13430 err_printf(m, "Pipe [%d]:\n", i);
13431 err_printf(m, " Power: %s\n",
13432 error->pipe[i].power_domain_on ? "on" : "off");
13433 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13434 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13435
13436 err_printf(m, "Plane [%d]:\n", i);
13437 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13438 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13439 if (INTEL_INFO(dev)->gen <= 3) {
13440 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13441 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13442 }
13443 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13444 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13445 if (INTEL_INFO(dev)->gen >= 4) {
13446 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13447 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13448 }
13449
13450 err_printf(m, "Cursor [%d]:\n", i);
13451 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13452 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13453 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13454 }
13455
13456 for (i = 0; i < error->num_transcoders; i++) {
13457 err_printf(m, "CPU transcoder: %c\n",
13458 transcoder_name(error->transcoder[i].cpu_transcoder));
13459 err_printf(m, " Power: %s\n",
13460 error->transcoder[i].power_domain_on ? "on" : "off");
13461 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13462 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13463 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13464 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13465 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13466 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13467 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13468 }
13469 }
13470
13471 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13472 {
13473 struct intel_crtc *crtc;
13474
13475 for_each_intel_crtc(dev, crtc) {
13476 struct intel_unpin_work *work;
13477 unsigned long irqflags;
13478
13479 spin_lock_irqsave(&dev->event_lock, irqflags);
13480
13481 work = crtc->unpin_work;
13482
13483 if (work && work->event &&
13484 work->event->base.file_priv == file) {
13485 kfree(work->event);
13486 work->event = NULL;
13487 }
13488
13489 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13490 }
13491 }
Linux kernel - Deliverables
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