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Merge tag 'devicetree-fixes-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 u32 reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 int reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 int pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1484 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1485 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1486 return false;
1487 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1488 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1489 return false;
1490 } else {
1491 if ((val & DP_PIPE_MASK) != (pipe << 30))
1492 return false;
1493 }
1494 return true;
1495 }
1496
1497 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1498 enum pipe pipe, u32 val)
1499 {
1500 if ((val & SDVO_ENABLE) == 0)
1501 return false;
1502
1503 if (HAS_PCH_CPT(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1505 return false;
1506 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1507 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1508 return false;
1509 } else {
1510 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1511 return false;
1512 }
1513 return true;
1514 }
1515
1516 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1517 enum pipe pipe, u32 val)
1518 {
1519 if ((val & LVDS_PORT_EN) == 0)
1520 return false;
1521
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1527 return false;
1528 }
1529 return true;
1530 }
1531
1532 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1533 enum pipe pipe, u32 val)
1534 {
1535 if ((val & ADPA_DAC_ENABLE) == 0)
1536 return false;
1537 if (HAS_PCH_CPT(dev_priv->dev)) {
1538 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1539 return false;
1540 } else {
1541 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1542 return false;
1543 }
1544 return true;
1545 }
1546
1547 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1548 enum pipe pipe, int reg, u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg, pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, int reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg, pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /*
1717 * Apparently we need to have VGA mode enabled prior to changing
1718 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719 * dividers, even though the register value does change.
1720 */
1721 I915_WRITE(reg, 0);
1722
1723 I915_WRITE(reg, dpll);
1724
1725 /* Wait for the clocks to stabilize. */
1726 POSTING_READ(reg);
1727 udelay(150);
1728
1729 if (INTEL_INFO(dev)->gen >= 4) {
1730 I915_WRITE(DPLL_MD(crtc->pipe),
1731 crtc->config->dpll_hw_state.dpll_md);
1732 } else {
1733 /* The pixel multiplier can only be updated once the
1734 * DPLL is enabled and the clocks are stable.
1735 *
1736 * So write it again.
1737 */
1738 I915_WRITE(reg, dpll);
1739 }
1740
1741 /* We do this three times for luck */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754 * i9xx_disable_pll - disable a PLL
1755 * @dev_priv: i915 private structure
1756 * @pipe: pipe PLL to disable
1757 *
1758 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 *
1760 * Note! This is for pre-ILK only.
1761 */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 enum pipe pipe = crtc->pipe;
1767
1768 /* Disable DVO 2x clock on both PLLs if necessary */
1769 if (IS_I830(dev) &&
1770 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771 !intel_num_dvo_pipes(dev)) {
1772 I915_WRITE(DPLL(PIPE_B),
1773 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774 I915_WRITE(DPLL(PIPE_A),
1775 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776 }
1777
1778 /* Don't disable pipe or pipe PLLs if needed */
1779 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781 return;
1782
1783 /* Make sure the pipe isn't still relying on us */
1784 assert_pipe_disabled(dev_priv, pipe);
1785
1786 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787 POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792 u32 val;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 /*
1798 * Leave integrated clock source and reference clock enabled for pipe B.
1799 * The latter is needed for VGA hotplug / manual detection.
1800 */
1801 val = DPLL_VGA_MODE_DIS;
1802 if (pipe == PIPE_B)
1803 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804 I915_WRITE(DPLL(pipe), val);
1805 POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812 u32 val;
1813
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv, pipe);
1816
1817 /* Set PLL en = 0 */
1818 val = DPLL_SSC_REF_CLK_CHV |
1819 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->sb_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 int dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 if (INTEL_INFO(dev)->gen < 5)
1930 return;
1931
1932 if (pll == NULL)
1933 return;
1934
1935 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936 return;
1937
1938 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939 pll->name, pll->active, pll->on,
1940 crtc->base.base.id);
1941
1942 if (WARN_ON(pll->active == 0)) {
1943 assert_shared_dpll_disabled(dev_priv, pll);
1944 return;
1945 }
1946
1947 assert_shared_dpll_enabled(dev_priv, pll);
1948 WARN_ON(!pll->on);
1949 if (--pll->active)
1950 return;
1951
1952 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953 pll->disable(dev_priv, pll);
1954 pll->on = false;
1955
1956 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 uint32_t reg, val, pipeconf_val;
1966
1967 /* PCH only available on ILK+ */
1968 BUG_ON(!HAS_PCH_SPLIT(dev));
1969
1970 /* Make sure PCH DPLL is enabled */
1971 assert_shared_dpll_enabled(dev_priv,
1972 intel_crtc_to_shared_dpll(intel_crtc));
1973
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv, pipe);
1976 assert_fdi_rx_enabled(dev_priv, pipe);
1977
1978 if (HAS_PCH_CPT(dev)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg = TRANS_CHICKEN2(pipe);
1982 val = I915_READ(reg);
1983 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1984 I915_WRITE(reg, val);
1985 }
1986
1987 reg = PCH_TRANSCONF(pipe);
1988 val = I915_READ(reg);
1989 pipeconf_val = I915_READ(PIPECONF(pipe));
1990
1991 if (HAS_PCH_IBX(dev_priv->dev)) {
1992 /*
1993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
1996 */
1997 val &= ~PIPECONF_BPC_MASK;
1998 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1999 val |= PIPECONF_8BPC;
2000 else
2001 val |= pipeconf_val & PIPECONF_BPC_MASK;
2002 }
2003
2004 val &= ~TRANS_INTERLACE_MASK;
2005 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2006 if (HAS_PCH_IBX(dev_priv->dev) &&
2007 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2008 val |= TRANS_LEGACY_INTERLACED_ILK;
2009 else
2010 val |= TRANS_INTERLACED;
2011 else
2012 val |= TRANS_PROGRESSIVE;
2013
2014 I915_WRITE(reg, val | TRANS_ENABLE);
2015 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2017 }
2018
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2020 enum transcoder cpu_transcoder)
2021 {
2022 u32 val, pipeconf_val;
2023
2024 /* PCH only available on ILK+ */
2025 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2026
2027 /* FDI must be feeding us bits for PCH ports */
2028 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2029 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2030
2031 /* Workaround: set timing override bit. */
2032 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2033 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2034 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2035
2036 val = TRANS_ENABLE;
2037 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2038
2039 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2040 PIPECONF_INTERLACED_ILK)
2041 val |= TRANS_INTERLACED;
2042 else
2043 val |= TRANS_PROGRESSIVE;
2044
2045 I915_WRITE(LPT_TRANSCONF, val);
2046 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2047 DRM_ERROR("Failed to enable PCH transcoder\n");
2048 }
2049
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2051 enum pipe pipe)
2052 {
2053 struct drm_device *dev = dev_priv->dev;
2054 uint32_t reg, val;
2055
2056 /* FDI relies on the transcoder */
2057 assert_fdi_tx_disabled(dev_priv, pipe);
2058 assert_fdi_rx_disabled(dev_priv, pipe);
2059
2060 /* Ports must be off as well */
2061 assert_pch_ports_disabled(dev_priv, pipe);
2062
2063 reg = PCH_TRANSCONF(pipe);
2064 val = I915_READ(reg);
2065 val &= ~TRANS_ENABLE;
2066 I915_WRITE(reg, val);
2067 /* wait for PCH transcoder off, transcoder state */
2068 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2069 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2070
2071 if (!HAS_PCH_IBX(dev)) {
2072 /* Workaround: Clear the timing override chicken bit again. */
2073 reg = TRANS_CHICKEN2(pipe);
2074 val = I915_READ(reg);
2075 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2076 I915_WRITE(reg, val);
2077 }
2078 }
2079
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2081 {
2082 u32 val;
2083
2084 val = I915_READ(LPT_TRANSCONF);
2085 val &= ~TRANS_ENABLE;
2086 I915_WRITE(LPT_TRANSCONF, val);
2087 /* wait for PCH transcoder off, transcoder state */
2088 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2089 DRM_ERROR("Failed to disable PCH transcoder\n");
2090
2091 /* Workaround: clear timing override bit. */
2092 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2095 }
2096
2097 /**
2098 * intel_enable_pipe - enable a pipe, asserting requirements
2099 * @crtc: crtc responsible for the pipe
2100 *
2101 * Enable @crtc's pipe, making sure that various hardware specific requirements
2102 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2103 */
2104 static void intel_enable_pipe(struct intel_crtc *crtc)
2105 {
2106 struct drm_device *dev = crtc->base.dev;
2107 struct drm_i915_private *dev_priv = dev->dev_private;
2108 enum pipe pipe = crtc->pipe;
2109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2110 pipe);
2111 enum pipe pch_transcoder;
2112 int reg;
2113 u32 val;
2114
2115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2116
2117 assert_planes_disabled(dev_priv, pipe);
2118 assert_cursor_disabled(dev_priv, pipe);
2119 assert_sprites_disabled(dev_priv, pipe);
2120
2121 if (HAS_PCH_LPT(dev_priv->dev))
2122 pch_transcoder = TRANSCODER_A;
2123 else
2124 pch_transcoder = pipe;
2125
2126 /*
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2129 * need the check.
2130 */
2131 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2132 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2133 assert_dsi_pll_enabled(dev_priv);
2134 else
2135 assert_pll_enabled(dev_priv, pipe);
2136 else {
2137 if (crtc->config->has_pch_encoder) {
2138 /* if driving the PCH, we need FDI enabled */
2139 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2140 assert_fdi_tx_pll_enabled(dev_priv,
2141 (enum pipe) cpu_transcoder);
2142 }
2143 /* FIXME: assert CPU port conditions for SNB+ */
2144 }
2145
2146 reg = PIPECONF(cpu_transcoder);
2147 val = I915_READ(reg);
2148 if (val & PIPECONF_ENABLE) {
2149 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2150 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2151 return;
2152 }
2153
2154 I915_WRITE(reg, val | PIPECONF_ENABLE);
2155 POSTING_READ(reg);
2156 }
2157
2158 /**
2159 * intel_disable_pipe - disable a pipe, asserting requirements
2160 * @crtc: crtc whose pipes is to be disabled
2161 *
2162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
2165 *
2166 * Will wait until the pipe has shut down before returning.
2167 */
2168 static void intel_disable_pipe(struct intel_crtc *crtc)
2169 {
2170 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2171 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2172 enum pipe pipe = crtc->pipe;
2173 int reg;
2174 u32 val;
2175
2176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
2183 assert_cursor_disabled(dev_priv, pipe);
2184 assert_sprites_disabled(dev_priv, pipe);
2185
2186 reg = PIPECONF(cpu_transcoder);
2187 val = I915_READ(reg);
2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
2195 if (crtc->config->double_wide)
2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
2206 }
2207
2208 static bool need_vtd_wa(struct drm_device *dev)
2209 {
2210 #ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2212 return true;
2213 #endif
2214 return false;
2215 }
2216
2217 unsigned int
2218 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2219 uint64_t fb_format_modifier, unsigned int plane)
2220 {
2221 unsigned int tile_height;
2222 uint32_t pixel_bytes;
2223
2224 switch (fb_format_modifier) {
2225 case DRM_FORMAT_MOD_NONE:
2226 tile_height = 1;
2227 break;
2228 case I915_FORMAT_MOD_X_TILED:
2229 tile_height = IS_GEN2(dev) ? 16 : 8;
2230 break;
2231 case I915_FORMAT_MOD_Y_TILED:
2232 tile_height = 32;
2233 break;
2234 case I915_FORMAT_MOD_Yf_TILED:
2235 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2236 switch (pixel_bytes) {
2237 default:
2238 case 1:
2239 tile_height = 64;
2240 break;
2241 case 2:
2242 case 4:
2243 tile_height = 32;
2244 break;
2245 case 8:
2246 tile_height = 16;
2247 break;
2248 case 16:
2249 WARN_ONCE(1,
2250 "128-bit pixels are not supported for display!");
2251 tile_height = 16;
2252 break;
2253 }
2254 break;
2255 default:
2256 MISSING_CASE(fb_format_modifier);
2257 tile_height = 1;
2258 break;
2259 }
2260
2261 return tile_height;
2262 }
2263
2264 unsigned int
2265 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2266 uint32_t pixel_format, uint64_t fb_format_modifier)
2267 {
2268 return ALIGN(height, intel_tile_height(dev, pixel_format,
2269 fb_format_modifier, 0));
2270 }
2271
2272 static int
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2274 const struct drm_plane_state *plane_state)
2275 {
2276 struct intel_rotation_info *info = &view->rotation_info;
2277 unsigned int tile_height, tile_pitch;
2278
2279 *view = i915_ggtt_view_normal;
2280
2281 if (!plane_state)
2282 return 0;
2283
2284 if (!intel_rotation_90_or_270(plane_state->rotation))
2285 return 0;
2286
2287 *view = i915_ggtt_view_rotated;
2288
2289 info->height = fb->height;
2290 info->pixel_format = fb->pixel_format;
2291 info->pitch = fb->pitches[0];
2292 info->uv_offset = fb->offsets[1];
2293 info->fb_modifier = fb->modifier[0];
2294
2295 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2296 fb->modifier[0], 0);
2297 tile_pitch = PAGE_SIZE / tile_height;
2298 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2299 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2300 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2301
2302 if (info->pixel_format == DRM_FORMAT_NV12) {
2303 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2304 fb->modifier[0], 1);
2305 tile_pitch = PAGE_SIZE / tile_height;
2306 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2307 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2308 tile_height);
2309 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2310 PAGE_SIZE;
2311 }
2312
2313 return 0;
2314 }
2315
2316 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2317 {
2318 if (INTEL_INFO(dev_priv)->gen >= 9)
2319 return 256 * 1024;
2320 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2321 IS_VALLEYVIEW(dev_priv))
2322 return 128 * 1024;
2323 else if (INTEL_INFO(dev_priv)->gen >= 4)
2324 return 4 * 1024;
2325 else
2326 return 0;
2327 }
2328
2329 int
2330 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2331 struct drm_framebuffer *fb,
2332 const struct drm_plane_state *plane_state,
2333 struct intel_engine_cs *pipelined,
2334 struct drm_i915_gem_request **pipelined_request)
2335 {
2336 struct drm_device *dev = fb->dev;
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2339 struct i915_ggtt_view view;
2340 u32 alignment;
2341 int ret;
2342
2343 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2344
2345 switch (fb->modifier[0]) {
2346 case DRM_FORMAT_MOD_NONE:
2347 alignment = intel_linear_alignment(dev_priv);
2348 break;
2349 case I915_FORMAT_MOD_X_TILED:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
2356 break;
2357 case I915_FORMAT_MOD_Y_TILED:
2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
2364 default:
2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
2367 }
2368
2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
2390 dev_priv->mm.interruptible = false;
2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2392 pipelined_request, &view);
2393 if (ret)
2394 goto err_interruptible;
2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
2401 if (view.type == I915_GGTT_VIEW_NORMAL) {
2402 ret = i915_gem_object_get_fence(obj);
2403 if (ret == -EDEADLK) {
2404 /*
2405 * -EDEADLK means there are no free fences
2406 * no pending flips.
2407 *
2408 * This is propagated to atomic, but it uses
2409 * -EDEADLK to force a locking recovery, so
2410 * change the returned error to -EBUSY.
2411 */
2412 ret = -EBUSY;
2413 goto err_unpin;
2414 } else if (ret)
2415 goto err_unpin;
2416
2417 i915_gem_object_pin_fence(obj);
2418 }
2419
2420 dev_priv->mm.interruptible = true;
2421 intel_runtime_pm_put(dev_priv);
2422 return 0;
2423
2424 err_unpin:
2425 i915_gem_object_unpin_from_display_plane(obj, &view);
2426 err_interruptible:
2427 dev_priv->mm.interruptible = true;
2428 intel_runtime_pm_put(dev_priv);
2429 return ret;
2430 }
2431
2432 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2433 const struct drm_plane_state *plane_state)
2434 {
2435 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2436 struct i915_ggtt_view view;
2437 int ret;
2438
2439 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442 WARN_ONCE(ret, "Couldn't get view from plane state!");
2443
2444 if (view.type == I915_GGTT_VIEW_NORMAL)
2445 i915_gem_object_unpin_fence(obj);
2446
2447 i915_gem_object_unpin_from_display_plane(obj, &view);
2448 }
2449
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
2457 {
2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
2460
2461 tile_rows = *y / 8;
2462 *y %= 8;
2463
2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
2476 }
2477 }
2478
2479 static int i9xx_format_to_fourcc(int format)
2480 {
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498 }
2499
2500 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501 {
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524 }
2525
2526 static bool
2527 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
2529 {
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_private *dev_priv = to_i915(dev);
2532 struct drm_i915_gem_object *obj = NULL;
2533 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2534 struct drm_framebuffer *fb = &plane_config->fb->base;
2535 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2536 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2537 PAGE_SIZE);
2538
2539 size_aligned -= base_aligned;
2540
2541 if (plane_config->size == 0)
2542 return false;
2543
2544 /* If the FB is too big, just don't use it since fbdev is not very
2545 * important and we should probably use that space with FBC or other
2546 * features. */
2547 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2548 return false;
2549
2550 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2551 base_aligned,
2552 base_aligned,
2553 size_aligned);
2554 if (!obj)
2555 return false;
2556
2557 obj->tiling_mode = plane_config->tiling;
2558 if (obj->tiling_mode == I915_TILING_X)
2559 obj->stride = fb->pitches[0];
2560
2561 mode_cmd.pixel_format = fb->pixel_format;
2562 mode_cmd.width = fb->width;
2563 mode_cmd.height = fb->height;
2564 mode_cmd.pitches[0] = fb->pitches[0];
2565 mode_cmd.modifier[0] = fb->modifier[0];
2566 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2567
2568 mutex_lock(&dev->struct_mutex);
2569 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2570 &mode_cmd, obj)) {
2571 DRM_DEBUG_KMS("intel fb init failed\n");
2572 goto out_unref_obj;
2573 }
2574 mutex_unlock(&dev->struct_mutex);
2575
2576 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2577 return true;
2578
2579 out_unref_obj:
2580 drm_gem_object_unreference(&obj->base);
2581 mutex_unlock(&dev->struct_mutex);
2582 return false;
2583 }
2584
2585 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2586 static void
2587 update_state_fb(struct drm_plane *plane)
2588 {
2589 if (plane->fb == plane->state->fb)
2590 return;
2591
2592 if (plane->state->fb)
2593 drm_framebuffer_unreference(plane->state->fb);
2594 plane->state->fb = plane->fb;
2595 if (plane->state->fb)
2596 drm_framebuffer_reference(plane->state->fb);
2597 }
2598
2599 static void
2600 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2601 struct intel_initial_plane_config *plane_config)
2602 {
2603 struct drm_device *dev = intel_crtc->base.dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct drm_crtc *c;
2606 struct intel_crtc *i;
2607 struct drm_i915_gem_object *obj;
2608 struct drm_plane *primary = intel_crtc->base.primary;
2609 struct drm_plane_state *plane_state = primary->state;
2610 struct drm_framebuffer *fb;
2611
2612 if (!plane_config->fb)
2613 return;
2614
2615 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2616 fb = &plane_config->fb->base;
2617 goto valid_fb;
2618 }
2619
2620 kfree(plane_config->fb);
2621
2622 /*
2623 * Failed to alloc the obj, check to see if we should share
2624 * an fb with another CRTC instead
2625 */
2626 for_each_crtc(dev, c) {
2627 i = to_intel_crtc(c);
2628
2629 if (c == &intel_crtc->base)
2630 continue;
2631
2632 if (!i->active)
2633 continue;
2634
2635 fb = c->primary->fb;
2636 if (!fb)
2637 continue;
2638
2639 obj = intel_fb_obj(fb);
2640 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2641 drm_framebuffer_reference(fb);
2642 goto valid_fb;
2643 }
2644 }
2645
2646 return;
2647
2648 valid_fb:
2649 plane_state->src_x = plane_state->src_y = 0;
2650 plane_state->src_w = fb->width << 16;
2651 plane_state->src_h = fb->height << 16;
2652
2653 plane_state->crtc_x = plane_state->src_y = 0;
2654 plane_state->crtc_w = fb->width;
2655 plane_state->crtc_h = fb->height;
2656
2657 obj = intel_fb_obj(fb);
2658 if (obj->tiling_mode != I915_TILING_NONE)
2659 dev_priv->preserve_bios_swizzle = true;
2660
2661 drm_framebuffer_reference(fb);
2662 primary->fb = primary->state->fb = fb;
2663 primary->crtc = primary->state->crtc = &intel_crtc->base;
2664 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2665 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2666 }
2667
2668 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2669 struct drm_framebuffer *fb,
2670 int x, int y)
2671 {
2672 struct drm_device *dev = crtc->dev;
2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2675 struct drm_plane *primary = crtc->primary;
2676 bool visible = to_intel_plane_state(primary->state)->visible;
2677 struct drm_i915_gem_object *obj;
2678 int plane = intel_crtc->plane;
2679 unsigned long linear_offset;
2680 u32 dspcntr;
2681 u32 reg = DSPCNTR(plane);
2682 int pixel_size;
2683
2684 if (!visible || !fb) {
2685 I915_WRITE(reg, 0);
2686 if (INTEL_INFO(dev)->gen >= 4)
2687 I915_WRITE(DSPSURF(plane), 0);
2688 else
2689 I915_WRITE(DSPADDR(plane), 0);
2690 POSTING_READ(reg);
2691 return;
2692 }
2693
2694 obj = intel_fb_obj(fb);
2695 if (WARN_ON(obj == NULL))
2696 return;
2697
2698 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2699
2700 dspcntr = DISPPLANE_GAMMA_ENABLE;
2701
2702 dspcntr |= DISPLAY_PLANE_ENABLE;
2703
2704 if (INTEL_INFO(dev)->gen < 4) {
2705 if (intel_crtc->pipe == PIPE_B)
2706 dspcntr |= DISPPLANE_SEL_PIPE_B;
2707
2708 /* pipesrc and dspsize control the size that is scaled from,
2709 * which should always be the user's requested size.
2710 */
2711 I915_WRITE(DSPSIZE(plane),
2712 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2713 (intel_crtc->config->pipe_src_w - 1));
2714 I915_WRITE(DSPPOS(plane), 0);
2715 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2716 I915_WRITE(PRIMSIZE(plane),
2717 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2718 (intel_crtc->config->pipe_src_w - 1));
2719 I915_WRITE(PRIMPOS(plane), 0);
2720 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2721 }
2722
2723 switch (fb->pixel_format) {
2724 case DRM_FORMAT_C8:
2725 dspcntr |= DISPPLANE_8BPP;
2726 break;
2727 case DRM_FORMAT_XRGB1555:
2728 dspcntr |= DISPPLANE_BGRX555;
2729 break;
2730 case DRM_FORMAT_RGB565:
2731 dspcntr |= DISPPLANE_BGRX565;
2732 break;
2733 case DRM_FORMAT_XRGB8888:
2734 dspcntr |= DISPPLANE_BGRX888;
2735 break;
2736 case DRM_FORMAT_XBGR8888:
2737 dspcntr |= DISPPLANE_RGBX888;
2738 break;
2739 case DRM_FORMAT_XRGB2101010:
2740 dspcntr |= DISPPLANE_BGRX101010;
2741 break;
2742 case DRM_FORMAT_XBGR2101010:
2743 dspcntr |= DISPPLANE_RGBX101010;
2744 break;
2745 default:
2746 BUG();
2747 }
2748
2749 if (INTEL_INFO(dev)->gen >= 4 &&
2750 obj->tiling_mode != I915_TILING_NONE)
2751 dspcntr |= DISPPLANE_TILED;
2752
2753 if (IS_G4X(dev))
2754 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2755
2756 linear_offset = y * fb->pitches[0] + x * pixel_size;
2757
2758 if (INTEL_INFO(dev)->gen >= 4) {
2759 intel_crtc->dspaddr_offset =
2760 intel_gen4_compute_page_offset(dev_priv,
2761 &x, &y, obj->tiling_mode,
2762 pixel_size,
2763 fb->pitches[0]);
2764 linear_offset -= intel_crtc->dspaddr_offset;
2765 } else {
2766 intel_crtc->dspaddr_offset = linear_offset;
2767 }
2768
2769 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2770 dspcntr |= DISPPLANE_ROTATE_180;
2771
2772 x += (intel_crtc->config->pipe_src_w - 1);
2773 y += (intel_crtc->config->pipe_src_h - 1);
2774
2775 /* Finding the last pixel of the last line of the display
2776 data and adding to linear_offset*/
2777 linear_offset +=
2778 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2779 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2780 }
2781
2782 intel_crtc->adjusted_x = x;
2783 intel_crtc->adjusted_y = y;
2784
2785 I915_WRITE(reg, dspcntr);
2786
2787 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2788 if (INTEL_INFO(dev)->gen >= 4) {
2789 I915_WRITE(DSPSURF(plane),
2790 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2791 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2792 I915_WRITE(DSPLINOFF(plane), linear_offset);
2793 } else
2794 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2795 POSTING_READ(reg);
2796 }
2797
2798 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2799 struct drm_framebuffer *fb,
2800 int x, int y)
2801 {
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 struct drm_plane *primary = crtc->primary;
2806 bool visible = to_intel_plane_state(primary->state)->visible;
2807 struct drm_i915_gem_object *obj;
2808 int plane = intel_crtc->plane;
2809 unsigned long linear_offset;
2810 u32 dspcntr;
2811 u32 reg = DSPCNTR(plane);
2812 int pixel_size;
2813
2814 if (!visible || !fb) {
2815 I915_WRITE(reg, 0);
2816 I915_WRITE(DSPSURF(plane), 0);
2817 POSTING_READ(reg);
2818 return;
2819 }
2820
2821 obj = intel_fb_obj(fb);
2822 if (WARN_ON(obj == NULL))
2823 return;
2824
2825 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2826
2827 dspcntr = DISPPLANE_GAMMA_ENABLE;
2828
2829 dspcntr |= DISPLAY_PLANE_ENABLE;
2830
2831 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2832 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2833
2834 switch (fb->pixel_format) {
2835 case DRM_FORMAT_C8:
2836 dspcntr |= DISPPLANE_8BPP;
2837 break;
2838 case DRM_FORMAT_RGB565:
2839 dspcntr |= DISPPLANE_BGRX565;
2840 break;
2841 case DRM_FORMAT_XRGB8888:
2842 dspcntr |= DISPPLANE_BGRX888;
2843 break;
2844 case DRM_FORMAT_XBGR8888:
2845 dspcntr |= DISPPLANE_RGBX888;
2846 break;
2847 case DRM_FORMAT_XRGB2101010:
2848 dspcntr |= DISPPLANE_BGRX101010;
2849 break;
2850 case DRM_FORMAT_XBGR2101010:
2851 dspcntr |= DISPPLANE_RGBX101010;
2852 break;
2853 default:
2854 BUG();
2855 }
2856
2857 if (obj->tiling_mode != I915_TILING_NONE)
2858 dspcntr |= DISPPLANE_TILED;
2859
2860 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2861 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2862
2863 linear_offset = y * fb->pitches[0] + x * pixel_size;
2864 intel_crtc->dspaddr_offset =
2865 intel_gen4_compute_page_offset(dev_priv,
2866 &x, &y, obj->tiling_mode,
2867 pixel_size,
2868 fb->pitches[0]);
2869 linear_offset -= intel_crtc->dspaddr_offset;
2870 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2871 dspcntr |= DISPPLANE_ROTATE_180;
2872
2873 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2874 x += (intel_crtc->config->pipe_src_w - 1);
2875 y += (intel_crtc->config->pipe_src_h - 1);
2876
2877 /* Finding the last pixel of the last line of the display
2878 data and adding to linear_offset*/
2879 linear_offset +=
2880 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2881 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2882 }
2883 }
2884
2885 intel_crtc->adjusted_x = x;
2886 intel_crtc->adjusted_y = y;
2887
2888 I915_WRITE(reg, dspcntr);
2889
2890 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2891 I915_WRITE(DSPSURF(plane),
2892 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2893 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2894 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2895 } else {
2896 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2897 I915_WRITE(DSPLINOFF(plane), linear_offset);
2898 }
2899 POSTING_READ(reg);
2900 }
2901
2902 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2903 uint32_t pixel_format)
2904 {
2905 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2906
2907 /*
2908 * The stride is either expressed as a multiple of 64 bytes
2909 * chunks for linear buffers or in number of tiles for tiled
2910 * buffers.
2911 */
2912 switch (fb_modifier) {
2913 case DRM_FORMAT_MOD_NONE:
2914 return 64;
2915 case I915_FORMAT_MOD_X_TILED:
2916 if (INTEL_INFO(dev)->gen == 2)
2917 return 128;
2918 return 512;
2919 case I915_FORMAT_MOD_Y_TILED:
2920 /* No need to check for old gens and Y tiling since this is
2921 * about the display engine and those will be blocked before
2922 * we get here.
2923 */
2924 return 128;
2925 case I915_FORMAT_MOD_Yf_TILED:
2926 if (bits_per_pixel == 8)
2927 return 64;
2928 else
2929 return 128;
2930 default:
2931 MISSING_CASE(fb_modifier);
2932 return 64;
2933 }
2934 }
2935
2936 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2937 struct drm_i915_gem_object *obj,
2938 unsigned int plane)
2939 {
2940 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2941 struct i915_vma *vma;
2942 unsigned char *offset;
2943
2944 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2945 view = &i915_ggtt_view_rotated;
2946
2947 vma = i915_gem_obj_to_ggtt_view(obj, view);
2948 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2949 view->type))
2950 return -1;
2951
2952 offset = (unsigned char *)vma->node.start;
2953
2954 if (plane == 1) {
2955 offset += vma->ggtt_view.rotation_info.uv_start_page *
2956 PAGE_SIZE;
2957 }
2958
2959 return (unsigned long)offset;
2960 }
2961
2962 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2963 {
2964 struct drm_device *dev = intel_crtc->base.dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
2966
2967 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2968 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2969 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2970 }
2971
2972 /*
2973 * This function detaches (aka. unbinds) unused scalers in hardware
2974 */
2975 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2976 {
2977 struct intel_crtc_scaler_state *scaler_state;
2978 int i;
2979
2980 scaler_state = &intel_crtc->config->scaler_state;
2981
2982 /* loop through and disable scalers that aren't in use */
2983 for (i = 0; i < intel_crtc->num_scalers; i++) {
2984 if (!scaler_state->scalers[i].in_use)
2985 skl_detach_scaler(intel_crtc, i);
2986 }
2987 }
2988
2989 u32 skl_plane_ctl_format(uint32_t pixel_format)
2990 {
2991 switch (pixel_format) {
2992 case DRM_FORMAT_C8:
2993 return PLANE_CTL_FORMAT_INDEXED;
2994 case DRM_FORMAT_RGB565:
2995 return PLANE_CTL_FORMAT_RGB_565;
2996 case DRM_FORMAT_XBGR8888:
2997 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2998 case DRM_FORMAT_XRGB8888:
2999 return PLANE_CTL_FORMAT_XRGB_8888;
3000 /*
3001 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3002 * to be already pre-multiplied. We need to add a knob (or a different
3003 * DRM_FORMAT) for user-space to configure that.
3004 */
3005 case DRM_FORMAT_ABGR8888:
3006 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3007 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3008 case DRM_FORMAT_ARGB8888:
3009 return PLANE_CTL_FORMAT_XRGB_8888 |
3010 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3011 case DRM_FORMAT_XRGB2101010:
3012 return PLANE_CTL_FORMAT_XRGB_2101010;
3013 case DRM_FORMAT_XBGR2101010:
3014 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3015 case DRM_FORMAT_YUYV:
3016 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3017 case DRM_FORMAT_YVYU:
3018 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3019 case DRM_FORMAT_UYVY:
3020 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3021 case DRM_FORMAT_VYUY:
3022 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3023 default:
3024 MISSING_CASE(pixel_format);
3025 }
3026
3027 return 0;
3028 }
3029
3030 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3031 {
3032 switch (fb_modifier) {
3033 case DRM_FORMAT_MOD_NONE:
3034 break;
3035 case I915_FORMAT_MOD_X_TILED:
3036 return PLANE_CTL_TILED_X;
3037 case I915_FORMAT_MOD_Y_TILED:
3038 return PLANE_CTL_TILED_Y;
3039 case I915_FORMAT_MOD_Yf_TILED:
3040 return PLANE_CTL_TILED_YF;
3041 default:
3042 MISSING_CASE(fb_modifier);
3043 }
3044
3045 return 0;
3046 }
3047
3048 u32 skl_plane_ctl_rotation(unsigned int rotation)
3049 {
3050 switch (rotation) {
3051 case BIT(DRM_ROTATE_0):
3052 break;
3053 /*
3054 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3055 * while i915 HW rotation is clockwise, thats why this swapping.
3056 */
3057 case BIT(DRM_ROTATE_90):
3058 return PLANE_CTL_ROTATE_270;
3059 case BIT(DRM_ROTATE_180):
3060 return PLANE_CTL_ROTATE_180;
3061 case BIT(DRM_ROTATE_270):
3062 return PLANE_CTL_ROTATE_90;
3063 default:
3064 MISSING_CASE(rotation);
3065 }
3066
3067 return 0;
3068 }
3069
3070 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3071 struct drm_framebuffer *fb,
3072 int x, int y)
3073 {
3074 struct drm_device *dev = crtc->dev;
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3077 struct drm_plane *plane = crtc->primary;
3078 bool visible = to_intel_plane_state(plane->state)->visible;
3079 struct drm_i915_gem_object *obj;
3080 int pipe = intel_crtc->pipe;
3081 u32 plane_ctl, stride_div, stride;
3082 u32 tile_height, plane_offset, plane_size;
3083 unsigned int rotation;
3084 int x_offset, y_offset;
3085 unsigned long surf_addr;
3086 struct intel_crtc_state *crtc_state = intel_crtc->config;
3087 struct intel_plane_state *plane_state;
3088 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3089 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3090 int scaler_id = -1;
3091
3092 plane_state = to_intel_plane_state(plane->state);
3093
3094 if (!visible || !fb) {
3095 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3096 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3097 POSTING_READ(PLANE_CTL(pipe, 0));
3098 return;
3099 }
3100
3101 plane_ctl = PLANE_CTL_ENABLE |
3102 PLANE_CTL_PIPE_GAMMA_ENABLE |
3103 PLANE_CTL_PIPE_CSC_ENABLE;
3104
3105 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3106 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3107 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3108
3109 rotation = plane->state->rotation;
3110 plane_ctl |= skl_plane_ctl_rotation(rotation);
3111
3112 obj = intel_fb_obj(fb);
3113 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3114 fb->pixel_format);
3115 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3116
3117 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3118
3119 scaler_id = plane_state->scaler_id;
3120 src_x = plane_state->src.x1 >> 16;
3121 src_y = plane_state->src.y1 >> 16;
3122 src_w = drm_rect_width(&plane_state->src) >> 16;
3123 src_h = drm_rect_height(&plane_state->src) >> 16;
3124 dst_x = plane_state->dst.x1;
3125 dst_y = plane_state->dst.y1;
3126 dst_w = drm_rect_width(&plane_state->dst);
3127 dst_h = drm_rect_height(&plane_state->dst);
3128
3129 WARN_ON(x != src_x || y != src_y);
3130
3131 if (intel_rotation_90_or_270(rotation)) {
3132 /* stride = Surface height in tiles */
3133 tile_height = intel_tile_height(dev, fb->pixel_format,
3134 fb->modifier[0], 0);
3135 stride = DIV_ROUND_UP(fb->height, tile_height);
3136 x_offset = stride * tile_height - y - src_h;
3137 y_offset = x;
3138 plane_size = (src_w - 1) << 16 | (src_h - 1);
3139 } else {
3140 stride = fb->pitches[0] / stride_div;
3141 x_offset = x;
3142 y_offset = y;
3143 plane_size = (src_h - 1) << 16 | (src_w - 1);
3144 }
3145 plane_offset = y_offset << 16 | x_offset;
3146
3147 intel_crtc->adjusted_x = x_offset;
3148 intel_crtc->adjusted_y = y_offset;
3149
3150 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3151 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3152 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3153 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3154
3155 if (scaler_id >= 0) {
3156 uint32_t ps_ctrl = 0;
3157
3158 WARN_ON(!dst_w || !dst_h);
3159 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3160 crtc_state->scaler_state.scalers[scaler_id].mode;
3161 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3162 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3163 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3164 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3165 I915_WRITE(PLANE_POS(pipe, 0), 0);
3166 } else {
3167 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3168 }
3169
3170 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3171
3172 POSTING_READ(PLANE_SURF(pipe, 0));
3173 }
3174
3175 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3176 static int
3177 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3178 int x, int y, enum mode_set_atomic state)
3179 {
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182
3183 if (dev_priv->fbc.disable_fbc)
3184 dev_priv->fbc.disable_fbc(dev_priv);
3185
3186 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3187
3188 return 0;
3189 }
3190
3191 static void intel_complete_page_flips(struct drm_device *dev)
3192 {
3193 struct drm_crtc *crtc;
3194
3195 for_each_crtc(dev, crtc) {
3196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3197 enum plane plane = intel_crtc->plane;
3198
3199 intel_prepare_page_flip(dev, plane);
3200 intel_finish_page_flip_plane(dev, plane);
3201 }
3202 }
3203
3204 static void intel_update_primary_planes(struct drm_device *dev)
3205 {
3206 struct drm_crtc *crtc;
3207
3208 for_each_crtc(dev, crtc) {
3209 struct intel_plane *plane = to_intel_plane(crtc->primary);
3210 struct intel_plane_state *plane_state;
3211
3212 drm_modeset_lock_crtc(crtc, &plane->base);
3213
3214 plane_state = to_intel_plane_state(plane->base.state);
3215
3216 if (plane_state->base.fb)
3217 plane->commit_plane(&plane->base, plane_state);
3218
3219 drm_modeset_unlock_crtc(crtc);
3220 }
3221 }
3222
3223 void intel_prepare_reset(struct drm_device *dev)
3224 {
3225 /* no reset support for gen2 */
3226 if (IS_GEN2(dev))
3227 return;
3228
3229 /* reset doesn't touch the display */
3230 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3231 return;
3232
3233 drm_modeset_lock_all(dev);
3234 /*
3235 * Disabling the crtcs gracefully seems nicer. Also the
3236 * g33 docs say we should at least disable all the planes.
3237 */
3238 intel_display_suspend(dev);
3239 }
3240
3241 void intel_finish_reset(struct drm_device *dev)
3242 {
3243 struct drm_i915_private *dev_priv = to_i915(dev);
3244
3245 /*
3246 * Flips in the rings will be nuked by the reset,
3247 * so complete all pending flips so that user space
3248 * will get its events and not get stuck.
3249 */
3250 intel_complete_page_flips(dev);
3251
3252 /* no reset support for gen2 */
3253 if (IS_GEN2(dev))
3254 return;
3255
3256 /* reset doesn't touch the display */
3257 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3258 /*
3259 * Flips in the rings have been nuked by the reset,
3260 * so update the base address of all primary
3261 * planes to the the last fb to make sure we're
3262 * showing the correct fb after a reset.
3263 *
3264 * FIXME: Atomic will make this obsolete since we won't schedule
3265 * CS-based flips (which might get lost in gpu resets) any more.
3266 */
3267 intel_update_primary_planes(dev);
3268 return;
3269 }
3270
3271 /*
3272 * The display has been reset as well,
3273 * so need a full re-initialization.
3274 */
3275 intel_runtime_pm_disable_interrupts(dev_priv);
3276 intel_runtime_pm_enable_interrupts(dev_priv);
3277
3278 intel_modeset_init_hw(dev);
3279
3280 spin_lock_irq(&dev_priv->irq_lock);
3281 if (dev_priv->display.hpd_irq_setup)
3282 dev_priv->display.hpd_irq_setup(dev);
3283 spin_unlock_irq(&dev_priv->irq_lock);
3284
3285 intel_display_resume(dev);
3286
3287 intel_hpd_init(dev_priv);
3288
3289 drm_modeset_unlock_all(dev);
3290 }
3291
3292 static void
3293 intel_finish_fb(struct drm_framebuffer *old_fb)
3294 {
3295 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3296 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3297 bool was_interruptible = dev_priv->mm.interruptible;
3298 int ret;
3299
3300 /* Big Hammer, we also need to ensure that any pending
3301 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3302 * current scanout is retired before unpinning the old
3303 * framebuffer. Note that we rely on userspace rendering
3304 * into the buffer attached to the pipe they are waiting
3305 * on. If not, userspace generates a GPU hang with IPEHR
3306 * point to the MI_WAIT_FOR_EVENT.
3307 *
3308 * This should only fail upon a hung GPU, in which case we
3309 * can safely continue.
3310 */
3311 dev_priv->mm.interruptible = false;
3312 ret = i915_gem_object_wait_rendering(obj, true);
3313 dev_priv->mm.interruptible = was_interruptible;
3314
3315 WARN_ON(ret);
3316 }
3317
3318 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3319 {
3320 struct drm_device *dev = crtc->dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 bool pending;
3324
3325 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3326 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3327 return false;
3328
3329 spin_lock_irq(&dev->event_lock);
3330 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3331 spin_unlock_irq(&dev->event_lock);
3332
3333 return pending;
3334 }
3335
3336 static void intel_update_pipe_config(struct intel_crtc *crtc,
3337 struct intel_crtc_state *old_crtc_state)
3338 {
3339 struct drm_device *dev = crtc->base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341 struct intel_crtc_state *pipe_config =
3342 to_intel_crtc_state(crtc->base.state);
3343
3344 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3345 crtc->base.mode = crtc->base.state->mode;
3346
3347 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3348 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3349 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3350
3351 if (HAS_DDI(dev))
3352 intel_set_pipe_csc(&crtc->base);
3353
3354 /*
3355 * Update pipe size and adjust fitter if needed: the reason for this is
3356 * that in compute_mode_changes we check the native mode (not the pfit
3357 * mode) to see if we can flip rather than do a full mode set. In the
3358 * fastboot case, we'll flip, but if we don't update the pipesrc and
3359 * pfit state, we'll end up with a big fb scanned out into the wrong
3360 * sized surface.
3361 */
3362
3363 I915_WRITE(PIPESRC(crtc->pipe),
3364 ((pipe_config->pipe_src_w - 1) << 16) |
3365 (pipe_config->pipe_src_h - 1));
3366
3367 /* on skylake this is done by detaching scalers */
3368 if (INTEL_INFO(dev)->gen >= 9) {
3369 skl_detach_scalers(crtc);
3370
3371 if (pipe_config->pch_pfit.enabled)
3372 skylake_pfit_enable(crtc);
3373 } else if (HAS_PCH_SPLIT(dev)) {
3374 if (pipe_config->pch_pfit.enabled)
3375 ironlake_pfit_enable(crtc);
3376 else if (old_crtc_state->pch_pfit.enabled)
3377 ironlake_pfit_disable(crtc, true);
3378 }
3379 }
3380
3381 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3382 {
3383 struct drm_device *dev = crtc->dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386 int pipe = intel_crtc->pipe;
3387 u32 reg, temp;
3388
3389 /* enable normal train */
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 if (IS_IVYBRIDGE(dev)) {
3393 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3394 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3395 } else {
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3398 }
3399 I915_WRITE(reg, temp);
3400
3401 reg = FDI_RX_CTL(pipe);
3402 temp = I915_READ(reg);
3403 if (HAS_PCH_CPT(dev)) {
3404 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3405 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3406 } else {
3407 temp &= ~FDI_LINK_TRAIN_NONE;
3408 temp |= FDI_LINK_TRAIN_NONE;
3409 }
3410 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3411
3412 /* wait one idle pattern time */
3413 POSTING_READ(reg);
3414 udelay(1000);
3415
3416 /* IVB wants error correction enabled */
3417 if (IS_IVYBRIDGE(dev))
3418 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3419 FDI_FE_ERRC_ENABLE);
3420 }
3421
3422 /* The FDI link training functions for ILK/Ibexpeak. */
3423 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3424 {
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3428 int pipe = intel_crtc->pipe;
3429 u32 reg, temp, tries;
3430
3431 /* FDI needs bits from pipe first */
3432 assert_pipe_enabled(dev_priv, pipe);
3433
3434 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3435 for train result */
3436 reg = FDI_RX_IMR(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_RX_SYMBOL_LOCK;
3439 temp &= ~FDI_RX_BIT_LOCK;
3440 I915_WRITE(reg, temp);
3441 I915_READ(reg);
3442 udelay(150);
3443
3444 /* enable CPU FDI TX and PCH FDI RX */
3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3448 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_1;
3451 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3452
3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_1;
3457 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3458
3459 POSTING_READ(reg);
3460 udelay(150);
3461
3462 /* Ironlake workaround, enable clock pointer after FDI enable*/
3463 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3464 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3465 FDI_RX_PHASE_SYNC_POINTER_EN);
3466
3467 reg = FDI_RX_IIR(pipe);
3468 for (tries = 0; tries < 5; tries++) {
3469 temp = I915_READ(reg);
3470 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3471
3472 if ((temp & FDI_RX_BIT_LOCK)) {
3473 DRM_DEBUG_KMS("FDI train 1 done.\n");
3474 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3475 break;
3476 }
3477 }
3478 if (tries == 5)
3479 DRM_ERROR("FDI train 1 fail!\n");
3480
3481 /* Train 2 */
3482 reg = FDI_TX_CTL(pipe);
3483 temp = I915_READ(reg);
3484 temp &= ~FDI_LINK_TRAIN_NONE;
3485 temp |= FDI_LINK_TRAIN_PATTERN_2;
3486 I915_WRITE(reg, temp);
3487
3488 reg = FDI_RX_CTL(pipe);
3489 temp = I915_READ(reg);
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_2;
3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
3495 udelay(150);
3496
3497 reg = FDI_RX_IIR(pipe);
3498 for (tries = 0; tries < 5; tries++) {
3499 temp = I915_READ(reg);
3500 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3501
3502 if (temp & FDI_RX_SYMBOL_LOCK) {
3503 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3504 DRM_DEBUG_KMS("FDI train 2 done.\n");
3505 break;
3506 }
3507 }
3508 if (tries == 5)
3509 DRM_ERROR("FDI train 2 fail!\n");
3510
3511 DRM_DEBUG_KMS("FDI train done\n");
3512
3513 }
3514
3515 static const int snb_b_fdi_train_param[] = {
3516 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3517 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3518 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3519 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3520 };
3521
3522 /* The FDI link training functions for SNB/Cougarpoint. */
3523 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3524 {
3525 struct drm_device *dev = crtc->dev;
3526 struct drm_i915_private *dev_priv = dev->dev_private;
3527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3528 int pipe = intel_crtc->pipe;
3529 u32 reg, temp, i, retry;
3530
3531 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3532 for train result */
3533 reg = FDI_RX_IMR(pipe);
3534 temp = I915_READ(reg);
3535 temp &= ~FDI_RX_SYMBOL_LOCK;
3536 temp &= ~FDI_RX_BIT_LOCK;
3537 I915_WRITE(reg, temp);
3538
3539 POSTING_READ(reg);
3540 udelay(150);
3541
3542 /* enable CPU FDI TX and PCH FDI RX */
3543 reg = FDI_TX_CTL(pipe);
3544 temp = I915_READ(reg);
3545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3547 temp &= ~FDI_LINK_TRAIN_NONE;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3550 /* SNB-B */
3551 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3553
3554 I915_WRITE(FDI_RX_MISC(pipe),
3555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3556
3557 reg = FDI_RX_CTL(pipe);
3558 temp = I915_READ(reg);
3559 if (HAS_PCH_CPT(dev)) {
3560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3562 } else {
3563 temp &= ~FDI_LINK_TRAIN_NONE;
3564 temp |= FDI_LINK_TRAIN_PATTERN_1;
3565 }
3566 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3567
3568 POSTING_READ(reg);
3569 udelay(150);
3570
3571 for (i = 0; i < 4; i++) {
3572 reg = FDI_TX_CTL(pipe);
3573 temp = I915_READ(reg);
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 temp |= snb_b_fdi_train_param[i];
3576 I915_WRITE(reg, temp);
3577
3578 POSTING_READ(reg);
3579 udelay(500);
3580
3581 for (retry = 0; retry < 5; retry++) {
3582 reg = FDI_RX_IIR(pipe);
3583 temp = I915_READ(reg);
3584 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3585 if (temp & FDI_RX_BIT_LOCK) {
3586 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3587 DRM_DEBUG_KMS("FDI train 1 done.\n");
3588 break;
3589 }
3590 udelay(50);
3591 }
3592 if (retry < 5)
3593 break;
3594 }
3595 if (i == 4)
3596 DRM_ERROR("FDI train 1 fail!\n");
3597
3598 /* Train 2 */
3599 reg = FDI_TX_CTL(pipe);
3600 temp = I915_READ(reg);
3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_PATTERN_2;
3603 if (IS_GEN6(dev)) {
3604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3605 /* SNB-B */
3606 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3607 }
3608 I915_WRITE(reg, temp);
3609
3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
3612 if (HAS_PCH_CPT(dev)) {
3613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3614 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3615 } else {
3616 temp &= ~FDI_LINK_TRAIN_NONE;
3617 temp |= FDI_LINK_TRAIN_PATTERN_2;
3618 }
3619 I915_WRITE(reg, temp);
3620
3621 POSTING_READ(reg);
3622 udelay(150);
3623
3624 for (i = 0; i < 4; i++) {
3625 reg = FDI_TX_CTL(pipe);
3626 temp = I915_READ(reg);
3627 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3628 temp |= snb_b_fdi_train_param[i];
3629 I915_WRITE(reg, temp);
3630
3631 POSTING_READ(reg);
3632 udelay(500);
3633
3634 for (retry = 0; retry < 5; retry++) {
3635 reg = FDI_RX_IIR(pipe);
3636 temp = I915_READ(reg);
3637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3638 if (temp & FDI_RX_SYMBOL_LOCK) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done.\n");
3641 break;
3642 }
3643 udelay(50);
3644 }
3645 if (retry < 5)
3646 break;
3647 }
3648 if (i == 4)
3649 DRM_ERROR("FDI train 2 fail!\n");
3650
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 /* Manual link training for Ivy Bridge A0 parts */
3655 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3656 {
3657 struct drm_device *dev = crtc->dev;
3658 struct drm_i915_private *dev_priv = dev->dev_private;
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 int pipe = intel_crtc->pipe;
3661 u32 reg, temp, i, j;
3662
3663 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3664 for train result */
3665 reg = FDI_RX_IMR(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_RX_SYMBOL_LOCK;
3668 temp &= ~FDI_RX_BIT_LOCK;
3669 I915_WRITE(reg, temp);
3670
3671 POSTING_READ(reg);
3672 udelay(150);
3673
3674 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3675 I915_READ(FDI_RX_IIR(pipe)));
3676
3677 /* Try each vswing and preemphasis setting twice before moving on */
3678 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3679 /* disable first in case we need to retry */
3680 reg = FDI_TX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3683 temp &= ~FDI_TX_ENABLE;
3684 I915_WRITE(reg, temp);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 temp &= ~FDI_LINK_TRAIN_AUTO;
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp &= ~FDI_RX_ENABLE;
3691 I915_WRITE(reg, temp);
3692
3693 /* enable CPU FDI TX and PCH FDI RX */
3694 reg = FDI_TX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3698 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3699 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3700 temp |= snb_b_fdi_train_param[j/2];
3701 temp |= FDI_COMPOSITE_SYNC;
3702 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3703
3704 I915_WRITE(FDI_RX_MISC(pipe),
3705 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3710 temp |= FDI_COMPOSITE_SYNC;
3711 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(1); /* should be 0.5us */
3715
3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3720
3721 if (temp & FDI_RX_BIT_LOCK ||
3722 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3724 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3725 i);
3726 break;
3727 }
3728 udelay(1); /* should be 0.5us */
3729 }
3730 if (i == 4) {
3731 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3732 continue;
3733 }
3734
3735 /* Train 2 */
3736 reg = FDI_TX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3739 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3740 I915_WRITE(reg, temp);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3745 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3746 I915_WRITE(reg, temp);
3747
3748 POSTING_READ(reg);
3749 udelay(2); /* should be 1.5us */
3750
3751 for (i = 0; i < 4; i++) {
3752 reg = FDI_RX_IIR(pipe);
3753 temp = I915_READ(reg);
3754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3755
3756 if (temp & FDI_RX_SYMBOL_LOCK ||
3757 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3758 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3759 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3760 i);
3761 goto train_done;
3762 }
3763 udelay(2); /* should be 1.5us */
3764 }
3765 if (i == 4)
3766 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3767 }
3768
3769 train_done:
3770 DRM_DEBUG_KMS("FDI train done.\n");
3771 }
3772
3773 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3774 {
3775 struct drm_device *dev = intel_crtc->base.dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe = intel_crtc->pipe;
3778 u32 reg, temp;
3779
3780
3781 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3785 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3787 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(200);
3791
3792 /* Switch from Rawclk to PCDclk */
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp | FDI_PCDCLK);
3795
3796 POSTING_READ(reg);
3797 udelay(200);
3798
3799 /* Enable CPU FDI TX PLL, always on for Ironlake */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3803 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3804
3805 POSTING_READ(reg);
3806 udelay(100);
3807 }
3808 }
3809
3810 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3811 {
3812 struct drm_device *dev = intel_crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 int pipe = intel_crtc->pipe;
3815 u32 reg, temp;
3816
3817 /* Switch from PCDclk to Rawclk */
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3821
3822 /* Disable CPU FDI TX PLL */
3823 reg = FDI_TX_CTL(pipe);
3824 temp = I915_READ(reg);
3825 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 reg = FDI_RX_CTL(pipe);
3831 temp = I915_READ(reg);
3832 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3833
3834 /* Wait for the clocks to turn off. */
3835 POSTING_READ(reg);
3836 udelay(100);
3837 }
3838
3839 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3840 {
3841 struct drm_device *dev = crtc->dev;
3842 struct drm_i915_private *dev_priv = dev->dev_private;
3843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3844 int pipe = intel_crtc->pipe;
3845 u32 reg, temp;
3846
3847 /* disable CPU FDI tx and PCH FDI rx */
3848 reg = FDI_TX_CTL(pipe);
3849 temp = I915_READ(reg);
3850 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3851 POSTING_READ(reg);
3852
3853 reg = FDI_RX_CTL(pipe);
3854 temp = I915_READ(reg);
3855 temp &= ~(0x7 << 16);
3856 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3857 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3858
3859 POSTING_READ(reg);
3860 udelay(100);
3861
3862 /* Ironlake workaround, disable clock pointer after downing FDI */
3863 if (HAS_PCH_IBX(dev))
3864 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3865
3866 /* still set train pattern 1 */
3867 reg = FDI_TX_CTL(pipe);
3868 temp = I915_READ(reg);
3869 temp &= ~FDI_LINK_TRAIN_NONE;
3870 temp |= FDI_LINK_TRAIN_PATTERN_1;
3871 I915_WRITE(reg, temp);
3872
3873 reg = FDI_RX_CTL(pipe);
3874 temp = I915_READ(reg);
3875 if (HAS_PCH_CPT(dev)) {
3876 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3877 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3878 } else {
3879 temp &= ~FDI_LINK_TRAIN_NONE;
3880 temp |= FDI_LINK_TRAIN_PATTERN_1;
3881 }
3882 /* BPC in FDI rx is consistent with that in PIPECONF */
3883 temp &= ~(0x07 << 16);
3884 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3885 I915_WRITE(reg, temp);
3886
3887 POSTING_READ(reg);
3888 udelay(100);
3889 }
3890
3891 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3892 {
3893 struct intel_crtc *crtc;
3894
3895 /* Note that we don't need to be called with mode_config.lock here
3896 * as our list of CRTC objects is static for the lifetime of the
3897 * device and so cannot disappear as we iterate. Similarly, we can
3898 * happily treat the predicates as racy, atomic checks as userspace
3899 * cannot claim and pin a new fb without at least acquring the
3900 * struct_mutex and so serialising with us.
3901 */
3902 for_each_intel_crtc(dev, crtc) {
3903 if (atomic_read(&crtc->unpin_work_count) == 0)
3904 continue;
3905
3906 if (crtc->unpin_work)
3907 intel_wait_for_vblank(dev, crtc->pipe);
3908
3909 return true;
3910 }
3911
3912 return false;
3913 }
3914
3915 static void page_flip_completed(struct intel_crtc *intel_crtc)
3916 {
3917 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3918 struct intel_unpin_work *work = intel_crtc->unpin_work;
3919
3920 /* ensure that the unpin work is consistent wrt ->pending. */
3921 smp_rmb();
3922 intel_crtc->unpin_work = NULL;
3923
3924 if (work->event)
3925 drm_send_vblank_event(intel_crtc->base.dev,
3926 intel_crtc->pipe,
3927 work->event);
3928
3929 drm_crtc_vblank_put(&intel_crtc->base);
3930
3931 wake_up_all(&dev_priv->pending_flip_queue);
3932 queue_work(dev_priv->wq, &work->work);
3933
3934 trace_i915_flip_complete(intel_crtc->plane,
3935 work->pending_flip_obj);
3936 }
3937
3938 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3939 {
3940 struct drm_device *dev = crtc->dev;
3941 struct drm_i915_private *dev_priv = dev->dev_private;
3942
3943 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3944 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3945 !intel_crtc_has_pending_flip(crtc),
3946 60*HZ) == 0)) {
3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3948
3949 spin_lock_irq(&dev->event_lock);
3950 if (intel_crtc->unpin_work) {
3951 WARN_ONCE(1, "Removing stuck page flip\n");
3952 page_flip_completed(intel_crtc);
3953 }
3954 spin_unlock_irq(&dev->event_lock);
3955 }
3956
3957 if (crtc->primary->fb) {
3958 mutex_lock(&dev->struct_mutex);
3959 intel_finish_fb(crtc->primary->fb);
3960 mutex_unlock(&dev->struct_mutex);
3961 }
3962 }
3963
3964 /* Program iCLKIP clock to the desired frequency */
3965 static void lpt_program_iclkip(struct drm_crtc *crtc)
3966 {
3967 struct drm_device *dev = crtc->dev;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3971 u32 temp;
3972
3973 mutex_lock(&dev_priv->sb_lock);
3974
3975 /* It is necessary to ungate the pixclk gate prior to programming
3976 * the divisors, and gate it back when it is done.
3977 */
3978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3979
3980 /* Disable SSCCTL */
3981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3983 SBI_SSCCTL_DISABLE,
3984 SBI_ICLK);
3985
3986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3987 if (clock == 20000) {
3988 auxdiv = 1;
3989 divsel = 0x41;
3990 phaseinc = 0x20;
3991 } else {
3992 /* The iCLK virtual clock root frequency is in MHz,
3993 * but the adjusted_mode->crtc_clock in in KHz. To get the
3994 * divisors, it is necessary to divide one by another, so we
3995 * convert the virtual clock precision to KHz here for higher
3996 * precision.
3997 */
3998 u32 iclk_virtual_root_freq = 172800 * 1000;
3999 u32 iclk_pi_range = 64;
4000 u32 desired_divisor, msb_divisor_value, pi_value;
4001
4002 desired_divisor = (iclk_virtual_root_freq / clock);
4003 msb_divisor_value = desired_divisor / iclk_pi_range;
4004 pi_value = desired_divisor % iclk_pi_range;
4005
4006 auxdiv = 0;
4007 divsel = msb_divisor_value - 2;
4008 phaseinc = pi_value;
4009 }
4010
4011 /* This should not happen with any sane values */
4012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4016
4017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4018 clock,
4019 auxdiv,
4020 divsel,
4021 phasedir,
4022 phaseinc);
4023
4024 /* Program SSCDIVINTPHASE6 */
4025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4033
4034 /* Program SSCAUXDIV */
4035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4039
4040 /* Enable modulator and associated divider */
4041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4042 temp &= ~SBI_SSCCTL_DISABLE;
4043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4044
4045 /* Wait for initialization time */
4046 udelay(24);
4047
4048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4049
4050 mutex_unlock(&dev_priv->sb_lock);
4051 }
4052
4053 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4054 enum pipe pch_transcoder)
4055 {
4056 struct drm_device *dev = crtc->base.dev;
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4059
4060 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4061 I915_READ(HTOTAL(cpu_transcoder)));
4062 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4063 I915_READ(HBLANK(cpu_transcoder)));
4064 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4065 I915_READ(HSYNC(cpu_transcoder)));
4066
4067 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4068 I915_READ(VTOTAL(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4070 I915_READ(VBLANK(cpu_transcoder)));
4071 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4072 I915_READ(VSYNC(cpu_transcoder)));
4073 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4074 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4075 }
4076
4077 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4078 {
4079 struct drm_i915_private *dev_priv = dev->dev_private;
4080 uint32_t temp;
4081
4082 temp = I915_READ(SOUTH_CHICKEN1);
4083 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4084 return;
4085
4086 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4087 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4088
4089 temp &= ~FDI_BC_BIFURCATION_SELECT;
4090 if (enable)
4091 temp |= FDI_BC_BIFURCATION_SELECT;
4092
4093 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4094 I915_WRITE(SOUTH_CHICKEN1, temp);
4095 POSTING_READ(SOUTH_CHICKEN1);
4096 }
4097
4098 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4099 {
4100 struct drm_device *dev = intel_crtc->base.dev;
4101
4102 switch (intel_crtc->pipe) {
4103 case PIPE_A:
4104 break;
4105 case PIPE_B:
4106 if (intel_crtc->config->fdi_lanes > 2)
4107 cpt_set_fdi_bc_bifurcation(dev, false);
4108 else
4109 cpt_set_fdi_bc_bifurcation(dev, true);
4110
4111 break;
4112 case PIPE_C:
4113 cpt_set_fdi_bc_bifurcation(dev, true);
4114
4115 break;
4116 default:
4117 BUG();
4118 }
4119 }
4120
4121 /*
4122 * Enable PCH resources required for PCH ports:
4123 * - PCH PLLs
4124 * - FDI training & RX/TX
4125 * - update transcoder timings
4126 * - DP transcoding bits
4127 * - transcoder
4128 */
4129 static void ironlake_pch_enable(struct drm_crtc *crtc)
4130 {
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4134 int pipe = intel_crtc->pipe;
4135 u32 reg, temp;
4136
4137 assert_pch_transcoder_disabled(dev_priv, pipe);
4138
4139 if (IS_IVYBRIDGE(dev))
4140 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4141
4142 /* Write the TU size bits before fdi link training, so that error
4143 * detection works. */
4144 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4145 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4146
4147 /* For PCH output, training FDI link */
4148 dev_priv->display.fdi_link_train(crtc);
4149
4150 /* We need to program the right clock selection before writing the pixel
4151 * mutliplier into the DPLL. */
4152 if (HAS_PCH_CPT(dev)) {
4153 u32 sel;
4154
4155 temp = I915_READ(PCH_DPLL_SEL);
4156 temp |= TRANS_DPLL_ENABLE(pipe);
4157 sel = TRANS_DPLLB_SEL(pipe);
4158 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4159 temp |= sel;
4160 else
4161 temp &= ~sel;
4162 I915_WRITE(PCH_DPLL_SEL, temp);
4163 }
4164
4165 /* XXX: pch pll's can be enabled any time before we enable the PCH
4166 * transcoder, and we actually should do this to not upset any PCH
4167 * transcoder that already use the clock when we share it.
4168 *
4169 * Note that enable_shared_dpll tries to do the right thing, but
4170 * get_shared_dpll unconditionally resets the pll - we need that to have
4171 * the right LVDS enable sequence. */
4172 intel_enable_shared_dpll(intel_crtc);
4173
4174 /* set transcoder timing, panel must allow it */
4175 assert_panel_unlocked(dev_priv, pipe);
4176 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4177
4178 intel_fdi_normal_train(crtc);
4179
4180 /* For PCH DP, enable TRANS_DP_CTL */
4181 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4182 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4183 reg = TRANS_DP_CTL(pipe);
4184 temp = I915_READ(reg);
4185 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4186 TRANS_DP_SYNC_MASK |
4187 TRANS_DP_BPC_MASK);
4188 temp |= TRANS_DP_OUTPUT_ENABLE;
4189 temp |= bpc << 9; /* same format but at 11:9 */
4190
4191 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4192 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4193 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4194 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4195
4196 switch (intel_trans_dp_port_sel(crtc)) {
4197 case PCH_DP_B:
4198 temp |= TRANS_DP_PORT_SEL_B;
4199 break;
4200 case PCH_DP_C:
4201 temp |= TRANS_DP_PORT_SEL_C;
4202 break;
4203 case PCH_DP_D:
4204 temp |= TRANS_DP_PORT_SEL_D;
4205 break;
4206 default:
4207 BUG();
4208 }
4209
4210 I915_WRITE(reg, temp);
4211 }
4212
4213 ironlake_enable_pch_transcoder(dev_priv, pipe);
4214 }
4215
4216 static void lpt_pch_enable(struct drm_crtc *crtc)
4217 {
4218 struct drm_device *dev = crtc->dev;
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4221 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4222
4223 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4224
4225 lpt_program_iclkip(crtc);
4226
4227 /* Set transcoder timing. */
4228 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4229
4230 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4231 }
4232
4233 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4234 struct intel_crtc_state *crtc_state)
4235 {
4236 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4237 struct intel_shared_dpll *pll;
4238 struct intel_shared_dpll_config *shared_dpll;
4239 enum intel_dpll_id i;
4240
4241 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4242
4243 if (HAS_PCH_IBX(dev_priv->dev)) {
4244 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4245 i = (enum intel_dpll_id) crtc->pipe;
4246 pll = &dev_priv->shared_dplls[i];
4247
4248 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4249 crtc->base.base.id, pll->name);
4250
4251 WARN_ON(shared_dpll[i].crtc_mask);
4252
4253 goto found;
4254 }
4255
4256 if (IS_BROXTON(dev_priv->dev)) {
4257 /* PLL is attached to port in bxt */
4258 struct intel_encoder *encoder;
4259 struct intel_digital_port *intel_dig_port;
4260
4261 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4262 if (WARN_ON(!encoder))
4263 return NULL;
4264
4265 intel_dig_port = enc_to_dig_port(&encoder->base);
4266 /* 1:1 mapping between ports and PLLs */
4267 i = (enum intel_dpll_id)intel_dig_port->port;
4268 pll = &dev_priv->shared_dplls[i];
4269 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4270 crtc->base.base.id, pll->name);
4271 WARN_ON(shared_dpll[i].crtc_mask);
4272
4273 goto found;
4274 }
4275
4276 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4277 pll = &dev_priv->shared_dplls[i];
4278
4279 /* Only want to check enabled timings first */
4280 if (shared_dpll[i].crtc_mask == 0)
4281 continue;
4282
4283 if (memcmp(&crtc_state->dpll_hw_state,
4284 &shared_dpll[i].hw_state,
4285 sizeof(crtc_state->dpll_hw_state)) == 0) {
4286 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4287 crtc->base.base.id, pll->name,
4288 shared_dpll[i].crtc_mask,
4289 pll->active);
4290 goto found;
4291 }
4292 }
4293
4294 /* Ok no matching timings, maybe there's a free one? */
4295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296 pll = &dev_priv->shared_dplls[i];
4297 if (shared_dpll[i].crtc_mask == 0) {
4298 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4299 crtc->base.base.id, pll->name);
4300 goto found;
4301 }
4302 }
4303
4304 return NULL;
4305
4306 found:
4307 if (shared_dpll[i].crtc_mask == 0)
4308 shared_dpll[i].hw_state =
4309 crtc_state->dpll_hw_state;
4310
4311 crtc_state->shared_dpll = i;
4312 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4313 pipe_name(crtc->pipe));
4314
4315 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4316
4317 return pll;
4318 }
4319
4320 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4321 {
4322 struct drm_i915_private *dev_priv = to_i915(state->dev);
4323 struct intel_shared_dpll_config *shared_dpll;
4324 struct intel_shared_dpll *pll;
4325 enum intel_dpll_id i;
4326
4327 if (!to_intel_atomic_state(state)->dpll_set)
4328 return;
4329
4330 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4331 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4332 pll = &dev_priv->shared_dplls[i];
4333 pll->config = shared_dpll[i];
4334 }
4335 }
4336
4337 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4338 {
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 int dslreg = PIPEDSL(pipe);
4341 u32 temp;
4342
4343 temp = I915_READ(dslreg);
4344 udelay(500);
4345 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4346 if (wait_for(I915_READ(dslreg) != temp, 5))
4347 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4348 }
4349 }
4350
4351 static int
4352 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4353 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4354 int src_w, int src_h, int dst_w, int dst_h)
4355 {
4356 struct intel_crtc_scaler_state *scaler_state =
4357 &crtc_state->scaler_state;
4358 struct intel_crtc *intel_crtc =
4359 to_intel_crtc(crtc_state->base.crtc);
4360 int need_scaling;
4361
4362 need_scaling = intel_rotation_90_or_270(rotation) ?
4363 (src_h != dst_w || src_w != dst_h):
4364 (src_w != dst_w || src_h != dst_h);
4365
4366 /*
4367 * if plane is being disabled or scaler is no more required or force detach
4368 * - free scaler binded to this plane/crtc
4369 * - in order to do this, update crtc->scaler_usage
4370 *
4371 * Here scaler state in crtc_state is set free so that
4372 * scaler can be assigned to other user. Actual register
4373 * update to free the scaler is done in plane/panel-fit programming.
4374 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4375 */
4376 if (force_detach || !need_scaling) {
4377 if (*scaler_id >= 0) {
4378 scaler_state->scaler_users &= ~(1 << scaler_user);
4379 scaler_state->scalers[*scaler_id].in_use = 0;
4380
4381 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4382 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4383 intel_crtc->pipe, scaler_user, *scaler_id,
4384 scaler_state->scaler_users);
4385 *scaler_id = -1;
4386 }
4387 return 0;
4388 }
4389
4390 /* range checks */
4391 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4392 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4393
4394 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4395 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4396 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4397 "size is out of scaler range\n",
4398 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4399 return -EINVAL;
4400 }
4401
4402 /* mark this plane as a scaler user in crtc_state */
4403 scaler_state->scaler_users |= (1 << scaler_user);
4404 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4405 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4406 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4407 scaler_state->scaler_users);
4408
4409 return 0;
4410 }
4411
4412 /**
4413 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4414 *
4415 * @state: crtc's scaler state
4416 *
4417 * Return
4418 * 0 - scaler_usage updated successfully
4419 * error - requested scaling cannot be supported or other error condition
4420 */
4421 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4422 {
4423 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4424 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4425
4426 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4427 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4428
4429 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4430 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4431 state->pipe_src_w, state->pipe_src_h,
4432 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4433 }
4434
4435 /**
4436 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4437 *
4438 * @state: crtc's scaler state
4439 * @plane_state: atomic plane state to update
4440 *
4441 * Return
4442 * 0 - scaler_usage updated successfully
4443 * error - requested scaling cannot be supported or other error condition
4444 */
4445 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4446 struct intel_plane_state *plane_state)
4447 {
4448
4449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4450 struct intel_plane *intel_plane =
4451 to_intel_plane(plane_state->base.plane);
4452 struct drm_framebuffer *fb = plane_state->base.fb;
4453 int ret;
4454
4455 bool force_detach = !fb || !plane_state->visible;
4456
4457 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4458 intel_plane->base.base.id, intel_crtc->pipe,
4459 drm_plane_index(&intel_plane->base));
4460
4461 ret = skl_update_scaler(crtc_state, force_detach,
4462 drm_plane_index(&intel_plane->base),
4463 &plane_state->scaler_id,
4464 plane_state->base.rotation,
4465 drm_rect_width(&plane_state->src) >> 16,
4466 drm_rect_height(&plane_state->src) >> 16,
4467 drm_rect_width(&plane_state->dst),
4468 drm_rect_height(&plane_state->dst));
4469
4470 if (ret || plane_state->scaler_id < 0)
4471 return ret;
4472
4473 /* check colorkey */
4474 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4475 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4476 intel_plane->base.base.id);
4477 return -EINVAL;
4478 }
4479
4480 /* Check src format */
4481 switch (fb->pixel_format) {
4482 case DRM_FORMAT_RGB565:
4483 case DRM_FORMAT_XBGR8888:
4484 case DRM_FORMAT_XRGB8888:
4485 case DRM_FORMAT_ABGR8888:
4486 case DRM_FORMAT_ARGB8888:
4487 case DRM_FORMAT_XRGB2101010:
4488 case DRM_FORMAT_XBGR2101010:
4489 case DRM_FORMAT_YUYV:
4490 case DRM_FORMAT_YVYU:
4491 case DRM_FORMAT_UYVY:
4492 case DRM_FORMAT_VYUY:
4493 break;
4494 default:
4495 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4496 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4497 return -EINVAL;
4498 }
4499
4500 return 0;
4501 }
4502
4503 static void skylake_scaler_disable(struct intel_crtc *crtc)
4504 {
4505 int i;
4506
4507 for (i = 0; i < crtc->num_scalers; i++)
4508 skl_detach_scaler(crtc, i);
4509 }
4510
4511 static void skylake_pfit_enable(struct intel_crtc *crtc)
4512 {
4513 struct drm_device *dev = crtc->base.dev;
4514 struct drm_i915_private *dev_priv = dev->dev_private;
4515 int pipe = crtc->pipe;
4516 struct intel_crtc_scaler_state *scaler_state =
4517 &crtc->config->scaler_state;
4518
4519 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4520
4521 if (crtc->config->pch_pfit.enabled) {
4522 int id;
4523
4524 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4525 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4526 return;
4527 }
4528
4529 id = scaler_state->scaler_id;
4530 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4531 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4532 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4533 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4534
4535 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4536 }
4537 }
4538
4539 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4540 {
4541 struct drm_device *dev = crtc->base.dev;
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 int pipe = crtc->pipe;
4544
4545 if (crtc->config->pch_pfit.enabled) {
4546 /* Force use of hard-coded filter coefficients
4547 * as some pre-programmed values are broken,
4548 * e.g. x201.
4549 */
4550 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4551 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4552 PF_PIPE_SEL_IVB(pipe));
4553 else
4554 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4555 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4556 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4557 }
4558 }
4559
4560 void hsw_enable_ips(struct intel_crtc *crtc)
4561 {
4562 struct drm_device *dev = crtc->base.dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564
4565 if (!crtc->config->ips_enabled)
4566 return;
4567
4568 /* We can only enable IPS after we enable a plane and wait for a vblank */
4569 intel_wait_for_vblank(dev, crtc->pipe);
4570
4571 assert_plane_enabled(dev_priv, crtc->plane);
4572 if (IS_BROADWELL(dev)) {
4573 mutex_lock(&dev_priv->rps.hw_lock);
4574 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4575 mutex_unlock(&dev_priv->rps.hw_lock);
4576 /* Quoting Art Runyan: "its not safe to expect any particular
4577 * value in IPS_CTL bit 31 after enabling IPS through the
4578 * mailbox." Moreover, the mailbox may return a bogus state,
4579 * so we need to just enable it and continue on.
4580 */
4581 } else {
4582 I915_WRITE(IPS_CTL, IPS_ENABLE);
4583 /* The bit only becomes 1 in the next vblank, so this wait here
4584 * is essentially intel_wait_for_vblank. If we don't have this
4585 * and don't wait for vblanks until the end of crtc_enable, then
4586 * the HW state readout code will complain that the expected
4587 * IPS_CTL value is not the one we read. */
4588 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4589 DRM_ERROR("Timed out waiting for IPS enable\n");
4590 }
4591 }
4592
4593 void hsw_disable_ips(struct intel_crtc *crtc)
4594 {
4595 struct drm_device *dev = crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597
4598 if (!crtc->config->ips_enabled)
4599 return;
4600
4601 assert_plane_enabled(dev_priv, crtc->plane);
4602 if (IS_BROADWELL(dev)) {
4603 mutex_lock(&dev_priv->rps.hw_lock);
4604 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4605 mutex_unlock(&dev_priv->rps.hw_lock);
4606 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4607 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4608 DRM_ERROR("Timed out waiting for IPS disable\n");
4609 } else {
4610 I915_WRITE(IPS_CTL, 0);
4611 POSTING_READ(IPS_CTL);
4612 }
4613
4614 /* We need to wait for a vblank before we can disable the plane. */
4615 intel_wait_for_vblank(dev, crtc->pipe);
4616 }
4617
4618 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4619 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4620 {
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 enum pipe pipe = intel_crtc->pipe;
4625 int i;
4626 bool reenable_ips = false;
4627
4628 /* The clocks have to be on to load the palette. */
4629 if (!crtc->state->active)
4630 return;
4631
4632 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4633 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4634 assert_dsi_pll_enabled(dev_priv);
4635 else
4636 assert_pll_enabled(dev_priv, pipe);
4637 }
4638
4639 /* Workaround : Do not read or write the pipe palette/gamma data while
4640 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4641 */
4642 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4643 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4644 GAMMA_MODE_MODE_SPLIT)) {
4645 hsw_disable_ips(intel_crtc);
4646 reenable_ips = true;
4647 }
4648
4649 for (i = 0; i < 256; i++) {
4650 u32 palreg;
4651
4652 if (HAS_GMCH_DISPLAY(dev))
4653 palreg = PALETTE(pipe, i);
4654 else
4655 palreg = LGC_PALETTE(pipe, i);
4656
4657 I915_WRITE(palreg,
4658 (intel_crtc->lut_r[i] << 16) |
4659 (intel_crtc->lut_g[i] << 8) |
4660 intel_crtc->lut_b[i]);
4661 }
4662
4663 if (reenable_ips)
4664 hsw_enable_ips(intel_crtc);
4665 }
4666
4667 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4668 {
4669 if (intel_crtc->overlay) {
4670 struct drm_device *dev = intel_crtc->base.dev;
4671 struct drm_i915_private *dev_priv = dev->dev_private;
4672
4673 mutex_lock(&dev->struct_mutex);
4674 dev_priv->mm.interruptible = false;
4675 (void) intel_overlay_switch_off(intel_crtc->overlay);
4676 dev_priv->mm.interruptible = true;
4677 mutex_unlock(&dev->struct_mutex);
4678 }
4679
4680 /* Let userspace switch the overlay on again. In most cases userspace
4681 * has to recompute where to put it anyway.
4682 */
4683 }
4684
4685 /**
4686 * intel_post_enable_primary - Perform operations after enabling primary plane
4687 * @crtc: the CRTC whose primary plane was just enabled
4688 *
4689 * Performs potentially sleeping operations that must be done after the primary
4690 * plane is enabled, such as updating FBC and IPS. Note that this may be
4691 * called due to an explicit primary plane update, or due to an implicit
4692 * re-enable that is caused when a sprite plane is updated to no longer
4693 * completely hide the primary plane.
4694 */
4695 static void
4696 intel_post_enable_primary(struct drm_crtc *crtc)
4697 {
4698 struct drm_device *dev = crtc->dev;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4701 int pipe = intel_crtc->pipe;
4702
4703 /*
4704 * BDW signals flip done immediately if the plane
4705 * is disabled, even if the plane enable is already
4706 * armed to occur at the next vblank :(
4707 */
4708 if (IS_BROADWELL(dev))
4709 intel_wait_for_vblank(dev, pipe);
4710
4711 /*
4712 * FIXME IPS should be fine as long as one plane is
4713 * enabled, but in practice it seems to have problems
4714 * when going from primary only to sprite only and vice
4715 * versa.
4716 */
4717 hsw_enable_ips(intel_crtc);
4718
4719 /*
4720 * Gen2 reports pipe underruns whenever all planes are disabled.
4721 * So don't enable underrun reporting before at least some planes
4722 * are enabled.
4723 * FIXME: Need to fix the logic to work when we turn off all planes
4724 * but leave the pipe running.
4725 */
4726 if (IS_GEN2(dev))
4727 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4728
4729 /* Underruns don't raise interrupts, so check manually. */
4730 if (HAS_GMCH_DISPLAY(dev))
4731 i9xx_check_fifo_underruns(dev_priv);
4732 }
4733
4734 /**
4735 * intel_pre_disable_primary - Perform operations before disabling primary plane
4736 * @crtc: the CRTC whose primary plane is to be disabled
4737 *
4738 * Performs potentially sleeping operations that must be done before the
4739 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4740 * be called due to an explicit primary plane update, or due to an implicit
4741 * disable that is caused when a sprite plane completely hides the primary
4742 * plane.
4743 */
4744 static void
4745 intel_pre_disable_primary(struct drm_crtc *crtc)
4746 {
4747 struct drm_device *dev = crtc->dev;
4748 struct drm_i915_private *dev_priv = dev->dev_private;
4749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4750 int pipe = intel_crtc->pipe;
4751
4752 /*
4753 * Gen2 reports pipe underruns whenever all planes are disabled.
4754 * So diasble underrun reporting before all the planes get disabled.
4755 * FIXME: Need to fix the logic to work when we turn off all planes
4756 * but leave the pipe running.
4757 */
4758 if (IS_GEN2(dev))
4759 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4760
4761 /*
4762 * Vblank time updates from the shadow to live plane control register
4763 * are blocked if the memory self-refresh mode is active at that
4764 * moment. So to make sure the plane gets truly disabled, disable
4765 * first the self-refresh mode. The self-refresh enable bit in turn
4766 * will be checked/applied by the HW only at the next frame start
4767 * event which is after the vblank start event, so we need to have a
4768 * wait-for-vblank between disabling the plane and the pipe.
4769 */
4770 if (HAS_GMCH_DISPLAY(dev)) {
4771 intel_set_memory_cxsr(dev_priv, false);
4772 dev_priv->wm.vlv.cxsr = false;
4773 intel_wait_for_vblank(dev, pipe);
4774 }
4775
4776 /*
4777 * FIXME IPS should be fine as long as one plane is
4778 * enabled, but in practice it seems to have problems
4779 * when going from primary only to sprite only and vice
4780 * versa.
4781 */
4782 hsw_disable_ips(intel_crtc);
4783 }
4784
4785 static void intel_post_plane_update(struct intel_crtc *crtc)
4786 {
4787 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4788 struct drm_device *dev = crtc->base.dev;
4789 struct drm_i915_private *dev_priv = dev->dev_private;
4790 struct drm_plane *plane;
4791
4792 if (atomic->wait_vblank)
4793 intel_wait_for_vblank(dev, crtc->pipe);
4794
4795 intel_frontbuffer_flip(dev, atomic->fb_bits);
4796
4797 if (atomic->disable_cxsr)
4798 crtc->wm.cxsr_allowed = true;
4799
4800 if (crtc->atomic.update_wm_post)
4801 intel_update_watermarks(&crtc->base);
4802
4803 if (atomic->update_fbc)
4804 intel_fbc_update(dev_priv);
4805
4806 if (atomic->post_enable_primary)
4807 intel_post_enable_primary(&crtc->base);
4808
4809 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4810 intel_update_sprite_watermarks(plane, &crtc->base,
4811 0, 0, 0, false, false);
4812
4813 memset(atomic, 0, sizeof(*atomic));
4814 }
4815
4816 static void intel_pre_plane_update(struct intel_crtc *crtc)
4817 {
4818 struct drm_device *dev = crtc->base.dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4821 struct drm_plane *p;
4822
4823 /* Track fb's for any planes being disabled */
4824 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4825 struct intel_plane *plane = to_intel_plane(p);
4826
4827 mutex_lock(&dev->struct_mutex);
4828 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4829 plane->frontbuffer_bit);
4830 mutex_unlock(&dev->struct_mutex);
4831 }
4832
4833 if (atomic->wait_for_flips)
4834 intel_crtc_wait_for_pending_flips(&crtc->base);
4835
4836 if (atomic->disable_fbc)
4837 intel_fbc_disable_crtc(crtc);
4838
4839 if (crtc->atomic.disable_ips)
4840 hsw_disable_ips(crtc);
4841
4842 if (atomic->pre_disable_primary)
4843 intel_pre_disable_primary(&crtc->base);
4844
4845 if (atomic->disable_cxsr) {
4846 crtc->wm.cxsr_allowed = false;
4847 intel_set_memory_cxsr(dev_priv, false);
4848 }
4849 }
4850
4851 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4852 {
4853 struct drm_device *dev = crtc->dev;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 struct drm_plane *p;
4856 int pipe = intel_crtc->pipe;
4857
4858 intel_crtc_dpms_overlay_disable(intel_crtc);
4859
4860 drm_for_each_plane_mask(p, dev, plane_mask)
4861 to_intel_plane(p)->disable_plane(p, crtc);
4862
4863 /*
4864 * FIXME: Once we grow proper nuclear flip support out of this we need
4865 * to compute the mask of flip planes precisely. For the time being
4866 * consider this a flip to a NULL plane.
4867 */
4868 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4869 }
4870
4871 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4872 {
4873 struct drm_device *dev = crtc->dev;
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4876 struct intel_encoder *encoder;
4877 int pipe = intel_crtc->pipe;
4878
4879 if (WARN_ON(intel_crtc->active))
4880 return;
4881
4882 if (intel_crtc->config->has_pch_encoder)
4883 intel_prepare_shared_dpll(intel_crtc);
4884
4885 if (intel_crtc->config->has_dp_encoder)
4886 intel_dp_set_m_n(intel_crtc, M1_N1);
4887
4888 intel_set_pipe_timings(intel_crtc);
4889
4890 if (intel_crtc->config->has_pch_encoder) {
4891 intel_cpu_transcoder_set_m_n(intel_crtc,
4892 &intel_crtc->config->fdi_m_n, NULL);
4893 }
4894
4895 ironlake_set_pipeconf(crtc);
4896
4897 intel_crtc->active = true;
4898
4899 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4900 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4901
4902 for_each_encoder_on_crtc(dev, crtc, encoder)
4903 if (encoder->pre_enable)
4904 encoder->pre_enable(encoder);
4905
4906 if (intel_crtc->config->has_pch_encoder) {
4907 /* Note: FDI PLL enabling _must_ be done before we enable the
4908 * cpu pipes, hence this is separate from all the other fdi/pch
4909 * enabling. */
4910 ironlake_fdi_pll_enable(intel_crtc);
4911 } else {
4912 assert_fdi_tx_disabled(dev_priv, pipe);
4913 assert_fdi_rx_disabled(dev_priv, pipe);
4914 }
4915
4916 ironlake_pfit_enable(intel_crtc);
4917
4918 /*
4919 * On ILK+ LUT must be loaded before the pipe is running but with
4920 * clocks enabled
4921 */
4922 intel_crtc_load_lut(crtc);
4923
4924 intel_update_watermarks(crtc);
4925 intel_enable_pipe(intel_crtc);
4926
4927 if (intel_crtc->config->has_pch_encoder)
4928 ironlake_pch_enable(crtc);
4929
4930 assert_vblank_disabled(crtc);
4931 drm_crtc_vblank_on(crtc);
4932
4933 for_each_encoder_on_crtc(dev, crtc, encoder)
4934 encoder->enable(encoder);
4935
4936 if (HAS_PCH_CPT(dev))
4937 cpt_verify_modeset(dev, intel_crtc->pipe);
4938 }
4939
4940 /* IPS only exists on ULT machines and is tied to pipe A. */
4941 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4942 {
4943 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4944 }
4945
4946 static void haswell_crtc_enable(struct drm_crtc *crtc)
4947 {
4948 struct drm_device *dev = crtc->dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4951 struct intel_encoder *encoder;
4952 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4953 struct intel_crtc_state *pipe_config =
4954 to_intel_crtc_state(crtc->state);
4955 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4956
4957 if (WARN_ON(intel_crtc->active))
4958 return;
4959
4960 if (intel_crtc_to_shared_dpll(intel_crtc))
4961 intel_enable_shared_dpll(intel_crtc);
4962
4963 if (intel_crtc->config->has_dp_encoder)
4964 intel_dp_set_m_n(intel_crtc, M1_N1);
4965
4966 intel_set_pipe_timings(intel_crtc);
4967
4968 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4969 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4970 intel_crtc->config->pixel_multiplier - 1);
4971 }
4972
4973 if (intel_crtc->config->has_pch_encoder) {
4974 intel_cpu_transcoder_set_m_n(intel_crtc,
4975 &intel_crtc->config->fdi_m_n, NULL);
4976 }
4977
4978 haswell_set_pipeconf(crtc);
4979
4980 intel_set_pipe_csc(crtc);
4981
4982 intel_crtc->active = true;
4983
4984 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4985 for_each_encoder_on_crtc(dev, crtc, encoder) {
4986 if (encoder->pre_pll_enable)
4987 encoder->pre_pll_enable(encoder);
4988 if (encoder->pre_enable)
4989 encoder->pre_enable(encoder);
4990 }
4991
4992 if (intel_crtc->config->has_pch_encoder) {
4993 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4994 true);
4995 dev_priv->display.fdi_link_train(crtc);
4996 }
4997
4998 if (!is_dsi)
4999 intel_ddi_enable_pipe_clock(intel_crtc);
5000
5001 if (INTEL_INFO(dev)->gen >= 9)
5002 skylake_pfit_enable(intel_crtc);
5003 else
5004 ironlake_pfit_enable(intel_crtc);
5005
5006 /*
5007 * On ILK+ LUT must be loaded before the pipe is running but with
5008 * clocks enabled
5009 */
5010 intel_crtc_load_lut(crtc);
5011
5012 intel_ddi_set_pipe_settings(crtc);
5013 if (!is_dsi)
5014 intel_ddi_enable_transcoder_func(crtc);
5015
5016 intel_update_watermarks(crtc);
5017 intel_enable_pipe(intel_crtc);
5018
5019 if (intel_crtc->config->has_pch_encoder)
5020 lpt_pch_enable(crtc);
5021
5022 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5023 intel_ddi_set_vc_payload_alloc(crtc, true);
5024
5025 assert_vblank_disabled(crtc);
5026 drm_crtc_vblank_on(crtc);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder) {
5029 encoder->enable(encoder);
5030 intel_opregion_notify_encoder(encoder, true);
5031 }
5032
5033 /* If we change the relative order between pipe/planes enabling, we need
5034 * to change the workaround. */
5035 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5036 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5037 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5038 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5039 }
5040 }
5041
5042 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5043 {
5044 struct drm_device *dev = crtc->base.dev;
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5046 int pipe = crtc->pipe;
5047
5048 /* To avoid upsetting the power well on haswell only disable the pfit if
5049 * it's in use. The hw state code will make sure we get this right. */
5050 if (force || crtc->config->pch_pfit.enabled) {
5051 I915_WRITE(PF_CTL(pipe), 0);
5052 I915_WRITE(PF_WIN_POS(pipe), 0);
5053 I915_WRITE(PF_WIN_SZ(pipe), 0);
5054 }
5055 }
5056
5057 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5058 {
5059 struct drm_device *dev = crtc->dev;
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5062 struct intel_encoder *encoder;
5063 int pipe = intel_crtc->pipe;
5064 u32 reg, temp;
5065
5066 for_each_encoder_on_crtc(dev, crtc, encoder)
5067 encoder->disable(encoder);
5068
5069 drm_crtc_vblank_off(crtc);
5070 assert_vblank_disabled(crtc);
5071
5072 if (intel_crtc->config->has_pch_encoder)
5073 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5074
5075 intel_disable_pipe(intel_crtc);
5076
5077 ironlake_pfit_disable(intel_crtc, false);
5078
5079 if (intel_crtc->config->has_pch_encoder)
5080 ironlake_fdi_disable(crtc);
5081
5082 for_each_encoder_on_crtc(dev, crtc, encoder)
5083 if (encoder->post_disable)
5084 encoder->post_disable(encoder);
5085
5086 if (intel_crtc->config->has_pch_encoder) {
5087 ironlake_disable_pch_transcoder(dev_priv, pipe);
5088
5089 if (HAS_PCH_CPT(dev)) {
5090 /* disable TRANS_DP_CTL */
5091 reg = TRANS_DP_CTL(pipe);
5092 temp = I915_READ(reg);
5093 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5094 TRANS_DP_PORT_SEL_MASK);
5095 temp |= TRANS_DP_PORT_SEL_NONE;
5096 I915_WRITE(reg, temp);
5097
5098 /* disable DPLL_SEL */
5099 temp = I915_READ(PCH_DPLL_SEL);
5100 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5101 I915_WRITE(PCH_DPLL_SEL, temp);
5102 }
5103
5104 ironlake_fdi_pll_disable(intel_crtc);
5105 }
5106 }
5107
5108 static void haswell_crtc_disable(struct drm_crtc *crtc)
5109 {
5110 struct drm_device *dev = crtc->dev;
5111 struct drm_i915_private *dev_priv = dev->dev_private;
5112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5113 struct intel_encoder *encoder;
5114 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5115 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5116
5117 for_each_encoder_on_crtc(dev, crtc, encoder) {
5118 intel_opregion_notify_encoder(encoder, false);
5119 encoder->disable(encoder);
5120 }
5121
5122 drm_crtc_vblank_off(crtc);
5123 assert_vblank_disabled(crtc);
5124
5125 if (intel_crtc->config->has_pch_encoder)
5126 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5127 false);
5128 intel_disable_pipe(intel_crtc);
5129
5130 if (intel_crtc->config->dp_encoder_is_mst)
5131 intel_ddi_set_vc_payload_alloc(crtc, false);
5132
5133 if (!is_dsi)
5134 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5135
5136 if (INTEL_INFO(dev)->gen >= 9)
5137 skylake_scaler_disable(intel_crtc);
5138 else
5139 ironlake_pfit_disable(intel_crtc, false);
5140
5141 if (!is_dsi)
5142 intel_ddi_disable_pipe_clock(intel_crtc);
5143
5144 if (intel_crtc->config->has_pch_encoder) {
5145 lpt_disable_pch_transcoder(dev_priv);
5146 intel_ddi_fdi_disable(crtc);
5147 }
5148
5149 for_each_encoder_on_crtc(dev, crtc, encoder)
5150 if (encoder->post_disable)
5151 encoder->post_disable(encoder);
5152 }
5153
5154 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5155 {
5156 struct drm_device *dev = crtc->base.dev;
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct intel_crtc_state *pipe_config = crtc->config;
5159
5160 if (!pipe_config->gmch_pfit.control)
5161 return;
5162
5163 /*
5164 * The panel fitter should only be adjusted whilst the pipe is disabled,
5165 * according to register description and PRM.
5166 */
5167 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5168 assert_pipe_disabled(dev_priv, crtc->pipe);
5169
5170 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5171 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5172
5173 /* Border color in case we don't scale up to the full screen. Black by
5174 * default, change to something else for debugging. */
5175 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5176 }
5177
5178 static enum intel_display_power_domain port_to_power_domain(enum port port)
5179 {
5180 switch (port) {
5181 case PORT_A:
5182 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5183 case PORT_B:
5184 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5185 case PORT_C:
5186 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5187 case PORT_D:
5188 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5189 case PORT_E:
5190 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
5191 default:
5192 WARN_ON_ONCE(1);
5193 return POWER_DOMAIN_PORT_OTHER;
5194 }
5195 }
5196
5197 #define for_each_power_domain(domain, mask) \
5198 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5199 if ((1 << (domain)) & (mask))
5200
5201 enum intel_display_power_domain
5202 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5203 {
5204 struct drm_device *dev = intel_encoder->base.dev;
5205 struct intel_digital_port *intel_dig_port;
5206
5207 switch (intel_encoder->type) {
5208 case INTEL_OUTPUT_UNKNOWN:
5209 /* Only DDI platforms should ever use this output type */
5210 WARN_ON_ONCE(!HAS_DDI(dev));
5211 case INTEL_OUTPUT_DISPLAYPORT:
5212 case INTEL_OUTPUT_HDMI:
5213 case INTEL_OUTPUT_EDP:
5214 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5215 return port_to_power_domain(intel_dig_port->port);
5216 case INTEL_OUTPUT_DP_MST:
5217 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5218 return port_to_power_domain(intel_dig_port->port);
5219 case INTEL_OUTPUT_ANALOG:
5220 return POWER_DOMAIN_PORT_CRT;
5221 case INTEL_OUTPUT_DSI:
5222 return POWER_DOMAIN_PORT_DSI;
5223 default:
5224 return POWER_DOMAIN_PORT_OTHER;
5225 }
5226 }
5227
5228 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5229 {
5230 struct drm_device *dev = crtc->dev;
5231 struct intel_encoder *intel_encoder;
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233 enum pipe pipe = intel_crtc->pipe;
5234 unsigned long mask;
5235 enum transcoder transcoder;
5236
5237 if (!crtc->state->active)
5238 return 0;
5239
5240 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5241
5242 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5243 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5244 if (intel_crtc->config->pch_pfit.enabled ||
5245 intel_crtc->config->pch_pfit.force_thru)
5246 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5247
5248 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5249 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5250
5251 return mask;
5252 }
5253
5254 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5255 {
5256 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 enum intel_display_power_domain domain;
5259 unsigned long domains, new_domains, old_domains;
5260
5261 old_domains = intel_crtc->enabled_power_domains;
5262 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5263
5264 domains = new_domains & ~old_domains;
5265
5266 for_each_power_domain(domain, domains)
5267 intel_display_power_get(dev_priv, domain);
5268
5269 return old_domains & ~new_domains;
5270 }
5271
5272 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5273 unsigned long domains)
5274 {
5275 enum intel_display_power_domain domain;
5276
5277 for_each_power_domain(domain, domains)
5278 intel_display_power_put(dev_priv, domain);
5279 }
5280
5281 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5282 {
5283 struct drm_device *dev = state->dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 unsigned long put_domains[I915_MAX_PIPES] = {};
5286 struct drm_crtc_state *crtc_state;
5287 struct drm_crtc *crtc;
5288 int i;
5289
5290 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5291 if (needs_modeset(crtc->state))
5292 put_domains[to_intel_crtc(crtc)->pipe] =
5293 modeset_get_crtc_power_domains(crtc);
5294 }
5295
5296 if (dev_priv->display.modeset_commit_cdclk) {
5297 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5298
5299 if (cdclk != dev_priv->cdclk_freq &&
5300 !WARN_ON(!state->allow_modeset))
5301 dev_priv->display.modeset_commit_cdclk(state);
5302 }
5303
5304 for (i = 0; i < I915_MAX_PIPES; i++)
5305 if (put_domains[i])
5306 modeset_put_power_domains(dev_priv, put_domains[i]);
5307 }
5308
5309 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5310 {
5311 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5312
5313 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5314 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5315 return max_cdclk_freq;
5316 else if (IS_CHERRYVIEW(dev_priv))
5317 return max_cdclk_freq*95/100;
5318 else if (INTEL_INFO(dev_priv)->gen < 4)
5319 return 2*max_cdclk_freq*90/100;
5320 else
5321 return max_cdclk_freq*90/100;
5322 }
5323
5324 static void intel_update_max_cdclk(struct drm_device *dev)
5325 {
5326 struct drm_i915_private *dev_priv = dev->dev_private;
5327
5328 if (IS_SKYLAKE(dev)) {
5329 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5330
5331 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5332 dev_priv->max_cdclk_freq = 675000;
5333 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5334 dev_priv->max_cdclk_freq = 540000;
5335 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5336 dev_priv->max_cdclk_freq = 450000;
5337 else
5338 dev_priv->max_cdclk_freq = 337500;
5339 } else if (IS_BROADWELL(dev)) {
5340 /*
5341 * FIXME with extra cooling we can allow
5342 * 540 MHz for ULX and 675 Mhz for ULT.
5343 * How can we know if extra cooling is
5344 * available? PCI ID, VTB, something else?
5345 */
5346 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5347 dev_priv->max_cdclk_freq = 450000;
5348 else if (IS_BDW_ULX(dev))
5349 dev_priv->max_cdclk_freq = 450000;
5350 else if (IS_BDW_ULT(dev))
5351 dev_priv->max_cdclk_freq = 540000;
5352 else
5353 dev_priv->max_cdclk_freq = 675000;
5354 } else if (IS_CHERRYVIEW(dev)) {
5355 dev_priv->max_cdclk_freq = 320000;
5356 } else if (IS_VALLEYVIEW(dev)) {
5357 dev_priv->max_cdclk_freq = 400000;
5358 } else {
5359 /* otherwise assume cdclk is fixed */
5360 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5361 }
5362
5363 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5364
5365 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5366 dev_priv->max_cdclk_freq);
5367
5368 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5369 dev_priv->max_dotclk_freq);
5370 }
5371
5372 static void intel_update_cdclk(struct drm_device *dev)
5373 {
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375
5376 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5377 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5378 dev_priv->cdclk_freq);
5379
5380 /*
5381 * Program the gmbus_freq based on the cdclk frequency.
5382 * BSpec erroneously claims we should aim for 4MHz, but
5383 * in fact 1MHz is the correct frequency.
5384 */
5385 if (IS_VALLEYVIEW(dev)) {
5386 /*
5387 * Program the gmbus_freq based on the cdclk frequency.
5388 * BSpec erroneously claims we should aim for 4MHz, but
5389 * in fact 1MHz is the correct frequency.
5390 */
5391 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5392 }
5393
5394 if (dev_priv->max_cdclk_freq == 0)
5395 intel_update_max_cdclk(dev);
5396 }
5397
5398 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5399 {
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 uint32_t divider;
5402 uint32_t ratio;
5403 uint32_t current_freq;
5404 int ret;
5405
5406 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5407 switch (frequency) {
5408 case 144000:
5409 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5410 ratio = BXT_DE_PLL_RATIO(60);
5411 break;
5412 case 288000:
5413 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5414 ratio = BXT_DE_PLL_RATIO(60);
5415 break;
5416 case 384000:
5417 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5418 ratio = BXT_DE_PLL_RATIO(60);
5419 break;
5420 case 576000:
5421 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5422 ratio = BXT_DE_PLL_RATIO(60);
5423 break;
5424 case 624000:
5425 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5426 ratio = BXT_DE_PLL_RATIO(65);
5427 break;
5428 case 19200:
5429 /*
5430 * Bypass frequency with DE PLL disabled. Init ratio, divider
5431 * to suppress GCC warning.
5432 */
5433 ratio = 0;
5434 divider = 0;
5435 break;
5436 default:
5437 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5438
5439 return;
5440 }
5441
5442 mutex_lock(&dev_priv->rps.hw_lock);
5443 /* Inform power controller of upcoming frequency change */
5444 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5445 0x80000000);
5446 mutex_unlock(&dev_priv->rps.hw_lock);
5447
5448 if (ret) {
5449 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5450 ret, frequency);
5451 return;
5452 }
5453
5454 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5455 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5456 current_freq = current_freq * 500 + 1000;
5457
5458 /*
5459 * DE PLL has to be disabled when
5460 * - setting to 19.2MHz (bypass, PLL isn't used)
5461 * - before setting to 624MHz (PLL needs toggling)
5462 * - before setting to any frequency from 624MHz (PLL needs toggling)
5463 */
5464 if (frequency == 19200 || frequency == 624000 ||
5465 current_freq == 624000) {
5466 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5467 /* Timeout 200us */
5468 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5469 1))
5470 DRM_ERROR("timout waiting for DE PLL unlock\n");
5471 }
5472
5473 if (frequency != 19200) {
5474 uint32_t val;
5475
5476 val = I915_READ(BXT_DE_PLL_CTL);
5477 val &= ~BXT_DE_PLL_RATIO_MASK;
5478 val |= ratio;
5479 I915_WRITE(BXT_DE_PLL_CTL, val);
5480
5481 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5482 /* Timeout 200us */
5483 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5484 DRM_ERROR("timeout waiting for DE PLL lock\n");
5485
5486 val = I915_READ(CDCLK_CTL);
5487 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5488 val |= divider;
5489 /*
5490 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5491 * enable otherwise.
5492 */
5493 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5494 if (frequency >= 500000)
5495 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5496
5497 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5498 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5499 val |= (frequency - 1000) / 500;
5500 I915_WRITE(CDCLK_CTL, val);
5501 }
5502
5503 mutex_lock(&dev_priv->rps.hw_lock);
5504 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5505 DIV_ROUND_UP(frequency, 25000));
5506 mutex_unlock(&dev_priv->rps.hw_lock);
5507
5508 if (ret) {
5509 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5510 ret, frequency);
5511 return;
5512 }
5513
5514 intel_update_cdclk(dev);
5515 }
5516
5517 void broxton_init_cdclk(struct drm_device *dev)
5518 {
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 uint32_t val;
5521
5522 /*
5523 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5524 * or else the reset will hang because there is no PCH to respond.
5525 * Move the handshake programming to initialization sequence.
5526 * Previously was left up to BIOS.
5527 */
5528 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5529 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5530 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5531
5532 /* Enable PG1 for cdclk */
5533 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5534
5535 /* check if cd clock is enabled */
5536 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5537 DRM_DEBUG_KMS("Display already initialized\n");
5538 return;
5539 }
5540
5541 /*
5542 * FIXME:
5543 * - The initial CDCLK needs to be read from VBT.
5544 * Need to make this change after VBT has changes for BXT.
5545 * - check if setting the max (or any) cdclk freq is really necessary
5546 * here, it belongs to modeset time
5547 */
5548 broxton_set_cdclk(dev, 624000);
5549
5550 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5551 POSTING_READ(DBUF_CTL);
5552
5553 udelay(10);
5554
5555 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5556 DRM_ERROR("DBuf power enable timeout!\n");
5557 }
5558
5559 void broxton_uninit_cdclk(struct drm_device *dev)
5560 {
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5562
5563 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5564 POSTING_READ(DBUF_CTL);
5565
5566 udelay(10);
5567
5568 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5569 DRM_ERROR("DBuf power disable timeout!\n");
5570
5571 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5572 broxton_set_cdclk(dev, 19200);
5573
5574 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5575 }
5576
5577 static const struct skl_cdclk_entry {
5578 unsigned int freq;
5579 unsigned int vco;
5580 } skl_cdclk_frequencies[] = {
5581 { .freq = 308570, .vco = 8640 },
5582 { .freq = 337500, .vco = 8100 },
5583 { .freq = 432000, .vco = 8640 },
5584 { .freq = 450000, .vco = 8100 },
5585 { .freq = 540000, .vco = 8100 },
5586 { .freq = 617140, .vco = 8640 },
5587 { .freq = 675000, .vco = 8100 },
5588 };
5589
5590 static unsigned int skl_cdclk_decimal(unsigned int freq)
5591 {
5592 return (freq - 1000) / 500;
5593 }
5594
5595 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5596 {
5597 unsigned int i;
5598
5599 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5600 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5601
5602 if (e->freq == freq)
5603 return e->vco;
5604 }
5605
5606 return 8100;
5607 }
5608
5609 static void
5610 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5611 {
5612 unsigned int min_freq;
5613 u32 val;
5614
5615 /* select the minimum CDCLK before enabling DPLL 0 */
5616 val = I915_READ(CDCLK_CTL);
5617 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5618 val |= CDCLK_FREQ_337_308;
5619
5620 if (required_vco == 8640)
5621 min_freq = 308570;
5622 else
5623 min_freq = 337500;
5624
5625 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5626
5627 I915_WRITE(CDCLK_CTL, val);
5628 POSTING_READ(CDCLK_CTL);
5629
5630 /*
5631 * We always enable DPLL0 with the lowest link rate possible, but still
5632 * taking into account the VCO required to operate the eDP panel at the
5633 * desired frequency. The usual DP link rates operate with a VCO of
5634 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5635 * The modeset code is responsible for the selection of the exact link
5636 * rate later on, with the constraint of choosing a frequency that
5637 * works with required_vco.
5638 */
5639 val = I915_READ(DPLL_CTRL1);
5640
5641 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5642 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5643 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5644 if (required_vco == 8640)
5645 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5646 SKL_DPLL0);
5647 else
5648 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5649 SKL_DPLL0);
5650
5651 I915_WRITE(DPLL_CTRL1, val);
5652 POSTING_READ(DPLL_CTRL1);
5653
5654 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5655
5656 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5657 DRM_ERROR("DPLL0 not locked\n");
5658 }
5659
5660 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5661 {
5662 int ret;
5663 u32 val;
5664
5665 /* inform PCU we want to change CDCLK */
5666 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5667 mutex_lock(&dev_priv->rps.hw_lock);
5668 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5669 mutex_unlock(&dev_priv->rps.hw_lock);
5670
5671 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5672 }
5673
5674 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5675 {
5676 unsigned int i;
5677
5678 for (i = 0; i < 15; i++) {
5679 if (skl_cdclk_pcu_ready(dev_priv))
5680 return true;
5681 udelay(10);
5682 }
5683
5684 return false;
5685 }
5686
5687 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5688 {
5689 struct drm_device *dev = dev_priv->dev;
5690 u32 freq_select, pcu_ack;
5691
5692 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5693
5694 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5695 DRM_ERROR("failed to inform PCU about cdclk change\n");
5696 return;
5697 }
5698
5699 /* set CDCLK_CTL */
5700 switch(freq) {
5701 case 450000:
5702 case 432000:
5703 freq_select = CDCLK_FREQ_450_432;
5704 pcu_ack = 1;
5705 break;
5706 case 540000:
5707 freq_select = CDCLK_FREQ_540;
5708 pcu_ack = 2;
5709 break;
5710 case 308570:
5711 case 337500:
5712 default:
5713 freq_select = CDCLK_FREQ_337_308;
5714 pcu_ack = 0;
5715 break;
5716 case 617140:
5717 case 675000:
5718 freq_select = CDCLK_FREQ_675_617;
5719 pcu_ack = 3;
5720 break;
5721 }
5722
5723 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5724 POSTING_READ(CDCLK_CTL);
5725
5726 /* inform PCU of the change */
5727 mutex_lock(&dev_priv->rps.hw_lock);
5728 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5729 mutex_unlock(&dev_priv->rps.hw_lock);
5730
5731 intel_update_cdclk(dev);
5732 }
5733
5734 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5735 {
5736 /* disable DBUF power */
5737 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5738 POSTING_READ(DBUF_CTL);
5739
5740 udelay(10);
5741
5742 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5743 DRM_ERROR("DBuf power disable timeout\n");
5744
5745 /*
5746 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5747 */
5748 if (dev_priv->csr.dmc_payload) {
5749 /* disable DPLL0 */
5750 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) &
5751 ~LCPLL_PLL_ENABLE);
5752 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5753 DRM_ERROR("Couldn't disable DPLL0\n");
5754 }
5755
5756 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5757 }
5758
5759 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5760 {
5761 u32 val;
5762 unsigned int required_vco;
5763
5764 /* enable PCH reset handshake */
5765 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5766 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5767
5768 /* enable PG1 and Misc I/O */
5769 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5770
5771 /* DPLL0 not enabled (happens on early BIOS versions) */
5772 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5773 /* enable DPLL0 */
5774 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5775 skl_dpll0_enable(dev_priv, required_vco);
5776 }
5777
5778 /* set CDCLK to the frequency the BIOS chose */
5779 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5780
5781 /* enable DBUF power */
5782 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5783 POSTING_READ(DBUF_CTL);
5784
5785 udelay(10);
5786
5787 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5788 DRM_ERROR("DBuf power enable timeout\n");
5789 }
5790
5791 /* Adjust CDclk dividers to allow high res or save power if possible */
5792 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5793 {
5794 struct drm_i915_private *dev_priv = dev->dev_private;
5795 u32 val, cmd;
5796
5797 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5798 != dev_priv->cdclk_freq);
5799
5800 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5801 cmd = 2;
5802 else if (cdclk == 266667)
5803 cmd = 1;
5804 else
5805 cmd = 0;
5806
5807 mutex_lock(&dev_priv->rps.hw_lock);
5808 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5809 val &= ~DSPFREQGUAR_MASK;
5810 val |= (cmd << DSPFREQGUAR_SHIFT);
5811 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5812 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5813 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5814 50)) {
5815 DRM_ERROR("timed out waiting for CDclk change\n");
5816 }
5817 mutex_unlock(&dev_priv->rps.hw_lock);
5818
5819 mutex_lock(&dev_priv->sb_lock);
5820
5821 if (cdclk == 400000) {
5822 u32 divider;
5823
5824 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5825
5826 /* adjust cdclk divider */
5827 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5828 val &= ~CCK_FREQUENCY_VALUES;
5829 val |= divider;
5830 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5831
5832 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5833 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5834 50))
5835 DRM_ERROR("timed out waiting for CDclk change\n");
5836 }
5837
5838 /* adjust self-refresh exit latency value */
5839 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5840 val &= ~0x7f;
5841
5842 /*
5843 * For high bandwidth configs, we set a higher latency in the bunit
5844 * so that the core display fetch happens in time to avoid underruns.
5845 */
5846 if (cdclk == 400000)
5847 val |= 4500 / 250; /* 4.5 usec */
5848 else
5849 val |= 3000 / 250; /* 3.0 usec */
5850 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5851
5852 mutex_unlock(&dev_priv->sb_lock);
5853
5854 intel_update_cdclk(dev);
5855 }
5856
5857 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5858 {
5859 struct drm_i915_private *dev_priv = dev->dev_private;
5860 u32 val, cmd;
5861
5862 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5863 != dev_priv->cdclk_freq);
5864
5865 switch (cdclk) {
5866 case 333333:
5867 case 320000:
5868 case 266667:
5869 case 200000:
5870 break;
5871 default:
5872 MISSING_CASE(cdclk);
5873 return;
5874 }
5875
5876 /*
5877 * Specs are full of misinformation, but testing on actual
5878 * hardware has shown that we just need to write the desired
5879 * CCK divider into the Punit register.
5880 */
5881 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5882
5883 mutex_lock(&dev_priv->rps.hw_lock);
5884 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5885 val &= ~DSPFREQGUAR_MASK_CHV;
5886 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5887 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5888 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5889 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5890 50)) {
5891 DRM_ERROR("timed out waiting for CDclk change\n");
5892 }
5893 mutex_unlock(&dev_priv->rps.hw_lock);
5894
5895 intel_update_cdclk(dev);
5896 }
5897
5898 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5899 int max_pixclk)
5900 {
5901 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5902 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5903
5904 /*
5905 * Really only a few cases to deal with, as only 4 CDclks are supported:
5906 * 200MHz
5907 * 267MHz
5908 * 320/333MHz (depends on HPLL freq)
5909 * 400MHz (VLV only)
5910 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5911 * of the lower bin and adjust if needed.
5912 *
5913 * We seem to get an unstable or solid color picture at 200MHz.
5914 * Not sure what's wrong. For now use 200MHz only when all pipes
5915 * are off.
5916 */
5917 if (!IS_CHERRYVIEW(dev_priv) &&
5918 max_pixclk > freq_320*limit/100)
5919 return 400000;
5920 else if (max_pixclk > 266667*limit/100)
5921 return freq_320;
5922 else if (max_pixclk > 0)
5923 return 266667;
5924 else
5925 return 200000;
5926 }
5927
5928 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5929 int max_pixclk)
5930 {
5931 /*
5932 * FIXME:
5933 * - remove the guardband, it's not needed on BXT
5934 * - set 19.2MHz bypass frequency if there are no active pipes
5935 */
5936 if (max_pixclk > 576000*9/10)
5937 return 624000;
5938 else if (max_pixclk > 384000*9/10)
5939 return 576000;
5940 else if (max_pixclk > 288000*9/10)
5941 return 384000;
5942 else if (max_pixclk > 144000*9/10)
5943 return 288000;
5944 else
5945 return 144000;
5946 }
5947
5948 /* Compute the max pixel clock for new configuration. Uses atomic state if
5949 * that's non-NULL, look at current state otherwise. */
5950 static int intel_mode_max_pixclk(struct drm_device *dev,
5951 struct drm_atomic_state *state)
5952 {
5953 struct intel_crtc *intel_crtc;
5954 struct intel_crtc_state *crtc_state;
5955 int max_pixclk = 0;
5956
5957 for_each_intel_crtc(dev, intel_crtc) {
5958 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5959 if (IS_ERR(crtc_state))
5960 return PTR_ERR(crtc_state);
5961
5962 if (!crtc_state->base.enable)
5963 continue;
5964
5965 max_pixclk = max(max_pixclk,
5966 crtc_state->base.adjusted_mode.crtc_clock);
5967 }
5968
5969 return max_pixclk;
5970 }
5971
5972 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5973 {
5974 struct drm_device *dev = state->dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private;
5976 int max_pixclk = intel_mode_max_pixclk(dev, state);
5977
5978 if (max_pixclk < 0)
5979 return max_pixclk;
5980
5981 to_intel_atomic_state(state)->cdclk =
5982 valleyview_calc_cdclk(dev_priv, max_pixclk);
5983
5984 return 0;
5985 }
5986
5987 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5988 {
5989 struct drm_device *dev = state->dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 int max_pixclk = intel_mode_max_pixclk(dev, state);
5992
5993 if (max_pixclk < 0)
5994 return max_pixclk;
5995
5996 to_intel_atomic_state(state)->cdclk =
5997 broxton_calc_cdclk(dev_priv, max_pixclk);
5998
5999 return 0;
6000 }
6001
6002 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6003 {
6004 unsigned int credits, default_credits;
6005
6006 if (IS_CHERRYVIEW(dev_priv))
6007 default_credits = PFI_CREDIT(12);
6008 else
6009 default_credits = PFI_CREDIT(8);
6010
6011 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6012 /* CHV suggested value is 31 or 63 */
6013 if (IS_CHERRYVIEW(dev_priv))
6014 credits = PFI_CREDIT_63;
6015 else
6016 credits = PFI_CREDIT(15);
6017 } else {
6018 credits = default_credits;
6019 }
6020
6021 /*
6022 * WA - write default credits before re-programming
6023 * FIXME: should we also set the resend bit here?
6024 */
6025 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6026 default_credits);
6027
6028 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6029 credits | PFI_CREDIT_RESEND);
6030
6031 /*
6032 * FIXME is this guaranteed to clear
6033 * immediately or should we poll for it?
6034 */
6035 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6036 }
6037
6038 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6039 {
6040 struct drm_device *dev = old_state->dev;
6041 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6042 struct drm_i915_private *dev_priv = dev->dev_private;
6043
6044 /*
6045 * FIXME: We can end up here with all power domains off, yet
6046 * with a CDCLK frequency other than the minimum. To account
6047 * for this take the PIPE-A power domain, which covers the HW
6048 * blocks needed for the following programming. This can be
6049 * removed once it's guaranteed that we get here either with
6050 * the minimum CDCLK set, or the required power domains
6051 * enabled.
6052 */
6053 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6054
6055 if (IS_CHERRYVIEW(dev))
6056 cherryview_set_cdclk(dev, req_cdclk);
6057 else
6058 valleyview_set_cdclk(dev, req_cdclk);
6059
6060 vlv_program_pfi_credits(dev_priv);
6061
6062 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6063 }
6064
6065 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6066 {
6067 struct drm_device *dev = crtc->dev;
6068 struct drm_i915_private *dev_priv = to_i915(dev);
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 struct intel_encoder *encoder;
6071 int pipe = intel_crtc->pipe;
6072 bool is_dsi;
6073
6074 if (WARN_ON(intel_crtc->active))
6075 return;
6076
6077 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6078
6079 if (intel_crtc->config->has_dp_encoder)
6080 intel_dp_set_m_n(intel_crtc, M1_N1);
6081
6082 intel_set_pipe_timings(intel_crtc);
6083
6084 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6088 I915_WRITE(CHV_CANVAS(pipe), 0);
6089 }
6090
6091 i9xx_set_pipeconf(intel_crtc);
6092
6093 intel_crtc->active = true;
6094
6095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6096
6097 for_each_encoder_on_crtc(dev, crtc, encoder)
6098 if (encoder->pre_pll_enable)
6099 encoder->pre_pll_enable(encoder);
6100
6101 if (!is_dsi) {
6102 if (IS_CHERRYVIEW(dev)) {
6103 chv_prepare_pll(intel_crtc, intel_crtc->config);
6104 chv_enable_pll(intel_crtc, intel_crtc->config);
6105 } else {
6106 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6107 vlv_enable_pll(intel_crtc, intel_crtc->config);
6108 }
6109 }
6110
6111 for_each_encoder_on_crtc(dev, crtc, encoder)
6112 if (encoder->pre_enable)
6113 encoder->pre_enable(encoder);
6114
6115 i9xx_pfit_enable(intel_crtc);
6116
6117 intel_crtc_load_lut(crtc);
6118
6119 intel_enable_pipe(intel_crtc);
6120
6121 assert_vblank_disabled(crtc);
6122 drm_crtc_vblank_on(crtc);
6123
6124 for_each_encoder_on_crtc(dev, crtc, encoder)
6125 encoder->enable(encoder);
6126 }
6127
6128 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6129 {
6130 struct drm_device *dev = crtc->base.dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132
6133 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6134 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6135 }
6136
6137 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6138 {
6139 struct drm_device *dev = crtc->dev;
6140 struct drm_i915_private *dev_priv = to_i915(dev);
6141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6142 struct intel_encoder *encoder;
6143 int pipe = intel_crtc->pipe;
6144
6145 if (WARN_ON(intel_crtc->active))
6146 return;
6147
6148 i9xx_set_pll_dividers(intel_crtc);
6149
6150 if (intel_crtc->config->has_dp_encoder)
6151 intel_dp_set_m_n(intel_crtc, M1_N1);
6152
6153 intel_set_pipe_timings(intel_crtc);
6154
6155 i9xx_set_pipeconf(intel_crtc);
6156
6157 intel_crtc->active = true;
6158
6159 if (!IS_GEN2(dev))
6160 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6161
6162 for_each_encoder_on_crtc(dev, crtc, encoder)
6163 if (encoder->pre_enable)
6164 encoder->pre_enable(encoder);
6165
6166 i9xx_enable_pll(intel_crtc);
6167
6168 i9xx_pfit_enable(intel_crtc);
6169
6170 intel_crtc_load_lut(crtc);
6171
6172 intel_update_watermarks(crtc);
6173 intel_enable_pipe(intel_crtc);
6174
6175 assert_vblank_disabled(crtc);
6176 drm_crtc_vblank_on(crtc);
6177
6178 for_each_encoder_on_crtc(dev, crtc, encoder)
6179 encoder->enable(encoder);
6180 }
6181
6182 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6183 {
6184 struct drm_device *dev = crtc->base.dev;
6185 struct drm_i915_private *dev_priv = dev->dev_private;
6186
6187 if (!crtc->config->gmch_pfit.control)
6188 return;
6189
6190 assert_pipe_disabled(dev_priv, crtc->pipe);
6191
6192 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6193 I915_READ(PFIT_CONTROL));
6194 I915_WRITE(PFIT_CONTROL, 0);
6195 }
6196
6197 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6198 {
6199 struct drm_device *dev = crtc->dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6202 struct intel_encoder *encoder;
6203 int pipe = intel_crtc->pipe;
6204
6205 /*
6206 * On gen2 planes are double buffered but the pipe isn't, so we must
6207 * wait for planes to fully turn off before disabling the pipe.
6208 * We also need to wait on all gmch platforms because of the
6209 * self-refresh mode constraint explained above.
6210 */
6211 intel_wait_for_vblank(dev, pipe);
6212
6213 for_each_encoder_on_crtc(dev, crtc, encoder)
6214 encoder->disable(encoder);
6215
6216 drm_crtc_vblank_off(crtc);
6217 assert_vblank_disabled(crtc);
6218
6219 intel_disable_pipe(intel_crtc);
6220
6221 i9xx_pfit_disable(intel_crtc);
6222
6223 for_each_encoder_on_crtc(dev, crtc, encoder)
6224 if (encoder->post_disable)
6225 encoder->post_disable(encoder);
6226
6227 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6228 if (IS_CHERRYVIEW(dev))
6229 chv_disable_pll(dev_priv, pipe);
6230 else if (IS_VALLEYVIEW(dev))
6231 vlv_disable_pll(dev_priv, pipe);
6232 else
6233 i9xx_disable_pll(intel_crtc);
6234 }
6235
6236 for_each_encoder_on_crtc(dev, crtc, encoder)
6237 if (encoder->post_pll_disable)
6238 encoder->post_pll_disable(encoder);
6239
6240 if (!IS_GEN2(dev))
6241 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6242 }
6243
6244 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6245 {
6246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6247 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6248 enum intel_display_power_domain domain;
6249 unsigned long domains;
6250
6251 if (!intel_crtc->active)
6252 return;
6253
6254 if (to_intel_plane_state(crtc->primary->state)->visible) {
6255 intel_crtc_wait_for_pending_flips(crtc);
6256 intel_pre_disable_primary(crtc);
6257 }
6258
6259 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6260 dev_priv->display.crtc_disable(crtc);
6261 intel_crtc->active = false;
6262 intel_update_watermarks(crtc);
6263 intel_disable_shared_dpll(intel_crtc);
6264
6265 domains = intel_crtc->enabled_power_domains;
6266 for_each_power_domain(domain, domains)
6267 intel_display_power_put(dev_priv, domain);
6268 intel_crtc->enabled_power_domains = 0;
6269 }
6270
6271 /*
6272 * turn all crtc's off, but do not adjust state
6273 * This has to be paired with a call to intel_modeset_setup_hw_state.
6274 */
6275 int intel_display_suspend(struct drm_device *dev)
6276 {
6277 struct drm_mode_config *config = &dev->mode_config;
6278 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6279 struct drm_atomic_state *state;
6280 struct drm_crtc *crtc;
6281 unsigned crtc_mask = 0;
6282 int ret = 0;
6283
6284 if (WARN_ON(!ctx))
6285 return 0;
6286
6287 lockdep_assert_held(&ctx->ww_ctx);
6288 state = drm_atomic_state_alloc(dev);
6289 if (WARN_ON(!state))
6290 return -ENOMEM;
6291
6292 state->acquire_ctx = ctx;
6293 state->allow_modeset = true;
6294
6295 for_each_crtc(dev, crtc) {
6296 struct drm_crtc_state *crtc_state =
6297 drm_atomic_get_crtc_state(state, crtc);
6298
6299 ret = PTR_ERR_OR_ZERO(crtc_state);
6300 if (ret)
6301 goto free;
6302
6303 if (!crtc_state->active)
6304 continue;
6305
6306 crtc_state->active = false;
6307 crtc_mask |= 1 << drm_crtc_index(crtc);
6308 }
6309
6310 if (crtc_mask) {
6311 ret = drm_atomic_commit(state);
6312
6313 if (!ret) {
6314 for_each_crtc(dev, crtc)
6315 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6316 crtc->state->active = true;
6317
6318 return ret;
6319 }
6320 }
6321
6322 free:
6323 if (ret)
6324 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6325 drm_atomic_state_free(state);
6326 return ret;
6327 }
6328
6329 void intel_encoder_destroy(struct drm_encoder *encoder)
6330 {
6331 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6332
6333 drm_encoder_cleanup(encoder);
6334 kfree(intel_encoder);
6335 }
6336
6337 /* Cross check the actual hw state with our own modeset state tracking (and it's
6338 * internal consistency). */
6339 static void intel_connector_check_state(struct intel_connector *connector)
6340 {
6341 struct drm_crtc *crtc = connector->base.state->crtc;
6342
6343 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6344 connector->base.base.id,
6345 connector->base.name);
6346
6347 if (connector->get_hw_state(connector)) {
6348 struct intel_encoder *encoder = connector->encoder;
6349 struct drm_connector_state *conn_state = connector->base.state;
6350
6351 I915_STATE_WARN(!crtc,
6352 "connector enabled without attached crtc\n");
6353
6354 if (!crtc)
6355 return;
6356
6357 I915_STATE_WARN(!crtc->state->active,
6358 "connector is active, but attached crtc isn't\n");
6359
6360 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6361 return;
6362
6363 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6364 "atomic encoder doesn't match attached encoder\n");
6365
6366 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6367 "attached encoder crtc differs from connector crtc\n");
6368 } else {
6369 I915_STATE_WARN(crtc && crtc->state->active,
6370 "attached crtc is active, but connector isn't\n");
6371 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6372 "best encoder set without crtc!\n");
6373 }
6374 }
6375
6376 int intel_connector_init(struct intel_connector *connector)
6377 {
6378 struct drm_connector_state *connector_state;
6379
6380 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6381 if (!connector_state)
6382 return -ENOMEM;
6383
6384 connector->base.state = connector_state;
6385 return 0;
6386 }
6387
6388 struct intel_connector *intel_connector_alloc(void)
6389 {
6390 struct intel_connector *connector;
6391
6392 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6393 if (!connector)
6394 return NULL;
6395
6396 if (intel_connector_init(connector) < 0) {
6397 kfree(connector);
6398 return NULL;
6399 }
6400
6401 return connector;
6402 }
6403
6404 /* Simple connector->get_hw_state implementation for encoders that support only
6405 * one connector and no cloning and hence the encoder state determines the state
6406 * of the connector. */
6407 bool intel_connector_get_hw_state(struct intel_connector *connector)
6408 {
6409 enum pipe pipe = 0;
6410 struct intel_encoder *encoder = connector->encoder;
6411
6412 return encoder->get_hw_state(encoder, &pipe);
6413 }
6414
6415 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6416 {
6417 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6418 return crtc_state->fdi_lanes;
6419
6420 return 0;
6421 }
6422
6423 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6424 struct intel_crtc_state *pipe_config)
6425 {
6426 struct drm_atomic_state *state = pipe_config->base.state;
6427 struct intel_crtc *other_crtc;
6428 struct intel_crtc_state *other_crtc_state;
6429
6430 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6431 pipe_name(pipe), pipe_config->fdi_lanes);
6432 if (pipe_config->fdi_lanes > 4) {
6433 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6434 pipe_name(pipe), pipe_config->fdi_lanes);
6435 return -EINVAL;
6436 }
6437
6438 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6439 if (pipe_config->fdi_lanes > 2) {
6440 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6441 pipe_config->fdi_lanes);
6442 return -EINVAL;
6443 } else {
6444 return 0;
6445 }
6446 }
6447
6448 if (INTEL_INFO(dev)->num_pipes == 2)
6449 return 0;
6450
6451 /* Ivybridge 3 pipe is really complicated */
6452 switch (pipe) {
6453 case PIPE_A:
6454 return 0;
6455 case PIPE_B:
6456 if (pipe_config->fdi_lanes <= 2)
6457 return 0;
6458
6459 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6460 other_crtc_state =
6461 intel_atomic_get_crtc_state(state, other_crtc);
6462 if (IS_ERR(other_crtc_state))
6463 return PTR_ERR(other_crtc_state);
6464
6465 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6466 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6467 pipe_name(pipe), pipe_config->fdi_lanes);
6468 return -EINVAL;
6469 }
6470 return 0;
6471 case PIPE_C:
6472 if (pipe_config->fdi_lanes > 2) {
6473 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6474 pipe_name(pipe), pipe_config->fdi_lanes);
6475 return -EINVAL;
6476 }
6477
6478 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6479 other_crtc_state =
6480 intel_atomic_get_crtc_state(state, other_crtc);
6481 if (IS_ERR(other_crtc_state))
6482 return PTR_ERR(other_crtc_state);
6483
6484 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6485 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6486 return -EINVAL;
6487 }
6488 return 0;
6489 default:
6490 BUG();
6491 }
6492 }
6493
6494 #define RETRY 1
6495 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6496 struct intel_crtc_state *pipe_config)
6497 {
6498 struct drm_device *dev = intel_crtc->base.dev;
6499 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6500 int lane, link_bw, fdi_dotclock, ret;
6501 bool needs_recompute = false;
6502
6503 retry:
6504 /* FDI is a binary signal running at ~2.7GHz, encoding
6505 * each output octet as 10 bits. The actual frequency
6506 * is stored as a divider into a 100MHz clock, and the
6507 * mode pixel clock is stored in units of 1KHz.
6508 * Hence the bw of each lane in terms of the mode signal
6509 * is:
6510 */
6511 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6512
6513 fdi_dotclock = adjusted_mode->crtc_clock;
6514
6515 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6516 pipe_config->pipe_bpp);
6517
6518 pipe_config->fdi_lanes = lane;
6519
6520 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6521 link_bw, &pipe_config->fdi_m_n);
6522
6523 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6524 intel_crtc->pipe, pipe_config);
6525 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6526 pipe_config->pipe_bpp -= 2*3;
6527 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6528 pipe_config->pipe_bpp);
6529 needs_recompute = true;
6530 pipe_config->bw_constrained = true;
6531
6532 goto retry;
6533 }
6534
6535 if (needs_recompute)
6536 return RETRY;
6537
6538 return ret;
6539 }
6540
6541 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6542 struct intel_crtc_state *pipe_config)
6543 {
6544 if (pipe_config->pipe_bpp > 24)
6545 return false;
6546
6547 /* HSW can handle pixel rate up to cdclk? */
6548 if (IS_HASWELL(dev_priv->dev))
6549 return true;
6550
6551 /*
6552 * We compare against max which means we must take
6553 * the increased cdclk requirement into account when
6554 * calculating the new cdclk.
6555 *
6556 * Should measure whether using a lower cdclk w/o IPS
6557 */
6558 return ilk_pipe_pixel_rate(pipe_config) <=
6559 dev_priv->max_cdclk_freq * 95 / 100;
6560 }
6561
6562 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6563 struct intel_crtc_state *pipe_config)
6564 {
6565 struct drm_device *dev = crtc->base.dev;
6566 struct drm_i915_private *dev_priv = dev->dev_private;
6567
6568 pipe_config->ips_enabled = i915.enable_ips &&
6569 hsw_crtc_supports_ips(crtc) &&
6570 pipe_config_supports_ips(dev_priv, pipe_config);
6571 }
6572
6573 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6574 struct intel_crtc_state *pipe_config)
6575 {
6576 struct drm_device *dev = crtc->base.dev;
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6579
6580 /* FIXME should check pixel clock limits on all platforms */
6581 if (INTEL_INFO(dev)->gen < 4) {
6582 int clock_limit = dev_priv->max_cdclk_freq;
6583
6584 /*
6585 * Enable pixel doubling when the dot clock
6586 * is > 90% of the (display) core speed.
6587 *
6588 * GDG double wide on either pipe,
6589 * otherwise pipe A only.
6590 */
6591 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6592 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6593 clock_limit *= 2;
6594 pipe_config->double_wide = true;
6595 }
6596
6597 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6598 return -EINVAL;
6599 }
6600
6601 /*
6602 * Pipe horizontal size must be even in:
6603 * - DVO ganged mode
6604 * - LVDS dual channel mode
6605 * - Double wide pipe
6606 */
6607 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6608 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6609 pipe_config->pipe_src_w &= ~1;
6610
6611 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6612 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6613 */
6614 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6615 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6616 return -EINVAL;
6617
6618 if (HAS_IPS(dev))
6619 hsw_compute_ips_config(crtc, pipe_config);
6620
6621 if (pipe_config->has_pch_encoder)
6622 return ironlake_fdi_compute_config(crtc, pipe_config);
6623
6624 return 0;
6625 }
6626
6627 static int skylake_get_display_clock_speed(struct drm_device *dev)
6628 {
6629 struct drm_i915_private *dev_priv = to_i915(dev);
6630 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6631 uint32_t cdctl = I915_READ(CDCLK_CTL);
6632 uint32_t linkrate;
6633
6634 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6635 return 24000; /* 24MHz is the cd freq with NSSC ref */
6636
6637 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6638 return 540000;
6639
6640 linkrate = (I915_READ(DPLL_CTRL1) &
6641 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6642
6643 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6644 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6645 /* vco 8640 */
6646 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6647 case CDCLK_FREQ_450_432:
6648 return 432000;
6649 case CDCLK_FREQ_337_308:
6650 return 308570;
6651 case CDCLK_FREQ_675_617:
6652 return 617140;
6653 default:
6654 WARN(1, "Unknown cd freq selection\n");
6655 }
6656 } else {
6657 /* vco 8100 */
6658 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6659 case CDCLK_FREQ_450_432:
6660 return 450000;
6661 case CDCLK_FREQ_337_308:
6662 return 337500;
6663 case CDCLK_FREQ_675_617:
6664 return 675000;
6665 default:
6666 WARN(1, "Unknown cd freq selection\n");
6667 }
6668 }
6669
6670 /* error case, do as if DPLL0 isn't enabled */
6671 return 24000;
6672 }
6673
6674 static int broxton_get_display_clock_speed(struct drm_device *dev)
6675 {
6676 struct drm_i915_private *dev_priv = to_i915(dev);
6677 uint32_t cdctl = I915_READ(CDCLK_CTL);
6678 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6679 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6680 int cdclk;
6681
6682 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6683 return 19200;
6684
6685 cdclk = 19200 * pll_ratio / 2;
6686
6687 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6688 case BXT_CDCLK_CD2X_DIV_SEL_1:
6689 return cdclk; /* 576MHz or 624MHz */
6690 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6691 return cdclk * 2 / 3; /* 384MHz */
6692 case BXT_CDCLK_CD2X_DIV_SEL_2:
6693 return cdclk / 2; /* 288MHz */
6694 case BXT_CDCLK_CD2X_DIV_SEL_4:
6695 return cdclk / 4; /* 144MHz */
6696 }
6697
6698 /* error case, do as if DE PLL isn't enabled */
6699 return 19200;
6700 }
6701
6702 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6703 {
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 uint32_t lcpll = I915_READ(LCPLL_CTL);
6706 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6707
6708 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6709 return 800000;
6710 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6711 return 450000;
6712 else if (freq == LCPLL_CLK_FREQ_450)
6713 return 450000;
6714 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6715 return 540000;
6716 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6717 return 337500;
6718 else
6719 return 675000;
6720 }
6721
6722 static int haswell_get_display_clock_speed(struct drm_device *dev)
6723 {
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 uint32_t lcpll = I915_READ(LCPLL_CTL);
6726 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6727
6728 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6729 return 800000;
6730 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6731 return 450000;
6732 else if (freq == LCPLL_CLK_FREQ_450)
6733 return 450000;
6734 else if (IS_HSW_ULT(dev))
6735 return 337500;
6736 else
6737 return 540000;
6738 }
6739
6740 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6741 {
6742 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6743 CCK_DISPLAY_CLOCK_CONTROL);
6744 }
6745
6746 static int ilk_get_display_clock_speed(struct drm_device *dev)
6747 {
6748 return 450000;
6749 }
6750
6751 static int i945_get_display_clock_speed(struct drm_device *dev)
6752 {
6753 return 400000;
6754 }
6755
6756 static int i915_get_display_clock_speed(struct drm_device *dev)
6757 {
6758 return 333333;
6759 }
6760
6761 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6762 {
6763 return 200000;
6764 }
6765
6766 static int pnv_get_display_clock_speed(struct drm_device *dev)
6767 {
6768 u16 gcfgc = 0;
6769
6770 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6771
6772 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6773 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6774 return 266667;
6775 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6776 return 333333;
6777 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6778 return 444444;
6779 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6780 return 200000;
6781 default:
6782 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6783 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6784 return 133333;
6785 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6786 return 166667;
6787 }
6788 }
6789
6790 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6791 {
6792 u16 gcfgc = 0;
6793
6794 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6795
6796 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6797 return 133333;
6798 else {
6799 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6800 case GC_DISPLAY_CLOCK_333_MHZ:
6801 return 333333;
6802 default:
6803 case GC_DISPLAY_CLOCK_190_200_MHZ:
6804 return 190000;
6805 }
6806 }
6807 }
6808
6809 static int i865_get_display_clock_speed(struct drm_device *dev)
6810 {
6811 return 266667;
6812 }
6813
6814 static int i85x_get_display_clock_speed(struct drm_device *dev)
6815 {
6816 u16 hpllcc = 0;
6817
6818 /*
6819 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6820 * encoding is different :(
6821 * FIXME is this the right way to detect 852GM/852GMV?
6822 */
6823 if (dev->pdev->revision == 0x1)
6824 return 133333;
6825
6826 pci_bus_read_config_word(dev->pdev->bus,
6827 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6828
6829 /* Assume that the hardware is in the high speed state. This
6830 * should be the default.
6831 */
6832 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6833 case GC_CLOCK_133_200:
6834 case GC_CLOCK_133_200_2:
6835 case GC_CLOCK_100_200:
6836 return 200000;
6837 case GC_CLOCK_166_250:
6838 return 250000;
6839 case GC_CLOCK_100_133:
6840 return 133333;
6841 case GC_CLOCK_133_266:
6842 case GC_CLOCK_133_266_2:
6843 case GC_CLOCK_166_266:
6844 return 266667;
6845 }
6846
6847 /* Shouldn't happen */
6848 return 0;
6849 }
6850
6851 static int i830_get_display_clock_speed(struct drm_device *dev)
6852 {
6853 return 133333;
6854 }
6855
6856 static unsigned int intel_hpll_vco(struct drm_device *dev)
6857 {
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6859 static const unsigned int blb_vco[8] = {
6860 [0] = 3200000,
6861 [1] = 4000000,
6862 [2] = 5333333,
6863 [3] = 4800000,
6864 [4] = 6400000,
6865 };
6866 static const unsigned int pnv_vco[8] = {
6867 [0] = 3200000,
6868 [1] = 4000000,
6869 [2] = 5333333,
6870 [3] = 4800000,
6871 [4] = 2666667,
6872 };
6873 static const unsigned int cl_vco[8] = {
6874 [0] = 3200000,
6875 [1] = 4000000,
6876 [2] = 5333333,
6877 [3] = 6400000,
6878 [4] = 3333333,
6879 [5] = 3566667,
6880 [6] = 4266667,
6881 };
6882 static const unsigned int elk_vco[8] = {
6883 [0] = 3200000,
6884 [1] = 4000000,
6885 [2] = 5333333,
6886 [3] = 4800000,
6887 };
6888 static const unsigned int ctg_vco[8] = {
6889 [0] = 3200000,
6890 [1] = 4000000,
6891 [2] = 5333333,
6892 [3] = 6400000,
6893 [4] = 2666667,
6894 [5] = 4266667,
6895 };
6896 const unsigned int *vco_table;
6897 unsigned int vco;
6898 uint8_t tmp = 0;
6899
6900 /* FIXME other chipsets? */
6901 if (IS_GM45(dev))
6902 vco_table = ctg_vco;
6903 else if (IS_G4X(dev))
6904 vco_table = elk_vco;
6905 else if (IS_CRESTLINE(dev))
6906 vco_table = cl_vco;
6907 else if (IS_PINEVIEW(dev))
6908 vco_table = pnv_vco;
6909 else if (IS_G33(dev))
6910 vco_table = blb_vco;
6911 else
6912 return 0;
6913
6914 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6915
6916 vco = vco_table[tmp & 0x7];
6917 if (vco == 0)
6918 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6919 else
6920 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6921
6922 return vco;
6923 }
6924
6925 static int gm45_get_display_clock_speed(struct drm_device *dev)
6926 {
6927 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6928 uint16_t tmp = 0;
6929
6930 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6931
6932 cdclk_sel = (tmp >> 12) & 0x1;
6933
6934 switch (vco) {
6935 case 2666667:
6936 case 4000000:
6937 case 5333333:
6938 return cdclk_sel ? 333333 : 222222;
6939 case 3200000:
6940 return cdclk_sel ? 320000 : 228571;
6941 default:
6942 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6943 return 222222;
6944 }
6945 }
6946
6947 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6948 {
6949 static const uint8_t div_3200[] = { 16, 10, 8 };
6950 static const uint8_t div_4000[] = { 20, 12, 10 };
6951 static const uint8_t div_5333[] = { 24, 16, 14 };
6952 const uint8_t *div_table;
6953 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6954 uint16_t tmp = 0;
6955
6956 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6957
6958 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6959
6960 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6961 goto fail;
6962
6963 switch (vco) {
6964 case 3200000:
6965 div_table = div_3200;
6966 break;
6967 case 4000000:
6968 div_table = div_4000;
6969 break;
6970 case 5333333:
6971 div_table = div_5333;
6972 break;
6973 default:
6974 goto fail;
6975 }
6976
6977 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6978
6979 fail:
6980 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6981 return 200000;
6982 }
6983
6984 static int g33_get_display_clock_speed(struct drm_device *dev)
6985 {
6986 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6987 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6988 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6989 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6990 const uint8_t *div_table;
6991 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6992 uint16_t tmp = 0;
6993
6994 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6995
6996 cdclk_sel = (tmp >> 4) & 0x7;
6997
6998 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6999 goto fail;
7000
7001 switch (vco) {
7002 case 3200000:
7003 div_table = div_3200;
7004 break;
7005 case 4000000:
7006 div_table = div_4000;
7007 break;
7008 case 4800000:
7009 div_table = div_4800;
7010 break;
7011 case 5333333:
7012 div_table = div_5333;
7013 break;
7014 default:
7015 goto fail;
7016 }
7017
7018 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7019
7020 fail:
7021 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7022 return 190476;
7023 }
7024
7025 static void
7026 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7027 {
7028 while (*num > DATA_LINK_M_N_MASK ||
7029 *den > DATA_LINK_M_N_MASK) {
7030 *num >>= 1;
7031 *den >>= 1;
7032 }
7033 }
7034
7035 static void compute_m_n(unsigned int m, unsigned int n,
7036 uint32_t *ret_m, uint32_t *ret_n)
7037 {
7038 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7039 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7040 intel_reduce_m_n_ratio(ret_m, ret_n);
7041 }
7042
7043 void
7044 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7045 int pixel_clock, int link_clock,
7046 struct intel_link_m_n *m_n)
7047 {
7048 m_n->tu = 64;
7049
7050 compute_m_n(bits_per_pixel * pixel_clock,
7051 link_clock * nlanes * 8,
7052 &m_n->gmch_m, &m_n->gmch_n);
7053
7054 compute_m_n(pixel_clock, link_clock,
7055 &m_n->link_m, &m_n->link_n);
7056 }
7057
7058 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7059 {
7060 if (i915.panel_use_ssc >= 0)
7061 return i915.panel_use_ssc != 0;
7062 return dev_priv->vbt.lvds_use_ssc
7063 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7064 }
7065
7066 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7067 int num_connectors)
7068 {
7069 struct drm_device *dev = crtc_state->base.crtc->dev;
7070 struct drm_i915_private *dev_priv = dev->dev_private;
7071 int refclk;
7072
7073 WARN_ON(!crtc_state->base.state);
7074
7075 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7076 refclk = 100000;
7077 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7078 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7079 refclk = dev_priv->vbt.lvds_ssc_freq;
7080 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7081 } else if (!IS_GEN2(dev)) {
7082 refclk = 96000;
7083 } else {
7084 refclk = 48000;
7085 }
7086
7087 return refclk;
7088 }
7089
7090 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7091 {
7092 return (1 << dpll->n) << 16 | dpll->m2;
7093 }
7094
7095 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7096 {
7097 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7098 }
7099
7100 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7101 struct intel_crtc_state *crtc_state,
7102 intel_clock_t *reduced_clock)
7103 {
7104 struct drm_device *dev = crtc->base.dev;
7105 u32 fp, fp2 = 0;
7106
7107 if (IS_PINEVIEW(dev)) {
7108 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7109 if (reduced_clock)
7110 fp2 = pnv_dpll_compute_fp(reduced_clock);
7111 } else {
7112 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7113 if (reduced_clock)
7114 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7115 }
7116
7117 crtc_state->dpll_hw_state.fp0 = fp;
7118
7119 crtc->lowfreq_avail = false;
7120 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7121 reduced_clock) {
7122 crtc_state->dpll_hw_state.fp1 = fp2;
7123 crtc->lowfreq_avail = true;
7124 } else {
7125 crtc_state->dpll_hw_state.fp1 = fp;
7126 }
7127 }
7128
7129 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7130 pipe)
7131 {
7132 u32 reg_val;
7133
7134 /*
7135 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7136 * and set it to a reasonable value instead.
7137 */
7138 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7139 reg_val &= 0xffffff00;
7140 reg_val |= 0x00000030;
7141 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7142
7143 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7144 reg_val &= 0x8cffffff;
7145 reg_val = 0x8c000000;
7146 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7147
7148 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7149 reg_val &= 0xffffff00;
7150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7151
7152 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7153 reg_val &= 0x00ffffff;
7154 reg_val |= 0xb0000000;
7155 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7156 }
7157
7158 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7159 struct intel_link_m_n *m_n)
7160 {
7161 struct drm_device *dev = crtc->base.dev;
7162 struct drm_i915_private *dev_priv = dev->dev_private;
7163 int pipe = crtc->pipe;
7164
7165 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7166 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7167 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7168 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7169 }
7170
7171 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7172 struct intel_link_m_n *m_n,
7173 struct intel_link_m_n *m2_n2)
7174 {
7175 struct drm_device *dev = crtc->base.dev;
7176 struct drm_i915_private *dev_priv = dev->dev_private;
7177 int pipe = crtc->pipe;
7178 enum transcoder transcoder = crtc->config->cpu_transcoder;
7179
7180 if (INTEL_INFO(dev)->gen >= 5) {
7181 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7182 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7183 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7184 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7185 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7186 * for gen < 8) and if DRRS is supported (to make sure the
7187 * registers are not unnecessarily accessed).
7188 */
7189 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7190 crtc->config->has_drrs) {
7191 I915_WRITE(PIPE_DATA_M2(transcoder),
7192 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7193 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7194 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7195 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7196 }
7197 } else {
7198 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7199 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7200 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7201 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7202 }
7203 }
7204
7205 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7206 {
7207 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7208
7209 if (m_n == M1_N1) {
7210 dp_m_n = &crtc->config->dp_m_n;
7211 dp_m2_n2 = &crtc->config->dp_m2_n2;
7212 } else if (m_n == M2_N2) {
7213
7214 /*
7215 * M2_N2 registers are not supported. Hence m2_n2 divider value
7216 * needs to be programmed into M1_N1.
7217 */
7218 dp_m_n = &crtc->config->dp_m2_n2;
7219 } else {
7220 DRM_ERROR("Unsupported divider value\n");
7221 return;
7222 }
7223
7224 if (crtc->config->has_pch_encoder)
7225 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7226 else
7227 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7228 }
7229
7230 static void vlv_compute_dpll(struct intel_crtc *crtc,
7231 struct intel_crtc_state *pipe_config)
7232 {
7233 u32 dpll, dpll_md;
7234
7235 /*
7236 * Enable DPIO clock input. We should never disable the reference
7237 * clock for pipe B, since VGA hotplug / manual detection depends
7238 * on it.
7239 */
7240 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7241 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7242 /* We should never disable this, set it here for state tracking */
7243 if (crtc->pipe == PIPE_B)
7244 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7245 dpll |= DPLL_VCO_ENABLE;
7246 pipe_config->dpll_hw_state.dpll = dpll;
7247
7248 dpll_md = (pipe_config->pixel_multiplier - 1)
7249 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7250 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7251 }
7252
7253 static void vlv_prepare_pll(struct intel_crtc *crtc,
7254 const struct intel_crtc_state *pipe_config)
7255 {
7256 struct drm_device *dev = crtc->base.dev;
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 int pipe = crtc->pipe;
7259 u32 mdiv;
7260 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7261 u32 coreclk, reg_val;
7262
7263 mutex_lock(&dev_priv->sb_lock);
7264
7265 bestn = pipe_config->dpll.n;
7266 bestm1 = pipe_config->dpll.m1;
7267 bestm2 = pipe_config->dpll.m2;
7268 bestp1 = pipe_config->dpll.p1;
7269 bestp2 = pipe_config->dpll.p2;
7270
7271 /* See eDP HDMI DPIO driver vbios notes doc */
7272
7273 /* PLL B needs special handling */
7274 if (pipe == PIPE_B)
7275 vlv_pllb_recal_opamp(dev_priv, pipe);
7276
7277 /* Set up Tx target for periodic Rcomp update */
7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7279
7280 /* Disable target IRef on PLL */
7281 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7282 reg_val &= 0x00ffffff;
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7284
7285 /* Disable fast lock */
7286 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7287
7288 /* Set idtafcrecal before PLL is enabled */
7289 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7290 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7291 mdiv |= ((bestn << DPIO_N_SHIFT));
7292 mdiv |= (1 << DPIO_K_SHIFT);
7293
7294 /*
7295 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7296 * but we don't support that).
7297 * Note: don't use the DAC post divider as it seems unstable.
7298 */
7299 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7300 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7301
7302 mdiv |= DPIO_ENABLE_CALIBRATION;
7303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7304
7305 /* Set HBR and RBR LPF coefficients */
7306 if (pipe_config->port_clock == 162000 ||
7307 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7308 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7310 0x009f0003);
7311 else
7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7313 0x00d0000f);
7314
7315 if (pipe_config->has_dp_encoder) {
7316 /* Use SSC source */
7317 if (pipe == PIPE_A)
7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7319 0x0df40000);
7320 else
7321 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7322 0x0df70000);
7323 } else { /* HDMI or VGA */
7324 /* Use bend source */
7325 if (pipe == PIPE_A)
7326 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7327 0x0df70000);
7328 else
7329 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7330 0x0df40000);
7331 }
7332
7333 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7334 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7335 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7336 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7337 coreclk |= 0x01000000;
7338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7339
7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7341 mutex_unlock(&dev_priv->sb_lock);
7342 }
7343
7344 static void chv_compute_dpll(struct intel_crtc *crtc,
7345 struct intel_crtc_state *pipe_config)
7346 {
7347 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7348 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7349 DPLL_VCO_ENABLE;
7350 if (crtc->pipe != PIPE_A)
7351 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7352
7353 pipe_config->dpll_hw_state.dpll_md =
7354 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7355 }
7356
7357 static void chv_prepare_pll(struct intel_crtc *crtc,
7358 const struct intel_crtc_state *pipe_config)
7359 {
7360 struct drm_device *dev = crtc->base.dev;
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362 int pipe = crtc->pipe;
7363 int dpll_reg = DPLL(crtc->pipe);
7364 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7365 u32 loopfilter, tribuf_calcntr;
7366 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7367 u32 dpio_val;
7368 int vco;
7369
7370 bestn = pipe_config->dpll.n;
7371 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7372 bestm1 = pipe_config->dpll.m1;
7373 bestm2 = pipe_config->dpll.m2 >> 22;
7374 bestp1 = pipe_config->dpll.p1;
7375 bestp2 = pipe_config->dpll.p2;
7376 vco = pipe_config->dpll.vco;
7377 dpio_val = 0;
7378 loopfilter = 0;
7379
7380 /*
7381 * Enable Refclk and SSC
7382 */
7383 I915_WRITE(dpll_reg,
7384 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7385
7386 mutex_lock(&dev_priv->sb_lock);
7387
7388 /* p1 and p2 divider */
7389 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7390 5 << DPIO_CHV_S1_DIV_SHIFT |
7391 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7392 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7393 1 << DPIO_CHV_K_DIV_SHIFT);
7394
7395 /* Feedback post-divider - m2 */
7396 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7397
7398 /* Feedback refclk divider - n and m1 */
7399 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7400 DPIO_CHV_M1_DIV_BY_2 |
7401 1 << DPIO_CHV_N_DIV_SHIFT);
7402
7403 /* M2 fraction division */
7404 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7405
7406 /* M2 fraction division enable */
7407 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7408 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7409 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7410 if (bestm2_frac)
7411 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7412 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7413
7414 /* Program digital lock detect threshold */
7415 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7416 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7417 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7418 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7419 if (!bestm2_frac)
7420 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7421 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7422
7423 /* Loop filter */
7424 if (vco == 5400000) {
7425 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7426 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7427 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7428 tribuf_calcntr = 0x9;
7429 } else if (vco <= 6200000) {
7430 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7431 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7432 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7433 tribuf_calcntr = 0x9;
7434 } else if (vco <= 6480000) {
7435 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7436 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7437 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438 tribuf_calcntr = 0x8;
7439 } else {
7440 /* Not supported. Apply the same limits as in the max case */
7441 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7442 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7443 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7444 tribuf_calcntr = 0;
7445 }
7446 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7447
7448 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7449 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7450 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7451 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7452
7453 /* AFC Recal */
7454 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7455 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7456 DPIO_AFC_RECAL);
7457
7458 mutex_unlock(&dev_priv->sb_lock);
7459 }
7460
7461 /**
7462 * vlv_force_pll_on - forcibly enable just the PLL
7463 * @dev_priv: i915 private structure
7464 * @pipe: pipe PLL to enable
7465 * @dpll: PLL configuration
7466 *
7467 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7468 * in cases where we need the PLL enabled even when @pipe is not going to
7469 * be enabled.
7470 */
7471 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7472 const struct dpll *dpll)
7473 {
7474 struct intel_crtc *crtc =
7475 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7476 struct intel_crtc_state pipe_config = {
7477 .base.crtc = &crtc->base,
7478 .pixel_multiplier = 1,
7479 .dpll = *dpll,
7480 };
7481
7482 if (IS_CHERRYVIEW(dev)) {
7483 chv_compute_dpll(crtc, &pipe_config);
7484 chv_prepare_pll(crtc, &pipe_config);
7485 chv_enable_pll(crtc, &pipe_config);
7486 } else {
7487 vlv_compute_dpll(crtc, &pipe_config);
7488 vlv_prepare_pll(crtc, &pipe_config);
7489 vlv_enable_pll(crtc, &pipe_config);
7490 }
7491 }
7492
7493 /**
7494 * vlv_force_pll_off - forcibly disable just the PLL
7495 * @dev_priv: i915 private structure
7496 * @pipe: pipe PLL to disable
7497 *
7498 * Disable the PLL for @pipe. To be used in cases where we need
7499 * the PLL enabled even when @pipe is not going to be enabled.
7500 */
7501 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7502 {
7503 if (IS_CHERRYVIEW(dev))
7504 chv_disable_pll(to_i915(dev), pipe);
7505 else
7506 vlv_disable_pll(to_i915(dev), pipe);
7507 }
7508
7509 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7510 struct intel_crtc_state *crtc_state,
7511 intel_clock_t *reduced_clock,
7512 int num_connectors)
7513 {
7514 struct drm_device *dev = crtc->base.dev;
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 u32 dpll;
7517 bool is_sdvo;
7518 struct dpll *clock = &crtc_state->dpll;
7519
7520 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7521
7522 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7523 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7524
7525 dpll = DPLL_VGA_MODE_DIS;
7526
7527 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7528 dpll |= DPLLB_MODE_LVDS;
7529 else
7530 dpll |= DPLLB_MODE_DAC_SERIAL;
7531
7532 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7533 dpll |= (crtc_state->pixel_multiplier - 1)
7534 << SDVO_MULTIPLIER_SHIFT_HIRES;
7535 }
7536
7537 if (is_sdvo)
7538 dpll |= DPLL_SDVO_HIGH_SPEED;
7539
7540 if (crtc_state->has_dp_encoder)
7541 dpll |= DPLL_SDVO_HIGH_SPEED;
7542
7543 /* compute bitmask from p1 value */
7544 if (IS_PINEVIEW(dev))
7545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7546 else {
7547 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7548 if (IS_G4X(dev) && reduced_clock)
7549 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7550 }
7551 switch (clock->p2) {
7552 case 5:
7553 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7554 break;
7555 case 7:
7556 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7557 break;
7558 case 10:
7559 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7560 break;
7561 case 14:
7562 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7563 break;
7564 }
7565 if (INTEL_INFO(dev)->gen >= 4)
7566 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7567
7568 if (crtc_state->sdvo_tv_clock)
7569 dpll |= PLL_REF_INPUT_TVCLKINBC;
7570 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7571 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7572 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7573 else
7574 dpll |= PLL_REF_INPUT_DREFCLK;
7575
7576 dpll |= DPLL_VCO_ENABLE;
7577 crtc_state->dpll_hw_state.dpll = dpll;
7578
7579 if (INTEL_INFO(dev)->gen >= 4) {
7580 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7581 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7582 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7583 }
7584 }
7585
7586 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7587 struct intel_crtc_state *crtc_state,
7588 intel_clock_t *reduced_clock,
7589 int num_connectors)
7590 {
7591 struct drm_device *dev = crtc->base.dev;
7592 struct drm_i915_private *dev_priv = dev->dev_private;
7593 u32 dpll;
7594 struct dpll *clock = &crtc_state->dpll;
7595
7596 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7597
7598 dpll = DPLL_VGA_MODE_DIS;
7599
7600 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7601 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7602 } else {
7603 if (clock->p1 == 2)
7604 dpll |= PLL_P1_DIVIDE_BY_TWO;
7605 else
7606 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7607 if (clock->p2 == 4)
7608 dpll |= PLL_P2_DIVIDE_BY_4;
7609 }
7610
7611 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7612 dpll |= DPLL_DVO_2X_MODE;
7613
7614 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7615 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7616 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7617 else
7618 dpll |= PLL_REF_INPUT_DREFCLK;
7619
7620 dpll |= DPLL_VCO_ENABLE;
7621 crtc_state->dpll_hw_state.dpll = dpll;
7622 }
7623
7624 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7625 {
7626 struct drm_device *dev = intel_crtc->base.dev;
7627 struct drm_i915_private *dev_priv = dev->dev_private;
7628 enum pipe pipe = intel_crtc->pipe;
7629 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7630 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7631 uint32_t crtc_vtotal, crtc_vblank_end;
7632 int vsyncshift = 0;
7633
7634 /* We need to be careful not to changed the adjusted mode, for otherwise
7635 * the hw state checker will get angry at the mismatch. */
7636 crtc_vtotal = adjusted_mode->crtc_vtotal;
7637 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7638
7639 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7640 /* the chip adds 2 halflines automatically */
7641 crtc_vtotal -= 1;
7642 crtc_vblank_end -= 1;
7643
7644 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7645 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7646 else
7647 vsyncshift = adjusted_mode->crtc_hsync_start -
7648 adjusted_mode->crtc_htotal / 2;
7649 if (vsyncshift < 0)
7650 vsyncshift += adjusted_mode->crtc_htotal;
7651 }
7652
7653 if (INTEL_INFO(dev)->gen > 3)
7654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7655
7656 I915_WRITE(HTOTAL(cpu_transcoder),
7657 (adjusted_mode->crtc_hdisplay - 1) |
7658 ((adjusted_mode->crtc_htotal - 1) << 16));
7659 I915_WRITE(HBLANK(cpu_transcoder),
7660 (adjusted_mode->crtc_hblank_start - 1) |
7661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7662 I915_WRITE(HSYNC(cpu_transcoder),
7663 (adjusted_mode->crtc_hsync_start - 1) |
7664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7665
7666 I915_WRITE(VTOTAL(cpu_transcoder),
7667 (adjusted_mode->crtc_vdisplay - 1) |
7668 ((crtc_vtotal - 1) << 16));
7669 I915_WRITE(VBLANK(cpu_transcoder),
7670 (adjusted_mode->crtc_vblank_start - 1) |
7671 ((crtc_vblank_end - 1) << 16));
7672 I915_WRITE(VSYNC(cpu_transcoder),
7673 (adjusted_mode->crtc_vsync_start - 1) |
7674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7675
7676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7679 * bits. */
7680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7681 (pipe == PIPE_B || pipe == PIPE_C))
7682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7683
7684 /* pipesrc controls the size that is scaled from, which should
7685 * always be the user's requested size.
7686 */
7687 I915_WRITE(PIPESRC(pipe),
7688 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7689 (intel_crtc->config->pipe_src_h - 1));
7690 }
7691
7692 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7693 struct intel_crtc_state *pipe_config)
7694 {
7695 struct drm_device *dev = crtc->base.dev;
7696 struct drm_i915_private *dev_priv = dev->dev_private;
7697 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7698 uint32_t tmp;
7699
7700 tmp = I915_READ(HTOTAL(cpu_transcoder));
7701 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7702 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7703 tmp = I915_READ(HBLANK(cpu_transcoder));
7704 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7705 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7706 tmp = I915_READ(HSYNC(cpu_transcoder));
7707 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7708 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7709
7710 tmp = I915_READ(VTOTAL(cpu_transcoder));
7711 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7712 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7713 tmp = I915_READ(VBLANK(cpu_transcoder));
7714 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7715 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7716 tmp = I915_READ(VSYNC(cpu_transcoder));
7717 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7718 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7719
7720 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7721 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7722 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7723 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7724 }
7725
7726 tmp = I915_READ(PIPESRC(crtc->pipe));
7727 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7728 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7729
7730 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7731 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7732 }
7733
7734 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7735 struct intel_crtc_state *pipe_config)
7736 {
7737 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7738 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7739 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7740 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7741
7742 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7743 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7744 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7745 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7746
7747 mode->flags = pipe_config->base.adjusted_mode.flags;
7748 mode->type = DRM_MODE_TYPE_DRIVER;
7749
7750 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7751 mode->flags |= pipe_config->base.adjusted_mode.flags;
7752
7753 mode->hsync = drm_mode_hsync(mode);
7754 mode->vrefresh = drm_mode_vrefresh(mode);
7755 drm_mode_set_name(mode);
7756 }
7757
7758 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7759 {
7760 struct drm_device *dev = intel_crtc->base.dev;
7761 struct drm_i915_private *dev_priv = dev->dev_private;
7762 uint32_t pipeconf;
7763
7764 pipeconf = 0;
7765
7766 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7767 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7768 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7769
7770 if (intel_crtc->config->double_wide)
7771 pipeconf |= PIPECONF_DOUBLE_WIDE;
7772
7773 /* only g4x and later have fancy bpc/dither controls */
7774 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7775 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7776 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7777 pipeconf |= PIPECONF_DITHER_EN |
7778 PIPECONF_DITHER_TYPE_SP;
7779
7780 switch (intel_crtc->config->pipe_bpp) {
7781 case 18:
7782 pipeconf |= PIPECONF_6BPC;
7783 break;
7784 case 24:
7785 pipeconf |= PIPECONF_8BPC;
7786 break;
7787 case 30:
7788 pipeconf |= PIPECONF_10BPC;
7789 break;
7790 default:
7791 /* Case prevented by intel_choose_pipe_bpp_dither. */
7792 BUG();
7793 }
7794 }
7795
7796 if (HAS_PIPE_CXSR(dev)) {
7797 if (intel_crtc->lowfreq_avail) {
7798 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7799 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7800 } else {
7801 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7802 }
7803 }
7804
7805 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7806 if (INTEL_INFO(dev)->gen < 4 ||
7807 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7809 else
7810 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7811 } else
7812 pipeconf |= PIPECONF_PROGRESSIVE;
7813
7814 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7815 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7816
7817 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7818 POSTING_READ(PIPECONF(intel_crtc->pipe));
7819 }
7820
7821 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7822 struct intel_crtc_state *crtc_state)
7823 {
7824 struct drm_device *dev = crtc->base.dev;
7825 struct drm_i915_private *dev_priv = dev->dev_private;
7826 int refclk, num_connectors = 0;
7827 intel_clock_t clock;
7828 bool ok;
7829 bool is_dsi = false;
7830 struct intel_encoder *encoder;
7831 const intel_limit_t *limit;
7832 struct drm_atomic_state *state = crtc_state->base.state;
7833 struct drm_connector *connector;
7834 struct drm_connector_state *connector_state;
7835 int i;
7836
7837 memset(&crtc_state->dpll_hw_state, 0,
7838 sizeof(crtc_state->dpll_hw_state));
7839
7840 for_each_connector_in_state(state, connector, connector_state, i) {
7841 if (connector_state->crtc != &crtc->base)
7842 continue;
7843
7844 encoder = to_intel_encoder(connector_state->best_encoder);
7845
7846 switch (encoder->type) {
7847 case INTEL_OUTPUT_DSI:
7848 is_dsi = true;
7849 break;
7850 default:
7851 break;
7852 }
7853
7854 num_connectors++;
7855 }
7856
7857 if (is_dsi)
7858 return 0;
7859
7860 if (!crtc_state->clock_set) {
7861 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7862
7863 /*
7864 * Returns a set of divisors for the desired target clock with
7865 * the given refclk, or FALSE. The returned values represent
7866 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7867 * 2) / p1 / p2.
7868 */
7869 limit = intel_limit(crtc_state, refclk);
7870 ok = dev_priv->display.find_dpll(limit, crtc_state,
7871 crtc_state->port_clock,
7872 refclk, NULL, &clock);
7873 if (!ok) {
7874 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7875 return -EINVAL;
7876 }
7877
7878 /* Compat-code for transition, will disappear. */
7879 crtc_state->dpll.n = clock.n;
7880 crtc_state->dpll.m1 = clock.m1;
7881 crtc_state->dpll.m2 = clock.m2;
7882 crtc_state->dpll.p1 = clock.p1;
7883 crtc_state->dpll.p2 = clock.p2;
7884 }
7885
7886 if (IS_GEN2(dev)) {
7887 i8xx_compute_dpll(crtc, crtc_state, NULL,
7888 num_connectors);
7889 } else if (IS_CHERRYVIEW(dev)) {
7890 chv_compute_dpll(crtc, crtc_state);
7891 } else if (IS_VALLEYVIEW(dev)) {
7892 vlv_compute_dpll(crtc, crtc_state);
7893 } else {
7894 i9xx_compute_dpll(crtc, crtc_state, NULL,
7895 num_connectors);
7896 }
7897
7898 return 0;
7899 }
7900
7901 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7902 struct intel_crtc_state *pipe_config)
7903 {
7904 struct drm_device *dev = crtc->base.dev;
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 uint32_t tmp;
7907
7908 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7909 return;
7910
7911 tmp = I915_READ(PFIT_CONTROL);
7912 if (!(tmp & PFIT_ENABLE))
7913 return;
7914
7915 /* Check whether the pfit is attached to our pipe. */
7916 if (INTEL_INFO(dev)->gen < 4) {
7917 if (crtc->pipe != PIPE_B)
7918 return;
7919 } else {
7920 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7921 return;
7922 }
7923
7924 pipe_config->gmch_pfit.control = tmp;
7925 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7926 if (INTEL_INFO(dev)->gen < 5)
7927 pipe_config->gmch_pfit.lvds_border_bits =
7928 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7929 }
7930
7931 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7932 struct intel_crtc_state *pipe_config)
7933 {
7934 struct drm_device *dev = crtc->base.dev;
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 int pipe = pipe_config->cpu_transcoder;
7937 intel_clock_t clock;
7938 u32 mdiv;
7939 int refclk = 100000;
7940
7941 /* In case of MIPI DPLL will not even be used */
7942 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7943 return;
7944
7945 mutex_lock(&dev_priv->sb_lock);
7946 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7947 mutex_unlock(&dev_priv->sb_lock);
7948
7949 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7950 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7951 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7952 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7953 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7954
7955 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7956 }
7957
7958 static void
7959 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7960 struct intel_initial_plane_config *plane_config)
7961 {
7962 struct drm_device *dev = crtc->base.dev;
7963 struct drm_i915_private *dev_priv = dev->dev_private;
7964 u32 val, base, offset;
7965 int pipe = crtc->pipe, plane = crtc->plane;
7966 int fourcc, pixel_format;
7967 unsigned int aligned_height;
7968 struct drm_framebuffer *fb;
7969 struct intel_framebuffer *intel_fb;
7970
7971 val = I915_READ(DSPCNTR(plane));
7972 if (!(val & DISPLAY_PLANE_ENABLE))
7973 return;
7974
7975 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7976 if (!intel_fb) {
7977 DRM_DEBUG_KMS("failed to alloc fb\n");
7978 return;
7979 }
7980
7981 fb = &intel_fb->base;
7982
7983 if (INTEL_INFO(dev)->gen >= 4) {
7984 if (val & DISPPLANE_TILED) {
7985 plane_config->tiling = I915_TILING_X;
7986 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7987 }
7988 }
7989
7990 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7991 fourcc = i9xx_format_to_fourcc(pixel_format);
7992 fb->pixel_format = fourcc;
7993 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7994
7995 if (INTEL_INFO(dev)->gen >= 4) {
7996 if (plane_config->tiling)
7997 offset = I915_READ(DSPTILEOFF(plane));
7998 else
7999 offset = I915_READ(DSPLINOFF(plane));
8000 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8001 } else {
8002 base = I915_READ(DSPADDR(plane));
8003 }
8004 plane_config->base = base;
8005
8006 val = I915_READ(PIPESRC(pipe));
8007 fb->width = ((val >> 16) & 0xfff) + 1;
8008 fb->height = ((val >> 0) & 0xfff) + 1;
8009
8010 val = I915_READ(DSPSTRIDE(pipe));
8011 fb->pitches[0] = val & 0xffffffc0;
8012
8013 aligned_height = intel_fb_align_height(dev, fb->height,
8014 fb->pixel_format,
8015 fb->modifier[0]);
8016
8017 plane_config->size = fb->pitches[0] * aligned_height;
8018
8019 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8020 pipe_name(pipe), plane, fb->width, fb->height,
8021 fb->bits_per_pixel, base, fb->pitches[0],
8022 plane_config->size);
8023
8024 plane_config->fb = intel_fb;
8025 }
8026
8027 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8028 struct intel_crtc_state *pipe_config)
8029 {
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 int pipe = pipe_config->cpu_transcoder;
8033 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8034 intel_clock_t clock;
8035 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8036 int refclk = 100000;
8037
8038 mutex_lock(&dev_priv->sb_lock);
8039 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8040 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8041 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8042 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8043 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8044 mutex_unlock(&dev_priv->sb_lock);
8045
8046 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8047 clock.m2 = (pll_dw0 & 0xff) << 22;
8048 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8049 clock.m2 |= pll_dw2 & 0x3fffff;
8050 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8051 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8052 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8053
8054 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8055 }
8056
8057 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8058 struct intel_crtc_state *pipe_config)
8059 {
8060 struct drm_device *dev = crtc->base.dev;
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062 uint32_t tmp;
8063
8064 if (!intel_display_power_is_enabled(dev_priv,
8065 POWER_DOMAIN_PIPE(crtc->pipe)))
8066 return false;
8067
8068 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8069 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8070
8071 tmp = I915_READ(PIPECONF(crtc->pipe));
8072 if (!(tmp & PIPECONF_ENABLE))
8073 return false;
8074
8075 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8076 switch (tmp & PIPECONF_BPC_MASK) {
8077 case PIPECONF_6BPC:
8078 pipe_config->pipe_bpp = 18;
8079 break;
8080 case PIPECONF_8BPC:
8081 pipe_config->pipe_bpp = 24;
8082 break;
8083 case PIPECONF_10BPC:
8084 pipe_config->pipe_bpp = 30;
8085 break;
8086 default:
8087 break;
8088 }
8089 }
8090
8091 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8092 pipe_config->limited_color_range = true;
8093
8094 if (INTEL_INFO(dev)->gen < 4)
8095 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8096
8097 intel_get_pipe_timings(crtc, pipe_config);
8098
8099 i9xx_get_pfit_config(crtc, pipe_config);
8100
8101 if (INTEL_INFO(dev)->gen >= 4) {
8102 tmp = I915_READ(DPLL_MD(crtc->pipe));
8103 pipe_config->pixel_multiplier =
8104 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8105 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8106 pipe_config->dpll_hw_state.dpll_md = tmp;
8107 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8108 tmp = I915_READ(DPLL(crtc->pipe));
8109 pipe_config->pixel_multiplier =
8110 ((tmp & SDVO_MULTIPLIER_MASK)
8111 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8112 } else {
8113 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8114 * port and will be fixed up in the encoder->get_config
8115 * function. */
8116 pipe_config->pixel_multiplier = 1;
8117 }
8118 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8119 if (!IS_VALLEYVIEW(dev)) {
8120 /*
8121 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8122 * on 830. Filter it out here so that we don't
8123 * report errors due to that.
8124 */
8125 if (IS_I830(dev))
8126 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8127
8128 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8129 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8130 } else {
8131 /* Mask out read-only status bits. */
8132 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8133 DPLL_PORTC_READY_MASK |
8134 DPLL_PORTB_READY_MASK);
8135 }
8136
8137 if (IS_CHERRYVIEW(dev))
8138 chv_crtc_clock_get(crtc, pipe_config);
8139 else if (IS_VALLEYVIEW(dev))
8140 vlv_crtc_clock_get(crtc, pipe_config);
8141 else
8142 i9xx_crtc_clock_get(crtc, pipe_config);
8143
8144 /*
8145 * Normally the dotclock is filled in by the encoder .get_config()
8146 * but in case the pipe is enabled w/o any ports we need a sane
8147 * default.
8148 */
8149 pipe_config->base.adjusted_mode.crtc_clock =
8150 pipe_config->port_clock / pipe_config->pixel_multiplier;
8151
8152 return true;
8153 }
8154
8155 static void ironlake_init_pch_refclk(struct drm_device *dev)
8156 {
8157 struct drm_i915_private *dev_priv = dev->dev_private;
8158 struct intel_encoder *encoder;
8159 u32 val, final;
8160 bool has_lvds = false;
8161 bool has_cpu_edp = false;
8162 bool has_panel = false;
8163 bool has_ck505 = false;
8164 bool can_ssc = false;
8165
8166 /* We need to take the global config into account */
8167 for_each_intel_encoder(dev, encoder) {
8168 switch (encoder->type) {
8169 case INTEL_OUTPUT_LVDS:
8170 has_panel = true;
8171 has_lvds = true;
8172 break;
8173 case INTEL_OUTPUT_EDP:
8174 has_panel = true;
8175 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8176 has_cpu_edp = true;
8177 break;
8178 default:
8179 break;
8180 }
8181 }
8182
8183 if (HAS_PCH_IBX(dev)) {
8184 has_ck505 = dev_priv->vbt.display_clock_mode;
8185 can_ssc = has_ck505;
8186 } else {
8187 has_ck505 = false;
8188 can_ssc = true;
8189 }
8190
8191 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8192 has_panel, has_lvds, has_ck505);
8193
8194 /* Ironlake: try to setup display ref clock before DPLL
8195 * enabling. This is only under driver's control after
8196 * PCH B stepping, previous chipset stepping should be
8197 * ignoring this setting.
8198 */
8199 val = I915_READ(PCH_DREF_CONTROL);
8200
8201 /* As we must carefully and slowly disable/enable each source in turn,
8202 * compute the final state we want first and check if we need to
8203 * make any changes at all.
8204 */
8205 final = val;
8206 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8207 if (has_ck505)
8208 final |= DREF_NONSPREAD_CK505_ENABLE;
8209 else
8210 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8211
8212 final &= ~DREF_SSC_SOURCE_MASK;
8213 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8214 final &= ~DREF_SSC1_ENABLE;
8215
8216 if (has_panel) {
8217 final |= DREF_SSC_SOURCE_ENABLE;
8218
8219 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8220 final |= DREF_SSC1_ENABLE;
8221
8222 if (has_cpu_edp) {
8223 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8224 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8225 else
8226 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8227 } else
8228 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8229 } else {
8230 final |= DREF_SSC_SOURCE_DISABLE;
8231 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8232 }
8233
8234 if (final == val)
8235 return;
8236
8237 /* Always enable nonspread source */
8238 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8239
8240 if (has_ck505)
8241 val |= DREF_NONSPREAD_CK505_ENABLE;
8242 else
8243 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8244
8245 if (has_panel) {
8246 val &= ~DREF_SSC_SOURCE_MASK;
8247 val |= DREF_SSC_SOURCE_ENABLE;
8248
8249 /* SSC must be turned on before enabling the CPU output */
8250 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8251 DRM_DEBUG_KMS("Using SSC on panel\n");
8252 val |= DREF_SSC1_ENABLE;
8253 } else
8254 val &= ~DREF_SSC1_ENABLE;
8255
8256 /* Get SSC going before enabling the outputs */
8257 I915_WRITE(PCH_DREF_CONTROL, val);
8258 POSTING_READ(PCH_DREF_CONTROL);
8259 udelay(200);
8260
8261 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8262
8263 /* Enable CPU source on CPU attached eDP */
8264 if (has_cpu_edp) {
8265 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8266 DRM_DEBUG_KMS("Using SSC on eDP\n");
8267 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8268 } else
8269 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8270 } else
8271 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8272
8273 I915_WRITE(PCH_DREF_CONTROL, val);
8274 POSTING_READ(PCH_DREF_CONTROL);
8275 udelay(200);
8276 } else {
8277 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8278
8279 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8280
8281 /* Turn off CPU output */
8282 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8283
8284 I915_WRITE(PCH_DREF_CONTROL, val);
8285 POSTING_READ(PCH_DREF_CONTROL);
8286 udelay(200);
8287
8288 /* Turn off the SSC source */
8289 val &= ~DREF_SSC_SOURCE_MASK;
8290 val |= DREF_SSC_SOURCE_DISABLE;
8291
8292 /* Turn off SSC1 */
8293 val &= ~DREF_SSC1_ENABLE;
8294
8295 I915_WRITE(PCH_DREF_CONTROL, val);
8296 POSTING_READ(PCH_DREF_CONTROL);
8297 udelay(200);
8298 }
8299
8300 BUG_ON(val != final);
8301 }
8302
8303 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8304 {
8305 uint32_t tmp;
8306
8307 tmp = I915_READ(SOUTH_CHICKEN2);
8308 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8309 I915_WRITE(SOUTH_CHICKEN2, tmp);
8310
8311 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8312 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8313 DRM_ERROR("FDI mPHY reset assert timeout\n");
8314
8315 tmp = I915_READ(SOUTH_CHICKEN2);
8316 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8317 I915_WRITE(SOUTH_CHICKEN2, tmp);
8318
8319 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8320 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8321 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8322 }
8323
8324 /* WaMPhyProgramming:hsw */
8325 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8326 {
8327 uint32_t tmp;
8328
8329 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8330 tmp &= ~(0xFF << 24);
8331 tmp |= (0x12 << 24);
8332 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8333
8334 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8335 tmp |= (1 << 11);
8336 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8337
8338 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8339 tmp |= (1 << 11);
8340 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8341
8342 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8343 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8344 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8345
8346 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8347 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8348 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8349
8350 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8351 tmp &= ~(7 << 13);
8352 tmp |= (5 << 13);
8353 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8354
8355 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8356 tmp &= ~(7 << 13);
8357 tmp |= (5 << 13);
8358 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8361 tmp &= ~0xFF;
8362 tmp |= 0x1C;
8363 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8366 tmp &= ~0xFF;
8367 tmp |= 0x1C;
8368 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8369
8370 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8371 tmp &= ~(0xFF << 16);
8372 tmp |= (0x1C << 16);
8373 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8374
8375 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8376 tmp &= ~(0xFF << 16);
8377 tmp |= (0x1C << 16);
8378 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8379
8380 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8381 tmp |= (1 << 27);
8382 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8383
8384 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8385 tmp |= (1 << 27);
8386 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8387
8388 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8389 tmp &= ~(0xF << 28);
8390 tmp |= (4 << 28);
8391 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8392
8393 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8394 tmp &= ~(0xF << 28);
8395 tmp |= (4 << 28);
8396 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8397 }
8398
8399 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8400 * Programming" based on the parameters passed:
8401 * - Sequence to enable CLKOUT_DP
8402 * - Sequence to enable CLKOUT_DP without spread
8403 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8404 */
8405 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8406 bool with_fdi)
8407 {
8408 struct drm_i915_private *dev_priv = dev->dev_private;
8409 uint32_t reg, tmp;
8410
8411 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8412 with_spread = true;
8413 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8414 with_fdi = false;
8415
8416 mutex_lock(&dev_priv->sb_lock);
8417
8418 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8419 tmp &= ~SBI_SSCCTL_DISABLE;
8420 tmp |= SBI_SSCCTL_PATHALT;
8421 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8422
8423 udelay(24);
8424
8425 if (with_spread) {
8426 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8427 tmp &= ~SBI_SSCCTL_PATHALT;
8428 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8429
8430 if (with_fdi) {
8431 lpt_reset_fdi_mphy(dev_priv);
8432 lpt_program_fdi_mphy(dev_priv);
8433 }
8434 }
8435
8436 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8437 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8438 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8439 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8440
8441 mutex_unlock(&dev_priv->sb_lock);
8442 }
8443
8444 /* Sequence to disable CLKOUT_DP */
8445 static void lpt_disable_clkout_dp(struct drm_device *dev)
8446 {
8447 struct drm_i915_private *dev_priv = dev->dev_private;
8448 uint32_t reg, tmp;
8449
8450 mutex_lock(&dev_priv->sb_lock);
8451
8452 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8453 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8454 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8455 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8456
8457 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8458 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8459 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8460 tmp |= SBI_SSCCTL_PATHALT;
8461 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8462 udelay(32);
8463 }
8464 tmp |= SBI_SSCCTL_DISABLE;
8465 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8466 }
8467
8468 mutex_unlock(&dev_priv->sb_lock);
8469 }
8470
8471 static void lpt_init_pch_refclk(struct drm_device *dev)
8472 {
8473 struct intel_encoder *encoder;
8474 bool has_vga = false;
8475
8476 for_each_intel_encoder(dev, encoder) {
8477 switch (encoder->type) {
8478 case INTEL_OUTPUT_ANALOG:
8479 has_vga = true;
8480 break;
8481 default:
8482 break;
8483 }
8484 }
8485
8486 if (has_vga)
8487 lpt_enable_clkout_dp(dev, true, true);
8488 else
8489 lpt_disable_clkout_dp(dev);
8490 }
8491
8492 /*
8493 * Initialize reference clocks when the driver loads
8494 */
8495 void intel_init_pch_refclk(struct drm_device *dev)
8496 {
8497 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8498 ironlake_init_pch_refclk(dev);
8499 else if (HAS_PCH_LPT(dev))
8500 lpt_init_pch_refclk(dev);
8501 }
8502
8503 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8504 {
8505 struct drm_device *dev = crtc_state->base.crtc->dev;
8506 struct drm_i915_private *dev_priv = dev->dev_private;
8507 struct drm_atomic_state *state = crtc_state->base.state;
8508 struct drm_connector *connector;
8509 struct drm_connector_state *connector_state;
8510 struct intel_encoder *encoder;
8511 int num_connectors = 0, i;
8512 bool is_lvds = false;
8513
8514 for_each_connector_in_state(state, connector, connector_state, i) {
8515 if (connector_state->crtc != crtc_state->base.crtc)
8516 continue;
8517
8518 encoder = to_intel_encoder(connector_state->best_encoder);
8519
8520 switch (encoder->type) {
8521 case INTEL_OUTPUT_LVDS:
8522 is_lvds = true;
8523 break;
8524 default:
8525 break;
8526 }
8527 num_connectors++;
8528 }
8529
8530 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8531 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8532 dev_priv->vbt.lvds_ssc_freq);
8533 return dev_priv->vbt.lvds_ssc_freq;
8534 }
8535
8536 return 120000;
8537 }
8538
8539 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8540 {
8541 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8543 int pipe = intel_crtc->pipe;
8544 uint32_t val;
8545
8546 val = 0;
8547
8548 switch (intel_crtc->config->pipe_bpp) {
8549 case 18:
8550 val |= PIPECONF_6BPC;
8551 break;
8552 case 24:
8553 val |= PIPECONF_8BPC;
8554 break;
8555 case 30:
8556 val |= PIPECONF_10BPC;
8557 break;
8558 case 36:
8559 val |= PIPECONF_12BPC;
8560 break;
8561 default:
8562 /* Case prevented by intel_choose_pipe_bpp_dither. */
8563 BUG();
8564 }
8565
8566 if (intel_crtc->config->dither)
8567 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8568
8569 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8570 val |= PIPECONF_INTERLACED_ILK;
8571 else
8572 val |= PIPECONF_PROGRESSIVE;
8573
8574 if (intel_crtc->config->limited_color_range)
8575 val |= PIPECONF_COLOR_RANGE_SELECT;
8576
8577 I915_WRITE(PIPECONF(pipe), val);
8578 POSTING_READ(PIPECONF(pipe));
8579 }
8580
8581 /*
8582 * Set up the pipe CSC unit.
8583 *
8584 * Currently only full range RGB to limited range RGB conversion
8585 * is supported, but eventually this should handle various
8586 * RGB<->YCbCr scenarios as well.
8587 */
8588 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8589 {
8590 struct drm_device *dev = crtc->dev;
8591 struct drm_i915_private *dev_priv = dev->dev_private;
8592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8593 int pipe = intel_crtc->pipe;
8594 uint16_t coeff = 0x7800; /* 1.0 */
8595
8596 /*
8597 * TODO: Check what kind of values actually come out of the pipe
8598 * with these coeff/postoff values and adjust to get the best
8599 * accuracy. Perhaps we even need to take the bpc value into
8600 * consideration.
8601 */
8602
8603 if (intel_crtc->config->limited_color_range)
8604 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8605
8606 /*
8607 * GY/GU and RY/RU should be the other way around according
8608 * to BSpec, but reality doesn't agree. Just set them up in
8609 * a way that results in the correct picture.
8610 */
8611 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8612 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8613
8614 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8615 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8616
8617 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8618 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8619
8620 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8621 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8622 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8623
8624 if (INTEL_INFO(dev)->gen > 6) {
8625 uint16_t postoff = 0;
8626
8627 if (intel_crtc->config->limited_color_range)
8628 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8629
8630 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8631 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8632 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8633
8634 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8635 } else {
8636 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8637
8638 if (intel_crtc->config->limited_color_range)
8639 mode |= CSC_BLACK_SCREEN_OFFSET;
8640
8641 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8642 }
8643 }
8644
8645 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8646 {
8647 struct drm_device *dev = crtc->dev;
8648 struct drm_i915_private *dev_priv = dev->dev_private;
8649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8650 enum pipe pipe = intel_crtc->pipe;
8651 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8652 uint32_t val;
8653
8654 val = 0;
8655
8656 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8657 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8658
8659 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8660 val |= PIPECONF_INTERLACED_ILK;
8661 else
8662 val |= PIPECONF_PROGRESSIVE;
8663
8664 I915_WRITE(PIPECONF(cpu_transcoder), val);
8665 POSTING_READ(PIPECONF(cpu_transcoder));
8666
8667 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8668 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8669
8670 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8671 val = 0;
8672
8673 switch (intel_crtc->config->pipe_bpp) {
8674 case 18:
8675 val |= PIPEMISC_DITHER_6_BPC;
8676 break;
8677 case 24:
8678 val |= PIPEMISC_DITHER_8_BPC;
8679 break;
8680 case 30:
8681 val |= PIPEMISC_DITHER_10_BPC;
8682 break;
8683 case 36:
8684 val |= PIPEMISC_DITHER_12_BPC;
8685 break;
8686 default:
8687 /* Case prevented by pipe_config_set_bpp. */
8688 BUG();
8689 }
8690
8691 if (intel_crtc->config->dither)
8692 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8693
8694 I915_WRITE(PIPEMISC(pipe), val);
8695 }
8696 }
8697
8698 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8699 struct intel_crtc_state *crtc_state,
8700 intel_clock_t *clock,
8701 bool *has_reduced_clock,
8702 intel_clock_t *reduced_clock)
8703 {
8704 struct drm_device *dev = crtc->dev;
8705 struct drm_i915_private *dev_priv = dev->dev_private;
8706 int refclk;
8707 const intel_limit_t *limit;
8708 bool ret;
8709
8710 refclk = ironlake_get_refclk(crtc_state);
8711
8712 /*
8713 * Returns a set of divisors for the desired target clock with the given
8714 * refclk, or FALSE. The returned values represent the clock equation:
8715 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8716 */
8717 limit = intel_limit(crtc_state, refclk);
8718 ret = dev_priv->display.find_dpll(limit, crtc_state,
8719 crtc_state->port_clock,
8720 refclk, NULL, clock);
8721 if (!ret)
8722 return false;
8723
8724 return true;
8725 }
8726
8727 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8728 {
8729 /*
8730 * Account for spread spectrum to avoid
8731 * oversubscribing the link. Max center spread
8732 * is 2.5%; use 5% for safety's sake.
8733 */
8734 u32 bps = target_clock * bpp * 21 / 20;
8735 return DIV_ROUND_UP(bps, link_bw * 8);
8736 }
8737
8738 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8739 {
8740 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8741 }
8742
8743 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8744 struct intel_crtc_state *crtc_state,
8745 u32 *fp,
8746 intel_clock_t *reduced_clock, u32 *fp2)
8747 {
8748 struct drm_crtc *crtc = &intel_crtc->base;
8749 struct drm_device *dev = crtc->dev;
8750 struct drm_i915_private *dev_priv = dev->dev_private;
8751 struct drm_atomic_state *state = crtc_state->base.state;
8752 struct drm_connector *connector;
8753 struct drm_connector_state *connector_state;
8754 struct intel_encoder *encoder;
8755 uint32_t dpll;
8756 int factor, num_connectors = 0, i;
8757 bool is_lvds = false, is_sdvo = false;
8758
8759 for_each_connector_in_state(state, connector, connector_state, i) {
8760 if (connector_state->crtc != crtc_state->base.crtc)
8761 continue;
8762
8763 encoder = to_intel_encoder(connector_state->best_encoder);
8764
8765 switch (encoder->type) {
8766 case INTEL_OUTPUT_LVDS:
8767 is_lvds = true;
8768 break;
8769 case INTEL_OUTPUT_SDVO:
8770 case INTEL_OUTPUT_HDMI:
8771 is_sdvo = true;
8772 break;
8773 default:
8774 break;
8775 }
8776
8777 num_connectors++;
8778 }
8779
8780 /* Enable autotuning of the PLL clock (if permissible) */
8781 factor = 21;
8782 if (is_lvds) {
8783 if ((intel_panel_use_ssc(dev_priv) &&
8784 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8785 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8786 factor = 25;
8787 } else if (crtc_state->sdvo_tv_clock)
8788 factor = 20;
8789
8790 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8791 *fp |= FP_CB_TUNE;
8792
8793 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8794 *fp2 |= FP_CB_TUNE;
8795
8796 dpll = 0;
8797
8798 if (is_lvds)
8799 dpll |= DPLLB_MODE_LVDS;
8800 else
8801 dpll |= DPLLB_MODE_DAC_SERIAL;
8802
8803 dpll |= (crtc_state->pixel_multiplier - 1)
8804 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8805
8806 if (is_sdvo)
8807 dpll |= DPLL_SDVO_HIGH_SPEED;
8808 if (crtc_state->has_dp_encoder)
8809 dpll |= DPLL_SDVO_HIGH_SPEED;
8810
8811 /* compute bitmask from p1 value */
8812 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8813 /* also FPA1 */
8814 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8815
8816 switch (crtc_state->dpll.p2) {
8817 case 5:
8818 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8819 break;
8820 case 7:
8821 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8822 break;
8823 case 10:
8824 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8825 break;
8826 case 14:
8827 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8828 break;
8829 }
8830
8831 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8832 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8833 else
8834 dpll |= PLL_REF_INPUT_DREFCLK;
8835
8836 return dpll | DPLL_VCO_ENABLE;
8837 }
8838
8839 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8840 struct intel_crtc_state *crtc_state)
8841 {
8842 struct drm_device *dev = crtc->base.dev;
8843 intel_clock_t clock, reduced_clock;
8844 u32 dpll = 0, fp = 0, fp2 = 0;
8845 bool ok, has_reduced_clock = false;
8846 bool is_lvds = false;
8847 struct intel_shared_dpll *pll;
8848
8849 memset(&crtc_state->dpll_hw_state, 0,
8850 sizeof(crtc_state->dpll_hw_state));
8851
8852 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8853
8854 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8855 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8856
8857 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8858 &has_reduced_clock, &reduced_clock);
8859 if (!ok && !crtc_state->clock_set) {
8860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8861 return -EINVAL;
8862 }
8863 /* Compat-code for transition, will disappear. */
8864 if (!crtc_state->clock_set) {
8865 crtc_state->dpll.n = clock.n;
8866 crtc_state->dpll.m1 = clock.m1;
8867 crtc_state->dpll.m2 = clock.m2;
8868 crtc_state->dpll.p1 = clock.p1;
8869 crtc_state->dpll.p2 = clock.p2;
8870 }
8871
8872 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8873 if (crtc_state->has_pch_encoder) {
8874 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8875 if (has_reduced_clock)
8876 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8877
8878 dpll = ironlake_compute_dpll(crtc, crtc_state,
8879 &fp, &reduced_clock,
8880 has_reduced_clock ? &fp2 : NULL);
8881
8882 crtc_state->dpll_hw_state.dpll = dpll;
8883 crtc_state->dpll_hw_state.fp0 = fp;
8884 if (has_reduced_clock)
8885 crtc_state->dpll_hw_state.fp1 = fp2;
8886 else
8887 crtc_state->dpll_hw_state.fp1 = fp;
8888
8889 pll = intel_get_shared_dpll(crtc, crtc_state);
8890 if (pll == NULL) {
8891 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8892 pipe_name(crtc->pipe));
8893 return -EINVAL;
8894 }
8895 }
8896
8897 if (is_lvds && has_reduced_clock)
8898 crtc->lowfreq_avail = true;
8899 else
8900 crtc->lowfreq_avail = false;
8901
8902 return 0;
8903 }
8904
8905 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8906 struct intel_link_m_n *m_n)
8907 {
8908 struct drm_device *dev = crtc->base.dev;
8909 struct drm_i915_private *dev_priv = dev->dev_private;
8910 enum pipe pipe = crtc->pipe;
8911
8912 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8913 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8914 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8915 & ~TU_SIZE_MASK;
8916 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8917 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8918 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8919 }
8920
8921 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8922 enum transcoder transcoder,
8923 struct intel_link_m_n *m_n,
8924 struct intel_link_m_n *m2_n2)
8925 {
8926 struct drm_device *dev = crtc->base.dev;
8927 struct drm_i915_private *dev_priv = dev->dev_private;
8928 enum pipe pipe = crtc->pipe;
8929
8930 if (INTEL_INFO(dev)->gen >= 5) {
8931 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8932 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8933 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8934 & ~TU_SIZE_MASK;
8935 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8936 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8937 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8938 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8939 * gen < 8) and if DRRS is supported (to make sure the
8940 * registers are not unnecessarily read).
8941 */
8942 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8943 crtc->config->has_drrs) {
8944 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8945 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8946 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8947 & ~TU_SIZE_MASK;
8948 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8949 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8950 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8951 }
8952 } else {
8953 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8954 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8955 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8956 & ~TU_SIZE_MASK;
8957 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8958 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8959 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8960 }
8961 }
8962
8963 void intel_dp_get_m_n(struct intel_crtc *crtc,
8964 struct intel_crtc_state *pipe_config)
8965 {
8966 if (pipe_config->has_pch_encoder)
8967 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8968 else
8969 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8970 &pipe_config->dp_m_n,
8971 &pipe_config->dp_m2_n2);
8972 }
8973
8974 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8975 struct intel_crtc_state *pipe_config)
8976 {
8977 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8978 &pipe_config->fdi_m_n, NULL);
8979 }
8980
8981 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8982 struct intel_crtc_state *pipe_config)
8983 {
8984 struct drm_device *dev = crtc->base.dev;
8985 struct drm_i915_private *dev_priv = dev->dev_private;
8986 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8987 uint32_t ps_ctrl = 0;
8988 int id = -1;
8989 int i;
8990
8991 /* find scaler attached to this pipe */
8992 for (i = 0; i < crtc->num_scalers; i++) {
8993 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8994 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8995 id = i;
8996 pipe_config->pch_pfit.enabled = true;
8997 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8998 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8999 break;
9000 }
9001 }
9002
9003 scaler_state->scaler_id = id;
9004 if (id >= 0) {
9005 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9006 } else {
9007 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9008 }
9009 }
9010
9011 static void
9012 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9013 struct intel_initial_plane_config *plane_config)
9014 {
9015 struct drm_device *dev = crtc->base.dev;
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017 u32 val, base, offset, stride_mult, tiling;
9018 int pipe = crtc->pipe;
9019 int fourcc, pixel_format;
9020 unsigned int aligned_height;
9021 struct drm_framebuffer *fb;
9022 struct intel_framebuffer *intel_fb;
9023
9024 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9025 if (!intel_fb) {
9026 DRM_DEBUG_KMS("failed to alloc fb\n");
9027 return;
9028 }
9029
9030 fb = &intel_fb->base;
9031
9032 val = I915_READ(PLANE_CTL(pipe, 0));
9033 if (!(val & PLANE_CTL_ENABLE))
9034 goto error;
9035
9036 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9037 fourcc = skl_format_to_fourcc(pixel_format,
9038 val & PLANE_CTL_ORDER_RGBX,
9039 val & PLANE_CTL_ALPHA_MASK);
9040 fb->pixel_format = fourcc;
9041 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9042
9043 tiling = val & PLANE_CTL_TILED_MASK;
9044 switch (tiling) {
9045 case PLANE_CTL_TILED_LINEAR:
9046 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9047 break;
9048 case PLANE_CTL_TILED_X:
9049 plane_config->tiling = I915_TILING_X;
9050 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9051 break;
9052 case PLANE_CTL_TILED_Y:
9053 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9054 break;
9055 case PLANE_CTL_TILED_YF:
9056 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9057 break;
9058 default:
9059 MISSING_CASE(tiling);
9060 goto error;
9061 }
9062
9063 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9064 plane_config->base = base;
9065
9066 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9067
9068 val = I915_READ(PLANE_SIZE(pipe, 0));
9069 fb->height = ((val >> 16) & 0xfff) + 1;
9070 fb->width = ((val >> 0) & 0x1fff) + 1;
9071
9072 val = I915_READ(PLANE_STRIDE(pipe, 0));
9073 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9074 fb->pixel_format);
9075 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9076
9077 aligned_height = intel_fb_align_height(dev, fb->height,
9078 fb->pixel_format,
9079 fb->modifier[0]);
9080
9081 plane_config->size = fb->pitches[0] * aligned_height;
9082
9083 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9084 pipe_name(pipe), fb->width, fb->height,
9085 fb->bits_per_pixel, base, fb->pitches[0],
9086 plane_config->size);
9087
9088 plane_config->fb = intel_fb;
9089 return;
9090
9091 error:
9092 kfree(fb);
9093 }
9094
9095 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9096 struct intel_crtc_state *pipe_config)
9097 {
9098 struct drm_device *dev = crtc->base.dev;
9099 struct drm_i915_private *dev_priv = dev->dev_private;
9100 uint32_t tmp;
9101
9102 tmp = I915_READ(PF_CTL(crtc->pipe));
9103
9104 if (tmp & PF_ENABLE) {
9105 pipe_config->pch_pfit.enabled = true;
9106 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9107 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9108
9109 /* We currently do not free assignements of panel fitters on
9110 * ivb/hsw (since we don't use the higher upscaling modes which
9111 * differentiates them) so just WARN about this case for now. */
9112 if (IS_GEN7(dev)) {
9113 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9114 PF_PIPE_SEL_IVB(crtc->pipe));
9115 }
9116 }
9117 }
9118
9119 static void
9120 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9121 struct intel_initial_plane_config *plane_config)
9122 {
9123 struct drm_device *dev = crtc->base.dev;
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 u32 val, base, offset;
9126 int pipe = crtc->pipe;
9127 int fourcc, pixel_format;
9128 unsigned int aligned_height;
9129 struct drm_framebuffer *fb;
9130 struct intel_framebuffer *intel_fb;
9131
9132 val = I915_READ(DSPCNTR(pipe));
9133 if (!(val & DISPLAY_PLANE_ENABLE))
9134 return;
9135
9136 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9137 if (!intel_fb) {
9138 DRM_DEBUG_KMS("failed to alloc fb\n");
9139 return;
9140 }
9141
9142 fb = &intel_fb->base;
9143
9144 if (INTEL_INFO(dev)->gen >= 4) {
9145 if (val & DISPPLANE_TILED) {
9146 plane_config->tiling = I915_TILING_X;
9147 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9148 }
9149 }
9150
9151 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9152 fourcc = i9xx_format_to_fourcc(pixel_format);
9153 fb->pixel_format = fourcc;
9154 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9155
9156 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9157 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9158 offset = I915_READ(DSPOFFSET(pipe));
9159 } else {
9160 if (plane_config->tiling)
9161 offset = I915_READ(DSPTILEOFF(pipe));
9162 else
9163 offset = I915_READ(DSPLINOFF(pipe));
9164 }
9165 plane_config->base = base;
9166
9167 val = I915_READ(PIPESRC(pipe));
9168 fb->width = ((val >> 16) & 0xfff) + 1;
9169 fb->height = ((val >> 0) & 0xfff) + 1;
9170
9171 val = I915_READ(DSPSTRIDE(pipe));
9172 fb->pitches[0] = val & 0xffffffc0;
9173
9174 aligned_height = intel_fb_align_height(dev, fb->height,
9175 fb->pixel_format,
9176 fb->modifier[0]);
9177
9178 plane_config->size = fb->pitches[0] * aligned_height;
9179
9180 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9181 pipe_name(pipe), fb->width, fb->height,
9182 fb->bits_per_pixel, base, fb->pitches[0],
9183 plane_config->size);
9184
9185 plane_config->fb = intel_fb;
9186 }
9187
9188 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9189 struct intel_crtc_state *pipe_config)
9190 {
9191 struct drm_device *dev = crtc->base.dev;
9192 struct drm_i915_private *dev_priv = dev->dev_private;
9193 uint32_t tmp;
9194
9195 if (!intel_display_power_is_enabled(dev_priv,
9196 POWER_DOMAIN_PIPE(crtc->pipe)))
9197 return false;
9198
9199 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9200 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9201
9202 tmp = I915_READ(PIPECONF(crtc->pipe));
9203 if (!(tmp & PIPECONF_ENABLE))
9204 return false;
9205
9206 switch (tmp & PIPECONF_BPC_MASK) {
9207 case PIPECONF_6BPC:
9208 pipe_config->pipe_bpp = 18;
9209 break;
9210 case PIPECONF_8BPC:
9211 pipe_config->pipe_bpp = 24;
9212 break;
9213 case PIPECONF_10BPC:
9214 pipe_config->pipe_bpp = 30;
9215 break;
9216 case PIPECONF_12BPC:
9217 pipe_config->pipe_bpp = 36;
9218 break;
9219 default:
9220 break;
9221 }
9222
9223 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9224 pipe_config->limited_color_range = true;
9225
9226 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9227 struct intel_shared_dpll *pll;
9228
9229 pipe_config->has_pch_encoder = true;
9230
9231 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9232 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9233 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9234
9235 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9236
9237 if (HAS_PCH_IBX(dev_priv->dev)) {
9238 pipe_config->shared_dpll =
9239 (enum intel_dpll_id) crtc->pipe;
9240 } else {
9241 tmp = I915_READ(PCH_DPLL_SEL);
9242 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9243 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9244 else
9245 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9246 }
9247
9248 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9249
9250 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9251 &pipe_config->dpll_hw_state));
9252
9253 tmp = pipe_config->dpll_hw_state.dpll;
9254 pipe_config->pixel_multiplier =
9255 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9256 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9257
9258 ironlake_pch_clock_get(crtc, pipe_config);
9259 } else {
9260 pipe_config->pixel_multiplier = 1;
9261 }
9262
9263 intel_get_pipe_timings(crtc, pipe_config);
9264
9265 ironlake_get_pfit_config(crtc, pipe_config);
9266
9267 return true;
9268 }
9269
9270 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9271 {
9272 struct drm_device *dev = dev_priv->dev;
9273 struct intel_crtc *crtc;
9274
9275 for_each_intel_crtc(dev, crtc)
9276 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9277 pipe_name(crtc->pipe));
9278
9279 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9280 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9281 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9282 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9283 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9284 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9285 "CPU PWM1 enabled\n");
9286 if (IS_HASWELL(dev))
9287 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9288 "CPU PWM2 enabled\n");
9289 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9290 "PCH PWM1 enabled\n");
9291 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9292 "Utility pin enabled\n");
9293 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9294
9295 /*
9296 * In theory we can still leave IRQs enabled, as long as only the HPD
9297 * interrupts remain enabled. We used to check for that, but since it's
9298 * gen-specific and since we only disable LCPLL after we fully disable
9299 * the interrupts, the check below should be enough.
9300 */
9301 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9302 }
9303
9304 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9305 {
9306 struct drm_device *dev = dev_priv->dev;
9307
9308 if (IS_HASWELL(dev))
9309 return I915_READ(D_COMP_HSW);
9310 else
9311 return I915_READ(D_COMP_BDW);
9312 }
9313
9314 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9315 {
9316 struct drm_device *dev = dev_priv->dev;
9317
9318 if (IS_HASWELL(dev)) {
9319 mutex_lock(&dev_priv->rps.hw_lock);
9320 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9321 val))
9322 DRM_ERROR("Failed to write to D_COMP\n");
9323 mutex_unlock(&dev_priv->rps.hw_lock);
9324 } else {
9325 I915_WRITE(D_COMP_BDW, val);
9326 POSTING_READ(D_COMP_BDW);
9327 }
9328 }
9329
9330 /*
9331 * This function implements pieces of two sequences from BSpec:
9332 * - Sequence for display software to disable LCPLL
9333 * - Sequence for display software to allow package C8+
9334 * The steps implemented here are just the steps that actually touch the LCPLL
9335 * register. Callers should take care of disabling all the display engine
9336 * functions, doing the mode unset, fixing interrupts, etc.
9337 */
9338 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9339 bool switch_to_fclk, bool allow_power_down)
9340 {
9341 uint32_t val;
9342
9343 assert_can_disable_lcpll(dev_priv);
9344
9345 val = I915_READ(LCPLL_CTL);
9346
9347 if (switch_to_fclk) {
9348 val |= LCPLL_CD_SOURCE_FCLK;
9349 I915_WRITE(LCPLL_CTL, val);
9350
9351 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9352 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9353 DRM_ERROR("Switching to FCLK failed\n");
9354
9355 val = I915_READ(LCPLL_CTL);
9356 }
9357
9358 val |= LCPLL_PLL_DISABLE;
9359 I915_WRITE(LCPLL_CTL, val);
9360 POSTING_READ(LCPLL_CTL);
9361
9362 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9363 DRM_ERROR("LCPLL still locked\n");
9364
9365 val = hsw_read_dcomp(dev_priv);
9366 val |= D_COMP_COMP_DISABLE;
9367 hsw_write_dcomp(dev_priv, val);
9368 ndelay(100);
9369
9370 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9371 1))
9372 DRM_ERROR("D_COMP RCOMP still in progress\n");
9373
9374 if (allow_power_down) {
9375 val = I915_READ(LCPLL_CTL);
9376 val |= LCPLL_POWER_DOWN_ALLOW;
9377 I915_WRITE(LCPLL_CTL, val);
9378 POSTING_READ(LCPLL_CTL);
9379 }
9380 }
9381
9382 /*
9383 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9384 * source.
9385 */
9386 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9387 {
9388 uint32_t val;
9389
9390 val = I915_READ(LCPLL_CTL);
9391
9392 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9393 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9394 return;
9395
9396 /*
9397 * Make sure we're not on PC8 state before disabling PC8, otherwise
9398 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9399 */
9400 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9401
9402 if (val & LCPLL_POWER_DOWN_ALLOW) {
9403 val &= ~LCPLL_POWER_DOWN_ALLOW;
9404 I915_WRITE(LCPLL_CTL, val);
9405 POSTING_READ(LCPLL_CTL);
9406 }
9407
9408 val = hsw_read_dcomp(dev_priv);
9409 val |= D_COMP_COMP_FORCE;
9410 val &= ~D_COMP_COMP_DISABLE;
9411 hsw_write_dcomp(dev_priv, val);
9412
9413 val = I915_READ(LCPLL_CTL);
9414 val &= ~LCPLL_PLL_DISABLE;
9415 I915_WRITE(LCPLL_CTL, val);
9416
9417 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9418 DRM_ERROR("LCPLL not locked yet\n");
9419
9420 if (val & LCPLL_CD_SOURCE_FCLK) {
9421 val = I915_READ(LCPLL_CTL);
9422 val &= ~LCPLL_CD_SOURCE_FCLK;
9423 I915_WRITE(LCPLL_CTL, val);
9424
9425 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9426 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9427 DRM_ERROR("Switching back to LCPLL failed\n");
9428 }
9429
9430 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9431 intel_update_cdclk(dev_priv->dev);
9432 }
9433
9434 /*
9435 * Package states C8 and deeper are really deep PC states that can only be
9436 * reached when all the devices on the system allow it, so even if the graphics
9437 * device allows PC8+, it doesn't mean the system will actually get to these
9438 * states. Our driver only allows PC8+ when going into runtime PM.
9439 *
9440 * The requirements for PC8+ are that all the outputs are disabled, the power
9441 * well is disabled and most interrupts are disabled, and these are also
9442 * requirements for runtime PM. When these conditions are met, we manually do
9443 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9444 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9445 * hang the machine.
9446 *
9447 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9448 * the state of some registers, so when we come back from PC8+ we need to
9449 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9450 * need to take care of the registers kept by RC6. Notice that this happens even
9451 * if we don't put the device in PCI D3 state (which is what currently happens
9452 * because of the runtime PM support).
9453 *
9454 * For more, read "Display Sequences for Package C8" on the hardware
9455 * documentation.
9456 */
9457 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9458 {
9459 struct drm_device *dev = dev_priv->dev;
9460 uint32_t val;
9461
9462 DRM_DEBUG_KMS("Enabling package C8+\n");
9463
9464 if (HAS_PCH_LPT_LP(dev)) {
9465 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9466 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9467 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9468 }
9469
9470 lpt_disable_clkout_dp(dev);
9471 hsw_disable_lcpll(dev_priv, true, true);
9472 }
9473
9474 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9475 {
9476 struct drm_device *dev = dev_priv->dev;
9477 uint32_t val;
9478
9479 DRM_DEBUG_KMS("Disabling package C8+\n");
9480
9481 hsw_restore_lcpll(dev_priv);
9482 lpt_init_pch_refclk(dev);
9483
9484 if (HAS_PCH_LPT_LP(dev)) {
9485 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9486 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9487 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9488 }
9489
9490 intel_prepare_ddi(dev);
9491 }
9492
9493 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9494 {
9495 struct drm_device *dev = old_state->dev;
9496 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9497
9498 broxton_set_cdclk(dev, req_cdclk);
9499 }
9500
9501 /* compute the max rate for new configuration */
9502 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9503 {
9504 struct intel_crtc *intel_crtc;
9505 struct intel_crtc_state *crtc_state;
9506 int max_pixel_rate = 0;
9507
9508 for_each_intel_crtc(state->dev, intel_crtc) {
9509 int pixel_rate;
9510
9511 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9512 if (IS_ERR(crtc_state))
9513 return PTR_ERR(crtc_state);
9514
9515 if (!crtc_state->base.enable)
9516 continue;
9517
9518 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9519
9520 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9521 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9522 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9523
9524 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9525 }
9526
9527 return max_pixel_rate;
9528 }
9529
9530 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9531 {
9532 struct drm_i915_private *dev_priv = dev->dev_private;
9533 uint32_t val, data;
9534 int ret;
9535
9536 if (WARN((I915_READ(LCPLL_CTL) &
9537 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9538 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9539 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9540 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9541 "trying to change cdclk frequency with cdclk not enabled\n"))
9542 return;
9543
9544 mutex_lock(&dev_priv->rps.hw_lock);
9545 ret = sandybridge_pcode_write(dev_priv,
9546 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9547 mutex_unlock(&dev_priv->rps.hw_lock);
9548 if (ret) {
9549 DRM_ERROR("failed to inform pcode about cdclk change\n");
9550 return;
9551 }
9552
9553 val = I915_READ(LCPLL_CTL);
9554 val |= LCPLL_CD_SOURCE_FCLK;
9555 I915_WRITE(LCPLL_CTL, val);
9556
9557 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9558 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9559 DRM_ERROR("Switching to FCLK failed\n");
9560
9561 val = I915_READ(LCPLL_CTL);
9562 val &= ~LCPLL_CLK_FREQ_MASK;
9563
9564 switch (cdclk) {
9565 case 450000:
9566 val |= LCPLL_CLK_FREQ_450;
9567 data = 0;
9568 break;
9569 case 540000:
9570 val |= LCPLL_CLK_FREQ_54O_BDW;
9571 data = 1;
9572 break;
9573 case 337500:
9574 val |= LCPLL_CLK_FREQ_337_5_BDW;
9575 data = 2;
9576 break;
9577 case 675000:
9578 val |= LCPLL_CLK_FREQ_675_BDW;
9579 data = 3;
9580 break;
9581 default:
9582 WARN(1, "invalid cdclk frequency\n");
9583 return;
9584 }
9585
9586 I915_WRITE(LCPLL_CTL, val);
9587
9588 val = I915_READ(LCPLL_CTL);
9589 val &= ~LCPLL_CD_SOURCE_FCLK;
9590 I915_WRITE(LCPLL_CTL, val);
9591
9592 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9593 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9594 DRM_ERROR("Switching back to LCPLL failed\n");
9595
9596 mutex_lock(&dev_priv->rps.hw_lock);
9597 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9598 mutex_unlock(&dev_priv->rps.hw_lock);
9599
9600 intel_update_cdclk(dev);
9601
9602 WARN(cdclk != dev_priv->cdclk_freq,
9603 "cdclk requested %d kHz but got %d kHz\n",
9604 cdclk, dev_priv->cdclk_freq);
9605 }
9606
9607 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9608 {
9609 struct drm_i915_private *dev_priv = to_i915(state->dev);
9610 int max_pixclk = ilk_max_pixel_rate(state);
9611 int cdclk;
9612
9613 /*
9614 * FIXME should also account for plane ratio
9615 * once 64bpp pixel formats are supported.
9616 */
9617 if (max_pixclk > 540000)
9618 cdclk = 675000;
9619 else if (max_pixclk > 450000)
9620 cdclk = 540000;
9621 else if (max_pixclk > 337500)
9622 cdclk = 450000;
9623 else
9624 cdclk = 337500;
9625
9626 /*
9627 * FIXME move the cdclk caclulation to
9628 * compute_config() so we can fail gracegully.
9629 */
9630 if (cdclk > dev_priv->max_cdclk_freq) {
9631 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9632 cdclk, dev_priv->max_cdclk_freq);
9633 cdclk = dev_priv->max_cdclk_freq;
9634 }
9635
9636 to_intel_atomic_state(state)->cdclk = cdclk;
9637
9638 return 0;
9639 }
9640
9641 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9642 {
9643 struct drm_device *dev = old_state->dev;
9644 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9645
9646 broadwell_set_cdclk(dev, req_cdclk);
9647 }
9648
9649 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9650 struct intel_crtc_state *crtc_state)
9651 {
9652 if (!intel_ddi_pll_select(crtc, crtc_state))
9653 return -EINVAL;
9654
9655 crtc->lowfreq_avail = false;
9656
9657 return 0;
9658 }
9659
9660 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9661 enum port port,
9662 struct intel_crtc_state *pipe_config)
9663 {
9664 switch (port) {
9665 case PORT_A:
9666 pipe_config->ddi_pll_sel = SKL_DPLL0;
9667 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9668 break;
9669 case PORT_B:
9670 pipe_config->ddi_pll_sel = SKL_DPLL1;
9671 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9672 break;
9673 case PORT_C:
9674 pipe_config->ddi_pll_sel = SKL_DPLL2;
9675 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9676 break;
9677 default:
9678 DRM_ERROR("Incorrect port type\n");
9679 }
9680 }
9681
9682 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9683 enum port port,
9684 struct intel_crtc_state *pipe_config)
9685 {
9686 u32 temp, dpll_ctl1;
9687
9688 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9689 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9690
9691 switch (pipe_config->ddi_pll_sel) {
9692 case SKL_DPLL0:
9693 /*
9694 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9695 * of the shared DPLL framework and thus needs to be read out
9696 * separately
9697 */
9698 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9699 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9700 break;
9701 case SKL_DPLL1:
9702 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9703 break;
9704 case SKL_DPLL2:
9705 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9706 break;
9707 case SKL_DPLL3:
9708 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9709 break;
9710 }
9711 }
9712
9713 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9714 enum port port,
9715 struct intel_crtc_state *pipe_config)
9716 {
9717 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9718
9719 switch (pipe_config->ddi_pll_sel) {
9720 case PORT_CLK_SEL_WRPLL1:
9721 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9722 break;
9723 case PORT_CLK_SEL_WRPLL2:
9724 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9725 break;
9726 }
9727 }
9728
9729 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9730 struct intel_crtc_state *pipe_config)
9731 {
9732 struct drm_device *dev = crtc->base.dev;
9733 struct drm_i915_private *dev_priv = dev->dev_private;
9734 struct intel_shared_dpll *pll;
9735 enum port port;
9736 uint32_t tmp;
9737
9738 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9739
9740 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9741
9742 if (IS_SKYLAKE(dev))
9743 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9744 else if (IS_BROXTON(dev))
9745 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9746 else
9747 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9748
9749 if (pipe_config->shared_dpll >= 0) {
9750 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9751
9752 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9753 &pipe_config->dpll_hw_state));
9754 }
9755
9756 /*
9757 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9758 * DDI E. So just check whether this pipe is wired to DDI E and whether
9759 * the PCH transcoder is on.
9760 */
9761 if (INTEL_INFO(dev)->gen < 9 &&
9762 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9763 pipe_config->has_pch_encoder = true;
9764
9765 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9766 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9767 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9768
9769 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9770 }
9771 }
9772
9773 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9774 struct intel_crtc_state *pipe_config)
9775 {
9776 struct drm_device *dev = crtc->base.dev;
9777 struct drm_i915_private *dev_priv = dev->dev_private;
9778 enum intel_display_power_domain pfit_domain;
9779 uint32_t tmp;
9780
9781 if (!intel_display_power_is_enabled(dev_priv,
9782 POWER_DOMAIN_PIPE(crtc->pipe)))
9783 return false;
9784
9785 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9786 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9787
9788 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9789 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9790 enum pipe trans_edp_pipe;
9791 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9792 default:
9793 WARN(1, "unknown pipe linked to edp transcoder\n");
9794 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9795 case TRANS_DDI_EDP_INPUT_A_ON:
9796 trans_edp_pipe = PIPE_A;
9797 break;
9798 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9799 trans_edp_pipe = PIPE_B;
9800 break;
9801 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9802 trans_edp_pipe = PIPE_C;
9803 break;
9804 }
9805
9806 if (trans_edp_pipe == crtc->pipe)
9807 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9808 }
9809
9810 if (!intel_display_power_is_enabled(dev_priv,
9811 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9812 return false;
9813
9814 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9815 if (!(tmp & PIPECONF_ENABLE))
9816 return false;
9817
9818 haswell_get_ddi_port_state(crtc, pipe_config);
9819
9820 intel_get_pipe_timings(crtc, pipe_config);
9821
9822 if (INTEL_INFO(dev)->gen >= 9) {
9823 skl_init_scalers(dev, crtc, pipe_config);
9824 }
9825
9826 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9827
9828 if (INTEL_INFO(dev)->gen >= 9) {
9829 pipe_config->scaler_state.scaler_id = -1;
9830 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9831 }
9832
9833 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9834 if (INTEL_INFO(dev)->gen >= 9)
9835 skylake_get_pfit_config(crtc, pipe_config);
9836 else
9837 ironlake_get_pfit_config(crtc, pipe_config);
9838 }
9839
9840 if (IS_HASWELL(dev))
9841 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9842 (I915_READ(IPS_CTL) & IPS_ENABLE);
9843
9844 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9845 pipe_config->pixel_multiplier =
9846 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9847 } else {
9848 pipe_config->pixel_multiplier = 1;
9849 }
9850
9851 return true;
9852 }
9853
9854 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9855 {
9856 struct drm_device *dev = crtc->dev;
9857 struct drm_i915_private *dev_priv = dev->dev_private;
9858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9859 uint32_t cntl = 0, size = 0;
9860
9861 if (base) {
9862 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9863 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9864 unsigned int stride = roundup_pow_of_two(width) * 4;
9865
9866 switch (stride) {
9867 default:
9868 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9869 width, stride);
9870 stride = 256;
9871 /* fallthrough */
9872 case 256:
9873 case 512:
9874 case 1024:
9875 case 2048:
9876 break;
9877 }
9878
9879 cntl |= CURSOR_ENABLE |
9880 CURSOR_GAMMA_ENABLE |
9881 CURSOR_FORMAT_ARGB |
9882 CURSOR_STRIDE(stride);
9883
9884 size = (height << 12) | width;
9885 }
9886
9887 if (intel_crtc->cursor_cntl != 0 &&
9888 (intel_crtc->cursor_base != base ||
9889 intel_crtc->cursor_size != size ||
9890 intel_crtc->cursor_cntl != cntl)) {
9891 /* On these chipsets we can only modify the base/size/stride
9892 * whilst the cursor is disabled.
9893 */
9894 I915_WRITE(CURCNTR(PIPE_A), 0);
9895 POSTING_READ(CURCNTR(PIPE_A));
9896 intel_crtc->cursor_cntl = 0;
9897 }
9898
9899 if (intel_crtc->cursor_base != base) {
9900 I915_WRITE(CURBASE(PIPE_A), base);
9901 intel_crtc->cursor_base = base;
9902 }
9903
9904 if (intel_crtc->cursor_size != size) {
9905 I915_WRITE(CURSIZE, size);
9906 intel_crtc->cursor_size = size;
9907 }
9908
9909 if (intel_crtc->cursor_cntl != cntl) {
9910 I915_WRITE(CURCNTR(PIPE_A), cntl);
9911 POSTING_READ(CURCNTR(PIPE_A));
9912 intel_crtc->cursor_cntl = cntl;
9913 }
9914 }
9915
9916 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9917 {
9918 struct drm_device *dev = crtc->dev;
9919 struct drm_i915_private *dev_priv = dev->dev_private;
9920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9921 int pipe = intel_crtc->pipe;
9922 uint32_t cntl;
9923
9924 cntl = 0;
9925 if (base) {
9926 cntl = MCURSOR_GAMMA_ENABLE;
9927 switch (intel_crtc->base.cursor->state->crtc_w) {
9928 case 64:
9929 cntl |= CURSOR_MODE_64_ARGB_AX;
9930 break;
9931 case 128:
9932 cntl |= CURSOR_MODE_128_ARGB_AX;
9933 break;
9934 case 256:
9935 cntl |= CURSOR_MODE_256_ARGB_AX;
9936 break;
9937 default:
9938 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9939 return;
9940 }
9941 cntl |= pipe << 28; /* Connect to correct pipe */
9942
9943 if (HAS_DDI(dev))
9944 cntl |= CURSOR_PIPE_CSC_ENABLE;
9945 }
9946
9947 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9948 cntl |= CURSOR_ROTATE_180;
9949
9950 if (intel_crtc->cursor_cntl != cntl) {
9951 I915_WRITE(CURCNTR(pipe), cntl);
9952 POSTING_READ(CURCNTR(pipe));
9953 intel_crtc->cursor_cntl = cntl;
9954 }
9955
9956 /* and commit changes on next vblank */
9957 I915_WRITE(CURBASE(pipe), base);
9958 POSTING_READ(CURBASE(pipe));
9959
9960 intel_crtc->cursor_base = base;
9961 }
9962
9963 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9964 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9965 bool on)
9966 {
9967 struct drm_device *dev = crtc->dev;
9968 struct drm_i915_private *dev_priv = dev->dev_private;
9969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9970 int pipe = intel_crtc->pipe;
9971 struct drm_plane_state *cursor_state = crtc->cursor->state;
9972 int x = cursor_state->crtc_x;
9973 int y = cursor_state->crtc_y;
9974 u32 base = 0, pos = 0;
9975
9976 if (on)
9977 base = intel_crtc->cursor_addr;
9978
9979 if (x >= intel_crtc->config->pipe_src_w)
9980 base = 0;
9981
9982 if (y >= intel_crtc->config->pipe_src_h)
9983 base = 0;
9984
9985 if (x < 0) {
9986 if (x + cursor_state->crtc_w <= 0)
9987 base = 0;
9988
9989 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9990 x = -x;
9991 }
9992 pos |= x << CURSOR_X_SHIFT;
9993
9994 if (y < 0) {
9995 if (y + cursor_state->crtc_h <= 0)
9996 base = 0;
9997
9998 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9999 y = -y;
10000 }
10001 pos |= y << CURSOR_Y_SHIFT;
10002
10003 if (base == 0 && intel_crtc->cursor_base == 0)
10004 return;
10005
10006 I915_WRITE(CURPOS(pipe), pos);
10007
10008 /* ILK+ do this automagically */
10009 if (HAS_GMCH_DISPLAY(dev) &&
10010 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10011 base += (cursor_state->crtc_h *
10012 cursor_state->crtc_w - 1) * 4;
10013 }
10014
10015 if (IS_845G(dev) || IS_I865G(dev))
10016 i845_update_cursor(crtc, base);
10017 else
10018 i9xx_update_cursor(crtc, base);
10019 }
10020
10021 static bool cursor_size_ok(struct drm_device *dev,
10022 uint32_t width, uint32_t height)
10023 {
10024 if (width == 0 || height == 0)
10025 return false;
10026
10027 /*
10028 * 845g/865g are special in that they are only limited by
10029 * the width of their cursors, the height is arbitrary up to
10030 * the precision of the register. Everything else requires
10031 * square cursors, limited to a few power-of-two sizes.
10032 */
10033 if (IS_845G(dev) || IS_I865G(dev)) {
10034 if ((width & 63) != 0)
10035 return false;
10036
10037 if (width > (IS_845G(dev) ? 64 : 512))
10038 return false;
10039
10040 if (height > 1023)
10041 return false;
10042 } else {
10043 switch (width | height) {
10044 case 256:
10045 case 128:
10046 if (IS_GEN2(dev))
10047 return false;
10048 case 64:
10049 break;
10050 default:
10051 return false;
10052 }
10053 }
10054
10055 return true;
10056 }
10057
10058 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10059 u16 *blue, uint32_t start, uint32_t size)
10060 {
10061 int end = (start + size > 256) ? 256 : start + size, i;
10062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063
10064 for (i = start; i < end; i++) {
10065 intel_crtc->lut_r[i] = red[i] >> 8;
10066 intel_crtc->lut_g[i] = green[i] >> 8;
10067 intel_crtc->lut_b[i] = blue[i] >> 8;
10068 }
10069
10070 intel_crtc_load_lut(crtc);
10071 }
10072
10073 /* VESA 640x480x72Hz mode to set on the pipe */
10074 static struct drm_display_mode load_detect_mode = {
10075 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10076 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10077 };
10078
10079 struct drm_framebuffer *
10080 __intel_framebuffer_create(struct drm_device *dev,
10081 struct drm_mode_fb_cmd2 *mode_cmd,
10082 struct drm_i915_gem_object *obj)
10083 {
10084 struct intel_framebuffer *intel_fb;
10085 int ret;
10086
10087 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10088 if (!intel_fb) {
10089 drm_gem_object_unreference(&obj->base);
10090 return ERR_PTR(-ENOMEM);
10091 }
10092
10093 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10094 if (ret)
10095 goto err;
10096
10097 return &intel_fb->base;
10098 err:
10099 drm_gem_object_unreference(&obj->base);
10100 kfree(intel_fb);
10101
10102 return ERR_PTR(ret);
10103 }
10104
10105 static struct drm_framebuffer *
10106 intel_framebuffer_create(struct drm_device *dev,
10107 struct drm_mode_fb_cmd2 *mode_cmd,
10108 struct drm_i915_gem_object *obj)
10109 {
10110 struct drm_framebuffer *fb;
10111 int ret;
10112
10113 ret = i915_mutex_lock_interruptible(dev);
10114 if (ret)
10115 return ERR_PTR(ret);
10116 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10117 mutex_unlock(&dev->struct_mutex);
10118
10119 return fb;
10120 }
10121
10122 static u32
10123 intel_framebuffer_pitch_for_width(int width, int bpp)
10124 {
10125 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10126 return ALIGN(pitch, 64);
10127 }
10128
10129 static u32
10130 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10131 {
10132 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10133 return PAGE_ALIGN(pitch * mode->vdisplay);
10134 }
10135
10136 static struct drm_framebuffer *
10137 intel_framebuffer_create_for_mode(struct drm_device *dev,
10138 struct drm_display_mode *mode,
10139 int depth, int bpp)
10140 {
10141 struct drm_i915_gem_object *obj;
10142 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10143
10144 obj = i915_gem_alloc_object(dev,
10145 intel_framebuffer_size_for_mode(mode, bpp));
10146 if (obj == NULL)
10147 return ERR_PTR(-ENOMEM);
10148
10149 mode_cmd.width = mode->hdisplay;
10150 mode_cmd.height = mode->vdisplay;
10151 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10152 bpp);
10153 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10154
10155 return intel_framebuffer_create(dev, &mode_cmd, obj);
10156 }
10157
10158 static struct drm_framebuffer *
10159 mode_fits_in_fbdev(struct drm_device *dev,
10160 struct drm_display_mode *mode)
10161 {
10162 #ifdef CONFIG_DRM_FBDEV_EMULATION
10163 struct drm_i915_private *dev_priv = dev->dev_private;
10164 struct drm_i915_gem_object *obj;
10165 struct drm_framebuffer *fb;
10166
10167 if (!dev_priv->fbdev)
10168 return NULL;
10169
10170 if (!dev_priv->fbdev->fb)
10171 return NULL;
10172
10173 obj = dev_priv->fbdev->fb->obj;
10174 BUG_ON(!obj);
10175
10176 fb = &dev_priv->fbdev->fb->base;
10177 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10178 fb->bits_per_pixel))
10179 return NULL;
10180
10181 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10182 return NULL;
10183
10184 return fb;
10185 #else
10186 return NULL;
10187 #endif
10188 }
10189
10190 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10191 struct drm_crtc *crtc,
10192 struct drm_display_mode *mode,
10193 struct drm_framebuffer *fb,
10194 int x, int y)
10195 {
10196 struct drm_plane_state *plane_state;
10197 int hdisplay, vdisplay;
10198 int ret;
10199
10200 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10201 if (IS_ERR(plane_state))
10202 return PTR_ERR(plane_state);
10203
10204 if (mode)
10205 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10206 else
10207 hdisplay = vdisplay = 0;
10208
10209 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10210 if (ret)
10211 return ret;
10212 drm_atomic_set_fb_for_plane(plane_state, fb);
10213 plane_state->crtc_x = 0;
10214 plane_state->crtc_y = 0;
10215 plane_state->crtc_w = hdisplay;
10216 plane_state->crtc_h = vdisplay;
10217 plane_state->src_x = x << 16;
10218 plane_state->src_y = y << 16;
10219 plane_state->src_w = hdisplay << 16;
10220 plane_state->src_h = vdisplay << 16;
10221
10222 return 0;
10223 }
10224
10225 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10226 struct drm_display_mode *mode,
10227 struct intel_load_detect_pipe *old,
10228 struct drm_modeset_acquire_ctx *ctx)
10229 {
10230 struct intel_crtc *intel_crtc;
10231 struct intel_encoder *intel_encoder =
10232 intel_attached_encoder(connector);
10233 struct drm_crtc *possible_crtc;
10234 struct drm_encoder *encoder = &intel_encoder->base;
10235 struct drm_crtc *crtc = NULL;
10236 struct drm_device *dev = encoder->dev;
10237 struct drm_framebuffer *fb;
10238 struct drm_mode_config *config = &dev->mode_config;
10239 struct drm_atomic_state *state = NULL;
10240 struct drm_connector_state *connector_state;
10241 struct intel_crtc_state *crtc_state;
10242 int ret, i = -1;
10243
10244 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10245 connector->base.id, connector->name,
10246 encoder->base.id, encoder->name);
10247
10248 retry:
10249 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10250 if (ret)
10251 goto fail;
10252
10253 /*
10254 * Algorithm gets a little messy:
10255 *
10256 * - if the connector already has an assigned crtc, use it (but make
10257 * sure it's on first)
10258 *
10259 * - try to find the first unused crtc that can drive this connector,
10260 * and use that if we find one
10261 */
10262
10263 /* See if we already have a CRTC for this connector */
10264 if (encoder->crtc) {
10265 crtc = encoder->crtc;
10266
10267 ret = drm_modeset_lock(&crtc->mutex, ctx);
10268 if (ret)
10269 goto fail;
10270 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10271 if (ret)
10272 goto fail;
10273
10274 old->dpms_mode = connector->dpms;
10275 old->load_detect_temp = false;
10276
10277 /* Make sure the crtc and connector are running */
10278 if (connector->dpms != DRM_MODE_DPMS_ON)
10279 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10280
10281 return true;
10282 }
10283
10284 /* Find an unused one (if possible) */
10285 for_each_crtc(dev, possible_crtc) {
10286 i++;
10287 if (!(encoder->possible_crtcs & (1 << i)))
10288 continue;
10289 if (possible_crtc->state->enable)
10290 continue;
10291
10292 crtc = possible_crtc;
10293 break;
10294 }
10295
10296 /*
10297 * If we didn't find an unused CRTC, don't use any.
10298 */
10299 if (!crtc) {
10300 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10301 goto fail;
10302 }
10303
10304 ret = drm_modeset_lock(&crtc->mutex, ctx);
10305 if (ret)
10306 goto fail;
10307 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10308 if (ret)
10309 goto fail;
10310
10311 intel_crtc = to_intel_crtc(crtc);
10312 old->dpms_mode = connector->dpms;
10313 old->load_detect_temp = true;
10314 old->release_fb = NULL;
10315
10316 state = drm_atomic_state_alloc(dev);
10317 if (!state)
10318 return false;
10319
10320 state->acquire_ctx = ctx;
10321
10322 connector_state = drm_atomic_get_connector_state(state, connector);
10323 if (IS_ERR(connector_state)) {
10324 ret = PTR_ERR(connector_state);
10325 goto fail;
10326 }
10327
10328 connector_state->crtc = crtc;
10329 connector_state->best_encoder = &intel_encoder->base;
10330
10331 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10332 if (IS_ERR(crtc_state)) {
10333 ret = PTR_ERR(crtc_state);
10334 goto fail;
10335 }
10336
10337 crtc_state->base.active = crtc_state->base.enable = true;
10338
10339 if (!mode)
10340 mode = &load_detect_mode;
10341
10342 /* We need a framebuffer large enough to accommodate all accesses
10343 * that the plane may generate whilst we perform load detection.
10344 * We can not rely on the fbcon either being present (we get called
10345 * during its initialisation to detect all boot displays, or it may
10346 * not even exist) or that it is large enough to satisfy the
10347 * requested mode.
10348 */
10349 fb = mode_fits_in_fbdev(dev, mode);
10350 if (fb == NULL) {
10351 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10352 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10353 old->release_fb = fb;
10354 } else
10355 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10356 if (IS_ERR(fb)) {
10357 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10358 goto fail;
10359 }
10360
10361 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10362 if (ret)
10363 goto fail;
10364
10365 drm_mode_copy(&crtc_state->base.mode, mode);
10366
10367 if (drm_atomic_commit(state)) {
10368 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10369 if (old->release_fb)
10370 old->release_fb->funcs->destroy(old->release_fb);
10371 goto fail;
10372 }
10373 crtc->primary->crtc = crtc;
10374
10375 /* let the connector get through one full cycle before testing */
10376 intel_wait_for_vblank(dev, intel_crtc->pipe);
10377 return true;
10378
10379 fail:
10380 drm_atomic_state_free(state);
10381 state = NULL;
10382
10383 if (ret == -EDEADLK) {
10384 drm_modeset_backoff(ctx);
10385 goto retry;
10386 }
10387
10388 return false;
10389 }
10390
10391 void intel_release_load_detect_pipe(struct drm_connector *connector,
10392 struct intel_load_detect_pipe *old,
10393 struct drm_modeset_acquire_ctx *ctx)
10394 {
10395 struct drm_device *dev = connector->dev;
10396 struct intel_encoder *intel_encoder =
10397 intel_attached_encoder(connector);
10398 struct drm_encoder *encoder = &intel_encoder->base;
10399 struct drm_crtc *crtc = encoder->crtc;
10400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10401 struct drm_atomic_state *state;
10402 struct drm_connector_state *connector_state;
10403 struct intel_crtc_state *crtc_state;
10404 int ret;
10405
10406 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10407 connector->base.id, connector->name,
10408 encoder->base.id, encoder->name);
10409
10410 if (old->load_detect_temp) {
10411 state = drm_atomic_state_alloc(dev);
10412 if (!state)
10413 goto fail;
10414
10415 state->acquire_ctx = ctx;
10416
10417 connector_state = drm_atomic_get_connector_state(state, connector);
10418 if (IS_ERR(connector_state))
10419 goto fail;
10420
10421 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10422 if (IS_ERR(crtc_state))
10423 goto fail;
10424
10425 connector_state->best_encoder = NULL;
10426 connector_state->crtc = NULL;
10427
10428 crtc_state->base.enable = crtc_state->base.active = false;
10429
10430 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10431 0, 0);
10432 if (ret)
10433 goto fail;
10434
10435 ret = drm_atomic_commit(state);
10436 if (ret)
10437 goto fail;
10438
10439 if (old->release_fb) {
10440 drm_framebuffer_unregister_private(old->release_fb);
10441 drm_framebuffer_unreference(old->release_fb);
10442 }
10443
10444 return;
10445 }
10446
10447 /* Switch crtc and encoder back off if necessary */
10448 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10449 connector->funcs->dpms(connector, old->dpms_mode);
10450
10451 return;
10452 fail:
10453 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10454 drm_atomic_state_free(state);
10455 }
10456
10457 static int i9xx_pll_refclk(struct drm_device *dev,
10458 const struct intel_crtc_state *pipe_config)
10459 {
10460 struct drm_i915_private *dev_priv = dev->dev_private;
10461 u32 dpll = pipe_config->dpll_hw_state.dpll;
10462
10463 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10464 return dev_priv->vbt.lvds_ssc_freq;
10465 else if (HAS_PCH_SPLIT(dev))
10466 return 120000;
10467 else if (!IS_GEN2(dev))
10468 return 96000;
10469 else
10470 return 48000;
10471 }
10472
10473 /* Returns the clock of the currently programmed mode of the given pipe. */
10474 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10475 struct intel_crtc_state *pipe_config)
10476 {
10477 struct drm_device *dev = crtc->base.dev;
10478 struct drm_i915_private *dev_priv = dev->dev_private;
10479 int pipe = pipe_config->cpu_transcoder;
10480 u32 dpll = pipe_config->dpll_hw_state.dpll;
10481 u32 fp;
10482 intel_clock_t clock;
10483 int port_clock;
10484 int refclk = i9xx_pll_refclk(dev, pipe_config);
10485
10486 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10487 fp = pipe_config->dpll_hw_state.fp0;
10488 else
10489 fp = pipe_config->dpll_hw_state.fp1;
10490
10491 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10492 if (IS_PINEVIEW(dev)) {
10493 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10494 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10495 } else {
10496 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10497 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10498 }
10499
10500 if (!IS_GEN2(dev)) {
10501 if (IS_PINEVIEW(dev))
10502 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10503 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10504 else
10505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10506 DPLL_FPA01_P1_POST_DIV_SHIFT);
10507
10508 switch (dpll & DPLL_MODE_MASK) {
10509 case DPLLB_MODE_DAC_SERIAL:
10510 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10511 5 : 10;
10512 break;
10513 case DPLLB_MODE_LVDS:
10514 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10515 7 : 14;
10516 break;
10517 default:
10518 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10519 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10520 return;
10521 }
10522
10523 if (IS_PINEVIEW(dev))
10524 port_clock = pnv_calc_dpll_params(refclk, &clock);
10525 else
10526 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10527 } else {
10528 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10529 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10530
10531 if (is_lvds) {
10532 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10533 DPLL_FPA01_P1_POST_DIV_SHIFT);
10534
10535 if (lvds & LVDS_CLKB_POWER_UP)
10536 clock.p2 = 7;
10537 else
10538 clock.p2 = 14;
10539 } else {
10540 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10541 clock.p1 = 2;
10542 else {
10543 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10544 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10545 }
10546 if (dpll & PLL_P2_DIVIDE_BY_4)
10547 clock.p2 = 4;
10548 else
10549 clock.p2 = 2;
10550 }
10551
10552 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10553 }
10554
10555 /*
10556 * This value includes pixel_multiplier. We will use
10557 * port_clock to compute adjusted_mode.crtc_clock in the
10558 * encoder's get_config() function.
10559 */
10560 pipe_config->port_clock = port_clock;
10561 }
10562
10563 int intel_dotclock_calculate(int link_freq,
10564 const struct intel_link_m_n *m_n)
10565 {
10566 /*
10567 * The calculation for the data clock is:
10568 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10569 * But we want to avoid losing precison if possible, so:
10570 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10571 *
10572 * and the link clock is simpler:
10573 * link_clock = (m * link_clock) / n
10574 */
10575
10576 if (!m_n->link_n)
10577 return 0;
10578
10579 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10580 }
10581
10582 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10583 struct intel_crtc_state *pipe_config)
10584 {
10585 struct drm_device *dev = crtc->base.dev;
10586
10587 /* read out port_clock from the DPLL */
10588 i9xx_crtc_clock_get(crtc, pipe_config);
10589
10590 /*
10591 * This value does not include pixel_multiplier.
10592 * We will check that port_clock and adjusted_mode.crtc_clock
10593 * agree once we know their relationship in the encoder's
10594 * get_config() function.
10595 */
10596 pipe_config->base.adjusted_mode.crtc_clock =
10597 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10598 &pipe_config->fdi_m_n);
10599 }
10600
10601 /** Returns the currently programmed mode of the given pipe. */
10602 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10603 struct drm_crtc *crtc)
10604 {
10605 struct drm_i915_private *dev_priv = dev->dev_private;
10606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10607 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10608 struct drm_display_mode *mode;
10609 struct intel_crtc_state pipe_config;
10610 int htot = I915_READ(HTOTAL(cpu_transcoder));
10611 int hsync = I915_READ(HSYNC(cpu_transcoder));
10612 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10613 int vsync = I915_READ(VSYNC(cpu_transcoder));
10614 enum pipe pipe = intel_crtc->pipe;
10615
10616 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10617 if (!mode)
10618 return NULL;
10619
10620 /*
10621 * Construct a pipe_config sufficient for getting the clock info
10622 * back out of crtc_clock_get.
10623 *
10624 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10625 * to use a real value here instead.
10626 */
10627 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10628 pipe_config.pixel_multiplier = 1;
10629 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10630 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10631 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10632 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10633
10634 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10635 mode->hdisplay = (htot & 0xffff) + 1;
10636 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10637 mode->hsync_start = (hsync & 0xffff) + 1;
10638 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10639 mode->vdisplay = (vtot & 0xffff) + 1;
10640 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10641 mode->vsync_start = (vsync & 0xffff) + 1;
10642 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10643
10644 drm_mode_set_name(mode);
10645
10646 return mode;
10647 }
10648
10649 void intel_mark_busy(struct drm_device *dev)
10650 {
10651 struct drm_i915_private *dev_priv = dev->dev_private;
10652
10653 if (dev_priv->mm.busy)
10654 return;
10655
10656 intel_runtime_pm_get(dev_priv);
10657 i915_update_gfx_val(dev_priv);
10658 if (INTEL_INFO(dev)->gen >= 6)
10659 gen6_rps_busy(dev_priv);
10660 dev_priv->mm.busy = true;
10661 }
10662
10663 void intel_mark_idle(struct drm_device *dev)
10664 {
10665 struct drm_i915_private *dev_priv = dev->dev_private;
10666
10667 if (!dev_priv->mm.busy)
10668 return;
10669
10670 dev_priv->mm.busy = false;
10671
10672 if (INTEL_INFO(dev)->gen >= 6)
10673 gen6_rps_idle(dev->dev_private);
10674
10675 intel_runtime_pm_put(dev_priv);
10676 }
10677
10678 static void intel_crtc_destroy(struct drm_crtc *crtc)
10679 {
10680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10681 struct drm_device *dev = crtc->dev;
10682 struct intel_unpin_work *work;
10683
10684 spin_lock_irq(&dev->event_lock);
10685 work = intel_crtc->unpin_work;
10686 intel_crtc->unpin_work = NULL;
10687 spin_unlock_irq(&dev->event_lock);
10688
10689 if (work) {
10690 cancel_work_sync(&work->work);
10691 kfree(work);
10692 }
10693
10694 drm_crtc_cleanup(crtc);
10695
10696 kfree(intel_crtc);
10697 }
10698
10699 static void intel_unpin_work_fn(struct work_struct *__work)
10700 {
10701 struct intel_unpin_work *work =
10702 container_of(__work, struct intel_unpin_work, work);
10703 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10704 struct drm_device *dev = crtc->base.dev;
10705 struct drm_plane *primary = crtc->base.primary;
10706
10707 mutex_lock(&dev->struct_mutex);
10708 intel_unpin_fb_obj(work->old_fb, primary->state);
10709 drm_gem_object_unreference(&work->pending_flip_obj->base);
10710
10711 if (work->flip_queued_req)
10712 i915_gem_request_assign(&work->flip_queued_req, NULL);
10713 mutex_unlock(&dev->struct_mutex);
10714
10715 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10716 drm_framebuffer_unreference(work->old_fb);
10717
10718 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10719 atomic_dec(&crtc->unpin_work_count);
10720
10721 kfree(work);
10722 }
10723
10724 static void do_intel_finish_page_flip(struct drm_device *dev,
10725 struct drm_crtc *crtc)
10726 {
10727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10728 struct intel_unpin_work *work;
10729 unsigned long flags;
10730
10731 /* Ignore early vblank irqs */
10732 if (intel_crtc == NULL)
10733 return;
10734
10735 /*
10736 * This is called both by irq handlers and the reset code (to complete
10737 * lost pageflips) so needs the full irqsave spinlocks.
10738 */
10739 spin_lock_irqsave(&dev->event_lock, flags);
10740 work = intel_crtc->unpin_work;
10741
10742 /* Ensure we don't miss a work->pending update ... */
10743 smp_rmb();
10744
10745 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10746 spin_unlock_irqrestore(&dev->event_lock, flags);
10747 return;
10748 }
10749
10750 page_flip_completed(intel_crtc);
10751
10752 spin_unlock_irqrestore(&dev->event_lock, flags);
10753 }
10754
10755 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10756 {
10757 struct drm_i915_private *dev_priv = dev->dev_private;
10758 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10759
10760 do_intel_finish_page_flip(dev, crtc);
10761 }
10762
10763 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10764 {
10765 struct drm_i915_private *dev_priv = dev->dev_private;
10766 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10767
10768 do_intel_finish_page_flip(dev, crtc);
10769 }
10770
10771 /* Is 'a' after or equal to 'b'? */
10772 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10773 {
10774 return !((a - b) & 0x80000000);
10775 }
10776
10777 static bool page_flip_finished(struct intel_crtc *crtc)
10778 {
10779 struct drm_device *dev = crtc->base.dev;
10780 struct drm_i915_private *dev_priv = dev->dev_private;
10781
10782 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10783 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10784 return true;
10785
10786 /*
10787 * The relevant registers doen't exist on pre-ctg.
10788 * As the flip done interrupt doesn't trigger for mmio
10789 * flips on gmch platforms, a flip count check isn't
10790 * really needed there. But since ctg has the registers,
10791 * include it in the check anyway.
10792 */
10793 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10794 return true;
10795
10796 /*
10797 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10798 * used the same base address. In that case the mmio flip might
10799 * have completed, but the CS hasn't even executed the flip yet.
10800 *
10801 * A flip count check isn't enough as the CS might have updated
10802 * the base address just after start of vblank, but before we
10803 * managed to process the interrupt. This means we'd complete the
10804 * CS flip too soon.
10805 *
10806 * Combining both checks should get us a good enough result. It may
10807 * still happen that the CS flip has been executed, but has not
10808 * yet actually completed. But in case the base address is the same
10809 * anyway, we don't really care.
10810 */
10811 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10812 crtc->unpin_work->gtt_offset &&
10813 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10814 crtc->unpin_work->flip_count);
10815 }
10816
10817 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10818 {
10819 struct drm_i915_private *dev_priv = dev->dev_private;
10820 struct intel_crtc *intel_crtc =
10821 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10822 unsigned long flags;
10823
10824
10825 /*
10826 * This is called both by irq handlers and the reset code (to complete
10827 * lost pageflips) so needs the full irqsave spinlocks.
10828 *
10829 * NB: An MMIO update of the plane base pointer will also
10830 * generate a page-flip completion irq, i.e. every modeset
10831 * is also accompanied by a spurious intel_prepare_page_flip().
10832 */
10833 spin_lock_irqsave(&dev->event_lock, flags);
10834 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10835 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10836 spin_unlock_irqrestore(&dev->event_lock, flags);
10837 }
10838
10839 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10840 {
10841 /* Ensure that the work item is consistent when activating it ... */
10842 smp_wmb();
10843 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10844 /* and that it is marked active as soon as the irq could fire. */
10845 smp_wmb();
10846 }
10847
10848 static int intel_gen2_queue_flip(struct drm_device *dev,
10849 struct drm_crtc *crtc,
10850 struct drm_framebuffer *fb,
10851 struct drm_i915_gem_object *obj,
10852 struct drm_i915_gem_request *req,
10853 uint32_t flags)
10854 {
10855 struct intel_engine_cs *ring = req->ring;
10856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857 u32 flip_mask;
10858 int ret;
10859
10860 ret = intel_ring_begin(req, 6);
10861 if (ret)
10862 return ret;
10863
10864 /* Can't queue multiple flips, so wait for the previous
10865 * one to finish before executing the next.
10866 */
10867 if (intel_crtc->plane)
10868 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10869 else
10870 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10871 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10872 intel_ring_emit(ring, MI_NOOP);
10873 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10874 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10875 intel_ring_emit(ring, fb->pitches[0]);
10876 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10877 intel_ring_emit(ring, 0); /* aux display base address, unused */
10878
10879 intel_mark_page_flip_active(intel_crtc->unpin_work);
10880 return 0;
10881 }
10882
10883 static int intel_gen3_queue_flip(struct drm_device *dev,
10884 struct drm_crtc *crtc,
10885 struct drm_framebuffer *fb,
10886 struct drm_i915_gem_object *obj,
10887 struct drm_i915_gem_request *req,
10888 uint32_t flags)
10889 {
10890 struct intel_engine_cs *ring = req->ring;
10891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10892 u32 flip_mask;
10893 int ret;
10894
10895 ret = intel_ring_begin(req, 6);
10896 if (ret)
10897 return ret;
10898
10899 if (intel_crtc->plane)
10900 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10901 else
10902 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10903 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10904 intel_ring_emit(ring, MI_NOOP);
10905 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10906 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10907 intel_ring_emit(ring, fb->pitches[0]);
10908 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10909 intel_ring_emit(ring, MI_NOOP);
10910
10911 intel_mark_page_flip_active(intel_crtc->unpin_work);
10912 return 0;
10913 }
10914
10915 static int intel_gen4_queue_flip(struct drm_device *dev,
10916 struct drm_crtc *crtc,
10917 struct drm_framebuffer *fb,
10918 struct drm_i915_gem_object *obj,
10919 struct drm_i915_gem_request *req,
10920 uint32_t flags)
10921 {
10922 struct intel_engine_cs *ring = req->ring;
10923 struct drm_i915_private *dev_priv = dev->dev_private;
10924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10925 uint32_t pf, pipesrc;
10926 int ret;
10927
10928 ret = intel_ring_begin(req, 4);
10929 if (ret)
10930 return ret;
10931
10932 /* i965+ uses the linear or tiled offsets from the
10933 * Display Registers (which do not change across a page-flip)
10934 * so we need only reprogram the base address.
10935 */
10936 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10937 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10938 intel_ring_emit(ring, fb->pitches[0]);
10939 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10940 obj->tiling_mode);
10941
10942 /* XXX Enabling the panel-fitter across page-flip is so far
10943 * untested on non-native modes, so ignore it for now.
10944 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10945 */
10946 pf = 0;
10947 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10948 intel_ring_emit(ring, pf | pipesrc);
10949
10950 intel_mark_page_flip_active(intel_crtc->unpin_work);
10951 return 0;
10952 }
10953
10954 static int intel_gen6_queue_flip(struct drm_device *dev,
10955 struct drm_crtc *crtc,
10956 struct drm_framebuffer *fb,
10957 struct drm_i915_gem_object *obj,
10958 struct drm_i915_gem_request *req,
10959 uint32_t flags)
10960 {
10961 struct intel_engine_cs *ring = req->ring;
10962 struct drm_i915_private *dev_priv = dev->dev_private;
10963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10964 uint32_t pf, pipesrc;
10965 int ret;
10966
10967 ret = intel_ring_begin(req, 4);
10968 if (ret)
10969 return ret;
10970
10971 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10972 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10973 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10974 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10975
10976 /* Contrary to the suggestions in the documentation,
10977 * "Enable Panel Fitter" does not seem to be required when page
10978 * flipping with a non-native mode, and worse causes a normal
10979 * modeset to fail.
10980 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10981 */
10982 pf = 0;
10983 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10984 intel_ring_emit(ring, pf | pipesrc);
10985
10986 intel_mark_page_flip_active(intel_crtc->unpin_work);
10987 return 0;
10988 }
10989
10990 static int intel_gen7_queue_flip(struct drm_device *dev,
10991 struct drm_crtc *crtc,
10992 struct drm_framebuffer *fb,
10993 struct drm_i915_gem_object *obj,
10994 struct drm_i915_gem_request *req,
10995 uint32_t flags)
10996 {
10997 struct intel_engine_cs *ring = req->ring;
10998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10999 uint32_t plane_bit = 0;
11000 int len, ret;
11001
11002 switch (intel_crtc->plane) {
11003 case PLANE_A:
11004 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11005 break;
11006 case PLANE_B:
11007 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11008 break;
11009 case PLANE_C:
11010 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11011 break;
11012 default:
11013 WARN_ONCE(1, "unknown plane in flip command\n");
11014 return -ENODEV;
11015 }
11016
11017 len = 4;
11018 if (ring->id == RCS) {
11019 len += 6;
11020 /*
11021 * On Gen 8, SRM is now taking an extra dword to accommodate
11022 * 48bits addresses, and we need a NOOP for the batch size to
11023 * stay even.
11024 */
11025 if (IS_GEN8(dev))
11026 len += 2;
11027 }
11028
11029 /*
11030 * BSpec MI_DISPLAY_FLIP for IVB:
11031 * "The full packet must be contained within the same cache line."
11032 *
11033 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11034 * cacheline, if we ever start emitting more commands before
11035 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11036 * then do the cacheline alignment, and finally emit the
11037 * MI_DISPLAY_FLIP.
11038 */
11039 ret = intel_ring_cacheline_align(req);
11040 if (ret)
11041 return ret;
11042
11043 ret = intel_ring_begin(req, len);
11044 if (ret)
11045 return ret;
11046
11047 /* Unmask the flip-done completion message. Note that the bspec says that
11048 * we should do this for both the BCS and RCS, and that we must not unmask
11049 * more than one flip event at any time (or ensure that one flip message
11050 * can be sent by waiting for flip-done prior to queueing new flips).
11051 * Experimentation says that BCS works despite DERRMR masking all
11052 * flip-done completion events and that unmasking all planes at once
11053 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11054 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11055 */
11056 if (ring->id == RCS) {
11057 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11058 intel_ring_emit(ring, DERRMR);
11059 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11060 DERRMR_PIPEB_PRI_FLIP_DONE |
11061 DERRMR_PIPEC_PRI_FLIP_DONE));
11062 if (IS_GEN8(dev))
11063 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11064 MI_SRM_LRM_GLOBAL_GTT);
11065 else
11066 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11067 MI_SRM_LRM_GLOBAL_GTT);
11068 intel_ring_emit(ring, DERRMR);
11069 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11070 if (IS_GEN8(dev)) {
11071 intel_ring_emit(ring, 0);
11072 intel_ring_emit(ring, MI_NOOP);
11073 }
11074 }
11075
11076 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11077 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11078 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11079 intel_ring_emit(ring, (MI_NOOP));
11080
11081 intel_mark_page_flip_active(intel_crtc->unpin_work);
11082 return 0;
11083 }
11084
11085 static bool use_mmio_flip(struct intel_engine_cs *ring,
11086 struct drm_i915_gem_object *obj)
11087 {
11088 /*
11089 * This is not being used for older platforms, because
11090 * non-availability of flip done interrupt forces us to use
11091 * CS flips. Older platforms derive flip done using some clever
11092 * tricks involving the flip_pending status bits and vblank irqs.
11093 * So using MMIO flips there would disrupt this mechanism.
11094 */
11095
11096 if (ring == NULL)
11097 return true;
11098
11099 if (INTEL_INFO(ring->dev)->gen < 5)
11100 return false;
11101
11102 if (i915.use_mmio_flip < 0)
11103 return false;
11104 else if (i915.use_mmio_flip > 0)
11105 return true;
11106 else if (i915.enable_execlists)
11107 return true;
11108 else
11109 return ring != i915_gem_request_get_ring(obj->last_write_req);
11110 }
11111
11112 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11113 struct intel_unpin_work *work)
11114 {
11115 struct drm_device *dev = intel_crtc->base.dev;
11116 struct drm_i915_private *dev_priv = dev->dev_private;
11117 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11118 const enum pipe pipe = intel_crtc->pipe;
11119 u32 ctl, stride;
11120
11121 ctl = I915_READ(PLANE_CTL(pipe, 0));
11122 ctl &= ~PLANE_CTL_TILED_MASK;
11123 switch (fb->modifier[0]) {
11124 case DRM_FORMAT_MOD_NONE:
11125 break;
11126 case I915_FORMAT_MOD_X_TILED:
11127 ctl |= PLANE_CTL_TILED_X;
11128 break;
11129 case I915_FORMAT_MOD_Y_TILED:
11130 ctl |= PLANE_CTL_TILED_Y;
11131 break;
11132 case I915_FORMAT_MOD_Yf_TILED:
11133 ctl |= PLANE_CTL_TILED_YF;
11134 break;
11135 default:
11136 MISSING_CASE(fb->modifier[0]);
11137 }
11138
11139 /*
11140 * The stride is either expressed as a multiple of 64 bytes chunks for
11141 * linear buffers or in number of tiles for tiled buffers.
11142 */
11143 stride = fb->pitches[0] /
11144 intel_fb_stride_alignment(dev, fb->modifier[0],
11145 fb->pixel_format);
11146
11147 /*
11148 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11149 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11150 */
11151 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11152 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11153
11154 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11155 POSTING_READ(PLANE_SURF(pipe, 0));
11156 }
11157
11158 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11159 struct intel_unpin_work *work)
11160 {
11161 struct drm_device *dev = intel_crtc->base.dev;
11162 struct drm_i915_private *dev_priv = dev->dev_private;
11163 struct intel_framebuffer *intel_fb =
11164 to_intel_framebuffer(intel_crtc->base.primary->fb);
11165 struct drm_i915_gem_object *obj = intel_fb->obj;
11166 u32 dspcntr;
11167 u32 reg;
11168
11169 reg = DSPCNTR(intel_crtc->plane);
11170 dspcntr = I915_READ(reg);
11171
11172 if (obj->tiling_mode != I915_TILING_NONE)
11173 dspcntr |= DISPPLANE_TILED;
11174 else
11175 dspcntr &= ~DISPPLANE_TILED;
11176
11177 I915_WRITE(reg, dspcntr);
11178
11179 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11180 POSTING_READ(DSPSURF(intel_crtc->plane));
11181 }
11182
11183 /*
11184 * XXX: This is the temporary way to update the plane registers until we get
11185 * around to using the usual plane update functions for MMIO flips
11186 */
11187 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11188 {
11189 struct intel_crtc *crtc = mmio_flip->crtc;
11190 struct intel_unpin_work *work;
11191
11192 spin_lock_irq(&crtc->base.dev->event_lock);
11193 work = crtc->unpin_work;
11194 spin_unlock_irq(&crtc->base.dev->event_lock);
11195 if (work == NULL)
11196 return;
11197
11198 intel_mark_page_flip_active(work);
11199
11200 intel_pipe_update_start(crtc);
11201
11202 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11203 skl_do_mmio_flip(crtc, work);
11204 else
11205 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11206 ilk_do_mmio_flip(crtc, work);
11207
11208 intel_pipe_update_end(crtc);
11209 }
11210
11211 static void intel_mmio_flip_work_func(struct work_struct *work)
11212 {
11213 struct intel_mmio_flip *mmio_flip =
11214 container_of(work, struct intel_mmio_flip, work);
11215
11216 if (mmio_flip->req) {
11217 WARN_ON(__i915_wait_request(mmio_flip->req,
11218 mmio_flip->crtc->reset_counter,
11219 false, NULL,
11220 &mmio_flip->i915->rps.mmioflips));
11221 i915_gem_request_unreference__unlocked(mmio_flip->req);
11222 }
11223
11224 intel_do_mmio_flip(mmio_flip);
11225 kfree(mmio_flip);
11226 }
11227
11228 static int intel_queue_mmio_flip(struct drm_device *dev,
11229 struct drm_crtc *crtc,
11230 struct drm_framebuffer *fb,
11231 struct drm_i915_gem_object *obj,
11232 struct intel_engine_cs *ring,
11233 uint32_t flags)
11234 {
11235 struct intel_mmio_flip *mmio_flip;
11236
11237 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11238 if (mmio_flip == NULL)
11239 return -ENOMEM;
11240
11241 mmio_flip->i915 = to_i915(dev);
11242 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11243 mmio_flip->crtc = to_intel_crtc(crtc);
11244
11245 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11246 schedule_work(&mmio_flip->work);
11247
11248 return 0;
11249 }
11250
11251 static int intel_default_queue_flip(struct drm_device *dev,
11252 struct drm_crtc *crtc,
11253 struct drm_framebuffer *fb,
11254 struct drm_i915_gem_object *obj,
11255 struct drm_i915_gem_request *req,
11256 uint32_t flags)
11257 {
11258 return -ENODEV;
11259 }
11260
11261 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11262 struct drm_crtc *crtc)
11263 {
11264 struct drm_i915_private *dev_priv = dev->dev_private;
11265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11266 struct intel_unpin_work *work = intel_crtc->unpin_work;
11267 u32 addr;
11268
11269 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11270 return true;
11271
11272 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11273 return false;
11274
11275 if (!work->enable_stall_check)
11276 return false;
11277
11278 if (work->flip_ready_vblank == 0) {
11279 if (work->flip_queued_req &&
11280 !i915_gem_request_completed(work->flip_queued_req, true))
11281 return false;
11282
11283 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11284 }
11285
11286 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11287 return false;
11288
11289 /* Potential stall - if we see that the flip has happened,
11290 * assume a missed interrupt. */
11291 if (INTEL_INFO(dev)->gen >= 4)
11292 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11293 else
11294 addr = I915_READ(DSPADDR(intel_crtc->plane));
11295
11296 /* There is a potential issue here with a false positive after a flip
11297 * to the same address. We could address this by checking for a
11298 * non-incrementing frame counter.
11299 */
11300 return addr == work->gtt_offset;
11301 }
11302
11303 void intel_check_page_flip(struct drm_device *dev, int pipe)
11304 {
11305 struct drm_i915_private *dev_priv = dev->dev_private;
11306 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11308 struct intel_unpin_work *work;
11309
11310 WARN_ON(!in_interrupt());
11311
11312 if (crtc == NULL)
11313 return;
11314
11315 spin_lock(&dev->event_lock);
11316 work = intel_crtc->unpin_work;
11317 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11318 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11319 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11320 page_flip_completed(intel_crtc);
11321 work = NULL;
11322 }
11323 if (work != NULL &&
11324 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11325 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11326 spin_unlock(&dev->event_lock);
11327 }
11328
11329 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11330 struct drm_framebuffer *fb,
11331 struct drm_pending_vblank_event *event,
11332 uint32_t page_flip_flags)
11333 {
11334 struct drm_device *dev = crtc->dev;
11335 struct drm_i915_private *dev_priv = dev->dev_private;
11336 struct drm_framebuffer *old_fb = crtc->primary->fb;
11337 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11339 struct drm_plane *primary = crtc->primary;
11340 enum pipe pipe = intel_crtc->pipe;
11341 struct intel_unpin_work *work;
11342 struct intel_engine_cs *ring;
11343 bool mmio_flip;
11344 struct drm_i915_gem_request *request = NULL;
11345 int ret;
11346
11347 /*
11348 * drm_mode_page_flip_ioctl() should already catch this, but double
11349 * check to be safe. In the future we may enable pageflipping from
11350 * a disabled primary plane.
11351 */
11352 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11353 return -EBUSY;
11354
11355 /* Can't change pixel format via MI display flips. */
11356 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11357 return -EINVAL;
11358
11359 /*
11360 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11361 * Note that pitch changes could also affect these register.
11362 */
11363 if (INTEL_INFO(dev)->gen > 3 &&
11364 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11365 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11366 return -EINVAL;
11367
11368 if (i915_terminally_wedged(&dev_priv->gpu_error))
11369 goto out_hang;
11370
11371 work = kzalloc(sizeof(*work), GFP_KERNEL);
11372 if (work == NULL)
11373 return -ENOMEM;
11374
11375 work->event = event;
11376 work->crtc = crtc;
11377 work->old_fb = old_fb;
11378 INIT_WORK(&work->work, intel_unpin_work_fn);
11379
11380 ret = drm_crtc_vblank_get(crtc);
11381 if (ret)
11382 goto free_work;
11383
11384 /* We borrow the event spin lock for protecting unpin_work */
11385 spin_lock_irq(&dev->event_lock);
11386 if (intel_crtc->unpin_work) {
11387 /* Before declaring the flip queue wedged, check if
11388 * the hardware completed the operation behind our backs.
11389 */
11390 if (__intel_pageflip_stall_check(dev, crtc)) {
11391 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11392 page_flip_completed(intel_crtc);
11393 } else {
11394 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11395 spin_unlock_irq(&dev->event_lock);
11396
11397 drm_crtc_vblank_put(crtc);
11398 kfree(work);
11399 return -EBUSY;
11400 }
11401 }
11402 intel_crtc->unpin_work = work;
11403 spin_unlock_irq(&dev->event_lock);
11404
11405 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11406 flush_workqueue(dev_priv->wq);
11407
11408 /* Reference the objects for the scheduled work. */
11409 drm_framebuffer_reference(work->old_fb);
11410 drm_gem_object_reference(&obj->base);
11411
11412 crtc->primary->fb = fb;
11413 update_state_fb(crtc->primary);
11414
11415 work->pending_flip_obj = obj;
11416
11417 ret = i915_mutex_lock_interruptible(dev);
11418 if (ret)
11419 goto cleanup;
11420
11421 atomic_inc(&intel_crtc->unpin_work_count);
11422 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11423
11424 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11425 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11426
11427 if (IS_VALLEYVIEW(dev)) {
11428 ring = &dev_priv->ring[BCS];
11429 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11430 /* vlv: DISPLAY_FLIP fails to change tiling */
11431 ring = NULL;
11432 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11433 ring = &dev_priv->ring[BCS];
11434 } else if (INTEL_INFO(dev)->gen >= 7) {
11435 ring = i915_gem_request_get_ring(obj->last_write_req);
11436 if (ring == NULL || ring->id != RCS)
11437 ring = &dev_priv->ring[BCS];
11438 } else {
11439 ring = &dev_priv->ring[RCS];
11440 }
11441
11442 mmio_flip = use_mmio_flip(ring, obj);
11443
11444 /* When using CS flips, we want to emit semaphores between rings.
11445 * However, when using mmio flips we will create a task to do the
11446 * synchronisation, so all we want here is to pin the framebuffer
11447 * into the display plane and skip any waits.
11448 */
11449 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11450 crtc->primary->state,
11451 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
11452 if (ret)
11453 goto cleanup_pending;
11454
11455 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11456 obj, 0);
11457 work->gtt_offset += intel_crtc->dspaddr_offset;
11458
11459 if (mmio_flip) {
11460 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11461 page_flip_flags);
11462 if (ret)
11463 goto cleanup_unpin;
11464
11465 i915_gem_request_assign(&work->flip_queued_req,
11466 obj->last_write_req);
11467 } else {
11468 if (!request) {
11469 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11470 if (ret)
11471 goto cleanup_unpin;
11472 }
11473
11474 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11475 page_flip_flags);
11476 if (ret)
11477 goto cleanup_unpin;
11478
11479 i915_gem_request_assign(&work->flip_queued_req, request);
11480 }
11481
11482 if (request)
11483 i915_add_request_no_flush(request);
11484
11485 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11486 work->enable_stall_check = true;
11487
11488 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11489 to_intel_plane(primary)->frontbuffer_bit);
11490 mutex_unlock(&dev->struct_mutex);
11491
11492 intel_fbc_disable_crtc(intel_crtc);
11493 intel_frontbuffer_flip_prepare(dev,
11494 to_intel_plane(primary)->frontbuffer_bit);
11495
11496 trace_i915_flip_request(intel_crtc->plane, obj);
11497
11498 return 0;
11499
11500 cleanup_unpin:
11501 intel_unpin_fb_obj(fb, crtc->primary->state);
11502 cleanup_pending:
11503 if (request)
11504 i915_gem_request_cancel(request);
11505 atomic_dec(&intel_crtc->unpin_work_count);
11506 mutex_unlock(&dev->struct_mutex);
11507 cleanup:
11508 crtc->primary->fb = old_fb;
11509 update_state_fb(crtc->primary);
11510
11511 drm_gem_object_unreference_unlocked(&obj->base);
11512 drm_framebuffer_unreference(work->old_fb);
11513
11514 spin_lock_irq(&dev->event_lock);
11515 intel_crtc->unpin_work = NULL;
11516 spin_unlock_irq(&dev->event_lock);
11517
11518 drm_crtc_vblank_put(crtc);
11519 free_work:
11520 kfree(work);
11521
11522 if (ret == -EIO) {
11523 struct drm_atomic_state *state;
11524 struct drm_plane_state *plane_state;
11525
11526 out_hang:
11527 state = drm_atomic_state_alloc(dev);
11528 if (!state)
11529 return -ENOMEM;
11530 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11531
11532 retry:
11533 plane_state = drm_atomic_get_plane_state(state, primary);
11534 ret = PTR_ERR_OR_ZERO(plane_state);
11535 if (!ret) {
11536 drm_atomic_set_fb_for_plane(plane_state, fb);
11537
11538 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11539 if (!ret)
11540 ret = drm_atomic_commit(state);
11541 }
11542
11543 if (ret == -EDEADLK) {
11544 drm_modeset_backoff(state->acquire_ctx);
11545 drm_atomic_state_clear(state);
11546 goto retry;
11547 }
11548
11549 if (ret)
11550 drm_atomic_state_free(state);
11551
11552 if (ret == 0 && event) {
11553 spin_lock_irq(&dev->event_lock);
11554 drm_send_vblank_event(dev, pipe, event);
11555 spin_unlock_irq(&dev->event_lock);
11556 }
11557 }
11558 return ret;
11559 }
11560
11561
11562 /**
11563 * intel_wm_need_update - Check whether watermarks need updating
11564 * @plane: drm plane
11565 * @state: new plane state
11566 *
11567 * Check current plane state versus the new one to determine whether
11568 * watermarks need to be recalculated.
11569 *
11570 * Returns true or false.
11571 */
11572 static bool intel_wm_need_update(struct drm_plane *plane,
11573 struct drm_plane_state *state)
11574 {
11575 /* Update watermarks on tiling changes. */
11576 if (!plane->state->fb || !state->fb ||
11577 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11578 plane->state->rotation != state->rotation)
11579 return true;
11580
11581 if (plane->state->crtc_w != state->crtc_w)
11582 return true;
11583
11584 return false;
11585 }
11586
11587 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11588 struct drm_plane_state *plane_state)
11589 {
11590 struct drm_crtc *crtc = crtc_state->crtc;
11591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11592 struct drm_plane *plane = plane_state->plane;
11593 struct drm_device *dev = crtc->dev;
11594 struct drm_i915_private *dev_priv = dev->dev_private;
11595 struct intel_plane_state *old_plane_state =
11596 to_intel_plane_state(plane->state);
11597 int idx = intel_crtc->base.base.id, ret;
11598 int i = drm_plane_index(plane);
11599 bool mode_changed = needs_modeset(crtc_state);
11600 bool was_crtc_enabled = crtc->state->active;
11601 bool is_crtc_enabled = crtc_state->active;
11602
11603 bool turn_off, turn_on, visible, was_visible;
11604 struct drm_framebuffer *fb = plane_state->fb;
11605
11606 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11607 plane->type != DRM_PLANE_TYPE_CURSOR) {
11608 ret = skl_update_scaler_plane(
11609 to_intel_crtc_state(crtc_state),
11610 to_intel_plane_state(plane_state));
11611 if (ret)
11612 return ret;
11613 }
11614
11615 /*
11616 * Disabling a plane is always okay; we just need to update
11617 * fb tracking in a special way since cleanup_fb() won't
11618 * get called by the plane helpers.
11619 */
11620 if (old_plane_state->base.fb && !fb)
11621 intel_crtc->atomic.disabled_planes |= 1 << i;
11622
11623 was_visible = old_plane_state->visible;
11624 visible = to_intel_plane_state(plane_state)->visible;
11625
11626 if (!was_crtc_enabled && WARN_ON(was_visible))
11627 was_visible = false;
11628
11629 if (!is_crtc_enabled && WARN_ON(visible))
11630 visible = false;
11631
11632 if (!was_visible && !visible)
11633 return 0;
11634
11635 turn_off = was_visible && (!visible || mode_changed);
11636 turn_on = visible && (!was_visible || mode_changed);
11637
11638 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11639 plane->base.id, fb ? fb->base.id : -1);
11640
11641 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11642 plane->base.id, was_visible, visible,
11643 turn_off, turn_on, mode_changed);
11644
11645 if (turn_on) {
11646 intel_crtc->atomic.update_wm_pre = true;
11647 /* must disable cxsr around plane enable/disable */
11648 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11649 intel_crtc->atomic.disable_cxsr = true;
11650 /* to potentially re-enable cxsr */
11651 intel_crtc->atomic.wait_vblank = true;
11652 intel_crtc->atomic.update_wm_post = true;
11653 }
11654 } else if (turn_off) {
11655 intel_crtc->atomic.update_wm_post = true;
11656 /* must disable cxsr around plane enable/disable */
11657 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11658 if (is_crtc_enabled)
11659 intel_crtc->atomic.wait_vblank = true;
11660 intel_crtc->atomic.disable_cxsr = true;
11661 }
11662 } else if (intel_wm_need_update(plane, plane_state)) {
11663 intel_crtc->atomic.update_wm_pre = true;
11664 }
11665
11666 if (visible || was_visible)
11667 intel_crtc->atomic.fb_bits |=
11668 to_intel_plane(plane)->frontbuffer_bit;
11669
11670 switch (plane->type) {
11671 case DRM_PLANE_TYPE_PRIMARY:
11672 intel_crtc->atomic.wait_for_flips = true;
11673 intel_crtc->atomic.pre_disable_primary = turn_off;
11674 intel_crtc->atomic.post_enable_primary = turn_on;
11675
11676 if (turn_off) {
11677 /*
11678 * FIXME: Actually if we will still have any other
11679 * plane enabled on the pipe we could let IPS enabled
11680 * still, but for now lets consider that when we make
11681 * primary invisible by setting DSPCNTR to 0 on
11682 * update_primary_plane function IPS needs to be
11683 * disable.
11684 */
11685 intel_crtc->atomic.disable_ips = true;
11686
11687 intel_crtc->atomic.disable_fbc = true;
11688 }
11689
11690 /*
11691 * FBC does not work on some platforms for rotated
11692 * planes, so disable it when rotation is not 0 and
11693 * update it when rotation is set back to 0.
11694 *
11695 * FIXME: This is redundant with the fbc update done in
11696 * the primary plane enable function except that that
11697 * one is done too late. We eventually need to unify
11698 * this.
11699 */
11700
11701 if (visible &&
11702 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11703 dev_priv->fbc.crtc == intel_crtc &&
11704 plane_state->rotation != BIT(DRM_ROTATE_0))
11705 intel_crtc->atomic.disable_fbc = true;
11706
11707 /*
11708 * BDW signals flip done immediately if the plane
11709 * is disabled, even if the plane enable is already
11710 * armed to occur at the next vblank :(
11711 */
11712 if (turn_on && IS_BROADWELL(dev))
11713 intel_crtc->atomic.wait_vblank = true;
11714
11715 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11716 break;
11717 case DRM_PLANE_TYPE_CURSOR:
11718 break;
11719 case DRM_PLANE_TYPE_OVERLAY:
11720 if (turn_off && !mode_changed) {
11721 intel_crtc->atomic.wait_vblank = true;
11722 intel_crtc->atomic.update_sprite_watermarks |=
11723 1 << i;
11724 }
11725 }
11726 return 0;
11727 }
11728
11729 static bool encoders_cloneable(const struct intel_encoder *a,
11730 const struct intel_encoder *b)
11731 {
11732 /* masks could be asymmetric, so check both ways */
11733 return a == b || (a->cloneable & (1 << b->type) &&
11734 b->cloneable & (1 << a->type));
11735 }
11736
11737 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11738 struct intel_crtc *crtc,
11739 struct intel_encoder *encoder)
11740 {
11741 struct intel_encoder *source_encoder;
11742 struct drm_connector *connector;
11743 struct drm_connector_state *connector_state;
11744 int i;
11745
11746 for_each_connector_in_state(state, connector, connector_state, i) {
11747 if (connector_state->crtc != &crtc->base)
11748 continue;
11749
11750 source_encoder =
11751 to_intel_encoder(connector_state->best_encoder);
11752 if (!encoders_cloneable(encoder, source_encoder))
11753 return false;
11754 }
11755
11756 return true;
11757 }
11758
11759 static bool check_encoder_cloning(struct drm_atomic_state *state,
11760 struct intel_crtc *crtc)
11761 {
11762 struct intel_encoder *encoder;
11763 struct drm_connector *connector;
11764 struct drm_connector_state *connector_state;
11765 int i;
11766
11767 for_each_connector_in_state(state, connector, connector_state, i) {
11768 if (connector_state->crtc != &crtc->base)
11769 continue;
11770
11771 encoder = to_intel_encoder(connector_state->best_encoder);
11772 if (!check_single_encoder_cloning(state, crtc, encoder))
11773 return false;
11774 }
11775
11776 return true;
11777 }
11778
11779 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11780 struct drm_crtc_state *crtc_state)
11781 {
11782 struct drm_device *dev = crtc->dev;
11783 struct drm_i915_private *dev_priv = dev->dev_private;
11784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11785 struct intel_crtc_state *pipe_config =
11786 to_intel_crtc_state(crtc_state);
11787 struct drm_atomic_state *state = crtc_state->state;
11788 int ret;
11789 bool mode_changed = needs_modeset(crtc_state);
11790
11791 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11792 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11793 return -EINVAL;
11794 }
11795
11796 if (mode_changed && !crtc_state->active)
11797 intel_crtc->atomic.update_wm_post = true;
11798
11799 if (mode_changed && crtc_state->enable &&
11800 dev_priv->display.crtc_compute_clock &&
11801 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11802 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11803 pipe_config);
11804 if (ret)
11805 return ret;
11806 }
11807
11808 ret = 0;
11809 if (INTEL_INFO(dev)->gen >= 9) {
11810 if (mode_changed)
11811 ret = skl_update_scaler_crtc(pipe_config);
11812
11813 if (!ret)
11814 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11815 pipe_config);
11816 }
11817
11818 return ret;
11819 }
11820
11821 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11822 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11823 .load_lut = intel_crtc_load_lut,
11824 .atomic_begin = intel_begin_crtc_commit,
11825 .atomic_flush = intel_finish_crtc_commit,
11826 .atomic_check = intel_crtc_atomic_check,
11827 };
11828
11829 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11830 {
11831 struct intel_connector *connector;
11832
11833 for_each_intel_connector(dev, connector) {
11834 if (connector->base.encoder) {
11835 connector->base.state->best_encoder =
11836 connector->base.encoder;
11837 connector->base.state->crtc =
11838 connector->base.encoder->crtc;
11839 } else {
11840 connector->base.state->best_encoder = NULL;
11841 connector->base.state->crtc = NULL;
11842 }
11843 }
11844 }
11845
11846 static void
11847 connected_sink_compute_bpp(struct intel_connector *connector,
11848 struct intel_crtc_state *pipe_config)
11849 {
11850 int bpp = pipe_config->pipe_bpp;
11851
11852 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11853 connector->base.base.id,
11854 connector->base.name);
11855
11856 /* Don't use an invalid EDID bpc value */
11857 if (connector->base.display_info.bpc &&
11858 connector->base.display_info.bpc * 3 < bpp) {
11859 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11860 bpp, connector->base.display_info.bpc*3);
11861 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11862 }
11863
11864 /* Clamp bpp to 8 on screens without EDID 1.4 */
11865 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11866 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11867 bpp);
11868 pipe_config->pipe_bpp = 24;
11869 }
11870 }
11871
11872 static int
11873 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11874 struct intel_crtc_state *pipe_config)
11875 {
11876 struct drm_device *dev = crtc->base.dev;
11877 struct drm_atomic_state *state;
11878 struct drm_connector *connector;
11879 struct drm_connector_state *connector_state;
11880 int bpp, i;
11881
11882 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11883 bpp = 10*3;
11884 else if (INTEL_INFO(dev)->gen >= 5)
11885 bpp = 12*3;
11886 else
11887 bpp = 8*3;
11888
11889
11890 pipe_config->pipe_bpp = bpp;
11891
11892 state = pipe_config->base.state;
11893
11894 /* Clamp display bpp to EDID value */
11895 for_each_connector_in_state(state, connector, connector_state, i) {
11896 if (connector_state->crtc != &crtc->base)
11897 continue;
11898
11899 connected_sink_compute_bpp(to_intel_connector(connector),
11900 pipe_config);
11901 }
11902
11903 return bpp;
11904 }
11905
11906 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11907 {
11908 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11909 "type: 0x%x flags: 0x%x\n",
11910 mode->crtc_clock,
11911 mode->crtc_hdisplay, mode->crtc_hsync_start,
11912 mode->crtc_hsync_end, mode->crtc_htotal,
11913 mode->crtc_vdisplay, mode->crtc_vsync_start,
11914 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11915 }
11916
11917 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11918 struct intel_crtc_state *pipe_config,
11919 const char *context)
11920 {
11921 struct drm_device *dev = crtc->base.dev;
11922 struct drm_plane *plane;
11923 struct intel_plane *intel_plane;
11924 struct intel_plane_state *state;
11925 struct drm_framebuffer *fb;
11926
11927 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11928 context, pipe_config, pipe_name(crtc->pipe));
11929
11930 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11931 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11932 pipe_config->pipe_bpp, pipe_config->dither);
11933 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11934 pipe_config->has_pch_encoder,
11935 pipe_config->fdi_lanes,
11936 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11937 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11938 pipe_config->fdi_m_n.tu);
11939 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11940 pipe_config->has_dp_encoder,
11941 pipe_config->lane_count,
11942 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11943 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11944 pipe_config->dp_m_n.tu);
11945
11946 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11947 pipe_config->has_dp_encoder,
11948 pipe_config->lane_count,
11949 pipe_config->dp_m2_n2.gmch_m,
11950 pipe_config->dp_m2_n2.gmch_n,
11951 pipe_config->dp_m2_n2.link_m,
11952 pipe_config->dp_m2_n2.link_n,
11953 pipe_config->dp_m2_n2.tu);
11954
11955 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11956 pipe_config->has_audio,
11957 pipe_config->has_infoframe);
11958
11959 DRM_DEBUG_KMS("requested mode:\n");
11960 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11961 DRM_DEBUG_KMS("adjusted mode:\n");
11962 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11963 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11964 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11965 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11966 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11967 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11968 crtc->num_scalers,
11969 pipe_config->scaler_state.scaler_users,
11970 pipe_config->scaler_state.scaler_id);
11971 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11972 pipe_config->gmch_pfit.control,
11973 pipe_config->gmch_pfit.pgm_ratios,
11974 pipe_config->gmch_pfit.lvds_border_bits);
11975 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11976 pipe_config->pch_pfit.pos,
11977 pipe_config->pch_pfit.size,
11978 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11979 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11980 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11981
11982 if (IS_BROXTON(dev)) {
11983 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
11984 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11985 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
11986 pipe_config->ddi_pll_sel,
11987 pipe_config->dpll_hw_state.ebb0,
11988 pipe_config->dpll_hw_state.ebb4,
11989 pipe_config->dpll_hw_state.pll0,
11990 pipe_config->dpll_hw_state.pll1,
11991 pipe_config->dpll_hw_state.pll2,
11992 pipe_config->dpll_hw_state.pll3,
11993 pipe_config->dpll_hw_state.pll6,
11994 pipe_config->dpll_hw_state.pll8,
11995 pipe_config->dpll_hw_state.pll9,
11996 pipe_config->dpll_hw_state.pll10,
11997 pipe_config->dpll_hw_state.pcsdw12);
11998 } else if (IS_SKYLAKE(dev)) {
11999 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12000 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12001 pipe_config->ddi_pll_sel,
12002 pipe_config->dpll_hw_state.ctrl1,
12003 pipe_config->dpll_hw_state.cfgcr1,
12004 pipe_config->dpll_hw_state.cfgcr2);
12005 } else if (HAS_DDI(dev)) {
12006 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12007 pipe_config->ddi_pll_sel,
12008 pipe_config->dpll_hw_state.wrpll);
12009 } else {
12010 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12011 "fp0: 0x%x, fp1: 0x%x\n",
12012 pipe_config->dpll_hw_state.dpll,
12013 pipe_config->dpll_hw_state.dpll_md,
12014 pipe_config->dpll_hw_state.fp0,
12015 pipe_config->dpll_hw_state.fp1);
12016 }
12017
12018 DRM_DEBUG_KMS("planes on this crtc\n");
12019 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12020 intel_plane = to_intel_plane(plane);
12021 if (intel_plane->pipe != crtc->pipe)
12022 continue;
12023
12024 state = to_intel_plane_state(plane->state);
12025 fb = state->base.fb;
12026 if (!fb) {
12027 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12028 "disabled, scaler_id = %d\n",
12029 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12030 plane->base.id, intel_plane->pipe,
12031 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12032 drm_plane_index(plane), state->scaler_id);
12033 continue;
12034 }
12035
12036 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12037 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12038 plane->base.id, intel_plane->pipe,
12039 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12040 drm_plane_index(plane));
12041 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12042 fb->base.id, fb->width, fb->height, fb->pixel_format);
12043 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12044 state->scaler_id,
12045 state->src.x1 >> 16, state->src.y1 >> 16,
12046 drm_rect_width(&state->src) >> 16,
12047 drm_rect_height(&state->src) >> 16,
12048 state->dst.x1, state->dst.y1,
12049 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12050 }
12051 }
12052
12053 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12054 {
12055 struct drm_device *dev = state->dev;
12056 struct intel_encoder *encoder;
12057 struct drm_connector *connector;
12058 struct drm_connector_state *connector_state;
12059 unsigned int used_ports = 0;
12060 int i;
12061
12062 /*
12063 * Walk the connector list instead of the encoder
12064 * list to detect the problem on ddi platforms
12065 * where there's just one encoder per digital port.
12066 */
12067 for_each_connector_in_state(state, connector, connector_state, i) {
12068 if (!connector_state->best_encoder)
12069 continue;
12070
12071 encoder = to_intel_encoder(connector_state->best_encoder);
12072
12073 WARN_ON(!connector_state->crtc);
12074
12075 switch (encoder->type) {
12076 unsigned int port_mask;
12077 case INTEL_OUTPUT_UNKNOWN:
12078 if (WARN_ON(!HAS_DDI(dev)))
12079 break;
12080 case INTEL_OUTPUT_DISPLAYPORT:
12081 case INTEL_OUTPUT_HDMI:
12082 case INTEL_OUTPUT_EDP:
12083 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12084
12085 /* the same port mustn't appear more than once */
12086 if (used_ports & port_mask)
12087 return false;
12088
12089 used_ports |= port_mask;
12090 default:
12091 break;
12092 }
12093 }
12094
12095 return true;
12096 }
12097
12098 static void
12099 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12100 {
12101 struct drm_crtc_state tmp_state;
12102 struct intel_crtc_scaler_state scaler_state;
12103 struct intel_dpll_hw_state dpll_hw_state;
12104 enum intel_dpll_id shared_dpll;
12105 uint32_t ddi_pll_sel;
12106 bool force_thru;
12107
12108 /* FIXME: before the switch to atomic started, a new pipe_config was
12109 * kzalloc'd. Code that depends on any field being zero should be
12110 * fixed, so that the crtc_state can be safely duplicated. For now,
12111 * only fields that are know to not cause problems are preserved. */
12112
12113 tmp_state = crtc_state->base;
12114 scaler_state = crtc_state->scaler_state;
12115 shared_dpll = crtc_state->shared_dpll;
12116 dpll_hw_state = crtc_state->dpll_hw_state;
12117 ddi_pll_sel = crtc_state->ddi_pll_sel;
12118 force_thru = crtc_state->pch_pfit.force_thru;
12119
12120 memset(crtc_state, 0, sizeof *crtc_state);
12121
12122 crtc_state->base = tmp_state;
12123 crtc_state->scaler_state = scaler_state;
12124 crtc_state->shared_dpll = shared_dpll;
12125 crtc_state->dpll_hw_state = dpll_hw_state;
12126 crtc_state->ddi_pll_sel = ddi_pll_sel;
12127 crtc_state->pch_pfit.force_thru = force_thru;
12128 }
12129
12130 static int
12131 intel_modeset_pipe_config(struct drm_crtc *crtc,
12132 struct intel_crtc_state *pipe_config)
12133 {
12134 struct drm_atomic_state *state = pipe_config->base.state;
12135 struct intel_encoder *encoder;
12136 struct drm_connector *connector;
12137 struct drm_connector_state *connector_state;
12138 int base_bpp, ret = -EINVAL;
12139 int i;
12140 bool retry = true;
12141
12142 clear_intel_crtc_state(pipe_config);
12143
12144 pipe_config->cpu_transcoder =
12145 (enum transcoder) to_intel_crtc(crtc)->pipe;
12146
12147 /*
12148 * Sanitize sync polarity flags based on requested ones. If neither
12149 * positive or negative polarity is requested, treat this as meaning
12150 * negative polarity.
12151 */
12152 if (!(pipe_config->base.adjusted_mode.flags &
12153 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12154 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12155
12156 if (!(pipe_config->base.adjusted_mode.flags &
12157 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12158 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12159
12160 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12161 pipe_config);
12162 if (base_bpp < 0)
12163 goto fail;
12164
12165 /*
12166 * Determine the real pipe dimensions. Note that stereo modes can
12167 * increase the actual pipe size due to the frame doubling and
12168 * insertion of additional space for blanks between the frame. This
12169 * is stored in the crtc timings. We use the requested mode to do this
12170 * computation to clearly distinguish it from the adjusted mode, which
12171 * can be changed by the connectors in the below retry loop.
12172 */
12173 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12174 &pipe_config->pipe_src_w,
12175 &pipe_config->pipe_src_h);
12176
12177 encoder_retry:
12178 /* Ensure the port clock defaults are reset when retrying. */
12179 pipe_config->port_clock = 0;
12180 pipe_config->pixel_multiplier = 1;
12181
12182 /* Fill in default crtc timings, allow encoders to overwrite them. */
12183 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12184 CRTC_STEREO_DOUBLE);
12185
12186 /* Pass our mode to the connectors and the CRTC to give them a chance to
12187 * adjust it according to limitations or connector properties, and also
12188 * a chance to reject the mode entirely.
12189 */
12190 for_each_connector_in_state(state, connector, connector_state, i) {
12191 if (connector_state->crtc != crtc)
12192 continue;
12193
12194 encoder = to_intel_encoder(connector_state->best_encoder);
12195
12196 if (!(encoder->compute_config(encoder, pipe_config))) {
12197 DRM_DEBUG_KMS("Encoder config failure\n");
12198 goto fail;
12199 }
12200 }
12201
12202 /* Set default port clock if not overwritten by the encoder. Needs to be
12203 * done afterwards in case the encoder adjusts the mode. */
12204 if (!pipe_config->port_clock)
12205 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12206 * pipe_config->pixel_multiplier;
12207
12208 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12209 if (ret < 0) {
12210 DRM_DEBUG_KMS("CRTC fixup failed\n");
12211 goto fail;
12212 }
12213
12214 if (ret == RETRY) {
12215 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12216 ret = -EINVAL;
12217 goto fail;
12218 }
12219
12220 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12221 retry = false;
12222 goto encoder_retry;
12223 }
12224
12225 /* Dithering seems to not pass-through bits correctly when it should, so
12226 * only enable it on 6bpc panels. */
12227 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12228 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12229 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12230
12231 fail:
12232 return ret;
12233 }
12234
12235 static void
12236 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12237 {
12238 struct drm_crtc *crtc;
12239 struct drm_crtc_state *crtc_state;
12240 int i;
12241
12242 /* Double check state. */
12243 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12244 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12245
12246 /* Update hwmode for vblank functions */
12247 if (crtc->state->active)
12248 crtc->hwmode = crtc->state->adjusted_mode;
12249 else
12250 crtc->hwmode.crtc_clock = 0;
12251 }
12252 }
12253
12254 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12255 {
12256 int diff;
12257
12258 if (clock1 == clock2)
12259 return true;
12260
12261 if (!clock1 || !clock2)
12262 return false;
12263
12264 diff = abs(clock1 - clock2);
12265
12266 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12267 return true;
12268
12269 return false;
12270 }
12271
12272 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12273 list_for_each_entry((intel_crtc), \
12274 &(dev)->mode_config.crtc_list, \
12275 base.head) \
12276 if (mask & (1 <<(intel_crtc)->pipe))
12277
12278 static bool
12279 intel_compare_m_n(unsigned int m, unsigned int n,
12280 unsigned int m2, unsigned int n2,
12281 bool exact)
12282 {
12283 if (m == m2 && n == n2)
12284 return true;
12285
12286 if (exact || !m || !n || !m2 || !n2)
12287 return false;
12288
12289 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12290
12291 if (m > m2) {
12292 while (m > m2) {
12293 m2 <<= 1;
12294 n2 <<= 1;
12295 }
12296 } else if (m < m2) {
12297 while (m < m2) {
12298 m <<= 1;
12299 n <<= 1;
12300 }
12301 }
12302
12303 return m == m2 && n == n2;
12304 }
12305
12306 static bool
12307 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12308 struct intel_link_m_n *m2_n2,
12309 bool adjust)
12310 {
12311 if (m_n->tu == m2_n2->tu &&
12312 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12313 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12314 intel_compare_m_n(m_n->link_m, m_n->link_n,
12315 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12316 if (adjust)
12317 *m2_n2 = *m_n;
12318
12319 return true;
12320 }
12321
12322 return false;
12323 }
12324
12325 static bool
12326 intel_pipe_config_compare(struct drm_device *dev,
12327 struct intel_crtc_state *current_config,
12328 struct intel_crtc_state *pipe_config,
12329 bool adjust)
12330 {
12331 bool ret = true;
12332
12333 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12334 do { \
12335 if (!adjust) \
12336 DRM_ERROR(fmt, ##__VA_ARGS__); \
12337 else \
12338 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12339 } while (0)
12340
12341 #define PIPE_CONF_CHECK_X(name) \
12342 if (current_config->name != pipe_config->name) { \
12343 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12344 "(expected 0x%08x, found 0x%08x)\n", \
12345 current_config->name, \
12346 pipe_config->name); \
12347 ret = false; \
12348 }
12349
12350 #define PIPE_CONF_CHECK_I(name) \
12351 if (current_config->name != pipe_config->name) { \
12352 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12353 "(expected %i, found %i)\n", \
12354 current_config->name, \
12355 pipe_config->name); \
12356 ret = false; \
12357 }
12358
12359 #define PIPE_CONF_CHECK_M_N(name) \
12360 if (!intel_compare_link_m_n(&current_config->name, \
12361 &pipe_config->name,\
12362 adjust)) { \
12363 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12364 "(expected tu %i gmch %i/%i link %i/%i, " \
12365 "found tu %i, gmch %i/%i link %i/%i)\n", \
12366 current_config->name.tu, \
12367 current_config->name.gmch_m, \
12368 current_config->name.gmch_n, \
12369 current_config->name.link_m, \
12370 current_config->name.link_n, \
12371 pipe_config->name.tu, \
12372 pipe_config->name.gmch_m, \
12373 pipe_config->name.gmch_n, \
12374 pipe_config->name.link_m, \
12375 pipe_config->name.link_n); \
12376 ret = false; \
12377 }
12378
12379 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12380 if (!intel_compare_link_m_n(&current_config->name, \
12381 &pipe_config->name, adjust) && \
12382 !intel_compare_link_m_n(&current_config->alt_name, \
12383 &pipe_config->name, adjust)) { \
12384 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12385 "(expected tu %i gmch %i/%i link %i/%i, " \
12386 "or tu %i gmch %i/%i link %i/%i, " \
12387 "found tu %i, gmch %i/%i link %i/%i)\n", \
12388 current_config->name.tu, \
12389 current_config->name.gmch_m, \
12390 current_config->name.gmch_n, \
12391 current_config->name.link_m, \
12392 current_config->name.link_n, \
12393 current_config->alt_name.tu, \
12394 current_config->alt_name.gmch_m, \
12395 current_config->alt_name.gmch_n, \
12396 current_config->alt_name.link_m, \
12397 current_config->alt_name.link_n, \
12398 pipe_config->name.tu, \
12399 pipe_config->name.gmch_m, \
12400 pipe_config->name.gmch_n, \
12401 pipe_config->name.link_m, \
12402 pipe_config->name.link_n); \
12403 ret = false; \
12404 }
12405
12406 /* This is required for BDW+ where there is only one set of registers for
12407 * switching between high and low RR.
12408 * This macro can be used whenever a comparison has to be made between one
12409 * hw state and multiple sw state variables.
12410 */
12411 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12412 if ((current_config->name != pipe_config->name) && \
12413 (current_config->alt_name != pipe_config->name)) { \
12414 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12415 "(expected %i or %i, found %i)\n", \
12416 current_config->name, \
12417 current_config->alt_name, \
12418 pipe_config->name); \
12419 ret = false; \
12420 }
12421
12422 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12423 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12424 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12425 "(expected %i, found %i)\n", \
12426 current_config->name & (mask), \
12427 pipe_config->name & (mask)); \
12428 ret = false; \
12429 }
12430
12431 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12432 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12433 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12434 "(expected %i, found %i)\n", \
12435 current_config->name, \
12436 pipe_config->name); \
12437 ret = false; \
12438 }
12439
12440 #define PIPE_CONF_QUIRK(quirk) \
12441 ((current_config->quirks | pipe_config->quirks) & (quirk))
12442
12443 PIPE_CONF_CHECK_I(cpu_transcoder);
12444
12445 PIPE_CONF_CHECK_I(has_pch_encoder);
12446 PIPE_CONF_CHECK_I(fdi_lanes);
12447 PIPE_CONF_CHECK_M_N(fdi_m_n);
12448
12449 PIPE_CONF_CHECK_I(has_dp_encoder);
12450 PIPE_CONF_CHECK_I(lane_count);
12451
12452 if (INTEL_INFO(dev)->gen < 8) {
12453 PIPE_CONF_CHECK_M_N(dp_m_n);
12454
12455 PIPE_CONF_CHECK_I(has_drrs);
12456 if (current_config->has_drrs)
12457 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12458 } else
12459 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12460
12461 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12462 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12463 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12464 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12465 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12466 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12467
12468 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12469 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12470 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12471 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12472 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12473 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12474
12475 PIPE_CONF_CHECK_I(pixel_multiplier);
12476 PIPE_CONF_CHECK_I(has_hdmi_sink);
12477 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12478 IS_VALLEYVIEW(dev))
12479 PIPE_CONF_CHECK_I(limited_color_range);
12480 PIPE_CONF_CHECK_I(has_infoframe);
12481
12482 PIPE_CONF_CHECK_I(has_audio);
12483
12484 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12485 DRM_MODE_FLAG_INTERLACE);
12486
12487 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12488 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12489 DRM_MODE_FLAG_PHSYNC);
12490 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12491 DRM_MODE_FLAG_NHSYNC);
12492 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12493 DRM_MODE_FLAG_PVSYNC);
12494 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12495 DRM_MODE_FLAG_NVSYNC);
12496 }
12497
12498 PIPE_CONF_CHECK_X(gmch_pfit.control);
12499 /* pfit ratios are autocomputed by the hw on gen4+ */
12500 if (INTEL_INFO(dev)->gen < 4)
12501 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12502 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12503
12504 if (!adjust) {
12505 PIPE_CONF_CHECK_I(pipe_src_w);
12506 PIPE_CONF_CHECK_I(pipe_src_h);
12507
12508 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12509 if (current_config->pch_pfit.enabled) {
12510 PIPE_CONF_CHECK_X(pch_pfit.pos);
12511 PIPE_CONF_CHECK_X(pch_pfit.size);
12512 }
12513
12514 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12515 }
12516
12517 /* BDW+ don't expose a synchronous way to read the state */
12518 if (IS_HASWELL(dev))
12519 PIPE_CONF_CHECK_I(ips_enabled);
12520
12521 PIPE_CONF_CHECK_I(double_wide);
12522
12523 PIPE_CONF_CHECK_X(ddi_pll_sel);
12524
12525 PIPE_CONF_CHECK_I(shared_dpll);
12526 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12527 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12528 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12529 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12530 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12531 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12532 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12533 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12534
12535 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12536 PIPE_CONF_CHECK_I(pipe_bpp);
12537
12538 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12539 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12540
12541 #undef PIPE_CONF_CHECK_X
12542 #undef PIPE_CONF_CHECK_I
12543 #undef PIPE_CONF_CHECK_I_ALT
12544 #undef PIPE_CONF_CHECK_FLAGS
12545 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12546 #undef PIPE_CONF_QUIRK
12547 #undef INTEL_ERR_OR_DBG_KMS
12548
12549 return ret;
12550 }
12551
12552 static void check_wm_state(struct drm_device *dev)
12553 {
12554 struct drm_i915_private *dev_priv = dev->dev_private;
12555 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12556 struct intel_crtc *intel_crtc;
12557 int plane;
12558
12559 if (INTEL_INFO(dev)->gen < 9)
12560 return;
12561
12562 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12563 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12564
12565 for_each_intel_crtc(dev, intel_crtc) {
12566 struct skl_ddb_entry *hw_entry, *sw_entry;
12567 const enum pipe pipe = intel_crtc->pipe;
12568
12569 if (!intel_crtc->active)
12570 continue;
12571
12572 /* planes */
12573 for_each_plane(dev_priv, pipe, plane) {
12574 hw_entry = &hw_ddb.plane[pipe][plane];
12575 sw_entry = &sw_ddb->plane[pipe][plane];
12576
12577 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12578 continue;
12579
12580 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12581 "(expected (%u,%u), found (%u,%u))\n",
12582 pipe_name(pipe), plane + 1,
12583 sw_entry->start, sw_entry->end,
12584 hw_entry->start, hw_entry->end);
12585 }
12586
12587 /* cursor */
12588 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12589 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12590
12591 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12592 continue;
12593
12594 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12595 "(expected (%u,%u), found (%u,%u))\n",
12596 pipe_name(pipe),
12597 sw_entry->start, sw_entry->end,
12598 hw_entry->start, hw_entry->end);
12599 }
12600 }
12601
12602 static void
12603 check_connector_state(struct drm_device *dev,
12604 struct drm_atomic_state *old_state)
12605 {
12606 struct drm_connector_state *old_conn_state;
12607 struct drm_connector *connector;
12608 int i;
12609
12610 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12611 struct drm_encoder *encoder = connector->encoder;
12612 struct drm_connector_state *state = connector->state;
12613
12614 /* This also checks the encoder/connector hw state with the
12615 * ->get_hw_state callbacks. */
12616 intel_connector_check_state(to_intel_connector(connector));
12617
12618 I915_STATE_WARN(state->best_encoder != encoder,
12619 "connector's atomic encoder doesn't match legacy encoder\n");
12620 }
12621 }
12622
12623 static void
12624 check_encoder_state(struct drm_device *dev)
12625 {
12626 struct intel_encoder *encoder;
12627 struct intel_connector *connector;
12628
12629 for_each_intel_encoder(dev, encoder) {
12630 bool enabled = false;
12631 enum pipe pipe;
12632
12633 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12634 encoder->base.base.id,
12635 encoder->base.name);
12636
12637 for_each_intel_connector(dev, connector) {
12638 if (connector->base.state->best_encoder != &encoder->base)
12639 continue;
12640 enabled = true;
12641
12642 I915_STATE_WARN(connector->base.state->crtc !=
12643 encoder->base.crtc,
12644 "connector's crtc doesn't match encoder crtc\n");
12645 }
12646
12647 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12648 "encoder's enabled state mismatch "
12649 "(expected %i, found %i)\n",
12650 !!encoder->base.crtc, enabled);
12651
12652 if (!encoder->base.crtc) {
12653 bool active;
12654
12655 active = encoder->get_hw_state(encoder, &pipe);
12656 I915_STATE_WARN(active,
12657 "encoder detached but still enabled on pipe %c.\n",
12658 pipe_name(pipe));
12659 }
12660 }
12661 }
12662
12663 static void
12664 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12665 {
12666 struct drm_i915_private *dev_priv = dev->dev_private;
12667 struct intel_encoder *encoder;
12668 struct drm_crtc_state *old_crtc_state;
12669 struct drm_crtc *crtc;
12670 int i;
12671
12672 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12674 struct intel_crtc_state *pipe_config, *sw_config;
12675 bool active;
12676
12677 if (!needs_modeset(crtc->state) &&
12678 !to_intel_crtc_state(crtc->state)->update_pipe)
12679 continue;
12680
12681 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12682 pipe_config = to_intel_crtc_state(old_crtc_state);
12683 memset(pipe_config, 0, sizeof(*pipe_config));
12684 pipe_config->base.crtc = crtc;
12685 pipe_config->base.state = old_state;
12686
12687 DRM_DEBUG_KMS("[CRTC:%d]\n",
12688 crtc->base.id);
12689
12690 active = dev_priv->display.get_pipe_config(intel_crtc,
12691 pipe_config);
12692
12693 /* hw state is inconsistent with the pipe quirk */
12694 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12695 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12696 active = crtc->state->active;
12697
12698 I915_STATE_WARN(crtc->state->active != active,
12699 "crtc active state doesn't match with hw state "
12700 "(expected %i, found %i)\n", crtc->state->active, active);
12701
12702 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12703 "transitional active state does not match atomic hw state "
12704 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12705
12706 for_each_encoder_on_crtc(dev, crtc, encoder) {
12707 enum pipe pipe;
12708
12709 active = encoder->get_hw_state(encoder, &pipe);
12710 I915_STATE_WARN(active != crtc->state->active,
12711 "[ENCODER:%i] active %i with crtc active %i\n",
12712 encoder->base.base.id, active, crtc->state->active);
12713
12714 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12715 "Encoder connected to wrong pipe %c\n",
12716 pipe_name(pipe));
12717
12718 if (active)
12719 encoder->get_config(encoder, pipe_config);
12720 }
12721
12722 if (!crtc->state->active)
12723 continue;
12724
12725 sw_config = to_intel_crtc_state(crtc->state);
12726 if (!intel_pipe_config_compare(dev, sw_config,
12727 pipe_config, false)) {
12728 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12729 intel_dump_pipe_config(intel_crtc, pipe_config,
12730 "[hw state]");
12731 intel_dump_pipe_config(intel_crtc, sw_config,
12732 "[sw state]");
12733 }
12734 }
12735 }
12736
12737 static void
12738 check_shared_dpll_state(struct drm_device *dev)
12739 {
12740 struct drm_i915_private *dev_priv = dev->dev_private;
12741 struct intel_crtc *crtc;
12742 struct intel_dpll_hw_state dpll_hw_state;
12743 int i;
12744
12745 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12746 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12747 int enabled_crtcs = 0, active_crtcs = 0;
12748 bool active;
12749
12750 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12751
12752 DRM_DEBUG_KMS("%s\n", pll->name);
12753
12754 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12755
12756 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12757 "more active pll users than references: %i vs %i\n",
12758 pll->active, hweight32(pll->config.crtc_mask));
12759 I915_STATE_WARN(pll->active && !pll->on,
12760 "pll in active use but not on in sw tracking\n");
12761 I915_STATE_WARN(pll->on && !pll->active,
12762 "pll in on but not on in use in sw tracking\n");
12763 I915_STATE_WARN(pll->on != active,
12764 "pll on state mismatch (expected %i, found %i)\n",
12765 pll->on, active);
12766
12767 for_each_intel_crtc(dev, crtc) {
12768 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12769 enabled_crtcs++;
12770 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12771 active_crtcs++;
12772 }
12773 I915_STATE_WARN(pll->active != active_crtcs,
12774 "pll active crtcs mismatch (expected %i, found %i)\n",
12775 pll->active, active_crtcs);
12776 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12777 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12778 hweight32(pll->config.crtc_mask), enabled_crtcs);
12779
12780 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12781 sizeof(dpll_hw_state)),
12782 "pll hw state mismatch\n");
12783 }
12784 }
12785
12786 static void
12787 intel_modeset_check_state(struct drm_device *dev,
12788 struct drm_atomic_state *old_state)
12789 {
12790 check_wm_state(dev);
12791 check_connector_state(dev, old_state);
12792 check_encoder_state(dev);
12793 check_crtc_state(dev, old_state);
12794 check_shared_dpll_state(dev);
12795 }
12796
12797 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12798 int dotclock)
12799 {
12800 /*
12801 * FDI already provided one idea for the dotclock.
12802 * Yell if the encoder disagrees.
12803 */
12804 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12805 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12806 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12807 }
12808
12809 static void update_scanline_offset(struct intel_crtc *crtc)
12810 {
12811 struct drm_device *dev = crtc->base.dev;
12812
12813 /*
12814 * The scanline counter increments at the leading edge of hsync.
12815 *
12816 * On most platforms it starts counting from vtotal-1 on the
12817 * first active line. That means the scanline counter value is
12818 * always one less than what we would expect. Ie. just after
12819 * start of vblank, which also occurs at start of hsync (on the
12820 * last active line), the scanline counter will read vblank_start-1.
12821 *
12822 * On gen2 the scanline counter starts counting from 1 instead
12823 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12824 * to keep the value positive), instead of adding one.
12825 *
12826 * On HSW+ the behaviour of the scanline counter depends on the output
12827 * type. For DP ports it behaves like most other platforms, but on HDMI
12828 * there's an extra 1 line difference. So we need to add two instead of
12829 * one to the value.
12830 */
12831 if (IS_GEN2(dev)) {
12832 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12833 int vtotal;
12834
12835 vtotal = adjusted_mode->crtc_vtotal;
12836 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12837 vtotal /= 2;
12838
12839 crtc->scanline_offset = vtotal - 1;
12840 } else if (HAS_DDI(dev) &&
12841 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12842 crtc->scanline_offset = 2;
12843 } else
12844 crtc->scanline_offset = 1;
12845 }
12846
12847 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12848 {
12849 struct drm_device *dev = state->dev;
12850 struct drm_i915_private *dev_priv = to_i915(dev);
12851 struct intel_shared_dpll_config *shared_dpll = NULL;
12852 struct intel_crtc *intel_crtc;
12853 struct intel_crtc_state *intel_crtc_state;
12854 struct drm_crtc *crtc;
12855 struct drm_crtc_state *crtc_state;
12856 int i;
12857
12858 if (!dev_priv->display.crtc_compute_clock)
12859 return;
12860
12861 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12862 int dpll;
12863
12864 intel_crtc = to_intel_crtc(crtc);
12865 intel_crtc_state = to_intel_crtc_state(crtc_state);
12866 dpll = intel_crtc_state->shared_dpll;
12867
12868 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12869 continue;
12870
12871 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12872
12873 if (!shared_dpll)
12874 shared_dpll = intel_atomic_get_shared_dpll_state(state);
12875
12876 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12877 }
12878 }
12879
12880 /*
12881 * This implements the workaround described in the "notes" section of the mode
12882 * set sequence documentation. When going from no pipes or single pipe to
12883 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12884 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12885 */
12886 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12887 {
12888 struct drm_crtc_state *crtc_state;
12889 struct intel_crtc *intel_crtc;
12890 struct drm_crtc *crtc;
12891 struct intel_crtc_state *first_crtc_state = NULL;
12892 struct intel_crtc_state *other_crtc_state = NULL;
12893 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12894 int i;
12895
12896 /* look at all crtc's that are going to be enabled in during modeset */
12897 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12898 intel_crtc = to_intel_crtc(crtc);
12899
12900 if (!crtc_state->active || !needs_modeset(crtc_state))
12901 continue;
12902
12903 if (first_crtc_state) {
12904 other_crtc_state = to_intel_crtc_state(crtc_state);
12905 break;
12906 } else {
12907 first_crtc_state = to_intel_crtc_state(crtc_state);
12908 first_pipe = intel_crtc->pipe;
12909 }
12910 }
12911
12912 /* No workaround needed? */
12913 if (!first_crtc_state)
12914 return 0;
12915
12916 /* w/a possibly needed, check how many crtc's are already enabled. */
12917 for_each_intel_crtc(state->dev, intel_crtc) {
12918 struct intel_crtc_state *pipe_config;
12919
12920 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12921 if (IS_ERR(pipe_config))
12922 return PTR_ERR(pipe_config);
12923
12924 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12925
12926 if (!pipe_config->base.active ||
12927 needs_modeset(&pipe_config->base))
12928 continue;
12929
12930 /* 2 or more enabled crtcs means no need for w/a */
12931 if (enabled_pipe != INVALID_PIPE)
12932 return 0;
12933
12934 enabled_pipe = intel_crtc->pipe;
12935 }
12936
12937 if (enabled_pipe != INVALID_PIPE)
12938 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12939 else if (other_crtc_state)
12940 other_crtc_state->hsw_workaround_pipe = first_pipe;
12941
12942 return 0;
12943 }
12944
12945 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12946 {
12947 struct drm_crtc *crtc;
12948 struct drm_crtc_state *crtc_state;
12949 int ret = 0;
12950
12951 /* add all active pipes to the state */
12952 for_each_crtc(state->dev, crtc) {
12953 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12954 if (IS_ERR(crtc_state))
12955 return PTR_ERR(crtc_state);
12956
12957 if (!crtc_state->active || needs_modeset(crtc_state))
12958 continue;
12959
12960 crtc_state->mode_changed = true;
12961
12962 ret = drm_atomic_add_affected_connectors(state, crtc);
12963 if (ret)
12964 break;
12965
12966 ret = drm_atomic_add_affected_planes(state, crtc);
12967 if (ret)
12968 break;
12969 }
12970
12971 return ret;
12972 }
12973
12974 static int intel_modeset_checks(struct drm_atomic_state *state)
12975 {
12976 struct drm_device *dev = state->dev;
12977 struct drm_i915_private *dev_priv = dev->dev_private;
12978 int ret;
12979
12980 if (!check_digital_port_conflicts(state)) {
12981 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12982 return -EINVAL;
12983 }
12984
12985 /*
12986 * See if the config requires any additional preparation, e.g.
12987 * to adjust global state with pipes off. We need to do this
12988 * here so we can get the modeset_pipe updated config for the new
12989 * mode set on this crtc. For other crtcs we need to use the
12990 * adjusted_mode bits in the crtc directly.
12991 */
12992 if (dev_priv->display.modeset_calc_cdclk) {
12993 unsigned int cdclk;
12994
12995 ret = dev_priv->display.modeset_calc_cdclk(state);
12996
12997 cdclk = to_intel_atomic_state(state)->cdclk;
12998 if (!ret && cdclk != dev_priv->cdclk_freq)
12999 ret = intel_modeset_all_pipes(state);
13000
13001 if (ret < 0)
13002 return ret;
13003 } else
13004 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13005
13006 intel_modeset_clear_plls(state);
13007
13008 if (IS_HASWELL(dev))
13009 return haswell_mode_set_planes_workaround(state);
13010
13011 return 0;
13012 }
13013
13014 /**
13015 * intel_atomic_check - validate state object
13016 * @dev: drm device
13017 * @state: state to validate
13018 */
13019 static int intel_atomic_check(struct drm_device *dev,
13020 struct drm_atomic_state *state)
13021 {
13022 struct drm_crtc *crtc;
13023 struct drm_crtc_state *crtc_state;
13024 int ret, i;
13025 bool any_ms = false;
13026
13027 ret = drm_atomic_helper_check_modeset(dev, state);
13028 if (ret)
13029 return ret;
13030
13031 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13032 struct intel_crtc_state *pipe_config =
13033 to_intel_crtc_state(crtc_state);
13034
13035 /* Catch I915_MODE_FLAG_INHERITED */
13036 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13037 crtc_state->mode_changed = true;
13038
13039 if (!crtc_state->enable) {
13040 if (needs_modeset(crtc_state))
13041 any_ms = true;
13042 continue;
13043 }
13044
13045 if (!needs_modeset(crtc_state))
13046 continue;
13047
13048 /* FIXME: For only active_changed we shouldn't need to do any
13049 * state recomputation at all. */
13050
13051 ret = drm_atomic_add_affected_connectors(state, crtc);
13052 if (ret)
13053 return ret;
13054
13055 ret = intel_modeset_pipe_config(crtc, pipe_config);
13056 if (ret)
13057 return ret;
13058
13059 if (intel_pipe_config_compare(state->dev,
13060 to_intel_crtc_state(crtc->state),
13061 pipe_config, true)) {
13062 crtc_state->mode_changed = false;
13063 to_intel_crtc_state(crtc_state)->update_pipe = true;
13064 }
13065
13066 if (needs_modeset(crtc_state)) {
13067 any_ms = true;
13068
13069 ret = drm_atomic_add_affected_planes(state, crtc);
13070 if (ret)
13071 return ret;
13072 }
13073
13074 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13075 needs_modeset(crtc_state) ?
13076 "[modeset]" : "[fastset]");
13077 }
13078
13079 if (any_ms) {
13080 ret = intel_modeset_checks(state);
13081
13082 if (ret)
13083 return ret;
13084 } else
13085 to_intel_atomic_state(state)->cdclk =
13086 to_i915(state->dev)->cdclk_freq;
13087
13088 return drm_atomic_helper_check_planes(state->dev, state);
13089 }
13090
13091 /**
13092 * intel_atomic_commit - commit validated state object
13093 * @dev: DRM device
13094 * @state: the top-level driver state object
13095 * @async: asynchronous commit
13096 *
13097 * This function commits a top-level state object that has been validated
13098 * with drm_atomic_helper_check().
13099 *
13100 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13101 * we can only handle plane-related operations and do not yet support
13102 * asynchronous commit.
13103 *
13104 * RETURNS
13105 * Zero for success or -errno.
13106 */
13107 static int intel_atomic_commit(struct drm_device *dev,
13108 struct drm_atomic_state *state,
13109 bool async)
13110 {
13111 struct drm_i915_private *dev_priv = dev->dev_private;
13112 struct drm_crtc *crtc;
13113 struct drm_crtc_state *crtc_state;
13114 int ret = 0;
13115 int i;
13116 bool any_ms = false;
13117
13118 if (async) {
13119 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13120 return -EINVAL;
13121 }
13122
13123 ret = drm_atomic_helper_prepare_planes(dev, state);
13124 if (ret)
13125 return ret;
13126
13127 drm_atomic_helper_swap_state(dev, state);
13128
13129 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13131
13132 if (!needs_modeset(crtc->state))
13133 continue;
13134
13135 any_ms = true;
13136 intel_pre_plane_update(intel_crtc);
13137
13138 if (crtc_state->active) {
13139 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13140 dev_priv->display.crtc_disable(crtc);
13141 intel_crtc->active = false;
13142 intel_disable_shared_dpll(intel_crtc);
13143 }
13144 }
13145
13146 /* Only after disabling all output pipelines that will be changed can we
13147 * update the the output configuration. */
13148 intel_modeset_update_crtc_state(state);
13149
13150 if (any_ms) {
13151 intel_shared_dpll_commit(state);
13152
13153 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13154 modeset_update_crtc_power_domains(state);
13155 }
13156
13157 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13158 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13160 bool modeset = needs_modeset(crtc->state);
13161 bool update_pipe = !modeset &&
13162 to_intel_crtc_state(crtc->state)->update_pipe;
13163 unsigned long put_domains = 0;
13164
13165 if (modeset && crtc->state->active) {
13166 update_scanline_offset(to_intel_crtc(crtc));
13167 dev_priv->display.crtc_enable(crtc);
13168 }
13169
13170 if (update_pipe) {
13171 put_domains = modeset_get_crtc_power_domains(crtc);
13172
13173 /* make sure intel_modeset_check_state runs */
13174 any_ms = true;
13175 }
13176
13177 if (!modeset)
13178 intel_pre_plane_update(intel_crtc);
13179
13180 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13181
13182 if (put_domains)
13183 modeset_put_power_domains(dev_priv, put_domains);
13184
13185 intel_post_plane_update(intel_crtc);
13186 }
13187
13188 /* FIXME: add subpixel order */
13189
13190 drm_atomic_helper_wait_for_vblanks(dev, state);
13191 drm_atomic_helper_cleanup_planes(dev, state);
13192
13193 if (any_ms)
13194 intel_modeset_check_state(dev, state);
13195
13196 drm_atomic_state_free(state);
13197
13198 return 0;
13199 }
13200
13201 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13202 {
13203 struct drm_device *dev = crtc->dev;
13204 struct drm_atomic_state *state;
13205 struct drm_crtc_state *crtc_state;
13206 int ret;
13207
13208 state = drm_atomic_state_alloc(dev);
13209 if (!state) {
13210 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13211 crtc->base.id);
13212 return;
13213 }
13214
13215 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13216
13217 retry:
13218 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13219 ret = PTR_ERR_OR_ZERO(crtc_state);
13220 if (!ret) {
13221 if (!crtc_state->active)
13222 goto out;
13223
13224 crtc_state->mode_changed = true;
13225 ret = drm_atomic_commit(state);
13226 }
13227
13228 if (ret == -EDEADLK) {
13229 drm_atomic_state_clear(state);
13230 drm_modeset_backoff(state->acquire_ctx);
13231 goto retry;
13232 }
13233
13234 if (ret)
13235 out:
13236 drm_atomic_state_free(state);
13237 }
13238
13239 #undef for_each_intel_crtc_masked
13240
13241 static const struct drm_crtc_funcs intel_crtc_funcs = {
13242 .gamma_set = intel_crtc_gamma_set,
13243 .set_config = drm_atomic_helper_set_config,
13244 .destroy = intel_crtc_destroy,
13245 .page_flip = intel_crtc_page_flip,
13246 .atomic_duplicate_state = intel_crtc_duplicate_state,
13247 .atomic_destroy_state = intel_crtc_destroy_state,
13248 };
13249
13250 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13251 struct intel_shared_dpll *pll,
13252 struct intel_dpll_hw_state *hw_state)
13253 {
13254 uint32_t val;
13255
13256 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13257 return false;
13258
13259 val = I915_READ(PCH_DPLL(pll->id));
13260 hw_state->dpll = val;
13261 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13262 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13263
13264 return val & DPLL_VCO_ENABLE;
13265 }
13266
13267 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13268 struct intel_shared_dpll *pll)
13269 {
13270 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13271 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13272 }
13273
13274 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13275 struct intel_shared_dpll *pll)
13276 {
13277 /* PCH refclock must be enabled first */
13278 ibx_assert_pch_refclk_enabled(dev_priv);
13279
13280 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13281
13282 /* Wait for the clocks to stabilize. */
13283 POSTING_READ(PCH_DPLL(pll->id));
13284 udelay(150);
13285
13286 /* The pixel multiplier can only be updated once the
13287 * DPLL is enabled and the clocks are stable.
13288 *
13289 * So write it again.
13290 */
13291 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13292 POSTING_READ(PCH_DPLL(pll->id));
13293 udelay(200);
13294 }
13295
13296 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13297 struct intel_shared_dpll *pll)
13298 {
13299 struct drm_device *dev = dev_priv->dev;
13300 struct intel_crtc *crtc;
13301
13302 /* Make sure no transcoder isn't still depending on us. */
13303 for_each_intel_crtc(dev, crtc) {
13304 if (intel_crtc_to_shared_dpll(crtc) == pll)
13305 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13306 }
13307
13308 I915_WRITE(PCH_DPLL(pll->id), 0);
13309 POSTING_READ(PCH_DPLL(pll->id));
13310 udelay(200);
13311 }
13312
13313 static char *ibx_pch_dpll_names[] = {
13314 "PCH DPLL A",
13315 "PCH DPLL B",
13316 };
13317
13318 static void ibx_pch_dpll_init(struct drm_device *dev)
13319 {
13320 struct drm_i915_private *dev_priv = dev->dev_private;
13321 int i;
13322
13323 dev_priv->num_shared_dpll = 2;
13324
13325 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13326 dev_priv->shared_dplls[i].id = i;
13327 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13328 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13329 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13330 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13331 dev_priv->shared_dplls[i].get_hw_state =
13332 ibx_pch_dpll_get_hw_state;
13333 }
13334 }
13335
13336 static void intel_shared_dpll_init(struct drm_device *dev)
13337 {
13338 struct drm_i915_private *dev_priv = dev->dev_private;
13339
13340 if (HAS_DDI(dev))
13341 intel_ddi_pll_init(dev);
13342 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13343 ibx_pch_dpll_init(dev);
13344 else
13345 dev_priv->num_shared_dpll = 0;
13346
13347 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13348 }
13349
13350 /**
13351 * intel_prepare_plane_fb - Prepare fb for usage on plane
13352 * @plane: drm plane to prepare for
13353 * @fb: framebuffer to prepare for presentation
13354 *
13355 * Prepares a framebuffer for usage on a display plane. Generally this
13356 * involves pinning the underlying object and updating the frontbuffer tracking
13357 * bits. Some older platforms need special physical address handling for
13358 * cursor planes.
13359 *
13360 * Returns 0 on success, negative error code on failure.
13361 */
13362 int
13363 intel_prepare_plane_fb(struct drm_plane *plane,
13364 const struct drm_plane_state *new_state)
13365 {
13366 struct drm_device *dev = plane->dev;
13367 struct drm_framebuffer *fb = new_state->fb;
13368 struct intel_plane *intel_plane = to_intel_plane(plane);
13369 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13370 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13371 int ret = 0;
13372
13373 if (!obj)
13374 return 0;
13375
13376 mutex_lock(&dev->struct_mutex);
13377
13378 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13379 INTEL_INFO(dev)->cursor_needs_physical) {
13380 int align = IS_I830(dev) ? 16 * 1024 : 256;
13381 ret = i915_gem_object_attach_phys(obj, align);
13382 if (ret)
13383 DRM_DEBUG_KMS("failed to attach phys object\n");
13384 } else {
13385 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
13386 }
13387
13388 if (ret == 0)
13389 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13390
13391 mutex_unlock(&dev->struct_mutex);
13392
13393 return ret;
13394 }
13395
13396 /**
13397 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13398 * @plane: drm plane to clean up for
13399 * @fb: old framebuffer that was on plane
13400 *
13401 * Cleans up a framebuffer that has just been removed from a plane.
13402 */
13403 void
13404 intel_cleanup_plane_fb(struct drm_plane *plane,
13405 const struct drm_plane_state *old_state)
13406 {
13407 struct drm_device *dev = plane->dev;
13408 struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb);
13409
13410 if (!obj)
13411 return;
13412
13413 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13414 !INTEL_INFO(dev)->cursor_needs_physical) {
13415 mutex_lock(&dev->struct_mutex);
13416 intel_unpin_fb_obj(old_state->fb, old_state);
13417 mutex_unlock(&dev->struct_mutex);
13418 }
13419 }
13420
13421 int
13422 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13423 {
13424 int max_scale;
13425 struct drm_device *dev;
13426 struct drm_i915_private *dev_priv;
13427 int crtc_clock, cdclk;
13428
13429 if (!intel_crtc || !crtc_state)
13430 return DRM_PLANE_HELPER_NO_SCALING;
13431
13432 dev = intel_crtc->base.dev;
13433 dev_priv = dev->dev_private;
13434 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13435 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13436
13437 if (!crtc_clock || !cdclk)
13438 return DRM_PLANE_HELPER_NO_SCALING;
13439
13440 /*
13441 * skl max scale is lower of:
13442 * close to 3 but not 3, -1 is for that purpose
13443 * or
13444 * cdclk/crtc_clock
13445 */
13446 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13447
13448 return max_scale;
13449 }
13450
13451 static int
13452 intel_check_primary_plane(struct drm_plane *plane,
13453 struct intel_crtc_state *crtc_state,
13454 struct intel_plane_state *state)
13455 {
13456 struct drm_crtc *crtc = state->base.crtc;
13457 struct drm_framebuffer *fb = state->base.fb;
13458 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13459 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13460 bool can_position = false;
13461
13462 /* use scaler when colorkey is not required */
13463 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13464 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13465 min_scale = 1;
13466 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13467 can_position = true;
13468 }
13469
13470 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13471 &state->dst, &state->clip,
13472 min_scale, max_scale,
13473 can_position, true,
13474 &state->visible);
13475 }
13476
13477 static void
13478 intel_commit_primary_plane(struct drm_plane *plane,
13479 struct intel_plane_state *state)
13480 {
13481 struct drm_crtc *crtc = state->base.crtc;
13482 struct drm_framebuffer *fb = state->base.fb;
13483 struct drm_device *dev = plane->dev;
13484 struct drm_i915_private *dev_priv = dev->dev_private;
13485 struct intel_crtc *intel_crtc;
13486 struct drm_rect *src = &state->src;
13487
13488 crtc = crtc ? crtc : plane->crtc;
13489 intel_crtc = to_intel_crtc(crtc);
13490
13491 plane->fb = fb;
13492 crtc->x = src->x1 >> 16;
13493 crtc->y = src->y1 >> 16;
13494
13495 if (!crtc->state->active)
13496 return;
13497
13498 dev_priv->display.update_primary_plane(crtc, fb,
13499 state->src.x1 >> 16,
13500 state->src.y1 >> 16);
13501 }
13502
13503 static void
13504 intel_disable_primary_plane(struct drm_plane *plane,
13505 struct drm_crtc *crtc)
13506 {
13507 struct drm_device *dev = plane->dev;
13508 struct drm_i915_private *dev_priv = dev->dev_private;
13509
13510 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13511 }
13512
13513 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13514 struct drm_crtc_state *old_crtc_state)
13515 {
13516 struct drm_device *dev = crtc->dev;
13517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13518 struct intel_crtc_state *old_intel_state =
13519 to_intel_crtc_state(old_crtc_state);
13520 bool modeset = needs_modeset(crtc->state);
13521
13522 if (intel_crtc->atomic.update_wm_pre)
13523 intel_update_watermarks(crtc);
13524
13525 /* Perform vblank evasion around commit operation */
13526 if (crtc->state->active)
13527 intel_pipe_update_start(intel_crtc);
13528
13529 if (modeset)
13530 return;
13531
13532 if (to_intel_crtc_state(crtc->state)->update_pipe)
13533 intel_update_pipe_config(intel_crtc, old_intel_state);
13534 else if (INTEL_INFO(dev)->gen >= 9)
13535 skl_detach_scalers(intel_crtc);
13536 }
13537
13538 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13539 struct drm_crtc_state *old_crtc_state)
13540 {
13541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13542
13543 if (crtc->state->active)
13544 intel_pipe_update_end(intel_crtc);
13545 }
13546
13547 /**
13548 * intel_plane_destroy - destroy a plane
13549 * @plane: plane to destroy
13550 *
13551 * Common destruction function for all types of planes (primary, cursor,
13552 * sprite).
13553 */
13554 void intel_plane_destroy(struct drm_plane *plane)
13555 {
13556 struct intel_plane *intel_plane = to_intel_plane(plane);
13557 drm_plane_cleanup(plane);
13558 kfree(intel_plane);
13559 }
13560
13561 const struct drm_plane_funcs intel_plane_funcs = {
13562 .update_plane = drm_atomic_helper_update_plane,
13563 .disable_plane = drm_atomic_helper_disable_plane,
13564 .destroy = intel_plane_destroy,
13565 .set_property = drm_atomic_helper_plane_set_property,
13566 .atomic_get_property = intel_plane_atomic_get_property,
13567 .atomic_set_property = intel_plane_atomic_set_property,
13568 .atomic_duplicate_state = intel_plane_duplicate_state,
13569 .atomic_destroy_state = intel_plane_destroy_state,
13570
13571 };
13572
13573 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13574 int pipe)
13575 {
13576 struct intel_plane *primary;
13577 struct intel_plane_state *state;
13578 const uint32_t *intel_primary_formats;
13579 unsigned int num_formats;
13580
13581 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13582 if (primary == NULL)
13583 return NULL;
13584
13585 state = intel_create_plane_state(&primary->base);
13586 if (!state) {
13587 kfree(primary);
13588 return NULL;
13589 }
13590 primary->base.state = &state->base;
13591
13592 primary->can_scale = false;
13593 primary->max_downscale = 1;
13594 if (INTEL_INFO(dev)->gen >= 9) {
13595 primary->can_scale = true;
13596 state->scaler_id = -1;
13597 }
13598 primary->pipe = pipe;
13599 primary->plane = pipe;
13600 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13601 primary->check_plane = intel_check_primary_plane;
13602 primary->commit_plane = intel_commit_primary_plane;
13603 primary->disable_plane = intel_disable_primary_plane;
13604 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13605 primary->plane = !pipe;
13606
13607 if (INTEL_INFO(dev)->gen >= 9) {
13608 intel_primary_formats = skl_primary_formats;
13609 num_formats = ARRAY_SIZE(skl_primary_formats);
13610 } else if (INTEL_INFO(dev)->gen >= 4) {
13611 intel_primary_formats = i965_primary_formats;
13612 num_formats = ARRAY_SIZE(i965_primary_formats);
13613 } else {
13614 intel_primary_formats = i8xx_primary_formats;
13615 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13616 }
13617
13618 drm_universal_plane_init(dev, &primary->base, 0,
13619 &intel_plane_funcs,
13620 intel_primary_formats, num_formats,
13621 DRM_PLANE_TYPE_PRIMARY);
13622
13623 if (INTEL_INFO(dev)->gen >= 4)
13624 intel_create_rotation_property(dev, primary);
13625
13626 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13627
13628 return &primary->base;
13629 }
13630
13631 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13632 {
13633 if (!dev->mode_config.rotation_property) {
13634 unsigned long flags = BIT(DRM_ROTATE_0) |
13635 BIT(DRM_ROTATE_180);
13636
13637 if (INTEL_INFO(dev)->gen >= 9)
13638 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13639
13640 dev->mode_config.rotation_property =
13641 drm_mode_create_rotation_property(dev, flags);
13642 }
13643 if (dev->mode_config.rotation_property)
13644 drm_object_attach_property(&plane->base.base,
13645 dev->mode_config.rotation_property,
13646 plane->base.state->rotation);
13647 }
13648
13649 static int
13650 intel_check_cursor_plane(struct drm_plane *plane,
13651 struct intel_crtc_state *crtc_state,
13652 struct intel_plane_state *state)
13653 {
13654 struct drm_crtc *crtc = crtc_state->base.crtc;
13655 struct drm_framebuffer *fb = state->base.fb;
13656 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13657 unsigned stride;
13658 int ret;
13659
13660 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13661 &state->dst, &state->clip,
13662 DRM_PLANE_HELPER_NO_SCALING,
13663 DRM_PLANE_HELPER_NO_SCALING,
13664 true, true, &state->visible);
13665 if (ret)
13666 return ret;
13667
13668 /* if we want to turn off the cursor ignore width and height */
13669 if (!obj)
13670 return 0;
13671
13672 /* Check for which cursor types we support */
13673 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13674 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13675 state->base.crtc_w, state->base.crtc_h);
13676 return -EINVAL;
13677 }
13678
13679 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13680 if (obj->base.size < stride * state->base.crtc_h) {
13681 DRM_DEBUG_KMS("buffer is too small\n");
13682 return -ENOMEM;
13683 }
13684
13685 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13686 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13687 return -EINVAL;
13688 }
13689
13690 return 0;
13691 }
13692
13693 static void
13694 intel_disable_cursor_plane(struct drm_plane *plane,
13695 struct drm_crtc *crtc)
13696 {
13697 intel_crtc_update_cursor(crtc, false);
13698 }
13699
13700 static void
13701 intel_commit_cursor_plane(struct drm_plane *plane,
13702 struct intel_plane_state *state)
13703 {
13704 struct drm_crtc *crtc = state->base.crtc;
13705 struct drm_device *dev = plane->dev;
13706 struct intel_crtc *intel_crtc;
13707 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13708 uint32_t addr;
13709
13710 crtc = crtc ? crtc : plane->crtc;
13711 intel_crtc = to_intel_crtc(crtc);
13712
13713 if (intel_crtc->cursor_bo == obj)
13714 goto update;
13715
13716 if (!obj)
13717 addr = 0;
13718 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13719 addr = i915_gem_obj_ggtt_offset(obj);
13720 else
13721 addr = obj->phys_handle->busaddr;
13722
13723 intel_crtc->cursor_addr = addr;
13724 intel_crtc->cursor_bo = obj;
13725
13726 update:
13727 if (crtc->state->active)
13728 intel_crtc_update_cursor(crtc, state->visible);
13729 }
13730
13731 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13732 int pipe)
13733 {
13734 struct intel_plane *cursor;
13735 struct intel_plane_state *state;
13736
13737 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13738 if (cursor == NULL)
13739 return NULL;
13740
13741 state = intel_create_plane_state(&cursor->base);
13742 if (!state) {
13743 kfree(cursor);
13744 return NULL;
13745 }
13746 cursor->base.state = &state->base;
13747
13748 cursor->can_scale = false;
13749 cursor->max_downscale = 1;
13750 cursor->pipe = pipe;
13751 cursor->plane = pipe;
13752 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13753 cursor->check_plane = intel_check_cursor_plane;
13754 cursor->commit_plane = intel_commit_cursor_plane;
13755 cursor->disable_plane = intel_disable_cursor_plane;
13756
13757 drm_universal_plane_init(dev, &cursor->base, 0,
13758 &intel_plane_funcs,
13759 intel_cursor_formats,
13760 ARRAY_SIZE(intel_cursor_formats),
13761 DRM_PLANE_TYPE_CURSOR);
13762
13763 if (INTEL_INFO(dev)->gen >= 4) {
13764 if (!dev->mode_config.rotation_property)
13765 dev->mode_config.rotation_property =
13766 drm_mode_create_rotation_property(dev,
13767 BIT(DRM_ROTATE_0) |
13768 BIT(DRM_ROTATE_180));
13769 if (dev->mode_config.rotation_property)
13770 drm_object_attach_property(&cursor->base.base,
13771 dev->mode_config.rotation_property,
13772 state->base.rotation);
13773 }
13774
13775 if (INTEL_INFO(dev)->gen >=9)
13776 state->scaler_id = -1;
13777
13778 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13779
13780 return &cursor->base;
13781 }
13782
13783 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13784 struct intel_crtc_state *crtc_state)
13785 {
13786 int i;
13787 struct intel_scaler *intel_scaler;
13788 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13789
13790 for (i = 0; i < intel_crtc->num_scalers; i++) {
13791 intel_scaler = &scaler_state->scalers[i];
13792 intel_scaler->in_use = 0;
13793 intel_scaler->mode = PS_SCALER_MODE_DYN;
13794 }
13795
13796 scaler_state->scaler_id = -1;
13797 }
13798
13799 static void intel_crtc_init(struct drm_device *dev, int pipe)
13800 {
13801 struct drm_i915_private *dev_priv = dev->dev_private;
13802 struct intel_crtc *intel_crtc;
13803 struct intel_crtc_state *crtc_state = NULL;
13804 struct drm_plane *primary = NULL;
13805 struct drm_plane *cursor = NULL;
13806 int i, ret;
13807
13808 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13809 if (intel_crtc == NULL)
13810 return;
13811
13812 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13813 if (!crtc_state)
13814 goto fail;
13815 intel_crtc->config = crtc_state;
13816 intel_crtc->base.state = &crtc_state->base;
13817 crtc_state->base.crtc = &intel_crtc->base;
13818
13819 /* initialize shared scalers */
13820 if (INTEL_INFO(dev)->gen >= 9) {
13821 if (pipe == PIPE_C)
13822 intel_crtc->num_scalers = 1;
13823 else
13824 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13825
13826 skl_init_scalers(dev, intel_crtc, crtc_state);
13827 }
13828
13829 primary = intel_primary_plane_create(dev, pipe);
13830 if (!primary)
13831 goto fail;
13832
13833 cursor = intel_cursor_plane_create(dev, pipe);
13834 if (!cursor)
13835 goto fail;
13836
13837 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13838 cursor, &intel_crtc_funcs);
13839 if (ret)
13840 goto fail;
13841
13842 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13843 for (i = 0; i < 256; i++) {
13844 intel_crtc->lut_r[i] = i;
13845 intel_crtc->lut_g[i] = i;
13846 intel_crtc->lut_b[i] = i;
13847 }
13848
13849 /*
13850 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13851 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13852 */
13853 intel_crtc->pipe = pipe;
13854 intel_crtc->plane = pipe;
13855 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13856 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13857 intel_crtc->plane = !pipe;
13858 }
13859
13860 intel_crtc->cursor_base = ~0;
13861 intel_crtc->cursor_cntl = ~0;
13862 intel_crtc->cursor_size = ~0;
13863
13864 intel_crtc->wm.cxsr_allowed = true;
13865
13866 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13867 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13868 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13869 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13870
13871 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13872
13873 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13874 return;
13875
13876 fail:
13877 if (primary)
13878 drm_plane_cleanup(primary);
13879 if (cursor)
13880 drm_plane_cleanup(cursor);
13881 kfree(crtc_state);
13882 kfree(intel_crtc);
13883 }
13884
13885 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13886 {
13887 struct drm_encoder *encoder = connector->base.encoder;
13888 struct drm_device *dev = connector->base.dev;
13889
13890 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13891
13892 if (!encoder || WARN_ON(!encoder->crtc))
13893 return INVALID_PIPE;
13894
13895 return to_intel_crtc(encoder->crtc)->pipe;
13896 }
13897
13898 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13899 struct drm_file *file)
13900 {
13901 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13902 struct drm_crtc *drmmode_crtc;
13903 struct intel_crtc *crtc;
13904
13905 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13906
13907 if (!drmmode_crtc) {
13908 DRM_ERROR("no such CRTC id\n");
13909 return -ENOENT;
13910 }
13911
13912 crtc = to_intel_crtc(drmmode_crtc);
13913 pipe_from_crtc_id->pipe = crtc->pipe;
13914
13915 return 0;
13916 }
13917
13918 static int intel_encoder_clones(struct intel_encoder *encoder)
13919 {
13920 struct drm_device *dev = encoder->base.dev;
13921 struct intel_encoder *source_encoder;
13922 int index_mask = 0;
13923 int entry = 0;
13924
13925 for_each_intel_encoder(dev, source_encoder) {
13926 if (encoders_cloneable(encoder, source_encoder))
13927 index_mask |= (1 << entry);
13928
13929 entry++;
13930 }
13931
13932 return index_mask;
13933 }
13934
13935 static bool has_edp_a(struct drm_device *dev)
13936 {
13937 struct drm_i915_private *dev_priv = dev->dev_private;
13938
13939 if (!IS_MOBILE(dev))
13940 return false;
13941
13942 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13943 return false;
13944
13945 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13946 return false;
13947
13948 return true;
13949 }
13950
13951 static bool intel_crt_present(struct drm_device *dev)
13952 {
13953 struct drm_i915_private *dev_priv = dev->dev_private;
13954
13955 if (INTEL_INFO(dev)->gen >= 9)
13956 return false;
13957
13958 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13959 return false;
13960
13961 if (IS_CHERRYVIEW(dev))
13962 return false;
13963
13964 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13965 return false;
13966
13967 return true;
13968 }
13969
13970 static void intel_setup_outputs(struct drm_device *dev)
13971 {
13972 struct drm_i915_private *dev_priv = dev->dev_private;
13973 struct intel_encoder *encoder;
13974 bool dpd_is_edp = false;
13975
13976 intel_lvds_init(dev);
13977
13978 if (intel_crt_present(dev))
13979 intel_crt_init(dev);
13980
13981 if (IS_BROXTON(dev)) {
13982 /*
13983 * FIXME: Broxton doesn't support port detection via the
13984 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13985 * detect the ports.
13986 */
13987 intel_ddi_init(dev, PORT_A);
13988 intel_ddi_init(dev, PORT_B);
13989 intel_ddi_init(dev, PORT_C);
13990 } else if (HAS_DDI(dev)) {
13991 int found;
13992
13993 /*
13994 * Haswell uses DDI functions to detect digital outputs.
13995 * On SKL pre-D0 the strap isn't connected, so we assume
13996 * it's there.
13997 */
13998 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
13999 /* WaIgnoreDDIAStrap: skl */
14000 if (found || IS_SKYLAKE(dev))
14001 intel_ddi_init(dev, PORT_A);
14002
14003 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14004 * register */
14005 found = I915_READ(SFUSE_STRAP);
14006
14007 if (found & SFUSE_STRAP_DDIB_DETECTED)
14008 intel_ddi_init(dev, PORT_B);
14009 if (found & SFUSE_STRAP_DDIC_DETECTED)
14010 intel_ddi_init(dev, PORT_C);
14011 if (found & SFUSE_STRAP_DDID_DETECTED)
14012 intel_ddi_init(dev, PORT_D);
14013 /*
14014 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14015 */
14016 if (IS_SKYLAKE(dev) &&
14017 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14018 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14019 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14020 intel_ddi_init(dev, PORT_E);
14021
14022 } else if (HAS_PCH_SPLIT(dev)) {
14023 int found;
14024 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14025
14026 if (has_edp_a(dev))
14027 intel_dp_init(dev, DP_A, PORT_A);
14028
14029 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14030 /* PCH SDVOB multiplex with HDMIB */
14031 found = intel_sdvo_init(dev, PCH_SDVOB, true);
14032 if (!found)
14033 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14034 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14035 intel_dp_init(dev, PCH_DP_B, PORT_B);
14036 }
14037
14038 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14039 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14040
14041 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14042 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14043
14044 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14045 intel_dp_init(dev, PCH_DP_C, PORT_C);
14046
14047 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14048 intel_dp_init(dev, PCH_DP_D, PORT_D);
14049 } else if (IS_VALLEYVIEW(dev)) {
14050 /*
14051 * The DP_DETECTED bit is the latched state of the DDC
14052 * SDA pin at boot. However since eDP doesn't require DDC
14053 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14054 * eDP ports may have been muxed to an alternate function.
14055 * Thus we can't rely on the DP_DETECTED bit alone to detect
14056 * eDP ports. Consult the VBT as well as DP_DETECTED to
14057 * detect eDP ports.
14058 */
14059 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14060 !intel_dp_is_edp(dev, PORT_B))
14061 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14062 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14063 intel_dp_is_edp(dev, PORT_B))
14064 intel_dp_init(dev, VLV_DP_B, PORT_B);
14065
14066 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14067 !intel_dp_is_edp(dev, PORT_C))
14068 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14069 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14070 intel_dp_is_edp(dev, PORT_C))
14071 intel_dp_init(dev, VLV_DP_C, PORT_C);
14072
14073 if (IS_CHERRYVIEW(dev)) {
14074 /* eDP not supported on port D, so don't check VBT */
14075 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14076 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14077 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14078 intel_dp_init(dev, CHV_DP_D, PORT_D);
14079 }
14080
14081 intel_dsi_init(dev);
14082 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14083 bool found = false;
14084
14085 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14086 DRM_DEBUG_KMS("probing SDVOB\n");
14087 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
14088 if (!found && IS_G4X(dev)) {
14089 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14090 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14091 }
14092
14093 if (!found && IS_G4X(dev))
14094 intel_dp_init(dev, DP_B, PORT_B);
14095 }
14096
14097 /* Before G4X SDVOC doesn't have its own detect register */
14098
14099 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14100 DRM_DEBUG_KMS("probing SDVOC\n");
14101 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
14102 }
14103
14104 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14105
14106 if (IS_G4X(dev)) {
14107 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14108 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14109 }
14110 if (IS_G4X(dev))
14111 intel_dp_init(dev, DP_C, PORT_C);
14112 }
14113
14114 if (IS_G4X(dev) &&
14115 (I915_READ(DP_D) & DP_DETECTED))
14116 intel_dp_init(dev, DP_D, PORT_D);
14117 } else if (IS_GEN2(dev))
14118 intel_dvo_init(dev);
14119
14120 if (SUPPORTS_TV(dev))
14121 intel_tv_init(dev);
14122
14123 intel_psr_init(dev);
14124
14125 for_each_intel_encoder(dev, encoder) {
14126 encoder->base.possible_crtcs = encoder->crtc_mask;
14127 encoder->base.possible_clones =
14128 intel_encoder_clones(encoder);
14129 }
14130
14131 intel_init_pch_refclk(dev);
14132
14133 drm_helper_move_panel_connectors_to_head(dev);
14134 }
14135
14136 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14137 {
14138 struct drm_device *dev = fb->dev;
14139 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14140
14141 drm_framebuffer_cleanup(fb);
14142 mutex_lock(&dev->struct_mutex);
14143 WARN_ON(!intel_fb->obj->framebuffer_references--);
14144 drm_gem_object_unreference(&intel_fb->obj->base);
14145 mutex_unlock(&dev->struct_mutex);
14146 kfree(intel_fb);
14147 }
14148
14149 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14150 struct drm_file *file,
14151 unsigned int *handle)
14152 {
14153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14154 struct drm_i915_gem_object *obj = intel_fb->obj;
14155
14156 if (obj->userptr.mm) {
14157 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14158 return -EINVAL;
14159 }
14160
14161 return drm_gem_handle_create(file, &obj->base, handle);
14162 }
14163
14164 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14165 struct drm_file *file,
14166 unsigned flags, unsigned color,
14167 struct drm_clip_rect *clips,
14168 unsigned num_clips)
14169 {
14170 struct drm_device *dev = fb->dev;
14171 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14172 struct drm_i915_gem_object *obj = intel_fb->obj;
14173
14174 mutex_lock(&dev->struct_mutex);
14175 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14176 mutex_unlock(&dev->struct_mutex);
14177
14178 return 0;
14179 }
14180
14181 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14182 .destroy = intel_user_framebuffer_destroy,
14183 .create_handle = intel_user_framebuffer_create_handle,
14184 .dirty = intel_user_framebuffer_dirty,
14185 };
14186
14187 static
14188 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14189 uint32_t pixel_format)
14190 {
14191 u32 gen = INTEL_INFO(dev)->gen;
14192
14193 if (gen >= 9) {
14194 /* "The stride in bytes must not exceed the of the size of 8K
14195 * pixels and 32K bytes."
14196 */
14197 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14198 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14199 return 32*1024;
14200 } else if (gen >= 4) {
14201 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14202 return 16*1024;
14203 else
14204 return 32*1024;
14205 } else if (gen >= 3) {
14206 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14207 return 8*1024;
14208 else
14209 return 16*1024;
14210 } else {
14211 /* XXX DSPC is limited to 4k tiled */
14212 return 8*1024;
14213 }
14214 }
14215
14216 static int intel_framebuffer_init(struct drm_device *dev,
14217 struct intel_framebuffer *intel_fb,
14218 struct drm_mode_fb_cmd2 *mode_cmd,
14219 struct drm_i915_gem_object *obj)
14220 {
14221 unsigned int aligned_height;
14222 int ret;
14223 u32 pitch_limit, stride_alignment;
14224
14225 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14226
14227 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14228 /* Enforce that fb modifier and tiling mode match, but only for
14229 * X-tiled. This is needed for FBC. */
14230 if (!!(obj->tiling_mode == I915_TILING_X) !=
14231 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14232 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14233 return -EINVAL;
14234 }
14235 } else {
14236 if (obj->tiling_mode == I915_TILING_X)
14237 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14238 else if (obj->tiling_mode == I915_TILING_Y) {
14239 DRM_DEBUG("No Y tiling for legacy addfb\n");
14240 return -EINVAL;
14241 }
14242 }
14243
14244 /* Passed in modifier sanity checking. */
14245 switch (mode_cmd->modifier[0]) {
14246 case I915_FORMAT_MOD_Y_TILED:
14247 case I915_FORMAT_MOD_Yf_TILED:
14248 if (INTEL_INFO(dev)->gen < 9) {
14249 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14250 mode_cmd->modifier[0]);
14251 return -EINVAL;
14252 }
14253 case DRM_FORMAT_MOD_NONE:
14254 case I915_FORMAT_MOD_X_TILED:
14255 break;
14256 default:
14257 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14258 mode_cmd->modifier[0]);
14259 return -EINVAL;
14260 }
14261
14262 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14263 mode_cmd->pixel_format);
14264 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14265 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14266 mode_cmd->pitches[0], stride_alignment);
14267 return -EINVAL;
14268 }
14269
14270 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14271 mode_cmd->pixel_format);
14272 if (mode_cmd->pitches[0] > pitch_limit) {
14273 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14274 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14275 "tiled" : "linear",
14276 mode_cmd->pitches[0], pitch_limit);
14277 return -EINVAL;
14278 }
14279
14280 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14281 mode_cmd->pitches[0] != obj->stride) {
14282 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14283 mode_cmd->pitches[0], obj->stride);
14284 return -EINVAL;
14285 }
14286
14287 /* Reject formats not supported by any plane early. */
14288 switch (mode_cmd->pixel_format) {
14289 case DRM_FORMAT_C8:
14290 case DRM_FORMAT_RGB565:
14291 case DRM_FORMAT_XRGB8888:
14292 case DRM_FORMAT_ARGB8888:
14293 break;
14294 case DRM_FORMAT_XRGB1555:
14295 if (INTEL_INFO(dev)->gen > 3) {
14296 DRM_DEBUG("unsupported pixel format: %s\n",
14297 drm_get_format_name(mode_cmd->pixel_format));
14298 return -EINVAL;
14299 }
14300 break;
14301 case DRM_FORMAT_ABGR8888:
14302 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14303 DRM_DEBUG("unsupported pixel format: %s\n",
14304 drm_get_format_name(mode_cmd->pixel_format));
14305 return -EINVAL;
14306 }
14307 break;
14308 case DRM_FORMAT_XBGR8888:
14309 case DRM_FORMAT_XRGB2101010:
14310 case DRM_FORMAT_XBGR2101010:
14311 if (INTEL_INFO(dev)->gen < 4) {
14312 DRM_DEBUG("unsupported pixel format: %s\n",
14313 drm_get_format_name(mode_cmd->pixel_format));
14314 return -EINVAL;
14315 }
14316 break;
14317 case DRM_FORMAT_ABGR2101010:
14318 if (!IS_VALLEYVIEW(dev)) {
14319 DRM_DEBUG("unsupported pixel format: %s\n",
14320 drm_get_format_name(mode_cmd->pixel_format));
14321 return -EINVAL;
14322 }
14323 break;
14324 case DRM_FORMAT_YUYV:
14325 case DRM_FORMAT_UYVY:
14326 case DRM_FORMAT_YVYU:
14327 case DRM_FORMAT_VYUY:
14328 if (INTEL_INFO(dev)->gen < 5) {
14329 DRM_DEBUG("unsupported pixel format: %s\n",
14330 drm_get_format_name(mode_cmd->pixel_format));
14331 return -EINVAL;
14332 }
14333 break;
14334 default:
14335 DRM_DEBUG("unsupported pixel format: %s\n",
14336 drm_get_format_name(mode_cmd->pixel_format));
14337 return -EINVAL;
14338 }
14339
14340 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14341 if (mode_cmd->offsets[0] != 0)
14342 return -EINVAL;
14343
14344 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14345 mode_cmd->pixel_format,
14346 mode_cmd->modifier[0]);
14347 /* FIXME drm helper for size checks (especially planar formats)? */
14348 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14349 return -EINVAL;
14350
14351 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14352 intel_fb->obj = obj;
14353 intel_fb->obj->framebuffer_references++;
14354
14355 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14356 if (ret) {
14357 DRM_ERROR("framebuffer init failed %d\n", ret);
14358 return ret;
14359 }
14360
14361 return 0;
14362 }
14363
14364 static struct drm_framebuffer *
14365 intel_user_framebuffer_create(struct drm_device *dev,
14366 struct drm_file *filp,
14367 struct drm_mode_fb_cmd2 *mode_cmd)
14368 {
14369 struct drm_i915_gem_object *obj;
14370
14371 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14372 mode_cmd->handles[0]));
14373 if (&obj->base == NULL)
14374 return ERR_PTR(-ENOENT);
14375
14376 return intel_framebuffer_create(dev, mode_cmd, obj);
14377 }
14378
14379 #ifndef CONFIG_DRM_FBDEV_EMULATION
14380 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14381 {
14382 }
14383 #endif
14384
14385 static const struct drm_mode_config_funcs intel_mode_funcs = {
14386 .fb_create = intel_user_framebuffer_create,
14387 .output_poll_changed = intel_fbdev_output_poll_changed,
14388 .atomic_check = intel_atomic_check,
14389 .atomic_commit = intel_atomic_commit,
14390 .atomic_state_alloc = intel_atomic_state_alloc,
14391 .atomic_state_clear = intel_atomic_state_clear,
14392 };
14393
14394 /* Set up chip specific display functions */
14395 static void intel_init_display(struct drm_device *dev)
14396 {
14397 struct drm_i915_private *dev_priv = dev->dev_private;
14398
14399 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14400 dev_priv->display.find_dpll = g4x_find_best_dpll;
14401 else if (IS_CHERRYVIEW(dev))
14402 dev_priv->display.find_dpll = chv_find_best_dpll;
14403 else if (IS_VALLEYVIEW(dev))
14404 dev_priv->display.find_dpll = vlv_find_best_dpll;
14405 else if (IS_PINEVIEW(dev))
14406 dev_priv->display.find_dpll = pnv_find_best_dpll;
14407 else
14408 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14409
14410 if (INTEL_INFO(dev)->gen >= 9) {
14411 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14412 dev_priv->display.get_initial_plane_config =
14413 skylake_get_initial_plane_config;
14414 dev_priv->display.crtc_compute_clock =
14415 haswell_crtc_compute_clock;
14416 dev_priv->display.crtc_enable = haswell_crtc_enable;
14417 dev_priv->display.crtc_disable = haswell_crtc_disable;
14418 dev_priv->display.update_primary_plane =
14419 skylake_update_primary_plane;
14420 } else if (HAS_DDI(dev)) {
14421 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14422 dev_priv->display.get_initial_plane_config =
14423 ironlake_get_initial_plane_config;
14424 dev_priv->display.crtc_compute_clock =
14425 haswell_crtc_compute_clock;
14426 dev_priv->display.crtc_enable = haswell_crtc_enable;
14427 dev_priv->display.crtc_disable = haswell_crtc_disable;
14428 dev_priv->display.update_primary_plane =
14429 ironlake_update_primary_plane;
14430 } else if (HAS_PCH_SPLIT(dev)) {
14431 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14432 dev_priv->display.get_initial_plane_config =
14433 ironlake_get_initial_plane_config;
14434 dev_priv->display.crtc_compute_clock =
14435 ironlake_crtc_compute_clock;
14436 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14437 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14438 dev_priv->display.update_primary_plane =
14439 ironlake_update_primary_plane;
14440 } else if (IS_VALLEYVIEW(dev)) {
14441 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14442 dev_priv->display.get_initial_plane_config =
14443 i9xx_get_initial_plane_config;
14444 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14445 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14446 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14447 dev_priv->display.update_primary_plane =
14448 i9xx_update_primary_plane;
14449 } else {
14450 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14451 dev_priv->display.get_initial_plane_config =
14452 i9xx_get_initial_plane_config;
14453 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14454 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14455 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14456 dev_priv->display.update_primary_plane =
14457 i9xx_update_primary_plane;
14458 }
14459
14460 /* Returns the core display clock speed */
14461 if (IS_SKYLAKE(dev))
14462 dev_priv->display.get_display_clock_speed =
14463 skylake_get_display_clock_speed;
14464 else if (IS_BROXTON(dev))
14465 dev_priv->display.get_display_clock_speed =
14466 broxton_get_display_clock_speed;
14467 else if (IS_BROADWELL(dev))
14468 dev_priv->display.get_display_clock_speed =
14469 broadwell_get_display_clock_speed;
14470 else if (IS_HASWELL(dev))
14471 dev_priv->display.get_display_clock_speed =
14472 haswell_get_display_clock_speed;
14473 else if (IS_VALLEYVIEW(dev))
14474 dev_priv->display.get_display_clock_speed =
14475 valleyview_get_display_clock_speed;
14476 else if (IS_GEN5(dev))
14477 dev_priv->display.get_display_clock_speed =
14478 ilk_get_display_clock_speed;
14479 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14480 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14481 dev_priv->display.get_display_clock_speed =
14482 i945_get_display_clock_speed;
14483 else if (IS_GM45(dev))
14484 dev_priv->display.get_display_clock_speed =
14485 gm45_get_display_clock_speed;
14486 else if (IS_CRESTLINE(dev))
14487 dev_priv->display.get_display_clock_speed =
14488 i965gm_get_display_clock_speed;
14489 else if (IS_PINEVIEW(dev))
14490 dev_priv->display.get_display_clock_speed =
14491 pnv_get_display_clock_speed;
14492 else if (IS_G33(dev) || IS_G4X(dev))
14493 dev_priv->display.get_display_clock_speed =
14494 g33_get_display_clock_speed;
14495 else if (IS_I915G(dev))
14496 dev_priv->display.get_display_clock_speed =
14497 i915_get_display_clock_speed;
14498 else if (IS_I945GM(dev) || IS_845G(dev))
14499 dev_priv->display.get_display_clock_speed =
14500 i9xx_misc_get_display_clock_speed;
14501 else if (IS_PINEVIEW(dev))
14502 dev_priv->display.get_display_clock_speed =
14503 pnv_get_display_clock_speed;
14504 else if (IS_I915GM(dev))
14505 dev_priv->display.get_display_clock_speed =
14506 i915gm_get_display_clock_speed;
14507 else if (IS_I865G(dev))
14508 dev_priv->display.get_display_clock_speed =
14509 i865_get_display_clock_speed;
14510 else if (IS_I85X(dev))
14511 dev_priv->display.get_display_clock_speed =
14512 i85x_get_display_clock_speed;
14513 else { /* 830 */
14514 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14515 dev_priv->display.get_display_clock_speed =
14516 i830_get_display_clock_speed;
14517 }
14518
14519 if (IS_GEN5(dev)) {
14520 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14521 } else if (IS_GEN6(dev)) {
14522 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14523 } else if (IS_IVYBRIDGE(dev)) {
14524 /* FIXME: detect B0+ stepping and use auto training */
14525 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14526 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14527 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14528 if (IS_BROADWELL(dev)) {
14529 dev_priv->display.modeset_commit_cdclk =
14530 broadwell_modeset_commit_cdclk;
14531 dev_priv->display.modeset_calc_cdclk =
14532 broadwell_modeset_calc_cdclk;
14533 }
14534 } else if (IS_VALLEYVIEW(dev)) {
14535 dev_priv->display.modeset_commit_cdclk =
14536 valleyview_modeset_commit_cdclk;
14537 dev_priv->display.modeset_calc_cdclk =
14538 valleyview_modeset_calc_cdclk;
14539 } else if (IS_BROXTON(dev)) {
14540 dev_priv->display.modeset_commit_cdclk =
14541 broxton_modeset_commit_cdclk;
14542 dev_priv->display.modeset_calc_cdclk =
14543 broxton_modeset_calc_cdclk;
14544 }
14545
14546 switch (INTEL_INFO(dev)->gen) {
14547 case 2:
14548 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14549 break;
14550
14551 case 3:
14552 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14553 break;
14554
14555 case 4:
14556 case 5:
14557 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14558 break;
14559
14560 case 6:
14561 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14562 break;
14563 case 7:
14564 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14565 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14566 break;
14567 case 9:
14568 /* Drop through - unsupported since execlist only. */
14569 default:
14570 /* Default just returns -ENODEV to indicate unsupported */
14571 dev_priv->display.queue_flip = intel_default_queue_flip;
14572 }
14573
14574 mutex_init(&dev_priv->pps_mutex);
14575 }
14576
14577 /*
14578 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14579 * resume, or other times. This quirk makes sure that's the case for
14580 * affected systems.
14581 */
14582 static void quirk_pipea_force(struct drm_device *dev)
14583 {
14584 struct drm_i915_private *dev_priv = dev->dev_private;
14585
14586 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14587 DRM_INFO("applying pipe a force quirk\n");
14588 }
14589
14590 static void quirk_pipeb_force(struct drm_device *dev)
14591 {
14592 struct drm_i915_private *dev_priv = dev->dev_private;
14593
14594 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14595 DRM_INFO("applying pipe b force quirk\n");
14596 }
14597
14598 /*
14599 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14600 */
14601 static void quirk_ssc_force_disable(struct drm_device *dev)
14602 {
14603 struct drm_i915_private *dev_priv = dev->dev_private;
14604 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14605 DRM_INFO("applying lvds SSC disable quirk\n");
14606 }
14607
14608 /*
14609 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14610 * brightness value
14611 */
14612 static void quirk_invert_brightness(struct drm_device *dev)
14613 {
14614 struct drm_i915_private *dev_priv = dev->dev_private;
14615 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14616 DRM_INFO("applying inverted panel brightness quirk\n");
14617 }
14618
14619 /* Some VBT's incorrectly indicate no backlight is present */
14620 static void quirk_backlight_present(struct drm_device *dev)
14621 {
14622 struct drm_i915_private *dev_priv = dev->dev_private;
14623 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14624 DRM_INFO("applying backlight present quirk\n");
14625 }
14626
14627 struct intel_quirk {
14628 int device;
14629 int subsystem_vendor;
14630 int subsystem_device;
14631 void (*hook)(struct drm_device *dev);
14632 };
14633
14634 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14635 struct intel_dmi_quirk {
14636 void (*hook)(struct drm_device *dev);
14637 const struct dmi_system_id (*dmi_id_list)[];
14638 };
14639
14640 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14641 {
14642 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14643 return 1;
14644 }
14645
14646 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14647 {
14648 .dmi_id_list = &(const struct dmi_system_id[]) {
14649 {
14650 .callback = intel_dmi_reverse_brightness,
14651 .ident = "NCR Corporation",
14652 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14653 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14654 },
14655 },
14656 { } /* terminating entry */
14657 },
14658 .hook = quirk_invert_brightness,
14659 },
14660 };
14661
14662 static struct intel_quirk intel_quirks[] = {
14663 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14664 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14665
14666 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14667 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14668
14669 /* 830 needs to leave pipe A & dpll A up */
14670 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14671
14672 /* 830 needs to leave pipe B & dpll B up */
14673 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14674
14675 /* Lenovo U160 cannot use SSC on LVDS */
14676 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14677
14678 /* Sony Vaio Y cannot use SSC on LVDS */
14679 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14680
14681 /* Acer Aspire 5734Z must invert backlight brightness */
14682 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14683
14684 /* Acer/eMachines G725 */
14685 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14686
14687 /* Acer/eMachines e725 */
14688 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14689
14690 /* Acer/Packard Bell NCL20 */
14691 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14692
14693 /* Acer Aspire 4736Z */
14694 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14695
14696 /* Acer Aspire 5336 */
14697 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14698
14699 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14700 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14701
14702 /* Acer C720 Chromebook (Core i3 4005U) */
14703 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14704
14705 /* Apple Macbook 2,1 (Core 2 T7400) */
14706 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14707
14708 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14709 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14710
14711 /* HP Chromebook 14 (Celeron 2955U) */
14712 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14713
14714 /* Dell Chromebook 11 */
14715 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14716
14717 /* Dell Chromebook 11 (2015 version) */
14718 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14719 };
14720
14721 static void intel_init_quirks(struct drm_device *dev)
14722 {
14723 struct pci_dev *d = dev->pdev;
14724 int i;
14725
14726 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14727 struct intel_quirk *q = &intel_quirks[i];
14728
14729 if (d->device == q->device &&
14730 (d->subsystem_vendor == q->subsystem_vendor ||
14731 q->subsystem_vendor == PCI_ANY_ID) &&
14732 (d->subsystem_device == q->subsystem_device ||
14733 q->subsystem_device == PCI_ANY_ID))
14734 q->hook(dev);
14735 }
14736 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14737 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14738 intel_dmi_quirks[i].hook(dev);
14739 }
14740 }
14741
14742 /* Disable the VGA plane that we never use */
14743 static void i915_disable_vga(struct drm_device *dev)
14744 {
14745 struct drm_i915_private *dev_priv = dev->dev_private;
14746 u8 sr1;
14747 u32 vga_reg = i915_vgacntrl_reg(dev);
14748
14749 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14750 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14751 outb(SR01, VGA_SR_INDEX);
14752 sr1 = inb(VGA_SR_DATA);
14753 outb(sr1 | 1<<5, VGA_SR_DATA);
14754 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14755 udelay(300);
14756
14757 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14758 POSTING_READ(vga_reg);
14759 }
14760
14761 void intel_modeset_init_hw(struct drm_device *dev)
14762 {
14763 intel_update_cdclk(dev);
14764 intel_prepare_ddi(dev);
14765 intel_init_clock_gating(dev);
14766 intel_enable_gt_powersave(dev);
14767 }
14768
14769 void intel_modeset_init(struct drm_device *dev)
14770 {
14771 struct drm_i915_private *dev_priv = dev->dev_private;
14772 int sprite, ret;
14773 enum pipe pipe;
14774 struct intel_crtc *crtc;
14775
14776 drm_mode_config_init(dev);
14777
14778 dev->mode_config.min_width = 0;
14779 dev->mode_config.min_height = 0;
14780
14781 dev->mode_config.preferred_depth = 24;
14782 dev->mode_config.prefer_shadow = 1;
14783
14784 dev->mode_config.allow_fb_modifiers = true;
14785
14786 dev->mode_config.funcs = &intel_mode_funcs;
14787
14788 intel_init_quirks(dev);
14789
14790 intel_init_pm(dev);
14791
14792 if (INTEL_INFO(dev)->num_pipes == 0)
14793 return;
14794
14795 /*
14796 * There may be no VBT; and if the BIOS enabled SSC we can
14797 * just keep using it to avoid unnecessary flicker. Whereas if the
14798 * BIOS isn't using it, don't assume it will work even if the VBT
14799 * indicates as much.
14800 */
14801 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14802 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14803 DREF_SSC1_ENABLE);
14804
14805 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14806 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14807 bios_lvds_use_ssc ? "en" : "dis",
14808 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14809 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14810 }
14811 }
14812
14813 intel_init_display(dev);
14814 intel_init_audio(dev);
14815
14816 if (IS_GEN2(dev)) {
14817 dev->mode_config.max_width = 2048;
14818 dev->mode_config.max_height = 2048;
14819 } else if (IS_GEN3(dev)) {
14820 dev->mode_config.max_width = 4096;
14821 dev->mode_config.max_height = 4096;
14822 } else {
14823 dev->mode_config.max_width = 8192;
14824 dev->mode_config.max_height = 8192;
14825 }
14826
14827 if (IS_845G(dev) || IS_I865G(dev)) {
14828 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14829 dev->mode_config.cursor_height = 1023;
14830 } else if (IS_GEN2(dev)) {
14831 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14832 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14833 } else {
14834 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14835 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14836 }
14837
14838 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14839
14840 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14841 INTEL_INFO(dev)->num_pipes,
14842 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14843
14844 for_each_pipe(dev_priv, pipe) {
14845 intel_crtc_init(dev, pipe);
14846 for_each_sprite(dev_priv, pipe, sprite) {
14847 ret = intel_plane_init(dev, pipe, sprite);
14848 if (ret)
14849 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14850 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14851 }
14852 }
14853
14854 intel_update_czclk(dev_priv);
14855 intel_update_cdclk(dev);
14856
14857 intel_shared_dpll_init(dev);
14858
14859 /* Just disable it once at startup */
14860 i915_disable_vga(dev);
14861 intel_setup_outputs(dev);
14862
14863 /* Just in case the BIOS is doing something questionable. */
14864 intel_fbc_disable(dev_priv);
14865
14866 drm_modeset_lock_all(dev);
14867 intel_modeset_setup_hw_state(dev);
14868 drm_modeset_unlock_all(dev);
14869
14870 for_each_intel_crtc(dev, crtc) {
14871 struct intel_initial_plane_config plane_config = {};
14872
14873 if (!crtc->active)
14874 continue;
14875
14876 /*
14877 * Note that reserving the BIOS fb up front prevents us
14878 * from stuffing other stolen allocations like the ring
14879 * on top. This prevents some ugliness at boot time, and
14880 * can even allow for smooth boot transitions if the BIOS
14881 * fb is large enough for the active pipe configuration.
14882 */
14883 dev_priv->display.get_initial_plane_config(crtc,
14884 &plane_config);
14885
14886 /*
14887 * If the fb is shared between multiple heads, we'll
14888 * just get the first one.
14889 */
14890 intel_find_initial_plane_obj(crtc, &plane_config);
14891 }
14892 }
14893
14894 static void intel_enable_pipe_a(struct drm_device *dev)
14895 {
14896 struct intel_connector *connector;
14897 struct drm_connector *crt = NULL;
14898 struct intel_load_detect_pipe load_detect_temp;
14899 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14900
14901 /* We can't just switch on the pipe A, we need to set things up with a
14902 * proper mode and output configuration. As a gross hack, enable pipe A
14903 * by enabling the load detect pipe once. */
14904 for_each_intel_connector(dev, connector) {
14905 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14906 crt = &connector->base;
14907 break;
14908 }
14909 }
14910
14911 if (!crt)
14912 return;
14913
14914 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14915 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14916 }
14917
14918 static bool
14919 intel_check_plane_mapping(struct intel_crtc *crtc)
14920 {
14921 struct drm_device *dev = crtc->base.dev;
14922 struct drm_i915_private *dev_priv = dev->dev_private;
14923 u32 val;
14924
14925 if (INTEL_INFO(dev)->num_pipes == 1)
14926 return true;
14927
14928 val = I915_READ(DSPCNTR(!crtc->plane));
14929
14930 if ((val & DISPLAY_PLANE_ENABLE) &&
14931 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14932 return false;
14933
14934 return true;
14935 }
14936
14937 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14938 {
14939 struct drm_device *dev = crtc->base.dev;
14940 struct intel_encoder *encoder;
14941
14942 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14943 return true;
14944
14945 return false;
14946 }
14947
14948 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14949 {
14950 struct drm_device *dev = crtc->base.dev;
14951 struct drm_i915_private *dev_priv = dev->dev_private;
14952 u32 reg;
14953
14954 /* Clear any frame start delays used for debugging left by the BIOS */
14955 reg = PIPECONF(crtc->config->cpu_transcoder);
14956 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14957
14958 /* restore vblank interrupts to correct state */
14959 drm_crtc_vblank_reset(&crtc->base);
14960 if (crtc->active) {
14961 struct intel_plane *plane;
14962
14963 drm_crtc_vblank_on(&crtc->base);
14964
14965 /* Disable everything but the primary plane */
14966 for_each_intel_plane_on_crtc(dev, crtc, plane) {
14967 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
14968 continue;
14969
14970 plane->disable_plane(&plane->base, &crtc->base);
14971 }
14972 }
14973
14974 /* We need to sanitize the plane -> pipe mapping first because this will
14975 * disable the crtc (and hence change the state) if it is wrong. Note
14976 * that gen4+ has a fixed plane -> pipe mapping. */
14977 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14978 bool plane;
14979
14980 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14981 crtc->base.base.id);
14982
14983 /* Pipe has the wrong plane attached and the plane is active.
14984 * Temporarily change the plane mapping and disable everything
14985 * ... */
14986 plane = crtc->plane;
14987 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14988 crtc->plane = !plane;
14989 intel_crtc_disable_noatomic(&crtc->base);
14990 crtc->plane = plane;
14991 }
14992
14993 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14994 crtc->pipe == PIPE_A && !crtc->active) {
14995 /* BIOS forgot to enable pipe A, this mostly happens after
14996 * resume. Force-enable the pipe to fix this, the update_dpms
14997 * call below we restore the pipe to the right state, but leave
14998 * the required bits on. */
14999 intel_enable_pipe_a(dev);
15000 }
15001
15002 /* Adjust the state of the output pipe according to whether we
15003 * have active connectors/encoders. */
15004 if (!intel_crtc_has_encoders(crtc))
15005 intel_crtc_disable_noatomic(&crtc->base);
15006
15007 if (crtc->active != crtc->base.state->active) {
15008 struct intel_encoder *encoder;
15009
15010 /* This can happen either due to bugs in the get_hw_state
15011 * functions or because of calls to intel_crtc_disable_noatomic,
15012 * or because the pipe is force-enabled due to the
15013 * pipe A quirk. */
15014 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15015 crtc->base.base.id,
15016 crtc->base.state->enable ? "enabled" : "disabled",
15017 crtc->active ? "enabled" : "disabled");
15018
15019 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15020 crtc->base.state->active = crtc->active;
15021 crtc->base.enabled = crtc->active;
15022
15023 /* Because we only establish the connector -> encoder ->
15024 * crtc links if something is active, this means the
15025 * crtc is now deactivated. Break the links. connector
15026 * -> encoder links are only establish when things are
15027 * actually up, hence no need to break them. */
15028 WARN_ON(crtc->active);
15029
15030 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15031 encoder->base.crtc = NULL;
15032 }
15033
15034 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15035 /*
15036 * We start out with underrun reporting disabled to avoid races.
15037 * For correct bookkeeping mark this on active crtcs.
15038 *
15039 * Also on gmch platforms we dont have any hardware bits to
15040 * disable the underrun reporting. Which means we need to start
15041 * out with underrun reporting disabled also on inactive pipes,
15042 * since otherwise we'll complain about the garbage we read when
15043 * e.g. coming up after runtime pm.
15044 *
15045 * No protection against concurrent access is required - at
15046 * worst a fifo underrun happens which also sets this to false.
15047 */
15048 crtc->cpu_fifo_underrun_disabled = true;
15049 crtc->pch_fifo_underrun_disabled = true;
15050 }
15051 }
15052
15053 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15054 {
15055 struct intel_connector *connector;
15056 struct drm_device *dev = encoder->base.dev;
15057 bool active = false;
15058
15059 /* We need to check both for a crtc link (meaning that the
15060 * encoder is active and trying to read from a pipe) and the
15061 * pipe itself being active. */
15062 bool has_active_crtc = encoder->base.crtc &&
15063 to_intel_crtc(encoder->base.crtc)->active;
15064
15065 for_each_intel_connector(dev, connector) {
15066 if (connector->base.encoder != &encoder->base)
15067 continue;
15068
15069 active = true;
15070 break;
15071 }
15072
15073 if (active && !has_active_crtc) {
15074 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15075 encoder->base.base.id,
15076 encoder->base.name);
15077
15078 /* Connector is active, but has no active pipe. This is
15079 * fallout from our resume register restoring. Disable
15080 * the encoder manually again. */
15081 if (encoder->base.crtc) {
15082 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15083 encoder->base.base.id,
15084 encoder->base.name);
15085 encoder->disable(encoder);
15086 if (encoder->post_disable)
15087 encoder->post_disable(encoder);
15088 }
15089 encoder->base.crtc = NULL;
15090
15091 /* Inconsistent output/port/pipe state happens presumably due to
15092 * a bug in one of the get_hw_state functions. Or someplace else
15093 * in our code, like the register restore mess on resume. Clamp
15094 * things to off as a safer default. */
15095 for_each_intel_connector(dev, connector) {
15096 if (connector->encoder != encoder)
15097 continue;
15098 connector->base.dpms = DRM_MODE_DPMS_OFF;
15099 connector->base.encoder = NULL;
15100 }
15101 }
15102 /* Enabled encoders without active connectors will be fixed in
15103 * the crtc fixup. */
15104 }
15105
15106 void i915_redisable_vga_power_on(struct drm_device *dev)
15107 {
15108 struct drm_i915_private *dev_priv = dev->dev_private;
15109 u32 vga_reg = i915_vgacntrl_reg(dev);
15110
15111 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15112 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15113 i915_disable_vga(dev);
15114 }
15115 }
15116
15117 void i915_redisable_vga(struct drm_device *dev)
15118 {
15119 struct drm_i915_private *dev_priv = dev->dev_private;
15120
15121 /* This function can be called both from intel_modeset_setup_hw_state or
15122 * at a very early point in our resume sequence, where the power well
15123 * structures are not yet restored. Since this function is at a very
15124 * paranoid "someone might have enabled VGA while we were not looking"
15125 * level, just check if the power well is enabled instead of trying to
15126 * follow the "don't touch the power well if we don't need it" policy
15127 * the rest of the driver uses. */
15128 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15129 return;
15130
15131 i915_redisable_vga_power_on(dev);
15132 }
15133
15134 static bool primary_get_hw_state(struct intel_plane *plane)
15135 {
15136 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15137
15138 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15139 }
15140
15141 /* FIXME read out full plane state for all planes */
15142 static void readout_plane_state(struct intel_crtc *crtc)
15143 {
15144 struct drm_plane *primary = crtc->base.primary;
15145 struct intel_plane_state *plane_state =
15146 to_intel_plane_state(primary->state);
15147
15148 plane_state->visible =
15149 primary_get_hw_state(to_intel_plane(primary));
15150
15151 if (plane_state->visible)
15152 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15153 }
15154
15155 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15156 {
15157 struct drm_i915_private *dev_priv = dev->dev_private;
15158 enum pipe pipe;
15159 struct intel_crtc *crtc;
15160 struct intel_encoder *encoder;
15161 struct intel_connector *connector;
15162 int i;
15163
15164 for_each_intel_crtc(dev, crtc) {
15165 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15166 memset(crtc->config, 0, sizeof(*crtc->config));
15167 crtc->config->base.crtc = &crtc->base;
15168
15169 crtc->active = dev_priv->display.get_pipe_config(crtc,
15170 crtc->config);
15171
15172 crtc->base.state->active = crtc->active;
15173 crtc->base.enabled = crtc->active;
15174
15175 readout_plane_state(crtc);
15176
15177 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15178 crtc->base.base.id,
15179 crtc->active ? "enabled" : "disabled");
15180 }
15181
15182 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15183 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15184
15185 pll->on = pll->get_hw_state(dev_priv, pll,
15186 &pll->config.hw_state);
15187 pll->active = 0;
15188 pll->config.crtc_mask = 0;
15189 for_each_intel_crtc(dev, crtc) {
15190 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15191 pll->active++;
15192 pll->config.crtc_mask |= 1 << crtc->pipe;
15193 }
15194 }
15195
15196 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15197 pll->name, pll->config.crtc_mask, pll->on);
15198
15199 if (pll->config.crtc_mask)
15200 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15201 }
15202
15203 for_each_intel_encoder(dev, encoder) {
15204 pipe = 0;
15205
15206 if (encoder->get_hw_state(encoder, &pipe)) {
15207 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15208 encoder->base.crtc = &crtc->base;
15209 encoder->get_config(encoder, crtc->config);
15210 } else {
15211 encoder->base.crtc = NULL;
15212 }
15213
15214 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15215 encoder->base.base.id,
15216 encoder->base.name,
15217 encoder->base.crtc ? "enabled" : "disabled",
15218 pipe_name(pipe));
15219 }
15220
15221 for_each_intel_connector(dev, connector) {
15222 if (connector->get_hw_state(connector)) {
15223 connector->base.dpms = DRM_MODE_DPMS_ON;
15224 connector->base.encoder = &connector->encoder->base;
15225 } else {
15226 connector->base.dpms = DRM_MODE_DPMS_OFF;
15227 connector->base.encoder = NULL;
15228 }
15229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15230 connector->base.base.id,
15231 connector->base.name,
15232 connector->base.encoder ? "enabled" : "disabled");
15233 }
15234
15235 for_each_intel_crtc(dev, crtc) {
15236 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15237
15238 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15239 if (crtc->base.state->active) {
15240 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15241 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15242 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15243
15244 /*
15245 * The initial mode needs to be set in order to keep
15246 * the atomic core happy. It wants a valid mode if the
15247 * crtc's enabled, so we do the above call.
15248 *
15249 * At this point some state updated by the connectors
15250 * in their ->detect() callback has not run yet, so
15251 * no recalculation can be done yet.
15252 *
15253 * Even if we could do a recalculation and modeset
15254 * right now it would cause a double modeset if
15255 * fbdev or userspace chooses a different initial mode.
15256 *
15257 * If that happens, someone indicated they wanted a
15258 * mode change, which means it's safe to do a full
15259 * recalculation.
15260 */
15261 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15262
15263 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15264 update_scanline_offset(crtc);
15265 }
15266 }
15267 }
15268
15269 /* Scan out the current hw modeset state,
15270 * and sanitizes it to the current state
15271 */
15272 static void
15273 intel_modeset_setup_hw_state(struct drm_device *dev)
15274 {
15275 struct drm_i915_private *dev_priv = dev->dev_private;
15276 enum pipe pipe;
15277 struct intel_crtc *crtc;
15278 struct intel_encoder *encoder;
15279 int i;
15280
15281 intel_modeset_readout_hw_state(dev);
15282
15283 /* HW state is read out, now we need to sanitize this mess. */
15284 for_each_intel_encoder(dev, encoder) {
15285 intel_sanitize_encoder(encoder);
15286 }
15287
15288 for_each_pipe(dev_priv, pipe) {
15289 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15290 intel_sanitize_crtc(crtc);
15291 intel_dump_pipe_config(crtc, crtc->config,
15292 "[setup_hw_state]");
15293 }
15294
15295 intel_modeset_update_connector_atomic_state(dev);
15296
15297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15298 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15299
15300 if (!pll->on || pll->active)
15301 continue;
15302
15303 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15304
15305 pll->disable(dev_priv, pll);
15306 pll->on = false;
15307 }
15308
15309 if (IS_VALLEYVIEW(dev))
15310 vlv_wm_get_hw_state(dev);
15311 else if (IS_GEN9(dev))
15312 skl_wm_get_hw_state(dev);
15313 else if (HAS_PCH_SPLIT(dev))
15314 ilk_wm_get_hw_state(dev);
15315
15316 for_each_intel_crtc(dev, crtc) {
15317 unsigned long put_domains;
15318
15319 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15320 if (WARN_ON(put_domains))
15321 modeset_put_power_domains(dev_priv, put_domains);
15322 }
15323 intel_display_set_init_power(dev_priv, false);
15324 }
15325
15326 void intel_display_resume(struct drm_device *dev)
15327 {
15328 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15329 struct intel_connector *conn;
15330 struct intel_plane *plane;
15331 struct drm_crtc *crtc;
15332 int ret;
15333
15334 if (!state)
15335 return;
15336
15337 state->acquire_ctx = dev->mode_config.acquire_ctx;
15338
15339 /* preserve complete old state, including dpll */
15340 intel_atomic_get_shared_dpll_state(state);
15341
15342 for_each_crtc(dev, crtc) {
15343 struct drm_crtc_state *crtc_state =
15344 drm_atomic_get_crtc_state(state, crtc);
15345
15346 ret = PTR_ERR_OR_ZERO(crtc_state);
15347 if (ret)
15348 goto err;
15349
15350 /* force a restore */
15351 crtc_state->mode_changed = true;
15352 }
15353
15354 for_each_intel_plane(dev, plane) {
15355 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15356 if (ret)
15357 goto err;
15358 }
15359
15360 for_each_intel_connector(dev, conn) {
15361 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15362 if (ret)
15363 goto err;
15364 }
15365
15366 intel_modeset_setup_hw_state(dev);
15367
15368 i915_redisable_vga(dev);
15369 ret = drm_atomic_commit(state);
15370 if (!ret)
15371 return;
15372
15373 err:
15374 DRM_ERROR("Restoring old state failed with %i\n", ret);
15375 drm_atomic_state_free(state);
15376 }
15377
15378 void intel_modeset_gem_init(struct drm_device *dev)
15379 {
15380 struct drm_crtc *c;
15381 struct drm_i915_gem_object *obj;
15382 int ret;
15383
15384 mutex_lock(&dev->struct_mutex);
15385 intel_init_gt_powersave(dev);
15386 mutex_unlock(&dev->struct_mutex);
15387
15388 intel_modeset_init_hw(dev);
15389
15390 intel_setup_overlay(dev);
15391
15392 /*
15393 * Make sure any fbs we allocated at startup are properly
15394 * pinned & fenced. When we do the allocation it's too early
15395 * for this.
15396 */
15397 for_each_crtc(dev, c) {
15398 obj = intel_fb_obj(c->primary->fb);
15399 if (obj == NULL)
15400 continue;
15401
15402 mutex_lock(&dev->struct_mutex);
15403 ret = intel_pin_and_fence_fb_obj(c->primary,
15404 c->primary->fb,
15405 c->primary->state,
15406 NULL, NULL);
15407 mutex_unlock(&dev->struct_mutex);
15408 if (ret) {
15409 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15410 to_intel_crtc(c)->pipe);
15411 drm_framebuffer_unreference(c->primary->fb);
15412 c->primary->fb = NULL;
15413 c->primary->crtc = c->primary->state->crtc = NULL;
15414 update_state_fb(c->primary);
15415 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15416 }
15417 }
15418
15419 intel_backlight_register(dev);
15420 }
15421
15422 void intel_connector_unregister(struct intel_connector *intel_connector)
15423 {
15424 struct drm_connector *connector = &intel_connector->base;
15425
15426 intel_panel_destroy_backlight(connector);
15427 drm_connector_unregister(connector);
15428 }
15429
15430 void intel_modeset_cleanup(struct drm_device *dev)
15431 {
15432 struct drm_i915_private *dev_priv = dev->dev_private;
15433 struct drm_connector *connector;
15434
15435 intel_disable_gt_powersave(dev);
15436
15437 intel_backlight_unregister(dev);
15438
15439 /*
15440 * Interrupts and polling as the first thing to avoid creating havoc.
15441 * Too much stuff here (turning of connectors, ...) would
15442 * experience fancy races otherwise.
15443 */
15444 intel_irq_uninstall(dev_priv);
15445
15446 /*
15447 * Due to the hpd irq storm handling the hotplug work can re-arm the
15448 * poll handlers. Hence disable polling after hpd handling is shut down.
15449 */
15450 drm_kms_helper_poll_fini(dev);
15451
15452 intel_unregister_dsm_handler();
15453
15454 intel_fbc_disable(dev_priv);
15455
15456 /* flush any delayed tasks or pending work */
15457 flush_scheduled_work();
15458
15459 /* destroy the backlight and sysfs files before encoders/connectors */
15460 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15461 struct intel_connector *intel_connector;
15462
15463 intel_connector = to_intel_connector(connector);
15464 intel_connector->unregister(intel_connector);
15465 }
15466
15467 drm_mode_config_cleanup(dev);
15468
15469 intel_cleanup_overlay(dev);
15470
15471 mutex_lock(&dev->struct_mutex);
15472 intel_cleanup_gt_powersave(dev);
15473 mutex_unlock(&dev->struct_mutex);
15474 }
15475
15476 /*
15477 * Return which encoder is currently attached for connector.
15478 */
15479 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15480 {
15481 return &intel_attached_encoder(connector)->base;
15482 }
15483
15484 void intel_connector_attach_encoder(struct intel_connector *connector,
15485 struct intel_encoder *encoder)
15486 {
15487 connector->encoder = encoder;
15488 drm_mode_connector_attach_encoder(&connector->base,
15489 &encoder->base);
15490 }
15491
15492 /*
15493 * set vga decode state - true == enable VGA decode
15494 */
15495 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15496 {
15497 struct drm_i915_private *dev_priv = dev->dev_private;
15498 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15499 u16 gmch_ctrl;
15500
15501 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15502 DRM_ERROR("failed to read control word\n");
15503 return -EIO;
15504 }
15505
15506 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15507 return 0;
15508
15509 if (state)
15510 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15511 else
15512 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15513
15514 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15515 DRM_ERROR("failed to write control word\n");
15516 return -EIO;
15517 }
15518
15519 return 0;
15520 }
15521
15522 struct intel_display_error_state {
15523
15524 u32 power_well_driver;
15525
15526 int num_transcoders;
15527
15528 struct intel_cursor_error_state {
15529 u32 control;
15530 u32 position;
15531 u32 base;
15532 u32 size;
15533 } cursor[I915_MAX_PIPES];
15534
15535 struct intel_pipe_error_state {
15536 bool power_domain_on;
15537 u32 source;
15538 u32 stat;
15539 } pipe[I915_MAX_PIPES];
15540
15541 struct intel_plane_error_state {
15542 u32 control;
15543 u32 stride;
15544 u32 size;
15545 u32 pos;
15546 u32 addr;
15547 u32 surface;
15548 u32 tile_offset;
15549 } plane[I915_MAX_PIPES];
15550
15551 struct intel_transcoder_error_state {
15552 bool power_domain_on;
15553 enum transcoder cpu_transcoder;
15554
15555 u32 conf;
15556
15557 u32 htotal;
15558 u32 hblank;
15559 u32 hsync;
15560 u32 vtotal;
15561 u32 vblank;
15562 u32 vsync;
15563 } transcoder[4];
15564 };
15565
15566 struct intel_display_error_state *
15567 intel_display_capture_error_state(struct drm_device *dev)
15568 {
15569 struct drm_i915_private *dev_priv = dev->dev_private;
15570 struct intel_display_error_state *error;
15571 int transcoders[] = {
15572 TRANSCODER_A,
15573 TRANSCODER_B,
15574 TRANSCODER_C,
15575 TRANSCODER_EDP,
15576 };
15577 int i;
15578
15579 if (INTEL_INFO(dev)->num_pipes == 0)
15580 return NULL;
15581
15582 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15583 if (error == NULL)
15584 return NULL;
15585
15586 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15587 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15588
15589 for_each_pipe(dev_priv, i) {
15590 error->pipe[i].power_domain_on =
15591 __intel_display_power_is_enabled(dev_priv,
15592 POWER_DOMAIN_PIPE(i));
15593 if (!error->pipe[i].power_domain_on)
15594 continue;
15595
15596 error->cursor[i].control = I915_READ(CURCNTR(i));
15597 error->cursor[i].position = I915_READ(CURPOS(i));
15598 error->cursor[i].base = I915_READ(CURBASE(i));
15599
15600 error->plane[i].control = I915_READ(DSPCNTR(i));
15601 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15602 if (INTEL_INFO(dev)->gen <= 3) {
15603 error->plane[i].size = I915_READ(DSPSIZE(i));
15604 error->plane[i].pos = I915_READ(DSPPOS(i));
15605 }
15606 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15607 error->plane[i].addr = I915_READ(DSPADDR(i));
15608 if (INTEL_INFO(dev)->gen >= 4) {
15609 error->plane[i].surface = I915_READ(DSPSURF(i));
15610 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15611 }
15612
15613 error->pipe[i].source = I915_READ(PIPESRC(i));
15614
15615 if (HAS_GMCH_DISPLAY(dev))
15616 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15617 }
15618
15619 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15620 if (HAS_DDI(dev_priv->dev))
15621 error->num_transcoders++; /* Account for eDP. */
15622
15623 for (i = 0; i < error->num_transcoders; i++) {
15624 enum transcoder cpu_transcoder = transcoders[i];
15625
15626 error->transcoder[i].power_domain_on =
15627 __intel_display_power_is_enabled(dev_priv,
15628 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15629 if (!error->transcoder[i].power_domain_on)
15630 continue;
15631
15632 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15633
15634 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15635 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15636 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15637 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15638 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15639 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15640 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15641 }
15642
15643 return error;
15644 }
15645
15646 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15647
15648 void
15649 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15650 struct drm_device *dev,
15651 struct intel_display_error_state *error)
15652 {
15653 struct drm_i915_private *dev_priv = dev->dev_private;
15654 int i;
15655
15656 if (!error)
15657 return;
15658
15659 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15660 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15661 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15662 error->power_well_driver);
15663 for_each_pipe(dev_priv, i) {
15664 err_printf(m, "Pipe [%d]:\n", i);
15665 err_printf(m, " Power: %s\n",
15666 error->pipe[i].power_domain_on ? "on" : "off");
15667 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15668 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15669
15670 err_printf(m, "Plane [%d]:\n", i);
15671 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15672 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15673 if (INTEL_INFO(dev)->gen <= 3) {
15674 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15675 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15676 }
15677 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15678 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15679 if (INTEL_INFO(dev)->gen >= 4) {
15680 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15681 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15682 }
15683
15684 err_printf(m, "Cursor [%d]:\n", i);
15685 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15686 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15687 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15688 }
15689
15690 for (i = 0; i < error->num_transcoders; i++) {
15691 err_printf(m, "CPU transcoder: %c\n",
15692 transcoder_name(error->transcoder[i].cpu_transcoder));
15693 err_printf(m, " Power: %s\n",
15694 error->transcoder[i].power_domain_on ? "on" : "off");
15695 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15696 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15697 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15698 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15699 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15700 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15701 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15702 }
15703 }
15704
15705 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15706 {
15707 struct intel_crtc *crtc;
15708
15709 for_each_intel_crtc(dev, crtc) {
15710 struct intel_unpin_work *work;
15711
15712 spin_lock_irq(&dev->event_lock);
15713
15714 work = crtc->unpin_work;
15715
15716 if (work && work->event &&
15717 work->event->base.file_priv == file) {
15718 kfree(work->event);
15719 work->event = NULL;
15720 }
15721
15722 spin_unlock_irq(&dev->event_lock);
15723 }
15724 }
Linux kernel - Deliverables
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