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drm/i915: Flush outstanding unpin tasks before pageflipping
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
47
48 typedef struct {
49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
58 } intel_clock_t;
59
60 typedef struct {
61 int min, max;
62 } intel_range_t;
63
64 typedef struct {
65 int dot_limit;
66 int p2_slow, p2_fast;
67 } intel_p2_t;
68
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
71 struct intel_limit {
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
76 };
77
78 /* FDI */
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
81 int
82 intel_pch_rawclk(struct drm_device *dev)
83 {
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89 }
90
91 static bool
92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
95 static bool
96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
99
100 static bool
101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
104 static bool
105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
109 static bool
110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
114 static inline u32 /* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device *dev)
116 {
117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
122 }
123
124 static const intel_limit_t intel_limits_i8xx_dvo = {
125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
135 .find_pll = intel_find_best_PLL,
136 };
137
138 static const intel_limit_t intel_limits_i8xx_lvds = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
149 .find_pll = intel_find_best_PLL,
150 };
151
152 static const intel_limit_t intel_limits_i9xx_sdvo = {
153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
163 .find_pll = intel_find_best_PLL,
164 };
165
166 static const intel_limit_t intel_limits_i9xx_lvds = {
167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
177 .find_pll = intel_find_best_PLL,
178 };
179
180
181 static const intel_limit_t intel_limits_g4x_sdvo = {
182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
193 },
194 .find_pll = intel_g4x_find_best_PLL,
195 };
196
197 static const intel_limit_t intel_limits_g4x_hdmi = {
198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
208 .find_pll = intel_g4x_find_best_PLL,
209 };
210
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
222 },
223 .find_pll = intel_g4x_find_best_PLL,
224 };
225
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
237 },
238 .find_pll = intel_g4x_find_best_PLL,
239 };
240
241 static const intel_limit_t intel_limits_g4x_display_port = {
242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
251 .p2_slow = 10, .p2_fast = 10 },
252 .find_pll = intel_find_pll_g4x_dp,
253 };
254
255 static const intel_limit_t intel_limits_pineview_sdvo = {
256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
268 .find_pll = intel_find_best_PLL,
269 };
270
271 static const intel_limit_t intel_limits_pineview_lvds = {
272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
282 .find_pll = intel_find_best_PLL,
283 };
284
285 /* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
290 static const intel_limit_t intel_limits_ironlake_dac = {
291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
301 .find_pll = intel_g4x_find_best_PLL,
302 };
303
304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
315 .find_pll = intel_g4x_find_best_PLL,
316 };
317
318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
329 .find_pll = intel_g4x_find_best_PLL,
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 .find_pll = intel_g4x_find_best_PLL,
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_ironlake_display_port = {
362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
371 .p2_slow = 10, .p2_fast = 10 },
372 .find_pll = intel_find_pll_ironlake_dp,
373 };
374
375 static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387 };
388
389 static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
391 .vco = { .min = 4000000, .max = 5994000},
392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401 };
402
403 static const intel_limit_t intel_limits_vlv_dp = {
404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
406 .n = { .min = 1, .max = 7 },
407 .m = { .min = 22, .max = 450 },
408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415 };
416
417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418 {
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437 out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440 }
441
442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444 {
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460 out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462 }
463
464 static void vlv_init_dpio(struct drm_device *dev)
465 {
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473 }
474
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476 {
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479 }
480
481 static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491 };
492
493 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495 {
496 unsigned int val;
497
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519 }
520
521 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
523 {
524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
526 const intel_limit_t *limit;
527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
530 /* LVDS dual channel */
531 if (refclk == 100000)
532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
536 if (refclk == 100000)
537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
543 limit = &intel_limits_ironlake_display_port;
544 else
545 limit = &intel_limits_ironlake_dac;
546
547 return limit;
548 }
549
550 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551 {
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
557 if (is_dual_link_lvds(dev_priv, LVDS))
558 /* LVDS with dual channel */
559 limit = &intel_limits_g4x_dual_channel_lvds;
560 else
561 /* LVDS with dual channel */
562 limit = &intel_limits_g4x_single_channel_lvds;
563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
565 limit = &intel_limits_g4x_hdmi;
566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
567 limit = &intel_limits_g4x_sdvo;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
569 limit = &intel_limits_g4x_display_port;
570 } else /* The option is for other outputs */
571 limit = &intel_limits_i9xx_sdvo;
572
573 return limit;
574 }
575
576 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
577 {
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
581 if (HAS_PCH_SPLIT(dev))
582 limit = intel_ironlake_limit(crtc, refclk);
583 else if (IS_G4X(dev)) {
584 limit = intel_g4x_limit(crtc);
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
588 else
589 limit = &intel_limits_pineview_sdvo;
590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
604 limit = &intel_limits_i8xx_lvds;
605 else
606 limit = &intel_limits_i8xx_dvo;
607 }
608 return limit;
609 }
610
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk, intel_clock_t *clock)
613 {
614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618 }
619
620 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621 {
622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
624 return;
625 }
626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630 }
631
632 /**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
635 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
636 {
637 struct drm_device *dev = crtc->dev;
638 struct intel_encoder *encoder;
639
640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
642 return true;
643
644 return false;
645 }
646
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
648 /**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
653 static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
656 {
657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock->p < limit->p.min || limit->p.max < clock->p)
660 INTELPllInvalid("p out of range\n");
661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock->m < limit->m.min || limit->m.max < clock->m)
668 INTELPllInvalid("m out of range\n");
669 if (clock->n < limit->n.min || limit->n.max < clock->n)
670 INTELPllInvalid("n out of range\n");
671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
677 INTELPllInvalid("dot out of range\n");
678
679 return true;
680 }
681
682 static bool
683 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686
687 {
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
691 int err = target;
692
693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
694 (I915_READ(LVDS)) != 0) {
695 /*
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
699 * even can.
700 */
701 if (is_dual_link_lvds(dev_priv, LVDS))
702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
712 memset(best_clock, 0, sizeof(*best_clock));
713
714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
718 /* m1 is always 0 in Pineview */
719 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
720 break;
721 for (clock.n = limit->n.min;
722 clock.n <= limit->n.max; clock.n++) {
723 for (clock.p1 = limit->p1.min;
724 clock.p1 <= limit->p1.max; clock.p1++) {
725 int this_err;
726
727 intel_clock(dev, refclk, &clock);
728 if (!intel_PLL_is_valid(dev, limit,
729 &clock))
730 continue;
731 if (match_clock &&
732 clock.p != match_clock->p)
733 continue;
734
735 this_err = abs(clock.dot - target);
736 if (this_err < err) {
737 *best_clock = clock;
738 err = this_err;
739 }
740 }
741 }
742 }
743 }
744
745 return (err != target);
746 }
747
748 static bool
749 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
750 int target, int refclk, intel_clock_t *match_clock,
751 intel_clock_t *best_clock)
752 {
753 struct drm_device *dev = crtc->dev;
754 struct drm_i915_private *dev_priv = dev->dev_private;
755 intel_clock_t clock;
756 int max_n;
757 bool found;
758 /* approximately equals target * 0.00585 */
759 int err_most = (target >> 8) + (target >> 9);
760 found = false;
761
762 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
763 int lvds_reg;
764
765 if (HAS_PCH_SPLIT(dev))
766 lvds_reg = PCH_LVDS;
767 else
768 lvds_reg = LVDS;
769 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
770 LVDS_CLKB_POWER_UP)
771 clock.p2 = limit->p2.p2_fast;
772 else
773 clock.p2 = limit->p2.p2_slow;
774 } else {
775 if (target < limit->p2.dot_limit)
776 clock.p2 = limit->p2.p2_slow;
777 else
778 clock.p2 = limit->p2.p2_fast;
779 }
780
781 memset(best_clock, 0, sizeof(*best_clock));
782 max_n = limit->n.max;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock.m1 = limit->m1.max;
787 clock.m1 >= limit->m1.min; clock.m1--) {
788 for (clock.m2 = limit->m2.max;
789 clock.m2 >= limit->m2.min; clock.m2--) {
790 for (clock.p1 = limit->p1.max;
791 clock.p1 >= limit->p1.min; clock.p1--) {
792 int this_err;
793
794 intel_clock(dev, refclk, &clock);
795 if (!intel_PLL_is_valid(dev, limit,
796 &clock))
797 continue;
798 if (match_clock &&
799 clock.p != match_clock->p)
800 continue;
801
802 this_err = abs(clock.dot - target);
803 if (this_err < err_most) {
804 *best_clock = clock;
805 err_most = this_err;
806 max_n = clock.n;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813 return found;
814 }
815
816 static bool
817 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820 {
821 struct drm_device *dev = crtc->dev;
822 intel_clock_t clock;
823
824 if (target < 200000) {
825 clock.n = 1;
826 clock.p1 = 2;
827 clock.p2 = 10;
828 clock.m1 = 12;
829 clock.m2 = 9;
830 } else {
831 clock.n = 2;
832 clock.p1 = 1;
833 clock.p2 = 10;
834 clock.m1 = 14;
835 clock.m2 = 8;
836 }
837 intel_clock(dev, refclk, &clock);
838 memcpy(best_clock, &clock, sizeof(intel_clock_t));
839 return true;
840 }
841
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
843 static bool
844 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
845 int target, int refclk, intel_clock_t *match_clock,
846 intel_clock_t *best_clock)
847 {
848 intel_clock_t clock;
849 if (target < 200000) {
850 clock.p1 = 2;
851 clock.p2 = 10;
852 clock.n = 2;
853 clock.m1 = 23;
854 clock.m2 = 8;
855 } else {
856 clock.p1 = 1;
857 clock.p2 = 10;
858 clock.n = 1;
859 clock.m1 = 14;
860 clock.m2 = 2;
861 }
862 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
863 clock.p = (clock.p1 * clock.p2);
864 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
865 clock.vco = 0;
866 memcpy(best_clock, &clock, sizeof(intel_clock_t));
867 return true;
868 }
869 static bool
870 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
871 int target, int refclk, intel_clock_t *match_clock,
872 intel_clock_t *best_clock)
873 {
874 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
875 u32 m, n, fastclk;
876 u32 updrate, minupdate, fracbits, p;
877 unsigned long bestppm, ppm, absppm;
878 int dotclk, flag;
879
880 flag = 0;
881 dotclk = target * 1000;
882 bestppm = 1000000;
883 ppm = absppm = 0;
884 fastclk = dotclk / (2*100);
885 updrate = 0;
886 minupdate = 19200;
887 fracbits = 1;
888 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
889 bestm1 = bestm2 = bestp1 = bestp2 = 0;
890
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
893 updrate = refclk / n;
894 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
895 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
896 if (p2 > 10)
897 p2 = p2 - 1;
898 p = p1 * p2;
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
901 m2 = (((2*(fastclk * p * n / m1 )) +
902 refclk) / (2*refclk));
903 m = m1 * m2;
904 vco = updrate * m;
905 if (vco >= limit->vco.min && vco < limit->vco.max) {
906 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
907 absppm = (ppm > 0) ? ppm : (-ppm);
908 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
909 bestppm = 0;
910 flag = 1;
911 }
912 if (absppm < bestppm - 10) {
913 bestppm = absppm;
914 flag = 1;
915 }
916 if (flag) {
917 bestn = n;
918 bestm1 = m1;
919 bestm2 = m2;
920 bestp1 = p1;
921 bestp2 = p2;
922 flag = 0;
923 }
924 }
925 }
926 }
927 }
928 }
929 best_clock->n = bestn;
930 best_clock->m1 = bestm1;
931 best_clock->m2 = bestm2;
932 best_clock->p1 = bestp1;
933 best_clock->p2 = bestp2;
934
935 return true;
936 }
937
938 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
939 enum pipe pipe)
940 {
941 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
943
944 return intel_crtc->cpu_transcoder;
945 }
946
947 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
948 {
949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 frame, frame_reg = PIPEFRAME(pipe);
951
952 frame = I915_READ(frame_reg);
953
954 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
956 }
957
958 /**
959 * intel_wait_for_vblank - wait for vblank on a given pipe
960 * @dev: drm device
961 * @pipe: pipe to wait for
962 *
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
964 * mode setting code.
965 */
966 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
967 {
968 struct drm_i915_private *dev_priv = dev->dev_private;
969 int pipestat_reg = PIPESTAT(pipe);
970
971 if (INTEL_INFO(dev)->gen >= 5) {
972 ironlake_wait_for_vblank(dev, pipe);
973 return;
974 }
975
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
978 *
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
985 * vblanks...
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
988 */
989 I915_WRITE(pipestat_reg,
990 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
991
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg) &
994 PIPE_VBLANK_INTERRUPT_STATUS,
995 50))
996 DRM_DEBUG_KMS("vblank wait timed out\n");
997 }
998
999 /*
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1001 * @dev: drm device
1002 * @pipe: pipe to wait for
1003 *
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1007 *
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1010 *
1011 * Otherwise:
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1014 *
1015 */
1016 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1017 {
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1020 pipe);
1021
1022 if (INTEL_INFO(dev)->gen >= 4) {
1023 int reg = PIPECONF(cpu_transcoder);
1024
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1027 100))
1028 WARN(1, "pipe_off wait timed out\n");
1029 } else {
1030 u32 last_line, line_mask;
1031 int reg = PIPEDSL(pipe);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033
1034 if (IS_GEN2(dev))
1035 line_mask = DSL_LINEMASK_GEN2;
1036 else
1037 line_mask = DSL_LINEMASK_GEN3;
1038
1039 /* Wait for the display line to settle */
1040 do {
1041 last_line = I915_READ(reg) & line_mask;
1042 mdelay(5);
1043 } while (((I915_READ(reg) & line_mask) != last_line) &&
1044 time_after(timeout, jiffies));
1045 if (time_after(jiffies, timeout))
1046 WARN(1, "pipe_off wait timed out\n");
1047 }
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1072
1073 /* For ILK+ */
1074 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1075 struct intel_pch_pll *pll,
1076 struct intel_crtc *crtc,
1077 bool state)
1078 {
1079 u32 val;
1080 bool cur_state;
1081
1082 if (HAS_PCH_LPT(dev_priv->dev)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1084 return;
1085 }
1086
1087 if (WARN (!pll,
1088 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1089 return;
1090
1091 val = I915_READ(pll->pll_reg);
1092 cur_state = !!(val & DPLL_VCO_ENABLE);
1093 WARN(cur_state != state,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll->pll_reg, state_string(state), state_string(cur_state), val);
1096
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1099 u32 pch_dpll;
1100
1101 pch_dpll = I915_READ(PCH_DPLL_SEL);
1102 cur_state = pll->pll_reg == _PCH_DPLL_B;
1103 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state, crtc->pipe, pch_dpll)) {
1106 cur_state = !!(val >> (4*crtc->pipe + 3));
1107 WARN(cur_state != state,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll->pll_reg == _PCH_DPLL_B,
1110 state_string(state),
1111 crtc->pipe,
1112 val);
1113 }
1114 }
1115 }
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1118
1119 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
1121 {
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1126 pipe);
1127
1128 if (IS_HASWELL(dev_priv->dev)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1133 } else {
1134 reg = FDI_TX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_TX_ENABLE);
1137 }
1138 WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141 }
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1147 {
1148 int reg;
1149 u32 val;
1150 bool cur_state;
1151
1152 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1153 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1154 return;
1155 } else {
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_ENABLE);
1159 }
1160 WARN(cur_state != state,
1161 "FDI RX state assertion failure (expected %s, current %s)\n",
1162 state_string(state), state_string(cur_state));
1163 }
1164 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1165 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1166
1167 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1168 enum pipe pipe)
1169 {
1170 int reg;
1171 u32 val;
1172
1173 /* ILK FDI PLL is always enabled */
1174 if (dev_priv->info->gen == 5)
1175 return;
1176
1177 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1178 if (IS_HASWELL(dev_priv->dev))
1179 return;
1180
1181 reg = FDI_TX_CTL(pipe);
1182 val = I915_READ(reg);
1183 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1184 }
1185
1186 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe)
1188 {
1189 int reg;
1190 u32 val;
1191
1192 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1193 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1194 return;
1195 }
1196 reg = FDI_RX_CTL(pipe);
1197 val = I915_READ(reg);
1198 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1199 }
1200
1201 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1202 enum pipe pipe)
1203 {
1204 int pp_reg, lvds_reg;
1205 u32 val;
1206 enum pipe panel_pipe = PIPE_A;
1207 bool locked = true;
1208
1209 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1210 pp_reg = PCH_PP_CONTROL;
1211 lvds_reg = PCH_LVDS;
1212 } else {
1213 pp_reg = PP_CONTROL;
1214 lvds_reg = LVDS;
1215 }
1216
1217 val = I915_READ(pp_reg);
1218 if (!(val & PANEL_POWER_ON) ||
1219 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1220 locked = false;
1221
1222 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224
1225 WARN(panel_pipe == pipe && locked,
1226 "panel assertion failure, pipe %c regs locked\n",
1227 pipe_name(pipe));
1228 }
1229
1230 void assert_pipe(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, bool state)
1232 {
1233 int reg;
1234 u32 val;
1235 bool cur_state;
1236 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1237 pipe);
1238
1239 /* if we need the pipe A quirk it must be always on */
1240 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1241 state = true;
1242
1243 reg = PIPECONF(cpu_transcoder);
1244 val = I915_READ(reg);
1245 cur_state = !!(val & PIPECONF_ENABLE);
1246 WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271 {
1272 int reg, i;
1273 u32 val;
1274 int cur_pipe;
1275
1276 /* Planes are fixed to pipes on ILK+ */
1277 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1278 reg = DSPCNTR(pipe);
1279 val = I915_READ(reg);
1280 WARN((val & DISPLAY_PLANE_ENABLE),
1281 "plane %c assertion failure, should be disabled but not\n",
1282 plane_name(pipe));
1283 return;
1284 }
1285
1286 /* Need to check both planes against the pipe */
1287 for (i = 0; i < 2; i++) {
1288 reg = DSPCNTR(i);
1289 val = I915_READ(reg);
1290 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1291 DISPPLANE_SEL_PIPE_SHIFT;
1292 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1293 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1294 plane_name(i), pipe_name(pipe));
1295 }
1296 }
1297
1298 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1299 {
1300 u32 val;
1301 bool enabled;
1302
1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1305 return;
1306 }
1307
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1312 }
1313
1314 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1315 enum pipe pipe)
1316 {
1317 int reg;
1318 u32 val;
1319 bool enabled;
1320
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1324 WARN(enabled,
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1326 pipe_name(pipe));
1327 }
1328
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1331 {
1332 if ((val & DP_PORT_EN) == 0)
1333 return false;
1334
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1339 return false;
1340 } else {
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1342 return false;
1343 }
1344 return true;
1345 }
1346
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1349 {
1350 if ((val & PORT_ENABLE) == 0)
1351 return false;
1352
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
1354 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1355 return false;
1356 } else {
1357 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1358 return false;
1359 }
1360 return true;
1361 }
1362
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1365 {
1366 if ((val & LVDS_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1371 return false;
1372 } else {
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1374 return false;
1375 }
1376 return true;
1377 }
1378
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1381 {
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1383 return false;
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1386 return false;
1387 } else {
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1389 return false;
1390 }
1391 return true;
1392 }
1393
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, int reg, u32 port_sel)
1396 {
1397 u32 val = I915_READ(reg);
1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400 reg, pipe_name(pipe));
1401
1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
1404 "IBX PCH dp port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1409 {
1410 u32 val = I915_READ(reg);
1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1414
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1416 && (val & SDVO_PIPE_B_SELECT),
1417 "IBX PCH hdmi port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe)
1422 {
1423 int reg;
1424 u32 val;
1425
1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1429
1430 reg = PCH_ADPA;
1431 val = I915_READ(reg);
1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
1434 pipe_name(pipe));
1435
1436 reg = PCH_LVDS;
1437 val = I915_READ(reg);
1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1440 pipe_name(pipe));
1441
1442 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1445 }
1446
1447 /**
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1451 *
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1455 *
1456 * Note! This is for pre-ILK only.
1457 *
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1459 */
1460 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1461 {
1462 int reg;
1463 u32 val;
1464
1465 /* No really, not for ILK+ */
1466 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1467
1468 /* PLL is protected by panel, make sure we can write it */
1469 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1470 assert_panel_unlocked(dev_priv, pipe);
1471
1472 reg = DPLL(pipe);
1473 val = I915_READ(reg);
1474 val |= DPLL_VCO_ENABLE;
1475
1476 /* We do this three times for luck */
1477 I915_WRITE(reg, val);
1478 POSTING_READ(reg);
1479 udelay(150); /* wait for warmup */
1480 I915_WRITE(reg, val);
1481 POSTING_READ(reg);
1482 udelay(150); /* wait for warmup */
1483 I915_WRITE(reg, val);
1484 POSTING_READ(reg);
1485 udelay(150); /* wait for warmup */
1486 }
1487
1488 /**
1489 * intel_disable_pll - disable a PLL
1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to disable
1492 *
1493 * Disable the PLL for @pipe, making sure the pipe is off first.
1494 *
1495 * Note! This is for pre-ILK only.
1496 */
1497 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1498 {
1499 int reg;
1500 u32 val;
1501
1502 /* Don't disable pipe A or pipe A PLLs if needed */
1503 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1504 return;
1505
1506 /* Make sure the pipe isn't still relying on us */
1507 assert_pipe_disabled(dev_priv, pipe);
1508
1509 reg = DPLL(pipe);
1510 val = I915_READ(reg);
1511 val &= ~DPLL_VCO_ENABLE;
1512 I915_WRITE(reg, val);
1513 POSTING_READ(reg);
1514 }
1515
1516 /* SBI access */
1517 static void
1518 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1519 {
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1523 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1524 100)) {
1525 DRM_ERROR("timeout waiting for SBI to become ready\n");
1526 goto out_unlock;
1527 }
1528
1529 I915_WRITE(SBI_ADDR,
1530 (reg << 16));
1531 I915_WRITE(SBI_DATA,
1532 value);
1533 I915_WRITE(SBI_CTL_STAT,
1534 SBI_BUSY |
1535 SBI_CTL_OP_CRWR);
1536
1537 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1540 goto out_unlock;
1541 }
1542
1543 out_unlock:
1544 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1545 }
1546
1547 static u32
1548 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1549 {
1550 unsigned long flags;
1551 u32 value = 0;
1552
1553 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1554 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1555 100)) {
1556 DRM_ERROR("timeout waiting for SBI to become ready\n");
1557 goto out_unlock;
1558 }
1559
1560 I915_WRITE(SBI_ADDR,
1561 (reg << 16));
1562 I915_WRITE(SBI_CTL_STAT,
1563 SBI_BUSY |
1564 SBI_CTL_OP_CRRD);
1565
1566 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1569 goto out_unlock;
1570 }
1571
1572 value = I915_READ(SBI_DATA);
1573
1574 out_unlock:
1575 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1576 return value;
1577 }
1578
1579 /**
1580 * ironlake_enable_pch_pll - enable PCH PLL
1581 * @dev_priv: i915 private structure
1582 * @pipe: pipe PLL to enable
1583 *
1584 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1585 * drives the transcoder clock.
1586 */
1587 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1588 {
1589 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1590 struct intel_pch_pll *pll;
1591 int reg;
1592 u32 val;
1593
1594 /* PCH PLLs only available on ILK, SNB and IVB */
1595 BUG_ON(dev_priv->info->gen < 5);
1596 pll = intel_crtc->pch_pll;
1597 if (pll == NULL)
1598 return;
1599
1600 if (WARN_ON(pll->refcount == 0))
1601 return;
1602
1603 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1604 pll->pll_reg, pll->active, pll->on,
1605 intel_crtc->base.base.id);
1606
1607 /* PCH refclock must be enabled first */
1608 assert_pch_refclk_enabled(dev_priv);
1609
1610 if (pll->active++ && pll->on) {
1611 assert_pch_pll_enabled(dev_priv, pll, NULL);
1612 return;
1613 }
1614
1615 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1616
1617 reg = pll->pll_reg;
1618 val = I915_READ(reg);
1619 val |= DPLL_VCO_ENABLE;
1620 I915_WRITE(reg, val);
1621 POSTING_READ(reg);
1622 udelay(200);
1623
1624 pll->on = true;
1625 }
1626
1627 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1628 {
1629 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1630 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1631 int reg;
1632 u32 val;
1633
1634 /* PCH only available on ILK+ */
1635 BUG_ON(dev_priv->info->gen < 5);
1636 if (pll == NULL)
1637 return;
1638
1639 if (WARN_ON(pll->refcount == 0))
1640 return;
1641
1642 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1643 pll->pll_reg, pll->active, pll->on,
1644 intel_crtc->base.base.id);
1645
1646 if (WARN_ON(pll->active == 0)) {
1647 assert_pch_pll_disabled(dev_priv, pll, NULL);
1648 return;
1649 }
1650
1651 if (--pll->active) {
1652 assert_pch_pll_enabled(dev_priv, pll, NULL);
1653 return;
1654 }
1655
1656 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1657
1658 /* Make sure transcoder isn't still depending on us */
1659 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1660
1661 reg = pll->pll_reg;
1662 val = I915_READ(reg);
1663 val &= ~DPLL_VCO_ENABLE;
1664 I915_WRITE(reg, val);
1665 POSTING_READ(reg);
1666 udelay(200);
1667
1668 pll->on = false;
1669 }
1670
1671 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1672 enum pipe pipe)
1673 {
1674 struct drm_device *dev = dev_priv->dev;
1675 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1676 uint32_t reg, val, pipeconf_val;
1677
1678 /* PCH only available on ILK+ */
1679 BUG_ON(dev_priv->info->gen < 5);
1680
1681 /* Make sure PCH DPLL is enabled */
1682 assert_pch_pll_enabled(dev_priv,
1683 to_intel_crtc(crtc)->pch_pll,
1684 to_intel_crtc(crtc));
1685
1686 /* FDI must be feeding us bits for PCH ports */
1687 assert_fdi_tx_enabled(dev_priv, pipe);
1688 assert_fdi_rx_enabled(dev_priv, pipe);
1689
1690 if (HAS_PCH_CPT(dev)) {
1691 /* Workaround: Set the timing override bit before enabling the
1692 * pch transcoder. */
1693 reg = TRANS_CHICKEN2(pipe);
1694 val = I915_READ(reg);
1695 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1696 I915_WRITE(reg, val);
1697 }
1698
1699 reg = TRANSCONF(pipe);
1700 val = I915_READ(reg);
1701 pipeconf_val = I915_READ(PIPECONF(pipe));
1702
1703 if (HAS_PCH_IBX(dev_priv->dev)) {
1704 /*
1705 * make the BPC in transcoder be consistent with
1706 * that in pipeconf reg.
1707 */
1708 val &= ~PIPE_BPC_MASK;
1709 val |= pipeconf_val & PIPE_BPC_MASK;
1710 }
1711
1712 val &= ~TRANS_INTERLACE_MASK;
1713 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1714 if (HAS_PCH_IBX(dev_priv->dev) &&
1715 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1716 val |= TRANS_LEGACY_INTERLACED_ILK;
1717 else
1718 val |= TRANS_INTERLACED;
1719 else
1720 val |= TRANS_PROGRESSIVE;
1721
1722 I915_WRITE(reg, val | TRANS_ENABLE);
1723 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1724 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1725 }
1726
1727 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1728 enum transcoder cpu_transcoder)
1729 {
1730 u32 val, pipeconf_val;
1731
1732 /* PCH only available on ILK+ */
1733 BUG_ON(dev_priv->info->gen < 5);
1734
1735 /* FDI must be feeding us bits for PCH ports */
1736 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1737 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1738
1739 /* Workaround: set timing override bit. */
1740 val = I915_READ(_TRANSA_CHICKEN2);
1741 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1742 I915_WRITE(_TRANSA_CHICKEN2, val);
1743
1744 val = TRANS_ENABLE;
1745 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1746
1747 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1748 PIPECONF_INTERLACED_ILK)
1749 val |= TRANS_INTERLACED;
1750 else
1751 val |= TRANS_PROGRESSIVE;
1752
1753 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1754 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1755 DRM_ERROR("Failed to enable PCH transcoder\n");
1756 }
1757
1758 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1759 enum pipe pipe)
1760 {
1761 struct drm_device *dev = dev_priv->dev;
1762 uint32_t reg, val;
1763
1764 /* FDI relies on the transcoder */
1765 assert_fdi_tx_disabled(dev_priv, pipe);
1766 assert_fdi_rx_disabled(dev_priv, pipe);
1767
1768 /* Ports must be off as well */
1769 assert_pch_ports_disabled(dev_priv, pipe);
1770
1771 reg = TRANSCONF(pipe);
1772 val = I915_READ(reg);
1773 val &= ~TRANS_ENABLE;
1774 I915_WRITE(reg, val);
1775 /* wait for PCH transcoder off, transcoder state */
1776 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1777 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1778
1779 if (!HAS_PCH_IBX(dev)) {
1780 /* Workaround: Clear the timing override chicken bit again. */
1781 reg = TRANS_CHICKEN2(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1784 I915_WRITE(reg, val);
1785 }
1786 }
1787
1788 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1789 {
1790 u32 val;
1791
1792 val = I915_READ(_TRANSACONF);
1793 val &= ~TRANS_ENABLE;
1794 I915_WRITE(_TRANSACONF, val);
1795 /* wait for PCH transcoder off, transcoder state */
1796 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1797 DRM_ERROR("Failed to disable PCH transcoder\n");
1798
1799 /* Workaround: clear timing override bit. */
1800 val = I915_READ(_TRANSA_CHICKEN2);
1801 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1802 I915_WRITE(_TRANSA_CHICKEN2, val);
1803 }
1804
1805 /**
1806 * intel_enable_pipe - enable a pipe, asserting requirements
1807 * @dev_priv: i915 private structure
1808 * @pipe: pipe to enable
1809 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1810 *
1811 * Enable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1813 *
1814 * @pipe should be %PIPE_A or %PIPE_B.
1815 *
1816 * Will wait until the pipe is actually running (i.e. first vblank) before
1817 * returning.
1818 */
1819 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1820 bool pch_port)
1821 {
1822 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1823 pipe);
1824 int reg;
1825 u32 val;
1826
1827 /*
1828 * A pipe without a PLL won't actually be able to drive bits from
1829 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1830 * need the check.
1831 */
1832 if (!HAS_PCH_SPLIT(dev_priv->dev))
1833 assert_pll_enabled(dev_priv, pipe);
1834 else {
1835 if (pch_port) {
1836 /* if driving the PCH, we need FDI enabled */
1837 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1838 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1839 }
1840 /* FIXME: assert CPU port conditions for SNB+ */
1841 }
1842
1843 reg = PIPECONF(cpu_transcoder);
1844 val = I915_READ(reg);
1845 if (val & PIPECONF_ENABLE)
1846 return;
1847
1848 I915_WRITE(reg, val | PIPECONF_ENABLE);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850 }
1851
1852 /**
1853 * intel_disable_pipe - disable a pipe, asserting requirements
1854 * @dev_priv: i915 private structure
1855 * @pipe: pipe to disable
1856 *
1857 * Disable @pipe, making sure that various hardware specific requirements
1858 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1859 *
1860 * @pipe should be %PIPE_A or %PIPE_B.
1861 *
1862 * Will wait until the pipe has shut down before returning.
1863 */
1864 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1865 enum pipe pipe)
1866 {
1867 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1868 pipe);
1869 int reg;
1870 u32 val;
1871
1872 /*
1873 * Make sure planes won't keep trying to pump pixels to us,
1874 * or we might hang the display.
1875 */
1876 assert_planes_disabled(dev_priv, pipe);
1877
1878 /* Don't disable pipe A or pipe A PLLs if needed */
1879 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1880 return;
1881
1882 reg = PIPECONF(cpu_transcoder);
1883 val = I915_READ(reg);
1884 if ((val & PIPECONF_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1888 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1889 }
1890
1891 /*
1892 * Plane regs are double buffered, going from enabled->disabled needs a
1893 * trigger in order to latch. The display address reg provides this.
1894 */
1895 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1896 enum plane plane)
1897 {
1898 if (dev_priv->info->gen >= 4)
1899 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1900 else
1901 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1902 }
1903
1904 /**
1905 * intel_enable_plane - enable a display plane on a given pipe
1906 * @dev_priv: i915 private structure
1907 * @plane: plane to enable
1908 * @pipe: pipe being fed
1909 *
1910 * Enable @plane on @pipe, making sure that @pipe is running first.
1911 */
1912 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1913 enum plane plane, enum pipe pipe)
1914 {
1915 int reg;
1916 u32 val;
1917
1918 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1919 assert_pipe_enabled(dev_priv, pipe);
1920
1921 reg = DSPCNTR(plane);
1922 val = I915_READ(reg);
1923 if (val & DISPLAY_PLANE_ENABLE)
1924 return;
1925
1926 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1927 intel_flush_display_plane(dev_priv, plane);
1928 intel_wait_for_vblank(dev_priv->dev, pipe);
1929 }
1930
1931 /**
1932 * intel_disable_plane - disable a display plane
1933 * @dev_priv: i915 private structure
1934 * @plane: plane to disable
1935 * @pipe: pipe consuming the data
1936 *
1937 * Disable @plane; should be an independent operation.
1938 */
1939 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1940 enum plane plane, enum pipe pipe)
1941 {
1942 int reg;
1943 u32 val;
1944
1945 reg = DSPCNTR(plane);
1946 val = I915_READ(reg);
1947 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1948 return;
1949
1950 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1951 intel_flush_display_plane(dev_priv, plane);
1952 intel_wait_for_vblank(dev_priv->dev, pipe);
1953 }
1954
1955 int
1956 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1957 struct drm_i915_gem_object *obj,
1958 struct intel_ring_buffer *pipelined)
1959 {
1960 struct drm_i915_private *dev_priv = dev->dev_private;
1961 u32 alignment;
1962 int ret;
1963
1964 switch (obj->tiling_mode) {
1965 case I915_TILING_NONE:
1966 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1967 alignment = 128 * 1024;
1968 else if (INTEL_INFO(dev)->gen >= 4)
1969 alignment = 4 * 1024;
1970 else
1971 alignment = 64 * 1024;
1972 break;
1973 case I915_TILING_X:
1974 /* pin() will align the object as required by fence */
1975 alignment = 0;
1976 break;
1977 case I915_TILING_Y:
1978 /* FIXME: Is this true? */
1979 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1980 return -EINVAL;
1981 default:
1982 BUG();
1983 }
1984
1985 dev_priv->mm.interruptible = false;
1986 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1987 if (ret)
1988 goto err_interruptible;
1989
1990 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1991 * fence, whereas 965+ only requires a fence if using
1992 * framebuffer compression. For simplicity, we always install
1993 * a fence as the cost is not that onerous.
1994 */
1995 ret = i915_gem_object_get_fence(obj);
1996 if (ret)
1997 goto err_unpin;
1998
1999 i915_gem_object_pin_fence(obj);
2000
2001 dev_priv->mm.interruptible = true;
2002 return 0;
2003
2004 err_unpin:
2005 i915_gem_object_unpin(obj);
2006 err_interruptible:
2007 dev_priv->mm.interruptible = true;
2008 return ret;
2009 }
2010
2011 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2012 {
2013 i915_gem_object_unpin_fence(obj);
2014 i915_gem_object_unpin(obj);
2015 }
2016
2017 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2018 * is assumed to be a power-of-two. */
2019 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2020 unsigned int bpp,
2021 unsigned int pitch)
2022 {
2023 int tile_rows, tiles;
2024
2025 tile_rows = *y / 8;
2026 *y %= 8;
2027 tiles = *x / (512/bpp);
2028 *x %= 512/bpp;
2029
2030 return tile_rows * pitch * 8 + tiles * 4096;
2031 }
2032
2033 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2034 int x, int y)
2035 {
2036 struct drm_device *dev = crtc->dev;
2037 struct drm_i915_private *dev_priv = dev->dev_private;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2039 struct intel_framebuffer *intel_fb;
2040 struct drm_i915_gem_object *obj;
2041 int plane = intel_crtc->plane;
2042 unsigned long linear_offset;
2043 u32 dspcntr;
2044 u32 reg;
2045
2046 switch (plane) {
2047 case 0:
2048 case 1:
2049 break;
2050 default:
2051 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2052 return -EINVAL;
2053 }
2054
2055 intel_fb = to_intel_framebuffer(fb);
2056 obj = intel_fb->obj;
2057
2058 reg = DSPCNTR(plane);
2059 dspcntr = I915_READ(reg);
2060 /* Mask out pixel format bits in case we change it */
2061 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2062 switch (fb->pixel_format) {
2063 case DRM_FORMAT_C8:
2064 dspcntr |= DISPPLANE_8BPP;
2065 break;
2066 case DRM_FORMAT_XRGB1555:
2067 case DRM_FORMAT_ARGB1555:
2068 dspcntr |= DISPPLANE_BGRX555;
2069 break;
2070 case DRM_FORMAT_RGB565:
2071 dspcntr |= DISPPLANE_BGRX565;
2072 break;
2073 case DRM_FORMAT_XRGB8888:
2074 case DRM_FORMAT_ARGB8888:
2075 dspcntr |= DISPPLANE_BGRX888;
2076 break;
2077 case DRM_FORMAT_XBGR8888:
2078 case DRM_FORMAT_ABGR8888:
2079 dspcntr |= DISPPLANE_RGBX888;
2080 break;
2081 case DRM_FORMAT_XRGB2101010:
2082 case DRM_FORMAT_ARGB2101010:
2083 dspcntr |= DISPPLANE_BGRX101010;
2084 break;
2085 case DRM_FORMAT_XBGR2101010:
2086 case DRM_FORMAT_ABGR2101010:
2087 dspcntr |= DISPPLANE_RGBX101010;
2088 break;
2089 default:
2090 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2091 return -EINVAL;
2092 }
2093
2094 if (INTEL_INFO(dev)->gen >= 4) {
2095 if (obj->tiling_mode != I915_TILING_NONE)
2096 dspcntr |= DISPPLANE_TILED;
2097 else
2098 dspcntr &= ~DISPPLANE_TILED;
2099 }
2100
2101 I915_WRITE(reg, dspcntr);
2102
2103 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2104
2105 if (INTEL_INFO(dev)->gen >= 4) {
2106 intel_crtc->dspaddr_offset =
2107 intel_gen4_compute_offset_xtiled(&x, &y,
2108 fb->bits_per_pixel / 8,
2109 fb->pitches[0]);
2110 linear_offset -= intel_crtc->dspaddr_offset;
2111 } else {
2112 intel_crtc->dspaddr_offset = linear_offset;
2113 }
2114
2115 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2116 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2117 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2118 if (INTEL_INFO(dev)->gen >= 4) {
2119 I915_MODIFY_DISPBASE(DSPSURF(plane),
2120 obj->gtt_offset + intel_crtc->dspaddr_offset);
2121 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2122 I915_WRITE(DSPLINOFF(plane), linear_offset);
2123 } else
2124 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2125 POSTING_READ(reg);
2126
2127 return 0;
2128 }
2129
2130 static int ironlake_update_plane(struct drm_crtc *crtc,
2131 struct drm_framebuffer *fb, int x, int y)
2132 {
2133 struct drm_device *dev = crtc->dev;
2134 struct drm_i915_private *dev_priv = dev->dev_private;
2135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2136 struct intel_framebuffer *intel_fb;
2137 struct drm_i915_gem_object *obj;
2138 int plane = intel_crtc->plane;
2139 unsigned long linear_offset;
2140 u32 dspcntr;
2141 u32 reg;
2142
2143 switch (plane) {
2144 case 0:
2145 case 1:
2146 case 2:
2147 break;
2148 default:
2149 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2150 return -EINVAL;
2151 }
2152
2153 intel_fb = to_intel_framebuffer(fb);
2154 obj = intel_fb->obj;
2155
2156 reg = DSPCNTR(plane);
2157 dspcntr = I915_READ(reg);
2158 /* Mask out pixel format bits in case we change it */
2159 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2160 switch (fb->pixel_format) {
2161 case DRM_FORMAT_C8:
2162 dspcntr |= DISPPLANE_8BPP;
2163 break;
2164 case DRM_FORMAT_RGB565:
2165 dspcntr |= DISPPLANE_BGRX565;
2166 break;
2167 case DRM_FORMAT_XRGB8888:
2168 case DRM_FORMAT_ARGB8888:
2169 dspcntr |= DISPPLANE_BGRX888;
2170 break;
2171 case DRM_FORMAT_XBGR8888:
2172 case DRM_FORMAT_ABGR8888:
2173 dspcntr |= DISPPLANE_RGBX888;
2174 break;
2175 case DRM_FORMAT_XRGB2101010:
2176 case DRM_FORMAT_ARGB2101010:
2177 dspcntr |= DISPPLANE_BGRX101010;
2178 break;
2179 case DRM_FORMAT_XBGR2101010:
2180 case DRM_FORMAT_ABGR2101010:
2181 dspcntr |= DISPPLANE_RGBX101010;
2182 break;
2183 default:
2184 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2185 return -EINVAL;
2186 }
2187
2188 if (obj->tiling_mode != I915_TILING_NONE)
2189 dspcntr |= DISPPLANE_TILED;
2190 else
2191 dspcntr &= ~DISPPLANE_TILED;
2192
2193 /* must disable */
2194 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2195
2196 I915_WRITE(reg, dspcntr);
2197
2198 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2199 intel_crtc->dspaddr_offset =
2200 intel_gen4_compute_offset_xtiled(&x, &y,
2201 fb->bits_per_pixel / 8,
2202 fb->pitches[0]);
2203 linear_offset -= intel_crtc->dspaddr_offset;
2204
2205 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2206 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2207 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2208 I915_MODIFY_DISPBASE(DSPSURF(plane),
2209 obj->gtt_offset + intel_crtc->dspaddr_offset);
2210 if (IS_HASWELL(dev)) {
2211 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2212 } else {
2213 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2214 I915_WRITE(DSPLINOFF(plane), linear_offset);
2215 }
2216 POSTING_READ(reg);
2217
2218 return 0;
2219 }
2220
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2222 static int
2223 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2224 int x, int y, enum mode_set_atomic state)
2225 {
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229 if (dev_priv->display.disable_fbc)
2230 dev_priv->display.disable_fbc(dev);
2231 intel_increase_pllclock(crtc);
2232
2233 return dev_priv->display.update_plane(crtc, fb, x, y);
2234 }
2235
2236 static int
2237 intel_finish_fb(struct drm_framebuffer *old_fb)
2238 {
2239 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2240 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2241 bool was_interruptible = dev_priv->mm.interruptible;
2242 int ret;
2243
2244 wait_event(dev_priv->pending_flip_queue,
2245 atomic_read(&dev_priv->mm.wedged) ||
2246 atomic_read(&obj->pending_flip) == 0);
2247
2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2251 * framebuffer.
2252 *
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2255 */
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_finish_gpu(obj);
2258 dev_priv->mm.interruptible = was_interruptible;
2259
2260 return ret;
2261 }
2262
2263 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2264 {
2265 struct drm_device *dev = crtc->dev;
2266 struct drm_i915_master_private *master_priv;
2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268
2269 if (!dev->primary->master)
2270 return;
2271
2272 master_priv = dev->primary->master->driver_priv;
2273 if (!master_priv->sarea_priv)
2274 return;
2275
2276 switch (intel_crtc->pipe) {
2277 case 0:
2278 master_priv->sarea_priv->pipeA_x = x;
2279 master_priv->sarea_priv->pipeA_y = y;
2280 break;
2281 case 1:
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2284 break;
2285 default:
2286 break;
2287 }
2288 }
2289
2290 static int
2291 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2292 struct drm_framebuffer *fb)
2293 {
2294 struct drm_device *dev = crtc->dev;
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2297 struct drm_framebuffer *old_fb;
2298 int ret;
2299
2300 /* no fb bound */
2301 if (!fb) {
2302 DRM_ERROR("No FB bound\n");
2303 return 0;
2304 }
2305
2306 if(intel_crtc->plane > dev_priv->num_pipe) {
2307 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2308 intel_crtc->plane,
2309 dev_priv->num_pipe);
2310 return -EINVAL;
2311 }
2312
2313 mutex_lock(&dev->struct_mutex);
2314 ret = intel_pin_and_fence_fb_obj(dev,
2315 to_intel_framebuffer(fb)->obj,
2316 NULL);
2317 if (ret != 0) {
2318 mutex_unlock(&dev->struct_mutex);
2319 DRM_ERROR("pin & fence failed\n");
2320 return ret;
2321 }
2322
2323 if (crtc->fb)
2324 intel_finish_fb(crtc->fb);
2325
2326 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2327 if (ret) {
2328 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2329 mutex_unlock(&dev->struct_mutex);
2330 DRM_ERROR("failed to update base address\n");
2331 return ret;
2332 }
2333
2334 old_fb = crtc->fb;
2335 crtc->fb = fb;
2336 crtc->x = x;
2337 crtc->y = y;
2338
2339 if (old_fb) {
2340 intel_wait_for_vblank(dev, intel_crtc->pipe);
2341 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2342 }
2343
2344 intel_update_fbc(dev);
2345 mutex_unlock(&dev->struct_mutex);
2346
2347 intel_crtc_update_sarea_pos(crtc, x, y);
2348
2349 return 0;
2350 }
2351
2352 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2353 {
2354 struct drm_device *dev = crtc->dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 u32 dpa_ctl;
2357
2358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2359 dpa_ctl = I915_READ(DP_A);
2360 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2361
2362 if (clock < 200000) {
2363 u32 temp;
2364 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2365 /* workaround for 160Mhz:
2366 1) program 0x4600c bits 15:0 = 0x8124
2367 2) program 0x46010 bit 0 = 1
2368 3) program 0x46034 bit 24 = 1
2369 4) program 0x64000 bit 14 = 1
2370 */
2371 temp = I915_READ(0x4600c);
2372 temp &= 0xffff0000;
2373 I915_WRITE(0x4600c, temp | 0x8124);
2374
2375 temp = I915_READ(0x46010);
2376 I915_WRITE(0x46010, temp | 1);
2377
2378 temp = I915_READ(0x46034);
2379 I915_WRITE(0x46034, temp | (1 << 24));
2380 } else {
2381 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2382 }
2383 I915_WRITE(DP_A, dpa_ctl);
2384
2385 POSTING_READ(DP_A);
2386 udelay(500);
2387 }
2388
2389 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2390 {
2391 struct drm_device *dev = crtc->dev;
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2394 int pipe = intel_crtc->pipe;
2395 u32 reg, temp;
2396
2397 /* enable normal train */
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 if (IS_IVYBRIDGE(dev)) {
2401 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2402 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2403 } else {
2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2406 }
2407 I915_WRITE(reg, temp);
2408
2409 reg = FDI_RX_CTL(pipe);
2410 temp = I915_READ(reg);
2411 if (HAS_PCH_CPT(dev)) {
2412 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2413 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2414 } else {
2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_NONE;
2417 }
2418 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2419
2420 /* wait one idle pattern time */
2421 POSTING_READ(reg);
2422 udelay(1000);
2423
2424 /* IVB wants error correction enabled */
2425 if (IS_IVYBRIDGE(dev))
2426 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2427 FDI_FE_ERRC_ENABLE);
2428 }
2429
2430 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2431 {
2432 struct drm_i915_private *dev_priv = dev->dev_private;
2433 u32 flags = I915_READ(SOUTH_CHICKEN1);
2434
2435 flags |= FDI_PHASE_SYNC_OVR(pipe);
2436 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2437 flags |= FDI_PHASE_SYNC_EN(pipe);
2438 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2439 POSTING_READ(SOUTH_CHICKEN1);
2440 }
2441
2442 static void ivb_modeset_global_resources(struct drm_device *dev)
2443 {
2444 struct drm_i915_private *dev_priv = dev->dev_private;
2445 struct intel_crtc *pipe_B_crtc =
2446 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2447 struct intel_crtc *pipe_C_crtc =
2448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2449 uint32_t temp;
2450
2451 /* When everything is off disable fdi C so that we could enable fdi B
2452 * with all lanes. XXX: This misses the case where a pipe is not using
2453 * any pch resources and so doesn't need any fdi lanes. */
2454 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2455 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2456 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2457
2458 temp = I915_READ(SOUTH_CHICKEN1);
2459 temp &= ~FDI_BC_BIFURCATION_SELECT;
2460 DRM_DEBUG_KMS("disabling fdi C rx\n");
2461 I915_WRITE(SOUTH_CHICKEN1, temp);
2462 }
2463 }
2464
2465 /* The FDI link training functions for ILK/Ibexpeak. */
2466 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2467 {
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 int pipe = intel_crtc->pipe;
2472 int plane = intel_crtc->plane;
2473 u32 reg, temp, tries;
2474
2475 /* FDI needs bits from pipe & plane first */
2476 assert_pipe_enabled(dev_priv, pipe);
2477 assert_plane_enabled(dev_priv, plane);
2478
2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 for train result */
2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
2485 I915_WRITE(reg, temp);
2486 I915_READ(reg);
2487 udelay(150);
2488
2489 /* enable CPU FDI TX and PCH FDI RX */
2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
2492 temp &= ~(7 << 19);
2493 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2494 temp &= ~FDI_LINK_TRAIN_NONE;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2503
2504 POSTING_READ(reg);
2505 udelay(150);
2506
2507 /* Ironlake workaround, enable clock pointer after FDI enable*/
2508 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2509 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2510 FDI_RX_PHASE_SYNC_POINTER_EN);
2511
2512 reg = FDI_RX_IIR(pipe);
2513 for (tries = 0; tries < 5; tries++) {
2514 temp = I915_READ(reg);
2515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2516
2517 if ((temp & FDI_RX_BIT_LOCK)) {
2518 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2520 break;
2521 }
2522 }
2523 if (tries == 5)
2524 DRM_ERROR("FDI train 1 fail!\n");
2525
2526 /* Train 2 */
2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
2531 I915_WRITE(reg, temp);
2532
2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 I915_WRITE(reg, temp);
2538
2539 POSTING_READ(reg);
2540 udelay(150);
2541
2542 reg = FDI_RX_IIR(pipe);
2543 for (tries = 0; tries < 5; tries++) {
2544 temp = I915_READ(reg);
2545 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2546
2547 if (temp & FDI_RX_SYMBOL_LOCK) {
2548 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549 DRM_DEBUG_KMS("FDI train 2 done.\n");
2550 break;
2551 }
2552 }
2553 if (tries == 5)
2554 DRM_ERROR("FDI train 2 fail!\n");
2555
2556 DRM_DEBUG_KMS("FDI train done\n");
2557
2558 }
2559
2560 static const int snb_b_fdi_train_param[] = {
2561 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2562 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2563 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2564 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2565 };
2566
2567 /* The FDI link training functions for SNB/Cougarpoint. */
2568 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2569 {
2570 struct drm_device *dev = crtc->dev;
2571 struct drm_i915_private *dev_priv = dev->dev_private;
2572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2573 int pipe = intel_crtc->pipe;
2574 u32 reg, temp, i, retry;
2575
2576 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2577 for train result */
2578 reg = FDI_RX_IMR(pipe);
2579 temp = I915_READ(reg);
2580 temp &= ~FDI_RX_SYMBOL_LOCK;
2581 temp &= ~FDI_RX_BIT_LOCK;
2582 I915_WRITE(reg, temp);
2583
2584 POSTING_READ(reg);
2585 udelay(150);
2586
2587 /* enable CPU FDI TX and PCH FDI RX */
2588 reg = FDI_TX_CTL(pipe);
2589 temp = I915_READ(reg);
2590 temp &= ~(7 << 19);
2591 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1;
2594 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2595 /* SNB-B */
2596 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2597 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2598
2599 I915_WRITE(FDI_RX_MISC(pipe),
2600 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2601
2602 reg = FDI_RX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 if (HAS_PCH_CPT(dev)) {
2605 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2606 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2607 } else {
2608 temp &= ~FDI_LINK_TRAIN_NONE;
2609 temp |= FDI_LINK_TRAIN_PATTERN_1;
2610 }
2611 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2612
2613 POSTING_READ(reg);
2614 udelay(150);
2615
2616 cpt_phase_pointer_enable(dev, pipe);
2617
2618 for (i = 0; i < 4; i++) {
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(500);
2627
2628 for (retry = 0; retry < 5; retry++) {
2629 reg = FDI_RX_IIR(pipe);
2630 temp = I915_READ(reg);
2631 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2632 if (temp & FDI_RX_BIT_LOCK) {
2633 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2634 DRM_DEBUG_KMS("FDI train 1 done.\n");
2635 break;
2636 }
2637 udelay(50);
2638 }
2639 if (retry < 5)
2640 break;
2641 }
2642 if (i == 4)
2643 DRM_ERROR("FDI train 1 fail!\n");
2644
2645 /* Train 2 */
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650 if (IS_GEN6(dev)) {
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 /* SNB-B */
2653 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2654 }
2655 I915_WRITE(reg, temp);
2656
2657 reg = FDI_RX_CTL(pipe);
2658 temp = I915_READ(reg);
2659 if (HAS_PCH_CPT(dev)) {
2660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2661 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2662 } else {
2663 temp &= ~FDI_LINK_TRAIN_NONE;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2;
2665 }
2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
2669 udelay(150);
2670
2671 for (i = 0; i < 4; i++) {
2672 reg = FDI_TX_CTL(pipe);
2673 temp = I915_READ(reg);
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= snb_b_fdi_train_param[i];
2676 I915_WRITE(reg, temp);
2677
2678 POSTING_READ(reg);
2679 udelay(500);
2680
2681 for (retry = 0; retry < 5; retry++) {
2682 reg = FDI_RX_IIR(pipe);
2683 temp = I915_READ(reg);
2684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2685 if (temp & FDI_RX_SYMBOL_LOCK) {
2686 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2687 DRM_DEBUG_KMS("FDI train 2 done.\n");
2688 break;
2689 }
2690 udelay(50);
2691 }
2692 if (retry < 5)
2693 break;
2694 }
2695 if (i == 4)
2696 DRM_ERROR("FDI train 2 fail!\n");
2697
2698 DRM_DEBUG_KMS("FDI train done.\n");
2699 }
2700
2701 /* Manual link training for Ivy Bridge A0 parts */
2702 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2703 {
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp, i;
2709
2710 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2711 for train result */
2712 reg = FDI_RX_IMR(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~FDI_RX_SYMBOL_LOCK;
2715 temp &= ~FDI_RX_BIT_LOCK;
2716 I915_WRITE(reg, temp);
2717
2718 POSTING_READ(reg);
2719 udelay(150);
2720
2721 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2722 I915_READ(FDI_RX_IIR(pipe)));
2723
2724 /* enable CPU FDI TX and PCH FDI RX */
2725 reg = FDI_TX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~(7 << 19);
2728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2729 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2735
2736 I915_WRITE(FDI_RX_MISC(pipe),
2737 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_AUTO;
2742 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2743 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2744 temp |= FDI_COMPOSITE_SYNC;
2745 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2746
2747 POSTING_READ(reg);
2748 udelay(150);
2749
2750 cpt_phase_pointer_enable(dev, pipe);
2751
2752 for (i = 0; i < 4; i++) {
2753 reg = FDI_TX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= snb_b_fdi_train_param[i];
2757 I915_WRITE(reg, temp);
2758
2759 POSTING_READ(reg);
2760 udelay(500);
2761
2762 reg = FDI_RX_IIR(pipe);
2763 temp = I915_READ(reg);
2764 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2765
2766 if (temp & FDI_RX_BIT_LOCK ||
2767 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2768 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2769 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2770 break;
2771 }
2772 }
2773 if (i == 4)
2774 DRM_ERROR("FDI train 1 fail!\n");
2775
2776 /* Train 2 */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2780 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2781 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2782 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2783 I915_WRITE(reg, temp);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2789 I915_WRITE(reg, temp);
2790
2791 POSTING_READ(reg);
2792 udelay(150);
2793
2794 for (i = 0; i < 4; i++) {
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2798 temp |= snb_b_fdi_train_param[i];
2799 I915_WRITE(reg, temp);
2800
2801 POSTING_READ(reg);
2802 udelay(500);
2803
2804 reg = FDI_RX_IIR(pipe);
2805 temp = I915_READ(reg);
2806 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2807
2808 if (temp & FDI_RX_SYMBOL_LOCK) {
2809 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2810 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2811 break;
2812 }
2813 }
2814 if (i == 4)
2815 DRM_ERROR("FDI train 2 fail!\n");
2816
2817 DRM_DEBUG_KMS("FDI train done.\n");
2818 }
2819
2820 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2821 {
2822 struct drm_device *dev = intel_crtc->base.dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 int pipe = intel_crtc->pipe;
2825 u32 reg, temp;
2826
2827
2828 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~((0x7 << 19) | (0x7 << 16));
2832 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2833 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2834 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2835
2836 POSTING_READ(reg);
2837 udelay(200);
2838
2839 /* Switch from Rawclk to PCDclk */
2840 temp = I915_READ(reg);
2841 I915_WRITE(reg, temp | FDI_PCDCLK);
2842
2843 POSTING_READ(reg);
2844 udelay(200);
2845
2846 /* On Haswell, the PLL configuration for ports and pipes is handled
2847 * separately, as part of DDI setup */
2848 if (!IS_HASWELL(dev)) {
2849 /* Enable CPU FDI TX PLL, always on for Ironlake */
2850 reg = FDI_TX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2853 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2854
2855 POSTING_READ(reg);
2856 udelay(100);
2857 }
2858 }
2859 }
2860
2861 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2862 {
2863 struct drm_device *dev = intel_crtc->base.dev;
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* Switch from PCDclk to Rawclk */
2869 reg = FDI_RX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2872
2873 /* Disable CPU FDI TX PLL */
2874 reg = FDI_TX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2877
2878 POSTING_READ(reg);
2879 udelay(100);
2880
2881 reg = FDI_RX_CTL(pipe);
2882 temp = I915_READ(reg);
2883 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2884
2885 /* Wait for the clocks to turn off. */
2886 POSTING_READ(reg);
2887 udelay(100);
2888 }
2889
2890 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2891 {
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893 u32 flags = I915_READ(SOUTH_CHICKEN1);
2894
2895 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2896 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2897 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2898 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2899 POSTING_READ(SOUTH_CHICKEN1);
2900 }
2901 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2902 {
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2906 int pipe = intel_crtc->pipe;
2907 u32 reg, temp;
2908
2909 /* disable CPU FDI tx and PCH FDI rx */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2913 POSTING_READ(reg);
2914
2915 reg = FDI_RX_CTL(pipe);
2916 temp = I915_READ(reg);
2917 temp &= ~(0x7 << 16);
2918 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2919 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2920
2921 POSTING_READ(reg);
2922 udelay(100);
2923
2924 /* Ironlake workaround, disable clock pointer after downing FDI */
2925 if (HAS_PCH_IBX(dev)) {
2926 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2927 } else if (HAS_PCH_CPT(dev)) {
2928 cpt_phase_pointer_disable(dev, pipe);
2929 }
2930
2931 /* still set train pattern 1 */
2932 reg = FDI_TX_CTL(pipe);
2933 temp = I915_READ(reg);
2934 temp &= ~FDI_LINK_TRAIN_NONE;
2935 temp |= FDI_LINK_TRAIN_PATTERN_1;
2936 I915_WRITE(reg, temp);
2937
2938 reg = FDI_RX_CTL(pipe);
2939 temp = I915_READ(reg);
2940 if (HAS_PCH_CPT(dev)) {
2941 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2943 } else {
2944 temp &= ~FDI_LINK_TRAIN_NONE;
2945 temp |= FDI_LINK_TRAIN_PATTERN_1;
2946 }
2947 /* BPC in FDI rx is consistent with that in PIPECONF */
2948 temp &= ~(0x07 << 16);
2949 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2950 I915_WRITE(reg, temp);
2951
2952 POSTING_READ(reg);
2953 udelay(100);
2954 }
2955
2956 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2957 {
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 unsigned long flags;
2961 bool pending;
2962
2963 if (atomic_read(&dev_priv->mm.wedged))
2964 return false;
2965
2966 spin_lock_irqsave(&dev->event_lock, flags);
2967 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2968 spin_unlock_irqrestore(&dev->event_lock, flags);
2969
2970 return pending;
2971 }
2972
2973 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2974 {
2975 struct drm_device *dev = crtc->dev;
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977
2978 if (crtc->fb == NULL)
2979 return;
2980
2981 wait_event(dev_priv->pending_flip_queue,
2982 !intel_crtc_has_pending_flip(crtc));
2983
2984 mutex_lock(&dev->struct_mutex);
2985 intel_finish_fb(crtc->fb);
2986 mutex_unlock(&dev->struct_mutex);
2987 }
2988
2989 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2990 {
2991 struct drm_device *dev = crtc->dev;
2992 struct intel_encoder *intel_encoder;
2993
2994 /*
2995 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2996 * must be driven by its own crtc; no sharing is possible.
2997 */
2998 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2999 switch (intel_encoder->type) {
3000 case INTEL_OUTPUT_EDP:
3001 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3002 return false;
3003 continue;
3004 }
3005 }
3006
3007 return true;
3008 }
3009
3010 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3011 {
3012 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3013 }
3014
3015 /* Program iCLKIP clock to the desired frequency */
3016 static void lpt_program_iclkip(struct drm_crtc *crtc)
3017 {
3018 struct drm_device *dev = crtc->dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3021 u32 temp;
3022
3023 /* It is necessary to ungate the pixclk gate prior to programming
3024 * the divisors, and gate it back when it is done.
3025 */
3026 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3027
3028 /* Disable SSCCTL */
3029 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3030 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3031 SBI_SSCCTL_DISABLE);
3032
3033 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3034 if (crtc->mode.clock == 20000) {
3035 auxdiv = 1;
3036 divsel = 0x41;
3037 phaseinc = 0x20;
3038 } else {
3039 /* The iCLK virtual clock root frequency is in MHz,
3040 * but the crtc->mode.clock in in KHz. To get the divisors,
3041 * it is necessary to divide one by another, so we
3042 * convert the virtual clock precision to KHz here for higher
3043 * precision.
3044 */
3045 u32 iclk_virtual_root_freq = 172800 * 1000;
3046 u32 iclk_pi_range = 64;
3047 u32 desired_divisor, msb_divisor_value, pi_value;
3048
3049 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3050 msb_divisor_value = desired_divisor / iclk_pi_range;
3051 pi_value = desired_divisor % iclk_pi_range;
3052
3053 auxdiv = 0;
3054 divsel = msb_divisor_value - 2;
3055 phaseinc = pi_value;
3056 }
3057
3058 /* This should not happen with any sane values */
3059 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3060 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3061 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3062 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3063
3064 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3065 crtc->mode.clock,
3066 auxdiv,
3067 divsel,
3068 phasedir,
3069 phaseinc);
3070
3071 /* Program SSCDIVINTPHASE6 */
3072 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3073 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3074 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3075 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3076 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3077 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3078 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3079
3080 intel_sbi_write(dev_priv,
3081 SBI_SSCDIVINTPHASE6,
3082 temp);
3083
3084 /* Program SSCAUXDIV */
3085 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3086 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3087 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3088 intel_sbi_write(dev_priv,
3089 SBI_SSCAUXDIV6,
3090 temp);
3091
3092
3093 /* Enable modulator and associated divider */
3094 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3095 temp &= ~SBI_SSCCTL_DISABLE;
3096 intel_sbi_write(dev_priv,
3097 SBI_SSCCTL6,
3098 temp);
3099
3100 /* Wait for initialization time */
3101 udelay(24);
3102
3103 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3104 }
3105
3106 /*
3107 * Enable PCH resources required for PCH ports:
3108 * - PCH PLLs
3109 * - FDI training & RX/TX
3110 * - update transcoder timings
3111 * - DP transcoding bits
3112 * - transcoder
3113 */
3114 static void ironlake_pch_enable(struct drm_crtc *crtc)
3115 {
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 int pipe = intel_crtc->pipe;
3120 u32 reg, temp;
3121
3122 assert_transcoder_disabled(dev_priv, pipe);
3123
3124 /* Write the TU size bits before fdi link training, so that error
3125 * detection works. */
3126 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3127 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3128
3129 /* For PCH output, training FDI link */
3130 dev_priv->display.fdi_link_train(crtc);
3131
3132 /* XXX: pch pll's can be enabled any time before we enable the PCH
3133 * transcoder, and we actually should do this to not upset any PCH
3134 * transcoder that already use the clock when we share it.
3135 *
3136 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3137 * unconditionally resets the pll - we need that to have the right LVDS
3138 * enable sequence. */
3139 ironlake_enable_pch_pll(intel_crtc);
3140
3141 if (HAS_PCH_CPT(dev)) {
3142 u32 sel;
3143
3144 temp = I915_READ(PCH_DPLL_SEL);
3145 switch (pipe) {
3146 default:
3147 case 0:
3148 temp |= TRANSA_DPLL_ENABLE;
3149 sel = TRANSA_DPLLB_SEL;
3150 break;
3151 case 1:
3152 temp |= TRANSB_DPLL_ENABLE;
3153 sel = TRANSB_DPLLB_SEL;
3154 break;
3155 case 2:
3156 temp |= TRANSC_DPLL_ENABLE;
3157 sel = TRANSC_DPLLB_SEL;
3158 break;
3159 }
3160 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3161 temp |= sel;
3162 else
3163 temp &= ~sel;
3164 I915_WRITE(PCH_DPLL_SEL, temp);
3165 }
3166
3167 /* set transcoder timing, panel must allow it */
3168 assert_panel_unlocked(dev_priv, pipe);
3169 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3170 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3171 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3172
3173 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3174 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3175 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3176 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3177
3178 intel_fdi_normal_train(crtc);
3179
3180 /* For PCH DP, enable TRANS_DP_CTL */
3181 if (HAS_PCH_CPT(dev) &&
3182 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3183 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3184 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3185 reg = TRANS_DP_CTL(pipe);
3186 temp = I915_READ(reg);
3187 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3188 TRANS_DP_SYNC_MASK |
3189 TRANS_DP_BPC_MASK);
3190 temp |= (TRANS_DP_OUTPUT_ENABLE |
3191 TRANS_DP_ENH_FRAMING);
3192 temp |= bpc << 9; /* same format but at 11:9 */
3193
3194 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3195 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3196 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3197 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3198
3199 switch (intel_trans_dp_port_sel(crtc)) {
3200 case PCH_DP_B:
3201 temp |= TRANS_DP_PORT_SEL_B;
3202 break;
3203 case PCH_DP_C:
3204 temp |= TRANS_DP_PORT_SEL_C;
3205 break;
3206 case PCH_DP_D:
3207 temp |= TRANS_DP_PORT_SEL_D;
3208 break;
3209 default:
3210 BUG();
3211 }
3212
3213 I915_WRITE(reg, temp);
3214 }
3215
3216 ironlake_enable_pch_transcoder(dev_priv, pipe);
3217 }
3218
3219 static void lpt_pch_enable(struct drm_crtc *crtc)
3220 {
3221 struct drm_device *dev = crtc->dev;
3222 struct drm_i915_private *dev_priv = dev->dev_private;
3223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3224 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3225
3226 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3227
3228 lpt_program_iclkip(crtc);
3229
3230 /* Set transcoder timing. */
3231 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3232 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3233 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3234
3235 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3236 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3237 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3238 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3239
3240 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3241 }
3242
3243 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3244 {
3245 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3246
3247 if (pll == NULL)
3248 return;
3249
3250 if (pll->refcount == 0) {
3251 WARN(1, "bad PCH PLL refcount\n");
3252 return;
3253 }
3254
3255 --pll->refcount;
3256 intel_crtc->pch_pll = NULL;
3257 }
3258
3259 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3260 {
3261 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3262 struct intel_pch_pll *pll;
3263 int i;
3264
3265 pll = intel_crtc->pch_pll;
3266 if (pll) {
3267 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3268 intel_crtc->base.base.id, pll->pll_reg);
3269 goto prepare;
3270 }
3271
3272 if (HAS_PCH_IBX(dev_priv->dev)) {
3273 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3274 i = intel_crtc->pipe;
3275 pll = &dev_priv->pch_plls[i];
3276
3277 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3278 intel_crtc->base.base.id, pll->pll_reg);
3279
3280 goto found;
3281 }
3282
3283 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3284 pll = &dev_priv->pch_plls[i];
3285
3286 /* Only want to check enabled timings first */
3287 if (pll->refcount == 0)
3288 continue;
3289
3290 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3291 fp == I915_READ(pll->fp0_reg)) {
3292 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3293 intel_crtc->base.base.id,
3294 pll->pll_reg, pll->refcount, pll->active);
3295
3296 goto found;
3297 }
3298 }
3299
3300 /* Ok no matching timings, maybe there's a free one? */
3301 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3302 pll = &dev_priv->pch_plls[i];
3303 if (pll->refcount == 0) {
3304 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3305 intel_crtc->base.base.id, pll->pll_reg);
3306 goto found;
3307 }
3308 }
3309
3310 return NULL;
3311
3312 found:
3313 intel_crtc->pch_pll = pll;
3314 pll->refcount++;
3315 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3316 prepare: /* separate function? */
3317 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3318
3319 /* Wait for the clocks to stabilize before rewriting the regs */
3320 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3321 POSTING_READ(pll->pll_reg);
3322 udelay(150);
3323
3324 I915_WRITE(pll->fp0_reg, fp);
3325 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3326 pll->on = false;
3327 return pll;
3328 }
3329
3330 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3331 {
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333 int dslreg = PIPEDSL(pipe);
3334 u32 temp;
3335
3336 temp = I915_READ(dslreg);
3337 udelay(500);
3338 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3339 if (wait_for(I915_READ(dslreg) != temp, 5))
3340 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3341 }
3342 }
3343
3344 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3345 {
3346 struct drm_device *dev = crtc->dev;
3347 struct drm_i915_private *dev_priv = dev->dev_private;
3348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3349 struct intel_encoder *encoder;
3350 int pipe = intel_crtc->pipe;
3351 int plane = intel_crtc->plane;
3352 u32 temp;
3353 bool is_pch_port;
3354
3355 WARN_ON(!crtc->enabled);
3356
3357 if (intel_crtc->active)
3358 return;
3359
3360 intel_crtc->active = true;
3361 intel_update_watermarks(dev);
3362
3363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3364 temp = I915_READ(PCH_LVDS);
3365 if ((temp & LVDS_PORT_EN) == 0)
3366 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3367 }
3368
3369 is_pch_port = ironlake_crtc_driving_pch(crtc);
3370
3371 if (is_pch_port) {
3372 /* Note: FDI PLL enabling _must_ be done before we enable the
3373 * cpu pipes, hence this is separate from all the other fdi/pch
3374 * enabling. */
3375 ironlake_fdi_pll_enable(intel_crtc);
3376 } else {
3377 assert_fdi_tx_disabled(dev_priv, pipe);
3378 assert_fdi_rx_disabled(dev_priv, pipe);
3379 }
3380
3381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 if (encoder->pre_enable)
3383 encoder->pre_enable(encoder);
3384
3385 /* Enable panel fitting for LVDS */
3386 if (dev_priv->pch_pf_size &&
3387 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3388 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3389 /* Force use of hard-coded filter coefficients
3390 * as some pre-programmed values are broken,
3391 * e.g. x201.
3392 */
3393 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3394 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3395 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3396 }
3397
3398 /*
3399 * On ILK+ LUT must be loaded before the pipe is running but with
3400 * clocks enabled
3401 */
3402 intel_crtc_load_lut(crtc);
3403
3404 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405 intel_enable_plane(dev_priv, plane, pipe);
3406
3407 if (is_pch_port)
3408 ironlake_pch_enable(crtc);
3409
3410 mutex_lock(&dev->struct_mutex);
3411 intel_update_fbc(dev);
3412 mutex_unlock(&dev->struct_mutex);
3413
3414 intel_crtc_update_cursor(crtc, true);
3415
3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->enable(encoder);
3418
3419 if (HAS_PCH_CPT(dev))
3420 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3421
3422 /*
3423 * There seems to be a race in PCH platform hw (at least on some
3424 * outputs) where an enabled pipe still completes any pageflip right
3425 * away (as if the pipe is off) instead of waiting for vblank. As soon
3426 * as the first vblank happend, everything works as expected. Hence just
3427 * wait for one vblank before returning to avoid strange things
3428 * happening.
3429 */
3430 intel_wait_for_vblank(dev, intel_crtc->pipe);
3431 }
3432
3433 static void haswell_crtc_enable(struct drm_crtc *crtc)
3434 {
3435 struct drm_device *dev = crtc->dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438 struct intel_encoder *encoder;
3439 int pipe = intel_crtc->pipe;
3440 int plane = intel_crtc->plane;
3441 bool is_pch_port;
3442
3443 WARN_ON(!crtc->enabled);
3444
3445 if (intel_crtc->active)
3446 return;
3447
3448 intel_crtc->active = true;
3449 intel_update_watermarks(dev);
3450
3451 is_pch_port = haswell_crtc_driving_pch(crtc);
3452
3453 if (is_pch_port)
3454 dev_priv->display.fdi_link_train(crtc);
3455
3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 if (encoder->pre_enable)
3458 encoder->pre_enable(encoder);
3459
3460 intel_ddi_enable_pipe_clock(intel_crtc);
3461
3462 /* Enable panel fitting for eDP */
3463 if (dev_priv->pch_pf_size &&
3464 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3465 /* Force use of hard-coded filter coefficients
3466 * as some pre-programmed values are broken,
3467 * e.g. x201.
3468 */
3469 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3470 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3471 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3472 }
3473
3474 /*
3475 * On ILK+ LUT must be loaded before the pipe is running but with
3476 * clocks enabled
3477 */
3478 intel_crtc_load_lut(crtc);
3479
3480 intel_ddi_set_pipe_settings(crtc);
3481 intel_ddi_enable_pipe_func(crtc);
3482
3483 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3484 intel_enable_plane(dev_priv, plane, pipe);
3485
3486 if (is_pch_port)
3487 lpt_pch_enable(crtc);
3488
3489 mutex_lock(&dev->struct_mutex);
3490 intel_update_fbc(dev);
3491 mutex_unlock(&dev->struct_mutex);
3492
3493 intel_crtc_update_cursor(crtc, true);
3494
3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->enable(encoder);
3497
3498 /*
3499 * There seems to be a race in PCH platform hw (at least on some
3500 * outputs) where an enabled pipe still completes any pageflip right
3501 * away (as if the pipe is off) instead of waiting for vblank. As soon
3502 * as the first vblank happend, everything works as expected. Hence just
3503 * wait for one vblank before returning to avoid strange things
3504 * happening.
3505 */
3506 intel_wait_for_vblank(dev, intel_crtc->pipe);
3507 }
3508
3509 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3510 {
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3517 u32 reg, temp;
3518
3519
3520 if (!intel_crtc->active)
3521 return;
3522
3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 encoder->disable(encoder);
3525
3526 intel_crtc_wait_for_pending_flips(crtc);
3527 drm_vblank_off(dev, pipe);
3528 intel_crtc_update_cursor(crtc, false);
3529
3530 intel_disable_plane(dev_priv, plane, pipe);
3531
3532 if (dev_priv->cfb_plane == plane)
3533 intel_disable_fbc(dev);
3534
3535 intel_disable_pipe(dev_priv, pipe);
3536
3537 /* Disable PF */
3538 I915_WRITE(PF_CTL(pipe), 0);
3539 I915_WRITE(PF_WIN_SZ(pipe), 0);
3540
3541 for_each_encoder_on_crtc(dev, crtc, encoder)
3542 if (encoder->post_disable)
3543 encoder->post_disable(encoder);
3544
3545 ironlake_fdi_disable(crtc);
3546
3547 ironlake_disable_pch_transcoder(dev_priv, pipe);
3548
3549 if (HAS_PCH_CPT(dev)) {
3550 /* disable TRANS_DP_CTL */
3551 reg = TRANS_DP_CTL(pipe);
3552 temp = I915_READ(reg);
3553 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3554 temp |= TRANS_DP_PORT_SEL_NONE;
3555 I915_WRITE(reg, temp);
3556
3557 /* disable DPLL_SEL */
3558 temp = I915_READ(PCH_DPLL_SEL);
3559 switch (pipe) {
3560 case 0:
3561 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3562 break;
3563 case 1:
3564 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3565 break;
3566 case 2:
3567 /* C shares PLL A or B */
3568 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3569 break;
3570 default:
3571 BUG(); /* wtf */
3572 }
3573 I915_WRITE(PCH_DPLL_SEL, temp);
3574 }
3575
3576 /* disable PCH DPLL */
3577 intel_disable_pch_pll(intel_crtc);
3578
3579 ironlake_fdi_pll_disable(intel_crtc);
3580
3581 intel_crtc->active = false;
3582 intel_update_watermarks(dev);
3583
3584 mutex_lock(&dev->struct_mutex);
3585 intel_update_fbc(dev);
3586 mutex_unlock(&dev->struct_mutex);
3587 }
3588
3589 static void haswell_crtc_disable(struct drm_crtc *crtc)
3590 {
3591 struct drm_device *dev = crtc->dev;
3592 struct drm_i915_private *dev_priv = dev->dev_private;
3593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3594 struct intel_encoder *encoder;
3595 int pipe = intel_crtc->pipe;
3596 int plane = intel_crtc->plane;
3597 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3598 bool is_pch_port;
3599
3600 if (!intel_crtc->active)
3601 return;
3602
3603 is_pch_port = haswell_crtc_driving_pch(crtc);
3604
3605 for_each_encoder_on_crtc(dev, crtc, encoder)
3606 encoder->disable(encoder);
3607
3608 intel_crtc_wait_for_pending_flips(crtc);
3609 drm_vblank_off(dev, pipe);
3610 intel_crtc_update_cursor(crtc, false);
3611
3612 intel_disable_plane(dev_priv, plane, pipe);
3613
3614 if (dev_priv->cfb_plane == plane)
3615 intel_disable_fbc(dev);
3616
3617 intel_disable_pipe(dev_priv, pipe);
3618
3619 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3620
3621 /* Disable PF */
3622 I915_WRITE(PF_CTL(pipe), 0);
3623 I915_WRITE(PF_WIN_SZ(pipe), 0);
3624
3625 intel_ddi_disable_pipe_clock(intel_crtc);
3626
3627 for_each_encoder_on_crtc(dev, crtc, encoder)
3628 if (encoder->post_disable)
3629 encoder->post_disable(encoder);
3630
3631 if (is_pch_port) {
3632 lpt_disable_pch_transcoder(dev_priv);
3633 intel_ddi_fdi_disable(crtc);
3634 }
3635
3636 intel_crtc->active = false;
3637 intel_update_watermarks(dev);
3638
3639 mutex_lock(&dev->struct_mutex);
3640 intel_update_fbc(dev);
3641 mutex_unlock(&dev->struct_mutex);
3642 }
3643
3644 static void ironlake_crtc_off(struct drm_crtc *crtc)
3645 {
3646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3647 intel_put_pch_pll(intel_crtc);
3648 }
3649
3650 static void haswell_crtc_off(struct drm_crtc *crtc)
3651 {
3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653
3654 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3655 * start using it. */
3656 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3657
3658 intel_ddi_put_crtc_pll(crtc);
3659 }
3660
3661 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3662 {
3663 if (!enable && intel_crtc->overlay) {
3664 struct drm_device *dev = intel_crtc->base.dev;
3665 struct drm_i915_private *dev_priv = dev->dev_private;
3666
3667 mutex_lock(&dev->struct_mutex);
3668 dev_priv->mm.interruptible = false;
3669 (void) intel_overlay_switch_off(intel_crtc->overlay);
3670 dev_priv->mm.interruptible = true;
3671 mutex_unlock(&dev->struct_mutex);
3672 }
3673
3674 /* Let userspace switch the overlay on again. In most cases userspace
3675 * has to recompute where to put it anyway.
3676 */
3677 }
3678
3679 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3680 {
3681 struct drm_device *dev = crtc->dev;
3682 struct drm_i915_private *dev_priv = dev->dev_private;
3683 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3684 struct intel_encoder *encoder;
3685 int pipe = intel_crtc->pipe;
3686 int plane = intel_crtc->plane;
3687
3688 WARN_ON(!crtc->enabled);
3689
3690 if (intel_crtc->active)
3691 return;
3692
3693 intel_crtc->active = true;
3694 intel_update_watermarks(dev);
3695
3696 intel_enable_pll(dev_priv, pipe);
3697 intel_enable_pipe(dev_priv, pipe, false);
3698 intel_enable_plane(dev_priv, plane, pipe);
3699
3700 intel_crtc_load_lut(crtc);
3701 intel_update_fbc(dev);
3702
3703 /* Give the overlay scaler a chance to enable if it's on this pipe */
3704 intel_crtc_dpms_overlay(intel_crtc, true);
3705 intel_crtc_update_cursor(crtc, true);
3706
3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 encoder->enable(encoder);
3709 }
3710
3711 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3712 {
3713 struct drm_device *dev = crtc->dev;
3714 struct drm_i915_private *dev_priv = dev->dev_private;
3715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3716 struct intel_encoder *encoder;
3717 int pipe = intel_crtc->pipe;
3718 int plane = intel_crtc->plane;
3719
3720
3721 if (!intel_crtc->active)
3722 return;
3723
3724 for_each_encoder_on_crtc(dev, crtc, encoder)
3725 encoder->disable(encoder);
3726
3727 /* Give the overlay scaler a chance to disable if it's on this pipe */
3728 intel_crtc_wait_for_pending_flips(crtc);
3729 drm_vblank_off(dev, pipe);
3730 intel_crtc_dpms_overlay(intel_crtc, false);
3731 intel_crtc_update_cursor(crtc, false);
3732
3733 if (dev_priv->cfb_plane == plane)
3734 intel_disable_fbc(dev);
3735
3736 intel_disable_plane(dev_priv, plane, pipe);
3737 intel_disable_pipe(dev_priv, pipe);
3738 intel_disable_pll(dev_priv, pipe);
3739
3740 intel_crtc->active = false;
3741 intel_update_fbc(dev);
3742 intel_update_watermarks(dev);
3743 }
3744
3745 static void i9xx_crtc_off(struct drm_crtc *crtc)
3746 {
3747 }
3748
3749 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3750 bool enabled)
3751 {
3752 struct drm_device *dev = crtc->dev;
3753 struct drm_i915_master_private *master_priv;
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3755 int pipe = intel_crtc->pipe;
3756
3757 if (!dev->primary->master)
3758 return;
3759
3760 master_priv = dev->primary->master->driver_priv;
3761 if (!master_priv->sarea_priv)
3762 return;
3763
3764 switch (pipe) {
3765 case 0:
3766 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3767 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3768 break;
3769 case 1:
3770 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3771 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3772 break;
3773 default:
3774 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3775 break;
3776 }
3777 }
3778
3779 /**
3780 * Sets the power management mode of the pipe and plane.
3781 */
3782 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3783 {
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_private *dev_priv = dev->dev_private;
3786 struct intel_encoder *intel_encoder;
3787 bool enable = false;
3788
3789 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3790 enable |= intel_encoder->connectors_active;
3791
3792 if (enable)
3793 dev_priv->display.crtc_enable(crtc);
3794 else
3795 dev_priv->display.crtc_disable(crtc);
3796
3797 intel_crtc_update_sarea(crtc, enable);
3798 }
3799
3800 static void intel_crtc_noop(struct drm_crtc *crtc)
3801 {
3802 }
3803
3804 static void intel_crtc_disable(struct drm_crtc *crtc)
3805 {
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_connector *connector;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809
3810 /* crtc should still be enabled when we disable it. */
3811 WARN_ON(!crtc->enabled);
3812
3813 dev_priv->display.crtc_disable(crtc);
3814 intel_crtc_update_sarea(crtc, false);
3815 dev_priv->display.off(crtc);
3816
3817 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3818 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3819
3820 if (crtc->fb) {
3821 mutex_lock(&dev->struct_mutex);
3822 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3823 mutex_unlock(&dev->struct_mutex);
3824 crtc->fb = NULL;
3825 }
3826
3827 /* Update computed state. */
3828 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3829 if (!connector->encoder || !connector->encoder->crtc)
3830 continue;
3831
3832 if (connector->encoder->crtc != crtc)
3833 continue;
3834
3835 connector->dpms = DRM_MODE_DPMS_OFF;
3836 to_intel_encoder(connector->encoder)->connectors_active = false;
3837 }
3838 }
3839
3840 void intel_modeset_disable(struct drm_device *dev)
3841 {
3842 struct drm_crtc *crtc;
3843
3844 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3845 if (crtc->enabled)
3846 intel_crtc_disable(crtc);
3847 }
3848 }
3849
3850 void intel_encoder_noop(struct drm_encoder *encoder)
3851 {
3852 }
3853
3854 void intel_encoder_destroy(struct drm_encoder *encoder)
3855 {
3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3857
3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
3860 }
3861
3862 /* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3866 {
3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
3870 intel_crtc_update_dpms(encoder->base.crtc);
3871 } else {
3872 encoder->connectors_active = false;
3873
3874 intel_crtc_update_dpms(encoder->base.crtc);
3875 }
3876 }
3877
3878 /* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
3880 static void intel_connector_check_state(struct intel_connector *connector)
3881 {
3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
3911 }
3912
3913 /* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915 void intel_connector_dpms(struct drm_connector *connector, int mode)
3916 {
3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
3918
3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
3922
3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
3932 WARN_ON(encoder->connectors_active != false);
3933
3934 intel_modeset_check_state(connector->dev);
3935 }
3936
3937 /* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940 bool intel_connector_get_hw_state(struct intel_connector *connector)
3941 {
3942 enum pipe pipe = 0;
3943 struct intel_encoder *encoder = connector->encoder;
3944
3945 return encoder->get_hw_state(encoder, &pipe);
3946 }
3947
3948 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3949 const struct drm_display_mode *mode,
3950 struct drm_display_mode *adjusted_mode)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953
3954 if (HAS_PCH_SPLIT(dev)) {
3955 /* FDI link clock is fixed at 2.7G */
3956 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3957 return false;
3958 }
3959
3960 /* All interlaced capable intel hw wants timings in frames. Note though
3961 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3962 * timings, so we need to be careful not to clobber these.*/
3963 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3964 drm_mode_set_crtcinfo(adjusted_mode, 0);
3965
3966 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3967 * with a hsync front porch of 0.
3968 */
3969 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3970 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3971 return false;
3972
3973 return true;
3974 }
3975
3976 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3977 {
3978 return 400000; /* FIXME */
3979 }
3980
3981 static int i945_get_display_clock_speed(struct drm_device *dev)
3982 {
3983 return 400000;
3984 }
3985
3986 static int i915_get_display_clock_speed(struct drm_device *dev)
3987 {
3988 return 333000;
3989 }
3990
3991 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3992 {
3993 return 200000;
3994 }
3995
3996 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3997 {
3998 u16 gcfgc = 0;
3999
4000 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4001
4002 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4003 return 133000;
4004 else {
4005 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4006 case GC_DISPLAY_CLOCK_333_MHZ:
4007 return 333000;
4008 default:
4009 case GC_DISPLAY_CLOCK_190_200_MHZ:
4010 return 190000;
4011 }
4012 }
4013 }
4014
4015 static int i865_get_display_clock_speed(struct drm_device *dev)
4016 {
4017 return 266000;
4018 }
4019
4020 static int i855_get_display_clock_speed(struct drm_device *dev)
4021 {
4022 u16 hpllcc = 0;
4023 /* Assume that the hardware is in the high speed state. This
4024 * should be the default.
4025 */
4026 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4027 case GC_CLOCK_133_200:
4028 case GC_CLOCK_100_200:
4029 return 200000;
4030 case GC_CLOCK_166_250:
4031 return 250000;
4032 case GC_CLOCK_100_133:
4033 return 133000;
4034 }
4035
4036 /* Shouldn't happen */
4037 return 0;
4038 }
4039
4040 static int i830_get_display_clock_speed(struct drm_device *dev)
4041 {
4042 return 133000;
4043 }
4044
4045 struct fdi_m_n {
4046 u32 tu;
4047 u32 gmch_m;
4048 u32 gmch_n;
4049 u32 link_m;
4050 u32 link_n;
4051 };
4052
4053 static void
4054 fdi_reduce_ratio(u32 *num, u32 *den)
4055 {
4056 while (*num > 0xffffff || *den > 0xffffff) {
4057 *num >>= 1;
4058 *den >>= 1;
4059 }
4060 }
4061
4062 static void
4063 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4064 int link_clock, struct fdi_m_n *m_n)
4065 {
4066 m_n->tu = 64; /* default size */
4067
4068 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4069 m_n->gmch_m = bits_per_pixel * pixel_clock;
4070 m_n->gmch_n = link_clock * nlanes * 8;
4071 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4072
4073 m_n->link_m = pixel_clock;
4074 m_n->link_n = link_clock;
4075 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4076 }
4077
4078 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4079 {
4080 if (i915_panel_use_ssc >= 0)
4081 return i915_panel_use_ssc != 0;
4082 return dev_priv->lvds_use_ssc
4083 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4084 }
4085
4086 /**
4087 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4088 * @crtc: CRTC structure
4089 * @mode: requested mode
4090 *
4091 * A pipe may be connected to one or more outputs. Based on the depth of the
4092 * attached framebuffer, choose a good color depth to use on the pipe.
4093 *
4094 * If possible, match the pipe depth to the fb depth. In some cases, this
4095 * isn't ideal, because the connected output supports a lesser or restricted
4096 * set of depths. Resolve that here:
4097 * LVDS typically supports only 6bpc, so clamp down in that case
4098 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4099 * Displays may support a restricted set as well, check EDID and clamp as
4100 * appropriate.
4101 * DP may want to dither down to 6bpc to fit larger modes
4102 *
4103 * RETURNS:
4104 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4105 * true if they don't match).
4106 */
4107 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4108 struct drm_framebuffer *fb,
4109 unsigned int *pipe_bpp,
4110 struct drm_display_mode *mode)
4111 {
4112 struct drm_device *dev = crtc->dev;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 struct drm_connector *connector;
4115 struct intel_encoder *intel_encoder;
4116 unsigned int display_bpc = UINT_MAX, bpc;
4117
4118 /* Walk the encoders & connectors on this crtc, get min bpc */
4119 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4120
4121 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4122 unsigned int lvds_bpc;
4123
4124 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4125 LVDS_A3_POWER_UP)
4126 lvds_bpc = 8;
4127 else
4128 lvds_bpc = 6;
4129
4130 if (lvds_bpc < display_bpc) {
4131 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4132 display_bpc = lvds_bpc;
4133 }
4134 continue;
4135 }
4136
4137 /* Not one of the known troublemakers, check the EDID */
4138 list_for_each_entry(connector, &dev->mode_config.connector_list,
4139 head) {
4140 if (connector->encoder != &intel_encoder->base)
4141 continue;
4142
4143 /* Don't use an invalid EDID bpc value */
4144 if (connector->display_info.bpc &&
4145 connector->display_info.bpc < display_bpc) {
4146 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4147 display_bpc = connector->display_info.bpc;
4148 }
4149 }
4150
4151 /*
4152 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4153 * through, clamp it down. (Note: >12bpc will be caught below.)
4154 */
4155 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4156 if (display_bpc > 8 && display_bpc < 12) {
4157 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4158 display_bpc = 12;
4159 } else {
4160 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4161 display_bpc = 8;
4162 }
4163 }
4164 }
4165
4166 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4167 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4168 display_bpc = 6;
4169 }
4170
4171 /*
4172 * We could just drive the pipe at the highest bpc all the time and
4173 * enable dithering as needed, but that costs bandwidth. So choose
4174 * the minimum value that expresses the full color range of the fb but
4175 * also stays within the max display bpc discovered above.
4176 */
4177
4178 switch (fb->depth) {
4179 case 8:
4180 bpc = 8; /* since we go through a colormap */
4181 break;
4182 case 15:
4183 case 16:
4184 bpc = 6; /* min is 18bpp */
4185 break;
4186 case 24:
4187 bpc = 8;
4188 break;
4189 case 30:
4190 bpc = 10;
4191 break;
4192 case 48:
4193 bpc = 12;
4194 break;
4195 default:
4196 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4197 bpc = min((unsigned int)8, display_bpc);
4198 break;
4199 }
4200
4201 display_bpc = min(display_bpc, bpc);
4202
4203 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4204 bpc, display_bpc);
4205
4206 *pipe_bpp = display_bpc * 3;
4207
4208 return display_bpc != bpc;
4209 }
4210
4211 static int vlv_get_refclk(struct drm_crtc *crtc)
4212 {
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 int refclk = 27000; /* for DP & HDMI */
4216
4217 return 100000; /* only one validated so far */
4218
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4220 refclk = 96000;
4221 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4222 if (intel_panel_use_ssc(dev_priv))
4223 refclk = 100000;
4224 else
4225 refclk = 96000;
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4227 refclk = 100000;
4228 }
4229
4230 return refclk;
4231 }
4232
4233 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4234 {
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int refclk;
4238
4239 if (IS_VALLEYVIEW(dev)) {
4240 refclk = vlv_get_refclk(crtc);
4241 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4242 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4243 refclk = dev_priv->lvds_ssc_freq * 1000;
4244 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4245 refclk / 1000);
4246 } else if (!IS_GEN2(dev)) {
4247 refclk = 96000;
4248 } else {
4249 refclk = 48000;
4250 }
4251
4252 return refclk;
4253 }
4254
4255 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4256 intel_clock_t *clock)
4257 {
4258 /* SDVO TV has fixed PLL values depend on its clock range,
4259 this mirrors vbios setting. */
4260 if (adjusted_mode->clock >= 100000
4261 && adjusted_mode->clock < 140500) {
4262 clock->p1 = 2;
4263 clock->p2 = 10;
4264 clock->n = 3;
4265 clock->m1 = 16;
4266 clock->m2 = 8;
4267 } else if (adjusted_mode->clock >= 140500
4268 && adjusted_mode->clock <= 200000) {
4269 clock->p1 = 1;
4270 clock->p2 = 10;
4271 clock->n = 6;
4272 clock->m1 = 12;
4273 clock->m2 = 8;
4274 }
4275 }
4276
4277 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4278 intel_clock_t *clock,
4279 intel_clock_t *reduced_clock)
4280 {
4281 struct drm_device *dev = crtc->dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284 int pipe = intel_crtc->pipe;
4285 u32 fp, fp2 = 0;
4286
4287 if (IS_PINEVIEW(dev)) {
4288 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4289 if (reduced_clock)
4290 fp2 = (1 << reduced_clock->n) << 16 |
4291 reduced_clock->m1 << 8 | reduced_clock->m2;
4292 } else {
4293 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4294 if (reduced_clock)
4295 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4296 reduced_clock->m2;
4297 }
4298
4299 I915_WRITE(FP0(pipe), fp);
4300
4301 intel_crtc->lowfreq_avail = false;
4302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4303 reduced_clock && i915_powersave) {
4304 I915_WRITE(FP1(pipe), fp2);
4305 intel_crtc->lowfreq_avail = true;
4306 } else {
4307 I915_WRITE(FP1(pipe), fp);
4308 }
4309 }
4310
4311 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4312 struct drm_display_mode *adjusted_mode)
4313 {
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 int pipe = intel_crtc->pipe;
4318 u32 temp;
4319
4320 temp = I915_READ(LVDS);
4321 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4322 if (pipe == 1) {
4323 temp |= LVDS_PIPEB_SELECT;
4324 } else {
4325 temp &= ~LVDS_PIPEB_SELECT;
4326 }
4327 /* set the corresponsding LVDS_BORDER bit */
4328 temp |= dev_priv->lvds_border_bits;
4329 /* Set the B0-B3 data pairs corresponding to whether we're going to
4330 * set the DPLLs for dual-channel mode or not.
4331 */
4332 if (clock->p2 == 7)
4333 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4334 else
4335 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4336
4337 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4338 * appropriately here, but we need to look more thoroughly into how
4339 * panels behave in the two modes.
4340 */
4341 /* set the dithering flag on LVDS as needed */
4342 if (INTEL_INFO(dev)->gen >= 4) {
4343 if (dev_priv->lvds_dither)
4344 temp |= LVDS_ENABLE_DITHER;
4345 else
4346 temp &= ~LVDS_ENABLE_DITHER;
4347 }
4348 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4349 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4350 temp |= LVDS_HSYNC_POLARITY;
4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4352 temp |= LVDS_VSYNC_POLARITY;
4353 I915_WRITE(LVDS, temp);
4354 }
4355
4356 static void vlv_update_pll(struct drm_crtc *crtc,
4357 struct drm_display_mode *mode,
4358 struct drm_display_mode *adjusted_mode,
4359 intel_clock_t *clock, intel_clock_t *reduced_clock,
4360 int num_connectors)
4361 {
4362 struct drm_device *dev = crtc->dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365 int pipe = intel_crtc->pipe;
4366 u32 dpll, mdiv, pdiv;
4367 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4368 bool is_sdvo;
4369 u32 temp;
4370
4371 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4372 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4373
4374 dpll = DPLL_VGA_MODE_DIS;
4375 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4378
4379 I915_WRITE(DPLL(pipe), dpll);
4380 POSTING_READ(DPLL(pipe));
4381
4382 bestn = clock->n;
4383 bestm1 = clock->m1;
4384 bestm2 = clock->m2;
4385 bestp1 = clock->p1;
4386 bestp2 = clock->p2;
4387
4388 /*
4389 * In Valleyview PLL and program lane counter registers are exposed
4390 * through DPIO interface
4391 */
4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
4395 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4396 mdiv |= (1 << DPIO_K_SHIFT);
4397 mdiv |= DPIO_ENABLE_CALIBRATION;
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4399
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4401
4402 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4403 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4404 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4405 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4407
4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4409
4410 dpll |= DPLL_VCO_ENABLE;
4411 I915_WRITE(DPLL(pipe), dpll);
4412 POSTING_READ(DPLL(pipe));
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4415
4416 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4417
4418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4420
4421 I915_WRITE(DPLL(pipe), dpll);
4422
4423 /* Wait for the clocks to stabilize. */
4424 POSTING_READ(DPLL(pipe));
4425 udelay(150);
4426
4427 temp = 0;
4428 if (is_sdvo) {
4429 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4430 if (temp > 1)
4431 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4432 else
4433 temp = 0;
4434 }
4435 I915_WRITE(DPLL_MD(pipe), temp);
4436 POSTING_READ(DPLL_MD(pipe));
4437
4438 /* Now program lane control registers */
4439 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4440 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4441 {
4442 temp = 0x1000C4;
4443 if(pipe == 1)
4444 temp |= (1 << 21);
4445 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4446 }
4447 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4448 {
4449 temp = 0x1000C4;
4450 if(pipe == 1)
4451 temp |= (1 << 21);
4452 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4453 }
4454 }
4455
4456 static void i9xx_update_pll(struct drm_crtc *crtc,
4457 struct drm_display_mode *mode,
4458 struct drm_display_mode *adjusted_mode,
4459 intel_clock_t *clock, intel_clock_t *reduced_clock,
4460 int num_connectors)
4461 {
4462 struct drm_device *dev = crtc->dev;
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 int pipe = intel_crtc->pipe;
4466 u32 dpll;
4467 bool is_sdvo;
4468
4469 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4470
4471 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4473
4474 dpll = DPLL_VGA_MODE_DIS;
4475
4476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477 dpll |= DPLLB_MODE_LVDS;
4478 else
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4480 if (is_sdvo) {
4481 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482 if (pixel_multiplier > 1) {
4483 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4485 }
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4487 }
4488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490
4491 /* compute bitmask from p1 value */
4492 if (IS_PINEVIEW(dev))
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4494 else {
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496 if (IS_G4X(dev) && reduced_clock)
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4498 }
4499 switch (clock->p2) {
4500 case 5:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4502 break;
4503 case 7:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4505 break;
4506 case 10:
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4508 break;
4509 case 14:
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4511 break;
4512 }
4513 if (INTEL_INFO(dev)->gen >= 4)
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4515
4516 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 /* XXX: just matching BIOS for now */
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521 dpll |= 3;
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525 else
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4531 udelay(150);
4532
4533 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4534 * This is an exception to the general rule that mode_set doesn't turn
4535 * things on.
4536 */
4537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4538 intel_update_lvds(crtc, clock, adjusted_mode);
4539
4540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4541 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4542
4543 I915_WRITE(DPLL(pipe), dpll);
4544
4545 /* Wait for the clocks to stabilize. */
4546 POSTING_READ(DPLL(pipe));
4547 udelay(150);
4548
4549 if (INTEL_INFO(dev)->gen >= 4) {
4550 u32 temp = 0;
4551 if (is_sdvo) {
4552 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4553 if (temp > 1)
4554 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4555 else
4556 temp = 0;
4557 }
4558 I915_WRITE(DPLL_MD(pipe), temp);
4559 } else {
4560 /* The pixel multiplier can only be updated once the
4561 * DPLL is enabled and the clocks are stable.
4562 *
4563 * So write it again.
4564 */
4565 I915_WRITE(DPLL(pipe), dpll);
4566 }
4567 }
4568
4569 static void i8xx_update_pll(struct drm_crtc *crtc,
4570 struct drm_display_mode *adjusted_mode,
4571 intel_clock_t *clock, intel_clock_t *reduced_clock,
4572 int num_connectors)
4573 {
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4578 u32 dpll;
4579
4580 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4581
4582 dpll = DPLL_VGA_MODE_DIS;
4583
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586 } else {
4587 if (clock->p1 == 2)
4588 dpll |= PLL_P1_DIVIDE_BY_TWO;
4589 else
4590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 if (clock->p2 == 4)
4592 dpll |= PLL_P2_DIVIDE_BY_4;
4593 }
4594
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4596 /* XXX: just matching BIOS for now */
4597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4598 dpll |= 3;
4599 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4602 else
4603 dpll |= PLL_REF_INPUT_DREFCLK;
4604
4605 dpll |= DPLL_VCO_ENABLE;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607 POSTING_READ(DPLL(pipe));
4608 udelay(150);
4609
4610 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4611 * This is an exception to the general rule that mode_set doesn't turn
4612 * things on.
4613 */
4614 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4615 intel_update_lvds(crtc, clock, adjusted_mode);
4616
4617 I915_WRITE(DPLL(pipe), dpll);
4618
4619 /* Wait for the clocks to stabilize. */
4620 POSTING_READ(DPLL(pipe));
4621 udelay(150);
4622
4623 /* The pixel multiplier can only be updated once the
4624 * DPLL is enabled and the clocks are stable.
4625 *
4626 * So write it again.
4627 */
4628 I915_WRITE(DPLL(pipe), dpll);
4629 }
4630
4631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4632 struct drm_display_mode *mode,
4633 struct drm_display_mode *adjusted_mode)
4634 {
4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 enum pipe pipe = intel_crtc->pipe;
4638 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4639 uint32_t vsyncshift;
4640
4641 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vtotal -= 1;
4644 adjusted_mode->crtc_vblank_end -= 1;
4645 vsyncshift = adjusted_mode->crtc_hsync_start
4646 - adjusted_mode->crtc_htotal / 2;
4647 } else {
4648 vsyncshift = 0;
4649 }
4650
4651 if (INTEL_INFO(dev)->gen > 3)
4652 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4653
4654 I915_WRITE(HTOTAL(cpu_transcoder),
4655 (adjusted_mode->crtc_hdisplay - 1) |
4656 ((adjusted_mode->crtc_htotal - 1) << 16));
4657 I915_WRITE(HBLANK(cpu_transcoder),
4658 (adjusted_mode->crtc_hblank_start - 1) |
4659 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4660 I915_WRITE(HSYNC(cpu_transcoder),
4661 (adjusted_mode->crtc_hsync_start - 1) |
4662 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4663
4664 I915_WRITE(VTOTAL(cpu_transcoder),
4665 (adjusted_mode->crtc_vdisplay - 1) |
4666 ((adjusted_mode->crtc_vtotal - 1) << 16));
4667 I915_WRITE(VBLANK(cpu_transcoder),
4668 (adjusted_mode->crtc_vblank_start - 1) |
4669 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4670 I915_WRITE(VSYNC(cpu_transcoder),
4671 (adjusted_mode->crtc_vsync_start - 1) |
4672 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4673
4674 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4675 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4676 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4677 * bits. */
4678 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4679 (pipe == PIPE_B || pipe == PIPE_C))
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4681
4682 /* pipesrc controls the size that is scaled from, which should
4683 * always be the user's requested size.
4684 */
4685 I915_WRITE(PIPESRC(pipe),
4686 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4687 }
4688
4689 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4690 struct drm_display_mode *mode,
4691 struct drm_display_mode *adjusted_mode,
4692 int x, int y,
4693 struct drm_framebuffer *fb)
4694 {
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
4699 int plane = intel_crtc->plane;
4700 int refclk, num_connectors = 0;
4701 intel_clock_t clock, reduced_clock;
4702 u32 dspcntr, pipeconf;
4703 bool ok, has_reduced_clock = false, is_sdvo = false;
4704 bool is_lvds = false, is_tv = false, is_dp = false;
4705 struct intel_encoder *encoder;
4706 const intel_limit_t *limit;
4707 int ret;
4708
4709 for_each_encoder_on_crtc(dev, crtc, encoder) {
4710 switch (encoder->type) {
4711 case INTEL_OUTPUT_LVDS:
4712 is_lvds = true;
4713 break;
4714 case INTEL_OUTPUT_SDVO:
4715 case INTEL_OUTPUT_HDMI:
4716 is_sdvo = true;
4717 if (encoder->needs_tv_clock)
4718 is_tv = true;
4719 break;
4720 case INTEL_OUTPUT_TVOUT:
4721 is_tv = true;
4722 break;
4723 case INTEL_OUTPUT_DISPLAYPORT:
4724 is_dp = true;
4725 break;
4726 }
4727
4728 num_connectors++;
4729 }
4730
4731 refclk = i9xx_get_refclk(crtc, num_connectors);
4732
4733 /*
4734 * Returns a set of divisors for the desired target clock with the given
4735 * refclk, or FALSE. The returned values represent the clock equation:
4736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4737 */
4738 limit = intel_limit(crtc, refclk);
4739 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4740 &clock);
4741 if (!ok) {
4742 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4743 return -EINVAL;
4744 }
4745
4746 /* Ensure that the cursor is valid for the new mode before changing... */
4747 intel_crtc_update_cursor(crtc, true);
4748
4749 if (is_lvds && dev_priv->lvds_downclock_avail) {
4750 /*
4751 * Ensure we match the reduced clock's P to the target clock.
4752 * If the clocks don't match, we can't switch the display clock
4753 * by using the FP0/FP1. In such case we will disable the LVDS
4754 * downclock feature.
4755 */
4756 has_reduced_clock = limit->find_pll(limit, crtc,
4757 dev_priv->lvds_downclock,
4758 refclk,
4759 &clock,
4760 &reduced_clock);
4761 }
4762
4763 if (is_sdvo && is_tv)
4764 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4765
4766 if (IS_GEN2(dev))
4767 i8xx_update_pll(crtc, adjusted_mode, &clock,
4768 has_reduced_clock ? &reduced_clock : NULL,
4769 num_connectors);
4770 else if (IS_VALLEYVIEW(dev))
4771 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4772 has_reduced_clock ? &reduced_clock : NULL,
4773 num_connectors);
4774 else
4775 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4776 has_reduced_clock ? &reduced_clock : NULL,
4777 num_connectors);
4778
4779 /* setup pipeconf */
4780 pipeconf = I915_READ(PIPECONF(pipe));
4781
4782 /* Set up the display plane register */
4783 dspcntr = DISPPLANE_GAMMA_ENABLE;
4784
4785 if (pipe == 0)
4786 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4787 else
4788 dspcntr |= DISPPLANE_SEL_PIPE_B;
4789
4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792 * core speed.
4793 *
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4796 */
4797 if (mode->clock >
4798 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799 pipeconf |= PIPECONF_DOUBLE_WIDE;
4800 else
4801 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4802 }
4803
4804 /* default to 8bpc */
4805 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4806 if (is_dp) {
4807 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4808 pipeconf |= PIPECONF_BPP_6 |
4809 PIPECONF_DITHER_EN |
4810 PIPECONF_DITHER_TYPE_SP;
4811 }
4812 }
4813
4814 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4815 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4816 pipeconf |= PIPECONF_BPP_6 |
4817 PIPECONF_ENABLE |
4818 I965_PIPECONF_ACTIVE;
4819 }
4820 }
4821
4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4823 drm_mode_debug_printmodeline(mode);
4824
4825 if (HAS_PIPE_CXSR(dev)) {
4826 if (intel_crtc->lowfreq_avail) {
4827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4829 } else {
4830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4831 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4832 }
4833 }
4834
4835 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4836 if (!IS_GEN2(dev) &&
4837 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4838 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4839 else
4840 pipeconf |= PIPECONF_PROGRESSIVE;
4841
4842 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4843
4844 /* pipesrc and dspsize control the size that is scaled from,
4845 * which should always be the user's requested size.
4846 */
4847 I915_WRITE(DSPSIZE(plane),
4848 ((mode->vdisplay - 1) << 16) |
4849 (mode->hdisplay - 1));
4850 I915_WRITE(DSPPOS(plane), 0);
4851
4852 I915_WRITE(PIPECONF(pipe), pipeconf);
4853 POSTING_READ(PIPECONF(pipe));
4854 intel_enable_pipe(dev_priv, pipe, false);
4855
4856 intel_wait_for_vblank(dev, pipe);
4857
4858 I915_WRITE(DSPCNTR(plane), dspcntr);
4859 POSTING_READ(DSPCNTR(plane));
4860
4861 ret = intel_pipe_set_base(crtc, x, y, fb);
4862
4863 intel_update_watermarks(dev);
4864
4865 return ret;
4866 }
4867
4868 /*
4869 * Initialize reference clocks when the driver loads
4870 */
4871 void ironlake_init_pch_refclk(struct drm_device *dev)
4872 {
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 struct drm_mode_config *mode_config = &dev->mode_config;
4875 struct intel_encoder *encoder;
4876 u32 temp;
4877 bool has_lvds = false;
4878 bool has_cpu_edp = false;
4879 bool has_pch_edp = false;
4880 bool has_panel = false;
4881 bool has_ck505 = false;
4882 bool can_ssc = false;
4883
4884 /* We need to take the global config into account */
4885 list_for_each_entry(encoder, &mode_config->encoder_list,
4886 base.head) {
4887 switch (encoder->type) {
4888 case INTEL_OUTPUT_LVDS:
4889 has_panel = true;
4890 has_lvds = true;
4891 break;
4892 case INTEL_OUTPUT_EDP:
4893 has_panel = true;
4894 if (intel_encoder_is_pch_edp(&encoder->base))
4895 has_pch_edp = true;
4896 else
4897 has_cpu_edp = true;
4898 break;
4899 }
4900 }
4901
4902 if (HAS_PCH_IBX(dev)) {
4903 has_ck505 = dev_priv->display_clock_mode;
4904 can_ssc = has_ck505;
4905 } else {
4906 has_ck505 = false;
4907 can_ssc = true;
4908 }
4909
4910 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4911 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4912 has_ck505);
4913
4914 /* Ironlake: try to setup display ref clock before DPLL
4915 * enabling. This is only under driver's control after
4916 * PCH B stepping, previous chipset stepping should be
4917 * ignoring this setting.
4918 */
4919 temp = I915_READ(PCH_DREF_CONTROL);
4920 /* Always enable nonspread source */
4921 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4922
4923 if (has_ck505)
4924 temp |= DREF_NONSPREAD_CK505_ENABLE;
4925 else
4926 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4927
4928 if (has_panel) {
4929 temp &= ~DREF_SSC_SOURCE_MASK;
4930 temp |= DREF_SSC_SOURCE_ENABLE;
4931
4932 /* SSC must be turned on before enabling the CPU output */
4933 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4934 DRM_DEBUG_KMS("Using SSC on panel\n");
4935 temp |= DREF_SSC1_ENABLE;
4936 } else
4937 temp &= ~DREF_SSC1_ENABLE;
4938
4939 /* Get SSC going before enabling the outputs */
4940 I915_WRITE(PCH_DREF_CONTROL, temp);
4941 POSTING_READ(PCH_DREF_CONTROL);
4942 udelay(200);
4943
4944 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4945
4946 /* Enable CPU source on CPU attached eDP */
4947 if (has_cpu_edp) {
4948 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4949 DRM_DEBUG_KMS("Using SSC on eDP\n");
4950 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4951 }
4952 else
4953 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4954 } else
4955 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4956
4957 I915_WRITE(PCH_DREF_CONTROL, temp);
4958 POSTING_READ(PCH_DREF_CONTROL);
4959 udelay(200);
4960 } else {
4961 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4962
4963 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4964
4965 /* Turn off CPU output */
4966 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4967
4968 I915_WRITE(PCH_DREF_CONTROL, temp);
4969 POSTING_READ(PCH_DREF_CONTROL);
4970 udelay(200);
4971
4972 /* Turn off the SSC source */
4973 temp &= ~DREF_SSC_SOURCE_MASK;
4974 temp |= DREF_SSC_SOURCE_DISABLE;
4975
4976 /* Turn off SSC1 */
4977 temp &= ~ DREF_SSC1_ENABLE;
4978
4979 I915_WRITE(PCH_DREF_CONTROL, temp);
4980 POSTING_READ(PCH_DREF_CONTROL);
4981 udelay(200);
4982 }
4983 }
4984
4985 static int ironlake_get_refclk(struct drm_crtc *crtc)
4986 {
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 struct intel_encoder *encoder;
4990 struct intel_encoder *edp_encoder = NULL;
4991 int num_connectors = 0;
4992 bool is_lvds = false;
4993
4994 for_each_encoder_on_crtc(dev, crtc, encoder) {
4995 switch (encoder->type) {
4996 case INTEL_OUTPUT_LVDS:
4997 is_lvds = true;
4998 break;
4999 case INTEL_OUTPUT_EDP:
5000 edp_encoder = encoder;
5001 break;
5002 }
5003 num_connectors++;
5004 }
5005
5006 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008 dev_priv->lvds_ssc_freq);
5009 return dev_priv->lvds_ssc_freq * 1000;
5010 }
5011
5012 return 120000;
5013 }
5014
5015 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5016 struct drm_display_mode *adjusted_mode,
5017 bool dither)
5018 {
5019 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5021 int pipe = intel_crtc->pipe;
5022 uint32_t val;
5023
5024 val = I915_READ(PIPECONF(pipe));
5025
5026 val &= ~PIPE_BPC_MASK;
5027 switch (intel_crtc->bpp) {
5028 case 18:
5029 val |= PIPE_6BPC;
5030 break;
5031 case 24:
5032 val |= PIPE_8BPC;
5033 break;
5034 case 30:
5035 val |= PIPE_10BPC;
5036 break;
5037 case 36:
5038 val |= PIPE_12BPC;
5039 break;
5040 default:
5041 /* Case prevented by intel_choose_pipe_bpp_dither. */
5042 BUG();
5043 }
5044
5045 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5046 if (dither)
5047 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5048
5049 val &= ~PIPECONF_INTERLACE_MASK;
5050 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5051 val |= PIPECONF_INTERLACED_ILK;
5052 else
5053 val |= PIPECONF_PROGRESSIVE;
5054
5055 I915_WRITE(PIPECONF(pipe), val);
5056 POSTING_READ(PIPECONF(pipe));
5057 }
5058
5059 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5060 struct drm_display_mode *adjusted_mode,
5061 bool dither)
5062 {
5063 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5065 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5066 uint32_t val;
5067
5068 val = I915_READ(PIPECONF(cpu_transcoder));
5069
5070 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5071 if (dither)
5072 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5073
5074 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5075 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5076 val |= PIPECONF_INTERLACED_ILK;
5077 else
5078 val |= PIPECONF_PROGRESSIVE;
5079
5080 I915_WRITE(PIPECONF(cpu_transcoder), val);
5081 POSTING_READ(PIPECONF(cpu_transcoder));
5082 }
5083
5084 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5085 struct drm_display_mode *adjusted_mode,
5086 intel_clock_t *clock,
5087 bool *has_reduced_clock,
5088 intel_clock_t *reduced_clock)
5089 {
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_encoder *intel_encoder;
5093 int refclk;
5094 const intel_limit_t *limit;
5095 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5096
5097 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5098 switch (intel_encoder->type) {
5099 case INTEL_OUTPUT_LVDS:
5100 is_lvds = true;
5101 break;
5102 case INTEL_OUTPUT_SDVO:
5103 case INTEL_OUTPUT_HDMI:
5104 is_sdvo = true;
5105 if (intel_encoder->needs_tv_clock)
5106 is_tv = true;
5107 break;
5108 case INTEL_OUTPUT_TVOUT:
5109 is_tv = true;
5110 break;
5111 }
5112 }
5113
5114 refclk = ironlake_get_refclk(crtc);
5115
5116 /*
5117 * Returns a set of divisors for the desired target clock with the given
5118 * refclk, or FALSE. The returned values represent the clock equation:
5119 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5120 */
5121 limit = intel_limit(crtc, refclk);
5122 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5123 clock);
5124 if (!ret)
5125 return false;
5126
5127 if (is_lvds && dev_priv->lvds_downclock_avail) {
5128 /*
5129 * Ensure we match the reduced clock's P to the target clock.
5130 * If the clocks don't match, we can't switch the display clock
5131 * by using the FP0/FP1. In such case we will disable the LVDS
5132 * downclock feature.
5133 */
5134 *has_reduced_clock = limit->find_pll(limit, crtc,
5135 dev_priv->lvds_downclock,
5136 refclk,
5137 clock,
5138 reduced_clock);
5139 }
5140
5141 if (is_sdvo && is_tv)
5142 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5143
5144 return true;
5145 }
5146
5147 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5148 {
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 uint32_t temp;
5151
5152 temp = I915_READ(SOUTH_CHICKEN1);
5153 if (temp & FDI_BC_BIFURCATION_SELECT)
5154 return;
5155
5156 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5157 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5158
5159 temp |= FDI_BC_BIFURCATION_SELECT;
5160 DRM_DEBUG_KMS("enabling fdi C rx\n");
5161 I915_WRITE(SOUTH_CHICKEN1, temp);
5162 POSTING_READ(SOUTH_CHICKEN1);
5163 }
5164
5165 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5166 {
5167 struct drm_device *dev = intel_crtc->base.dev;
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 struct intel_crtc *pipe_B_crtc =
5170 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5171
5172 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5173 intel_crtc->pipe, intel_crtc->fdi_lanes);
5174 if (intel_crtc->fdi_lanes > 4) {
5175 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5176 intel_crtc->pipe, intel_crtc->fdi_lanes);
5177 /* Clamp lanes to avoid programming the hw with bogus values. */
5178 intel_crtc->fdi_lanes = 4;
5179
5180 return false;
5181 }
5182
5183 if (dev_priv->num_pipe == 2)
5184 return true;
5185
5186 switch (intel_crtc->pipe) {
5187 case PIPE_A:
5188 return true;
5189 case PIPE_B:
5190 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5191 intel_crtc->fdi_lanes > 2) {
5192 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5193 intel_crtc->pipe, intel_crtc->fdi_lanes);
5194 /* Clamp lanes to avoid programming the hw with bogus values. */
5195 intel_crtc->fdi_lanes = 2;
5196
5197 return false;
5198 }
5199
5200 if (intel_crtc->fdi_lanes > 2)
5201 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5202 else
5203 cpt_enable_fdi_bc_bifurcation(dev);
5204
5205 return true;
5206 case PIPE_C:
5207 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5208 if (intel_crtc->fdi_lanes > 2) {
5209 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5210 intel_crtc->pipe, intel_crtc->fdi_lanes);
5211 /* Clamp lanes to avoid programming the hw with bogus values. */
5212 intel_crtc->fdi_lanes = 2;
5213
5214 return false;
5215 }
5216 } else {
5217 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5218 return false;
5219 }
5220
5221 cpt_enable_fdi_bc_bifurcation(dev);
5222
5223 return true;
5224 default:
5225 BUG();
5226 }
5227 }
5228
5229 static void ironlake_set_m_n(struct drm_crtc *crtc,
5230 struct drm_display_mode *mode,
5231 struct drm_display_mode *adjusted_mode)
5232 {
5233 struct drm_device *dev = crtc->dev;
5234 struct drm_i915_private *dev_priv = dev->dev_private;
5235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5236 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5237 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5238 struct fdi_m_n m_n = {0};
5239 int target_clock, pixel_multiplier, lane, link_bw;
5240 bool is_dp = false, is_cpu_edp = false;
5241
5242 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5243 switch (intel_encoder->type) {
5244 case INTEL_OUTPUT_DISPLAYPORT:
5245 is_dp = true;
5246 break;
5247 case INTEL_OUTPUT_EDP:
5248 is_dp = true;
5249 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5250 is_cpu_edp = true;
5251 edp_encoder = intel_encoder;
5252 break;
5253 }
5254 }
5255
5256 /* FDI link */
5257 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5258 lane = 0;
5259 /* CPU eDP doesn't require FDI link, so just set DP M/N
5260 according to current link config */
5261 if (is_cpu_edp) {
5262 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5263 } else {
5264 /* FDI is a binary signal running at ~2.7GHz, encoding
5265 * each output octet as 10 bits. The actual frequency
5266 * is stored as a divider into a 100MHz clock, and the
5267 * mode pixel clock is stored in units of 1KHz.
5268 * Hence the bw of each lane in terms of the mode signal
5269 * is:
5270 */
5271 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5272 }
5273
5274 /* [e]DP over FDI requires target mode clock instead of link clock. */
5275 if (edp_encoder)
5276 target_clock = intel_edp_target_clock(edp_encoder, mode);
5277 else if (is_dp)
5278 target_clock = mode->clock;
5279 else
5280 target_clock = adjusted_mode->clock;
5281
5282 if (!lane) {
5283 /*
5284 * Account for spread spectrum to avoid
5285 * oversubscribing the link. Max center spread
5286 * is 2.5%; use 5% for safety's sake.
5287 */
5288 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5289 lane = bps / (link_bw * 8) + 1;
5290 }
5291
5292 intel_crtc->fdi_lanes = lane;
5293
5294 if (pixel_multiplier > 1)
5295 link_bw *= pixel_multiplier;
5296 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5297 &m_n);
5298
5299 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5300 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5301 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5302 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5303 }
5304
5305 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5306 struct drm_display_mode *adjusted_mode,
5307 intel_clock_t *clock, u32 fp)
5308 {
5309 struct drm_crtc *crtc = &intel_crtc->base;
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct intel_encoder *intel_encoder;
5313 uint32_t dpll;
5314 int factor, pixel_multiplier, num_connectors = 0;
5315 bool is_lvds = false, is_sdvo = false, is_tv = false;
5316 bool is_dp = false, is_cpu_edp = false;
5317
5318 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5319 switch (intel_encoder->type) {
5320 case INTEL_OUTPUT_LVDS:
5321 is_lvds = true;
5322 break;
5323 case INTEL_OUTPUT_SDVO:
5324 case INTEL_OUTPUT_HDMI:
5325 is_sdvo = true;
5326 if (intel_encoder->needs_tv_clock)
5327 is_tv = true;
5328 break;
5329 case INTEL_OUTPUT_TVOUT:
5330 is_tv = true;
5331 break;
5332 case INTEL_OUTPUT_DISPLAYPORT:
5333 is_dp = true;
5334 break;
5335 case INTEL_OUTPUT_EDP:
5336 is_dp = true;
5337 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5338 is_cpu_edp = true;
5339 break;
5340 }
5341
5342 num_connectors++;
5343 }
5344
5345 /* Enable autotuning of the PLL clock (if permissible) */
5346 factor = 21;
5347 if (is_lvds) {
5348 if ((intel_panel_use_ssc(dev_priv) &&
5349 dev_priv->lvds_ssc_freq == 100) ||
5350 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5351 factor = 25;
5352 } else if (is_sdvo && is_tv)
5353 factor = 20;
5354
5355 if (clock->m < factor * clock->n)
5356 fp |= FP_CB_TUNE;
5357
5358 dpll = 0;
5359
5360 if (is_lvds)
5361 dpll |= DPLLB_MODE_LVDS;
5362 else
5363 dpll |= DPLLB_MODE_DAC_SERIAL;
5364 if (is_sdvo) {
5365 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5366 if (pixel_multiplier > 1) {
5367 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5368 }
5369 dpll |= DPLL_DVO_HIGH_SPEED;
5370 }
5371 if (is_dp && !is_cpu_edp)
5372 dpll |= DPLL_DVO_HIGH_SPEED;
5373
5374 /* compute bitmask from p1 value */
5375 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5376 /* also FPA1 */
5377 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5378
5379 switch (clock->p2) {
5380 case 5:
5381 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5382 break;
5383 case 7:
5384 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5385 break;
5386 case 10:
5387 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5388 break;
5389 case 14:
5390 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5391 break;
5392 }
5393
5394 if (is_sdvo && is_tv)
5395 dpll |= PLL_REF_INPUT_TVCLKINBC;
5396 else if (is_tv)
5397 /* XXX: just matching BIOS for now */
5398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5399 dpll |= 3;
5400 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5401 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5402 else
5403 dpll |= PLL_REF_INPUT_DREFCLK;
5404
5405 return dpll;
5406 }
5407
5408 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5409 struct drm_display_mode *mode,
5410 struct drm_display_mode *adjusted_mode,
5411 int x, int y,
5412 struct drm_framebuffer *fb)
5413 {
5414 struct drm_device *dev = crtc->dev;
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5417 int pipe = intel_crtc->pipe;
5418 int plane = intel_crtc->plane;
5419 int num_connectors = 0;
5420 intel_clock_t clock, reduced_clock;
5421 u32 dpll, fp = 0, fp2 = 0;
5422 bool ok, has_reduced_clock = false;
5423 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5424 struct intel_encoder *encoder;
5425 u32 temp;
5426 int ret;
5427 bool dither, fdi_config_ok;
5428
5429 for_each_encoder_on_crtc(dev, crtc, encoder) {
5430 switch (encoder->type) {
5431 case INTEL_OUTPUT_LVDS:
5432 is_lvds = true;
5433 break;
5434 case INTEL_OUTPUT_DISPLAYPORT:
5435 is_dp = true;
5436 break;
5437 case INTEL_OUTPUT_EDP:
5438 is_dp = true;
5439 if (!intel_encoder_is_pch_edp(&encoder->base))
5440 is_cpu_edp = true;
5441 break;
5442 }
5443
5444 num_connectors++;
5445 }
5446
5447 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5448 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5449
5450 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5451 &has_reduced_clock, &reduced_clock);
5452 if (!ok) {
5453 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454 return -EINVAL;
5455 }
5456
5457 /* Ensure that the cursor is valid for the new mode before changing... */
5458 intel_crtc_update_cursor(crtc, true);
5459
5460 /* determine panel color depth */
5461 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5462 adjusted_mode);
5463 if (is_lvds && dev_priv->lvds_dither)
5464 dither = true;
5465
5466 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5467 if (has_reduced_clock)
5468 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5469 reduced_clock.m2;
5470
5471 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5472
5473 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5474 drm_mode_debug_printmodeline(mode);
5475
5476 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5477 if (!is_cpu_edp) {
5478 struct intel_pch_pll *pll;
5479
5480 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5481 if (pll == NULL) {
5482 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5483 pipe);
5484 return -EINVAL;
5485 }
5486 } else
5487 intel_put_pch_pll(intel_crtc);
5488
5489 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5490 * This is an exception to the general rule that mode_set doesn't turn
5491 * things on.
5492 */
5493 if (is_lvds) {
5494 temp = I915_READ(PCH_LVDS);
5495 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5496 if (HAS_PCH_CPT(dev)) {
5497 temp &= ~PORT_TRANS_SEL_MASK;
5498 temp |= PORT_TRANS_SEL_CPT(pipe);
5499 } else {
5500 if (pipe == 1)
5501 temp |= LVDS_PIPEB_SELECT;
5502 else
5503 temp &= ~LVDS_PIPEB_SELECT;
5504 }
5505
5506 /* set the corresponsding LVDS_BORDER bit */
5507 temp |= dev_priv->lvds_border_bits;
5508 /* Set the B0-B3 data pairs corresponding to whether we're going to
5509 * set the DPLLs for dual-channel mode or not.
5510 */
5511 if (clock.p2 == 7)
5512 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5513 else
5514 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5515
5516 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5517 * appropriately here, but we need to look more thoroughly into how
5518 * panels behave in the two modes.
5519 */
5520 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5521 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5522 temp |= LVDS_HSYNC_POLARITY;
5523 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5524 temp |= LVDS_VSYNC_POLARITY;
5525 I915_WRITE(PCH_LVDS, temp);
5526 }
5527
5528 if (is_dp && !is_cpu_edp) {
5529 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5530 } else {
5531 /* For non-DP output, clear any trans DP clock recovery setting.*/
5532 I915_WRITE(TRANSDATA_M1(pipe), 0);
5533 I915_WRITE(TRANSDATA_N1(pipe), 0);
5534 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5535 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5536 }
5537
5538 if (intel_crtc->pch_pll) {
5539 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5540
5541 /* Wait for the clocks to stabilize. */
5542 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5543 udelay(150);
5544
5545 /* The pixel multiplier can only be updated once the
5546 * DPLL is enabled and the clocks are stable.
5547 *
5548 * So write it again.
5549 */
5550 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5551 }
5552
5553 intel_crtc->lowfreq_avail = false;
5554 if (intel_crtc->pch_pll) {
5555 if (is_lvds && has_reduced_clock && i915_powersave) {
5556 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5557 intel_crtc->lowfreq_avail = true;
5558 } else {
5559 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5560 }
5561 }
5562
5563 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5564
5565 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5566 * ironlake_check_fdi_lanes. */
5567 ironlake_set_m_n(crtc, mode, adjusted_mode);
5568
5569 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5570
5571 if (is_cpu_edp)
5572 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5573
5574 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5575
5576 intel_wait_for_vblank(dev, pipe);
5577
5578 /* Set up the display plane register */
5579 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5580 POSTING_READ(DSPCNTR(plane));
5581
5582 ret = intel_pipe_set_base(crtc, x, y, fb);
5583
5584 intel_update_watermarks(dev);
5585
5586 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5587
5588 return fdi_config_ok ? ret : -EINVAL;
5589 }
5590
5591 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5592 struct drm_display_mode *mode,
5593 struct drm_display_mode *adjusted_mode,
5594 int x, int y,
5595 struct drm_framebuffer *fb)
5596 {
5597 struct drm_device *dev = crtc->dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5600 int pipe = intel_crtc->pipe;
5601 int plane = intel_crtc->plane;
5602 int num_connectors = 0;
5603 intel_clock_t clock, reduced_clock;
5604 u32 dpll = 0, fp = 0, fp2 = 0;
5605 bool ok, has_reduced_clock = false;
5606 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5607 struct intel_encoder *encoder;
5608 u32 temp;
5609 int ret;
5610 bool dither;
5611
5612 for_each_encoder_on_crtc(dev, crtc, encoder) {
5613 switch (encoder->type) {
5614 case INTEL_OUTPUT_LVDS:
5615 is_lvds = true;
5616 break;
5617 case INTEL_OUTPUT_DISPLAYPORT:
5618 is_dp = true;
5619 break;
5620 case INTEL_OUTPUT_EDP:
5621 is_dp = true;
5622 if (!intel_encoder_is_pch_edp(&encoder->base))
5623 is_cpu_edp = true;
5624 break;
5625 }
5626
5627 num_connectors++;
5628 }
5629
5630 if (is_cpu_edp)
5631 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5632 else
5633 intel_crtc->cpu_transcoder = pipe;
5634
5635 /* We are not sure yet this won't happen. */
5636 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5637 INTEL_PCH_TYPE(dev));
5638
5639 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5640 num_connectors, pipe_name(pipe));
5641
5642 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5643 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5644
5645 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5646
5647 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5648 return -EINVAL;
5649
5650 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5651 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5652 &has_reduced_clock,
5653 &reduced_clock);
5654 if (!ok) {
5655 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5656 return -EINVAL;
5657 }
5658 }
5659
5660 /* Ensure that the cursor is valid for the new mode before changing... */
5661 intel_crtc_update_cursor(crtc, true);
5662
5663 /* determine panel color depth */
5664 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5665 adjusted_mode);
5666 if (is_lvds && dev_priv->lvds_dither)
5667 dither = true;
5668
5669 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5670 drm_mode_debug_printmodeline(mode);
5671
5672 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5673 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5674 if (has_reduced_clock)
5675 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5676 reduced_clock.m2;
5677
5678 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5679 fp);
5680
5681 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5682 * own on pre-Haswell/LPT generation */
5683 if (!is_cpu_edp) {
5684 struct intel_pch_pll *pll;
5685
5686 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5687 if (pll == NULL) {
5688 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5689 pipe);
5690 return -EINVAL;
5691 }
5692 } else
5693 intel_put_pch_pll(intel_crtc);
5694
5695 /* The LVDS pin pair needs to be on before the DPLLs are
5696 * enabled. This is an exception to the general rule that
5697 * mode_set doesn't turn things on.
5698 */
5699 if (is_lvds) {
5700 temp = I915_READ(PCH_LVDS);
5701 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5702 if (HAS_PCH_CPT(dev)) {
5703 temp &= ~PORT_TRANS_SEL_MASK;
5704 temp |= PORT_TRANS_SEL_CPT(pipe);
5705 } else {
5706 if (pipe == 1)
5707 temp |= LVDS_PIPEB_SELECT;
5708 else
5709 temp &= ~LVDS_PIPEB_SELECT;
5710 }
5711
5712 /* set the corresponsding LVDS_BORDER bit */
5713 temp |= dev_priv->lvds_border_bits;
5714 /* Set the B0-B3 data pairs corresponding to whether
5715 * we're going to set the DPLLs for dual-channel mode or
5716 * not.
5717 */
5718 if (clock.p2 == 7)
5719 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5720 else
5721 temp &= ~(LVDS_B0B3_POWER_UP |
5722 LVDS_CLKB_POWER_UP);
5723
5724 /* It would be nice to set 24 vs 18-bit mode
5725 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5726 * look more thoroughly into how panels behave in the
5727 * two modes.
5728 */
5729 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5730 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5731 temp |= LVDS_HSYNC_POLARITY;
5732 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5733 temp |= LVDS_VSYNC_POLARITY;
5734 I915_WRITE(PCH_LVDS, temp);
5735 }
5736 }
5737
5738 if (is_dp && !is_cpu_edp) {
5739 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5740 } else {
5741 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5742 /* For non-DP output, clear any trans DP clock recovery
5743 * setting.*/
5744 I915_WRITE(TRANSDATA_M1(pipe), 0);
5745 I915_WRITE(TRANSDATA_N1(pipe), 0);
5746 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5747 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5748 }
5749 }
5750
5751 intel_crtc->lowfreq_avail = false;
5752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5753 if (intel_crtc->pch_pll) {
5754 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5755
5756 /* Wait for the clocks to stabilize. */
5757 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5758 udelay(150);
5759
5760 /* The pixel multiplier can only be updated once the
5761 * DPLL is enabled and the clocks are stable.
5762 *
5763 * So write it again.
5764 */
5765 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5766 }
5767
5768 if (intel_crtc->pch_pll) {
5769 if (is_lvds && has_reduced_clock && i915_powersave) {
5770 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5771 intel_crtc->lowfreq_avail = true;
5772 } else {
5773 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5774 }
5775 }
5776 }
5777
5778 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5779
5780 if (!is_dp || is_cpu_edp)
5781 ironlake_set_m_n(crtc, mode, adjusted_mode);
5782
5783 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5784 if (is_cpu_edp)
5785 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5786
5787 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5788
5789 /* Set up the display plane register */
5790 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5791 POSTING_READ(DSPCNTR(plane));
5792
5793 ret = intel_pipe_set_base(crtc, x, y, fb);
5794
5795 intel_update_watermarks(dev);
5796
5797 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5798
5799 return ret;
5800 }
5801
5802 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5803 struct drm_display_mode *mode,
5804 struct drm_display_mode *adjusted_mode,
5805 int x, int y,
5806 struct drm_framebuffer *fb)
5807 {
5808 struct drm_device *dev = crtc->dev;
5809 struct drm_i915_private *dev_priv = dev->dev_private;
5810 struct drm_encoder_helper_funcs *encoder_funcs;
5811 struct intel_encoder *encoder;
5812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813 int pipe = intel_crtc->pipe;
5814 int ret;
5815
5816 drm_vblank_pre_modeset(dev, pipe);
5817
5818 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5819 x, y, fb);
5820 drm_vblank_post_modeset(dev, pipe);
5821
5822 if (ret != 0)
5823 return ret;
5824
5825 for_each_encoder_on_crtc(dev, crtc, encoder) {
5826 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5827 encoder->base.base.id,
5828 drm_get_encoder_name(&encoder->base),
5829 mode->base.id, mode->name);
5830 encoder_funcs = encoder->base.helper_private;
5831 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5832 }
5833
5834 return 0;
5835 }
5836
5837 static bool intel_eld_uptodate(struct drm_connector *connector,
5838 int reg_eldv, uint32_t bits_eldv,
5839 int reg_elda, uint32_t bits_elda,
5840 int reg_edid)
5841 {
5842 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5843 uint8_t *eld = connector->eld;
5844 uint32_t i;
5845
5846 i = I915_READ(reg_eldv);
5847 i &= bits_eldv;
5848
5849 if (!eld[0])
5850 return !i;
5851
5852 if (!i)
5853 return false;
5854
5855 i = I915_READ(reg_elda);
5856 i &= ~bits_elda;
5857 I915_WRITE(reg_elda, i);
5858
5859 for (i = 0; i < eld[2]; i++)
5860 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5861 return false;
5862
5863 return true;
5864 }
5865
5866 static void g4x_write_eld(struct drm_connector *connector,
5867 struct drm_crtc *crtc)
5868 {
5869 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5870 uint8_t *eld = connector->eld;
5871 uint32_t eldv;
5872 uint32_t len;
5873 uint32_t i;
5874
5875 i = I915_READ(G4X_AUD_VID_DID);
5876
5877 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5878 eldv = G4X_ELDV_DEVCL_DEVBLC;
5879 else
5880 eldv = G4X_ELDV_DEVCTG;
5881
5882 if (intel_eld_uptodate(connector,
5883 G4X_AUD_CNTL_ST, eldv,
5884 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5885 G4X_HDMIW_HDMIEDID))
5886 return;
5887
5888 i = I915_READ(G4X_AUD_CNTL_ST);
5889 i &= ~(eldv | G4X_ELD_ADDR);
5890 len = (i >> 9) & 0x1f; /* ELD buffer size */
5891 I915_WRITE(G4X_AUD_CNTL_ST, i);
5892
5893 if (!eld[0])
5894 return;
5895
5896 len = min_t(uint8_t, eld[2], len);
5897 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5898 for (i = 0; i < len; i++)
5899 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5900
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i |= eldv;
5903 I915_WRITE(G4X_AUD_CNTL_ST, i);
5904 }
5905
5906 static void haswell_write_eld(struct drm_connector *connector,
5907 struct drm_crtc *crtc)
5908 {
5909 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5910 uint8_t *eld = connector->eld;
5911 struct drm_device *dev = crtc->dev;
5912 uint32_t eldv;
5913 uint32_t i;
5914 int len;
5915 int pipe = to_intel_crtc(crtc)->pipe;
5916 int tmp;
5917
5918 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5919 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5920 int aud_config = HSW_AUD_CFG(pipe);
5921 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5922
5923
5924 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5925
5926 /* Audio output enable */
5927 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5928 tmp = I915_READ(aud_cntrl_st2);
5929 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5930 I915_WRITE(aud_cntrl_st2, tmp);
5931
5932 /* Wait for 1 vertical blank */
5933 intel_wait_for_vblank(dev, pipe);
5934
5935 /* Set ELD valid state */
5936 tmp = I915_READ(aud_cntrl_st2);
5937 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5938 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5939 I915_WRITE(aud_cntrl_st2, tmp);
5940 tmp = I915_READ(aud_cntrl_st2);
5941 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5942
5943 /* Enable HDMI mode */
5944 tmp = I915_READ(aud_config);
5945 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5946 /* clear N_programing_enable and N_value_index */
5947 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5948 I915_WRITE(aud_config, tmp);
5949
5950 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5951
5952 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5953
5954 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5955 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5956 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5957 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5958 } else
5959 I915_WRITE(aud_config, 0);
5960
5961 if (intel_eld_uptodate(connector,
5962 aud_cntrl_st2, eldv,
5963 aud_cntl_st, IBX_ELD_ADDRESS,
5964 hdmiw_hdmiedid))
5965 return;
5966
5967 i = I915_READ(aud_cntrl_st2);
5968 i &= ~eldv;
5969 I915_WRITE(aud_cntrl_st2, i);
5970
5971 if (!eld[0])
5972 return;
5973
5974 i = I915_READ(aud_cntl_st);
5975 i &= ~IBX_ELD_ADDRESS;
5976 I915_WRITE(aud_cntl_st, i);
5977 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5978 DRM_DEBUG_DRIVER("port num:%d\n", i);
5979
5980 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5981 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5982 for (i = 0; i < len; i++)
5983 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5984
5985 i = I915_READ(aud_cntrl_st2);
5986 i |= eldv;
5987 I915_WRITE(aud_cntrl_st2, i);
5988
5989 }
5990
5991 static void ironlake_write_eld(struct drm_connector *connector,
5992 struct drm_crtc *crtc)
5993 {
5994 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5995 uint8_t *eld = connector->eld;
5996 uint32_t eldv;
5997 uint32_t i;
5998 int len;
5999 int hdmiw_hdmiedid;
6000 int aud_config;
6001 int aud_cntl_st;
6002 int aud_cntrl_st2;
6003 int pipe = to_intel_crtc(crtc)->pipe;
6004
6005 if (HAS_PCH_IBX(connector->dev)) {
6006 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6007 aud_config = IBX_AUD_CFG(pipe);
6008 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6009 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6010 } else {
6011 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6012 aud_config = CPT_AUD_CFG(pipe);
6013 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6014 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6015 }
6016
6017 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6018
6019 i = I915_READ(aud_cntl_st);
6020 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6021 if (!i) {
6022 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6023 /* operate blindly on all ports */
6024 eldv = IBX_ELD_VALIDB;
6025 eldv |= IBX_ELD_VALIDB << 4;
6026 eldv |= IBX_ELD_VALIDB << 8;
6027 } else {
6028 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6029 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6030 }
6031
6032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6033 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6034 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6035 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6036 } else
6037 I915_WRITE(aud_config, 0);
6038
6039 if (intel_eld_uptodate(connector,
6040 aud_cntrl_st2, eldv,
6041 aud_cntl_st, IBX_ELD_ADDRESS,
6042 hdmiw_hdmiedid))
6043 return;
6044
6045 i = I915_READ(aud_cntrl_st2);
6046 i &= ~eldv;
6047 I915_WRITE(aud_cntrl_st2, i);
6048
6049 if (!eld[0])
6050 return;
6051
6052 i = I915_READ(aud_cntl_st);
6053 i &= ~IBX_ELD_ADDRESS;
6054 I915_WRITE(aud_cntl_st, i);
6055
6056 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6057 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6058 for (i = 0; i < len; i++)
6059 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6060
6061 i = I915_READ(aud_cntrl_st2);
6062 i |= eldv;
6063 I915_WRITE(aud_cntrl_st2, i);
6064 }
6065
6066 void intel_write_eld(struct drm_encoder *encoder,
6067 struct drm_display_mode *mode)
6068 {
6069 struct drm_crtc *crtc = encoder->crtc;
6070 struct drm_connector *connector;
6071 struct drm_device *dev = encoder->dev;
6072 struct drm_i915_private *dev_priv = dev->dev_private;
6073
6074 connector = drm_select_eld(encoder, mode);
6075 if (!connector)
6076 return;
6077
6078 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6079 connector->base.id,
6080 drm_get_connector_name(connector),
6081 connector->encoder->base.id,
6082 drm_get_encoder_name(connector->encoder));
6083
6084 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6085
6086 if (dev_priv->display.write_eld)
6087 dev_priv->display.write_eld(connector, crtc);
6088 }
6089
6090 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6091 void intel_crtc_load_lut(struct drm_crtc *crtc)
6092 {
6093 struct drm_device *dev = crtc->dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6096 int palreg = PALETTE(intel_crtc->pipe);
6097 int i;
6098
6099 /* The clocks have to be on to load the palette. */
6100 if (!crtc->enabled || !intel_crtc->active)
6101 return;
6102
6103 /* use legacy palette for Ironlake */
6104 if (HAS_PCH_SPLIT(dev))
6105 palreg = LGC_PALETTE(intel_crtc->pipe);
6106
6107 for (i = 0; i < 256; i++) {
6108 I915_WRITE(palreg + 4 * i,
6109 (intel_crtc->lut_r[i] << 16) |
6110 (intel_crtc->lut_g[i] << 8) |
6111 intel_crtc->lut_b[i]);
6112 }
6113 }
6114
6115 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6116 {
6117 struct drm_device *dev = crtc->dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 bool visible = base != 0;
6121 u32 cntl;
6122
6123 if (intel_crtc->cursor_visible == visible)
6124 return;
6125
6126 cntl = I915_READ(_CURACNTR);
6127 if (visible) {
6128 /* On these chipsets we can only modify the base whilst
6129 * the cursor is disabled.
6130 */
6131 I915_WRITE(_CURABASE, base);
6132
6133 cntl &= ~(CURSOR_FORMAT_MASK);
6134 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6135 cntl |= CURSOR_ENABLE |
6136 CURSOR_GAMMA_ENABLE |
6137 CURSOR_FORMAT_ARGB;
6138 } else
6139 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6140 I915_WRITE(_CURACNTR, cntl);
6141
6142 intel_crtc->cursor_visible = visible;
6143 }
6144
6145 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6146 {
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 int pipe = intel_crtc->pipe;
6151 bool visible = base != 0;
6152
6153 if (intel_crtc->cursor_visible != visible) {
6154 uint32_t cntl = I915_READ(CURCNTR(pipe));
6155 if (base) {
6156 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6157 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6158 cntl |= pipe << 28; /* Connect to correct pipe */
6159 } else {
6160 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6161 cntl |= CURSOR_MODE_DISABLE;
6162 }
6163 I915_WRITE(CURCNTR(pipe), cntl);
6164
6165 intel_crtc->cursor_visible = visible;
6166 }
6167 /* and commit changes on next vblank */
6168 I915_WRITE(CURBASE(pipe), base);
6169 }
6170
6171 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6172 {
6173 struct drm_device *dev = crtc->dev;
6174 struct drm_i915_private *dev_priv = dev->dev_private;
6175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6176 int pipe = intel_crtc->pipe;
6177 bool visible = base != 0;
6178
6179 if (intel_crtc->cursor_visible != visible) {
6180 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6181 if (base) {
6182 cntl &= ~CURSOR_MODE;
6183 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6184 } else {
6185 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6186 cntl |= CURSOR_MODE_DISABLE;
6187 }
6188 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6189
6190 intel_crtc->cursor_visible = visible;
6191 }
6192 /* and commit changes on next vblank */
6193 I915_WRITE(CURBASE_IVB(pipe), base);
6194 }
6195
6196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6197 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6198 bool on)
6199 {
6200 struct drm_device *dev = crtc->dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6203 int pipe = intel_crtc->pipe;
6204 int x = intel_crtc->cursor_x;
6205 int y = intel_crtc->cursor_y;
6206 u32 base, pos;
6207 bool visible;
6208
6209 pos = 0;
6210
6211 if (on && crtc->enabled && crtc->fb) {
6212 base = intel_crtc->cursor_addr;
6213 if (x > (int) crtc->fb->width)
6214 base = 0;
6215
6216 if (y > (int) crtc->fb->height)
6217 base = 0;
6218 } else
6219 base = 0;
6220
6221 if (x < 0) {
6222 if (x + intel_crtc->cursor_width < 0)
6223 base = 0;
6224
6225 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6226 x = -x;
6227 }
6228 pos |= x << CURSOR_X_SHIFT;
6229
6230 if (y < 0) {
6231 if (y + intel_crtc->cursor_height < 0)
6232 base = 0;
6233
6234 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6235 y = -y;
6236 }
6237 pos |= y << CURSOR_Y_SHIFT;
6238
6239 visible = base != 0;
6240 if (!visible && !intel_crtc->cursor_visible)
6241 return;
6242
6243 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6244 I915_WRITE(CURPOS_IVB(pipe), pos);
6245 ivb_update_cursor(crtc, base);
6246 } else {
6247 I915_WRITE(CURPOS(pipe), pos);
6248 if (IS_845G(dev) || IS_I865G(dev))
6249 i845_update_cursor(crtc, base);
6250 else
6251 i9xx_update_cursor(crtc, base);
6252 }
6253 }
6254
6255 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6256 struct drm_file *file,
6257 uint32_t handle,
6258 uint32_t width, uint32_t height)
6259 {
6260 struct drm_device *dev = crtc->dev;
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6263 struct drm_i915_gem_object *obj;
6264 uint32_t addr;
6265 int ret;
6266
6267 /* if we want to turn off the cursor ignore width and height */
6268 if (!handle) {
6269 DRM_DEBUG_KMS("cursor off\n");
6270 addr = 0;
6271 obj = NULL;
6272 mutex_lock(&dev->struct_mutex);
6273 goto finish;
6274 }
6275
6276 /* Currently we only support 64x64 cursors */
6277 if (width != 64 || height != 64) {
6278 DRM_ERROR("we currently only support 64x64 cursors\n");
6279 return -EINVAL;
6280 }
6281
6282 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6283 if (&obj->base == NULL)
6284 return -ENOENT;
6285
6286 if (obj->base.size < width * height * 4) {
6287 DRM_ERROR("buffer is to small\n");
6288 ret = -ENOMEM;
6289 goto fail;
6290 }
6291
6292 /* we only need to pin inside GTT if cursor is non-phy */
6293 mutex_lock(&dev->struct_mutex);
6294 if (!dev_priv->info->cursor_needs_physical) {
6295 if (obj->tiling_mode) {
6296 DRM_ERROR("cursor cannot be tiled\n");
6297 ret = -EINVAL;
6298 goto fail_locked;
6299 }
6300
6301 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6302 if (ret) {
6303 DRM_ERROR("failed to move cursor bo into the GTT\n");
6304 goto fail_locked;
6305 }
6306
6307 ret = i915_gem_object_put_fence(obj);
6308 if (ret) {
6309 DRM_ERROR("failed to release fence for cursor");
6310 goto fail_unpin;
6311 }
6312
6313 addr = obj->gtt_offset;
6314 } else {
6315 int align = IS_I830(dev) ? 16 * 1024 : 256;
6316 ret = i915_gem_attach_phys_object(dev, obj,
6317 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6318 align);
6319 if (ret) {
6320 DRM_ERROR("failed to attach phys object\n");
6321 goto fail_locked;
6322 }
6323 addr = obj->phys_obj->handle->busaddr;
6324 }
6325
6326 if (IS_GEN2(dev))
6327 I915_WRITE(CURSIZE, (height << 12) | width);
6328
6329 finish:
6330 if (intel_crtc->cursor_bo) {
6331 if (dev_priv->info->cursor_needs_physical) {
6332 if (intel_crtc->cursor_bo != obj)
6333 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6334 } else
6335 i915_gem_object_unpin(intel_crtc->cursor_bo);
6336 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6337 }
6338
6339 mutex_unlock(&dev->struct_mutex);
6340
6341 intel_crtc->cursor_addr = addr;
6342 intel_crtc->cursor_bo = obj;
6343 intel_crtc->cursor_width = width;
6344 intel_crtc->cursor_height = height;
6345
6346 intel_crtc_update_cursor(crtc, true);
6347
6348 return 0;
6349 fail_unpin:
6350 i915_gem_object_unpin(obj);
6351 fail_locked:
6352 mutex_unlock(&dev->struct_mutex);
6353 fail:
6354 drm_gem_object_unreference_unlocked(&obj->base);
6355 return ret;
6356 }
6357
6358 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6359 {
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361
6362 intel_crtc->cursor_x = x;
6363 intel_crtc->cursor_y = y;
6364
6365 intel_crtc_update_cursor(crtc, true);
6366
6367 return 0;
6368 }
6369
6370 /** Sets the color ramps on behalf of RandR */
6371 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6372 u16 blue, int regno)
6373 {
6374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6375
6376 intel_crtc->lut_r[regno] = red >> 8;
6377 intel_crtc->lut_g[regno] = green >> 8;
6378 intel_crtc->lut_b[regno] = blue >> 8;
6379 }
6380
6381 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6382 u16 *blue, int regno)
6383 {
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385
6386 *red = intel_crtc->lut_r[regno] << 8;
6387 *green = intel_crtc->lut_g[regno] << 8;
6388 *blue = intel_crtc->lut_b[regno] << 8;
6389 }
6390
6391 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6392 u16 *blue, uint32_t start, uint32_t size)
6393 {
6394 int end = (start + size > 256) ? 256 : start + size, i;
6395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6396
6397 for (i = start; i < end; i++) {
6398 intel_crtc->lut_r[i] = red[i] >> 8;
6399 intel_crtc->lut_g[i] = green[i] >> 8;
6400 intel_crtc->lut_b[i] = blue[i] >> 8;
6401 }
6402
6403 intel_crtc_load_lut(crtc);
6404 }
6405
6406 /**
6407 * Get a pipe with a simple mode set on it for doing load-based monitor
6408 * detection.
6409 *
6410 * It will be up to the load-detect code to adjust the pipe as appropriate for
6411 * its requirements. The pipe will be connected to no other encoders.
6412 *
6413 * Currently this code will only succeed if there is a pipe with no encoders
6414 * configured for it. In the future, it could choose to temporarily disable
6415 * some outputs to free up a pipe for its use.
6416 *
6417 * \return crtc, or NULL if no pipes are available.
6418 */
6419
6420 /* VESA 640x480x72Hz mode to set on the pipe */
6421 static struct drm_display_mode load_detect_mode = {
6422 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6423 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6424 };
6425
6426 static struct drm_framebuffer *
6427 intel_framebuffer_create(struct drm_device *dev,
6428 struct drm_mode_fb_cmd2 *mode_cmd,
6429 struct drm_i915_gem_object *obj)
6430 {
6431 struct intel_framebuffer *intel_fb;
6432 int ret;
6433
6434 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6435 if (!intel_fb) {
6436 drm_gem_object_unreference_unlocked(&obj->base);
6437 return ERR_PTR(-ENOMEM);
6438 }
6439
6440 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6441 if (ret) {
6442 drm_gem_object_unreference_unlocked(&obj->base);
6443 kfree(intel_fb);
6444 return ERR_PTR(ret);
6445 }
6446
6447 return &intel_fb->base;
6448 }
6449
6450 static u32
6451 intel_framebuffer_pitch_for_width(int width, int bpp)
6452 {
6453 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6454 return ALIGN(pitch, 64);
6455 }
6456
6457 static u32
6458 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6459 {
6460 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6461 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6462 }
6463
6464 static struct drm_framebuffer *
6465 intel_framebuffer_create_for_mode(struct drm_device *dev,
6466 struct drm_display_mode *mode,
6467 int depth, int bpp)
6468 {
6469 struct drm_i915_gem_object *obj;
6470 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6471
6472 obj = i915_gem_alloc_object(dev,
6473 intel_framebuffer_size_for_mode(mode, bpp));
6474 if (obj == NULL)
6475 return ERR_PTR(-ENOMEM);
6476
6477 mode_cmd.width = mode->hdisplay;
6478 mode_cmd.height = mode->vdisplay;
6479 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6480 bpp);
6481 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6482
6483 return intel_framebuffer_create(dev, &mode_cmd, obj);
6484 }
6485
6486 static struct drm_framebuffer *
6487 mode_fits_in_fbdev(struct drm_device *dev,
6488 struct drm_display_mode *mode)
6489 {
6490 struct drm_i915_private *dev_priv = dev->dev_private;
6491 struct drm_i915_gem_object *obj;
6492 struct drm_framebuffer *fb;
6493
6494 if (dev_priv->fbdev == NULL)
6495 return NULL;
6496
6497 obj = dev_priv->fbdev->ifb.obj;
6498 if (obj == NULL)
6499 return NULL;
6500
6501 fb = &dev_priv->fbdev->ifb.base;
6502 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6503 fb->bits_per_pixel))
6504 return NULL;
6505
6506 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6507 return NULL;
6508
6509 return fb;
6510 }
6511
6512 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6513 struct drm_display_mode *mode,
6514 struct intel_load_detect_pipe *old)
6515 {
6516 struct intel_crtc *intel_crtc;
6517 struct intel_encoder *intel_encoder =
6518 intel_attached_encoder(connector);
6519 struct drm_crtc *possible_crtc;
6520 struct drm_encoder *encoder = &intel_encoder->base;
6521 struct drm_crtc *crtc = NULL;
6522 struct drm_device *dev = encoder->dev;
6523 struct drm_framebuffer *fb;
6524 int i = -1;
6525
6526 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6527 connector->base.id, drm_get_connector_name(connector),
6528 encoder->base.id, drm_get_encoder_name(encoder));
6529
6530 /*
6531 * Algorithm gets a little messy:
6532 *
6533 * - if the connector already has an assigned crtc, use it (but make
6534 * sure it's on first)
6535 *
6536 * - try to find the first unused crtc that can drive this connector,
6537 * and use that if we find one
6538 */
6539
6540 /* See if we already have a CRTC for this connector */
6541 if (encoder->crtc) {
6542 crtc = encoder->crtc;
6543
6544 old->dpms_mode = connector->dpms;
6545 old->load_detect_temp = false;
6546
6547 /* Make sure the crtc and connector are running */
6548 if (connector->dpms != DRM_MODE_DPMS_ON)
6549 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6550
6551 return true;
6552 }
6553
6554 /* Find an unused one (if possible) */
6555 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6556 i++;
6557 if (!(encoder->possible_crtcs & (1 << i)))
6558 continue;
6559 if (!possible_crtc->enabled) {
6560 crtc = possible_crtc;
6561 break;
6562 }
6563 }
6564
6565 /*
6566 * If we didn't find an unused CRTC, don't use any.
6567 */
6568 if (!crtc) {
6569 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6570 return false;
6571 }
6572
6573 intel_encoder->new_crtc = to_intel_crtc(crtc);
6574 to_intel_connector(connector)->new_encoder = intel_encoder;
6575
6576 intel_crtc = to_intel_crtc(crtc);
6577 old->dpms_mode = connector->dpms;
6578 old->load_detect_temp = true;
6579 old->release_fb = NULL;
6580
6581 if (!mode)
6582 mode = &load_detect_mode;
6583
6584 /* We need a framebuffer large enough to accommodate all accesses
6585 * that the plane may generate whilst we perform load detection.
6586 * We can not rely on the fbcon either being present (we get called
6587 * during its initialisation to detect all boot displays, or it may
6588 * not even exist) or that it is large enough to satisfy the
6589 * requested mode.
6590 */
6591 fb = mode_fits_in_fbdev(dev, mode);
6592 if (fb == NULL) {
6593 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6594 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6595 old->release_fb = fb;
6596 } else
6597 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6598 if (IS_ERR(fb)) {
6599 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6600 return false;
6601 }
6602
6603 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6604 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6605 if (old->release_fb)
6606 old->release_fb->funcs->destroy(old->release_fb);
6607 return false;
6608 }
6609
6610 /* let the connector get through one full cycle before testing */
6611 intel_wait_for_vblank(dev, intel_crtc->pipe);
6612 return true;
6613 }
6614
6615 void intel_release_load_detect_pipe(struct drm_connector *connector,
6616 struct intel_load_detect_pipe *old)
6617 {
6618 struct intel_encoder *intel_encoder =
6619 intel_attached_encoder(connector);
6620 struct drm_encoder *encoder = &intel_encoder->base;
6621
6622 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6623 connector->base.id, drm_get_connector_name(connector),
6624 encoder->base.id, drm_get_encoder_name(encoder));
6625
6626 if (old->load_detect_temp) {
6627 struct drm_crtc *crtc = encoder->crtc;
6628
6629 to_intel_connector(connector)->new_encoder = NULL;
6630 intel_encoder->new_crtc = NULL;
6631 intel_set_mode(crtc, NULL, 0, 0, NULL);
6632
6633 if (old->release_fb)
6634 old->release_fb->funcs->destroy(old->release_fb);
6635
6636 return;
6637 }
6638
6639 /* Switch crtc and encoder back off if necessary */
6640 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6641 connector->funcs->dpms(connector, old->dpms_mode);
6642 }
6643
6644 /* Returns the clock of the currently programmed mode of the given pipe. */
6645 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6646 {
6647 struct drm_i915_private *dev_priv = dev->dev_private;
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649 int pipe = intel_crtc->pipe;
6650 u32 dpll = I915_READ(DPLL(pipe));
6651 u32 fp;
6652 intel_clock_t clock;
6653
6654 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6655 fp = I915_READ(FP0(pipe));
6656 else
6657 fp = I915_READ(FP1(pipe));
6658
6659 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6660 if (IS_PINEVIEW(dev)) {
6661 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6662 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6663 } else {
6664 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6665 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6666 }
6667
6668 if (!IS_GEN2(dev)) {
6669 if (IS_PINEVIEW(dev))
6670 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6671 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6672 else
6673 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6674 DPLL_FPA01_P1_POST_DIV_SHIFT);
6675
6676 switch (dpll & DPLL_MODE_MASK) {
6677 case DPLLB_MODE_DAC_SERIAL:
6678 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6679 5 : 10;
6680 break;
6681 case DPLLB_MODE_LVDS:
6682 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6683 7 : 14;
6684 break;
6685 default:
6686 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6687 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6688 return 0;
6689 }
6690
6691 /* XXX: Handle the 100Mhz refclk */
6692 intel_clock(dev, 96000, &clock);
6693 } else {
6694 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6695
6696 if (is_lvds) {
6697 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6698 DPLL_FPA01_P1_POST_DIV_SHIFT);
6699 clock.p2 = 14;
6700
6701 if ((dpll & PLL_REF_INPUT_MASK) ==
6702 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6703 /* XXX: might not be 66MHz */
6704 intel_clock(dev, 66000, &clock);
6705 } else
6706 intel_clock(dev, 48000, &clock);
6707 } else {
6708 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6709 clock.p1 = 2;
6710 else {
6711 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6712 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6713 }
6714 if (dpll & PLL_P2_DIVIDE_BY_4)
6715 clock.p2 = 4;
6716 else
6717 clock.p2 = 2;
6718
6719 intel_clock(dev, 48000, &clock);
6720 }
6721 }
6722
6723 /* XXX: It would be nice to validate the clocks, but we can't reuse
6724 * i830PllIsValid() because it relies on the xf86_config connector
6725 * configuration being accurate, which it isn't necessarily.
6726 */
6727
6728 return clock.dot;
6729 }
6730
6731 /** Returns the currently programmed mode of the given pipe. */
6732 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6733 struct drm_crtc *crtc)
6734 {
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6737 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6738 struct drm_display_mode *mode;
6739 int htot = I915_READ(HTOTAL(cpu_transcoder));
6740 int hsync = I915_READ(HSYNC(cpu_transcoder));
6741 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6742 int vsync = I915_READ(VSYNC(cpu_transcoder));
6743
6744 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6745 if (!mode)
6746 return NULL;
6747
6748 mode->clock = intel_crtc_clock_get(dev, crtc);
6749 mode->hdisplay = (htot & 0xffff) + 1;
6750 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6751 mode->hsync_start = (hsync & 0xffff) + 1;
6752 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6753 mode->vdisplay = (vtot & 0xffff) + 1;
6754 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6755 mode->vsync_start = (vsync & 0xffff) + 1;
6756 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6757
6758 drm_mode_set_name(mode);
6759
6760 return mode;
6761 }
6762
6763 static void intel_increase_pllclock(struct drm_crtc *crtc)
6764 {
6765 struct drm_device *dev = crtc->dev;
6766 drm_i915_private_t *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6768 int pipe = intel_crtc->pipe;
6769 int dpll_reg = DPLL(pipe);
6770 int dpll;
6771
6772 if (HAS_PCH_SPLIT(dev))
6773 return;
6774
6775 if (!dev_priv->lvds_downclock_avail)
6776 return;
6777
6778 dpll = I915_READ(dpll_reg);
6779 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6780 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6781
6782 assert_panel_unlocked(dev_priv, pipe);
6783
6784 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6785 I915_WRITE(dpll_reg, dpll);
6786 intel_wait_for_vblank(dev, pipe);
6787
6788 dpll = I915_READ(dpll_reg);
6789 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6790 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6791 }
6792 }
6793
6794 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6795 {
6796 struct drm_device *dev = crtc->dev;
6797 drm_i915_private_t *dev_priv = dev->dev_private;
6798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6799
6800 if (HAS_PCH_SPLIT(dev))
6801 return;
6802
6803 if (!dev_priv->lvds_downclock_avail)
6804 return;
6805
6806 /*
6807 * Since this is called by a timer, we should never get here in
6808 * the manual case.
6809 */
6810 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6811 int pipe = intel_crtc->pipe;
6812 int dpll_reg = DPLL(pipe);
6813 int dpll;
6814
6815 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6816
6817 assert_panel_unlocked(dev_priv, pipe);
6818
6819 dpll = I915_READ(dpll_reg);
6820 dpll |= DISPLAY_RATE_SELECT_FPA1;
6821 I915_WRITE(dpll_reg, dpll);
6822 intel_wait_for_vblank(dev, pipe);
6823 dpll = I915_READ(dpll_reg);
6824 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6825 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6826 }
6827
6828 }
6829
6830 void intel_mark_busy(struct drm_device *dev)
6831 {
6832 i915_update_gfx_val(dev->dev_private);
6833 }
6834
6835 void intel_mark_idle(struct drm_device *dev)
6836 {
6837 }
6838
6839 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6840 {
6841 struct drm_device *dev = obj->base.dev;
6842 struct drm_crtc *crtc;
6843
6844 if (!i915_powersave)
6845 return;
6846
6847 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6848 if (!crtc->fb)
6849 continue;
6850
6851 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6852 intel_increase_pllclock(crtc);
6853 }
6854 }
6855
6856 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6857 {
6858 struct drm_device *dev = obj->base.dev;
6859 struct drm_crtc *crtc;
6860
6861 if (!i915_powersave)
6862 return;
6863
6864 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6865 if (!crtc->fb)
6866 continue;
6867
6868 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6869 intel_decrease_pllclock(crtc);
6870 }
6871 }
6872
6873 static void intel_crtc_destroy(struct drm_crtc *crtc)
6874 {
6875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6876 struct drm_device *dev = crtc->dev;
6877 struct intel_unpin_work *work;
6878 unsigned long flags;
6879
6880 spin_lock_irqsave(&dev->event_lock, flags);
6881 work = intel_crtc->unpin_work;
6882 intel_crtc->unpin_work = NULL;
6883 spin_unlock_irqrestore(&dev->event_lock, flags);
6884
6885 if (work) {
6886 cancel_work_sync(&work->work);
6887 kfree(work);
6888 }
6889
6890 drm_crtc_cleanup(crtc);
6891
6892 kfree(intel_crtc);
6893 }
6894
6895 static void intel_unpin_work_fn(struct work_struct *__work)
6896 {
6897 struct intel_unpin_work *work =
6898 container_of(__work, struct intel_unpin_work, work);
6899 struct drm_device *dev = work->crtc->dev;
6900
6901 mutex_lock(&dev->struct_mutex);
6902 intel_unpin_fb_obj(work->old_fb_obj);
6903 drm_gem_object_unreference(&work->pending_flip_obj->base);
6904 drm_gem_object_unreference(&work->old_fb_obj->base);
6905
6906 intel_update_fbc(dev);
6907 mutex_unlock(&dev->struct_mutex);
6908
6909 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6910 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6911
6912 kfree(work);
6913 }
6914
6915 static void do_intel_finish_page_flip(struct drm_device *dev,
6916 struct drm_crtc *crtc)
6917 {
6918 drm_i915_private_t *dev_priv = dev->dev_private;
6919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920 struct intel_unpin_work *work;
6921 struct drm_i915_gem_object *obj;
6922 struct drm_pending_vblank_event *e;
6923 struct timeval tvbl;
6924 unsigned long flags;
6925
6926 /* Ignore early vblank irqs */
6927 if (intel_crtc == NULL)
6928 return;
6929
6930 spin_lock_irqsave(&dev->event_lock, flags);
6931 work = intel_crtc->unpin_work;
6932 if (work == NULL || !work->pending) {
6933 spin_unlock_irqrestore(&dev->event_lock, flags);
6934 return;
6935 }
6936
6937 intel_crtc->unpin_work = NULL;
6938
6939 if (work->event) {
6940 e = work->event;
6941 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6942
6943 e->event.tv_sec = tvbl.tv_sec;
6944 e->event.tv_usec = tvbl.tv_usec;
6945
6946 list_add_tail(&e->base.link,
6947 &e->base.file_priv->event_list);
6948 wake_up_interruptible(&e->base.file_priv->event_wait);
6949 }
6950
6951 drm_vblank_put(dev, intel_crtc->pipe);
6952
6953 spin_unlock_irqrestore(&dev->event_lock, flags);
6954
6955 obj = work->old_fb_obj;
6956
6957 atomic_clear_mask(1 << intel_crtc->plane,
6958 &obj->pending_flip.counter);
6959 wake_up(&dev_priv->pending_flip_queue);
6960
6961 queue_work(dev_priv->wq, &work->work);
6962
6963 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6964 }
6965
6966 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6967 {
6968 drm_i915_private_t *dev_priv = dev->dev_private;
6969 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6970
6971 do_intel_finish_page_flip(dev, crtc);
6972 }
6973
6974 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6975 {
6976 drm_i915_private_t *dev_priv = dev->dev_private;
6977 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6978
6979 do_intel_finish_page_flip(dev, crtc);
6980 }
6981
6982 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6983 {
6984 drm_i915_private_t *dev_priv = dev->dev_private;
6985 struct intel_crtc *intel_crtc =
6986 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6987 unsigned long flags;
6988
6989 spin_lock_irqsave(&dev->event_lock, flags);
6990 if (intel_crtc->unpin_work) {
6991 if ((++intel_crtc->unpin_work->pending) > 1)
6992 DRM_ERROR("Prepared flip multiple times\n");
6993 } else {
6994 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6995 }
6996 spin_unlock_irqrestore(&dev->event_lock, flags);
6997 }
6998
6999 static int intel_gen2_queue_flip(struct drm_device *dev,
7000 struct drm_crtc *crtc,
7001 struct drm_framebuffer *fb,
7002 struct drm_i915_gem_object *obj)
7003 {
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 u32 flip_mask;
7007 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7008 int ret;
7009
7010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7011 if (ret)
7012 goto err;
7013
7014 ret = intel_ring_begin(ring, 6);
7015 if (ret)
7016 goto err_unpin;
7017
7018 /* Can't queue multiple flips, so wait for the previous
7019 * one to finish before executing the next.
7020 */
7021 if (intel_crtc->plane)
7022 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7023 else
7024 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7025 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7026 intel_ring_emit(ring, MI_NOOP);
7027 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 intel_ring_emit(ring, fb->pitches[0]);
7030 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7031 intel_ring_emit(ring, 0); /* aux display base address, unused */
7032 intel_ring_advance(ring);
7033 return 0;
7034
7035 err_unpin:
7036 intel_unpin_fb_obj(obj);
7037 err:
7038 return ret;
7039 }
7040
7041 static int intel_gen3_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7045 {
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7048 u32 flip_mask;
7049 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7050 int ret;
7051
7052 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7053 if (ret)
7054 goto err;
7055
7056 ret = intel_ring_begin(ring, 6);
7057 if (ret)
7058 goto err_unpin;
7059
7060 if (intel_crtc->plane)
7061 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7062 else
7063 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7064 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7065 intel_ring_emit(ring, MI_NOOP);
7066 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7068 intel_ring_emit(ring, fb->pitches[0]);
7069 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7070 intel_ring_emit(ring, MI_NOOP);
7071
7072 intel_ring_advance(ring);
7073 return 0;
7074
7075 err_unpin:
7076 intel_unpin_fb_obj(obj);
7077 err:
7078 return ret;
7079 }
7080
7081 static int intel_gen4_queue_flip(struct drm_device *dev,
7082 struct drm_crtc *crtc,
7083 struct drm_framebuffer *fb,
7084 struct drm_i915_gem_object *obj)
7085 {
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088 uint32_t pf, pipesrc;
7089 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7090 int ret;
7091
7092 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7093 if (ret)
7094 goto err;
7095
7096 ret = intel_ring_begin(ring, 4);
7097 if (ret)
7098 goto err_unpin;
7099
7100 /* i965+ uses the linear or tiled offsets from the
7101 * Display Registers (which do not change across a page-flip)
7102 * so we need only reprogram the base address.
7103 */
7104 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106 intel_ring_emit(ring, fb->pitches[0]);
7107 intel_ring_emit(ring,
7108 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7109 obj->tiling_mode);
7110
7111 /* XXX Enabling the panel-fitter across page-flip is so far
7112 * untested on non-native modes, so ignore it for now.
7113 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7114 */
7115 pf = 0;
7116 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7117 intel_ring_emit(ring, pf | pipesrc);
7118 intel_ring_advance(ring);
7119 return 0;
7120
7121 err_unpin:
7122 intel_unpin_fb_obj(obj);
7123 err:
7124 return ret;
7125 }
7126
7127 static int intel_gen6_queue_flip(struct drm_device *dev,
7128 struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_i915_gem_object *obj)
7131 {
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7134 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7135 uint32_t pf, pipesrc;
7136 int ret;
7137
7138 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7139 if (ret)
7140 goto err;
7141
7142 ret = intel_ring_begin(ring, 4);
7143 if (ret)
7144 goto err_unpin;
7145
7146 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7147 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7148 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7149 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7150
7151 /* Contrary to the suggestions in the documentation,
7152 * "Enable Panel Fitter" does not seem to be required when page
7153 * flipping with a non-native mode, and worse causes a normal
7154 * modeset to fail.
7155 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7156 */
7157 pf = 0;
7158 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7159 intel_ring_emit(ring, pf | pipesrc);
7160 intel_ring_advance(ring);
7161 return 0;
7162
7163 err_unpin:
7164 intel_unpin_fb_obj(obj);
7165 err:
7166 return ret;
7167 }
7168
7169 /*
7170 * On gen7 we currently use the blit ring because (in early silicon at least)
7171 * the render ring doesn't give us interrpts for page flip completion, which
7172 * means clients will hang after the first flip is queued. Fortunately the
7173 * blit ring generates interrupts properly, so use it instead.
7174 */
7175 static int intel_gen7_queue_flip(struct drm_device *dev,
7176 struct drm_crtc *crtc,
7177 struct drm_framebuffer *fb,
7178 struct drm_i915_gem_object *obj)
7179 {
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7183 uint32_t plane_bit = 0;
7184 int ret;
7185
7186 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 if (ret)
7188 goto err;
7189
7190 switch(intel_crtc->plane) {
7191 case PLANE_A:
7192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7193 break;
7194 case PLANE_B:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7196 break;
7197 case PLANE_C:
7198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7199 break;
7200 default:
7201 WARN_ONCE(1, "unknown plane in flip command\n");
7202 ret = -ENODEV;
7203 goto err_unpin;
7204 }
7205
7206 ret = intel_ring_begin(ring, 4);
7207 if (ret)
7208 goto err_unpin;
7209
7210 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7211 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7213 intel_ring_emit(ring, (MI_NOOP));
7214 intel_ring_advance(ring);
7215 return 0;
7216
7217 err_unpin:
7218 intel_unpin_fb_obj(obj);
7219 err:
7220 return ret;
7221 }
7222
7223 static int intel_default_queue_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_i915_gem_object *obj)
7227 {
7228 return -ENODEV;
7229 }
7230
7231 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7232 struct drm_framebuffer *fb,
7233 struct drm_pending_vblank_event *event)
7234 {
7235 struct drm_device *dev = crtc->dev;
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237 struct intel_framebuffer *intel_fb;
7238 struct drm_i915_gem_object *obj;
7239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7240 struct intel_unpin_work *work;
7241 unsigned long flags;
7242 int ret;
7243
7244 /* Can't change pixel format via MI display flips. */
7245 if (fb->pixel_format != crtc->fb->pixel_format)
7246 return -EINVAL;
7247
7248 /*
7249 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7250 * Note that pitch changes could also affect these register.
7251 */
7252 if (INTEL_INFO(dev)->gen > 3 &&
7253 (fb->offsets[0] != crtc->fb->offsets[0] ||
7254 fb->pitches[0] != crtc->fb->pitches[0]))
7255 return -EINVAL;
7256
7257 work = kzalloc(sizeof *work, GFP_KERNEL);
7258 if (work == NULL)
7259 return -ENOMEM;
7260
7261 work->event = event;
7262 work->crtc = crtc;
7263 intel_fb = to_intel_framebuffer(crtc->fb);
7264 work->old_fb_obj = intel_fb->obj;
7265 INIT_WORK(&work->work, intel_unpin_work_fn);
7266
7267 ret = drm_vblank_get(dev, intel_crtc->pipe);
7268 if (ret)
7269 goto free_work;
7270
7271 /* We borrow the event spin lock for protecting unpin_work */
7272 spin_lock_irqsave(&dev->event_lock, flags);
7273 if (intel_crtc->unpin_work) {
7274 spin_unlock_irqrestore(&dev->event_lock, flags);
7275 kfree(work);
7276 drm_vblank_put(dev, intel_crtc->pipe);
7277
7278 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7279 return -EBUSY;
7280 }
7281 intel_crtc->unpin_work = work;
7282 spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284 intel_fb = to_intel_framebuffer(fb);
7285 obj = intel_fb->obj;
7286
7287 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7288 flush_workqueue(dev_priv->wq);
7289
7290 ret = i915_mutex_lock_interruptible(dev);
7291 if (ret)
7292 goto cleanup;
7293
7294 /* Reference the objects for the scheduled work. */
7295 drm_gem_object_reference(&work->old_fb_obj->base);
7296 drm_gem_object_reference(&obj->base);
7297
7298 crtc->fb = fb;
7299
7300 work->pending_flip_obj = obj;
7301
7302 work->enable_stall_check = true;
7303
7304 /* Block clients from rendering to the new back buffer until
7305 * the flip occurs and the object is no longer visible.
7306 */
7307 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7308 atomic_inc(&intel_crtc->unpin_work_count);
7309
7310 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7311 if (ret)
7312 goto cleanup_pending;
7313
7314 intel_disable_fbc(dev);
7315 intel_mark_fb_busy(obj);
7316 mutex_unlock(&dev->struct_mutex);
7317
7318 trace_i915_flip_request(intel_crtc->plane, obj);
7319
7320 return 0;
7321
7322 cleanup_pending:
7323 atomic_dec(&intel_crtc->unpin_work_count);
7324 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7325 drm_gem_object_unreference(&work->old_fb_obj->base);
7326 drm_gem_object_unreference(&obj->base);
7327 mutex_unlock(&dev->struct_mutex);
7328
7329 cleanup:
7330 spin_lock_irqsave(&dev->event_lock, flags);
7331 intel_crtc->unpin_work = NULL;
7332 spin_unlock_irqrestore(&dev->event_lock, flags);
7333
7334 drm_vblank_put(dev, intel_crtc->pipe);
7335 free_work:
7336 kfree(work);
7337
7338 return ret;
7339 }
7340
7341 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7342 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7343 .load_lut = intel_crtc_load_lut,
7344 .disable = intel_crtc_noop,
7345 };
7346
7347 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7348 {
7349 struct intel_encoder *other_encoder;
7350 struct drm_crtc *crtc = &encoder->new_crtc->base;
7351
7352 if (WARN_ON(!crtc))
7353 return false;
7354
7355 list_for_each_entry(other_encoder,
7356 &crtc->dev->mode_config.encoder_list,
7357 base.head) {
7358
7359 if (&other_encoder->new_crtc->base != crtc ||
7360 encoder == other_encoder)
7361 continue;
7362 else
7363 return true;
7364 }
7365
7366 return false;
7367 }
7368
7369 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7370 struct drm_crtc *crtc)
7371 {
7372 struct drm_device *dev;
7373 struct drm_crtc *tmp;
7374 int crtc_mask = 1;
7375
7376 WARN(!crtc, "checking null crtc?\n");
7377
7378 dev = crtc->dev;
7379
7380 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7381 if (tmp == crtc)
7382 break;
7383 crtc_mask <<= 1;
7384 }
7385
7386 if (encoder->possible_crtcs & crtc_mask)
7387 return true;
7388 return false;
7389 }
7390
7391 /**
7392 * intel_modeset_update_staged_output_state
7393 *
7394 * Updates the staged output configuration state, e.g. after we've read out the
7395 * current hw state.
7396 */
7397 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7398 {
7399 struct intel_encoder *encoder;
7400 struct intel_connector *connector;
7401
7402 list_for_each_entry(connector, &dev->mode_config.connector_list,
7403 base.head) {
7404 connector->new_encoder =
7405 to_intel_encoder(connector->base.encoder);
7406 }
7407
7408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7409 base.head) {
7410 encoder->new_crtc =
7411 to_intel_crtc(encoder->base.crtc);
7412 }
7413 }
7414
7415 /**
7416 * intel_modeset_commit_output_state
7417 *
7418 * This function copies the stage display pipe configuration to the real one.
7419 */
7420 static void intel_modeset_commit_output_state(struct drm_device *dev)
7421 {
7422 struct intel_encoder *encoder;
7423 struct intel_connector *connector;
7424
7425 list_for_each_entry(connector, &dev->mode_config.connector_list,
7426 base.head) {
7427 connector->base.encoder = &connector->new_encoder->base;
7428 }
7429
7430 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7431 base.head) {
7432 encoder->base.crtc = &encoder->new_crtc->base;
7433 }
7434 }
7435
7436 static struct drm_display_mode *
7437 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7438 struct drm_display_mode *mode)
7439 {
7440 struct drm_device *dev = crtc->dev;
7441 struct drm_display_mode *adjusted_mode;
7442 struct drm_encoder_helper_funcs *encoder_funcs;
7443 struct intel_encoder *encoder;
7444
7445 adjusted_mode = drm_mode_duplicate(dev, mode);
7446 if (!adjusted_mode)
7447 return ERR_PTR(-ENOMEM);
7448
7449 /* Pass our mode to the connectors and the CRTC to give them a chance to
7450 * adjust it according to limitations or connector properties, and also
7451 * a chance to reject the mode entirely.
7452 */
7453 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7454 base.head) {
7455
7456 if (&encoder->new_crtc->base != crtc)
7457 continue;
7458 encoder_funcs = encoder->base.helper_private;
7459 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7460 adjusted_mode))) {
7461 DRM_DEBUG_KMS("Encoder fixup failed\n");
7462 goto fail;
7463 }
7464 }
7465
7466 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7467 DRM_DEBUG_KMS("CRTC fixup failed\n");
7468 goto fail;
7469 }
7470 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7471
7472 return adjusted_mode;
7473 fail:
7474 drm_mode_destroy(dev, adjusted_mode);
7475 return ERR_PTR(-EINVAL);
7476 }
7477
7478 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7479 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7480 static void
7481 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7482 unsigned *prepare_pipes, unsigned *disable_pipes)
7483 {
7484 struct intel_crtc *intel_crtc;
7485 struct drm_device *dev = crtc->dev;
7486 struct intel_encoder *encoder;
7487 struct intel_connector *connector;
7488 struct drm_crtc *tmp_crtc;
7489
7490 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7491
7492 /* Check which crtcs have changed outputs connected to them, these need
7493 * to be part of the prepare_pipes mask. We don't (yet) support global
7494 * modeset across multiple crtcs, so modeset_pipes will only have one
7495 * bit set at most. */
7496 list_for_each_entry(connector, &dev->mode_config.connector_list,
7497 base.head) {
7498 if (connector->base.encoder == &connector->new_encoder->base)
7499 continue;
7500
7501 if (connector->base.encoder) {
7502 tmp_crtc = connector->base.encoder->crtc;
7503
7504 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7505 }
7506
7507 if (connector->new_encoder)
7508 *prepare_pipes |=
7509 1 << connector->new_encoder->new_crtc->pipe;
7510 }
7511
7512 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7513 base.head) {
7514 if (encoder->base.crtc == &encoder->new_crtc->base)
7515 continue;
7516
7517 if (encoder->base.crtc) {
7518 tmp_crtc = encoder->base.crtc;
7519
7520 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7521 }
7522
7523 if (encoder->new_crtc)
7524 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7525 }
7526
7527 /* Check for any pipes that will be fully disabled ... */
7528 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7529 base.head) {
7530 bool used = false;
7531
7532 /* Don't try to disable disabled crtcs. */
7533 if (!intel_crtc->base.enabled)
7534 continue;
7535
7536 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7537 base.head) {
7538 if (encoder->new_crtc == intel_crtc)
7539 used = true;
7540 }
7541
7542 if (!used)
7543 *disable_pipes |= 1 << intel_crtc->pipe;
7544 }
7545
7546
7547 /* set_mode is also used to update properties on life display pipes. */
7548 intel_crtc = to_intel_crtc(crtc);
7549 if (crtc->enabled)
7550 *prepare_pipes |= 1 << intel_crtc->pipe;
7551
7552 /* We only support modeset on one single crtc, hence we need to do that
7553 * only for the passed in crtc iff we change anything else than just
7554 * disable crtcs.
7555 *
7556 * This is actually not true, to be fully compatible with the old crtc
7557 * helper we automatically disable _any_ output (i.e. doesn't need to be
7558 * connected to the crtc we're modesetting on) if it's disconnected.
7559 * Which is a rather nutty api (since changed the output configuration
7560 * without userspace's explicit request can lead to confusion), but
7561 * alas. Hence we currently need to modeset on all pipes we prepare. */
7562 if (*prepare_pipes)
7563 *modeset_pipes = *prepare_pipes;
7564
7565 /* ... and mask these out. */
7566 *modeset_pipes &= ~(*disable_pipes);
7567 *prepare_pipes &= ~(*disable_pipes);
7568 }
7569
7570 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7571 {
7572 struct drm_encoder *encoder;
7573 struct drm_device *dev = crtc->dev;
7574
7575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7576 if (encoder->crtc == crtc)
7577 return true;
7578
7579 return false;
7580 }
7581
7582 static void
7583 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7584 {
7585 struct intel_encoder *intel_encoder;
7586 struct intel_crtc *intel_crtc;
7587 struct drm_connector *connector;
7588
7589 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7590 base.head) {
7591 if (!intel_encoder->base.crtc)
7592 continue;
7593
7594 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7595
7596 if (prepare_pipes & (1 << intel_crtc->pipe))
7597 intel_encoder->connectors_active = false;
7598 }
7599
7600 intel_modeset_commit_output_state(dev);
7601
7602 /* Update computed state. */
7603 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7604 base.head) {
7605 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7606 }
7607
7608 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7609 if (!connector->encoder || !connector->encoder->crtc)
7610 continue;
7611
7612 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7613
7614 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7615 struct drm_property *dpms_property =
7616 dev->mode_config.dpms_property;
7617
7618 connector->dpms = DRM_MODE_DPMS_ON;
7619 drm_connector_property_set_value(connector,
7620 dpms_property,
7621 DRM_MODE_DPMS_ON);
7622
7623 intel_encoder = to_intel_encoder(connector->encoder);
7624 intel_encoder->connectors_active = true;
7625 }
7626 }
7627
7628 }
7629
7630 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7631 list_for_each_entry((intel_crtc), \
7632 &(dev)->mode_config.crtc_list, \
7633 base.head) \
7634 if (mask & (1 <<(intel_crtc)->pipe)) \
7635
7636 void
7637 intel_modeset_check_state(struct drm_device *dev)
7638 {
7639 struct intel_crtc *crtc;
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
7642
7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 base.head) {
7645 /* This also checks the encoder/connector hw state with the
7646 * ->get_hw_state callbacks. */
7647 intel_connector_check_state(connector);
7648
7649 WARN(&connector->new_encoder->base != connector->base.encoder,
7650 "connector's staged encoder doesn't match current encoder\n");
7651 }
7652
7653 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7654 base.head) {
7655 bool enabled = false;
7656 bool active = false;
7657 enum pipe pipe, tracked_pipe;
7658
7659 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7660 encoder->base.base.id,
7661 drm_get_encoder_name(&encoder->base));
7662
7663 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7664 "encoder's stage crtc doesn't match current crtc\n");
7665 WARN(encoder->connectors_active && !encoder->base.crtc,
7666 "encoder's active_connectors set, but no crtc\n");
7667
7668 list_for_each_entry(connector, &dev->mode_config.connector_list,
7669 base.head) {
7670 if (connector->base.encoder != &encoder->base)
7671 continue;
7672 enabled = true;
7673 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7674 active = true;
7675 }
7676 WARN(!!encoder->base.crtc != enabled,
7677 "encoder's enabled state mismatch "
7678 "(expected %i, found %i)\n",
7679 !!encoder->base.crtc, enabled);
7680 WARN(active && !encoder->base.crtc,
7681 "active encoder with no crtc\n");
7682
7683 WARN(encoder->connectors_active != active,
7684 "encoder's computed active state doesn't match tracked active state "
7685 "(expected %i, found %i)\n", active, encoder->connectors_active);
7686
7687 active = encoder->get_hw_state(encoder, &pipe);
7688 WARN(active != encoder->connectors_active,
7689 "encoder's hw state doesn't match sw tracking "
7690 "(expected %i, found %i)\n",
7691 encoder->connectors_active, active);
7692
7693 if (!encoder->base.crtc)
7694 continue;
7695
7696 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7697 WARN(active && pipe != tracked_pipe,
7698 "active encoder's pipe doesn't match"
7699 "(expected %i, found %i)\n",
7700 tracked_pipe, pipe);
7701
7702 }
7703
7704 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7705 base.head) {
7706 bool enabled = false;
7707 bool active = false;
7708
7709 DRM_DEBUG_KMS("[CRTC:%d]\n",
7710 crtc->base.base.id);
7711
7712 WARN(crtc->active && !crtc->base.enabled,
7713 "active crtc, but not enabled in sw tracking\n");
7714
7715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7716 base.head) {
7717 if (encoder->base.crtc != &crtc->base)
7718 continue;
7719 enabled = true;
7720 if (encoder->connectors_active)
7721 active = true;
7722 }
7723 WARN(active != crtc->active,
7724 "crtc's computed active state doesn't match tracked active state "
7725 "(expected %i, found %i)\n", active, crtc->active);
7726 WARN(enabled != crtc->base.enabled,
7727 "crtc's computed enabled state doesn't match tracked enabled state "
7728 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7729
7730 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7731 }
7732 }
7733
7734 bool intel_set_mode(struct drm_crtc *crtc,
7735 struct drm_display_mode *mode,
7736 int x, int y, struct drm_framebuffer *fb)
7737 {
7738 struct drm_device *dev = crtc->dev;
7739 drm_i915_private_t *dev_priv = dev->dev_private;
7740 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7741 struct intel_crtc *intel_crtc;
7742 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7743 bool ret = true;
7744
7745 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7746 &prepare_pipes, &disable_pipes);
7747
7748 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7749 modeset_pipes, prepare_pipes, disable_pipes);
7750
7751 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7752 intel_crtc_disable(&intel_crtc->base);
7753
7754 saved_hwmode = crtc->hwmode;
7755 saved_mode = crtc->mode;
7756
7757 /* Hack: Because we don't (yet) support global modeset on multiple
7758 * crtcs, we don't keep track of the new mode for more than one crtc.
7759 * Hence simply check whether any bit is set in modeset_pipes in all the
7760 * pieces of code that are not yet converted to deal with mutliple crtcs
7761 * changing their mode at the same time. */
7762 adjusted_mode = NULL;
7763 if (modeset_pipes) {
7764 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7765 if (IS_ERR(adjusted_mode)) {
7766 return false;
7767 }
7768 }
7769
7770 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7771 if (intel_crtc->base.enabled)
7772 dev_priv->display.crtc_disable(&intel_crtc->base);
7773 }
7774
7775 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7776 * to set it here already despite that we pass it down the callchain.
7777 */
7778 if (modeset_pipes)
7779 crtc->mode = *mode;
7780
7781 /* Only after disabling all output pipelines that will be changed can we
7782 * update the the output configuration. */
7783 intel_modeset_update_state(dev, prepare_pipes);
7784
7785 if (dev_priv->display.modeset_global_resources)
7786 dev_priv->display.modeset_global_resources(dev);
7787
7788 /* Set up the DPLL and any encoders state that needs to adjust or depend
7789 * on the DPLL.
7790 */
7791 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7792 ret = !intel_crtc_mode_set(&intel_crtc->base,
7793 mode, adjusted_mode,
7794 x, y, fb);
7795 if (!ret)
7796 goto done;
7797 }
7798
7799 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7800 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7801 dev_priv->display.crtc_enable(&intel_crtc->base);
7802
7803 if (modeset_pipes) {
7804 /* Store real post-adjustment hardware mode. */
7805 crtc->hwmode = *adjusted_mode;
7806
7807 /* Calculate and store various constants which
7808 * are later needed by vblank and swap-completion
7809 * timestamping. They are derived from true hwmode.
7810 */
7811 drm_calc_timestamping_constants(crtc);
7812 }
7813
7814 /* FIXME: add subpixel order */
7815 done:
7816 drm_mode_destroy(dev, adjusted_mode);
7817 if (!ret && crtc->enabled) {
7818 crtc->hwmode = saved_hwmode;
7819 crtc->mode = saved_mode;
7820 } else {
7821 intel_modeset_check_state(dev);
7822 }
7823
7824 return ret;
7825 }
7826
7827 #undef for_each_intel_crtc_masked
7828
7829 static void intel_set_config_free(struct intel_set_config *config)
7830 {
7831 if (!config)
7832 return;
7833
7834 kfree(config->save_connector_encoders);
7835 kfree(config->save_encoder_crtcs);
7836 kfree(config);
7837 }
7838
7839 static int intel_set_config_save_state(struct drm_device *dev,
7840 struct intel_set_config *config)
7841 {
7842 struct drm_encoder *encoder;
7843 struct drm_connector *connector;
7844 int count;
7845
7846 config->save_encoder_crtcs =
7847 kcalloc(dev->mode_config.num_encoder,
7848 sizeof(struct drm_crtc *), GFP_KERNEL);
7849 if (!config->save_encoder_crtcs)
7850 return -ENOMEM;
7851
7852 config->save_connector_encoders =
7853 kcalloc(dev->mode_config.num_connector,
7854 sizeof(struct drm_encoder *), GFP_KERNEL);
7855 if (!config->save_connector_encoders)
7856 return -ENOMEM;
7857
7858 /* Copy data. Note that driver private data is not affected.
7859 * Should anything bad happen only the expected state is
7860 * restored, not the drivers personal bookkeeping.
7861 */
7862 count = 0;
7863 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7864 config->save_encoder_crtcs[count++] = encoder->crtc;
7865 }
7866
7867 count = 0;
7868 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7869 config->save_connector_encoders[count++] = connector->encoder;
7870 }
7871
7872 return 0;
7873 }
7874
7875 static void intel_set_config_restore_state(struct drm_device *dev,
7876 struct intel_set_config *config)
7877 {
7878 struct intel_encoder *encoder;
7879 struct intel_connector *connector;
7880 int count;
7881
7882 count = 0;
7883 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7884 encoder->new_crtc =
7885 to_intel_crtc(config->save_encoder_crtcs[count++]);
7886 }
7887
7888 count = 0;
7889 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7890 connector->new_encoder =
7891 to_intel_encoder(config->save_connector_encoders[count++]);
7892 }
7893 }
7894
7895 static void
7896 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7897 struct intel_set_config *config)
7898 {
7899
7900 /* We should be able to check here if the fb has the same properties
7901 * and then just flip_or_move it */
7902 if (set->crtc->fb != set->fb) {
7903 /* If we have no fb then treat it as a full mode set */
7904 if (set->crtc->fb == NULL) {
7905 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7906 config->mode_changed = true;
7907 } else if (set->fb == NULL) {
7908 config->mode_changed = true;
7909 } else if (set->fb->depth != set->crtc->fb->depth) {
7910 config->mode_changed = true;
7911 } else if (set->fb->bits_per_pixel !=
7912 set->crtc->fb->bits_per_pixel) {
7913 config->mode_changed = true;
7914 } else
7915 config->fb_changed = true;
7916 }
7917
7918 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7919 config->fb_changed = true;
7920
7921 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7922 DRM_DEBUG_KMS("modes are different, full mode set\n");
7923 drm_mode_debug_printmodeline(&set->crtc->mode);
7924 drm_mode_debug_printmodeline(set->mode);
7925 config->mode_changed = true;
7926 }
7927 }
7928
7929 static int
7930 intel_modeset_stage_output_state(struct drm_device *dev,
7931 struct drm_mode_set *set,
7932 struct intel_set_config *config)
7933 {
7934 struct drm_crtc *new_crtc;
7935 struct intel_connector *connector;
7936 struct intel_encoder *encoder;
7937 int count, ro;
7938
7939 /* The upper layers ensure that we either disabl a crtc or have a list
7940 * of connectors. For paranoia, double-check this. */
7941 WARN_ON(!set->fb && (set->num_connectors != 0));
7942 WARN_ON(set->fb && (set->num_connectors == 0));
7943
7944 count = 0;
7945 list_for_each_entry(connector, &dev->mode_config.connector_list,
7946 base.head) {
7947 /* Otherwise traverse passed in connector list and get encoders
7948 * for them. */
7949 for (ro = 0; ro < set->num_connectors; ro++) {
7950 if (set->connectors[ro] == &connector->base) {
7951 connector->new_encoder = connector->encoder;
7952 break;
7953 }
7954 }
7955
7956 /* If we disable the crtc, disable all its connectors. Also, if
7957 * the connector is on the changing crtc but not on the new
7958 * connector list, disable it. */
7959 if ((!set->fb || ro == set->num_connectors) &&
7960 connector->base.encoder &&
7961 connector->base.encoder->crtc == set->crtc) {
7962 connector->new_encoder = NULL;
7963
7964 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7965 connector->base.base.id,
7966 drm_get_connector_name(&connector->base));
7967 }
7968
7969
7970 if (&connector->new_encoder->base != connector->base.encoder) {
7971 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7972 config->mode_changed = true;
7973 }
7974
7975 /* Disable all disconnected encoders. */
7976 if (connector->base.status == connector_status_disconnected)
7977 connector->new_encoder = NULL;
7978 }
7979 /* connector->new_encoder is now updated for all connectors. */
7980
7981 /* Update crtc of enabled connectors. */
7982 count = 0;
7983 list_for_each_entry(connector, &dev->mode_config.connector_list,
7984 base.head) {
7985 if (!connector->new_encoder)
7986 continue;
7987
7988 new_crtc = connector->new_encoder->base.crtc;
7989
7990 for (ro = 0; ro < set->num_connectors; ro++) {
7991 if (set->connectors[ro] == &connector->base)
7992 new_crtc = set->crtc;
7993 }
7994
7995 /* Make sure the new CRTC will work with the encoder */
7996 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7997 new_crtc)) {
7998 return -EINVAL;
7999 }
8000 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8001
8002 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8003 connector->base.base.id,
8004 drm_get_connector_name(&connector->base),
8005 new_crtc->base.id);
8006 }
8007
8008 /* Check for any encoders that needs to be disabled. */
8009 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8010 base.head) {
8011 list_for_each_entry(connector,
8012 &dev->mode_config.connector_list,
8013 base.head) {
8014 if (connector->new_encoder == encoder) {
8015 WARN_ON(!connector->new_encoder->new_crtc);
8016
8017 goto next_encoder;
8018 }
8019 }
8020 encoder->new_crtc = NULL;
8021 next_encoder:
8022 /* Only now check for crtc changes so we don't miss encoders
8023 * that will be disabled. */
8024 if (&encoder->new_crtc->base != encoder->base.crtc) {
8025 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8026 config->mode_changed = true;
8027 }
8028 }
8029 /* Now we've also updated encoder->new_crtc for all encoders. */
8030
8031 return 0;
8032 }
8033
8034 static int intel_crtc_set_config(struct drm_mode_set *set)
8035 {
8036 struct drm_device *dev;
8037 struct drm_mode_set save_set;
8038 struct intel_set_config *config;
8039 int ret;
8040
8041 BUG_ON(!set);
8042 BUG_ON(!set->crtc);
8043 BUG_ON(!set->crtc->helper_private);
8044
8045 if (!set->mode)
8046 set->fb = NULL;
8047
8048 /* The fb helper likes to play gross jokes with ->mode_set_config.
8049 * Unfortunately the crtc helper doesn't do much at all for this case,
8050 * so we have to cope with this madness until the fb helper is fixed up. */
8051 if (set->fb && set->num_connectors == 0)
8052 return 0;
8053
8054 if (set->fb) {
8055 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8056 set->crtc->base.id, set->fb->base.id,
8057 (int)set->num_connectors, set->x, set->y);
8058 } else {
8059 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8060 }
8061
8062 dev = set->crtc->dev;
8063
8064 ret = -ENOMEM;
8065 config = kzalloc(sizeof(*config), GFP_KERNEL);
8066 if (!config)
8067 goto out_config;
8068
8069 ret = intel_set_config_save_state(dev, config);
8070 if (ret)
8071 goto out_config;
8072
8073 save_set.crtc = set->crtc;
8074 save_set.mode = &set->crtc->mode;
8075 save_set.x = set->crtc->x;
8076 save_set.y = set->crtc->y;
8077 save_set.fb = set->crtc->fb;
8078
8079 /* Compute whether we need a full modeset, only an fb base update or no
8080 * change at all. In the future we might also check whether only the
8081 * mode changed, e.g. for LVDS where we only change the panel fitter in
8082 * such cases. */
8083 intel_set_config_compute_mode_changes(set, config);
8084
8085 ret = intel_modeset_stage_output_state(dev, set, config);
8086 if (ret)
8087 goto fail;
8088
8089 if (config->mode_changed) {
8090 if (set->mode) {
8091 DRM_DEBUG_KMS("attempting to set mode from"
8092 " userspace\n");
8093 drm_mode_debug_printmodeline(set->mode);
8094 }
8095
8096 if (!intel_set_mode(set->crtc, set->mode,
8097 set->x, set->y, set->fb)) {
8098 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8099 set->crtc->base.id);
8100 ret = -EINVAL;
8101 goto fail;
8102 }
8103 } else if (config->fb_changed) {
8104 ret = intel_pipe_set_base(set->crtc,
8105 set->x, set->y, set->fb);
8106 }
8107
8108 intel_set_config_free(config);
8109
8110 return 0;
8111
8112 fail:
8113 intel_set_config_restore_state(dev, config);
8114
8115 /* Try to restore the config */
8116 if (config->mode_changed &&
8117 !intel_set_mode(save_set.crtc, save_set.mode,
8118 save_set.x, save_set.y, save_set.fb))
8119 DRM_ERROR("failed to restore config after modeset failure\n");
8120
8121 out_config:
8122 intel_set_config_free(config);
8123 return ret;
8124 }
8125
8126 static const struct drm_crtc_funcs intel_crtc_funcs = {
8127 .cursor_set = intel_crtc_cursor_set,
8128 .cursor_move = intel_crtc_cursor_move,
8129 .gamma_set = intel_crtc_gamma_set,
8130 .set_config = intel_crtc_set_config,
8131 .destroy = intel_crtc_destroy,
8132 .page_flip = intel_crtc_page_flip,
8133 };
8134
8135 static void intel_cpu_pll_init(struct drm_device *dev)
8136 {
8137 if (IS_HASWELL(dev))
8138 intel_ddi_pll_init(dev);
8139 }
8140
8141 static void intel_pch_pll_init(struct drm_device *dev)
8142 {
8143 drm_i915_private_t *dev_priv = dev->dev_private;
8144 int i;
8145
8146 if (dev_priv->num_pch_pll == 0) {
8147 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8148 return;
8149 }
8150
8151 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8152 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8153 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8154 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8155 }
8156 }
8157
8158 static void intel_crtc_init(struct drm_device *dev, int pipe)
8159 {
8160 drm_i915_private_t *dev_priv = dev->dev_private;
8161 struct intel_crtc *intel_crtc;
8162 int i;
8163
8164 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8165 if (intel_crtc == NULL)
8166 return;
8167
8168 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8169
8170 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8171 for (i = 0; i < 256; i++) {
8172 intel_crtc->lut_r[i] = i;
8173 intel_crtc->lut_g[i] = i;
8174 intel_crtc->lut_b[i] = i;
8175 }
8176
8177 /* Swap pipes & planes for FBC on pre-965 */
8178 intel_crtc->pipe = pipe;
8179 intel_crtc->plane = pipe;
8180 intel_crtc->cpu_transcoder = pipe;
8181 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8182 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8183 intel_crtc->plane = !pipe;
8184 }
8185
8186 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8187 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8188 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8189 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8190
8191 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8192
8193 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8194 }
8195
8196 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8197 struct drm_file *file)
8198 {
8199 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8200 struct drm_mode_object *drmmode_obj;
8201 struct intel_crtc *crtc;
8202
8203 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8204 return -ENODEV;
8205
8206 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8207 DRM_MODE_OBJECT_CRTC);
8208
8209 if (!drmmode_obj) {
8210 DRM_ERROR("no such CRTC id\n");
8211 return -EINVAL;
8212 }
8213
8214 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8215 pipe_from_crtc_id->pipe = crtc->pipe;
8216
8217 return 0;
8218 }
8219
8220 static int intel_encoder_clones(struct intel_encoder *encoder)
8221 {
8222 struct drm_device *dev = encoder->base.dev;
8223 struct intel_encoder *source_encoder;
8224 int index_mask = 0;
8225 int entry = 0;
8226
8227 list_for_each_entry(source_encoder,
8228 &dev->mode_config.encoder_list, base.head) {
8229
8230 if (encoder == source_encoder)
8231 index_mask |= (1 << entry);
8232
8233 /* Intel hw has only one MUX where enocoders could be cloned. */
8234 if (encoder->cloneable && source_encoder->cloneable)
8235 index_mask |= (1 << entry);
8236
8237 entry++;
8238 }
8239
8240 return index_mask;
8241 }
8242
8243 static bool has_edp_a(struct drm_device *dev)
8244 {
8245 struct drm_i915_private *dev_priv = dev->dev_private;
8246
8247 if (!IS_MOBILE(dev))
8248 return false;
8249
8250 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8251 return false;
8252
8253 if (IS_GEN5(dev) &&
8254 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8255 return false;
8256
8257 return true;
8258 }
8259
8260 static void intel_setup_outputs(struct drm_device *dev)
8261 {
8262 struct drm_i915_private *dev_priv = dev->dev_private;
8263 struct intel_encoder *encoder;
8264 bool dpd_is_edp = false;
8265 bool has_lvds;
8266
8267 has_lvds = intel_lvds_init(dev);
8268 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8269 /* disable the panel fitter on everything but LVDS */
8270 I915_WRITE(PFIT_CONTROL, 0);
8271 }
8272
8273 intel_crt_init(dev);
8274
8275 if (IS_HASWELL(dev)) {
8276 int found;
8277
8278 /* Haswell uses DDI functions to detect digital outputs */
8279 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8280 /* DDI A only supports eDP */
8281 if (found)
8282 intel_ddi_init(dev, PORT_A);
8283
8284 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8285 * register */
8286 found = I915_READ(SFUSE_STRAP);
8287
8288 if (found & SFUSE_STRAP_DDIB_DETECTED)
8289 intel_ddi_init(dev, PORT_B);
8290 if (found & SFUSE_STRAP_DDIC_DETECTED)
8291 intel_ddi_init(dev, PORT_C);
8292 if (found & SFUSE_STRAP_DDID_DETECTED)
8293 intel_ddi_init(dev, PORT_D);
8294 } else if (HAS_PCH_SPLIT(dev)) {
8295 int found;
8296 dpd_is_edp = intel_dpd_is_edp(dev);
8297
8298 if (has_edp_a(dev))
8299 intel_dp_init(dev, DP_A, PORT_A);
8300
8301 if (I915_READ(HDMIB) & PORT_DETECTED) {
8302 /* PCH SDVOB multiplex with HDMIB */
8303 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8304 if (!found)
8305 intel_hdmi_init(dev, HDMIB, PORT_B);
8306 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8307 intel_dp_init(dev, PCH_DP_B, PORT_B);
8308 }
8309
8310 if (I915_READ(HDMIC) & PORT_DETECTED)
8311 intel_hdmi_init(dev, HDMIC, PORT_C);
8312
8313 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8314 intel_hdmi_init(dev, HDMID, PORT_D);
8315
8316 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8317 intel_dp_init(dev, PCH_DP_C, PORT_C);
8318
8319 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8320 intel_dp_init(dev, PCH_DP_D, PORT_D);
8321 } else if (IS_VALLEYVIEW(dev)) {
8322 int found;
8323
8324 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8325 if (I915_READ(DP_C) & DP_DETECTED)
8326 intel_dp_init(dev, DP_C, PORT_C);
8327
8328 if (I915_READ(SDVOB) & PORT_DETECTED) {
8329 /* SDVOB multiplex with HDMIB */
8330 found = intel_sdvo_init(dev, SDVOB, true);
8331 if (!found)
8332 intel_hdmi_init(dev, SDVOB, PORT_B);
8333 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8334 intel_dp_init(dev, DP_B, PORT_B);
8335 }
8336
8337 if (I915_READ(SDVOC) & PORT_DETECTED)
8338 intel_hdmi_init(dev, SDVOC, PORT_C);
8339
8340 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8341 bool found = false;
8342
8343 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8344 DRM_DEBUG_KMS("probing SDVOB\n");
8345 found = intel_sdvo_init(dev, SDVOB, true);
8346 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8347 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8348 intel_hdmi_init(dev, SDVOB, PORT_B);
8349 }
8350
8351 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8352 DRM_DEBUG_KMS("probing DP_B\n");
8353 intel_dp_init(dev, DP_B, PORT_B);
8354 }
8355 }
8356
8357 /* Before G4X SDVOC doesn't have its own detect register */
8358
8359 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8360 DRM_DEBUG_KMS("probing SDVOC\n");
8361 found = intel_sdvo_init(dev, SDVOC, false);
8362 }
8363
8364 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8365
8366 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8367 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8368 intel_hdmi_init(dev, SDVOC, PORT_C);
8369 }
8370 if (SUPPORTS_INTEGRATED_DP(dev)) {
8371 DRM_DEBUG_KMS("probing DP_C\n");
8372 intel_dp_init(dev, DP_C, PORT_C);
8373 }
8374 }
8375
8376 if (SUPPORTS_INTEGRATED_DP(dev) &&
8377 (I915_READ(DP_D) & DP_DETECTED)) {
8378 DRM_DEBUG_KMS("probing DP_D\n");
8379 intel_dp_init(dev, DP_D, PORT_D);
8380 }
8381 } else if (IS_GEN2(dev))
8382 intel_dvo_init(dev);
8383
8384 if (SUPPORTS_TV(dev))
8385 intel_tv_init(dev);
8386
8387 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8388 encoder->base.possible_crtcs = encoder->crtc_mask;
8389 encoder->base.possible_clones =
8390 intel_encoder_clones(encoder);
8391 }
8392
8393 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8394 ironlake_init_pch_refclk(dev);
8395
8396 drm_helper_move_panel_connectors_to_head(dev);
8397 }
8398
8399 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8400 {
8401 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8402
8403 drm_framebuffer_cleanup(fb);
8404 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8405
8406 kfree(intel_fb);
8407 }
8408
8409 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8410 struct drm_file *file,
8411 unsigned int *handle)
8412 {
8413 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8414 struct drm_i915_gem_object *obj = intel_fb->obj;
8415
8416 return drm_gem_handle_create(file, &obj->base, handle);
8417 }
8418
8419 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8420 .destroy = intel_user_framebuffer_destroy,
8421 .create_handle = intel_user_framebuffer_create_handle,
8422 };
8423
8424 int intel_framebuffer_init(struct drm_device *dev,
8425 struct intel_framebuffer *intel_fb,
8426 struct drm_mode_fb_cmd2 *mode_cmd,
8427 struct drm_i915_gem_object *obj)
8428 {
8429 int ret;
8430
8431 if (obj->tiling_mode == I915_TILING_Y)
8432 return -EINVAL;
8433
8434 if (mode_cmd->pitches[0] & 63)
8435 return -EINVAL;
8436
8437 /* FIXME <= Gen4 stride limits are bit unclear */
8438 if (mode_cmd->pitches[0] > 32768)
8439 return -EINVAL;
8440
8441 if (obj->tiling_mode != I915_TILING_NONE &&
8442 mode_cmd->pitches[0] != obj->stride)
8443 return -EINVAL;
8444
8445 /* Reject formats not supported by any plane early. */
8446 switch (mode_cmd->pixel_format) {
8447 case DRM_FORMAT_C8:
8448 case DRM_FORMAT_RGB565:
8449 case DRM_FORMAT_XRGB8888:
8450 case DRM_FORMAT_ARGB8888:
8451 break;
8452 case DRM_FORMAT_XRGB1555:
8453 case DRM_FORMAT_ARGB1555:
8454 if (INTEL_INFO(dev)->gen > 3)
8455 return -EINVAL;
8456 break;
8457 case DRM_FORMAT_XBGR8888:
8458 case DRM_FORMAT_ABGR8888:
8459 case DRM_FORMAT_XRGB2101010:
8460 case DRM_FORMAT_ARGB2101010:
8461 case DRM_FORMAT_XBGR2101010:
8462 case DRM_FORMAT_ABGR2101010:
8463 if (INTEL_INFO(dev)->gen < 4)
8464 return -EINVAL;
8465 break;
8466 case DRM_FORMAT_YUYV:
8467 case DRM_FORMAT_UYVY:
8468 case DRM_FORMAT_YVYU:
8469 case DRM_FORMAT_VYUY:
8470 if (INTEL_INFO(dev)->gen < 6)
8471 return -EINVAL;
8472 break;
8473 default:
8474 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8475 return -EINVAL;
8476 }
8477
8478 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8479 if (mode_cmd->offsets[0] != 0)
8480 return -EINVAL;
8481
8482 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8483 if (ret) {
8484 DRM_ERROR("framebuffer init failed %d\n", ret);
8485 return ret;
8486 }
8487
8488 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8489 intel_fb->obj = obj;
8490 return 0;
8491 }
8492
8493 static struct drm_framebuffer *
8494 intel_user_framebuffer_create(struct drm_device *dev,
8495 struct drm_file *filp,
8496 struct drm_mode_fb_cmd2 *mode_cmd)
8497 {
8498 struct drm_i915_gem_object *obj;
8499
8500 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8501 mode_cmd->handles[0]));
8502 if (&obj->base == NULL)
8503 return ERR_PTR(-ENOENT);
8504
8505 return intel_framebuffer_create(dev, mode_cmd, obj);
8506 }
8507
8508 static const struct drm_mode_config_funcs intel_mode_funcs = {
8509 .fb_create = intel_user_framebuffer_create,
8510 .output_poll_changed = intel_fb_output_poll_changed,
8511 };
8512
8513 /* Set up chip specific display functions */
8514 static void intel_init_display(struct drm_device *dev)
8515 {
8516 struct drm_i915_private *dev_priv = dev->dev_private;
8517
8518 /* We always want a DPMS function */
8519 if (IS_HASWELL(dev)) {
8520 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8521 dev_priv->display.crtc_enable = haswell_crtc_enable;
8522 dev_priv->display.crtc_disable = haswell_crtc_disable;
8523 dev_priv->display.off = haswell_crtc_off;
8524 dev_priv->display.update_plane = ironlake_update_plane;
8525 } else if (HAS_PCH_SPLIT(dev)) {
8526 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8527 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8528 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8529 dev_priv->display.off = ironlake_crtc_off;
8530 dev_priv->display.update_plane = ironlake_update_plane;
8531 } else {
8532 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8533 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8534 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8535 dev_priv->display.off = i9xx_crtc_off;
8536 dev_priv->display.update_plane = i9xx_update_plane;
8537 }
8538
8539 /* Returns the core display clock speed */
8540 if (IS_VALLEYVIEW(dev))
8541 dev_priv->display.get_display_clock_speed =
8542 valleyview_get_display_clock_speed;
8543 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8544 dev_priv->display.get_display_clock_speed =
8545 i945_get_display_clock_speed;
8546 else if (IS_I915G(dev))
8547 dev_priv->display.get_display_clock_speed =
8548 i915_get_display_clock_speed;
8549 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8550 dev_priv->display.get_display_clock_speed =
8551 i9xx_misc_get_display_clock_speed;
8552 else if (IS_I915GM(dev))
8553 dev_priv->display.get_display_clock_speed =
8554 i915gm_get_display_clock_speed;
8555 else if (IS_I865G(dev))
8556 dev_priv->display.get_display_clock_speed =
8557 i865_get_display_clock_speed;
8558 else if (IS_I85X(dev))
8559 dev_priv->display.get_display_clock_speed =
8560 i855_get_display_clock_speed;
8561 else /* 852, 830 */
8562 dev_priv->display.get_display_clock_speed =
8563 i830_get_display_clock_speed;
8564
8565 if (HAS_PCH_SPLIT(dev)) {
8566 if (IS_GEN5(dev)) {
8567 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8568 dev_priv->display.write_eld = ironlake_write_eld;
8569 } else if (IS_GEN6(dev)) {
8570 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8571 dev_priv->display.write_eld = ironlake_write_eld;
8572 } else if (IS_IVYBRIDGE(dev)) {
8573 /* FIXME: detect B0+ stepping and use auto training */
8574 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8575 dev_priv->display.write_eld = ironlake_write_eld;
8576 dev_priv->display.modeset_global_resources =
8577 ivb_modeset_global_resources;
8578 } else if (IS_HASWELL(dev)) {
8579 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8580 dev_priv->display.write_eld = haswell_write_eld;
8581 } else
8582 dev_priv->display.update_wm = NULL;
8583 } else if (IS_G4X(dev)) {
8584 dev_priv->display.write_eld = g4x_write_eld;
8585 }
8586
8587 /* Default just returns -ENODEV to indicate unsupported */
8588 dev_priv->display.queue_flip = intel_default_queue_flip;
8589
8590 switch (INTEL_INFO(dev)->gen) {
8591 case 2:
8592 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8593 break;
8594
8595 case 3:
8596 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8597 break;
8598
8599 case 4:
8600 case 5:
8601 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8602 break;
8603
8604 case 6:
8605 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8606 break;
8607 case 7:
8608 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8609 break;
8610 }
8611 }
8612
8613 /*
8614 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8615 * resume, or other times. This quirk makes sure that's the case for
8616 * affected systems.
8617 */
8618 static void quirk_pipea_force(struct drm_device *dev)
8619 {
8620 struct drm_i915_private *dev_priv = dev->dev_private;
8621
8622 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8623 DRM_INFO("applying pipe a force quirk\n");
8624 }
8625
8626 /*
8627 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8628 */
8629 static void quirk_ssc_force_disable(struct drm_device *dev)
8630 {
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8632 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8633 DRM_INFO("applying lvds SSC disable quirk\n");
8634 }
8635
8636 /*
8637 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8638 * brightness value
8639 */
8640 static void quirk_invert_brightness(struct drm_device *dev)
8641 {
8642 struct drm_i915_private *dev_priv = dev->dev_private;
8643 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8644 DRM_INFO("applying inverted panel brightness quirk\n");
8645 }
8646
8647 struct intel_quirk {
8648 int device;
8649 int subsystem_vendor;
8650 int subsystem_device;
8651 void (*hook)(struct drm_device *dev);
8652 };
8653
8654 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8655 struct intel_dmi_quirk {
8656 void (*hook)(struct drm_device *dev);
8657 const struct dmi_system_id (*dmi_id_list)[];
8658 };
8659
8660 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8661 {
8662 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8663 return 1;
8664 }
8665
8666 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8667 {
8668 .dmi_id_list = &(const struct dmi_system_id[]) {
8669 {
8670 .callback = intel_dmi_reverse_brightness,
8671 .ident = "NCR Corporation",
8672 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8673 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8674 },
8675 },
8676 { } /* terminating entry */
8677 },
8678 .hook = quirk_invert_brightness,
8679 },
8680 };
8681
8682 static struct intel_quirk intel_quirks[] = {
8683 /* HP Mini needs pipe A force quirk (LP: #322104) */
8684 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8685
8686 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8687 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8688
8689 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8690 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8691
8692 /* 830/845 need to leave pipe A & dpll A up */
8693 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8694 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8695
8696 /* Lenovo U160 cannot use SSC on LVDS */
8697 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8698
8699 /* Sony Vaio Y cannot use SSC on LVDS */
8700 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8701
8702 /* Acer Aspire 5734Z must invert backlight brightness */
8703 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8704 };
8705
8706 static void intel_init_quirks(struct drm_device *dev)
8707 {
8708 struct pci_dev *d = dev->pdev;
8709 int i;
8710
8711 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8712 struct intel_quirk *q = &intel_quirks[i];
8713
8714 if (d->device == q->device &&
8715 (d->subsystem_vendor == q->subsystem_vendor ||
8716 q->subsystem_vendor == PCI_ANY_ID) &&
8717 (d->subsystem_device == q->subsystem_device ||
8718 q->subsystem_device == PCI_ANY_ID))
8719 q->hook(dev);
8720 }
8721 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8722 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8723 intel_dmi_quirks[i].hook(dev);
8724 }
8725 }
8726
8727 /* Disable the VGA plane that we never use */
8728 static void i915_disable_vga(struct drm_device *dev)
8729 {
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731 u8 sr1;
8732 u32 vga_reg;
8733
8734 if (HAS_PCH_SPLIT(dev))
8735 vga_reg = CPU_VGACNTRL;
8736 else
8737 vga_reg = VGACNTRL;
8738
8739 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8740 outb(SR01, VGA_SR_INDEX);
8741 sr1 = inb(VGA_SR_DATA);
8742 outb(sr1 | 1<<5, VGA_SR_DATA);
8743 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8744 udelay(300);
8745
8746 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8747 POSTING_READ(vga_reg);
8748 }
8749
8750 void intel_modeset_init_hw(struct drm_device *dev)
8751 {
8752 /* We attempt to init the necessary power wells early in the initialization
8753 * time, so the subsystems that expect power to be enabled can work.
8754 */
8755 intel_init_power_wells(dev);
8756
8757 intel_prepare_ddi(dev);
8758
8759 intel_init_clock_gating(dev);
8760
8761 mutex_lock(&dev->struct_mutex);
8762 intel_enable_gt_powersave(dev);
8763 mutex_unlock(&dev->struct_mutex);
8764 }
8765
8766 void intel_modeset_init(struct drm_device *dev)
8767 {
8768 struct drm_i915_private *dev_priv = dev->dev_private;
8769 int i, ret;
8770
8771 drm_mode_config_init(dev);
8772
8773 dev->mode_config.min_width = 0;
8774 dev->mode_config.min_height = 0;
8775
8776 dev->mode_config.preferred_depth = 24;
8777 dev->mode_config.prefer_shadow = 1;
8778
8779 dev->mode_config.funcs = &intel_mode_funcs;
8780
8781 intel_init_quirks(dev);
8782
8783 intel_init_pm(dev);
8784
8785 intel_init_display(dev);
8786
8787 if (IS_GEN2(dev)) {
8788 dev->mode_config.max_width = 2048;
8789 dev->mode_config.max_height = 2048;
8790 } else if (IS_GEN3(dev)) {
8791 dev->mode_config.max_width = 4096;
8792 dev->mode_config.max_height = 4096;
8793 } else {
8794 dev->mode_config.max_width = 8192;
8795 dev->mode_config.max_height = 8192;
8796 }
8797 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8798
8799 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8800 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8801
8802 for (i = 0; i < dev_priv->num_pipe; i++) {
8803 intel_crtc_init(dev, i);
8804 ret = intel_plane_init(dev, i);
8805 if (ret)
8806 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8807 }
8808
8809 intel_cpu_pll_init(dev);
8810 intel_pch_pll_init(dev);
8811
8812 /* Just disable it once at startup */
8813 i915_disable_vga(dev);
8814 intel_setup_outputs(dev);
8815 }
8816
8817 static void
8818 intel_connector_break_all_links(struct intel_connector *connector)
8819 {
8820 connector->base.dpms = DRM_MODE_DPMS_OFF;
8821 connector->base.encoder = NULL;
8822 connector->encoder->connectors_active = false;
8823 connector->encoder->base.crtc = NULL;
8824 }
8825
8826 static void intel_enable_pipe_a(struct drm_device *dev)
8827 {
8828 struct intel_connector *connector;
8829 struct drm_connector *crt = NULL;
8830 struct intel_load_detect_pipe load_detect_temp;
8831
8832 /* We can't just switch on the pipe A, we need to set things up with a
8833 * proper mode and output configuration. As a gross hack, enable pipe A
8834 * by enabling the load detect pipe once. */
8835 list_for_each_entry(connector,
8836 &dev->mode_config.connector_list,
8837 base.head) {
8838 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8839 crt = &connector->base;
8840 break;
8841 }
8842 }
8843
8844 if (!crt)
8845 return;
8846
8847 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8848 intel_release_load_detect_pipe(crt, &load_detect_temp);
8849
8850
8851 }
8852
8853 static bool
8854 intel_check_plane_mapping(struct intel_crtc *crtc)
8855 {
8856 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8857 u32 reg, val;
8858
8859 if (dev_priv->num_pipe == 1)
8860 return true;
8861
8862 reg = DSPCNTR(!crtc->plane);
8863 val = I915_READ(reg);
8864
8865 if ((val & DISPLAY_PLANE_ENABLE) &&
8866 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8867 return false;
8868
8869 return true;
8870 }
8871
8872 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8873 {
8874 struct drm_device *dev = crtc->base.dev;
8875 struct drm_i915_private *dev_priv = dev->dev_private;
8876 u32 reg;
8877
8878 /* Clear any frame start delays used for debugging left by the BIOS */
8879 reg = PIPECONF(crtc->cpu_transcoder);
8880 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8881
8882 /* We need to sanitize the plane -> pipe mapping first because this will
8883 * disable the crtc (and hence change the state) if it is wrong. Note
8884 * that gen4+ has a fixed plane -> pipe mapping. */
8885 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8886 struct intel_connector *connector;
8887 bool plane;
8888
8889 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8890 crtc->base.base.id);
8891
8892 /* Pipe has the wrong plane attached and the plane is active.
8893 * Temporarily change the plane mapping and disable everything
8894 * ... */
8895 plane = crtc->plane;
8896 crtc->plane = !plane;
8897 dev_priv->display.crtc_disable(&crtc->base);
8898 crtc->plane = plane;
8899
8900 /* ... and break all links. */
8901 list_for_each_entry(connector, &dev->mode_config.connector_list,
8902 base.head) {
8903 if (connector->encoder->base.crtc != &crtc->base)
8904 continue;
8905
8906 intel_connector_break_all_links(connector);
8907 }
8908
8909 WARN_ON(crtc->active);
8910 crtc->base.enabled = false;
8911 }
8912
8913 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8914 crtc->pipe == PIPE_A && !crtc->active) {
8915 /* BIOS forgot to enable pipe A, this mostly happens after
8916 * resume. Force-enable the pipe to fix this, the update_dpms
8917 * call below we restore the pipe to the right state, but leave
8918 * the required bits on. */
8919 intel_enable_pipe_a(dev);
8920 }
8921
8922 /* Adjust the state of the output pipe according to whether we
8923 * have active connectors/encoders. */
8924 intel_crtc_update_dpms(&crtc->base);
8925
8926 if (crtc->active != crtc->base.enabled) {
8927 struct intel_encoder *encoder;
8928
8929 /* This can happen either due to bugs in the get_hw_state
8930 * functions or because the pipe is force-enabled due to the
8931 * pipe A quirk. */
8932 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8933 crtc->base.base.id,
8934 crtc->base.enabled ? "enabled" : "disabled",
8935 crtc->active ? "enabled" : "disabled");
8936
8937 crtc->base.enabled = crtc->active;
8938
8939 /* Because we only establish the connector -> encoder ->
8940 * crtc links if something is active, this means the
8941 * crtc is now deactivated. Break the links. connector
8942 * -> encoder links are only establish when things are
8943 * actually up, hence no need to break them. */
8944 WARN_ON(crtc->active);
8945
8946 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8947 WARN_ON(encoder->connectors_active);
8948 encoder->base.crtc = NULL;
8949 }
8950 }
8951 }
8952
8953 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8954 {
8955 struct intel_connector *connector;
8956 struct drm_device *dev = encoder->base.dev;
8957
8958 /* We need to check both for a crtc link (meaning that the
8959 * encoder is active and trying to read from a pipe) and the
8960 * pipe itself being active. */
8961 bool has_active_crtc = encoder->base.crtc &&
8962 to_intel_crtc(encoder->base.crtc)->active;
8963
8964 if (encoder->connectors_active && !has_active_crtc) {
8965 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8966 encoder->base.base.id,
8967 drm_get_encoder_name(&encoder->base));
8968
8969 /* Connector is active, but has no active pipe. This is
8970 * fallout from our resume register restoring. Disable
8971 * the encoder manually again. */
8972 if (encoder->base.crtc) {
8973 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8974 encoder->base.base.id,
8975 drm_get_encoder_name(&encoder->base));
8976 encoder->disable(encoder);
8977 }
8978
8979 /* Inconsistent output/port/pipe state happens presumably due to
8980 * a bug in one of the get_hw_state functions. Or someplace else
8981 * in our code, like the register restore mess on resume. Clamp
8982 * things to off as a safer default. */
8983 list_for_each_entry(connector,
8984 &dev->mode_config.connector_list,
8985 base.head) {
8986 if (connector->encoder != encoder)
8987 continue;
8988
8989 intel_connector_break_all_links(connector);
8990 }
8991 }
8992 /* Enabled encoders without active connectors will be fixed in
8993 * the crtc fixup. */
8994 }
8995
8996 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8997 * and i915 state tracking structures. */
8998 void intel_modeset_setup_hw_state(struct drm_device *dev)
8999 {
9000 struct drm_i915_private *dev_priv = dev->dev_private;
9001 enum pipe pipe;
9002 u32 tmp;
9003 struct intel_crtc *crtc;
9004 struct intel_encoder *encoder;
9005 struct intel_connector *connector;
9006
9007 if (IS_HASWELL(dev)) {
9008 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9009
9010 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9011 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9012 case TRANS_DDI_EDP_INPUT_A_ON:
9013 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9014 pipe = PIPE_A;
9015 break;
9016 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9017 pipe = PIPE_B;
9018 break;
9019 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9020 pipe = PIPE_C;
9021 break;
9022 }
9023
9024 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9025 crtc->cpu_transcoder = TRANSCODER_EDP;
9026
9027 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9028 pipe_name(pipe));
9029 }
9030 }
9031
9032 for_each_pipe(pipe) {
9033 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9034
9035 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9036 if (tmp & PIPECONF_ENABLE)
9037 crtc->active = true;
9038 else
9039 crtc->active = false;
9040
9041 crtc->base.enabled = crtc->active;
9042
9043 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9044 crtc->base.base.id,
9045 crtc->active ? "enabled" : "disabled");
9046 }
9047
9048 if (IS_HASWELL(dev))
9049 intel_ddi_setup_hw_pll_state(dev);
9050
9051 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9052 base.head) {
9053 pipe = 0;
9054
9055 if (encoder->get_hw_state(encoder, &pipe)) {
9056 encoder->base.crtc =
9057 dev_priv->pipe_to_crtc_mapping[pipe];
9058 } else {
9059 encoder->base.crtc = NULL;
9060 }
9061
9062 encoder->connectors_active = false;
9063 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9064 encoder->base.base.id,
9065 drm_get_encoder_name(&encoder->base),
9066 encoder->base.crtc ? "enabled" : "disabled",
9067 pipe);
9068 }
9069
9070 list_for_each_entry(connector, &dev->mode_config.connector_list,
9071 base.head) {
9072 if (connector->get_hw_state(connector)) {
9073 connector->base.dpms = DRM_MODE_DPMS_ON;
9074 connector->encoder->connectors_active = true;
9075 connector->base.encoder = &connector->encoder->base;
9076 } else {
9077 connector->base.dpms = DRM_MODE_DPMS_OFF;
9078 connector->base.encoder = NULL;
9079 }
9080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9081 connector->base.base.id,
9082 drm_get_connector_name(&connector->base),
9083 connector->base.encoder ? "enabled" : "disabled");
9084 }
9085
9086 /* HW state is read out, now we need to sanitize this mess. */
9087 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9088 base.head) {
9089 intel_sanitize_encoder(encoder);
9090 }
9091
9092 for_each_pipe(pipe) {
9093 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9094 intel_sanitize_crtc(crtc);
9095 }
9096
9097 intel_modeset_update_staged_output_state(dev);
9098
9099 intel_modeset_check_state(dev);
9100
9101 drm_mode_config_reset(dev);
9102 }
9103
9104 void intel_modeset_gem_init(struct drm_device *dev)
9105 {
9106 intel_modeset_init_hw(dev);
9107
9108 intel_setup_overlay(dev);
9109
9110 intel_modeset_setup_hw_state(dev);
9111 }
9112
9113 void intel_modeset_cleanup(struct drm_device *dev)
9114 {
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 struct drm_crtc *crtc;
9117 struct intel_crtc *intel_crtc;
9118
9119 drm_kms_helper_poll_fini(dev);
9120 mutex_lock(&dev->struct_mutex);
9121
9122 intel_unregister_dsm_handler();
9123
9124
9125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9126 /* Skip inactive CRTCs */
9127 if (!crtc->fb)
9128 continue;
9129
9130 intel_crtc = to_intel_crtc(crtc);
9131 intel_increase_pllclock(crtc);
9132 }
9133
9134 intel_disable_fbc(dev);
9135
9136 intel_disable_gt_powersave(dev);
9137
9138 ironlake_teardown_rc6(dev);
9139
9140 if (IS_VALLEYVIEW(dev))
9141 vlv_init_dpio(dev);
9142
9143 mutex_unlock(&dev->struct_mutex);
9144
9145 /* Disable the irq before mode object teardown, for the irq might
9146 * enqueue unpin/hotplug work. */
9147 drm_irq_uninstall(dev);
9148 cancel_work_sync(&dev_priv->hotplug_work);
9149 cancel_work_sync(&dev_priv->rps.work);
9150
9151 /* flush any delayed tasks or pending work */
9152 flush_scheduled_work();
9153
9154 drm_mode_config_cleanup(dev);
9155 }
9156
9157 /*
9158 * Return which encoder is currently attached for connector.
9159 */
9160 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9161 {
9162 return &intel_attached_encoder(connector)->base;
9163 }
9164
9165 void intel_connector_attach_encoder(struct intel_connector *connector,
9166 struct intel_encoder *encoder)
9167 {
9168 connector->encoder = encoder;
9169 drm_mode_connector_attach_encoder(&connector->base,
9170 &encoder->base);
9171 }
9172
9173 /*
9174 * set vga decode state - true == enable VGA decode
9175 */
9176 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9177 {
9178 struct drm_i915_private *dev_priv = dev->dev_private;
9179 u16 gmch_ctrl;
9180
9181 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9182 if (state)
9183 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9184 else
9185 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9186 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9187 return 0;
9188 }
9189
9190 #ifdef CONFIG_DEBUG_FS
9191 #include <linux/seq_file.h>
9192
9193 struct intel_display_error_state {
9194 struct intel_cursor_error_state {
9195 u32 control;
9196 u32 position;
9197 u32 base;
9198 u32 size;
9199 } cursor[I915_MAX_PIPES];
9200
9201 struct intel_pipe_error_state {
9202 u32 conf;
9203 u32 source;
9204
9205 u32 htotal;
9206 u32 hblank;
9207 u32 hsync;
9208 u32 vtotal;
9209 u32 vblank;
9210 u32 vsync;
9211 } pipe[I915_MAX_PIPES];
9212
9213 struct intel_plane_error_state {
9214 u32 control;
9215 u32 stride;
9216 u32 size;
9217 u32 pos;
9218 u32 addr;
9219 u32 surface;
9220 u32 tile_offset;
9221 } plane[I915_MAX_PIPES];
9222 };
9223
9224 struct intel_display_error_state *
9225 intel_display_capture_error_state(struct drm_device *dev)
9226 {
9227 drm_i915_private_t *dev_priv = dev->dev_private;
9228 struct intel_display_error_state *error;
9229 enum transcoder cpu_transcoder;
9230 int i;
9231
9232 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9233 if (error == NULL)
9234 return NULL;
9235
9236 for_each_pipe(i) {
9237 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9238
9239 error->cursor[i].control = I915_READ(CURCNTR(i));
9240 error->cursor[i].position = I915_READ(CURPOS(i));
9241 error->cursor[i].base = I915_READ(CURBASE(i));
9242
9243 error->plane[i].control = I915_READ(DSPCNTR(i));
9244 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9245 error->plane[i].size = I915_READ(DSPSIZE(i));
9246 error->plane[i].pos = I915_READ(DSPPOS(i));
9247 error->plane[i].addr = I915_READ(DSPADDR(i));
9248 if (INTEL_INFO(dev)->gen >= 4) {
9249 error->plane[i].surface = I915_READ(DSPSURF(i));
9250 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9251 }
9252
9253 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9254 error->pipe[i].source = I915_READ(PIPESRC(i));
9255 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9256 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9257 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9258 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9259 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9260 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9261 }
9262
9263 return error;
9264 }
9265
9266 void
9267 intel_display_print_error_state(struct seq_file *m,
9268 struct drm_device *dev,
9269 struct intel_display_error_state *error)
9270 {
9271 drm_i915_private_t *dev_priv = dev->dev_private;
9272 int i;
9273
9274 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9275 for_each_pipe(i) {
9276 seq_printf(m, "Pipe [%d]:\n", i);
9277 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9278 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9279 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9280 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9281 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9282 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9283 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9284 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9285
9286 seq_printf(m, "Plane [%d]:\n", i);
9287 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9288 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9289 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9290 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9291 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9292 if (INTEL_INFO(dev)->gen >= 4) {
9293 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9294 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9295 }
9296
9297 seq_printf(m, "Cursor [%d]:\n", i);
9298 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9299 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9300 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9301 }
9302 }
9303 #endif
Linux kernel - Deliverables
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