2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
50 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
51 struct intel_crtc_config
*pipe_config
);
52 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
53 struct intel_crtc_config
*pipe_config
);
55 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
56 int x
, int y
, struct drm_framebuffer
*old_fb
);
57 static int intel_framebuffer_init(struct drm_device
*dev
,
58 struct intel_framebuffer
*ifb
,
59 struct drm_mode_fb_cmd2
*mode_cmd
,
60 struct drm_i915_gem_object
*obj
);
61 static void intel_dp_set_m_n(struct intel_crtc
*crtc
);
62 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
63 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
65 struct intel_link_m_n
*m_n
);
66 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
67 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
68 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
69 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
80 typedef struct intel_limit intel_limit_t
;
82 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
87 intel_pch_rawclk(struct drm_device
*dev
)
89 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
91 WARN_ON(!HAS_PCH_SPLIT(dev
));
93 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
96 static inline u32
/* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device
*dev
)
100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
101 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
106 static const intel_limit_t intel_limits_i8xx_dac
= {
107 .dot
= { .min
= 25000, .max
= 350000 },
108 .vco
= { .min
= 908000, .max
= 1512000 },
109 .n
= { .min
= 2, .max
= 16 },
110 .m
= { .min
= 96, .max
= 140 },
111 .m1
= { .min
= 18, .max
= 26 },
112 .m2
= { .min
= 6, .max
= 16 },
113 .p
= { .min
= 4, .max
= 128 },
114 .p1
= { .min
= 2, .max
= 33 },
115 .p2
= { .dot_limit
= 165000,
116 .p2_slow
= 4, .p2_fast
= 2 },
119 static const intel_limit_t intel_limits_i8xx_dvo
= {
120 .dot
= { .min
= 25000, .max
= 350000 },
121 .vco
= { .min
= 908000, .max
= 1512000 },
122 .n
= { .min
= 2, .max
= 16 },
123 .m
= { .min
= 96, .max
= 140 },
124 .m1
= { .min
= 18, .max
= 26 },
125 .m2
= { .min
= 6, .max
= 16 },
126 .p
= { .min
= 4, .max
= 128 },
127 .p1
= { .min
= 2, .max
= 33 },
128 .p2
= { .dot_limit
= 165000,
129 .p2_slow
= 4, .p2_fast
= 4 },
132 static const intel_limit_t intel_limits_i8xx_lvds
= {
133 .dot
= { .min
= 25000, .max
= 350000 },
134 .vco
= { .min
= 908000, .max
= 1512000 },
135 .n
= { .min
= 2, .max
= 16 },
136 .m
= { .min
= 96, .max
= 140 },
137 .m1
= { .min
= 18, .max
= 26 },
138 .m2
= { .min
= 6, .max
= 16 },
139 .p
= { .min
= 4, .max
= 128 },
140 .p1
= { .min
= 1, .max
= 6 },
141 .p2
= { .dot_limit
= 165000,
142 .p2_slow
= 14, .p2_fast
= 7 },
145 static const intel_limit_t intel_limits_i9xx_sdvo
= {
146 .dot
= { .min
= 20000, .max
= 400000 },
147 .vco
= { .min
= 1400000, .max
= 2800000 },
148 .n
= { .min
= 1, .max
= 6 },
149 .m
= { .min
= 70, .max
= 120 },
150 .m1
= { .min
= 8, .max
= 18 },
151 .m2
= { .min
= 3, .max
= 7 },
152 .p
= { .min
= 5, .max
= 80 },
153 .p1
= { .min
= 1, .max
= 8 },
154 .p2
= { .dot_limit
= 200000,
155 .p2_slow
= 10, .p2_fast
= 5 },
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 8, .max
= 18 },
164 .m2
= { .min
= 3, .max
= 7 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
172 static const intel_limit_t intel_limits_g4x_sdvo
= {
173 .dot
= { .min
= 25000, .max
= 270000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 17, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 10, .max
= 30 },
180 .p1
= { .min
= 1, .max
= 3},
181 .p2
= { .dot_limit
= 270000,
187 static const intel_limit_t intel_limits_g4x_hdmi
= {
188 .dot
= { .min
= 22000, .max
= 400000 },
189 .vco
= { .min
= 1750000, .max
= 3500000},
190 .n
= { .min
= 1, .max
= 4 },
191 .m
= { .min
= 104, .max
= 138 },
192 .m1
= { .min
= 16, .max
= 23 },
193 .m2
= { .min
= 5, .max
= 11 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8},
196 .p2
= { .dot_limit
= 165000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
201 .dot
= { .min
= 20000, .max
= 115000 },
202 .vco
= { .min
= 1750000, .max
= 3500000 },
203 .n
= { .min
= 1, .max
= 3 },
204 .m
= { .min
= 104, .max
= 138 },
205 .m1
= { .min
= 17, .max
= 23 },
206 .m2
= { .min
= 5, .max
= 11 },
207 .p
= { .min
= 28, .max
= 112 },
208 .p1
= { .min
= 2, .max
= 8 },
209 .p2
= { .dot_limit
= 0,
210 .p2_slow
= 14, .p2_fast
= 14
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
215 .dot
= { .min
= 80000, .max
= 224000 },
216 .vco
= { .min
= 1750000, .max
= 3500000 },
217 .n
= { .min
= 1, .max
= 3 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 14, .max
= 42 },
222 .p1
= { .min
= 2, .max
= 6 },
223 .p2
= { .dot_limit
= 0,
224 .p2_slow
= 7, .p2_fast
= 7
228 static const intel_limit_t intel_limits_pineview_sdvo
= {
229 .dot
= { .min
= 20000, .max
= 400000},
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 /* Pineview's Ncounter is a ring counter */
232 .n
= { .min
= 3, .max
= 6 },
233 .m
= { .min
= 2, .max
= 256 },
234 /* Pineview only has one combined m divider, which we treat as m2. */
235 .m1
= { .min
= 0, .max
= 0 },
236 .m2
= { .min
= 0, .max
= 254 },
237 .p
= { .min
= 5, .max
= 80 },
238 .p1
= { .min
= 1, .max
= 8 },
239 .p2
= { .dot_limit
= 200000,
240 .p2_slow
= 10, .p2_fast
= 5 },
243 static const intel_limit_t intel_limits_pineview_lvds
= {
244 .dot
= { .min
= 20000, .max
= 400000 },
245 .vco
= { .min
= 1700000, .max
= 3500000 },
246 .n
= { .min
= 3, .max
= 6 },
247 .m
= { .min
= 2, .max
= 256 },
248 .m1
= { .min
= 0, .max
= 0 },
249 .m2
= { .min
= 0, .max
= 254 },
250 .p
= { .min
= 7, .max
= 112 },
251 .p1
= { .min
= 1, .max
= 8 },
252 .p2
= { .dot_limit
= 112000,
253 .p2_slow
= 14, .p2_fast
= 14 },
256 /* Ironlake / Sandybridge
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
261 static const intel_limit_t intel_limits_ironlake_dac
= {
262 .dot
= { .min
= 25000, .max
= 350000 },
263 .vco
= { .min
= 1760000, .max
= 3510000 },
264 .n
= { .min
= 1, .max
= 5 },
265 .m
= { .min
= 79, .max
= 127 },
266 .m1
= { .min
= 12, .max
= 22 },
267 .m2
= { .min
= 5, .max
= 9 },
268 .p
= { .min
= 5, .max
= 80 },
269 .p1
= { .min
= 1, .max
= 8 },
270 .p2
= { .dot_limit
= 225000,
271 .p2_slow
= 10, .p2_fast
= 5 },
274 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
275 .dot
= { .min
= 25000, .max
= 350000 },
276 .vco
= { .min
= 1760000, .max
= 3510000 },
277 .n
= { .min
= 1, .max
= 3 },
278 .m
= { .min
= 79, .max
= 118 },
279 .m1
= { .min
= 12, .max
= 22 },
280 .m2
= { .min
= 5, .max
= 9 },
281 .p
= { .min
= 28, .max
= 112 },
282 .p1
= { .min
= 2, .max
= 8 },
283 .p2
= { .dot_limit
= 225000,
284 .p2_slow
= 14, .p2_fast
= 14 },
287 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
288 .dot
= { .min
= 25000, .max
= 350000 },
289 .vco
= { .min
= 1760000, .max
= 3510000 },
290 .n
= { .min
= 1, .max
= 3 },
291 .m
= { .min
= 79, .max
= 127 },
292 .m1
= { .min
= 12, .max
= 22 },
293 .m2
= { .min
= 5, .max
= 9 },
294 .p
= { .min
= 14, .max
= 56 },
295 .p1
= { .min
= 2, .max
= 8 },
296 .p2
= { .dot_limit
= 225000,
297 .p2_slow
= 7, .p2_fast
= 7 },
300 /* LVDS 100mhz refclk limits. */
301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
302 .dot
= { .min
= 25000, .max
= 350000 },
303 .vco
= { .min
= 1760000, .max
= 3510000 },
304 .n
= { .min
= 1, .max
= 2 },
305 .m
= { .min
= 79, .max
= 126 },
306 .m1
= { .min
= 12, .max
= 22 },
307 .m2
= { .min
= 5, .max
= 9 },
308 .p
= { .min
= 28, .max
= 112 },
309 .p1
= { .min
= 2, .max
= 8 },
310 .p2
= { .dot_limit
= 225000,
311 .p2_slow
= 14, .p2_fast
= 14 },
314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
315 .dot
= { .min
= 25000, .max
= 350000 },
316 .vco
= { .min
= 1760000, .max
= 3510000 },
317 .n
= { .min
= 1, .max
= 3 },
318 .m
= { .min
= 79, .max
= 126 },
319 .m1
= { .min
= 12, .max
= 22 },
320 .m2
= { .min
= 5, .max
= 9 },
321 .p
= { .min
= 14, .max
= 42 },
322 .p1
= { .min
= 2, .max
= 6 },
323 .p2
= { .dot_limit
= 225000,
324 .p2_slow
= 7, .p2_fast
= 7 },
327 static const intel_limit_t intel_limits_vlv
= {
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
334 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
335 .vco
= { .min
= 4000000, .max
= 6000000 },
336 .n
= { .min
= 1, .max
= 7 },
337 .m1
= { .min
= 2, .max
= 3 },
338 .m2
= { .min
= 11, .max
= 156 },
339 .p1
= { .min
= 2, .max
= 3 },
340 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
343 static const intel_limit_t intel_limits_chv
= {
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
350 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
351 .vco
= { .min
= 4860000, .max
= 6700000 },
352 .n
= { .min
= 1, .max
= 1 },
353 .m1
= { .min
= 2, .max
= 2 },
354 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
355 .p1
= { .min
= 2, .max
= 4 },
356 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
359 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
361 clock
->m
= clock
->m1
* clock
->m2
;
362 clock
->p
= clock
->p1
* clock
->p2
;
363 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
365 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
366 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
370 * Returns whether any output on the specified pipe is of the specified type
372 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
374 struct drm_device
*dev
= crtc
->dev
;
375 struct intel_encoder
*encoder
;
377 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
378 if (encoder
->type
== type
)
384 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
387 struct drm_device
*dev
= crtc
->dev
;
388 const intel_limit_t
*limit
;
390 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
391 if (intel_is_dual_link_lvds(dev
)) {
392 if (refclk
== 100000)
393 limit
= &intel_limits_ironlake_dual_lvds_100m
;
395 limit
= &intel_limits_ironlake_dual_lvds
;
397 if (refclk
== 100000)
398 limit
= &intel_limits_ironlake_single_lvds_100m
;
400 limit
= &intel_limits_ironlake_single_lvds
;
403 limit
= &intel_limits_ironlake_dac
;
408 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
410 struct drm_device
*dev
= crtc
->dev
;
411 const intel_limit_t
*limit
;
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
414 if (intel_is_dual_link_lvds(dev
))
415 limit
= &intel_limits_g4x_dual_channel_lvds
;
417 limit
= &intel_limits_g4x_single_channel_lvds
;
418 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
419 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
420 limit
= &intel_limits_g4x_hdmi
;
421 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
422 limit
= &intel_limits_g4x_sdvo
;
423 } else /* The option is for other outputs */
424 limit
= &intel_limits_i9xx_sdvo
;
429 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
431 struct drm_device
*dev
= crtc
->dev
;
432 const intel_limit_t
*limit
;
434 if (HAS_PCH_SPLIT(dev
))
435 limit
= intel_ironlake_limit(crtc
, refclk
);
436 else if (IS_G4X(dev
)) {
437 limit
= intel_g4x_limit(crtc
);
438 } else if (IS_PINEVIEW(dev
)) {
439 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
440 limit
= &intel_limits_pineview_lvds
;
442 limit
= &intel_limits_pineview_sdvo
;
443 } else if (IS_CHERRYVIEW(dev
)) {
444 limit
= &intel_limits_chv
;
445 } else if (IS_VALLEYVIEW(dev
)) {
446 limit
= &intel_limits_vlv
;
447 } else if (!IS_GEN2(dev
)) {
448 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
449 limit
= &intel_limits_i9xx_lvds
;
451 limit
= &intel_limits_i9xx_sdvo
;
453 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
454 limit
= &intel_limits_i8xx_lvds
;
455 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
456 limit
= &intel_limits_i8xx_dvo
;
458 limit
= &intel_limits_i8xx_dac
;
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
466 clock
->m
= clock
->m2
+ 2;
467 clock
->p
= clock
->p1
* clock
->p2
;
468 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
470 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
471 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
474 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
476 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
479 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
481 clock
->m
= i9xx_dpll_compute_m(clock
);
482 clock
->p
= clock
->p1
* clock
->p2
;
483 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
485 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
486 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
489 static void chv_clock(int refclk
, intel_clock_t
*clock
)
491 clock
->m
= clock
->m1
* clock
->m2
;
492 clock
->p
= clock
->p1
* clock
->p2
;
493 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
495 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
497 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
500 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
506 static bool intel_PLL_is_valid(struct drm_device
*dev
,
507 const intel_limit_t
*limit
,
508 const intel_clock_t
*clock
)
510 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
511 INTELPllInvalid("n out of range\n");
512 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
513 INTELPllInvalid("p1 out of range\n");
514 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
515 INTELPllInvalid("m2 out of range\n");
516 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
517 INTELPllInvalid("m1 out of range\n");
519 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
520 if (clock
->m1
<= clock
->m2
)
521 INTELPllInvalid("m1 <= m2\n");
523 if (!IS_VALLEYVIEW(dev
)) {
524 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
525 INTELPllInvalid("p out of range\n");
526 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
527 INTELPllInvalid("m out of range\n");
530 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
531 INTELPllInvalid("vco out of range\n");
532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
535 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
536 INTELPllInvalid("dot out of range\n");
542 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
543 int target
, int refclk
, intel_clock_t
*match_clock
,
544 intel_clock_t
*best_clock
)
546 struct drm_device
*dev
= crtc
->dev
;
550 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
556 if (intel_is_dual_link_lvds(dev
))
557 clock
.p2
= limit
->p2
.p2_fast
;
559 clock
.p2
= limit
->p2
.p2_slow
;
561 if (target
< limit
->p2
.dot_limit
)
562 clock
.p2
= limit
->p2
.p2_slow
;
564 clock
.p2
= limit
->p2
.p2_fast
;
567 memset(best_clock
, 0, sizeof(*best_clock
));
569 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
571 for (clock
.m2
= limit
->m2
.min
;
572 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
573 if (clock
.m2
>= clock
.m1
)
575 for (clock
.n
= limit
->n
.min
;
576 clock
.n
<= limit
->n
.max
; clock
.n
++) {
577 for (clock
.p1
= limit
->p1
.min
;
578 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
581 i9xx_clock(refclk
, &clock
);
582 if (!intel_PLL_is_valid(dev
, limit
,
586 clock
.p
!= match_clock
->p
)
589 this_err
= abs(clock
.dot
- target
);
590 if (this_err
< err
) {
599 return (err
!= target
);
603 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
604 int target
, int refclk
, intel_clock_t
*match_clock
,
605 intel_clock_t
*best_clock
)
607 struct drm_device
*dev
= crtc
->dev
;
611 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
617 if (intel_is_dual_link_lvds(dev
))
618 clock
.p2
= limit
->p2
.p2_fast
;
620 clock
.p2
= limit
->p2
.p2_slow
;
622 if (target
< limit
->p2
.dot_limit
)
623 clock
.p2
= limit
->p2
.p2_slow
;
625 clock
.p2
= limit
->p2
.p2_fast
;
628 memset(best_clock
, 0, sizeof(*best_clock
));
630 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
632 for (clock
.m2
= limit
->m2
.min
;
633 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
634 for (clock
.n
= limit
->n
.min
;
635 clock
.n
<= limit
->n
.max
; clock
.n
++) {
636 for (clock
.p1
= limit
->p1
.min
;
637 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
640 pineview_clock(refclk
, &clock
);
641 if (!intel_PLL_is_valid(dev
, limit
,
645 clock
.p
!= match_clock
->p
)
648 this_err
= abs(clock
.dot
- target
);
649 if (this_err
< err
) {
658 return (err
!= target
);
662 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
663 int target
, int refclk
, intel_clock_t
*match_clock
,
664 intel_clock_t
*best_clock
)
666 struct drm_device
*dev
= crtc
->dev
;
670 /* approximately equals target * 0.00585 */
671 int err_most
= (target
>> 8) + (target
>> 9);
674 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
675 if (intel_is_dual_link_lvds(dev
))
676 clock
.p2
= limit
->p2
.p2_fast
;
678 clock
.p2
= limit
->p2
.p2_slow
;
680 if (target
< limit
->p2
.dot_limit
)
681 clock
.p2
= limit
->p2
.p2_slow
;
683 clock
.p2
= limit
->p2
.p2_fast
;
686 memset(best_clock
, 0, sizeof(*best_clock
));
687 max_n
= limit
->n
.max
;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
690 /* based on hardware requirement, prefere larger m1,m2 */
691 for (clock
.m1
= limit
->m1
.max
;
692 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
693 for (clock
.m2
= limit
->m2
.max
;
694 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
695 for (clock
.p1
= limit
->p1
.max
;
696 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
699 i9xx_clock(refclk
, &clock
);
700 if (!intel_PLL_is_valid(dev
, limit
,
704 this_err
= abs(clock
.dot
- target
);
705 if (this_err
< err_most
) {
719 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
720 int target
, int refclk
, intel_clock_t
*match_clock
,
721 intel_clock_t
*best_clock
)
723 struct drm_device
*dev
= crtc
->dev
;
725 unsigned int bestppm
= 1000000;
726 /* min update 19.2 MHz */
727 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
730 target
*= 5; /* fast clock */
732 memset(best_clock
, 0, sizeof(*best_clock
));
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
736 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
737 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
738 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
739 clock
.p
= clock
.p1
* clock
.p2
;
740 /* based on hardware requirement, prefer bigger m1,m2 values */
741 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
742 unsigned int ppm
, diff
;
744 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
747 vlv_clock(refclk
, &clock
);
749 if (!intel_PLL_is_valid(dev
, limit
,
753 diff
= abs(clock
.dot
- target
);
754 ppm
= div_u64(1000000ULL * diff
, target
);
756 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
762 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
776 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
777 int target
, int refclk
, intel_clock_t
*match_clock
,
778 intel_clock_t
*best_clock
)
780 struct drm_device
*dev
= crtc
->dev
;
785 memset(best_clock
, 0, sizeof(*best_clock
));
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
792 clock
.n
= 1, clock
.m1
= 2;
793 target
*= 5; /* fast clock */
795 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
796 for (clock
.p2
= limit
->p2
.p2_fast
;
797 clock
.p2
>= limit
->p2
.p2_slow
;
798 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
800 clock
.p
= clock
.p1
* clock
.p2
;
802 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
803 clock
.n
) << 22, refclk
* clock
.m1
);
805 if (m2
> INT_MAX
/clock
.m1
)
810 chv_clock(refclk
, &clock
);
812 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
815 /* based on hardware requirement, prefer bigger p
817 if (clock
.p
> best_clock
->p
) {
827 bool intel_crtc_active(struct drm_crtc
*crtc
)
829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
834 * We can ditch the adjusted_mode.crtc_clock check as soon
835 * as Haswell has gained clock readout/fastboot support.
837 * We can ditch the crtc->primary->fb check as soon as we can
838 * properly reconstruct framebuffers.
840 return intel_crtc
->active
&& crtc
->primary
->fb
&&
841 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
844 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
847 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
850 return intel_crtc
->config
.cpu_transcoder
;
853 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
856 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
858 frame
= I915_READ(frame_reg
);
860 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
861 WARN(1, "vblank wait timed out\n");
865 * intel_wait_for_vblank - wait for vblank on a given pipe
867 * @pipe: pipe to wait for
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
872 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
875 int pipestat_reg
= PIPESTAT(pipe
);
877 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
878 g4x_wait_for_vblank(dev
, pipe
);
882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
895 I915_WRITE(pipestat_reg
,
896 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
898 /* Wait for vblank interrupt bit to set */
899 if (wait_for(I915_READ(pipestat_reg
) &
900 PIPE_VBLANK_INTERRUPT_STATUS
,
902 DRM_DEBUG_KMS("vblank wait timed out\n");
905 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
908 u32 reg
= PIPEDSL(pipe
);
913 line_mask
= DSL_LINEMASK_GEN2
;
915 line_mask
= DSL_LINEMASK_GEN3
;
917 line1
= I915_READ(reg
) & line_mask
;
919 line2
= I915_READ(reg
) & line_mask
;
921 return line1
== line2
;
925 * intel_wait_for_pipe_off - wait for pipe to turn off
927 * @pipe: pipe to wait for
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
934 * wait for the pipe register state bit to turn off
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
941 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
944 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
947 if (INTEL_INFO(dev
)->gen
>= 4) {
948 int reg
= PIPECONF(cpu_transcoder
);
950 /* Wait for the Pipe State to go off */
951 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
953 WARN(1, "pipe_off wait timed out\n");
955 /* Wait for the display line to settle */
956 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
957 WARN(1, "pipe_off wait timed out\n");
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
966 * Returns true if @port is connected, false otherwise.
968 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
969 struct intel_digital_port
*port
)
973 if (HAS_PCH_IBX(dev_priv
->dev
)) {
974 switch (port
->port
) {
976 bit
= SDE_PORTB_HOTPLUG
;
979 bit
= SDE_PORTC_HOTPLUG
;
982 bit
= SDE_PORTD_HOTPLUG
;
988 switch (port
->port
) {
990 bit
= SDE_PORTB_HOTPLUG_CPT
;
993 bit
= SDE_PORTC_HOTPLUG_CPT
;
996 bit
= SDE_PORTD_HOTPLUG_CPT
;
1003 return I915_READ(SDEISR
) & bit
;
1006 static const char *state_string(bool enabled
)
1008 return enabled
? "on" : "off";
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private
*dev_priv
,
1013 enum pipe pipe
, bool state
)
1020 val
= I915_READ(reg
);
1021 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1022 WARN(cur_state
!= state
,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state
), state_string(cur_state
));
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1033 mutex_lock(&dev_priv
->dpio_lock
);
1034 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1035 mutex_unlock(&dev_priv
->dpio_lock
);
1037 cur_state
= val
& DSI_PLL_VCO_EN
;
1038 WARN(cur_state
!= state
,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state
), state_string(cur_state
));
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1045 struct intel_shared_dpll
*
1046 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1048 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1050 if (crtc
->config
.shared_dpll
< 0)
1053 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1057 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1058 struct intel_shared_dpll
*pll
,
1062 struct intel_dpll_hw_state hw_state
;
1064 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1070 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1073 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1074 WARN(cur_state
!= state
,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll
->name
, state_string(state
), state_string(cur_state
));
1079 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1080 enum pipe pipe
, bool state
)
1085 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1088 if (HAS_DDI(dev_priv
->dev
)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1091 val
= I915_READ(reg
);
1092 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1094 reg
= FDI_TX_CTL(pipe
);
1095 val
= I915_READ(reg
);
1096 cur_state
= !!(val
& FDI_TX_ENABLE
);
1098 WARN(cur_state
!= state
,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state
), state_string(cur_state
));
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1105 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1106 enum pipe pipe
, bool state
)
1112 reg
= FDI_RX_CTL(pipe
);
1113 val
= I915_READ(reg
);
1114 cur_state
= !!(val
& FDI_RX_ENABLE
);
1115 WARN(cur_state
!= state
,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state
), state_string(cur_state
));
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv
->dev
))
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1141 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1142 enum pipe pipe
, bool state
)
1148 reg
= FDI_RX_CTL(pipe
);
1149 val
= I915_READ(reg
);
1150 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1151 WARN(cur_state
!= state
,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state
), state_string(cur_state
));
1156 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1159 int pp_reg
, lvds_reg
;
1161 enum pipe panel_pipe
= PIPE_A
;
1164 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1165 pp_reg
= PCH_PP_CONTROL
;
1166 lvds_reg
= PCH_LVDS
;
1168 pp_reg
= PP_CONTROL
;
1172 val
= I915_READ(pp_reg
);
1173 if (!(val
& PANEL_POWER_ON
) ||
1174 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1177 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1178 panel_pipe
= PIPE_B
;
1180 WARN(panel_pipe
== pipe
&& locked
,
1181 "panel assertion failure, pipe %c regs locked\n",
1185 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1186 enum pipe pipe
, bool state
)
1188 struct drm_device
*dev
= dev_priv
->dev
;
1191 if (IS_845G(dev
) || IS_I865G(dev
))
1192 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1194 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1196 WARN(cur_state
!= state
,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1203 void assert_pipe(struct drm_i915_private
*dev_priv
,
1204 enum pipe pipe
, bool state
)
1209 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1216 if (!intel_display_power_enabled(dev_priv
,
1217 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1220 reg
= PIPECONF(cpu_transcoder
);
1221 val
= I915_READ(reg
);
1222 cur_state
= !!(val
& PIPECONF_ENABLE
);
1225 WARN(cur_state
!= state
,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
1227 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1230 static void assert_plane(struct drm_i915_private
*dev_priv
,
1231 enum plane plane
, bool state
)
1237 reg
= DSPCNTR(plane
);
1238 val
= I915_READ(reg
);
1239 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1240 WARN(cur_state
!= state
,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane
), state_string(state
), state_string(cur_state
));
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1251 struct drm_device
*dev
= dev_priv
->dev
;
1256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev
)->gen
>= 4) {
1258 reg
= DSPCNTR(pipe
);
1259 val
= I915_READ(reg
);
1260 WARN(val
& DISPLAY_PLANE_ENABLE
,
1261 "plane %c assertion failure, should be disabled but not\n",
1266 /* Need to check both planes against the pipe */
1269 val
= I915_READ(reg
);
1270 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1271 DISPPLANE_SEL_PIPE_SHIFT
;
1272 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i
), pipe_name(pipe
));
1278 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1281 struct drm_device
*dev
= dev_priv
->dev
;
1285 if (IS_VALLEYVIEW(dev
)) {
1286 for_each_sprite(pipe
, sprite
) {
1287 reg
= SPCNTR(pipe
, sprite
);
1288 val
= I915_READ(reg
);
1289 WARN(val
& SP_ENABLE
,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1293 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1295 val
= I915_READ(reg
);
1296 WARN(val
& SPRITE_ENABLE
,
1297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298 plane_name(pipe
), pipe_name(pipe
));
1299 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1300 reg
= DVSCNTR(pipe
);
1301 val
= I915_READ(reg
);
1302 WARN(val
& DVS_ENABLE
,
1303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe
), pipe_name(pipe
));
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1313 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1315 val
= I915_READ(PCH_DREF_CONTROL
);
1316 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1317 DREF_SUPERSPREAD_SOURCE_MASK
));
1318 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1328 reg
= PCH_TRANSCONF(pipe
);
1329 val
= I915_READ(reg
);
1330 enabled
= !!(val
& TRANS_ENABLE
);
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1336 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1337 enum pipe pipe
, u32 port_sel
, u32 val
)
1339 if ((val
& DP_PORT_EN
) == 0)
1342 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1343 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1344 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1345 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1347 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1348 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1351 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1357 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1358 enum pipe pipe
, u32 val
)
1360 if ((val
& SDVO_ENABLE
) == 0)
1363 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1364 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1366 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1367 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1370 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1376 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1377 enum pipe pipe
, u32 val
)
1379 if ((val
& LVDS_PORT_EN
) == 0)
1382 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1383 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1386 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1392 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1393 enum pipe pipe
, u32 val
)
1395 if ((val
& ADPA_DAC_ENABLE
) == 0)
1397 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1398 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1401 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1407 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1408 enum pipe pipe
, int reg
, u32 port_sel
)
1410 u32 val
= I915_READ(reg
);
1411 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg
, pipe_name(pipe
));
1415 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1416 && (val
& DP_PIPEB_SELECT
),
1417 "IBX PCH dp port still using transcoder B\n");
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1421 enum pipe pipe
, int reg
)
1423 u32 val
= I915_READ(reg
);
1424 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426 reg
, pipe_name(pipe
));
1428 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1429 && (val
& SDVO_PIPE_B_SELECT
),
1430 "IBX PCH hdmi port still using transcoder B\n");
1433 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1439 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1440 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1441 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1444 val
= I915_READ(reg
);
1445 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1446 "PCH VGA enabled on transcoder %c, should be disabled\n",
1450 val
= I915_READ(reg
);
1451 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1455 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1456 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1457 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1460 static void intel_init_dpio(struct drm_device
*dev
)
1462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1464 if (!IS_VALLEYVIEW(dev
))
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1472 if (IS_CHERRYVIEW(dev
)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1480 static void intel_reset_dpio(struct drm_device
*dev
)
1482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1484 if (!IS_VALLEYVIEW(dev
))
1487 if (IS_CHERRYVIEW(dev
)) {
1491 for (phy
= DPIO_PHY0
; phy
< I915_NUM_PHYS_VLV
; phy
++) {
1492 /* Poll for phypwrgood signal */
1493 if (wait_for(I915_READ(DISPLAY_PHY_STATUS
) &
1494 PHY_POWERGOOD(phy
), 1))
1495 DRM_ERROR("Display PHY %d is not power up\n", phy
);
1498 * Deassert common lane reset for PHY.
1500 * This should only be done on init and resume from S3
1501 * with both PLLs disabled, or we risk losing DPIO and
1502 * PLL synchronization.
1504 val
= I915_READ(DISPLAY_PHY_CONTROL
);
1505 I915_WRITE(DISPLAY_PHY_CONTROL
,
1506 PHY_COM_LANE_RESET_DEASSERT(phy
, val
));
1511 * If DPIO has already been reset, e.g. by BIOS, just skip all
1514 if (I915_READ(DPIO_CTL
) & DPIO_CMNRST
)
1518 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519 * Need to assert and de-assert PHY SB reset by gating the
1520 * common lane power, then un-gating it.
1521 * Simply ungating isn't enough to reset the PHY enough to get
1522 * ports and lanes running.
1524 __vlv_set_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
,
1526 __vlv_set_power_well(dev_priv
, PUNIT_POWER_WELL_DPIO_CMN_BC
,
1531 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1533 struct drm_device
*dev
= crtc
->base
.dev
;
1534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1535 int reg
= DPLL(crtc
->pipe
);
1536 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1538 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1540 /* No really, not for ILK+ */
1541 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1543 /* PLL is protected by panel, make sure we can write it */
1544 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1545 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1547 I915_WRITE(reg
, dpll
);
1551 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1554 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1555 POSTING_READ(DPLL_MD(crtc
->pipe
));
1557 /* We do this three times for luck */
1558 I915_WRITE(reg
, dpll
);
1560 udelay(150); /* wait for warmup */
1561 I915_WRITE(reg
, dpll
);
1563 udelay(150); /* wait for warmup */
1564 I915_WRITE(reg
, dpll
);
1566 udelay(150); /* wait for warmup */
1569 static void chv_enable_pll(struct intel_crtc
*crtc
)
1571 struct drm_device
*dev
= crtc
->base
.dev
;
1572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1573 int pipe
= crtc
->pipe
;
1574 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1577 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1579 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1581 mutex_lock(&dev_priv
->dpio_lock
);
1583 /* Enable back the 10bit clock to display controller */
1584 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1585 tmp
|= DPIO_DCLKP_EN
;
1586 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1589 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1594 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1596 /* Check PLL is locked */
1597 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1598 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1600 /* not sure when this should be written */
1601 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1602 POSTING_READ(DPLL_MD(pipe
));
1604 mutex_unlock(&dev_priv
->dpio_lock
);
1607 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1609 struct drm_device
*dev
= crtc
->base
.dev
;
1610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1611 int reg
= DPLL(crtc
->pipe
);
1612 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1614 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1616 /* No really, not for ILK+ */
1617 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1619 /* PLL is protected by panel, make sure we can write it */
1620 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1621 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1623 I915_WRITE(reg
, dpll
);
1625 /* Wait for the clocks to stabilize. */
1629 if (INTEL_INFO(dev
)->gen
>= 4) {
1630 I915_WRITE(DPLL_MD(crtc
->pipe
),
1631 crtc
->config
.dpll_hw_state
.dpll_md
);
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1636 * So write it again.
1638 I915_WRITE(reg
, dpll
);
1641 /* We do this three times for luck */
1642 I915_WRITE(reg
, dpll
);
1644 udelay(150); /* wait for warmup */
1645 I915_WRITE(reg
, dpll
);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg
, dpll
);
1650 udelay(150); /* wait for warmup */
1654 * i9xx_disable_pll - disable a PLL
1655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 * Note! This is for pre-ILK only.
1662 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv
, pipe
);
1671 I915_WRITE(DPLL(pipe
), 0);
1672 POSTING_READ(DPLL(pipe
));
1675 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv
, pipe
);
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1687 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1688 I915_WRITE(DPLL(pipe
), val
);
1689 POSTING_READ(DPLL(pipe
));
1693 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1695 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv
, pipe
);
1701 /* Set PLL en = 0 */
1702 val
= DPLL_SSC_REF_CLOCK_CHV
;
1704 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1705 I915_WRITE(DPLL(pipe
), val
);
1706 POSTING_READ(DPLL(pipe
));
1708 mutex_lock(&dev_priv
->dpio_lock
);
1710 /* Disable 10bit clock to display controller */
1711 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1712 val
&= ~DPIO_DCLKP_EN
;
1713 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1715 mutex_unlock(&dev_priv
->dpio_lock
);
1718 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1719 struct intel_digital_port
*dport
)
1724 switch (dport
->port
) {
1726 port_mask
= DPLL_PORTB_READY_MASK
;
1730 port_mask
= DPLL_PORTC_READY_MASK
;
1734 port_mask
= DPLL_PORTD_READY_MASK
;
1735 dpll_reg
= DPIO_PHY_STATUS
;
1741 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1742 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1743 port_name(dport
->port
), I915_READ(dpll_reg
));
1746 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1748 struct drm_device
*dev
= crtc
->base
.dev
;
1749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1750 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1752 WARN_ON(!pll
->refcount
);
1753 if (pll
->active
== 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1756 assert_shared_dpll_disabled(dev_priv
, pll
);
1758 pll
->mode_set(dev_priv
, pll
);
1763 * intel_enable_shared_dpll - enable PCH PLL
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1770 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1772 struct drm_device
*dev
= crtc
->base
.dev
;
1773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1774 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1776 if (WARN_ON(pll
== NULL
))
1779 if (WARN_ON(pll
->refcount
== 0))
1782 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1783 pll
->name
, pll
->active
, pll
->on
,
1784 crtc
->base
.base
.id
);
1786 if (pll
->active
++) {
1788 assert_shared_dpll_enabled(dev_priv
, pll
);
1793 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1794 pll
->enable(dev_priv
, pll
);
1798 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1800 struct drm_device
*dev
= crtc
->base
.dev
;
1801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1802 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1804 /* PCH only available on ILK+ */
1805 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1806 if (WARN_ON(pll
== NULL
))
1809 if (WARN_ON(pll
->refcount
== 0))
1812 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1813 pll
->name
, pll
->active
, pll
->on
,
1814 crtc
->base
.base
.id
);
1816 if (WARN_ON(pll
->active
== 0)) {
1817 assert_shared_dpll_disabled(dev_priv
, pll
);
1821 assert_shared_dpll_enabled(dev_priv
, pll
);
1826 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1827 pll
->disable(dev_priv
, pll
);
1831 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1834 struct drm_device
*dev
= dev_priv
->dev
;
1835 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1836 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1837 uint32_t reg
, val
, pipeconf_val
;
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1842 /* Make sure PCH DPLL is enabled */
1843 assert_shared_dpll_enabled(dev_priv
,
1844 intel_crtc_to_shared_dpll(intel_crtc
));
1846 /* FDI must be feeding us bits for PCH ports */
1847 assert_fdi_tx_enabled(dev_priv
, pipe
);
1848 assert_fdi_rx_enabled(dev_priv
, pipe
);
1850 if (HAS_PCH_CPT(dev
)) {
1851 /* Workaround: Set the timing override bit before enabling the
1852 * pch transcoder. */
1853 reg
= TRANS_CHICKEN2(pipe
);
1854 val
= I915_READ(reg
);
1855 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1856 I915_WRITE(reg
, val
);
1859 reg
= PCH_TRANSCONF(pipe
);
1860 val
= I915_READ(reg
);
1861 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1863 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1865 * make the BPC in transcoder be consistent with
1866 * that in pipeconf reg.
1868 val
&= ~PIPECONF_BPC_MASK
;
1869 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1872 val
&= ~TRANS_INTERLACE_MASK
;
1873 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1874 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1875 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1876 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1878 val
|= TRANS_INTERLACED
;
1880 val
|= TRANS_PROGRESSIVE
;
1882 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1883 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1884 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1887 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1888 enum transcoder cpu_transcoder
)
1890 u32 val
, pipeconf_val
;
1892 /* PCH only available on ILK+ */
1893 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1895 /* FDI must be feeding us bits for PCH ports */
1896 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1897 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1899 /* Workaround: set timing override bit. */
1900 val
= I915_READ(_TRANSA_CHICKEN2
);
1901 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1902 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1905 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1907 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1908 PIPECONF_INTERLACED_ILK
)
1909 val
|= TRANS_INTERLACED
;
1911 val
|= TRANS_PROGRESSIVE
;
1913 I915_WRITE(LPT_TRANSCONF
, val
);
1914 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1915 DRM_ERROR("Failed to enable PCH transcoder\n");
1918 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1921 struct drm_device
*dev
= dev_priv
->dev
;
1924 /* FDI relies on the transcoder */
1925 assert_fdi_tx_disabled(dev_priv
, pipe
);
1926 assert_fdi_rx_disabled(dev_priv
, pipe
);
1928 /* Ports must be off as well */
1929 assert_pch_ports_disabled(dev_priv
, pipe
);
1931 reg
= PCH_TRANSCONF(pipe
);
1932 val
= I915_READ(reg
);
1933 val
&= ~TRANS_ENABLE
;
1934 I915_WRITE(reg
, val
);
1935 /* wait for PCH transcoder off, transcoder state */
1936 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1937 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1939 if (!HAS_PCH_IBX(dev
)) {
1940 /* Workaround: Clear the timing override chicken bit again. */
1941 reg
= TRANS_CHICKEN2(pipe
);
1942 val
= I915_READ(reg
);
1943 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1944 I915_WRITE(reg
, val
);
1948 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1952 val
= I915_READ(LPT_TRANSCONF
);
1953 val
&= ~TRANS_ENABLE
;
1954 I915_WRITE(LPT_TRANSCONF
, val
);
1955 /* wait for PCH transcoder off, transcoder state */
1956 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1957 DRM_ERROR("Failed to disable PCH transcoder\n");
1959 /* Workaround: clear timing override bit. */
1960 val
= I915_READ(_TRANSA_CHICKEN2
);
1961 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1962 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1966 * intel_enable_pipe - enable a pipe, asserting requirements
1967 * @crtc: crtc responsible for the pipe
1969 * Enable @crtc's pipe, making sure that various hardware specific requirements
1970 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1972 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1974 struct drm_device
*dev
= crtc
->base
.dev
;
1975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1976 enum pipe pipe
= crtc
->pipe
;
1977 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1979 enum pipe pch_transcoder
;
1983 assert_planes_disabled(dev_priv
, pipe
);
1984 assert_cursor_disabled(dev_priv
, pipe
);
1985 assert_sprites_disabled(dev_priv
, pipe
);
1987 if (HAS_PCH_LPT(dev_priv
->dev
))
1988 pch_transcoder
= TRANSCODER_A
;
1990 pch_transcoder
= pipe
;
1993 * A pipe without a PLL won't actually be able to drive bits from
1994 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1997 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1998 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
1999 assert_dsi_pll_enabled(dev_priv
);
2001 assert_pll_enabled(dev_priv
, pipe
);
2003 if (crtc
->config
.has_pch_encoder
) {
2004 /* if driving the PCH, we need FDI enabled */
2005 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2006 assert_fdi_tx_pll_enabled(dev_priv
,
2007 (enum pipe
) cpu_transcoder
);
2009 /* FIXME: assert CPU port conditions for SNB+ */
2012 reg
= PIPECONF(cpu_transcoder
);
2013 val
= I915_READ(reg
);
2014 if (val
& PIPECONF_ENABLE
) {
2015 WARN_ON(!(pipe
== PIPE_A
&&
2016 dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
2020 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2025 * intel_disable_pipe - disable a pipe, asserting requirements
2026 * @dev_priv: i915 private structure
2027 * @pipe: pipe to disable
2029 * Disable @pipe, making sure that various hardware specific requirements
2030 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2032 * @pipe should be %PIPE_A or %PIPE_B.
2034 * Will wait until the pipe has shut down before returning.
2036 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
2039 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2045 * Make sure planes won't keep trying to pump pixels to us,
2046 * or we might hang the display.
2048 assert_planes_disabled(dev_priv
, pipe
);
2049 assert_cursor_disabled(dev_priv
, pipe
);
2050 assert_sprites_disabled(dev_priv
, pipe
);
2052 /* Don't disable pipe A or pipe A PLLs if needed */
2053 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2056 reg
= PIPECONF(cpu_transcoder
);
2057 val
= I915_READ(reg
);
2058 if ((val
& PIPECONF_ENABLE
) == 0)
2061 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
2062 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
2066 * Plane regs are double buffered, going from enabled->disabled needs a
2067 * trigger in order to latch. The display address reg provides this.
2069 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2072 struct drm_device
*dev
= dev_priv
->dev
;
2073 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2075 I915_WRITE(reg
, I915_READ(reg
));
2080 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2081 * @dev_priv: i915 private structure
2082 * @plane: plane to enable
2083 * @pipe: pipe being fed
2085 * Enable @plane on @pipe, making sure that @pipe is running first.
2087 static void intel_enable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2088 enum plane plane
, enum pipe pipe
)
2090 struct drm_device
*dev
= dev_priv
->dev
;
2091 struct intel_crtc
*intel_crtc
=
2092 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2096 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2097 assert_pipe_enabled(dev_priv
, pipe
);
2099 if (intel_crtc
->primary_enabled
)
2102 intel_crtc
->primary_enabled
= true;
2104 reg
= DSPCNTR(plane
);
2105 val
= I915_READ(reg
);
2106 WARN_ON(val
& DISPLAY_PLANE_ENABLE
);
2108 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
2109 intel_flush_primary_plane(dev_priv
, plane
);
2112 * BDW signals flip done immediately if the plane
2113 * is disabled, even if the plane enable is already
2114 * armed to occur at the next vblank :(
2116 if (IS_BROADWELL(dev
))
2117 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2121 * intel_disable_primary_hw_plane - disable the primary hardware plane
2122 * @dev_priv: i915 private structure
2123 * @plane: plane to disable
2124 * @pipe: pipe consuming the data
2126 * Disable @plane; should be an independent operation.
2128 static void intel_disable_primary_hw_plane(struct drm_i915_private
*dev_priv
,
2129 enum plane plane
, enum pipe pipe
)
2131 struct intel_crtc
*intel_crtc
=
2132 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
2136 if (!intel_crtc
->primary_enabled
)
2139 intel_crtc
->primary_enabled
= false;
2141 reg
= DSPCNTR(plane
);
2142 val
= I915_READ(reg
);
2143 WARN_ON((val
& DISPLAY_PLANE_ENABLE
) == 0);
2145 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
2146 intel_flush_primary_plane(dev_priv
, plane
);
2149 static bool need_vtd_wa(struct drm_device
*dev
)
2151 #ifdef CONFIG_INTEL_IOMMU
2152 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2158 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2162 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2163 return ALIGN(height
, tile_height
);
2167 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2168 struct drm_i915_gem_object
*obj
,
2169 struct intel_engine_cs
*pipelined
)
2171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2175 switch (obj
->tiling_mode
) {
2176 case I915_TILING_NONE
:
2177 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2178 alignment
= 128 * 1024;
2179 else if (INTEL_INFO(dev
)->gen
>= 4)
2180 alignment
= 4 * 1024;
2182 alignment
= 64 * 1024;
2185 /* pin() will align the object as required by fence */
2189 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2195 /* Note that the w/a also requires 64 PTE of padding following the
2196 * bo. We currently fill all unused PTE with the shadow page and so
2197 * we should always have valid PTE following the scanout preventing
2200 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2201 alignment
= 256 * 1024;
2203 dev_priv
->mm
.interruptible
= false;
2204 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2206 goto err_interruptible
;
2208 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2209 * fence, whereas 965+ only requires a fence if using
2210 * framebuffer compression. For simplicity, we always install
2211 * a fence as the cost is not that onerous.
2213 ret
= i915_gem_object_get_fence(obj
);
2217 i915_gem_object_pin_fence(obj
);
2219 dev_priv
->mm
.interruptible
= true;
2223 i915_gem_object_unpin_from_display_plane(obj
);
2225 dev_priv
->mm
.interruptible
= true;
2229 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2231 i915_gem_object_unpin_fence(obj
);
2232 i915_gem_object_unpin_from_display_plane(obj
);
2235 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2236 * is assumed to be a power-of-two. */
2237 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2238 unsigned int tiling_mode
,
2242 if (tiling_mode
!= I915_TILING_NONE
) {
2243 unsigned int tile_rows
, tiles
;
2248 tiles
= *x
/ (512/cpp
);
2251 return tile_rows
* pitch
* 8 + tiles
* 4096;
2253 unsigned int offset
;
2255 offset
= *y
* pitch
+ *x
* cpp
;
2257 *x
= (offset
& 4095) / cpp
;
2258 return offset
& -4096;
2262 int intel_format_to_fourcc(int format
)
2265 case DISPPLANE_8BPP
:
2266 return DRM_FORMAT_C8
;
2267 case DISPPLANE_BGRX555
:
2268 return DRM_FORMAT_XRGB1555
;
2269 case DISPPLANE_BGRX565
:
2270 return DRM_FORMAT_RGB565
;
2272 case DISPPLANE_BGRX888
:
2273 return DRM_FORMAT_XRGB8888
;
2274 case DISPPLANE_RGBX888
:
2275 return DRM_FORMAT_XBGR8888
;
2276 case DISPPLANE_BGRX101010
:
2277 return DRM_FORMAT_XRGB2101010
;
2278 case DISPPLANE_RGBX101010
:
2279 return DRM_FORMAT_XBGR2101010
;
2283 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2284 struct intel_plane_config
*plane_config
)
2286 struct drm_device
*dev
= crtc
->base
.dev
;
2287 struct drm_i915_gem_object
*obj
= NULL
;
2288 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2289 u32 base
= plane_config
->base
;
2291 if (plane_config
->size
== 0)
2294 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2295 plane_config
->size
);
2299 if (plane_config
->tiled
) {
2300 obj
->tiling_mode
= I915_TILING_X
;
2301 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2304 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2305 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2306 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2307 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2309 mutex_lock(&dev
->struct_mutex
);
2311 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2313 DRM_DEBUG_KMS("intel fb init failed\n");
2317 mutex_unlock(&dev
->struct_mutex
);
2319 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2323 drm_gem_object_unreference(&obj
->base
);
2324 mutex_unlock(&dev
->struct_mutex
);
2328 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2329 struct intel_plane_config
*plane_config
)
2331 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2333 struct intel_crtc
*i
;
2334 struct intel_framebuffer
*fb
;
2336 if (!intel_crtc
->base
.primary
->fb
)
2339 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2342 kfree(intel_crtc
->base
.primary
->fb
);
2343 intel_crtc
->base
.primary
->fb
= NULL
;
2346 * Failed to alloc the obj, check to see if we should share
2347 * an fb with another CRTC instead
2349 for_each_crtc(dev
, c
) {
2350 i
= to_intel_crtc(c
);
2352 if (c
== &intel_crtc
->base
)
2355 if (!i
->active
|| !c
->primary
->fb
)
2358 fb
= to_intel_framebuffer(c
->primary
->fb
);
2359 if (i915_gem_obj_ggtt_offset(fb
->obj
) == plane_config
->base
) {
2360 drm_framebuffer_reference(c
->primary
->fb
);
2361 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2367 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2368 struct drm_framebuffer
*fb
,
2371 struct drm_device
*dev
= crtc
->dev
;
2372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2373 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2374 struct intel_framebuffer
*intel_fb
;
2375 struct drm_i915_gem_object
*obj
;
2376 int plane
= intel_crtc
->plane
;
2377 unsigned long linear_offset
;
2381 intel_fb
= to_intel_framebuffer(fb
);
2382 obj
= intel_fb
->obj
;
2384 reg
= DSPCNTR(plane
);
2385 dspcntr
= I915_READ(reg
);
2386 /* Mask out pixel format bits in case we change it */
2387 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2388 switch (fb
->pixel_format
) {
2390 dspcntr
|= DISPPLANE_8BPP
;
2392 case DRM_FORMAT_XRGB1555
:
2393 case DRM_FORMAT_ARGB1555
:
2394 dspcntr
|= DISPPLANE_BGRX555
;
2396 case DRM_FORMAT_RGB565
:
2397 dspcntr
|= DISPPLANE_BGRX565
;
2399 case DRM_FORMAT_XRGB8888
:
2400 case DRM_FORMAT_ARGB8888
:
2401 dspcntr
|= DISPPLANE_BGRX888
;
2403 case DRM_FORMAT_XBGR8888
:
2404 case DRM_FORMAT_ABGR8888
:
2405 dspcntr
|= DISPPLANE_RGBX888
;
2407 case DRM_FORMAT_XRGB2101010
:
2408 case DRM_FORMAT_ARGB2101010
:
2409 dspcntr
|= DISPPLANE_BGRX101010
;
2411 case DRM_FORMAT_XBGR2101010
:
2412 case DRM_FORMAT_ABGR2101010
:
2413 dspcntr
|= DISPPLANE_RGBX101010
;
2419 if (INTEL_INFO(dev
)->gen
>= 4) {
2420 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2421 dspcntr
|= DISPPLANE_TILED
;
2423 dspcntr
&= ~DISPPLANE_TILED
;
2427 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2429 I915_WRITE(reg
, dspcntr
);
2431 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2433 if (INTEL_INFO(dev
)->gen
>= 4) {
2434 intel_crtc
->dspaddr_offset
=
2435 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2436 fb
->bits_per_pixel
/ 8,
2438 linear_offset
-= intel_crtc
->dspaddr_offset
;
2440 intel_crtc
->dspaddr_offset
= linear_offset
;
2443 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2444 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2446 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2447 if (INTEL_INFO(dev
)->gen
>= 4) {
2448 I915_WRITE(DSPSURF(plane
),
2449 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2450 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2451 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2453 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2457 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2458 struct drm_framebuffer
*fb
,
2461 struct drm_device
*dev
= crtc
->dev
;
2462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2463 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2464 struct intel_framebuffer
*intel_fb
;
2465 struct drm_i915_gem_object
*obj
;
2466 int plane
= intel_crtc
->plane
;
2467 unsigned long linear_offset
;
2471 intel_fb
= to_intel_framebuffer(fb
);
2472 obj
= intel_fb
->obj
;
2474 reg
= DSPCNTR(plane
);
2475 dspcntr
= I915_READ(reg
);
2476 /* Mask out pixel format bits in case we change it */
2477 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2478 switch (fb
->pixel_format
) {
2480 dspcntr
|= DISPPLANE_8BPP
;
2482 case DRM_FORMAT_RGB565
:
2483 dspcntr
|= DISPPLANE_BGRX565
;
2485 case DRM_FORMAT_XRGB8888
:
2486 case DRM_FORMAT_ARGB8888
:
2487 dspcntr
|= DISPPLANE_BGRX888
;
2489 case DRM_FORMAT_XBGR8888
:
2490 case DRM_FORMAT_ABGR8888
:
2491 dspcntr
|= DISPPLANE_RGBX888
;
2493 case DRM_FORMAT_XRGB2101010
:
2494 case DRM_FORMAT_ARGB2101010
:
2495 dspcntr
|= DISPPLANE_BGRX101010
;
2497 case DRM_FORMAT_XBGR2101010
:
2498 case DRM_FORMAT_ABGR2101010
:
2499 dspcntr
|= DISPPLANE_RGBX101010
;
2505 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2506 dspcntr
|= DISPPLANE_TILED
;
2508 dspcntr
&= ~DISPPLANE_TILED
;
2510 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2511 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2513 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2515 I915_WRITE(reg
, dspcntr
);
2517 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2518 intel_crtc
->dspaddr_offset
=
2519 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2520 fb
->bits_per_pixel
/ 8,
2522 linear_offset
-= intel_crtc
->dspaddr_offset
;
2524 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2525 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2527 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2528 I915_WRITE(DSPSURF(plane
),
2529 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2530 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2531 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2533 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2534 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2539 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2541 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2542 int x
, int y
, enum mode_set_atomic state
)
2544 struct drm_device
*dev
= crtc
->dev
;
2545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 if (dev_priv
->display
.disable_fbc
)
2548 dev_priv
->display
.disable_fbc(dev
);
2549 intel_increase_pllclock(crtc
);
2551 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2556 void intel_display_handle_reset(struct drm_device
*dev
)
2558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2559 struct drm_crtc
*crtc
;
2562 * Flips in the rings have been nuked by the reset,
2563 * so complete all pending flips so that user space
2564 * will get its events and not get stuck.
2566 * Also update the base address of all primary
2567 * planes to the the last fb to make sure we're
2568 * showing the correct fb after a reset.
2570 * Need to make two loops over the crtcs so that we
2571 * don't try to grab a crtc mutex before the
2572 * pending_flip_queue really got woken up.
2575 for_each_crtc(dev
, crtc
) {
2576 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2577 enum plane plane
= intel_crtc
->plane
;
2579 intel_prepare_page_flip(dev
, plane
);
2580 intel_finish_page_flip_plane(dev
, plane
);
2583 for_each_crtc(dev
, crtc
) {
2584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2586 drm_modeset_lock(&crtc
->mutex
, NULL
);
2588 * FIXME: Once we have proper support for primary planes (and
2589 * disabling them without disabling the entire crtc) allow again
2590 * a NULL crtc->primary->fb.
2592 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2593 dev_priv
->display
.update_primary_plane(crtc
,
2597 drm_modeset_unlock(&crtc
->mutex
);
2602 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2604 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2605 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2606 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2609 /* Big Hammer, we also need to ensure that any pending
2610 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2611 * current scanout is retired before unpinning the old
2614 * This should only fail upon a hung GPU, in which case we
2615 * can safely continue.
2617 dev_priv
->mm
.interruptible
= false;
2618 ret
= i915_gem_object_finish_gpu(obj
);
2619 dev_priv
->mm
.interruptible
= was_interruptible
;
2624 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2626 struct drm_device
*dev
= crtc
->dev
;
2627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2629 unsigned long flags
;
2632 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2633 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2636 spin_lock_irqsave(&dev
->event_lock
, flags
);
2637 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2638 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2644 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2645 struct drm_framebuffer
*fb
)
2647 struct drm_device
*dev
= crtc
->dev
;
2648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2650 struct drm_framebuffer
*old_fb
;
2653 if (intel_crtc_has_pending_flip(crtc
)) {
2654 DRM_ERROR("pipe is still busy with an old pageflip\n");
2660 DRM_ERROR("No FB bound\n");
2664 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2665 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2666 plane_name(intel_crtc
->plane
),
2667 INTEL_INFO(dev
)->num_pipes
);
2671 mutex_lock(&dev
->struct_mutex
);
2672 ret
= intel_pin_and_fence_fb_obj(dev
,
2673 to_intel_framebuffer(fb
)->obj
,
2675 mutex_unlock(&dev
->struct_mutex
);
2677 DRM_ERROR("pin & fence failed\n");
2682 * Update pipe size and adjust fitter if needed: the reason for this is
2683 * that in compute_mode_changes we check the native mode (not the pfit
2684 * mode) to see if we can flip rather than do a full mode set. In the
2685 * fastboot case, we'll flip, but if we don't update the pipesrc and
2686 * pfit state, we'll end up with a big fb scanned out into the wrong
2689 * To fix this properly, we need to hoist the checks up into
2690 * compute_mode_changes (or above), check the actual pfit state and
2691 * whether the platform allows pfit disable with pipe active, and only
2692 * then update the pipesrc and pfit state, even on the flip path.
2694 if (i915
.fastboot
) {
2695 const struct drm_display_mode
*adjusted_mode
=
2696 &intel_crtc
->config
.adjusted_mode
;
2698 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2699 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2700 (adjusted_mode
->crtc_vdisplay
- 1));
2701 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2702 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2703 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2704 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2705 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2706 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2708 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2709 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2712 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2714 old_fb
= crtc
->primary
->fb
;
2715 crtc
->primary
->fb
= fb
;
2720 if (intel_crtc
->active
&& old_fb
!= fb
)
2721 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2722 mutex_lock(&dev
->struct_mutex
);
2723 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2724 mutex_unlock(&dev
->struct_mutex
);
2727 mutex_lock(&dev
->struct_mutex
);
2728 intel_update_fbc(dev
);
2729 intel_edp_psr_update(dev
);
2730 mutex_unlock(&dev
->struct_mutex
);
2735 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2737 struct drm_device
*dev
= crtc
->dev
;
2738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2740 int pipe
= intel_crtc
->pipe
;
2743 /* enable normal train */
2744 reg
= FDI_TX_CTL(pipe
);
2745 temp
= I915_READ(reg
);
2746 if (IS_IVYBRIDGE(dev
)) {
2747 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2748 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2750 temp
&= ~FDI_LINK_TRAIN_NONE
;
2751 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2753 I915_WRITE(reg
, temp
);
2755 reg
= FDI_RX_CTL(pipe
);
2756 temp
= I915_READ(reg
);
2757 if (HAS_PCH_CPT(dev
)) {
2758 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2759 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2761 temp
&= ~FDI_LINK_TRAIN_NONE
;
2762 temp
|= FDI_LINK_TRAIN_NONE
;
2764 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2766 /* wait one idle pattern time */
2770 /* IVB wants error correction enabled */
2771 if (IS_IVYBRIDGE(dev
))
2772 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2773 FDI_FE_ERRC_ENABLE
);
2776 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2778 return crtc
->base
.enabled
&& crtc
->active
&&
2779 crtc
->config
.has_pch_encoder
;
2782 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 struct intel_crtc
*pipe_B_crtc
=
2786 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2787 struct intel_crtc
*pipe_C_crtc
=
2788 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2792 * When everything is off disable fdi C so that we could enable fdi B
2793 * with all lanes. Note that we don't care about enabled pipes without
2794 * an enabled pch encoder.
2796 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2797 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2798 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2799 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2801 temp
= I915_READ(SOUTH_CHICKEN1
);
2802 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2803 DRM_DEBUG_KMS("disabling fdi C rx\n");
2804 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2808 /* The FDI link training functions for ILK/Ibexpeak. */
2809 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2811 struct drm_device
*dev
= crtc
->dev
;
2812 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2813 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2814 int pipe
= intel_crtc
->pipe
;
2815 u32 reg
, temp
, tries
;
2817 /* FDI needs bits from pipe first */
2818 assert_pipe_enabled(dev_priv
, pipe
);
2820 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2822 reg
= FDI_RX_IMR(pipe
);
2823 temp
= I915_READ(reg
);
2824 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2825 temp
&= ~FDI_RX_BIT_LOCK
;
2826 I915_WRITE(reg
, temp
);
2830 /* enable CPU FDI TX and PCH FDI RX */
2831 reg
= FDI_TX_CTL(pipe
);
2832 temp
= I915_READ(reg
);
2833 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2834 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2835 temp
&= ~FDI_LINK_TRAIN_NONE
;
2836 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2837 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2839 reg
= FDI_RX_CTL(pipe
);
2840 temp
= I915_READ(reg
);
2841 temp
&= ~FDI_LINK_TRAIN_NONE
;
2842 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2843 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2848 /* Ironlake workaround, enable clock pointer after FDI enable*/
2849 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2850 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2851 FDI_RX_PHASE_SYNC_POINTER_EN
);
2853 reg
= FDI_RX_IIR(pipe
);
2854 for (tries
= 0; tries
< 5; tries
++) {
2855 temp
= I915_READ(reg
);
2856 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2858 if ((temp
& FDI_RX_BIT_LOCK
)) {
2859 DRM_DEBUG_KMS("FDI train 1 done.\n");
2860 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2865 DRM_ERROR("FDI train 1 fail!\n");
2868 reg
= FDI_TX_CTL(pipe
);
2869 temp
= I915_READ(reg
);
2870 temp
&= ~FDI_LINK_TRAIN_NONE
;
2871 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2872 I915_WRITE(reg
, temp
);
2874 reg
= FDI_RX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 temp
&= ~FDI_LINK_TRAIN_NONE
;
2877 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2878 I915_WRITE(reg
, temp
);
2883 reg
= FDI_RX_IIR(pipe
);
2884 for (tries
= 0; tries
< 5; tries
++) {
2885 temp
= I915_READ(reg
);
2886 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2888 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2889 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2890 DRM_DEBUG_KMS("FDI train 2 done.\n");
2895 DRM_ERROR("FDI train 2 fail!\n");
2897 DRM_DEBUG_KMS("FDI train done\n");
2901 static const int snb_b_fdi_train_param
[] = {
2902 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2903 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2904 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2905 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2908 /* The FDI link training functions for SNB/Cougarpoint. */
2909 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2911 struct drm_device
*dev
= crtc
->dev
;
2912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2914 int pipe
= intel_crtc
->pipe
;
2915 u32 reg
, temp
, i
, retry
;
2917 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2919 reg
= FDI_RX_IMR(pipe
);
2920 temp
= I915_READ(reg
);
2921 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2922 temp
&= ~FDI_RX_BIT_LOCK
;
2923 I915_WRITE(reg
, temp
);
2928 /* enable CPU FDI TX and PCH FDI RX */
2929 reg
= FDI_TX_CTL(pipe
);
2930 temp
= I915_READ(reg
);
2931 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2932 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2933 temp
&= ~FDI_LINK_TRAIN_NONE
;
2934 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2935 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2937 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2938 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2940 I915_WRITE(FDI_RX_MISC(pipe
),
2941 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2943 reg
= FDI_RX_CTL(pipe
);
2944 temp
= I915_READ(reg
);
2945 if (HAS_PCH_CPT(dev
)) {
2946 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2947 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2949 temp
&= ~FDI_LINK_TRAIN_NONE
;
2950 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2952 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2957 for (i
= 0; i
< 4; i
++) {
2958 reg
= FDI_TX_CTL(pipe
);
2959 temp
= I915_READ(reg
);
2960 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2961 temp
|= snb_b_fdi_train_param
[i
];
2962 I915_WRITE(reg
, temp
);
2967 for (retry
= 0; retry
< 5; retry
++) {
2968 reg
= FDI_RX_IIR(pipe
);
2969 temp
= I915_READ(reg
);
2970 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2971 if (temp
& FDI_RX_BIT_LOCK
) {
2972 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2973 DRM_DEBUG_KMS("FDI train 1 done.\n");
2982 DRM_ERROR("FDI train 1 fail!\n");
2985 reg
= FDI_TX_CTL(pipe
);
2986 temp
= I915_READ(reg
);
2987 temp
&= ~FDI_LINK_TRAIN_NONE
;
2988 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2990 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2992 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2994 I915_WRITE(reg
, temp
);
2996 reg
= FDI_RX_CTL(pipe
);
2997 temp
= I915_READ(reg
);
2998 if (HAS_PCH_CPT(dev
)) {
2999 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3000 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3002 temp
&= ~FDI_LINK_TRAIN_NONE
;
3003 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3005 I915_WRITE(reg
, temp
);
3010 for (i
= 0; i
< 4; i
++) {
3011 reg
= FDI_TX_CTL(pipe
);
3012 temp
= I915_READ(reg
);
3013 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3014 temp
|= snb_b_fdi_train_param
[i
];
3015 I915_WRITE(reg
, temp
);
3020 for (retry
= 0; retry
< 5; retry
++) {
3021 reg
= FDI_RX_IIR(pipe
);
3022 temp
= I915_READ(reg
);
3023 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3024 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3025 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3026 DRM_DEBUG_KMS("FDI train 2 done.\n");
3035 DRM_ERROR("FDI train 2 fail!\n");
3037 DRM_DEBUG_KMS("FDI train done.\n");
3040 /* Manual link training for Ivy Bridge A0 parts */
3041 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3043 struct drm_device
*dev
= crtc
->dev
;
3044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3045 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3046 int pipe
= intel_crtc
->pipe
;
3047 u32 reg
, temp
, i
, j
;
3049 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3051 reg
= FDI_RX_IMR(pipe
);
3052 temp
= I915_READ(reg
);
3053 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3054 temp
&= ~FDI_RX_BIT_LOCK
;
3055 I915_WRITE(reg
, temp
);
3060 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3061 I915_READ(FDI_RX_IIR(pipe
)));
3063 /* Try each vswing and preemphasis setting twice before moving on */
3064 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3065 /* disable first in case we need to retry */
3066 reg
= FDI_TX_CTL(pipe
);
3067 temp
= I915_READ(reg
);
3068 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3069 temp
&= ~FDI_TX_ENABLE
;
3070 I915_WRITE(reg
, temp
);
3072 reg
= FDI_RX_CTL(pipe
);
3073 temp
= I915_READ(reg
);
3074 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3075 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3076 temp
&= ~FDI_RX_ENABLE
;
3077 I915_WRITE(reg
, temp
);
3079 /* enable CPU FDI TX and PCH FDI RX */
3080 reg
= FDI_TX_CTL(pipe
);
3081 temp
= I915_READ(reg
);
3082 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3083 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3084 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3085 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3086 temp
|= snb_b_fdi_train_param
[j
/2];
3087 temp
|= FDI_COMPOSITE_SYNC
;
3088 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3090 I915_WRITE(FDI_RX_MISC(pipe
),
3091 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3093 reg
= FDI_RX_CTL(pipe
);
3094 temp
= I915_READ(reg
);
3095 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3096 temp
|= FDI_COMPOSITE_SYNC
;
3097 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3100 udelay(1); /* should be 0.5us */
3102 for (i
= 0; i
< 4; i
++) {
3103 reg
= FDI_RX_IIR(pipe
);
3104 temp
= I915_READ(reg
);
3105 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3107 if (temp
& FDI_RX_BIT_LOCK
||
3108 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3109 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3110 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3114 udelay(1); /* should be 0.5us */
3117 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3122 reg
= FDI_TX_CTL(pipe
);
3123 temp
= I915_READ(reg
);
3124 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3125 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3126 I915_WRITE(reg
, temp
);
3128 reg
= FDI_RX_CTL(pipe
);
3129 temp
= I915_READ(reg
);
3130 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3131 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3132 I915_WRITE(reg
, temp
);
3135 udelay(2); /* should be 1.5us */
3137 for (i
= 0; i
< 4; i
++) {
3138 reg
= FDI_RX_IIR(pipe
);
3139 temp
= I915_READ(reg
);
3140 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3142 if (temp
& FDI_RX_SYMBOL_LOCK
||
3143 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3144 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3145 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3149 udelay(2); /* should be 1.5us */
3152 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3156 DRM_DEBUG_KMS("FDI train done.\n");
3159 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3161 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3163 int pipe
= intel_crtc
->pipe
;
3167 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3168 reg
= FDI_RX_CTL(pipe
);
3169 temp
= I915_READ(reg
);
3170 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3171 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3172 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3173 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3178 /* Switch from Rawclk to PCDclk */
3179 temp
= I915_READ(reg
);
3180 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3185 /* Enable CPU FDI TX PLL, always on for Ironlake */
3186 reg
= FDI_TX_CTL(pipe
);
3187 temp
= I915_READ(reg
);
3188 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3189 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3196 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3198 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3200 int pipe
= intel_crtc
->pipe
;
3203 /* Switch from PCDclk to Rawclk */
3204 reg
= FDI_RX_CTL(pipe
);
3205 temp
= I915_READ(reg
);
3206 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3208 /* Disable CPU FDI TX PLL */
3209 reg
= FDI_TX_CTL(pipe
);
3210 temp
= I915_READ(reg
);
3211 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3216 reg
= FDI_RX_CTL(pipe
);
3217 temp
= I915_READ(reg
);
3218 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3220 /* Wait for the clocks to turn off. */
3225 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3227 struct drm_device
*dev
= crtc
->dev
;
3228 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3229 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3230 int pipe
= intel_crtc
->pipe
;
3233 /* disable CPU FDI tx and PCH FDI rx */
3234 reg
= FDI_TX_CTL(pipe
);
3235 temp
= I915_READ(reg
);
3236 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3239 reg
= FDI_RX_CTL(pipe
);
3240 temp
= I915_READ(reg
);
3241 temp
&= ~(0x7 << 16);
3242 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3243 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3248 /* Ironlake workaround, disable clock pointer after downing FDI */
3249 if (HAS_PCH_IBX(dev
))
3250 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3252 /* still set train pattern 1 */
3253 reg
= FDI_TX_CTL(pipe
);
3254 temp
= I915_READ(reg
);
3255 temp
&= ~FDI_LINK_TRAIN_NONE
;
3256 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3257 I915_WRITE(reg
, temp
);
3259 reg
= FDI_RX_CTL(pipe
);
3260 temp
= I915_READ(reg
);
3261 if (HAS_PCH_CPT(dev
)) {
3262 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3263 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3265 temp
&= ~FDI_LINK_TRAIN_NONE
;
3266 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3268 /* BPC in FDI rx is consistent with that in PIPECONF */
3269 temp
&= ~(0x07 << 16);
3270 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3271 I915_WRITE(reg
, temp
);
3277 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3279 struct intel_crtc
*crtc
;
3281 /* Note that we don't need to be called with mode_config.lock here
3282 * as our list of CRTC objects is static for the lifetime of the
3283 * device and so cannot disappear as we iterate. Similarly, we can
3284 * happily treat the predicates as racy, atomic checks as userspace
3285 * cannot claim and pin a new fb without at least acquring the
3286 * struct_mutex and so serialising with us.
3288 for_each_intel_crtc(dev
, crtc
) {
3289 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3292 if (crtc
->unpin_work
)
3293 intel_wait_for_vblank(dev
, crtc
->pipe
);
3301 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3303 struct drm_device
*dev
= crtc
->dev
;
3304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3306 if (crtc
->primary
->fb
== NULL
)
3309 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3311 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3312 !intel_crtc_has_pending_flip(crtc
),
3315 mutex_lock(&dev
->struct_mutex
);
3316 intel_finish_fb(crtc
->primary
->fb
);
3317 mutex_unlock(&dev
->struct_mutex
);
3320 /* Program iCLKIP clock to the desired frequency */
3321 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3323 struct drm_device
*dev
= crtc
->dev
;
3324 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3325 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3326 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3329 mutex_lock(&dev_priv
->dpio_lock
);
3331 /* It is necessary to ungate the pixclk gate prior to programming
3332 * the divisors, and gate it back when it is done.
3334 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3336 /* Disable SSCCTL */
3337 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3338 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3342 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3343 if (clock
== 20000) {
3348 /* The iCLK virtual clock root frequency is in MHz,
3349 * but the adjusted_mode->crtc_clock in in KHz. To get the
3350 * divisors, it is necessary to divide one by another, so we
3351 * convert the virtual clock precision to KHz here for higher
3354 u32 iclk_virtual_root_freq
= 172800 * 1000;
3355 u32 iclk_pi_range
= 64;
3356 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3358 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3359 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3360 pi_value
= desired_divisor
% iclk_pi_range
;
3363 divsel
= msb_divisor_value
- 2;
3364 phaseinc
= pi_value
;
3367 /* This should not happen with any sane values */
3368 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3369 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3370 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3371 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3373 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3380 /* Program SSCDIVINTPHASE6 */
3381 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3382 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3383 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3384 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3385 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3386 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3387 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3388 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3390 /* Program SSCAUXDIV */
3391 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3392 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3393 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3394 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3396 /* Enable modulator and associated divider */
3397 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3398 temp
&= ~SBI_SSCCTL_DISABLE
;
3399 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3401 /* Wait for initialization time */
3404 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3406 mutex_unlock(&dev_priv
->dpio_lock
);
3409 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3410 enum pipe pch_transcoder
)
3412 struct drm_device
*dev
= crtc
->base
.dev
;
3413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3416 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3417 I915_READ(HTOTAL(cpu_transcoder
)));
3418 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3419 I915_READ(HBLANK(cpu_transcoder
)));
3420 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3421 I915_READ(HSYNC(cpu_transcoder
)));
3423 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3424 I915_READ(VTOTAL(cpu_transcoder
)));
3425 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3426 I915_READ(VBLANK(cpu_transcoder
)));
3427 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3428 I915_READ(VSYNC(cpu_transcoder
)));
3429 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3430 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3433 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3438 temp
= I915_READ(SOUTH_CHICKEN1
);
3439 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3442 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3443 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3445 temp
|= FDI_BC_BIFURCATION_SELECT
;
3446 DRM_DEBUG_KMS("enabling fdi C rx\n");
3447 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3448 POSTING_READ(SOUTH_CHICKEN1
);
3451 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3453 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3456 switch (intel_crtc
->pipe
) {
3460 if (intel_crtc
->config
.fdi_lanes
> 2)
3461 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3463 cpt_enable_fdi_bc_bifurcation(dev
);
3467 cpt_enable_fdi_bc_bifurcation(dev
);
3476 * Enable PCH resources required for PCH ports:
3478 * - FDI training & RX/TX
3479 * - update transcoder timings
3480 * - DP transcoding bits
3483 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3485 struct drm_device
*dev
= crtc
->dev
;
3486 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3488 int pipe
= intel_crtc
->pipe
;
3491 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3493 if (IS_IVYBRIDGE(dev
))
3494 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3496 /* Write the TU size bits before fdi link training, so that error
3497 * detection works. */
3498 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3499 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3501 /* For PCH output, training FDI link */
3502 dev_priv
->display
.fdi_link_train(crtc
);
3504 /* We need to program the right clock selection before writing the pixel
3505 * mutliplier into the DPLL. */
3506 if (HAS_PCH_CPT(dev
)) {
3509 temp
= I915_READ(PCH_DPLL_SEL
);
3510 temp
|= TRANS_DPLL_ENABLE(pipe
);
3511 sel
= TRANS_DPLLB_SEL(pipe
);
3512 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3516 I915_WRITE(PCH_DPLL_SEL
, temp
);
3519 /* XXX: pch pll's can be enabled any time before we enable the PCH
3520 * transcoder, and we actually should do this to not upset any PCH
3521 * transcoder that already use the clock when we share it.
3523 * Note that enable_shared_dpll tries to do the right thing, but
3524 * get_shared_dpll unconditionally resets the pll - we need that to have
3525 * the right LVDS enable sequence. */
3526 intel_enable_shared_dpll(intel_crtc
);
3528 /* set transcoder timing, panel must allow it */
3529 assert_panel_unlocked(dev_priv
, pipe
);
3530 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3532 intel_fdi_normal_train(crtc
);
3534 /* For PCH DP, enable TRANS_DP_CTL */
3535 if (HAS_PCH_CPT(dev
) &&
3536 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3537 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3538 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3539 reg
= TRANS_DP_CTL(pipe
);
3540 temp
= I915_READ(reg
);
3541 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3542 TRANS_DP_SYNC_MASK
|
3544 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3545 TRANS_DP_ENH_FRAMING
);
3546 temp
|= bpc
<< 9; /* same format but at 11:9 */
3548 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3549 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3550 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3551 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3553 switch (intel_trans_dp_port_sel(crtc
)) {
3555 temp
|= TRANS_DP_PORT_SEL_B
;
3558 temp
|= TRANS_DP_PORT_SEL_C
;
3561 temp
|= TRANS_DP_PORT_SEL_D
;
3567 I915_WRITE(reg
, temp
);
3570 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3573 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3575 struct drm_device
*dev
= crtc
->dev
;
3576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3577 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3578 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3580 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3582 lpt_program_iclkip(crtc
);
3584 /* Set transcoder timing. */
3585 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3587 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3590 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3592 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3597 if (pll
->refcount
== 0) {
3598 WARN(1, "bad %s refcount\n", pll
->name
);
3602 if (--pll
->refcount
== 0) {
3604 WARN_ON(pll
->active
);
3607 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3610 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3612 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3613 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3614 enum intel_dpll_id i
;
3617 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3618 crtc
->base
.base
.id
, pll
->name
);
3619 intel_put_shared_dpll(crtc
);
3622 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3623 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3624 i
= (enum intel_dpll_id
) crtc
->pipe
;
3625 pll
= &dev_priv
->shared_dplls
[i
];
3627 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3628 crtc
->base
.base
.id
, pll
->name
);
3630 WARN_ON(pll
->refcount
);
3635 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3636 pll
= &dev_priv
->shared_dplls
[i
];
3638 /* Only want to check enabled timings first */
3639 if (pll
->refcount
== 0)
3642 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3643 sizeof(pll
->hw_state
)) == 0) {
3644 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3646 pll
->name
, pll
->refcount
, pll
->active
);
3652 /* Ok no matching timings, maybe there's a free one? */
3653 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3654 pll
= &dev_priv
->shared_dplls
[i
];
3655 if (pll
->refcount
== 0) {
3656 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3657 crtc
->base
.base
.id
, pll
->name
);
3665 if (pll
->refcount
== 0)
3666 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3668 crtc
->config
.shared_dpll
= i
;
3669 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3670 pipe_name(crtc
->pipe
));
3677 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3680 int dslreg
= PIPEDSL(pipe
);
3683 temp
= I915_READ(dslreg
);
3685 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3686 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3687 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3691 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3693 struct drm_device
*dev
= crtc
->base
.dev
;
3694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 int pipe
= crtc
->pipe
;
3697 if (crtc
->config
.pch_pfit
.enabled
) {
3698 /* Force use of hard-coded filter coefficients
3699 * as some pre-programmed values are broken,
3702 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3703 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3704 PF_PIPE_SEL_IVB(pipe
));
3706 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3707 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3708 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3712 static void intel_enable_planes(struct drm_crtc
*crtc
)
3714 struct drm_device
*dev
= crtc
->dev
;
3715 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3716 struct drm_plane
*plane
;
3717 struct intel_plane
*intel_plane
;
3719 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3720 intel_plane
= to_intel_plane(plane
);
3721 if (intel_plane
->pipe
== pipe
)
3722 intel_plane_restore(&intel_plane
->base
);
3726 static void intel_disable_planes(struct drm_crtc
*crtc
)
3728 struct drm_device
*dev
= crtc
->dev
;
3729 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3730 struct drm_plane
*plane
;
3731 struct intel_plane
*intel_plane
;
3733 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3734 intel_plane
= to_intel_plane(plane
);
3735 if (intel_plane
->pipe
== pipe
)
3736 intel_plane_disable(&intel_plane
->base
);
3740 void hsw_enable_ips(struct intel_crtc
*crtc
)
3742 struct drm_device
*dev
= crtc
->base
.dev
;
3743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3745 if (!crtc
->config
.ips_enabled
)
3748 /* We can only enable IPS after we enable a plane and wait for a vblank */
3749 intel_wait_for_vblank(dev
, crtc
->pipe
);
3751 assert_plane_enabled(dev_priv
, crtc
->plane
);
3752 if (IS_BROADWELL(dev
)) {
3753 mutex_lock(&dev_priv
->rps
.hw_lock
);
3754 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3755 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3756 /* Quoting Art Runyan: "its not safe to expect any particular
3757 * value in IPS_CTL bit 31 after enabling IPS through the
3758 * mailbox." Moreover, the mailbox may return a bogus state,
3759 * so we need to just enable it and continue on.
3762 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3763 /* The bit only becomes 1 in the next vblank, so this wait here
3764 * is essentially intel_wait_for_vblank. If we don't have this
3765 * and don't wait for vblanks until the end of crtc_enable, then
3766 * the HW state readout code will complain that the expected
3767 * IPS_CTL value is not the one we read. */
3768 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3769 DRM_ERROR("Timed out waiting for IPS enable\n");
3773 void hsw_disable_ips(struct intel_crtc
*crtc
)
3775 struct drm_device
*dev
= crtc
->base
.dev
;
3776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3778 if (!crtc
->config
.ips_enabled
)
3781 assert_plane_enabled(dev_priv
, crtc
->plane
);
3782 if (IS_BROADWELL(dev
)) {
3783 mutex_lock(&dev_priv
->rps
.hw_lock
);
3784 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3785 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3786 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3787 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3788 DRM_ERROR("Timed out waiting for IPS disable\n");
3790 I915_WRITE(IPS_CTL
, 0);
3791 POSTING_READ(IPS_CTL
);
3794 /* We need to wait for a vblank before we can disable the plane. */
3795 intel_wait_for_vblank(dev
, crtc
->pipe
);
3798 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3799 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3801 struct drm_device
*dev
= crtc
->dev
;
3802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3803 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3804 enum pipe pipe
= intel_crtc
->pipe
;
3805 int palreg
= PALETTE(pipe
);
3807 bool reenable_ips
= false;
3809 /* The clocks have to be on to load the palette. */
3810 if (!crtc
->enabled
|| !intel_crtc
->active
)
3813 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3814 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3815 assert_dsi_pll_enabled(dev_priv
);
3817 assert_pll_enabled(dev_priv
, pipe
);
3820 /* use legacy palette for Ironlake */
3821 if (HAS_PCH_SPLIT(dev
))
3822 palreg
= LGC_PALETTE(pipe
);
3824 /* Workaround : Do not read or write the pipe palette/gamma data while
3825 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3827 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3828 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3829 GAMMA_MODE_MODE_SPLIT
)) {
3830 hsw_disable_ips(intel_crtc
);
3831 reenable_ips
= true;
3834 for (i
= 0; i
< 256; i
++) {
3835 I915_WRITE(palreg
+ 4 * i
,
3836 (intel_crtc
->lut_r
[i
] << 16) |
3837 (intel_crtc
->lut_g
[i
] << 8) |
3838 intel_crtc
->lut_b
[i
]);
3842 hsw_enable_ips(intel_crtc
);
3845 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3847 if (!enable
&& intel_crtc
->overlay
) {
3848 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3851 mutex_lock(&dev
->struct_mutex
);
3852 dev_priv
->mm
.interruptible
= false;
3853 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3854 dev_priv
->mm
.interruptible
= true;
3855 mutex_unlock(&dev
->struct_mutex
);
3858 /* Let userspace switch the overlay on again. In most cases userspace
3859 * has to recompute where to put it anyway.
3864 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3865 * cursor plane briefly if not already running after enabling the display
3867 * This workaround avoids occasional blank screens when self refresh is
3871 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3873 u32 cntl
= I915_READ(CURCNTR(pipe
));
3875 if ((cntl
& CURSOR_MODE
) == 0) {
3876 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3878 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3879 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3880 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3881 I915_WRITE(CURCNTR(pipe
), cntl
);
3882 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3883 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3887 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3889 struct drm_device
*dev
= crtc
->dev
;
3890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3891 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3892 int pipe
= intel_crtc
->pipe
;
3893 int plane
= intel_crtc
->plane
;
3895 intel_enable_primary_hw_plane(dev_priv
, plane
, pipe
);
3896 intel_enable_planes(crtc
);
3897 /* The fixup needs to happen before cursor is enabled */
3899 g4x_fixup_plane(dev_priv
, pipe
);
3900 intel_crtc_update_cursor(crtc
, true);
3901 intel_crtc_dpms_overlay(intel_crtc
, true);
3903 hsw_enable_ips(intel_crtc
);
3905 mutex_lock(&dev
->struct_mutex
);
3906 intel_update_fbc(dev
);
3907 intel_edp_psr_update(dev
);
3908 mutex_unlock(&dev
->struct_mutex
);
3911 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3913 struct drm_device
*dev
= crtc
->dev
;
3914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3916 int pipe
= intel_crtc
->pipe
;
3917 int plane
= intel_crtc
->plane
;
3919 intel_crtc_wait_for_pending_flips(crtc
);
3920 drm_crtc_vblank_off(crtc
);
3922 if (dev_priv
->fbc
.plane
== plane
)
3923 intel_disable_fbc(dev
);
3925 hsw_disable_ips(intel_crtc
);
3927 intel_crtc_dpms_overlay(intel_crtc
, false);
3928 intel_crtc_update_cursor(crtc
, false);
3929 intel_disable_planes(crtc
);
3930 intel_disable_primary_hw_plane(dev_priv
, plane
, pipe
);
3933 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3935 struct drm_device
*dev
= crtc
->dev
;
3936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3937 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3938 struct intel_encoder
*encoder
;
3939 int pipe
= intel_crtc
->pipe
;
3940 enum plane plane
= intel_crtc
->plane
;
3942 WARN_ON(!crtc
->enabled
);
3944 if (intel_crtc
->active
)
3947 if (intel_crtc
->config
.has_pch_encoder
)
3948 intel_prepare_shared_dpll(intel_crtc
);
3950 if (intel_crtc
->config
.has_dp_encoder
)
3951 intel_dp_set_m_n(intel_crtc
);
3953 intel_set_pipe_timings(intel_crtc
);
3955 if (intel_crtc
->config
.has_pch_encoder
) {
3956 intel_cpu_transcoder_set_m_n(intel_crtc
,
3957 &intel_crtc
->config
.fdi_m_n
);
3960 ironlake_set_pipeconf(crtc
);
3962 /* Set up the display plane register */
3963 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
3964 POSTING_READ(DSPCNTR(plane
));
3966 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
3969 intel_crtc
->active
= true;
3971 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3972 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3974 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3975 if (encoder
->pre_enable
)
3976 encoder
->pre_enable(encoder
);
3978 if (intel_crtc
->config
.has_pch_encoder
) {
3979 /* Note: FDI PLL enabling _must_ be done before we enable the
3980 * cpu pipes, hence this is separate from all the other fdi/pch
3982 ironlake_fdi_pll_enable(intel_crtc
);
3984 assert_fdi_tx_disabled(dev_priv
, pipe
);
3985 assert_fdi_rx_disabled(dev_priv
, pipe
);
3988 ironlake_pfit_enable(intel_crtc
);
3991 * On ILK+ LUT must be loaded before the pipe is running but with
3994 intel_crtc_load_lut(crtc
);
3996 intel_update_watermarks(crtc
);
3997 intel_enable_pipe(intel_crtc
);
3999 if (intel_crtc
->config
.has_pch_encoder
)
4000 ironlake_pch_enable(crtc
);
4002 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4003 encoder
->enable(encoder
);
4005 if (HAS_PCH_CPT(dev
))
4006 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4008 intel_crtc_enable_planes(crtc
);
4010 drm_crtc_vblank_on(crtc
);
4013 /* IPS only exists on ULT machines and is tied to pipe A. */
4014 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4016 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4020 * This implements the workaround described in the "notes" section of the mode
4021 * set sequence documentation. When going from no pipes or single pipe to
4022 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4023 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4025 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4027 struct drm_device
*dev
= crtc
->base
.dev
;
4028 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4030 /* We want to get the other_active_crtc only if there's only 1 other
4032 for_each_intel_crtc(dev
, crtc_it
) {
4033 if (!crtc_it
->active
|| crtc_it
== crtc
)
4036 if (other_active_crtc
)
4039 other_active_crtc
= crtc_it
;
4041 if (!other_active_crtc
)
4044 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4045 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4048 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4050 struct drm_device
*dev
= crtc
->dev
;
4051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4053 struct intel_encoder
*encoder
;
4054 int pipe
= intel_crtc
->pipe
;
4055 enum plane plane
= intel_crtc
->plane
;
4057 WARN_ON(!crtc
->enabled
);
4059 if (intel_crtc
->active
)
4062 if (intel_crtc
->config
.has_dp_encoder
)
4063 intel_dp_set_m_n(intel_crtc
);
4065 intel_set_pipe_timings(intel_crtc
);
4067 if (intel_crtc
->config
.has_pch_encoder
) {
4068 intel_cpu_transcoder_set_m_n(intel_crtc
,
4069 &intel_crtc
->config
.fdi_m_n
);
4072 haswell_set_pipeconf(crtc
);
4074 intel_set_pipe_csc(crtc
);
4076 /* Set up the display plane register */
4077 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
4078 POSTING_READ(DSPCNTR(plane
));
4080 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4083 intel_crtc
->active
= true;
4085 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4086 if (intel_crtc
->config
.has_pch_encoder
)
4087 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4089 if (intel_crtc
->config
.has_pch_encoder
)
4090 dev_priv
->display
.fdi_link_train(crtc
);
4092 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4093 if (encoder
->pre_enable
)
4094 encoder
->pre_enable(encoder
);
4096 intel_ddi_enable_pipe_clock(intel_crtc
);
4098 ironlake_pfit_enable(intel_crtc
);
4101 * On ILK+ LUT must be loaded before the pipe is running but with
4104 intel_crtc_load_lut(crtc
);
4106 intel_ddi_set_pipe_settings(crtc
);
4107 intel_ddi_enable_transcoder_func(crtc
);
4109 intel_update_watermarks(crtc
);
4110 intel_enable_pipe(intel_crtc
);
4112 if (intel_crtc
->config
.has_pch_encoder
)
4113 lpt_pch_enable(crtc
);
4115 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4116 encoder
->enable(encoder
);
4117 intel_opregion_notify_encoder(encoder
, true);
4120 /* If we change the relative order between pipe/planes enabling, we need
4121 * to change the workaround. */
4122 haswell_mode_set_planes_workaround(intel_crtc
);
4123 intel_crtc_enable_planes(crtc
);
4125 drm_crtc_vblank_on(crtc
);
4128 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4130 struct drm_device
*dev
= crtc
->base
.dev
;
4131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4132 int pipe
= crtc
->pipe
;
4134 /* To avoid upsetting the power well on haswell only disable the pfit if
4135 * it's in use. The hw state code will make sure we get this right. */
4136 if (crtc
->config
.pch_pfit
.enabled
) {
4137 I915_WRITE(PF_CTL(pipe
), 0);
4138 I915_WRITE(PF_WIN_POS(pipe
), 0);
4139 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4143 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4145 struct drm_device
*dev
= crtc
->dev
;
4146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4148 struct intel_encoder
*encoder
;
4149 int pipe
= intel_crtc
->pipe
;
4152 if (!intel_crtc
->active
)
4155 intel_crtc_disable_planes(crtc
);
4157 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4158 encoder
->disable(encoder
);
4160 if (intel_crtc
->config
.has_pch_encoder
)
4161 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4163 intel_disable_pipe(dev_priv
, pipe
);
4165 ironlake_pfit_disable(intel_crtc
);
4167 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4168 if (encoder
->post_disable
)
4169 encoder
->post_disable(encoder
);
4171 if (intel_crtc
->config
.has_pch_encoder
) {
4172 ironlake_fdi_disable(crtc
);
4174 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4175 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4177 if (HAS_PCH_CPT(dev
)) {
4178 /* disable TRANS_DP_CTL */
4179 reg
= TRANS_DP_CTL(pipe
);
4180 temp
= I915_READ(reg
);
4181 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4182 TRANS_DP_PORT_SEL_MASK
);
4183 temp
|= TRANS_DP_PORT_SEL_NONE
;
4184 I915_WRITE(reg
, temp
);
4186 /* disable DPLL_SEL */
4187 temp
= I915_READ(PCH_DPLL_SEL
);
4188 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4189 I915_WRITE(PCH_DPLL_SEL
, temp
);
4192 /* disable PCH DPLL */
4193 intel_disable_shared_dpll(intel_crtc
);
4195 ironlake_fdi_pll_disable(intel_crtc
);
4198 intel_crtc
->active
= false;
4199 intel_update_watermarks(crtc
);
4201 mutex_lock(&dev
->struct_mutex
);
4202 intel_update_fbc(dev
);
4203 intel_edp_psr_update(dev
);
4204 mutex_unlock(&dev
->struct_mutex
);
4207 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4209 struct drm_device
*dev
= crtc
->dev
;
4210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4211 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4212 struct intel_encoder
*encoder
;
4213 int pipe
= intel_crtc
->pipe
;
4214 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4216 if (!intel_crtc
->active
)
4219 intel_crtc_disable_planes(crtc
);
4221 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4222 intel_opregion_notify_encoder(encoder
, false);
4223 encoder
->disable(encoder
);
4226 if (intel_crtc
->config
.has_pch_encoder
)
4227 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4228 intel_disable_pipe(dev_priv
, pipe
);
4230 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4232 ironlake_pfit_disable(intel_crtc
);
4234 intel_ddi_disable_pipe_clock(intel_crtc
);
4236 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4237 if (encoder
->post_disable
)
4238 encoder
->post_disable(encoder
);
4240 if (intel_crtc
->config
.has_pch_encoder
) {
4241 lpt_disable_pch_transcoder(dev_priv
);
4242 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4243 intel_ddi_fdi_disable(crtc
);
4246 intel_crtc
->active
= false;
4247 intel_update_watermarks(crtc
);
4249 mutex_lock(&dev
->struct_mutex
);
4250 intel_update_fbc(dev
);
4251 intel_edp_psr_update(dev
);
4252 mutex_unlock(&dev
->struct_mutex
);
4255 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4258 intel_put_shared_dpll(intel_crtc
);
4261 static void haswell_crtc_off(struct drm_crtc
*crtc
)
4263 intel_ddi_put_crtc_pll(crtc
);
4266 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4268 struct drm_device
*dev
= crtc
->base
.dev
;
4269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4270 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4272 if (!crtc
->config
.gmch_pfit
.control
)
4276 * The panel fitter should only be adjusted whilst the pipe is disabled,
4277 * according to register description and PRM.
4279 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4280 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4282 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4283 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4285 /* Border color in case we don't scale up to the full screen. Black by
4286 * default, change to something else for debugging. */
4287 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4290 #define for_each_power_domain(domain, mask) \
4291 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4292 if ((1 << (domain)) & (mask))
4294 enum intel_display_power_domain
4295 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4297 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4298 struct intel_digital_port
*intel_dig_port
;
4300 switch (intel_encoder
->type
) {
4301 case INTEL_OUTPUT_UNKNOWN
:
4302 /* Only DDI platforms should ever use this output type */
4303 WARN_ON_ONCE(!HAS_DDI(dev
));
4304 case INTEL_OUTPUT_DISPLAYPORT
:
4305 case INTEL_OUTPUT_HDMI
:
4306 case INTEL_OUTPUT_EDP
:
4307 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4308 switch (intel_dig_port
->port
) {
4310 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4312 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4314 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4316 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4319 return POWER_DOMAIN_PORT_OTHER
;
4321 case INTEL_OUTPUT_ANALOG
:
4322 return POWER_DOMAIN_PORT_CRT
;
4323 case INTEL_OUTPUT_DSI
:
4324 return POWER_DOMAIN_PORT_DSI
;
4326 return POWER_DOMAIN_PORT_OTHER
;
4330 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4332 struct drm_device
*dev
= crtc
->dev
;
4333 struct intel_encoder
*intel_encoder
;
4334 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4335 enum pipe pipe
= intel_crtc
->pipe
;
4336 bool pfit_enabled
= intel_crtc
->config
.pch_pfit
.enabled
;
4338 enum transcoder transcoder
;
4340 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4342 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4343 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4345 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4347 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4348 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4353 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4356 if (dev_priv
->power_domains
.init_power_on
== enable
)
4360 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4362 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4364 dev_priv
->power_domains
.init_power_on
= enable
;
4367 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4370 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4371 struct intel_crtc
*crtc
;
4374 * First get all needed power domains, then put all unneeded, to avoid
4375 * any unnecessary toggling of the power wells.
4377 for_each_intel_crtc(dev
, crtc
) {
4378 enum intel_display_power_domain domain
;
4380 if (!crtc
->base
.enabled
)
4383 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4385 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4386 intel_display_power_get(dev_priv
, domain
);
4389 for_each_intel_crtc(dev
, crtc
) {
4390 enum intel_display_power_domain domain
;
4392 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4393 intel_display_power_put(dev_priv
, domain
);
4395 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4398 intel_display_set_init_power(dev_priv
, false);
4401 int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4403 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4405 /* Obtain SKU information */
4406 mutex_lock(&dev_priv
->dpio_lock
);
4407 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4408 CCK_FUSE_HPLL_FREQ_MASK
;
4409 mutex_unlock(&dev_priv
->dpio_lock
);
4411 return vco_freq
[hpll_freq
];
4414 /* Adjust CDclk dividers to allow high res or save power if possible */
4415 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4420 WARN_ON(valleyview_cur_cdclk(dev_priv
) != dev_priv
->vlv_cdclk_freq
);
4421 dev_priv
->vlv_cdclk_freq
= cdclk
;
4423 if (cdclk
>= 320) /* jump to highest voltage for 400MHz too */
4425 else if (cdclk
== 266)
4430 mutex_lock(&dev_priv
->rps
.hw_lock
);
4431 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4432 val
&= ~DSPFREQGUAR_MASK
;
4433 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4434 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4435 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4436 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4438 DRM_ERROR("timed out waiting for CDclk change\n");
4440 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4445 vco
= valleyview_get_vco(dev_priv
);
4446 divider
= ((vco
<< 1) / cdclk
) - 1;
4448 mutex_lock(&dev_priv
->dpio_lock
);
4449 /* adjust cdclk divider */
4450 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4453 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4454 mutex_unlock(&dev_priv
->dpio_lock
);
4457 mutex_lock(&dev_priv
->dpio_lock
);
4458 /* adjust self-refresh exit latency value */
4459 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4463 * For high bandwidth configs, we set a higher latency in the bunit
4464 * so that the core display fetch happens in time to avoid underruns.
4467 val
|= 4500 / 250; /* 4.5 usec */
4469 val
|= 3000 / 250; /* 3.0 usec */
4470 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4471 mutex_unlock(&dev_priv
->dpio_lock
);
4473 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4474 intel_i2c_reset(dev
);
4477 int valleyview_cur_cdclk(struct drm_i915_private
*dev_priv
)
4482 vco
= valleyview_get_vco(dev_priv
);
4484 mutex_lock(&dev_priv
->dpio_lock
);
4485 divider
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4486 mutex_unlock(&dev_priv
->dpio_lock
);
4490 cur_cdclk
= (vco
<< 1) / (divider
+ 1);
4495 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4499 * Really only a few cases to deal with, as only 4 CDclks are supported:
4504 * So we check to see whether we're above 90% of the lower bin and
4507 if (max_pixclk
> 288000) {
4509 } else if (max_pixclk
> 240000) {
4513 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4516 /* compute the max pixel clock for new configuration */
4517 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4519 struct drm_device
*dev
= dev_priv
->dev
;
4520 struct intel_crtc
*intel_crtc
;
4523 for_each_intel_crtc(dev
, intel_crtc
) {
4524 if (intel_crtc
->new_enabled
)
4525 max_pixclk
= max(max_pixclk
,
4526 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4532 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4533 unsigned *prepare_pipes
)
4535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4536 struct intel_crtc
*intel_crtc
;
4537 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4539 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4540 dev_priv
->vlv_cdclk_freq
)
4543 /* disable/enable all currently active pipes while we change cdclk */
4544 for_each_intel_crtc(dev
, intel_crtc
)
4545 if (intel_crtc
->base
.enabled
)
4546 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4549 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4552 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4553 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4555 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
)
4556 valleyview_set_cdclk(dev
, req_cdclk
);
4557 modeset_update_crtc_power_domains(dev
);
4560 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4562 struct drm_device
*dev
= crtc
->dev
;
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4565 struct intel_encoder
*encoder
;
4566 int pipe
= intel_crtc
->pipe
;
4567 int plane
= intel_crtc
->plane
;
4571 WARN_ON(!crtc
->enabled
);
4573 if (intel_crtc
->active
)
4576 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4578 if (!is_dsi
&& !IS_CHERRYVIEW(dev
))
4579 vlv_prepare_pll(intel_crtc
);
4581 /* Set up the display plane register */
4582 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4584 if (intel_crtc
->config
.has_dp_encoder
)
4585 intel_dp_set_m_n(intel_crtc
);
4587 intel_set_pipe_timings(intel_crtc
);
4589 /* pipesrc and dspsize control the size that is scaled from,
4590 * which should always be the user's requested size.
4592 I915_WRITE(DSPSIZE(plane
),
4593 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4594 (intel_crtc
->config
.pipe_src_w
- 1));
4595 I915_WRITE(DSPPOS(plane
), 0);
4597 i9xx_set_pipeconf(intel_crtc
);
4599 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4600 POSTING_READ(DSPCNTR(plane
));
4602 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4605 intel_crtc
->active
= true;
4607 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4609 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4610 if (encoder
->pre_pll_enable
)
4611 encoder
->pre_pll_enable(encoder
);
4614 if (IS_CHERRYVIEW(dev
))
4615 chv_enable_pll(intel_crtc
);
4617 vlv_enable_pll(intel_crtc
);
4620 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4621 if (encoder
->pre_enable
)
4622 encoder
->pre_enable(encoder
);
4624 i9xx_pfit_enable(intel_crtc
);
4626 intel_crtc_load_lut(crtc
);
4628 intel_update_watermarks(crtc
);
4629 intel_enable_pipe(intel_crtc
);
4631 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4632 encoder
->enable(encoder
);
4634 intel_crtc_enable_planes(crtc
);
4636 drm_crtc_vblank_on(crtc
);
4638 /* Underruns don't raise interrupts, so check manually. */
4639 i9xx_check_fifo_underruns(dev
);
4642 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4644 struct drm_device
*dev
= crtc
->base
.dev
;
4645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4647 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4648 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4651 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4653 struct drm_device
*dev
= crtc
->dev
;
4654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4656 struct intel_encoder
*encoder
;
4657 int pipe
= intel_crtc
->pipe
;
4658 int plane
= intel_crtc
->plane
;
4661 WARN_ON(!crtc
->enabled
);
4663 if (intel_crtc
->active
)
4666 i9xx_set_pll_dividers(intel_crtc
);
4668 /* Set up the display plane register */
4669 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4672 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4674 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4676 if (intel_crtc
->config
.has_dp_encoder
)
4677 intel_dp_set_m_n(intel_crtc
);
4679 intel_set_pipe_timings(intel_crtc
);
4681 /* pipesrc and dspsize control the size that is scaled from,
4682 * which should always be the user's requested size.
4684 I915_WRITE(DSPSIZE(plane
),
4685 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
4686 (intel_crtc
->config
.pipe_src_w
- 1));
4687 I915_WRITE(DSPPOS(plane
), 0);
4689 i9xx_set_pipeconf(intel_crtc
);
4691 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4692 POSTING_READ(DSPCNTR(plane
));
4694 dev_priv
->display
.update_primary_plane(crtc
, crtc
->primary
->fb
,
4697 intel_crtc
->active
= true;
4700 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4702 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4703 if (encoder
->pre_enable
)
4704 encoder
->pre_enable(encoder
);
4706 i9xx_enable_pll(intel_crtc
);
4708 i9xx_pfit_enable(intel_crtc
);
4710 intel_crtc_load_lut(crtc
);
4712 intel_update_watermarks(crtc
);
4713 intel_enable_pipe(intel_crtc
);
4715 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4716 encoder
->enable(encoder
);
4718 intel_crtc_enable_planes(crtc
);
4721 * Gen2 reports pipe underruns whenever all planes are disabled.
4722 * So don't enable underrun reporting before at least some planes
4724 * FIXME: Need to fix the logic to work when we turn off all planes
4725 * but leave the pipe running.
4728 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4730 drm_crtc_vblank_on(crtc
);
4732 /* Underruns don't raise interrupts, so check manually. */
4733 i9xx_check_fifo_underruns(dev
);
4736 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4738 struct drm_device
*dev
= crtc
->base
.dev
;
4739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4741 if (!crtc
->config
.gmch_pfit
.control
)
4744 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4746 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4747 I915_READ(PFIT_CONTROL
));
4748 I915_WRITE(PFIT_CONTROL
, 0);
4751 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4753 struct drm_device
*dev
= crtc
->dev
;
4754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4755 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4756 struct intel_encoder
*encoder
;
4757 int pipe
= intel_crtc
->pipe
;
4759 if (!intel_crtc
->active
)
4763 * Gen2 reports pipe underruns whenever all planes are disabled.
4764 * So diasble underrun reporting before all the planes get disabled.
4765 * FIXME: Need to fix the logic to work when we turn off all planes
4766 * but leave the pipe running.
4769 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4771 intel_crtc_disable_planes(crtc
);
4773 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4774 encoder
->disable(encoder
);
4777 * On gen2 planes are double buffered but the pipe isn't, so we must
4778 * wait for planes to fully turn off before disabling the pipe.
4781 intel_wait_for_vblank(dev
, pipe
);
4783 intel_disable_pipe(dev_priv
, pipe
);
4785 i9xx_pfit_disable(intel_crtc
);
4787 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4788 if (encoder
->post_disable
)
4789 encoder
->post_disable(encoder
);
4791 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4792 if (IS_CHERRYVIEW(dev
))
4793 chv_disable_pll(dev_priv
, pipe
);
4794 else if (IS_VALLEYVIEW(dev
))
4795 vlv_disable_pll(dev_priv
, pipe
);
4797 i9xx_disable_pll(dev_priv
, pipe
);
4801 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4803 intel_crtc
->active
= false;
4804 intel_update_watermarks(crtc
);
4806 mutex_lock(&dev
->struct_mutex
);
4807 intel_update_fbc(dev
);
4808 intel_edp_psr_update(dev
);
4809 mutex_unlock(&dev
->struct_mutex
);
4812 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4816 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4819 struct drm_device
*dev
= crtc
->dev
;
4820 struct drm_i915_master_private
*master_priv
;
4821 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4822 int pipe
= intel_crtc
->pipe
;
4824 if (!dev
->primary
->master
)
4827 master_priv
= dev
->primary
->master
->driver_priv
;
4828 if (!master_priv
->sarea_priv
)
4833 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4834 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4837 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4838 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4841 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4847 * Sets the power management mode of the pipe and plane.
4849 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4851 struct drm_device
*dev
= crtc
->dev
;
4852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4853 struct intel_encoder
*intel_encoder
;
4854 bool enable
= false;
4856 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4857 enable
|= intel_encoder
->connectors_active
;
4860 dev_priv
->display
.crtc_enable(crtc
);
4862 dev_priv
->display
.crtc_disable(crtc
);
4864 intel_crtc_update_sarea(crtc
, enable
);
4867 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4869 struct drm_device
*dev
= crtc
->dev
;
4870 struct drm_connector
*connector
;
4871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4873 /* crtc should still be enabled when we disable it. */
4874 WARN_ON(!crtc
->enabled
);
4876 dev_priv
->display
.crtc_disable(crtc
);
4877 intel_crtc_update_sarea(crtc
, false);
4878 dev_priv
->display
.off(crtc
);
4880 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4881 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4882 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4884 if (crtc
->primary
->fb
) {
4885 mutex_lock(&dev
->struct_mutex
);
4886 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->primary
->fb
)->obj
);
4887 mutex_unlock(&dev
->struct_mutex
);
4888 crtc
->primary
->fb
= NULL
;
4891 /* Update computed state. */
4892 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4893 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4896 if (connector
->encoder
->crtc
!= crtc
)
4899 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4900 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4904 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4906 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4908 drm_encoder_cleanup(encoder
);
4909 kfree(intel_encoder
);
4912 /* Simple dpms helper for encoders with just one connector, no cloning and only
4913 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4914 * state of the entire output pipe. */
4915 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4917 if (mode
== DRM_MODE_DPMS_ON
) {
4918 encoder
->connectors_active
= true;
4920 intel_crtc_update_dpms(encoder
->base
.crtc
);
4922 encoder
->connectors_active
= false;
4924 intel_crtc_update_dpms(encoder
->base
.crtc
);
4928 /* Cross check the actual hw state with our own modeset state tracking (and it's
4929 * internal consistency). */
4930 static void intel_connector_check_state(struct intel_connector
*connector
)
4932 if (connector
->get_hw_state(connector
)) {
4933 struct intel_encoder
*encoder
= connector
->encoder
;
4934 struct drm_crtc
*crtc
;
4935 bool encoder_enabled
;
4938 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4939 connector
->base
.base
.id
,
4940 connector
->base
.name
);
4942 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4943 "wrong connector dpms state\n");
4944 WARN(connector
->base
.encoder
!= &encoder
->base
,
4945 "active connector not linked to encoder\n");
4946 WARN(!encoder
->connectors_active
,
4947 "encoder->connectors_active not set\n");
4949 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4950 WARN(!encoder_enabled
, "encoder not enabled\n");
4951 if (WARN_ON(!encoder
->base
.crtc
))
4954 crtc
= encoder
->base
.crtc
;
4956 WARN(!crtc
->enabled
, "crtc not enabled\n");
4957 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4958 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4959 "encoder active on the wrong pipe\n");
4963 /* Even simpler default implementation, if there's really no special case to
4965 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4967 /* All the simple cases only support two dpms states. */
4968 if (mode
!= DRM_MODE_DPMS_ON
)
4969 mode
= DRM_MODE_DPMS_OFF
;
4971 if (mode
== connector
->dpms
)
4974 connector
->dpms
= mode
;
4976 /* Only need to change hw state when actually enabled */
4977 if (connector
->encoder
)
4978 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
4980 intel_modeset_check_state(connector
->dev
);
4983 /* Simple connector->get_hw_state implementation for encoders that support only
4984 * one connector and no cloning and hence the encoder state determines the state
4985 * of the connector. */
4986 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4989 struct intel_encoder
*encoder
= connector
->encoder
;
4991 return encoder
->get_hw_state(encoder
, &pipe
);
4994 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4995 struct intel_crtc_config
*pipe_config
)
4997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4998 struct intel_crtc
*pipe_B_crtc
=
4999 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5001 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5002 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5003 if (pipe_config
->fdi_lanes
> 4) {
5004 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5005 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5009 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5010 if (pipe_config
->fdi_lanes
> 2) {
5011 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5012 pipe_config
->fdi_lanes
);
5019 if (INTEL_INFO(dev
)->num_pipes
== 2)
5022 /* Ivybridge 3 pipe is really complicated */
5027 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5028 pipe_config
->fdi_lanes
> 2) {
5029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5030 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5035 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5036 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5037 if (pipe_config
->fdi_lanes
> 2) {
5038 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5039 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5043 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5053 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5054 struct intel_crtc_config
*pipe_config
)
5056 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5057 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5058 int lane
, link_bw
, fdi_dotclock
;
5059 bool setup_ok
, needs_recompute
= false;
5062 /* FDI is a binary signal running at ~2.7GHz, encoding
5063 * each output octet as 10 bits. The actual frequency
5064 * is stored as a divider into a 100MHz clock, and the
5065 * mode pixel clock is stored in units of 1KHz.
5066 * Hence the bw of each lane in terms of the mode signal
5069 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5071 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5073 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5074 pipe_config
->pipe_bpp
);
5076 pipe_config
->fdi_lanes
= lane
;
5078 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5079 link_bw
, &pipe_config
->fdi_m_n
);
5081 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5082 intel_crtc
->pipe
, pipe_config
);
5083 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5084 pipe_config
->pipe_bpp
-= 2*3;
5085 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5086 pipe_config
->pipe_bpp
);
5087 needs_recompute
= true;
5088 pipe_config
->bw_constrained
= true;
5093 if (needs_recompute
)
5096 return setup_ok
? 0 : -EINVAL
;
5099 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5100 struct intel_crtc_config
*pipe_config
)
5102 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5103 hsw_crtc_supports_ips(crtc
) &&
5104 pipe_config
->pipe_bpp
<= 24;
5107 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5108 struct intel_crtc_config
*pipe_config
)
5110 struct drm_device
*dev
= crtc
->base
.dev
;
5111 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5113 /* FIXME should check pixel clock limits on all platforms */
5114 if (INTEL_INFO(dev
)->gen
< 4) {
5115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5117 dev_priv
->display
.get_display_clock_speed(dev
);
5120 * Enable pixel doubling when the dot clock
5121 * is > 90% of the (display) core speed.
5123 * GDG double wide on either pipe,
5124 * otherwise pipe A only.
5126 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5127 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5129 pipe_config
->double_wide
= true;
5132 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5137 * Pipe horizontal size must be even in:
5139 * - LVDS dual channel mode
5140 * - Double wide pipe
5142 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5143 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5144 pipe_config
->pipe_src_w
&= ~1;
5146 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5147 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5149 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5150 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5153 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5154 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5155 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5156 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5158 pipe_config
->pipe_bpp
= 8*3;
5162 hsw_compute_ips_config(crtc
, pipe_config
);
5164 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5165 * clock survives for now. */
5166 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5167 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5169 if (pipe_config
->has_pch_encoder
)
5170 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5175 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5177 return 400000; /* FIXME */
5180 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5185 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5190 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5195 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5199 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5201 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5202 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5204 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5206 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5208 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5211 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5212 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5214 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5219 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5223 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5225 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5228 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5229 case GC_DISPLAY_CLOCK_333_MHZ
:
5232 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5238 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5243 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5246 /* Assume that the hardware is in the high speed state. This
5247 * should be the default.
5249 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5250 case GC_CLOCK_133_200
:
5251 case GC_CLOCK_100_200
:
5253 case GC_CLOCK_166_250
:
5255 case GC_CLOCK_100_133
:
5259 /* Shouldn't happen */
5263 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5269 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5271 while (*num
> DATA_LINK_M_N_MASK
||
5272 *den
> DATA_LINK_M_N_MASK
) {
5278 static void compute_m_n(unsigned int m
, unsigned int n
,
5279 uint32_t *ret_m
, uint32_t *ret_n
)
5281 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5282 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5283 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5287 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5288 int pixel_clock
, int link_clock
,
5289 struct intel_link_m_n
*m_n
)
5293 compute_m_n(bits_per_pixel
* pixel_clock
,
5294 link_clock
* nlanes
* 8,
5295 &m_n
->gmch_m
, &m_n
->gmch_n
);
5297 compute_m_n(pixel_clock
, link_clock
,
5298 &m_n
->link_m
, &m_n
->link_n
);
5301 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5303 if (i915
.panel_use_ssc
>= 0)
5304 return i915
.panel_use_ssc
!= 0;
5305 return dev_priv
->vbt
.lvds_use_ssc
5306 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5309 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5311 struct drm_device
*dev
= crtc
->dev
;
5312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5315 if (IS_VALLEYVIEW(dev
)) {
5317 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5318 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5319 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5320 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5321 } else if (!IS_GEN2(dev
)) {
5330 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5332 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5335 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5337 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5340 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5341 intel_clock_t
*reduced_clock
)
5343 struct drm_device
*dev
= crtc
->base
.dev
;
5346 if (IS_PINEVIEW(dev
)) {
5347 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5349 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5351 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5353 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5356 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5358 crtc
->lowfreq_avail
= false;
5359 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5360 reduced_clock
&& i915
.powersave
) {
5361 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5362 crtc
->lowfreq_avail
= true;
5364 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5368 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5374 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5375 * and set it to a reasonable value instead.
5377 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5378 reg_val
&= 0xffffff00;
5379 reg_val
|= 0x00000030;
5380 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5382 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5383 reg_val
&= 0x8cffffff;
5384 reg_val
= 0x8c000000;
5385 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5387 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5388 reg_val
&= 0xffffff00;
5389 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5391 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5392 reg_val
&= 0x00ffffff;
5393 reg_val
|= 0xb0000000;
5394 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5397 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5398 struct intel_link_m_n
*m_n
)
5400 struct drm_device
*dev
= crtc
->base
.dev
;
5401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5402 int pipe
= crtc
->pipe
;
5404 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5405 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5406 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5407 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5410 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5411 struct intel_link_m_n
*m_n
)
5413 struct drm_device
*dev
= crtc
->base
.dev
;
5414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5415 int pipe
= crtc
->pipe
;
5416 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5418 if (INTEL_INFO(dev
)->gen
>= 5) {
5419 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5420 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5421 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5422 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5424 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5425 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5426 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5427 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5431 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5433 if (crtc
->config
.has_pch_encoder
)
5434 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5436 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5439 static void vlv_update_pll(struct intel_crtc
*crtc
)
5444 * Enable DPIO clock input. We should never disable the reference
5445 * clock for pipe B, since VGA hotplug / manual detection depends
5448 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5449 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5450 /* We should never disable this, set it here for state tracking */
5451 if (crtc
->pipe
== PIPE_B
)
5452 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5453 dpll
|= DPLL_VCO_ENABLE
;
5454 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5456 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5457 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5458 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5461 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5463 struct drm_device
*dev
= crtc
->base
.dev
;
5464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5465 int pipe
= crtc
->pipe
;
5467 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5468 u32 coreclk
, reg_val
;
5470 mutex_lock(&dev_priv
->dpio_lock
);
5472 bestn
= crtc
->config
.dpll
.n
;
5473 bestm1
= crtc
->config
.dpll
.m1
;
5474 bestm2
= crtc
->config
.dpll
.m2
;
5475 bestp1
= crtc
->config
.dpll
.p1
;
5476 bestp2
= crtc
->config
.dpll
.p2
;
5478 /* See eDP HDMI DPIO driver vbios notes doc */
5480 /* PLL B needs special handling */
5482 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5484 /* Set up Tx target for periodic Rcomp update */
5485 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5487 /* Disable target IRef on PLL */
5488 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5489 reg_val
&= 0x00ffffff;
5490 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5492 /* Disable fast lock */
5493 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5495 /* Set idtafcrecal before PLL is enabled */
5496 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5497 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5498 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5499 mdiv
|= (1 << DPIO_K_SHIFT
);
5502 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5503 * but we don't support that).
5504 * Note: don't use the DAC post divider as it seems unstable.
5506 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5507 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5509 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5510 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5512 /* Set HBR and RBR LPF coefficients */
5513 if (crtc
->config
.port_clock
== 162000 ||
5514 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5515 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5516 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5519 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5522 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5523 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5524 /* Use SSC source */
5526 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5529 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5531 } else { /* HDMI or VGA */
5532 /* Use bend source */
5534 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5537 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5541 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5542 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5543 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5544 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5545 coreclk
|= 0x01000000;
5546 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5548 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5549 mutex_unlock(&dev_priv
->dpio_lock
);
5552 static void chv_update_pll(struct intel_crtc
*crtc
)
5554 struct drm_device
*dev
= crtc
->base
.dev
;
5555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5556 int pipe
= crtc
->pipe
;
5557 int dpll_reg
= DPLL(crtc
->pipe
);
5558 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5559 u32 loopfilter
, intcoeff
;
5560 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5563 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5564 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5567 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5569 crtc
->config
.dpll_hw_state
.dpll_md
=
5570 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5572 bestn
= crtc
->config
.dpll
.n
;
5573 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5574 bestm1
= crtc
->config
.dpll
.m1
;
5575 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5576 bestp1
= crtc
->config
.dpll
.p1
;
5577 bestp2
= crtc
->config
.dpll
.p2
;
5580 * Enable Refclk and SSC
5582 I915_WRITE(dpll_reg
,
5583 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5585 mutex_lock(&dev_priv
->dpio_lock
);
5587 /* p1 and p2 divider */
5588 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5589 5 << DPIO_CHV_S1_DIV_SHIFT
|
5590 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5591 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5592 1 << DPIO_CHV_K_DIV_SHIFT
);
5594 /* Feedback post-divider - m2 */
5595 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5597 /* Feedback refclk divider - n and m1 */
5598 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5599 DPIO_CHV_M1_DIV_BY_2
|
5600 1 << DPIO_CHV_N_DIV_SHIFT
);
5602 /* M2 fraction division */
5603 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5605 /* M2 fraction division enable */
5606 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5607 DPIO_CHV_FRAC_DIV_EN
|
5608 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5611 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5612 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5613 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5614 if (refclk
== 100000)
5616 else if (refclk
== 38400)
5620 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5621 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5624 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5625 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5628 mutex_unlock(&dev_priv
->dpio_lock
);
5631 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5632 intel_clock_t
*reduced_clock
,
5635 struct drm_device
*dev
= crtc
->base
.dev
;
5636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5639 struct dpll
*clock
= &crtc
->config
.dpll
;
5641 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5643 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5644 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5646 dpll
= DPLL_VGA_MODE_DIS
;
5648 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5649 dpll
|= DPLLB_MODE_LVDS
;
5651 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5653 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5654 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5655 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5659 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5661 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5662 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5664 /* compute bitmask from p1 value */
5665 if (IS_PINEVIEW(dev
))
5666 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5668 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5669 if (IS_G4X(dev
) && reduced_clock
)
5670 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5672 switch (clock
->p2
) {
5674 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5677 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5680 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5683 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5686 if (INTEL_INFO(dev
)->gen
>= 4)
5687 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5689 if (crtc
->config
.sdvo_tv_clock
)
5690 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5691 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5692 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5693 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5695 dpll
|= PLL_REF_INPUT_DREFCLK
;
5697 dpll
|= DPLL_VCO_ENABLE
;
5698 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5700 if (INTEL_INFO(dev
)->gen
>= 4) {
5701 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5702 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5703 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5707 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5708 intel_clock_t
*reduced_clock
,
5711 struct drm_device
*dev
= crtc
->base
.dev
;
5712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5714 struct dpll
*clock
= &crtc
->config
.dpll
;
5716 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5718 dpll
= DPLL_VGA_MODE_DIS
;
5720 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5721 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5724 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5726 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5728 dpll
|= PLL_P2_DIVIDE_BY_4
;
5731 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5732 dpll
|= DPLL_DVO_2X_MODE
;
5734 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5735 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5736 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5738 dpll
|= PLL_REF_INPUT_DREFCLK
;
5740 dpll
|= DPLL_VCO_ENABLE
;
5741 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5744 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5746 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5748 enum pipe pipe
= intel_crtc
->pipe
;
5749 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5750 struct drm_display_mode
*adjusted_mode
=
5751 &intel_crtc
->config
.adjusted_mode
;
5752 uint32_t crtc_vtotal
, crtc_vblank_end
;
5755 /* We need to be careful not to changed the adjusted mode, for otherwise
5756 * the hw state checker will get angry at the mismatch. */
5757 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5758 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5760 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5761 /* the chip adds 2 halflines automatically */
5763 crtc_vblank_end
-= 1;
5765 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5766 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5768 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5769 adjusted_mode
->crtc_htotal
/ 2;
5771 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5774 if (INTEL_INFO(dev
)->gen
> 3)
5775 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5777 I915_WRITE(HTOTAL(cpu_transcoder
),
5778 (adjusted_mode
->crtc_hdisplay
- 1) |
5779 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5780 I915_WRITE(HBLANK(cpu_transcoder
),
5781 (adjusted_mode
->crtc_hblank_start
- 1) |
5782 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5783 I915_WRITE(HSYNC(cpu_transcoder
),
5784 (adjusted_mode
->crtc_hsync_start
- 1) |
5785 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5787 I915_WRITE(VTOTAL(cpu_transcoder
),
5788 (adjusted_mode
->crtc_vdisplay
- 1) |
5789 ((crtc_vtotal
- 1) << 16));
5790 I915_WRITE(VBLANK(cpu_transcoder
),
5791 (adjusted_mode
->crtc_vblank_start
- 1) |
5792 ((crtc_vblank_end
- 1) << 16));
5793 I915_WRITE(VSYNC(cpu_transcoder
),
5794 (adjusted_mode
->crtc_vsync_start
- 1) |
5795 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5797 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5798 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5799 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5801 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5802 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5803 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5805 /* pipesrc controls the size that is scaled from, which should
5806 * always be the user's requested size.
5808 I915_WRITE(PIPESRC(pipe
),
5809 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5810 (intel_crtc
->config
.pipe_src_h
- 1));
5813 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5814 struct intel_crtc_config
*pipe_config
)
5816 struct drm_device
*dev
= crtc
->base
.dev
;
5817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5818 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5821 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5822 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5823 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5824 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5825 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5826 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5827 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5828 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5829 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5831 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5832 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5833 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5834 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5835 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5836 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5837 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5838 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5839 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5841 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5842 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5843 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5844 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5847 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5848 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5849 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5851 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5852 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5855 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
5856 struct intel_crtc_config
*pipe_config
)
5858 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5859 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5860 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5861 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5863 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5864 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5865 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5866 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5868 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
5870 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5871 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
5874 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5876 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5882 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5883 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5884 pipeconf
|= PIPECONF_ENABLE
;
5886 if (intel_crtc
->config
.double_wide
)
5887 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5889 /* only g4x and later have fancy bpc/dither controls */
5890 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5891 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5892 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5893 pipeconf
|= PIPECONF_DITHER_EN
|
5894 PIPECONF_DITHER_TYPE_SP
;
5896 switch (intel_crtc
->config
.pipe_bpp
) {
5898 pipeconf
|= PIPECONF_6BPC
;
5901 pipeconf
|= PIPECONF_8BPC
;
5904 pipeconf
|= PIPECONF_10BPC
;
5907 /* Case prevented by intel_choose_pipe_bpp_dither. */
5912 if (HAS_PIPE_CXSR(dev
)) {
5913 if (intel_crtc
->lowfreq_avail
) {
5914 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5915 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5917 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5921 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
5922 if (INTEL_INFO(dev
)->gen
< 4 ||
5923 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5924 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5926 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
5928 pipeconf
|= PIPECONF_PROGRESSIVE
;
5930 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5931 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5933 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5934 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5937 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5939 struct drm_framebuffer
*fb
)
5941 struct drm_device
*dev
= crtc
->dev
;
5942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5944 int refclk
, num_connectors
= 0;
5945 intel_clock_t clock
, reduced_clock
;
5946 bool ok
, has_reduced_clock
= false;
5947 bool is_lvds
= false, is_dsi
= false;
5948 struct intel_encoder
*encoder
;
5949 const intel_limit_t
*limit
;
5951 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5952 switch (encoder
->type
) {
5953 case INTEL_OUTPUT_LVDS
:
5956 case INTEL_OUTPUT_DSI
:
5967 if (!intel_crtc
->config
.clock_set
) {
5968 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5971 * Returns a set of divisors for the desired target clock with
5972 * the given refclk, or FALSE. The returned values represent
5973 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5976 limit
= intel_limit(crtc
, refclk
);
5977 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5978 intel_crtc
->config
.port_clock
,
5979 refclk
, NULL
, &clock
);
5981 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5985 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5987 * Ensure we match the reduced clock's P to the target
5988 * clock. If the clocks don't match, we can't switch
5989 * the display clock by using the FP0/FP1. In such case
5990 * we will disable the LVDS downclock feature.
5993 dev_priv
->display
.find_dpll(limit
, crtc
,
5994 dev_priv
->lvds_downclock
,
5998 /* Compat-code for transition, will disappear. */
5999 intel_crtc
->config
.dpll
.n
= clock
.n
;
6000 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6001 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6002 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6003 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6007 i8xx_update_pll(intel_crtc
,
6008 has_reduced_clock
? &reduced_clock
: NULL
,
6010 } else if (IS_CHERRYVIEW(dev
)) {
6011 chv_update_pll(intel_crtc
);
6012 } else if (IS_VALLEYVIEW(dev
)) {
6013 vlv_update_pll(intel_crtc
);
6015 i9xx_update_pll(intel_crtc
,
6016 has_reduced_clock
? &reduced_clock
: NULL
,
6023 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6024 struct intel_crtc_config
*pipe_config
)
6026 struct drm_device
*dev
= crtc
->base
.dev
;
6027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6030 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6033 tmp
= I915_READ(PFIT_CONTROL
);
6034 if (!(tmp
& PFIT_ENABLE
))
6037 /* Check whether the pfit is attached to our pipe. */
6038 if (INTEL_INFO(dev
)->gen
< 4) {
6039 if (crtc
->pipe
!= PIPE_B
)
6042 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6046 pipe_config
->gmch_pfit
.control
= tmp
;
6047 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6048 if (INTEL_INFO(dev
)->gen
< 5)
6049 pipe_config
->gmch_pfit
.lvds_border_bits
=
6050 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6053 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6054 struct intel_crtc_config
*pipe_config
)
6056 struct drm_device
*dev
= crtc
->base
.dev
;
6057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6058 int pipe
= pipe_config
->cpu_transcoder
;
6059 intel_clock_t clock
;
6061 int refclk
= 100000;
6063 mutex_lock(&dev_priv
->dpio_lock
);
6064 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6065 mutex_unlock(&dev_priv
->dpio_lock
);
6067 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6068 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6069 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6070 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6071 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6073 vlv_clock(refclk
, &clock
);
6075 /* clock.dot is the fast clock */
6076 pipe_config
->port_clock
= clock
.dot
/ 5;
6079 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6080 struct intel_plane_config
*plane_config
)
6082 struct drm_device
*dev
= crtc
->base
.dev
;
6083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6084 u32 val
, base
, offset
;
6085 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6086 int fourcc
, pixel_format
;
6089 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6090 if (!crtc
->base
.primary
->fb
) {
6091 DRM_DEBUG_KMS("failed to alloc fb\n");
6095 val
= I915_READ(DSPCNTR(plane
));
6097 if (INTEL_INFO(dev
)->gen
>= 4)
6098 if (val
& DISPPLANE_TILED
)
6099 plane_config
->tiled
= true;
6101 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6102 fourcc
= intel_format_to_fourcc(pixel_format
);
6103 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6104 crtc
->base
.primary
->fb
->bits_per_pixel
=
6105 drm_format_plane_cpp(fourcc
, 0) * 8;
6107 if (INTEL_INFO(dev
)->gen
>= 4) {
6108 if (plane_config
->tiled
)
6109 offset
= I915_READ(DSPTILEOFF(plane
));
6111 offset
= I915_READ(DSPLINOFF(plane
));
6112 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6114 base
= I915_READ(DSPADDR(plane
));
6116 plane_config
->base
= base
;
6118 val
= I915_READ(PIPESRC(pipe
));
6119 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6120 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6122 val
= I915_READ(DSPSTRIDE(pipe
));
6123 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
6125 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6126 plane_config
->tiled
);
6128 plane_config
->size
= ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6129 aligned_height
, PAGE_SIZE
);
6131 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6132 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6133 crtc
->base
.primary
->fb
->height
,
6134 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6135 crtc
->base
.primary
->fb
->pitches
[0],
6136 plane_config
->size
);
6140 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6141 struct intel_crtc_config
*pipe_config
)
6143 struct drm_device
*dev
= crtc
->base
.dev
;
6144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6145 int pipe
= pipe_config
->cpu_transcoder
;
6146 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6147 intel_clock_t clock
;
6148 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6149 int refclk
= 100000;
6151 mutex_lock(&dev_priv
->dpio_lock
);
6152 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6153 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6154 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6155 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6156 mutex_unlock(&dev_priv
->dpio_lock
);
6158 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6159 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6160 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6161 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6162 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6164 chv_clock(refclk
, &clock
);
6166 /* clock.dot is the fast clock */
6167 pipe_config
->port_clock
= clock
.dot
/ 5;
6170 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6171 struct intel_crtc_config
*pipe_config
)
6173 struct drm_device
*dev
= crtc
->base
.dev
;
6174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6177 if (!intel_display_power_enabled(dev_priv
,
6178 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6181 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6182 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6184 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6185 if (!(tmp
& PIPECONF_ENABLE
))
6188 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6189 switch (tmp
& PIPECONF_BPC_MASK
) {
6191 pipe_config
->pipe_bpp
= 18;
6194 pipe_config
->pipe_bpp
= 24;
6196 case PIPECONF_10BPC
:
6197 pipe_config
->pipe_bpp
= 30;
6204 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6205 pipe_config
->limited_color_range
= true;
6207 if (INTEL_INFO(dev
)->gen
< 4)
6208 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6210 intel_get_pipe_timings(crtc
, pipe_config
);
6212 i9xx_get_pfit_config(crtc
, pipe_config
);
6214 if (INTEL_INFO(dev
)->gen
>= 4) {
6215 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6216 pipe_config
->pixel_multiplier
=
6217 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6218 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6219 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6220 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6221 tmp
= I915_READ(DPLL(crtc
->pipe
));
6222 pipe_config
->pixel_multiplier
=
6223 ((tmp
& SDVO_MULTIPLIER_MASK
)
6224 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6226 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6227 * port and will be fixed up in the encoder->get_config
6229 pipe_config
->pixel_multiplier
= 1;
6231 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6232 if (!IS_VALLEYVIEW(dev
)) {
6233 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6234 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6236 /* Mask out read-only status bits. */
6237 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6238 DPLL_PORTC_READY_MASK
|
6239 DPLL_PORTB_READY_MASK
);
6242 if (IS_CHERRYVIEW(dev
))
6243 chv_crtc_clock_get(crtc
, pipe_config
);
6244 else if (IS_VALLEYVIEW(dev
))
6245 vlv_crtc_clock_get(crtc
, pipe_config
);
6247 i9xx_crtc_clock_get(crtc
, pipe_config
);
6252 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6255 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6256 struct intel_encoder
*encoder
;
6258 bool has_lvds
= false;
6259 bool has_cpu_edp
= false;
6260 bool has_panel
= false;
6261 bool has_ck505
= false;
6262 bool can_ssc
= false;
6264 /* We need to take the global config into account */
6265 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
6267 switch (encoder
->type
) {
6268 case INTEL_OUTPUT_LVDS
:
6272 case INTEL_OUTPUT_EDP
:
6274 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6280 if (HAS_PCH_IBX(dev
)) {
6281 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6282 can_ssc
= has_ck505
;
6288 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6289 has_panel
, has_lvds
, has_ck505
);
6291 /* Ironlake: try to setup display ref clock before DPLL
6292 * enabling. This is only under driver's control after
6293 * PCH B stepping, previous chipset stepping should be
6294 * ignoring this setting.
6296 val
= I915_READ(PCH_DREF_CONTROL
);
6298 /* As we must carefully and slowly disable/enable each source in turn,
6299 * compute the final state we want first and check if we need to
6300 * make any changes at all.
6303 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6305 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6307 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6309 final
&= ~DREF_SSC_SOURCE_MASK
;
6310 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6311 final
&= ~DREF_SSC1_ENABLE
;
6314 final
|= DREF_SSC_SOURCE_ENABLE
;
6316 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6317 final
|= DREF_SSC1_ENABLE
;
6320 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6321 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6323 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6325 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6327 final
|= DREF_SSC_SOURCE_DISABLE
;
6328 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6334 /* Always enable nonspread source */
6335 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6338 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6340 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6343 val
&= ~DREF_SSC_SOURCE_MASK
;
6344 val
|= DREF_SSC_SOURCE_ENABLE
;
6346 /* SSC must be turned on before enabling the CPU output */
6347 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6348 DRM_DEBUG_KMS("Using SSC on panel\n");
6349 val
|= DREF_SSC1_ENABLE
;
6351 val
&= ~DREF_SSC1_ENABLE
;
6353 /* Get SSC going before enabling the outputs */
6354 I915_WRITE(PCH_DREF_CONTROL
, val
);
6355 POSTING_READ(PCH_DREF_CONTROL
);
6358 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6360 /* Enable CPU source on CPU attached eDP */
6362 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6363 DRM_DEBUG_KMS("Using SSC on eDP\n");
6364 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6366 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6368 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6370 I915_WRITE(PCH_DREF_CONTROL
, val
);
6371 POSTING_READ(PCH_DREF_CONTROL
);
6374 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6376 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6378 /* Turn off CPU output */
6379 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6381 I915_WRITE(PCH_DREF_CONTROL
, val
);
6382 POSTING_READ(PCH_DREF_CONTROL
);
6385 /* Turn off the SSC source */
6386 val
&= ~DREF_SSC_SOURCE_MASK
;
6387 val
|= DREF_SSC_SOURCE_DISABLE
;
6390 val
&= ~DREF_SSC1_ENABLE
;
6392 I915_WRITE(PCH_DREF_CONTROL
, val
);
6393 POSTING_READ(PCH_DREF_CONTROL
);
6397 BUG_ON(val
!= final
);
6400 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6404 tmp
= I915_READ(SOUTH_CHICKEN2
);
6405 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6406 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6408 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6409 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6410 DRM_ERROR("FDI mPHY reset assert timeout\n");
6412 tmp
= I915_READ(SOUTH_CHICKEN2
);
6413 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6414 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6416 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6417 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6418 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6421 /* WaMPhyProgramming:hsw */
6422 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6426 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6427 tmp
&= ~(0xFF << 24);
6428 tmp
|= (0x12 << 24);
6429 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6431 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6433 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6435 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6437 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6439 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6440 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6441 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6443 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6444 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6445 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6447 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6450 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6452 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6455 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6457 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6460 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6462 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6465 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6467 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6468 tmp
&= ~(0xFF << 16);
6469 tmp
|= (0x1C << 16);
6470 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6472 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6473 tmp
&= ~(0xFF << 16);
6474 tmp
|= (0x1C << 16);
6475 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6477 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6479 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6481 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6483 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6485 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6486 tmp
&= ~(0xF << 28);
6488 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6490 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6491 tmp
&= ~(0xF << 28);
6493 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6496 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6497 * Programming" based on the parameters passed:
6498 * - Sequence to enable CLKOUT_DP
6499 * - Sequence to enable CLKOUT_DP without spread
6500 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6502 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6508 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6510 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6511 with_fdi
, "LP PCH doesn't have FDI\n"))
6514 mutex_lock(&dev_priv
->dpio_lock
);
6516 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6517 tmp
&= ~SBI_SSCCTL_DISABLE
;
6518 tmp
|= SBI_SSCCTL_PATHALT
;
6519 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6524 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6525 tmp
&= ~SBI_SSCCTL_PATHALT
;
6526 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6529 lpt_reset_fdi_mphy(dev_priv
);
6530 lpt_program_fdi_mphy(dev_priv
);
6534 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6535 SBI_GEN0
: SBI_DBUFF0
;
6536 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6537 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6538 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6540 mutex_unlock(&dev_priv
->dpio_lock
);
6543 /* Sequence to disable CLKOUT_DP */
6544 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6549 mutex_lock(&dev_priv
->dpio_lock
);
6551 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6552 SBI_GEN0
: SBI_DBUFF0
;
6553 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6554 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6555 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6557 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6558 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6559 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6560 tmp
|= SBI_SSCCTL_PATHALT
;
6561 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6564 tmp
|= SBI_SSCCTL_DISABLE
;
6565 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6568 mutex_unlock(&dev_priv
->dpio_lock
);
6571 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6573 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
6574 struct intel_encoder
*encoder
;
6575 bool has_vga
= false;
6577 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
6578 switch (encoder
->type
) {
6579 case INTEL_OUTPUT_ANALOG
:
6586 lpt_enable_clkout_dp(dev
, true, true);
6588 lpt_disable_clkout_dp(dev
);
6592 * Initialize reference clocks when the driver loads
6594 void intel_init_pch_refclk(struct drm_device
*dev
)
6596 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6597 ironlake_init_pch_refclk(dev
);
6598 else if (HAS_PCH_LPT(dev
))
6599 lpt_init_pch_refclk(dev
);
6602 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6604 struct drm_device
*dev
= crtc
->dev
;
6605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6606 struct intel_encoder
*encoder
;
6607 int num_connectors
= 0;
6608 bool is_lvds
= false;
6610 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6611 switch (encoder
->type
) {
6612 case INTEL_OUTPUT_LVDS
:
6619 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6620 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6621 dev_priv
->vbt
.lvds_ssc_freq
);
6622 return dev_priv
->vbt
.lvds_ssc_freq
;
6628 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6630 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6632 int pipe
= intel_crtc
->pipe
;
6637 switch (intel_crtc
->config
.pipe_bpp
) {
6639 val
|= PIPECONF_6BPC
;
6642 val
|= PIPECONF_8BPC
;
6645 val
|= PIPECONF_10BPC
;
6648 val
|= PIPECONF_12BPC
;
6651 /* Case prevented by intel_choose_pipe_bpp_dither. */
6655 if (intel_crtc
->config
.dither
)
6656 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6658 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6659 val
|= PIPECONF_INTERLACED_ILK
;
6661 val
|= PIPECONF_PROGRESSIVE
;
6663 if (intel_crtc
->config
.limited_color_range
)
6664 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6666 I915_WRITE(PIPECONF(pipe
), val
);
6667 POSTING_READ(PIPECONF(pipe
));
6671 * Set up the pipe CSC unit.
6673 * Currently only full range RGB to limited range RGB conversion
6674 * is supported, but eventually this should handle various
6675 * RGB<->YCbCr scenarios as well.
6677 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6679 struct drm_device
*dev
= crtc
->dev
;
6680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6681 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6682 int pipe
= intel_crtc
->pipe
;
6683 uint16_t coeff
= 0x7800; /* 1.0 */
6686 * TODO: Check what kind of values actually come out of the pipe
6687 * with these coeff/postoff values and adjust to get the best
6688 * accuracy. Perhaps we even need to take the bpc value into
6692 if (intel_crtc
->config
.limited_color_range
)
6693 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6696 * GY/GU and RY/RU should be the other way around according
6697 * to BSpec, but reality doesn't agree. Just set them up in
6698 * a way that results in the correct picture.
6700 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6701 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6703 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6704 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6706 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6707 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6709 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6710 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6711 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6713 if (INTEL_INFO(dev
)->gen
> 6) {
6714 uint16_t postoff
= 0;
6716 if (intel_crtc
->config
.limited_color_range
)
6717 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6719 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6720 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6721 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6723 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6725 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6727 if (intel_crtc
->config
.limited_color_range
)
6728 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6730 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6734 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6736 struct drm_device
*dev
= crtc
->dev
;
6737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6739 enum pipe pipe
= intel_crtc
->pipe
;
6740 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6745 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6746 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6748 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6749 val
|= PIPECONF_INTERLACED_ILK
;
6751 val
|= PIPECONF_PROGRESSIVE
;
6753 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6754 POSTING_READ(PIPECONF(cpu_transcoder
));
6756 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6757 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6759 if (IS_BROADWELL(dev
)) {
6762 switch (intel_crtc
->config
.pipe_bpp
) {
6764 val
|= PIPEMISC_DITHER_6_BPC
;
6767 val
|= PIPEMISC_DITHER_8_BPC
;
6770 val
|= PIPEMISC_DITHER_10_BPC
;
6773 val
|= PIPEMISC_DITHER_12_BPC
;
6776 /* Case prevented by pipe_config_set_bpp. */
6780 if (intel_crtc
->config
.dither
)
6781 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6783 I915_WRITE(PIPEMISC(pipe
), val
);
6787 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6788 intel_clock_t
*clock
,
6789 bool *has_reduced_clock
,
6790 intel_clock_t
*reduced_clock
)
6792 struct drm_device
*dev
= crtc
->dev
;
6793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6794 struct intel_encoder
*intel_encoder
;
6796 const intel_limit_t
*limit
;
6797 bool ret
, is_lvds
= false;
6799 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6800 switch (intel_encoder
->type
) {
6801 case INTEL_OUTPUT_LVDS
:
6807 refclk
= ironlake_get_refclk(crtc
);
6810 * Returns a set of divisors for the desired target clock with the given
6811 * refclk, or FALSE. The returned values represent the clock equation:
6812 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6814 limit
= intel_limit(crtc
, refclk
);
6815 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6816 to_intel_crtc(crtc
)->config
.port_clock
,
6817 refclk
, NULL
, clock
);
6821 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6823 * Ensure we match the reduced clock's P to the target clock.
6824 * If the clocks don't match, we can't switch the display clock
6825 * by using the FP0/FP1. In such case we will disable the LVDS
6826 * downclock feature.
6828 *has_reduced_clock
=
6829 dev_priv
->display
.find_dpll(limit
, crtc
,
6830 dev_priv
->lvds_downclock
,
6838 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6841 * Account for spread spectrum to avoid
6842 * oversubscribing the link. Max center spread
6843 * is 2.5%; use 5% for safety's sake.
6845 u32 bps
= target_clock
* bpp
* 21 / 20;
6846 return DIV_ROUND_UP(bps
, link_bw
* 8);
6849 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6851 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6854 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6856 intel_clock_t
*reduced_clock
, u32
*fp2
)
6858 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6859 struct drm_device
*dev
= crtc
->dev
;
6860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6861 struct intel_encoder
*intel_encoder
;
6863 int factor
, num_connectors
= 0;
6864 bool is_lvds
= false, is_sdvo
= false;
6866 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6867 switch (intel_encoder
->type
) {
6868 case INTEL_OUTPUT_LVDS
:
6871 case INTEL_OUTPUT_SDVO
:
6872 case INTEL_OUTPUT_HDMI
:
6880 /* Enable autotuning of the PLL clock (if permissible) */
6883 if ((intel_panel_use_ssc(dev_priv
) &&
6884 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
6885 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
6887 } else if (intel_crtc
->config
.sdvo_tv_clock
)
6890 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
6893 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
6899 dpll
|= DPLLB_MODE_LVDS
;
6901 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6903 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
6904 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6907 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6908 if (intel_crtc
->config
.has_dp_encoder
)
6909 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6911 /* compute bitmask from p1 value */
6912 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6914 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6916 switch (intel_crtc
->config
.dpll
.p2
) {
6918 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6921 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6924 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6927 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6931 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6932 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6934 dpll
|= PLL_REF_INPUT_DREFCLK
;
6936 return dpll
| DPLL_VCO_ENABLE
;
6939 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
6941 struct drm_framebuffer
*fb
)
6943 struct drm_device
*dev
= crtc
->dev
;
6944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6945 int num_connectors
= 0;
6946 intel_clock_t clock
, reduced_clock
;
6947 u32 dpll
= 0, fp
= 0, fp2
= 0;
6948 bool ok
, has_reduced_clock
= false;
6949 bool is_lvds
= false;
6950 struct intel_encoder
*encoder
;
6951 struct intel_shared_dpll
*pll
;
6953 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6954 switch (encoder
->type
) {
6955 case INTEL_OUTPUT_LVDS
:
6963 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6964 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6966 ok
= ironlake_compute_clocks(crtc
, &clock
,
6967 &has_reduced_clock
, &reduced_clock
);
6968 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6969 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6972 /* Compat-code for transition, will disappear. */
6973 if (!intel_crtc
->config
.clock_set
) {
6974 intel_crtc
->config
.dpll
.n
= clock
.n
;
6975 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6976 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6977 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6978 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6981 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6982 if (intel_crtc
->config
.has_pch_encoder
) {
6983 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6984 if (has_reduced_clock
)
6985 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6987 dpll
= ironlake_compute_dpll(intel_crtc
,
6988 &fp
, &reduced_clock
,
6989 has_reduced_clock
? &fp2
: NULL
);
6991 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6992 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6993 if (has_reduced_clock
)
6994 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6996 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6998 pll
= intel_get_shared_dpll(intel_crtc
);
7000 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7001 pipe_name(intel_crtc
->pipe
));
7005 intel_put_shared_dpll(intel_crtc
);
7007 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7008 intel_crtc
->lowfreq_avail
= true;
7010 intel_crtc
->lowfreq_avail
= false;
7015 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7016 struct intel_link_m_n
*m_n
)
7018 struct drm_device
*dev
= crtc
->base
.dev
;
7019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7020 enum pipe pipe
= crtc
->pipe
;
7022 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7023 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7024 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7026 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7027 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7028 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7031 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7032 enum transcoder transcoder
,
7033 struct intel_link_m_n
*m_n
)
7035 struct drm_device
*dev
= crtc
->base
.dev
;
7036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7037 enum pipe pipe
= crtc
->pipe
;
7039 if (INTEL_INFO(dev
)->gen
>= 5) {
7040 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7041 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7042 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7044 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7045 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7046 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7048 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7049 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7050 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7052 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7053 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7054 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7058 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7059 struct intel_crtc_config
*pipe_config
)
7061 if (crtc
->config
.has_pch_encoder
)
7062 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7064 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7065 &pipe_config
->dp_m_n
);
7068 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7069 struct intel_crtc_config
*pipe_config
)
7071 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7072 &pipe_config
->fdi_m_n
);
7075 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7076 struct intel_crtc_config
*pipe_config
)
7078 struct drm_device
*dev
= crtc
->base
.dev
;
7079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7082 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7084 if (tmp
& PF_ENABLE
) {
7085 pipe_config
->pch_pfit
.enabled
= true;
7086 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7087 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7089 /* We currently do not free assignements of panel fitters on
7090 * ivb/hsw (since we don't use the higher upscaling modes which
7091 * differentiates them) so just WARN about this case for now. */
7093 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7094 PF_PIPE_SEL_IVB(crtc
->pipe
));
7099 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7100 struct intel_plane_config
*plane_config
)
7102 struct drm_device
*dev
= crtc
->base
.dev
;
7103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7104 u32 val
, base
, offset
;
7105 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7106 int fourcc
, pixel_format
;
7109 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7110 if (!crtc
->base
.primary
->fb
) {
7111 DRM_DEBUG_KMS("failed to alloc fb\n");
7115 val
= I915_READ(DSPCNTR(plane
));
7117 if (INTEL_INFO(dev
)->gen
>= 4)
7118 if (val
& DISPPLANE_TILED
)
7119 plane_config
->tiled
= true;
7121 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7122 fourcc
= intel_format_to_fourcc(pixel_format
);
7123 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7124 crtc
->base
.primary
->fb
->bits_per_pixel
=
7125 drm_format_plane_cpp(fourcc
, 0) * 8;
7127 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7128 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7129 offset
= I915_READ(DSPOFFSET(plane
));
7131 if (plane_config
->tiled
)
7132 offset
= I915_READ(DSPTILEOFF(plane
));
7134 offset
= I915_READ(DSPLINOFF(plane
));
7136 plane_config
->base
= base
;
7138 val
= I915_READ(PIPESRC(pipe
));
7139 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7140 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7142 val
= I915_READ(DSPSTRIDE(pipe
));
7143 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffff80;
7145 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7146 plane_config
->tiled
);
7148 plane_config
->size
= ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7149 aligned_height
, PAGE_SIZE
);
7151 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7152 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7153 crtc
->base
.primary
->fb
->height
,
7154 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7155 crtc
->base
.primary
->fb
->pitches
[0],
7156 plane_config
->size
);
7159 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7160 struct intel_crtc_config
*pipe_config
)
7162 struct drm_device
*dev
= crtc
->base
.dev
;
7163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7166 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7167 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7169 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7170 if (!(tmp
& PIPECONF_ENABLE
))
7173 switch (tmp
& PIPECONF_BPC_MASK
) {
7175 pipe_config
->pipe_bpp
= 18;
7178 pipe_config
->pipe_bpp
= 24;
7180 case PIPECONF_10BPC
:
7181 pipe_config
->pipe_bpp
= 30;
7183 case PIPECONF_12BPC
:
7184 pipe_config
->pipe_bpp
= 36;
7190 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7191 pipe_config
->limited_color_range
= true;
7193 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7194 struct intel_shared_dpll
*pll
;
7196 pipe_config
->has_pch_encoder
= true;
7198 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7199 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7200 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7202 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7204 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7205 pipe_config
->shared_dpll
=
7206 (enum intel_dpll_id
) crtc
->pipe
;
7208 tmp
= I915_READ(PCH_DPLL_SEL
);
7209 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7210 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7212 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7215 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7217 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7218 &pipe_config
->dpll_hw_state
));
7220 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7221 pipe_config
->pixel_multiplier
=
7222 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7223 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7225 ironlake_pch_clock_get(crtc
, pipe_config
);
7227 pipe_config
->pixel_multiplier
= 1;
7230 intel_get_pipe_timings(crtc
, pipe_config
);
7232 ironlake_get_pfit_config(crtc
, pipe_config
);
7237 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7239 struct drm_device
*dev
= dev_priv
->dev
;
7240 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
7241 struct intel_crtc
*crtc
;
7243 for_each_intel_crtc(dev
, crtc
)
7244 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7245 pipe_name(crtc
->pipe
));
7247 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7248 WARN(plls
->spll_refcount
, "SPLL enabled\n");
7249 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
7250 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
7251 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7252 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7253 "CPU PWM1 enabled\n");
7254 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7255 "CPU PWM2 enabled\n");
7256 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7257 "PCH PWM1 enabled\n");
7258 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7259 "Utility pin enabled\n");
7260 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7263 * In theory we can still leave IRQs enabled, as long as only the HPD
7264 * interrupts remain enabled. We used to check for that, but since it's
7265 * gen-specific and since we only disable LCPLL after we fully disable
7266 * the interrupts, the check below should be enough.
7268 WARN(!dev_priv
->pm
.irqs_disabled
, "IRQs enabled\n");
7271 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7273 struct drm_device
*dev
= dev_priv
->dev
;
7275 if (IS_HASWELL(dev
)) {
7276 mutex_lock(&dev_priv
->rps
.hw_lock
);
7277 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7279 DRM_ERROR("Failed to disable D_COMP\n");
7280 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7282 I915_WRITE(D_COMP
, val
);
7284 POSTING_READ(D_COMP
);
7288 * This function implements pieces of two sequences from BSpec:
7289 * - Sequence for display software to disable LCPLL
7290 * - Sequence for display software to allow package C8+
7291 * The steps implemented here are just the steps that actually touch the LCPLL
7292 * register. Callers should take care of disabling all the display engine
7293 * functions, doing the mode unset, fixing interrupts, etc.
7295 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7296 bool switch_to_fclk
, bool allow_power_down
)
7300 assert_can_disable_lcpll(dev_priv
);
7302 val
= I915_READ(LCPLL_CTL
);
7304 if (switch_to_fclk
) {
7305 val
|= LCPLL_CD_SOURCE_FCLK
;
7306 I915_WRITE(LCPLL_CTL
, val
);
7308 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7309 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7310 DRM_ERROR("Switching to FCLK failed\n");
7312 val
= I915_READ(LCPLL_CTL
);
7315 val
|= LCPLL_PLL_DISABLE
;
7316 I915_WRITE(LCPLL_CTL
, val
);
7317 POSTING_READ(LCPLL_CTL
);
7319 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7320 DRM_ERROR("LCPLL still locked\n");
7322 val
= I915_READ(D_COMP
);
7323 val
|= D_COMP_COMP_DISABLE
;
7324 hsw_write_dcomp(dev_priv
, val
);
7327 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
7328 DRM_ERROR("D_COMP RCOMP still in progress\n");
7330 if (allow_power_down
) {
7331 val
= I915_READ(LCPLL_CTL
);
7332 val
|= LCPLL_POWER_DOWN_ALLOW
;
7333 I915_WRITE(LCPLL_CTL
, val
);
7334 POSTING_READ(LCPLL_CTL
);
7339 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7342 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7345 unsigned long irqflags
;
7347 val
= I915_READ(LCPLL_CTL
);
7349 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7350 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7354 * Make sure we're not on PC8 state before disabling PC8, otherwise
7355 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7357 * The other problem is that hsw_restore_lcpll() is called as part of
7358 * the runtime PM resume sequence, so we can't just call
7359 * gen6_gt_force_wake_get() because that function calls
7360 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7361 * while we are on the resume sequence. So to solve this problem we have
7362 * to call special forcewake code that doesn't touch runtime PM and
7363 * doesn't enable the forcewake delayed work.
7365 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7366 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7367 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7368 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7370 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7371 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7372 I915_WRITE(LCPLL_CTL
, val
);
7373 POSTING_READ(LCPLL_CTL
);
7376 val
= I915_READ(D_COMP
);
7377 val
|= D_COMP_COMP_FORCE
;
7378 val
&= ~D_COMP_COMP_DISABLE
;
7379 hsw_write_dcomp(dev_priv
, val
);
7381 val
= I915_READ(LCPLL_CTL
);
7382 val
&= ~LCPLL_PLL_DISABLE
;
7383 I915_WRITE(LCPLL_CTL
, val
);
7385 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7386 DRM_ERROR("LCPLL not locked yet\n");
7388 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7389 val
= I915_READ(LCPLL_CTL
);
7390 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7391 I915_WRITE(LCPLL_CTL
, val
);
7393 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7394 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7395 DRM_ERROR("Switching back to LCPLL failed\n");
7398 /* See the big comment above. */
7399 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7400 if (--dev_priv
->uncore
.forcewake_count
== 0)
7401 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7402 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7406 * Package states C8 and deeper are really deep PC states that can only be
7407 * reached when all the devices on the system allow it, so even if the graphics
7408 * device allows PC8+, it doesn't mean the system will actually get to these
7409 * states. Our driver only allows PC8+ when going into runtime PM.
7411 * The requirements for PC8+ are that all the outputs are disabled, the power
7412 * well is disabled and most interrupts are disabled, and these are also
7413 * requirements for runtime PM. When these conditions are met, we manually do
7414 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7415 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7418 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7419 * the state of some registers, so when we come back from PC8+ we need to
7420 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7421 * need to take care of the registers kept by RC6. Notice that this happens even
7422 * if we don't put the device in PCI D3 state (which is what currently happens
7423 * because of the runtime PM support).
7425 * For more, read "Display Sequences for Package C8" on the hardware
7428 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7430 struct drm_device
*dev
= dev_priv
->dev
;
7433 DRM_DEBUG_KMS("Enabling package C8+\n");
7435 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7436 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7437 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7438 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7441 lpt_disable_clkout_dp(dev
);
7442 hsw_disable_lcpll(dev_priv
, true, true);
7445 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7447 struct drm_device
*dev
= dev_priv
->dev
;
7450 DRM_DEBUG_KMS("Disabling package C8+\n");
7452 hsw_restore_lcpll(dev_priv
);
7453 lpt_init_pch_refclk(dev
);
7455 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7456 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7457 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7458 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7461 intel_prepare_ddi(dev
);
7464 static void snb_modeset_global_resources(struct drm_device
*dev
)
7466 modeset_update_crtc_power_domains(dev
);
7469 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7471 modeset_update_crtc_power_domains(dev
);
7474 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7476 struct drm_framebuffer
*fb
)
7478 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7480 if (!intel_ddi_pll_select(intel_crtc
))
7482 intel_ddi_pll_enable(intel_crtc
);
7484 intel_crtc
->lowfreq_avail
= false;
7489 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7490 struct intel_crtc_config
*pipe_config
)
7492 struct drm_device
*dev
= crtc
->base
.dev
;
7493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7494 enum intel_display_power_domain pfit_domain
;
7497 if (!intel_display_power_enabled(dev_priv
,
7498 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7501 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7502 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7504 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7505 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7506 enum pipe trans_edp_pipe
;
7507 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7509 WARN(1, "unknown pipe linked to edp transcoder\n");
7510 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7511 case TRANS_DDI_EDP_INPUT_A_ON
:
7512 trans_edp_pipe
= PIPE_A
;
7514 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7515 trans_edp_pipe
= PIPE_B
;
7517 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7518 trans_edp_pipe
= PIPE_C
;
7522 if (trans_edp_pipe
== crtc
->pipe
)
7523 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7526 if (!intel_display_power_enabled(dev_priv
,
7527 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7530 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7531 if (!(tmp
& PIPECONF_ENABLE
))
7535 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7536 * DDI E. So just check whether this pipe is wired to DDI E and whether
7537 * the PCH transcoder is on.
7539 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7540 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
7541 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7542 pipe_config
->has_pch_encoder
= true;
7544 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7545 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7546 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7548 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7551 intel_get_pipe_timings(crtc
, pipe_config
);
7553 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7554 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7555 ironlake_get_pfit_config(crtc
, pipe_config
);
7557 if (IS_HASWELL(dev
))
7558 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7559 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7561 pipe_config
->pixel_multiplier
= 1;
7569 } hdmi_audio_clock
[] = {
7570 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7571 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7572 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7573 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7574 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7575 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7576 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7577 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7578 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7579 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7582 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7583 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7587 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7588 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7592 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7593 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7597 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7598 hdmi_audio_clock
[i
].clock
,
7599 hdmi_audio_clock
[i
].config
);
7601 return hdmi_audio_clock
[i
].config
;
7604 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7605 int reg_eldv
, uint32_t bits_eldv
,
7606 int reg_elda
, uint32_t bits_elda
,
7609 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7610 uint8_t *eld
= connector
->eld
;
7613 i
= I915_READ(reg_eldv
);
7622 i
= I915_READ(reg_elda
);
7624 I915_WRITE(reg_elda
, i
);
7626 for (i
= 0; i
< eld
[2]; i
++)
7627 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7633 static void g4x_write_eld(struct drm_connector
*connector
,
7634 struct drm_crtc
*crtc
,
7635 struct drm_display_mode
*mode
)
7637 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7638 uint8_t *eld
= connector
->eld
;
7643 i
= I915_READ(G4X_AUD_VID_DID
);
7645 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7646 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7648 eldv
= G4X_ELDV_DEVCTG
;
7650 if (intel_eld_uptodate(connector
,
7651 G4X_AUD_CNTL_ST
, eldv
,
7652 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7653 G4X_HDMIW_HDMIEDID
))
7656 i
= I915_READ(G4X_AUD_CNTL_ST
);
7657 i
&= ~(eldv
| G4X_ELD_ADDR
);
7658 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7659 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7664 len
= min_t(uint8_t, eld
[2], len
);
7665 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7666 for (i
= 0; i
< len
; i
++)
7667 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7669 i
= I915_READ(G4X_AUD_CNTL_ST
);
7671 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7674 static void haswell_write_eld(struct drm_connector
*connector
,
7675 struct drm_crtc
*crtc
,
7676 struct drm_display_mode
*mode
)
7678 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7679 uint8_t *eld
= connector
->eld
;
7683 int pipe
= to_intel_crtc(crtc
)->pipe
;
7686 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7687 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7688 int aud_config
= HSW_AUD_CFG(pipe
);
7689 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7691 /* Audio output enable */
7692 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7693 tmp
= I915_READ(aud_cntrl_st2
);
7694 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7695 I915_WRITE(aud_cntrl_st2
, tmp
);
7696 POSTING_READ(aud_cntrl_st2
);
7698 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7700 /* Set ELD valid state */
7701 tmp
= I915_READ(aud_cntrl_st2
);
7702 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7703 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7704 I915_WRITE(aud_cntrl_st2
, tmp
);
7705 tmp
= I915_READ(aud_cntrl_st2
);
7706 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7708 /* Enable HDMI mode */
7709 tmp
= I915_READ(aud_config
);
7710 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7711 /* clear N_programing_enable and N_value_index */
7712 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7713 I915_WRITE(aud_config
, tmp
);
7715 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7717 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7719 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7720 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7721 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7722 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7724 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7727 if (intel_eld_uptodate(connector
,
7728 aud_cntrl_st2
, eldv
,
7729 aud_cntl_st
, IBX_ELD_ADDRESS
,
7733 i
= I915_READ(aud_cntrl_st2
);
7735 I915_WRITE(aud_cntrl_st2
, i
);
7740 i
= I915_READ(aud_cntl_st
);
7741 i
&= ~IBX_ELD_ADDRESS
;
7742 I915_WRITE(aud_cntl_st
, i
);
7743 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7744 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7746 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7747 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7748 for (i
= 0; i
< len
; i
++)
7749 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7751 i
= I915_READ(aud_cntrl_st2
);
7753 I915_WRITE(aud_cntrl_st2
, i
);
7757 static void ironlake_write_eld(struct drm_connector
*connector
,
7758 struct drm_crtc
*crtc
,
7759 struct drm_display_mode
*mode
)
7761 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7762 uint8_t *eld
= connector
->eld
;
7770 int pipe
= to_intel_crtc(crtc
)->pipe
;
7772 if (HAS_PCH_IBX(connector
->dev
)) {
7773 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7774 aud_config
= IBX_AUD_CFG(pipe
);
7775 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7776 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7777 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7778 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7779 aud_config
= VLV_AUD_CFG(pipe
);
7780 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7781 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7783 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7784 aud_config
= CPT_AUD_CFG(pipe
);
7785 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7786 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7789 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7791 if (IS_VALLEYVIEW(connector
->dev
)) {
7792 struct intel_encoder
*intel_encoder
;
7793 struct intel_digital_port
*intel_dig_port
;
7795 intel_encoder
= intel_attached_encoder(connector
);
7796 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7797 i
= intel_dig_port
->port
;
7799 i
= I915_READ(aud_cntl_st
);
7800 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7801 /* DIP_Port_Select, 0x1 = PortB */
7805 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7806 /* operate blindly on all ports */
7807 eldv
= IBX_ELD_VALIDB
;
7808 eldv
|= IBX_ELD_VALIDB
<< 4;
7809 eldv
|= IBX_ELD_VALIDB
<< 8;
7811 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7812 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7815 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7816 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7817 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7818 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7820 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7823 if (intel_eld_uptodate(connector
,
7824 aud_cntrl_st2
, eldv
,
7825 aud_cntl_st
, IBX_ELD_ADDRESS
,
7829 i
= I915_READ(aud_cntrl_st2
);
7831 I915_WRITE(aud_cntrl_st2
, i
);
7836 i
= I915_READ(aud_cntl_st
);
7837 i
&= ~IBX_ELD_ADDRESS
;
7838 I915_WRITE(aud_cntl_st
, i
);
7840 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7841 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7842 for (i
= 0; i
< len
; i
++)
7843 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7845 i
= I915_READ(aud_cntrl_st2
);
7847 I915_WRITE(aud_cntrl_st2
, i
);
7850 void intel_write_eld(struct drm_encoder
*encoder
,
7851 struct drm_display_mode
*mode
)
7853 struct drm_crtc
*crtc
= encoder
->crtc
;
7854 struct drm_connector
*connector
;
7855 struct drm_device
*dev
= encoder
->dev
;
7856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7858 connector
= drm_select_eld(encoder
, mode
);
7862 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7865 connector
->encoder
->base
.id
,
7866 connector
->encoder
->name
);
7868 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
7870 if (dev_priv
->display
.write_eld
)
7871 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
7874 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7876 struct drm_device
*dev
= crtc
->dev
;
7877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7878 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7881 if (base
!= intel_crtc
->cursor_base
) {
7882 /* On these chipsets we can only modify the base whilst
7883 * the cursor is disabled.
7885 if (intel_crtc
->cursor_cntl
) {
7886 I915_WRITE(_CURACNTR
, 0);
7887 POSTING_READ(_CURACNTR
);
7888 intel_crtc
->cursor_cntl
= 0;
7891 I915_WRITE(_CURABASE
, base
);
7892 POSTING_READ(_CURABASE
);
7895 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7898 cntl
= (CURSOR_ENABLE
|
7899 CURSOR_GAMMA_ENABLE
|
7900 CURSOR_FORMAT_ARGB
);
7901 if (intel_crtc
->cursor_cntl
!= cntl
) {
7902 I915_WRITE(_CURACNTR
, cntl
);
7903 POSTING_READ(_CURACNTR
);
7904 intel_crtc
->cursor_cntl
= cntl
;
7908 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7910 struct drm_device
*dev
= crtc
->dev
;
7911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7912 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7913 int pipe
= intel_crtc
->pipe
;
7918 cntl
= MCURSOR_GAMMA_ENABLE
;
7919 switch (intel_crtc
->cursor_width
) {
7921 cntl
|= CURSOR_MODE_64_ARGB_AX
;
7924 cntl
|= CURSOR_MODE_128_ARGB_AX
;
7927 cntl
|= CURSOR_MODE_256_ARGB_AX
;
7933 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7935 if (intel_crtc
->cursor_cntl
!= cntl
) {
7936 I915_WRITE(CURCNTR(pipe
), cntl
);
7937 POSTING_READ(CURCNTR(pipe
));
7938 intel_crtc
->cursor_cntl
= cntl
;
7941 /* and commit changes on next vblank */
7942 I915_WRITE(CURBASE(pipe
), base
);
7943 POSTING_READ(CURBASE(pipe
));
7946 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7948 struct drm_device
*dev
= crtc
->dev
;
7949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7951 int pipe
= intel_crtc
->pipe
;
7956 cntl
= MCURSOR_GAMMA_ENABLE
;
7957 switch (intel_crtc
->cursor_width
) {
7959 cntl
|= CURSOR_MODE_64_ARGB_AX
;
7962 cntl
|= CURSOR_MODE_128_ARGB_AX
;
7965 cntl
|= CURSOR_MODE_256_ARGB_AX
;
7972 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
7973 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7975 if (intel_crtc
->cursor_cntl
!= cntl
) {
7976 I915_WRITE(CURCNTR(pipe
), cntl
);
7977 POSTING_READ(CURCNTR(pipe
));
7978 intel_crtc
->cursor_cntl
= cntl
;
7981 /* and commit changes on next vblank */
7982 I915_WRITE(CURBASE(pipe
), base
);
7983 POSTING_READ(CURBASE(pipe
));
7986 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7987 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7990 struct drm_device
*dev
= crtc
->dev
;
7991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7992 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7993 int pipe
= intel_crtc
->pipe
;
7994 int x
= intel_crtc
->cursor_x
;
7995 int y
= intel_crtc
->cursor_y
;
7996 u32 base
= 0, pos
= 0;
7999 base
= intel_crtc
->cursor_addr
;
8001 if (x
>= intel_crtc
->config
.pipe_src_w
)
8004 if (y
>= intel_crtc
->config
.pipe_src_h
)
8008 if (x
+ intel_crtc
->cursor_width
<= 0)
8011 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8014 pos
|= x
<< CURSOR_X_SHIFT
;
8017 if (y
+ intel_crtc
->cursor_height
<= 0)
8020 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8023 pos
|= y
<< CURSOR_Y_SHIFT
;
8025 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8028 I915_WRITE(CURPOS(pipe
), pos
);
8030 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8031 ivb_update_cursor(crtc
, base
);
8032 else if (IS_845G(dev
) || IS_I865G(dev
))
8033 i845_update_cursor(crtc
, base
);
8035 i9xx_update_cursor(crtc
, base
);
8036 intel_crtc
->cursor_base
= base
;
8039 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
8040 struct drm_file
*file
,
8042 uint32_t width
, uint32_t height
)
8044 struct drm_device
*dev
= crtc
->dev
;
8045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8046 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8047 struct drm_i915_gem_object
*obj
;
8052 /* if we want to turn off the cursor ignore width and height */
8054 DRM_DEBUG_KMS("cursor off\n");
8057 mutex_lock(&dev
->struct_mutex
);
8061 /* Check for which cursor types we support */
8062 if (!((width
== 64 && height
== 64) ||
8063 (width
== 128 && height
== 128 && !IS_GEN2(dev
)) ||
8064 (width
== 256 && height
== 256 && !IS_GEN2(dev
)))) {
8065 DRM_DEBUG("Cursor dimension not supported\n");
8069 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
8070 if (&obj
->base
== NULL
)
8073 if (obj
->base
.size
< width
* height
* 4) {
8074 DRM_DEBUG_KMS("buffer is to small\n");
8079 /* we only need to pin inside GTT if cursor is non-phy */
8080 mutex_lock(&dev
->struct_mutex
);
8081 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8084 if (obj
->tiling_mode
) {
8085 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8090 /* Note that the w/a also requires 2 PTE of padding following
8091 * the bo. We currently fill all unused PTE with the shadow
8092 * page and so we should always have valid PTE following the
8093 * cursor preventing the VT-d warning.
8096 if (need_vtd_wa(dev
))
8097 alignment
= 64*1024;
8099 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8101 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8105 ret
= i915_gem_object_put_fence(obj
);
8107 DRM_DEBUG_KMS("failed to release fence for cursor");
8111 addr
= i915_gem_obj_ggtt_offset(obj
);
8113 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8114 ret
= i915_gem_object_attach_phys(obj
, align
);
8116 DRM_DEBUG_KMS("failed to attach phys object\n");
8119 addr
= obj
->phys_handle
->busaddr
;
8123 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
8126 if (intel_crtc
->cursor_bo
) {
8127 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8128 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8129 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
8132 mutex_unlock(&dev
->struct_mutex
);
8134 old_width
= intel_crtc
->cursor_width
;
8136 intel_crtc
->cursor_addr
= addr
;
8137 intel_crtc
->cursor_bo
= obj
;
8138 intel_crtc
->cursor_width
= width
;
8139 intel_crtc
->cursor_height
= height
;
8141 if (intel_crtc
->active
) {
8142 if (old_width
!= width
)
8143 intel_update_watermarks(crtc
);
8144 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8149 i915_gem_object_unpin_from_display_plane(obj
);
8151 mutex_unlock(&dev
->struct_mutex
);
8153 drm_gem_object_unreference_unlocked(&obj
->base
);
8157 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
8159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8161 intel_crtc
->cursor_x
= clamp_t(int, x
, SHRT_MIN
, SHRT_MAX
);
8162 intel_crtc
->cursor_y
= clamp_t(int, y
, SHRT_MIN
, SHRT_MAX
);
8164 if (intel_crtc
->active
)
8165 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8170 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8171 u16
*blue
, uint32_t start
, uint32_t size
)
8173 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8176 for (i
= start
; i
< end
; i
++) {
8177 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8178 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8179 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8182 intel_crtc_load_lut(crtc
);
8185 /* VESA 640x480x72Hz mode to set on the pipe */
8186 static struct drm_display_mode load_detect_mode
= {
8187 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8188 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8191 struct drm_framebuffer
*
8192 __intel_framebuffer_create(struct drm_device
*dev
,
8193 struct drm_mode_fb_cmd2
*mode_cmd
,
8194 struct drm_i915_gem_object
*obj
)
8196 struct intel_framebuffer
*intel_fb
;
8199 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8201 drm_gem_object_unreference_unlocked(&obj
->base
);
8202 return ERR_PTR(-ENOMEM
);
8205 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8209 return &intel_fb
->base
;
8211 drm_gem_object_unreference_unlocked(&obj
->base
);
8214 return ERR_PTR(ret
);
8217 static struct drm_framebuffer
*
8218 intel_framebuffer_create(struct drm_device
*dev
,
8219 struct drm_mode_fb_cmd2
*mode_cmd
,
8220 struct drm_i915_gem_object
*obj
)
8222 struct drm_framebuffer
*fb
;
8225 ret
= i915_mutex_lock_interruptible(dev
);
8227 return ERR_PTR(ret
);
8228 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8229 mutex_unlock(&dev
->struct_mutex
);
8235 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8237 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8238 return ALIGN(pitch
, 64);
8242 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8244 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8245 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
8248 static struct drm_framebuffer
*
8249 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8250 struct drm_display_mode
*mode
,
8253 struct drm_i915_gem_object
*obj
;
8254 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8256 obj
= i915_gem_alloc_object(dev
,
8257 intel_framebuffer_size_for_mode(mode
, bpp
));
8259 return ERR_PTR(-ENOMEM
);
8261 mode_cmd
.width
= mode
->hdisplay
;
8262 mode_cmd
.height
= mode
->vdisplay
;
8263 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8265 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8267 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8270 static struct drm_framebuffer
*
8271 mode_fits_in_fbdev(struct drm_device
*dev
,
8272 struct drm_display_mode
*mode
)
8274 #ifdef CONFIG_DRM_I915_FBDEV
8275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8276 struct drm_i915_gem_object
*obj
;
8277 struct drm_framebuffer
*fb
;
8279 if (!dev_priv
->fbdev
)
8282 if (!dev_priv
->fbdev
->fb
)
8285 obj
= dev_priv
->fbdev
->fb
->obj
;
8288 fb
= &dev_priv
->fbdev
->fb
->base
;
8289 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8290 fb
->bits_per_pixel
))
8293 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8302 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8303 struct drm_display_mode
*mode
,
8304 struct intel_load_detect_pipe
*old
,
8305 struct drm_modeset_acquire_ctx
*ctx
)
8307 struct intel_crtc
*intel_crtc
;
8308 struct intel_encoder
*intel_encoder
=
8309 intel_attached_encoder(connector
);
8310 struct drm_crtc
*possible_crtc
;
8311 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8312 struct drm_crtc
*crtc
= NULL
;
8313 struct drm_device
*dev
= encoder
->dev
;
8314 struct drm_framebuffer
*fb
;
8315 struct drm_mode_config
*config
= &dev
->mode_config
;
8318 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8319 connector
->base
.id
, connector
->name
,
8320 encoder
->base
.id
, encoder
->name
);
8322 drm_modeset_acquire_init(ctx
, 0);
8325 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8330 * Algorithm gets a little messy:
8332 * - if the connector already has an assigned crtc, use it (but make
8333 * sure it's on first)
8335 * - try to find the first unused crtc that can drive this connector,
8336 * and use that if we find one
8339 /* See if we already have a CRTC for this connector */
8340 if (encoder
->crtc
) {
8341 crtc
= encoder
->crtc
;
8343 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8347 old
->dpms_mode
= connector
->dpms
;
8348 old
->load_detect_temp
= false;
8350 /* Make sure the crtc and connector are running */
8351 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8352 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8357 /* Find an unused one (if possible) */
8358 for_each_crtc(dev
, possible_crtc
) {
8360 if (!(encoder
->possible_crtcs
& (1 << i
)))
8362 if (!possible_crtc
->enabled
) {
8363 crtc
= possible_crtc
;
8369 * If we didn't find an unused CRTC, don't use any.
8372 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8376 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8379 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8380 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8382 intel_crtc
= to_intel_crtc(crtc
);
8383 intel_crtc
->new_enabled
= true;
8384 intel_crtc
->new_config
= &intel_crtc
->config
;
8385 old
->dpms_mode
= connector
->dpms
;
8386 old
->load_detect_temp
= true;
8387 old
->release_fb
= NULL
;
8390 mode
= &load_detect_mode
;
8392 /* We need a framebuffer large enough to accommodate all accesses
8393 * that the plane may generate whilst we perform load detection.
8394 * We can not rely on the fbcon either being present (we get called
8395 * during its initialisation to detect all boot displays, or it may
8396 * not even exist) or that it is large enough to satisfy the
8399 fb
= mode_fits_in_fbdev(dev
, mode
);
8401 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8402 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8403 old
->release_fb
= fb
;
8405 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8407 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8411 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8412 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8413 if (old
->release_fb
)
8414 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8418 /* let the connector get through one full cycle before testing */
8419 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8423 intel_crtc
->new_enabled
= crtc
->enabled
;
8424 if (intel_crtc
->new_enabled
)
8425 intel_crtc
->new_config
= &intel_crtc
->config
;
8427 intel_crtc
->new_config
= NULL
;
8429 if (ret
== -EDEADLK
) {
8430 drm_modeset_backoff(ctx
);
8434 drm_modeset_drop_locks(ctx
);
8435 drm_modeset_acquire_fini(ctx
);
8440 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8441 struct intel_load_detect_pipe
*old
,
8442 struct drm_modeset_acquire_ctx
*ctx
)
8444 struct intel_encoder
*intel_encoder
=
8445 intel_attached_encoder(connector
);
8446 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8447 struct drm_crtc
*crtc
= encoder
->crtc
;
8448 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8451 connector
->base
.id
, connector
->name
,
8452 encoder
->base
.id
, encoder
->name
);
8454 if (old
->load_detect_temp
) {
8455 to_intel_connector(connector
)->new_encoder
= NULL
;
8456 intel_encoder
->new_crtc
= NULL
;
8457 intel_crtc
->new_enabled
= false;
8458 intel_crtc
->new_config
= NULL
;
8459 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8461 if (old
->release_fb
) {
8462 drm_framebuffer_unregister_private(old
->release_fb
);
8463 drm_framebuffer_unreference(old
->release_fb
);
8470 /* Switch crtc and encoder back off if necessary */
8471 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8472 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8475 drm_modeset_drop_locks(ctx
);
8476 drm_modeset_acquire_fini(ctx
);
8479 static int i9xx_pll_refclk(struct drm_device
*dev
,
8480 const struct intel_crtc_config
*pipe_config
)
8482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8483 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8485 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8486 return dev_priv
->vbt
.lvds_ssc_freq
;
8487 else if (HAS_PCH_SPLIT(dev
))
8489 else if (!IS_GEN2(dev
))
8495 /* Returns the clock of the currently programmed mode of the given pipe. */
8496 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8497 struct intel_crtc_config
*pipe_config
)
8499 struct drm_device
*dev
= crtc
->base
.dev
;
8500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8501 int pipe
= pipe_config
->cpu_transcoder
;
8502 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8504 intel_clock_t clock
;
8505 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8507 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8508 fp
= pipe_config
->dpll_hw_state
.fp0
;
8510 fp
= pipe_config
->dpll_hw_state
.fp1
;
8512 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8513 if (IS_PINEVIEW(dev
)) {
8514 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8515 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8517 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8518 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8521 if (!IS_GEN2(dev
)) {
8522 if (IS_PINEVIEW(dev
))
8523 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8524 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8526 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8527 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8529 switch (dpll
& DPLL_MODE_MASK
) {
8530 case DPLLB_MODE_DAC_SERIAL
:
8531 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8534 case DPLLB_MODE_LVDS
:
8535 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8539 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8540 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8544 if (IS_PINEVIEW(dev
))
8545 pineview_clock(refclk
, &clock
);
8547 i9xx_clock(refclk
, &clock
);
8549 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8550 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8553 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8554 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8556 if (lvds
& LVDS_CLKB_POWER_UP
)
8561 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8564 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8565 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8567 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8573 i9xx_clock(refclk
, &clock
);
8577 * This value includes pixel_multiplier. We will use
8578 * port_clock to compute adjusted_mode.crtc_clock in the
8579 * encoder's get_config() function.
8581 pipe_config
->port_clock
= clock
.dot
;
8584 int intel_dotclock_calculate(int link_freq
,
8585 const struct intel_link_m_n
*m_n
)
8588 * The calculation for the data clock is:
8589 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8590 * But we want to avoid losing precison if possible, so:
8591 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8593 * and the link clock is simpler:
8594 * link_clock = (m * link_clock) / n
8600 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8603 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8604 struct intel_crtc_config
*pipe_config
)
8606 struct drm_device
*dev
= crtc
->base
.dev
;
8608 /* read out port_clock from the DPLL */
8609 i9xx_crtc_clock_get(crtc
, pipe_config
);
8612 * This value does not include pixel_multiplier.
8613 * We will check that port_clock and adjusted_mode.crtc_clock
8614 * agree once we know their relationship in the encoder's
8615 * get_config() function.
8617 pipe_config
->adjusted_mode
.crtc_clock
=
8618 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8619 &pipe_config
->fdi_m_n
);
8622 /** Returns the currently programmed mode of the given pipe. */
8623 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8624 struct drm_crtc
*crtc
)
8626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8627 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8628 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8629 struct drm_display_mode
*mode
;
8630 struct intel_crtc_config pipe_config
;
8631 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8632 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8633 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8634 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8635 enum pipe pipe
= intel_crtc
->pipe
;
8637 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8642 * Construct a pipe_config sufficient for getting the clock info
8643 * back out of crtc_clock_get.
8645 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8646 * to use a real value here instead.
8648 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8649 pipe_config
.pixel_multiplier
= 1;
8650 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8651 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8652 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8653 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8655 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8656 mode
->hdisplay
= (htot
& 0xffff) + 1;
8657 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8658 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8659 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8660 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8661 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8662 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8663 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8665 drm_mode_set_name(mode
);
8670 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
8672 struct drm_device
*dev
= crtc
->dev
;
8673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8674 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8675 int pipe
= intel_crtc
->pipe
;
8676 int dpll_reg
= DPLL(pipe
);
8679 if (HAS_PCH_SPLIT(dev
))
8682 if (!dev_priv
->lvds_downclock_avail
)
8685 dpll
= I915_READ(dpll_reg
);
8686 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8687 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8689 assert_panel_unlocked(dev_priv
, pipe
);
8691 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8692 I915_WRITE(dpll_reg
, dpll
);
8693 intel_wait_for_vblank(dev
, pipe
);
8695 dpll
= I915_READ(dpll_reg
);
8696 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8697 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8701 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8703 struct drm_device
*dev
= crtc
->dev
;
8704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8705 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8707 if (HAS_PCH_SPLIT(dev
))
8710 if (!dev_priv
->lvds_downclock_avail
)
8714 * Since this is called by a timer, we should never get here in
8717 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8718 int pipe
= intel_crtc
->pipe
;
8719 int dpll_reg
= DPLL(pipe
);
8722 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8724 assert_panel_unlocked(dev_priv
, pipe
);
8726 dpll
= I915_READ(dpll_reg
);
8727 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8728 I915_WRITE(dpll_reg
, dpll
);
8729 intel_wait_for_vblank(dev
, pipe
);
8730 dpll
= I915_READ(dpll_reg
);
8731 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8732 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8737 void intel_mark_busy(struct drm_device
*dev
)
8739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8741 if (dev_priv
->mm
.busy
)
8744 intel_runtime_pm_get(dev_priv
);
8745 i915_update_gfx_val(dev_priv
);
8746 dev_priv
->mm
.busy
= true;
8749 void intel_mark_idle(struct drm_device
*dev
)
8751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8752 struct drm_crtc
*crtc
;
8754 if (!dev_priv
->mm
.busy
)
8757 dev_priv
->mm
.busy
= false;
8759 if (!i915
.powersave
)
8762 for_each_crtc(dev
, crtc
) {
8763 if (!crtc
->primary
->fb
)
8766 intel_decrease_pllclock(crtc
);
8769 if (INTEL_INFO(dev
)->gen
>= 6)
8770 gen6_rps_idle(dev
->dev_private
);
8773 intel_runtime_pm_put(dev_priv
);
8776 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
8777 struct intel_engine_cs
*ring
)
8779 struct drm_device
*dev
= obj
->base
.dev
;
8780 struct drm_crtc
*crtc
;
8782 if (!i915
.powersave
)
8785 for_each_crtc(dev
, crtc
) {
8786 if (!crtc
->primary
->fb
)
8789 if (to_intel_framebuffer(crtc
->primary
->fb
)->obj
!= obj
)
8792 intel_increase_pllclock(crtc
);
8793 if (ring
&& intel_fbc_enabled(dev
))
8794 ring
->fbc_dirty
= true;
8798 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8801 struct drm_device
*dev
= crtc
->dev
;
8802 struct intel_unpin_work
*work
;
8803 unsigned long flags
;
8805 spin_lock_irqsave(&dev
->event_lock
, flags
);
8806 work
= intel_crtc
->unpin_work
;
8807 intel_crtc
->unpin_work
= NULL
;
8808 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8811 cancel_work_sync(&work
->work
);
8815 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
8817 drm_crtc_cleanup(crtc
);
8822 static void intel_unpin_work_fn(struct work_struct
*__work
)
8824 struct intel_unpin_work
*work
=
8825 container_of(__work
, struct intel_unpin_work
, work
);
8826 struct drm_device
*dev
= work
->crtc
->dev
;
8828 mutex_lock(&dev
->struct_mutex
);
8829 intel_unpin_fb_obj(work
->old_fb_obj
);
8830 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8831 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8833 intel_update_fbc(dev
);
8834 mutex_unlock(&dev
->struct_mutex
);
8836 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
8837 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
8842 static void do_intel_finish_page_flip(struct drm_device
*dev
,
8843 struct drm_crtc
*crtc
)
8845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8846 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8847 struct intel_unpin_work
*work
;
8848 unsigned long flags
;
8850 /* Ignore early vblank irqs */
8851 if (intel_crtc
== NULL
)
8854 spin_lock_irqsave(&dev
->event_lock
, flags
);
8855 work
= intel_crtc
->unpin_work
;
8857 /* Ensure we don't miss a work->pending update ... */
8860 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
8861 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8865 /* and that the unpin work is consistent wrt ->pending. */
8868 intel_crtc
->unpin_work
= NULL
;
8871 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
8873 drm_crtc_vblank_put(crtc
);
8875 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8877 wake_up_all(&dev_priv
->pending_flip_queue
);
8879 queue_work(dev_priv
->wq
, &work
->work
);
8881 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
8884 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
8886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8887 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
8889 do_intel_finish_page_flip(dev
, crtc
);
8892 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
8894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8895 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
8897 do_intel_finish_page_flip(dev
, crtc
);
8900 /* Is 'a' after or equal to 'b'? */
8901 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
8903 return !((a
- b
) & 0x80000000);
8906 static bool page_flip_finished(struct intel_crtc
*crtc
)
8908 struct drm_device
*dev
= crtc
->base
.dev
;
8909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8912 * The relevant registers doen't exist on pre-ctg.
8913 * As the flip done interrupt doesn't trigger for mmio
8914 * flips on gmch platforms, a flip count check isn't
8915 * really needed there. But since ctg has the registers,
8916 * include it in the check anyway.
8918 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
8922 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8923 * used the same base address. In that case the mmio flip might
8924 * have completed, but the CS hasn't even executed the flip yet.
8926 * A flip count check isn't enough as the CS might have updated
8927 * the base address just after start of vblank, but before we
8928 * managed to process the interrupt. This means we'd complete the
8931 * Combining both checks should get us a good enough result. It may
8932 * still happen that the CS flip has been executed, but has not
8933 * yet actually completed. But in case the base address is the same
8934 * anyway, we don't really care.
8936 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
8937 crtc
->unpin_work
->gtt_offset
&&
8938 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
8939 crtc
->unpin_work
->flip_count
);
8942 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
8944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8945 struct intel_crtc
*intel_crtc
=
8946 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
8947 unsigned long flags
;
8949 /* NB: An MMIO update of the plane base pointer will also
8950 * generate a page-flip completion irq, i.e. every modeset
8951 * is also accompanied by a spurious intel_prepare_page_flip().
8953 spin_lock_irqsave(&dev
->event_lock
, flags
);
8954 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
8955 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
8956 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8959 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
8961 /* Ensure that the work item is consistent when activating it ... */
8963 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
8964 /* and that it is marked active as soon as the irq could fire. */
8968 static int intel_gen2_queue_flip(struct drm_device
*dev
,
8969 struct drm_crtc
*crtc
,
8970 struct drm_framebuffer
*fb
,
8971 struct drm_i915_gem_object
*obj
,
8972 struct intel_engine_cs
*ring
,
8975 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8979 ret
= intel_ring_begin(ring
, 6);
8983 /* Can't queue multiple flips, so wait for the previous
8984 * one to finish before executing the next.
8986 if (intel_crtc
->plane
)
8987 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8989 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8990 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8991 intel_ring_emit(ring
, MI_NOOP
);
8992 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8993 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8994 intel_ring_emit(ring
, fb
->pitches
[0]);
8995 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
8996 intel_ring_emit(ring
, 0); /* aux display base address, unused */
8998 intel_mark_page_flip_active(intel_crtc
);
8999 __intel_ring_advance(ring
);
9003 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9004 struct drm_crtc
*crtc
,
9005 struct drm_framebuffer
*fb
,
9006 struct drm_i915_gem_object
*obj
,
9007 struct intel_engine_cs
*ring
,
9010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9014 ret
= intel_ring_begin(ring
, 6);
9018 if (intel_crtc
->plane
)
9019 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9021 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9022 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9023 intel_ring_emit(ring
, MI_NOOP
);
9024 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9025 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9026 intel_ring_emit(ring
, fb
->pitches
[0]);
9027 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9028 intel_ring_emit(ring
, MI_NOOP
);
9030 intel_mark_page_flip_active(intel_crtc
);
9031 __intel_ring_advance(ring
);
9035 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9036 struct drm_crtc
*crtc
,
9037 struct drm_framebuffer
*fb
,
9038 struct drm_i915_gem_object
*obj
,
9039 struct intel_engine_cs
*ring
,
9042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9043 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9044 uint32_t pf
, pipesrc
;
9047 ret
= intel_ring_begin(ring
, 4);
9051 /* i965+ uses the linear or tiled offsets from the
9052 * Display Registers (which do not change across a page-flip)
9053 * so we need only reprogram the base address.
9055 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9056 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9057 intel_ring_emit(ring
, fb
->pitches
[0]);
9058 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9061 /* XXX Enabling the panel-fitter across page-flip is so far
9062 * untested on non-native modes, so ignore it for now.
9063 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9066 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9067 intel_ring_emit(ring
, pf
| pipesrc
);
9069 intel_mark_page_flip_active(intel_crtc
);
9070 __intel_ring_advance(ring
);
9074 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9075 struct drm_crtc
*crtc
,
9076 struct drm_framebuffer
*fb
,
9077 struct drm_i915_gem_object
*obj
,
9078 struct intel_engine_cs
*ring
,
9081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9083 uint32_t pf
, pipesrc
;
9086 ret
= intel_ring_begin(ring
, 4);
9090 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9091 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9092 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9093 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9095 /* Contrary to the suggestions in the documentation,
9096 * "Enable Panel Fitter" does not seem to be required when page
9097 * flipping with a non-native mode, and worse causes a normal
9099 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9102 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9103 intel_ring_emit(ring
, pf
| pipesrc
);
9105 intel_mark_page_flip_active(intel_crtc
);
9106 __intel_ring_advance(ring
);
9110 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9111 struct drm_crtc
*crtc
,
9112 struct drm_framebuffer
*fb
,
9113 struct drm_i915_gem_object
*obj
,
9114 struct intel_engine_cs
*ring
,
9117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9118 uint32_t plane_bit
= 0;
9121 switch (intel_crtc
->plane
) {
9123 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9126 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9129 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9132 WARN_ONCE(1, "unknown plane in flip command\n");
9137 if (ring
->id
== RCS
) {
9140 * On Gen 8, SRM is now taking an extra dword to accommodate
9141 * 48bits addresses, and we need a NOOP for the batch size to
9149 * BSpec MI_DISPLAY_FLIP for IVB:
9150 * "The full packet must be contained within the same cache line."
9152 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9153 * cacheline, if we ever start emitting more commands before
9154 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9155 * then do the cacheline alignment, and finally emit the
9158 ret
= intel_ring_cacheline_align(ring
);
9162 ret
= intel_ring_begin(ring
, len
);
9166 /* Unmask the flip-done completion message. Note that the bspec says that
9167 * we should do this for both the BCS and RCS, and that we must not unmask
9168 * more than one flip event at any time (or ensure that one flip message
9169 * can be sent by waiting for flip-done prior to queueing new flips).
9170 * Experimentation says that BCS works despite DERRMR masking all
9171 * flip-done completion events and that unmasking all planes at once
9172 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9173 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9175 if (ring
->id
== RCS
) {
9176 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9177 intel_ring_emit(ring
, DERRMR
);
9178 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9179 DERRMR_PIPEB_PRI_FLIP_DONE
|
9180 DERRMR_PIPEC_PRI_FLIP_DONE
));
9182 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9183 MI_SRM_LRM_GLOBAL_GTT
);
9185 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9186 MI_SRM_LRM_GLOBAL_GTT
);
9187 intel_ring_emit(ring
, DERRMR
);
9188 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9190 intel_ring_emit(ring
, 0);
9191 intel_ring_emit(ring
, MI_NOOP
);
9195 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9196 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9197 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9198 intel_ring_emit(ring
, (MI_NOOP
));
9200 intel_mark_page_flip_active(intel_crtc
);
9201 __intel_ring_advance(ring
);
9205 static int intel_default_queue_flip(struct drm_device
*dev
,
9206 struct drm_crtc
*crtc
,
9207 struct drm_framebuffer
*fb
,
9208 struct drm_i915_gem_object
*obj
,
9209 struct intel_engine_cs
*ring
,
9215 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9216 struct drm_framebuffer
*fb
,
9217 struct drm_pending_vblank_event
*event
,
9218 uint32_t page_flip_flags
)
9220 struct drm_device
*dev
= crtc
->dev
;
9221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9222 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9223 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
9224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9225 struct intel_unpin_work
*work
;
9226 struct intel_engine_cs
*ring
;
9227 unsigned long flags
;
9230 /* Can't change pixel format via MI display flips. */
9231 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9235 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9236 * Note that pitch changes could also affect these register.
9238 if (INTEL_INFO(dev
)->gen
> 3 &&
9239 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9240 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9243 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9246 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9250 work
->event
= event
;
9252 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
9253 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9255 ret
= drm_crtc_vblank_get(crtc
);
9259 /* We borrow the event spin lock for protecting unpin_work */
9260 spin_lock_irqsave(&dev
->event_lock
, flags
);
9261 if (intel_crtc
->unpin_work
) {
9262 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9264 drm_crtc_vblank_put(crtc
);
9266 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9269 intel_crtc
->unpin_work
= work
;
9270 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9272 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9273 flush_workqueue(dev_priv
->wq
);
9275 ret
= i915_mutex_lock_interruptible(dev
);
9279 /* Reference the objects for the scheduled work. */
9280 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9281 drm_gem_object_reference(&obj
->base
);
9283 crtc
->primary
->fb
= fb
;
9285 work
->pending_flip_obj
= obj
;
9287 work
->enable_stall_check
= true;
9289 atomic_inc(&intel_crtc
->unpin_work_count
);
9290 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9292 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9293 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc
->pipe
)) + 1;
9295 if (IS_VALLEYVIEW(dev
)) {
9296 ring
= &dev_priv
->ring
[BCS
];
9297 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9299 if (ring
== NULL
|| ring
->id
!= RCS
)
9300 ring
= &dev_priv
->ring
[BCS
];
9302 ring
= &dev_priv
->ring
[RCS
];
9305 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9307 goto cleanup_pending
;
9310 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9312 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
, page_flip_flags
);
9316 intel_disable_fbc(dev
);
9317 intel_mark_fb_busy(obj
, NULL
);
9318 mutex_unlock(&dev
->struct_mutex
);
9320 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9325 intel_unpin_fb_obj(obj
);
9327 atomic_dec(&intel_crtc
->unpin_work_count
);
9328 crtc
->primary
->fb
= old_fb
;
9329 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9330 drm_gem_object_unreference(&obj
->base
);
9331 mutex_unlock(&dev
->struct_mutex
);
9334 spin_lock_irqsave(&dev
->event_lock
, flags
);
9335 intel_crtc
->unpin_work
= NULL
;
9336 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9338 drm_crtc_vblank_put(crtc
);
9344 intel_crtc_wait_for_pending_flips(crtc
);
9345 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9346 if (ret
== 0 && event
)
9347 drm_send_vblank_event(dev
, intel_crtc
->pipe
, event
);
9352 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9353 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9354 .load_lut
= intel_crtc_load_lut
,
9358 * intel_modeset_update_staged_output_state
9360 * Updates the staged output configuration state, e.g. after we've read out the
9363 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9365 struct intel_crtc
*crtc
;
9366 struct intel_encoder
*encoder
;
9367 struct intel_connector
*connector
;
9369 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9371 connector
->new_encoder
=
9372 to_intel_encoder(connector
->base
.encoder
);
9375 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9378 to_intel_crtc(encoder
->base
.crtc
);
9381 for_each_intel_crtc(dev
, crtc
) {
9382 crtc
->new_enabled
= crtc
->base
.enabled
;
9384 if (crtc
->new_enabled
)
9385 crtc
->new_config
= &crtc
->config
;
9387 crtc
->new_config
= NULL
;
9392 * intel_modeset_commit_output_state
9394 * This function copies the stage display pipe configuration to the real one.
9396 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9398 struct intel_crtc
*crtc
;
9399 struct intel_encoder
*encoder
;
9400 struct intel_connector
*connector
;
9402 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9404 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9407 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9409 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9412 for_each_intel_crtc(dev
, crtc
) {
9413 crtc
->base
.enabled
= crtc
->new_enabled
;
9418 connected_sink_compute_bpp(struct intel_connector
*connector
,
9419 struct intel_crtc_config
*pipe_config
)
9421 int bpp
= pipe_config
->pipe_bpp
;
9423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9424 connector
->base
.base
.id
,
9425 connector
->base
.name
);
9427 /* Don't use an invalid EDID bpc value */
9428 if (connector
->base
.display_info
.bpc
&&
9429 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9430 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9431 bpp
, connector
->base
.display_info
.bpc
*3);
9432 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9435 /* Clamp bpp to 8 on screens without EDID 1.4 */
9436 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9437 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9439 pipe_config
->pipe_bpp
= 24;
9444 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9445 struct drm_framebuffer
*fb
,
9446 struct intel_crtc_config
*pipe_config
)
9448 struct drm_device
*dev
= crtc
->base
.dev
;
9449 struct intel_connector
*connector
;
9452 switch (fb
->pixel_format
) {
9454 bpp
= 8*3; /* since we go through a colormap */
9456 case DRM_FORMAT_XRGB1555
:
9457 case DRM_FORMAT_ARGB1555
:
9458 /* checked in intel_framebuffer_init already */
9459 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
9461 case DRM_FORMAT_RGB565
:
9462 bpp
= 6*3; /* min is 18bpp */
9464 case DRM_FORMAT_XBGR8888
:
9465 case DRM_FORMAT_ABGR8888
:
9466 /* checked in intel_framebuffer_init already */
9467 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9469 case DRM_FORMAT_XRGB8888
:
9470 case DRM_FORMAT_ARGB8888
:
9473 case DRM_FORMAT_XRGB2101010
:
9474 case DRM_FORMAT_ARGB2101010
:
9475 case DRM_FORMAT_XBGR2101010
:
9476 case DRM_FORMAT_ABGR2101010
:
9477 /* checked in intel_framebuffer_init already */
9478 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
9482 /* TODO: gen4+ supports 16 bpc floating point, too. */
9484 DRM_DEBUG_KMS("unsupported depth\n");
9488 pipe_config
->pipe_bpp
= bpp
;
9490 /* Clamp display bpp to EDID value */
9491 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9493 if (!connector
->new_encoder
||
9494 connector
->new_encoder
->new_crtc
!= crtc
)
9497 connected_sink_compute_bpp(connector
, pipe_config
);
9503 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
9505 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9506 "type: 0x%x flags: 0x%x\n",
9508 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
9509 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
9510 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
9511 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
9514 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
9515 struct intel_crtc_config
*pipe_config
,
9516 const char *context
)
9518 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
9519 context
, pipe_name(crtc
->pipe
));
9521 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
9522 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9523 pipe_config
->pipe_bpp
, pipe_config
->dither
);
9524 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9525 pipe_config
->has_pch_encoder
,
9526 pipe_config
->fdi_lanes
,
9527 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
9528 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
9529 pipe_config
->fdi_m_n
.tu
);
9530 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9531 pipe_config
->has_dp_encoder
,
9532 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
9533 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
9534 pipe_config
->dp_m_n
.tu
);
9535 DRM_DEBUG_KMS("requested mode:\n");
9536 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
9537 DRM_DEBUG_KMS("adjusted mode:\n");
9538 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
9539 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
9540 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
9541 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9542 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
9543 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9544 pipe_config
->gmch_pfit
.control
,
9545 pipe_config
->gmch_pfit
.pgm_ratios
,
9546 pipe_config
->gmch_pfit
.lvds_border_bits
);
9547 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9548 pipe_config
->pch_pfit
.pos
,
9549 pipe_config
->pch_pfit
.size
,
9550 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
9551 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
9552 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
9555 static bool encoders_cloneable(const struct intel_encoder
*a
,
9556 const struct intel_encoder
*b
)
9558 /* masks could be asymmetric, so check both ways */
9559 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
9560 b
->cloneable
& (1 << a
->type
));
9563 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
9564 struct intel_encoder
*encoder
)
9566 struct drm_device
*dev
= crtc
->base
.dev
;
9567 struct intel_encoder
*source_encoder
;
9569 list_for_each_entry(source_encoder
,
9570 &dev
->mode_config
.encoder_list
, base
.head
) {
9571 if (source_encoder
->new_crtc
!= crtc
)
9574 if (!encoders_cloneable(encoder
, source_encoder
))
9581 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
9583 struct drm_device
*dev
= crtc
->base
.dev
;
9584 struct intel_encoder
*encoder
;
9586 list_for_each_entry(encoder
,
9587 &dev
->mode_config
.encoder_list
, base
.head
) {
9588 if (encoder
->new_crtc
!= crtc
)
9591 if (!check_single_encoder_cloning(crtc
, encoder
))
9598 static struct intel_crtc_config
*
9599 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
9600 struct drm_framebuffer
*fb
,
9601 struct drm_display_mode
*mode
)
9603 struct drm_device
*dev
= crtc
->dev
;
9604 struct intel_encoder
*encoder
;
9605 struct intel_crtc_config
*pipe_config
;
9606 int plane_bpp
, ret
= -EINVAL
;
9609 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
9610 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9611 return ERR_PTR(-EINVAL
);
9614 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
9616 return ERR_PTR(-ENOMEM
);
9618 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
9619 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
9621 pipe_config
->cpu_transcoder
=
9622 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
9623 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9626 * Sanitize sync polarity flags based on requested ones. If neither
9627 * positive or negative polarity is requested, treat this as meaning
9628 * negative polarity.
9630 if (!(pipe_config
->adjusted_mode
.flags
&
9631 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
9632 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
9634 if (!(pipe_config
->adjusted_mode
.flags
&
9635 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
9636 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
9638 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9639 * plane pixel format and any sink constraints into account. Returns the
9640 * source plane bpp so that dithering can be selected on mismatches
9641 * after encoders and crtc also have had their say. */
9642 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
9648 * Determine the real pipe dimensions. Note that stereo modes can
9649 * increase the actual pipe size due to the frame doubling and
9650 * insertion of additional space for blanks between the frame. This
9651 * is stored in the crtc timings. We use the requested mode to do this
9652 * computation to clearly distinguish it from the adjusted mode, which
9653 * can be changed by the connectors in the below retry loop.
9655 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
9656 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
9657 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
9660 /* Ensure the port clock defaults are reset when retrying. */
9661 pipe_config
->port_clock
= 0;
9662 pipe_config
->pixel_multiplier
= 1;
9664 /* Fill in default crtc timings, allow encoders to overwrite them. */
9665 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
9667 /* Pass our mode to the connectors and the CRTC to give them a chance to
9668 * adjust it according to limitations or connector properties, and also
9669 * a chance to reject the mode entirely.
9671 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9674 if (&encoder
->new_crtc
->base
!= crtc
)
9677 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
9678 DRM_DEBUG_KMS("Encoder config failure\n");
9683 /* Set default port clock if not overwritten by the encoder. Needs to be
9684 * done afterwards in case the encoder adjusts the mode. */
9685 if (!pipe_config
->port_clock
)
9686 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
9687 * pipe_config
->pixel_multiplier
;
9689 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
9691 DRM_DEBUG_KMS("CRTC fixup failed\n");
9696 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
9701 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9706 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
9707 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9708 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
9713 return ERR_PTR(ret
);
9716 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9717 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9719 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
9720 unsigned *prepare_pipes
, unsigned *disable_pipes
)
9722 struct intel_crtc
*intel_crtc
;
9723 struct drm_device
*dev
= crtc
->dev
;
9724 struct intel_encoder
*encoder
;
9725 struct intel_connector
*connector
;
9726 struct drm_crtc
*tmp_crtc
;
9728 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
9730 /* Check which crtcs have changed outputs connected to them, these need
9731 * to be part of the prepare_pipes mask. We don't (yet) support global
9732 * modeset across multiple crtcs, so modeset_pipes will only have one
9733 * bit set at most. */
9734 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9736 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
9739 if (connector
->base
.encoder
) {
9740 tmp_crtc
= connector
->base
.encoder
->crtc
;
9742 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9745 if (connector
->new_encoder
)
9747 1 << connector
->new_encoder
->new_crtc
->pipe
;
9750 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9752 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
9755 if (encoder
->base
.crtc
) {
9756 tmp_crtc
= encoder
->base
.crtc
;
9758 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9761 if (encoder
->new_crtc
)
9762 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
9765 /* Check for pipes that will be enabled/disabled ... */
9766 for_each_intel_crtc(dev
, intel_crtc
) {
9767 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
9770 if (!intel_crtc
->new_enabled
)
9771 *disable_pipes
|= 1 << intel_crtc
->pipe
;
9773 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9777 /* set_mode is also used to update properties on life display pipes. */
9778 intel_crtc
= to_intel_crtc(crtc
);
9779 if (intel_crtc
->new_enabled
)
9780 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9783 * For simplicity do a full modeset on any pipe where the output routing
9784 * changed. We could be more clever, but that would require us to be
9785 * more careful with calling the relevant encoder->mode_set functions.
9788 *modeset_pipes
= *prepare_pipes
;
9790 /* ... and mask these out. */
9791 *modeset_pipes
&= ~(*disable_pipes
);
9792 *prepare_pipes
&= ~(*disable_pipes
);
9795 * HACK: We don't (yet) fully support global modesets. intel_set_config
9796 * obies this rule, but the modeset restore mode of
9797 * intel_modeset_setup_hw_state does not.
9799 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
9800 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
9802 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9803 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
9806 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
9808 struct drm_encoder
*encoder
;
9809 struct drm_device
*dev
= crtc
->dev
;
9811 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
9812 if (encoder
->crtc
== crtc
)
9819 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
9821 struct intel_encoder
*intel_encoder
;
9822 struct intel_crtc
*intel_crtc
;
9823 struct drm_connector
*connector
;
9825 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
9827 if (!intel_encoder
->base
.crtc
)
9830 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
9832 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
9833 intel_encoder
->connectors_active
= false;
9836 intel_modeset_commit_output_state(dev
);
9838 /* Double check state. */
9839 for_each_intel_crtc(dev
, intel_crtc
) {
9840 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
9841 WARN_ON(intel_crtc
->new_config
&&
9842 intel_crtc
->new_config
!= &intel_crtc
->config
);
9843 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
9846 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9847 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
9850 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
9852 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
9853 struct drm_property
*dpms_property
=
9854 dev
->mode_config
.dpms_property
;
9856 connector
->dpms
= DRM_MODE_DPMS_ON
;
9857 drm_object_property_set_value(&connector
->base
,
9861 intel_encoder
= to_intel_encoder(connector
->encoder
);
9862 intel_encoder
->connectors_active
= true;
9868 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
9872 if (clock1
== clock2
)
9875 if (!clock1
|| !clock2
)
9878 diff
= abs(clock1
- clock2
);
9880 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
9886 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9887 list_for_each_entry((intel_crtc), \
9888 &(dev)->mode_config.crtc_list, \
9890 if (mask & (1 <<(intel_crtc)->pipe))
9893 intel_pipe_config_compare(struct drm_device
*dev
,
9894 struct intel_crtc_config
*current_config
,
9895 struct intel_crtc_config
*pipe_config
)
9897 #define PIPE_CONF_CHECK_X(name) \
9898 if (current_config->name != pipe_config->name) { \
9899 DRM_ERROR("mismatch in " #name " " \
9900 "(expected 0x%08x, found 0x%08x)\n", \
9901 current_config->name, \
9902 pipe_config->name); \
9906 #define PIPE_CONF_CHECK_I(name) \
9907 if (current_config->name != pipe_config->name) { \
9908 DRM_ERROR("mismatch in " #name " " \
9909 "(expected %i, found %i)\n", \
9910 current_config->name, \
9911 pipe_config->name); \
9915 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9916 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9917 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9918 "(expected %i, found %i)\n", \
9919 current_config->name & (mask), \
9920 pipe_config->name & (mask)); \
9924 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9925 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9926 DRM_ERROR("mismatch in " #name " " \
9927 "(expected %i, found %i)\n", \
9928 current_config->name, \
9929 pipe_config->name); \
9933 #define PIPE_CONF_QUIRK(quirk) \
9934 ((current_config->quirks | pipe_config->quirks) & (quirk))
9936 PIPE_CONF_CHECK_I(cpu_transcoder
);
9938 PIPE_CONF_CHECK_I(has_pch_encoder
);
9939 PIPE_CONF_CHECK_I(fdi_lanes
);
9940 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
9941 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
9942 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
9943 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
9944 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
9946 PIPE_CONF_CHECK_I(has_dp_encoder
);
9947 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
9948 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
9949 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
9950 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
9951 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
9953 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
9954 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
9955 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
9956 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
9957 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
9958 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
9960 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
9961 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
9962 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
9963 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
9964 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
9965 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
9967 PIPE_CONF_CHECK_I(pixel_multiplier
);
9968 PIPE_CONF_CHECK_I(has_hdmi_sink
);
9969 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
9971 PIPE_CONF_CHECK_I(limited_color_range
);
9973 PIPE_CONF_CHECK_I(has_audio
);
9975 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9976 DRM_MODE_FLAG_INTERLACE
);
9978 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
9979 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9980 DRM_MODE_FLAG_PHSYNC
);
9981 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9982 DRM_MODE_FLAG_NHSYNC
);
9983 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9984 DRM_MODE_FLAG_PVSYNC
);
9985 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9986 DRM_MODE_FLAG_NVSYNC
);
9989 PIPE_CONF_CHECK_I(pipe_src_w
);
9990 PIPE_CONF_CHECK_I(pipe_src_h
);
9993 * FIXME: BIOS likes to set up a cloned config with lvds+external
9994 * screen. Since we don't yet re-compute the pipe config when moving
9995 * just the lvds port away to another pipe the sw tracking won't match.
9997 * Proper atomic modesets with recomputed global state will fix this.
9998 * Until then just don't check gmch state for inherited modes.
10000 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10001 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10002 /* pfit ratios are autocomputed by the hw on gen4+ */
10003 if (INTEL_INFO(dev
)->gen
< 4)
10004 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10005 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10008 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10009 if (current_config
->pch_pfit
.enabled
) {
10010 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10011 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10014 /* BDW+ don't expose a synchronous way to read the state */
10015 if (IS_HASWELL(dev
))
10016 PIPE_CONF_CHECK_I(ips_enabled
);
10018 PIPE_CONF_CHECK_I(double_wide
);
10020 PIPE_CONF_CHECK_I(shared_dpll
);
10021 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10022 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10023 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10024 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10026 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10027 PIPE_CONF_CHECK_I(pipe_bpp
);
10029 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10030 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10032 #undef PIPE_CONF_CHECK_X
10033 #undef PIPE_CONF_CHECK_I
10034 #undef PIPE_CONF_CHECK_FLAGS
10035 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10036 #undef PIPE_CONF_QUIRK
10042 check_connector_state(struct drm_device
*dev
)
10044 struct intel_connector
*connector
;
10046 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10048 /* This also checks the encoder/connector hw state with the
10049 * ->get_hw_state callbacks. */
10050 intel_connector_check_state(connector
);
10052 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10053 "connector's staged encoder doesn't match current encoder\n");
10058 check_encoder_state(struct drm_device
*dev
)
10060 struct intel_encoder
*encoder
;
10061 struct intel_connector
*connector
;
10063 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10065 bool enabled
= false;
10066 bool active
= false;
10067 enum pipe pipe
, tracked_pipe
;
10069 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10070 encoder
->base
.base
.id
,
10071 encoder
->base
.name
);
10073 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10074 "encoder's stage crtc doesn't match current crtc\n");
10075 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10076 "encoder's active_connectors set, but no crtc\n");
10078 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10080 if (connector
->base
.encoder
!= &encoder
->base
)
10083 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10086 WARN(!!encoder
->base
.crtc
!= enabled
,
10087 "encoder's enabled state mismatch "
10088 "(expected %i, found %i)\n",
10089 !!encoder
->base
.crtc
, enabled
);
10090 WARN(active
&& !encoder
->base
.crtc
,
10091 "active encoder with no crtc\n");
10093 WARN(encoder
->connectors_active
!= active
,
10094 "encoder's computed active state doesn't match tracked active state "
10095 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10097 active
= encoder
->get_hw_state(encoder
, &pipe
);
10098 WARN(active
!= encoder
->connectors_active
,
10099 "encoder's hw state doesn't match sw tracking "
10100 "(expected %i, found %i)\n",
10101 encoder
->connectors_active
, active
);
10103 if (!encoder
->base
.crtc
)
10106 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10107 WARN(active
&& pipe
!= tracked_pipe
,
10108 "active encoder's pipe doesn't match"
10109 "(expected %i, found %i)\n",
10110 tracked_pipe
, pipe
);
10116 check_crtc_state(struct drm_device
*dev
)
10118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10119 struct intel_crtc
*crtc
;
10120 struct intel_encoder
*encoder
;
10121 struct intel_crtc_config pipe_config
;
10123 for_each_intel_crtc(dev
, crtc
) {
10124 bool enabled
= false;
10125 bool active
= false;
10127 memset(&pipe_config
, 0, sizeof(pipe_config
));
10129 DRM_DEBUG_KMS("[CRTC:%d]\n",
10130 crtc
->base
.base
.id
);
10132 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10133 "active crtc, but not enabled in sw tracking\n");
10135 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10137 if (encoder
->base
.crtc
!= &crtc
->base
)
10140 if (encoder
->connectors_active
)
10144 WARN(active
!= crtc
->active
,
10145 "crtc's computed active state doesn't match tracked active state "
10146 "(expected %i, found %i)\n", active
, crtc
->active
);
10147 WARN(enabled
!= crtc
->base
.enabled
,
10148 "crtc's computed enabled state doesn't match tracked enabled state "
10149 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10151 active
= dev_priv
->display
.get_pipe_config(crtc
,
10154 /* hw state is inconsistent with the pipe A quirk */
10155 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
10156 active
= crtc
->active
;
10158 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10161 if (encoder
->base
.crtc
!= &crtc
->base
)
10163 if (encoder
->get_hw_state(encoder
, &pipe
))
10164 encoder
->get_config(encoder
, &pipe_config
);
10167 WARN(crtc
->active
!= active
,
10168 "crtc active state doesn't match with hw state "
10169 "(expected %i, found %i)\n", crtc
->active
, active
);
10172 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10173 WARN(1, "pipe state doesn't match!\n");
10174 intel_dump_pipe_config(crtc
, &pipe_config
,
10176 intel_dump_pipe_config(crtc
, &crtc
->config
,
10183 check_shared_dpll_state(struct drm_device
*dev
)
10185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10186 struct intel_crtc
*crtc
;
10187 struct intel_dpll_hw_state dpll_hw_state
;
10190 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10191 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10192 int enabled_crtcs
= 0, active_crtcs
= 0;
10195 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10197 DRM_DEBUG_KMS("%s\n", pll
->name
);
10199 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10201 WARN(pll
->active
> pll
->refcount
,
10202 "more active pll users than references: %i vs %i\n",
10203 pll
->active
, pll
->refcount
);
10204 WARN(pll
->active
&& !pll
->on
,
10205 "pll in active use but not on in sw tracking\n");
10206 WARN(pll
->on
&& !pll
->active
,
10207 "pll in on but not on in use in sw tracking\n");
10208 WARN(pll
->on
!= active
,
10209 "pll on state mismatch (expected %i, found %i)\n",
10212 for_each_intel_crtc(dev
, crtc
) {
10213 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10215 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10218 WARN(pll
->active
!= active_crtcs
,
10219 "pll active crtcs mismatch (expected %i, found %i)\n",
10220 pll
->active
, active_crtcs
);
10221 WARN(pll
->refcount
!= enabled_crtcs
,
10222 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10223 pll
->refcount
, enabled_crtcs
);
10225 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10226 sizeof(dpll_hw_state
)),
10227 "pll hw state mismatch\n");
10232 intel_modeset_check_state(struct drm_device
*dev
)
10234 check_connector_state(dev
);
10235 check_encoder_state(dev
);
10236 check_crtc_state(dev
);
10237 check_shared_dpll_state(dev
);
10240 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10244 * FDI already provided one idea for the dotclock.
10245 * Yell if the encoder disagrees.
10247 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10248 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10249 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10252 static void update_scanline_offset(struct intel_crtc
*crtc
)
10254 struct drm_device
*dev
= crtc
->base
.dev
;
10257 * The scanline counter increments at the leading edge of hsync.
10259 * On most platforms it starts counting from vtotal-1 on the
10260 * first active line. That means the scanline counter value is
10261 * always one less than what we would expect. Ie. just after
10262 * start of vblank, which also occurs at start of hsync (on the
10263 * last active line), the scanline counter will read vblank_start-1.
10265 * On gen2 the scanline counter starts counting from 1 instead
10266 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10267 * to keep the value positive), instead of adding one.
10269 * On HSW+ the behaviour of the scanline counter depends on the output
10270 * type. For DP ports it behaves like most other platforms, but on HDMI
10271 * there's an extra 1 line difference. So we need to add two instead of
10272 * one to the value.
10274 if (IS_GEN2(dev
)) {
10275 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10278 vtotal
= mode
->crtc_vtotal
;
10279 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10282 crtc
->scanline_offset
= vtotal
- 1;
10283 } else if (HAS_DDI(dev
) &&
10284 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10285 crtc
->scanline_offset
= 2;
10287 crtc
->scanline_offset
= 1;
10290 static int __intel_set_mode(struct drm_crtc
*crtc
,
10291 struct drm_display_mode
*mode
,
10292 int x
, int y
, struct drm_framebuffer
*fb
)
10294 struct drm_device
*dev
= crtc
->dev
;
10295 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10296 struct drm_display_mode
*saved_mode
;
10297 struct intel_crtc_config
*pipe_config
= NULL
;
10298 struct intel_crtc
*intel_crtc
;
10299 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10302 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10306 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10307 &prepare_pipes
, &disable_pipes
);
10309 *saved_mode
= crtc
->mode
;
10311 /* Hack: Because we don't (yet) support global modeset on multiple
10312 * crtcs, we don't keep track of the new mode for more than one crtc.
10313 * Hence simply check whether any bit is set in modeset_pipes in all the
10314 * pieces of code that are not yet converted to deal with mutliple crtcs
10315 * changing their mode at the same time. */
10316 if (modeset_pipes
) {
10317 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10318 if (IS_ERR(pipe_config
)) {
10319 ret
= PTR_ERR(pipe_config
);
10320 pipe_config
= NULL
;
10324 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10326 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10330 * See if the config requires any additional preparation, e.g.
10331 * to adjust global state with pipes off. We need to do this
10332 * here so we can get the modeset_pipe updated config for the new
10333 * mode set on this crtc. For other crtcs we need to use the
10334 * adjusted_mode bits in the crtc directly.
10336 if (IS_VALLEYVIEW(dev
)) {
10337 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10339 /* may have added more to prepare_pipes than we should */
10340 prepare_pipes
&= ~disable_pipes
;
10343 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10344 intel_crtc_disable(&intel_crtc
->base
);
10346 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10347 if (intel_crtc
->base
.enabled
)
10348 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10351 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10352 * to set it here already despite that we pass it down the callchain.
10354 if (modeset_pipes
) {
10355 crtc
->mode
= *mode
;
10356 /* mode_set/enable/disable functions rely on a correct pipe
10358 to_intel_crtc(crtc
)->config
= *pipe_config
;
10359 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10362 * Calculate and store various constants which
10363 * are later needed by vblank and swap-completion
10364 * timestamping. They are derived from true hwmode.
10366 drm_calc_timestamping_constants(crtc
,
10367 &pipe_config
->adjusted_mode
);
10370 /* Only after disabling all output pipelines that will be changed can we
10371 * update the the output configuration. */
10372 intel_modeset_update_state(dev
, prepare_pipes
);
10374 if (dev_priv
->display
.modeset_global_resources
)
10375 dev_priv
->display
.modeset_global_resources(dev
);
10377 /* Set up the DPLL and any encoders state that needs to adjust or depend
10380 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10381 struct drm_framebuffer
*old_fb
;
10383 mutex_lock(&dev
->struct_mutex
);
10384 ret
= intel_pin_and_fence_fb_obj(dev
,
10385 to_intel_framebuffer(fb
)->obj
,
10388 DRM_ERROR("pin & fence failed\n");
10389 mutex_unlock(&dev
->struct_mutex
);
10392 old_fb
= crtc
->primary
->fb
;
10394 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
10395 mutex_unlock(&dev
->struct_mutex
);
10397 crtc
->primary
->fb
= fb
;
10401 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
10407 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10408 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10409 update_scanline_offset(intel_crtc
);
10411 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
10414 /* FIXME: add subpixel order */
10416 if (ret
&& crtc
->enabled
)
10417 crtc
->mode
= *saved_mode
;
10420 kfree(pipe_config
);
10425 static int intel_set_mode(struct drm_crtc
*crtc
,
10426 struct drm_display_mode
*mode
,
10427 int x
, int y
, struct drm_framebuffer
*fb
)
10431 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
10434 intel_modeset_check_state(crtc
->dev
);
10439 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
10441 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
10444 #undef for_each_intel_crtc_masked
10446 static void intel_set_config_free(struct intel_set_config
*config
)
10451 kfree(config
->save_connector_encoders
);
10452 kfree(config
->save_encoder_crtcs
);
10453 kfree(config
->save_crtc_enabled
);
10457 static int intel_set_config_save_state(struct drm_device
*dev
,
10458 struct intel_set_config
*config
)
10460 struct drm_crtc
*crtc
;
10461 struct drm_encoder
*encoder
;
10462 struct drm_connector
*connector
;
10465 config
->save_crtc_enabled
=
10466 kcalloc(dev
->mode_config
.num_crtc
,
10467 sizeof(bool), GFP_KERNEL
);
10468 if (!config
->save_crtc_enabled
)
10471 config
->save_encoder_crtcs
=
10472 kcalloc(dev
->mode_config
.num_encoder
,
10473 sizeof(struct drm_crtc
*), GFP_KERNEL
);
10474 if (!config
->save_encoder_crtcs
)
10477 config
->save_connector_encoders
=
10478 kcalloc(dev
->mode_config
.num_connector
,
10479 sizeof(struct drm_encoder
*), GFP_KERNEL
);
10480 if (!config
->save_connector_encoders
)
10483 /* Copy data. Note that driver private data is not affected.
10484 * Should anything bad happen only the expected state is
10485 * restored, not the drivers personal bookkeeping.
10488 for_each_crtc(dev
, crtc
) {
10489 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
10493 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
10494 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
10498 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10499 config
->save_connector_encoders
[count
++] = connector
->encoder
;
10505 static void intel_set_config_restore_state(struct drm_device
*dev
,
10506 struct intel_set_config
*config
)
10508 struct intel_crtc
*crtc
;
10509 struct intel_encoder
*encoder
;
10510 struct intel_connector
*connector
;
10514 for_each_intel_crtc(dev
, crtc
) {
10515 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
10517 if (crtc
->new_enabled
)
10518 crtc
->new_config
= &crtc
->config
;
10520 crtc
->new_config
= NULL
;
10524 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10525 encoder
->new_crtc
=
10526 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
10530 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
10531 connector
->new_encoder
=
10532 to_intel_encoder(config
->save_connector_encoders
[count
++]);
10537 is_crtc_connector_off(struct drm_mode_set
*set
)
10541 if (set
->num_connectors
== 0)
10544 if (WARN_ON(set
->connectors
== NULL
))
10547 for (i
= 0; i
< set
->num_connectors
; i
++)
10548 if (set
->connectors
[i
]->encoder
&&
10549 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
10550 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
10557 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
10558 struct intel_set_config
*config
)
10561 /* We should be able to check here if the fb has the same properties
10562 * and then just flip_or_move it */
10563 if (is_crtc_connector_off(set
)) {
10564 config
->mode_changed
= true;
10565 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
10566 /* If we have no fb then treat it as a full mode set */
10567 if (set
->crtc
->primary
->fb
== NULL
) {
10568 struct intel_crtc
*intel_crtc
=
10569 to_intel_crtc(set
->crtc
);
10571 if (intel_crtc
->active
&& i915
.fastboot
) {
10572 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10573 config
->fb_changed
= true;
10575 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10576 config
->mode_changed
= true;
10578 } else if (set
->fb
== NULL
) {
10579 config
->mode_changed
= true;
10580 } else if (set
->fb
->pixel_format
!=
10581 set
->crtc
->primary
->fb
->pixel_format
) {
10582 config
->mode_changed
= true;
10584 config
->fb_changed
= true;
10588 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
10589 config
->fb_changed
= true;
10591 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
10592 DRM_DEBUG_KMS("modes are different, full mode set\n");
10593 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
10594 drm_mode_debug_printmodeline(set
->mode
);
10595 config
->mode_changed
= true;
10598 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10599 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
10603 intel_modeset_stage_output_state(struct drm_device
*dev
,
10604 struct drm_mode_set
*set
,
10605 struct intel_set_config
*config
)
10607 struct intel_connector
*connector
;
10608 struct intel_encoder
*encoder
;
10609 struct intel_crtc
*crtc
;
10612 /* The upper layers ensure that we either disable a crtc or have a list
10613 * of connectors. For paranoia, double-check this. */
10614 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
10615 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
10617 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10619 /* Otherwise traverse passed in connector list and get encoders
10621 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
10622 if (set
->connectors
[ro
] == &connector
->base
) {
10623 connector
->new_encoder
= connector
->encoder
;
10628 /* If we disable the crtc, disable all its connectors. Also, if
10629 * the connector is on the changing crtc but not on the new
10630 * connector list, disable it. */
10631 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
10632 connector
->base
.encoder
&&
10633 connector
->base
.encoder
->crtc
== set
->crtc
) {
10634 connector
->new_encoder
= NULL
;
10636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10637 connector
->base
.base
.id
,
10638 connector
->base
.name
);
10642 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
10643 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10644 config
->mode_changed
= true;
10647 /* connector->new_encoder is now updated for all connectors. */
10649 /* Update crtc of enabled connectors. */
10650 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10652 struct drm_crtc
*new_crtc
;
10654 if (!connector
->new_encoder
)
10657 new_crtc
= connector
->new_encoder
->base
.crtc
;
10659 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
10660 if (set
->connectors
[ro
] == &connector
->base
)
10661 new_crtc
= set
->crtc
;
10664 /* Make sure the new CRTC will work with the encoder */
10665 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
10669 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
10671 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10672 connector
->base
.base
.id
,
10673 connector
->base
.name
,
10674 new_crtc
->base
.id
);
10677 /* Check for any encoders that needs to be disabled. */
10678 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10680 int num_connectors
= 0;
10681 list_for_each_entry(connector
,
10682 &dev
->mode_config
.connector_list
,
10684 if (connector
->new_encoder
== encoder
) {
10685 WARN_ON(!connector
->new_encoder
->new_crtc
);
10690 if (num_connectors
== 0)
10691 encoder
->new_crtc
= NULL
;
10692 else if (num_connectors
> 1)
10695 /* Only now check for crtc changes so we don't miss encoders
10696 * that will be disabled. */
10697 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
10698 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10699 config
->mode_changed
= true;
10702 /* Now we've also updated encoder->new_crtc for all encoders. */
10704 for_each_intel_crtc(dev
, crtc
) {
10705 crtc
->new_enabled
= false;
10707 list_for_each_entry(encoder
,
10708 &dev
->mode_config
.encoder_list
,
10710 if (encoder
->new_crtc
== crtc
) {
10711 crtc
->new_enabled
= true;
10716 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
10717 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10718 crtc
->new_enabled
? "en" : "dis");
10719 config
->mode_changed
= true;
10722 if (crtc
->new_enabled
)
10723 crtc
->new_config
= &crtc
->config
;
10725 crtc
->new_config
= NULL
;
10731 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
10733 struct drm_device
*dev
= crtc
->base
.dev
;
10734 struct intel_encoder
*encoder
;
10735 struct intel_connector
*connector
;
10737 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10738 pipe_name(crtc
->pipe
));
10740 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
10741 if (connector
->new_encoder
&&
10742 connector
->new_encoder
->new_crtc
== crtc
)
10743 connector
->new_encoder
= NULL
;
10746 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10747 if (encoder
->new_crtc
== crtc
)
10748 encoder
->new_crtc
= NULL
;
10751 crtc
->new_enabled
= false;
10752 crtc
->new_config
= NULL
;
10755 static int intel_crtc_set_config(struct drm_mode_set
*set
)
10757 struct drm_device
*dev
;
10758 struct drm_mode_set save_set
;
10759 struct intel_set_config
*config
;
10763 BUG_ON(!set
->crtc
);
10764 BUG_ON(!set
->crtc
->helper_private
);
10766 /* Enforce sane interface api - has been abused by the fb helper. */
10767 BUG_ON(!set
->mode
&& set
->fb
);
10768 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
10771 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10772 set
->crtc
->base
.id
, set
->fb
->base
.id
,
10773 (int)set
->num_connectors
, set
->x
, set
->y
);
10775 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
10778 dev
= set
->crtc
->dev
;
10781 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
10785 ret
= intel_set_config_save_state(dev
, config
);
10789 save_set
.crtc
= set
->crtc
;
10790 save_set
.mode
= &set
->crtc
->mode
;
10791 save_set
.x
= set
->crtc
->x
;
10792 save_set
.y
= set
->crtc
->y
;
10793 save_set
.fb
= set
->crtc
->primary
->fb
;
10795 /* Compute whether we need a full modeset, only an fb base update or no
10796 * change at all. In the future we might also check whether only the
10797 * mode changed, e.g. for LVDS where we only change the panel fitter in
10799 intel_set_config_compute_mode_changes(set
, config
);
10801 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
10805 if (config
->mode_changed
) {
10806 ret
= intel_set_mode(set
->crtc
, set
->mode
,
10807 set
->x
, set
->y
, set
->fb
);
10808 } else if (config
->fb_changed
) {
10809 intel_crtc_wait_for_pending_flips(set
->crtc
);
10811 ret
= intel_pipe_set_base(set
->crtc
,
10812 set
->x
, set
->y
, set
->fb
);
10814 * In the fastboot case this may be our only check of the
10815 * state after boot. It would be better to only do it on
10816 * the first update, but we don't have a nice way of doing that
10817 * (and really, set_config isn't used much for high freq page
10818 * flipping, so increasing its cost here shouldn't be a big
10821 if (i915
.fastboot
&& ret
== 0)
10822 intel_modeset_check_state(set
->crtc
->dev
);
10826 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10827 set
->crtc
->base
.id
, ret
);
10829 intel_set_config_restore_state(dev
, config
);
10832 * HACK: if the pipe was on, but we didn't have a framebuffer,
10833 * force the pipe off to avoid oopsing in the modeset code
10834 * due to fb==NULL. This should only happen during boot since
10835 * we don't yet reconstruct the FB from the hardware state.
10837 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
10838 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
10840 /* Try to restore the config */
10841 if (config
->mode_changed
&&
10842 intel_set_mode(save_set
.crtc
, save_set
.mode
,
10843 save_set
.x
, save_set
.y
, save_set
.fb
))
10844 DRM_ERROR("failed to restore config after modeset failure\n");
10848 intel_set_config_free(config
);
10852 static const struct drm_crtc_funcs intel_crtc_funcs
= {
10853 .cursor_set
= intel_crtc_cursor_set
,
10854 .cursor_move
= intel_crtc_cursor_move
,
10855 .gamma_set
= intel_crtc_gamma_set
,
10856 .set_config
= intel_crtc_set_config
,
10857 .destroy
= intel_crtc_destroy
,
10858 .page_flip
= intel_crtc_page_flip
,
10861 static void intel_cpu_pll_init(struct drm_device
*dev
)
10864 intel_ddi_pll_init(dev
);
10867 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
10868 struct intel_shared_dpll
*pll
,
10869 struct intel_dpll_hw_state
*hw_state
)
10873 val
= I915_READ(PCH_DPLL(pll
->id
));
10874 hw_state
->dpll
= val
;
10875 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
10876 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
10878 return val
& DPLL_VCO_ENABLE
;
10881 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
10882 struct intel_shared_dpll
*pll
)
10884 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
10885 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
10888 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
10889 struct intel_shared_dpll
*pll
)
10891 /* PCH refclock must be enabled first */
10892 ibx_assert_pch_refclk_enabled(dev_priv
);
10894 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10896 /* Wait for the clocks to stabilize. */
10897 POSTING_READ(PCH_DPLL(pll
->id
));
10900 /* The pixel multiplier can only be updated once the
10901 * DPLL is enabled and the clocks are stable.
10903 * So write it again.
10905 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10906 POSTING_READ(PCH_DPLL(pll
->id
));
10910 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
10911 struct intel_shared_dpll
*pll
)
10913 struct drm_device
*dev
= dev_priv
->dev
;
10914 struct intel_crtc
*crtc
;
10916 /* Make sure no transcoder isn't still depending on us. */
10917 for_each_intel_crtc(dev
, crtc
) {
10918 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
10919 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
10922 I915_WRITE(PCH_DPLL(pll
->id
), 0);
10923 POSTING_READ(PCH_DPLL(pll
->id
));
10927 static char *ibx_pch_dpll_names
[] = {
10932 static void ibx_pch_dpll_init(struct drm_device
*dev
)
10934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10937 dev_priv
->num_shared_dpll
= 2;
10939 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10940 dev_priv
->shared_dplls
[i
].id
= i
;
10941 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
10942 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
10943 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
10944 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
10945 dev_priv
->shared_dplls
[i
].get_hw_state
=
10946 ibx_pch_dpll_get_hw_state
;
10950 static void intel_shared_dpll_init(struct drm_device
*dev
)
10952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10954 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
10955 ibx_pch_dpll_init(dev
);
10957 dev_priv
->num_shared_dpll
= 0;
10959 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
10962 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
10964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10965 struct intel_crtc
*intel_crtc
;
10968 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
10969 if (intel_crtc
== NULL
)
10972 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
10974 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
10975 for (i
= 0; i
< 256; i
++) {
10976 intel_crtc
->lut_r
[i
] = i
;
10977 intel_crtc
->lut_g
[i
] = i
;
10978 intel_crtc
->lut_b
[i
] = i
;
10982 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10983 * is hooked to plane B. Hence we want plane A feeding pipe B.
10985 intel_crtc
->pipe
= pipe
;
10986 intel_crtc
->plane
= pipe
;
10987 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
10988 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10989 intel_crtc
->plane
= !pipe
;
10992 intel_crtc
->cursor_base
= ~0;
10993 intel_crtc
->cursor_cntl
= ~0;
10995 init_waitqueue_head(&intel_crtc
->vbl_wait
);
10997 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
10998 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
10999 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11000 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11002 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11004 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11007 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
11009 struct drm_encoder
*encoder
= connector
->base
.encoder
;
11010 struct drm_device
*dev
= connector
->base
.dev
;
11012 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
11015 return INVALID_PIPE
;
11017 return to_intel_crtc(encoder
->crtc
)->pipe
;
11020 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
11021 struct drm_file
*file
)
11023 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
11024 struct drm_mode_object
*drmmode_obj
;
11025 struct intel_crtc
*crtc
;
11027 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
11030 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
11031 DRM_MODE_OBJECT_CRTC
);
11033 if (!drmmode_obj
) {
11034 DRM_ERROR("no such CRTC id\n");
11038 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
11039 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
11044 static int intel_encoder_clones(struct intel_encoder
*encoder
)
11046 struct drm_device
*dev
= encoder
->base
.dev
;
11047 struct intel_encoder
*source_encoder
;
11048 int index_mask
= 0;
11051 list_for_each_entry(source_encoder
,
11052 &dev
->mode_config
.encoder_list
, base
.head
) {
11053 if (encoders_cloneable(encoder
, source_encoder
))
11054 index_mask
|= (1 << entry
);
11062 static bool has_edp_a(struct drm_device
*dev
)
11064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11066 if (!IS_MOBILE(dev
))
11069 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
11072 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
11078 const char *intel_output_name(int output
)
11080 static const char *names
[] = {
11081 [INTEL_OUTPUT_UNUSED
] = "Unused",
11082 [INTEL_OUTPUT_ANALOG
] = "Analog",
11083 [INTEL_OUTPUT_DVO
] = "DVO",
11084 [INTEL_OUTPUT_SDVO
] = "SDVO",
11085 [INTEL_OUTPUT_LVDS
] = "LVDS",
11086 [INTEL_OUTPUT_TVOUT
] = "TV",
11087 [INTEL_OUTPUT_HDMI
] = "HDMI",
11088 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
11089 [INTEL_OUTPUT_EDP
] = "eDP",
11090 [INTEL_OUTPUT_DSI
] = "DSI",
11091 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
11094 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
11097 return names
[output
];
11100 static bool intel_crt_present(struct drm_device
*dev
)
11102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11107 if (IS_CHERRYVIEW(dev
))
11110 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
11116 static void intel_setup_outputs(struct drm_device
*dev
)
11118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11119 struct intel_encoder
*encoder
;
11120 bool dpd_is_edp
= false;
11122 intel_lvds_init(dev
);
11124 if (intel_crt_present(dev
))
11125 intel_crt_init(dev
);
11127 if (HAS_DDI(dev
)) {
11130 /* Haswell uses DDI functions to detect digital outputs */
11131 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
11132 /* DDI A only supports eDP */
11134 intel_ddi_init(dev
, PORT_A
);
11136 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11138 found
= I915_READ(SFUSE_STRAP
);
11140 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
11141 intel_ddi_init(dev
, PORT_B
);
11142 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
11143 intel_ddi_init(dev
, PORT_C
);
11144 if (found
& SFUSE_STRAP_DDID_DETECTED
)
11145 intel_ddi_init(dev
, PORT_D
);
11146 } else if (HAS_PCH_SPLIT(dev
)) {
11148 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
11150 if (has_edp_a(dev
))
11151 intel_dp_init(dev
, DP_A
, PORT_A
);
11153 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
11154 /* PCH SDVOB multiplex with HDMIB */
11155 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
11157 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
11158 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
11159 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
11162 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
11163 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
11165 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
11166 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
11168 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
11169 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
11171 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
11172 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
11173 } else if (IS_VALLEYVIEW(dev
)) {
11174 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
11175 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
11177 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
11178 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
11181 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
11182 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
11184 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
11185 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
11188 if (IS_CHERRYVIEW(dev
)) {
11189 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
11190 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
11192 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
11193 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
11197 intel_dsi_init(dev
);
11198 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
11199 bool found
= false;
11201 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
11202 DRM_DEBUG_KMS("probing SDVOB\n");
11203 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
11204 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
11205 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11206 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
11209 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
11210 intel_dp_init(dev
, DP_B
, PORT_B
);
11213 /* Before G4X SDVOC doesn't have its own detect register */
11215 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
11216 DRM_DEBUG_KMS("probing SDVOC\n");
11217 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
11220 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
11222 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
11223 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11224 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
11226 if (SUPPORTS_INTEGRATED_DP(dev
))
11227 intel_dp_init(dev
, DP_C
, PORT_C
);
11230 if (SUPPORTS_INTEGRATED_DP(dev
) &&
11231 (I915_READ(DP_D
) & DP_DETECTED
))
11232 intel_dp_init(dev
, DP_D
, PORT_D
);
11233 } else if (IS_GEN2(dev
))
11234 intel_dvo_init(dev
);
11236 if (SUPPORTS_TV(dev
))
11237 intel_tv_init(dev
);
11239 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
11240 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
11241 encoder
->base
.possible_clones
=
11242 intel_encoder_clones(encoder
);
11245 intel_init_pch_refclk(dev
);
11247 drm_helper_move_panel_connectors_to_head(dev
);
11250 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
11252 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11254 drm_framebuffer_cleanup(fb
);
11255 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
11256 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
11260 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
11261 struct drm_file
*file
,
11262 unsigned int *handle
)
11264 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11265 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11267 return drm_gem_handle_create(file
, &obj
->base
, handle
);
11270 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
11271 .destroy
= intel_user_framebuffer_destroy
,
11272 .create_handle
= intel_user_framebuffer_create_handle
,
11275 static int intel_framebuffer_init(struct drm_device
*dev
,
11276 struct intel_framebuffer
*intel_fb
,
11277 struct drm_mode_fb_cmd2
*mode_cmd
,
11278 struct drm_i915_gem_object
*obj
)
11280 int aligned_height
;
11284 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
11286 if (obj
->tiling_mode
== I915_TILING_Y
) {
11287 DRM_DEBUG("hardware does not support tiling Y\n");
11291 if (mode_cmd
->pitches
[0] & 63) {
11292 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11293 mode_cmd
->pitches
[0]);
11297 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
11298 pitch_limit
= 32*1024;
11299 } else if (INTEL_INFO(dev
)->gen
>= 4) {
11300 if (obj
->tiling_mode
)
11301 pitch_limit
= 16*1024;
11303 pitch_limit
= 32*1024;
11304 } else if (INTEL_INFO(dev
)->gen
>= 3) {
11305 if (obj
->tiling_mode
)
11306 pitch_limit
= 8*1024;
11308 pitch_limit
= 16*1024;
11310 /* XXX DSPC is limited to 4k tiled */
11311 pitch_limit
= 8*1024;
11313 if (mode_cmd
->pitches
[0] > pitch_limit
) {
11314 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11315 obj
->tiling_mode
? "tiled" : "linear",
11316 mode_cmd
->pitches
[0], pitch_limit
);
11320 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
11321 mode_cmd
->pitches
[0] != obj
->stride
) {
11322 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11323 mode_cmd
->pitches
[0], obj
->stride
);
11327 /* Reject formats not supported by any plane early. */
11328 switch (mode_cmd
->pixel_format
) {
11329 case DRM_FORMAT_C8
:
11330 case DRM_FORMAT_RGB565
:
11331 case DRM_FORMAT_XRGB8888
:
11332 case DRM_FORMAT_ARGB8888
:
11334 case DRM_FORMAT_XRGB1555
:
11335 case DRM_FORMAT_ARGB1555
:
11336 if (INTEL_INFO(dev
)->gen
> 3) {
11337 DRM_DEBUG("unsupported pixel format: %s\n",
11338 drm_get_format_name(mode_cmd
->pixel_format
));
11342 case DRM_FORMAT_XBGR8888
:
11343 case DRM_FORMAT_ABGR8888
:
11344 case DRM_FORMAT_XRGB2101010
:
11345 case DRM_FORMAT_ARGB2101010
:
11346 case DRM_FORMAT_XBGR2101010
:
11347 case DRM_FORMAT_ABGR2101010
:
11348 if (INTEL_INFO(dev
)->gen
< 4) {
11349 DRM_DEBUG("unsupported pixel format: %s\n",
11350 drm_get_format_name(mode_cmd
->pixel_format
));
11354 case DRM_FORMAT_YUYV
:
11355 case DRM_FORMAT_UYVY
:
11356 case DRM_FORMAT_YVYU
:
11357 case DRM_FORMAT_VYUY
:
11358 if (INTEL_INFO(dev
)->gen
< 5) {
11359 DRM_DEBUG("unsupported pixel format: %s\n",
11360 drm_get_format_name(mode_cmd
->pixel_format
));
11365 DRM_DEBUG("unsupported pixel format: %s\n",
11366 drm_get_format_name(mode_cmd
->pixel_format
));
11370 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11371 if (mode_cmd
->offsets
[0] != 0)
11374 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
11376 /* FIXME drm helper for size checks (especially planar formats)? */
11377 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
11380 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
11381 intel_fb
->obj
= obj
;
11382 intel_fb
->obj
->framebuffer_references
++;
11384 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
11386 DRM_ERROR("framebuffer init failed %d\n", ret
);
11393 static struct drm_framebuffer
*
11394 intel_user_framebuffer_create(struct drm_device
*dev
,
11395 struct drm_file
*filp
,
11396 struct drm_mode_fb_cmd2
*mode_cmd
)
11398 struct drm_i915_gem_object
*obj
;
11400 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
11401 mode_cmd
->handles
[0]));
11402 if (&obj
->base
== NULL
)
11403 return ERR_PTR(-ENOENT
);
11405 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
11408 #ifndef CONFIG_DRM_I915_FBDEV
11409 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
11414 static const struct drm_mode_config_funcs intel_mode_funcs
= {
11415 .fb_create
= intel_user_framebuffer_create
,
11416 .output_poll_changed
= intel_fbdev_output_poll_changed
,
11419 /* Set up chip specific display functions */
11420 static void intel_init_display(struct drm_device
*dev
)
11422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11424 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
11425 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
11426 else if (IS_CHERRYVIEW(dev
))
11427 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
11428 else if (IS_VALLEYVIEW(dev
))
11429 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
11430 else if (IS_PINEVIEW(dev
))
11431 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
11433 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
11435 if (HAS_DDI(dev
)) {
11436 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
11437 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
11438 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
11439 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
11440 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
11441 dev_priv
->display
.off
= haswell_crtc_off
;
11442 dev_priv
->display
.update_primary_plane
=
11443 ironlake_update_primary_plane
;
11444 } else if (HAS_PCH_SPLIT(dev
)) {
11445 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
11446 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
11447 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
11448 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
11449 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
11450 dev_priv
->display
.off
= ironlake_crtc_off
;
11451 dev_priv
->display
.update_primary_plane
=
11452 ironlake_update_primary_plane
;
11453 } else if (IS_VALLEYVIEW(dev
)) {
11454 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
11455 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
11456 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
11457 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
11458 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
11459 dev_priv
->display
.off
= i9xx_crtc_off
;
11460 dev_priv
->display
.update_primary_plane
=
11461 i9xx_update_primary_plane
;
11463 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
11464 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
11465 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
11466 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
11467 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
11468 dev_priv
->display
.off
= i9xx_crtc_off
;
11469 dev_priv
->display
.update_primary_plane
=
11470 i9xx_update_primary_plane
;
11473 /* Returns the core display clock speed */
11474 if (IS_VALLEYVIEW(dev
))
11475 dev_priv
->display
.get_display_clock_speed
=
11476 valleyview_get_display_clock_speed
;
11477 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
11478 dev_priv
->display
.get_display_clock_speed
=
11479 i945_get_display_clock_speed
;
11480 else if (IS_I915G(dev
))
11481 dev_priv
->display
.get_display_clock_speed
=
11482 i915_get_display_clock_speed
;
11483 else if (IS_I945GM(dev
) || IS_845G(dev
))
11484 dev_priv
->display
.get_display_clock_speed
=
11485 i9xx_misc_get_display_clock_speed
;
11486 else if (IS_PINEVIEW(dev
))
11487 dev_priv
->display
.get_display_clock_speed
=
11488 pnv_get_display_clock_speed
;
11489 else if (IS_I915GM(dev
))
11490 dev_priv
->display
.get_display_clock_speed
=
11491 i915gm_get_display_clock_speed
;
11492 else if (IS_I865G(dev
))
11493 dev_priv
->display
.get_display_clock_speed
=
11494 i865_get_display_clock_speed
;
11495 else if (IS_I85X(dev
))
11496 dev_priv
->display
.get_display_clock_speed
=
11497 i855_get_display_clock_speed
;
11498 else /* 852, 830 */
11499 dev_priv
->display
.get_display_clock_speed
=
11500 i830_get_display_clock_speed
;
11502 if (HAS_PCH_SPLIT(dev
)) {
11503 if (IS_GEN5(dev
)) {
11504 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
11505 dev_priv
->display
.write_eld
= ironlake_write_eld
;
11506 } else if (IS_GEN6(dev
)) {
11507 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
11508 dev_priv
->display
.write_eld
= ironlake_write_eld
;
11509 dev_priv
->display
.modeset_global_resources
=
11510 snb_modeset_global_resources
;
11511 } else if (IS_IVYBRIDGE(dev
)) {
11512 /* FIXME: detect B0+ stepping and use auto training */
11513 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
11514 dev_priv
->display
.write_eld
= ironlake_write_eld
;
11515 dev_priv
->display
.modeset_global_resources
=
11516 ivb_modeset_global_resources
;
11517 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
11518 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
11519 dev_priv
->display
.write_eld
= haswell_write_eld
;
11520 dev_priv
->display
.modeset_global_resources
=
11521 haswell_modeset_global_resources
;
11523 } else if (IS_G4X(dev
)) {
11524 dev_priv
->display
.write_eld
= g4x_write_eld
;
11525 } else if (IS_VALLEYVIEW(dev
)) {
11526 dev_priv
->display
.modeset_global_resources
=
11527 valleyview_modeset_global_resources
;
11528 dev_priv
->display
.write_eld
= ironlake_write_eld
;
11531 /* Default just returns -ENODEV to indicate unsupported */
11532 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
11534 switch (INTEL_INFO(dev
)->gen
) {
11536 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
11540 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
11545 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
11549 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
11552 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11553 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
11557 intel_panel_init_backlight_funcs(dev
);
11561 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11562 * resume, or other times. This quirk makes sure that's the case for
11563 * affected systems.
11565 static void quirk_pipea_force(struct drm_device
*dev
)
11567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11569 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
11570 DRM_INFO("applying pipe a force quirk\n");
11574 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11576 static void quirk_ssc_force_disable(struct drm_device
*dev
)
11578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11579 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
11580 DRM_INFO("applying lvds SSC disable quirk\n");
11584 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11587 static void quirk_invert_brightness(struct drm_device
*dev
)
11589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11590 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
11591 DRM_INFO("applying inverted panel brightness quirk\n");
11594 struct intel_quirk
{
11596 int subsystem_vendor
;
11597 int subsystem_device
;
11598 void (*hook
)(struct drm_device
*dev
);
11601 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11602 struct intel_dmi_quirk
{
11603 void (*hook
)(struct drm_device
*dev
);
11604 const struct dmi_system_id (*dmi_id_list
)[];
11607 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
11609 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
11613 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
11615 .dmi_id_list
= &(const struct dmi_system_id
[]) {
11617 .callback
= intel_dmi_reverse_brightness
,
11618 .ident
= "NCR Corporation",
11619 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
11620 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
11623 { } /* terminating entry */
11625 .hook
= quirk_invert_brightness
,
11629 static struct intel_quirk intel_quirks
[] = {
11630 /* HP Mini needs pipe A force quirk (LP: #322104) */
11631 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
11633 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11634 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
11636 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11637 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
11639 /* Lenovo U160 cannot use SSC on LVDS */
11640 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
11642 /* Sony Vaio Y cannot use SSC on LVDS */
11643 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
11645 /* Acer Aspire 5734Z must invert backlight brightness */
11646 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
11648 /* Acer/eMachines G725 */
11649 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
11651 /* Acer/eMachines e725 */
11652 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
11654 /* Acer/Packard Bell NCL20 */
11655 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
11657 /* Acer Aspire 4736Z */
11658 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
11660 /* Acer Aspire 5336 */
11661 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
11664 static void intel_init_quirks(struct drm_device
*dev
)
11666 struct pci_dev
*d
= dev
->pdev
;
11669 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
11670 struct intel_quirk
*q
= &intel_quirks
[i
];
11672 if (d
->device
== q
->device
&&
11673 (d
->subsystem_vendor
== q
->subsystem_vendor
||
11674 q
->subsystem_vendor
== PCI_ANY_ID
) &&
11675 (d
->subsystem_device
== q
->subsystem_device
||
11676 q
->subsystem_device
== PCI_ANY_ID
))
11679 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
11680 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
11681 intel_dmi_quirks
[i
].hook(dev
);
11685 /* Disable the VGA plane that we never use */
11686 static void i915_disable_vga(struct drm_device
*dev
)
11688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11690 u32 vga_reg
= i915_vgacntrl_reg(dev
);
11692 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11693 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
11694 outb(SR01
, VGA_SR_INDEX
);
11695 sr1
= inb(VGA_SR_DATA
);
11696 outb(sr1
| 1<<5, VGA_SR_DATA
);
11697 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
11700 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
11701 POSTING_READ(vga_reg
);
11704 void intel_modeset_init_hw(struct drm_device
*dev
)
11706 intel_prepare_ddi(dev
);
11708 intel_init_clock_gating(dev
);
11710 intel_reset_dpio(dev
);
11712 intel_enable_gt_powersave(dev
);
11715 void intel_modeset_suspend_hw(struct drm_device
*dev
)
11717 intel_suspend_hw(dev
);
11720 void intel_modeset_init(struct drm_device
*dev
)
11722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11725 struct intel_crtc
*crtc
;
11727 drm_mode_config_init(dev
);
11729 dev
->mode_config
.min_width
= 0;
11730 dev
->mode_config
.min_height
= 0;
11732 dev
->mode_config
.preferred_depth
= 24;
11733 dev
->mode_config
.prefer_shadow
= 1;
11735 dev
->mode_config
.funcs
= &intel_mode_funcs
;
11737 intel_init_quirks(dev
);
11739 intel_init_pm(dev
);
11741 if (INTEL_INFO(dev
)->num_pipes
== 0)
11744 intel_init_display(dev
);
11746 if (IS_GEN2(dev
)) {
11747 dev
->mode_config
.max_width
= 2048;
11748 dev
->mode_config
.max_height
= 2048;
11749 } else if (IS_GEN3(dev
)) {
11750 dev
->mode_config
.max_width
= 4096;
11751 dev
->mode_config
.max_height
= 4096;
11753 dev
->mode_config
.max_width
= 8192;
11754 dev
->mode_config
.max_height
= 8192;
11757 if (IS_GEN2(dev
)) {
11758 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
11759 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
11761 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
11762 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
11765 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
11767 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11768 INTEL_INFO(dev
)->num_pipes
,
11769 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
11771 for_each_pipe(pipe
) {
11772 intel_crtc_init(dev
, pipe
);
11773 for_each_sprite(pipe
, sprite
) {
11774 ret
= intel_plane_init(dev
, pipe
, sprite
);
11776 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11777 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
11781 intel_init_dpio(dev
);
11782 intel_reset_dpio(dev
);
11784 intel_cpu_pll_init(dev
);
11785 intel_shared_dpll_init(dev
);
11787 /* Just disable it once at startup */
11788 i915_disable_vga(dev
);
11789 intel_setup_outputs(dev
);
11791 /* Just in case the BIOS is doing something questionable. */
11792 intel_disable_fbc(dev
);
11794 drm_modeset_lock_all(dev
);
11795 intel_modeset_setup_hw_state(dev
, false);
11796 drm_modeset_unlock_all(dev
);
11798 for_each_intel_crtc(dev
, crtc
) {
11803 * Note that reserving the BIOS fb up front prevents us
11804 * from stuffing other stolen allocations like the ring
11805 * on top. This prevents some ugliness at boot time, and
11806 * can even allow for smooth boot transitions if the BIOS
11807 * fb is large enough for the active pipe configuration.
11809 if (dev_priv
->display
.get_plane_config
) {
11810 dev_priv
->display
.get_plane_config(crtc
,
11811 &crtc
->plane_config
);
11813 * If the fb is shared between multiple heads, we'll
11814 * just get the first one.
11816 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
11821 static void intel_enable_pipe_a(struct drm_device
*dev
)
11823 struct intel_connector
*connector
;
11824 struct drm_connector
*crt
= NULL
;
11825 struct intel_load_detect_pipe load_detect_temp
;
11826 struct drm_modeset_acquire_ctx ctx
;
11828 /* We can't just switch on the pipe A, we need to set things up with a
11829 * proper mode and output configuration. As a gross hack, enable pipe A
11830 * by enabling the load detect pipe once. */
11831 list_for_each_entry(connector
,
11832 &dev
->mode_config
.connector_list
,
11834 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
11835 crt
= &connector
->base
;
11843 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, &ctx
))
11844 intel_release_load_detect_pipe(crt
, &load_detect_temp
, &ctx
);
11850 intel_check_plane_mapping(struct intel_crtc
*crtc
)
11852 struct drm_device
*dev
= crtc
->base
.dev
;
11853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11856 if (INTEL_INFO(dev
)->num_pipes
== 1)
11859 reg
= DSPCNTR(!crtc
->plane
);
11860 val
= I915_READ(reg
);
11862 if ((val
& DISPLAY_PLANE_ENABLE
) &&
11863 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
11869 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
11871 struct drm_device
*dev
= crtc
->base
.dev
;
11872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11875 /* Clear any frame start delays used for debugging left by the BIOS */
11876 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
11877 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
11879 /* restore vblank interrupts to correct state */
11881 drm_vblank_on(dev
, crtc
->pipe
);
11883 drm_vblank_off(dev
, crtc
->pipe
);
11885 /* We need to sanitize the plane -> pipe mapping first because this will
11886 * disable the crtc (and hence change the state) if it is wrong. Note
11887 * that gen4+ has a fixed plane -> pipe mapping. */
11888 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
11889 struct intel_connector
*connector
;
11892 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11893 crtc
->base
.base
.id
);
11895 /* Pipe has the wrong plane attached and the plane is active.
11896 * Temporarily change the plane mapping and disable everything
11898 plane
= crtc
->plane
;
11899 crtc
->plane
= !plane
;
11900 dev_priv
->display
.crtc_disable(&crtc
->base
);
11901 crtc
->plane
= plane
;
11903 /* ... and break all links. */
11904 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11906 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
11909 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
11910 connector
->base
.encoder
= NULL
;
11912 /* multiple connectors may have the same encoder:
11913 * handle them and break crtc link separately */
11914 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11916 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
11917 connector
->encoder
->base
.crtc
= NULL
;
11918 connector
->encoder
->connectors_active
= false;
11921 WARN_ON(crtc
->active
);
11922 crtc
->base
.enabled
= false;
11925 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
11926 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
11927 /* BIOS forgot to enable pipe A, this mostly happens after
11928 * resume. Force-enable the pipe to fix this, the update_dpms
11929 * call below we restore the pipe to the right state, but leave
11930 * the required bits on. */
11931 intel_enable_pipe_a(dev
);
11934 /* Adjust the state of the output pipe according to whether we
11935 * have active connectors/encoders. */
11936 intel_crtc_update_dpms(&crtc
->base
);
11938 if (crtc
->active
!= crtc
->base
.enabled
) {
11939 struct intel_encoder
*encoder
;
11941 /* This can happen either due to bugs in the get_hw_state
11942 * functions or because the pipe is force-enabled due to the
11944 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11945 crtc
->base
.base
.id
,
11946 crtc
->base
.enabled
? "enabled" : "disabled",
11947 crtc
->active
? "enabled" : "disabled");
11949 crtc
->base
.enabled
= crtc
->active
;
11951 /* Because we only establish the connector -> encoder ->
11952 * crtc links if something is active, this means the
11953 * crtc is now deactivated. Break the links. connector
11954 * -> encoder links are only establish when things are
11955 * actually up, hence no need to break them. */
11956 WARN_ON(crtc
->active
);
11958 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
11959 WARN_ON(encoder
->connectors_active
);
11960 encoder
->base
.crtc
= NULL
;
11964 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
11966 * We start out with underrun reporting disabled to avoid races.
11967 * For correct bookkeeping mark this on active crtcs.
11969 * Also on gmch platforms we dont have any hardware bits to
11970 * disable the underrun reporting. Which means we need to start
11971 * out with underrun reporting disabled also on inactive pipes,
11972 * since otherwise we'll complain about the garbage we read when
11973 * e.g. coming up after runtime pm.
11975 * No protection against concurrent access is required - at
11976 * worst a fifo underrun happens which also sets this to false.
11978 crtc
->cpu_fifo_underrun_disabled
= true;
11979 crtc
->pch_fifo_underrun_disabled
= true;
11981 update_scanline_offset(crtc
);
11985 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
11987 struct intel_connector
*connector
;
11988 struct drm_device
*dev
= encoder
->base
.dev
;
11990 /* We need to check both for a crtc link (meaning that the
11991 * encoder is active and trying to read from a pipe) and the
11992 * pipe itself being active. */
11993 bool has_active_crtc
= encoder
->base
.crtc
&&
11994 to_intel_crtc(encoder
->base
.crtc
)->active
;
11996 if (encoder
->connectors_active
&& !has_active_crtc
) {
11997 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11998 encoder
->base
.base
.id
,
11999 encoder
->base
.name
);
12001 /* Connector is active, but has no active pipe. This is
12002 * fallout from our resume register restoring. Disable
12003 * the encoder manually again. */
12004 if (encoder
->base
.crtc
) {
12005 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12006 encoder
->base
.base
.id
,
12007 encoder
->base
.name
);
12008 encoder
->disable(encoder
);
12010 encoder
->base
.crtc
= NULL
;
12011 encoder
->connectors_active
= false;
12013 /* Inconsistent output/port/pipe state happens presumably due to
12014 * a bug in one of the get_hw_state functions. Or someplace else
12015 * in our code, like the register restore mess on resume. Clamp
12016 * things to off as a safer default. */
12017 list_for_each_entry(connector
,
12018 &dev
->mode_config
.connector_list
,
12020 if (connector
->encoder
!= encoder
)
12022 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12023 connector
->base
.encoder
= NULL
;
12026 /* Enabled encoders without active connectors will be fixed in
12027 * the crtc fixup. */
12030 void i915_redisable_vga_power_on(struct drm_device
*dev
)
12032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12033 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12035 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
12036 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12037 i915_disable_vga(dev
);
12041 void i915_redisable_vga(struct drm_device
*dev
)
12043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12045 /* This function can be called both from intel_modeset_setup_hw_state or
12046 * at a very early point in our resume sequence, where the power well
12047 * structures are not yet restored. Since this function is at a very
12048 * paranoid "someone might have enabled VGA while we were not looking"
12049 * level, just check if the power well is enabled instead of trying to
12050 * follow the "don't touch the power well if we don't need it" policy
12051 * the rest of the driver uses. */
12052 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
12055 i915_redisable_vga_power_on(dev
);
12058 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
12060 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
12065 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
12068 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
12070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12072 struct intel_crtc
*crtc
;
12073 struct intel_encoder
*encoder
;
12074 struct intel_connector
*connector
;
12077 for_each_intel_crtc(dev
, crtc
) {
12078 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
12080 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
12082 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
12085 crtc
->base
.enabled
= crtc
->active
;
12086 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
12088 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12089 crtc
->base
.base
.id
,
12090 crtc
->active
? "enabled" : "disabled");
12093 /* FIXME: Smash this into the new shared dpll infrastructure. */
12095 intel_ddi_setup_hw_pll_state(dev
);
12097 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12098 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12100 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
12102 for_each_intel_crtc(dev
, crtc
) {
12103 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12106 pll
->refcount
= pll
->active
;
12108 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12109 pll
->name
, pll
->refcount
, pll
->on
);
12112 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
12116 if (encoder
->get_hw_state(encoder
, &pipe
)) {
12117 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
12118 encoder
->base
.crtc
= &crtc
->base
;
12119 encoder
->get_config(encoder
, &crtc
->config
);
12121 encoder
->base
.crtc
= NULL
;
12124 encoder
->connectors_active
= false;
12125 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12126 encoder
->base
.base
.id
,
12127 encoder
->base
.name
,
12128 encoder
->base
.crtc
? "enabled" : "disabled",
12132 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12134 if (connector
->get_hw_state(connector
)) {
12135 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
12136 connector
->encoder
->connectors_active
= true;
12137 connector
->base
.encoder
= &connector
->encoder
->base
;
12139 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12140 connector
->base
.encoder
= NULL
;
12142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12143 connector
->base
.base
.id
,
12144 connector
->base
.name
,
12145 connector
->base
.encoder
? "enabled" : "disabled");
12149 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12150 * and i915 state tracking structures. */
12151 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
12152 bool force_restore
)
12154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12156 struct intel_crtc
*crtc
;
12157 struct intel_encoder
*encoder
;
12160 intel_modeset_readout_hw_state(dev
);
12163 * Now that we have the config, copy it to each CRTC struct
12164 * Note that this could go away if we move to using crtc_config
12165 * checking everywhere.
12167 for_each_intel_crtc(dev
, crtc
) {
12168 if (crtc
->active
&& i915
.fastboot
) {
12169 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
12170 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12171 crtc
->base
.base
.id
);
12172 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
12176 /* HW state is read out, now we need to sanitize this mess. */
12177 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
12179 intel_sanitize_encoder(encoder
);
12182 for_each_pipe(pipe
) {
12183 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
12184 intel_sanitize_crtc(crtc
);
12185 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
12188 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12189 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12191 if (!pll
->on
|| pll
->active
)
12194 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
12196 pll
->disable(dev_priv
, pll
);
12200 if (HAS_PCH_SPLIT(dev
))
12201 ilk_wm_get_hw_state(dev
);
12203 if (force_restore
) {
12204 i915_redisable_vga(dev
);
12207 * We need to use raw interfaces for restoring state to avoid
12208 * checking (bogus) intermediate states.
12210 for_each_pipe(pipe
) {
12211 struct drm_crtc
*crtc
=
12212 dev_priv
->pipe_to_crtc_mapping
[pipe
];
12214 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
12215 crtc
->primary
->fb
);
12218 intel_modeset_update_staged_output_state(dev
);
12221 intel_modeset_check_state(dev
);
12224 void intel_modeset_gem_init(struct drm_device
*dev
)
12226 struct drm_crtc
*c
;
12227 struct intel_framebuffer
*fb
;
12229 mutex_lock(&dev
->struct_mutex
);
12230 intel_init_gt_powersave(dev
);
12231 mutex_unlock(&dev
->struct_mutex
);
12233 intel_modeset_init_hw(dev
);
12235 intel_setup_overlay(dev
);
12238 * Make sure any fbs we allocated at startup are properly
12239 * pinned & fenced. When we do the allocation it's too early
12242 mutex_lock(&dev
->struct_mutex
);
12243 for_each_crtc(dev
, c
) {
12244 if (!c
->primary
->fb
)
12247 fb
= to_intel_framebuffer(c
->primary
->fb
);
12248 if (intel_pin_and_fence_fb_obj(dev
, fb
->obj
, NULL
)) {
12249 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12250 to_intel_crtc(c
)->pipe
);
12251 drm_framebuffer_unreference(c
->primary
->fb
);
12252 c
->primary
->fb
= NULL
;
12255 mutex_unlock(&dev
->struct_mutex
);
12258 void intel_connector_unregister(struct intel_connector
*intel_connector
)
12260 struct drm_connector
*connector
= &intel_connector
->base
;
12262 intel_panel_destroy_backlight(connector
);
12263 drm_sysfs_connector_remove(connector
);
12266 void intel_modeset_cleanup(struct drm_device
*dev
)
12268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12269 struct drm_crtc
*crtc
;
12270 struct drm_connector
*connector
;
12273 * Interrupts and polling as the first thing to avoid creating havoc.
12274 * Too much stuff here (turning of rps, connectors, ...) would
12275 * experience fancy races otherwise.
12277 drm_irq_uninstall(dev
);
12278 cancel_work_sync(&dev_priv
->hotplug_work
);
12280 * Due to the hpd irq storm handling the hotplug work can re-arm the
12281 * poll handlers. Hence disable polling after hpd handling is shut down.
12283 drm_kms_helper_poll_fini(dev
);
12285 mutex_lock(&dev
->struct_mutex
);
12287 intel_unregister_dsm_handler();
12289 for_each_crtc(dev
, crtc
) {
12290 /* Skip inactive CRTCs */
12291 if (!crtc
->primary
->fb
)
12294 intel_increase_pllclock(crtc
);
12297 intel_disable_fbc(dev
);
12299 intel_disable_gt_powersave(dev
);
12301 ironlake_teardown_rc6(dev
);
12303 mutex_unlock(&dev
->struct_mutex
);
12305 /* flush any delayed tasks or pending work */
12306 flush_scheduled_work();
12308 /* destroy the backlight and sysfs files before encoders/connectors */
12309 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
12310 struct intel_connector
*intel_connector
;
12312 intel_connector
= to_intel_connector(connector
);
12313 intel_connector
->unregister(intel_connector
);
12316 drm_mode_config_cleanup(dev
);
12318 intel_cleanup_overlay(dev
);
12320 mutex_lock(&dev
->struct_mutex
);
12321 intel_cleanup_gt_powersave(dev
);
12322 mutex_unlock(&dev
->struct_mutex
);
12326 * Return which encoder is currently attached for connector.
12328 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
12330 return &intel_attached_encoder(connector
)->base
;
12333 void intel_connector_attach_encoder(struct intel_connector
*connector
,
12334 struct intel_encoder
*encoder
)
12336 connector
->encoder
= encoder
;
12337 drm_mode_connector_attach_encoder(&connector
->base
,
12342 * set vga decode state - true == enable VGA decode
12344 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
12346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12347 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
12350 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
12351 DRM_ERROR("failed to read control word\n");
12355 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
12359 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
12361 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
12363 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
12364 DRM_ERROR("failed to write control word\n");
12371 struct intel_display_error_state
{
12373 u32 power_well_driver
;
12375 int num_transcoders
;
12377 struct intel_cursor_error_state
{
12382 } cursor
[I915_MAX_PIPES
];
12384 struct intel_pipe_error_state
{
12385 bool power_domain_on
;
12388 } pipe
[I915_MAX_PIPES
];
12390 struct intel_plane_error_state
{
12398 } plane
[I915_MAX_PIPES
];
12400 struct intel_transcoder_error_state
{
12401 bool power_domain_on
;
12402 enum transcoder cpu_transcoder
;
12415 struct intel_display_error_state
*
12416 intel_display_capture_error_state(struct drm_device
*dev
)
12418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12419 struct intel_display_error_state
*error
;
12420 int transcoders
[] = {
12428 if (INTEL_INFO(dev
)->num_pipes
== 0)
12431 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
12435 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
12436 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
12439 error
->pipe
[i
].power_domain_on
=
12440 intel_display_power_enabled_unlocked(dev_priv
,
12441 POWER_DOMAIN_PIPE(i
));
12442 if (!error
->pipe
[i
].power_domain_on
)
12445 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
12446 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
12447 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
12449 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
12450 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
12451 if (INTEL_INFO(dev
)->gen
<= 3) {
12452 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
12453 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
12455 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
12456 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
12457 if (INTEL_INFO(dev
)->gen
>= 4) {
12458 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
12459 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
12462 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
12464 if (!HAS_PCH_SPLIT(dev
))
12465 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
12468 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
12469 if (HAS_DDI(dev_priv
->dev
))
12470 error
->num_transcoders
++; /* Account for eDP. */
12472 for (i
= 0; i
< error
->num_transcoders
; i
++) {
12473 enum transcoder cpu_transcoder
= transcoders
[i
];
12475 error
->transcoder
[i
].power_domain_on
=
12476 intel_display_power_enabled_unlocked(dev_priv
,
12477 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
12478 if (!error
->transcoder
[i
].power_domain_on
)
12481 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
12483 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
12484 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
12485 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
12486 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
12487 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
12488 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
12489 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
12495 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12498 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
12499 struct drm_device
*dev
,
12500 struct intel_display_error_state
*error
)
12507 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
12508 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
12509 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
12510 error
->power_well_driver
);
12512 err_printf(m
, "Pipe [%d]:\n", i
);
12513 err_printf(m
, " Power: %s\n",
12514 error
->pipe
[i
].power_domain_on
? "on" : "off");
12515 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
12516 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
12518 err_printf(m
, "Plane [%d]:\n", i
);
12519 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
12520 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
12521 if (INTEL_INFO(dev
)->gen
<= 3) {
12522 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
12523 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
12525 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
12526 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
12527 if (INTEL_INFO(dev
)->gen
>= 4) {
12528 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
12529 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
12532 err_printf(m
, "Cursor [%d]:\n", i
);
12533 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
12534 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
12535 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
12538 for (i
= 0; i
< error
->num_transcoders
; i
++) {
12539 err_printf(m
, "CPU transcoder: %c\n",
12540 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
12541 err_printf(m
, " Power: %s\n",
12542 error
->transcoder
[i
].power_domain_on
? "on" : "off");
12543 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
12544 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
12545 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
12546 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
12547 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
12548 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
12549 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);