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drm/i915: Limit mmio flip RPS boosts
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 };
76
77 /* Cursor formats */
78 static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80 };
81
82 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
83
84 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_state *pipe_config);
86 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
87 struct intel_crtc_state *pipe_config);
88
89 static int intel_set_mode(struct drm_crtc *crtc,
90 struct drm_atomic_state *state);
91 static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
100 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
101 static void haswell_set_pipeconf(struct drm_crtc *crtc);
102 static void intel_set_pipe_csc(struct drm_crtc *crtc);
103 static void vlv_prepare_pll(struct intel_crtc *crtc,
104 const struct intel_crtc_state *pipe_config);
105 static void chv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
109 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
111 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
113 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
115
116 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117 {
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122 }
123
124 typedef struct {
125 int min, max;
126 } intel_range_t;
127
128 typedef struct {
129 int dot_limit;
130 int p2_slow, p2_fast;
131 } intel_p2_t;
132
133 typedef struct intel_limit intel_limit_t;
134 struct intel_limit {
135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
137 };
138
139 int
140 intel_pch_rawclk(struct drm_device *dev)
141 {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147 }
148
149 static inline u32 /* units of 100MHz */
150 intel_fdi_link_freq(struct drm_device *dev)
151 {
152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
157 }
158
159 static const intel_limit_t intel_limits_i8xx_dac = {
160 .dot = { .min = 25000, .max = 350000 },
161 .vco = { .min = 908000, .max = 1512000 },
162 .n = { .min = 2, .max = 16 },
163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
170 };
171
172 static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
174 .vco = { .min = 908000, .max = 1512000 },
175 .n = { .min = 2, .max = 16 },
176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183 };
184
185 static const intel_limit_t intel_limits_i8xx_lvds = {
186 .dot = { .min = 25000, .max = 350000 },
187 .vco = { .min = 908000, .max = 1512000 },
188 .n = { .min = 2, .max = 16 },
189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
196 };
197
198 static const intel_limit_t intel_limits_i9xx_sdvo = {
199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
209 };
210
211 static const intel_limit_t intel_limits_i9xx_lvds = {
212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
222 };
223
224
225 static const intel_limit_t intel_limits_g4x_sdvo = {
226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
237 },
238 };
239
240 static const intel_limit_t intel_limits_g4x_hdmi = {
241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
264 },
265 };
266
267 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
278 },
279 };
280
281 static const intel_limit_t intel_limits_pineview_sdvo = {
282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
284 /* Pineview's Ncounter is a ring counter */
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 /* Pineview only has one combined m divider, which we treat as m2. */
288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
294 };
295
296 static const intel_limit_t intel_limits_pineview_lvds = {
297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
307 };
308
309 /* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
314 static const intel_limit_t intel_limits_ironlake_dac = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
325 };
326
327 static const intel_limit_t intel_limits_ironlake_single_lvds = {
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
338 };
339
340 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
351 };
352
353 /* LVDS 100mhz refclk limits. */
354 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
362 .p1 = { .min = 2, .max = 8 },
363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
365 };
366
367 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
375 .p1 = { .min = 2, .max = 6 },
376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
378 };
379
380 static const intel_limit_t intel_limits_vlv = {
381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
388 .vco = { .min = 4000000, .max = 6000000 },
389 .n = { .min = 1, .max = 7 },
390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
392 .p1 = { .min = 2, .max = 3 },
393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
394 };
395
396 static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
404 .vco = { .min = 4800000, .max = 6480000 },
405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410 };
411
412 static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422 };
423
424 static void vlv_clock(int refclk, intel_clock_t *clock)
425 {
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
432 }
433
434 /**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
437 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
438 {
439 struct drm_device *dev = crtc->base.dev;
440 struct intel_encoder *encoder;
441
442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
443 if (encoder->type == type)
444 return true;
445
446 return false;
447 }
448
449 /**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
455 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
457 {
458 struct drm_atomic_state *state = crtc_state->base.state;
459 struct drm_connector *connector;
460 struct drm_connector_state *connector_state;
461 struct intel_encoder *encoder;
462 int i, num_connectors = 0;
463
464 for_each_connector_in_state(state, connector, connector_state, i) {
465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
469
470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
472 return true;
473 }
474
475 WARN_ON(num_connectors == 0);
476
477 return false;
478 }
479
480 static const intel_limit_t *
481 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
482 {
483 struct drm_device *dev = crtc_state->base.crtc->dev;
484 const intel_limit_t *limit;
485
486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
487 if (intel_is_dual_link_lvds(dev)) {
488 if (refclk == 100000)
489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
493 if (refclk == 100000)
494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
498 } else
499 limit = &intel_limits_ironlake_dac;
500
501 return limit;
502 }
503
504 static const intel_limit_t *
505 intel_g4x_limit(struct intel_crtc_state *crtc_state)
506 {
507 struct drm_device *dev = crtc_state->base.crtc->dev;
508 const intel_limit_t *limit;
509
510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
511 if (intel_is_dual_link_lvds(dev))
512 limit = &intel_limits_g4x_dual_channel_lvds;
513 else
514 limit = &intel_limits_g4x_single_channel_lvds;
515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
517 limit = &intel_limits_g4x_hdmi;
518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
519 limit = &intel_limits_g4x_sdvo;
520 } else /* The option is for other outputs */
521 limit = &intel_limits_i9xx_sdvo;
522
523 return limit;
524 }
525
526 static const intel_limit_t *
527 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
528 {
529 struct drm_device *dev = crtc_state->base.crtc->dev;
530 const intel_limit_t *limit;
531
532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
535 limit = intel_ironlake_limit(crtc_state, refclk);
536 else if (IS_G4X(dev)) {
537 limit = intel_g4x_limit(crtc_state);
538 } else if (IS_PINEVIEW(dev)) {
539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
540 limit = &intel_limits_pineview_lvds;
541 else
542 limit = &intel_limits_pineview_sdvo;
543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
545 } else if (IS_VALLEYVIEW(dev)) {
546 limit = &intel_limits_vlv;
547 } else if (!IS_GEN2(dev)) {
548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
552 } else {
553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
554 limit = &intel_limits_i8xx_lvds;
555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
556 limit = &intel_limits_i8xx_dvo;
557 else
558 limit = &intel_limits_i8xx_dac;
559 }
560 return limit;
561 }
562
563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
564 static void pineview_clock(int refclk, intel_clock_t *clock)
565 {
566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 }
573
574 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575 {
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577 }
578
579 static void i9xx_clock(int refclk, intel_clock_t *clock)
580 {
581 clock->m = i9xx_dpll_compute_m(clock);
582 clock->p = clock->p1 * clock->p2;
583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
587 }
588
589 static void chv_clock(int refclk, intel_clock_t *clock)
590 {
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598 }
599
600 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
601 /**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
606 static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
609 {
610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
613 INTELPllInvalid("p1 out of range\n");
614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
615 INTELPllInvalid("m2 out of range\n");
616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
617 INTELPllInvalid("m1 out of range\n");
618
619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
631 INTELPllInvalid("vco out of range\n");
632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
636 INTELPllInvalid("dot out of range\n");
637
638 return true;
639 }
640
641 static bool
642 i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
646 {
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
648 struct drm_device *dev = crtc->base.dev;
649 intel_clock_t clock;
650 int err = target;
651
652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
653 /*
654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
657 */
658 if (intel_is_dual_link_lvds(dev))
659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
669 memset(best_clock, 0, sizeof(*best_clock));
670
671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
675 if (clock.m2 >= clock.m1)
676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
681 int this_err;
682
683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702 }
703
704 static bool
705 pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
709 {
710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
711 struct drm_device *dev = crtc->base.dev;
712 intel_clock_t clock;
713 int err = target;
714
715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
716 /*
717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
720 */
721 if (intel_is_dual_link_lvds(dev))
722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
742 int this_err;
743
744 pineview_clock(refclk, &clock);
745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
747 continue;
748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763 }
764
765 static bool
766 g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
770 {
771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
772 struct drm_device *dev = crtc->base.dev;
773 intel_clock_t clock;
774 int max_n;
775 bool found;
776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
778 found = false;
779
780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
781 if (intel_is_dual_link_lvds(dev))
782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 /* based on hardware requirement, prefere larger m1,m2 */
797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
805 i9xx_clock(refclk, &clock);
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 this_err = abs(clock.dot - target);
811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
821 return found;
822 }
823
824 /*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833 {
834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862 }
863
864 static bool
865 vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
869 {
870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
871 struct drm_device *dev = crtc->base.dev;
872 intel_clock_t clock;
873 unsigned int bestppm = 1000000;
874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
876 bool found = false;
877
878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
881
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
887 clock.p = clock.p1 * clock.p2;
888 /* based on hardware requirement, prefer bigger m1,m2 values */
889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
890 unsigned int ppm;
891
892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
896
897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
899 continue;
900
901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
906
907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
910 }
911 }
912 }
913 }
914
915 return found;
916 }
917
918 static bool
919 chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923 {
924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
925 struct drm_device *dev = crtc->base.dev;
926 unsigned int best_error_ppm;
927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
932 best_error_ppm = 1000000;
933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
946 unsigned int error_ppm;
947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
970 }
971 }
972
973 return found;
974 }
975
976 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978 {
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983 }
984
985 bool intel_crtc_active(struct drm_crtc *crtc)
986 {
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
992 * We can ditch the adjusted_mode.crtc_clock check as soon
993 * as Haswell has gained clock readout/fastboot support.
994 *
995 * We can ditch the crtc->primary->fb check as soon as we can
996 * properly reconstruct framebuffers.
997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
1001 */
1002 return intel_crtc->active && crtc->primary->state->fb &&
1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
1004 }
1005
1006 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008 {
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
1012 return intel_crtc->config->cpu_transcoder;
1013 }
1014
1015 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016 {
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032 }
1033
1034 /*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
1036 * @crtc: crtc whose pipe to wait for
1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
1048 *
1049 */
1050 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1051 {
1052 struct drm_device *dev = crtc->base.dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1055 enum pipe pipe = crtc->pipe;
1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
1058 int reg = PIPECONF(cpu_transcoder);
1059
1060 /* Wait for the Pipe State to go off */
1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 } else {
1065 /* Wait for the display line to settle */
1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1067 WARN(1, "pipe_off wait timed out\n");
1068 }
1069 }
1070
1071 /*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080 {
1081 u32 bit;
1082
1083 if (HAS_PCH_IBX(dev_priv->dev)) {
1084 switch (port->port) {
1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
1098 switch (port->port) {
1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114 }
1115
1116 static const char *state_string(bool enabled)
1117 {
1118 return enabled ? "on" : "off";
1119 }
1120
1121 /* Only for pre-ILK configs */
1122 void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
1124 {
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
1132 I915_STATE_WARN(cur_state != state,
1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135 }
1136
1137 /* XXX: the dsi pll is shared between MIPI DSI ports */
1138 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139 {
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
1148 I915_STATE_WARN(cur_state != state,
1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
1155 struct intel_shared_dpll *
1156 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157 {
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
1160 if (crtc->config->shared_dpll < 0)
1161 return NULL;
1162
1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1164 }
1165
1166 /* For ILK+ */
1167 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
1170 {
1171 bool cur_state;
1172 struct intel_dpll_hw_state hw_state;
1173
1174 if (WARN (!pll,
1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
1176 return;
1177
1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1179 I915_STATE_WARN(cur_state != state,
1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186 {
1187 int reg;
1188 u32 val;
1189 bool cur_state;
1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
1192
1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
1203 I915_STATE_WARN(cur_state != state,
1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206 }
1207 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212 {
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
1220 I915_STATE_WARN(cur_state != state,
1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223 }
1224 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229 {
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1235 return;
1236
1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1238 if (HAS_DDI(dev_priv->dev))
1239 return;
1240
1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1244 }
1245
1246 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
1248 {
1249 int reg;
1250 u32 val;
1251 bool cur_state;
1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1256 I915_STATE_WARN(cur_state != state,
1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
1259 }
1260
1261 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263 {
1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
1268 bool locked = true;
1269
1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
1276 pp_reg = PCH_PP_CONTROL;
1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
1287 } else {
1288 pp_reg = PP_CONTROL;
1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1296 locked = false;
1297
1298 I915_STATE_WARN(panel_pipe == pipe && locked,
1299 "panel assertion failure, pipe %c regs locked\n",
1300 pipe_name(pipe));
1301 }
1302
1303 static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305 {
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
1309 if (IS_845G(dev) || IS_I865G(dev))
1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1311 else
1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1313
1314 I915_STATE_WARN(cur_state != state,
1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317 }
1318 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
1321 void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
1323 {
1324 int reg;
1325 u32 val;
1326 bool cur_state;
1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
1329
1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1333 state = true;
1334
1335 if (!intel_display_power_is_enabled(dev_priv,
1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
1344 I915_STATE_WARN(cur_state != state,
1345 "pipe %c assertion failure (expected %s, current %s)\n",
1346 pipe_name(pipe), state_string(state), state_string(cur_state));
1347 }
1348
1349 static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
1351 {
1352 int reg;
1353 u32 val;
1354 bool cur_state;
1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1359 I915_STATE_WARN(cur_state != state,
1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
1362 }
1363
1364 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
1367 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369 {
1370 struct drm_device *dev = dev_priv->dev;
1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
1382 return;
1383 }
1384
1385 /* Need to check both planes against the pipe */
1386 for_each_pipe(dev_priv, i) {
1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
1394 }
1395 }
1396
1397 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399 {
1400 struct drm_device *dev = dev_priv->dev;
1401 int reg, sprite;
1402 u32 val;
1403
1404 if (INTEL_INFO(dev)->gen >= 9) {
1405 for_each_sprite(dev_priv, pipe, sprite) {
1406 val = I915_READ(PLANE_CTL(pipe, sprite));
1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
1412 for_each_sprite(dev_priv, pipe, sprite) {
1413 reg = SPCNTR(pipe, sprite);
1414 val = I915_READ(reg);
1415 I915_STATE_WARN(val & SP_ENABLE,
1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1417 sprite_name(pipe, sprite), pipe_name(pipe));
1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
1421 val = I915_READ(reg);
1422 I915_STATE_WARN(val & SPRITE_ENABLE,
1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
1427 val = I915_READ(reg);
1428 I915_STATE_WARN(val & DVS_ENABLE,
1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1430 plane_name(pipe), pipe_name(pipe));
1431 }
1432 }
1433
1434 static void assert_vblank_disabled(struct drm_crtc *crtc)
1435 {
1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1437 drm_crtc_vblank_put(crtc);
1438 }
1439
1440 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1441 {
1442 u32 val;
1443 bool enabled;
1444
1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1446
1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1451 }
1452
1453 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
1455 {
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
1460 reg = PCH_TRANSCONF(pipe);
1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
1463 I915_STATE_WARN(enabled,
1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
1466 }
1467
1468 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
1470 {
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487 }
1488
1489 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491 {
1492 if ((val & SDVO_ENABLE) == 0)
1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1497 return false;
1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1501 } else {
1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1503 return false;
1504 }
1505 return true;
1506 }
1507
1508 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510 {
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522 }
1523
1524 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526 {
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537 }
1538
1539 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1540 enum pipe pipe, int reg, u32 port_sel)
1541 {
1542 u32 val = I915_READ(reg);
1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1545 reg, pipe_name(pipe));
1546
1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1548 && (val & DP_PIPEB_SELECT),
1549 "IBX PCH dp port still using transcoder B\n");
1550 }
1551
1552 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554 {
1555 u32 val = I915_READ(reg);
1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1558 reg, pipe_name(pipe));
1559
1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1561 && (val & SDVO_PIPE_B_SELECT),
1562 "IBX PCH hdmi port still using transcoder B\n");
1563 }
1564
1565 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567 {
1568 int reg;
1569 u32 val;
1570
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
1579 pipe_name(pipe));
1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1590 }
1591
1592 static void intel_init_dpio(struct drm_device *dev)
1593 {
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
1610 }
1611
1612 static void vlv_enable_pll(struct intel_crtc *crtc,
1613 const struct intel_crtc_state *pipe_config)
1614 {
1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
1619
1620 assert_pipe_disabled(dev_priv, crtc->pipe);
1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
1626 if (IS_MOBILE(dev_priv->dev))
1627 assert_panel_unlocked(dev_priv, crtc->pipe);
1628
1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1637 POSTING_READ(DPLL_MD(crtc->pipe));
1638
1639 /* We do this three times for luck */
1640 I915_WRITE(reg, dpll);
1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 }
1650
1651 static void chv_enable_pll(struct intel_crtc *crtc,
1652 const struct intel_crtc_state *pipe_config)
1653 {
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1678
1679 /* Check PLL is locked */
1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
1683 /* not sure when this should be written */
1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1685 POSTING_READ(DPLL_MD(pipe));
1686
1687 mutex_unlock(&dev_priv->dpio_lock);
1688 }
1689
1690 static int intel_num_dvo_pipes(struct drm_device *dev)
1691 {
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1698
1699 return count;
1700 }
1701
1702 static void i9xx_enable_pll(struct intel_crtc *crtc)
1703 {
1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
1708
1709 assert_pipe_disabled(dev_priv, crtc->pipe);
1710
1711 /* No really, not for ILK+ */
1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1713
1714 /* PLL is protected by panel, make sure we can write it */
1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
1717
1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
1737 crtc->config->dpll_hw_state.dpll_md);
1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
1746
1747 /* We do this three times for luck */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg, dpll);
1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754 I915_WRITE(reg, dpll);
1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757 }
1758
1759 /**
1760 * i9xx_disable_pll - disable a PLL
1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1768 static void i9xx_disable_pll(struct intel_crtc *crtc)
1769 {
1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
1794 }
1795
1796 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797 {
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
1807 if (pipe == PIPE_B)
1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
1811
1812 }
1813
1814 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815 {
1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1817 u32 val;
1818
1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
1821
1822 /* Set PLL en = 0 */
1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
1847 mutex_unlock(&dev_priv->dpio_lock);
1848 }
1849
1850 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
1853 {
1854 u32 port_mask;
1855 int dpll_reg;
1856
1857 switch (dport->port) {
1858 case PORT_B:
1859 port_mask = DPLL_PORTB_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_C:
1863 port_mask = DPLL_PORTC_READY_MASK;
1864 dpll_reg = DPLL(0);
1865 expected_mask <<= 4;
1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
1870 break;
1871 default:
1872 BUG();
1873 }
1874
1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1878 }
1879
1880 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881 {
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
1886 if (WARN_ON(pll == NULL))
1887 return;
1888
1889 WARN_ON(!pll->config.crtc_mask);
1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897 }
1898
1899 /**
1900 * intel_enable_shared_dpll - enable PCH PLL
1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
1907 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1908 {
1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1912
1913 if (WARN_ON(pll == NULL))
1914 return;
1915
1916 if (WARN_ON(pll->config.crtc_mask == 0))
1917 return;
1918
1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1920 pll->name, pll->active, pll->on,
1921 crtc->base.base.id);
1922
1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
1925 assert_shared_dpll_enabled(dev_priv, pll);
1926 return;
1927 }
1928 WARN_ON(pll->on);
1929
1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1933 pll->enable(dev_priv, pll);
1934 pll->on = true;
1935 }
1936
1937 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1938 {
1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1942
1943 /* PCH only available on ILK+ */
1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
1945 if (WARN_ON(pll == NULL))
1946 return;
1947
1948 if (WARN_ON(pll->config.crtc_mask == 0))
1949 return;
1950
1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
1953 crtc->base.base.id);
1954
1955 if (WARN_ON(pll->active == 0)) {
1956 assert_shared_dpll_disabled(dev_priv, pll);
1957 return;
1958 }
1959
1960 assert_shared_dpll_enabled(dev_priv, pll);
1961 WARN_ON(!pll->on);
1962 if (--pll->active)
1963 return;
1964
1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1966 pll->disable(dev_priv, pll);
1967 pll->on = false;
1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1970 }
1971
1972 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
1974 {
1975 struct drm_device *dev = dev_priv->dev;
1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 uint32_t reg, val, pipeconf_val;
1979
1980 /* PCH only available on ILK+ */
1981 BUG_ON(!HAS_PCH_SPLIT(dev));
1982
1983 /* Make sure PCH DPLL is enabled */
1984 assert_shared_dpll_enabled(dev_priv,
1985 intel_crtc_to_shared_dpll(intel_crtc));
1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
1998 }
1999
2000 reg = PCH_TRANSCONF(pipe);
2001 val = I915_READ(reg);
2002 pipeconf_val = I915_READ(PIPECONF(pipe));
2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
2011 }
2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2015 if (HAS_PCH_IBX(dev_priv->dev) &&
2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2026 }
2027
2028 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum transcoder cpu_transcoder)
2030 {
2031 u32 val, pipeconf_val;
2032
2033 /* PCH only available on ILK+ */
2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2035
2036 /* FDI must be feeding us bits for PCH ports */
2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2039
2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
2045 val = TRANS_ENABLE;
2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2047
2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
2050 val |= TRANS_INTERLACED;
2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2056 DRM_ERROR("Failed to enable PCH transcoder\n");
2057 }
2058
2059 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
2072 reg = PCH_TRANSCONF(pipe);
2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
2087 }
2088
2089 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2090 {
2091 u32 val;
2092
2093 val = I915_READ(LPT_TRANSCONF);
2094 val &= ~TRANS_ENABLE;
2095 I915_WRITE(LPT_TRANSCONF, val);
2096 /* wait for PCH transcoder off, transcoder state */
2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2098 DRM_ERROR("Failed to disable PCH transcoder\n");
2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2103 I915_WRITE(_TRANSA_CHICKEN2, val);
2104 }
2105
2106 /**
2107 * intel_enable_pipe - enable a pipe, asserting requirements
2108 * @crtc: crtc responsible for the pipe
2109 *
2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2112 */
2113 static void intel_enable_pipe(struct intel_crtc *crtc)
2114 {
2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
2120 enum pipe pch_transcoder;
2121 int reg;
2122 u32 val;
2123
2124 assert_planes_disabled(dev_priv, pipe);
2125 assert_cursor_disabled(dev_priv, pipe);
2126 assert_sprites_disabled(dev_priv, pipe);
2127
2128 if (HAS_PCH_LPT(dev_priv->dev))
2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
2143 else {
2144 if (crtc->config->has_pch_encoder) {
2145 /* if driving the PCH, we need FDI enabled */
2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
2152
2153 reg = PIPECONF(cpu_transcoder);
2154 val = I915_READ(reg);
2155 if (val & PIPECONF_ENABLE) {
2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2158 return;
2159 }
2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
2162 POSTING_READ(reg);
2163 }
2164
2165 /**
2166 * intel_disable_pipe - disable a pipe, asserting requirements
2167 * @crtc: crtc whose pipes is to be disabled
2168 *
2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
2175 static void intel_disable_pipe(struct intel_crtc *crtc)
2176 {
2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2179 enum pipe pipe = crtc->pipe;
2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
2188 assert_cursor_disabled(dev_priv, pipe);
2189 assert_sprites_disabled(dev_priv, pipe);
2190
2191 reg = PIPECONF(cpu_transcoder);
2192 val = I915_READ(reg);
2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
2200 if (crtc->config->double_wide)
2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
2211 }
2212
2213 /*
2214 * Plane regs are double buffered, going from enabled->disabled needs a
2215 * trigger in order to latch. The display address reg provides this.
2216 */
2217 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218 enum plane plane)
2219 {
2220 struct drm_device *dev = dev_priv->dev;
2221 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2222
2223 I915_WRITE(reg, I915_READ(reg));
2224 POSTING_READ(reg);
2225 }
2226
2227 /**
2228 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2229 * @plane: plane to be enabled
2230 * @crtc: crtc for the plane
2231 *
2232 * Enable @plane on @crtc, making sure that the pipe is running first.
2233 */
2234 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235 struct drm_crtc *crtc)
2236 {
2237 struct drm_device *dev = plane->dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2240
2241 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2242 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2243 to_intel_plane_state(plane->state)->visible = true;
2244
2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
2247 }
2248
2249 static bool need_vtd_wa(struct drm_device *dev)
2250 {
2251 #ifdef CONFIG_INTEL_IOMMU
2252 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253 return true;
2254 #endif
2255 return false;
2256 }
2257
2258 unsigned int
2259 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260 uint64_t fb_format_modifier)
2261 {
2262 unsigned int tile_height;
2263 uint32_t pixel_bytes;
2264
2265 switch (fb_format_modifier) {
2266 case DRM_FORMAT_MOD_NONE:
2267 tile_height = 1;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 tile_height = IS_GEN2(dev) ? 16 : 8;
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 tile_height = 32;
2274 break;
2275 case I915_FORMAT_MOD_Yf_TILED:
2276 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277 switch (pixel_bytes) {
2278 default:
2279 case 1:
2280 tile_height = 64;
2281 break;
2282 case 2:
2283 case 4:
2284 tile_height = 32;
2285 break;
2286 case 8:
2287 tile_height = 16;
2288 break;
2289 case 16:
2290 WARN_ONCE(1,
2291 "128-bit pixels are not supported for display!");
2292 tile_height = 16;
2293 break;
2294 }
2295 break;
2296 default:
2297 MISSING_CASE(fb_format_modifier);
2298 tile_height = 1;
2299 break;
2300 }
2301
2302 return tile_height;
2303 }
2304
2305 unsigned int
2306 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307 uint32_t pixel_format, uint64_t fb_format_modifier)
2308 {
2309 return ALIGN(height, intel_tile_height(dev, pixel_format,
2310 fb_format_modifier));
2311 }
2312
2313 static int
2314 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315 const struct drm_plane_state *plane_state)
2316 {
2317 struct intel_rotation_info *info = &view->rotation_info;
2318
2319 *view = i915_ggtt_view_normal;
2320
2321 if (!plane_state)
2322 return 0;
2323
2324 if (!intel_rotation_90_or_270(plane_state->rotation))
2325 return 0;
2326
2327 *view = i915_ggtt_view_rotated;
2328
2329 info->height = fb->height;
2330 info->pixel_format = fb->pixel_format;
2331 info->pitch = fb->pitches[0];
2332 info->fb_modifier = fb->modifier[0];
2333
2334 return 0;
2335 }
2336
2337 int
2338 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339 struct drm_framebuffer *fb,
2340 const struct drm_plane_state *plane_state,
2341 struct intel_engine_cs *pipelined)
2342 {
2343 struct drm_device *dev = fb->dev;
2344 struct drm_i915_private *dev_priv = dev->dev_private;
2345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2346 struct i915_ggtt_view view;
2347 u32 alignment;
2348 int ret;
2349
2350 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
2352 switch (fb->modifier[0]) {
2353 case DRM_FORMAT_MOD_NONE:
2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2357 alignment = 128 * 1024;
2358 else if (INTEL_INFO(dev)->gen >= 4)
2359 alignment = 4 * 1024;
2360 else
2361 alignment = 64 * 1024;
2362 break;
2363 case I915_FORMAT_MOD_X_TILED:
2364 if (INTEL_INFO(dev)->gen >= 9)
2365 alignment = 256 * 1024;
2366 else {
2367 /* pin() will align the object as required by fence */
2368 alignment = 0;
2369 }
2370 break;
2371 case I915_FORMAT_MOD_Y_TILED:
2372 case I915_FORMAT_MOD_Yf_TILED:
2373 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374 "Y tiling bo slipped through, driver bug!\n"))
2375 return -EINVAL;
2376 alignment = 1 * 1024 * 1024;
2377 break;
2378 default:
2379 MISSING_CASE(fb->modifier[0]);
2380 return -EINVAL;
2381 }
2382
2383 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384 if (ret)
2385 return ret;
2386
2387 /* Note that the w/a also requires 64 PTE of padding following the
2388 * bo. We currently fill all unused PTE with the shadow page and so
2389 * we should always have valid PTE following the scanout preventing
2390 * the VT-d warning.
2391 */
2392 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393 alignment = 256 * 1024;
2394
2395 /*
2396 * Global gtt pte registers are special registers which actually forward
2397 * writes to a chunk of system memory. Which means that there is no risk
2398 * that the register values disappear as soon as we call
2399 * intel_runtime_pm_put(), so it is correct to wrap only the
2400 * pin/unpin/fence and not more.
2401 */
2402 intel_runtime_pm_get(dev_priv);
2403
2404 dev_priv->mm.interruptible = false;
2405 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2406 &view);
2407 if (ret)
2408 goto err_interruptible;
2409
2410 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411 * fence, whereas 965+ only requires a fence if using
2412 * framebuffer compression. For simplicity, we always install
2413 * a fence as the cost is not that onerous.
2414 */
2415 ret = i915_gem_object_get_fence(obj);
2416 if (ret)
2417 goto err_unpin;
2418
2419 i915_gem_object_pin_fence(obj);
2420
2421 dev_priv->mm.interruptible = true;
2422 intel_runtime_pm_put(dev_priv);
2423 return 0;
2424
2425 err_unpin:
2426 i915_gem_object_unpin_from_display_plane(obj, &view);
2427 err_interruptible:
2428 dev_priv->mm.interruptible = true;
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435 {
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438 int ret;
2439
2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
2445 i915_gem_object_unpin_fence(obj);
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452 unsigned int tiling_mode,
2453 unsigned int cpp,
2454 unsigned int pitch)
2455 {
2456 if (tiling_mode != I915_TILING_NONE) {
2457 unsigned int tile_rows, tiles;
2458
2459 tile_rows = *y / 8;
2460 *y %= 8;
2461
2462 tiles = *x / (512/cpp);
2463 *x %= 512/cpp;
2464
2465 return tile_rows * pitch * 8 + tiles * 4096;
2466 } else {
2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
2470 *y = 0;
2471 *x = (offset & 4095) / cpp;
2472 return offset & -4096;
2473 }
2474 }
2475
2476 static int i9xx_format_to_fourcc(int format)
2477 {
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495 }
2496
2497 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498 {
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521 }
2522
2523 static bool
2524 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
2526 {
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2530 struct drm_framebuffer *fb = &plane_config->fb->base;
2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
2536
2537 if (plane_config->size == 0)
2538 return false;
2539
2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
2544 if (!obj)
2545 return false;
2546
2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
2549 obj->stride = fb->pitches[0];
2550
2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558 mutex_lock(&dev->struct_mutex);
2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560 &mode_cmd, obj)) {
2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
2564 mutex_unlock(&dev->struct_mutex);
2565
2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567 return true;
2568
2569 out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
2572 return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
2592 {
2593 struct drm_device *dev = intel_crtc->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2597 struct drm_i915_gem_object *obj;
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_framebuffer *fb;
2600
2601 if (!plane_config->fb)
2602 return;
2603
2604 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2605 fb = &plane_config->fb->base;
2606 goto valid_fb;
2607 }
2608
2609 kfree(plane_config->fb);
2610
2611 /*
2612 * Failed to alloc the obj, check to see if we should share
2613 * an fb with another CRTC instead
2614 */
2615 for_each_crtc(dev, c) {
2616 i = to_intel_crtc(c);
2617
2618 if (c == &intel_crtc->base)
2619 continue;
2620
2621 if (!i->active)
2622 continue;
2623
2624 fb = c->primary->fb;
2625 if (!fb)
2626 continue;
2627
2628 obj = intel_fb_obj(fb);
2629 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2630 drm_framebuffer_reference(fb);
2631 goto valid_fb;
2632 }
2633 }
2634
2635 return;
2636
2637 valid_fb:
2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
2642 primary->fb = fb;
2643 primary->state->crtc = &intel_crtc->base;
2644 primary->crtc = &intel_crtc->base;
2645 update_state_fb(primary);
2646 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2647 }
2648
2649 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
2652 {
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
2658 struct drm_i915_gem_object *obj;
2659 int plane = intel_crtc->plane;
2660 unsigned long linear_offset;
2661 u32 dspcntr;
2662 u32 reg = DSPCNTR(plane);
2663 int pixel_size;
2664
2665 if (!visible || !fb) {
2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
2683 dspcntr |= DISPLAY_PLANE_ENABLE;
2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
2695 I915_WRITE(DSPPOS(plane), 0);
2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2702 }
2703
2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
2708 case DRM_FORMAT_XRGB1555:
2709 dspcntr |= DISPPLANE_BGRX555;
2710 break;
2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 dspcntr |= DISPPLANE_RGBX101010;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
2733
2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
2738
2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
2746 intel_crtc->dspaddr_offset = linear_offset;
2747 }
2748
2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2765 if (INTEL_INFO(dev)->gen >= 4) {
2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 } else
2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2772 POSTING_READ(reg);
2773 }
2774
2775 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
2778 {
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
2784 struct drm_i915_gem_object *obj;
2785 int plane = intel_crtc->plane;
2786 unsigned long linear_offset;
2787 u32 dspcntr;
2788 u32 reg = DSPCNTR(plane);
2789 int pixel_size;
2790
2791 if (!visible || !fb) {
2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
2806 dspcntr |= DISPLAY_PLANE_ENABLE;
2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2810
2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
2817 break;
2818 case DRM_FORMAT_XRGB8888:
2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
2822 dspcntr |= DISPPLANE_RGBX888;
2823 break;
2824 case DRM_FORMAT_XRGB2101010:
2825 dspcntr |= DISPPLANE_BGRX101010;
2826 break;
2827 case DRM_FORMAT_XBGR2101010:
2828 dspcntr |= DISPPLANE_RGBX101010;
2829 break;
2830 default:
2831 BUG();
2832 }
2833
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
2836
2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2839
2840 linear_offset = y * fb->pitches[0] + x * pixel_size;
2841 intel_crtc->dspaddr_offset =
2842 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2843 pixel_size,
2844 fb->pitches[0]);
2845 linear_offset -= intel_crtc->dspaddr_offset;
2846 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2847 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2850 x += (intel_crtc->config->pipe_src_w - 1);
2851 y += (intel_crtc->config->pipe_src_h - 1);
2852
2853 /* Finding the last pixel of the last line of the display
2854 data and adding to linear_offset*/
2855 linear_offset +=
2856 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2858 }
2859 }
2860
2861 I915_WRITE(reg, dspcntr);
2862
2863 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2864 I915_WRITE(DSPSURF(plane),
2865 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2867 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868 } else {
2869 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871 }
2872 POSTING_READ(reg);
2873 }
2874
2875 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876 uint32_t pixel_format)
2877 {
2878 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880 /*
2881 * The stride is either expressed as a multiple of 64 bytes
2882 * chunks for linear buffers or in number of tiles for tiled
2883 * buffers.
2884 */
2885 switch (fb_modifier) {
2886 case DRM_FORMAT_MOD_NONE:
2887 return 64;
2888 case I915_FORMAT_MOD_X_TILED:
2889 if (INTEL_INFO(dev)->gen == 2)
2890 return 128;
2891 return 512;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 /* No need to check for old gens and Y tiling since this is
2894 * about the display engine and those will be blocked before
2895 * we get here.
2896 */
2897 return 128;
2898 case I915_FORMAT_MOD_Yf_TILED:
2899 if (bits_per_pixel == 8)
2900 return 64;
2901 else
2902 return 128;
2903 default:
2904 MISSING_CASE(fb_modifier);
2905 return 64;
2906 }
2907 }
2908
2909 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910 struct drm_i915_gem_object *obj)
2911 {
2912 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2913
2914 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2915 view = &i915_ggtt_view_rotated;
2916
2917 return i915_gem_obj_ggtt_offset_view(obj, view);
2918 }
2919
2920 /*
2921 * This function detaches (aka. unbinds) unused scalers in hardware
2922 */
2923 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924 {
2925 struct drm_device *dev;
2926 struct drm_i915_private *dev_priv;
2927 struct intel_crtc_scaler_state *scaler_state;
2928 int i;
2929
2930 if (!intel_crtc || !intel_crtc->config)
2931 return;
2932
2933 dev = intel_crtc->base.dev;
2934 dev_priv = dev->dev_private;
2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use) {
2940 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945 }
2946 }
2947 }
2948
2949 u32 skl_plane_ctl_format(uint32_t pixel_format)
2950 {
2951 switch (pixel_format) {
2952 case DRM_FORMAT_C8:
2953 return PLANE_CTL_FORMAT_INDEXED;
2954 case DRM_FORMAT_RGB565:
2955 return PLANE_CTL_FORMAT_RGB_565;
2956 case DRM_FORMAT_XBGR8888:
2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2958 case DRM_FORMAT_XRGB8888:
2959 return PLANE_CTL_FORMAT_XRGB_8888;
2960 /*
2961 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962 * to be already pre-multiplied. We need to add a knob (or a different
2963 * DRM_FORMAT) for user-space to configure that.
2964 */
2965 case DRM_FORMAT_ABGR8888:
2966 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2968 case DRM_FORMAT_ARGB8888:
2969 return PLANE_CTL_FORMAT_XRGB_8888 |
2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2971 case DRM_FORMAT_XRGB2101010:
2972 return PLANE_CTL_FORMAT_XRGB_2101010;
2973 case DRM_FORMAT_XBGR2101010:
2974 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2975 case DRM_FORMAT_YUYV:
2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2977 case DRM_FORMAT_YVYU:
2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2979 case DRM_FORMAT_UYVY:
2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2981 case DRM_FORMAT_VYUY:
2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2983 default:
2984 MISSING_CASE(pixel_format);
2985 }
2986
2987 return 0;
2988 }
2989
2990 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991 {
2992 switch (fb_modifier) {
2993 case DRM_FORMAT_MOD_NONE:
2994 break;
2995 case I915_FORMAT_MOD_X_TILED:
2996 return PLANE_CTL_TILED_X;
2997 case I915_FORMAT_MOD_Y_TILED:
2998 return PLANE_CTL_TILED_Y;
2999 case I915_FORMAT_MOD_Yf_TILED:
3000 return PLANE_CTL_TILED_YF;
3001 default:
3002 MISSING_CASE(fb_modifier);
3003 }
3004
3005 return 0;
3006 }
3007
3008 u32 skl_plane_ctl_rotation(unsigned int rotation)
3009 {
3010 switch (rotation) {
3011 case BIT(DRM_ROTATE_0):
3012 break;
3013 /*
3014 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3015 * while i915 HW rotation is clockwise, thats why this swapping.
3016 */
3017 case BIT(DRM_ROTATE_90):
3018 return PLANE_CTL_ROTATE_270;
3019 case BIT(DRM_ROTATE_180):
3020 return PLANE_CTL_ROTATE_180;
3021 case BIT(DRM_ROTATE_270):
3022 return PLANE_CTL_ROTATE_90;
3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
3027 return 0;
3028 }
3029
3030 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033 {
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
3052 plane_state = to_intel_plane_state(plane->state);
3053
3054 if (!visible || !fb) {
3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3059 }
3060
3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
3104 x_offset = stride * tile_height - y - src_h;
3105 y_offset = x;
3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3112 }
3113 plane_offset = y_offset << 16 | x_offset;
3114
3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138 }
3139
3140 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3141 static int
3142 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144 {
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147
3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
3150
3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
3154 }
3155
3156 static void intel_complete_page_flips(struct drm_device *dev)
3157 {
3158 struct drm_crtc *crtc;
3159
3160 for_each_crtc(dev, crtc) {
3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
3167 }
3168
3169 static void intel_update_primary_planes(struct drm_device *dev)
3170 {
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
3173
3174 for_each_crtc(dev, crtc) {
3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
3177 drm_modeset_lock(&crtc->mutex, NULL);
3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
3181 * a NULL crtc->primary->fb.
3182 */
3183 if (intel_crtc->active && crtc->primary->fb)
3184 dev_priv->display.update_primary_plane(crtc,
3185 crtc->primary->fb,
3186 crtc->x,
3187 crtc->y);
3188 drm_modeset_unlock(&crtc->mutex);
3189 }
3190 }
3191
3192 void intel_crtc_reset(struct intel_crtc *crtc)
3193 {
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203 }
3204
3205 void intel_prepare_reset(struct drm_device *dev)
3206 {
3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
3230 }
3231 }
3232
3233 void intel_finish_reset(struct drm_device *dev)
3234 {
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279 }
3280
3281 static void
3282 intel_finish_fb(struct drm_framebuffer *old_fb)
3283 {
3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
3301 ret = i915_gem_object_wait_rendering(obj, true);
3302 dev_priv->mm.interruptible = was_interruptible;
3303
3304 WARN_ON(ret);
3305 }
3306
3307 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308 {
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
3318 spin_lock_irq(&dev->event_lock);
3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3320 spin_unlock_irq(&dev->event_lock);
3321
3322 return pending;
3323 }
3324
3325 static void intel_update_pipe_size(struct intel_crtc *crtc)
3326 {
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
3348 adjusted_mode = &crtc->config->base.adjusted_mode;
3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
3353 if (!crtc->config->pch_pfit.enabled &&
3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3362 }
3363
3364 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365 {
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
3375 if (IS_IVYBRIDGE(dev)) {
3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3381 }
3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
3403 }
3404
3405 /* The FDI link training functions for ILK/Ibexpeak. */
3406 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407 {
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
3412 u32 reg, temp, tries;
3413
3414 /* FDI needs bits from pipe first */
3415 assert_pipe_enabled(dev_priv, pipe);
3416
3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
3425 udelay(150);
3426
3427 /* enable CPU FDI TX and PCH FDI RX */
3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3435
3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
3443 udelay(150);
3444
3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
3449
3450 reg = FDI_RX_IIR(pipe);
3451 for (tries = 0; tries < 5; tries++) {
3452 temp = I915_READ(reg);
3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3458 break;
3459 }
3460 }
3461 if (tries == 5)
3462 DRM_ERROR("FDI train 1 fail!\n");
3463
3464 /* Train 2 */
3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
3469 I915_WRITE(reg, temp);
3470
3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
3475 I915_WRITE(reg, temp);
3476
3477 POSTING_READ(reg);
3478 udelay(150);
3479
3480 reg = FDI_RX_IIR(pipe);
3481 for (tries = 0; tries < 5; tries++) {
3482 temp = I915_READ(reg);
3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
3490 }
3491 if (tries == 5)
3492 DRM_ERROR("FDI train 2 fail!\n");
3493
3494 DRM_DEBUG_KMS("FDI train done\n");
3495
3496 }
3497
3498 static const int snb_b_fdi_train_param[] = {
3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503 };
3504
3505 /* The FDI link training functions for SNB/Cougarpoint. */
3506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507 {
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
3512 u32 reg, temp, i, retry;
3513
3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
3523 udelay(150);
3524
3525 /* enable CPU FDI TX and PCH FDI RX */
3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3536
3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
3552 udelay(150);
3553
3554 for (i = 0; i < 4; i++) {
3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
3562 udelay(500);
3563
3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
3574 }
3575 if (retry < 5)
3576 break;
3577 }
3578 if (i == 4)
3579 DRM_ERROR("FDI train 1 fail!\n");
3580
3581 /* Train 2 */
3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
3591 I915_WRITE(reg, temp);
3592
3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(150);
3606
3607 for (i = 0; i < 4; i++) {
3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
3615 udelay(500);
3616
3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
3627 }
3628 if (retry < 5)
3629 break;
3630 }
3631 if (i == 4)
3632 DRM_ERROR("FDI train 2 fail!\n");
3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635 }
3636
3637 /* Manual link training for Ivy Bridge A0 parts */
3638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639 {
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
3644 u32 reg, temp, i, j;
3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
3668
3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
3675
3676 /* enable CPU FDI TX and PCH FDI RX */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3686
3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3689
3690 reg = FDI_RX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3695
3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
3698
3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3703
3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
3717
3718 /* Train 2 */
3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
3732 udelay(2); /* should be 1.5us */
3733
3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3738
3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
3747 }
3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3750 }
3751
3752 train_done:
3753 DRM_DEBUG_KMS("FDI train done.\n");
3754 }
3755
3756 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3757 {
3758 struct drm_device *dev = intel_crtc->base.dev;
3759 struct drm_i915_private *dev_priv = dev->dev_private;
3760 int pipe = intel_crtc->pipe;
3761 u32 reg, temp;
3762
3763
3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
3780 udelay(200);
3781
3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3787
3788 POSTING_READ(reg);
3789 udelay(100);
3790 }
3791 }
3792
3793 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794 {
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820 }
3821
3822 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823 {
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
3846 if (HAS_PCH_IBX(dev))
3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872 }
3873
3874 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875 {
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
3885 for_each_intel_crtc(dev, crtc) {
3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896 }
3897
3898 static void page_flip_completed(struct intel_crtc *intel_crtc)
3899 {
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919 }
3920
3921 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925
3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3931
3932 spin_lock_irq(&dev->event_lock);
3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
3937 spin_unlock_irq(&dev->event_lock);
3938 }
3939
3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
3945 }
3946
3947 /* Program iCLKIP clock to the desired frequency */
3948 static void lpt_program_iclkip(struct drm_crtc *crtc)
3949 {
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
3956 mutex_lock(&dev_priv->dpio_lock);
3957
3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3970 if (clock == 20000) {
3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
3985 desired_divisor = (iclk_virtual_root_freq / clock);
3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4001 clock,
4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4016
4017 /* Program SSCAUXDIV */
4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4022
4023 /* Enable modulator and associated divider */
4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4025 temp &= ~SBI_SSCCTL_DISABLE;
4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4032
4033 mutex_unlock(&dev_priv->dpio_lock);
4034 }
4035
4036 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038 {
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058 }
4059
4060 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4061 {
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079 }
4080
4081 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082 {
4083 struct drm_device *dev = intel_crtc->base.dev;
4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
4089 if (intel_crtc->config->fdi_lanes > 2)
4090 cpt_set_fdi_bc_bifurcation(dev, false);
4091 else
4092 cpt_set_fdi_bc_bifurcation(dev, true);
4093
4094 break;
4095 case PIPE_C:
4096 cpt_set_fdi_bc_bifurcation(dev, true);
4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102 }
4103
4104 /*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112 static void ironlake_pch_enable(struct drm_crtc *crtc)
4113 {
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
4118 u32 reg, temp;
4119
4120 assert_pch_transcoder_disabled(dev_priv, pipe);
4121
4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
4130 /* For PCH output, training FDI link */
4131 dev_priv->display.fdi_link_train(crtc);
4132
4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
4135 if (HAS_PCH_CPT(dev)) {
4136 u32 sel;
4137
4138 temp = I915_READ(PCH_DPLL_SEL);
4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4142 temp |= sel;
4143 else
4144 temp &= ~sel;
4145 I915_WRITE(PCH_DPLL_SEL, temp);
4146 }
4147
4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
4155 intel_enable_shared_dpll(intel_crtc);
4156
4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4160
4161 intel_fdi_normal_train(crtc);
4162
4163 /* For PCH DP, enable TRANS_DP_CTL */
4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
4171 temp |= (TRANS_DP_OUTPUT_ENABLE |
4172 TRANS_DP_ENH_FRAMING);
4173 temp |= bpc << 9; /* same format but at 11:9 */
4174
4175 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4176 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4177 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4178 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4179
4180 switch (intel_trans_dp_port_sel(crtc)) {
4181 case PCH_DP_B:
4182 temp |= TRANS_DP_PORT_SEL_B;
4183 break;
4184 case PCH_DP_C:
4185 temp |= TRANS_DP_PORT_SEL_C;
4186 break;
4187 case PCH_DP_D:
4188 temp |= TRANS_DP_PORT_SEL_D;
4189 break;
4190 default:
4191 BUG();
4192 }
4193
4194 I915_WRITE(reg, temp);
4195 }
4196
4197 ironlake_enable_pch_transcoder(dev_priv, pipe);
4198 }
4199
4200 static void lpt_pch_enable(struct drm_crtc *crtc)
4201 {
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4206
4207 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4208
4209 lpt_program_iclkip(crtc);
4210
4211 /* Set transcoder timing. */
4212 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4213
4214 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4215 }
4216
4217 void intel_put_shared_dpll(struct intel_crtc *crtc)
4218 {
4219 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4220
4221 if (pll == NULL)
4222 return;
4223
4224 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4225 WARN(1, "bad %s crtc mask\n", pll->name);
4226 return;
4227 }
4228
4229 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4230 if (pll->config.crtc_mask == 0) {
4231 WARN_ON(pll->on);
4232 WARN_ON(pll->active);
4233 }
4234
4235 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4236 }
4237
4238 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239 struct intel_crtc_state *crtc_state)
4240 {
4241 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4242 struct intel_shared_dpll *pll;
4243 enum intel_dpll_id i;
4244
4245 if (HAS_PCH_IBX(dev_priv->dev)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4247 i = (enum intel_dpll_id) crtc->pipe;
4248 pll = &dev_priv->shared_dplls[i];
4249
4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc->base.base.id, pll->name);
4252
4253 WARN_ON(pll->new_config->crtc_mask);
4254
4255 goto found;
4256 }
4257
4258 if (IS_BROXTON(dev_priv->dev)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder *encoder;
4261 struct intel_digital_port *intel_dig_port;
4262
4263 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264 if (WARN_ON(!encoder))
4265 return NULL;
4266
4267 intel_dig_port = enc_to_dig_port(&encoder->base);
4268 /* 1:1 mapping between ports and PLLs */
4269 i = (enum intel_dpll_id)intel_dig_port->port;
4270 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 WARN_ON(pll->new_config->crtc_mask);
4274
4275 goto found;
4276 }
4277
4278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279 pll = &dev_priv->shared_dplls[i];
4280
4281 /* Only want to check enabled timings first */
4282 if (pll->new_config->crtc_mask == 0)
4283 continue;
4284
4285 if (memcmp(&crtc_state->dpll_hw_state,
4286 &pll->new_config->hw_state,
4287 sizeof(pll->new_config->hw_state)) == 0) {
4288 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4289 crtc->base.base.id, pll->name,
4290 pll->new_config->crtc_mask,
4291 pll->active);
4292 goto found;
4293 }
4294 }
4295
4296 /* Ok no matching timings, maybe there's a free one? */
4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
4299 if (pll->new_config->crtc_mask == 0) {
4300 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301 crtc->base.base.id, pll->name);
4302 goto found;
4303 }
4304 }
4305
4306 return NULL;
4307
4308 found:
4309 if (pll->new_config->crtc_mask == 0)
4310 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4311
4312 crtc_state->shared_dpll = i;
4313 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4314 pipe_name(crtc->pipe));
4315
4316 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4317
4318 return pll;
4319 }
4320
4321 /**
4322 * intel_shared_dpll_start_config - start a new PLL staged config
4323 * @dev_priv: DRM device
4324 * @clear_pipes: mask of pipes that will have their PLLs freed
4325 *
4326 * Starts a new PLL staged config, copying the current config but
4327 * releasing the references of pipes specified in clear_pipes.
4328 */
4329 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4330 unsigned clear_pipes)
4331 {
4332 struct intel_shared_dpll *pll;
4333 enum intel_dpll_id i;
4334
4335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4336 pll = &dev_priv->shared_dplls[i];
4337
4338 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4339 GFP_KERNEL);
4340 if (!pll->new_config)
4341 goto cleanup;
4342
4343 pll->new_config->crtc_mask &= ~clear_pipes;
4344 }
4345
4346 return 0;
4347
4348 cleanup:
4349 while (--i >= 0) {
4350 pll = &dev_priv->shared_dplls[i];
4351 kfree(pll->new_config);
4352 pll->new_config = NULL;
4353 }
4354
4355 return -ENOMEM;
4356 }
4357
4358 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4359 {
4360 struct intel_shared_dpll *pll;
4361 enum intel_dpll_id i;
4362
4363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4364 pll = &dev_priv->shared_dplls[i];
4365
4366 WARN_ON(pll->new_config == &pll->config);
4367
4368 pll->config = *pll->new_config;
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372 }
4373
4374 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4375 {
4376 struct intel_shared_dpll *pll;
4377 enum intel_dpll_id i;
4378
4379 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4380 pll = &dev_priv->shared_dplls[i];
4381
4382 WARN_ON(pll->new_config == &pll->config);
4383
4384 kfree(pll->new_config);
4385 pll->new_config = NULL;
4386 }
4387 }
4388
4389 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4390 {
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392 int dslreg = PIPEDSL(pipe);
4393 u32 temp;
4394
4395 temp = I915_READ(dslreg);
4396 udelay(500);
4397 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4398 if (wait_for(I915_READ(dslreg) != temp, 5))
4399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4400 }
4401 }
4402
4403 /**
4404 * skl_update_scaler_users - Stages update to crtc's scaler state
4405 * @intel_crtc: crtc
4406 * @crtc_state: crtc_state
4407 * @plane: plane (NULL indicates crtc is requesting update)
4408 * @plane_state: plane's state
4409 * @force_detach: request unconditional detachment of scaler
4410 *
4411 * This function updates scaler state for requested plane or crtc.
4412 * To request scaler usage update for a plane, caller shall pass plane pointer.
4413 * To request scaler usage update for crtc, caller shall pass plane pointer
4414 * as NULL.
4415 *
4416 * Return
4417 * 0 - scaler_usage updated successfully
4418 * error - requested scaling cannot be supported or other error condition
4419 */
4420 int
4421 skl_update_scaler_users(
4422 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4423 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4424 int force_detach)
4425 {
4426 int need_scaling;
4427 int idx;
4428 int src_w, src_h, dst_w, dst_h;
4429 int *scaler_id;
4430 struct drm_framebuffer *fb;
4431 struct intel_crtc_scaler_state *scaler_state;
4432 unsigned int rotation;
4433
4434 if (!intel_crtc || !crtc_state)
4435 return 0;
4436
4437 scaler_state = &crtc_state->scaler_state;
4438
4439 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4440 fb = intel_plane ? plane_state->base.fb : NULL;
4441
4442 if (intel_plane) {
4443 src_w = drm_rect_width(&plane_state->src) >> 16;
4444 src_h = drm_rect_height(&plane_state->src) >> 16;
4445 dst_w = drm_rect_width(&plane_state->dst);
4446 dst_h = drm_rect_height(&plane_state->dst);
4447 scaler_id = &plane_state->scaler_id;
4448 rotation = plane_state->base.rotation;
4449 } else {
4450 struct drm_display_mode *adjusted_mode =
4451 &crtc_state->base.adjusted_mode;
4452 src_w = crtc_state->pipe_src_w;
4453 src_h = crtc_state->pipe_src_h;
4454 dst_w = adjusted_mode->hdisplay;
4455 dst_h = adjusted_mode->vdisplay;
4456 scaler_id = &scaler_state->scaler_id;
4457 rotation = DRM_ROTATE_0;
4458 }
4459
4460 need_scaling = intel_rotation_90_or_270(rotation) ?
4461 (src_h != dst_w || src_w != dst_h):
4462 (src_w != dst_w || src_h != dst_h);
4463
4464 /*
4465 * if plane is being disabled or scaler is no more required or force detach
4466 * - free scaler binded to this plane/crtc
4467 * - in order to do this, update crtc->scaler_usage
4468 *
4469 * Here scaler state in crtc_state is set free so that
4470 * scaler can be assigned to other user. Actual register
4471 * update to free the scaler is done in plane/panel-fit programming.
4472 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4473 */
4474 if (force_detach || !need_scaling || (intel_plane &&
4475 (!fb || !plane_state->visible))) {
4476 if (*scaler_id >= 0) {
4477 scaler_state->scaler_users &= ~(1 << idx);
4478 scaler_state->scalers[*scaler_id].in_use = 0;
4479
4480 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4481 "crtc_state = %p scaler_users = 0x%x\n",
4482 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4483 intel_plane ? intel_plane->base.base.id :
4484 intel_crtc->base.base.id, crtc_state,
4485 scaler_state->scaler_users);
4486 *scaler_id = -1;
4487 }
4488 return 0;
4489 }
4490
4491 /* range checks */
4492 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4493 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4494
4495 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4496 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4497 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4498 "size is out of scaler range\n",
4499 intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4501 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4502 return -EINVAL;
4503 }
4504
4505 /* check colorkey */
4506 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4508 intel_plane->base.base.id);
4509 return -EINVAL;
4510 }
4511
4512 /* Check src format */
4513 if (intel_plane) {
4514 switch (fb->pixel_format) {
4515 case DRM_FORMAT_RGB565:
4516 case DRM_FORMAT_XBGR8888:
4517 case DRM_FORMAT_XRGB8888:
4518 case DRM_FORMAT_ABGR8888:
4519 case DRM_FORMAT_ARGB8888:
4520 case DRM_FORMAT_XRGB2101010:
4521 case DRM_FORMAT_XBGR2101010:
4522 case DRM_FORMAT_YUYV:
4523 case DRM_FORMAT_YVYU:
4524 case DRM_FORMAT_UYVY:
4525 case DRM_FORMAT_VYUY:
4526 break;
4527 default:
4528 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4529 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4530 return -EINVAL;
4531 }
4532 }
4533
4534 /* mark this plane as a scaler user in crtc_state */
4535 scaler_state->scaler_users |= (1 << idx);
4536 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4537 "crtc_state = %p scaler_users = 0x%x\n",
4538 intel_plane ? "PLANE" : "CRTC",
4539 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4540 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4541 return 0;
4542 }
4543
4544 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4545 {
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
4549 struct intel_crtc_scaler_state *scaler_state =
4550 &crtc->config->scaler_state;
4551
4552 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4553
4554 /* To update pfit, first update scaler state */
4555 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4556 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4557 skl_detach_scalers(crtc);
4558 if (!enable)
4559 return;
4560
4561 if (crtc->config->pch_pfit.enabled) {
4562 int id;
4563
4564 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4565 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4566 return;
4567 }
4568
4569 id = scaler_state->scaler_id;
4570 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4571 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4572 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4573 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4574
4575 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4576 }
4577 }
4578
4579 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4580 {
4581 struct drm_device *dev = crtc->base.dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 int pipe = crtc->pipe;
4584
4585 if (crtc->config->pch_pfit.enabled) {
4586 /* Force use of hard-coded filter coefficients
4587 * as some pre-programmed values are broken,
4588 * e.g. x201.
4589 */
4590 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4591 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4592 PF_PIPE_SEL_IVB(pipe));
4593 else
4594 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4595 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4596 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4597 }
4598 }
4599
4600 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4601 {
4602 struct drm_device *dev = crtc->dev;
4603 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4604 struct drm_plane *plane;
4605 struct intel_plane *intel_plane;
4606
4607 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4608 intel_plane = to_intel_plane(plane);
4609 if (intel_plane->pipe == pipe)
4610 intel_plane_restore(&intel_plane->base);
4611 }
4612 }
4613
4614 void hsw_enable_ips(struct intel_crtc *crtc)
4615 {
4616 struct drm_device *dev = crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
4618
4619 if (!crtc->config->ips_enabled)
4620 return;
4621
4622 /* We can only enable IPS after we enable a plane and wait for a vblank */
4623 intel_wait_for_vblank(dev, crtc->pipe);
4624
4625 assert_plane_enabled(dev_priv, crtc->plane);
4626 if (IS_BROADWELL(dev)) {
4627 mutex_lock(&dev_priv->rps.hw_lock);
4628 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4629 mutex_unlock(&dev_priv->rps.hw_lock);
4630 /* Quoting Art Runyan: "its not safe to expect any particular
4631 * value in IPS_CTL bit 31 after enabling IPS through the
4632 * mailbox." Moreover, the mailbox may return a bogus state,
4633 * so we need to just enable it and continue on.
4634 */
4635 } else {
4636 I915_WRITE(IPS_CTL, IPS_ENABLE);
4637 /* The bit only becomes 1 in the next vblank, so this wait here
4638 * is essentially intel_wait_for_vblank. If we don't have this
4639 * and don't wait for vblanks until the end of crtc_enable, then
4640 * the HW state readout code will complain that the expected
4641 * IPS_CTL value is not the one we read. */
4642 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4643 DRM_ERROR("Timed out waiting for IPS enable\n");
4644 }
4645 }
4646
4647 void hsw_disable_ips(struct intel_crtc *crtc)
4648 {
4649 struct drm_device *dev = crtc->base.dev;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
4652 if (!crtc->config->ips_enabled)
4653 return;
4654
4655 assert_plane_enabled(dev_priv, crtc->plane);
4656 if (IS_BROADWELL(dev)) {
4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4659 mutex_unlock(&dev_priv->rps.hw_lock);
4660 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4661 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4662 DRM_ERROR("Timed out waiting for IPS disable\n");
4663 } else {
4664 I915_WRITE(IPS_CTL, 0);
4665 POSTING_READ(IPS_CTL);
4666 }
4667
4668 /* We need to wait for a vblank before we can disable the plane. */
4669 intel_wait_for_vblank(dev, crtc->pipe);
4670 }
4671
4672 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4673 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4674 {
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 enum pipe pipe = intel_crtc->pipe;
4679 int palreg = PALETTE(pipe);
4680 int i;
4681 bool reenable_ips = false;
4682
4683 /* The clocks have to be on to load the palette. */
4684 if (!crtc->state->enable || !intel_crtc->active)
4685 return;
4686
4687 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4688 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4689 assert_dsi_pll_enabled(dev_priv);
4690 else
4691 assert_pll_enabled(dev_priv, pipe);
4692 }
4693
4694 /* use legacy palette for Ironlake */
4695 if (!HAS_GMCH_DISPLAY(dev))
4696 palreg = LGC_PALETTE(pipe);
4697
4698 /* Workaround : Do not read or write the pipe palette/gamma data while
4699 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4700 */
4701 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4702 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4703 GAMMA_MODE_MODE_SPLIT)) {
4704 hsw_disable_ips(intel_crtc);
4705 reenable_ips = true;
4706 }
4707
4708 for (i = 0; i < 256; i++) {
4709 I915_WRITE(palreg + 4 * i,
4710 (intel_crtc->lut_r[i] << 16) |
4711 (intel_crtc->lut_g[i] << 8) |
4712 intel_crtc->lut_b[i]);
4713 }
4714
4715 if (reenable_ips)
4716 hsw_enable_ips(intel_crtc);
4717 }
4718
4719 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4720 {
4721 if (intel_crtc->overlay) {
4722 struct drm_device *dev = intel_crtc->base.dev;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725 mutex_lock(&dev->struct_mutex);
4726 dev_priv->mm.interruptible = false;
4727 (void) intel_overlay_switch_off(intel_crtc->overlay);
4728 dev_priv->mm.interruptible = true;
4729 mutex_unlock(&dev->struct_mutex);
4730 }
4731
4732 /* Let userspace switch the overlay on again. In most cases userspace
4733 * has to recompute where to put it anyway.
4734 */
4735 }
4736
4737 /**
4738 * intel_post_enable_primary - Perform operations after enabling primary plane
4739 * @crtc: the CRTC whose primary plane was just enabled
4740 *
4741 * Performs potentially sleeping operations that must be done after the primary
4742 * plane is enabled, such as updating FBC and IPS. Note that this may be
4743 * called due to an explicit primary plane update, or due to an implicit
4744 * re-enable that is caused when a sprite plane is updated to no longer
4745 * completely hide the primary plane.
4746 */
4747 static void
4748 intel_post_enable_primary(struct drm_crtc *crtc)
4749 {
4750 struct drm_device *dev = crtc->dev;
4751 struct drm_i915_private *dev_priv = dev->dev_private;
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
4754
4755 /*
4756 * BDW signals flip done immediately if the plane
4757 * is disabled, even if the plane enable is already
4758 * armed to occur at the next vblank :(
4759 */
4760 if (IS_BROADWELL(dev))
4761 intel_wait_for_vblank(dev, pipe);
4762
4763 /*
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4767 * versa.
4768 */
4769 hsw_enable_ips(intel_crtc);
4770
4771 mutex_lock(&dev->struct_mutex);
4772 intel_fbc_update(dev);
4773 mutex_unlock(&dev->struct_mutex);
4774
4775 /*
4776 * Gen2 reports pipe underruns whenever all planes are disabled.
4777 * So don't enable underrun reporting before at least some planes
4778 * are enabled.
4779 * FIXME: Need to fix the logic to work when we turn off all planes
4780 * but leave the pipe running.
4781 */
4782 if (IS_GEN2(dev))
4783 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4784
4785 /* Underruns don't raise interrupts, so check manually. */
4786 if (HAS_GMCH_DISPLAY(dev))
4787 i9xx_check_fifo_underruns(dev_priv);
4788 }
4789
4790 /**
4791 * intel_pre_disable_primary - Perform operations before disabling primary plane
4792 * @crtc: the CRTC whose primary plane is to be disabled
4793 *
4794 * Performs potentially sleeping operations that must be done before the
4795 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4796 * be called due to an explicit primary plane update, or due to an implicit
4797 * disable that is caused when a sprite plane completely hides the primary
4798 * plane.
4799 */
4800 static void
4801 intel_pre_disable_primary(struct drm_crtc *crtc)
4802 {
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 int pipe = intel_crtc->pipe;
4807
4808 /*
4809 * Gen2 reports pipe underruns whenever all planes are disabled.
4810 * So diasble underrun reporting before all the planes get disabled.
4811 * FIXME: Need to fix the logic to work when we turn off all planes
4812 * but leave the pipe running.
4813 */
4814 if (IS_GEN2(dev))
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4816
4817 /*
4818 * Vblank time updates from the shadow to live plane control register
4819 * are blocked if the memory self-refresh mode is active at that
4820 * moment. So to make sure the plane gets truly disabled, disable
4821 * first the self-refresh mode. The self-refresh enable bit in turn
4822 * will be checked/applied by the HW only at the next frame start
4823 * event which is after the vblank start event, so we need to have a
4824 * wait-for-vblank between disabling the plane and the pipe.
4825 */
4826 if (HAS_GMCH_DISPLAY(dev))
4827 intel_set_memory_cxsr(dev_priv, false);
4828
4829 mutex_lock(&dev->struct_mutex);
4830 if (dev_priv->fbc.crtc == intel_crtc)
4831 intel_fbc_disable(dev);
4832 mutex_unlock(&dev->struct_mutex);
4833
4834 /*
4835 * FIXME IPS should be fine as long as one plane is
4836 * enabled, but in practice it seems to have problems
4837 * when going from primary only to sprite only and vice
4838 * versa.
4839 */
4840 hsw_disable_ips(intel_crtc);
4841 }
4842
4843 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4844 {
4845 intel_enable_primary_hw_plane(crtc->primary, crtc);
4846 intel_enable_sprite_planes(crtc);
4847 intel_crtc_update_cursor(crtc, true);
4848
4849 intel_post_enable_primary(crtc);
4850 }
4851
4852 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4853 {
4854 struct drm_device *dev = crtc->dev;
4855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 struct intel_plane *intel_plane;
4857 int pipe = intel_crtc->pipe;
4858
4859 intel_crtc_wait_for_pending_flips(crtc);
4860
4861 intel_pre_disable_primary(crtc);
4862
4863 intel_crtc_dpms_overlay_disable(intel_crtc);
4864 for_each_intel_plane(dev, intel_plane) {
4865 if (intel_plane->pipe == pipe) {
4866 struct drm_crtc *from = intel_plane->base.crtc;
4867
4868 intel_plane->disable_plane(&intel_plane->base,
4869 from ?: crtc, true);
4870 }
4871 }
4872
4873 /*
4874 * FIXME: Once we grow proper nuclear flip support out of this we need
4875 * to compute the mask of flip planes precisely. For the time being
4876 * consider this a flip to a NULL plane.
4877 */
4878 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4879 }
4880
4881 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4882 {
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4886 struct intel_encoder *encoder;
4887 int pipe = intel_crtc->pipe;
4888
4889 WARN_ON(!crtc->state->enable);
4890
4891 if (intel_crtc->active)
4892 return;
4893
4894 if (intel_crtc->config->has_pch_encoder)
4895 intel_prepare_shared_dpll(intel_crtc);
4896
4897 if (intel_crtc->config->has_dp_encoder)
4898 intel_dp_set_m_n(intel_crtc, M1_N1);
4899
4900 intel_set_pipe_timings(intel_crtc);
4901
4902 if (intel_crtc->config->has_pch_encoder) {
4903 intel_cpu_transcoder_set_m_n(intel_crtc,
4904 &intel_crtc->config->fdi_m_n, NULL);
4905 }
4906
4907 ironlake_set_pipeconf(crtc);
4908
4909 intel_crtc->active = true;
4910
4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4912 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4913
4914 for_each_encoder_on_crtc(dev, crtc, encoder)
4915 if (encoder->pre_enable)
4916 encoder->pre_enable(encoder);
4917
4918 if (intel_crtc->config->has_pch_encoder) {
4919 /* Note: FDI PLL enabling _must_ be done before we enable the
4920 * cpu pipes, hence this is separate from all the other fdi/pch
4921 * enabling. */
4922 ironlake_fdi_pll_enable(intel_crtc);
4923 } else {
4924 assert_fdi_tx_disabled(dev_priv, pipe);
4925 assert_fdi_rx_disabled(dev_priv, pipe);
4926 }
4927
4928 ironlake_pfit_enable(intel_crtc);
4929
4930 /*
4931 * On ILK+ LUT must be loaded before the pipe is running but with
4932 * clocks enabled
4933 */
4934 intel_crtc_load_lut(crtc);
4935
4936 intel_update_watermarks(crtc);
4937 intel_enable_pipe(intel_crtc);
4938
4939 if (intel_crtc->config->has_pch_encoder)
4940 ironlake_pch_enable(crtc);
4941
4942 assert_vblank_disabled(crtc);
4943 drm_crtc_vblank_on(crtc);
4944
4945 for_each_encoder_on_crtc(dev, crtc, encoder)
4946 encoder->enable(encoder);
4947
4948 if (HAS_PCH_CPT(dev))
4949 cpt_verify_modeset(dev, intel_crtc->pipe);
4950 }
4951
4952 /* IPS only exists on ULT machines and is tied to pipe A. */
4953 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954 {
4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4956 }
4957
4958 /*
4959 * This implements the workaround described in the "notes" section of the mode
4960 * set sequence documentation. When going from no pipes or single pipe to
4961 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4962 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4963 */
4964 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4965 {
4966 struct drm_device *dev = crtc->base.dev;
4967 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4968
4969 /* We want to get the other_active_crtc only if there's only 1 other
4970 * active crtc. */
4971 for_each_intel_crtc(dev, crtc_it) {
4972 if (!crtc_it->active || crtc_it == crtc)
4973 continue;
4974
4975 if (other_active_crtc)
4976 return;
4977
4978 other_active_crtc = crtc_it;
4979 }
4980 if (!other_active_crtc)
4981 return;
4982
4983 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4984 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985 }
4986
4987 static void haswell_crtc_enable(struct drm_crtc *crtc)
4988 {
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992 struct intel_encoder *encoder;
4993 int pipe = intel_crtc->pipe;
4994
4995 WARN_ON(!crtc->state->enable);
4996
4997 if (intel_crtc->active)
4998 return;
4999
5000 if (intel_crtc_to_shared_dpll(intel_crtc))
5001 intel_enable_shared_dpll(intel_crtc);
5002
5003 if (intel_crtc->config->has_dp_encoder)
5004 intel_dp_set_m_n(intel_crtc, M1_N1);
5005
5006 intel_set_pipe_timings(intel_crtc);
5007
5008 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5009 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5010 intel_crtc->config->pixel_multiplier - 1);
5011 }
5012
5013 if (intel_crtc->config->has_pch_encoder) {
5014 intel_cpu_transcoder_set_m_n(intel_crtc,
5015 &intel_crtc->config->fdi_m_n, NULL);
5016 }
5017
5018 haswell_set_pipeconf(crtc);
5019
5020 intel_set_pipe_csc(crtc);
5021
5022 intel_crtc->active = true;
5023
5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->pre_enable)
5027 encoder->pre_enable(encoder);
5028
5029 if (intel_crtc->config->has_pch_encoder) {
5030 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5031 true);
5032 dev_priv->display.fdi_link_train(crtc);
5033 }
5034
5035 intel_ddi_enable_pipe_clock(intel_crtc);
5036
5037 if (INTEL_INFO(dev)->gen == 9)
5038 skylake_pfit_update(intel_crtc, 1);
5039 else if (INTEL_INFO(dev)->gen < 9)
5040 ironlake_pfit_enable(intel_crtc);
5041 else
5042 MISSING_CASE(INTEL_INFO(dev)->gen);
5043
5044 /*
5045 * On ILK+ LUT must be loaded before the pipe is running but with
5046 * clocks enabled
5047 */
5048 intel_crtc_load_lut(crtc);
5049
5050 intel_ddi_set_pipe_settings(crtc);
5051 intel_ddi_enable_transcoder_func(crtc);
5052
5053 intel_update_watermarks(crtc);
5054 intel_enable_pipe(intel_crtc);
5055
5056 if (intel_crtc->config->has_pch_encoder)
5057 lpt_pch_enable(crtc);
5058
5059 if (intel_crtc->config->dp_encoder_is_mst)
5060 intel_ddi_set_vc_payload_alloc(crtc, true);
5061
5062 assert_vblank_disabled(crtc);
5063 drm_crtc_vblank_on(crtc);
5064
5065 for_each_encoder_on_crtc(dev, crtc, encoder) {
5066 encoder->enable(encoder);
5067 intel_opregion_notify_encoder(encoder, true);
5068 }
5069
5070 /* If we change the relative order between pipe/planes enabling, we need
5071 * to change the workaround. */
5072 haswell_mode_set_planes_workaround(intel_crtc);
5073 }
5074
5075 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5076 {
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 int pipe = crtc->pipe;
5080
5081 /* To avoid upsetting the power well on haswell only disable the pfit if
5082 * it's in use. The hw state code will make sure we get this right. */
5083 if (crtc->config->pch_pfit.enabled) {
5084 I915_WRITE(PF_CTL(pipe), 0);
5085 I915_WRITE(PF_WIN_POS(pipe), 0);
5086 I915_WRITE(PF_WIN_SZ(pipe), 0);
5087 }
5088 }
5089
5090 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5091 {
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5095 struct intel_encoder *encoder;
5096 int pipe = intel_crtc->pipe;
5097 u32 reg, temp;
5098
5099 if (!intel_crtc->active)
5100 return;
5101
5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 encoder->disable(encoder);
5104
5105 drm_crtc_vblank_off(crtc);
5106 assert_vblank_disabled(crtc);
5107
5108 if (intel_crtc->config->has_pch_encoder)
5109 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5110
5111 intel_disable_pipe(intel_crtc);
5112
5113 ironlake_pfit_disable(intel_crtc);
5114
5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
5118
5119 if (intel_crtc->config->has_pch_encoder) {
5120 ironlake_fdi_disable(crtc);
5121
5122 ironlake_disable_pch_transcoder(dev_priv, pipe);
5123
5124 if (HAS_PCH_CPT(dev)) {
5125 /* disable TRANS_DP_CTL */
5126 reg = TRANS_DP_CTL(pipe);
5127 temp = I915_READ(reg);
5128 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5129 TRANS_DP_PORT_SEL_MASK);
5130 temp |= TRANS_DP_PORT_SEL_NONE;
5131 I915_WRITE(reg, temp);
5132
5133 /* disable DPLL_SEL */
5134 temp = I915_READ(PCH_DPLL_SEL);
5135 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5136 I915_WRITE(PCH_DPLL_SEL, temp);
5137 }
5138
5139 /* disable PCH DPLL */
5140 intel_disable_shared_dpll(intel_crtc);
5141
5142 ironlake_fdi_pll_disable(intel_crtc);
5143 }
5144
5145 intel_crtc->active = false;
5146 intel_update_watermarks(crtc);
5147
5148 mutex_lock(&dev->struct_mutex);
5149 intel_fbc_update(dev);
5150 mutex_unlock(&dev->struct_mutex);
5151 }
5152
5153 static void haswell_crtc_disable(struct drm_crtc *crtc)
5154 {
5155 struct drm_device *dev = crtc->dev;
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5158 struct intel_encoder *encoder;
5159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5160
5161 if (!intel_crtc->active)
5162 return;
5163
5164 for_each_encoder_on_crtc(dev, crtc, encoder) {
5165 intel_opregion_notify_encoder(encoder, false);
5166 encoder->disable(encoder);
5167 }
5168
5169 drm_crtc_vblank_off(crtc);
5170 assert_vblank_disabled(crtc);
5171
5172 if (intel_crtc->config->has_pch_encoder)
5173 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5174 false);
5175 intel_disable_pipe(intel_crtc);
5176
5177 if (intel_crtc->config->dp_encoder_is_mst)
5178 intel_ddi_set_vc_payload_alloc(crtc, false);
5179
5180 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5181
5182 if (INTEL_INFO(dev)->gen == 9)
5183 skylake_pfit_update(intel_crtc, 0);
5184 else if (INTEL_INFO(dev)->gen < 9)
5185 ironlake_pfit_disable(intel_crtc);
5186 else
5187 MISSING_CASE(INTEL_INFO(dev)->gen);
5188
5189 intel_ddi_disable_pipe_clock(intel_crtc);
5190
5191 if (intel_crtc->config->has_pch_encoder) {
5192 lpt_disable_pch_transcoder(dev_priv);
5193 intel_ddi_fdi_disable(crtc);
5194 }
5195
5196 for_each_encoder_on_crtc(dev, crtc, encoder)
5197 if (encoder->post_disable)
5198 encoder->post_disable(encoder);
5199
5200 intel_crtc->active = false;
5201 intel_update_watermarks(crtc);
5202
5203 mutex_lock(&dev->struct_mutex);
5204 intel_fbc_update(dev);
5205 mutex_unlock(&dev->struct_mutex);
5206
5207 if (intel_crtc_to_shared_dpll(intel_crtc))
5208 intel_disable_shared_dpll(intel_crtc);
5209 }
5210
5211 static void ironlake_crtc_off(struct drm_crtc *crtc)
5212 {
5213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5214 intel_put_shared_dpll(intel_crtc);
5215 }
5216
5217
5218 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5219 {
5220 struct drm_device *dev = crtc->base.dev;
5221 struct drm_i915_private *dev_priv = dev->dev_private;
5222 struct intel_crtc_state *pipe_config = crtc->config;
5223
5224 if (!pipe_config->gmch_pfit.control)
5225 return;
5226
5227 /*
5228 * The panel fitter should only be adjusted whilst the pipe is disabled,
5229 * according to register description and PRM.
5230 */
5231 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5232 assert_pipe_disabled(dev_priv, crtc->pipe);
5233
5234 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5235 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5236
5237 /* Border color in case we don't scale up to the full screen. Black by
5238 * default, change to something else for debugging. */
5239 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5240 }
5241
5242 static enum intel_display_power_domain port_to_power_domain(enum port port)
5243 {
5244 switch (port) {
5245 case PORT_A:
5246 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5247 case PORT_B:
5248 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5249 case PORT_C:
5250 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5251 case PORT_D:
5252 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5253 default:
5254 WARN_ON_ONCE(1);
5255 return POWER_DOMAIN_PORT_OTHER;
5256 }
5257 }
5258
5259 #define for_each_power_domain(domain, mask) \
5260 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5261 if ((1 << (domain)) & (mask))
5262
5263 enum intel_display_power_domain
5264 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5265 {
5266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5268
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5277 return port_to_power_domain(intel_dig_port->port);
5278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
5281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5285 default:
5286 return POWER_DOMAIN_PORT_OTHER;
5287 }
5288 }
5289
5290 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5291 {
5292 struct drm_device *dev = crtc->dev;
5293 struct intel_encoder *intel_encoder;
5294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295 enum pipe pipe = intel_crtc->pipe;
5296 unsigned long mask;
5297 enum transcoder transcoder;
5298
5299 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5300
5301 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5302 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5303 if (intel_crtc->config->pch_pfit.enabled ||
5304 intel_crtc->config->pch_pfit.force_thru)
5305 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5306
5307 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5308 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5309
5310 return mask;
5311 }
5312
5313 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5314 {
5315 struct drm_device *dev = state->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5318 struct intel_crtc *crtc;
5319
5320 /*
5321 * First get all needed power domains, then put all unneeded, to avoid
5322 * any unnecessary toggling of the power wells.
5323 */
5324 for_each_intel_crtc(dev, crtc) {
5325 enum intel_display_power_domain domain;
5326
5327 if (!crtc->base.state->enable)
5328 continue;
5329
5330 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5331
5332 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5333 intel_display_power_get(dev_priv, domain);
5334 }
5335
5336 if (dev_priv->display.modeset_global_resources)
5337 dev_priv->display.modeset_global_resources(state);
5338
5339 for_each_intel_crtc(dev, crtc) {
5340 enum intel_display_power_domain domain;
5341
5342 for_each_power_domain(domain, crtc->enabled_power_domains)
5343 intel_display_power_put(dev_priv, domain);
5344
5345 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5346 }
5347
5348 intel_display_set_init_power(dev_priv, false);
5349 }
5350
5351 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5352 {
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 uint32_t divider;
5355 uint32_t ratio;
5356 uint32_t current_freq;
5357 int ret;
5358
5359 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5360 switch (frequency) {
5361 case 144000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 288000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 384000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5371 ratio = BXT_DE_PLL_RATIO(60);
5372 break;
5373 case 576000:
5374 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375 ratio = BXT_DE_PLL_RATIO(60);
5376 break;
5377 case 624000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5379 ratio = BXT_DE_PLL_RATIO(65);
5380 break;
5381 case 19200:
5382 /*
5383 * Bypass frequency with DE PLL disabled. Init ratio, divider
5384 * to suppress GCC warning.
5385 */
5386 ratio = 0;
5387 divider = 0;
5388 break;
5389 default:
5390 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5391
5392 return;
5393 }
5394
5395 mutex_lock(&dev_priv->rps.hw_lock);
5396 /* Inform power controller of upcoming frequency change */
5397 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 0x80000000);
5399 mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401 if (ret) {
5402 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5403 ret, frequency);
5404 return;
5405 }
5406
5407 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5408 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5409 current_freq = current_freq * 500 + 1000;
5410
5411 /*
5412 * DE PLL has to be disabled when
5413 * - setting to 19.2MHz (bypass, PLL isn't used)
5414 * - before setting to 624MHz (PLL needs toggling)
5415 * - before setting to any frequency from 624MHz (PLL needs toggling)
5416 */
5417 if (frequency == 19200 || frequency == 624000 ||
5418 current_freq == 624000) {
5419 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5420 /* Timeout 200us */
5421 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5422 1))
5423 DRM_ERROR("timout waiting for DE PLL unlock\n");
5424 }
5425
5426 if (frequency != 19200) {
5427 uint32_t val;
5428
5429 val = I915_READ(BXT_DE_PLL_CTL);
5430 val &= ~BXT_DE_PLL_RATIO_MASK;
5431 val |= ratio;
5432 I915_WRITE(BXT_DE_PLL_CTL, val);
5433
5434 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5437 DRM_ERROR("timeout waiting for DE PLL lock\n");
5438
5439 val = I915_READ(CDCLK_CTL);
5440 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5441 val |= divider;
5442 /*
5443 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5444 * enable otherwise.
5445 */
5446 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447 if (frequency >= 500000)
5448 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449
5450 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5451 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5452 val |= (frequency - 1000) / 500;
5453 I915_WRITE(CDCLK_CTL, val);
5454 }
5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5458 DIV_ROUND_UP(frequency, 25000));
5459 mutex_unlock(&dev_priv->rps.hw_lock);
5460
5461 if (ret) {
5462 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5463 ret, frequency);
5464 return;
5465 }
5466
5467 dev_priv->cdclk_freq = frequency;
5468 }
5469
5470 void broxton_init_cdclk(struct drm_device *dev)
5471 {
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 uint32_t val;
5474
5475 /*
5476 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5477 * or else the reset will hang because there is no PCH to respond.
5478 * Move the handshake programming to initialization sequence.
5479 * Previously was left up to BIOS.
5480 */
5481 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5482 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5483 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5484
5485 /* Enable PG1 for cdclk */
5486 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5487
5488 /* check if cd clock is enabled */
5489 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5490 DRM_DEBUG_KMS("Display already initialized\n");
5491 return;
5492 }
5493
5494 /*
5495 * FIXME:
5496 * - The initial CDCLK needs to be read from VBT.
5497 * Need to make this change after VBT has changes for BXT.
5498 * - check if setting the max (or any) cdclk freq is really necessary
5499 * here, it belongs to modeset time
5500 */
5501 broxton_set_cdclk(dev, 624000);
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5504 POSTING_READ(DBUF_CTL);
5505
5506 udelay(10);
5507
5508 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5509 DRM_ERROR("DBuf power enable timeout!\n");
5510 }
5511
5512 void broxton_uninit_cdclk(struct drm_device *dev)
5513 {
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5517 POSTING_READ(DBUF_CTL);
5518
5519 udelay(10);
5520
5521 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5522 DRM_ERROR("DBuf power disable timeout!\n");
5523
5524 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5525 broxton_set_cdclk(dev, 19200);
5526
5527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5528 }
5529
5530 /* returns HPLL frequency in kHz */
5531 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5532 {
5533 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5534
5535 /* Obtain SKU information */
5536 mutex_lock(&dev_priv->dpio_lock);
5537 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5538 CCK_FUSE_HPLL_FREQ_MASK;
5539 mutex_unlock(&dev_priv->dpio_lock);
5540
5541 return vco_freq[hpll_freq] * 1000;
5542 }
5543
5544 static void vlv_update_cdclk(struct drm_device *dev)
5545 {
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547
5548 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5549 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5550 dev_priv->cdclk_freq);
5551
5552 /*
5553 * Program the gmbus_freq based on the cdclk frequency.
5554 * BSpec erroneously claims we should aim for 4MHz, but
5555 * in fact 1MHz is the correct frequency.
5556 */
5557 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5558 }
5559
5560 /* Adjust CDclk dividers to allow high res or save power if possible */
5561 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5562 {
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 u32 val, cmd;
5565
5566 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5567 != dev_priv->cdclk_freq);
5568
5569 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5570 cmd = 2;
5571 else if (cdclk == 266667)
5572 cmd = 1;
5573 else
5574 cmd = 0;
5575
5576 mutex_lock(&dev_priv->rps.hw_lock);
5577 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5578 val &= ~DSPFREQGUAR_MASK;
5579 val |= (cmd << DSPFREQGUAR_SHIFT);
5580 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5581 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5582 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5583 50)) {
5584 DRM_ERROR("timed out waiting for CDclk change\n");
5585 }
5586 mutex_unlock(&dev_priv->rps.hw_lock);
5587
5588 if (cdclk == 400000) {
5589 u32 divider;
5590
5591 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5592
5593 mutex_lock(&dev_priv->dpio_lock);
5594 /* adjust cdclk divider */
5595 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5596 val &= ~DISPLAY_FREQUENCY_VALUES;
5597 val |= divider;
5598 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5599
5600 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5601 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5602 50))
5603 DRM_ERROR("timed out waiting for CDclk change\n");
5604 mutex_unlock(&dev_priv->dpio_lock);
5605 }
5606
5607 mutex_lock(&dev_priv->dpio_lock);
5608 /* adjust self-refresh exit latency value */
5609 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5610 val &= ~0x7f;
5611
5612 /*
5613 * For high bandwidth configs, we set a higher latency in the bunit
5614 * so that the core display fetch happens in time to avoid underruns.
5615 */
5616 if (cdclk == 400000)
5617 val |= 4500 / 250; /* 4.5 usec */
5618 else
5619 val |= 3000 / 250; /* 3.0 usec */
5620 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5621 mutex_unlock(&dev_priv->dpio_lock);
5622
5623 vlv_update_cdclk(dev);
5624 }
5625
5626 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5627 {
5628 struct drm_i915_private *dev_priv = dev->dev_private;
5629 u32 val, cmd;
5630
5631 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5632 != dev_priv->cdclk_freq);
5633
5634 switch (cdclk) {
5635 case 333333:
5636 case 320000:
5637 case 266667:
5638 case 200000:
5639 break;
5640 default:
5641 MISSING_CASE(cdclk);
5642 return;
5643 }
5644
5645 /*
5646 * Specs are full of misinformation, but testing on actual
5647 * hardware has shown that we just need to write the desired
5648 * CCK divider into the Punit register.
5649 */
5650 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5651
5652 mutex_lock(&dev_priv->rps.hw_lock);
5653 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5654 val &= ~DSPFREQGUAR_MASK_CHV;
5655 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5656 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5657 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5658 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5659 50)) {
5660 DRM_ERROR("timed out waiting for CDclk change\n");
5661 }
5662 mutex_unlock(&dev_priv->rps.hw_lock);
5663
5664 vlv_update_cdclk(dev);
5665 }
5666
5667 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5668 int max_pixclk)
5669 {
5670 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5671 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5672
5673 /*
5674 * Really only a few cases to deal with, as only 4 CDclks are supported:
5675 * 200MHz
5676 * 267MHz
5677 * 320/333MHz (depends on HPLL freq)
5678 * 400MHz (VLV only)
5679 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5680 * of the lower bin and adjust if needed.
5681 *
5682 * We seem to get an unstable or solid color picture at 200MHz.
5683 * Not sure what's wrong. For now use 200MHz only when all pipes
5684 * are off.
5685 */
5686 if (!IS_CHERRYVIEW(dev_priv) &&
5687 max_pixclk > freq_320*limit/100)
5688 return 400000;
5689 else if (max_pixclk > 266667*limit/100)
5690 return freq_320;
5691 else if (max_pixclk > 0)
5692 return 266667;
5693 else
5694 return 200000;
5695 }
5696
5697 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5698 int max_pixclk)
5699 {
5700 /*
5701 * FIXME:
5702 * - remove the guardband, it's not needed on BXT
5703 * - set 19.2MHz bypass frequency if there are no active pipes
5704 */
5705 if (max_pixclk > 576000*9/10)
5706 return 624000;
5707 else if (max_pixclk > 384000*9/10)
5708 return 576000;
5709 else if (max_pixclk > 288000*9/10)
5710 return 384000;
5711 else if (max_pixclk > 144000*9/10)
5712 return 288000;
5713 else
5714 return 144000;
5715 }
5716
5717 /* Compute the max pixel clock for new configuration. Uses atomic state if
5718 * that's non-NULL, look at current state otherwise. */
5719 static int intel_mode_max_pixclk(struct drm_device *dev,
5720 struct drm_atomic_state *state)
5721 {
5722 struct intel_crtc *intel_crtc;
5723 struct intel_crtc_state *crtc_state;
5724 int max_pixclk = 0;
5725
5726 for_each_intel_crtc(dev, intel_crtc) {
5727 if (state)
5728 crtc_state =
5729 intel_atomic_get_crtc_state(state, intel_crtc);
5730 else
5731 crtc_state = intel_crtc->config;
5732 if (IS_ERR(crtc_state))
5733 return PTR_ERR(crtc_state);
5734
5735 if (!crtc_state->base.enable)
5736 continue;
5737
5738 max_pixclk = max(max_pixclk,
5739 crtc_state->base.adjusted_mode.crtc_clock);
5740 }
5741
5742 return max_pixclk;
5743 }
5744
5745 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5746 {
5747 struct drm_i915_private *dev_priv = to_i915(state->dev);
5748 struct drm_crtc *crtc;
5749 struct drm_crtc_state *crtc_state;
5750 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5751 int cdclk, i;
5752
5753 if (max_pixclk < 0)
5754 return max_pixclk;
5755
5756 if (IS_VALLEYVIEW(dev_priv))
5757 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5758 else
5759 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5760
5761 if (cdclk == dev_priv->cdclk_freq)
5762 return 0;
5763
5764 /* add all active pipes to the state */
5765 for_each_crtc(state->dev, crtc) {
5766 if (!crtc->state->enable)
5767 continue;
5768
5769 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5770 if (IS_ERR(crtc_state))
5771 return PTR_ERR(crtc_state);
5772 }
5773
5774 /* disable/enable all currently active pipes while we change cdclk */
5775 for_each_crtc_in_state(state, crtc, crtc_state, i)
5776 if (crtc_state->enable)
5777 crtc_state->mode_changed = true;
5778
5779 return 0;
5780 }
5781
5782 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5783 {
5784 unsigned int credits, default_credits;
5785
5786 if (IS_CHERRYVIEW(dev_priv))
5787 default_credits = PFI_CREDIT(12);
5788 else
5789 default_credits = PFI_CREDIT(8);
5790
5791 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5792 /* CHV suggested value is 31 or 63 */
5793 if (IS_CHERRYVIEW(dev_priv))
5794 credits = PFI_CREDIT_31;
5795 else
5796 credits = PFI_CREDIT(15);
5797 } else {
5798 credits = default_credits;
5799 }
5800
5801 /*
5802 * WA - write default credits before re-programming
5803 * FIXME: should we also set the resend bit here?
5804 */
5805 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5806 default_credits);
5807
5808 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5809 credits | PFI_CREDIT_RESEND);
5810
5811 /*
5812 * FIXME is this guaranteed to clear
5813 * immediately or should we poll for it?
5814 */
5815 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5816 }
5817
5818 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5819 {
5820 struct drm_device *dev = old_state->dev;
5821 struct drm_i915_private *dev_priv = dev->dev_private;
5822 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5823 int req_cdclk;
5824
5825 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5826 * never fail. */
5827 if (WARN_ON(max_pixclk < 0))
5828 return;
5829
5830 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5831
5832 if (req_cdclk != dev_priv->cdclk_freq) {
5833 /*
5834 * FIXME: We can end up here with all power domains off, yet
5835 * with a CDCLK frequency other than the minimum. To account
5836 * for this take the PIPE-A power domain, which covers the HW
5837 * blocks needed for the following programming. This can be
5838 * removed once it's guaranteed that we get here either with
5839 * the minimum CDCLK set, or the required power domains
5840 * enabled.
5841 */
5842 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5843
5844 if (IS_CHERRYVIEW(dev))
5845 cherryview_set_cdclk(dev, req_cdclk);
5846 else
5847 valleyview_set_cdclk(dev, req_cdclk);
5848
5849 vlv_program_pfi_credits(dev_priv);
5850
5851 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5852 }
5853 }
5854
5855 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5856 {
5857 struct drm_device *dev = crtc->dev;
5858 struct drm_i915_private *dev_priv = to_i915(dev);
5859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860 struct intel_encoder *encoder;
5861 int pipe = intel_crtc->pipe;
5862 bool is_dsi;
5863
5864 WARN_ON(!crtc->state->enable);
5865
5866 if (intel_crtc->active)
5867 return;
5868
5869 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5870
5871 if (!is_dsi) {
5872 if (IS_CHERRYVIEW(dev))
5873 chv_prepare_pll(intel_crtc, intel_crtc->config);
5874 else
5875 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5876 }
5877
5878 if (intel_crtc->config->has_dp_encoder)
5879 intel_dp_set_m_n(intel_crtc, M1_N1);
5880
5881 intel_set_pipe_timings(intel_crtc);
5882
5883 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885
5886 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5887 I915_WRITE(CHV_CANVAS(pipe), 0);
5888 }
5889
5890 i9xx_set_pipeconf(intel_crtc);
5891
5892 intel_crtc->active = true;
5893
5894 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5895
5896 for_each_encoder_on_crtc(dev, crtc, encoder)
5897 if (encoder->pre_pll_enable)
5898 encoder->pre_pll_enable(encoder);
5899
5900 if (!is_dsi) {
5901 if (IS_CHERRYVIEW(dev))
5902 chv_enable_pll(intel_crtc, intel_crtc->config);
5903 else
5904 vlv_enable_pll(intel_crtc, intel_crtc->config);
5905 }
5906
5907 for_each_encoder_on_crtc(dev, crtc, encoder)
5908 if (encoder->pre_enable)
5909 encoder->pre_enable(encoder);
5910
5911 i9xx_pfit_enable(intel_crtc);
5912
5913 intel_crtc_load_lut(crtc);
5914
5915 intel_update_watermarks(crtc);
5916 intel_enable_pipe(intel_crtc);
5917
5918 assert_vblank_disabled(crtc);
5919 drm_crtc_vblank_on(crtc);
5920
5921 for_each_encoder_on_crtc(dev, crtc, encoder)
5922 encoder->enable(encoder);
5923 }
5924
5925 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5926 {
5927 struct drm_device *dev = crtc->base.dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929
5930 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5931 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5932 }
5933
5934 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5935 {
5936 struct drm_device *dev = crtc->dev;
5937 struct drm_i915_private *dev_priv = to_i915(dev);
5938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5939 struct intel_encoder *encoder;
5940 int pipe = intel_crtc->pipe;
5941
5942 WARN_ON(!crtc->state->enable);
5943
5944 if (intel_crtc->active)
5945 return;
5946
5947 i9xx_set_pll_dividers(intel_crtc);
5948
5949 if (intel_crtc->config->has_dp_encoder)
5950 intel_dp_set_m_n(intel_crtc, M1_N1);
5951
5952 intel_set_pipe_timings(intel_crtc);
5953
5954 i9xx_set_pipeconf(intel_crtc);
5955
5956 intel_crtc->active = true;
5957
5958 if (!IS_GEN2(dev))
5959 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5960
5961 for_each_encoder_on_crtc(dev, crtc, encoder)
5962 if (encoder->pre_enable)
5963 encoder->pre_enable(encoder);
5964
5965 i9xx_enable_pll(intel_crtc);
5966
5967 i9xx_pfit_enable(intel_crtc);
5968
5969 intel_crtc_load_lut(crtc);
5970
5971 intel_update_watermarks(crtc);
5972 intel_enable_pipe(intel_crtc);
5973
5974 assert_vblank_disabled(crtc);
5975 drm_crtc_vblank_on(crtc);
5976
5977 for_each_encoder_on_crtc(dev, crtc, encoder)
5978 encoder->enable(encoder);
5979 }
5980
5981 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5982 {
5983 struct drm_device *dev = crtc->base.dev;
5984 struct drm_i915_private *dev_priv = dev->dev_private;
5985
5986 if (!crtc->config->gmch_pfit.control)
5987 return;
5988
5989 assert_pipe_disabled(dev_priv, crtc->pipe);
5990
5991 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5992 I915_READ(PFIT_CONTROL));
5993 I915_WRITE(PFIT_CONTROL, 0);
5994 }
5995
5996 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5997 {
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 struct intel_encoder *encoder;
6002 int pipe = intel_crtc->pipe;
6003
6004 if (!intel_crtc->active)
6005 return;
6006
6007 /*
6008 * On gen2 planes are double buffered but the pipe isn't, so we must
6009 * wait for planes to fully turn off before disabling the pipe.
6010 * We also need to wait on all gmch platforms because of the
6011 * self-refresh mode constraint explained above.
6012 */
6013 intel_wait_for_vblank(dev, pipe);
6014
6015 for_each_encoder_on_crtc(dev, crtc, encoder)
6016 encoder->disable(encoder);
6017
6018 drm_crtc_vblank_off(crtc);
6019 assert_vblank_disabled(crtc);
6020
6021 intel_disable_pipe(intel_crtc);
6022
6023 i9xx_pfit_disable(intel_crtc);
6024
6025 for_each_encoder_on_crtc(dev, crtc, encoder)
6026 if (encoder->post_disable)
6027 encoder->post_disable(encoder);
6028
6029 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6030 if (IS_CHERRYVIEW(dev))
6031 chv_disable_pll(dev_priv, pipe);
6032 else if (IS_VALLEYVIEW(dev))
6033 vlv_disable_pll(dev_priv, pipe);
6034 else
6035 i9xx_disable_pll(intel_crtc);
6036 }
6037
6038 if (!IS_GEN2(dev))
6039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6040
6041 intel_crtc->active = false;
6042 intel_update_watermarks(crtc);
6043
6044 mutex_lock(&dev->struct_mutex);
6045 intel_fbc_update(dev);
6046 mutex_unlock(&dev->struct_mutex);
6047 }
6048
6049 static void i9xx_crtc_off(struct drm_crtc *crtc)
6050 {
6051 }
6052
6053 /* Master function to enable/disable CRTC and corresponding power wells */
6054 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6055 {
6056 struct drm_device *dev = crtc->dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6059 enum intel_display_power_domain domain;
6060 unsigned long domains;
6061
6062 if (enable) {
6063 if (!intel_crtc->active) {
6064 domains = get_crtc_power_domains(crtc);
6065 for_each_power_domain(domain, domains)
6066 intel_display_power_get(dev_priv, domain);
6067 intel_crtc->enabled_power_domains = domains;
6068
6069 dev_priv->display.crtc_enable(crtc);
6070 intel_crtc_enable_planes(crtc);
6071 }
6072 } else {
6073 if (intel_crtc->active) {
6074 intel_crtc_disable_planes(crtc);
6075 dev_priv->display.crtc_disable(crtc);
6076
6077 domains = intel_crtc->enabled_power_domains;
6078 for_each_power_domain(domain, domains)
6079 intel_display_power_put(dev_priv, domain);
6080 intel_crtc->enabled_power_domains = 0;
6081 }
6082 }
6083 }
6084
6085 /**
6086 * Sets the power management mode of the pipe and plane.
6087 */
6088 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6089 {
6090 struct drm_device *dev = crtc->dev;
6091 struct intel_encoder *intel_encoder;
6092 bool enable = false;
6093
6094 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6095 enable |= intel_encoder->connectors_active;
6096
6097 intel_crtc_control(crtc, enable);
6098
6099 crtc->state->active = enable;
6100 }
6101
6102 static void intel_crtc_disable(struct drm_crtc *crtc)
6103 {
6104 struct drm_device *dev = crtc->dev;
6105 struct drm_connector *connector;
6106 struct drm_i915_private *dev_priv = dev->dev_private;
6107
6108 /* crtc should still be enabled when we disable it. */
6109 WARN_ON(!crtc->state->enable);
6110
6111 intel_crtc_disable_planes(crtc);
6112 dev_priv->display.crtc_disable(crtc);
6113 dev_priv->display.off(crtc);
6114
6115 drm_plane_helper_disable(crtc->primary);
6116
6117 /* Update computed state. */
6118 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6119 if (!connector->encoder || !connector->encoder->crtc)
6120 continue;
6121
6122 if (connector->encoder->crtc != crtc)
6123 continue;
6124
6125 connector->dpms = DRM_MODE_DPMS_OFF;
6126 to_intel_encoder(connector->encoder)->connectors_active = false;
6127 }
6128 }
6129
6130 void intel_encoder_destroy(struct drm_encoder *encoder)
6131 {
6132 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6133
6134 drm_encoder_cleanup(encoder);
6135 kfree(intel_encoder);
6136 }
6137
6138 /* Simple dpms helper for encoders with just one connector, no cloning and only
6139 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6140 * state of the entire output pipe. */
6141 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6142 {
6143 if (mode == DRM_MODE_DPMS_ON) {
6144 encoder->connectors_active = true;
6145
6146 intel_crtc_update_dpms(encoder->base.crtc);
6147 } else {
6148 encoder->connectors_active = false;
6149
6150 intel_crtc_update_dpms(encoder->base.crtc);
6151 }
6152 }
6153
6154 /* Cross check the actual hw state with our own modeset state tracking (and it's
6155 * internal consistency). */
6156 static void intel_connector_check_state(struct intel_connector *connector)
6157 {
6158 if (connector->get_hw_state(connector)) {
6159 struct intel_encoder *encoder = connector->encoder;
6160 struct drm_crtc *crtc;
6161 bool encoder_enabled;
6162 enum pipe pipe;
6163
6164 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6165 connector->base.base.id,
6166 connector->base.name);
6167
6168 /* there is no real hw state for MST connectors */
6169 if (connector->mst_port)
6170 return;
6171
6172 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6173 "wrong connector dpms state\n");
6174 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6175 "active connector not linked to encoder\n");
6176
6177 if (encoder) {
6178 I915_STATE_WARN(!encoder->connectors_active,
6179 "encoder->connectors_active not set\n");
6180
6181 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6182 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6183 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6184 return;
6185
6186 crtc = encoder->base.crtc;
6187
6188 I915_STATE_WARN(!crtc->state->enable,
6189 "crtc not enabled\n");
6190 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6191 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6192 "encoder active on the wrong pipe\n");
6193 }
6194 }
6195 }
6196
6197 int intel_connector_init(struct intel_connector *connector)
6198 {
6199 struct drm_connector_state *connector_state;
6200
6201 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6202 if (!connector_state)
6203 return -ENOMEM;
6204
6205 connector->base.state = connector_state;
6206 return 0;
6207 }
6208
6209 struct intel_connector *intel_connector_alloc(void)
6210 {
6211 struct intel_connector *connector;
6212
6213 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6214 if (!connector)
6215 return NULL;
6216
6217 if (intel_connector_init(connector) < 0) {
6218 kfree(connector);
6219 return NULL;
6220 }
6221
6222 return connector;
6223 }
6224
6225 /* Even simpler default implementation, if there's really no special case to
6226 * consider. */
6227 void intel_connector_dpms(struct drm_connector *connector, int mode)
6228 {
6229 /* All the simple cases only support two dpms states. */
6230 if (mode != DRM_MODE_DPMS_ON)
6231 mode = DRM_MODE_DPMS_OFF;
6232
6233 if (mode == connector->dpms)
6234 return;
6235
6236 connector->dpms = mode;
6237
6238 /* Only need to change hw state when actually enabled */
6239 if (connector->encoder)
6240 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6241
6242 intel_modeset_check_state(connector->dev);
6243 }
6244
6245 /* Simple connector->get_hw_state implementation for encoders that support only
6246 * one connector and no cloning and hence the encoder state determines the state
6247 * of the connector. */
6248 bool intel_connector_get_hw_state(struct intel_connector *connector)
6249 {
6250 enum pipe pipe = 0;
6251 struct intel_encoder *encoder = connector->encoder;
6252
6253 return encoder->get_hw_state(encoder, &pipe);
6254 }
6255
6256 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6257 {
6258 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6259 return crtc_state->fdi_lanes;
6260
6261 return 0;
6262 }
6263
6264 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6265 struct intel_crtc_state *pipe_config)
6266 {
6267 struct drm_atomic_state *state = pipe_config->base.state;
6268 struct intel_crtc *other_crtc;
6269 struct intel_crtc_state *other_crtc_state;
6270
6271 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6272 pipe_name(pipe), pipe_config->fdi_lanes);
6273 if (pipe_config->fdi_lanes > 4) {
6274 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6275 pipe_name(pipe), pipe_config->fdi_lanes);
6276 return -EINVAL;
6277 }
6278
6279 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6280 if (pipe_config->fdi_lanes > 2) {
6281 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6282 pipe_config->fdi_lanes);
6283 return -EINVAL;
6284 } else {
6285 return 0;
6286 }
6287 }
6288
6289 if (INTEL_INFO(dev)->num_pipes == 2)
6290 return 0;
6291
6292 /* Ivybridge 3 pipe is really complicated */
6293 switch (pipe) {
6294 case PIPE_A:
6295 return 0;
6296 case PIPE_B:
6297 if (pipe_config->fdi_lanes <= 2)
6298 return 0;
6299
6300 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6301 other_crtc_state =
6302 intel_atomic_get_crtc_state(state, other_crtc);
6303 if (IS_ERR(other_crtc_state))
6304 return PTR_ERR(other_crtc_state);
6305
6306 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6307 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6308 pipe_name(pipe), pipe_config->fdi_lanes);
6309 return -EINVAL;
6310 }
6311 return 0;
6312 case PIPE_C:
6313 if (pipe_config->fdi_lanes > 2) {
6314 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6315 pipe_name(pipe), pipe_config->fdi_lanes);
6316 return -EINVAL;
6317 }
6318
6319 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6320 other_crtc_state =
6321 intel_atomic_get_crtc_state(state, other_crtc);
6322 if (IS_ERR(other_crtc_state))
6323 return PTR_ERR(other_crtc_state);
6324
6325 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6326 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6327 return -EINVAL;
6328 }
6329 return 0;
6330 default:
6331 BUG();
6332 }
6333 }
6334
6335 #define RETRY 1
6336 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6337 struct intel_crtc_state *pipe_config)
6338 {
6339 struct drm_device *dev = intel_crtc->base.dev;
6340 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6341 int lane, link_bw, fdi_dotclock, ret;
6342 bool needs_recompute = false;
6343
6344 retry:
6345 /* FDI is a binary signal running at ~2.7GHz, encoding
6346 * each output octet as 10 bits. The actual frequency
6347 * is stored as a divider into a 100MHz clock, and the
6348 * mode pixel clock is stored in units of 1KHz.
6349 * Hence the bw of each lane in terms of the mode signal
6350 * is:
6351 */
6352 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6353
6354 fdi_dotclock = adjusted_mode->crtc_clock;
6355
6356 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6357 pipe_config->pipe_bpp);
6358
6359 pipe_config->fdi_lanes = lane;
6360
6361 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6362 link_bw, &pipe_config->fdi_m_n);
6363
6364 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6365 intel_crtc->pipe, pipe_config);
6366 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6367 pipe_config->pipe_bpp -= 2*3;
6368 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6369 pipe_config->pipe_bpp);
6370 needs_recompute = true;
6371 pipe_config->bw_constrained = true;
6372
6373 goto retry;
6374 }
6375
6376 if (needs_recompute)
6377 return RETRY;
6378
6379 return ret;
6380 }
6381
6382 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6383 struct intel_crtc_state *pipe_config)
6384 {
6385 pipe_config->ips_enabled = i915.enable_ips &&
6386 hsw_crtc_supports_ips(crtc) &&
6387 pipe_config->pipe_bpp <= 24;
6388 }
6389
6390 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6391 struct intel_crtc_state *pipe_config)
6392 {
6393 struct drm_device *dev = crtc->base.dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6396 int ret;
6397
6398 /* FIXME should check pixel clock limits on all platforms */
6399 if (INTEL_INFO(dev)->gen < 4) {
6400 int clock_limit =
6401 dev_priv->display.get_display_clock_speed(dev);
6402
6403 /*
6404 * Enable pixel doubling when the dot clock
6405 * is > 90% of the (display) core speed.
6406 *
6407 * GDG double wide on either pipe,
6408 * otherwise pipe A only.
6409 */
6410 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6411 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6412 clock_limit *= 2;
6413 pipe_config->double_wide = true;
6414 }
6415
6416 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6417 return -EINVAL;
6418 }
6419
6420 /*
6421 * Pipe horizontal size must be even in:
6422 * - DVO ganged mode
6423 * - LVDS dual channel mode
6424 * - Double wide pipe
6425 */
6426 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6427 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6428 pipe_config->pipe_src_w &= ~1;
6429
6430 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6431 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6432 */
6433 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6434 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6435 return -EINVAL;
6436
6437 if (HAS_IPS(dev))
6438 hsw_compute_ips_config(crtc, pipe_config);
6439
6440 if (pipe_config->has_pch_encoder)
6441 return ironlake_fdi_compute_config(crtc, pipe_config);
6442
6443 /* FIXME: remove below call once atomic mode set is place and all crtc
6444 * related checks called from atomic_crtc_check function */
6445 ret = 0;
6446 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6447 crtc, pipe_config->base.state);
6448 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6449
6450 return ret;
6451 }
6452
6453 static int skylake_get_display_clock_speed(struct drm_device *dev)
6454 {
6455 struct drm_i915_private *dev_priv = to_i915(dev);
6456 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6457 uint32_t cdctl = I915_READ(CDCLK_CTL);
6458 uint32_t linkrate;
6459
6460 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6461 WARN(1, "LCPLL1 not enabled\n");
6462 return 24000; /* 24MHz is the cd freq with NSSC ref */
6463 }
6464
6465 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6466 return 540000;
6467
6468 linkrate = (I915_READ(DPLL_CTRL1) &
6469 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6470
6471 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6472 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6473 /* vco 8640 */
6474 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6475 case CDCLK_FREQ_450_432:
6476 return 432000;
6477 case CDCLK_FREQ_337_308:
6478 return 308570;
6479 case CDCLK_FREQ_675_617:
6480 return 617140;
6481 default:
6482 WARN(1, "Unknown cd freq selection\n");
6483 }
6484 } else {
6485 /* vco 8100 */
6486 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6487 case CDCLK_FREQ_450_432:
6488 return 450000;
6489 case CDCLK_FREQ_337_308:
6490 return 337500;
6491 case CDCLK_FREQ_675_617:
6492 return 675000;
6493 default:
6494 WARN(1, "Unknown cd freq selection\n");
6495 }
6496 }
6497
6498 /* error case, do as if DPLL0 isn't enabled */
6499 return 24000;
6500 }
6501
6502 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6503 {
6504 struct drm_i915_private *dev_priv = dev->dev_private;
6505 uint32_t lcpll = I915_READ(LCPLL_CTL);
6506 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6507
6508 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6509 return 800000;
6510 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6511 return 450000;
6512 else if (freq == LCPLL_CLK_FREQ_450)
6513 return 450000;
6514 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6515 return 540000;
6516 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6517 return 337500;
6518 else
6519 return 675000;
6520 }
6521
6522 static int haswell_get_display_clock_speed(struct drm_device *dev)
6523 {
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 uint32_t lcpll = I915_READ(LCPLL_CTL);
6526 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6527
6528 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6529 return 800000;
6530 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6531 return 450000;
6532 else if (freq == LCPLL_CLK_FREQ_450)
6533 return 450000;
6534 else if (IS_HSW_ULT(dev))
6535 return 337500;
6536 else
6537 return 540000;
6538 }
6539
6540 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6541 {
6542 struct drm_i915_private *dev_priv = dev->dev_private;
6543 u32 val;
6544 int divider;
6545
6546 if (dev_priv->hpll_freq == 0)
6547 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6548
6549 mutex_lock(&dev_priv->dpio_lock);
6550 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6551 mutex_unlock(&dev_priv->dpio_lock);
6552
6553 divider = val & DISPLAY_FREQUENCY_VALUES;
6554
6555 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6556 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6557 "cdclk change in progress\n");
6558
6559 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6560 }
6561
6562 static int ilk_get_display_clock_speed(struct drm_device *dev)
6563 {
6564 return 450000;
6565 }
6566
6567 static int i945_get_display_clock_speed(struct drm_device *dev)
6568 {
6569 return 400000;
6570 }
6571
6572 static int i915_get_display_clock_speed(struct drm_device *dev)
6573 {
6574 return 333333;
6575 }
6576
6577 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6578 {
6579 return 200000;
6580 }
6581
6582 static int pnv_get_display_clock_speed(struct drm_device *dev)
6583 {
6584 u16 gcfgc = 0;
6585
6586 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6587
6588 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6589 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6590 return 266667;
6591 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6592 return 333333;
6593 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6594 return 444444;
6595 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6596 return 200000;
6597 default:
6598 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6599 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6600 return 133333;
6601 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6602 return 166667;
6603 }
6604 }
6605
6606 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6607 {
6608 u16 gcfgc = 0;
6609
6610 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6611
6612 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6613 return 133333;
6614 else {
6615 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6616 case GC_DISPLAY_CLOCK_333_MHZ:
6617 return 333333;
6618 default:
6619 case GC_DISPLAY_CLOCK_190_200_MHZ:
6620 return 190000;
6621 }
6622 }
6623 }
6624
6625 static int i865_get_display_clock_speed(struct drm_device *dev)
6626 {
6627 return 266667;
6628 }
6629
6630 static int i855_get_display_clock_speed(struct drm_device *dev)
6631 {
6632 u16 hpllcc = 0;
6633 /* Assume that the hardware is in the high speed state. This
6634 * should be the default.
6635 */
6636 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6637 case GC_CLOCK_133_200:
6638 case GC_CLOCK_100_200:
6639 return 200000;
6640 case GC_CLOCK_166_250:
6641 return 250000;
6642 case GC_CLOCK_100_133:
6643 return 133333;
6644 }
6645
6646 /* Shouldn't happen */
6647 return 0;
6648 }
6649
6650 static int i830_get_display_clock_speed(struct drm_device *dev)
6651 {
6652 return 133333;
6653 }
6654
6655 static void
6656 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6657 {
6658 while (*num > DATA_LINK_M_N_MASK ||
6659 *den > DATA_LINK_M_N_MASK) {
6660 *num >>= 1;
6661 *den >>= 1;
6662 }
6663 }
6664
6665 static void compute_m_n(unsigned int m, unsigned int n,
6666 uint32_t *ret_m, uint32_t *ret_n)
6667 {
6668 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6669 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6670 intel_reduce_m_n_ratio(ret_m, ret_n);
6671 }
6672
6673 void
6674 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6675 int pixel_clock, int link_clock,
6676 struct intel_link_m_n *m_n)
6677 {
6678 m_n->tu = 64;
6679
6680 compute_m_n(bits_per_pixel * pixel_clock,
6681 link_clock * nlanes * 8,
6682 &m_n->gmch_m, &m_n->gmch_n);
6683
6684 compute_m_n(pixel_clock, link_clock,
6685 &m_n->link_m, &m_n->link_n);
6686 }
6687
6688 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6689 {
6690 if (i915.panel_use_ssc >= 0)
6691 return i915.panel_use_ssc != 0;
6692 return dev_priv->vbt.lvds_use_ssc
6693 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6694 }
6695
6696 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6697 int num_connectors)
6698 {
6699 struct drm_device *dev = crtc_state->base.crtc->dev;
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 int refclk;
6702
6703 WARN_ON(!crtc_state->base.state);
6704
6705 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6706 refclk = 100000;
6707 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6708 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6709 refclk = dev_priv->vbt.lvds_ssc_freq;
6710 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6711 } else if (!IS_GEN2(dev)) {
6712 refclk = 96000;
6713 } else {
6714 refclk = 48000;
6715 }
6716
6717 return refclk;
6718 }
6719
6720 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6721 {
6722 return (1 << dpll->n) << 16 | dpll->m2;
6723 }
6724
6725 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6726 {
6727 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6728 }
6729
6730 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6731 struct intel_crtc_state *crtc_state,
6732 intel_clock_t *reduced_clock)
6733 {
6734 struct drm_device *dev = crtc->base.dev;
6735 u32 fp, fp2 = 0;
6736
6737 if (IS_PINEVIEW(dev)) {
6738 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6739 if (reduced_clock)
6740 fp2 = pnv_dpll_compute_fp(reduced_clock);
6741 } else {
6742 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6743 if (reduced_clock)
6744 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6745 }
6746
6747 crtc_state->dpll_hw_state.fp0 = fp;
6748
6749 crtc->lowfreq_avail = false;
6750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6751 reduced_clock) {
6752 crtc_state->dpll_hw_state.fp1 = fp2;
6753 crtc->lowfreq_avail = true;
6754 } else {
6755 crtc_state->dpll_hw_state.fp1 = fp;
6756 }
6757 }
6758
6759 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6760 pipe)
6761 {
6762 u32 reg_val;
6763
6764 /*
6765 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6766 * and set it to a reasonable value instead.
6767 */
6768 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6769 reg_val &= 0xffffff00;
6770 reg_val |= 0x00000030;
6771 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6772
6773 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6774 reg_val &= 0x8cffffff;
6775 reg_val = 0x8c000000;
6776 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6777
6778 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6779 reg_val &= 0xffffff00;
6780 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6781
6782 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6783 reg_val &= 0x00ffffff;
6784 reg_val |= 0xb0000000;
6785 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6786 }
6787
6788 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6789 struct intel_link_m_n *m_n)
6790 {
6791 struct drm_device *dev = crtc->base.dev;
6792 struct drm_i915_private *dev_priv = dev->dev_private;
6793 int pipe = crtc->pipe;
6794
6795 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6796 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6797 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6798 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6799 }
6800
6801 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6802 struct intel_link_m_n *m_n,
6803 struct intel_link_m_n *m2_n2)
6804 {
6805 struct drm_device *dev = crtc->base.dev;
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 int pipe = crtc->pipe;
6808 enum transcoder transcoder = crtc->config->cpu_transcoder;
6809
6810 if (INTEL_INFO(dev)->gen >= 5) {
6811 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6812 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6813 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6814 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6815 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6816 * for gen < 8) and if DRRS is supported (to make sure the
6817 * registers are not unnecessarily accessed).
6818 */
6819 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6820 crtc->config->has_drrs) {
6821 I915_WRITE(PIPE_DATA_M2(transcoder),
6822 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6823 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6824 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6825 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6826 }
6827 } else {
6828 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6829 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6830 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6831 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6832 }
6833 }
6834
6835 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6836 {
6837 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6838
6839 if (m_n == M1_N1) {
6840 dp_m_n = &crtc->config->dp_m_n;
6841 dp_m2_n2 = &crtc->config->dp_m2_n2;
6842 } else if (m_n == M2_N2) {
6843
6844 /*
6845 * M2_N2 registers are not supported. Hence m2_n2 divider value
6846 * needs to be programmed into M1_N1.
6847 */
6848 dp_m_n = &crtc->config->dp_m2_n2;
6849 } else {
6850 DRM_ERROR("Unsupported divider value\n");
6851 return;
6852 }
6853
6854 if (crtc->config->has_pch_encoder)
6855 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6856 else
6857 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6858 }
6859
6860 static void vlv_update_pll(struct intel_crtc *crtc,
6861 struct intel_crtc_state *pipe_config)
6862 {
6863 u32 dpll, dpll_md;
6864
6865 /*
6866 * Enable DPIO clock input. We should never disable the reference
6867 * clock for pipe B, since VGA hotplug / manual detection depends
6868 * on it.
6869 */
6870 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6871 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6872 /* We should never disable this, set it here for state tracking */
6873 if (crtc->pipe == PIPE_B)
6874 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6875 dpll |= DPLL_VCO_ENABLE;
6876 pipe_config->dpll_hw_state.dpll = dpll;
6877
6878 dpll_md = (pipe_config->pixel_multiplier - 1)
6879 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6880 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6881 }
6882
6883 static void vlv_prepare_pll(struct intel_crtc *crtc,
6884 const struct intel_crtc_state *pipe_config)
6885 {
6886 struct drm_device *dev = crtc->base.dev;
6887 struct drm_i915_private *dev_priv = dev->dev_private;
6888 int pipe = crtc->pipe;
6889 u32 mdiv;
6890 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6891 u32 coreclk, reg_val;
6892
6893 mutex_lock(&dev_priv->dpio_lock);
6894
6895 bestn = pipe_config->dpll.n;
6896 bestm1 = pipe_config->dpll.m1;
6897 bestm2 = pipe_config->dpll.m2;
6898 bestp1 = pipe_config->dpll.p1;
6899 bestp2 = pipe_config->dpll.p2;
6900
6901 /* See eDP HDMI DPIO driver vbios notes doc */
6902
6903 /* PLL B needs special handling */
6904 if (pipe == PIPE_B)
6905 vlv_pllb_recal_opamp(dev_priv, pipe);
6906
6907 /* Set up Tx target for periodic Rcomp update */
6908 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6909
6910 /* Disable target IRef on PLL */
6911 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6912 reg_val &= 0x00ffffff;
6913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6914
6915 /* Disable fast lock */
6916 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6917
6918 /* Set idtafcrecal before PLL is enabled */
6919 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6920 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6921 mdiv |= ((bestn << DPIO_N_SHIFT));
6922 mdiv |= (1 << DPIO_K_SHIFT);
6923
6924 /*
6925 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6926 * but we don't support that).
6927 * Note: don't use the DAC post divider as it seems unstable.
6928 */
6929 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6931
6932 mdiv |= DPIO_ENABLE_CALIBRATION;
6933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6934
6935 /* Set HBR and RBR LPF coefficients */
6936 if (pipe_config->port_clock == 162000 ||
6937 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6938 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6940 0x009f0003);
6941 else
6942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6943 0x00d0000f);
6944
6945 if (pipe_config->has_dp_encoder) {
6946 /* Use SSC source */
6947 if (pipe == PIPE_A)
6948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6949 0x0df40000);
6950 else
6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6952 0x0df70000);
6953 } else { /* HDMI or VGA */
6954 /* Use bend source */
6955 if (pipe == PIPE_A)
6956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6957 0x0df70000);
6958 else
6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6960 0x0df40000);
6961 }
6962
6963 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6964 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6965 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6966 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6967 coreclk |= 0x01000000;
6968 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6969
6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6971 mutex_unlock(&dev_priv->dpio_lock);
6972 }
6973
6974 static void chv_update_pll(struct intel_crtc *crtc,
6975 struct intel_crtc_state *pipe_config)
6976 {
6977 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6978 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6979 DPLL_VCO_ENABLE;
6980 if (crtc->pipe != PIPE_A)
6981 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6982
6983 pipe_config->dpll_hw_state.dpll_md =
6984 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6985 }
6986
6987 static void chv_prepare_pll(struct intel_crtc *crtc,
6988 const struct intel_crtc_state *pipe_config)
6989 {
6990 struct drm_device *dev = crtc->base.dev;
6991 struct drm_i915_private *dev_priv = dev->dev_private;
6992 int pipe = crtc->pipe;
6993 int dpll_reg = DPLL(crtc->pipe);
6994 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6995 u32 loopfilter, tribuf_calcntr;
6996 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6997 u32 dpio_val;
6998 int vco;
6999
7000 bestn = pipe_config->dpll.n;
7001 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7002 bestm1 = pipe_config->dpll.m1;
7003 bestm2 = pipe_config->dpll.m2 >> 22;
7004 bestp1 = pipe_config->dpll.p1;
7005 bestp2 = pipe_config->dpll.p2;
7006 vco = pipe_config->dpll.vco;
7007 dpio_val = 0;
7008 loopfilter = 0;
7009
7010 /*
7011 * Enable Refclk and SSC
7012 */
7013 I915_WRITE(dpll_reg,
7014 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7015
7016 mutex_lock(&dev_priv->dpio_lock);
7017
7018 /* p1 and p2 divider */
7019 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7020 5 << DPIO_CHV_S1_DIV_SHIFT |
7021 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7022 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7023 1 << DPIO_CHV_K_DIV_SHIFT);
7024
7025 /* Feedback post-divider - m2 */
7026 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7027
7028 /* Feedback refclk divider - n and m1 */
7029 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7030 DPIO_CHV_M1_DIV_BY_2 |
7031 1 << DPIO_CHV_N_DIV_SHIFT);
7032
7033 /* M2 fraction division */
7034 if (bestm2_frac)
7035 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7036
7037 /* M2 fraction division enable */
7038 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7039 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7040 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7041 if (bestm2_frac)
7042 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7043 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7044
7045 /* Program digital lock detect threshold */
7046 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7047 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7048 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7049 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7050 if (!bestm2_frac)
7051 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7052 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7053
7054 /* Loop filter */
7055 if (vco == 5400000) {
7056 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7057 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7058 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7059 tribuf_calcntr = 0x9;
7060 } else if (vco <= 6200000) {
7061 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7062 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7063 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7064 tribuf_calcntr = 0x9;
7065 } else if (vco <= 6480000) {
7066 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7067 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7068 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7069 tribuf_calcntr = 0x8;
7070 } else {
7071 /* Not supported. Apply the same limits as in the max case */
7072 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0;
7076 }
7077 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7078
7079 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7080 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7081 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7082 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7083
7084 /* AFC Recal */
7085 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7086 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7087 DPIO_AFC_RECAL);
7088
7089 mutex_unlock(&dev_priv->dpio_lock);
7090 }
7091
7092 /**
7093 * vlv_force_pll_on - forcibly enable just the PLL
7094 * @dev_priv: i915 private structure
7095 * @pipe: pipe PLL to enable
7096 * @dpll: PLL configuration
7097 *
7098 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7099 * in cases where we need the PLL enabled even when @pipe is not going to
7100 * be enabled.
7101 */
7102 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7103 const struct dpll *dpll)
7104 {
7105 struct intel_crtc *crtc =
7106 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7107 struct intel_crtc_state pipe_config = {
7108 .base.crtc = &crtc->base,
7109 .pixel_multiplier = 1,
7110 .dpll = *dpll,
7111 };
7112
7113 if (IS_CHERRYVIEW(dev)) {
7114 chv_update_pll(crtc, &pipe_config);
7115 chv_prepare_pll(crtc, &pipe_config);
7116 chv_enable_pll(crtc, &pipe_config);
7117 } else {
7118 vlv_update_pll(crtc, &pipe_config);
7119 vlv_prepare_pll(crtc, &pipe_config);
7120 vlv_enable_pll(crtc, &pipe_config);
7121 }
7122 }
7123
7124 /**
7125 * vlv_force_pll_off - forcibly disable just the PLL
7126 * @dev_priv: i915 private structure
7127 * @pipe: pipe PLL to disable
7128 *
7129 * Disable the PLL for @pipe. To be used in cases where we need
7130 * the PLL enabled even when @pipe is not going to be enabled.
7131 */
7132 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7133 {
7134 if (IS_CHERRYVIEW(dev))
7135 chv_disable_pll(to_i915(dev), pipe);
7136 else
7137 vlv_disable_pll(to_i915(dev), pipe);
7138 }
7139
7140 static void i9xx_update_pll(struct intel_crtc *crtc,
7141 struct intel_crtc_state *crtc_state,
7142 intel_clock_t *reduced_clock,
7143 int num_connectors)
7144 {
7145 struct drm_device *dev = crtc->base.dev;
7146 struct drm_i915_private *dev_priv = dev->dev_private;
7147 u32 dpll;
7148 bool is_sdvo;
7149 struct dpll *clock = &crtc_state->dpll;
7150
7151 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7152
7153 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7154 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7155
7156 dpll = DPLL_VGA_MODE_DIS;
7157
7158 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7159 dpll |= DPLLB_MODE_LVDS;
7160 else
7161 dpll |= DPLLB_MODE_DAC_SERIAL;
7162
7163 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7164 dpll |= (crtc_state->pixel_multiplier - 1)
7165 << SDVO_MULTIPLIER_SHIFT_HIRES;
7166 }
7167
7168 if (is_sdvo)
7169 dpll |= DPLL_SDVO_HIGH_SPEED;
7170
7171 if (crtc_state->has_dp_encoder)
7172 dpll |= DPLL_SDVO_HIGH_SPEED;
7173
7174 /* compute bitmask from p1 value */
7175 if (IS_PINEVIEW(dev))
7176 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7177 else {
7178 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7179 if (IS_G4X(dev) && reduced_clock)
7180 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7181 }
7182 switch (clock->p2) {
7183 case 5:
7184 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7185 break;
7186 case 7:
7187 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7188 break;
7189 case 10:
7190 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7191 break;
7192 case 14:
7193 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7194 break;
7195 }
7196 if (INTEL_INFO(dev)->gen >= 4)
7197 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7198
7199 if (crtc_state->sdvo_tv_clock)
7200 dpll |= PLL_REF_INPUT_TVCLKINBC;
7201 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7202 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7203 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7204 else
7205 dpll |= PLL_REF_INPUT_DREFCLK;
7206
7207 dpll |= DPLL_VCO_ENABLE;
7208 crtc_state->dpll_hw_state.dpll = dpll;
7209
7210 if (INTEL_INFO(dev)->gen >= 4) {
7211 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7212 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7213 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7214 }
7215 }
7216
7217 static void i8xx_update_pll(struct intel_crtc *crtc,
7218 struct intel_crtc_state *crtc_state,
7219 intel_clock_t *reduced_clock,
7220 int num_connectors)
7221 {
7222 struct drm_device *dev = crtc->base.dev;
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 u32 dpll;
7225 struct dpll *clock = &crtc_state->dpll;
7226
7227 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7228
7229 dpll = DPLL_VGA_MODE_DIS;
7230
7231 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7232 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7233 } else {
7234 if (clock->p1 == 2)
7235 dpll |= PLL_P1_DIVIDE_BY_TWO;
7236 else
7237 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7238 if (clock->p2 == 4)
7239 dpll |= PLL_P2_DIVIDE_BY_4;
7240 }
7241
7242 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7243 dpll |= DPLL_DVO_2X_MODE;
7244
7245 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7246 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7248 else
7249 dpll |= PLL_REF_INPUT_DREFCLK;
7250
7251 dpll |= DPLL_VCO_ENABLE;
7252 crtc_state->dpll_hw_state.dpll = dpll;
7253 }
7254
7255 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7256 {
7257 struct drm_device *dev = intel_crtc->base.dev;
7258 struct drm_i915_private *dev_priv = dev->dev_private;
7259 enum pipe pipe = intel_crtc->pipe;
7260 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7261 struct drm_display_mode *adjusted_mode =
7262 &intel_crtc->config->base.adjusted_mode;
7263 uint32_t crtc_vtotal, crtc_vblank_end;
7264 int vsyncshift = 0;
7265
7266 /* We need to be careful not to changed the adjusted mode, for otherwise
7267 * the hw state checker will get angry at the mismatch. */
7268 crtc_vtotal = adjusted_mode->crtc_vtotal;
7269 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7270
7271 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7272 /* the chip adds 2 halflines automatically */
7273 crtc_vtotal -= 1;
7274 crtc_vblank_end -= 1;
7275
7276 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7277 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7278 else
7279 vsyncshift = adjusted_mode->crtc_hsync_start -
7280 adjusted_mode->crtc_htotal / 2;
7281 if (vsyncshift < 0)
7282 vsyncshift += adjusted_mode->crtc_htotal;
7283 }
7284
7285 if (INTEL_INFO(dev)->gen > 3)
7286 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7287
7288 I915_WRITE(HTOTAL(cpu_transcoder),
7289 (adjusted_mode->crtc_hdisplay - 1) |
7290 ((adjusted_mode->crtc_htotal - 1) << 16));
7291 I915_WRITE(HBLANK(cpu_transcoder),
7292 (adjusted_mode->crtc_hblank_start - 1) |
7293 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7294 I915_WRITE(HSYNC(cpu_transcoder),
7295 (adjusted_mode->crtc_hsync_start - 1) |
7296 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7297
7298 I915_WRITE(VTOTAL(cpu_transcoder),
7299 (adjusted_mode->crtc_vdisplay - 1) |
7300 ((crtc_vtotal - 1) << 16));
7301 I915_WRITE(VBLANK(cpu_transcoder),
7302 (adjusted_mode->crtc_vblank_start - 1) |
7303 ((crtc_vblank_end - 1) << 16));
7304 I915_WRITE(VSYNC(cpu_transcoder),
7305 (adjusted_mode->crtc_vsync_start - 1) |
7306 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7307
7308 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7309 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7310 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7311 * bits. */
7312 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7313 (pipe == PIPE_B || pipe == PIPE_C))
7314 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7315
7316 /* pipesrc controls the size that is scaled from, which should
7317 * always be the user's requested size.
7318 */
7319 I915_WRITE(PIPESRC(pipe),
7320 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7321 (intel_crtc->config->pipe_src_h - 1));
7322 }
7323
7324 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7325 struct intel_crtc_state *pipe_config)
7326 {
7327 struct drm_device *dev = crtc->base.dev;
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7330 uint32_t tmp;
7331
7332 tmp = I915_READ(HTOTAL(cpu_transcoder));
7333 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7334 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7335 tmp = I915_READ(HBLANK(cpu_transcoder));
7336 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7337 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7338 tmp = I915_READ(HSYNC(cpu_transcoder));
7339 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7340 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7341
7342 tmp = I915_READ(VTOTAL(cpu_transcoder));
7343 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7344 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7345 tmp = I915_READ(VBLANK(cpu_transcoder));
7346 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7347 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7348 tmp = I915_READ(VSYNC(cpu_transcoder));
7349 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7351
7352 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7353 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7354 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7355 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7356 }
7357
7358 tmp = I915_READ(PIPESRC(crtc->pipe));
7359 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7360 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7361
7362 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7363 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7364 }
7365
7366 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7367 struct intel_crtc_state *pipe_config)
7368 {
7369 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7370 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7371 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7372 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7373
7374 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7375 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7376 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7377 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7378
7379 mode->flags = pipe_config->base.adjusted_mode.flags;
7380
7381 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7382 mode->flags |= pipe_config->base.adjusted_mode.flags;
7383 }
7384
7385 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7386 {
7387 struct drm_device *dev = intel_crtc->base.dev;
7388 struct drm_i915_private *dev_priv = dev->dev_private;
7389 uint32_t pipeconf;
7390
7391 pipeconf = 0;
7392
7393 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7394 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7395 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7396
7397 if (intel_crtc->config->double_wide)
7398 pipeconf |= PIPECONF_DOUBLE_WIDE;
7399
7400 /* only g4x and later have fancy bpc/dither controls */
7401 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7402 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7403 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7404 pipeconf |= PIPECONF_DITHER_EN |
7405 PIPECONF_DITHER_TYPE_SP;
7406
7407 switch (intel_crtc->config->pipe_bpp) {
7408 case 18:
7409 pipeconf |= PIPECONF_6BPC;
7410 break;
7411 case 24:
7412 pipeconf |= PIPECONF_8BPC;
7413 break;
7414 case 30:
7415 pipeconf |= PIPECONF_10BPC;
7416 break;
7417 default:
7418 /* Case prevented by intel_choose_pipe_bpp_dither. */
7419 BUG();
7420 }
7421 }
7422
7423 if (HAS_PIPE_CXSR(dev)) {
7424 if (intel_crtc->lowfreq_avail) {
7425 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7426 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7427 } else {
7428 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7429 }
7430 }
7431
7432 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7433 if (INTEL_INFO(dev)->gen < 4 ||
7434 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7435 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7436 else
7437 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7438 } else
7439 pipeconf |= PIPECONF_PROGRESSIVE;
7440
7441 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7442 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7443
7444 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7445 POSTING_READ(PIPECONF(intel_crtc->pipe));
7446 }
7447
7448 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7449 struct intel_crtc_state *crtc_state)
7450 {
7451 struct drm_device *dev = crtc->base.dev;
7452 struct drm_i915_private *dev_priv = dev->dev_private;
7453 int refclk, num_connectors = 0;
7454 intel_clock_t clock, reduced_clock;
7455 bool ok, has_reduced_clock = false;
7456 bool is_lvds = false, is_dsi = false;
7457 struct intel_encoder *encoder;
7458 const intel_limit_t *limit;
7459 struct drm_atomic_state *state = crtc_state->base.state;
7460 struct drm_connector *connector;
7461 struct drm_connector_state *connector_state;
7462 int i;
7463
7464 memset(&crtc_state->dpll_hw_state, 0,
7465 sizeof(crtc_state->dpll_hw_state));
7466
7467 for_each_connector_in_state(state, connector, connector_state, i) {
7468 if (connector_state->crtc != &crtc->base)
7469 continue;
7470
7471 encoder = to_intel_encoder(connector_state->best_encoder);
7472
7473 switch (encoder->type) {
7474 case INTEL_OUTPUT_LVDS:
7475 is_lvds = true;
7476 break;
7477 case INTEL_OUTPUT_DSI:
7478 is_dsi = true;
7479 break;
7480 default:
7481 break;
7482 }
7483
7484 num_connectors++;
7485 }
7486
7487 if (is_dsi)
7488 return 0;
7489
7490 if (!crtc_state->clock_set) {
7491 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7492
7493 /*
7494 * Returns a set of divisors for the desired target clock with
7495 * the given refclk, or FALSE. The returned values represent
7496 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7497 * 2) / p1 / p2.
7498 */
7499 limit = intel_limit(crtc_state, refclk);
7500 ok = dev_priv->display.find_dpll(limit, crtc_state,
7501 crtc_state->port_clock,
7502 refclk, NULL, &clock);
7503 if (!ok) {
7504 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7505 return -EINVAL;
7506 }
7507
7508 if (is_lvds && dev_priv->lvds_downclock_avail) {
7509 /*
7510 * Ensure we match the reduced clock's P to the target
7511 * clock. If the clocks don't match, we can't switch
7512 * the display clock by using the FP0/FP1. In such case
7513 * we will disable the LVDS downclock feature.
7514 */
7515 has_reduced_clock =
7516 dev_priv->display.find_dpll(limit, crtc_state,
7517 dev_priv->lvds_downclock,
7518 refclk, &clock,
7519 &reduced_clock);
7520 }
7521 /* Compat-code for transition, will disappear. */
7522 crtc_state->dpll.n = clock.n;
7523 crtc_state->dpll.m1 = clock.m1;
7524 crtc_state->dpll.m2 = clock.m2;
7525 crtc_state->dpll.p1 = clock.p1;
7526 crtc_state->dpll.p2 = clock.p2;
7527 }
7528
7529 if (IS_GEN2(dev)) {
7530 i8xx_update_pll(crtc, crtc_state,
7531 has_reduced_clock ? &reduced_clock : NULL,
7532 num_connectors);
7533 } else if (IS_CHERRYVIEW(dev)) {
7534 chv_update_pll(crtc, crtc_state);
7535 } else if (IS_VALLEYVIEW(dev)) {
7536 vlv_update_pll(crtc, crtc_state);
7537 } else {
7538 i9xx_update_pll(crtc, crtc_state,
7539 has_reduced_clock ? &reduced_clock : NULL,
7540 num_connectors);
7541 }
7542
7543 return 0;
7544 }
7545
7546 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7547 struct intel_crtc_state *pipe_config)
7548 {
7549 struct drm_device *dev = crtc->base.dev;
7550 struct drm_i915_private *dev_priv = dev->dev_private;
7551 uint32_t tmp;
7552
7553 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7554 return;
7555
7556 tmp = I915_READ(PFIT_CONTROL);
7557 if (!(tmp & PFIT_ENABLE))
7558 return;
7559
7560 /* Check whether the pfit is attached to our pipe. */
7561 if (INTEL_INFO(dev)->gen < 4) {
7562 if (crtc->pipe != PIPE_B)
7563 return;
7564 } else {
7565 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7566 return;
7567 }
7568
7569 pipe_config->gmch_pfit.control = tmp;
7570 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7571 if (INTEL_INFO(dev)->gen < 5)
7572 pipe_config->gmch_pfit.lvds_border_bits =
7573 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7574 }
7575
7576 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7577 struct intel_crtc_state *pipe_config)
7578 {
7579 struct drm_device *dev = crtc->base.dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 int pipe = pipe_config->cpu_transcoder;
7582 intel_clock_t clock;
7583 u32 mdiv;
7584 int refclk = 100000;
7585
7586 /* In case of MIPI DPLL will not even be used */
7587 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7588 return;
7589
7590 mutex_lock(&dev_priv->dpio_lock);
7591 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7592 mutex_unlock(&dev_priv->dpio_lock);
7593
7594 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7595 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7596 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7597 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7598 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7599
7600 vlv_clock(refclk, &clock);
7601
7602 /* clock.dot is the fast clock */
7603 pipe_config->port_clock = clock.dot / 5;
7604 }
7605
7606 static void
7607 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7608 struct intel_initial_plane_config *plane_config)
7609 {
7610 struct drm_device *dev = crtc->base.dev;
7611 struct drm_i915_private *dev_priv = dev->dev_private;
7612 u32 val, base, offset;
7613 int pipe = crtc->pipe, plane = crtc->plane;
7614 int fourcc, pixel_format;
7615 unsigned int aligned_height;
7616 struct drm_framebuffer *fb;
7617 struct intel_framebuffer *intel_fb;
7618
7619 val = I915_READ(DSPCNTR(plane));
7620 if (!(val & DISPLAY_PLANE_ENABLE))
7621 return;
7622
7623 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7624 if (!intel_fb) {
7625 DRM_DEBUG_KMS("failed to alloc fb\n");
7626 return;
7627 }
7628
7629 fb = &intel_fb->base;
7630
7631 if (INTEL_INFO(dev)->gen >= 4) {
7632 if (val & DISPPLANE_TILED) {
7633 plane_config->tiling = I915_TILING_X;
7634 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7635 }
7636 }
7637
7638 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7639 fourcc = i9xx_format_to_fourcc(pixel_format);
7640 fb->pixel_format = fourcc;
7641 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7642
7643 if (INTEL_INFO(dev)->gen >= 4) {
7644 if (plane_config->tiling)
7645 offset = I915_READ(DSPTILEOFF(plane));
7646 else
7647 offset = I915_READ(DSPLINOFF(plane));
7648 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7649 } else {
7650 base = I915_READ(DSPADDR(plane));
7651 }
7652 plane_config->base = base;
7653
7654 val = I915_READ(PIPESRC(pipe));
7655 fb->width = ((val >> 16) & 0xfff) + 1;
7656 fb->height = ((val >> 0) & 0xfff) + 1;
7657
7658 val = I915_READ(DSPSTRIDE(pipe));
7659 fb->pitches[0] = val & 0xffffffc0;
7660
7661 aligned_height = intel_fb_align_height(dev, fb->height,
7662 fb->pixel_format,
7663 fb->modifier[0]);
7664
7665 plane_config->size = fb->pitches[0] * aligned_height;
7666
7667 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7668 pipe_name(pipe), plane, fb->width, fb->height,
7669 fb->bits_per_pixel, base, fb->pitches[0],
7670 plane_config->size);
7671
7672 plane_config->fb = intel_fb;
7673 }
7674
7675 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7676 struct intel_crtc_state *pipe_config)
7677 {
7678 struct drm_device *dev = crtc->base.dev;
7679 struct drm_i915_private *dev_priv = dev->dev_private;
7680 int pipe = pipe_config->cpu_transcoder;
7681 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7682 intel_clock_t clock;
7683 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7684 int refclk = 100000;
7685
7686 mutex_lock(&dev_priv->dpio_lock);
7687 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7688 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7689 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7690 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7691 mutex_unlock(&dev_priv->dpio_lock);
7692
7693 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7694 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7695 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7696 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7697 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7698
7699 chv_clock(refclk, &clock);
7700
7701 /* clock.dot is the fast clock */
7702 pipe_config->port_clock = clock.dot / 5;
7703 }
7704
7705 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7706 struct intel_crtc_state *pipe_config)
7707 {
7708 struct drm_device *dev = crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 uint32_t tmp;
7711
7712 if (!intel_display_power_is_enabled(dev_priv,
7713 POWER_DOMAIN_PIPE(crtc->pipe)))
7714 return false;
7715
7716 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7717 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7718
7719 tmp = I915_READ(PIPECONF(crtc->pipe));
7720 if (!(tmp & PIPECONF_ENABLE))
7721 return false;
7722
7723 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7724 switch (tmp & PIPECONF_BPC_MASK) {
7725 case PIPECONF_6BPC:
7726 pipe_config->pipe_bpp = 18;
7727 break;
7728 case PIPECONF_8BPC:
7729 pipe_config->pipe_bpp = 24;
7730 break;
7731 case PIPECONF_10BPC:
7732 pipe_config->pipe_bpp = 30;
7733 break;
7734 default:
7735 break;
7736 }
7737 }
7738
7739 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7740 pipe_config->limited_color_range = true;
7741
7742 if (INTEL_INFO(dev)->gen < 4)
7743 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7744
7745 intel_get_pipe_timings(crtc, pipe_config);
7746
7747 i9xx_get_pfit_config(crtc, pipe_config);
7748
7749 if (INTEL_INFO(dev)->gen >= 4) {
7750 tmp = I915_READ(DPLL_MD(crtc->pipe));
7751 pipe_config->pixel_multiplier =
7752 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7753 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7754 pipe_config->dpll_hw_state.dpll_md = tmp;
7755 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7756 tmp = I915_READ(DPLL(crtc->pipe));
7757 pipe_config->pixel_multiplier =
7758 ((tmp & SDVO_MULTIPLIER_MASK)
7759 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7760 } else {
7761 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7762 * port and will be fixed up in the encoder->get_config
7763 * function. */
7764 pipe_config->pixel_multiplier = 1;
7765 }
7766 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7767 if (!IS_VALLEYVIEW(dev)) {
7768 /*
7769 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7770 * on 830. Filter it out here so that we don't
7771 * report errors due to that.
7772 */
7773 if (IS_I830(dev))
7774 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7775
7776 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7777 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7778 } else {
7779 /* Mask out read-only status bits. */
7780 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7781 DPLL_PORTC_READY_MASK |
7782 DPLL_PORTB_READY_MASK);
7783 }
7784
7785 if (IS_CHERRYVIEW(dev))
7786 chv_crtc_clock_get(crtc, pipe_config);
7787 else if (IS_VALLEYVIEW(dev))
7788 vlv_crtc_clock_get(crtc, pipe_config);
7789 else
7790 i9xx_crtc_clock_get(crtc, pipe_config);
7791
7792 return true;
7793 }
7794
7795 static void ironlake_init_pch_refclk(struct drm_device *dev)
7796 {
7797 struct drm_i915_private *dev_priv = dev->dev_private;
7798 struct intel_encoder *encoder;
7799 u32 val, final;
7800 bool has_lvds = false;
7801 bool has_cpu_edp = false;
7802 bool has_panel = false;
7803 bool has_ck505 = false;
7804 bool can_ssc = false;
7805
7806 /* We need to take the global config into account */
7807 for_each_intel_encoder(dev, encoder) {
7808 switch (encoder->type) {
7809 case INTEL_OUTPUT_LVDS:
7810 has_panel = true;
7811 has_lvds = true;
7812 break;
7813 case INTEL_OUTPUT_EDP:
7814 has_panel = true;
7815 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7816 has_cpu_edp = true;
7817 break;
7818 default:
7819 break;
7820 }
7821 }
7822
7823 if (HAS_PCH_IBX(dev)) {
7824 has_ck505 = dev_priv->vbt.display_clock_mode;
7825 can_ssc = has_ck505;
7826 } else {
7827 has_ck505 = false;
7828 can_ssc = true;
7829 }
7830
7831 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7832 has_panel, has_lvds, has_ck505);
7833
7834 /* Ironlake: try to setup display ref clock before DPLL
7835 * enabling. This is only under driver's control after
7836 * PCH B stepping, previous chipset stepping should be
7837 * ignoring this setting.
7838 */
7839 val = I915_READ(PCH_DREF_CONTROL);
7840
7841 /* As we must carefully and slowly disable/enable each source in turn,
7842 * compute the final state we want first and check if we need to
7843 * make any changes at all.
7844 */
7845 final = val;
7846 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7847 if (has_ck505)
7848 final |= DREF_NONSPREAD_CK505_ENABLE;
7849 else
7850 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7851
7852 final &= ~DREF_SSC_SOURCE_MASK;
7853 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7854 final &= ~DREF_SSC1_ENABLE;
7855
7856 if (has_panel) {
7857 final |= DREF_SSC_SOURCE_ENABLE;
7858
7859 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7860 final |= DREF_SSC1_ENABLE;
7861
7862 if (has_cpu_edp) {
7863 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7864 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7865 else
7866 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7867 } else
7868 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7869 } else {
7870 final |= DREF_SSC_SOURCE_DISABLE;
7871 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7872 }
7873
7874 if (final == val)
7875 return;
7876
7877 /* Always enable nonspread source */
7878 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7879
7880 if (has_ck505)
7881 val |= DREF_NONSPREAD_CK505_ENABLE;
7882 else
7883 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7884
7885 if (has_panel) {
7886 val &= ~DREF_SSC_SOURCE_MASK;
7887 val |= DREF_SSC_SOURCE_ENABLE;
7888
7889 /* SSC must be turned on before enabling the CPU output */
7890 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7891 DRM_DEBUG_KMS("Using SSC on panel\n");
7892 val |= DREF_SSC1_ENABLE;
7893 } else
7894 val &= ~DREF_SSC1_ENABLE;
7895
7896 /* Get SSC going before enabling the outputs */
7897 I915_WRITE(PCH_DREF_CONTROL, val);
7898 POSTING_READ(PCH_DREF_CONTROL);
7899 udelay(200);
7900
7901 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7902
7903 /* Enable CPU source on CPU attached eDP */
7904 if (has_cpu_edp) {
7905 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7906 DRM_DEBUG_KMS("Using SSC on eDP\n");
7907 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7908 } else
7909 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7910 } else
7911 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7912
7913 I915_WRITE(PCH_DREF_CONTROL, val);
7914 POSTING_READ(PCH_DREF_CONTROL);
7915 udelay(200);
7916 } else {
7917 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7918
7919 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7920
7921 /* Turn off CPU output */
7922 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7923
7924 I915_WRITE(PCH_DREF_CONTROL, val);
7925 POSTING_READ(PCH_DREF_CONTROL);
7926 udelay(200);
7927
7928 /* Turn off the SSC source */
7929 val &= ~DREF_SSC_SOURCE_MASK;
7930 val |= DREF_SSC_SOURCE_DISABLE;
7931
7932 /* Turn off SSC1 */
7933 val &= ~DREF_SSC1_ENABLE;
7934
7935 I915_WRITE(PCH_DREF_CONTROL, val);
7936 POSTING_READ(PCH_DREF_CONTROL);
7937 udelay(200);
7938 }
7939
7940 BUG_ON(val != final);
7941 }
7942
7943 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7944 {
7945 uint32_t tmp;
7946
7947 tmp = I915_READ(SOUTH_CHICKEN2);
7948 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7949 I915_WRITE(SOUTH_CHICKEN2, tmp);
7950
7951 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7952 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7953 DRM_ERROR("FDI mPHY reset assert timeout\n");
7954
7955 tmp = I915_READ(SOUTH_CHICKEN2);
7956 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7957 I915_WRITE(SOUTH_CHICKEN2, tmp);
7958
7959 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7960 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7961 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7962 }
7963
7964 /* WaMPhyProgramming:hsw */
7965 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7966 {
7967 uint32_t tmp;
7968
7969 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7970 tmp &= ~(0xFF << 24);
7971 tmp |= (0x12 << 24);
7972 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7973
7974 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7975 tmp |= (1 << 11);
7976 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7977
7978 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7979 tmp |= (1 << 11);
7980 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7981
7982 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7983 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7984 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7985
7986 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7987 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7988 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7989
7990 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7991 tmp &= ~(7 << 13);
7992 tmp |= (5 << 13);
7993 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7994
7995 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7996 tmp &= ~(7 << 13);
7997 tmp |= (5 << 13);
7998 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7999
8000 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8001 tmp &= ~0xFF;
8002 tmp |= 0x1C;
8003 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8004
8005 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8006 tmp &= ~0xFF;
8007 tmp |= 0x1C;
8008 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8009
8010 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8011 tmp &= ~(0xFF << 16);
8012 tmp |= (0x1C << 16);
8013 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8014
8015 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8016 tmp &= ~(0xFF << 16);
8017 tmp |= (0x1C << 16);
8018 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8019
8020 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8021 tmp |= (1 << 27);
8022 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8023
8024 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8025 tmp |= (1 << 27);
8026 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8027
8028 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8029 tmp &= ~(0xF << 28);
8030 tmp |= (4 << 28);
8031 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8032
8033 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8034 tmp &= ~(0xF << 28);
8035 tmp |= (4 << 28);
8036 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8037 }
8038
8039 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8040 * Programming" based on the parameters passed:
8041 * - Sequence to enable CLKOUT_DP
8042 * - Sequence to enable CLKOUT_DP without spread
8043 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8044 */
8045 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8046 bool with_fdi)
8047 {
8048 struct drm_i915_private *dev_priv = dev->dev_private;
8049 uint32_t reg, tmp;
8050
8051 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8052 with_spread = true;
8053 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8054 with_fdi, "LP PCH doesn't have FDI\n"))
8055 with_fdi = false;
8056
8057 mutex_lock(&dev_priv->dpio_lock);
8058
8059 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8060 tmp &= ~SBI_SSCCTL_DISABLE;
8061 tmp |= SBI_SSCCTL_PATHALT;
8062 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8063
8064 udelay(24);
8065
8066 if (with_spread) {
8067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8068 tmp &= ~SBI_SSCCTL_PATHALT;
8069 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8070
8071 if (with_fdi) {
8072 lpt_reset_fdi_mphy(dev_priv);
8073 lpt_program_fdi_mphy(dev_priv);
8074 }
8075 }
8076
8077 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8078 SBI_GEN0 : SBI_DBUFF0;
8079 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8080 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8081 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8082
8083 mutex_unlock(&dev_priv->dpio_lock);
8084 }
8085
8086 /* Sequence to disable CLKOUT_DP */
8087 static void lpt_disable_clkout_dp(struct drm_device *dev)
8088 {
8089 struct drm_i915_private *dev_priv = dev->dev_private;
8090 uint32_t reg, tmp;
8091
8092 mutex_lock(&dev_priv->dpio_lock);
8093
8094 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8095 SBI_GEN0 : SBI_DBUFF0;
8096 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8097 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8098 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8099
8100 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8101 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8102 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8103 tmp |= SBI_SSCCTL_PATHALT;
8104 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8105 udelay(32);
8106 }
8107 tmp |= SBI_SSCCTL_DISABLE;
8108 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8109 }
8110
8111 mutex_unlock(&dev_priv->dpio_lock);
8112 }
8113
8114 static void lpt_init_pch_refclk(struct drm_device *dev)
8115 {
8116 struct intel_encoder *encoder;
8117 bool has_vga = false;
8118
8119 for_each_intel_encoder(dev, encoder) {
8120 switch (encoder->type) {
8121 case INTEL_OUTPUT_ANALOG:
8122 has_vga = true;
8123 break;
8124 default:
8125 break;
8126 }
8127 }
8128
8129 if (has_vga)
8130 lpt_enable_clkout_dp(dev, true, true);
8131 else
8132 lpt_disable_clkout_dp(dev);
8133 }
8134
8135 /*
8136 * Initialize reference clocks when the driver loads
8137 */
8138 void intel_init_pch_refclk(struct drm_device *dev)
8139 {
8140 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8141 ironlake_init_pch_refclk(dev);
8142 else if (HAS_PCH_LPT(dev))
8143 lpt_init_pch_refclk(dev);
8144 }
8145
8146 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8147 {
8148 struct drm_device *dev = crtc_state->base.crtc->dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 struct drm_atomic_state *state = crtc_state->base.state;
8151 struct drm_connector *connector;
8152 struct drm_connector_state *connector_state;
8153 struct intel_encoder *encoder;
8154 int num_connectors = 0, i;
8155 bool is_lvds = false;
8156
8157 for_each_connector_in_state(state, connector, connector_state, i) {
8158 if (connector_state->crtc != crtc_state->base.crtc)
8159 continue;
8160
8161 encoder = to_intel_encoder(connector_state->best_encoder);
8162
8163 switch (encoder->type) {
8164 case INTEL_OUTPUT_LVDS:
8165 is_lvds = true;
8166 break;
8167 default:
8168 break;
8169 }
8170 num_connectors++;
8171 }
8172
8173 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8174 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8175 dev_priv->vbt.lvds_ssc_freq);
8176 return dev_priv->vbt.lvds_ssc_freq;
8177 }
8178
8179 return 120000;
8180 }
8181
8182 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8183 {
8184 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8186 int pipe = intel_crtc->pipe;
8187 uint32_t val;
8188
8189 val = 0;
8190
8191 switch (intel_crtc->config->pipe_bpp) {
8192 case 18:
8193 val |= PIPECONF_6BPC;
8194 break;
8195 case 24:
8196 val |= PIPECONF_8BPC;
8197 break;
8198 case 30:
8199 val |= PIPECONF_10BPC;
8200 break;
8201 case 36:
8202 val |= PIPECONF_12BPC;
8203 break;
8204 default:
8205 /* Case prevented by intel_choose_pipe_bpp_dither. */
8206 BUG();
8207 }
8208
8209 if (intel_crtc->config->dither)
8210 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8211
8212 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8213 val |= PIPECONF_INTERLACED_ILK;
8214 else
8215 val |= PIPECONF_PROGRESSIVE;
8216
8217 if (intel_crtc->config->limited_color_range)
8218 val |= PIPECONF_COLOR_RANGE_SELECT;
8219
8220 I915_WRITE(PIPECONF(pipe), val);
8221 POSTING_READ(PIPECONF(pipe));
8222 }
8223
8224 /*
8225 * Set up the pipe CSC unit.
8226 *
8227 * Currently only full range RGB to limited range RGB conversion
8228 * is supported, but eventually this should handle various
8229 * RGB<->YCbCr scenarios as well.
8230 */
8231 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8232 {
8233 struct drm_device *dev = crtc->dev;
8234 struct drm_i915_private *dev_priv = dev->dev_private;
8235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8236 int pipe = intel_crtc->pipe;
8237 uint16_t coeff = 0x7800; /* 1.0 */
8238
8239 /*
8240 * TODO: Check what kind of values actually come out of the pipe
8241 * with these coeff/postoff values and adjust to get the best
8242 * accuracy. Perhaps we even need to take the bpc value into
8243 * consideration.
8244 */
8245
8246 if (intel_crtc->config->limited_color_range)
8247 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8248
8249 /*
8250 * GY/GU and RY/RU should be the other way around according
8251 * to BSpec, but reality doesn't agree. Just set them up in
8252 * a way that results in the correct picture.
8253 */
8254 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8255 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8256
8257 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8258 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8259
8260 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8261 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8262
8263 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8264 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8265 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8266
8267 if (INTEL_INFO(dev)->gen > 6) {
8268 uint16_t postoff = 0;
8269
8270 if (intel_crtc->config->limited_color_range)
8271 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8272
8273 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8274 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8275 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8276
8277 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8278 } else {
8279 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8280
8281 if (intel_crtc->config->limited_color_range)
8282 mode |= CSC_BLACK_SCREEN_OFFSET;
8283
8284 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8285 }
8286 }
8287
8288 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8289 {
8290 struct drm_device *dev = crtc->dev;
8291 struct drm_i915_private *dev_priv = dev->dev_private;
8292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8293 enum pipe pipe = intel_crtc->pipe;
8294 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8295 uint32_t val;
8296
8297 val = 0;
8298
8299 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8300 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8301
8302 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8303 val |= PIPECONF_INTERLACED_ILK;
8304 else
8305 val |= PIPECONF_PROGRESSIVE;
8306
8307 I915_WRITE(PIPECONF(cpu_transcoder), val);
8308 POSTING_READ(PIPECONF(cpu_transcoder));
8309
8310 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8311 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8312
8313 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8314 val = 0;
8315
8316 switch (intel_crtc->config->pipe_bpp) {
8317 case 18:
8318 val |= PIPEMISC_DITHER_6_BPC;
8319 break;
8320 case 24:
8321 val |= PIPEMISC_DITHER_8_BPC;
8322 break;
8323 case 30:
8324 val |= PIPEMISC_DITHER_10_BPC;
8325 break;
8326 case 36:
8327 val |= PIPEMISC_DITHER_12_BPC;
8328 break;
8329 default:
8330 /* Case prevented by pipe_config_set_bpp. */
8331 BUG();
8332 }
8333
8334 if (intel_crtc->config->dither)
8335 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8336
8337 I915_WRITE(PIPEMISC(pipe), val);
8338 }
8339 }
8340
8341 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8342 struct intel_crtc_state *crtc_state,
8343 intel_clock_t *clock,
8344 bool *has_reduced_clock,
8345 intel_clock_t *reduced_clock)
8346 {
8347 struct drm_device *dev = crtc->dev;
8348 struct drm_i915_private *dev_priv = dev->dev_private;
8349 int refclk;
8350 const intel_limit_t *limit;
8351 bool ret, is_lvds = false;
8352
8353 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8354
8355 refclk = ironlake_get_refclk(crtc_state);
8356
8357 /*
8358 * Returns a set of divisors for the desired target clock with the given
8359 * refclk, or FALSE. The returned values represent the clock equation:
8360 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8361 */
8362 limit = intel_limit(crtc_state, refclk);
8363 ret = dev_priv->display.find_dpll(limit, crtc_state,
8364 crtc_state->port_clock,
8365 refclk, NULL, clock);
8366 if (!ret)
8367 return false;
8368
8369 if (is_lvds && dev_priv->lvds_downclock_avail) {
8370 /*
8371 * Ensure we match the reduced clock's P to the target clock.
8372 * If the clocks don't match, we can't switch the display clock
8373 * by using the FP0/FP1. In such case we will disable the LVDS
8374 * downclock feature.
8375 */
8376 *has_reduced_clock =
8377 dev_priv->display.find_dpll(limit, crtc_state,
8378 dev_priv->lvds_downclock,
8379 refclk, clock,
8380 reduced_clock);
8381 }
8382
8383 return true;
8384 }
8385
8386 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8387 {
8388 /*
8389 * Account for spread spectrum to avoid
8390 * oversubscribing the link. Max center spread
8391 * is 2.5%; use 5% for safety's sake.
8392 */
8393 u32 bps = target_clock * bpp * 21 / 20;
8394 return DIV_ROUND_UP(bps, link_bw * 8);
8395 }
8396
8397 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8398 {
8399 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8400 }
8401
8402 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8403 struct intel_crtc_state *crtc_state,
8404 u32 *fp,
8405 intel_clock_t *reduced_clock, u32 *fp2)
8406 {
8407 struct drm_crtc *crtc = &intel_crtc->base;
8408 struct drm_device *dev = crtc->dev;
8409 struct drm_i915_private *dev_priv = dev->dev_private;
8410 struct drm_atomic_state *state = crtc_state->base.state;
8411 struct drm_connector *connector;
8412 struct drm_connector_state *connector_state;
8413 struct intel_encoder *encoder;
8414 uint32_t dpll;
8415 int factor, num_connectors = 0, i;
8416 bool is_lvds = false, is_sdvo = false;
8417
8418 for_each_connector_in_state(state, connector, connector_state, i) {
8419 if (connector_state->crtc != crtc_state->base.crtc)
8420 continue;
8421
8422 encoder = to_intel_encoder(connector_state->best_encoder);
8423
8424 switch (encoder->type) {
8425 case INTEL_OUTPUT_LVDS:
8426 is_lvds = true;
8427 break;
8428 case INTEL_OUTPUT_SDVO:
8429 case INTEL_OUTPUT_HDMI:
8430 is_sdvo = true;
8431 break;
8432 default:
8433 break;
8434 }
8435
8436 num_connectors++;
8437 }
8438
8439 /* Enable autotuning of the PLL clock (if permissible) */
8440 factor = 21;
8441 if (is_lvds) {
8442 if ((intel_panel_use_ssc(dev_priv) &&
8443 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8444 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8445 factor = 25;
8446 } else if (crtc_state->sdvo_tv_clock)
8447 factor = 20;
8448
8449 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8450 *fp |= FP_CB_TUNE;
8451
8452 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8453 *fp2 |= FP_CB_TUNE;
8454
8455 dpll = 0;
8456
8457 if (is_lvds)
8458 dpll |= DPLLB_MODE_LVDS;
8459 else
8460 dpll |= DPLLB_MODE_DAC_SERIAL;
8461
8462 dpll |= (crtc_state->pixel_multiplier - 1)
8463 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8464
8465 if (is_sdvo)
8466 dpll |= DPLL_SDVO_HIGH_SPEED;
8467 if (crtc_state->has_dp_encoder)
8468 dpll |= DPLL_SDVO_HIGH_SPEED;
8469
8470 /* compute bitmask from p1 value */
8471 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8472 /* also FPA1 */
8473 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8474
8475 switch (crtc_state->dpll.p2) {
8476 case 5:
8477 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8478 break;
8479 case 7:
8480 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8481 break;
8482 case 10:
8483 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8484 break;
8485 case 14:
8486 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8487 break;
8488 }
8489
8490 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8491 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8492 else
8493 dpll |= PLL_REF_INPUT_DREFCLK;
8494
8495 return dpll | DPLL_VCO_ENABLE;
8496 }
8497
8498 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8499 struct intel_crtc_state *crtc_state)
8500 {
8501 struct drm_device *dev = crtc->base.dev;
8502 intel_clock_t clock, reduced_clock;
8503 u32 dpll = 0, fp = 0, fp2 = 0;
8504 bool ok, has_reduced_clock = false;
8505 bool is_lvds = false;
8506 struct intel_shared_dpll *pll;
8507
8508 memset(&crtc_state->dpll_hw_state, 0,
8509 sizeof(crtc_state->dpll_hw_state));
8510
8511 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8512
8513 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8514 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8515
8516 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8517 &has_reduced_clock, &reduced_clock);
8518 if (!ok && !crtc_state->clock_set) {
8519 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8520 return -EINVAL;
8521 }
8522 /* Compat-code for transition, will disappear. */
8523 if (!crtc_state->clock_set) {
8524 crtc_state->dpll.n = clock.n;
8525 crtc_state->dpll.m1 = clock.m1;
8526 crtc_state->dpll.m2 = clock.m2;
8527 crtc_state->dpll.p1 = clock.p1;
8528 crtc_state->dpll.p2 = clock.p2;
8529 }
8530
8531 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8532 if (crtc_state->has_pch_encoder) {
8533 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8534 if (has_reduced_clock)
8535 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8536
8537 dpll = ironlake_compute_dpll(crtc, crtc_state,
8538 &fp, &reduced_clock,
8539 has_reduced_clock ? &fp2 : NULL);
8540
8541 crtc_state->dpll_hw_state.dpll = dpll;
8542 crtc_state->dpll_hw_state.fp0 = fp;
8543 if (has_reduced_clock)
8544 crtc_state->dpll_hw_state.fp1 = fp2;
8545 else
8546 crtc_state->dpll_hw_state.fp1 = fp;
8547
8548 pll = intel_get_shared_dpll(crtc, crtc_state);
8549 if (pll == NULL) {
8550 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8551 pipe_name(crtc->pipe));
8552 return -EINVAL;
8553 }
8554 }
8555
8556 if (is_lvds && has_reduced_clock)
8557 crtc->lowfreq_avail = true;
8558 else
8559 crtc->lowfreq_avail = false;
8560
8561 return 0;
8562 }
8563
8564 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8565 struct intel_link_m_n *m_n)
8566 {
8567 struct drm_device *dev = crtc->base.dev;
8568 struct drm_i915_private *dev_priv = dev->dev_private;
8569 enum pipe pipe = crtc->pipe;
8570
8571 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8572 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8573 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8574 & ~TU_SIZE_MASK;
8575 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8576 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8577 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8578 }
8579
8580 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8581 enum transcoder transcoder,
8582 struct intel_link_m_n *m_n,
8583 struct intel_link_m_n *m2_n2)
8584 {
8585 struct drm_device *dev = crtc->base.dev;
8586 struct drm_i915_private *dev_priv = dev->dev_private;
8587 enum pipe pipe = crtc->pipe;
8588
8589 if (INTEL_INFO(dev)->gen >= 5) {
8590 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8591 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8592 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8593 & ~TU_SIZE_MASK;
8594 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8595 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8596 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8597 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8598 * gen < 8) and if DRRS is supported (to make sure the
8599 * registers are not unnecessarily read).
8600 */
8601 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8602 crtc->config->has_drrs) {
8603 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8604 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8605 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8606 & ~TU_SIZE_MASK;
8607 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8608 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8609 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8610 }
8611 } else {
8612 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8613 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8614 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8615 & ~TU_SIZE_MASK;
8616 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8617 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8618 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8619 }
8620 }
8621
8622 void intel_dp_get_m_n(struct intel_crtc *crtc,
8623 struct intel_crtc_state *pipe_config)
8624 {
8625 if (pipe_config->has_pch_encoder)
8626 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8627 else
8628 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8629 &pipe_config->dp_m_n,
8630 &pipe_config->dp_m2_n2);
8631 }
8632
8633 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8634 struct intel_crtc_state *pipe_config)
8635 {
8636 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8637 &pipe_config->fdi_m_n, NULL);
8638 }
8639
8640 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8641 struct intel_crtc_state *pipe_config)
8642 {
8643 struct drm_device *dev = crtc->base.dev;
8644 struct drm_i915_private *dev_priv = dev->dev_private;
8645 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8646 uint32_t ps_ctrl = 0;
8647 int id = -1;
8648 int i;
8649
8650 /* find scaler attached to this pipe */
8651 for (i = 0; i < crtc->num_scalers; i++) {
8652 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8653 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8654 id = i;
8655 pipe_config->pch_pfit.enabled = true;
8656 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8657 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8658 break;
8659 }
8660 }
8661
8662 scaler_state->scaler_id = id;
8663 if (id >= 0) {
8664 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8665 } else {
8666 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8667 }
8668 }
8669
8670 static void
8671 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8672 struct intel_initial_plane_config *plane_config)
8673 {
8674 struct drm_device *dev = crtc->base.dev;
8675 struct drm_i915_private *dev_priv = dev->dev_private;
8676 u32 val, base, offset, stride_mult, tiling;
8677 int pipe = crtc->pipe;
8678 int fourcc, pixel_format;
8679 unsigned int aligned_height;
8680 struct drm_framebuffer *fb;
8681 struct intel_framebuffer *intel_fb;
8682
8683 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8684 if (!intel_fb) {
8685 DRM_DEBUG_KMS("failed to alloc fb\n");
8686 return;
8687 }
8688
8689 fb = &intel_fb->base;
8690
8691 val = I915_READ(PLANE_CTL(pipe, 0));
8692 if (!(val & PLANE_CTL_ENABLE))
8693 goto error;
8694
8695 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8696 fourcc = skl_format_to_fourcc(pixel_format,
8697 val & PLANE_CTL_ORDER_RGBX,
8698 val & PLANE_CTL_ALPHA_MASK);
8699 fb->pixel_format = fourcc;
8700 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8701
8702 tiling = val & PLANE_CTL_TILED_MASK;
8703 switch (tiling) {
8704 case PLANE_CTL_TILED_LINEAR:
8705 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8706 break;
8707 case PLANE_CTL_TILED_X:
8708 plane_config->tiling = I915_TILING_X;
8709 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8710 break;
8711 case PLANE_CTL_TILED_Y:
8712 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8713 break;
8714 case PLANE_CTL_TILED_YF:
8715 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8716 break;
8717 default:
8718 MISSING_CASE(tiling);
8719 goto error;
8720 }
8721
8722 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8723 plane_config->base = base;
8724
8725 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8726
8727 val = I915_READ(PLANE_SIZE(pipe, 0));
8728 fb->height = ((val >> 16) & 0xfff) + 1;
8729 fb->width = ((val >> 0) & 0x1fff) + 1;
8730
8731 val = I915_READ(PLANE_STRIDE(pipe, 0));
8732 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8733 fb->pixel_format);
8734 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8735
8736 aligned_height = intel_fb_align_height(dev, fb->height,
8737 fb->pixel_format,
8738 fb->modifier[0]);
8739
8740 plane_config->size = fb->pitches[0] * aligned_height;
8741
8742 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8743 pipe_name(pipe), fb->width, fb->height,
8744 fb->bits_per_pixel, base, fb->pitches[0],
8745 plane_config->size);
8746
8747 plane_config->fb = intel_fb;
8748 return;
8749
8750 error:
8751 kfree(fb);
8752 }
8753
8754 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8755 struct intel_crtc_state *pipe_config)
8756 {
8757 struct drm_device *dev = crtc->base.dev;
8758 struct drm_i915_private *dev_priv = dev->dev_private;
8759 uint32_t tmp;
8760
8761 tmp = I915_READ(PF_CTL(crtc->pipe));
8762
8763 if (tmp & PF_ENABLE) {
8764 pipe_config->pch_pfit.enabled = true;
8765 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8766 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8767
8768 /* We currently do not free assignements of panel fitters on
8769 * ivb/hsw (since we don't use the higher upscaling modes which
8770 * differentiates them) so just WARN about this case for now. */
8771 if (IS_GEN7(dev)) {
8772 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8773 PF_PIPE_SEL_IVB(crtc->pipe));
8774 }
8775 }
8776 }
8777
8778 static void
8779 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8780 struct intel_initial_plane_config *plane_config)
8781 {
8782 struct drm_device *dev = crtc->base.dev;
8783 struct drm_i915_private *dev_priv = dev->dev_private;
8784 u32 val, base, offset;
8785 int pipe = crtc->pipe;
8786 int fourcc, pixel_format;
8787 unsigned int aligned_height;
8788 struct drm_framebuffer *fb;
8789 struct intel_framebuffer *intel_fb;
8790
8791 val = I915_READ(DSPCNTR(pipe));
8792 if (!(val & DISPLAY_PLANE_ENABLE))
8793 return;
8794
8795 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8796 if (!intel_fb) {
8797 DRM_DEBUG_KMS("failed to alloc fb\n");
8798 return;
8799 }
8800
8801 fb = &intel_fb->base;
8802
8803 if (INTEL_INFO(dev)->gen >= 4) {
8804 if (val & DISPPLANE_TILED) {
8805 plane_config->tiling = I915_TILING_X;
8806 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8807 }
8808 }
8809
8810 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8811 fourcc = i9xx_format_to_fourcc(pixel_format);
8812 fb->pixel_format = fourcc;
8813 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8814
8815 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8816 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8817 offset = I915_READ(DSPOFFSET(pipe));
8818 } else {
8819 if (plane_config->tiling)
8820 offset = I915_READ(DSPTILEOFF(pipe));
8821 else
8822 offset = I915_READ(DSPLINOFF(pipe));
8823 }
8824 plane_config->base = base;
8825
8826 val = I915_READ(PIPESRC(pipe));
8827 fb->width = ((val >> 16) & 0xfff) + 1;
8828 fb->height = ((val >> 0) & 0xfff) + 1;
8829
8830 val = I915_READ(DSPSTRIDE(pipe));
8831 fb->pitches[0] = val & 0xffffffc0;
8832
8833 aligned_height = intel_fb_align_height(dev, fb->height,
8834 fb->pixel_format,
8835 fb->modifier[0]);
8836
8837 plane_config->size = fb->pitches[0] * aligned_height;
8838
8839 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8840 pipe_name(pipe), fb->width, fb->height,
8841 fb->bits_per_pixel, base, fb->pitches[0],
8842 plane_config->size);
8843
8844 plane_config->fb = intel_fb;
8845 }
8846
8847 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8848 struct intel_crtc_state *pipe_config)
8849 {
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8852 uint32_t tmp;
8853
8854 if (!intel_display_power_is_enabled(dev_priv,
8855 POWER_DOMAIN_PIPE(crtc->pipe)))
8856 return false;
8857
8858 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8859 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8860
8861 tmp = I915_READ(PIPECONF(crtc->pipe));
8862 if (!(tmp & PIPECONF_ENABLE))
8863 return false;
8864
8865 switch (tmp & PIPECONF_BPC_MASK) {
8866 case PIPECONF_6BPC:
8867 pipe_config->pipe_bpp = 18;
8868 break;
8869 case PIPECONF_8BPC:
8870 pipe_config->pipe_bpp = 24;
8871 break;
8872 case PIPECONF_10BPC:
8873 pipe_config->pipe_bpp = 30;
8874 break;
8875 case PIPECONF_12BPC:
8876 pipe_config->pipe_bpp = 36;
8877 break;
8878 default:
8879 break;
8880 }
8881
8882 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8883 pipe_config->limited_color_range = true;
8884
8885 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8886 struct intel_shared_dpll *pll;
8887
8888 pipe_config->has_pch_encoder = true;
8889
8890 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8891 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8892 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8893
8894 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8895
8896 if (HAS_PCH_IBX(dev_priv->dev)) {
8897 pipe_config->shared_dpll =
8898 (enum intel_dpll_id) crtc->pipe;
8899 } else {
8900 tmp = I915_READ(PCH_DPLL_SEL);
8901 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8902 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8903 else
8904 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8905 }
8906
8907 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8908
8909 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8910 &pipe_config->dpll_hw_state));
8911
8912 tmp = pipe_config->dpll_hw_state.dpll;
8913 pipe_config->pixel_multiplier =
8914 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8915 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8916
8917 ironlake_pch_clock_get(crtc, pipe_config);
8918 } else {
8919 pipe_config->pixel_multiplier = 1;
8920 }
8921
8922 intel_get_pipe_timings(crtc, pipe_config);
8923
8924 ironlake_get_pfit_config(crtc, pipe_config);
8925
8926 return true;
8927 }
8928
8929 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8930 {
8931 struct drm_device *dev = dev_priv->dev;
8932 struct intel_crtc *crtc;
8933
8934 for_each_intel_crtc(dev, crtc)
8935 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8936 pipe_name(crtc->pipe));
8937
8938 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8939 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8940 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8941 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8942 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8943 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8944 "CPU PWM1 enabled\n");
8945 if (IS_HASWELL(dev))
8946 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8947 "CPU PWM2 enabled\n");
8948 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8949 "PCH PWM1 enabled\n");
8950 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8951 "Utility pin enabled\n");
8952 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8953
8954 /*
8955 * In theory we can still leave IRQs enabled, as long as only the HPD
8956 * interrupts remain enabled. We used to check for that, but since it's
8957 * gen-specific and since we only disable LCPLL after we fully disable
8958 * the interrupts, the check below should be enough.
8959 */
8960 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8961 }
8962
8963 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8964 {
8965 struct drm_device *dev = dev_priv->dev;
8966
8967 if (IS_HASWELL(dev))
8968 return I915_READ(D_COMP_HSW);
8969 else
8970 return I915_READ(D_COMP_BDW);
8971 }
8972
8973 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8974 {
8975 struct drm_device *dev = dev_priv->dev;
8976
8977 if (IS_HASWELL(dev)) {
8978 mutex_lock(&dev_priv->rps.hw_lock);
8979 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8980 val))
8981 DRM_ERROR("Failed to write to D_COMP\n");
8982 mutex_unlock(&dev_priv->rps.hw_lock);
8983 } else {
8984 I915_WRITE(D_COMP_BDW, val);
8985 POSTING_READ(D_COMP_BDW);
8986 }
8987 }
8988
8989 /*
8990 * This function implements pieces of two sequences from BSpec:
8991 * - Sequence for display software to disable LCPLL
8992 * - Sequence for display software to allow package C8+
8993 * The steps implemented here are just the steps that actually touch the LCPLL
8994 * register. Callers should take care of disabling all the display engine
8995 * functions, doing the mode unset, fixing interrupts, etc.
8996 */
8997 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8998 bool switch_to_fclk, bool allow_power_down)
8999 {
9000 uint32_t val;
9001
9002 assert_can_disable_lcpll(dev_priv);
9003
9004 val = I915_READ(LCPLL_CTL);
9005
9006 if (switch_to_fclk) {
9007 val |= LCPLL_CD_SOURCE_FCLK;
9008 I915_WRITE(LCPLL_CTL, val);
9009
9010 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9011 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9012 DRM_ERROR("Switching to FCLK failed\n");
9013
9014 val = I915_READ(LCPLL_CTL);
9015 }
9016
9017 val |= LCPLL_PLL_DISABLE;
9018 I915_WRITE(LCPLL_CTL, val);
9019 POSTING_READ(LCPLL_CTL);
9020
9021 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9022 DRM_ERROR("LCPLL still locked\n");
9023
9024 val = hsw_read_dcomp(dev_priv);
9025 val |= D_COMP_COMP_DISABLE;
9026 hsw_write_dcomp(dev_priv, val);
9027 ndelay(100);
9028
9029 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9030 1))
9031 DRM_ERROR("D_COMP RCOMP still in progress\n");
9032
9033 if (allow_power_down) {
9034 val = I915_READ(LCPLL_CTL);
9035 val |= LCPLL_POWER_DOWN_ALLOW;
9036 I915_WRITE(LCPLL_CTL, val);
9037 POSTING_READ(LCPLL_CTL);
9038 }
9039 }
9040
9041 /*
9042 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9043 * source.
9044 */
9045 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9046 {
9047 uint32_t val;
9048
9049 val = I915_READ(LCPLL_CTL);
9050
9051 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9052 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9053 return;
9054
9055 /*
9056 * Make sure we're not on PC8 state before disabling PC8, otherwise
9057 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9058 */
9059 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9060
9061 if (val & LCPLL_POWER_DOWN_ALLOW) {
9062 val &= ~LCPLL_POWER_DOWN_ALLOW;
9063 I915_WRITE(LCPLL_CTL, val);
9064 POSTING_READ(LCPLL_CTL);
9065 }
9066
9067 val = hsw_read_dcomp(dev_priv);
9068 val |= D_COMP_COMP_FORCE;
9069 val &= ~D_COMP_COMP_DISABLE;
9070 hsw_write_dcomp(dev_priv, val);
9071
9072 val = I915_READ(LCPLL_CTL);
9073 val &= ~LCPLL_PLL_DISABLE;
9074 I915_WRITE(LCPLL_CTL, val);
9075
9076 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9077 DRM_ERROR("LCPLL not locked yet\n");
9078
9079 if (val & LCPLL_CD_SOURCE_FCLK) {
9080 val = I915_READ(LCPLL_CTL);
9081 val &= ~LCPLL_CD_SOURCE_FCLK;
9082 I915_WRITE(LCPLL_CTL, val);
9083
9084 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9085 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9086 DRM_ERROR("Switching back to LCPLL failed\n");
9087 }
9088
9089 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9090 }
9091
9092 /*
9093 * Package states C8 and deeper are really deep PC states that can only be
9094 * reached when all the devices on the system allow it, so even if the graphics
9095 * device allows PC8+, it doesn't mean the system will actually get to these
9096 * states. Our driver only allows PC8+ when going into runtime PM.
9097 *
9098 * The requirements for PC8+ are that all the outputs are disabled, the power
9099 * well is disabled and most interrupts are disabled, and these are also
9100 * requirements for runtime PM. When these conditions are met, we manually do
9101 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9102 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9103 * hang the machine.
9104 *
9105 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9106 * the state of some registers, so when we come back from PC8+ we need to
9107 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9108 * need to take care of the registers kept by RC6. Notice that this happens even
9109 * if we don't put the device in PCI D3 state (which is what currently happens
9110 * because of the runtime PM support).
9111 *
9112 * For more, read "Display Sequences for Package C8" on the hardware
9113 * documentation.
9114 */
9115 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9116 {
9117 struct drm_device *dev = dev_priv->dev;
9118 uint32_t val;
9119
9120 DRM_DEBUG_KMS("Enabling package C8+\n");
9121
9122 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9123 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9124 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9125 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9126 }
9127
9128 lpt_disable_clkout_dp(dev);
9129 hsw_disable_lcpll(dev_priv, true, true);
9130 }
9131
9132 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9133 {
9134 struct drm_device *dev = dev_priv->dev;
9135 uint32_t val;
9136
9137 DRM_DEBUG_KMS("Disabling package C8+\n");
9138
9139 hsw_restore_lcpll(dev_priv);
9140 lpt_init_pch_refclk(dev);
9141
9142 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9143 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9144 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9145 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9146 }
9147
9148 intel_prepare_ddi(dev);
9149 }
9150
9151 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9152 {
9153 struct drm_device *dev = old_state->dev;
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9156 int req_cdclk;
9157
9158 /* see the comment in valleyview_modeset_global_resources */
9159 if (WARN_ON(max_pixclk < 0))
9160 return;
9161
9162 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9163
9164 if (req_cdclk != dev_priv->cdclk_freq)
9165 broxton_set_cdclk(dev, req_cdclk);
9166 }
9167
9168 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9169 struct intel_crtc_state *crtc_state)
9170 {
9171 if (!intel_ddi_pll_select(crtc, crtc_state))
9172 return -EINVAL;
9173
9174 crtc->lowfreq_avail = false;
9175
9176 return 0;
9177 }
9178
9179 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9180 enum port port,
9181 struct intel_crtc_state *pipe_config)
9182 {
9183 switch (port) {
9184 case PORT_A:
9185 pipe_config->ddi_pll_sel = SKL_DPLL0;
9186 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9187 break;
9188 case PORT_B:
9189 pipe_config->ddi_pll_sel = SKL_DPLL1;
9190 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9191 break;
9192 case PORT_C:
9193 pipe_config->ddi_pll_sel = SKL_DPLL2;
9194 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9195 break;
9196 default:
9197 DRM_ERROR("Incorrect port type\n");
9198 }
9199 }
9200
9201 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9202 enum port port,
9203 struct intel_crtc_state *pipe_config)
9204 {
9205 u32 temp, dpll_ctl1;
9206
9207 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9208 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9209
9210 switch (pipe_config->ddi_pll_sel) {
9211 case SKL_DPLL0:
9212 /*
9213 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9214 * of the shared DPLL framework and thus needs to be read out
9215 * separately
9216 */
9217 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9218 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9219 break;
9220 case SKL_DPLL1:
9221 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9222 break;
9223 case SKL_DPLL2:
9224 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9225 break;
9226 case SKL_DPLL3:
9227 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9228 break;
9229 }
9230 }
9231
9232 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9233 enum port port,
9234 struct intel_crtc_state *pipe_config)
9235 {
9236 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9237
9238 switch (pipe_config->ddi_pll_sel) {
9239 case PORT_CLK_SEL_WRPLL1:
9240 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9241 break;
9242 case PORT_CLK_SEL_WRPLL2:
9243 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9244 break;
9245 }
9246 }
9247
9248 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9249 struct intel_crtc_state *pipe_config)
9250 {
9251 struct drm_device *dev = crtc->base.dev;
9252 struct drm_i915_private *dev_priv = dev->dev_private;
9253 struct intel_shared_dpll *pll;
9254 enum port port;
9255 uint32_t tmp;
9256
9257 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9258
9259 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9260
9261 if (IS_SKYLAKE(dev))
9262 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9263 else if (IS_BROXTON(dev))
9264 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9265 else
9266 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9267
9268 if (pipe_config->shared_dpll >= 0) {
9269 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9270
9271 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9272 &pipe_config->dpll_hw_state));
9273 }
9274
9275 /*
9276 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9277 * DDI E. So just check whether this pipe is wired to DDI E and whether
9278 * the PCH transcoder is on.
9279 */
9280 if (INTEL_INFO(dev)->gen < 9 &&
9281 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9282 pipe_config->has_pch_encoder = true;
9283
9284 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9285 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9286 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9287
9288 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9289 }
9290 }
9291
9292 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9293 struct intel_crtc_state *pipe_config)
9294 {
9295 struct drm_device *dev = crtc->base.dev;
9296 struct drm_i915_private *dev_priv = dev->dev_private;
9297 enum intel_display_power_domain pfit_domain;
9298 uint32_t tmp;
9299
9300 if (!intel_display_power_is_enabled(dev_priv,
9301 POWER_DOMAIN_PIPE(crtc->pipe)))
9302 return false;
9303
9304 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9305 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9306
9307 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9308 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9309 enum pipe trans_edp_pipe;
9310 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9311 default:
9312 WARN(1, "unknown pipe linked to edp transcoder\n");
9313 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9314 case TRANS_DDI_EDP_INPUT_A_ON:
9315 trans_edp_pipe = PIPE_A;
9316 break;
9317 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9318 trans_edp_pipe = PIPE_B;
9319 break;
9320 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9321 trans_edp_pipe = PIPE_C;
9322 break;
9323 }
9324
9325 if (trans_edp_pipe == crtc->pipe)
9326 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9327 }
9328
9329 if (!intel_display_power_is_enabled(dev_priv,
9330 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9331 return false;
9332
9333 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9334 if (!(tmp & PIPECONF_ENABLE))
9335 return false;
9336
9337 haswell_get_ddi_port_state(crtc, pipe_config);
9338
9339 intel_get_pipe_timings(crtc, pipe_config);
9340
9341 if (INTEL_INFO(dev)->gen >= 9) {
9342 skl_init_scalers(dev, crtc, pipe_config);
9343 }
9344
9345 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9346
9347 if (INTEL_INFO(dev)->gen >= 9) {
9348 pipe_config->scaler_state.scaler_id = -1;
9349 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9350 }
9351
9352 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9353 if (INTEL_INFO(dev)->gen == 9)
9354 skylake_get_pfit_config(crtc, pipe_config);
9355 else if (INTEL_INFO(dev)->gen < 9)
9356 ironlake_get_pfit_config(crtc, pipe_config);
9357 else
9358 MISSING_CASE(INTEL_INFO(dev)->gen);
9359 }
9360
9361 if (IS_HASWELL(dev))
9362 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9363 (I915_READ(IPS_CTL) & IPS_ENABLE);
9364
9365 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9366 pipe_config->pixel_multiplier =
9367 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9368 } else {
9369 pipe_config->pixel_multiplier = 1;
9370 }
9371
9372 return true;
9373 }
9374
9375 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9376 {
9377 struct drm_device *dev = crtc->dev;
9378 struct drm_i915_private *dev_priv = dev->dev_private;
9379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9380 uint32_t cntl = 0, size = 0;
9381
9382 if (base) {
9383 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9384 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9385 unsigned int stride = roundup_pow_of_two(width) * 4;
9386
9387 switch (stride) {
9388 default:
9389 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9390 width, stride);
9391 stride = 256;
9392 /* fallthrough */
9393 case 256:
9394 case 512:
9395 case 1024:
9396 case 2048:
9397 break;
9398 }
9399
9400 cntl |= CURSOR_ENABLE |
9401 CURSOR_GAMMA_ENABLE |
9402 CURSOR_FORMAT_ARGB |
9403 CURSOR_STRIDE(stride);
9404
9405 size = (height << 12) | width;
9406 }
9407
9408 if (intel_crtc->cursor_cntl != 0 &&
9409 (intel_crtc->cursor_base != base ||
9410 intel_crtc->cursor_size != size ||
9411 intel_crtc->cursor_cntl != cntl)) {
9412 /* On these chipsets we can only modify the base/size/stride
9413 * whilst the cursor is disabled.
9414 */
9415 I915_WRITE(_CURACNTR, 0);
9416 POSTING_READ(_CURACNTR);
9417 intel_crtc->cursor_cntl = 0;
9418 }
9419
9420 if (intel_crtc->cursor_base != base) {
9421 I915_WRITE(_CURABASE, base);
9422 intel_crtc->cursor_base = base;
9423 }
9424
9425 if (intel_crtc->cursor_size != size) {
9426 I915_WRITE(CURSIZE, size);
9427 intel_crtc->cursor_size = size;
9428 }
9429
9430 if (intel_crtc->cursor_cntl != cntl) {
9431 I915_WRITE(_CURACNTR, cntl);
9432 POSTING_READ(_CURACNTR);
9433 intel_crtc->cursor_cntl = cntl;
9434 }
9435 }
9436
9437 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9438 {
9439 struct drm_device *dev = crtc->dev;
9440 struct drm_i915_private *dev_priv = dev->dev_private;
9441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9442 int pipe = intel_crtc->pipe;
9443 uint32_t cntl;
9444
9445 cntl = 0;
9446 if (base) {
9447 cntl = MCURSOR_GAMMA_ENABLE;
9448 switch (intel_crtc->base.cursor->state->crtc_w) {
9449 case 64:
9450 cntl |= CURSOR_MODE_64_ARGB_AX;
9451 break;
9452 case 128:
9453 cntl |= CURSOR_MODE_128_ARGB_AX;
9454 break;
9455 case 256:
9456 cntl |= CURSOR_MODE_256_ARGB_AX;
9457 break;
9458 default:
9459 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9460 return;
9461 }
9462 cntl |= pipe << 28; /* Connect to correct pipe */
9463
9464 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9465 cntl |= CURSOR_PIPE_CSC_ENABLE;
9466 }
9467
9468 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9469 cntl |= CURSOR_ROTATE_180;
9470
9471 if (intel_crtc->cursor_cntl != cntl) {
9472 I915_WRITE(CURCNTR(pipe), cntl);
9473 POSTING_READ(CURCNTR(pipe));
9474 intel_crtc->cursor_cntl = cntl;
9475 }
9476
9477 /* and commit changes on next vblank */
9478 I915_WRITE(CURBASE(pipe), base);
9479 POSTING_READ(CURBASE(pipe));
9480
9481 intel_crtc->cursor_base = base;
9482 }
9483
9484 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9485 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9486 bool on)
9487 {
9488 struct drm_device *dev = crtc->dev;
9489 struct drm_i915_private *dev_priv = dev->dev_private;
9490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9491 int pipe = intel_crtc->pipe;
9492 int x = crtc->cursor_x;
9493 int y = crtc->cursor_y;
9494 u32 base = 0, pos = 0;
9495
9496 if (on)
9497 base = intel_crtc->cursor_addr;
9498
9499 if (x >= intel_crtc->config->pipe_src_w)
9500 base = 0;
9501
9502 if (y >= intel_crtc->config->pipe_src_h)
9503 base = 0;
9504
9505 if (x < 0) {
9506 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9507 base = 0;
9508
9509 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9510 x = -x;
9511 }
9512 pos |= x << CURSOR_X_SHIFT;
9513
9514 if (y < 0) {
9515 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9516 base = 0;
9517
9518 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9519 y = -y;
9520 }
9521 pos |= y << CURSOR_Y_SHIFT;
9522
9523 if (base == 0 && intel_crtc->cursor_base == 0)
9524 return;
9525
9526 I915_WRITE(CURPOS(pipe), pos);
9527
9528 /* ILK+ do this automagically */
9529 if (HAS_GMCH_DISPLAY(dev) &&
9530 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9531 base += (intel_crtc->base.cursor->state->crtc_h *
9532 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9533 }
9534
9535 if (IS_845G(dev) || IS_I865G(dev))
9536 i845_update_cursor(crtc, base);
9537 else
9538 i9xx_update_cursor(crtc, base);
9539 }
9540
9541 static bool cursor_size_ok(struct drm_device *dev,
9542 uint32_t width, uint32_t height)
9543 {
9544 if (width == 0 || height == 0)
9545 return false;
9546
9547 /*
9548 * 845g/865g are special in that they are only limited by
9549 * the width of their cursors, the height is arbitrary up to
9550 * the precision of the register. Everything else requires
9551 * square cursors, limited to a few power-of-two sizes.
9552 */
9553 if (IS_845G(dev) || IS_I865G(dev)) {
9554 if ((width & 63) != 0)
9555 return false;
9556
9557 if (width > (IS_845G(dev) ? 64 : 512))
9558 return false;
9559
9560 if (height > 1023)
9561 return false;
9562 } else {
9563 switch (width | height) {
9564 case 256:
9565 case 128:
9566 if (IS_GEN2(dev))
9567 return false;
9568 case 64:
9569 break;
9570 default:
9571 return false;
9572 }
9573 }
9574
9575 return true;
9576 }
9577
9578 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9579 u16 *blue, uint32_t start, uint32_t size)
9580 {
9581 int end = (start + size > 256) ? 256 : start + size, i;
9582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9583
9584 for (i = start; i < end; i++) {
9585 intel_crtc->lut_r[i] = red[i] >> 8;
9586 intel_crtc->lut_g[i] = green[i] >> 8;
9587 intel_crtc->lut_b[i] = blue[i] >> 8;
9588 }
9589
9590 intel_crtc_load_lut(crtc);
9591 }
9592
9593 /* VESA 640x480x72Hz mode to set on the pipe */
9594 static struct drm_display_mode load_detect_mode = {
9595 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9596 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9597 };
9598
9599 struct drm_framebuffer *
9600 __intel_framebuffer_create(struct drm_device *dev,
9601 struct drm_mode_fb_cmd2 *mode_cmd,
9602 struct drm_i915_gem_object *obj)
9603 {
9604 struct intel_framebuffer *intel_fb;
9605 int ret;
9606
9607 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9608 if (!intel_fb) {
9609 drm_gem_object_unreference(&obj->base);
9610 return ERR_PTR(-ENOMEM);
9611 }
9612
9613 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9614 if (ret)
9615 goto err;
9616
9617 return &intel_fb->base;
9618 err:
9619 drm_gem_object_unreference(&obj->base);
9620 kfree(intel_fb);
9621
9622 return ERR_PTR(ret);
9623 }
9624
9625 static struct drm_framebuffer *
9626 intel_framebuffer_create(struct drm_device *dev,
9627 struct drm_mode_fb_cmd2 *mode_cmd,
9628 struct drm_i915_gem_object *obj)
9629 {
9630 struct drm_framebuffer *fb;
9631 int ret;
9632
9633 ret = i915_mutex_lock_interruptible(dev);
9634 if (ret)
9635 return ERR_PTR(ret);
9636 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9637 mutex_unlock(&dev->struct_mutex);
9638
9639 return fb;
9640 }
9641
9642 static u32
9643 intel_framebuffer_pitch_for_width(int width, int bpp)
9644 {
9645 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9646 return ALIGN(pitch, 64);
9647 }
9648
9649 static u32
9650 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9651 {
9652 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9653 return PAGE_ALIGN(pitch * mode->vdisplay);
9654 }
9655
9656 static struct drm_framebuffer *
9657 intel_framebuffer_create_for_mode(struct drm_device *dev,
9658 struct drm_display_mode *mode,
9659 int depth, int bpp)
9660 {
9661 struct drm_i915_gem_object *obj;
9662 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9663
9664 obj = i915_gem_alloc_object(dev,
9665 intel_framebuffer_size_for_mode(mode, bpp));
9666 if (obj == NULL)
9667 return ERR_PTR(-ENOMEM);
9668
9669 mode_cmd.width = mode->hdisplay;
9670 mode_cmd.height = mode->vdisplay;
9671 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9672 bpp);
9673 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9674
9675 return intel_framebuffer_create(dev, &mode_cmd, obj);
9676 }
9677
9678 static struct drm_framebuffer *
9679 mode_fits_in_fbdev(struct drm_device *dev,
9680 struct drm_display_mode *mode)
9681 {
9682 #ifdef CONFIG_DRM_I915_FBDEV
9683 struct drm_i915_private *dev_priv = dev->dev_private;
9684 struct drm_i915_gem_object *obj;
9685 struct drm_framebuffer *fb;
9686
9687 if (!dev_priv->fbdev)
9688 return NULL;
9689
9690 if (!dev_priv->fbdev->fb)
9691 return NULL;
9692
9693 obj = dev_priv->fbdev->fb->obj;
9694 BUG_ON(!obj);
9695
9696 fb = &dev_priv->fbdev->fb->base;
9697 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9698 fb->bits_per_pixel))
9699 return NULL;
9700
9701 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9702 return NULL;
9703
9704 return fb;
9705 #else
9706 return NULL;
9707 #endif
9708 }
9709
9710 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9711 struct drm_crtc *crtc,
9712 struct drm_display_mode *mode,
9713 struct drm_framebuffer *fb,
9714 int x, int y)
9715 {
9716 struct drm_plane_state *plane_state;
9717 int hdisplay, vdisplay;
9718 int ret;
9719
9720 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9721 if (IS_ERR(plane_state))
9722 return PTR_ERR(plane_state);
9723
9724 if (mode)
9725 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9726 else
9727 hdisplay = vdisplay = 0;
9728
9729 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9730 if (ret)
9731 return ret;
9732 drm_atomic_set_fb_for_plane(plane_state, fb);
9733 plane_state->crtc_x = 0;
9734 plane_state->crtc_y = 0;
9735 plane_state->crtc_w = hdisplay;
9736 plane_state->crtc_h = vdisplay;
9737 plane_state->src_x = x << 16;
9738 plane_state->src_y = y << 16;
9739 plane_state->src_w = hdisplay << 16;
9740 plane_state->src_h = vdisplay << 16;
9741
9742 return 0;
9743 }
9744
9745 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9746 struct drm_display_mode *mode,
9747 struct intel_load_detect_pipe *old,
9748 struct drm_modeset_acquire_ctx *ctx)
9749 {
9750 struct intel_crtc *intel_crtc;
9751 struct intel_encoder *intel_encoder =
9752 intel_attached_encoder(connector);
9753 struct drm_crtc *possible_crtc;
9754 struct drm_encoder *encoder = &intel_encoder->base;
9755 struct drm_crtc *crtc = NULL;
9756 struct drm_device *dev = encoder->dev;
9757 struct drm_framebuffer *fb;
9758 struct drm_mode_config *config = &dev->mode_config;
9759 struct drm_atomic_state *state = NULL;
9760 struct drm_connector_state *connector_state;
9761 struct intel_crtc_state *crtc_state;
9762 int ret, i = -1;
9763
9764 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9765 connector->base.id, connector->name,
9766 encoder->base.id, encoder->name);
9767
9768 retry:
9769 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9770 if (ret)
9771 goto fail_unlock;
9772
9773 /*
9774 * Algorithm gets a little messy:
9775 *
9776 * - if the connector already has an assigned crtc, use it (but make
9777 * sure it's on first)
9778 *
9779 * - try to find the first unused crtc that can drive this connector,
9780 * and use that if we find one
9781 */
9782
9783 /* See if we already have a CRTC for this connector */
9784 if (encoder->crtc) {
9785 crtc = encoder->crtc;
9786
9787 ret = drm_modeset_lock(&crtc->mutex, ctx);
9788 if (ret)
9789 goto fail_unlock;
9790 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9791 if (ret)
9792 goto fail_unlock;
9793
9794 old->dpms_mode = connector->dpms;
9795 old->load_detect_temp = false;
9796
9797 /* Make sure the crtc and connector are running */
9798 if (connector->dpms != DRM_MODE_DPMS_ON)
9799 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9800
9801 return true;
9802 }
9803
9804 /* Find an unused one (if possible) */
9805 for_each_crtc(dev, possible_crtc) {
9806 i++;
9807 if (!(encoder->possible_crtcs & (1 << i)))
9808 continue;
9809 if (possible_crtc->state->enable)
9810 continue;
9811 /* This can occur when applying the pipe A quirk on resume. */
9812 if (to_intel_crtc(possible_crtc)->new_enabled)
9813 continue;
9814
9815 crtc = possible_crtc;
9816 break;
9817 }
9818
9819 /*
9820 * If we didn't find an unused CRTC, don't use any.
9821 */
9822 if (!crtc) {
9823 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9824 goto fail_unlock;
9825 }
9826
9827 ret = drm_modeset_lock(&crtc->mutex, ctx);
9828 if (ret)
9829 goto fail_unlock;
9830 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9831 if (ret)
9832 goto fail_unlock;
9833 intel_encoder->new_crtc = to_intel_crtc(crtc);
9834 to_intel_connector(connector)->new_encoder = intel_encoder;
9835
9836 intel_crtc = to_intel_crtc(crtc);
9837 intel_crtc->new_enabled = true;
9838 old->dpms_mode = connector->dpms;
9839 old->load_detect_temp = true;
9840 old->release_fb = NULL;
9841
9842 state = drm_atomic_state_alloc(dev);
9843 if (!state)
9844 return false;
9845
9846 state->acquire_ctx = ctx;
9847
9848 connector_state = drm_atomic_get_connector_state(state, connector);
9849 if (IS_ERR(connector_state)) {
9850 ret = PTR_ERR(connector_state);
9851 goto fail;
9852 }
9853
9854 connector_state->crtc = crtc;
9855 connector_state->best_encoder = &intel_encoder->base;
9856
9857 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9858 if (IS_ERR(crtc_state)) {
9859 ret = PTR_ERR(crtc_state);
9860 goto fail;
9861 }
9862
9863 crtc_state->base.active = crtc_state->base.enable = true;
9864
9865 if (!mode)
9866 mode = &load_detect_mode;
9867
9868 /* We need a framebuffer large enough to accommodate all accesses
9869 * that the plane may generate whilst we perform load detection.
9870 * We can not rely on the fbcon either being present (we get called
9871 * during its initialisation to detect all boot displays, or it may
9872 * not even exist) or that it is large enough to satisfy the
9873 * requested mode.
9874 */
9875 fb = mode_fits_in_fbdev(dev, mode);
9876 if (fb == NULL) {
9877 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9878 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9879 old->release_fb = fb;
9880 } else
9881 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9882 if (IS_ERR(fb)) {
9883 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9884 goto fail;
9885 }
9886
9887 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9888 if (ret)
9889 goto fail;
9890
9891 drm_mode_copy(&crtc_state->base.mode, mode);
9892
9893 if (intel_set_mode(crtc, state)) {
9894 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9895 if (old->release_fb)
9896 old->release_fb->funcs->destroy(old->release_fb);
9897 goto fail;
9898 }
9899 crtc->primary->crtc = crtc;
9900
9901 /* let the connector get through one full cycle before testing */
9902 intel_wait_for_vblank(dev, intel_crtc->pipe);
9903 return true;
9904
9905 fail:
9906 intel_crtc->new_enabled = crtc->state->enable;
9907 fail_unlock:
9908 drm_atomic_state_free(state);
9909 state = NULL;
9910
9911 if (ret == -EDEADLK) {
9912 drm_modeset_backoff(ctx);
9913 goto retry;
9914 }
9915
9916 return false;
9917 }
9918
9919 void intel_release_load_detect_pipe(struct drm_connector *connector,
9920 struct intel_load_detect_pipe *old,
9921 struct drm_modeset_acquire_ctx *ctx)
9922 {
9923 struct drm_device *dev = connector->dev;
9924 struct intel_encoder *intel_encoder =
9925 intel_attached_encoder(connector);
9926 struct drm_encoder *encoder = &intel_encoder->base;
9927 struct drm_crtc *crtc = encoder->crtc;
9928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9929 struct drm_atomic_state *state;
9930 struct drm_connector_state *connector_state;
9931 struct intel_crtc_state *crtc_state;
9932 int ret;
9933
9934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9935 connector->base.id, connector->name,
9936 encoder->base.id, encoder->name);
9937
9938 if (old->load_detect_temp) {
9939 state = drm_atomic_state_alloc(dev);
9940 if (!state)
9941 goto fail;
9942
9943 state->acquire_ctx = ctx;
9944
9945 connector_state = drm_atomic_get_connector_state(state, connector);
9946 if (IS_ERR(connector_state))
9947 goto fail;
9948
9949 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9950 if (IS_ERR(crtc_state))
9951 goto fail;
9952
9953 to_intel_connector(connector)->new_encoder = NULL;
9954 intel_encoder->new_crtc = NULL;
9955 intel_crtc->new_enabled = false;
9956
9957 connector_state->best_encoder = NULL;
9958 connector_state->crtc = NULL;
9959
9960 crtc_state->base.enable = crtc_state->base.active = false;
9961
9962 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9963 0, 0);
9964 if (ret)
9965 goto fail;
9966
9967 ret = intel_set_mode(crtc, state);
9968 if (ret)
9969 goto fail;
9970
9971 if (old->release_fb) {
9972 drm_framebuffer_unregister_private(old->release_fb);
9973 drm_framebuffer_unreference(old->release_fb);
9974 }
9975
9976 return;
9977 }
9978
9979 /* Switch crtc and encoder back off if necessary */
9980 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9981 connector->funcs->dpms(connector, old->dpms_mode);
9982
9983 return;
9984 fail:
9985 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9986 drm_atomic_state_free(state);
9987 }
9988
9989 static int i9xx_pll_refclk(struct drm_device *dev,
9990 const struct intel_crtc_state *pipe_config)
9991 {
9992 struct drm_i915_private *dev_priv = dev->dev_private;
9993 u32 dpll = pipe_config->dpll_hw_state.dpll;
9994
9995 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9996 return dev_priv->vbt.lvds_ssc_freq;
9997 else if (HAS_PCH_SPLIT(dev))
9998 return 120000;
9999 else if (!IS_GEN2(dev))
10000 return 96000;
10001 else
10002 return 48000;
10003 }
10004
10005 /* Returns the clock of the currently programmed mode of the given pipe. */
10006 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10007 struct intel_crtc_state *pipe_config)
10008 {
10009 struct drm_device *dev = crtc->base.dev;
10010 struct drm_i915_private *dev_priv = dev->dev_private;
10011 int pipe = pipe_config->cpu_transcoder;
10012 u32 dpll = pipe_config->dpll_hw_state.dpll;
10013 u32 fp;
10014 intel_clock_t clock;
10015 int refclk = i9xx_pll_refclk(dev, pipe_config);
10016
10017 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10018 fp = pipe_config->dpll_hw_state.fp0;
10019 else
10020 fp = pipe_config->dpll_hw_state.fp1;
10021
10022 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10023 if (IS_PINEVIEW(dev)) {
10024 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10025 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10026 } else {
10027 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10028 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10029 }
10030
10031 if (!IS_GEN2(dev)) {
10032 if (IS_PINEVIEW(dev))
10033 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10034 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10035 else
10036 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10037 DPLL_FPA01_P1_POST_DIV_SHIFT);
10038
10039 switch (dpll & DPLL_MODE_MASK) {
10040 case DPLLB_MODE_DAC_SERIAL:
10041 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10042 5 : 10;
10043 break;
10044 case DPLLB_MODE_LVDS:
10045 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10046 7 : 14;
10047 break;
10048 default:
10049 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10050 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10051 return;
10052 }
10053
10054 if (IS_PINEVIEW(dev))
10055 pineview_clock(refclk, &clock);
10056 else
10057 i9xx_clock(refclk, &clock);
10058 } else {
10059 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10060 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10061
10062 if (is_lvds) {
10063 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10064 DPLL_FPA01_P1_POST_DIV_SHIFT);
10065
10066 if (lvds & LVDS_CLKB_POWER_UP)
10067 clock.p2 = 7;
10068 else
10069 clock.p2 = 14;
10070 } else {
10071 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10072 clock.p1 = 2;
10073 else {
10074 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10075 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10076 }
10077 if (dpll & PLL_P2_DIVIDE_BY_4)
10078 clock.p2 = 4;
10079 else
10080 clock.p2 = 2;
10081 }
10082
10083 i9xx_clock(refclk, &clock);
10084 }
10085
10086 /*
10087 * This value includes pixel_multiplier. We will use
10088 * port_clock to compute adjusted_mode.crtc_clock in the
10089 * encoder's get_config() function.
10090 */
10091 pipe_config->port_clock = clock.dot;
10092 }
10093
10094 int intel_dotclock_calculate(int link_freq,
10095 const struct intel_link_m_n *m_n)
10096 {
10097 /*
10098 * The calculation for the data clock is:
10099 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10100 * But we want to avoid losing precison if possible, so:
10101 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10102 *
10103 * and the link clock is simpler:
10104 * link_clock = (m * link_clock) / n
10105 */
10106
10107 if (!m_n->link_n)
10108 return 0;
10109
10110 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10111 }
10112
10113 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10114 struct intel_crtc_state *pipe_config)
10115 {
10116 struct drm_device *dev = crtc->base.dev;
10117
10118 /* read out port_clock from the DPLL */
10119 i9xx_crtc_clock_get(crtc, pipe_config);
10120
10121 /*
10122 * This value does not include pixel_multiplier.
10123 * We will check that port_clock and adjusted_mode.crtc_clock
10124 * agree once we know their relationship in the encoder's
10125 * get_config() function.
10126 */
10127 pipe_config->base.adjusted_mode.crtc_clock =
10128 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10129 &pipe_config->fdi_m_n);
10130 }
10131
10132 /** Returns the currently programmed mode of the given pipe. */
10133 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10134 struct drm_crtc *crtc)
10135 {
10136 struct drm_i915_private *dev_priv = dev->dev_private;
10137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10138 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10139 struct drm_display_mode *mode;
10140 struct intel_crtc_state pipe_config;
10141 int htot = I915_READ(HTOTAL(cpu_transcoder));
10142 int hsync = I915_READ(HSYNC(cpu_transcoder));
10143 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10144 int vsync = I915_READ(VSYNC(cpu_transcoder));
10145 enum pipe pipe = intel_crtc->pipe;
10146
10147 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10148 if (!mode)
10149 return NULL;
10150
10151 /*
10152 * Construct a pipe_config sufficient for getting the clock info
10153 * back out of crtc_clock_get.
10154 *
10155 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10156 * to use a real value here instead.
10157 */
10158 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10159 pipe_config.pixel_multiplier = 1;
10160 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10161 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10162 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10163 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10164
10165 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10166 mode->hdisplay = (htot & 0xffff) + 1;
10167 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10168 mode->hsync_start = (hsync & 0xffff) + 1;
10169 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10170 mode->vdisplay = (vtot & 0xffff) + 1;
10171 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10172 mode->vsync_start = (vsync & 0xffff) + 1;
10173 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10174
10175 drm_mode_set_name(mode);
10176
10177 return mode;
10178 }
10179
10180 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10181 {
10182 struct drm_device *dev = crtc->dev;
10183 struct drm_i915_private *dev_priv = dev->dev_private;
10184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10185
10186 if (!HAS_GMCH_DISPLAY(dev))
10187 return;
10188
10189 if (!dev_priv->lvds_downclock_avail)
10190 return;
10191
10192 /*
10193 * Since this is called by a timer, we should never get here in
10194 * the manual case.
10195 */
10196 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10197 int pipe = intel_crtc->pipe;
10198 int dpll_reg = DPLL(pipe);
10199 int dpll;
10200
10201 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10202
10203 assert_panel_unlocked(dev_priv, pipe);
10204
10205 dpll = I915_READ(dpll_reg);
10206 dpll |= DISPLAY_RATE_SELECT_FPA1;
10207 I915_WRITE(dpll_reg, dpll);
10208 intel_wait_for_vblank(dev, pipe);
10209 dpll = I915_READ(dpll_reg);
10210 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10211 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10212 }
10213
10214 }
10215
10216 void intel_mark_busy(struct drm_device *dev)
10217 {
10218 struct drm_i915_private *dev_priv = dev->dev_private;
10219
10220 if (dev_priv->mm.busy)
10221 return;
10222
10223 intel_runtime_pm_get(dev_priv);
10224 i915_update_gfx_val(dev_priv);
10225 if (INTEL_INFO(dev)->gen >= 6)
10226 gen6_rps_busy(dev_priv);
10227 dev_priv->mm.busy = true;
10228 }
10229
10230 void intel_mark_idle(struct drm_device *dev)
10231 {
10232 struct drm_i915_private *dev_priv = dev->dev_private;
10233 struct drm_crtc *crtc;
10234
10235 if (!dev_priv->mm.busy)
10236 return;
10237
10238 dev_priv->mm.busy = false;
10239
10240 for_each_crtc(dev, crtc) {
10241 if (!crtc->primary->fb)
10242 continue;
10243
10244 intel_decrease_pllclock(crtc);
10245 }
10246
10247 if (INTEL_INFO(dev)->gen >= 6)
10248 gen6_rps_idle(dev->dev_private);
10249
10250 intel_runtime_pm_put(dev_priv);
10251 }
10252
10253 static void intel_crtc_destroy(struct drm_crtc *crtc)
10254 {
10255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10256 struct drm_device *dev = crtc->dev;
10257 struct intel_unpin_work *work;
10258
10259 spin_lock_irq(&dev->event_lock);
10260 work = intel_crtc->unpin_work;
10261 intel_crtc->unpin_work = NULL;
10262 spin_unlock_irq(&dev->event_lock);
10263
10264 if (work) {
10265 cancel_work_sync(&work->work);
10266 kfree(work);
10267 }
10268
10269 drm_crtc_cleanup(crtc);
10270
10271 kfree(intel_crtc);
10272 }
10273
10274 static void intel_unpin_work_fn(struct work_struct *__work)
10275 {
10276 struct intel_unpin_work *work =
10277 container_of(__work, struct intel_unpin_work, work);
10278 struct drm_device *dev = work->crtc->dev;
10279 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10280
10281 mutex_lock(&dev->struct_mutex);
10282 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10283 drm_gem_object_unreference(&work->pending_flip_obj->base);
10284
10285 intel_fbc_update(dev);
10286
10287 if (work->flip_queued_req)
10288 i915_gem_request_assign(&work->flip_queued_req, NULL);
10289 mutex_unlock(&dev->struct_mutex);
10290
10291 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10292 drm_framebuffer_unreference(work->old_fb);
10293
10294 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10295 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10296
10297 kfree(work);
10298 }
10299
10300 static void do_intel_finish_page_flip(struct drm_device *dev,
10301 struct drm_crtc *crtc)
10302 {
10303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10304 struct intel_unpin_work *work;
10305 unsigned long flags;
10306
10307 /* Ignore early vblank irqs */
10308 if (intel_crtc == NULL)
10309 return;
10310
10311 /*
10312 * This is called both by irq handlers and the reset code (to complete
10313 * lost pageflips) so needs the full irqsave spinlocks.
10314 */
10315 spin_lock_irqsave(&dev->event_lock, flags);
10316 work = intel_crtc->unpin_work;
10317
10318 /* Ensure we don't miss a work->pending update ... */
10319 smp_rmb();
10320
10321 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10322 spin_unlock_irqrestore(&dev->event_lock, flags);
10323 return;
10324 }
10325
10326 page_flip_completed(intel_crtc);
10327
10328 spin_unlock_irqrestore(&dev->event_lock, flags);
10329 }
10330
10331 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10332 {
10333 struct drm_i915_private *dev_priv = dev->dev_private;
10334 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10335
10336 do_intel_finish_page_flip(dev, crtc);
10337 }
10338
10339 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10340 {
10341 struct drm_i915_private *dev_priv = dev->dev_private;
10342 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10343
10344 do_intel_finish_page_flip(dev, crtc);
10345 }
10346
10347 /* Is 'a' after or equal to 'b'? */
10348 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10349 {
10350 return !((a - b) & 0x80000000);
10351 }
10352
10353 static bool page_flip_finished(struct intel_crtc *crtc)
10354 {
10355 struct drm_device *dev = crtc->base.dev;
10356 struct drm_i915_private *dev_priv = dev->dev_private;
10357
10358 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10359 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10360 return true;
10361
10362 /*
10363 * The relevant registers doen't exist on pre-ctg.
10364 * As the flip done interrupt doesn't trigger for mmio
10365 * flips on gmch platforms, a flip count check isn't
10366 * really needed there. But since ctg has the registers,
10367 * include it in the check anyway.
10368 */
10369 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10370 return true;
10371
10372 /*
10373 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10374 * used the same base address. In that case the mmio flip might
10375 * have completed, but the CS hasn't even executed the flip yet.
10376 *
10377 * A flip count check isn't enough as the CS might have updated
10378 * the base address just after start of vblank, but before we
10379 * managed to process the interrupt. This means we'd complete the
10380 * CS flip too soon.
10381 *
10382 * Combining both checks should get us a good enough result. It may
10383 * still happen that the CS flip has been executed, but has not
10384 * yet actually completed. But in case the base address is the same
10385 * anyway, we don't really care.
10386 */
10387 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10388 crtc->unpin_work->gtt_offset &&
10389 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10390 crtc->unpin_work->flip_count);
10391 }
10392
10393 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10394 {
10395 struct drm_i915_private *dev_priv = dev->dev_private;
10396 struct intel_crtc *intel_crtc =
10397 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10398 unsigned long flags;
10399
10400
10401 /*
10402 * This is called both by irq handlers and the reset code (to complete
10403 * lost pageflips) so needs the full irqsave spinlocks.
10404 *
10405 * NB: An MMIO update of the plane base pointer will also
10406 * generate a page-flip completion irq, i.e. every modeset
10407 * is also accompanied by a spurious intel_prepare_page_flip().
10408 */
10409 spin_lock_irqsave(&dev->event_lock, flags);
10410 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10411 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10412 spin_unlock_irqrestore(&dev->event_lock, flags);
10413 }
10414
10415 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10416 {
10417 /* Ensure that the work item is consistent when activating it ... */
10418 smp_wmb();
10419 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10420 /* and that it is marked active as soon as the irq could fire. */
10421 smp_wmb();
10422 }
10423
10424 static int intel_gen2_queue_flip(struct drm_device *dev,
10425 struct drm_crtc *crtc,
10426 struct drm_framebuffer *fb,
10427 struct drm_i915_gem_object *obj,
10428 struct intel_engine_cs *ring,
10429 uint32_t flags)
10430 {
10431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10432 u32 flip_mask;
10433 int ret;
10434
10435 ret = intel_ring_begin(ring, 6);
10436 if (ret)
10437 return ret;
10438
10439 /* Can't queue multiple flips, so wait for the previous
10440 * one to finish before executing the next.
10441 */
10442 if (intel_crtc->plane)
10443 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10444 else
10445 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10446 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10447 intel_ring_emit(ring, MI_NOOP);
10448 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10449 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10450 intel_ring_emit(ring, fb->pitches[0]);
10451 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10452 intel_ring_emit(ring, 0); /* aux display base address, unused */
10453
10454 intel_mark_page_flip_active(intel_crtc);
10455 __intel_ring_advance(ring);
10456 return 0;
10457 }
10458
10459 static int intel_gen3_queue_flip(struct drm_device *dev,
10460 struct drm_crtc *crtc,
10461 struct drm_framebuffer *fb,
10462 struct drm_i915_gem_object *obj,
10463 struct intel_engine_cs *ring,
10464 uint32_t flags)
10465 {
10466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10467 u32 flip_mask;
10468 int ret;
10469
10470 ret = intel_ring_begin(ring, 6);
10471 if (ret)
10472 return ret;
10473
10474 if (intel_crtc->plane)
10475 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10476 else
10477 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10478 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10479 intel_ring_emit(ring, MI_NOOP);
10480 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10481 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10482 intel_ring_emit(ring, fb->pitches[0]);
10483 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10484 intel_ring_emit(ring, MI_NOOP);
10485
10486 intel_mark_page_flip_active(intel_crtc);
10487 __intel_ring_advance(ring);
10488 return 0;
10489 }
10490
10491 static int intel_gen4_queue_flip(struct drm_device *dev,
10492 struct drm_crtc *crtc,
10493 struct drm_framebuffer *fb,
10494 struct drm_i915_gem_object *obj,
10495 struct intel_engine_cs *ring,
10496 uint32_t flags)
10497 {
10498 struct drm_i915_private *dev_priv = dev->dev_private;
10499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10500 uint32_t pf, pipesrc;
10501 int ret;
10502
10503 ret = intel_ring_begin(ring, 4);
10504 if (ret)
10505 return ret;
10506
10507 /* i965+ uses the linear or tiled offsets from the
10508 * Display Registers (which do not change across a page-flip)
10509 * so we need only reprogram the base address.
10510 */
10511 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10512 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10513 intel_ring_emit(ring, fb->pitches[0]);
10514 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10515 obj->tiling_mode);
10516
10517 /* XXX Enabling the panel-fitter across page-flip is so far
10518 * untested on non-native modes, so ignore it for now.
10519 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10520 */
10521 pf = 0;
10522 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10523 intel_ring_emit(ring, pf | pipesrc);
10524
10525 intel_mark_page_flip_active(intel_crtc);
10526 __intel_ring_advance(ring);
10527 return 0;
10528 }
10529
10530 static int intel_gen6_queue_flip(struct drm_device *dev,
10531 struct drm_crtc *crtc,
10532 struct drm_framebuffer *fb,
10533 struct drm_i915_gem_object *obj,
10534 struct intel_engine_cs *ring,
10535 uint32_t flags)
10536 {
10537 struct drm_i915_private *dev_priv = dev->dev_private;
10538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10539 uint32_t pf, pipesrc;
10540 int ret;
10541
10542 ret = intel_ring_begin(ring, 4);
10543 if (ret)
10544 return ret;
10545
10546 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10547 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10548 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10549 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10550
10551 /* Contrary to the suggestions in the documentation,
10552 * "Enable Panel Fitter" does not seem to be required when page
10553 * flipping with a non-native mode, and worse causes a normal
10554 * modeset to fail.
10555 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10556 */
10557 pf = 0;
10558 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10559 intel_ring_emit(ring, pf | pipesrc);
10560
10561 intel_mark_page_flip_active(intel_crtc);
10562 __intel_ring_advance(ring);
10563 return 0;
10564 }
10565
10566 static int intel_gen7_queue_flip(struct drm_device *dev,
10567 struct drm_crtc *crtc,
10568 struct drm_framebuffer *fb,
10569 struct drm_i915_gem_object *obj,
10570 struct intel_engine_cs *ring,
10571 uint32_t flags)
10572 {
10573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10574 uint32_t plane_bit = 0;
10575 int len, ret;
10576
10577 switch (intel_crtc->plane) {
10578 case PLANE_A:
10579 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10580 break;
10581 case PLANE_B:
10582 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10583 break;
10584 case PLANE_C:
10585 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10586 break;
10587 default:
10588 WARN_ONCE(1, "unknown plane in flip command\n");
10589 return -ENODEV;
10590 }
10591
10592 len = 4;
10593 if (ring->id == RCS) {
10594 len += 6;
10595 /*
10596 * On Gen 8, SRM is now taking an extra dword to accommodate
10597 * 48bits addresses, and we need a NOOP for the batch size to
10598 * stay even.
10599 */
10600 if (IS_GEN8(dev))
10601 len += 2;
10602 }
10603
10604 /*
10605 * BSpec MI_DISPLAY_FLIP for IVB:
10606 * "The full packet must be contained within the same cache line."
10607 *
10608 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10609 * cacheline, if we ever start emitting more commands before
10610 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10611 * then do the cacheline alignment, and finally emit the
10612 * MI_DISPLAY_FLIP.
10613 */
10614 ret = intel_ring_cacheline_align(ring);
10615 if (ret)
10616 return ret;
10617
10618 ret = intel_ring_begin(ring, len);
10619 if (ret)
10620 return ret;
10621
10622 /* Unmask the flip-done completion message. Note that the bspec says that
10623 * we should do this for both the BCS and RCS, and that we must not unmask
10624 * more than one flip event at any time (or ensure that one flip message
10625 * can be sent by waiting for flip-done prior to queueing new flips).
10626 * Experimentation says that BCS works despite DERRMR masking all
10627 * flip-done completion events and that unmasking all planes at once
10628 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10629 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10630 */
10631 if (ring->id == RCS) {
10632 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10633 intel_ring_emit(ring, DERRMR);
10634 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10635 DERRMR_PIPEB_PRI_FLIP_DONE |
10636 DERRMR_PIPEC_PRI_FLIP_DONE));
10637 if (IS_GEN8(dev))
10638 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10639 MI_SRM_LRM_GLOBAL_GTT);
10640 else
10641 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10642 MI_SRM_LRM_GLOBAL_GTT);
10643 intel_ring_emit(ring, DERRMR);
10644 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10645 if (IS_GEN8(dev)) {
10646 intel_ring_emit(ring, 0);
10647 intel_ring_emit(ring, MI_NOOP);
10648 }
10649 }
10650
10651 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10652 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10653 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10654 intel_ring_emit(ring, (MI_NOOP));
10655
10656 intel_mark_page_flip_active(intel_crtc);
10657 __intel_ring_advance(ring);
10658 return 0;
10659 }
10660
10661 static bool use_mmio_flip(struct intel_engine_cs *ring,
10662 struct drm_i915_gem_object *obj)
10663 {
10664 /*
10665 * This is not being used for older platforms, because
10666 * non-availability of flip done interrupt forces us to use
10667 * CS flips. Older platforms derive flip done using some clever
10668 * tricks involving the flip_pending status bits and vblank irqs.
10669 * So using MMIO flips there would disrupt this mechanism.
10670 */
10671
10672 if (ring == NULL)
10673 return true;
10674
10675 if (INTEL_INFO(ring->dev)->gen < 5)
10676 return false;
10677
10678 if (i915.use_mmio_flip < 0)
10679 return false;
10680 else if (i915.use_mmio_flip > 0)
10681 return true;
10682 else if (i915.enable_execlists)
10683 return true;
10684 else
10685 return ring != i915_gem_request_get_ring(obj->last_write_req);
10686 }
10687
10688 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10689 {
10690 struct drm_device *dev = intel_crtc->base.dev;
10691 struct drm_i915_private *dev_priv = dev->dev_private;
10692 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10693 const enum pipe pipe = intel_crtc->pipe;
10694 u32 ctl, stride;
10695
10696 ctl = I915_READ(PLANE_CTL(pipe, 0));
10697 ctl &= ~PLANE_CTL_TILED_MASK;
10698 switch (fb->modifier[0]) {
10699 case DRM_FORMAT_MOD_NONE:
10700 break;
10701 case I915_FORMAT_MOD_X_TILED:
10702 ctl |= PLANE_CTL_TILED_X;
10703 break;
10704 case I915_FORMAT_MOD_Y_TILED:
10705 ctl |= PLANE_CTL_TILED_Y;
10706 break;
10707 case I915_FORMAT_MOD_Yf_TILED:
10708 ctl |= PLANE_CTL_TILED_YF;
10709 break;
10710 default:
10711 MISSING_CASE(fb->modifier[0]);
10712 }
10713
10714 /*
10715 * The stride is either expressed as a multiple of 64 bytes chunks for
10716 * linear buffers or in number of tiles for tiled buffers.
10717 */
10718 stride = fb->pitches[0] /
10719 intel_fb_stride_alignment(dev, fb->modifier[0],
10720 fb->pixel_format);
10721
10722 /*
10723 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10724 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10725 */
10726 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10727 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10728
10729 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10730 POSTING_READ(PLANE_SURF(pipe, 0));
10731 }
10732
10733 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10734 {
10735 struct drm_device *dev = intel_crtc->base.dev;
10736 struct drm_i915_private *dev_priv = dev->dev_private;
10737 struct intel_framebuffer *intel_fb =
10738 to_intel_framebuffer(intel_crtc->base.primary->fb);
10739 struct drm_i915_gem_object *obj = intel_fb->obj;
10740 u32 dspcntr;
10741 u32 reg;
10742
10743 reg = DSPCNTR(intel_crtc->plane);
10744 dspcntr = I915_READ(reg);
10745
10746 if (obj->tiling_mode != I915_TILING_NONE)
10747 dspcntr |= DISPPLANE_TILED;
10748 else
10749 dspcntr &= ~DISPPLANE_TILED;
10750
10751 I915_WRITE(reg, dspcntr);
10752
10753 I915_WRITE(DSPSURF(intel_crtc->plane),
10754 intel_crtc->unpin_work->gtt_offset);
10755 POSTING_READ(DSPSURF(intel_crtc->plane));
10756
10757 }
10758
10759 /*
10760 * XXX: This is the temporary way to update the plane registers until we get
10761 * around to using the usual plane update functions for MMIO flips
10762 */
10763 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10764 {
10765 struct drm_device *dev = intel_crtc->base.dev;
10766 bool atomic_update;
10767 u32 start_vbl_count;
10768
10769 intel_mark_page_flip_active(intel_crtc);
10770
10771 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10772
10773 if (INTEL_INFO(dev)->gen >= 9)
10774 skl_do_mmio_flip(intel_crtc);
10775 else
10776 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10777 ilk_do_mmio_flip(intel_crtc);
10778
10779 if (atomic_update)
10780 intel_pipe_update_end(intel_crtc, start_vbl_count);
10781 }
10782
10783 static void intel_mmio_flip_work_func(struct work_struct *work)
10784 {
10785 struct intel_mmio_flip *mmio_flip =
10786 container_of(work, struct intel_mmio_flip, work);
10787
10788 if (mmio_flip->req)
10789 WARN_ON(__i915_wait_request(mmio_flip->req,
10790 mmio_flip->crtc->reset_counter,
10791 false, NULL,
10792 &mmio_flip->i915->rps.mmioflips));
10793
10794 intel_do_mmio_flip(mmio_flip->crtc);
10795
10796 i915_gem_request_unreference__unlocked(mmio_flip->req);
10797 kfree(mmio_flip);
10798 }
10799
10800 static int intel_queue_mmio_flip(struct drm_device *dev,
10801 struct drm_crtc *crtc,
10802 struct drm_framebuffer *fb,
10803 struct drm_i915_gem_object *obj,
10804 struct intel_engine_cs *ring,
10805 uint32_t flags)
10806 {
10807 struct intel_mmio_flip *mmio_flip;
10808
10809 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10810 if (mmio_flip == NULL)
10811 return -ENOMEM;
10812
10813 mmio_flip->i915 = to_i915(dev);
10814 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
10815 mmio_flip->crtc = to_intel_crtc(crtc);
10816
10817 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10818 schedule_work(&mmio_flip->work);
10819
10820 return 0;
10821 }
10822
10823 static int intel_default_queue_flip(struct drm_device *dev,
10824 struct drm_crtc *crtc,
10825 struct drm_framebuffer *fb,
10826 struct drm_i915_gem_object *obj,
10827 struct intel_engine_cs *ring,
10828 uint32_t flags)
10829 {
10830 return -ENODEV;
10831 }
10832
10833 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10834 struct drm_crtc *crtc)
10835 {
10836 struct drm_i915_private *dev_priv = dev->dev_private;
10837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10838 struct intel_unpin_work *work = intel_crtc->unpin_work;
10839 u32 addr;
10840
10841 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10842 return true;
10843
10844 if (!work->enable_stall_check)
10845 return false;
10846
10847 if (work->flip_ready_vblank == 0) {
10848 if (work->flip_queued_req &&
10849 !i915_gem_request_completed(work->flip_queued_req, true))
10850 return false;
10851
10852 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10853 }
10854
10855 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10856 return false;
10857
10858 /* Potential stall - if we see that the flip has happened,
10859 * assume a missed interrupt. */
10860 if (INTEL_INFO(dev)->gen >= 4)
10861 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10862 else
10863 addr = I915_READ(DSPADDR(intel_crtc->plane));
10864
10865 /* There is a potential issue here with a false positive after a flip
10866 * to the same address. We could address this by checking for a
10867 * non-incrementing frame counter.
10868 */
10869 return addr == work->gtt_offset;
10870 }
10871
10872 void intel_check_page_flip(struct drm_device *dev, int pipe)
10873 {
10874 struct drm_i915_private *dev_priv = dev->dev_private;
10875 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10877 struct intel_unpin_work *work;
10878
10879 WARN_ON(!in_interrupt());
10880
10881 if (crtc == NULL)
10882 return;
10883
10884 spin_lock(&dev->event_lock);
10885 work = intel_crtc->unpin_work;
10886 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10887 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10888 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10889 page_flip_completed(intel_crtc);
10890 work = NULL;
10891 }
10892 if (work != NULL &&
10893 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10894 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10895 spin_unlock(&dev->event_lock);
10896 }
10897
10898 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10899 struct drm_framebuffer *fb,
10900 struct drm_pending_vblank_event *event,
10901 uint32_t page_flip_flags)
10902 {
10903 struct drm_device *dev = crtc->dev;
10904 struct drm_i915_private *dev_priv = dev->dev_private;
10905 struct drm_framebuffer *old_fb = crtc->primary->fb;
10906 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10908 struct drm_plane *primary = crtc->primary;
10909 enum pipe pipe = intel_crtc->pipe;
10910 struct intel_unpin_work *work;
10911 struct intel_engine_cs *ring;
10912 bool mmio_flip;
10913 int ret;
10914
10915 /*
10916 * drm_mode_page_flip_ioctl() should already catch this, but double
10917 * check to be safe. In the future we may enable pageflipping from
10918 * a disabled primary plane.
10919 */
10920 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10921 return -EBUSY;
10922
10923 /* Can't change pixel format via MI display flips. */
10924 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10925 return -EINVAL;
10926
10927 /*
10928 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10929 * Note that pitch changes could also affect these register.
10930 */
10931 if (INTEL_INFO(dev)->gen > 3 &&
10932 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10933 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10934 return -EINVAL;
10935
10936 if (i915_terminally_wedged(&dev_priv->gpu_error))
10937 goto out_hang;
10938
10939 work = kzalloc(sizeof(*work), GFP_KERNEL);
10940 if (work == NULL)
10941 return -ENOMEM;
10942
10943 work->event = event;
10944 work->crtc = crtc;
10945 work->old_fb = old_fb;
10946 INIT_WORK(&work->work, intel_unpin_work_fn);
10947
10948 ret = drm_crtc_vblank_get(crtc);
10949 if (ret)
10950 goto free_work;
10951
10952 /* We borrow the event spin lock for protecting unpin_work */
10953 spin_lock_irq(&dev->event_lock);
10954 if (intel_crtc->unpin_work) {
10955 /* Before declaring the flip queue wedged, check if
10956 * the hardware completed the operation behind our backs.
10957 */
10958 if (__intel_pageflip_stall_check(dev, crtc)) {
10959 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10960 page_flip_completed(intel_crtc);
10961 } else {
10962 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10963 spin_unlock_irq(&dev->event_lock);
10964
10965 drm_crtc_vblank_put(crtc);
10966 kfree(work);
10967 return -EBUSY;
10968 }
10969 }
10970 intel_crtc->unpin_work = work;
10971 spin_unlock_irq(&dev->event_lock);
10972
10973 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10974 flush_workqueue(dev_priv->wq);
10975
10976 /* Reference the objects for the scheduled work. */
10977 drm_framebuffer_reference(work->old_fb);
10978 drm_gem_object_reference(&obj->base);
10979
10980 crtc->primary->fb = fb;
10981 update_state_fb(crtc->primary);
10982
10983 work->pending_flip_obj = obj;
10984
10985 ret = i915_mutex_lock_interruptible(dev);
10986 if (ret)
10987 goto cleanup;
10988
10989 atomic_inc(&intel_crtc->unpin_work_count);
10990 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10991
10992 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10993 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10994
10995 if (IS_VALLEYVIEW(dev)) {
10996 ring = &dev_priv->ring[BCS];
10997 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10998 /* vlv: DISPLAY_FLIP fails to change tiling */
10999 ring = NULL;
11000 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11001 ring = &dev_priv->ring[BCS];
11002 } else if (INTEL_INFO(dev)->gen >= 7) {
11003 ring = i915_gem_request_get_ring(obj->last_write_req);
11004 if (ring == NULL || ring->id != RCS)
11005 ring = &dev_priv->ring[BCS];
11006 } else {
11007 ring = &dev_priv->ring[RCS];
11008 }
11009
11010 mmio_flip = use_mmio_flip(ring, obj);
11011
11012 /* When using CS flips, we want to emit semaphores between rings.
11013 * However, when using mmio flips we will create a task to do the
11014 * synchronisation, so all we want here is to pin the framebuffer
11015 * into the display plane and skip any waits.
11016 */
11017 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11018 crtc->primary->state,
11019 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
11020 if (ret)
11021 goto cleanup_pending;
11022
11023 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11024 + intel_crtc->dspaddr_offset;
11025
11026 if (mmio_flip) {
11027 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11028 page_flip_flags);
11029 if (ret)
11030 goto cleanup_unpin;
11031
11032 i915_gem_request_assign(&work->flip_queued_req,
11033 obj->last_write_req);
11034 } else {
11035 if (obj->last_write_req) {
11036 ret = i915_gem_check_olr(obj->last_write_req);
11037 if (ret)
11038 goto cleanup_unpin;
11039 }
11040
11041 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11042 page_flip_flags);
11043 if (ret)
11044 goto cleanup_unpin;
11045
11046 i915_gem_request_assign(&work->flip_queued_req,
11047 intel_ring_get_request(ring));
11048 }
11049
11050 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11051 work->enable_stall_check = true;
11052
11053 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11054 INTEL_FRONTBUFFER_PRIMARY(pipe));
11055
11056 intel_fbc_disable(dev);
11057 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11058 mutex_unlock(&dev->struct_mutex);
11059
11060 trace_i915_flip_request(intel_crtc->plane, obj);
11061
11062 return 0;
11063
11064 cleanup_unpin:
11065 intel_unpin_fb_obj(fb, crtc->primary->state);
11066 cleanup_pending:
11067 atomic_dec(&intel_crtc->unpin_work_count);
11068 mutex_unlock(&dev->struct_mutex);
11069 cleanup:
11070 crtc->primary->fb = old_fb;
11071 update_state_fb(crtc->primary);
11072
11073 drm_gem_object_unreference_unlocked(&obj->base);
11074 drm_framebuffer_unreference(work->old_fb);
11075
11076 spin_lock_irq(&dev->event_lock);
11077 intel_crtc->unpin_work = NULL;
11078 spin_unlock_irq(&dev->event_lock);
11079
11080 drm_crtc_vblank_put(crtc);
11081 free_work:
11082 kfree(work);
11083
11084 if (ret == -EIO) {
11085 out_hang:
11086 ret = intel_plane_restore(primary);
11087 if (ret == 0 && event) {
11088 spin_lock_irq(&dev->event_lock);
11089 drm_send_vblank_event(dev, pipe, event);
11090 spin_unlock_irq(&dev->event_lock);
11091 }
11092 }
11093 return ret;
11094 }
11095
11096 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11097 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11098 .load_lut = intel_crtc_load_lut,
11099 .atomic_begin = intel_begin_crtc_commit,
11100 .atomic_flush = intel_finish_crtc_commit,
11101 };
11102
11103 /**
11104 * intel_modeset_update_staged_output_state
11105 *
11106 * Updates the staged output configuration state, e.g. after we've read out the
11107 * current hw state.
11108 */
11109 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11110 {
11111 struct intel_crtc *crtc;
11112 struct intel_encoder *encoder;
11113 struct intel_connector *connector;
11114
11115 for_each_intel_connector(dev, connector) {
11116 connector->new_encoder =
11117 to_intel_encoder(connector->base.encoder);
11118 }
11119
11120 for_each_intel_encoder(dev, encoder) {
11121 encoder->new_crtc =
11122 to_intel_crtc(encoder->base.crtc);
11123 }
11124
11125 for_each_intel_crtc(dev, crtc) {
11126 crtc->new_enabled = crtc->base.state->enable;
11127 }
11128 }
11129
11130 /* Transitional helper to copy current connector/encoder state to
11131 * connector->state. This is needed so that code that is partially
11132 * converted to atomic does the right thing.
11133 */
11134 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11135 {
11136 struct intel_connector *connector;
11137
11138 for_each_intel_connector(dev, connector) {
11139 if (connector->base.encoder) {
11140 connector->base.state->best_encoder =
11141 connector->base.encoder;
11142 connector->base.state->crtc =
11143 connector->base.encoder->crtc;
11144 } else {
11145 connector->base.state->best_encoder = NULL;
11146 connector->base.state->crtc = NULL;
11147 }
11148 }
11149 }
11150
11151 /* Fixup legacy state after an atomic state swap.
11152 */
11153 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11154 {
11155 struct intel_crtc *crtc;
11156 struct intel_encoder *encoder;
11157 struct intel_connector *connector;
11158
11159 for_each_intel_connector(state->dev, connector) {
11160 connector->base.encoder = connector->base.state->best_encoder;
11161 if (connector->base.encoder)
11162 connector->base.encoder->crtc =
11163 connector->base.state->crtc;
11164 }
11165
11166 /* Update crtc of disabled encoders */
11167 for_each_intel_encoder(state->dev, encoder) {
11168 int num_connectors = 0;
11169
11170 for_each_intel_connector(state->dev, connector)
11171 if (connector->base.encoder == &encoder->base)
11172 num_connectors++;
11173
11174 if (num_connectors == 0)
11175 encoder->base.crtc = NULL;
11176 }
11177
11178 for_each_intel_crtc(state->dev, crtc) {
11179 crtc->base.enabled = crtc->base.state->enable;
11180 crtc->config = to_intel_crtc_state(crtc->base.state);
11181 }
11182
11183 /* Copy the new configuration to the staged state, to keep the few
11184 * pieces of code that haven't been converted yet happy */
11185 intel_modeset_update_staged_output_state(state->dev);
11186 }
11187
11188 static void
11189 connected_sink_compute_bpp(struct intel_connector *connector,
11190 struct intel_crtc_state *pipe_config)
11191 {
11192 int bpp = pipe_config->pipe_bpp;
11193
11194 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11195 connector->base.base.id,
11196 connector->base.name);
11197
11198 /* Don't use an invalid EDID bpc value */
11199 if (connector->base.display_info.bpc &&
11200 connector->base.display_info.bpc * 3 < bpp) {
11201 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11202 bpp, connector->base.display_info.bpc*3);
11203 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11204 }
11205
11206 /* Clamp bpp to 8 on screens without EDID 1.4 */
11207 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11208 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11209 bpp);
11210 pipe_config->pipe_bpp = 24;
11211 }
11212 }
11213
11214 static int
11215 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11216 struct intel_crtc_state *pipe_config)
11217 {
11218 struct drm_device *dev = crtc->base.dev;
11219 struct drm_atomic_state *state;
11220 struct drm_connector *connector;
11221 struct drm_connector_state *connector_state;
11222 int bpp, i;
11223
11224 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11225 bpp = 10*3;
11226 else if (INTEL_INFO(dev)->gen >= 5)
11227 bpp = 12*3;
11228 else
11229 bpp = 8*3;
11230
11231
11232 pipe_config->pipe_bpp = bpp;
11233
11234 state = pipe_config->base.state;
11235
11236 /* Clamp display bpp to EDID value */
11237 for_each_connector_in_state(state, connector, connector_state, i) {
11238 if (connector_state->crtc != &crtc->base)
11239 continue;
11240
11241 connected_sink_compute_bpp(to_intel_connector(connector),
11242 pipe_config);
11243 }
11244
11245 return bpp;
11246 }
11247
11248 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11249 {
11250 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11251 "type: 0x%x flags: 0x%x\n",
11252 mode->crtc_clock,
11253 mode->crtc_hdisplay, mode->crtc_hsync_start,
11254 mode->crtc_hsync_end, mode->crtc_htotal,
11255 mode->crtc_vdisplay, mode->crtc_vsync_start,
11256 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11257 }
11258
11259 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11260 struct intel_crtc_state *pipe_config,
11261 const char *context)
11262 {
11263 struct drm_device *dev = crtc->base.dev;
11264 struct drm_plane *plane;
11265 struct intel_plane *intel_plane;
11266 struct intel_plane_state *state;
11267 struct drm_framebuffer *fb;
11268
11269 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11270 context, pipe_config, pipe_name(crtc->pipe));
11271
11272 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11273 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11274 pipe_config->pipe_bpp, pipe_config->dither);
11275 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11276 pipe_config->has_pch_encoder,
11277 pipe_config->fdi_lanes,
11278 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11279 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11280 pipe_config->fdi_m_n.tu);
11281 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11282 pipe_config->has_dp_encoder,
11283 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11284 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11285 pipe_config->dp_m_n.tu);
11286
11287 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11288 pipe_config->has_dp_encoder,
11289 pipe_config->dp_m2_n2.gmch_m,
11290 pipe_config->dp_m2_n2.gmch_n,
11291 pipe_config->dp_m2_n2.link_m,
11292 pipe_config->dp_m2_n2.link_n,
11293 pipe_config->dp_m2_n2.tu);
11294
11295 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11296 pipe_config->has_audio,
11297 pipe_config->has_infoframe);
11298
11299 DRM_DEBUG_KMS("requested mode:\n");
11300 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11301 DRM_DEBUG_KMS("adjusted mode:\n");
11302 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11303 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11304 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11305 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11306 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11307 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11308 crtc->num_scalers,
11309 pipe_config->scaler_state.scaler_users,
11310 pipe_config->scaler_state.scaler_id);
11311 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11312 pipe_config->gmch_pfit.control,
11313 pipe_config->gmch_pfit.pgm_ratios,
11314 pipe_config->gmch_pfit.lvds_border_bits);
11315 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11316 pipe_config->pch_pfit.pos,
11317 pipe_config->pch_pfit.size,
11318 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11319 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11320 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11321
11322 if (IS_BROXTON(dev)) {
11323 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11324 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11325 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11326 pipe_config->ddi_pll_sel,
11327 pipe_config->dpll_hw_state.ebb0,
11328 pipe_config->dpll_hw_state.pll0,
11329 pipe_config->dpll_hw_state.pll1,
11330 pipe_config->dpll_hw_state.pll2,
11331 pipe_config->dpll_hw_state.pll3,
11332 pipe_config->dpll_hw_state.pll6,
11333 pipe_config->dpll_hw_state.pll8,
11334 pipe_config->dpll_hw_state.pcsdw12);
11335 } else if (IS_SKYLAKE(dev)) {
11336 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11337 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11338 pipe_config->ddi_pll_sel,
11339 pipe_config->dpll_hw_state.ctrl1,
11340 pipe_config->dpll_hw_state.cfgcr1,
11341 pipe_config->dpll_hw_state.cfgcr2);
11342 } else if (HAS_DDI(dev)) {
11343 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11344 pipe_config->ddi_pll_sel,
11345 pipe_config->dpll_hw_state.wrpll);
11346 } else {
11347 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11348 "fp0: 0x%x, fp1: 0x%x\n",
11349 pipe_config->dpll_hw_state.dpll,
11350 pipe_config->dpll_hw_state.dpll_md,
11351 pipe_config->dpll_hw_state.fp0,
11352 pipe_config->dpll_hw_state.fp1);
11353 }
11354
11355 DRM_DEBUG_KMS("planes on this crtc\n");
11356 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11357 intel_plane = to_intel_plane(plane);
11358 if (intel_plane->pipe != crtc->pipe)
11359 continue;
11360
11361 state = to_intel_plane_state(plane->state);
11362 fb = state->base.fb;
11363 if (!fb) {
11364 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11365 "disabled, scaler_id = %d\n",
11366 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11367 plane->base.id, intel_plane->pipe,
11368 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11369 drm_plane_index(plane), state->scaler_id);
11370 continue;
11371 }
11372
11373 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11374 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11375 plane->base.id, intel_plane->pipe,
11376 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11377 drm_plane_index(plane));
11378 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11379 fb->base.id, fb->width, fb->height, fb->pixel_format);
11380 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11381 state->scaler_id,
11382 state->src.x1 >> 16, state->src.y1 >> 16,
11383 drm_rect_width(&state->src) >> 16,
11384 drm_rect_height(&state->src) >> 16,
11385 state->dst.x1, state->dst.y1,
11386 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11387 }
11388 }
11389
11390 static bool encoders_cloneable(const struct intel_encoder *a,
11391 const struct intel_encoder *b)
11392 {
11393 /* masks could be asymmetric, so check both ways */
11394 return a == b || (a->cloneable & (1 << b->type) &&
11395 b->cloneable & (1 << a->type));
11396 }
11397
11398 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11399 struct intel_crtc *crtc,
11400 struct intel_encoder *encoder)
11401 {
11402 struct intel_encoder *source_encoder;
11403 struct drm_connector *connector;
11404 struct drm_connector_state *connector_state;
11405 int i;
11406
11407 for_each_connector_in_state(state, connector, connector_state, i) {
11408 if (connector_state->crtc != &crtc->base)
11409 continue;
11410
11411 source_encoder =
11412 to_intel_encoder(connector_state->best_encoder);
11413 if (!encoders_cloneable(encoder, source_encoder))
11414 return false;
11415 }
11416
11417 return true;
11418 }
11419
11420 static bool check_encoder_cloning(struct drm_atomic_state *state,
11421 struct intel_crtc *crtc)
11422 {
11423 struct intel_encoder *encoder;
11424 struct drm_connector *connector;
11425 struct drm_connector_state *connector_state;
11426 int i;
11427
11428 for_each_connector_in_state(state, connector, connector_state, i) {
11429 if (connector_state->crtc != &crtc->base)
11430 continue;
11431
11432 encoder = to_intel_encoder(connector_state->best_encoder);
11433 if (!check_single_encoder_cloning(state, crtc, encoder))
11434 return false;
11435 }
11436
11437 return true;
11438 }
11439
11440 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11441 {
11442 struct drm_device *dev = state->dev;
11443 struct intel_encoder *encoder;
11444 struct drm_connector *connector;
11445 struct drm_connector_state *connector_state;
11446 unsigned int used_ports = 0;
11447 int i;
11448
11449 /*
11450 * Walk the connector list instead of the encoder
11451 * list to detect the problem on ddi platforms
11452 * where there's just one encoder per digital port.
11453 */
11454 for_each_connector_in_state(state, connector, connector_state, i) {
11455 if (!connector_state->best_encoder)
11456 continue;
11457
11458 encoder = to_intel_encoder(connector_state->best_encoder);
11459
11460 WARN_ON(!connector_state->crtc);
11461
11462 switch (encoder->type) {
11463 unsigned int port_mask;
11464 case INTEL_OUTPUT_UNKNOWN:
11465 if (WARN_ON(!HAS_DDI(dev)))
11466 break;
11467 case INTEL_OUTPUT_DISPLAYPORT:
11468 case INTEL_OUTPUT_HDMI:
11469 case INTEL_OUTPUT_EDP:
11470 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11471
11472 /* the same port mustn't appear more than once */
11473 if (used_ports & port_mask)
11474 return false;
11475
11476 used_ports |= port_mask;
11477 default:
11478 break;
11479 }
11480 }
11481
11482 return true;
11483 }
11484
11485 static void
11486 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11487 {
11488 struct drm_crtc_state tmp_state;
11489 struct intel_crtc_scaler_state scaler_state;
11490 struct intel_dpll_hw_state dpll_hw_state;
11491 enum intel_dpll_id shared_dpll;
11492 uint32_t ddi_pll_sel;
11493
11494 /* FIXME: before the switch to atomic started, a new pipe_config was
11495 * kzalloc'd. Code that depends on any field being zero should be
11496 * fixed, so that the crtc_state can be safely duplicated. For now,
11497 * only fields that are know to not cause problems are preserved. */
11498
11499 tmp_state = crtc_state->base;
11500 scaler_state = crtc_state->scaler_state;
11501 shared_dpll = crtc_state->shared_dpll;
11502 dpll_hw_state = crtc_state->dpll_hw_state;
11503 ddi_pll_sel = crtc_state->ddi_pll_sel;
11504
11505 memset(crtc_state, 0, sizeof *crtc_state);
11506
11507 crtc_state->base = tmp_state;
11508 crtc_state->scaler_state = scaler_state;
11509 crtc_state->shared_dpll = shared_dpll;
11510 crtc_state->dpll_hw_state = dpll_hw_state;
11511 crtc_state->ddi_pll_sel = ddi_pll_sel;
11512 }
11513
11514 static int
11515 intel_modeset_pipe_config(struct drm_crtc *crtc,
11516 struct drm_atomic_state *state,
11517 struct intel_crtc_state *pipe_config)
11518 {
11519 struct intel_encoder *encoder;
11520 struct drm_connector *connector;
11521 struct drm_connector_state *connector_state;
11522 int base_bpp, ret = -EINVAL;
11523 int i;
11524 bool retry = true;
11525
11526 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11527 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11528 return -EINVAL;
11529 }
11530
11531 if (!check_digital_port_conflicts(state)) {
11532 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11533 return -EINVAL;
11534 }
11535
11536 clear_intel_crtc_state(pipe_config);
11537
11538 pipe_config->cpu_transcoder =
11539 (enum transcoder) to_intel_crtc(crtc)->pipe;
11540
11541 /*
11542 * Sanitize sync polarity flags based on requested ones. If neither
11543 * positive or negative polarity is requested, treat this as meaning
11544 * negative polarity.
11545 */
11546 if (!(pipe_config->base.adjusted_mode.flags &
11547 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11548 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11549
11550 if (!(pipe_config->base.adjusted_mode.flags &
11551 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11552 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11553
11554 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11555 * plane pixel format and any sink constraints into account. Returns the
11556 * source plane bpp so that dithering can be selected on mismatches
11557 * after encoders and crtc also have had their say. */
11558 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11559 pipe_config);
11560 if (base_bpp < 0)
11561 goto fail;
11562
11563 /*
11564 * Determine the real pipe dimensions. Note that stereo modes can
11565 * increase the actual pipe size due to the frame doubling and
11566 * insertion of additional space for blanks between the frame. This
11567 * is stored in the crtc timings. We use the requested mode to do this
11568 * computation to clearly distinguish it from the adjusted mode, which
11569 * can be changed by the connectors in the below retry loop.
11570 */
11571 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11572 &pipe_config->pipe_src_w,
11573 &pipe_config->pipe_src_h);
11574
11575 encoder_retry:
11576 /* Ensure the port clock defaults are reset when retrying. */
11577 pipe_config->port_clock = 0;
11578 pipe_config->pixel_multiplier = 1;
11579
11580 /* Fill in default crtc timings, allow encoders to overwrite them. */
11581 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11582 CRTC_STEREO_DOUBLE);
11583
11584 /* Pass our mode to the connectors and the CRTC to give them a chance to
11585 * adjust it according to limitations or connector properties, and also
11586 * a chance to reject the mode entirely.
11587 */
11588 for_each_connector_in_state(state, connector, connector_state, i) {
11589 if (connector_state->crtc != crtc)
11590 continue;
11591
11592 encoder = to_intel_encoder(connector_state->best_encoder);
11593
11594 if (!(encoder->compute_config(encoder, pipe_config))) {
11595 DRM_DEBUG_KMS("Encoder config failure\n");
11596 goto fail;
11597 }
11598 }
11599
11600 /* Set default port clock if not overwritten by the encoder. Needs to be
11601 * done afterwards in case the encoder adjusts the mode. */
11602 if (!pipe_config->port_clock)
11603 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11604 * pipe_config->pixel_multiplier;
11605
11606 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11607 if (ret < 0) {
11608 DRM_DEBUG_KMS("CRTC fixup failed\n");
11609 goto fail;
11610 }
11611
11612 if (ret == RETRY) {
11613 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11614 ret = -EINVAL;
11615 goto fail;
11616 }
11617
11618 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11619 retry = false;
11620 goto encoder_retry;
11621 }
11622
11623 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11624 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11625 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11626
11627 return 0;
11628 fail:
11629 return ret;
11630 }
11631
11632 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11633 {
11634 struct drm_encoder *encoder;
11635 struct drm_device *dev = crtc->dev;
11636
11637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11638 if (encoder->crtc == crtc)
11639 return true;
11640
11641 return false;
11642 }
11643
11644 static bool
11645 needs_modeset(struct drm_crtc_state *state)
11646 {
11647 return state->mode_changed || state->active_changed;
11648 }
11649
11650 static void
11651 intel_modeset_update_state(struct drm_atomic_state *state)
11652 {
11653 struct drm_device *dev = state->dev;
11654 struct drm_i915_private *dev_priv = dev->dev_private;
11655 struct intel_encoder *intel_encoder;
11656 struct drm_crtc *crtc;
11657 struct drm_crtc_state *crtc_state;
11658 struct drm_connector *connector;
11659 int i;
11660
11661 intel_shared_dpll_commit(dev_priv);
11662
11663 for_each_intel_encoder(dev, intel_encoder) {
11664 if (!intel_encoder->base.crtc)
11665 continue;
11666
11667 for_each_crtc_in_state(state, crtc, crtc_state, i)
11668 if (crtc == intel_encoder->base.crtc)
11669 break;
11670
11671 if (crtc != intel_encoder->base.crtc)
11672 continue;
11673
11674 if (crtc_state->enable && needs_modeset(crtc_state))
11675 intel_encoder->connectors_active = false;
11676 }
11677
11678 drm_atomic_helper_swap_state(state->dev, state);
11679 intel_modeset_fixup_state(state);
11680
11681 /* Double check state. */
11682 for_each_crtc(dev, crtc) {
11683 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11684 }
11685
11686 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11687 if (!connector->encoder || !connector->encoder->crtc)
11688 continue;
11689
11690 for_each_crtc_in_state(state, crtc, crtc_state, i)
11691 if (crtc == connector->encoder->crtc)
11692 break;
11693
11694 if (crtc != connector->encoder->crtc)
11695 continue;
11696
11697 if (crtc->state->enable && needs_modeset(crtc->state)) {
11698 struct drm_property *dpms_property =
11699 dev->mode_config.dpms_property;
11700
11701 connector->dpms = DRM_MODE_DPMS_ON;
11702 drm_object_property_set_value(&connector->base,
11703 dpms_property,
11704 DRM_MODE_DPMS_ON);
11705
11706 intel_encoder = to_intel_encoder(connector->encoder);
11707 intel_encoder->connectors_active = true;
11708 }
11709 }
11710
11711 }
11712
11713 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11714 {
11715 int diff;
11716
11717 if (clock1 == clock2)
11718 return true;
11719
11720 if (!clock1 || !clock2)
11721 return false;
11722
11723 diff = abs(clock1 - clock2);
11724
11725 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11726 return true;
11727
11728 return false;
11729 }
11730
11731 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11732 list_for_each_entry((intel_crtc), \
11733 &(dev)->mode_config.crtc_list, \
11734 base.head) \
11735 if (mask & (1 <<(intel_crtc)->pipe))
11736
11737 static bool
11738 intel_pipe_config_compare(struct drm_device *dev,
11739 struct intel_crtc_state *current_config,
11740 struct intel_crtc_state *pipe_config)
11741 {
11742 #define PIPE_CONF_CHECK_X(name) \
11743 if (current_config->name != pipe_config->name) { \
11744 DRM_ERROR("mismatch in " #name " " \
11745 "(expected 0x%08x, found 0x%08x)\n", \
11746 current_config->name, \
11747 pipe_config->name); \
11748 return false; \
11749 }
11750
11751 #define PIPE_CONF_CHECK_I(name) \
11752 if (current_config->name != pipe_config->name) { \
11753 DRM_ERROR("mismatch in " #name " " \
11754 "(expected %i, found %i)\n", \
11755 current_config->name, \
11756 pipe_config->name); \
11757 return false; \
11758 }
11759
11760 /* This is required for BDW+ where there is only one set of registers for
11761 * switching between high and low RR.
11762 * This macro can be used whenever a comparison has to be made between one
11763 * hw state and multiple sw state variables.
11764 */
11765 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11766 if ((current_config->name != pipe_config->name) && \
11767 (current_config->alt_name != pipe_config->name)) { \
11768 DRM_ERROR("mismatch in " #name " " \
11769 "(expected %i or %i, found %i)\n", \
11770 current_config->name, \
11771 current_config->alt_name, \
11772 pipe_config->name); \
11773 return false; \
11774 }
11775
11776 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11777 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11778 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11779 "(expected %i, found %i)\n", \
11780 current_config->name & (mask), \
11781 pipe_config->name & (mask)); \
11782 return false; \
11783 }
11784
11785 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11786 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11787 DRM_ERROR("mismatch in " #name " " \
11788 "(expected %i, found %i)\n", \
11789 current_config->name, \
11790 pipe_config->name); \
11791 return false; \
11792 }
11793
11794 #define PIPE_CONF_QUIRK(quirk) \
11795 ((current_config->quirks | pipe_config->quirks) & (quirk))
11796
11797 PIPE_CONF_CHECK_I(cpu_transcoder);
11798
11799 PIPE_CONF_CHECK_I(has_pch_encoder);
11800 PIPE_CONF_CHECK_I(fdi_lanes);
11801 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11802 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11803 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11804 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11805 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11806
11807 PIPE_CONF_CHECK_I(has_dp_encoder);
11808
11809 if (INTEL_INFO(dev)->gen < 8) {
11810 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11811 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11812 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11813 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11814 PIPE_CONF_CHECK_I(dp_m_n.tu);
11815
11816 if (current_config->has_drrs) {
11817 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11818 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11819 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11820 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11821 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11822 }
11823 } else {
11824 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11825 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11826 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11827 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11828 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11829 }
11830
11831 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11832 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11833 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11834 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11835 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11836 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11837
11838 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11839 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11840 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11841 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11842 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11843 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11844
11845 PIPE_CONF_CHECK_I(pixel_multiplier);
11846 PIPE_CONF_CHECK_I(has_hdmi_sink);
11847 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11848 IS_VALLEYVIEW(dev))
11849 PIPE_CONF_CHECK_I(limited_color_range);
11850 PIPE_CONF_CHECK_I(has_infoframe);
11851
11852 PIPE_CONF_CHECK_I(has_audio);
11853
11854 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11855 DRM_MODE_FLAG_INTERLACE);
11856
11857 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11858 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11859 DRM_MODE_FLAG_PHSYNC);
11860 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11861 DRM_MODE_FLAG_NHSYNC);
11862 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11863 DRM_MODE_FLAG_PVSYNC);
11864 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11865 DRM_MODE_FLAG_NVSYNC);
11866 }
11867
11868 PIPE_CONF_CHECK_I(pipe_src_w);
11869 PIPE_CONF_CHECK_I(pipe_src_h);
11870
11871 /*
11872 * FIXME: BIOS likes to set up a cloned config with lvds+external
11873 * screen. Since we don't yet re-compute the pipe config when moving
11874 * just the lvds port away to another pipe the sw tracking won't match.
11875 *
11876 * Proper atomic modesets with recomputed global state will fix this.
11877 * Until then just don't check gmch state for inherited modes.
11878 */
11879 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11880 PIPE_CONF_CHECK_I(gmch_pfit.control);
11881 /* pfit ratios are autocomputed by the hw on gen4+ */
11882 if (INTEL_INFO(dev)->gen < 4)
11883 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11884 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11885 }
11886
11887 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11888 if (current_config->pch_pfit.enabled) {
11889 PIPE_CONF_CHECK_I(pch_pfit.pos);
11890 PIPE_CONF_CHECK_I(pch_pfit.size);
11891 }
11892
11893 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11894
11895 /* BDW+ don't expose a synchronous way to read the state */
11896 if (IS_HASWELL(dev))
11897 PIPE_CONF_CHECK_I(ips_enabled);
11898
11899 PIPE_CONF_CHECK_I(double_wide);
11900
11901 PIPE_CONF_CHECK_X(ddi_pll_sel);
11902
11903 PIPE_CONF_CHECK_I(shared_dpll);
11904 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11905 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11906 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11907 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11908 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11909 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11910 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11911 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11912
11913 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11914 PIPE_CONF_CHECK_I(pipe_bpp);
11915
11916 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11917 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11918
11919 #undef PIPE_CONF_CHECK_X
11920 #undef PIPE_CONF_CHECK_I
11921 #undef PIPE_CONF_CHECK_I_ALT
11922 #undef PIPE_CONF_CHECK_FLAGS
11923 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11924 #undef PIPE_CONF_QUIRK
11925
11926 return true;
11927 }
11928
11929 static void check_wm_state(struct drm_device *dev)
11930 {
11931 struct drm_i915_private *dev_priv = dev->dev_private;
11932 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11933 struct intel_crtc *intel_crtc;
11934 int plane;
11935
11936 if (INTEL_INFO(dev)->gen < 9)
11937 return;
11938
11939 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11940 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11941
11942 for_each_intel_crtc(dev, intel_crtc) {
11943 struct skl_ddb_entry *hw_entry, *sw_entry;
11944 const enum pipe pipe = intel_crtc->pipe;
11945
11946 if (!intel_crtc->active)
11947 continue;
11948
11949 /* planes */
11950 for_each_plane(dev_priv, pipe, plane) {
11951 hw_entry = &hw_ddb.plane[pipe][plane];
11952 sw_entry = &sw_ddb->plane[pipe][plane];
11953
11954 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11955 continue;
11956
11957 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11958 "(expected (%u,%u), found (%u,%u))\n",
11959 pipe_name(pipe), plane + 1,
11960 sw_entry->start, sw_entry->end,
11961 hw_entry->start, hw_entry->end);
11962 }
11963
11964 /* cursor */
11965 hw_entry = &hw_ddb.cursor[pipe];
11966 sw_entry = &sw_ddb->cursor[pipe];
11967
11968 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11969 continue;
11970
11971 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11972 "(expected (%u,%u), found (%u,%u))\n",
11973 pipe_name(pipe),
11974 sw_entry->start, sw_entry->end,
11975 hw_entry->start, hw_entry->end);
11976 }
11977 }
11978
11979 static void
11980 check_connector_state(struct drm_device *dev)
11981 {
11982 struct intel_connector *connector;
11983
11984 for_each_intel_connector(dev, connector) {
11985 /* This also checks the encoder/connector hw state with the
11986 * ->get_hw_state callbacks. */
11987 intel_connector_check_state(connector);
11988
11989 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11990 "connector's staged encoder doesn't match current encoder\n");
11991 }
11992 }
11993
11994 static void
11995 check_encoder_state(struct drm_device *dev)
11996 {
11997 struct intel_encoder *encoder;
11998 struct intel_connector *connector;
11999
12000 for_each_intel_encoder(dev, encoder) {
12001 bool enabled = false;
12002 bool active = false;
12003 enum pipe pipe, tracked_pipe;
12004
12005 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12006 encoder->base.base.id,
12007 encoder->base.name);
12008
12009 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
12010 "encoder's stage crtc doesn't match current crtc\n");
12011 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
12012 "encoder's active_connectors set, but no crtc\n");
12013
12014 for_each_intel_connector(dev, connector) {
12015 if (connector->base.encoder != &encoder->base)
12016 continue;
12017 enabled = true;
12018 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12019 active = true;
12020 }
12021 /*
12022 * for MST connectors if we unplug the connector is gone
12023 * away but the encoder is still connected to a crtc
12024 * until a modeset happens in response to the hotplug.
12025 */
12026 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12027 continue;
12028
12029 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12030 "encoder's enabled state mismatch "
12031 "(expected %i, found %i)\n",
12032 !!encoder->base.crtc, enabled);
12033 I915_STATE_WARN(active && !encoder->base.crtc,
12034 "active encoder with no crtc\n");
12035
12036 I915_STATE_WARN(encoder->connectors_active != active,
12037 "encoder's computed active state doesn't match tracked active state "
12038 "(expected %i, found %i)\n", active, encoder->connectors_active);
12039
12040 active = encoder->get_hw_state(encoder, &pipe);
12041 I915_STATE_WARN(active != encoder->connectors_active,
12042 "encoder's hw state doesn't match sw tracking "
12043 "(expected %i, found %i)\n",
12044 encoder->connectors_active, active);
12045
12046 if (!encoder->base.crtc)
12047 continue;
12048
12049 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12050 I915_STATE_WARN(active && pipe != tracked_pipe,
12051 "active encoder's pipe doesn't match"
12052 "(expected %i, found %i)\n",
12053 tracked_pipe, pipe);
12054
12055 }
12056 }
12057
12058 static void
12059 check_crtc_state(struct drm_device *dev)
12060 {
12061 struct drm_i915_private *dev_priv = dev->dev_private;
12062 struct intel_crtc *crtc;
12063 struct intel_encoder *encoder;
12064 struct intel_crtc_state pipe_config;
12065
12066 for_each_intel_crtc(dev, crtc) {
12067 bool enabled = false;
12068 bool active = false;
12069
12070 memset(&pipe_config, 0, sizeof(pipe_config));
12071
12072 DRM_DEBUG_KMS("[CRTC:%d]\n",
12073 crtc->base.base.id);
12074
12075 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12076 "active crtc, but not enabled in sw tracking\n");
12077
12078 for_each_intel_encoder(dev, encoder) {
12079 if (encoder->base.crtc != &crtc->base)
12080 continue;
12081 enabled = true;
12082 if (encoder->connectors_active)
12083 active = true;
12084 }
12085
12086 I915_STATE_WARN(active != crtc->active,
12087 "crtc's computed active state doesn't match tracked active state "
12088 "(expected %i, found %i)\n", active, crtc->active);
12089 I915_STATE_WARN(enabled != crtc->base.state->enable,
12090 "crtc's computed enabled state doesn't match tracked enabled state "
12091 "(expected %i, found %i)\n", enabled,
12092 crtc->base.state->enable);
12093
12094 active = dev_priv->display.get_pipe_config(crtc,
12095 &pipe_config);
12096
12097 /* hw state is inconsistent with the pipe quirk */
12098 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12099 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12100 active = crtc->active;
12101
12102 for_each_intel_encoder(dev, encoder) {
12103 enum pipe pipe;
12104 if (encoder->base.crtc != &crtc->base)
12105 continue;
12106 if (encoder->get_hw_state(encoder, &pipe))
12107 encoder->get_config(encoder, &pipe_config);
12108 }
12109
12110 I915_STATE_WARN(crtc->active != active,
12111 "crtc active state doesn't match with hw state "
12112 "(expected %i, found %i)\n", crtc->active, active);
12113
12114 if (active &&
12115 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12116 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12117 intel_dump_pipe_config(crtc, &pipe_config,
12118 "[hw state]");
12119 intel_dump_pipe_config(crtc, crtc->config,
12120 "[sw state]");
12121 }
12122 }
12123 }
12124
12125 static void
12126 check_shared_dpll_state(struct drm_device *dev)
12127 {
12128 struct drm_i915_private *dev_priv = dev->dev_private;
12129 struct intel_crtc *crtc;
12130 struct intel_dpll_hw_state dpll_hw_state;
12131 int i;
12132
12133 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12134 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12135 int enabled_crtcs = 0, active_crtcs = 0;
12136 bool active;
12137
12138 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12139
12140 DRM_DEBUG_KMS("%s\n", pll->name);
12141
12142 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12143
12144 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12145 "more active pll users than references: %i vs %i\n",
12146 pll->active, hweight32(pll->config.crtc_mask));
12147 I915_STATE_WARN(pll->active && !pll->on,
12148 "pll in active use but not on in sw tracking\n");
12149 I915_STATE_WARN(pll->on && !pll->active,
12150 "pll in on but not on in use in sw tracking\n");
12151 I915_STATE_WARN(pll->on != active,
12152 "pll on state mismatch (expected %i, found %i)\n",
12153 pll->on, active);
12154
12155 for_each_intel_crtc(dev, crtc) {
12156 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12157 enabled_crtcs++;
12158 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12159 active_crtcs++;
12160 }
12161 I915_STATE_WARN(pll->active != active_crtcs,
12162 "pll active crtcs mismatch (expected %i, found %i)\n",
12163 pll->active, active_crtcs);
12164 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12165 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12166 hweight32(pll->config.crtc_mask), enabled_crtcs);
12167
12168 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12169 sizeof(dpll_hw_state)),
12170 "pll hw state mismatch\n");
12171 }
12172 }
12173
12174 void
12175 intel_modeset_check_state(struct drm_device *dev)
12176 {
12177 check_wm_state(dev);
12178 check_connector_state(dev);
12179 check_encoder_state(dev);
12180 check_crtc_state(dev);
12181 check_shared_dpll_state(dev);
12182 }
12183
12184 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12185 int dotclock)
12186 {
12187 /*
12188 * FDI already provided one idea for the dotclock.
12189 * Yell if the encoder disagrees.
12190 */
12191 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12192 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12193 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12194 }
12195
12196 static void update_scanline_offset(struct intel_crtc *crtc)
12197 {
12198 struct drm_device *dev = crtc->base.dev;
12199
12200 /*
12201 * The scanline counter increments at the leading edge of hsync.
12202 *
12203 * On most platforms it starts counting from vtotal-1 on the
12204 * first active line. That means the scanline counter value is
12205 * always one less than what we would expect. Ie. just after
12206 * start of vblank, which also occurs at start of hsync (on the
12207 * last active line), the scanline counter will read vblank_start-1.
12208 *
12209 * On gen2 the scanline counter starts counting from 1 instead
12210 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12211 * to keep the value positive), instead of adding one.
12212 *
12213 * On HSW+ the behaviour of the scanline counter depends on the output
12214 * type. For DP ports it behaves like most other platforms, but on HDMI
12215 * there's an extra 1 line difference. So we need to add two instead of
12216 * one to the value.
12217 */
12218 if (IS_GEN2(dev)) {
12219 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12220 int vtotal;
12221
12222 vtotal = mode->crtc_vtotal;
12223 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12224 vtotal /= 2;
12225
12226 crtc->scanline_offset = vtotal - 1;
12227 } else if (HAS_DDI(dev) &&
12228 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12229 crtc->scanline_offset = 2;
12230 } else
12231 crtc->scanline_offset = 1;
12232 }
12233
12234 static struct intel_crtc_state *
12235 intel_modeset_compute_config(struct drm_crtc *crtc,
12236 struct drm_atomic_state *state)
12237 {
12238 struct intel_crtc_state *pipe_config;
12239 int ret = 0;
12240
12241 ret = drm_atomic_add_affected_connectors(state, crtc);
12242 if (ret)
12243 return ERR_PTR(ret);
12244
12245 ret = drm_atomic_helper_check_modeset(state->dev, state);
12246 if (ret)
12247 return ERR_PTR(ret);
12248
12249 /*
12250 * Note this needs changes when we start tracking multiple modes
12251 * and crtcs. At that point we'll need to compute the whole config
12252 * (i.e. one pipe_config for each crtc) rather than just the one
12253 * for this crtc.
12254 */
12255 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12256 if (IS_ERR(pipe_config))
12257 return pipe_config;
12258
12259 if (!pipe_config->base.enable)
12260 return pipe_config;
12261
12262 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12263 if (ret)
12264 return ERR_PTR(ret);
12265
12266 /* Check things that can only be changed through modeset */
12267 if (pipe_config->has_audio !=
12268 to_intel_crtc(crtc)->config->has_audio)
12269 pipe_config->base.mode_changed = true;
12270
12271 /*
12272 * Note we have an issue here with infoframes: current code
12273 * only updates them on the full mode set path per hw
12274 * requirements. So here we should be checking for any
12275 * required changes and forcing a mode set.
12276 */
12277
12278 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12279
12280 ret = drm_atomic_helper_check_planes(state->dev, state);
12281 if (ret)
12282 return ERR_PTR(ret);
12283
12284 return pipe_config;
12285 }
12286
12287 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12288 {
12289 struct drm_device *dev = state->dev;
12290 struct drm_i915_private *dev_priv = to_i915(dev);
12291 unsigned clear_pipes = 0;
12292 struct intel_crtc *intel_crtc;
12293 struct intel_crtc_state *intel_crtc_state;
12294 struct drm_crtc *crtc;
12295 struct drm_crtc_state *crtc_state;
12296 int ret = 0;
12297 int i;
12298
12299 if (!dev_priv->display.crtc_compute_clock)
12300 return 0;
12301
12302 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12303 intel_crtc = to_intel_crtc(crtc);
12304 intel_crtc_state = to_intel_crtc_state(crtc_state);
12305
12306 if (needs_modeset(crtc_state)) {
12307 clear_pipes |= 1 << intel_crtc->pipe;
12308 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12309 }
12310 }
12311
12312 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12313 if (ret)
12314 goto done;
12315
12316 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12317 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12318 continue;
12319
12320 intel_crtc = to_intel_crtc(crtc);
12321 intel_crtc_state = to_intel_crtc_state(crtc_state);
12322
12323 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12324 intel_crtc_state);
12325 if (ret) {
12326 intel_shared_dpll_abort_config(dev_priv);
12327 goto done;
12328 }
12329 }
12330
12331 done:
12332 return ret;
12333 }
12334
12335 /* Code that should eventually be part of atomic_check() */
12336 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12337 {
12338 struct drm_device *dev = state->dev;
12339 int ret;
12340
12341 /*
12342 * See if the config requires any additional preparation, e.g.
12343 * to adjust global state with pipes off. We need to do this
12344 * here so we can get the modeset_pipe updated config for the new
12345 * mode set on this crtc. For other crtcs we need to use the
12346 * adjusted_mode bits in the crtc directly.
12347 */
12348 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12349 ret = valleyview_modeset_global_pipes(state);
12350 if (ret)
12351 return ret;
12352 }
12353
12354 ret = __intel_set_mode_setup_plls(state);
12355 if (ret)
12356 return ret;
12357
12358 return 0;
12359 }
12360
12361 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12362 struct intel_crtc_state *pipe_config)
12363 {
12364 struct drm_device *dev = modeset_crtc->dev;
12365 struct drm_i915_private *dev_priv = dev->dev_private;
12366 struct drm_atomic_state *state = pipe_config->base.state;
12367 struct drm_crtc *crtc;
12368 struct drm_crtc_state *crtc_state;
12369 int ret = 0;
12370 int i;
12371
12372 ret = __intel_set_mode_checks(state);
12373 if (ret < 0)
12374 return ret;
12375
12376 ret = drm_atomic_helper_prepare_planes(dev, state);
12377 if (ret)
12378 return ret;
12379
12380 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12381 if (!needs_modeset(crtc_state))
12382 continue;
12383
12384 if (!crtc_state->enable) {
12385 intel_crtc_disable(crtc);
12386 } else if (crtc->state->enable) {
12387 intel_crtc_disable_planes(crtc);
12388 dev_priv->display.crtc_disable(crtc);
12389 }
12390 }
12391
12392 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12393 * to set it here already despite that we pass it down the callchain.
12394 *
12395 * Note we'll need to fix this up when we start tracking multiple
12396 * pipes; here we assume a single modeset_pipe and only track the
12397 * single crtc and mode.
12398 */
12399 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12400 modeset_crtc->mode = pipe_config->base.mode;
12401
12402 /*
12403 * Calculate and store various constants which
12404 * are later needed by vblank and swap-completion
12405 * timestamping. They are derived from true hwmode.
12406 */
12407 drm_calc_timestamping_constants(modeset_crtc,
12408 &pipe_config->base.adjusted_mode);
12409 }
12410
12411 /* Only after disabling all output pipelines that will be changed can we
12412 * update the the output configuration. */
12413 intel_modeset_update_state(state);
12414
12415 /* The state has been swaped above, so state actually contains the
12416 * old state now. */
12417
12418 modeset_update_crtc_power_domains(state);
12419
12420 drm_atomic_helper_commit_planes(dev, state);
12421
12422 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12423 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12424 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12425 continue;
12426
12427 update_scanline_offset(to_intel_crtc(crtc));
12428
12429 dev_priv->display.crtc_enable(crtc);
12430 intel_crtc_enable_planes(crtc);
12431 }
12432
12433 /* FIXME: add subpixel order */
12434
12435 drm_atomic_helper_cleanup_planes(dev, state);
12436
12437 drm_atomic_state_free(state);
12438
12439 return 0;
12440 }
12441
12442 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12443 struct intel_crtc_state *pipe_config)
12444 {
12445 int ret;
12446
12447 ret = __intel_set_mode(crtc, pipe_config);
12448
12449 if (ret == 0)
12450 intel_modeset_check_state(crtc->dev);
12451
12452 return ret;
12453 }
12454
12455 static int intel_set_mode(struct drm_crtc *crtc,
12456 struct drm_atomic_state *state)
12457 {
12458 struct intel_crtc_state *pipe_config;
12459 int ret = 0;
12460
12461 pipe_config = intel_modeset_compute_config(crtc, state);
12462 if (IS_ERR(pipe_config)) {
12463 ret = PTR_ERR(pipe_config);
12464 goto out;
12465 }
12466
12467 ret = intel_set_mode_with_config(crtc, pipe_config);
12468 if (ret)
12469 goto out;
12470
12471 out:
12472 return ret;
12473 }
12474
12475 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12476 {
12477 struct drm_device *dev = crtc->dev;
12478 struct drm_atomic_state *state;
12479 struct intel_crtc *intel_crtc;
12480 struct intel_encoder *encoder;
12481 struct intel_connector *connector;
12482 struct drm_connector_state *connector_state;
12483 struct intel_crtc_state *crtc_state;
12484 int ret;
12485
12486 state = drm_atomic_state_alloc(dev);
12487 if (!state) {
12488 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12489 crtc->base.id);
12490 return;
12491 }
12492
12493 state->acquire_ctx = dev->mode_config.acquire_ctx;
12494
12495 /* The force restore path in the HW readout code relies on the staged
12496 * config still keeping the user requested config while the actual
12497 * state has been overwritten by the configuration read from HW. We
12498 * need to copy the staged config to the atomic state, otherwise the
12499 * mode set will just reapply the state the HW is already in. */
12500 for_each_intel_encoder(dev, encoder) {
12501 if (&encoder->new_crtc->base != crtc)
12502 continue;
12503
12504 for_each_intel_connector(dev, connector) {
12505 if (connector->new_encoder != encoder)
12506 continue;
12507
12508 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12509 if (IS_ERR(connector_state)) {
12510 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12511 connector->base.base.id,
12512 connector->base.name,
12513 PTR_ERR(connector_state));
12514 continue;
12515 }
12516
12517 connector_state->crtc = crtc;
12518 connector_state->best_encoder = &encoder->base;
12519 }
12520 }
12521
12522 for_each_intel_crtc(dev, intel_crtc) {
12523 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12524 continue;
12525
12526 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12527 if (IS_ERR(crtc_state)) {
12528 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12529 intel_crtc->base.base.id,
12530 PTR_ERR(crtc_state));
12531 continue;
12532 }
12533
12534 crtc_state->base.active = crtc_state->base.enable =
12535 intel_crtc->new_enabled;
12536
12537 if (&intel_crtc->base == crtc)
12538 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12539 }
12540
12541 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12542 crtc->primary->fb, crtc->x, crtc->y);
12543
12544 ret = intel_set_mode(crtc, state);
12545 if (ret)
12546 drm_atomic_state_free(state);
12547 }
12548
12549 #undef for_each_intel_crtc_masked
12550
12551 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12552 struct drm_mode_set *set)
12553 {
12554 int ro;
12555
12556 for (ro = 0; ro < set->num_connectors; ro++)
12557 if (set->connectors[ro] == &connector->base)
12558 return true;
12559
12560 return false;
12561 }
12562
12563 static int
12564 intel_modeset_stage_output_state(struct drm_device *dev,
12565 struct drm_mode_set *set,
12566 struct drm_atomic_state *state)
12567 {
12568 struct intel_connector *connector;
12569 struct drm_connector *drm_connector;
12570 struct drm_connector_state *connector_state;
12571 struct drm_crtc *crtc;
12572 struct drm_crtc_state *crtc_state;
12573 int i, ret;
12574
12575 /* The upper layers ensure that we either disable a crtc or have a list
12576 * of connectors. For paranoia, double-check this. */
12577 WARN_ON(!set->fb && (set->num_connectors != 0));
12578 WARN_ON(set->fb && (set->num_connectors == 0));
12579
12580 for_each_intel_connector(dev, connector) {
12581 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12582
12583 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12584 continue;
12585
12586 connector_state =
12587 drm_atomic_get_connector_state(state, &connector->base);
12588 if (IS_ERR(connector_state))
12589 return PTR_ERR(connector_state);
12590
12591 if (in_mode_set) {
12592 int pipe = to_intel_crtc(set->crtc)->pipe;
12593 connector_state->best_encoder =
12594 &intel_find_encoder(connector, pipe)->base;
12595 }
12596
12597 if (connector->base.state->crtc != set->crtc)
12598 continue;
12599
12600 /* If we disable the crtc, disable all its connectors. Also, if
12601 * the connector is on the changing crtc but not on the new
12602 * connector list, disable it. */
12603 if (!set->fb || !in_mode_set) {
12604 connector_state->best_encoder = NULL;
12605
12606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12607 connector->base.base.id,
12608 connector->base.name);
12609 }
12610 }
12611 /* connector->new_encoder is now updated for all connectors. */
12612
12613 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12614 connector = to_intel_connector(drm_connector);
12615
12616 if (!connector_state->best_encoder) {
12617 ret = drm_atomic_set_crtc_for_connector(connector_state,
12618 NULL);
12619 if (ret)
12620 return ret;
12621
12622 continue;
12623 }
12624
12625 if (intel_connector_in_mode_set(connector, set)) {
12626 struct drm_crtc *crtc = connector->base.state->crtc;
12627
12628 /* If this connector was in a previous crtc, add it
12629 * to the state. We might need to disable it. */
12630 if (crtc) {
12631 crtc_state =
12632 drm_atomic_get_crtc_state(state, crtc);
12633 if (IS_ERR(crtc_state))
12634 return PTR_ERR(crtc_state);
12635 }
12636
12637 ret = drm_atomic_set_crtc_for_connector(connector_state,
12638 set->crtc);
12639 if (ret)
12640 return ret;
12641 }
12642
12643 /* Make sure the new CRTC will work with the encoder */
12644 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12645 connector_state->crtc)) {
12646 return -EINVAL;
12647 }
12648
12649 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12650 connector->base.base.id,
12651 connector->base.name,
12652 connector_state->crtc->base.id);
12653
12654 if (connector_state->best_encoder != &connector->encoder->base)
12655 connector->encoder =
12656 to_intel_encoder(connector_state->best_encoder);
12657 }
12658
12659 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12660 bool has_connectors;
12661
12662 ret = drm_atomic_add_affected_connectors(state, crtc);
12663 if (ret)
12664 return ret;
12665
12666 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12667 if (has_connectors != crtc_state->enable)
12668 crtc_state->enable =
12669 crtc_state->active = has_connectors;
12670 }
12671
12672 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12673 set->fb, set->x, set->y);
12674 if (ret)
12675 return ret;
12676
12677 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12678 if (IS_ERR(crtc_state))
12679 return PTR_ERR(crtc_state);
12680
12681 if (set->mode)
12682 drm_mode_copy(&crtc_state->mode, set->mode);
12683
12684 if (set->num_connectors)
12685 crtc_state->active = true;
12686
12687 return 0;
12688 }
12689
12690 static bool primary_plane_visible(struct drm_crtc *crtc)
12691 {
12692 struct intel_plane_state *plane_state =
12693 to_intel_plane_state(crtc->primary->state);
12694
12695 return plane_state->visible;
12696 }
12697
12698 static int intel_crtc_set_config(struct drm_mode_set *set)
12699 {
12700 struct drm_device *dev;
12701 struct drm_atomic_state *state = NULL;
12702 struct intel_crtc_state *pipe_config;
12703 bool primary_plane_was_visible;
12704 int ret;
12705
12706 BUG_ON(!set);
12707 BUG_ON(!set->crtc);
12708 BUG_ON(!set->crtc->helper_private);
12709
12710 /* Enforce sane interface api - has been abused by the fb helper. */
12711 BUG_ON(!set->mode && set->fb);
12712 BUG_ON(set->fb && set->num_connectors == 0);
12713
12714 if (set->fb) {
12715 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12716 set->crtc->base.id, set->fb->base.id,
12717 (int)set->num_connectors, set->x, set->y);
12718 } else {
12719 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12720 }
12721
12722 dev = set->crtc->dev;
12723
12724 state = drm_atomic_state_alloc(dev);
12725 if (!state)
12726 return -ENOMEM;
12727
12728 state->acquire_ctx = dev->mode_config.acquire_ctx;
12729
12730 ret = intel_modeset_stage_output_state(dev, set, state);
12731 if (ret)
12732 goto out;
12733
12734 pipe_config = intel_modeset_compute_config(set->crtc, state);
12735 if (IS_ERR(pipe_config)) {
12736 ret = PTR_ERR(pipe_config);
12737 goto out;
12738 }
12739
12740 intel_update_pipe_size(to_intel_crtc(set->crtc));
12741
12742 primary_plane_was_visible = primary_plane_visible(set->crtc);
12743
12744 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12745
12746 if (ret == 0 &&
12747 pipe_config->base.enable &&
12748 pipe_config->base.planes_changed &&
12749 !needs_modeset(&pipe_config->base)) {
12750 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12751
12752 /*
12753 * We need to make sure the primary plane is re-enabled if it
12754 * has previously been turned off.
12755 */
12756 if (ret == 0 && !primary_plane_was_visible &&
12757 primary_plane_visible(set->crtc)) {
12758 WARN_ON(!intel_crtc->active);
12759 intel_post_enable_primary(set->crtc);
12760 }
12761
12762 /*
12763 * In the fastboot case this may be our only check of the
12764 * state after boot. It would be better to only do it on
12765 * the first update, but we don't have a nice way of doing that
12766 * (and really, set_config isn't used much for high freq page
12767 * flipping, so increasing its cost here shouldn't be a big
12768 * deal).
12769 */
12770 if (i915.fastboot && ret == 0)
12771 intel_modeset_check_state(set->crtc->dev);
12772 }
12773
12774 if (ret) {
12775 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12776 set->crtc->base.id, ret);
12777 }
12778
12779 out:
12780 if (ret)
12781 drm_atomic_state_free(state);
12782 return ret;
12783 }
12784
12785 static const struct drm_crtc_funcs intel_crtc_funcs = {
12786 .gamma_set = intel_crtc_gamma_set,
12787 .set_config = intel_crtc_set_config,
12788 .destroy = intel_crtc_destroy,
12789 .page_flip = intel_crtc_page_flip,
12790 .atomic_duplicate_state = intel_crtc_duplicate_state,
12791 .atomic_destroy_state = intel_crtc_destroy_state,
12792 };
12793
12794 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12795 struct intel_shared_dpll *pll,
12796 struct intel_dpll_hw_state *hw_state)
12797 {
12798 uint32_t val;
12799
12800 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12801 return false;
12802
12803 val = I915_READ(PCH_DPLL(pll->id));
12804 hw_state->dpll = val;
12805 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12806 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12807
12808 return val & DPLL_VCO_ENABLE;
12809 }
12810
12811 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12812 struct intel_shared_dpll *pll)
12813 {
12814 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12815 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12816 }
12817
12818 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12819 struct intel_shared_dpll *pll)
12820 {
12821 /* PCH refclock must be enabled first */
12822 ibx_assert_pch_refclk_enabled(dev_priv);
12823
12824 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12825
12826 /* Wait for the clocks to stabilize. */
12827 POSTING_READ(PCH_DPLL(pll->id));
12828 udelay(150);
12829
12830 /* The pixel multiplier can only be updated once the
12831 * DPLL is enabled and the clocks are stable.
12832 *
12833 * So write it again.
12834 */
12835 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12836 POSTING_READ(PCH_DPLL(pll->id));
12837 udelay(200);
12838 }
12839
12840 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12841 struct intel_shared_dpll *pll)
12842 {
12843 struct drm_device *dev = dev_priv->dev;
12844 struct intel_crtc *crtc;
12845
12846 /* Make sure no transcoder isn't still depending on us. */
12847 for_each_intel_crtc(dev, crtc) {
12848 if (intel_crtc_to_shared_dpll(crtc) == pll)
12849 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12850 }
12851
12852 I915_WRITE(PCH_DPLL(pll->id), 0);
12853 POSTING_READ(PCH_DPLL(pll->id));
12854 udelay(200);
12855 }
12856
12857 static char *ibx_pch_dpll_names[] = {
12858 "PCH DPLL A",
12859 "PCH DPLL B",
12860 };
12861
12862 static void ibx_pch_dpll_init(struct drm_device *dev)
12863 {
12864 struct drm_i915_private *dev_priv = dev->dev_private;
12865 int i;
12866
12867 dev_priv->num_shared_dpll = 2;
12868
12869 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12870 dev_priv->shared_dplls[i].id = i;
12871 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12872 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12873 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12874 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12875 dev_priv->shared_dplls[i].get_hw_state =
12876 ibx_pch_dpll_get_hw_state;
12877 }
12878 }
12879
12880 static void intel_shared_dpll_init(struct drm_device *dev)
12881 {
12882 struct drm_i915_private *dev_priv = dev->dev_private;
12883
12884 if (HAS_DDI(dev))
12885 intel_ddi_pll_init(dev);
12886 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12887 ibx_pch_dpll_init(dev);
12888 else
12889 dev_priv->num_shared_dpll = 0;
12890
12891 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12892 }
12893
12894 /**
12895 * intel_wm_need_update - Check whether watermarks need updating
12896 * @plane: drm plane
12897 * @state: new plane state
12898 *
12899 * Check current plane state versus the new one to determine whether
12900 * watermarks need to be recalculated.
12901 *
12902 * Returns true or false.
12903 */
12904 bool intel_wm_need_update(struct drm_plane *plane,
12905 struct drm_plane_state *state)
12906 {
12907 /* Update watermarks on tiling changes. */
12908 if (!plane->state->fb || !state->fb ||
12909 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12910 plane->state->rotation != state->rotation)
12911 return true;
12912
12913 return false;
12914 }
12915
12916 /**
12917 * intel_prepare_plane_fb - Prepare fb for usage on plane
12918 * @plane: drm plane to prepare for
12919 * @fb: framebuffer to prepare for presentation
12920 *
12921 * Prepares a framebuffer for usage on a display plane. Generally this
12922 * involves pinning the underlying object and updating the frontbuffer tracking
12923 * bits. Some older platforms need special physical address handling for
12924 * cursor planes.
12925 *
12926 * Returns 0 on success, negative error code on failure.
12927 */
12928 int
12929 intel_prepare_plane_fb(struct drm_plane *plane,
12930 struct drm_framebuffer *fb,
12931 const struct drm_plane_state *new_state)
12932 {
12933 struct drm_device *dev = plane->dev;
12934 struct intel_plane *intel_plane = to_intel_plane(plane);
12935 enum pipe pipe = intel_plane->pipe;
12936 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12937 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12938 unsigned frontbuffer_bits = 0;
12939 int ret = 0;
12940
12941 if (!obj)
12942 return 0;
12943
12944 switch (plane->type) {
12945 case DRM_PLANE_TYPE_PRIMARY:
12946 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12947 break;
12948 case DRM_PLANE_TYPE_CURSOR:
12949 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12950 break;
12951 case DRM_PLANE_TYPE_OVERLAY:
12952 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12953 break;
12954 }
12955
12956 mutex_lock(&dev->struct_mutex);
12957
12958 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12959 INTEL_INFO(dev)->cursor_needs_physical) {
12960 int align = IS_I830(dev) ? 16 * 1024 : 256;
12961 ret = i915_gem_object_attach_phys(obj, align);
12962 if (ret)
12963 DRM_DEBUG_KMS("failed to attach phys object\n");
12964 } else {
12965 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12966 }
12967
12968 if (ret == 0)
12969 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12970
12971 mutex_unlock(&dev->struct_mutex);
12972
12973 return ret;
12974 }
12975
12976 /**
12977 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12978 * @plane: drm plane to clean up for
12979 * @fb: old framebuffer that was on plane
12980 *
12981 * Cleans up a framebuffer that has just been removed from a plane.
12982 */
12983 void
12984 intel_cleanup_plane_fb(struct drm_plane *plane,
12985 struct drm_framebuffer *fb,
12986 const struct drm_plane_state *old_state)
12987 {
12988 struct drm_device *dev = plane->dev;
12989 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12990
12991 if (WARN_ON(!obj))
12992 return;
12993
12994 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12995 !INTEL_INFO(dev)->cursor_needs_physical) {
12996 mutex_lock(&dev->struct_mutex);
12997 intel_unpin_fb_obj(fb, old_state);
12998 mutex_unlock(&dev->struct_mutex);
12999 }
13000 }
13001
13002 int
13003 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13004 {
13005 int max_scale;
13006 struct drm_device *dev;
13007 struct drm_i915_private *dev_priv;
13008 int crtc_clock, cdclk;
13009
13010 if (!intel_crtc || !crtc_state)
13011 return DRM_PLANE_HELPER_NO_SCALING;
13012
13013 dev = intel_crtc->base.dev;
13014 dev_priv = dev->dev_private;
13015 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13016 cdclk = dev_priv->display.get_display_clock_speed(dev);
13017
13018 if (!crtc_clock || !cdclk)
13019 return DRM_PLANE_HELPER_NO_SCALING;
13020
13021 /*
13022 * skl max scale is lower of:
13023 * close to 3 but not 3, -1 is for that purpose
13024 * or
13025 * cdclk/crtc_clock
13026 */
13027 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13028
13029 return max_scale;
13030 }
13031
13032 static int
13033 intel_check_primary_plane(struct drm_plane *plane,
13034 struct intel_plane_state *state)
13035 {
13036 struct drm_device *dev = plane->dev;
13037 struct drm_i915_private *dev_priv = dev->dev_private;
13038 struct drm_crtc *crtc = state->base.crtc;
13039 struct intel_crtc *intel_crtc;
13040 struct intel_crtc_state *crtc_state;
13041 struct drm_framebuffer *fb = state->base.fb;
13042 struct drm_rect *dest = &state->dst;
13043 struct drm_rect *src = &state->src;
13044 const struct drm_rect *clip = &state->clip;
13045 bool can_position = false;
13046 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13047 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13048 int ret;
13049
13050 crtc = crtc ? crtc : plane->crtc;
13051 intel_crtc = to_intel_crtc(crtc);
13052 crtc_state = state->base.state ?
13053 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13054
13055 if (INTEL_INFO(dev)->gen >= 9) {
13056 min_scale = 1;
13057 max_scale = skl_max_scale(intel_crtc, crtc_state);
13058 can_position = true;
13059 }
13060
13061 ret = drm_plane_helper_check_update(plane, crtc, fb,
13062 src, dest, clip,
13063 min_scale,
13064 max_scale,
13065 can_position, true,
13066 &state->visible);
13067 if (ret)
13068 return ret;
13069
13070 if (intel_crtc->active) {
13071 struct intel_plane_state *old_state =
13072 to_intel_plane_state(plane->state);
13073
13074 intel_crtc->atomic.wait_for_flips = true;
13075
13076 /*
13077 * FBC does not work on some platforms for rotated
13078 * planes, so disable it when rotation is not 0 and
13079 * update it when rotation is set back to 0.
13080 *
13081 * FIXME: This is redundant with the fbc update done in
13082 * the primary plane enable function except that that
13083 * one is done too late. We eventually need to unify
13084 * this.
13085 */
13086 if (state->visible &&
13087 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13088 dev_priv->fbc.crtc == intel_crtc &&
13089 state->base.rotation != BIT(DRM_ROTATE_0)) {
13090 intel_crtc->atomic.disable_fbc = true;
13091 }
13092
13093 if (state->visible && !old_state->visible) {
13094 /*
13095 * BDW signals flip done immediately if the plane
13096 * is disabled, even if the plane enable is already
13097 * armed to occur at the next vblank :(
13098 */
13099 if (IS_BROADWELL(dev))
13100 intel_crtc->atomic.wait_vblank = true;
13101 }
13102
13103 intel_crtc->atomic.fb_bits |=
13104 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13105
13106 intel_crtc->atomic.update_fbc = true;
13107
13108 if (intel_wm_need_update(plane, &state->base))
13109 intel_crtc->atomic.update_wm = true;
13110 }
13111
13112 if (INTEL_INFO(dev)->gen >= 9) {
13113 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13114 to_intel_plane(plane), state, 0);
13115 if (ret)
13116 return ret;
13117 }
13118
13119 return 0;
13120 }
13121
13122 static void
13123 intel_commit_primary_plane(struct drm_plane *plane,
13124 struct intel_plane_state *state)
13125 {
13126 struct drm_crtc *crtc = state->base.crtc;
13127 struct drm_framebuffer *fb = state->base.fb;
13128 struct drm_device *dev = plane->dev;
13129 struct drm_i915_private *dev_priv = dev->dev_private;
13130 struct intel_crtc *intel_crtc;
13131 struct drm_rect *src = &state->src;
13132
13133 crtc = crtc ? crtc : plane->crtc;
13134 intel_crtc = to_intel_crtc(crtc);
13135
13136 plane->fb = fb;
13137 crtc->x = src->x1 >> 16;
13138 crtc->y = src->y1 >> 16;
13139
13140 if (intel_crtc->active) {
13141 if (state->visible)
13142 /* FIXME: kill this fastboot hack */
13143 intel_update_pipe_size(intel_crtc);
13144
13145 dev_priv->display.update_primary_plane(crtc, plane->fb,
13146 crtc->x, crtc->y);
13147 }
13148 }
13149
13150 static void
13151 intel_disable_primary_plane(struct drm_plane *plane,
13152 struct drm_crtc *crtc,
13153 bool force)
13154 {
13155 struct drm_device *dev = plane->dev;
13156 struct drm_i915_private *dev_priv = dev->dev_private;
13157
13158 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13159 }
13160
13161 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13162 {
13163 struct drm_device *dev = crtc->dev;
13164 struct drm_i915_private *dev_priv = dev->dev_private;
13165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13166 struct intel_plane *intel_plane;
13167 struct drm_plane *p;
13168 unsigned fb_bits = 0;
13169
13170 /* Track fb's for any planes being disabled */
13171 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13172 intel_plane = to_intel_plane(p);
13173
13174 if (intel_crtc->atomic.disabled_planes &
13175 (1 << drm_plane_index(p))) {
13176 switch (p->type) {
13177 case DRM_PLANE_TYPE_PRIMARY:
13178 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13179 break;
13180 case DRM_PLANE_TYPE_CURSOR:
13181 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13182 break;
13183 case DRM_PLANE_TYPE_OVERLAY:
13184 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13185 break;
13186 }
13187
13188 mutex_lock(&dev->struct_mutex);
13189 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13190 mutex_unlock(&dev->struct_mutex);
13191 }
13192 }
13193
13194 if (intel_crtc->atomic.wait_for_flips)
13195 intel_crtc_wait_for_pending_flips(crtc);
13196
13197 if (intel_crtc->atomic.disable_fbc)
13198 intel_fbc_disable(dev);
13199
13200 if (intel_crtc->atomic.pre_disable_primary)
13201 intel_pre_disable_primary(crtc);
13202
13203 if (intel_crtc->atomic.update_wm)
13204 intel_update_watermarks(crtc);
13205
13206 intel_runtime_pm_get(dev_priv);
13207
13208 /* Perform vblank evasion around commit operation */
13209 if (intel_crtc->active)
13210 intel_crtc->atomic.evade =
13211 intel_pipe_update_start(intel_crtc,
13212 &intel_crtc->atomic.start_vbl_count);
13213 }
13214
13215 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13216 {
13217 struct drm_device *dev = crtc->dev;
13218 struct drm_i915_private *dev_priv = dev->dev_private;
13219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13220 struct drm_plane *p;
13221
13222 if (intel_crtc->atomic.evade)
13223 intel_pipe_update_end(intel_crtc,
13224 intel_crtc->atomic.start_vbl_count);
13225
13226 intel_runtime_pm_put(dev_priv);
13227
13228 if (intel_crtc->atomic.wait_vblank)
13229 intel_wait_for_vblank(dev, intel_crtc->pipe);
13230
13231 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13232
13233 if (intel_crtc->atomic.update_fbc) {
13234 mutex_lock(&dev->struct_mutex);
13235 intel_fbc_update(dev);
13236 mutex_unlock(&dev->struct_mutex);
13237 }
13238
13239 if (intel_crtc->atomic.post_enable_primary)
13240 intel_post_enable_primary(crtc);
13241
13242 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13243 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13244 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13245 false, false);
13246
13247 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13248 }
13249
13250 /**
13251 * intel_plane_destroy - destroy a plane
13252 * @plane: plane to destroy
13253 *
13254 * Common destruction function for all types of planes (primary, cursor,
13255 * sprite).
13256 */
13257 void intel_plane_destroy(struct drm_plane *plane)
13258 {
13259 struct intel_plane *intel_plane = to_intel_plane(plane);
13260 drm_plane_cleanup(plane);
13261 kfree(intel_plane);
13262 }
13263
13264 const struct drm_plane_funcs intel_plane_funcs = {
13265 .update_plane = drm_atomic_helper_update_plane,
13266 .disable_plane = drm_atomic_helper_disable_plane,
13267 .destroy = intel_plane_destroy,
13268 .set_property = drm_atomic_helper_plane_set_property,
13269 .atomic_get_property = intel_plane_atomic_get_property,
13270 .atomic_set_property = intel_plane_atomic_set_property,
13271 .atomic_duplicate_state = intel_plane_duplicate_state,
13272 .atomic_destroy_state = intel_plane_destroy_state,
13273
13274 };
13275
13276 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13277 int pipe)
13278 {
13279 struct intel_plane *primary;
13280 struct intel_plane_state *state;
13281 const uint32_t *intel_primary_formats;
13282 int num_formats;
13283
13284 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13285 if (primary == NULL)
13286 return NULL;
13287
13288 state = intel_create_plane_state(&primary->base);
13289 if (!state) {
13290 kfree(primary);
13291 return NULL;
13292 }
13293 primary->base.state = &state->base;
13294
13295 primary->can_scale = false;
13296 primary->max_downscale = 1;
13297 if (INTEL_INFO(dev)->gen >= 9) {
13298 primary->can_scale = true;
13299 state->scaler_id = -1;
13300 }
13301 primary->pipe = pipe;
13302 primary->plane = pipe;
13303 primary->check_plane = intel_check_primary_plane;
13304 primary->commit_plane = intel_commit_primary_plane;
13305 primary->disable_plane = intel_disable_primary_plane;
13306 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13307 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13308 primary->plane = !pipe;
13309
13310 if (INTEL_INFO(dev)->gen >= 9) {
13311 intel_primary_formats = skl_primary_formats;
13312 num_formats = ARRAY_SIZE(skl_primary_formats);
13313 } else if (INTEL_INFO(dev)->gen >= 4) {
13314 intel_primary_formats = i965_primary_formats;
13315 num_formats = ARRAY_SIZE(i965_primary_formats);
13316 } else {
13317 intel_primary_formats = i8xx_primary_formats;
13318 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13319 }
13320
13321 drm_universal_plane_init(dev, &primary->base, 0,
13322 &intel_plane_funcs,
13323 intel_primary_formats, num_formats,
13324 DRM_PLANE_TYPE_PRIMARY);
13325
13326 if (INTEL_INFO(dev)->gen >= 4)
13327 intel_create_rotation_property(dev, primary);
13328
13329 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13330
13331 return &primary->base;
13332 }
13333
13334 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13335 {
13336 if (!dev->mode_config.rotation_property) {
13337 unsigned long flags = BIT(DRM_ROTATE_0) |
13338 BIT(DRM_ROTATE_180);
13339
13340 if (INTEL_INFO(dev)->gen >= 9)
13341 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13342
13343 dev->mode_config.rotation_property =
13344 drm_mode_create_rotation_property(dev, flags);
13345 }
13346 if (dev->mode_config.rotation_property)
13347 drm_object_attach_property(&plane->base.base,
13348 dev->mode_config.rotation_property,
13349 plane->base.state->rotation);
13350 }
13351
13352 static int
13353 intel_check_cursor_plane(struct drm_plane *plane,
13354 struct intel_plane_state *state)
13355 {
13356 struct drm_crtc *crtc = state->base.crtc;
13357 struct drm_device *dev = plane->dev;
13358 struct drm_framebuffer *fb = state->base.fb;
13359 struct drm_rect *dest = &state->dst;
13360 struct drm_rect *src = &state->src;
13361 const struct drm_rect *clip = &state->clip;
13362 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13363 struct intel_crtc *intel_crtc;
13364 unsigned stride;
13365 int ret;
13366
13367 crtc = crtc ? crtc : plane->crtc;
13368 intel_crtc = to_intel_crtc(crtc);
13369
13370 ret = drm_plane_helper_check_update(plane, crtc, fb,
13371 src, dest, clip,
13372 DRM_PLANE_HELPER_NO_SCALING,
13373 DRM_PLANE_HELPER_NO_SCALING,
13374 true, true, &state->visible);
13375 if (ret)
13376 return ret;
13377
13378
13379 /* if we want to turn off the cursor ignore width and height */
13380 if (!obj)
13381 goto finish;
13382
13383 /* Check for which cursor types we support */
13384 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13385 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13386 state->base.crtc_w, state->base.crtc_h);
13387 return -EINVAL;
13388 }
13389
13390 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13391 if (obj->base.size < stride * state->base.crtc_h) {
13392 DRM_DEBUG_KMS("buffer is too small\n");
13393 return -ENOMEM;
13394 }
13395
13396 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13397 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13398 ret = -EINVAL;
13399 }
13400
13401 finish:
13402 if (intel_crtc->active) {
13403 if (plane->state->crtc_w != state->base.crtc_w)
13404 intel_crtc->atomic.update_wm = true;
13405
13406 intel_crtc->atomic.fb_bits |=
13407 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13408 }
13409
13410 return ret;
13411 }
13412
13413 static void
13414 intel_disable_cursor_plane(struct drm_plane *plane,
13415 struct drm_crtc *crtc,
13416 bool force)
13417 {
13418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13419
13420 if (!force) {
13421 plane->fb = NULL;
13422 intel_crtc->cursor_bo = NULL;
13423 intel_crtc->cursor_addr = 0;
13424 }
13425
13426 intel_crtc_update_cursor(crtc, false);
13427 }
13428
13429 static void
13430 intel_commit_cursor_plane(struct drm_plane *plane,
13431 struct intel_plane_state *state)
13432 {
13433 struct drm_crtc *crtc = state->base.crtc;
13434 struct drm_device *dev = plane->dev;
13435 struct intel_crtc *intel_crtc;
13436 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13437 uint32_t addr;
13438
13439 crtc = crtc ? crtc : plane->crtc;
13440 intel_crtc = to_intel_crtc(crtc);
13441
13442 plane->fb = state->base.fb;
13443 crtc->cursor_x = state->base.crtc_x;
13444 crtc->cursor_y = state->base.crtc_y;
13445
13446 if (intel_crtc->cursor_bo == obj)
13447 goto update;
13448
13449 if (!obj)
13450 addr = 0;
13451 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13452 addr = i915_gem_obj_ggtt_offset(obj);
13453 else
13454 addr = obj->phys_handle->busaddr;
13455
13456 intel_crtc->cursor_addr = addr;
13457 intel_crtc->cursor_bo = obj;
13458 update:
13459
13460 if (intel_crtc->active)
13461 intel_crtc_update_cursor(crtc, state->visible);
13462 }
13463
13464 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13465 int pipe)
13466 {
13467 struct intel_plane *cursor;
13468 struct intel_plane_state *state;
13469
13470 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13471 if (cursor == NULL)
13472 return NULL;
13473
13474 state = intel_create_plane_state(&cursor->base);
13475 if (!state) {
13476 kfree(cursor);
13477 return NULL;
13478 }
13479 cursor->base.state = &state->base;
13480
13481 cursor->can_scale = false;
13482 cursor->max_downscale = 1;
13483 cursor->pipe = pipe;
13484 cursor->plane = pipe;
13485 cursor->check_plane = intel_check_cursor_plane;
13486 cursor->commit_plane = intel_commit_cursor_plane;
13487 cursor->disable_plane = intel_disable_cursor_plane;
13488
13489 drm_universal_plane_init(dev, &cursor->base, 0,
13490 &intel_plane_funcs,
13491 intel_cursor_formats,
13492 ARRAY_SIZE(intel_cursor_formats),
13493 DRM_PLANE_TYPE_CURSOR);
13494
13495 if (INTEL_INFO(dev)->gen >= 4) {
13496 if (!dev->mode_config.rotation_property)
13497 dev->mode_config.rotation_property =
13498 drm_mode_create_rotation_property(dev,
13499 BIT(DRM_ROTATE_0) |
13500 BIT(DRM_ROTATE_180));
13501 if (dev->mode_config.rotation_property)
13502 drm_object_attach_property(&cursor->base.base,
13503 dev->mode_config.rotation_property,
13504 state->base.rotation);
13505 }
13506
13507 if (INTEL_INFO(dev)->gen >=9)
13508 state->scaler_id = -1;
13509
13510 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13511
13512 return &cursor->base;
13513 }
13514
13515 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13516 struct intel_crtc_state *crtc_state)
13517 {
13518 int i;
13519 struct intel_scaler *intel_scaler;
13520 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13521
13522 for (i = 0; i < intel_crtc->num_scalers; i++) {
13523 intel_scaler = &scaler_state->scalers[i];
13524 intel_scaler->in_use = 0;
13525 intel_scaler->id = i;
13526
13527 intel_scaler->mode = PS_SCALER_MODE_DYN;
13528 }
13529
13530 scaler_state->scaler_id = -1;
13531 }
13532
13533 static void intel_crtc_init(struct drm_device *dev, int pipe)
13534 {
13535 struct drm_i915_private *dev_priv = dev->dev_private;
13536 struct intel_crtc *intel_crtc;
13537 struct intel_crtc_state *crtc_state = NULL;
13538 struct drm_plane *primary = NULL;
13539 struct drm_plane *cursor = NULL;
13540 int i, ret;
13541
13542 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13543 if (intel_crtc == NULL)
13544 return;
13545
13546 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13547 if (!crtc_state)
13548 goto fail;
13549 intel_crtc->config = crtc_state;
13550 intel_crtc->base.state = &crtc_state->base;
13551 crtc_state->base.crtc = &intel_crtc->base;
13552
13553 /* initialize shared scalers */
13554 if (INTEL_INFO(dev)->gen >= 9) {
13555 if (pipe == PIPE_C)
13556 intel_crtc->num_scalers = 1;
13557 else
13558 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13559
13560 skl_init_scalers(dev, intel_crtc, crtc_state);
13561 }
13562
13563 primary = intel_primary_plane_create(dev, pipe);
13564 if (!primary)
13565 goto fail;
13566
13567 cursor = intel_cursor_plane_create(dev, pipe);
13568 if (!cursor)
13569 goto fail;
13570
13571 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13572 cursor, &intel_crtc_funcs);
13573 if (ret)
13574 goto fail;
13575
13576 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13577 for (i = 0; i < 256; i++) {
13578 intel_crtc->lut_r[i] = i;
13579 intel_crtc->lut_g[i] = i;
13580 intel_crtc->lut_b[i] = i;
13581 }
13582
13583 /*
13584 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13585 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13586 */
13587 intel_crtc->pipe = pipe;
13588 intel_crtc->plane = pipe;
13589 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13590 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13591 intel_crtc->plane = !pipe;
13592 }
13593
13594 intel_crtc->cursor_base = ~0;
13595 intel_crtc->cursor_cntl = ~0;
13596 intel_crtc->cursor_size = ~0;
13597
13598 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13599 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13600 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13601 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13602
13603 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13604
13605 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13606 return;
13607
13608 fail:
13609 if (primary)
13610 drm_plane_cleanup(primary);
13611 if (cursor)
13612 drm_plane_cleanup(cursor);
13613 kfree(crtc_state);
13614 kfree(intel_crtc);
13615 }
13616
13617 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13618 {
13619 struct drm_encoder *encoder = connector->base.encoder;
13620 struct drm_device *dev = connector->base.dev;
13621
13622 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13623
13624 if (!encoder || WARN_ON(!encoder->crtc))
13625 return INVALID_PIPE;
13626
13627 return to_intel_crtc(encoder->crtc)->pipe;
13628 }
13629
13630 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13631 struct drm_file *file)
13632 {
13633 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13634 struct drm_crtc *drmmode_crtc;
13635 struct intel_crtc *crtc;
13636
13637 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13638
13639 if (!drmmode_crtc) {
13640 DRM_ERROR("no such CRTC id\n");
13641 return -ENOENT;
13642 }
13643
13644 crtc = to_intel_crtc(drmmode_crtc);
13645 pipe_from_crtc_id->pipe = crtc->pipe;
13646
13647 return 0;
13648 }
13649
13650 static int intel_encoder_clones(struct intel_encoder *encoder)
13651 {
13652 struct drm_device *dev = encoder->base.dev;
13653 struct intel_encoder *source_encoder;
13654 int index_mask = 0;
13655 int entry = 0;
13656
13657 for_each_intel_encoder(dev, source_encoder) {
13658 if (encoders_cloneable(encoder, source_encoder))
13659 index_mask |= (1 << entry);
13660
13661 entry++;
13662 }
13663
13664 return index_mask;
13665 }
13666
13667 static bool has_edp_a(struct drm_device *dev)
13668 {
13669 struct drm_i915_private *dev_priv = dev->dev_private;
13670
13671 if (!IS_MOBILE(dev))
13672 return false;
13673
13674 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13675 return false;
13676
13677 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13678 return false;
13679
13680 return true;
13681 }
13682
13683 static bool intel_crt_present(struct drm_device *dev)
13684 {
13685 struct drm_i915_private *dev_priv = dev->dev_private;
13686
13687 if (INTEL_INFO(dev)->gen >= 9)
13688 return false;
13689
13690 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13691 return false;
13692
13693 if (IS_CHERRYVIEW(dev))
13694 return false;
13695
13696 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13697 return false;
13698
13699 return true;
13700 }
13701
13702 static void intel_setup_outputs(struct drm_device *dev)
13703 {
13704 struct drm_i915_private *dev_priv = dev->dev_private;
13705 struct intel_encoder *encoder;
13706 bool dpd_is_edp = false;
13707
13708 intel_lvds_init(dev);
13709
13710 if (intel_crt_present(dev))
13711 intel_crt_init(dev);
13712
13713 if (IS_BROXTON(dev)) {
13714 /*
13715 * FIXME: Broxton doesn't support port detection via the
13716 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13717 * detect the ports.
13718 */
13719 intel_ddi_init(dev, PORT_A);
13720 intel_ddi_init(dev, PORT_B);
13721 intel_ddi_init(dev, PORT_C);
13722 } else if (HAS_DDI(dev)) {
13723 int found;
13724
13725 /*
13726 * Haswell uses DDI functions to detect digital outputs.
13727 * On SKL pre-D0 the strap isn't connected, so we assume
13728 * it's there.
13729 */
13730 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13731 /* WaIgnoreDDIAStrap: skl */
13732 if (found ||
13733 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13734 intel_ddi_init(dev, PORT_A);
13735
13736 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13737 * register */
13738 found = I915_READ(SFUSE_STRAP);
13739
13740 if (found & SFUSE_STRAP_DDIB_DETECTED)
13741 intel_ddi_init(dev, PORT_B);
13742 if (found & SFUSE_STRAP_DDIC_DETECTED)
13743 intel_ddi_init(dev, PORT_C);
13744 if (found & SFUSE_STRAP_DDID_DETECTED)
13745 intel_ddi_init(dev, PORT_D);
13746 } else if (HAS_PCH_SPLIT(dev)) {
13747 int found;
13748 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13749
13750 if (has_edp_a(dev))
13751 intel_dp_init(dev, DP_A, PORT_A);
13752
13753 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13754 /* PCH SDVOB multiplex with HDMIB */
13755 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13756 if (!found)
13757 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13758 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13759 intel_dp_init(dev, PCH_DP_B, PORT_B);
13760 }
13761
13762 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13763 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13764
13765 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13766 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13767
13768 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13769 intel_dp_init(dev, PCH_DP_C, PORT_C);
13770
13771 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13772 intel_dp_init(dev, PCH_DP_D, PORT_D);
13773 } else if (IS_VALLEYVIEW(dev)) {
13774 /*
13775 * The DP_DETECTED bit is the latched state of the DDC
13776 * SDA pin at boot. However since eDP doesn't require DDC
13777 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13778 * eDP ports may have been muxed to an alternate function.
13779 * Thus we can't rely on the DP_DETECTED bit alone to detect
13780 * eDP ports. Consult the VBT as well as DP_DETECTED to
13781 * detect eDP ports.
13782 */
13783 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13784 !intel_dp_is_edp(dev, PORT_B))
13785 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13786 PORT_B);
13787 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13788 intel_dp_is_edp(dev, PORT_B))
13789 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13790
13791 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13792 !intel_dp_is_edp(dev, PORT_C))
13793 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13794 PORT_C);
13795 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13796 intel_dp_is_edp(dev, PORT_C))
13797 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13798
13799 if (IS_CHERRYVIEW(dev)) {
13800 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13801 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13802 PORT_D);
13803 /* eDP not supported on port D, so don't check VBT */
13804 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13805 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13806 }
13807
13808 intel_dsi_init(dev);
13809 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13810 bool found = false;
13811
13812 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13813 DRM_DEBUG_KMS("probing SDVOB\n");
13814 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13815 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13816 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13817 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13818 }
13819
13820 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13821 intel_dp_init(dev, DP_B, PORT_B);
13822 }
13823
13824 /* Before G4X SDVOC doesn't have its own detect register */
13825
13826 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13827 DRM_DEBUG_KMS("probing SDVOC\n");
13828 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13829 }
13830
13831 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13832
13833 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13834 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13835 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13836 }
13837 if (SUPPORTS_INTEGRATED_DP(dev))
13838 intel_dp_init(dev, DP_C, PORT_C);
13839 }
13840
13841 if (SUPPORTS_INTEGRATED_DP(dev) &&
13842 (I915_READ(DP_D) & DP_DETECTED))
13843 intel_dp_init(dev, DP_D, PORT_D);
13844 } else if (IS_GEN2(dev))
13845 intel_dvo_init(dev);
13846
13847 if (SUPPORTS_TV(dev))
13848 intel_tv_init(dev);
13849
13850 intel_psr_init(dev);
13851
13852 for_each_intel_encoder(dev, encoder) {
13853 encoder->base.possible_crtcs = encoder->crtc_mask;
13854 encoder->base.possible_clones =
13855 intel_encoder_clones(encoder);
13856 }
13857
13858 intel_init_pch_refclk(dev);
13859
13860 drm_helper_move_panel_connectors_to_head(dev);
13861 }
13862
13863 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13864 {
13865 struct drm_device *dev = fb->dev;
13866 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13867
13868 drm_framebuffer_cleanup(fb);
13869 mutex_lock(&dev->struct_mutex);
13870 WARN_ON(!intel_fb->obj->framebuffer_references--);
13871 drm_gem_object_unreference(&intel_fb->obj->base);
13872 mutex_unlock(&dev->struct_mutex);
13873 kfree(intel_fb);
13874 }
13875
13876 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13877 struct drm_file *file,
13878 unsigned int *handle)
13879 {
13880 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13881 struct drm_i915_gem_object *obj = intel_fb->obj;
13882
13883 return drm_gem_handle_create(file, &obj->base, handle);
13884 }
13885
13886 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13887 .destroy = intel_user_framebuffer_destroy,
13888 .create_handle = intel_user_framebuffer_create_handle,
13889 };
13890
13891 static
13892 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13893 uint32_t pixel_format)
13894 {
13895 u32 gen = INTEL_INFO(dev)->gen;
13896
13897 if (gen >= 9) {
13898 /* "The stride in bytes must not exceed the of the size of 8K
13899 * pixels and 32K bytes."
13900 */
13901 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13902 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13903 return 32*1024;
13904 } else if (gen >= 4) {
13905 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13906 return 16*1024;
13907 else
13908 return 32*1024;
13909 } else if (gen >= 3) {
13910 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13911 return 8*1024;
13912 else
13913 return 16*1024;
13914 } else {
13915 /* XXX DSPC is limited to 4k tiled */
13916 return 8*1024;
13917 }
13918 }
13919
13920 static int intel_framebuffer_init(struct drm_device *dev,
13921 struct intel_framebuffer *intel_fb,
13922 struct drm_mode_fb_cmd2 *mode_cmd,
13923 struct drm_i915_gem_object *obj)
13924 {
13925 unsigned int aligned_height;
13926 int ret;
13927 u32 pitch_limit, stride_alignment;
13928
13929 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13930
13931 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13932 /* Enforce that fb modifier and tiling mode match, but only for
13933 * X-tiled. This is needed for FBC. */
13934 if (!!(obj->tiling_mode == I915_TILING_X) !=
13935 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13936 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13937 return -EINVAL;
13938 }
13939 } else {
13940 if (obj->tiling_mode == I915_TILING_X)
13941 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13942 else if (obj->tiling_mode == I915_TILING_Y) {
13943 DRM_DEBUG("No Y tiling for legacy addfb\n");
13944 return -EINVAL;
13945 }
13946 }
13947
13948 /* Passed in modifier sanity checking. */
13949 switch (mode_cmd->modifier[0]) {
13950 case I915_FORMAT_MOD_Y_TILED:
13951 case I915_FORMAT_MOD_Yf_TILED:
13952 if (INTEL_INFO(dev)->gen < 9) {
13953 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13954 mode_cmd->modifier[0]);
13955 return -EINVAL;
13956 }
13957 case DRM_FORMAT_MOD_NONE:
13958 case I915_FORMAT_MOD_X_TILED:
13959 break;
13960 default:
13961 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13962 mode_cmd->modifier[0]);
13963 return -EINVAL;
13964 }
13965
13966 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13967 mode_cmd->pixel_format);
13968 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13969 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13970 mode_cmd->pitches[0], stride_alignment);
13971 return -EINVAL;
13972 }
13973
13974 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13975 mode_cmd->pixel_format);
13976 if (mode_cmd->pitches[0] > pitch_limit) {
13977 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13978 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13979 "tiled" : "linear",
13980 mode_cmd->pitches[0], pitch_limit);
13981 return -EINVAL;
13982 }
13983
13984 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13985 mode_cmd->pitches[0] != obj->stride) {
13986 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13987 mode_cmd->pitches[0], obj->stride);
13988 return -EINVAL;
13989 }
13990
13991 /* Reject formats not supported by any plane early. */
13992 switch (mode_cmd->pixel_format) {
13993 case DRM_FORMAT_C8:
13994 case DRM_FORMAT_RGB565:
13995 case DRM_FORMAT_XRGB8888:
13996 case DRM_FORMAT_ARGB8888:
13997 break;
13998 case DRM_FORMAT_XRGB1555:
13999 if (INTEL_INFO(dev)->gen > 3) {
14000 DRM_DEBUG("unsupported pixel format: %s\n",
14001 drm_get_format_name(mode_cmd->pixel_format));
14002 return -EINVAL;
14003 }
14004 break;
14005 case DRM_FORMAT_ABGR8888:
14006 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14007 DRM_DEBUG("unsupported pixel format: %s\n",
14008 drm_get_format_name(mode_cmd->pixel_format));
14009 return -EINVAL;
14010 }
14011 break;
14012 case DRM_FORMAT_XBGR8888:
14013 case DRM_FORMAT_XRGB2101010:
14014 case DRM_FORMAT_XBGR2101010:
14015 if (INTEL_INFO(dev)->gen < 4) {
14016 DRM_DEBUG("unsupported pixel format: %s\n",
14017 drm_get_format_name(mode_cmd->pixel_format));
14018 return -EINVAL;
14019 }
14020 break;
14021 case DRM_FORMAT_ABGR2101010:
14022 if (!IS_VALLEYVIEW(dev)) {
14023 DRM_DEBUG("unsupported pixel format: %s\n",
14024 drm_get_format_name(mode_cmd->pixel_format));
14025 return -EINVAL;
14026 }
14027 break;
14028 case DRM_FORMAT_YUYV:
14029 case DRM_FORMAT_UYVY:
14030 case DRM_FORMAT_YVYU:
14031 case DRM_FORMAT_VYUY:
14032 if (INTEL_INFO(dev)->gen < 5) {
14033 DRM_DEBUG("unsupported pixel format: %s\n",
14034 drm_get_format_name(mode_cmd->pixel_format));
14035 return -EINVAL;
14036 }
14037 break;
14038 default:
14039 DRM_DEBUG("unsupported pixel format: %s\n",
14040 drm_get_format_name(mode_cmd->pixel_format));
14041 return -EINVAL;
14042 }
14043
14044 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14045 if (mode_cmd->offsets[0] != 0)
14046 return -EINVAL;
14047
14048 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14049 mode_cmd->pixel_format,
14050 mode_cmd->modifier[0]);
14051 /* FIXME drm helper for size checks (especially planar formats)? */
14052 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14053 return -EINVAL;
14054
14055 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14056 intel_fb->obj = obj;
14057 intel_fb->obj->framebuffer_references++;
14058
14059 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14060 if (ret) {
14061 DRM_ERROR("framebuffer init failed %d\n", ret);
14062 return ret;
14063 }
14064
14065 return 0;
14066 }
14067
14068 static struct drm_framebuffer *
14069 intel_user_framebuffer_create(struct drm_device *dev,
14070 struct drm_file *filp,
14071 struct drm_mode_fb_cmd2 *mode_cmd)
14072 {
14073 struct drm_i915_gem_object *obj;
14074
14075 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14076 mode_cmd->handles[0]));
14077 if (&obj->base == NULL)
14078 return ERR_PTR(-ENOENT);
14079
14080 return intel_framebuffer_create(dev, mode_cmd, obj);
14081 }
14082
14083 #ifndef CONFIG_DRM_I915_FBDEV
14084 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14085 {
14086 }
14087 #endif
14088
14089 static const struct drm_mode_config_funcs intel_mode_funcs = {
14090 .fb_create = intel_user_framebuffer_create,
14091 .output_poll_changed = intel_fbdev_output_poll_changed,
14092 .atomic_check = intel_atomic_check,
14093 .atomic_commit = intel_atomic_commit,
14094 };
14095
14096 /* Set up chip specific display functions */
14097 static void intel_init_display(struct drm_device *dev)
14098 {
14099 struct drm_i915_private *dev_priv = dev->dev_private;
14100
14101 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14102 dev_priv->display.find_dpll = g4x_find_best_dpll;
14103 else if (IS_CHERRYVIEW(dev))
14104 dev_priv->display.find_dpll = chv_find_best_dpll;
14105 else if (IS_VALLEYVIEW(dev))
14106 dev_priv->display.find_dpll = vlv_find_best_dpll;
14107 else if (IS_PINEVIEW(dev))
14108 dev_priv->display.find_dpll = pnv_find_best_dpll;
14109 else
14110 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14111
14112 if (INTEL_INFO(dev)->gen >= 9) {
14113 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14114 dev_priv->display.get_initial_plane_config =
14115 skylake_get_initial_plane_config;
14116 dev_priv->display.crtc_compute_clock =
14117 haswell_crtc_compute_clock;
14118 dev_priv->display.crtc_enable = haswell_crtc_enable;
14119 dev_priv->display.crtc_disable = haswell_crtc_disable;
14120 dev_priv->display.off = ironlake_crtc_off;
14121 dev_priv->display.update_primary_plane =
14122 skylake_update_primary_plane;
14123 } else if (HAS_DDI(dev)) {
14124 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14125 dev_priv->display.get_initial_plane_config =
14126 ironlake_get_initial_plane_config;
14127 dev_priv->display.crtc_compute_clock =
14128 haswell_crtc_compute_clock;
14129 dev_priv->display.crtc_enable = haswell_crtc_enable;
14130 dev_priv->display.crtc_disable = haswell_crtc_disable;
14131 dev_priv->display.off = ironlake_crtc_off;
14132 dev_priv->display.update_primary_plane =
14133 ironlake_update_primary_plane;
14134 } else if (HAS_PCH_SPLIT(dev)) {
14135 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14136 dev_priv->display.get_initial_plane_config =
14137 ironlake_get_initial_plane_config;
14138 dev_priv->display.crtc_compute_clock =
14139 ironlake_crtc_compute_clock;
14140 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14141 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14142 dev_priv->display.off = ironlake_crtc_off;
14143 dev_priv->display.update_primary_plane =
14144 ironlake_update_primary_plane;
14145 } else if (IS_VALLEYVIEW(dev)) {
14146 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14147 dev_priv->display.get_initial_plane_config =
14148 i9xx_get_initial_plane_config;
14149 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14150 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14151 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14152 dev_priv->display.off = i9xx_crtc_off;
14153 dev_priv->display.update_primary_plane =
14154 i9xx_update_primary_plane;
14155 } else {
14156 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14157 dev_priv->display.get_initial_plane_config =
14158 i9xx_get_initial_plane_config;
14159 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14160 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14161 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14162 dev_priv->display.off = i9xx_crtc_off;
14163 dev_priv->display.update_primary_plane =
14164 i9xx_update_primary_plane;
14165 }
14166
14167 /* Returns the core display clock speed */
14168 if (IS_SKYLAKE(dev))
14169 dev_priv->display.get_display_clock_speed =
14170 skylake_get_display_clock_speed;
14171 else if (IS_BROADWELL(dev))
14172 dev_priv->display.get_display_clock_speed =
14173 broadwell_get_display_clock_speed;
14174 else if (IS_HASWELL(dev))
14175 dev_priv->display.get_display_clock_speed =
14176 haswell_get_display_clock_speed;
14177 else if (IS_VALLEYVIEW(dev))
14178 dev_priv->display.get_display_clock_speed =
14179 valleyview_get_display_clock_speed;
14180 else if (IS_GEN5(dev))
14181 dev_priv->display.get_display_clock_speed =
14182 ilk_get_display_clock_speed;
14183 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14184 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14185 dev_priv->display.get_display_clock_speed =
14186 i945_get_display_clock_speed;
14187 else if (IS_I915G(dev))
14188 dev_priv->display.get_display_clock_speed =
14189 i915_get_display_clock_speed;
14190 else if (IS_I945GM(dev) || IS_845G(dev))
14191 dev_priv->display.get_display_clock_speed =
14192 i9xx_misc_get_display_clock_speed;
14193 else if (IS_PINEVIEW(dev))
14194 dev_priv->display.get_display_clock_speed =
14195 pnv_get_display_clock_speed;
14196 else if (IS_I915GM(dev))
14197 dev_priv->display.get_display_clock_speed =
14198 i915gm_get_display_clock_speed;
14199 else if (IS_I865G(dev))
14200 dev_priv->display.get_display_clock_speed =
14201 i865_get_display_clock_speed;
14202 else if (IS_I85X(dev))
14203 dev_priv->display.get_display_clock_speed =
14204 i855_get_display_clock_speed;
14205 else /* 852, 830 */
14206 dev_priv->display.get_display_clock_speed =
14207 i830_get_display_clock_speed;
14208
14209 if (IS_GEN5(dev)) {
14210 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14211 } else if (IS_GEN6(dev)) {
14212 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14213 } else if (IS_IVYBRIDGE(dev)) {
14214 /* FIXME: detect B0+ stepping and use auto training */
14215 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14216 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14217 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14218 } else if (IS_VALLEYVIEW(dev)) {
14219 dev_priv->display.modeset_global_resources =
14220 valleyview_modeset_global_resources;
14221 } else if (IS_BROXTON(dev)) {
14222 dev_priv->display.modeset_global_resources =
14223 broxton_modeset_global_resources;
14224 }
14225
14226 switch (INTEL_INFO(dev)->gen) {
14227 case 2:
14228 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14229 break;
14230
14231 case 3:
14232 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14233 break;
14234
14235 case 4:
14236 case 5:
14237 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14238 break;
14239
14240 case 6:
14241 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14242 break;
14243 case 7:
14244 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14245 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14246 break;
14247 case 9:
14248 /* Drop through - unsupported since execlist only. */
14249 default:
14250 /* Default just returns -ENODEV to indicate unsupported */
14251 dev_priv->display.queue_flip = intel_default_queue_flip;
14252 }
14253
14254 intel_panel_init_backlight_funcs(dev);
14255
14256 mutex_init(&dev_priv->pps_mutex);
14257 }
14258
14259 /*
14260 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14261 * resume, or other times. This quirk makes sure that's the case for
14262 * affected systems.
14263 */
14264 static void quirk_pipea_force(struct drm_device *dev)
14265 {
14266 struct drm_i915_private *dev_priv = dev->dev_private;
14267
14268 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14269 DRM_INFO("applying pipe a force quirk\n");
14270 }
14271
14272 static void quirk_pipeb_force(struct drm_device *dev)
14273 {
14274 struct drm_i915_private *dev_priv = dev->dev_private;
14275
14276 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14277 DRM_INFO("applying pipe b force quirk\n");
14278 }
14279
14280 /*
14281 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14282 */
14283 static void quirk_ssc_force_disable(struct drm_device *dev)
14284 {
14285 struct drm_i915_private *dev_priv = dev->dev_private;
14286 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14287 DRM_INFO("applying lvds SSC disable quirk\n");
14288 }
14289
14290 /*
14291 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14292 * brightness value
14293 */
14294 static void quirk_invert_brightness(struct drm_device *dev)
14295 {
14296 struct drm_i915_private *dev_priv = dev->dev_private;
14297 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14298 DRM_INFO("applying inverted panel brightness quirk\n");
14299 }
14300
14301 /* Some VBT's incorrectly indicate no backlight is present */
14302 static void quirk_backlight_present(struct drm_device *dev)
14303 {
14304 struct drm_i915_private *dev_priv = dev->dev_private;
14305 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14306 DRM_INFO("applying backlight present quirk\n");
14307 }
14308
14309 struct intel_quirk {
14310 int device;
14311 int subsystem_vendor;
14312 int subsystem_device;
14313 void (*hook)(struct drm_device *dev);
14314 };
14315
14316 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14317 struct intel_dmi_quirk {
14318 void (*hook)(struct drm_device *dev);
14319 const struct dmi_system_id (*dmi_id_list)[];
14320 };
14321
14322 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14323 {
14324 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14325 return 1;
14326 }
14327
14328 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14329 {
14330 .dmi_id_list = &(const struct dmi_system_id[]) {
14331 {
14332 .callback = intel_dmi_reverse_brightness,
14333 .ident = "NCR Corporation",
14334 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14335 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14336 },
14337 },
14338 { } /* terminating entry */
14339 },
14340 .hook = quirk_invert_brightness,
14341 },
14342 };
14343
14344 static struct intel_quirk intel_quirks[] = {
14345 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14346 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14347
14348 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14349 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14350
14351 /* 830 needs to leave pipe A & dpll A up */
14352 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14353
14354 /* 830 needs to leave pipe B & dpll B up */
14355 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14356
14357 /* Lenovo U160 cannot use SSC on LVDS */
14358 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14359
14360 /* Sony Vaio Y cannot use SSC on LVDS */
14361 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14362
14363 /* Acer Aspire 5734Z must invert backlight brightness */
14364 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14365
14366 /* Acer/eMachines G725 */
14367 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14368
14369 /* Acer/eMachines e725 */
14370 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14371
14372 /* Acer/Packard Bell NCL20 */
14373 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14374
14375 /* Acer Aspire 4736Z */
14376 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14377
14378 /* Acer Aspire 5336 */
14379 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14380
14381 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14382 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14383
14384 /* Acer C720 Chromebook (Core i3 4005U) */
14385 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14386
14387 /* Apple Macbook 2,1 (Core 2 T7400) */
14388 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14389
14390 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14391 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14392
14393 /* HP Chromebook 14 (Celeron 2955U) */
14394 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14395
14396 /* Dell Chromebook 11 */
14397 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14398 };
14399
14400 static void intel_init_quirks(struct drm_device *dev)
14401 {
14402 struct pci_dev *d = dev->pdev;
14403 int i;
14404
14405 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14406 struct intel_quirk *q = &intel_quirks[i];
14407
14408 if (d->device == q->device &&
14409 (d->subsystem_vendor == q->subsystem_vendor ||
14410 q->subsystem_vendor == PCI_ANY_ID) &&
14411 (d->subsystem_device == q->subsystem_device ||
14412 q->subsystem_device == PCI_ANY_ID))
14413 q->hook(dev);
14414 }
14415 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14416 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14417 intel_dmi_quirks[i].hook(dev);
14418 }
14419 }
14420
14421 /* Disable the VGA plane that we never use */
14422 static void i915_disable_vga(struct drm_device *dev)
14423 {
14424 struct drm_i915_private *dev_priv = dev->dev_private;
14425 u8 sr1;
14426 u32 vga_reg = i915_vgacntrl_reg(dev);
14427
14428 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14429 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14430 outb(SR01, VGA_SR_INDEX);
14431 sr1 = inb(VGA_SR_DATA);
14432 outb(sr1 | 1<<5, VGA_SR_DATA);
14433 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14434 udelay(300);
14435
14436 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14437 POSTING_READ(vga_reg);
14438 }
14439
14440 void intel_modeset_init_hw(struct drm_device *dev)
14441 {
14442 intel_prepare_ddi(dev);
14443
14444 if (IS_VALLEYVIEW(dev))
14445 vlv_update_cdclk(dev);
14446
14447 intel_init_clock_gating(dev);
14448
14449 intel_enable_gt_powersave(dev);
14450 }
14451
14452 void intel_modeset_init(struct drm_device *dev)
14453 {
14454 struct drm_i915_private *dev_priv = dev->dev_private;
14455 int sprite, ret;
14456 enum pipe pipe;
14457 struct intel_crtc *crtc;
14458
14459 drm_mode_config_init(dev);
14460
14461 dev->mode_config.min_width = 0;
14462 dev->mode_config.min_height = 0;
14463
14464 dev->mode_config.preferred_depth = 24;
14465 dev->mode_config.prefer_shadow = 1;
14466
14467 dev->mode_config.allow_fb_modifiers = true;
14468
14469 dev->mode_config.funcs = &intel_mode_funcs;
14470
14471 intel_init_quirks(dev);
14472
14473 intel_init_pm(dev);
14474
14475 if (INTEL_INFO(dev)->num_pipes == 0)
14476 return;
14477
14478 intel_init_display(dev);
14479 intel_init_audio(dev);
14480
14481 if (IS_GEN2(dev)) {
14482 dev->mode_config.max_width = 2048;
14483 dev->mode_config.max_height = 2048;
14484 } else if (IS_GEN3(dev)) {
14485 dev->mode_config.max_width = 4096;
14486 dev->mode_config.max_height = 4096;
14487 } else {
14488 dev->mode_config.max_width = 8192;
14489 dev->mode_config.max_height = 8192;
14490 }
14491
14492 if (IS_845G(dev) || IS_I865G(dev)) {
14493 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14494 dev->mode_config.cursor_height = 1023;
14495 } else if (IS_GEN2(dev)) {
14496 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14497 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14498 } else {
14499 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14500 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14501 }
14502
14503 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14504
14505 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14506 INTEL_INFO(dev)->num_pipes,
14507 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14508
14509 for_each_pipe(dev_priv, pipe) {
14510 intel_crtc_init(dev, pipe);
14511 for_each_sprite(dev_priv, pipe, sprite) {
14512 ret = intel_plane_init(dev, pipe, sprite);
14513 if (ret)
14514 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14515 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14516 }
14517 }
14518
14519 intel_init_dpio(dev);
14520
14521 intel_shared_dpll_init(dev);
14522
14523 /* Just disable it once at startup */
14524 i915_disable_vga(dev);
14525 intel_setup_outputs(dev);
14526
14527 /* Just in case the BIOS is doing something questionable. */
14528 intel_fbc_disable(dev);
14529
14530 drm_modeset_lock_all(dev);
14531 intel_modeset_setup_hw_state(dev, false);
14532 drm_modeset_unlock_all(dev);
14533
14534 for_each_intel_crtc(dev, crtc) {
14535 if (!crtc->active)
14536 continue;
14537
14538 /*
14539 * Note that reserving the BIOS fb up front prevents us
14540 * from stuffing other stolen allocations like the ring
14541 * on top. This prevents some ugliness at boot time, and
14542 * can even allow for smooth boot transitions if the BIOS
14543 * fb is large enough for the active pipe configuration.
14544 */
14545 if (dev_priv->display.get_initial_plane_config) {
14546 dev_priv->display.get_initial_plane_config(crtc,
14547 &crtc->plane_config);
14548 /*
14549 * If the fb is shared between multiple heads, we'll
14550 * just get the first one.
14551 */
14552 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14553 }
14554 }
14555 }
14556
14557 static void intel_enable_pipe_a(struct drm_device *dev)
14558 {
14559 struct intel_connector *connector;
14560 struct drm_connector *crt = NULL;
14561 struct intel_load_detect_pipe load_detect_temp;
14562 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14563
14564 /* We can't just switch on the pipe A, we need to set things up with a
14565 * proper mode and output configuration. As a gross hack, enable pipe A
14566 * by enabling the load detect pipe once. */
14567 for_each_intel_connector(dev, connector) {
14568 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14569 crt = &connector->base;
14570 break;
14571 }
14572 }
14573
14574 if (!crt)
14575 return;
14576
14577 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14578 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14579 }
14580
14581 static bool
14582 intel_check_plane_mapping(struct intel_crtc *crtc)
14583 {
14584 struct drm_device *dev = crtc->base.dev;
14585 struct drm_i915_private *dev_priv = dev->dev_private;
14586 u32 reg, val;
14587
14588 if (INTEL_INFO(dev)->num_pipes == 1)
14589 return true;
14590
14591 reg = DSPCNTR(!crtc->plane);
14592 val = I915_READ(reg);
14593
14594 if ((val & DISPLAY_PLANE_ENABLE) &&
14595 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14596 return false;
14597
14598 return true;
14599 }
14600
14601 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14602 {
14603 struct drm_device *dev = crtc->base.dev;
14604 struct drm_i915_private *dev_priv = dev->dev_private;
14605 u32 reg;
14606
14607 /* Clear any frame start delays used for debugging left by the BIOS */
14608 reg = PIPECONF(crtc->config->cpu_transcoder);
14609 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14610
14611 /* restore vblank interrupts to correct state */
14612 drm_crtc_vblank_reset(&crtc->base);
14613 if (crtc->active) {
14614 update_scanline_offset(crtc);
14615 drm_crtc_vblank_on(&crtc->base);
14616 }
14617
14618 /* We need to sanitize the plane -> pipe mapping first because this will
14619 * disable the crtc (and hence change the state) if it is wrong. Note
14620 * that gen4+ has a fixed plane -> pipe mapping. */
14621 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14622 struct intel_connector *connector;
14623 bool plane;
14624
14625 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14626 crtc->base.base.id);
14627
14628 /* Pipe has the wrong plane attached and the plane is active.
14629 * Temporarily change the plane mapping and disable everything
14630 * ... */
14631 plane = crtc->plane;
14632 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14633 crtc->plane = !plane;
14634 intel_crtc_disable_planes(&crtc->base);
14635 dev_priv->display.crtc_disable(&crtc->base);
14636 crtc->plane = plane;
14637
14638 /* ... and break all links. */
14639 for_each_intel_connector(dev, connector) {
14640 if (connector->encoder->base.crtc != &crtc->base)
14641 continue;
14642
14643 connector->base.dpms = DRM_MODE_DPMS_OFF;
14644 connector->base.encoder = NULL;
14645 }
14646 /* multiple connectors may have the same encoder:
14647 * handle them and break crtc link separately */
14648 for_each_intel_connector(dev, connector)
14649 if (connector->encoder->base.crtc == &crtc->base) {
14650 connector->encoder->base.crtc = NULL;
14651 connector->encoder->connectors_active = false;
14652 }
14653
14654 WARN_ON(crtc->active);
14655 crtc->base.state->enable = false;
14656 crtc->base.state->active = false;
14657 crtc->base.enabled = false;
14658 }
14659
14660 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14661 crtc->pipe == PIPE_A && !crtc->active) {
14662 /* BIOS forgot to enable pipe A, this mostly happens after
14663 * resume. Force-enable the pipe to fix this, the update_dpms
14664 * call below we restore the pipe to the right state, but leave
14665 * the required bits on. */
14666 intel_enable_pipe_a(dev);
14667 }
14668
14669 /* Adjust the state of the output pipe according to whether we
14670 * have active connectors/encoders. */
14671 intel_crtc_update_dpms(&crtc->base);
14672
14673 if (crtc->active != crtc->base.state->enable) {
14674 struct intel_encoder *encoder;
14675
14676 /* This can happen either due to bugs in the get_hw_state
14677 * functions or because the pipe is force-enabled due to the
14678 * pipe A quirk. */
14679 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14680 crtc->base.base.id,
14681 crtc->base.state->enable ? "enabled" : "disabled",
14682 crtc->active ? "enabled" : "disabled");
14683
14684 crtc->base.state->enable = crtc->active;
14685 crtc->base.state->active = crtc->active;
14686 crtc->base.enabled = crtc->active;
14687
14688 /* Because we only establish the connector -> encoder ->
14689 * crtc links if something is active, this means the
14690 * crtc is now deactivated. Break the links. connector
14691 * -> encoder links are only establish when things are
14692 * actually up, hence no need to break them. */
14693 WARN_ON(crtc->active);
14694
14695 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14696 WARN_ON(encoder->connectors_active);
14697 encoder->base.crtc = NULL;
14698 }
14699 }
14700
14701 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14702 /*
14703 * We start out with underrun reporting disabled to avoid races.
14704 * For correct bookkeeping mark this on active crtcs.
14705 *
14706 * Also on gmch platforms we dont have any hardware bits to
14707 * disable the underrun reporting. Which means we need to start
14708 * out with underrun reporting disabled also on inactive pipes,
14709 * since otherwise we'll complain about the garbage we read when
14710 * e.g. coming up after runtime pm.
14711 *
14712 * No protection against concurrent access is required - at
14713 * worst a fifo underrun happens which also sets this to false.
14714 */
14715 crtc->cpu_fifo_underrun_disabled = true;
14716 crtc->pch_fifo_underrun_disabled = true;
14717 }
14718 }
14719
14720 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14721 {
14722 struct intel_connector *connector;
14723 struct drm_device *dev = encoder->base.dev;
14724
14725 /* We need to check both for a crtc link (meaning that the
14726 * encoder is active and trying to read from a pipe) and the
14727 * pipe itself being active. */
14728 bool has_active_crtc = encoder->base.crtc &&
14729 to_intel_crtc(encoder->base.crtc)->active;
14730
14731 if (encoder->connectors_active && !has_active_crtc) {
14732 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14733 encoder->base.base.id,
14734 encoder->base.name);
14735
14736 /* Connector is active, but has no active pipe. This is
14737 * fallout from our resume register restoring. Disable
14738 * the encoder manually again. */
14739 if (encoder->base.crtc) {
14740 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14741 encoder->base.base.id,
14742 encoder->base.name);
14743 encoder->disable(encoder);
14744 if (encoder->post_disable)
14745 encoder->post_disable(encoder);
14746 }
14747 encoder->base.crtc = NULL;
14748 encoder->connectors_active = false;
14749
14750 /* Inconsistent output/port/pipe state happens presumably due to
14751 * a bug in one of the get_hw_state functions. Or someplace else
14752 * in our code, like the register restore mess on resume. Clamp
14753 * things to off as a safer default. */
14754 for_each_intel_connector(dev, connector) {
14755 if (connector->encoder != encoder)
14756 continue;
14757 connector->base.dpms = DRM_MODE_DPMS_OFF;
14758 connector->base.encoder = NULL;
14759 }
14760 }
14761 /* Enabled encoders without active connectors will be fixed in
14762 * the crtc fixup. */
14763 }
14764
14765 void i915_redisable_vga_power_on(struct drm_device *dev)
14766 {
14767 struct drm_i915_private *dev_priv = dev->dev_private;
14768 u32 vga_reg = i915_vgacntrl_reg(dev);
14769
14770 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14771 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14772 i915_disable_vga(dev);
14773 }
14774 }
14775
14776 void i915_redisable_vga(struct drm_device *dev)
14777 {
14778 struct drm_i915_private *dev_priv = dev->dev_private;
14779
14780 /* This function can be called both from intel_modeset_setup_hw_state or
14781 * at a very early point in our resume sequence, where the power well
14782 * structures are not yet restored. Since this function is at a very
14783 * paranoid "someone might have enabled VGA while we were not looking"
14784 * level, just check if the power well is enabled instead of trying to
14785 * follow the "don't touch the power well if we don't need it" policy
14786 * the rest of the driver uses. */
14787 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14788 return;
14789
14790 i915_redisable_vga_power_on(dev);
14791 }
14792
14793 static bool primary_get_hw_state(struct intel_crtc *crtc)
14794 {
14795 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14796
14797 if (!crtc->active)
14798 return false;
14799
14800 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14801 }
14802
14803 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14804 {
14805 struct drm_i915_private *dev_priv = dev->dev_private;
14806 enum pipe pipe;
14807 struct intel_crtc *crtc;
14808 struct intel_encoder *encoder;
14809 struct intel_connector *connector;
14810 int i;
14811
14812 for_each_intel_crtc(dev, crtc) {
14813 struct drm_plane *primary = crtc->base.primary;
14814 struct intel_plane_state *plane_state;
14815
14816 memset(crtc->config, 0, sizeof(*crtc->config));
14817
14818 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14819
14820 crtc->active = dev_priv->display.get_pipe_config(crtc,
14821 crtc->config);
14822
14823 crtc->base.state->enable = crtc->active;
14824 crtc->base.state->active = crtc->active;
14825 crtc->base.enabled = crtc->active;
14826
14827 plane_state = to_intel_plane_state(primary->state);
14828 plane_state->visible = primary_get_hw_state(crtc);
14829
14830 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14831 crtc->base.base.id,
14832 crtc->active ? "enabled" : "disabled");
14833 }
14834
14835 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14836 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14837
14838 pll->on = pll->get_hw_state(dev_priv, pll,
14839 &pll->config.hw_state);
14840 pll->active = 0;
14841 pll->config.crtc_mask = 0;
14842 for_each_intel_crtc(dev, crtc) {
14843 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14844 pll->active++;
14845 pll->config.crtc_mask |= 1 << crtc->pipe;
14846 }
14847 }
14848
14849 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14850 pll->name, pll->config.crtc_mask, pll->on);
14851
14852 if (pll->config.crtc_mask)
14853 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14854 }
14855
14856 for_each_intel_encoder(dev, encoder) {
14857 pipe = 0;
14858
14859 if (encoder->get_hw_state(encoder, &pipe)) {
14860 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14861 encoder->base.crtc = &crtc->base;
14862 encoder->get_config(encoder, crtc->config);
14863 } else {
14864 encoder->base.crtc = NULL;
14865 }
14866
14867 encoder->connectors_active = false;
14868 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14869 encoder->base.base.id,
14870 encoder->base.name,
14871 encoder->base.crtc ? "enabled" : "disabled",
14872 pipe_name(pipe));
14873 }
14874
14875 for_each_intel_connector(dev, connector) {
14876 if (connector->get_hw_state(connector)) {
14877 connector->base.dpms = DRM_MODE_DPMS_ON;
14878 connector->encoder->connectors_active = true;
14879 connector->base.encoder = &connector->encoder->base;
14880 } else {
14881 connector->base.dpms = DRM_MODE_DPMS_OFF;
14882 connector->base.encoder = NULL;
14883 }
14884 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14885 connector->base.base.id,
14886 connector->base.name,
14887 connector->base.encoder ? "enabled" : "disabled");
14888 }
14889 }
14890
14891 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14892 * and i915 state tracking structures. */
14893 void intel_modeset_setup_hw_state(struct drm_device *dev,
14894 bool force_restore)
14895 {
14896 struct drm_i915_private *dev_priv = dev->dev_private;
14897 enum pipe pipe;
14898 struct intel_crtc *crtc;
14899 struct intel_encoder *encoder;
14900 int i;
14901
14902 intel_modeset_readout_hw_state(dev);
14903
14904 /*
14905 * Now that we have the config, copy it to each CRTC struct
14906 * Note that this could go away if we move to using crtc_config
14907 * checking everywhere.
14908 */
14909 for_each_intel_crtc(dev, crtc) {
14910 if (crtc->active && i915.fastboot) {
14911 intel_mode_from_pipe_config(&crtc->base.mode,
14912 crtc->config);
14913 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14914 crtc->base.base.id);
14915 drm_mode_debug_printmodeline(&crtc->base.mode);
14916 }
14917 }
14918
14919 /* HW state is read out, now we need to sanitize this mess. */
14920 for_each_intel_encoder(dev, encoder) {
14921 intel_sanitize_encoder(encoder);
14922 }
14923
14924 for_each_pipe(dev_priv, pipe) {
14925 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14926 intel_sanitize_crtc(crtc);
14927 intel_dump_pipe_config(crtc, crtc->config,
14928 "[setup_hw_state]");
14929 }
14930
14931 intel_modeset_update_connector_atomic_state(dev);
14932
14933 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14934 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14935
14936 if (!pll->on || pll->active)
14937 continue;
14938
14939 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14940
14941 pll->disable(dev_priv, pll);
14942 pll->on = false;
14943 }
14944
14945 if (IS_GEN9(dev))
14946 skl_wm_get_hw_state(dev);
14947 else if (HAS_PCH_SPLIT(dev))
14948 ilk_wm_get_hw_state(dev);
14949
14950 if (force_restore) {
14951 i915_redisable_vga(dev);
14952
14953 /*
14954 * We need to use raw interfaces for restoring state to avoid
14955 * checking (bogus) intermediate states.
14956 */
14957 for_each_pipe(dev_priv, pipe) {
14958 struct drm_crtc *crtc =
14959 dev_priv->pipe_to_crtc_mapping[pipe];
14960
14961 intel_crtc_restore_mode(crtc);
14962 }
14963 } else {
14964 intel_modeset_update_staged_output_state(dev);
14965 }
14966
14967 intel_modeset_check_state(dev);
14968 }
14969
14970 void intel_modeset_gem_init(struct drm_device *dev)
14971 {
14972 struct drm_i915_private *dev_priv = dev->dev_private;
14973 struct drm_crtc *c;
14974 struct drm_i915_gem_object *obj;
14975 int ret;
14976
14977 mutex_lock(&dev->struct_mutex);
14978 intel_init_gt_powersave(dev);
14979 mutex_unlock(&dev->struct_mutex);
14980
14981 /*
14982 * There may be no VBT; and if the BIOS enabled SSC we can
14983 * just keep using it to avoid unnecessary flicker. Whereas if the
14984 * BIOS isn't using it, don't assume it will work even if the VBT
14985 * indicates as much.
14986 */
14987 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14988 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14989 DREF_SSC1_ENABLE);
14990
14991 intel_modeset_init_hw(dev);
14992
14993 intel_setup_overlay(dev);
14994
14995 /*
14996 * Make sure any fbs we allocated at startup are properly
14997 * pinned & fenced. When we do the allocation it's too early
14998 * for this.
14999 */
15000 for_each_crtc(dev, c) {
15001 obj = intel_fb_obj(c->primary->fb);
15002 if (obj == NULL)
15003 continue;
15004
15005 mutex_lock(&dev->struct_mutex);
15006 ret = intel_pin_and_fence_fb_obj(c->primary,
15007 c->primary->fb,
15008 c->primary->state,
15009 NULL);
15010 mutex_unlock(&dev->struct_mutex);
15011 if (ret) {
15012 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15013 to_intel_crtc(c)->pipe);
15014 drm_framebuffer_unreference(c->primary->fb);
15015 c->primary->fb = NULL;
15016 update_state_fb(c->primary);
15017 }
15018 }
15019
15020 intel_backlight_register(dev);
15021 }
15022
15023 void intel_connector_unregister(struct intel_connector *intel_connector)
15024 {
15025 struct drm_connector *connector = &intel_connector->base;
15026
15027 intel_panel_destroy_backlight(connector);
15028 drm_connector_unregister(connector);
15029 }
15030
15031 void intel_modeset_cleanup(struct drm_device *dev)
15032 {
15033 struct drm_i915_private *dev_priv = dev->dev_private;
15034 struct drm_connector *connector;
15035
15036 intel_disable_gt_powersave(dev);
15037
15038 intel_backlight_unregister(dev);
15039
15040 /*
15041 * Interrupts and polling as the first thing to avoid creating havoc.
15042 * Too much stuff here (turning of connectors, ...) would
15043 * experience fancy races otherwise.
15044 */
15045 intel_irq_uninstall(dev_priv);
15046
15047 /*
15048 * Due to the hpd irq storm handling the hotplug work can re-arm the
15049 * poll handlers. Hence disable polling after hpd handling is shut down.
15050 */
15051 drm_kms_helper_poll_fini(dev);
15052
15053 mutex_lock(&dev->struct_mutex);
15054
15055 intel_unregister_dsm_handler();
15056
15057 intel_fbc_disable(dev);
15058
15059 mutex_unlock(&dev->struct_mutex);
15060
15061 /* flush any delayed tasks or pending work */
15062 flush_scheduled_work();
15063
15064 /* destroy the backlight and sysfs files before encoders/connectors */
15065 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15066 struct intel_connector *intel_connector;
15067
15068 intel_connector = to_intel_connector(connector);
15069 intel_connector->unregister(intel_connector);
15070 }
15071
15072 drm_mode_config_cleanup(dev);
15073
15074 intel_cleanup_overlay(dev);
15075
15076 mutex_lock(&dev->struct_mutex);
15077 intel_cleanup_gt_powersave(dev);
15078 mutex_unlock(&dev->struct_mutex);
15079 }
15080
15081 /*
15082 * Return which encoder is currently attached for connector.
15083 */
15084 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15085 {
15086 return &intel_attached_encoder(connector)->base;
15087 }
15088
15089 void intel_connector_attach_encoder(struct intel_connector *connector,
15090 struct intel_encoder *encoder)
15091 {
15092 connector->encoder = encoder;
15093 drm_mode_connector_attach_encoder(&connector->base,
15094 &encoder->base);
15095 }
15096
15097 /*
15098 * set vga decode state - true == enable VGA decode
15099 */
15100 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15101 {
15102 struct drm_i915_private *dev_priv = dev->dev_private;
15103 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15104 u16 gmch_ctrl;
15105
15106 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15107 DRM_ERROR("failed to read control word\n");
15108 return -EIO;
15109 }
15110
15111 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15112 return 0;
15113
15114 if (state)
15115 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15116 else
15117 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15118
15119 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15120 DRM_ERROR("failed to write control word\n");
15121 return -EIO;
15122 }
15123
15124 return 0;
15125 }
15126
15127 struct intel_display_error_state {
15128
15129 u32 power_well_driver;
15130
15131 int num_transcoders;
15132
15133 struct intel_cursor_error_state {
15134 u32 control;
15135 u32 position;
15136 u32 base;
15137 u32 size;
15138 } cursor[I915_MAX_PIPES];
15139
15140 struct intel_pipe_error_state {
15141 bool power_domain_on;
15142 u32 source;
15143 u32 stat;
15144 } pipe[I915_MAX_PIPES];
15145
15146 struct intel_plane_error_state {
15147 u32 control;
15148 u32 stride;
15149 u32 size;
15150 u32 pos;
15151 u32 addr;
15152 u32 surface;
15153 u32 tile_offset;
15154 } plane[I915_MAX_PIPES];
15155
15156 struct intel_transcoder_error_state {
15157 bool power_domain_on;
15158 enum transcoder cpu_transcoder;
15159
15160 u32 conf;
15161
15162 u32 htotal;
15163 u32 hblank;
15164 u32 hsync;
15165 u32 vtotal;
15166 u32 vblank;
15167 u32 vsync;
15168 } transcoder[4];
15169 };
15170
15171 struct intel_display_error_state *
15172 intel_display_capture_error_state(struct drm_device *dev)
15173 {
15174 struct drm_i915_private *dev_priv = dev->dev_private;
15175 struct intel_display_error_state *error;
15176 int transcoders[] = {
15177 TRANSCODER_A,
15178 TRANSCODER_B,
15179 TRANSCODER_C,
15180 TRANSCODER_EDP,
15181 };
15182 int i;
15183
15184 if (INTEL_INFO(dev)->num_pipes == 0)
15185 return NULL;
15186
15187 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15188 if (error == NULL)
15189 return NULL;
15190
15191 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15192 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15193
15194 for_each_pipe(dev_priv, i) {
15195 error->pipe[i].power_domain_on =
15196 __intel_display_power_is_enabled(dev_priv,
15197 POWER_DOMAIN_PIPE(i));
15198 if (!error->pipe[i].power_domain_on)
15199 continue;
15200
15201 error->cursor[i].control = I915_READ(CURCNTR(i));
15202 error->cursor[i].position = I915_READ(CURPOS(i));
15203 error->cursor[i].base = I915_READ(CURBASE(i));
15204
15205 error->plane[i].control = I915_READ(DSPCNTR(i));
15206 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15207 if (INTEL_INFO(dev)->gen <= 3) {
15208 error->plane[i].size = I915_READ(DSPSIZE(i));
15209 error->plane[i].pos = I915_READ(DSPPOS(i));
15210 }
15211 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15212 error->plane[i].addr = I915_READ(DSPADDR(i));
15213 if (INTEL_INFO(dev)->gen >= 4) {
15214 error->plane[i].surface = I915_READ(DSPSURF(i));
15215 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15216 }
15217
15218 error->pipe[i].source = I915_READ(PIPESRC(i));
15219
15220 if (HAS_GMCH_DISPLAY(dev))
15221 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15222 }
15223
15224 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15225 if (HAS_DDI(dev_priv->dev))
15226 error->num_transcoders++; /* Account for eDP. */
15227
15228 for (i = 0; i < error->num_transcoders; i++) {
15229 enum transcoder cpu_transcoder = transcoders[i];
15230
15231 error->transcoder[i].power_domain_on =
15232 __intel_display_power_is_enabled(dev_priv,
15233 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15234 if (!error->transcoder[i].power_domain_on)
15235 continue;
15236
15237 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15238
15239 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15240 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15241 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15242 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15243 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15244 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15245 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15246 }
15247
15248 return error;
15249 }
15250
15251 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15252
15253 void
15254 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15255 struct drm_device *dev,
15256 struct intel_display_error_state *error)
15257 {
15258 struct drm_i915_private *dev_priv = dev->dev_private;
15259 int i;
15260
15261 if (!error)
15262 return;
15263
15264 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15265 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15266 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15267 error->power_well_driver);
15268 for_each_pipe(dev_priv, i) {
15269 err_printf(m, "Pipe [%d]:\n", i);
15270 err_printf(m, " Power: %s\n",
15271 error->pipe[i].power_domain_on ? "on" : "off");
15272 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15273 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15274
15275 err_printf(m, "Plane [%d]:\n", i);
15276 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15277 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15278 if (INTEL_INFO(dev)->gen <= 3) {
15279 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15280 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15281 }
15282 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15283 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15284 if (INTEL_INFO(dev)->gen >= 4) {
15285 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15286 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15287 }
15288
15289 err_printf(m, "Cursor [%d]:\n", i);
15290 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15291 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15292 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15293 }
15294
15295 for (i = 0; i < error->num_transcoders; i++) {
15296 err_printf(m, "CPU transcoder: %c\n",
15297 transcoder_name(error->transcoder[i].cpu_transcoder));
15298 err_printf(m, " Power: %s\n",
15299 error->transcoder[i].power_domain_on ? "on" : "off");
15300 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15301 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15302 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15303 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15304 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15305 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15306 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15307 }
15308 }
15309
15310 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15311 {
15312 struct intel_crtc *crtc;
15313
15314 for_each_intel_crtc(dev, crtc) {
15315 struct intel_unpin_work *work;
15316
15317 spin_lock_irq(&dev->event_lock);
15318
15319 work = crtc->unpin_work;
15320
15321 if (work && work->event &&
15322 work->event->base.file_priv == file) {
15323 kfree(work->event);
15324 work->event = NULL;
15325 }
15326
15327 spin_unlock_irq(&dev->event_lock);
15328 }
15329 }
Linux kernel - Deliverables
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