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drm/i915: Kill intel_plane->obj
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 static bool
780 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
781 int target, int refclk, intel_clock_t *match_clock,
782 intel_clock_t *best_clock)
783 {
784 struct drm_device *dev = crtc->base.dev;
785 intel_clock_t clock;
786 unsigned int bestppm = 1000000;
787 /* min update 19.2 MHz */
788 int max_n = min(limit->n.max, refclk / 19200);
789 bool found = false;
790
791 target *= 5; /* fast clock */
792
793 memset(best_clock, 0, sizeof(*best_clock));
794
795 /* based on hardware requirement, prefer smaller n to precision */
796 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
797 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
798 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
799 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
800 clock.p = clock.p1 * clock.p2;
801 /* based on hardware requirement, prefer bigger m1,m2 values */
802 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
803 unsigned int ppm, diff;
804
805 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
806 refclk * clock.m1);
807
808 vlv_clock(refclk, &clock);
809
810 if (!intel_PLL_is_valid(dev, limit,
811 &clock))
812 continue;
813
814 diff = abs(clock.dot - target);
815 ppm = div_u64(1000000ULL * diff, target);
816
817 if (ppm < 100 && clock.p > best_clock->p) {
818 bestppm = 0;
819 *best_clock = clock;
820 found = true;
821 }
822
823 if (bestppm >= 10 && ppm < bestppm - 10) {
824 bestppm = ppm;
825 *best_clock = clock;
826 found = true;
827 }
828 }
829 }
830 }
831 }
832
833 return found;
834 }
835
836 static bool
837 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
838 int target, int refclk, intel_clock_t *match_clock,
839 intel_clock_t *best_clock)
840 {
841 struct drm_device *dev = crtc->base.dev;
842 intel_clock_t clock;
843 uint64_t m2;
844 int found = false;
845
846 memset(best_clock, 0, sizeof(*best_clock));
847
848 /*
849 * Based on hardware doc, the n always set to 1, and m1 always
850 * set to 2. If requires to support 200Mhz refclk, we need to
851 * revisit this because n may not 1 anymore.
852 */
853 clock.n = 1, clock.m1 = 2;
854 target *= 5; /* fast clock */
855
856 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
857 for (clock.p2 = limit->p2.p2_fast;
858 clock.p2 >= limit->p2.p2_slow;
859 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
860
861 clock.p = clock.p1 * clock.p2;
862
863 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
864 clock.n) << 22, refclk * clock.m1);
865
866 if (m2 > INT_MAX/clock.m1)
867 continue;
868
869 clock.m2 = m2;
870
871 chv_clock(refclk, &clock);
872
873 if (!intel_PLL_is_valid(dev, limit, &clock))
874 continue;
875
876 /* based on hardware requirement, prefer bigger p
877 */
878 if (clock.p > best_clock->p) {
879 *best_clock = clock;
880 found = true;
881 }
882 }
883 }
884
885 return found;
886 }
887
888 bool intel_crtc_active(struct drm_crtc *crtc)
889 {
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 /* Be paranoid as we can arrive here with only partial
893 * state retrieved from the hardware during setup.
894 *
895 * We can ditch the adjusted_mode.crtc_clock check as soon
896 * as Haswell has gained clock readout/fastboot support.
897 *
898 * We can ditch the crtc->primary->fb check as soon as we can
899 * properly reconstruct framebuffers.
900 *
901 * FIXME: The intel_crtc->active here should be switched to
902 * crtc->state->active once we have proper CRTC states wired up
903 * for atomic.
904 */
905 return intel_crtc->active && crtc->primary->state->fb &&
906 intel_crtc->config->base.adjusted_mode.crtc_clock;
907 }
908
909 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
910 enum pipe pipe)
911 {
912 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
914
915 return intel_crtc->config->cpu_transcoder;
916 }
917
918 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
919 {
920 struct drm_i915_private *dev_priv = dev->dev_private;
921 u32 reg = PIPEDSL(pipe);
922 u32 line1, line2;
923 u32 line_mask;
924
925 if (IS_GEN2(dev))
926 line_mask = DSL_LINEMASK_GEN2;
927 else
928 line_mask = DSL_LINEMASK_GEN3;
929
930 line1 = I915_READ(reg) & line_mask;
931 mdelay(5);
932 line2 = I915_READ(reg) & line_mask;
933
934 return line1 == line2;
935 }
936
937 /*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
939 * @crtc: crtc whose pipe to wait for
940 *
941 * After disabling a pipe, we can't wait for vblank in the usual way,
942 * spinning on the vblank interrupt status bit, since we won't actually
943 * see an interrupt when the pipe is disabled.
944 *
945 * On Gen4 and above:
946 * wait for the pipe register state bit to turn off
947 *
948 * Otherwise:
949 * wait for the display line value to settle (it usually
950 * ends up stopping at the start of the next frame).
951 *
952 */
953 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
954 {
955 struct drm_device *dev = crtc->base.dev;
956 struct drm_i915_private *dev_priv = dev->dev_private;
957 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
958 enum pipe pipe = crtc->pipe;
959
960 if (INTEL_INFO(dev)->gen >= 4) {
961 int reg = PIPECONF(cpu_transcoder);
962
963 /* Wait for the Pipe State to go off */
964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
966 WARN(1, "pipe_off wait timed out\n");
967 } else {
968 /* Wait for the display line to settle */
969 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
970 WARN(1, "pipe_off wait timed out\n");
971 }
972 }
973
974 /*
975 * ibx_digital_port_connected - is the specified port connected?
976 * @dev_priv: i915 private structure
977 * @port: the port to test
978 *
979 * Returns true if @port is connected, false otherwise.
980 */
981 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
982 struct intel_digital_port *port)
983 {
984 u32 bit;
985
986 if (HAS_PCH_IBX(dev_priv->dev)) {
987 switch (port->port) {
988 case PORT_B:
989 bit = SDE_PORTB_HOTPLUG;
990 break;
991 case PORT_C:
992 bit = SDE_PORTC_HOTPLUG;
993 break;
994 case PORT_D:
995 bit = SDE_PORTD_HOTPLUG;
996 break;
997 default:
998 return true;
999 }
1000 } else {
1001 switch (port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG_CPT;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG_CPT;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG_CPT;
1010 break;
1011 default:
1012 return true;
1013 }
1014 }
1015
1016 return I915_READ(SDEISR) & bit;
1017 }
1018
1019 static const char *state_string(bool enabled)
1020 {
1021 return enabled ? "on" : "off";
1022 }
1023
1024 /* Only for pre-ILK configs */
1025 void assert_pll(struct drm_i915_private *dev_priv,
1026 enum pipe pipe, bool state)
1027 {
1028 int reg;
1029 u32 val;
1030 bool cur_state;
1031
1032 reg = DPLL(pipe);
1033 val = I915_READ(reg);
1034 cur_state = !!(val & DPLL_VCO_ENABLE);
1035 I915_STATE_WARN(cur_state != state,
1036 "PLL state assertion failure (expected %s, current %s)\n",
1037 state_string(state), state_string(cur_state));
1038 }
1039
1040 /* XXX: the dsi pll is shared between MIPI DSI ports */
1041 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1042 {
1043 u32 val;
1044 bool cur_state;
1045
1046 mutex_lock(&dev_priv->dpio_lock);
1047 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1048 mutex_unlock(&dev_priv->dpio_lock);
1049
1050 cur_state = val & DSI_PLL_VCO_EN;
1051 I915_STATE_WARN(cur_state != state,
1052 "DSI PLL state assertion failure (expected %s, current %s)\n",
1053 state_string(state), state_string(cur_state));
1054 }
1055 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1056 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1057
1058 struct intel_shared_dpll *
1059 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1060 {
1061 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1062
1063 if (crtc->config->shared_dpll < 0)
1064 return NULL;
1065
1066 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1067 }
1068
1069 /* For ILK+ */
1070 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1071 struct intel_shared_dpll *pll,
1072 bool state)
1073 {
1074 bool cur_state;
1075 struct intel_dpll_hw_state hw_state;
1076
1077 if (WARN (!pll,
1078 "asserting DPLL %s with no DPLL\n", state_string(state)))
1079 return;
1080
1081 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1082 I915_STATE_WARN(cur_state != state,
1083 "%s assertion failure (expected %s, current %s)\n",
1084 pll->name, state_string(state), state_string(cur_state));
1085 }
1086
1087 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1088 enum pipe pipe, bool state)
1089 {
1090 int reg;
1091 u32 val;
1092 bool cur_state;
1093 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1094 pipe);
1095
1096 if (HAS_DDI(dev_priv->dev)) {
1097 /* DDI does not have a specific FDI_TX register */
1098 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1099 val = I915_READ(reg);
1100 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1101 } else {
1102 reg = FDI_TX_CTL(pipe);
1103 val = I915_READ(reg);
1104 cur_state = !!(val & FDI_TX_ENABLE);
1105 }
1106 I915_STATE_WARN(cur_state != state,
1107 "FDI TX state assertion failure (expected %s, current %s)\n",
1108 state_string(state), state_string(cur_state));
1109 }
1110 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1111 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1112
1113 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1114 enum pipe pipe, bool state)
1115 {
1116 int reg;
1117 u32 val;
1118 bool cur_state;
1119
1120 reg = FDI_RX_CTL(pipe);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & FDI_RX_ENABLE);
1123 I915_STATE_WARN(cur_state != state,
1124 "FDI RX state assertion failure (expected %s, current %s)\n",
1125 state_string(state), state_string(cur_state));
1126 }
1127 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1128 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1129
1130 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132 {
1133 int reg;
1134 u32 val;
1135
1136 /* ILK FDI PLL is always enabled */
1137 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1138 return;
1139
1140 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1141 if (HAS_DDI(dev_priv->dev))
1142 return;
1143
1144 reg = FDI_TX_CTL(pipe);
1145 val = I915_READ(reg);
1146 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1147 }
1148
1149 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1150 enum pipe pipe, bool state)
1151 {
1152 int reg;
1153 u32 val;
1154 bool cur_state;
1155
1156 reg = FDI_RX_CTL(pipe);
1157 val = I915_READ(reg);
1158 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1159 I915_STATE_WARN(cur_state != state,
1160 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1161 state_string(state), state_string(cur_state));
1162 }
1163
1164 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166 {
1167 struct drm_device *dev = dev_priv->dev;
1168 int pp_reg;
1169 u32 val;
1170 enum pipe panel_pipe = PIPE_A;
1171 bool locked = true;
1172
1173 if (WARN_ON(HAS_DDI(dev)))
1174 return;
1175
1176 if (HAS_PCH_SPLIT(dev)) {
1177 u32 port_sel;
1178
1179 pp_reg = PCH_PP_CONTROL;
1180 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1181
1182 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1183 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1184 panel_pipe = PIPE_B;
1185 /* XXX: else fix for eDP */
1186 } else if (IS_VALLEYVIEW(dev)) {
1187 /* presumably write lock depends on pipe, not port select */
1188 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1189 panel_pipe = pipe;
1190 } else {
1191 pp_reg = PP_CONTROL;
1192 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1193 panel_pipe = PIPE_B;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 I915_STATE_WARN(panel_pipe == pipe && locked,
1202 "panel assertion failure, pipe %c regs locked\n",
1203 pipe_name(pipe));
1204 }
1205
1206 static void assert_cursor(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 struct drm_device *dev = dev_priv->dev;
1210 bool cur_state;
1211
1212 if (IS_845G(dev) || IS_I865G(dev))
1213 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1214 else
1215 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1216
1217 I915_STATE_WARN(cur_state != state,
1218 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1219 pipe_name(pipe), state_string(state), state_string(cur_state));
1220 }
1221 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1222 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1223
1224 void assert_pipe(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, bool state)
1226 {
1227 int reg;
1228 u32 val;
1229 bool cur_state;
1230 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1231 pipe);
1232
1233 /* if we need the pipe quirk it must be always on */
1234 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1235 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1236 state = true;
1237
1238 if (!intel_display_power_is_enabled(dev_priv,
1239 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1240 cur_state = false;
1241 } else {
1242 reg = PIPECONF(cpu_transcoder);
1243 val = I915_READ(reg);
1244 cur_state = !!(val & PIPECONF_ENABLE);
1245 }
1246
1247 I915_STATE_WARN(cur_state != state,
1248 "pipe %c assertion failure (expected %s, current %s)\n",
1249 pipe_name(pipe), state_string(state), state_string(cur_state));
1250 }
1251
1252 static void assert_plane(struct drm_i915_private *dev_priv,
1253 enum plane plane, bool state)
1254 {
1255 int reg;
1256 u32 val;
1257 bool cur_state;
1258
1259 reg = DSPCNTR(plane);
1260 val = I915_READ(reg);
1261 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1262 I915_STATE_WARN(cur_state != state,
1263 "plane %c assertion failure (expected %s, current %s)\n",
1264 plane_name(plane), state_string(state), state_string(cur_state));
1265 }
1266
1267 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1268 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1269
1270 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1271 enum pipe pipe)
1272 {
1273 struct drm_device *dev = dev_priv->dev;
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
1278 /* Primary planes are fixed to pipes on gen4+ */
1279 if (INTEL_INFO(dev)->gen >= 4) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
1285 return;
1286 }
1287
1288 /* Need to check both planes against the pipe */
1289 for_each_pipe(dev_priv, i) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
1297 }
1298 }
1299
1300 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1301 enum pipe pipe)
1302 {
1303 struct drm_device *dev = dev_priv->dev;
1304 int reg, sprite;
1305 u32 val;
1306
1307 if (INTEL_INFO(dev)->gen >= 9) {
1308 for_each_sprite(dev_priv, pipe, sprite) {
1309 val = I915_READ(PLANE_CTL(pipe, sprite));
1310 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1311 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1312 sprite, pipe_name(pipe));
1313 }
1314 } else if (IS_VALLEYVIEW(dev)) {
1315 for_each_sprite(dev_priv, pipe, sprite) {
1316 reg = SPCNTR(pipe, sprite);
1317 val = I915_READ(reg);
1318 I915_STATE_WARN(val & SP_ENABLE,
1319 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1320 sprite_name(pipe, sprite), pipe_name(pipe));
1321 }
1322 } else if (INTEL_INFO(dev)->gen >= 7) {
1323 reg = SPRCTL(pipe);
1324 val = I915_READ(reg);
1325 I915_STATE_WARN(val & SPRITE_ENABLE,
1326 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(pipe), pipe_name(pipe));
1328 } else if (INTEL_INFO(dev)->gen >= 5) {
1329 reg = DVSCNTR(pipe);
1330 val = I915_READ(reg);
1331 I915_STATE_WARN(val & DVS_ENABLE,
1332 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1333 plane_name(pipe), pipe_name(pipe));
1334 }
1335 }
1336
1337 static void assert_vblank_disabled(struct drm_crtc *crtc)
1338 {
1339 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1340 drm_crtc_vblank_put(crtc);
1341 }
1342
1343 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1344 {
1345 u32 val;
1346 bool enabled;
1347
1348 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1349
1350 val = I915_READ(PCH_DREF_CONTROL);
1351 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1352 DREF_SUPERSPREAD_SOURCE_MASK));
1353 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1354 }
1355
1356 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe)
1358 {
1359 int reg;
1360 u32 val;
1361 bool enabled;
1362
1363 reg = PCH_TRANSCONF(pipe);
1364 val = I915_READ(reg);
1365 enabled = !!(val & TRANS_ENABLE);
1366 I915_STATE_WARN(enabled,
1367 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1368 pipe_name(pipe));
1369 }
1370
1371 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, u32 port_sel, u32 val)
1373 {
1374 if ((val & DP_PORT_EN) == 0)
1375 return false;
1376
1377 if (HAS_PCH_CPT(dev_priv->dev)) {
1378 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1379 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1381 return false;
1382 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1384 return false;
1385 } else {
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & SDVO_ENABLE) == 0)
1396 return false;
1397
1398 if (HAS_PCH_CPT(dev_priv->dev)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1400 return false;
1401 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1403 return false;
1404 } else {
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1413 {
1414 if ((val & LVDS_PORT_EN) == 0)
1415 return false;
1416
1417 if (HAS_PCH_CPT(dev_priv->dev)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1419 return false;
1420 } else {
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1422 return false;
1423 }
1424 return true;
1425 }
1426
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1429 {
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1431 return false;
1432 if (HAS_PCH_CPT(dev_priv->dev)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1434 return false;
1435 } else {
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1437 return false;
1438 }
1439 return true;
1440 }
1441
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, int reg, u32 port_sel)
1444 {
1445 u32 val = I915_READ(reg);
1446 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1447 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1448 reg, pipe_name(pipe));
1449
1450 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1451 && (val & DP_PIPEB_SELECT),
1452 "IBX PCH dp port still using transcoder B\n");
1453 }
1454
1455 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe, int reg)
1457 {
1458 u32 val = I915_READ(reg);
1459 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1460 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1461 reg, pipe_name(pipe));
1462
1463 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1464 && (val & SDVO_PIPE_B_SELECT),
1465 "IBX PCH hdmi port still using transcoder B\n");
1466 }
1467
1468 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe)
1470 {
1471 int reg;
1472 u32 val;
1473
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1477
1478 reg = PCH_ADPA;
1479 val = I915_READ(reg);
1480 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1481 "PCH VGA enabled on transcoder %c, should be disabled\n",
1482 pipe_name(pipe));
1483
1484 reg = PCH_LVDS;
1485 val = I915_READ(reg);
1486 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1487 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488 pipe_name(pipe));
1489
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1492 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 }
1494
1495 static void intel_init_dpio(struct drm_device *dev)
1496 {
1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498
1499 if (!IS_VALLEYVIEW(dev))
1500 return;
1501
1502 /*
1503 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1504 * CHV x1 PHY (DP/HDMI D)
1505 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1506 */
1507 if (IS_CHERRYVIEW(dev)) {
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1509 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1510 } else {
1511 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1512 }
1513 }
1514
1515 static void vlv_enable_pll(struct intel_crtc *crtc,
1516 const struct intel_crtc_state *pipe_config)
1517 {
1518 struct drm_device *dev = crtc->base.dev;
1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 int reg = DPLL(crtc->pipe);
1521 u32 dpll = pipe_config->dpll_hw_state.dpll;
1522
1523 assert_pipe_disabled(dev_priv, crtc->pipe);
1524
1525 /* No really, not for ILK+ */
1526 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1527
1528 /* PLL is protected by panel, make sure we can write it */
1529 if (IS_MOBILE(dev_priv->dev))
1530 assert_panel_unlocked(dev_priv, crtc->pipe);
1531
1532 I915_WRITE(reg, dpll);
1533 POSTING_READ(reg);
1534 udelay(150);
1535
1536 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1537 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1538
1539 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1540 POSTING_READ(DPLL_MD(crtc->pipe));
1541
1542 /* We do this three times for luck */
1543 I915_WRITE(reg, dpll);
1544 POSTING_READ(reg);
1545 udelay(150); /* wait for warmup */
1546 I915_WRITE(reg, dpll);
1547 POSTING_READ(reg);
1548 udelay(150); /* wait for warmup */
1549 I915_WRITE(reg, dpll);
1550 POSTING_READ(reg);
1551 udelay(150); /* wait for warmup */
1552 }
1553
1554 static void chv_enable_pll(struct intel_crtc *crtc,
1555 const struct intel_crtc_state *pipe_config)
1556 {
1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int pipe = crtc->pipe;
1560 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1561 u32 tmp;
1562
1563 assert_pipe_disabled(dev_priv, crtc->pipe);
1564
1565 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1566
1567 mutex_lock(&dev_priv->dpio_lock);
1568
1569 /* Enable back the 10bit clock to display controller */
1570 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1571 tmp |= DPIO_DCLKP_EN;
1572 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1573
1574 /*
1575 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1576 */
1577 udelay(1);
1578
1579 /* Enable PLL */
1580 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1581
1582 /* Check PLL is locked */
1583 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1584 DRM_ERROR("PLL %d failed to lock\n", pipe);
1585
1586 /* not sure when this should be written */
1587 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1588 POSTING_READ(DPLL_MD(pipe));
1589
1590 mutex_unlock(&dev_priv->dpio_lock);
1591 }
1592
1593 static int intel_num_dvo_pipes(struct drm_device *dev)
1594 {
1595 struct intel_crtc *crtc;
1596 int count = 0;
1597
1598 for_each_intel_crtc(dev, crtc)
1599 count += crtc->active &&
1600 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1601
1602 return count;
1603 }
1604
1605 static void i9xx_enable_pll(struct intel_crtc *crtc)
1606 {
1607 struct drm_device *dev = crtc->base.dev;
1608 struct drm_i915_private *dev_priv = dev->dev_private;
1609 int reg = DPLL(crtc->pipe);
1610 u32 dpll = crtc->config->dpll_hw_state.dpll;
1611
1612 assert_pipe_disabled(dev_priv, crtc->pipe);
1613
1614 /* No really, not for ILK+ */
1615 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1616
1617 /* PLL is protected by panel, make sure we can write it */
1618 if (IS_MOBILE(dev) && !IS_I830(dev))
1619 assert_panel_unlocked(dev_priv, crtc->pipe);
1620
1621 /* Enable DVO 2x clock on both PLLs if necessary */
1622 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1623 /*
1624 * It appears to be important that we don't enable this
1625 * for the current pipe before otherwise configuring the
1626 * PLL. No idea how this should be handled if multiple
1627 * DVO outputs are enabled simultaneosly.
1628 */
1629 dpll |= DPLL_DVO_2X_MODE;
1630 I915_WRITE(DPLL(!crtc->pipe),
1631 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1632 }
1633
1634 /* Wait for the clocks to stabilize. */
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (INTEL_INFO(dev)->gen >= 4) {
1639 I915_WRITE(DPLL_MD(crtc->pipe),
1640 crtc->config->dpll_hw_state.dpll_md);
1641 } else {
1642 /* The pixel multiplier can only be updated once the
1643 * DPLL is enabled and the clocks are stable.
1644 *
1645 * So write it again.
1646 */
1647 I915_WRITE(reg, dpll);
1648 }
1649
1650 /* We do this three times for luck */
1651 I915_WRITE(reg, dpll);
1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654 I915_WRITE(reg, dpll);
1655 POSTING_READ(reg);
1656 udelay(150); /* wait for warmup */
1657 I915_WRITE(reg, dpll);
1658 POSTING_READ(reg);
1659 udelay(150); /* wait for warmup */
1660 }
1661
1662 /**
1663 * i9xx_disable_pll - disable a PLL
1664 * @dev_priv: i915 private structure
1665 * @pipe: pipe PLL to disable
1666 *
1667 * Disable the PLL for @pipe, making sure the pipe is off first.
1668 *
1669 * Note! This is for pre-ILK only.
1670 */
1671 static void i9xx_disable_pll(struct intel_crtc *crtc)
1672 {
1673 struct drm_device *dev = crtc->base.dev;
1674 struct drm_i915_private *dev_priv = dev->dev_private;
1675 enum pipe pipe = crtc->pipe;
1676
1677 /* Disable DVO 2x clock on both PLLs if necessary */
1678 if (IS_I830(dev) &&
1679 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1680 intel_num_dvo_pipes(dev) == 1) {
1681 I915_WRITE(DPLL(PIPE_B),
1682 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1683 I915_WRITE(DPLL(PIPE_A),
1684 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1685 }
1686
1687 /* Don't disable pipe or pipe PLLs if needed */
1688 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1689 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1690 return;
1691
1692 /* Make sure the pipe isn't still relying on us */
1693 assert_pipe_disabled(dev_priv, pipe);
1694
1695 I915_WRITE(DPLL(pipe), 0);
1696 POSTING_READ(DPLL(pipe));
1697 }
1698
1699 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1700 {
1701 u32 val = 0;
1702
1703 /* Make sure the pipe isn't still relying on us */
1704 assert_pipe_disabled(dev_priv, pipe);
1705
1706 /*
1707 * Leave integrated clock source and reference clock enabled for pipe B.
1708 * The latter is needed for VGA hotplug / manual detection.
1709 */
1710 if (pipe == PIPE_B)
1711 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1712 I915_WRITE(DPLL(pipe), val);
1713 POSTING_READ(DPLL(pipe));
1714
1715 }
1716
1717 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1718 {
1719 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1720 u32 val;
1721
1722 /* Make sure the pipe isn't still relying on us */
1723 assert_pipe_disabled(dev_priv, pipe);
1724
1725 /* Set PLL en = 0 */
1726 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1727 if (pipe != PIPE_A)
1728 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1729 I915_WRITE(DPLL(pipe), val);
1730 POSTING_READ(DPLL(pipe));
1731
1732 mutex_lock(&dev_priv->dpio_lock);
1733
1734 /* Disable 10bit clock to display controller */
1735 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1736 val &= ~DPIO_DCLKP_EN;
1737 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1738
1739 /* disable left/right clock distribution */
1740 if (pipe != PIPE_B) {
1741 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1742 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1743 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1744 } else {
1745 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1746 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1747 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1748 }
1749
1750 mutex_unlock(&dev_priv->dpio_lock);
1751 }
1752
1753 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1754 struct intel_digital_port *dport)
1755 {
1756 u32 port_mask;
1757 int dpll_reg;
1758
1759 switch (dport->port) {
1760 case PORT_B:
1761 port_mask = DPLL_PORTB_READY_MASK;
1762 dpll_reg = DPLL(0);
1763 break;
1764 case PORT_C:
1765 port_mask = DPLL_PORTC_READY_MASK;
1766 dpll_reg = DPLL(0);
1767 break;
1768 case PORT_D:
1769 port_mask = DPLL_PORTD_READY_MASK;
1770 dpll_reg = DPIO_PHY_STATUS;
1771 break;
1772 default:
1773 BUG();
1774 }
1775
1776 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1777 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1778 port_name(dport->port), I915_READ(dpll_reg));
1779 }
1780
1781 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1782 {
1783 struct drm_device *dev = crtc->base.dev;
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1786
1787 if (WARN_ON(pll == NULL))
1788 return;
1789
1790 WARN_ON(!pll->config.crtc_mask);
1791 if (pll->active == 0) {
1792 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1793 WARN_ON(pll->on);
1794 assert_shared_dpll_disabled(dev_priv, pll);
1795
1796 pll->mode_set(dev_priv, pll);
1797 }
1798 }
1799
1800 /**
1801 * intel_enable_shared_dpll - enable PCH PLL
1802 * @dev_priv: i915 private structure
1803 * @pipe: pipe PLL to enable
1804 *
1805 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1806 * drives the transcoder clock.
1807 */
1808 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1809 {
1810 struct drm_device *dev = crtc->base.dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1813
1814 if (WARN_ON(pll == NULL))
1815 return;
1816
1817 if (WARN_ON(pll->config.crtc_mask == 0))
1818 return;
1819
1820 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1821 pll->name, pll->active, pll->on,
1822 crtc->base.base.id);
1823
1824 if (pll->active++) {
1825 WARN_ON(!pll->on);
1826 assert_shared_dpll_enabled(dev_priv, pll);
1827 return;
1828 }
1829 WARN_ON(pll->on);
1830
1831 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1832
1833 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1834 pll->enable(dev_priv, pll);
1835 pll->on = true;
1836 }
1837
1838 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1839 {
1840 struct drm_device *dev = crtc->base.dev;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1843
1844 /* PCH only available on ILK+ */
1845 BUG_ON(INTEL_INFO(dev)->gen < 5);
1846 if (WARN_ON(pll == NULL))
1847 return;
1848
1849 if (WARN_ON(pll->config.crtc_mask == 0))
1850 return;
1851
1852 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1853 pll->name, pll->active, pll->on,
1854 crtc->base.base.id);
1855
1856 if (WARN_ON(pll->active == 0)) {
1857 assert_shared_dpll_disabled(dev_priv, pll);
1858 return;
1859 }
1860
1861 assert_shared_dpll_enabled(dev_priv, pll);
1862 WARN_ON(!pll->on);
1863 if (--pll->active)
1864 return;
1865
1866 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1867 pll->disable(dev_priv, pll);
1868 pll->on = false;
1869
1870 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1871 }
1872
1873 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1874 enum pipe pipe)
1875 {
1876 struct drm_device *dev = dev_priv->dev;
1877 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1879 uint32_t reg, val, pipeconf_val;
1880
1881 /* PCH only available on ILK+ */
1882 BUG_ON(!HAS_PCH_SPLIT(dev));
1883
1884 /* Make sure PCH DPLL is enabled */
1885 assert_shared_dpll_enabled(dev_priv,
1886 intel_crtc_to_shared_dpll(intel_crtc));
1887
1888 /* FDI must be feeding us bits for PCH ports */
1889 assert_fdi_tx_enabled(dev_priv, pipe);
1890 assert_fdi_rx_enabled(dev_priv, pipe);
1891
1892 if (HAS_PCH_CPT(dev)) {
1893 /* Workaround: Set the timing override bit before enabling the
1894 * pch transcoder. */
1895 reg = TRANS_CHICKEN2(pipe);
1896 val = I915_READ(reg);
1897 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1898 I915_WRITE(reg, val);
1899 }
1900
1901 reg = PCH_TRANSCONF(pipe);
1902 val = I915_READ(reg);
1903 pipeconf_val = I915_READ(PIPECONF(pipe));
1904
1905 if (HAS_PCH_IBX(dev_priv->dev)) {
1906 /*
1907 * make the BPC in transcoder be consistent with
1908 * that in pipeconf reg.
1909 */
1910 val &= ~PIPECONF_BPC_MASK;
1911 val |= pipeconf_val & PIPECONF_BPC_MASK;
1912 }
1913
1914 val &= ~TRANS_INTERLACE_MASK;
1915 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1916 if (HAS_PCH_IBX(dev_priv->dev) &&
1917 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1918 val |= TRANS_LEGACY_INTERLACED_ILK;
1919 else
1920 val |= TRANS_INTERLACED;
1921 else
1922 val |= TRANS_PROGRESSIVE;
1923
1924 I915_WRITE(reg, val | TRANS_ENABLE);
1925 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1926 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1927 }
1928
1929 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1930 enum transcoder cpu_transcoder)
1931 {
1932 u32 val, pipeconf_val;
1933
1934 /* PCH only available on ILK+ */
1935 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1936
1937 /* FDI must be feeding us bits for PCH ports */
1938 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1939 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1940
1941 /* Workaround: set timing override bit. */
1942 val = I915_READ(_TRANSA_CHICKEN2);
1943 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1944 I915_WRITE(_TRANSA_CHICKEN2, val);
1945
1946 val = TRANS_ENABLE;
1947 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1948
1949 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1950 PIPECONF_INTERLACED_ILK)
1951 val |= TRANS_INTERLACED;
1952 else
1953 val |= TRANS_PROGRESSIVE;
1954
1955 I915_WRITE(LPT_TRANSCONF, val);
1956 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1957 DRM_ERROR("Failed to enable PCH transcoder\n");
1958 }
1959
1960 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1961 enum pipe pipe)
1962 {
1963 struct drm_device *dev = dev_priv->dev;
1964 uint32_t reg, val;
1965
1966 /* FDI relies on the transcoder */
1967 assert_fdi_tx_disabled(dev_priv, pipe);
1968 assert_fdi_rx_disabled(dev_priv, pipe);
1969
1970 /* Ports must be off as well */
1971 assert_pch_ports_disabled(dev_priv, pipe);
1972
1973 reg = PCH_TRANSCONF(pipe);
1974 val = I915_READ(reg);
1975 val &= ~TRANS_ENABLE;
1976 I915_WRITE(reg, val);
1977 /* wait for PCH transcoder off, transcoder state */
1978 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1979 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1980
1981 if (!HAS_PCH_IBX(dev)) {
1982 /* Workaround: Clear the timing override chicken bit again. */
1983 reg = TRANS_CHICKEN2(pipe);
1984 val = I915_READ(reg);
1985 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1986 I915_WRITE(reg, val);
1987 }
1988 }
1989
1990 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1991 {
1992 u32 val;
1993
1994 val = I915_READ(LPT_TRANSCONF);
1995 val &= ~TRANS_ENABLE;
1996 I915_WRITE(LPT_TRANSCONF, val);
1997 /* wait for PCH transcoder off, transcoder state */
1998 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1999 DRM_ERROR("Failed to disable PCH transcoder\n");
2000
2001 /* Workaround: clear timing override bit. */
2002 val = I915_READ(_TRANSA_CHICKEN2);
2003 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2004 I915_WRITE(_TRANSA_CHICKEN2, val);
2005 }
2006
2007 /**
2008 * intel_enable_pipe - enable a pipe, asserting requirements
2009 * @crtc: crtc responsible for the pipe
2010 *
2011 * Enable @crtc's pipe, making sure that various hardware specific requirements
2012 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2013 */
2014 static void intel_enable_pipe(struct intel_crtc *crtc)
2015 {
2016 struct drm_device *dev = crtc->base.dev;
2017 struct drm_i915_private *dev_priv = dev->dev_private;
2018 enum pipe pipe = crtc->pipe;
2019 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2020 pipe);
2021 enum pipe pch_transcoder;
2022 int reg;
2023 u32 val;
2024
2025 assert_planes_disabled(dev_priv, pipe);
2026 assert_cursor_disabled(dev_priv, pipe);
2027 assert_sprites_disabled(dev_priv, pipe);
2028
2029 if (HAS_PCH_LPT(dev_priv->dev))
2030 pch_transcoder = TRANSCODER_A;
2031 else
2032 pch_transcoder = pipe;
2033
2034 /*
2035 * A pipe without a PLL won't actually be able to drive bits from
2036 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2037 * need the check.
2038 */
2039 if (!HAS_PCH_SPLIT(dev_priv->dev))
2040 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2041 assert_dsi_pll_enabled(dev_priv);
2042 else
2043 assert_pll_enabled(dev_priv, pipe);
2044 else {
2045 if (crtc->config->has_pch_encoder) {
2046 /* if driving the PCH, we need FDI enabled */
2047 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2048 assert_fdi_tx_pll_enabled(dev_priv,
2049 (enum pipe) cpu_transcoder);
2050 }
2051 /* FIXME: assert CPU port conditions for SNB+ */
2052 }
2053
2054 reg = PIPECONF(cpu_transcoder);
2055 val = I915_READ(reg);
2056 if (val & PIPECONF_ENABLE) {
2057 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2058 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2059 return;
2060 }
2061
2062 I915_WRITE(reg, val | PIPECONF_ENABLE);
2063 POSTING_READ(reg);
2064 }
2065
2066 /**
2067 * intel_disable_pipe - disable a pipe, asserting requirements
2068 * @crtc: crtc whose pipes is to be disabled
2069 *
2070 * Disable the pipe of @crtc, making sure that various hardware
2071 * specific requirements are met, if applicable, e.g. plane
2072 * disabled, panel fitter off, etc.
2073 *
2074 * Will wait until the pipe has shut down before returning.
2075 */
2076 static void intel_disable_pipe(struct intel_crtc *crtc)
2077 {
2078 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2079 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2080 enum pipe pipe = crtc->pipe;
2081 int reg;
2082 u32 val;
2083
2084 /*
2085 * Make sure planes won't keep trying to pump pixels to us,
2086 * or we might hang the display.
2087 */
2088 assert_planes_disabled(dev_priv, pipe);
2089 assert_cursor_disabled(dev_priv, pipe);
2090 assert_sprites_disabled(dev_priv, pipe);
2091
2092 reg = PIPECONF(cpu_transcoder);
2093 val = I915_READ(reg);
2094 if ((val & PIPECONF_ENABLE) == 0)
2095 return;
2096
2097 /*
2098 * Double wide has implications for planes
2099 * so best keep it disabled when not needed.
2100 */
2101 if (crtc->config->double_wide)
2102 val &= ~PIPECONF_DOUBLE_WIDE;
2103
2104 /* Don't disable pipe or pipe PLLs if needed */
2105 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2106 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2107 val &= ~PIPECONF_ENABLE;
2108
2109 I915_WRITE(reg, val);
2110 if ((val & PIPECONF_ENABLE) == 0)
2111 intel_wait_for_pipe_off(crtc);
2112 }
2113
2114 /*
2115 * Plane regs are double buffered, going from enabled->disabled needs a
2116 * trigger in order to latch. The display address reg provides this.
2117 */
2118 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2119 enum plane plane)
2120 {
2121 struct drm_device *dev = dev_priv->dev;
2122 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2123
2124 I915_WRITE(reg, I915_READ(reg));
2125 POSTING_READ(reg);
2126 }
2127
2128 /**
2129 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2130 * @plane: plane to be enabled
2131 * @crtc: crtc for the plane
2132 *
2133 * Enable @plane on @crtc, making sure that the pipe is running first.
2134 */
2135 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2136 struct drm_crtc *crtc)
2137 {
2138 struct drm_device *dev = plane->dev;
2139 struct drm_i915_private *dev_priv = dev->dev_private;
2140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2141
2142 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2143 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2144
2145 if (intel_crtc->primary_enabled)
2146 return;
2147
2148 intel_crtc->primary_enabled = true;
2149
2150 dev_priv->display.update_primary_plane(crtc, plane->fb,
2151 crtc->x, crtc->y);
2152
2153 /*
2154 * BDW signals flip done immediately if the plane
2155 * is disabled, even if the plane enable is already
2156 * armed to occur at the next vblank :(
2157 */
2158 if (IS_BROADWELL(dev))
2159 intel_wait_for_vblank(dev, intel_crtc->pipe);
2160 }
2161
2162 /**
2163 * intel_disable_primary_hw_plane - disable the primary hardware plane
2164 * @plane: plane to be disabled
2165 * @crtc: crtc for the plane
2166 *
2167 * Disable @plane on @crtc, making sure that the pipe is running first.
2168 */
2169 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2170 struct drm_crtc *crtc)
2171 {
2172 struct drm_device *dev = plane->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2175
2176 if (WARN_ON(!intel_crtc->active))
2177 return;
2178
2179 if (!intel_crtc->primary_enabled)
2180 return;
2181
2182 intel_crtc->primary_enabled = false;
2183
2184 dev_priv->display.update_primary_plane(crtc, plane->fb,
2185 crtc->x, crtc->y);
2186 }
2187
2188 static bool need_vtd_wa(struct drm_device *dev)
2189 {
2190 #ifdef CONFIG_INTEL_IOMMU
2191 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2192 return true;
2193 #endif
2194 return false;
2195 }
2196
2197 int
2198 intel_fb_align_height(struct drm_device *dev, int height,
2199 uint32_t pixel_format,
2200 uint64_t fb_format_modifier)
2201 {
2202 int tile_height;
2203 uint32_t bits_per_pixel;
2204
2205 switch (fb_format_modifier) {
2206 case DRM_FORMAT_MOD_NONE:
2207 tile_height = 1;
2208 break;
2209 case I915_FORMAT_MOD_X_TILED:
2210 tile_height = IS_GEN2(dev) ? 16 : 8;
2211 break;
2212 case I915_FORMAT_MOD_Y_TILED:
2213 tile_height = 32;
2214 break;
2215 case I915_FORMAT_MOD_Yf_TILED:
2216 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2217 switch (bits_per_pixel) {
2218 default:
2219 case 8:
2220 tile_height = 64;
2221 break;
2222 case 16:
2223 case 32:
2224 tile_height = 32;
2225 break;
2226 case 64:
2227 tile_height = 16;
2228 break;
2229 case 128:
2230 WARN_ONCE(1,
2231 "128-bit pixels are not supported for display!");
2232 tile_height = 16;
2233 break;
2234 }
2235 break;
2236 default:
2237 MISSING_CASE(fb_format_modifier);
2238 tile_height = 1;
2239 break;
2240 }
2241
2242 return ALIGN(height, tile_height);
2243 }
2244
2245 int
2246 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2247 struct drm_framebuffer *fb,
2248 struct intel_engine_cs *pipelined)
2249 {
2250 struct drm_device *dev = fb->dev;
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2253 u32 alignment;
2254 int ret;
2255
2256 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2257
2258 switch (fb->modifier[0]) {
2259 case DRM_FORMAT_MOD_NONE:
2260 if (INTEL_INFO(dev)->gen >= 9)
2261 alignment = 256 * 1024;
2262 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2263 alignment = 128 * 1024;
2264 else if (INTEL_INFO(dev)->gen >= 4)
2265 alignment = 4 * 1024;
2266 else
2267 alignment = 64 * 1024;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 if (INTEL_INFO(dev)->gen >= 9)
2271 alignment = 256 * 1024;
2272 else {
2273 /* pin() will align the object as required by fence */
2274 alignment = 0;
2275 }
2276 break;
2277 case I915_FORMAT_MOD_Y_TILED:
2278 case I915_FORMAT_MOD_Yf_TILED:
2279 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2280 "Y tiling bo slipped through, driver bug!\n"))
2281 return -EINVAL;
2282 alignment = 1 * 1024 * 1024;
2283 break;
2284 default:
2285 MISSING_CASE(fb->modifier[0]);
2286 return -EINVAL;
2287 }
2288
2289 /* Note that the w/a also requires 64 PTE of padding following the
2290 * bo. We currently fill all unused PTE with the shadow page and so
2291 * we should always have valid PTE following the scanout preventing
2292 * the VT-d warning.
2293 */
2294 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2295 alignment = 256 * 1024;
2296
2297 /*
2298 * Global gtt pte registers are special registers which actually forward
2299 * writes to a chunk of system memory. Which means that there is no risk
2300 * that the register values disappear as soon as we call
2301 * intel_runtime_pm_put(), so it is correct to wrap only the
2302 * pin/unpin/fence and not more.
2303 */
2304 intel_runtime_pm_get(dev_priv);
2305
2306 dev_priv->mm.interruptible = false;
2307 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2308 if (ret)
2309 goto err_interruptible;
2310
2311 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2312 * fence, whereas 965+ only requires a fence if using
2313 * framebuffer compression. For simplicity, we always install
2314 * a fence as the cost is not that onerous.
2315 */
2316 ret = i915_gem_object_get_fence(obj);
2317 if (ret)
2318 goto err_unpin;
2319
2320 i915_gem_object_pin_fence(obj);
2321
2322 dev_priv->mm.interruptible = true;
2323 intel_runtime_pm_put(dev_priv);
2324 return 0;
2325
2326 err_unpin:
2327 i915_gem_object_unpin_from_display_plane(obj);
2328 err_interruptible:
2329 dev_priv->mm.interruptible = true;
2330 intel_runtime_pm_put(dev_priv);
2331 return ret;
2332 }
2333
2334 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2335 {
2336 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2337
2338 i915_gem_object_unpin_fence(obj);
2339 i915_gem_object_unpin_from_display_plane(obj);
2340 }
2341
2342 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2343 * is assumed to be a power-of-two. */
2344 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2345 unsigned int tiling_mode,
2346 unsigned int cpp,
2347 unsigned int pitch)
2348 {
2349 if (tiling_mode != I915_TILING_NONE) {
2350 unsigned int tile_rows, tiles;
2351
2352 tile_rows = *y / 8;
2353 *y %= 8;
2354
2355 tiles = *x / (512/cpp);
2356 *x %= 512/cpp;
2357
2358 return tile_rows * pitch * 8 + tiles * 4096;
2359 } else {
2360 unsigned int offset;
2361
2362 offset = *y * pitch + *x * cpp;
2363 *y = 0;
2364 *x = (offset & 4095) / cpp;
2365 return offset & -4096;
2366 }
2367 }
2368
2369 static int i9xx_format_to_fourcc(int format)
2370 {
2371 switch (format) {
2372 case DISPPLANE_8BPP:
2373 return DRM_FORMAT_C8;
2374 case DISPPLANE_BGRX555:
2375 return DRM_FORMAT_XRGB1555;
2376 case DISPPLANE_BGRX565:
2377 return DRM_FORMAT_RGB565;
2378 default:
2379 case DISPPLANE_BGRX888:
2380 return DRM_FORMAT_XRGB8888;
2381 case DISPPLANE_RGBX888:
2382 return DRM_FORMAT_XBGR8888;
2383 case DISPPLANE_BGRX101010:
2384 return DRM_FORMAT_XRGB2101010;
2385 case DISPPLANE_RGBX101010:
2386 return DRM_FORMAT_XBGR2101010;
2387 }
2388 }
2389
2390 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2391 {
2392 switch (format) {
2393 case PLANE_CTL_FORMAT_RGB_565:
2394 return DRM_FORMAT_RGB565;
2395 default:
2396 case PLANE_CTL_FORMAT_XRGB_8888:
2397 if (rgb_order) {
2398 if (alpha)
2399 return DRM_FORMAT_ABGR8888;
2400 else
2401 return DRM_FORMAT_XBGR8888;
2402 } else {
2403 if (alpha)
2404 return DRM_FORMAT_ARGB8888;
2405 else
2406 return DRM_FORMAT_XRGB8888;
2407 }
2408 case PLANE_CTL_FORMAT_XRGB_2101010:
2409 if (rgb_order)
2410 return DRM_FORMAT_XBGR2101010;
2411 else
2412 return DRM_FORMAT_XRGB2101010;
2413 }
2414 }
2415
2416 static bool
2417 intel_alloc_plane_obj(struct intel_crtc *crtc,
2418 struct intel_initial_plane_config *plane_config)
2419 {
2420 struct drm_device *dev = crtc->base.dev;
2421 struct drm_i915_gem_object *obj = NULL;
2422 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2423 struct drm_framebuffer *fb = &plane_config->fb->base;
2424 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2425 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2426 PAGE_SIZE);
2427
2428 size_aligned -= base_aligned;
2429
2430 if (plane_config->size == 0)
2431 return false;
2432
2433 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2434 base_aligned,
2435 base_aligned,
2436 size_aligned);
2437 if (!obj)
2438 return false;
2439
2440 obj->tiling_mode = plane_config->tiling;
2441 if (obj->tiling_mode == I915_TILING_X)
2442 obj->stride = fb->pitches[0];
2443
2444 mode_cmd.pixel_format = fb->pixel_format;
2445 mode_cmd.width = fb->width;
2446 mode_cmd.height = fb->height;
2447 mode_cmd.pitches[0] = fb->pitches[0];
2448 mode_cmd.modifier[0] = fb->modifier[0];
2449 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2450
2451 mutex_lock(&dev->struct_mutex);
2452
2453 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2454 &mode_cmd, obj)) {
2455 DRM_DEBUG_KMS("intel fb init failed\n");
2456 goto out_unref_obj;
2457 }
2458
2459 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2460 mutex_unlock(&dev->struct_mutex);
2461
2462 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2463 return true;
2464
2465 out_unref_obj:
2466 drm_gem_object_unreference(&obj->base);
2467 mutex_unlock(&dev->struct_mutex);
2468 return false;
2469 }
2470
2471 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2472 static void
2473 update_state_fb(struct drm_plane *plane)
2474 {
2475 if (plane->fb == plane->state->fb)
2476 return;
2477
2478 if (plane->state->fb)
2479 drm_framebuffer_unreference(plane->state->fb);
2480 plane->state->fb = plane->fb;
2481 if (plane->state->fb)
2482 drm_framebuffer_reference(plane->state->fb);
2483 }
2484
2485 static void
2486 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2487 struct intel_initial_plane_config *plane_config)
2488 {
2489 struct drm_device *dev = intel_crtc->base.dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct drm_crtc *c;
2492 struct intel_crtc *i;
2493 struct drm_i915_gem_object *obj;
2494
2495 if (!plane_config->fb)
2496 return;
2497
2498 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2499 struct drm_plane *primary = intel_crtc->base.primary;
2500
2501 primary->fb = &plane_config->fb->base;
2502 primary->state->crtc = &intel_crtc->base;
2503 update_state_fb(primary);
2504
2505 return;
2506 }
2507
2508 kfree(plane_config->fb);
2509
2510 /*
2511 * Failed to alloc the obj, check to see if we should share
2512 * an fb with another CRTC instead
2513 */
2514 for_each_crtc(dev, c) {
2515 i = to_intel_crtc(c);
2516
2517 if (c == &intel_crtc->base)
2518 continue;
2519
2520 if (!i->active)
2521 continue;
2522
2523 obj = intel_fb_obj(c->primary->fb);
2524 if (obj == NULL)
2525 continue;
2526
2527 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2528 struct drm_plane *primary = intel_crtc->base.primary;
2529
2530 if (obj->tiling_mode != I915_TILING_NONE)
2531 dev_priv->preserve_bios_swizzle = true;
2532
2533 drm_framebuffer_reference(c->primary->fb);
2534 primary->fb = c->primary->fb;
2535 primary->state->crtc = &intel_crtc->base;
2536 update_state_fb(intel_crtc->base.primary);
2537 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2538 break;
2539 }
2540 }
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544 struct drm_framebuffer *fb,
2545 int x, int y)
2546 {
2547 struct drm_device *dev = crtc->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550 struct drm_i915_gem_object *obj;
2551 int plane = intel_crtc->plane;
2552 unsigned long linear_offset;
2553 u32 dspcntr;
2554 u32 reg = DSPCNTR(plane);
2555 int pixel_size;
2556
2557 if (!intel_crtc->primary_enabled) {
2558 I915_WRITE(reg, 0);
2559 if (INTEL_INFO(dev)->gen >= 4)
2560 I915_WRITE(DSPSURF(plane), 0);
2561 else
2562 I915_WRITE(DSPADDR(plane), 0);
2563 POSTING_READ(reg);
2564 return;
2565 }
2566
2567 obj = intel_fb_obj(fb);
2568 if (WARN_ON(obj == NULL))
2569 return;
2570
2571 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573 dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575 dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577 if (INTEL_INFO(dev)->gen < 4) {
2578 if (intel_crtc->pipe == PIPE_B)
2579 dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581 /* pipesrc and dspsize control the size that is scaled from,
2582 * which should always be the user's requested size.
2583 */
2584 I915_WRITE(DSPSIZE(plane),
2585 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586 (intel_crtc->config->pipe_src_w - 1));
2587 I915_WRITE(DSPPOS(plane), 0);
2588 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589 I915_WRITE(PRIMSIZE(plane),
2590 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591 (intel_crtc->config->pipe_src_w - 1));
2592 I915_WRITE(PRIMPOS(plane), 0);
2593 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594 }
2595
2596 switch (fb->pixel_format) {
2597 case DRM_FORMAT_C8:
2598 dspcntr |= DISPPLANE_8BPP;
2599 break;
2600 case DRM_FORMAT_XRGB1555:
2601 case DRM_FORMAT_ARGB1555:
2602 dspcntr |= DISPPLANE_BGRX555;
2603 break;
2604 case DRM_FORMAT_RGB565:
2605 dspcntr |= DISPPLANE_BGRX565;
2606 break;
2607 case DRM_FORMAT_XRGB8888:
2608 case DRM_FORMAT_ARGB8888:
2609 dspcntr |= DISPPLANE_BGRX888;
2610 break;
2611 case DRM_FORMAT_XBGR8888:
2612 case DRM_FORMAT_ABGR8888:
2613 dspcntr |= DISPPLANE_RGBX888;
2614 break;
2615 case DRM_FORMAT_XRGB2101010:
2616 case DRM_FORMAT_ARGB2101010:
2617 dspcntr |= DISPPLANE_BGRX101010;
2618 break;
2619 case DRM_FORMAT_XBGR2101010:
2620 case DRM_FORMAT_ABGR2101010:
2621 dspcntr |= DISPPLANE_RGBX101010;
2622 break;
2623 default:
2624 BUG();
2625 }
2626
2627 if (INTEL_INFO(dev)->gen >= 4 &&
2628 obj->tiling_mode != I915_TILING_NONE)
2629 dspcntr |= DISPPLANE_TILED;
2630
2631 if (IS_G4X(dev))
2632 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634 linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636 if (INTEL_INFO(dev)->gen >= 4) {
2637 intel_crtc->dspaddr_offset =
2638 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639 pixel_size,
2640 fb->pitches[0]);
2641 linear_offset -= intel_crtc->dspaddr_offset;
2642 } else {
2643 intel_crtc->dspaddr_offset = linear_offset;
2644 }
2645
2646 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 x += (intel_crtc->config->pipe_src_w - 1);
2650 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652 /* Finding the last pixel of the last line of the display
2653 data and adding to linear_offset*/
2654 linear_offset +=
2655 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657 }
2658
2659 I915_WRITE(reg, dspcntr);
2660
2661 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2662 if (INTEL_INFO(dev)->gen >= 4) {
2663 I915_WRITE(DSPSURF(plane),
2664 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2665 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2666 I915_WRITE(DSPLINOFF(plane), linear_offset);
2667 } else
2668 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2669 POSTING_READ(reg);
2670 }
2671
2672 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2673 struct drm_framebuffer *fb,
2674 int x, int y)
2675 {
2676 struct drm_device *dev = crtc->dev;
2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2679 struct drm_i915_gem_object *obj;
2680 int plane = intel_crtc->plane;
2681 unsigned long linear_offset;
2682 u32 dspcntr;
2683 u32 reg = DSPCNTR(plane);
2684 int pixel_size;
2685
2686 if (!intel_crtc->primary_enabled) {
2687 I915_WRITE(reg, 0);
2688 I915_WRITE(DSPSURF(plane), 0);
2689 POSTING_READ(reg);
2690 return;
2691 }
2692
2693 obj = intel_fb_obj(fb);
2694 if (WARN_ON(obj == NULL))
2695 return;
2696
2697 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2698
2699 dspcntr = DISPPLANE_GAMMA_ENABLE;
2700
2701 dspcntr |= DISPLAY_PLANE_ENABLE;
2702
2703 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2704 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2705
2706 switch (fb->pixel_format) {
2707 case DRM_FORMAT_C8:
2708 dspcntr |= DISPPLANE_8BPP;
2709 break;
2710 case DRM_FORMAT_RGB565:
2711 dspcntr |= DISPPLANE_BGRX565;
2712 break;
2713 case DRM_FORMAT_XRGB8888:
2714 case DRM_FORMAT_ARGB8888:
2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
2718 case DRM_FORMAT_ABGR8888:
2719 dspcntr |= DISPPLANE_RGBX888;
2720 break;
2721 case DRM_FORMAT_XRGB2101010:
2722 case DRM_FORMAT_ARGB2101010:
2723 dspcntr |= DISPPLANE_BGRX101010;
2724 break;
2725 case DRM_FORMAT_XBGR2101010:
2726 case DRM_FORMAT_ABGR2101010:
2727 dspcntr |= DISPPLANE_RGBX101010;
2728 break;
2729 default:
2730 BUG();
2731 }
2732
2733 if (obj->tiling_mode != I915_TILING_NONE)
2734 dspcntr |= DISPPLANE_TILED;
2735
2736 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2737 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738
2739 linear_offset = y * fb->pitches[0] + x * pixel_size;
2740 intel_crtc->dspaddr_offset =
2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2742 pixel_size,
2743 fb->pitches[0]);
2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2746 dspcntr |= DISPPLANE_ROTATE_180;
2747
2748 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2749 x += (intel_crtc->config->pipe_src_w - 1);
2750 y += (intel_crtc->config->pipe_src_h - 1);
2751
2752 /* Finding the last pixel of the last line of the display
2753 data and adding to linear_offset*/
2754 linear_offset +=
2755 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2756 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2757 }
2758 }
2759
2760 I915_WRITE(reg, dspcntr);
2761
2762 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2763 I915_WRITE(DSPSURF(plane),
2764 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2765 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2767 } else {
2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
2770 }
2771 POSTING_READ(reg);
2772 }
2773
2774 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2775 uint32_t pixel_format)
2776 {
2777 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2778
2779 /*
2780 * The stride is either expressed as a multiple of 64 bytes
2781 * chunks for linear buffers or in number of tiles for tiled
2782 * buffers.
2783 */
2784 switch (fb_modifier) {
2785 case DRM_FORMAT_MOD_NONE:
2786 return 64;
2787 case I915_FORMAT_MOD_X_TILED:
2788 if (INTEL_INFO(dev)->gen == 2)
2789 return 128;
2790 return 512;
2791 case I915_FORMAT_MOD_Y_TILED:
2792 /* No need to check for old gens and Y tiling since this is
2793 * about the display engine and those will be blocked before
2794 * we get here.
2795 */
2796 return 128;
2797 case I915_FORMAT_MOD_Yf_TILED:
2798 if (bits_per_pixel == 8)
2799 return 64;
2800 else
2801 return 128;
2802 default:
2803 MISSING_CASE(fb_modifier);
2804 return 64;
2805 }
2806 }
2807
2808 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2809 struct drm_framebuffer *fb,
2810 int x, int y)
2811 {
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 struct drm_i915_gem_object *obj;
2816 int pipe = intel_crtc->pipe;
2817 u32 plane_ctl, stride_div;
2818
2819 if (!intel_crtc->primary_enabled) {
2820 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2821 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2822 POSTING_READ(PLANE_CTL(pipe, 0));
2823 return;
2824 }
2825
2826 plane_ctl = PLANE_CTL_ENABLE |
2827 PLANE_CTL_PIPE_GAMMA_ENABLE |
2828 PLANE_CTL_PIPE_CSC_ENABLE;
2829
2830 switch (fb->pixel_format) {
2831 case DRM_FORMAT_RGB565:
2832 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2833 break;
2834 case DRM_FORMAT_XRGB8888:
2835 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2836 break;
2837 case DRM_FORMAT_ARGB8888:
2838 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2839 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2840 break;
2841 case DRM_FORMAT_XBGR8888:
2842 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2843 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2844 break;
2845 case DRM_FORMAT_ABGR8888:
2846 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2847 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2848 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2849 break;
2850 case DRM_FORMAT_XRGB2101010:
2851 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2852 break;
2853 case DRM_FORMAT_XBGR2101010:
2854 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2855 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2856 break;
2857 default:
2858 BUG();
2859 }
2860
2861 switch (fb->modifier[0]) {
2862 case DRM_FORMAT_MOD_NONE:
2863 break;
2864 case I915_FORMAT_MOD_X_TILED:
2865 plane_ctl |= PLANE_CTL_TILED_X;
2866 break;
2867 case I915_FORMAT_MOD_Y_TILED:
2868 plane_ctl |= PLANE_CTL_TILED_Y;
2869 break;
2870 case I915_FORMAT_MOD_Yf_TILED:
2871 plane_ctl |= PLANE_CTL_TILED_YF;
2872 break;
2873 default:
2874 MISSING_CASE(fb->modifier[0]);
2875 }
2876
2877 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2878 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2879 plane_ctl |= PLANE_CTL_ROTATE_180;
2880
2881 obj = intel_fb_obj(fb);
2882 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2883 fb->pixel_format);
2884
2885 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2886
2887 I915_WRITE(PLANE_POS(pipe, 0), 0);
2888 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2889 I915_WRITE(PLANE_SIZE(pipe, 0),
2890 (intel_crtc->config->pipe_src_h - 1) << 16 |
2891 (intel_crtc->config->pipe_src_w - 1));
2892 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2893 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2894
2895 POSTING_READ(PLANE_SURF(pipe, 0));
2896 }
2897
2898 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2899 static int
2900 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2901 int x, int y, enum mode_set_atomic state)
2902 {
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905
2906 if (dev_priv->display.disable_fbc)
2907 dev_priv->display.disable_fbc(dev);
2908
2909 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2910
2911 return 0;
2912 }
2913
2914 static void intel_complete_page_flips(struct drm_device *dev)
2915 {
2916 struct drm_crtc *crtc;
2917
2918 for_each_crtc(dev, crtc) {
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2920 enum plane plane = intel_crtc->plane;
2921
2922 intel_prepare_page_flip(dev, plane);
2923 intel_finish_page_flip_plane(dev, plane);
2924 }
2925 }
2926
2927 static void intel_update_primary_planes(struct drm_device *dev)
2928 {
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930 struct drm_crtc *crtc;
2931
2932 for_each_crtc(dev, crtc) {
2933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2934
2935 drm_modeset_lock(&crtc->mutex, NULL);
2936 /*
2937 * FIXME: Once we have proper support for primary planes (and
2938 * disabling them without disabling the entire crtc) allow again
2939 * a NULL crtc->primary->fb.
2940 */
2941 if (intel_crtc->active && crtc->primary->fb)
2942 dev_priv->display.update_primary_plane(crtc,
2943 crtc->primary->fb,
2944 crtc->x,
2945 crtc->y);
2946 drm_modeset_unlock(&crtc->mutex);
2947 }
2948 }
2949
2950 void intel_prepare_reset(struct drm_device *dev)
2951 {
2952 struct drm_i915_private *dev_priv = to_i915(dev);
2953 struct intel_crtc *crtc;
2954
2955 /* no reset support for gen2 */
2956 if (IS_GEN2(dev))
2957 return;
2958
2959 /* reset doesn't touch the display */
2960 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2961 return;
2962
2963 drm_modeset_lock_all(dev);
2964
2965 /*
2966 * Disabling the crtcs gracefully seems nicer. Also the
2967 * g33 docs say we should at least disable all the planes.
2968 */
2969 for_each_intel_crtc(dev, crtc) {
2970 if (crtc->active)
2971 dev_priv->display.crtc_disable(&crtc->base);
2972 }
2973 }
2974
2975 void intel_finish_reset(struct drm_device *dev)
2976 {
2977 struct drm_i915_private *dev_priv = to_i915(dev);
2978
2979 /*
2980 * Flips in the rings will be nuked by the reset,
2981 * so complete all pending flips so that user space
2982 * will get its events and not get stuck.
2983 */
2984 intel_complete_page_flips(dev);
2985
2986 /* no reset support for gen2 */
2987 if (IS_GEN2(dev))
2988 return;
2989
2990 /* reset doesn't touch the display */
2991 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
2992 /*
2993 * Flips in the rings have been nuked by the reset,
2994 * so update the base address of all primary
2995 * planes to the the last fb to make sure we're
2996 * showing the correct fb after a reset.
2997 */
2998 intel_update_primary_planes(dev);
2999 return;
3000 }
3001
3002 /*
3003 * The display has been reset as well,
3004 * so need a full re-initialization.
3005 */
3006 intel_runtime_pm_disable_interrupts(dev_priv);
3007 intel_runtime_pm_enable_interrupts(dev_priv);
3008
3009 intel_modeset_init_hw(dev);
3010
3011 spin_lock_irq(&dev_priv->irq_lock);
3012 if (dev_priv->display.hpd_irq_setup)
3013 dev_priv->display.hpd_irq_setup(dev);
3014 spin_unlock_irq(&dev_priv->irq_lock);
3015
3016 intel_modeset_setup_hw_state(dev, true);
3017
3018 intel_hpd_init(dev_priv);
3019
3020 drm_modeset_unlock_all(dev);
3021 }
3022
3023 static int
3024 intel_finish_fb(struct drm_framebuffer *old_fb)
3025 {
3026 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3027 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3028 bool was_interruptible = dev_priv->mm.interruptible;
3029 int ret;
3030
3031 /* Big Hammer, we also need to ensure that any pending
3032 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3033 * current scanout is retired before unpinning the old
3034 * framebuffer.
3035 *
3036 * This should only fail upon a hung GPU, in which case we
3037 * can safely continue.
3038 */
3039 dev_priv->mm.interruptible = false;
3040 ret = i915_gem_object_finish_gpu(obj);
3041 dev_priv->mm.interruptible = was_interruptible;
3042
3043 return ret;
3044 }
3045
3046 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3047 {
3048 struct drm_device *dev = crtc->dev;
3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3051 bool pending;
3052
3053 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3054 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3055 return false;
3056
3057 spin_lock_irq(&dev->event_lock);
3058 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3059 spin_unlock_irq(&dev->event_lock);
3060
3061 return pending;
3062 }
3063
3064 static void intel_update_pipe_size(struct intel_crtc *crtc)
3065 {
3066 struct drm_device *dev = crtc->base.dev;
3067 struct drm_i915_private *dev_priv = dev->dev_private;
3068 const struct drm_display_mode *adjusted_mode;
3069
3070 if (!i915.fastboot)
3071 return;
3072
3073 /*
3074 * Update pipe size and adjust fitter if needed: the reason for this is
3075 * that in compute_mode_changes we check the native mode (not the pfit
3076 * mode) to see if we can flip rather than do a full mode set. In the
3077 * fastboot case, we'll flip, but if we don't update the pipesrc and
3078 * pfit state, we'll end up with a big fb scanned out into the wrong
3079 * sized surface.
3080 *
3081 * To fix this properly, we need to hoist the checks up into
3082 * compute_mode_changes (or above), check the actual pfit state and
3083 * whether the platform allows pfit disable with pipe active, and only
3084 * then update the pipesrc and pfit state, even on the flip path.
3085 */
3086
3087 adjusted_mode = &crtc->config->base.adjusted_mode;
3088
3089 I915_WRITE(PIPESRC(crtc->pipe),
3090 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3091 (adjusted_mode->crtc_vdisplay - 1));
3092 if (!crtc->config->pch_pfit.enabled &&
3093 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3094 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3095 I915_WRITE(PF_CTL(crtc->pipe), 0);
3096 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3097 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3098 }
3099 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3100 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3101 }
3102
3103 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3104 {
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 int pipe = intel_crtc->pipe;
3109 u32 reg, temp;
3110
3111 /* enable normal train */
3112 reg = FDI_TX_CTL(pipe);
3113 temp = I915_READ(reg);
3114 if (IS_IVYBRIDGE(dev)) {
3115 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3117 } else {
3118 temp &= ~FDI_LINK_TRAIN_NONE;
3119 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3120 }
3121 I915_WRITE(reg, temp);
3122
3123 reg = FDI_RX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 if (HAS_PCH_CPT(dev)) {
3126 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3127 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3128 } else {
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_NONE;
3131 }
3132 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3133
3134 /* wait one idle pattern time */
3135 POSTING_READ(reg);
3136 udelay(1000);
3137
3138 /* IVB wants error correction enabled */
3139 if (IS_IVYBRIDGE(dev))
3140 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3141 FDI_FE_ERRC_ENABLE);
3142 }
3143
3144 /* The FDI link training functions for ILK/Ibexpeak. */
3145 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3146 {
3147 struct drm_device *dev = crtc->dev;
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3150 int pipe = intel_crtc->pipe;
3151 u32 reg, temp, tries;
3152
3153 /* FDI needs bits from pipe first */
3154 assert_pipe_enabled(dev_priv, pipe);
3155
3156 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3157 for train result */
3158 reg = FDI_RX_IMR(pipe);
3159 temp = I915_READ(reg);
3160 temp &= ~FDI_RX_SYMBOL_LOCK;
3161 temp &= ~FDI_RX_BIT_LOCK;
3162 I915_WRITE(reg, temp);
3163 I915_READ(reg);
3164 udelay(150);
3165
3166 /* enable CPU FDI TX and PCH FDI RX */
3167 reg = FDI_TX_CTL(pipe);
3168 temp = I915_READ(reg);
3169 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3170 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3171 temp &= ~FDI_LINK_TRAIN_NONE;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1;
3173 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3174
3175 reg = FDI_RX_CTL(pipe);
3176 temp = I915_READ(reg);
3177 temp &= ~FDI_LINK_TRAIN_NONE;
3178 temp |= FDI_LINK_TRAIN_PATTERN_1;
3179 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3180
3181 POSTING_READ(reg);
3182 udelay(150);
3183
3184 /* Ironlake workaround, enable clock pointer after FDI enable*/
3185 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3186 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3187 FDI_RX_PHASE_SYNC_POINTER_EN);
3188
3189 reg = FDI_RX_IIR(pipe);
3190 for (tries = 0; tries < 5; tries++) {
3191 temp = I915_READ(reg);
3192 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3193
3194 if ((temp & FDI_RX_BIT_LOCK)) {
3195 DRM_DEBUG_KMS("FDI train 1 done.\n");
3196 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3197 break;
3198 }
3199 }
3200 if (tries == 5)
3201 DRM_ERROR("FDI train 1 fail!\n");
3202
3203 /* Train 2 */
3204 reg = FDI_TX_CTL(pipe);
3205 temp = I915_READ(reg);
3206 temp &= ~FDI_LINK_TRAIN_NONE;
3207 temp |= FDI_LINK_TRAIN_PATTERN_2;
3208 I915_WRITE(reg, temp);
3209
3210 reg = FDI_RX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 I915_WRITE(reg, temp);
3215
3216 POSTING_READ(reg);
3217 udelay(150);
3218
3219 reg = FDI_RX_IIR(pipe);
3220 for (tries = 0; tries < 5; tries++) {
3221 temp = I915_READ(reg);
3222 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3223
3224 if (temp & FDI_RX_SYMBOL_LOCK) {
3225 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3226 DRM_DEBUG_KMS("FDI train 2 done.\n");
3227 break;
3228 }
3229 }
3230 if (tries == 5)
3231 DRM_ERROR("FDI train 2 fail!\n");
3232
3233 DRM_DEBUG_KMS("FDI train done\n");
3234
3235 }
3236
3237 static const int snb_b_fdi_train_param[] = {
3238 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3239 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3240 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3241 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3242 };
3243
3244 /* The FDI link training functions for SNB/Cougarpoint. */
3245 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3246 {
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3250 int pipe = intel_crtc->pipe;
3251 u32 reg, temp, i, retry;
3252
3253 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3254 for train result */
3255 reg = FDI_RX_IMR(pipe);
3256 temp = I915_READ(reg);
3257 temp &= ~FDI_RX_SYMBOL_LOCK;
3258 temp &= ~FDI_RX_BIT_LOCK;
3259 I915_WRITE(reg, temp);
3260
3261 POSTING_READ(reg);
3262 udelay(150);
3263
3264 /* enable CPU FDI TX and PCH FDI RX */
3265 reg = FDI_TX_CTL(pipe);
3266 temp = I915_READ(reg);
3267 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3268 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3269 temp &= ~FDI_LINK_TRAIN_NONE;
3270 temp |= FDI_LINK_TRAIN_PATTERN_1;
3271 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3272 /* SNB-B */
3273 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3274 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3275
3276 I915_WRITE(FDI_RX_MISC(pipe),
3277 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3278
3279 reg = FDI_RX_CTL(pipe);
3280 temp = I915_READ(reg);
3281 if (HAS_PCH_CPT(dev)) {
3282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3284 } else {
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_PATTERN_1;
3287 }
3288 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3289
3290 POSTING_READ(reg);
3291 udelay(150);
3292
3293 for (i = 0; i < 4; i++) {
3294 reg = FDI_TX_CTL(pipe);
3295 temp = I915_READ(reg);
3296 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3297 temp |= snb_b_fdi_train_param[i];
3298 I915_WRITE(reg, temp);
3299
3300 POSTING_READ(reg);
3301 udelay(500);
3302
3303 for (retry = 0; retry < 5; retry++) {
3304 reg = FDI_RX_IIR(pipe);
3305 temp = I915_READ(reg);
3306 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3307 if (temp & FDI_RX_BIT_LOCK) {
3308 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3309 DRM_DEBUG_KMS("FDI train 1 done.\n");
3310 break;
3311 }
3312 udelay(50);
3313 }
3314 if (retry < 5)
3315 break;
3316 }
3317 if (i == 4)
3318 DRM_ERROR("FDI train 1 fail!\n");
3319
3320 /* Train 2 */
3321 reg = FDI_TX_CTL(pipe);
3322 temp = I915_READ(reg);
3323 temp &= ~FDI_LINK_TRAIN_NONE;
3324 temp |= FDI_LINK_TRAIN_PATTERN_2;
3325 if (IS_GEN6(dev)) {
3326 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3327 /* SNB-B */
3328 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3329 }
3330 I915_WRITE(reg, temp);
3331
3332 reg = FDI_RX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 if (HAS_PCH_CPT(dev)) {
3335 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3336 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3337 } else {
3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_2;
3340 }
3341 I915_WRITE(reg, temp);
3342
3343 POSTING_READ(reg);
3344 udelay(150);
3345
3346 for (i = 0; i < 4; i++) {
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3350 temp |= snb_b_fdi_train_param[i];
3351 I915_WRITE(reg, temp);
3352
3353 POSTING_READ(reg);
3354 udelay(500);
3355
3356 for (retry = 0; retry < 5; retry++) {
3357 reg = FDI_RX_IIR(pipe);
3358 temp = I915_READ(reg);
3359 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3360 if (temp & FDI_RX_SYMBOL_LOCK) {
3361 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3362 DRM_DEBUG_KMS("FDI train 2 done.\n");
3363 break;
3364 }
3365 udelay(50);
3366 }
3367 if (retry < 5)
3368 break;
3369 }
3370 if (i == 4)
3371 DRM_ERROR("FDI train 2 fail!\n");
3372
3373 DRM_DEBUG_KMS("FDI train done.\n");
3374 }
3375
3376 /* Manual link training for Ivy Bridge A0 parts */
3377 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3378 {
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp, i, j;
3384
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
3391 I915_WRITE(reg, temp);
3392
3393 POSTING_READ(reg);
3394 udelay(150);
3395
3396 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3397 I915_READ(FDI_RX_IIR(pipe)));
3398
3399 /* Try each vswing and preemphasis setting twice before moving on */
3400 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3401 /* disable first in case we need to retry */
3402 reg = FDI_TX_CTL(pipe);
3403 temp = I915_READ(reg);
3404 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3405 temp &= ~FDI_TX_ENABLE;
3406 I915_WRITE(reg, temp);
3407
3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
3410 temp &= ~FDI_LINK_TRAIN_AUTO;
3411 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3412 temp &= ~FDI_RX_ENABLE;
3413 I915_WRITE(reg, temp);
3414
3415 /* enable CPU FDI TX and PCH FDI RX */
3416 reg = FDI_TX_CTL(pipe);
3417 temp = I915_READ(reg);
3418 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3419 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3420 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3421 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3422 temp |= snb_b_fdi_train_param[j/2];
3423 temp |= FDI_COMPOSITE_SYNC;
3424 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3425
3426 I915_WRITE(FDI_RX_MISC(pipe),
3427 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3428
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3432 temp |= FDI_COMPOSITE_SYNC;
3433 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3434
3435 POSTING_READ(reg);
3436 udelay(1); /* should be 0.5us */
3437
3438 for (i = 0; i < 4; i++) {
3439 reg = FDI_RX_IIR(pipe);
3440 temp = I915_READ(reg);
3441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3442
3443 if (temp & FDI_RX_BIT_LOCK ||
3444 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3445 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3446 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3447 i);
3448 break;
3449 }
3450 udelay(1); /* should be 0.5us */
3451 }
3452 if (i == 4) {
3453 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3454 continue;
3455 }
3456
3457 /* Train 2 */
3458 reg = FDI_TX_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3461 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3462 I915_WRITE(reg, temp);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3467 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3468 I915_WRITE(reg, temp);
3469
3470 POSTING_READ(reg);
3471 udelay(2); /* should be 1.5us */
3472
3473 for (i = 0; i < 4; i++) {
3474 reg = FDI_RX_IIR(pipe);
3475 temp = I915_READ(reg);
3476 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3477
3478 if (temp & FDI_RX_SYMBOL_LOCK ||
3479 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3481 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3482 i);
3483 goto train_done;
3484 }
3485 udelay(2); /* should be 1.5us */
3486 }
3487 if (i == 4)
3488 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3489 }
3490
3491 train_done:
3492 DRM_DEBUG_KMS("FDI train done.\n");
3493 }
3494
3495 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3496 {
3497 struct drm_device *dev = intel_crtc->base.dev;
3498 struct drm_i915_private *dev_priv = dev->dev_private;
3499 int pipe = intel_crtc->pipe;
3500 u32 reg, temp;
3501
3502
3503 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3504 reg = FDI_RX_CTL(pipe);
3505 temp = I915_READ(reg);
3506 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3507 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3508 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3509 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3510
3511 POSTING_READ(reg);
3512 udelay(200);
3513
3514 /* Switch from Rawclk to PCDclk */
3515 temp = I915_READ(reg);
3516 I915_WRITE(reg, temp | FDI_PCDCLK);
3517
3518 POSTING_READ(reg);
3519 udelay(200);
3520
3521 /* Enable CPU FDI TX PLL, always on for Ironlake */
3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3525 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3526
3527 POSTING_READ(reg);
3528 udelay(100);
3529 }
3530 }
3531
3532 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3533 {
3534 struct drm_device *dev = intel_crtc->base.dev;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 int pipe = intel_crtc->pipe;
3537 u32 reg, temp;
3538
3539 /* Switch from PCDclk to Rawclk */
3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3543
3544 /* Disable CPU FDI TX PLL */
3545 reg = FDI_TX_CTL(pipe);
3546 temp = I915_READ(reg);
3547 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3548
3549 POSTING_READ(reg);
3550 udelay(100);
3551
3552 reg = FDI_RX_CTL(pipe);
3553 temp = I915_READ(reg);
3554 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3555
3556 /* Wait for the clocks to turn off. */
3557 POSTING_READ(reg);
3558 udelay(100);
3559 }
3560
3561 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3562 {
3563 struct drm_device *dev = crtc->dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566 int pipe = intel_crtc->pipe;
3567 u32 reg, temp;
3568
3569 /* disable CPU FDI tx and PCH FDI rx */
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3573 POSTING_READ(reg);
3574
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(0x7 << 16);
3578 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3579 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3580
3581 POSTING_READ(reg);
3582 udelay(100);
3583
3584 /* Ironlake workaround, disable clock pointer after downing FDI */
3585 if (HAS_PCH_IBX(dev))
3586 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3587
3588 /* still set train pattern 1 */
3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
3591 temp &= ~FDI_LINK_TRAIN_NONE;
3592 temp |= FDI_LINK_TRAIN_PATTERN_1;
3593 I915_WRITE(reg, temp);
3594
3595 reg = FDI_RX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 if (HAS_PCH_CPT(dev)) {
3598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3600 } else {
3601 temp &= ~FDI_LINK_TRAIN_NONE;
3602 temp |= FDI_LINK_TRAIN_PATTERN_1;
3603 }
3604 /* BPC in FDI rx is consistent with that in PIPECONF */
3605 temp &= ~(0x07 << 16);
3606 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3607 I915_WRITE(reg, temp);
3608
3609 POSTING_READ(reg);
3610 udelay(100);
3611 }
3612
3613 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3614 {
3615 struct intel_crtc *crtc;
3616
3617 /* Note that we don't need to be called with mode_config.lock here
3618 * as our list of CRTC objects is static for the lifetime of the
3619 * device and so cannot disappear as we iterate. Similarly, we can
3620 * happily treat the predicates as racy, atomic checks as userspace
3621 * cannot claim and pin a new fb without at least acquring the
3622 * struct_mutex and so serialising with us.
3623 */
3624 for_each_intel_crtc(dev, crtc) {
3625 if (atomic_read(&crtc->unpin_work_count) == 0)
3626 continue;
3627
3628 if (crtc->unpin_work)
3629 intel_wait_for_vblank(dev, crtc->pipe);
3630
3631 return true;
3632 }
3633
3634 return false;
3635 }
3636
3637 static void page_flip_completed(struct intel_crtc *intel_crtc)
3638 {
3639 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3640 struct intel_unpin_work *work = intel_crtc->unpin_work;
3641
3642 /* ensure that the unpin work is consistent wrt ->pending. */
3643 smp_rmb();
3644 intel_crtc->unpin_work = NULL;
3645
3646 if (work->event)
3647 drm_send_vblank_event(intel_crtc->base.dev,
3648 intel_crtc->pipe,
3649 work->event);
3650
3651 drm_crtc_vblank_put(&intel_crtc->base);
3652
3653 wake_up_all(&dev_priv->pending_flip_queue);
3654 queue_work(dev_priv->wq, &work->work);
3655
3656 trace_i915_flip_complete(intel_crtc->plane,
3657 work->pending_flip_obj);
3658 }
3659
3660 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3661 {
3662 struct drm_device *dev = crtc->dev;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664
3665 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3666 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3667 !intel_crtc_has_pending_flip(crtc),
3668 60*HZ) == 0)) {
3669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670
3671 spin_lock_irq(&dev->event_lock);
3672 if (intel_crtc->unpin_work) {
3673 WARN_ONCE(1, "Removing stuck page flip\n");
3674 page_flip_completed(intel_crtc);
3675 }
3676 spin_unlock_irq(&dev->event_lock);
3677 }
3678
3679 if (crtc->primary->fb) {
3680 mutex_lock(&dev->struct_mutex);
3681 intel_finish_fb(crtc->primary->fb);
3682 mutex_unlock(&dev->struct_mutex);
3683 }
3684 }
3685
3686 /* Program iCLKIP clock to the desired frequency */
3687 static void lpt_program_iclkip(struct drm_crtc *crtc)
3688 {
3689 struct drm_device *dev = crtc->dev;
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3692 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3693 u32 temp;
3694
3695 mutex_lock(&dev_priv->dpio_lock);
3696
3697 /* It is necessary to ungate the pixclk gate prior to programming
3698 * the divisors, and gate it back when it is done.
3699 */
3700 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3701
3702 /* Disable SSCCTL */
3703 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3704 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3705 SBI_SSCCTL_DISABLE,
3706 SBI_ICLK);
3707
3708 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3709 if (clock == 20000) {
3710 auxdiv = 1;
3711 divsel = 0x41;
3712 phaseinc = 0x20;
3713 } else {
3714 /* The iCLK virtual clock root frequency is in MHz,
3715 * but the adjusted_mode->crtc_clock in in KHz. To get the
3716 * divisors, it is necessary to divide one by another, so we
3717 * convert the virtual clock precision to KHz here for higher
3718 * precision.
3719 */
3720 u32 iclk_virtual_root_freq = 172800 * 1000;
3721 u32 iclk_pi_range = 64;
3722 u32 desired_divisor, msb_divisor_value, pi_value;
3723
3724 desired_divisor = (iclk_virtual_root_freq / clock);
3725 msb_divisor_value = desired_divisor / iclk_pi_range;
3726 pi_value = desired_divisor % iclk_pi_range;
3727
3728 auxdiv = 0;
3729 divsel = msb_divisor_value - 2;
3730 phaseinc = pi_value;
3731 }
3732
3733 /* This should not happen with any sane values */
3734 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3735 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3736 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3737 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3738
3739 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3740 clock,
3741 auxdiv,
3742 divsel,
3743 phasedir,
3744 phaseinc);
3745
3746 /* Program SSCDIVINTPHASE6 */
3747 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3748 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3749 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3750 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3751 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3752 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3753 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3754 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3755
3756 /* Program SSCAUXDIV */
3757 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3758 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3759 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3760 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3761
3762 /* Enable modulator and associated divider */
3763 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3764 temp &= ~SBI_SSCCTL_DISABLE;
3765 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3766
3767 /* Wait for initialization time */
3768 udelay(24);
3769
3770 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3771
3772 mutex_unlock(&dev_priv->dpio_lock);
3773 }
3774
3775 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3776 enum pipe pch_transcoder)
3777 {
3778 struct drm_device *dev = crtc->base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3781
3782 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3783 I915_READ(HTOTAL(cpu_transcoder)));
3784 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3785 I915_READ(HBLANK(cpu_transcoder)));
3786 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3787 I915_READ(HSYNC(cpu_transcoder)));
3788
3789 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3790 I915_READ(VTOTAL(cpu_transcoder)));
3791 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3792 I915_READ(VBLANK(cpu_transcoder)));
3793 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3794 I915_READ(VSYNC(cpu_transcoder)));
3795 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3796 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3797 }
3798
3799 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3800 {
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 uint32_t temp;
3803
3804 temp = I915_READ(SOUTH_CHICKEN1);
3805 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3806 return;
3807
3808 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3809 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3810
3811 temp &= ~FDI_BC_BIFURCATION_SELECT;
3812 if (enable)
3813 temp |= FDI_BC_BIFURCATION_SELECT;
3814
3815 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3816 I915_WRITE(SOUTH_CHICKEN1, temp);
3817 POSTING_READ(SOUTH_CHICKEN1);
3818 }
3819
3820 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3821 {
3822 struct drm_device *dev = intel_crtc->base.dev;
3823
3824 switch (intel_crtc->pipe) {
3825 case PIPE_A:
3826 break;
3827 case PIPE_B:
3828 if (intel_crtc->config->fdi_lanes > 2)
3829 cpt_set_fdi_bc_bifurcation(dev, false);
3830 else
3831 cpt_set_fdi_bc_bifurcation(dev, true);
3832
3833 break;
3834 case PIPE_C:
3835 cpt_set_fdi_bc_bifurcation(dev, true);
3836
3837 break;
3838 default:
3839 BUG();
3840 }
3841 }
3842
3843 /*
3844 * Enable PCH resources required for PCH ports:
3845 * - PCH PLLs
3846 * - FDI training & RX/TX
3847 * - update transcoder timings
3848 * - DP transcoding bits
3849 * - transcoder
3850 */
3851 static void ironlake_pch_enable(struct drm_crtc *crtc)
3852 {
3853 struct drm_device *dev = crtc->dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856 int pipe = intel_crtc->pipe;
3857 u32 reg, temp;
3858
3859 assert_pch_transcoder_disabled(dev_priv, pipe);
3860
3861 if (IS_IVYBRIDGE(dev))
3862 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3863
3864 /* Write the TU size bits before fdi link training, so that error
3865 * detection works. */
3866 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3867 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3868
3869 /* For PCH output, training FDI link */
3870 dev_priv->display.fdi_link_train(crtc);
3871
3872 /* We need to program the right clock selection before writing the pixel
3873 * mutliplier into the DPLL. */
3874 if (HAS_PCH_CPT(dev)) {
3875 u32 sel;
3876
3877 temp = I915_READ(PCH_DPLL_SEL);
3878 temp |= TRANS_DPLL_ENABLE(pipe);
3879 sel = TRANS_DPLLB_SEL(pipe);
3880 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3881 temp |= sel;
3882 else
3883 temp &= ~sel;
3884 I915_WRITE(PCH_DPLL_SEL, temp);
3885 }
3886
3887 /* XXX: pch pll's can be enabled any time before we enable the PCH
3888 * transcoder, and we actually should do this to not upset any PCH
3889 * transcoder that already use the clock when we share it.
3890 *
3891 * Note that enable_shared_dpll tries to do the right thing, but
3892 * get_shared_dpll unconditionally resets the pll - we need that to have
3893 * the right LVDS enable sequence. */
3894 intel_enable_shared_dpll(intel_crtc);
3895
3896 /* set transcoder timing, panel must allow it */
3897 assert_panel_unlocked(dev_priv, pipe);
3898 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3899
3900 intel_fdi_normal_train(crtc);
3901
3902 /* For PCH DP, enable TRANS_DP_CTL */
3903 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3904 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3905 reg = TRANS_DP_CTL(pipe);
3906 temp = I915_READ(reg);
3907 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3908 TRANS_DP_SYNC_MASK |
3909 TRANS_DP_BPC_MASK);
3910 temp |= (TRANS_DP_OUTPUT_ENABLE |
3911 TRANS_DP_ENH_FRAMING);
3912 temp |= bpc << 9; /* same format but at 11:9 */
3913
3914 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3915 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3916 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3917 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3918
3919 switch (intel_trans_dp_port_sel(crtc)) {
3920 case PCH_DP_B:
3921 temp |= TRANS_DP_PORT_SEL_B;
3922 break;
3923 case PCH_DP_C:
3924 temp |= TRANS_DP_PORT_SEL_C;
3925 break;
3926 case PCH_DP_D:
3927 temp |= TRANS_DP_PORT_SEL_D;
3928 break;
3929 default:
3930 BUG();
3931 }
3932
3933 I915_WRITE(reg, temp);
3934 }
3935
3936 ironlake_enable_pch_transcoder(dev_priv, pipe);
3937 }
3938
3939 static void lpt_pch_enable(struct drm_crtc *crtc)
3940 {
3941 struct drm_device *dev = crtc->dev;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3945
3946 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3947
3948 lpt_program_iclkip(crtc);
3949
3950 /* Set transcoder timing. */
3951 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3952
3953 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3954 }
3955
3956 void intel_put_shared_dpll(struct intel_crtc *crtc)
3957 {
3958 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3959
3960 if (pll == NULL)
3961 return;
3962
3963 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3964 WARN(1, "bad %s crtc mask\n", pll->name);
3965 return;
3966 }
3967
3968 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3969 if (pll->config.crtc_mask == 0) {
3970 WARN_ON(pll->on);
3971 WARN_ON(pll->active);
3972 }
3973
3974 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3975 }
3976
3977 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3978 struct intel_crtc_state *crtc_state)
3979 {
3980 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3981 struct intel_shared_dpll *pll;
3982 enum intel_dpll_id i;
3983
3984 if (HAS_PCH_IBX(dev_priv->dev)) {
3985 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3986 i = (enum intel_dpll_id) crtc->pipe;
3987 pll = &dev_priv->shared_dplls[i];
3988
3989 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3990 crtc->base.base.id, pll->name);
3991
3992 WARN_ON(pll->new_config->crtc_mask);
3993
3994 goto found;
3995 }
3996
3997 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3998 pll = &dev_priv->shared_dplls[i];
3999
4000 /* Only want to check enabled timings first */
4001 if (pll->new_config->crtc_mask == 0)
4002 continue;
4003
4004 if (memcmp(&crtc_state->dpll_hw_state,
4005 &pll->new_config->hw_state,
4006 sizeof(pll->new_config->hw_state)) == 0) {
4007 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4008 crtc->base.base.id, pll->name,
4009 pll->new_config->crtc_mask,
4010 pll->active);
4011 goto found;
4012 }
4013 }
4014
4015 /* Ok no matching timings, maybe there's a free one? */
4016 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4017 pll = &dev_priv->shared_dplls[i];
4018 if (pll->new_config->crtc_mask == 0) {
4019 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4020 crtc->base.base.id, pll->name);
4021 goto found;
4022 }
4023 }
4024
4025 return NULL;
4026
4027 found:
4028 if (pll->new_config->crtc_mask == 0)
4029 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4030
4031 crtc_state->shared_dpll = i;
4032 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4033 pipe_name(crtc->pipe));
4034
4035 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4036
4037 return pll;
4038 }
4039
4040 /**
4041 * intel_shared_dpll_start_config - start a new PLL staged config
4042 * @dev_priv: DRM device
4043 * @clear_pipes: mask of pipes that will have their PLLs freed
4044 *
4045 * Starts a new PLL staged config, copying the current config but
4046 * releasing the references of pipes specified in clear_pipes.
4047 */
4048 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4049 unsigned clear_pipes)
4050 {
4051 struct intel_shared_dpll *pll;
4052 enum intel_dpll_id i;
4053
4054 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4055 pll = &dev_priv->shared_dplls[i];
4056
4057 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4058 GFP_KERNEL);
4059 if (!pll->new_config)
4060 goto cleanup;
4061
4062 pll->new_config->crtc_mask &= ~clear_pipes;
4063 }
4064
4065 return 0;
4066
4067 cleanup:
4068 while (--i >= 0) {
4069 pll = &dev_priv->shared_dplls[i];
4070 kfree(pll->new_config);
4071 pll->new_config = NULL;
4072 }
4073
4074 return -ENOMEM;
4075 }
4076
4077 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4078 {
4079 struct intel_shared_dpll *pll;
4080 enum intel_dpll_id i;
4081
4082 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4083 pll = &dev_priv->shared_dplls[i];
4084
4085 WARN_ON(pll->new_config == &pll->config);
4086
4087 pll->config = *pll->new_config;
4088 kfree(pll->new_config);
4089 pll->new_config = NULL;
4090 }
4091 }
4092
4093 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4094 {
4095 struct intel_shared_dpll *pll;
4096 enum intel_dpll_id i;
4097
4098 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4099 pll = &dev_priv->shared_dplls[i];
4100
4101 WARN_ON(pll->new_config == &pll->config);
4102
4103 kfree(pll->new_config);
4104 pll->new_config = NULL;
4105 }
4106 }
4107
4108 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4109 {
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111 int dslreg = PIPEDSL(pipe);
4112 u32 temp;
4113
4114 temp = I915_READ(dslreg);
4115 udelay(500);
4116 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4117 if (wait_for(I915_READ(dslreg) != temp, 5))
4118 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4119 }
4120 }
4121
4122 static void skylake_pfit_enable(struct intel_crtc *crtc)
4123 {
4124 struct drm_device *dev = crtc->base.dev;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 int pipe = crtc->pipe;
4127
4128 if (crtc->config->pch_pfit.enabled) {
4129 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4130 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4131 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4132 }
4133 }
4134
4135 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4136 {
4137 struct drm_device *dev = crtc->base.dev;
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139 int pipe = crtc->pipe;
4140
4141 if (crtc->config->pch_pfit.enabled) {
4142 /* Force use of hard-coded filter coefficients
4143 * as some pre-programmed values are broken,
4144 * e.g. x201.
4145 */
4146 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4147 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4148 PF_PIPE_SEL_IVB(pipe));
4149 else
4150 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4151 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4152 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4153 }
4154 }
4155
4156 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4157 {
4158 struct drm_device *dev = crtc->dev;
4159 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4160 struct drm_plane *plane;
4161 struct intel_plane *intel_plane;
4162
4163 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4164 intel_plane = to_intel_plane(plane);
4165 if (intel_plane->pipe == pipe)
4166 intel_plane_restore(&intel_plane->base);
4167 }
4168 }
4169
4170 /*
4171 * Disable a plane internally without actually modifying the plane's state.
4172 * This will allow us to easily restore the plane later by just reprogramming
4173 * its state.
4174 */
4175 static void disable_plane_internal(struct drm_plane *plane)
4176 {
4177 struct intel_plane *intel_plane = to_intel_plane(plane);
4178 struct drm_plane_state *state =
4179 plane->funcs->atomic_duplicate_state(plane);
4180 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4181
4182 intel_state->visible = false;
4183 intel_plane->commit_plane(plane, intel_state);
4184
4185 intel_plane_destroy_state(plane, state);
4186 }
4187
4188 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4189 {
4190 struct drm_device *dev = crtc->dev;
4191 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4192 struct drm_plane *plane;
4193 struct intel_plane *intel_plane;
4194
4195 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4196 intel_plane = to_intel_plane(plane);
4197 if (plane->fb && intel_plane->pipe == pipe)
4198 disable_plane_internal(plane);
4199 }
4200 }
4201
4202 void hsw_enable_ips(struct intel_crtc *crtc)
4203 {
4204 struct drm_device *dev = crtc->base.dev;
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206
4207 if (!crtc->config->ips_enabled)
4208 return;
4209
4210 /* We can only enable IPS after we enable a plane and wait for a vblank */
4211 intel_wait_for_vblank(dev, crtc->pipe);
4212
4213 assert_plane_enabled(dev_priv, crtc->plane);
4214 if (IS_BROADWELL(dev)) {
4215 mutex_lock(&dev_priv->rps.hw_lock);
4216 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4217 mutex_unlock(&dev_priv->rps.hw_lock);
4218 /* Quoting Art Runyan: "its not safe to expect any particular
4219 * value in IPS_CTL bit 31 after enabling IPS through the
4220 * mailbox." Moreover, the mailbox may return a bogus state,
4221 * so we need to just enable it and continue on.
4222 */
4223 } else {
4224 I915_WRITE(IPS_CTL, IPS_ENABLE);
4225 /* The bit only becomes 1 in the next vblank, so this wait here
4226 * is essentially intel_wait_for_vblank. If we don't have this
4227 * and don't wait for vblanks until the end of crtc_enable, then
4228 * the HW state readout code will complain that the expected
4229 * IPS_CTL value is not the one we read. */
4230 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4231 DRM_ERROR("Timed out waiting for IPS enable\n");
4232 }
4233 }
4234
4235 void hsw_disable_ips(struct intel_crtc *crtc)
4236 {
4237 struct drm_device *dev = crtc->base.dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239
4240 if (!crtc->config->ips_enabled)
4241 return;
4242
4243 assert_plane_enabled(dev_priv, crtc->plane);
4244 if (IS_BROADWELL(dev)) {
4245 mutex_lock(&dev_priv->rps.hw_lock);
4246 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4247 mutex_unlock(&dev_priv->rps.hw_lock);
4248 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4249 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4250 DRM_ERROR("Timed out waiting for IPS disable\n");
4251 } else {
4252 I915_WRITE(IPS_CTL, 0);
4253 POSTING_READ(IPS_CTL);
4254 }
4255
4256 /* We need to wait for a vblank before we can disable the plane. */
4257 intel_wait_for_vblank(dev, crtc->pipe);
4258 }
4259
4260 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4261 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4262 {
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266 enum pipe pipe = intel_crtc->pipe;
4267 int palreg = PALETTE(pipe);
4268 int i;
4269 bool reenable_ips = false;
4270
4271 /* The clocks have to be on to load the palette. */
4272 if (!crtc->state->enable || !intel_crtc->active)
4273 return;
4274
4275 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4276 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4277 assert_dsi_pll_enabled(dev_priv);
4278 else
4279 assert_pll_enabled(dev_priv, pipe);
4280 }
4281
4282 /* use legacy palette for Ironlake */
4283 if (!HAS_GMCH_DISPLAY(dev))
4284 palreg = LGC_PALETTE(pipe);
4285
4286 /* Workaround : Do not read or write the pipe palette/gamma data while
4287 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4288 */
4289 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4290 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4291 GAMMA_MODE_MODE_SPLIT)) {
4292 hsw_disable_ips(intel_crtc);
4293 reenable_ips = true;
4294 }
4295
4296 for (i = 0; i < 256; i++) {
4297 I915_WRITE(palreg + 4 * i,
4298 (intel_crtc->lut_r[i] << 16) |
4299 (intel_crtc->lut_g[i] << 8) |
4300 intel_crtc->lut_b[i]);
4301 }
4302
4303 if (reenable_ips)
4304 hsw_enable_ips(intel_crtc);
4305 }
4306
4307 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4308 {
4309 if (!enable && intel_crtc->overlay) {
4310 struct drm_device *dev = intel_crtc->base.dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312
4313 mutex_lock(&dev->struct_mutex);
4314 dev_priv->mm.interruptible = false;
4315 (void) intel_overlay_switch_off(intel_crtc->overlay);
4316 dev_priv->mm.interruptible = true;
4317 mutex_unlock(&dev->struct_mutex);
4318 }
4319
4320 /* Let userspace switch the overlay on again. In most cases userspace
4321 * has to recompute where to put it anyway.
4322 */
4323 }
4324
4325 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4326 {
4327 struct drm_device *dev = crtc->dev;
4328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4329 int pipe = intel_crtc->pipe;
4330
4331 intel_enable_primary_hw_plane(crtc->primary, crtc);
4332 intel_enable_sprite_planes(crtc);
4333 intel_crtc_update_cursor(crtc, true);
4334 intel_crtc_dpms_overlay(intel_crtc, true);
4335
4336 hsw_enable_ips(intel_crtc);
4337
4338 mutex_lock(&dev->struct_mutex);
4339 intel_fbc_update(dev);
4340 mutex_unlock(&dev->struct_mutex);
4341
4342 /*
4343 * FIXME: Once we grow proper nuclear flip support out of this we need
4344 * to compute the mask of flip planes precisely. For the time being
4345 * consider this a flip from a NULL plane.
4346 */
4347 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4348 }
4349
4350 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4351 {
4352 struct drm_device *dev = crtc->dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4355 int pipe = intel_crtc->pipe;
4356
4357 intel_crtc_wait_for_pending_flips(crtc);
4358
4359 if (dev_priv->fbc.crtc == intel_crtc)
4360 intel_fbc_disable(dev);
4361
4362 hsw_disable_ips(intel_crtc);
4363
4364 intel_crtc_dpms_overlay(intel_crtc, false);
4365 intel_crtc_update_cursor(crtc, false);
4366 intel_disable_sprite_planes(crtc);
4367 intel_disable_primary_hw_plane(crtc->primary, crtc);
4368
4369 /*
4370 * FIXME: Once we grow proper nuclear flip support out of this we need
4371 * to compute the mask of flip planes precisely. For the time being
4372 * consider this a flip to a NULL plane.
4373 */
4374 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4375 }
4376
4377 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4378 {
4379 struct drm_device *dev = crtc->dev;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4382 struct intel_encoder *encoder;
4383 int pipe = intel_crtc->pipe;
4384
4385 WARN_ON(!crtc->state->enable);
4386
4387 if (intel_crtc->active)
4388 return;
4389
4390 if (intel_crtc->config->has_pch_encoder)
4391 intel_prepare_shared_dpll(intel_crtc);
4392
4393 if (intel_crtc->config->has_dp_encoder)
4394 intel_dp_set_m_n(intel_crtc, M1_N1);
4395
4396 intel_set_pipe_timings(intel_crtc);
4397
4398 if (intel_crtc->config->has_pch_encoder) {
4399 intel_cpu_transcoder_set_m_n(intel_crtc,
4400 &intel_crtc->config->fdi_m_n, NULL);
4401 }
4402
4403 ironlake_set_pipeconf(crtc);
4404
4405 intel_crtc->active = true;
4406
4407 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4408 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4409
4410 for_each_encoder_on_crtc(dev, crtc, encoder)
4411 if (encoder->pre_enable)
4412 encoder->pre_enable(encoder);
4413
4414 if (intel_crtc->config->has_pch_encoder) {
4415 /* Note: FDI PLL enabling _must_ be done before we enable the
4416 * cpu pipes, hence this is separate from all the other fdi/pch
4417 * enabling. */
4418 ironlake_fdi_pll_enable(intel_crtc);
4419 } else {
4420 assert_fdi_tx_disabled(dev_priv, pipe);
4421 assert_fdi_rx_disabled(dev_priv, pipe);
4422 }
4423
4424 ironlake_pfit_enable(intel_crtc);
4425
4426 /*
4427 * On ILK+ LUT must be loaded before the pipe is running but with
4428 * clocks enabled
4429 */
4430 intel_crtc_load_lut(crtc);
4431
4432 intel_update_watermarks(crtc);
4433 intel_enable_pipe(intel_crtc);
4434
4435 if (intel_crtc->config->has_pch_encoder)
4436 ironlake_pch_enable(crtc);
4437
4438 assert_vblank_disabled(crtc);
4439 drm_crtc_vblank_on(crtc);
4440
4441 for_each_encoder_on_crtc(dev, crtc, encoder)
4442 encoder->enable(encoder);
4443
4444 if (HAS_PCH_CPT(dev))
4445 cpt_verify_modeset(dev, intel_crtc->pipe);
4446
4447 intel_crtc_enable_planes(crtc);
4448 }
4449
4450 /* IPS only exists on ULT machines and is tied to pipe A. */
4451 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4452 {
4453 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4454 }
4455
4456 /*
4457 * This implements the workaround described in the "notes" section of the mode
4458 * set sequence documentation. When going from no pipes or single pipe to
4459 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4460 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4461 */
4462 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4463 {
4464 struct drm_device *dev = crtc->base.dev;
4465 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4466
4467 /* We want to get the other_active_crtc only if there's only 1 other
4468 * active crtc. */
4469 for_each_intel_crtc(dev, crtc_it) {
4470 if (!crtc_it->active || crtc_it == crtc)
4471 continue;
4472
4473 if (other_active_crtc)
4474 return;
4475
4476 other_active_crtc = crtc_it;
4477 }
4478 if (!other_active_crtc)
4479 return;
4480
4481 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4482 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4483 }
4484
4485 static void haswell_crtc_enable(struct drm_crtc *crtc)
4486 {
4487 struct drm_device *dev = crtc->dev;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4490 struct intel_encoder *encoder;
4491 int pipe = intel_crtc->pipe;
4492
4493 WARN_ON(!crtc->state->enable);
4494
4495 if (intel_crtc->active)
4496 return;
4497
4498 if (intel_crtc_to_shared_dpll(intel_crtc))
4499 intel_enable_shared_dpll(intel_crtc);
4500
4501 if (intel_crtc->config->has_dp_encoder)
4502 intel_dp_set_m_n(intel_crtc, M1_N1);
4503
4504 intel_set_pipe_timings(intel_crtc);
4505
4506 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4507 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4508 intel_crtc->config->pixel_multiplier - 1);
4509 }
4510
4511 if (intel_crtc->config->has_pch_encoder) {
4512 intel_cpu_transcoder_set_m_n(intel_crtc,
4513 &intel_crtc->config->fdi_m_n, NULL);
4514 }
4515
4516 haswell_set_pipeconf(crtc);
4517
4518 intel_set_pipe_csc(crtc);
4519
4520 intel_crtc->active = true;
4521
4522 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4523 for_each_encoder_on_crtc(dev, crtc, encoder)
4524 if (encoder->pre_enable)
4525 encoder->pre_enable(encoder);
4526
4527 if (intel_crtc->config->has_pch_encoder) {
4528 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4529 true);
4530 dev_priv->display.fdi_link_train(crtc);
4531 }
4532
4533 intel_ddi_enable_pipe_clock(intel_crtc);
4534
4535 if (IS_SKYLAKE(dev))
4536 skylake_pfit_enable(intel_crtc);
4537 else
4538 ironlake_pfit_enable(intel_crtc);
4539
4540 /*
4541 * On ILK+ LUT must be loaded before the pipe is running but with
4542 * clocks enabled
4543 */
4544 intel_crtc_load_lut(crtc);
4545
4546 intel_ddi_set_pipe_settings(crtc);
4547 intel_ddi_enable_transcoder_func(crtc);
4548
4549 intel_update_watermarks(crtc);
4550 intel_enable_pipe(intel_crtc);
4551
4552 if (intel_crtc->config->has_pch_encoder)
4553 lpt_pch_enable(crtc);
4554
4555 if (intel_crtc->config->dp_encoder_is_mst)
4556 intel_ddi_set_vc_payload_alloc(crtc, true);
4557
4558 assert_vblank_disabled(crtc);
4559 drm_crtc_vblank_on(crtc);
4560
4561 for_each_encoder_on_crtc(dev, crtc, encoder) {
4562 encoder->enable(encoder);
4563 intel_opregion_notify_encoder(encoder, true);
4564 }
4565
4566 /* If we change the relative order between pipe/planes enabling, we need
4567 * to change the workaround. */
4568 haswell_mode_set_planes_workaround(intel_crtc);
4569 intel_crtc_enable_planes(crtc);
4570 }
4571
4572 static void skylake_pfit_disable(struct intel_crtc *crtc)
4573 {
4574 struct drm_device *dev = crtc->base.dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 int pipe = crtc->pipe;
4577
4578 /* To avoid upsetting the power well on haswell only disable the pfit if
4579 * it's in use. The hw state code will make sure we get this right. */
4580 if (crtc->config->pch_pfit.enabled) {
4581 I915_WRITE(PS_CTL(pipe), 0);
4582 I915_WRITE(PS_WIN_POS(pipe), 0);
4583 I915_WRITE(PS_WIN_SZ(pipe), 0);
4584 }
4585 }
4586
4587 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4588 {
4589 struct drm_device *dev = crtc->base.dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 int pipe = crtc->pipe;
4592
4593 /* To avoid upsetting the power well on haswell only disable the pfit if
4594 * it's in use. The hw state code will make sure we get this right. */
4595 if (crtc->config->pch_pfit.enabled) {
4596 I915_WRITE(PF_CTL(pipe), 0);
4597 I915_WRITE(PF_WIN_POS(pipe), 0);
4598 I915_WRITE(PF_WIN_SZ(pipe), 0);
4599 }
4600 }
4601
4602 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4603 {
4604 struct drm_device *dev = crtc->dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4607 struct intel_encoder *encoder;
4608 int pipe = intel_crtc->pipe;
4609 u32 reg, temp;
4610
4611 if (!intel_crtc->active)
4612 return;
4613
4614 intel_crtc_disable_planes(crtc);
4615
4616 for_each_encoder_on_crtc(dev, crtc, encoder)
4617 encoder->disable(encoder);
4618
4619 drm_crtc_vblank_off(crtc);
4620 assert_vblank_disabled(crtc);
4621
4622 if (intel_crtc->config->has_pch_encoder)
4623 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4624
4625 intel_disable_pipe(intel_crtc);
4626
4627 ironlake_pfit_disable(intel_crtc);
4628
4629 for_each_encoder_on_crtc(dev, crtc, encoder)
4630 if (encoder->post_disable)
4631 encoder->post_disable(encoder);
4632
4633 if (intel_crtc->config->has_pch_encoder) {
4634 ironlake_fdi_disable(crtc);
4635
4636 ironlake_disable_pch_transcoder(dev_priv, pipe);
4637
4638 if (HAS_PCH_CPT(dev)) {
4639 /* disable TRANS_DP_CTL */
4640 reg = TRANS_DP_CTL(pipe);
4641 temp = I915_READ(reg);
4642 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4643 TRANS_DP_PORT_SEL_MASK);
4644 temp |= TRANS_DP_PORT_SEL_NONE;
4645 I915_WRITE(reg, temp);
4646
4647 /* disable DPLL_SEL */
4648 temp = I915_READ(PCH_DPLL_SEL);
4649 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4650 I915_WRITE(PCH_DPLL_SEL, temp);
4651 }
4652
4653 /* disable PCH DPLL */
4654 intel_disable_shared_dpll(intel_crtc);
4655
4656 ironlake_fdi_pll_disable(intel_crtc);
4657 }
4658
4659 intel_crtc->active = false;
4660 intel_update_watermarks(crtc);
4661
4662 mutex_lock(&dev->struct_mutex);
4663 intel_fbc_update(dev);
4664 mutex_unlock(&dev->struct_mutex);
4665 }
4666
4667 static void haswell_crtc_disable(struct drm_crtc *crtc)
4668 {
4669 struct drm_device *dev = crtc->dev;
4670 struct drm_i915_private *dev_priv = dev->dev_private;
4671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4672 struct intel_encoder *encoder;
4673 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4674
4675 if (!intel_crtc->active)
4676 return;
4677
4678 intel_crtc_disable_planes(crtc);
4679
4680 for_each_encoder_on_crtc(dev, crtc, encoder) {
4681 intel_opregion_notify_encoder(encoder, false);
4682 encoder->disable(encoder);
4683 }
4684
4685 drm_crtc_vblank_off(crtc);
4686 assert_vblank_disabled(crtc);
4687
4688 if (intel_crtc->config->has_pch_encoder)
4689 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4690 false);
4691 intel_disable_pipe(intel_crtc);
4692
4693 if (intel_crtc->config->dp_encoder_is_mst)
4694 intel_ddi_set_vc_payload_alloc(crtc, false);
4695
4696 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4697
4698 if (IS_SKYLAKE(dev))
4699 skylake_pfit_disable(intel_crtc);
4700 else
4701 ironlake_pfit_disable(intel_crtc);
4702
4703 intel_ddi_disable_pipe_clock(intel_crtc);
4704
4705 if (intel_crtc->config->has_pch_encoder) {
4706 lpt_disable_pch_transcoder(dev_priv);
4707 intel_ddi_fdi_disable(crtc);
4708 }
4709
4710 for_each_encoder_on_crtc(dev, crtc, encoder)
4711 if (encoder->post_disable)
4712 encoder->post_disable(encoder);
4713
4714 intel_crtc->active = false;
4715 intel_update_watermarks(crtc);
4716
4717 mutex_lock(&dev->struct_mutex);
4718 intel_fbc_update(dev);
4719 mutex_unlock(&dev->struct_mutex);
4720
4721 if (intel_crtc_to_shared_dpll(intel_crtc))
4722 intel_disable_shared_dpll(intel_crtc);
4723 }
4724
4725 static void ironlake_crtc_off(struct drm_crtc *crtc)
4726 {
4727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4728 intel_put_shared_dpll(intel_crtc);
4729 }
4730
4731
4732 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4733 {
4734 struct drm_device *dev = crtc->base.dev;
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 struct intel_crtc_state *pipe_config = crtc->config;
4737
4738 if (!pipe_config->gmch_pfit.control)
4739 return;
4740
4741 /*
4742 * The panel fitter should only be adjusted whilst the pipe is disabled,
4743 * according to register description and PRM.
4744 */
4745 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4746 assert_pipe_disabled(dev_priv, crtc->pipe);
4747
4748 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4749 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4750
4751 /* Border color in case we don't scale up to the full screen. Black by
4752 * default, change to something else for debugging. */
4753 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4754 }
4755
4756 static enum intel_display_power_domain port_to_power_domain(enum port port)
4757 {
4758 switch (port) {
4759 case PORT_A:
4760 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4761 case PORT_B:
4762 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4763 case PORT_C:
4764 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4765 case PORT_D:
4766 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4767 default:
4768 WARN_ON_ONCE(1);
4769 return POWER_DOMAIN_PORT_OTHER;
4770 }
4771 }
4772
4773 #define for_each_power_domain(domain, mask) \
4774 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4775 if ((1 << (domain)) & (mask))
4776
4777 enum intel_display_power_domain
4778 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4779 {
4780 struct drm_device *dev = intel_encoder->base.dev;
4781 struct intel_digital_port *intel_dig_port;
4782
4783 switch (intel_encoder->type) {
4784 case INTEL_OUTPUT_UNKNOWN:
4785 /* Only DDI platforms should ever use this output type */
4786 WARN_ON_ONCE(!HAS_DDI(dev));
4787 case INTEL_OUTPUT_DISPLAYPORT:
4788 case INTEL_OUTPUT_HDMI:
4789 case INTEL_OUTPUT_EDP:
4790 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4791 return port_to_power_domain(intel_dig_port->port);
4792 case INTEL_OUTPUT_DP_MST:
4793 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4794 return port_to_power_domain(intel_dig_port->port);
4795 case INTEL_OUTPUT_ANALOG:
4796 return POWER_DOMAIN_PORT_CRT;
4797 case INTEL_OUTPUT_DSI:
4798 return POWER_DOMAIN_PORT_DSI;
4799 default:
4800 return POWER_DOMAIN_PORT_OTHER;
4801 }
4802 }
4803
4804 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4805 {
4806 struct drm_device *dev = crtc->dev;
4807 struct intel_encoder *intel_encoder;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 enum pipe pipe = intel_crtc->pipe;
4810 unsigned long mask;
4811 enum transcoder transcoder;
4812
4813 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4814
4815 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4816 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4817 if (intel_crtc->config->pch_pfit.enabled ||
4818 intel_crtc->config->pch_pfit.force_thru)
4819 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4820
4821 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4822 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4823
4824 return mask;
4825 }
4826
4827 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4828 {
4829 struct drm_i915_private *dev_priv = dev->dev_private;
4830 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4831 struct intel_crtc *crtc;
4832
4833 /*
4834 * First get all needed power domains, then put all unneeded, to avoid
4835 * any unnecessary toggling of the power wells.
4836 */
4837 for_each_intel_crtc(dev, crtc) {
4838 enum intel_display_power_domain domain;
4839
4840 if (!crtc->base.state->enable)
4841 continue;
4842
4843 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4844
4845 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4846 intel_display_power_get(dev_priv, domain);
4847 }
4848
4849 if (dev_priv->display.modeset_global_resources)
4850 dev_priv->display.modeset_global_resources(dev);
4851
4852 for_each_intel_crtc(dev, crtc) {
4853 enum intel_display_power_domain domain;
4854
4855 for_each_power_domain(domain, crtc->enabled_power_domains)
4856 intel_display_power_put(dev_priv, domain);
4857
4858 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4859 }
4860
4861 intel_display_set_init_power(dev_priv, false);
4862 }
4863
4864 /* returns HPLL frequency in kHz */
4865 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4866 {
4867 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4868
4869 /* Obtain SKU information */
4870 mutex_lock(&dev_priv->dpio_lock);
4871 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4872 CCK_FUSE_HPLL_FREQ_MASK;
4873 mutex_unlock(&dev_priv->dpio_lock);
4874
4875 return vco_freq[hpll_freq] * 1000;
4876 }
4877
4878 static void vlv_update_cdclk(struct drm_device *dev)
4879 {
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881
4882 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4883 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4884 dev_priv->vlv_cdclk_freq);
4885
4886 /*
4887 * Program the gmbus_freq based on the cdclk frequency.
4888 * BSpec erroneously claims we should aim for 4MHz, but
4889 * in fact 1MHz is the correct frequency.
4890 */
4891 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4892 }
4893
4894 /* Adjust CDclk dividers to allow high res or save power if possible */
4895 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4896 {
4897 struct drm_i915_private *dev_priv = dev->dev_private;
4898 u32 val, cmd;
4899
4900 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4901
4902 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4903 cmd = 2;
4904 else if (cdclk == 266667)
4905 cmd = 1;
4906 else
4907 cmd = 0;
4908
4909 mutex_lock(&dev_priv->rps.hw_lock);
4910 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4911 val &= ~DSPFREQGUAR_MASK;
4912 val |= (cmd << DSPFREQGUAR_SHIFT);
4913 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4914 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4915 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4916 50)) {
4917 DRM_ERROR("timed out waiting for CDclk change\n");
4918 }
4919 mutex_unlock(&dev_priv->rps.hw_lock);
4920
4921 if (cdclk == 400000) {
4922 u32 divider;
4923
4924 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4925
4926 mutex_lock(&dev_priv->dpio_lock);
4927 /* adjust cdclk divider */
4928 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4929 val &= ~DISPLAY_FREQUENCY_VALUES;
4930 val |= divider;
4931 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4932
4933 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4934 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4935 50))
4936 DRM_ERROR("timed out waiting for CDclk change\n");
4937 mutex_unlock(&dev_priv->dpio_lock);
4938 }
4939
4940 mutex_lock(&dev_priv->dpio_lock);
4941 /* adjust self-refresh exit latency value */
4942 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4943 val &= ~0x7f;
4944
4945 /*
4946 * For high bandwidth configs, we set a higher latency in the bunit
4947 * so that the core display fetch happens in time to avoid underruns.
4948 */
4949 if (cdclk == 400000)
4950 val |= 4500 / 250; /* 4.5 usec */
4951 else
4952 val |= 3000 / 250; /* 3.0 usec */
4953 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4954 mutex_unlock(&dev_priv->dpio_lock);
4955
4956 vlv_update_cdclk(dev);
4957 }
4958
4959 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4960 {
4961 struct drm_i915_private *dev_priv = dev->dev_private;
4962 u32 val, cmd;
4963
4964 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4965
4966 switch (cdclk) {
4967 case 333333:
4968 case 320000:
4969 case 266667:
4970 case 200000:
4971 break;
4972 default:
4973 MISSING_CASE(cdclk);
4974 return;
4975 }
4976
4977 /*
4978 * Specs are full of misinformation, but testing on actual
4979 * hardware has shown that we just need to write the desired
4980 * CCK divider into the Punit register.
4981 */
4982 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4983
4984 mutex_lock(&dev_priv->rps.hw_lock);
4985 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4986 val &= ~DSPFREQGUAR_MASK_CHV;
4987 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4988 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4989 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4990 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4991 50)) {
4992 DRM_ERROR("timed out waiting for CDclk change\n");
4993 }
4994 mutex_unlock(&dev_priv->rps.hw_lock);
4995
4996 vlv_update_cdclk(dev);
4997 }
4998
4999 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5000 int max_pixclk)
5001 {
5002 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5003 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5004
5005 /*
5006 * Really only a few cases to deal with, as only 4 CDclks are supported:
5007 * 200MHz
5008 * 267MHz
5009 * 320/333MHz (depends on HPLL freq)
5010 * 400MHz (VLV only)
5011 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5012 * of the lower bin and adjust if needed.
5013 *
5014 * We seem to get an unstable or solid color picture at 200MHz.
5015 * Not sure what's wrong. For now use 200MHz only when all pipes
5016 * are off.
5017 */
5018 if (!IS_CHERRYVIEW(dev_priv) &&
5019 max_pixclk > freq_320*limit/100)
5020 return 400000;
5021 else if (max_pixclk > 266667*limit/100)
5022 return freq_320;
5023 else if (max_pixclk > 0)
5024 return 266667;
5025 else
5026 return 200000;
5027 }
5028
5029 /* compute the max pixel clock for new configuration */
5030 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5031 {
5032 struct drm_device *dev = dev_priv->dev;
5033 struct intel_crtc *intel_crtc;
5034 int max_pixclk = 0;
5035
5036 for_each_intel_crtc(dev, intel_crtc) {
5037 if (intel_crtc->new_enabled)
5038 max_pixclk = max(max_pixclk,
5039 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5040 }
5041
5042 return max_pixclk;
5043 }
5044
5045 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5046 unsigned *prepare_pipes)
5047 {
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 struct intel_crtc *intel_crtc;
5050 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5051
5052 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5053 dev_priv->vlv_cdclk_freq)
5054 return;
5055
5056 /* disable/enable all currently active pipes while we change cdclk */
5057 for_each_intel_crtc(dev, intel_crtc)
5058 if (intel_crtc->base.state->enable)
5059 *prepare_pipes |= (1 << intel_crtc->pipe);
5060 }
5061
5062 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5063 {
5064 unsigned int credits, default_credits;
5065
5066 if (IS_CHERRYVIEW(dev_priv))
5067 default_credits = PFI_CREDIT(12);
5068 else
5069 default_credits = PFI_CREDIT(8);
5070
5071 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5072 /* CHV suggested value is 31 or 63 */
5073 if (IS_CHERRYVIEW(dev_priv))
5074 credits = PFI_CREDIT_31;
5075 else
5076 credits = PFI_CREDIT(15);
5077 } else {
5078 credits = default_credits;
5079 }
5080
5081 /*
5082 * WA - write default credits before re-programming
5083 * FIXME: should we also set the resend bit here?
5084 */
5085 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5086 default_credits);
5087
5088 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5089 credits | PFI_CREDIT_RESEND);
5090
5091 /*
5092 * FIXME is this guaranteed to clear
5093 * immediately or should we poll for it?
5094 */
5095 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5096 }
5097
5098 static void valleyview_modeset_global_resources(struct drm_device *dev)
5099 {
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5102 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5103
5104 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5105 /*
5106 * FIXME: We can end up here with all power domains off, yet
5107 * with a CDCLK frequency other than the minimum. To account
5108 * for this take the PIPE-A power domain, which covers the HW
5109 * blocks needed for the following programming. This can be
5110 * removed once it's guaranteed that we get here either with
5111 * the minimum CDCLK set, or the required power domains
5112 * enabled.
5113 */
5114 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5115
5116 if (IS_CHERRYVIEW(dev))
5117 cherryview_set_cdclk(dev, req_cdclk);
5118 else
5119 valleyview_set_cdclk(dev, req_cdclk);
5120
5121 vlv_program_pfi_credits(dev_priv);
5122
5123 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5124 }
5125 }
5126
5127 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5128 {
5129 struct drm_device *dev = crtc->dev;
5130 struct drm_i915_private *dev_priv = to_i915(dev);
5131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5132 struct intel_encoder *encoder;
5133 int pipe = intel_crtc->pipe;
5134 bool is_dsi;
5135
5136 WARN_ON(!crtc->state->enable);
5137
5138 if (intel_crtc->active)
5139 return;
5140
5141 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5142
5143 if (!is_dsi) {
5144 if (IS_CHERRYVIEW(dev))
5145 chv_prepare_pll(intel_crtc, intel_crtc->config);
5146 else
5147 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5148 }
5149
5150 if (intel_crtc->config->has_dp_encoder)
5151 intel_dp_set_m_n(intel_crtc, M1_N1);
5152
5153 intel_set_pipe_timings(intel_crtc);
5154
5155 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157
5158 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5159 I915_WRITE(CHV_CANVAS(pipe), 0);
5160 }
5161
5162 i9xx_set_pipeconf(intel_crtc);
5163
5164 intel_crtc->active = true;
5165
5166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5167
5168 for_each_encoder_on_crtc(dev, crtc, encoder)
5169 if (encoder->pre_pll_enable)
5170 encoder->pre_pll_enable(encoder);
5171
5172 if (!is_dsi) {
5173 if (IS_CHERRYVIEW(dev))
5174 chv_enable_pll(intel_crtc, intel_crtc->config);
5175 else
5176 vlv_enable_pll(intel_crtc, intel_crtc->config);
5177 }
5178
5179 for_each_encoder_on_crtc(dev, crtc, encoder)
5180 if (encoder->pre_enable)
5181 encoder->pre_enable(encoder);
5182
5183 i9xx_pfit_enable(intel_crtc);
5184
5185 intel_crtc_load_lut(crtc);
5186
5187 intel_update_watermarks(crtc);
5188 intel_enable_pipe(intel_crtc);
5189
5190 assert_vblank_disabled(crtc);
5191 drm_crtc_vblank_on(crtc);
5192
5193 for_each_encoder_on_crtc(dev, crtc, encoder)
5194 encoder->enable(encoder);
5195
5196 intel_crtc_enable_planes(crtc);
5197
5198 /* Underruns don't raise interrupts, so check manually. */
5199 i9xx_check_fifo_underruns(dev_priv);
5200 }
5201
5202 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5203 {
5204 struct drm_device *dev = crtc->base.dev;
5205 struct drm_i915_private *dev_priv = dev->dev_private;
5206
5207 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5208 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5209 }
5210
5211 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5212 {
5213 struct drm_device *dev = crtc->dev;
5214 struct drm_i915_private *dev_priv = to_i915(dev);
5215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5216 struct intel_encoder *encoder;
5217 int pipe = intel_crtc->pipe;
5218
5219 WARN_ON(!crtc->state->enable);
5220
5221 if (intel_crtc->active)
5222 return;
5223
5224 i9xx_set_pll_dividers(intel_crtc);
5225
5226 if (intel_crtc->config->has_dp_encoder)
5227 intel_dp_set_m_n(intel_crtc, M1_N1);
5228
5229 intel_set_pipe_timings(intel_crtc);
5230
5231 i9xx_set_pipeconf(intel_crtc);
5232
5233 intel_crtc->active = true;
5234
5235 if (!IS_GEN2(dev))
5236 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5237
5238 for_each_encoder_on_crtc(dev, crtc, encoder)
5239 if (encoder->pre_enable)
5240 encoder->pre_enable(encoder);
5241
5242 i9xx_enable_pll(intel_crtc);
5243
5244 i9xx_pfit_enable(intel_crtc);
5245
5246 intel_crtc_load_lut(crtc);
5247
5248 intel_update_watermarks(crtc);
5249 intel_enable_pipe(intel_crtc);
5250
5251 assert_vblank_disabled(crtc);
5252 drm_crtc_vblank_on(crtc);
5253
5254 for_each_encoder_on_crtc(dev, crtc, encoder)
5255 encoder->enable(encoder);
5256
5257 intel_crtc_enable_planes(crtc);
5258
5259 /*
5260 * Gen2 reports pipe underruns whenever all planes are disabled.
5261 * So don't enable underrun reporting before at least some planes
5262 * are enabled.
5263 * FIXME: Need to fix the logic to work when we turn off all planes
5264 * but leave the pipe running.
5265 */
5266 if (IS_GEN2(dev))
5267 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5268
5269 /* Underruns don't raise interrupts, so check manually. */
5270 i9xx_check_fifo_underruns(dev_priv);
5271 }
5272
5273 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5274 {
5275 struct drm_device *dev = crtc->base.dev;
5276 struct drm_i915_private *dev_priv = dev->dev_private;
5277
5278 if (!crtc->config->gmch_pfit.control)
5279 return;
5280
5281 assert_pipe_disabled(dev_priv, crtc->pipe);
5282
5283 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5284 I915_READ(PFIT_CONTROL));
5285 I915_WRITE(PFIT_CONTROL, 0);
5286 }
5287
5288 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5289 {
5290 struct drm_device *dev = crtc->dev;
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5293 struct intel_encoder *encoder;
5294 int pipe = intel_crtc->pipe;
5295
5296 if (!intel_crtc->active)
5297 return;
5298
5299 /*
5300 * Gen2 reports pipe underruns whenever all planes are disabled.
5301 * So diasble underrun reporting before all the planes get disabled.
5302 * FIXME: Need to fix the logic to work when we turn off all planes
5303 * but leave the pipe running.
5304 */
5305 if (IS_GEN2(dev))
5306 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5307
5308 /*
5309 * Vblank time updates from the shadow to live plane control register
5310 * are blocked if the memory self-refresh mode is active at that
5311 * moment. So to make sure the plane gets truly disabled, disable
5312 * first the self-refresh mode. The self-refresh enable bit in turn
5313 * will be checked/applied by the HW only at the next frame start
5314 * event which is after the vblank start event, so we need to have a
5315 * wait-for-vblank between disabling the plane and the pipe.
5316 */
5317 intel_set_memory_cxsr(dev_priv, false);
5318 intel_crtc_disable_planes(crtc);
5319
5320 /*
5321 * On gen2 planes are double buffered but the pipe isn't, so we must
5322 * wait for planes to fully turn off before disabling the pipe.
5323 * We also need to wait on all gmch platforms because of the
5324 * self-refresh mode constraint explained above.
5325 */
5326 intel_wait_for_vblank(dev, pipe);
5327
5328 for_each_encoder_on_crtc(dev, crtc, encoder)
5329 encoder->disable(encoder);
5330
5331 drm_crtc_vblank_off(crtc);
5332 assert_vblank_disabled(crtc);
5333
5334 intel_disable_pipe(intel_crtc);
5335
5336 i9xx_pfit_disable(intel_crtc);
5337
5338 for_each_encoder_on_crtc(dev, crtc, encoder)
5339 if (encoder->post_disable)
5340 encoder->post_disable(encoder);
5341
5342 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5343 if (IS_CHERRYVIEW(dev))
5344 chv_disable_pll(dev_priv, pipe);
5345 else if (IS_VALLEYVIEW(dev))
5346 vlv_disable_pll(dev_priv, pipe);
5347 else
5348 i9xx_disable_pll(intel_crtc);
5349 }
5350
5351 if (!IS_GEN2(dev))
5352 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5353
5354 intel_crtc->active = false;
5355 intel_update_watermarks(crtc);
5356
5357 mutex_lock(&dev->struct_mutex);
5358 intel_fbc_update(dev);
5359 mutex_unlock(&dev->struct_mutex);
5360 }
5361
5362 static void i9xx_crtc_off(struct drm_crtc *crtc)
5363 {
5364 }
5365
5366 /* Master function to enable/disable CRTC and corresponding power wells */
5367 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5368 {
5369 struct drm_device *dev = crtc->dev;
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5372 enum intel_display_power_domain domain;
5373 unsigned long domains;
5374
5375 if (enable) {
5376 if (!intel_crtc->active) {
5377 domains = get_crtc_power_domains(crtc);
5378 for_each_power_domain(domain, domains)
5379 intel_display_power_get(dev_priv, domain);
5380 intel_crtc->enabled_power_domains = domains;
5381
5382 dev_priv->display.crtc_enable(crtc);
5383 }
5384 } else {
5385 if (intel_crtc->active) {
5386 dev_priv->display.crtc_disable(crtc);
5387
5388 domains = intel_crtc->enabled_power_domains;
5389 for_each_power_domain(domain, domains)
5390 intel_display_power_put(dev_priv, domain);
5391 intel_crtc->enabled_power_domains = 0;
5392 }
5393 }
5394 }
5395
5396 /**
5397 * Sets the power management mode of the pipe and plane.
5398 */
5399 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5400 {
5401 struct drm_device *dev = crtc->dev;
5402 struct intel_encoder *intel_encoder;
5403 bool enable = false;
5404
5405 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5406 enable |= intel_encoder->connectors_active;
5407
5408 intel_crtc_control(crtc, enable);
5409 }
5410
5411 static void intel_crtc_disable(struct drm_crtc *crtc)
5412 {
5413 struct drm_device *dev = crtc->dev;
5414 struct drm_connector *connector;
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416
5417 /* crtc should still be enabled when we disable it. */
5418 WARN_ON(!crtc->state->enable);
5419
5420 dev_priv->display.crtc_disable(crtc);
5421 dev_priv->display.off(crtc);
5422
5423 crtc->primary->funcs->disable_plane(crtc->primary);
5424
5425 /* Update computed state. */
5426 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5427 if (!connector->encoder || !connector->encoder->crtc)
5428 continue;
5429
5430 if (connector->encoder->crtc != crtc)
5431 continue;
5432
5433 connector->dpms = DRM_MODE_DPMS_OFF;
5434 to_intel_encoder(connector->encoder)->connectors_active = false;
5435 }
5436 }
5437
5438 void intel_encoder_destroy(struct drm_encoder *encoder)
5439 {
5440 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5441
5442 drm_encoder_cleanup(encoder);
5443 kfree(intel_encoder);
5444 }
5445
5446 /* Simple dpms helper for encoders with just one connector, no cloning and only
5447 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5448 * state of the entire output pipe. */
5449 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5450 {
5451 if (mode == DRM_MODE_DPMS_ON) {
5452 encoder->connectors_active = true;
5453
5454 intel_crtc_update_dpms(encoder->base.crtc);
5455 } else {
5456 encoder->connectors_active = false;
5457
5458 intel_crtc_update_dpms(encoder->base.crtc);
5459 }
5460 }
5461
5462 /* Cross check the actual hw state with our own modeset state tracking (and it's
5463 * internal consistency). */
5464 static void intel_connector_check_state(struct intel_connector *connector)
5465 {
5466 if (connector->get_hw_state(connector)) {
5467 struct intel_encoder *encoder = connector->encoder;
5468 struct drm_crtc *crtc;
5469 bool encoder_enabled;
5470 enum pipe pipe;
5471
5472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5473 connector->base.base.id,
5474 connector->base.name);
5475
5476 /* there is no real hw state for MST connectors */
5477 if (connector->mst_port)
5478 return;
5479
5480 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5481 "wrong connector dpms state\n");
5482 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5483 "active connector not linked to encoder\n");
5484
5485 if (encoder) {
5486 I915_STATE_WARN(!encoder->connectors_active,
5487 "encoder->connectors_active not set\n");
5488
5489 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5490 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5491 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5492 return;
5493
5494 crtc = encoder->base.crtc;
5495
5496 I915_STATE_WARN(!crtc->state->enable,
5497 "crtc not enabled\n");
5498 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5499 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5500 "encoder active on the wrong pipe\n");
5501 }
5502 }
5503 }
5504
5505 /* Even simpler default implementation, if there's really no special case to
5506 * consider. */
5507 void intel_connector_dpms(struct drm_connector *connector, int mode)
5508 {
5509 /* All the simple cases only support two dpms states. */
5510 if (mode != DRM_MODE_DPMS_ON)
5511 mode = DRM_MODE_DPMS_OFF;
5512
5513 if (mode == connector->dpms)
5514 return;
5515
5516 connector->dpms = mode;
5517
5518 /* Only need to change hw state when actually enabled */
5519 if (connector->encoder)
5520 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5521
5522 intel_modeset_check_state(connector->dev);
5523 }
5524
5525 /* Simple connector->get_hw_state implementation for encoders that support only
5526 * one connector and no cloning and hence the encoder state determines the state
5527 * of the connector. */
5528 bool intel_connector_get_hw_state(struct intel_connector *connector)
5529 {
5530 enum pipe pipe = 0;
5531 struct intel_encoder *encoder = connector->encoder;
5532
5533 return encoder->get_hw_state(encoder, &pipe);
5534 }
5535
5536 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5537 {
5538 struct intel_crtc *crtc =
5539 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5540
5541 if (crtc->base.state->enable &&
5542 crtc->config->has_pch_encoder)
5543 return crtc->config->fdi_lanes;
5544
5545 return 0;
5546 }
5547
5548 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5549 struct intel_crtc_state *pipe_config)
5550 {
5551 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5552 pipe_name(pipe), pipe_config->fdi_lanes);
5553 if (pipe_config->fdi_lanes > 4) {
5554 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5555 pipe_name(pipe), pipe_config->fdi_lanes);
5556 return false;
5557 }
5558
5559 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5560 if (pipe_config->fdi_lanes > 2) {
5561 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5562 pipe_config->fdi_lanes);
5563 return false;
5564 } else {
5565 return true;
5566 }
5567 }
5568
5569 if (INTEL_INFO(dev)->num_pipes == 2)
5570 return true;
5571
5572 /* Ivybridge 3 pipe is really complicated */
5573 switch (pipe) {
5574 case PIPE_A:
5575 return true;
5576 case PIPE_B:
5577 if (pipe_config->fdi_lanes > 2 &&
5578 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5579 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5580 pipe_name(pipe), pipe_config->fdi_lanes);
5581 return false;
5582 }
5583 return true;
5584 case PIPE_C:
5585 if (pipe_config->fdi_lanes > 2) {
5586 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5587 pipe_name(pipe), pipe_config->fdi_lanes);
5588 return false;
5589 }
5590 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5591 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5592 return false;
5593 }
5594 return true;
5595 default:
5596 BUG();
5597 }
5598 }
5599
5600 #define RETRY 1
5601 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5602 struct intel_crtc_state *pipe_config)
5603 {
5604 struct drm_device *dev = intel_crtc->base.dev;
5605 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5606 int lane, link_bw, fdi_dotclock;
5607 bool setup_ok, needs_recompute = false;
5608
5609 retry:
5610 /* FDI is a binary signal running at ~2.7GHz, encoding
5611 * each output octet as 10 bits. The actual frequency
5612 * is stored as a divider into a 100MHz clock, and the
5613 * mode pixel clock is stored in units of 1KHz.
5614 * Hence the bw of each lane in terms of the mode signal
5615 * is:
5616 */
5617 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5618
5619 fdi_dotclock = adjusted_mode->crtc_clock;
5620
5621 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5622 pipe_config->pipe_bpp);
5623
5624 pipe_config->fdi_lanes = lane;
5625
5626 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5627 link_bw, &pipe_config->fdi_m_n);
5628
5629 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5630 intel_crtc->pipe, pipe_config);
5631 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5632 pipe_config->pipe_bpp -= 2*3;
5633 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5634 pipe_config->pipe_bpp);
5635 needs_recompute = true;
5636 pipe_config->bw_constrained = true;
5637
5638 goto retry;
5639 }
5640
5641 if (needs_recompute)
5642 return RETRY;
5643
5644 return setup_ok ? 0 : -EINVAL;
5645 }
5646
5647 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5648 struct intel_crtc_state *pipe_config)
5649 {
5650 pipe_config->ips_enabled = i915.enable_ips &&
5651 hsw_crtc_supports_ips(crtc) &&
5652 pipe_config->pipe_bpp <= 24;
5653 }
5654
5655 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5656 struct intel_crtc_state *pipe_config)
5657 {
5658 struct drm_device *dev = crtc->base.dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5661
5662 /* FIXME should check pixel clock limits on all platforms */
5663 if (INTEL_INFO(dev)->gen < 4) {
5664 int clock_limit =
5665 dev_priv->display.get_display_clock_speed(dev);
5666
5667 /*
5668 * Enable pixel doubling when the dot clock
5669 * is > 90% of the (display) core speed.
5670 *
5671 * GDG double wide on either pipe,
5672 * otherwise pipe A only.
5673 */
5674 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5675 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5676 clock_limit *= 2;
5677 pipe_config->double_wide = true;
5678 }
5679
5680 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5681 return -EINVAL;
5682 }
5683
5684 /*
5685 * Pipe horizontal size must be even in:
5686 * - DVO ganged mode
5687 * - LVDS dual channel mode
5688 * - Double wide pipe
5689 */
5690 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5691 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5692 pipe_config->pipe_src_w &= ~1;
5693
5694 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5695 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5696 */
5697 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5698 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5699 return -EINVAL;
5700
5701 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5702 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5703 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5704 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5705 * for lvds. */
5706 pipe_config->pipe_bpp = 8*3;
5707 }
5708
5709 if (HAS_IPS(dev))
5710 hsw_compute_ips_config(crtc, pipe_config);
5711
5712 if (pipe_config->has_pch_encoder)
5713 return ironlake_fdi_compute_config(crtc, pipe_config);
5714
5715 return 0;
5716 }
5717
5718 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5719 {
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 u32 val;
5722 int divider;
5723
5724 if (dev_priv->hpll_freq == 0)
5725 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5726
5727 mutex_lock(&dev_priv->dpio_lock);
5728 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5729 mutex_unlock(&dev_priv->dpio_lock);
5730
5731 divider = val & DISPLAY_FREQUENCY_VALUES;
5732
5733 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5734 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5735 "cdclk change in progress\n");
5736
5737 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5738 }
5739
5740 static int i945_get_display_clock_speed(struct drm_device *dev)
5741 {
5742 return 400000;
5743 }
5744
5745 static int i915_get_display_clock_speed(struct drm_device *dev)
5746 {
5747 return 333000;
5748 }
5749
5750 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5751 {
5752 return 200000;
5753 }
5754
5755 static int pnv_get_display_clock_speed(struct drm_device *dev)
5756 {
5757 u16 gcfgc = 0;
5758
5759 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5760
5761 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5762 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5763 return 267000;
5764 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5765 return 333000;
5766 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5767 return 444000;
5768 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5769 return 200000;
5770 default:
5771 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5772 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5773 return 133000;
5774 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5775 return 167000;
5776 }
5777 }
5778
5779 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5780 {
5781 u16 gcfgc = 0;
5782
5783 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5784
5785 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5786 return 133000;
5787 else {
5788 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5789 case GC_DISPLAY_CLOCK_333_MHZ:
5790 return 333000;
5791 default:
5792 case GC_DISPLAY_CLOCK_190_200_MHZ:
5793 return 190000;
5794 }
5795 }
5796 }
5797
5798 static int i865_get_display_clock_speed(struct drm_device *dev)
5799 {
5800 return 266000;
5801 }
5802
5803 static int i855_get_display_clock_speed(struct drm_device *dev)
5804 {
5805 u16 hpllcc = 0;
5806 /* Assume that the hardware is in the high speed state. This
5807 * should be the default.
5808 */
5809 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5810 case GC_CLOCK_133_200:
5811 case GC_CLOCK_100_200:
5812 return 200000;
5813 case GC_CLOCK_166_250:
5814 return 250000;
5815 case GC_CLOCK_100_133:
5816 return 133000;
5817 }
5818
5819 /* Shouldn't happen */
5820 return 0;
5821 }
5822
5823 static int i830_get_display_clock_speed(struct drm_device *dev)
5824 {
5825 return 133000;
5826 }
5827
5828 static void
5829 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5830 {
5831 while (*num > DATA_LINK_M_N_MASK ||
5832 *den > DATA_LINK_M_N_MASK) {
5833 *num >>= 1;
5834 *den >>= 1;
5835 }
5836 }
5837
5838 static void compute_m_n(unsigned int m, unsigned int n,
5839 uint32_t *ret_m, uint32_t *ret_n)
5840 {
5841 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5842 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5843 intel_reduce_m_n_ratio(ret_m, ret_n);
5844 }
5845
5846 void
5847 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5848 int pixel_clock, int link_clock,
5849 struct intel_link_m_n *m_n)
5850 {
5851 m_n->tu = 64;
5852
5853 compute_m_n(bits_per_pixel * pixel_clock,
5854 link_clock * nlanes * 8,
5855 &m_n->gmch_m, &m_n->gmch_n);
5856
5857 compute_m_n(pixel_clock, link_clock,
5858 &m_n->link_m, &m_n->link_n);
5859 }
5860
5861 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5862 {
5863 if (i915.panel_use_ssc >= 0)
5864 return i915.panel_use_ssc != 0;
5865 return dev_priv->vbt.lvds_use_ssc
5866 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5867 }
5868
5869 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5870 {
5871 struct drm_device *dev = crtc->base.dev;
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5873 int refclk;
5874
5875 if (IS_VALLEYVIEW(dev)) {
5876 refclk = 100000;
5877 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5878 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5879 refclk = dev_priv->vbt.lvds_ssc_freq;
5880 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5881 } else if (!IS_GEN2(dev)) {
5882 refclk = 96000;
5883 } else {
5884 refclk = 48000;
5885 }
5886
5887 return refclk;
5888 }
5889
5890 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5891 {
5892 return (1 << dpll->n) << 16 | dpll->m2;
5893 }
5894
5895 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5896 {
5897 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5898 }
5899
5900 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5901 struct intel_crtc_state *crtc_state,
5902 intel_clock_t *reduced_clock)
5903 {
5904 struct drm_device *dev = crtc->base.dev;
5905 u32 fp, fp2 = 0;
5906
5907 if (IS_PINEVIEW(dev)) {
5908 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5909 if (reduced_clock)
5910 fp2 = pnv_dpll_compute_fp(reduced_clock);
5911 } else {
5912 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5913 if (reduced_clock)
5914 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5915 }
5916
5917 crtc_state->dpll_hw_state.fp0 = fp;
5918
5919 crtc->lowfreq_avail = false;
5920 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5921 reduced_clock && i915.powersave) {
5922 crtc_state->dpll_hw_state.fp1 = fp2;
5923 crtc->lowfreq_avail = true;
5924 } else {
5925 crtc_state->dpll_hw_state.fp1 = fp;
5926 }
5927 }
5928
5929 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5930 pipe)
5931 {
5932 u32 reg_val;
5933
5934 /*
5935 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5936 * and set it to a reasonable value instead.
5937 */
5938 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5939 reg_val &= 0xffffff00;
5940 reg_val |= 0x00000030;
5941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5942
5943 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5944 reg_val &= 0x8cffffff;
5945 reg_val = 0x8c000000;
5946 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5947
5948 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5949 reg_val &= 0xffffff00;
5950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5951
5952 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5953 reg_val &= 0x00ffffff;
5954 reg_val |= 0xb0000000;
5955 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5956 }
5957
5958 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5959 struct intel_link_m_n *m_n)
5960 {
5961 struct drm_device *dev = crtc->base.dev;
5962 struct drm_i915_private *dev_priv = dev->dev_private;
5963 int pipe = crtc->pipe;
5964
5965 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5966 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5967 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5968 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5969 }
5970
5971 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5972 struct intel_link_m_n *m_n,
5973 struct intel_link_m_n *m2_n2)
5974 {
5975 struct drm_device *dev = crtc->base.dev;
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int pipe = crtc->pipe;
5978 enum transcoder transcoder = crtc->config->cpu_transcoder;
5979
5980 if (INTEL_INFO(dev)->gen >= 5) {
5981 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5982 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5983 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5984 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5985 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5986 * for gen < 8) and if DRRS is supported (to make sure the
5987 * registers are not unnecessarily accessed).
5988 */
5989 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
5990 crtc->config->has_drrs) {
5991 I915_WRITE(PIPE_DATA_M2(transcoder),
5992 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5993 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5994 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5995 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5996 }
5997 } else {
5998 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5999 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6000 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6001 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6002 }
6003 }
6004
6005 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6006 {
6007 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6008
6009 if (m_n == M1_N1) {
6010 dp_m_n = &crtc->config->dp_m_n;
6011 dp_m2_n2 = &crtc->config->dp_m2_n2;
6012 } else if (m_n == M2_N2) {
6013
6014 /*
6015 * M2_N2 registers are not supported. Hence m2_n2 divider value
6016 * needs to be programmed into M1_N1.
6017 */
6018 dp_m_n = &crtc->config->dp_m2_n2;
6019 } else {
6020 DRM_ERROR("Unsupported divider value\n");
6021 return;
6022 }
6023
6024 if (crtc->config->has_pch_encoder)
6025 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6026 else
6027 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6028 }
6029
6030 static void vlv_update_pll(struct intel_crtc *crtc,
6031 struct intel_crtc_state *pipe_config)
6032 {
6033 u32 dpll, dpll_md;
6034
6035 /*
6036 * Enable DPIO clock input. We should never disable the reference
6037 * clock for pipe B, since VGA hotplug / manual detection depends
6038 * on it.
6039 */
6040 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6041 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6042 /* We should never disable this, set it here for state tracking */
6043 if (crtc->pipe == PIPE_B)
6044 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6045 dpll |= DPLL_VCO_ENABLE;
6046 pipe_config->dpll_hw_state.dpll = dpll;
6047
6048 dpll_md = (pipe_config->pixel_multiplier - 1)
6049 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6050 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6051 }
6052
6053 static void vlv_prepare_pll(struct intel_crtc *crtc,
6054 const struct intel_crtc_state *pipe_config)
6055 {
6056 struct drm_device *dev = crtc->base.dev;
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 int pipe = crtc->pipe;
6059 u32 mdiv;
6060 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6061 u32 coreclk, reg_val;
6062
6063 mutex_lock(&dev_priv->dpio_lock);
6064
6065 bestn = pipe_config->dpll.n;
6066 bestm1 = pipe_config->dpll.m1;
6067 bestm2 = pipe_config->dpll.m2;
6068 bestp1 = pipe_config->dpll.p1;
6069 bestp2 = pipe_config->dpll.p2;
6070
6071 /* See eDP HDMI DPIO driver vbios notes doc */
6072
6073 /* PLL B needs special handling */
6074 if (pipe == PIPE_B)
6075 vlv_pllb_recal_opamp(dev_priv, pipe);
6076
6077 /* Set up Tx target for periodic Rcomp update */
6078 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6079
6080 /* Disable target IRef on PLL */
6081 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6082 reg_val &= 0x00ffffff;
6083 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6084
6085 /* Disable fast lock */
6086 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6087
6088 /* Set idtafcrecal before PLL is enabled */
6089 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6090 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6091 mdiv |= ((bestn << DPIO_N_SHIFT));
6092 mdiv |= (1 << DPIO_K_SHIFT);
6093
6094 /*
6095 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6096 * but we don't support that).
6097 * Note: don't use the DAC post divider as it seems unstable.
6098 */
6099 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6100 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6101
6102 mdiv |= DPIO_ENABLE_CALIBRATION;
6103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6104
6105 /* Set HBR and RBR LPF coefficients */
6106 if (pipe_config->port_clock == 162000 ||
6107 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6108 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6109 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6110 0x009f0003);
6111 else
6112 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6113 0x00d0000f);
6114
6115 if (pipe_config->has_dp_encoder) {
6116 /* Use SSC source */
6117 if (pipe == PIPE_A)
6118 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6119 0x0df40000);
6120 else
6121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6122 0x0df70000);
6123 } else { /* HDMI or VGA */
6124 /* Use bend source */
6125 if (pipe == PIPE_A)
6126 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6127 0x0df70000);
6128 else
6129 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6130 0x0df40000);
6131 }
6132
6133 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6134 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6136 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6137 coreclk |= 0x01000000;
6138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6139
6140 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6141 mutex_unlock(&dev_priv->dpio_lock);
6142 }
6143
6144 static void chv_update_pll(struct intel_crtc *crtc,
6145 struct intel_crtc_state *pipe_config)
6146 {
6147 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6148 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6149 DPLL_VCO_ENABLE;
6150 if (crtc->pipe != PIPE_A)
6151 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6152
6153 pipe_config->dpll_hw_state.dpll_md =
6154 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6155 }
6156
6157 static void chv_prepare_pll(struct intel_crtc *crtc,
6158 const struct intel_crtc_state *pipe_config)
6159 {
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 int pipe = crtc->pipe;
6163 int dpll_reg = DPLL(crtc->pipe);
6164 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6165 u32 loopfilter, tribuf_calcntr;
6166 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6167 u32 dpio_val;
6168 int vco;
6169
6170 bestn = pipe_config->dpll.n;
6171 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6172 bestm1 = pipe_config->dpll.m1;
6173 bestm2 = pipe_config->dpll.m2 >> 22;
6174 bestp1 = pipe_config->dpll.p1;
6175 bestp2 = pipe_config->dpll.p2;
6176 vco = pipe_config->dpll.vco;
6177 dpio_val = 0;
6178 loopfilter = 0;
6179
6180 /*
6181 * Enable Refclk and SSC
6182 */
6183 I915_WRITE(dpll_reg,
6184 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6185
6186 mutex_lock(&dev_priv->dpio_lock);
6187
6188 /* p1 and p2 divider */
6189 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6190 5 << DPIO_CHV_S1_DIV_SHIFT |
6191 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6192 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6193 1 << DPIO_CHV_K_DIV_SHIFT);
6194
6195 /* Feedback post-divider - m2 */
6196 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6197
6198 /* Feedback refclk divider - n and m1 */
6199 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6200 DPIO_CHV_M1_DIV_BY_2 |
6201 1 << DPIO_CHV_N_DIV_SHIFT);
6202
6203 /* M2 fraction division */
6204 if (bestm2_frac)
6205 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6206
6207 /* M2 fraction division enable */
6208 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6209 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6210 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6211 if (bestm2_frac)
6212 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6213 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6214
6215 /* Program digital lock detect threshold */
6216 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6217 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6218 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6219 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6220 if (!bestm2_frac)
6221 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6222 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6223
6224 /* Loop filter */
6225 if (vco == 5400000) {
6226 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6227 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6228 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6229 tribuf_calcntr = 0x9;
6230 } else if (vco <= 6200000) {
6231 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6232 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6233 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6234 tribuf_calcntr = 0x9;
6235 } else if (vco <= 6480000) {
6236 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6237 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6238 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6239 tribuf_calcntr = 0x8;
6240 } else {
6241 /* Not supported. Apply the same limits as in the max case */
6242 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6243 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6244 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6245 tribuf_calcntr = 0;
6246 }
6247 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6248
6249 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6250 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6251 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6252 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6253
6254 /* AFC Recal */
6255 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6256 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6257 DPIO_AFC_RECAL);
6258
6259 mutex_unlock(&dev_priv->dpio_lock);
6260 }
6261
6262 /**
6263 * vlv_force_pll_on - forcibly enable just the PLL
6264 * @dev_priv: i915 private structure
6265 * @pipe: pipe PLL to enable
6266 * @dpll: PLL configuration
6267 *
6268 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6269 * in cases where we need the PLL enabled even when @pipe is not going to
6270 * be enabled.
6271 */
6272 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6273 const struct dpll *dpll)
6274 {
6275 struct intel_crtc *crtc =
6276 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6277 struct intel_crtc_state pipe_config = {
6278 .pixel_multiplier = 1,
6279 .dpll = *dpll,
6280 };
6281
6282 if (IS_CHERRYVIEW(dev)) {
6283 chv_update_pll(crtc, &pipe_config);
6284 chv_prepare_pll(crtc, &pipe_config);
6285 chv_enable_pll(crtc, &pipe_config);
6286 } else {
6287 vlv_update_pll(crtc, &pipe_config);
6288 vlv_prepare_pll(crtc, &pipe_config);
6289 vlv_enable_pll(crtc, &pipe_config);
6290 }
6291 }
6292
6293 /**
6294 * vlv_force_pll_off - forcibly disable just the PLL
6295 * @dev_priv: i915 private structure
6296 * @pipe: pipe PLL to disable
6297 *
6298 * Disable the PLL for @pipe. To be used in cases where we need
6299 * the PLL enabled even when @pipe is not going to be enabled.
6300 */
6301 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6302 {
6303 if (IS_CHERRYVIEW(dev))
6304 chv_disable_pll(to_i915(dev), pipe);
6305 else
6306 vlv_disable_pll(to_i915(dev), pipe);
6307 }
6308
6309 static void i9xx_update_pll(struct intel_crtc *crtc,
6310 struct intel_crtc_state *crtc_state,
6311 intel_clock_t *reduced_clock,
6312 int num_connectors)
6313 {
6314 struct drm_device *dev = crtc->base.dev;
6315 struct drm_i915_private *dev_priv = dev->dev_private;
6316 u32 dpll;
6317 bool is_sdvo;
6318 struct dpll *clock = &crtc_state->dpll;
6319
6320 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6321
6322 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6323 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6324
6325 dpll = DPLL_VGA_MODE_DIS;
6326
6327 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6328 dpll |= DPLLB_MODE_LVDS;
6329 else
6330 dpll |= DPLLB_MODE_DAC_SERIAL;
6331
6332 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6333 dpll |= (crtc_state->pixel_multiplier - 1)
6334 << SDVO_MULTIPLIER_SHIFT_HIRES;
6335 }
6336
6337 if (is_sdvo)
6338 dpll |= DPLL_SDVO_HIGH_SPEED;
6339
6340 if (crtc_state->has_dp_encoder)
6341 dpll |= DPLL_SDVO_HIGH_SPEED;
6342
6343 /* compute bitmask from p1 value */
6344 if (IS_PINEVIEW(dev))
6345 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6346 else {
6347 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6348 if (IS_G4X(dev) && reduced_clock)
6349 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6350 }
6351 switch (clock->p2) {
6352 case 5:
6353 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6354 break;
6355 case 7:
6356 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6357 break;
6358 case 10:
6359 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6360 break;
6361 case 14:
6362 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6363 break;
6364 }
6365 if (INTEL_INFO(dev)->gen >= 4)
6366 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6367
6368 if (crtc_state->sdvo_tv_clock)
6369 dpll |= PLL_REF_INPUT_TVCLKINBC;
6370 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6371 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6372 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6373 else
6374 dpll |= PLL_REF_INPUT_DREFCLK;
6375
6376 dpll |= DPLL_VCO_ENABLE;
6377 crtc_state->dpll_hw_state.dpll = dpll;
6378
6379 if (INTEL_INFO(dev)->gen >= 4) {
6380 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6381 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6382 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6383 }
6384 }
6385
6386 static void i8xx_update_pll(struct intel_crtc *crtc,
6387 struct intel_crtc_state *crtc_state,
6388 intel_clock_t *reduced_clock,
6389 int num_connectors)
6390 {
6391 struct drm_device *dev = crtc->base.dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 u32 dpll;
6394 struct dpll *clock = &crtc_state->dpll;
6395
6396 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6397
6398 dpll = DPLL_VGA_MODE_DIS;
6399
6400 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6401 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6402 } else {
6403 if (clock->p1 == 2)
6404 dpll |= PLL_P1_DIVIDE_BY_TWO;
6405 else
6406 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6407 if (clock->p2 == 4)
6408 dpll |= PLL_P2_DIVIDE_BY_4;
6409 }
6410
6411 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6412 dpll |= DPLL_DVO_2X_MODE;
6413
6414 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6415 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6416 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6417 else
6418 dpll |= PLL_REF_INPUT_DREFCLK;
6419
6420 dpll |= DPLL_VCO_ENABLE;
6421 crtc_state->dpll_hw_state.dpll = dpll;
6422 }
6423
6424 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6425 {
6426 struct drm_device *dev = intel_crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 enum pipe pipe = intel_crtc->pipe;
6429 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6430 struct drm_display_mode *adjusted_mode =
6431 &intel_crtc->config->base.adjusted_mode;
6432 uint32_t crtc_vtotal, crtc_vblank_end;
6433 int vsyncshift = 0;
6434
6435 /* We need to be careful not to changed the adjusted mode, for otherwise
6436 * the hw state checker will get angry at the mismatch. */
6437 crtc_vtotal = adjusted_mode->crtc_vtotal;
6438 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6439
6440 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6441 /* the chip adds 2 halflines automatically */
6442 crtc_vtotal -= 1;
6443 crtc_vblank_end -= 1;
6444
6445 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6446 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6447 else
6448 vsyncshift = adjusted_mode->crtc_hsync_start -
6449 adjusted_mode->crtc_htotal / 2;
6450 if (vsyncshift < 0)
6451 vsyncshift += adjusted_mode->crtc_htotal;
6452 }
6453
6454 if (INTEL_INFO(dev)->gen > 3)
6455 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6456
6457 I915_WRITE(HTOTAL(cpu_transcoder),
6458 (adjusted_mode->crtc_hdisplay - 1) |
6459 ((adjusted_mode->crtc_htotal - 1) << 16));
6460 I915_WRITE(HBLANK(cpu_transcoder),
6461 (adjusted_mode->crtc_hblank_start - 1) |
6462 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6463 I915_WRITE(HSYNC(cpu_transcoder),
6464 (adjusted_mode->crtc_hsync_start - 1) |
6465 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6466
6467 I915_WRITE(VTOTAL(cpu_transcoder),
6468 (adjusted_mode->crtc_vdisplay - 1) |
6469 ((crtc_vtotal - 1) << 16));
6470 I915_WRITE(VBLANK(cpu_transcoder),
6471 (adjusted_mode->crtc_vblank_start - 1) |
6472 ((crtc_vblank_end - 1) << 16));
6473 I915_WRITE(VSYNC(cpu_transcoder),
6474 (adjusted_mode->crtc_vsync_start - 1) |
6475 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6476
6477 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6478 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6479 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6480 * bits. */
6481 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6482 (pipe == PIPE_B || pipe == PIPE_C))
6483 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6484
6485 /* pipesrc controls the size that is scaled from, which should
6486 * always be the user's requested size.
6487 */
6488 I915_WRITE(PIPESRC(pipe),
6489 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6490 (intel_crtc->config->pipe_src_h - 1));
6491 }
6492
6493 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6494 struct intel_crtc_state *pipe_config)
6495 {
6496 struct drm_device *dev = crtc->base.dev;
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6499 uint32_t tmp;
6500
6501 tmp = I915_READ(HTOTAL(cpu_transcoder));
6502 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6503 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6504 tmp = I915_READ(HBLANK(cpu_transcoder));
6505 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6506 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6507 tmp = I915_READ(HSYNC(cpu_transcoder));
6508 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6509 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6510
6511 tmp = I915_READ(VTOTAL(cpu_transcoder));
6512 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6513 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6514 tmp = I915_READ(VBLANK(cpu_transcoder));
6515 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6516 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6517 tmp = I915_READ(VSYNC(cpu_transcoder));
6518 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6519 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6520
6521 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6522 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6523 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6524 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6525 }
6526
6527 tmp = I915_READ(PIPESRC(crtc->pipe));
6528 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6529 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6530
6531 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6532 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6533 }
6534
6535 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6536 struct intel_crtc_state *pipe_config)
6537 {
6538 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6539 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6540 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6541 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6542
6543 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6544 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6545 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6546 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6547
6548 mode->flags = pipe_config->base.adjusted_mode.flags;
6549
6550 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6551 mode->flags |= pipe_config->base.adjusted_mode.flags;
6552 }
6553
6554 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6555 {
6556 struct drm_device *dev = intel_crtc->base.dev;
6557 struct drm_i915_private *dev_priv = dev->dev_private;
6558 uint32_t pipeconf;
6559
6560 pipeconf = 0;
6561
6562 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6563 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6564 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6565
6566 if (intel_crtc->config->double_wide)
6567 pipeconf |= PIPECONF_DOUBLE_WIDE;
6568
6569 /* only g4x and later have fancy bpc/dither controls */
6570 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6571 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6572 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6573 pipeconf |= PIPECONF_DITHER_EN |
6574 PIPECONF_DITHER_TYPE_SP;
6575
6576 switch (intel_crtc->config->pipe_bpp) {
6577 case 18:
6578 pipeconf |= PIPECONF_6BPC;
6579 break;
6580 case 24:
6581 pipeconf |= PIPECONF_8BPC;
6582 break;
6583 case 30:
6584 pipeconf |= PIPECONF_10BPC;
6585 break;
6586 default:
6587 /* Case prevented by intel_choose_pipe_bpp_dither. */
6588 BUG();
6589 }
6590 }
6591
6592 if (HAS_PIPE_CXSR(dev)) {
6593 if (intel_crtc->lowfreq_avail) {
6594 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6595 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6596 } else {
6597 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6598 }
6599 }
6600
6601 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6602 if (INTEL_INFO(dev)->gen < 4 ||
6603 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6604 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6605 else
6606 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6607 } else
6608 pipeconf |= PIPECONF_PROGRESSIVE;
6609
6610 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6611 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6612
6613 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6614 POSTING_READ(PIPECONF(intel_crtc->pipe));
6615 }
6616
6617 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6618 struct intel_crtc_state *crtc_state)
6619 {
6620 struct drm_device *dev = crtc->base.dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
6622 int refclk, num_connectors = 0;
6623 intel_clock_t clock, reduced_clock;
6624 bool ok, has_reduced_clock = false;
6625 bool is_lvds = false, is_dsi = false;
6626 struct intel_encoder *encoder;
6627 const intel_limit_t *limit;
6628
6629 for_each_intel_encoder(dev, encoder) {
6630 if (encoder->new_crtc != crtc)
6631 continue;
6632
6633 switch (encoder->type) {
6634 case INTEL_OUTPUT_LVDS:
6635 is_lvds = true;
6636 break;
6637 case INTEL_OUTPUT_DSI:
6638 is_dsi = true;
6639 break;
6640 default:
6641 break;
6642 }
6643
6644 num_connectors++;
6645 }
6646
6647 if (is_dsi)
6648 return 0;
6649
6650 if (!crtc_state->clock_set) {
6651 refclk = i9xx_get_refclk(crtc, num_connectors);
6652
6653 /*
6654 * Returns a set of divisors for the desired target clock with
6655 * the given refclk, or FALSE. The returned values represent
6656 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6657 * 2) / p1 / p2.
6658 */
6659 limit = intel_limit(crtc, refclk);
6660 ok = dev_priv->display.find_dpll(limit, crtc,
6661 crtc_state->port_clock,
6662 refclk, NULL, &clock);
6663 if (!ok) {
6664 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6665 return -EINVAL;
6666 }
6667
6668 if (is_lvds && dev_priv->lvds_downclock_avail) {
6669 /*
6670 * Ensure we match the reduced clock's P to the target
6671 * clock. If the clocks don't match, we can't switch
6672 * the display clock by using the FP0/FP1. In such case
6673 * we will disable the LVDS downclock feature.
6674 */
6675 has_reduced_clock =
6676 dev_priv->display.find_dpll(limit, crtc,
6677 dev_priv->lvds_downclock,
6678 refclk, &clock,
6679 &reduced_clock);
6680 }
6681 /* Compat-code for transition, will disappear. */
6682 crtc_state->dpll.n = clock.n;
6683 crtc_state->dpll.m1 = clock.m1;
6684 crtc_state->dpll.m2 = clock.m2;
6685 crtc_state->dpll.p1 = clock.p1;
6686 crtc_state->dpll.p2 = clock.p2;
6687 }
6688
6689 if (IS_GEN2(dev)) {
6690 i8xx_update_pll(crtc, crtc_state,
6691 has_reduced_clock ? &reduced_clock : NULL,
6692 num_connectors);
6693 } else if (IS_CHERRYVIEW(dev)) {
6694 chv_update_pll(crtc, crtc_state);
6695 } else if (IS_VALLEYVIEW(dev)) {
6696 vlv_update_pll(crtc, crtc_state);
6697 } else {
6698 i9xx_update_pll(crtc, crtc_state,
6699 has_reduced_clock ? &reduced_clock : NULL,
6700 num_connectors);
6701 }
6702
6703 return 0;
6704 }
6705
6706 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6707 struct intel_crtc_state *pipe_config)
6708 {
6709 struct drm_device *dev = crtc->base.dev;
6710 struct drm_i915_private *dev_priv = dev->dev_private;
6711 uint32_t tmp;
6712
6713 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6714 return;
6715
6716 tmp = I915_READ(PFIT_CONTROL);
6717 if (!(tmp & PFIT_ENABLE))
6718 return;
6719
6720 /* Check whether the pfit is attached to our pipe. */
6721 if (INTEL_INFO(dev)->gen < 4) {
6722 if (crtc->pipe != PIPE_B)
6723 return;
6724 } else {
6725 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6726 return;
6727 }
6728
6729 pipe_config->gmch_pfit.control = tmp;
6730 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6731 if (INTEL_INFO(dev)->gen < 5)
6732 pipe_config->gmch_pfit.lvds_border_bits =
6733 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6734 }
6735
6736 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6737 struct intel_crtc_state *pipe_config)
6738 {
6739 struct drm_device *dev = crtc->base.dev;
6740 struct drm_i915_private *dev_priv = dev->dev_private;
6741 int pipe = pipe_config->cpu_transcoder;
6742 intel_clock_t clock;
6743 u32 mdiv;
6744 int refclk = 100000;
6745
6746 /* In case of MIPI DPLL will not even be used */
6747 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6748 return;
6749
6750 mutex_lock(&dev_priv->dpio_lock);
6751 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6752 mutex_unlock(&dev_priv->dpio_lock);
6753
6754 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6755 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6756 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6757 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6758 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6759
6760 vlv_clock(refclk, &clock);
6761
6762 /* clock.dot is the fast clock */
6763 pipe_config->port_clock = clock.dot / 5;
6764 }
6765
6766 static void
6767 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6768 struct intel_initial_plane_config *plane_config)
6769 {
6770 struct drm_device *dev = crtc->base.dev;
6771 struct drm_i915_private *dev_priv = dev->dev_private;
6772 u32 val, base, offset;
6773 int pipe = crtc->pipe, plane = crtc->plane;
6774 int fourcc, pixel_format;
6775 int aligned_height;
6776 struct drm_framebuffer *fb;
6777 struct intel_framebuffer *intel_fb;
6778
6779 val = I915_READ(DSPCNTR(plane));
6780 if (!(val & DISPLAY_PLANE_ENABLE))
6781 return;
6782
6783 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6784 if (!intel_fb) {
6785 DRM_DEBUG_KMS("failed to alloc fb\n");
6786 return;
6787 }
6788
6789 fb = &intel_fb->base;
6790
6791 if (INTEL_INFO(dev)->gen >= 4) {
6792 if (val & DISPPLANE_TILED) {
6793 plane_config->tiling = I915_TILING_X;
6794 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6795 }
6796 }
6797
6798 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6799 fourcc = i9xx_format_to_fourcc(pixel_format);
6800 fb->pixel_format = fourcc;
6801 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6802
6803 if (INTEL_INFO(dev)->gen >= 4) {
6804 if (plane_config->tiling)
6805 offset = I915_READ(DSPTILEOFF(plane));
6806 else
6807 offset = I915_READ(DSPLINOFF(plane));
6808 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6809 } else {
6810 base = I915_READ(DSPADDR(plane));
6811 }
6812 plane_config->base = base;
6813
6814 val = I915_READ(PIPESRC(pipe));
6815 fb->width = ((val >> 16) & 0xfff) + 1;
6816 fb->height = ((val >> 0) & 0xfff) + 1;
6817
6818 val = I915_READ(DSPSTRIDE(pipe));
6819 fb->pitches[0] = val & 0xffffffc0;
6820
6821 aligned_height = intel_fb_align_height(dev, fb->height,
6822 fb->pixel_format,
6823 fb->modifier[0]);
6824
6825 plane_config->size = fb->pitches[0] * aligned_height;
6826
6827 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6828 pipe_name(pipe), plane, fb->width, fb->height,
6829 fb->bits_per_pixel, base, fb->pitches[0],
6830 plane_config->size);
6831
6832 plane_config->fb = intel_fb;
6833 }
6834
6835 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6836 struct intel_crtc_state *pipe_config)
6837 {
6838 struct drm_device *dev = crtc->base.dev;
6839 struct drm_i915_private *dev_priv = dev->dev_private;
6840 int pipe = pipe_config->cpu_transcoder;
6841 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6842 intel_clock_t clock;
6843 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6844 int refclk = 100000;
6845
6846 mutex_lock(&dev_priv->dpio_lock);
6847 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6848 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6849 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6850 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6851 mutex_unlock(&dev_priv->dpio_lock);
6852
6853 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6854 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6855 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6856 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6857 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6858
6859 chv_clock(refclk, &clock);
6860
6861 /* clock.dot is the fast clock */
6862 pipe_config->port_clock = clock.dot / 5;
6863 }
6864
6865 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6866 struct intel_crtc_state *pipe_config)
6867 {
6868 struct drm_device *dev = crtc->base.dev;
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 uint32_t tmp;
6871
6872 if (!intel_display_power_is_enabled(dev_priv,
6873 POWER_DOMAIN_PIPE(crtc->pipe)))
6874 return false;
6875
6876 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6877 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6878
6879 tmp = I915_READ(PIPECONF(crtc->pipe));
6880 if (!(tmp & PIPECONF_ENABLE))
6881 return false;
6882
6883 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6884 switch (tmp & PIPECONF_BPC_MASK) {
6885 case PIPECONF_6BPC:
6886 pipe_config->pipe_bpp = 18;
6887 break;
6888 case PIPECONF_8BPC:
6889 pipe_config->pipe_bpp = 24;
6890 break;
6891 case PIPECONF_10BPC:
6892 pipe_config->pipe_bpp = 30;
6893 break;
6894 default:
6895 break;
6896 }
6897 }
6898
6899 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6900 pipe_config->limited_color_range = true;
6901
6902 if (INTEL_INFO(dev)->gen < 4)
6903 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6904
6905 intel_get_pipe_timings(crtc, pipe_config);
6906
6907 i9xx_get_pfit_config(crtc, pipe_config);
6908
6909 if (INTEL_INFO(dev)->gen >= 4) {
6910 tmp = I915_READ(DPLL_MD(crtc->pipe));
6911 pipe_config->pixel_multiplier =
6912 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6913 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6914 pipe_config->dpll_hw_state.dpll_md = tmp;
6915 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6916 tmp = I915_READ(DPLL(crtc->pipe));
6917 pipe_config->pixel_multiplier =
6918 ((tmp & SDVO_MULTIPLIER_MASK)
6919 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6920 } else {
6921 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6922 * port and will be fixed up in the encoder->get_config
6923 * function. */
6924 pipe_config->pixel_multiplier = 1;
6925 }
6926 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6927 if (!IS_VALLEYVIEW(dev)) {
6928 /*
6929 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6930 * on 830. Filter it out here so that we don't
6931 * report errors due to that.
6932 */
6933 if (IS_I830(dev))
6934 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6935
6936 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6937 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6938 } else {
6939 /* Mask out read-only status bits. */
6940 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6941 DPLL_PORTC_READY_MASK |
6942 DPLL_PORTB_READY_MASK);
6943 }
6944
6945 if (IS_CHERRYVIEW(dev))
6946 chv_crtc_clock_get(crtc, pipe_config);
6947 else if (IS_VALLEYVIEW(dev))
6948 vlv_crtc_clock_get(crtc, pipe_config);
6949 else
6950 i9xx_crtc_clock_get(crtc, pipe_config);
6951
6952 return true;
6953 }
6954
6955 static void ironlake_init_pch_refclk(struct drm_device *dev)
6956 {
6957 struct drm_i915_private *dev_priv = dev->dev_private;
6958 struct intel_encoder *encoder;
6959 u32 val, final;
6960 bool has_lvds = false;
6961 bool has_cpu_edp = false;
6962 bool has_panel = false;
6963 bool has_ck505 = false;
6964 bool can_ssc = false;
6965
6966 /* We need to take the global config into account */
6967 for_each_intel_encoder(dev, encoder) {
6968 switch (encoder->type) {
6969 case INTEL_OUTPUT_LVDS:
6970 has_panel = true;
6971 has_lvds = true;
6972 break;
6973 case INTEL_OUTPUT_EDP:
6974 has_panel = true;
6975 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6976 has_cpu_edp = true;
6977 break;
6978 default:
6979 break;
6980 }
6981 }
6982
6983 if (HAS_PCH_IBX(dev)) {
6984 has_ck505 = dev_priv->vbt.display_clock_mode;
6985 can_ssc = has_ck505;
6986 } else {
6987 has_ck505 = false;
6988 can_ssc = true;
6989 }
6990
6991 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6992 has_panel, has_lvds, has_ck505);
6993
6994 /* Ironlake: try to setup display ref clock before DPLL
6995 * enabling. This is only under driver's control after
6996 * PCH B stepping, previous chipset stepping should be
6997 * ignoring this setting.
6998 */
6999 val = I915_READ(PCH_DREF_CONTROL);
7000
7001 /* As we must carefully and slowly disable/enable each source in turn,
7002 * compute the final state we want first and check if we need to
7003 * make any changes at all.
7004 */
7005 final = val;
7006 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7007 if (has_ck505)
7008 final |= DREF_NONSPREAD_CK505_ENABLE;
7009 else
7010 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7011
7012 final &= ~DREF_SSC_SOURCE_MASK;
7013 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7014 final &= ~DREF_SSC1_ENABLE;
7015
7016 if (has_panel) {
7017 final |= DREF_SSC_SOURCE_ENABLE;
7018
7019 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7020 final |= DREF_SSC1_ENABLE;
7021
7022 if (has_cpu_edp) {
7023 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7024 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7025 else
7026 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7027 } else
7028 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7029 } else {
7030 final |= DREF_SSC_SOURCE_DISABLE;
7031 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7032 }
7033
7034 if (final == val)
7035 return;
7036
7037 /* Always enable nonspread source */
7038 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7039
7040 if (has_ck505)
7041 val |= DREF_NONSPREAD_CK505_ENABLE;
7042 else
7043 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7044
7045 if (has_panel) {
7046 val &= ~DREF_SSC_SOURCE_MASK;
7047 val |= DREF_SSC_SOURCE_ENABLE;
7048
7049 /* SSC must be turned on before enabling the CPU output */
7050 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7051 DRM_DEBUG_KMS("Using SSC on panel\n");
7052 val |= DREF_SSC1_ENABLE;
7053 } else
7054 val &= ~DREF_SSC1_ENABLE;
7055
7056 /* Get SSC going before enabling the outputs */
7057 I915_WRITE(PCH_DREF_CONTROL, val);
7058 POSTING_READ(PCH_DREF_CONTROL);
7059 udelay(200);
7060
7061 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7062
7063 /* Enable CPU source on CPU attached eDP */
7064 if (has_cpu_edp) {
7065 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7066 DRM_DEBUG_KMS("Using SSC on eDP\n");
7067 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7068 } else
7069 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7070 } else
7071 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7072
7073 I915_WRITE(PCH_DREF_CONTROL, val);
7074 POSTING_READ(PCH_DREF_CONTROL);
7075 udelay(200);
7076 } else {
7077 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7078
7079 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7080
7081 /* Turn off CPU output */
7082 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7083
7084 I915_WRITE(PCH_DREF_CONTROL, val);
7085 POSTING_READ(PCH_DREF_CONTROL);
7086 udelay(200);
7087
7088 /* Turn off the SSC source */
7089 val &= ~DREF_SSC_SOURCE_MASK;
7090 val |= DREF_SSC_SOURCE_DISABLE;
7091
7092 /* Turn off SSC1 */
7093 val &= ~DREF_SSC1_ENABLE;
7094
7095 I915_WRITE(PCH_DREF_CONTROL, val);
7096 POSTING_READ(PCH_DREF_CONTROL);
7097 udelay(200);
7098 }
7099
7100 BUG_ON(val != final);
7101 }
7102
7103 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7104 {
7105 uint32_t tmp;
7106
7107 tmp = I915_READ(SOUTH_CHICKEN2);
7108 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7109 I915_WRITE(SOUTH_CHICKEN2, tmp);
7110
7111 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7112 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7113 DRM_ERROR("FDI mPHY reset assert timeout\n");
7114
7115 tmp = I915_READ(SOUTH_CHICKEN2);
7116 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7117 I915_WRITE(SOUTH_CHICKEN2, tmp);
7118
7119 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7120 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7121 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7122 }
7123
7124 /* WaMPhyProgramming:hsw */
7125 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7126 {
7127 uint32_t tmp;
7128
7129 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7130 tmp &= ~(0xFF << 24);
7131 tmp |= (0x12 << 24);
7132 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7133
7134 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7135 tmp |= (1 << 11);
7136 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7137
7138 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7139 tmp |= (1 << 11);
7140 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7141
7142 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7143 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7144 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7145
7146 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7147 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7148 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7149
7150 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7151 tmp &= ~(7 << 13);
7152 tmp |= (5 << 13);
7153 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7154
7155 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7156 tmp &= ~(7 << 13);
7157 tmp |= (5 << 13);
7158 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7159
7160 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7161 tmp &= ~0xFF;
7162 tmp |= 0x1C;
7163 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7164
7165 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7166 tmp &= ~0xFF;
7167 tmp |= 0x1C;
7168 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7169
7170 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7171 tmp &= ~(0xFF << 16);
7172 tmp |= (0x1C << 16);
7173 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7174
7175 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7176 tmp &= ~(0xFF << 16);
7177 tmp |= (0x1C << 16);
7178 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7179
7180 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7181 tmp |= (1 << 27);
7182 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7183
7184 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7185 tmp |= (1 << 27);
7186 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7187
7188 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7189 tmp &= ~(0xF << 28);
7190 tmp |= (4 << 28);
7191 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7192
7193 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7194 tmp &= ~(0xF << 28);
7195 tmp |= (4 << 28);
7196 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7197 }
7198
7199 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7200 * Programming" based on the parameters passed:
7201 * - Sequence to enable CLKOUT_DP
7202 * - Sequence to enable CLKOUT_DP without spread
7203 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7204 */
7205 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7206 bool with_fdi)
7207 {
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 uint32_t reg, tmp;
7210
7211 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7212 with_spread = true;
7213 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7214 with_fdi, "LP PCH doesn't have FDI\n"))
7215 with_fdi = false;
7216
7217 mutex_lock(&dev_priv->dpio_lock);
7218
7219 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7220 tmp &= ~SBI_SSCCTL_DISABLE;
7221 tmp |= SBI_SSCCTL_PATHALT;
7222 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7223
7224 udelay(24);
7225
7226 if (with_spread) {
7227 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7228 tmp &= ~SBI_SSCCTL_PATHALT;
7229 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7230
7231 if (with_fdi) {
7232 lpt_reset_fdi_mphy(dev_priv);
7233 lpt_program_fdi_mphy(dev_priv);
7234 }
7235 }
7236
7237 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7238 SBI_GEN0 : SBI_DBUFF0;
7239 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7240 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7241 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7242
7243 mutex_unlock(&dev_priv->dpio_lock);
7244 }
7245
7246 /* Sequence to disable CLKOUT_DP */
7247 static void lpt_disable_clkout_dp(struct drm_device *dev)
7248 {
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 uint32_t reg, tmp;
7251
7252 mutex_lock(&dev_priv->dpio_lock);
7253
7254 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7255 SBI_GEN0 : SBI_DBUFF0;
7256 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7257 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7258 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7259
7260 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7261 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7262 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7263 tmp |= SBI_SSCCTL_PATHALT;
7264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7265 udelay(32);
7266 }
7267 tmp |= SBI_SSCCTL_DISABLE;
7268 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7269 }
7270
7271 mutex_unlock(&dev_priv->dpio_lock);
7272 }
7273
7274 static void lpt_init_pch_refclk(struct drm_device *dev)
7275 {
7276 struct intel_encoder *encoder;
7277 bool has_vga = false;
7278
7279 for_each_intel_encoder(dev, encoder) {
7280 switch (encoder->type) {
7281 case INTEL_OUTPUT_ANALOG:
7282 has_vga = true;
7283 break;
7284 default:
7285 break;
7286 }
7287 }
7288
7289 if (has_vga)
7290 lpt_enable_clkout_dp(dev, true, true);
7291 else
7292 lpt_disable_clkout_dp(dev);
7293 }
7294
7295 /*
7296 * Initialize reference clocks when the driver loads
7297 */
7298 void intel_init_pch_refclk(struct drm_device *dev)
7299 {
7300 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7301 ironlake_init_pch_refclk(dev);
7302 else if (HAS_PCH_LPT(dev))
7303 lpt_init_pch_refclk(dev);
7304 }
7305
7306 static int ironlake_get_refclk(struct drm_crtc *crtc)
7307 {
7308 struct drm_device *dev = crtc->dev;
7309 struct drm_i915_private *dev_priv = dev->dev_private;
7310 struct intel_encoder *encoder;
7311 int num_connectors = 0;
7312 bool is_lvds = false;
7313
7314 for_each_intel_encoder(dev, encoder) {
7315 if (encoder->new_crtc != to_intel_crtc(crtc))
7316 continue;
7317
7318 switch (encoder->type) {
7319 case INTEL_OUTPUT_LVDS:
7320 is_lvds = true;
7321 break;
7322 default:
7323 break;
7324 }
7325 num_connectors++;
7326 }
7327
7328 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7329 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7330 dev_priv->vbt.lvds_ssc_freq);
7331 return dev_priv->vbt.lvds_ssc_freq;
7332 }
7333
7334 return 120000;
7335 }
7336
7337 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7338 {
7339 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7341 int pipe = intel_crtc->pipe;
7342 uint32_t val;
7343
7344 val = 0;
7345
7346 switch (intel_crtc->config->pipe_bpp) {
7347 case 18:
7348 val |= PIPECONF_6BPC;
7349 break;
7350 case 24:
7351 val |= PIPECONF_8BPC;
7352 break;
7353 case 30:
7354 val |= PIPECONF_10BPC;
7355 break;
7356 case 36:
7357 val |= PIPECONF_12BPC;
7358 break;
7359 default:
7360 /* Case prevented by intel_choose_pipe_bpp_dither. */
7361 BUG();
7362 }
7363
7364 if (intel_crtc->config->dither)
7365 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7366
7367 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7368 val |= PIPECONF_INTERLACED_ILK;
7369 else
7370 val |= PIPECONF_PROGRESSIVE;
7371
7372 if (intel_crtc->config->limited_color_range)
7373 val |= PIPECONF_COLOR_RANGE_SELECT;
7374
7375 I915_WRITE(PIPECONF(pipe), val);
7376 POSTING_READ(PIPECONF(pipe));
7377 }
7378
7379 /*
7380 * Set up the pipe CSC unit.
7381 *
7382 * Currently only full range RGB to limited range RGB conversion
7383 * is supported, but eventually this should handle various
7384 * RGB<->YCbCr scenarios as well.
7385 */
7386 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7387 {
7388 struct drm_device *dev = crtc->dev;
7389 struct drm_i915_private *dev_priv = dev->dev_private;
7390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7391 int pipe = intel_crtc->pipe;
7392 uint16_t coeff = 0x7800; /* 1.0 */
7393
7394 /*
7395 * TODO: Check what kind of values actually come out of the pipe
7396 * with these coeff/postoff values and adjust to get the best
7397 * accuracy. Perhaps we even need to take the bpc value into
7398 * consideration.
7399 */
7400
7401 if (intel_crtc->config->limited_color_range)
7402 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7403
7404 /*
7405 * GY/GU and RY/RU should be the other way around according
7406 * to BSpec, but reality doesn't agree. Just set them up in
7407 * a way that results in the correct picture.
7408 */
7409 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7410 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7411
7412 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7413 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7414
7415 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7416 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7417
7418 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7419 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7420 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7421
7422 if (INTEL_INFO(dev)->gen > 6) {
7423 uint16_t postoff = 0;
7424
7425 if (intel_crtc->config->limited_color_range)
7426 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7427
7428 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7429 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7430 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7431
7432 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7433 } else {
7434 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7435
7436 if (intel_crtc->config->limited_color_range)
7437 mode |= CSC_BLACK_SCREEN_OFFSET;
7438
7439 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7440 }
7441 }
7442
7443 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7444 {
7445 struct drm_device *dev = crtc->dev;
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7448 enum pipe pipe = intel_crtc->pipe;
7449 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7450 uint32_t val;
7451
7452 val = 0;
7453
7454 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7455 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7456
7457 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7458 val |= PIPECONF_INTERLACED_ILK;
7459 else
7460 val |= PIPECONF_PROGRESSIVE;
7461
7462 I915_WRITE(PIPECONF(cpu_transcoder), val);
7463 POSTING_READ(PIPECONF(cpu_transcoder));
7464
7465 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7466 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7467
7468 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7469 val = 0;
7470
7471 switch (intel_crtc->config->pipe_bpp) {
7472 case 18:
7473 val |= PIPEMISC_DITHER_6_BPC;
7474 break;
7475 case 24:
7476 val |= PIPEMISC_DITHER_8_BPC;
7477 break;
7478 case 30:
7479 val |= PIPEMISC_DITHER_10_BPC;
7480 break;
7481 case 36:
7482 val |= PIPEMISC_DITHER_12_BPC;
7483 break;
7484 default:
7485 /* Case prevented by pipe_config_set_bpp. */
7486 BUG();
7487 }
7488
7489 if (intel_crtc->config->dither)
7490 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7491
7492 I915_WRITE(PIPEMISC(pipe), val);
7493 }
7494 }
7495
7496 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7497 struct intel_crtc_state *crtc_state,
7498 intel_clock_t *clock,
7499 bool *has_reduced_clock,
7500 intel_clock_t *reduced_clock)
7501 {
7502 struct drm_device *dev = crtc->dev;
7503 struct drm_i915_private *dev_priv = dev->dev_private;
7504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7505 int refclk;
7506 const intel_limit_t *limit;
7507 bool ret, is_lvds = false;
7508
7509 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7510
7511 refclk = ironlake_get_refclk(crtc);
7512
7513 /*
7514 * Returns a set of divisors for the desired target clock with the given
7515 * refclk, or FALSE. The returned values represent the clock equation:
7516 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7517 */
7518 limit = intel_limit(intel_crtc, refclk);
7519 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7520 crtc_state->port_clock,
7521 refclk, NULL, clock);
7522 if (!ret)
7523 return false;
7524
7525 if (is_lvds && dev_priv->lvds_downclock_avail) {
7526 /*
7527 * Ensure we match the reduced clock's P to the target clock.
7528 * If the clocks don't match, we can't switch the display clock
7529 * by using the FP0/FP1. In such case we will disable the LVDS
7530 * downclock feature.
7531 */
7532 *has_reduced_clock =
7533 dev_priv->display.find_dpll(limit, intel_crtc,
7534 dev_priv->lvds_downclock,
7535 refclk, clock,
7536 reduced_clock);
7537 }
7538
7539 return true;
7540 }
7541
7542 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7543 {
7544 /*
7545 * Account for spread spectrum to avoid
7546 * oversubscribing the link. Max center spread
7547 * is 2.5%; use 5% for safety's sake.
7548 */
7549 u32 bps = target_clock * bpp * 21 / 20;
7550 return DIV_ROUND_UP(bps, link_bw * 8);
7551 }
7552
7553 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7554 {
7555 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7556 }
7557
7558 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7559 struct intel_crtc_state *crtc_state,
7560 u32 *fp,
7561 intel_clock_t *reduced_clock, u32 *fp2)
7562 {
7563 struct drm_crtc *crtc = &intel_crtc->base;
7564 struct drm_device *dev = crtc->dev;
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7566 struct intel_encoder *intel_encoder;
7567 uint32_t dpll;
7568 int factor, num_connectors = 0;
7569 bool is_lvds = false, is_sdvo = false;
7570
7571 for_each_intel_encoder(dev, intel_encoder) {
7572 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7573 continue;
7574
7575 switch (intel_encoder->type) {
7576 case INTEL_OUTPUT_LVDS:
7577 is_lvds = true;
7578 break;
7579 case INTEL_OUTPUT_SDVO:
7580 case INTEL_OUTPUT_HDMI:
7581 is_sdvo = true;
7582 break;
7583 default:
7584 break;
7585 }
7586
7587 num_connectors++;
7588 }
7589
7590 /* Enable autotuning of the PLL clock (if permissible) */
7591 factor = 21;
7592 if (is_lvds) {
7593 if ((intel_panel_use_ssc(dev_priv) &&
7594 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7595 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7596 factor = 25;
7597 } else if (crtc_state->sdvo_tv_clock)
7598 factor = 20;
7599
7600 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7601 *fp |= FP_CB_TUNE;
7602
7603 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7604 *fp2 |= FP_CB_TUNE;
7605
7606 dpll = 0;
7607
7608 if (is_lvds)
7609 dpll |= DPLLB_MODE_LVDS;
7610 else
7611 dpll |= DPLLB_MODE_DAC_SERIAL;
7612
7613 dpll |= (crtc_state->pixel_multiplier - 1)
7614 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7615
7616 if (is_sdvo)
7617 dpll |= DPLL_SDVO_HIGH_SPEED;
7618 if (crtc_state->has_dp_encoder)
7619 dpll |= DPLL_SDVO_HIGH_SPEED;
7620
7621 /* compute bitmask from p1 value */
7622 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7623 /* also FPA1 */
7624 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7625
7626 switch (crtc_state->dpll.p2) {
7627 case 5:
7628 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7629 break;
7630 case 7:
7631 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7632 break;
7633 case 10:
7634 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7635 break;
7636 case 14:
7637 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7638 break;
7639 }
7640
7641 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7642 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7643 else
7644 dpll |= PLL_REF_INPUT_DREFCLK;
7645
7646 return dpll | DPLL_VCO_ENABLE;
7647 }
7648
7649 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state)
7651 {
7652 struct drm_device *dev = crtc->base.dev;
7653 intel_clock_t clock, reduced_clock;
7654 u32 dpll = 0, fp = 0, fp2 = 0;
7655 bool ok, has_reduced_clock = false;
7656 bool is_lvds = false;
7657 struct intel_shared_dpll *pll;
7658
7659 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7660
7661 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7662 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7663
7664 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7665 &has_reduced_clock, &reduced_clock);
7666 if (!ok && !crtc_state->clock_set) {
7667 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7668 return -EINVAL;
7669 }
7670 /* Compat-code for transition, will disappear. */
7671 if (!crtc_state->clock_set) {
7672 crtc_state->dpll.n = clock.n;
7673 crtc_state->dpll.m1 = clock.m1;
7674 crtc_state->dpll.m2 = clock.m2;
7675 crtc_state->dpll.p1 = clock.p1;
7676 crtc_state->dpll.p2 = clock.p2;
7677 }
7678
7679 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7680 if (crtc_state->has_pch_encoder) {
7681 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7682 if (has_reduced_clock)
7683 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7684
7685 dpll = ironlake_compute_dpll(crtc, crtc_state,
7686 &fp, &reduced_clock,
7687 has_reduced_clock ? &fp2 : NULL);
7688
7689 crtc_state->dpll_hw_state.dpll = dpll;
7690 crtc_state->dpll_hw_state.fp0 = fp;
7691 if (has_reduced_clock)
7692 crtc_state->dpll_hw_state.fp1 = fp2;
7693 else
7694 crtc_state->dpll_hw_state.fp1 = fp;
7695
7696 pll = intel_get_shared_dpll(crtc, crtc_state);
7697 if (pll == NULL) {
7698 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7699 pipe_name(crtc->pipe));
7700 return -EINVAL;
7701 }
7702 }
7703
7704 if (is_lvds && has_reduced_clock && i915.powersave)
7705 crtc->lowfreq_avail = true;
7706 else
7707 crtc->lowfreq_avail = false;
7708
7709 return 0;
7710 }
7711
7712 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7713 struct intel_link_m_n *m_n)
7714 {
7715 struct drm_device *dev = crtc->base.dev;
7716 struct drm_i915_private *dev_priv = dev->dev_private;
7717 enum pipe pipe = crtc->pipe;
7718
7719 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7720 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7721 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7722 & ~TU_SIZE_MASK;
7723 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7724 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7725 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7726 }
7727
7728 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7729 enum transcoder transcoder,
7730 struct intel_link_m_n *m_n,
7731 struct intel_link_m_n *m2_n2)
7732 {
7733 struct drm_device *dev = crtc->base.dev;
7734 struct drm_i915_private *dev_priv = dev->dev_private;
7735 enum pipe pipe = crtc->pipe;
7736
7737 if (INTEL_INFO(dev)->gen >= 5) {
7738 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7739 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7740 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7741 & ~TU_SIZE_MASK;
7742 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7743 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7744 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7745 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7746 * gen < 8) and if DRRS is supported (to make sure the
7747 * registers are not unnecessarily read).
7748 */
7749 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7750 crtc->config->has_drrs) {
7751 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7752 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7753 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7754 & ~TU_SIZE_MASK;
7755 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7756 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7757 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7758 }
7759 } else {
7760 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7761 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7762 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7763 & ~TU_SIZE_MASK;
7764 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7765 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7766 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7767 }
7768 }
7769
7770 void intel_dp_get_m_n(struct intel_crtc *crtc,
7771 struct intel_crtc_state *pipe_config)
7772 {
7773 if (pipe_config->has_pch_encoder)
7774 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7775 else
7776 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7777 &pipe_config->dp_m_n,
7778 &pipe_config->dp_m2_n2);
7779 }
7780
7781 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7782 struct intel_crtc_state *pipe_config)
7783 {
7784 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7785 &pipe_config->fdi_m_n, NULL);
7786 }
7787
7788 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7789 struct intel_crtc_state *pipe_config)
7790 {
7791 struct drm_device *dev = crtc->base.dev;
7792 struct drm_i915_private *dev_priv = dev->dev_private;
7793 uint32_t tmp;
7794
7795 tmp = I915_READ(PS_CTL(crtc->pipe));
7796
7797 if (tmp & PS_ENABLE) {
7798 pipe_config->pch_pfit.enabled = true;
7799 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7800 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7801 }
7802 }
7803
7804 static void
7805 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7806 struct intel_initial_plane_config *plane_config)
7807 {
7808 struct drm_device *dev = crtc->base.dev;
7809 struct drm_i915_private *dev_priv = dev->dev_private;
7810 u32 val, base, offset, stride_mult, tiling;
7811 int pipe = crtc->pipe;
7812 int fourcc, pixel_format;
7813 int aligned_height;
7814 struct drm_framebuffer *fb;
7815 struct intel_framebuffer *intel_fb;
7816
7817 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7818 if (!intel_fb) {
7819 DRM_DEBUG_KMS("failed to alloc fb\n");
7820 return;
7821 }
7822
7823 fb = &intel_fb->base;
7824
7825 val = I915_READ(PLANE_CTL(pipe, 0));
7826 if (!(val & PLANE_CTL_ENABLE))
7827 goto error;
7828
7829 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7830 fourcc = skl_format_to_fourcc(pixel_format,
7831 val & PLANE_CTL_ORDER_RGBX,
7832 val & PLANE_CTL_ALPHA_MASK);
7833 fb->pixel_format = fourcc;
7834 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7835
7836 tiling = val & PLANE_CTL_TILED_MASK;
7837 switch (tiling) {
7838 case PLANE_CTL_TILED_LINEAR:
7839 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7840 break;
7841 case PLANE_CTL_TILED_X:
7842 plane_config->tiling = I915_TILING_X;
7843 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7844 break;
7845 case PLANE_CTL_TILED_Y:
7846 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7847 break;
7848 case PLANE_CTL_TILED_YF:
7849 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7850 break;
7851 default:
7852 MISSING_CASE(tiling);
7853 goto error;
7854 }
7855
7856 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7857 plane_config->base = base;
7858
7859 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7860
7861 val = I915_READ(PLANE_SIZE(pipe, 0));
7862 fb->height = ((val >> 16) & 0xfff) + 1;
7863 fb->width = ((val >> 0) & 0x1fff) + 1;
7864
7865 val = I915_READ(PLANE_STRIDE(pipe, 0));
7866 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7867 fb->pixel_format);
7868 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7869
7870 aligned_height = intel_fb_align_height(dev, fb->height,
7871 fb->pixel_format,
7872 fb->modifier[0]);
7873
7874 plane_config->size = fb->pitches[0] * aligned_height;
7875
7876 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7877 pipe_name(pipe), fb->width, fb->height,
7878 fb->bits_per_pixel, base, fb->pitches[0],
7879 plane_config->size);
7880
7881 plane_config->fb = intel_fb;
7882 return;
7883
7884 error:
7885 kfree(fb);
7886 }
7887
7888 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7889 struct intel_crtc_state *pipe_config)
7890 {
7891 struct drm_device *dev = crtc->base.dev;
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7893 uint32_t tmp;
7894
7895 tmp = I915_READ(PF_CTL(crtc->pipe));
7896
7897 if (tmp & PF_ENABLE) {
7898 pipe_config->pch_pfit.enabled = true;
7899 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7900 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7901
7902 /* We currently do not free assignements of panel fitters on
7903 * ivb/hsw (since we don't use the higher upscaling modes which
7904 * differentiates them) so just WARN about this case for now. */
7905 if (IS_GEN7(dev)) {
7906 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7907 PF_PIPE_SEL_IVB(crtc->pipe));
7908 }
7909 }
7910 }
7911
7912 static void
7913 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7914 struct intel_initial_plane_config *plane_config)
7915 {
7916 struct drm_device *dev = crtc->base.dev;
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 u32 val, base, offset;
7919 int pipe = crtc->pipe;
7920 int fourcc, pixel_format;
7921 int aligned_height;
7922 struct drm_framebuffer *fb;
7923 struct intel_framebuffer *intel_fb;
7924
7925 val = I915_READ(DSPCNTR(pipe));
7926 if (!(val & DISPLAY_PLANE_ENABLE))
7927 return;
7928
7929 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7930 if (!intel_fb) {
7931 DRM_DEBUG_KMS("failed to alloc fb\n");
7932 return;
7933 }
7934
7935 fb = &intel_fb->base;
7936
7937 if (INTEL_INFO(dev)->gen >= 4) {
7938 if (val & DISPPLANE_TILED) {
7939 plane_config->tiling = I915_TILING_X;
7940 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7941 }
7942 }
7943
7944 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7945 fourcc = i9xx_format_to_fourcc(pixel_format);
7946 fb->pixel_format = fourcc;
7947 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7948
7949 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7950 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7951 offset = I915_READ(DSPOFFSET(pipe));
7952 } else {
7953 if (plane_config->tiling)
7954 offset = I915_READ(DSPTILEOFF(pipe));
7955 else
7956 offset = I915_READ(DSPLINOFF(pipe));
7957 }
7958 plane_config->base = base;
7959
7960 val = I915_READ(PIPESRC(pipe));
7961 fb->width = ((val >> 16) & 0xfff) + 1;
7962 fb->height = ((val >> 0) & 0xfff) + 1;
7963
7964 val = I915_READ(DSPSTRIDE(pipe));
7965 fb->pitches[0] = val & 0xffffffc0;
7966
7967 aligned_height = intel_fb_align_height(dev, fb->height,
7968 fb->pixel_format,
7969 fb->modifier[0]);
7970
7971 plane_config->size = fb->pitches[0] * aligned_height;
7972
7973 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7974 pipe_name(pipe), fb->width, fb->height,
7975 fb->bits_per_pixel, base, fb->pitches[0],
7976 plane_config->size);
7977
7978 plane_config->fb = intel_fb;
7979 }
7980
7981 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7982 struct intel_crtc_state *pipe_config)
7983 {
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 uint32_t tmp;
7987
7988 if (!intel_display_power_is_enabled(dev_priv,
7989 POWER_DOMAIN_PIPE(crtc->pipe)))
7990 return false;
7991
7992 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7993 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7994
7995 tmp = I915_READ(PIPECONF(crtc->pipe));
7996 if (!(tmp & PIPECONF_ENABLE))
7997 return false;
7998
7999 switch (tmp & PIPECONF_BPC_MASK) {
8000 case PIPECONF_6BPC:
8001 pipe_config->pipe_bpp = 18;
8002 break;
8003 case PIPECONF_8BPC:
8004 pipe_config->pipe_bpp = 24;
8005 break;
8006 case PIPECONF_10BPC:
8007 pipe_config->pipe_bpp = 30;
8008 break;
8009 case PIPECONF_12BPC:
8010 pipe_config->pipe_bpp = 36;
8011 break;
8012 default:
8013 break;
8014 }
8015
8016 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8017 pipe_config->limited_color_range = true;
8018
8019 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8020 struct intel_shared_dpll *pll;
8021
8022 pipe_config->has_pch_encoder = true;
8023
8024 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8025 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8026 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8027
8028 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8029
8030 if (HAS_PCH_IBX(dev_priv->dev)) {
8031 pipe_config->shared_dpll =
8032 (enum intel_dpll_id) crtc->pipe;
8033 } else {
8034 tmp = I915_READ(PCH_DPLL_SEL);
8035 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8036 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8037 else
8038 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8039 }
8040
8041 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8042
8043 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8044 &pipe_config->dpll_hw_state));
8045
8046 tmp = pipe_config->dpll_hw_state.dpll;
8047 pipe_config->pixel_multiplier =
8048 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8049 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8050
8051 ironlake_pch_clock_get(crtc, pipe_config);
8052 } else {
8053 pipe_config->pixel_multiplier = 1;
8054 }
8055
8056 intel_get_pipe_timings(crtc, pipe_config);
8057
8058 ironlake_get_pfit_config(crtc, pipe_config);
8059
8060 return true;
8061 }
8062
8063 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8064 {
8065 struct drm_device *dev = dev_priv->dev;
8066 struct intel_crtc *crtc;
8067
8068 for_each_intel_crtc(dev, crtc)
8069 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8070 pipe_name(crtc->pipe));
8071
8072 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8073 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8074 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8075 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8076 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8077 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8078 "CPU PWM1 enabled\n");
8079 if (IS_HASWELL(dev))
8080 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8081 "CPU PWM2 enabled\n");
8082 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8083 "PCH PWM1 enabled\n");
8084 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8085 "Utility pin enabled\n");
8086 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8087
8088 /*
8089 * In theory we can still leave IRQs enabled, as long as only the HPD
8090 * interrupts remain enabled. We used to check for that, but since it's
8091 * gen-specific and since we only disable LCPLL after we fully disable
8092 * the interrupts, the check below should be enough.
8093 */
8094 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8095 }
8096
8097 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8098 {
8099 struct drm_device *dev = dev_priv->dev;
8100
8101 if (IS_HASWELL(dev))
8102 return I915_READ(D_COMP_HSW);
8103 else
8104 return I915_READ(D_COMP_BDW);
8105 }
8106
8107 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8108 {
8109 struct drm_device *dev = dev_priv->dev;
8110
8111 if (IS_HASWELL(dev)) {
8112 mutex_lock(&dev_priv->rps.hw_lock);
8113 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8114 val))
8115 DRM_ERROR("Failed to write to D_COMP\n");
8116 mutex_unlock(&dev_priv->rps.hw_lock);
8117 } else {
8118 I915_WRITE(D_COMP_BDW, val);
8119 POSTING_READ(D_COMP_BDW);
8120 }
8121 }
8122
8123 /*
8124 * This function implements pieces of two sequences from BSpec:
8125 * - Sequence for display software to disable LCPLL
8126 * - Sequence for display software to allow package C8+
8127 * The steps implemented here are just the steps that actually touch the LCPLL
8128 * register. Callers should take care of disabling all the display engine
8129 * functions, doing the mode unset, fixing interrupts, etc.
8130 */
8131 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8132 bool switch_to_fclk, bool allow_power_down)
8133 {
8134 uint32_t val;
8135
8136 assert_can_disable_lcpll(dev_priv);
8137
8138 val = I915_READ(LCPLL_CTL);
8139
8140 if (switch_to_fclk) {
8141 val |= LCPLL_CD_SOURCE_FCLK;
8142 I915_WRITE(LCPLL_CTL, val);
8143
8144 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8145 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8146 DRM_ERROR("Switching to FCLK failed\n");
8147
8148 val = I915_READ(LCPLL_CTL);
8149 }
8150
8151 val |= LCPLL_PLL_DISABLE;
8152 I915_WRITE(LCPLL_CTL, val);
8153 POSTING_READ(LCPLL_CTL);
8154
8155 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8156 DRM_ERROR("LCPLL still locked\n");
8157
8158 val = hsw_read_dcomp(dev_priv);
8159 val |= D_COMP_COMP_DISABLE;
8160 hsw_write_dcomp(dev_priv, val);
8161 ndelay(100);
8162
8163 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8164 1))
8165 DRM_ERROR("D_COMP RCOMP still in progress\n");
8166
8167 if (allow_power_down) {
8168 val = I915_READ(LCPLL_CTL);
8169 val |= LCPLL_POWER_DOWN_ALLOW;
8170 I915_WRITE(LCPLL_CTL, val);
8171 POSTING_READ(LCPLL_CTL);
8172 }
8173 }
8174
8175 /*
8176 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8177 * source.
8178 */
8179 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8180 {
8181 uint32_t val;
8182
8183 val = I915_READ(LCPLL_CTL);
8184
8185 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8186 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8187 return;
8188
8189 /*
8190 * Make sure we're not on PC8 state before disabling PC8, otherwise
8191 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8192 */
8193 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8194
8195 if (val & LCPLL_POWER_DOWN_ALLOW) {
8196 val &= ~LCPLL_POWER_DOWN_ALLOW;
8197 I915_WRITE(LCPLL_CTL, val);
8198 POSTING_READ(LCPLL_CTL);
8199 }
8200
8201 val = hsw_read_dcomp(dev_priv);
8202 val |= D_COMP_COMP_FORCE;
8203 val &= ~D_COMP_COMP_DISABLE;
8204 hsw_write_dcomp(dev_priv, val);
8205
8206 val = I915_READ(LCPLL_CTL);
8207 val &= ~LCPLL_PLL_DISABLE;
8208 I915_WRITE(LCPLL_CTL, val);
8209
8210 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8211 DRM_ERROR("LCPLL not locked yet\n");
8212
8213 if (val & LCPLL_CD_SOURCE_FCLK) {
8214 val = I915_READ(LCPLL_CTL);
8215 val &= ~LCPLL_CD_SOURCE_FCLK;
8216 I915_WRITE(LCPLL_CTL, val);
8217
8218 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8219 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8220 DRM_ERROR("Switching back to LCPLL failed\n");
8221 }
8222
8223 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8224 }
8225
8226 /*
8227 * Package states C8 and deeper are really deep PC states that can only be
8228 * reached when all the devices on the system allow it, so even if the graphics
8229 * device allows PC8+, it doesn't mean the system will actually get to these
8230 * states. Our driver only allows PC8+ when going into runtime PM.
8231 *
8232 * The requirements for PC8+ are that all the outputs are disabled, the power
8233 * well is disabled and most interrupts are disabled, and these are also
8234 * requirements for runtime PM. When these conditions are met, we manually do
8235 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8236 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8237 * hang the machine.
8238 *
8239 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8240 * the state of some registers, so when we come back from PC8+ we need to
8241 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8242 * need to take care of the registers kept by RC6. Notice that this happens even
8243 * if we don't put the device in PCI D3 state (which is what currently happens
8244 * because of the runtime PM support).
8245 *
8246 * For more, read "Display Sequences for Package C8" on the hardware
8247 * documentation.
8248 */
8249 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8250 {
8251 struct drm_device *dev = dev_priv->dev;
8252 uint32_t val;
8253
8254 DRM_DEBUG_KMS("Enabling package C8+\n");
8255
8256 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8257 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8258 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8259 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8260 }
8261
8262 lpt_disable_clkout_dp(dev);
8263 hsw_disable_lcpll(dev_priv, true, true);
8264 }
8265
8266 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8267 {
8268 struct drm_device *dev = dev_priv->dev;
8269 uint32_t val;
8270
8271 DRM_DEBUG_KMS("Disabling package C8+\n");
8272
8273 hsw_restore_lcpll(dev_priv);
8274 lpt_init_pch_refclk(dev);
8275
8276 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8277 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8278 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8279 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8280 }
8281
8282 intel_prepare_ddi(dev);
8283 }
8284
8285 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8286 struct intel_crtc_state *crtc_state)
8287 {
8288 if (!intel_ddi_pll_select(crtc, crtc_state))
8289 return -EINVAL;
8290
8291 crtc->lowfreq_avail = false;
8292
8293 return 0;
8294 }
8295
8296 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8297 enum port port,
8298 struct intel_crtc_state *pipe_config)
8299 {
8300 u32 temp, dpll_ctl1;
8301
8302 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8303 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8304
8305 switch (pipe_config->ddi_pll_sel) {
8306 case SKL_DPLL0:
8307 /*
8308 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8309 * of the shared DPLL framework and thus needs to be read out
8310 * separately
8311 */
8312 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8313 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8314 break;
8315 case SKL_DPLL1:
8316 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8317 break;
8318 case SKL_DPLL2:
8319 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8320 break;
8321 case SKL_DPLL3:
8322 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8323 break;
8324 }
8325 }
8326
8327 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8328 enum port port,
8329 struct intel_crtc_state *pipe_config)
8330 {
8331 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8332
8333 switch (pipe_config->ddi_pll_sel) {
8334 case PORT_CLK_SEL_WRPLL1:
8335 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8336 break;
8337 case PORT_CLK_SEL_WRPLL2:
8338 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8339 break;
8340 }
8341 }
8342
8343 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8344 struct intel_crtc_state *pipe_config)
8345 {
8346 struct drm_device *dev = crtc->base.dev;
8347 struct drm_i915_private *dev_priv = dev->dev_private;
8348 struct intel_shared_dpll *pll;
8349 enum port port;
8350 uint32_t tmp;
8351
8352 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8353
8354 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8355
8356 if (IS_SKYLAKE(dev))
8357 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8358 else
8359 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8360
8361 if (pipe_config->shared_dpll >= 0) {
8362 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8363
8364 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8365 &pipe_config->dpll_hw_state));
8366 }
8367
8368 /*
8369 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8370 * DDI E. So just check whether this pipe is wired to DDI E and whether
8371 * the PCH transcoder is on.
8372 */
8373 if (INTEL_INFO(dev)->gen < 9 &&
8374 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8375 pipe_config->has_pch_encoder = true;
8376
8377 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8378 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8379 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8380
8381 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8382 }
8383 }
8384
8385 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8386 struct intel_crtc_state *pipe_config)
8387 {
8388 struct drm_device *dev = crtc->base.dev;
8389 struct drm_i915_private *dev_priv = dev->dev_private;
8390 enum intel_display_power_domain pfit_domain;
8391 uint32_t tmp;
8392
8393 if (!intel_display_power_is_enabled(dev_priv,
8394 POWER_DOMAIN_PIPE(crtc->pipe)))
8395 return false;
8396
8397 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8398 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8399
8400 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8401 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8402 enum pipe trans_edp_pipe;
8403 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8404 default:
8405 WARN(1, "unknown pipe linked to edp transcoder\n");
8406 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8407 case TRANS_DDI_EDP_INPUT_A_ON:
8408 trans_edp_pipe = PIPE_A;
8409 break;
8410 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8411 trans_edp_pipe = PIPE_B;
8412 break;
8413 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8414 trans_edp_pipe = PIPE_C;
8415 break;
8416 }
8417
8418 if (trans_edp_pipe == crtc->pipe)
8419 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8420 }
8421
8422 if (!intel_display_power_is_enabled(dev_priv,
8423 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8424 return false;
8425
8426 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8427 if (!(tmp & PIPECONF_ENABLE))
8428 return false;
8429
8430 haswell_get_ddi_port_state(crtc, pipe_config);
8431
8432 intel_get_pipe_timings(crtc, pipe_config);
8433
8434 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8435 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8436 if (IS_SKYLAKE(dev))
8437 skylake_get_pfit_config(crtc, pipe_config);
8438 else
8439 ironlake_get_pfit_config(crtc, pipe_config);
8440 }
8441
8442 if (IS_HASWELL(dev))
8443 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8444 (I915_READ(IPS_CTL) & IPS_ENABLE);
8445
8446 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8447 pipe_config->pixel_multiplier =
8448 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8449 } else {
8450 pipe_config->pixel_multiplier = 1;
8451 }
8452
8453 return true;
8454 }
8455
8456 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8457 {
8458 struct drm_device *dev = crtc->dev;
8459 struct drm_i915_private *dev_priv = dev->dev_private;
8460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8461 uint32_t cntl = 0, size = 0;
8462
8463 if (base) {
8464 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8465 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8466 unsigned int stride = roundup_pow_of_two(width) * 4;
8467
8468 switch (stride) {
8469 default:
8470 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8471 width, stride);
8472 stride = 256;
8473 /* fallthrough */
8474 case 256:
8475 case 512:
8476 case 1024:
8477 case 2048:
8478 break;
8479 }
8480
8481 cntl |= CURSOR_ENABLE |
8482 CURSOR_GAMMA_ENABLE |
8483 CURSOR_FORMAT_ARGB |
8484 CURSOR_STRIDE(stride);
8485
8486 size = (height << 12) | width;
8487 }
8488
8489 if (intel_crtc->cursor_cntl != 0 &&
8490 (intel_crtc->cursor_base != base ||
8491 intel_crtc->cursor_size != size ||
8492 intel_crtc->cursor_cntl != cntl)) {
8493 /* On these chipsets we can only modify the base/size/stride
8494 * whilst the cursor is disabled.
8495 */
8496 I915_WRITE(_CURACNTR, 0);
8497 POSTING_READ(_CURACNTR);
8498 intel_crtc->cursor_cntl = 0;
8499 }
8500
8501 if (intel_crtc->cursor_base != base) {
8502 I915_WRITE(_CURABASE, base);
8503 intel_crtc->cursor_base = base;
8504 }
8505
8506 if (intel_crtc->cursor_size != size) {
8507 I915_WRITE(CURSIZE, size);
8508 intel_crtc->cursor_size = size;
8509 }
8510
8511 if (intel_crtc->cursor_cntl != cntl) {
8512 I915_WRITE(_CURACNTR, cntl);
8513 POSTING_READ(_CURACNTR);
8514 intel_crtc->cursor_cntl = cntl;
8515 }
8516 }
8517
8518 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8519 {
8520 struct drm_device *dev = crtc->dev;
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8523 int pipe = intel_crtc->pipe;
8524 uint32_t cntl;
8525
8526 cntl = 0;
8527 if (base) {
8528 cntl = MCURSOR_GAMMA_ENABLE;
8529 switch (intel_crtc->base.cursor->state->crtc_w) {
8530 case 64:
8531 cntl |= CURSOR_MODE_64_ARGB_AX;
8532 break;
8533 case 128:
8534 cntl |= CURSOR_MODE_128_ARGB_AX;
8535 break;
8536 case 256:
8537 cntl |= CURSOR_MODE_256_ARGB_AX;
8538 break;
8539 default:
8540 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8541 return;
8542 }
8543 cntl |= pipe << 28; /* Connect to correct pipe */
8544
8545 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8546 cntl |= CURSOR_PIPE_CSC_ENABLE;
8547 }
8548
8549 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8550 cntl |= CURSOR_ROTATE_180;
8551
8552 if (intel_crtc->cursor_cntl != cntl) {
8553 I915_WRITE(CURCNTR(pipe), cntl);
8554 POSTING_READ(CURCNTR(pipe));
8555 intel_crtc->cursor_cntl = cntl;
8556 }
8557
8558 /* and commit changes on next vblank */
8559 I915_WRITE(CURBASE(pipe), base);
8560 POSTING_READ(CURBASE(pipe));
8561
8562 intel_crtc->cursor_base = base;
8563 }
8564
8565 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8566 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8567 bool on)
8568 {
8569 struct drm_device *dev = crtc->dev;
8570 struct drm_i915_private *dev_priv = dev->dev_private;
8571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8572 int pipe = intel_crtc->pipe;
8573 int x = crtc->cursor_x;
8574 int y = crtc->cursor_y;
8575 u32 base = 0, pos = 0;
8576
8577 if (on)
8578 base = intel_crtc->cursor_addr;
8579
8580 if (x >= intel_crtc->config->pipe_src_w)
8581 base = 0;
8582
8583 if (y >= intel_crtc->config->pipe_src_h)
8584 base = 0;
8585
8586 if (x < 0) {
8587 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8588 base = 0;
8589
8590 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8591 x = -x;
8592 }
8593 pos |= x << CURSOR_X_SHIFT;
8594
8595 if (y < 0) {
8596 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8597 base = 0;
8598
8599 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8600 y = -y;
8601 }
8602 pos |= y << CURSOR_Y_SHIFT;
8603
8604 if (base == 0 && intel_crtc->cursor_base == 0)
8605 return;
8606
8607 I915_WRITE(CURPOS(pipe), pos);
8608
8609 /* ILK+ do this automagically */
8610 if (HAS_GMCH_DISPLAY(dev) &&
8611 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8612 base += (intel_crtc->base.cursor->state->crtc_h *
8613 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8614 }
8615
8616 if (IS_845G(dev) || IS_I865G(dev))
8617 i845_update_cursor(crtc, base);
8618 else
8619 i9xx_update_cursor(crtc, base);
8620 }
8621
8622 static bool cursor_size_ok(struct drm_device *dev,
8623 uint32_t width, uint32_t height)
8624 {
8625 if (width == 0 || height == 0)
8626 return false;
8627
8628 /*
8629 * 845g/865g are special in that they are only limited by
8630 * the width of their cursors, the height is arbitrary up to
8631 * the precision of the register. Everything else requires
8632 * square cursors, limited to a few power-of-two sizes.
8633 */
8634 if (IS_845G(dev) || IS_I865G(dev)) {
8635 if ((width & 63) != 0)
8636 return false;
8637
8638 if (width > (IS_845G(dev) ? 64 : 512))
8639 return false;
8640
8641 if (height > 1023)
8642 return false;
8643 } else {
8644 switch (width | height) {
8645 case 256:
8646 case 128:
8647 if (IS_GEN2(dev))
8648 return false;
8649 case 64:
8650 break;
8651 default:
8652 return false;
8653 }
8654 }
8655
8656 return true;
8657 }
8658
8659 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8660 u16 *blue, uint32_t start, uint32_t size)
8661 {
8662 int end = (start + size > 256) ? 256 : start + size, i;
8663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664
8665 for (i = start; i < end; i++) {
8666 intel_crtc->lut_r[i] = red[i] >> 8;
8667 intel_crtc->lut_g[i] = green[i] >> 8;
8668 intel_crtc->lut_b[i] = blue[i] >> 8;
8669 }
8670
8671 intel_crtc_load_lut(crtc);
8672 }
8673
8674 /* VESA 640x480x72Hz mode to set on the pipe */
8675 static struct drm_display_mode load_detect_mode = {
8676 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8677 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8678 };
8679
8680 struct drm_framebuffer *
8681 __intel_framebuffer_create(struct drm_device *dev,
8682 struct drm_mode_fb_cmd2 *mode_cmd,
8683 struct drm_i915_gem_object *obj)
8684 {
8685 struct intel_framebuffer *intel_fb;
8686 int ret;
8687
8688 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8689 if (!intel_fb) {
8690 drm_gem_object_unreference(&obj->base);
8691 return ERR_PTR(-ENOMEM);
8692 }
8693
8694 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8695 if (ret)
8696 goto err;
8697
8698 return &intel_fb->base;
8699 err:
8700 drm_gem_object_unreference(&obj->base);
8701 kfree(intel_fb);
8702
8703 return ERR_PTR(ret);
8704 }
8705
8706 static struct drm_framebuffer *
8707 intel_framebuffer_create(struct drm_device *dev,
8708 struct drm_mode_fb_cmd2 *mode_cmd,
8709 struct drm_i915_gem_object *obj)
8710 {
8711 struct drm_framebuffer *fb;
8712 int ret;
8713
8714 ret = i915_mutex_lock_interruptible(dev);
8715 if (ret)
8716 return ERR_PTR(ret);
8717 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8718 mutex_unlock(&dev->struct_mutex);
8719
8720 return fb;
8721 }
8722
8723 static u32
8724 intel_framebuffer_pitch_for_width(int width, int bpp)
8725 {
8726 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8727 return ALIGN(pitch, 64);
8728 }
8729
8730 static u32
8731 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8732 {
8733 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8734 return PAGE_ALIGN(pitch * mode->vdisplay);
8735 }
8736
8737 static struct drm_framebuffer *
8738 intel_framebuffer_create_for_mode(struct drm_device *dev,
8739 struct drm_display_mode *mode,
8740 int depth, int bpp)
8741 {
8742 struct drm_i915_gem_object *obj;
8743 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8744
8745 obj = i915_gem_alloc_object(dev,
8746 intel_framebuffer_size_for_mode(mode, bpp));
8747 if (obj == NULL)
8748 return ERR_PTR(-ENOMEM);
8749
8750 mode_cmd.width = mode->hdisplay;
8751 mode_cmd.height = mode->vdisplay;
8752 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8753 bpp);
8754 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8755
8756 return intel_framebuffer_create(dev, &mode_cmd, obj);
8757 }
8758
8759 static struct drm_framebuffer *
8760 mode_fits_in_fbdev(struct drm_device *dev,
8761 struct drm_display_mode *mode)
8762 {
8763 #ifdef CONFIG_DRM_I915_FBDEV
8764 struct drm_i915_private *dev_priv = dev->dev_private;
8765 struct drm_i915_gem_object *obj;
8766 struct drm_framebuffer *fb;
8767
8768 if (!dev_priv->fbdev)
8769 return NULL;
8770
8771 if (!dev_priv->fbdev->fb)
8772 return NULL;
8773
8774 obj = dev_priv->fbdev->fb->obj;
8775 BUG_ON(!obj);
8776
8777 fb = &dev_priv->fbdev->fb->base;
8778 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8779 fb->bits_per_pixel))
8780 return NULL;
8781
8782 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8783 return NULL;
8784
8785 return fb;
8786 #else
8787 return NULL;
8788 #endif
8789 }
8790
8791 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8792 struct drm_display_mode *mode,
8793 struct intel_load_detect_pipe *old,
8794 struct drm_modeset_acquire_ctx *ctx)
8795 {
8796 struct intel_crtc *intel_crtc;
8797 struct intel_encoder *intel_encoder =
8798 intel_attached_encoder(connector);
8799 struct drm_crtc *possible_crtc;
8800 struct drm_encoder *encoder = &intel_encoder->base;
8801 struct drm_crtc *crtc = NULL;
8802 struct drm_device *dev = encoder->dev;
8803 struct drm_framebuffer *fb;
8804 struct drm_mode_config *config = &dev->mode_config;
8805 int ret, i = -1;
8806
8807 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8808 connector->base.id, connector->name,
8809 encoder->base.id, encoder->name);
8810
8811 retry:
8812 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8813 if (ret)
8814 goto fail_unlock;
8815
8816 /*
8817 * Algorithm gets a little messy:
8818 *
8819 * - if the connector already has an assigned crtc, use it (but make
8820 * sure it's on first)
8821 *
8822 * - try to find the first unused crtc that can drive this connector,
8823 * and use that if we find one
8824 */
8825
8826 /* See if we already have a CRTC for this connector */
8827 if (encoder->crtc) {
8828 crtc = encoder->crtc;
8829
8830 ret = drm_modeset_lock(&crtc->mutex, ctx);
8831 if (ret)
8832 goto fail_unlock;
8833 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8834 if (ret)
8835 goto fail_unlock;
8836
8837 old->dpms_mode = connector->dpms;
8838 old->load_detect_temp = false;
8839
8840 /* Make sure the crtc and connector are running */
8841 if (connector->dpms != DRM_MODE_DPMS_ON)
8842 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8843
8844 return true;
8845 }
8846
8847 /* Find an unused one (if possible) */
8848 for_each_crtc(dev, possible_crtc) {
8849 i++;
8850 if (!(encoder->possible_crtcs & (1 << i)))
8851 continue;
8852 if (possible_crtc->state->enable)
8853 continue;
8854 /* This can occur when applying the pipe A quirk on resume. */
8855 if (to_intel_crtc(possible_crtc)->new_enabled)
8856 continue;
8857
8858 crtc = possible_crtc;
8859 break;
8860 }
8861
8862 /*
8863 * If we didn't find an unused CRTC, don't use any.
8864 */
8865 if (!crtc) {
8866 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8867 goto fail_unlock;
8868 }
8869
8870 ret = drm_modeset_lock(&crtc->mutex, ctx);
8871 if (ret)
8872 goto fail_unlock;
8873 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8874 if (ret)
8875 goto fail_unlock;
8876 intel_encoder->new_crtc = to_intel_crtc(crtc);
8877 to_intel_connector(connector)->new_encoder = intel_encoder;
8878
8879 intel_crtc = to_intel_crtc(crtc);
8880 intel_crtc->new_enabled = true;
8881 intel_crtc->new_config = intel_crtc->config;
8882 old->dpms_mode = connector->dpms;
8883 old->load_detect_temp = true;
8884 old->release_fb = NULL;
8885
8886 if (!mode)
8887 mode = &load_detect_mode;
8888
8889 /* We need a framebuffer large enough to accommodate all accesses
8890 * that the plane may generate whilst we perform load detection.
8891 * We can not rely on the fbcon either being present (we get called
8892 * during its initialisation to detect all boot displays, or it may
8893 * not even exist) or that it is large enough to satisfy the
8894 * requested mode.
8895 */
8896 fb = mode_fits_in_fbdev(dev, mode);
8897 if (fb == NULL) {
8898 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8899 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8900 old->release_fb = fb;
8901 } else
8902 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8903 if (IS_ERR(fb)) {
8904 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8905 goto fail;
8906 }
8907
8908 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8909 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8910 if (old->release_fb)
8911 old->release_fb->funcs->destroy(old->release_fb);
8912 goto fail;
8913 }
8914 crtc->primary->crtc = crtc;
8915
8916 /* let the connector get through one full cycle before testing */
8917 intel_wait_for_vblank(dev, intel_crtc->pipe);
8918 return true;
8919
8920 fail:
8921 intel_crtc->new_enabled = crtc->state->enable;
8922 if (intel_crtc->new_enabled)
8923 intel_crtc->new_config = intel_crtc->config;
8924 else
8925 intel_crtc->new_config = NULL;
8926 fail_unlock:
8927 if (ret == -EDEADLK) {
8928 drm_modeset_backoff(ctx);
8929 goto retry;
8930 }
8931
8932 return false;
8933 }
8934
8935 void intel_release_load_detect_pipe(struct drm_connector *connector,
8936 struct intel_load_detect_pipe *old)
8937 {
8938 struct intel_encoder *intel_encoder =
8939 intel_attached_encoder(connector);
8940 struct drm_encoder *encoder = &intel_encoder->base;
8941 struct drm_crtc *crtc = encoder->crtc;
8942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8943
8944 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8945 connector->base.id, connector->name,
8946 encoder->base.id, encoder->name);
8947
8948 if (old->load_detect_temp) {
8949 to_intel_connector(connector)->new_encoder = NULL;
8950 intel_encoder->new_crtc = NULL;
8951 intel_crtc->new_enabled = false;
8952 intel_crtc->new_config = NULL;
8953 intel_set_mode(crtc, NULL, 0, 0, NULL);
8954
8955 if (old->release_fb) {
8956 drm_framebuffer_unregister_private(old->release_fb);
8957 drm_framebuffer_unreference(old->release_fb);
8958 }
8959
8960 return;
8961 }
8962
8963 /* Switch crtc and encoder back off if necessary */
8964 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8965 connector->funcs->dpms(connector, old->dpms_mode);
8966 }
8967
8968 static int i9xx_pll_refclk(struct drm_device *dev,
8969 const struct intel_crtc_state *pipe_config)
8970 {
8971 struct drm_i915_private *dev_priv = dev->dev_private;
8972 u32 dpll = pipe_config->dpll_hw_state.dpll;
8973
8974 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8975 return dev_priv->vbt.lvds_ssc_freq;
8976 else if (HAS_PCH_SPLIT(dev))
8977 return 120000;
8978 else if (!IS_GEN2(dev))
8979 return 96000;
8980 else
8981 return 48000;
8982 }
8983
8984 /* Returns the clock of the currently programmed mode of the given pipe. */
8985 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8986 struct intel_crtc_state *pipe_config)
8987 {
8988 struct drm_device *dev = crtc->base.dev;
8989 struct drm_i915_private *dev_priv = dev->dev_private;
8990 int pipe = pipe_config->cpu_transcoder;
8991 u32 dpll = pipe_config->dpll_hw_state.dpll;
8992 u32 fp;
8993 intel_clock_t clock;
8994 int refclk = i9xx_pll_refclk(dev, pipe_config);
8995
8996 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8997 fp = pipe_config->dpll_hw_state.fp0;
8998 else
8999 fp = pipe_config->dpll_hw_state.fp1;
9000
9001 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9002 if (IS_PINEVIEW(dev)) {
9003 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9004 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9005 } else {
9006 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9007 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9008 }
9009
9010 if (!IS_GEN2(dev)) {
9011 if (IS_PINEVIEW(dev))
9012 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9013 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9014 else
9015 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9016 DPLL_FPA01_P1_POST_DIV_SHIFT);
9017
9018 switch (dpll & DPLL_MODE_MASK) {
9019 case DPLLB_MODE_DAC_SERIAL:
9020 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9021 5 : 10;
9022 break;
9023 case DPLLB_MODE_LVDS:
9024 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9025 7 : 14;
9026 break;
9027 default:
9028 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9029 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9030 return;
9031 }
9032
9033 if (IS_PINEVIEW(dev))
9034 pineview_clock(refclk, &clock);
9035 else
9036 i9xx_clock(refclk, &clock);
9037 } else {
9038 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9039 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9040
9041 if (is_lvds) {
9042 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9043 DPLL_FPA01_P1_POST_DIV_SHIFT);
9044
9045 if (lvds & LVDS_CLKB_POWER_UP)
9046 clock.p2 = 7;
9047 else
9048 clock.p2 = 14;
9049 } else {
9050 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9051 clock.p1 = 2;
9052 else {
9053 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9054 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9055 }
9056 if (dpll & PLL_P2_DIVIDE_BY_4)
9057 clock.p2 = 4;
9058 else
9059 clock.p2 = 2;
9060 }
9061
9062 i9xx_clock(refclk, &clock);
9063 }
9064
9065 /*
9066 * This value includes pixel_multiplier. We will use
9067 * port_clock to compute adjusted_mode.crtc_clock in the
9068 * encoder's get_config() function.
9069 */
9070 pipe_config->port_clock = clock.dot;
9071 }
9072
9073 int intel_dotclock_calculate(int link_freq,
9074 const struct intel_link_m_n *m_n)
9075 {
9076 /*
9077 * The calculation for the data clock is:
9078 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9079 * But we want to avoid losing precison if possible, so:
9080 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9081 *
9082 * and the link clock is simpler:
9083 * link_clock = (m * link_clock) / n
9084 */
9085
9086 if (!m_n->link_n)
9087 return 0;
9088
9089 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9090 }
9091
9092 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9093 struct intel_crtc_state *pipe_config)
9094 {
9095 struct drm_device *dev = crtc->base.dev;
9096
9097 /* read out port_clock from the DPLL */
9098 i9xx_crtc_clock_get(crtc, pipe_config);
9099
9100 /*
9101 * This value does not include pixel_multiplier.
9102 * We will check that port_clock and adjusted_mode.crtc_clock
9103 * agree once we know their relationship in the encoder's
9104 * get_config() function.
9105 */
9106 pipe_config->base.adjusted_mode.crtc_clock =
9107 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9108 &pipe_config->fdi_m_n);
9109 }
9110
9111 /** Returns the currently programmed mode of the given pipe. */
9112 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9113 struct drm_crtc *crtc)
9114 {
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9117 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9118 struct drm_display_mode *mode;
9119 struct intel_crtc_state pipe_config;
9120 int htot = I915_READ(HTOTAL(cpu_transcoder));
9121 int hsync = I915_READ(HSYNC(cpu_transcoder));
9122 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9123 int vsync = I915_READ(VSYNC(cpu_transcoder));
9124 enum pipe pipe = intel_crtc->pipe;
9125
9126 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9127 if (!mode)
9128 return NULL;
9129
9130 /*
9131 * Construct a pipe_config sufficient for getting the clock info
9132 * back out of crtc_clock_get.
9133 *
9134 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9135 * to use a real value here instead.
9136 */
9137 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9138 pipe_config.pixel_multiplier = 1;
9139 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9140 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9141 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9142 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9143
9144 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9145 mode->hdisplay = (htot & 0xffff) + 1;
9146 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9147 mode->hsync_start = (hsync & 0xffff) + 1;
9148 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9149 mode->vdisplay = (vtot & 0xffff) + 1;
9150 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9151 mode->vsync_start = (vsync & 0xffff) + 1;
9152 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9153
9154 drm_mode_set_name(mode);
9155
9156 return mode;
9157 }
9158
9159 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9160 {
9161 struct drm_device *dev = crtc->dev;
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9164
9165 if (!HAS_GMCH_DISPLAY(dev))
9166 return;
9167
9168 if (!dev_priv->lvds_downclock_avail)
9169 return;
9170
9171 /*
9172 * Since this is called by a timer, we should never get here in
9173 * the manual case.
9174 */
9175 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9176 int pipe = intel_crtc->pipe;
9177 int dpll_reg = DPLL(pipe);
9178 int dpll;
9179
9180 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9181
9182 assert_panel_unlocked(dev_priv, pipe);
9183
9184 dpll = I915_READ(dpll_reg);
9185 dpll |= DISPLAY_RATE_SELECT_FPA1;
9186 I915_WRITE(dpll_reg, dpll);
9187 intel_wait_for_vblank(dev, pipe);
9188 dpll = I915_READ(dpll_reg);
9189 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9190 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9191 }
9192
9193 }
9194
9195 void intel_mark_busy(struct drm_device *dev)
9196 {
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9198
9199 if (dev_priv->mm.busy)
9200 return;
9201
9202 intel_runtime_pm_get(dev_priv);
9203 i915_update_gfx_val(dev_priv);
9204 if (INTEL_INFO(dev)->gen >= 6)
9205 gen6_rps_busy(dev_priv);
9206 dev_priv->mm.busy = true;
9207 }
9208
9209 void intel_mark_idle(struct drm_device *dev)
9210 {
9211 struct drm_i915_private *dev_priv = dev->dev_private;
9212 struct drm_crtc *crtc;
9213
9214 if (!dev_priv->mm.busy)
9215 return;
9216
9217 dev_priv->mm.busy = false;
9218
9219 if (!i915.powersave)
9220 goto out;
9221
9222 for_each_crtc(dev, crtc) {
9223 if (!crtc->primary->fb)
9224 continue;
9225
9226 intel_decrease_pllclock(crtc);
9227 }
9228
9229 if (INTEL_INFO(dev)->gen >= 6)
9230 gen6_rps_idle(dev->dev_private);
9231
9232 out:
9233 intel_runtime_pm_put(dev_priv);
9234 }
9235
9236 static void intel_crtc_set_state(struct intel_crtc *crtc,
9237 struct intel_crtc_state *crtc_state)
9238 {
9239 kfree(crtc->config);
9240 crtc->config = crtc_state;
9241 crtc->base.state = &crtc_state->base;
9242 }
9243
9244 static void intel_crtc_destroy(struct drm_crtc *crtc)
9245 {
9246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9247 struct drm_device *dev = crtc->dev;
9248 struct intel_unpin_work *work;
9249
9250 spin_lock_irq(&dev->event_lock);
9251 work = intel_crtc->unpin_work;
9252 intel_crtc->unpin_work = NULL;
9253 spin_unlock_irq(&dev->event_lock);
9254
9255 if (work) {
9256 cancel_work_sync(&work->work);
9257 kfree(work);
9258 }
9259
9260 intel_crtc_set_state(intel_crtc, NULL);
9261 drm_crtc_cleanup(crtc);
9262
9263 kfree(intel_crtc);
9264 }
9265
9266 static void intel_unpin_work_fn(struct work_struct *__work)
9267 {
9268 struct intel_unpin_work *work =
9269 container_of(__work, struct intel_unpin_work, work);
9270 struct drm_device *dev = work->crtc->dev;
9271 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9272
9273 mutex_lock(&dev->struct_mutex);
9274 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9275 drm_gem_object_unreference(&work->pending_flip_obj->base);
9276
9277 intel_fbc_update(dev);
9278
9279 if (work->flip_queued_req)
9280 i915_gem_request_assign(&work->flip_queued_req, NULL);
9281 mutex_unlock(&dev->struct_mutex);
9282
9283 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9284 drm_framebuffer_unreference(work->old_fb);
9285
9286 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9287 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9288
9289 kfree(work);
9290 }
9291
9292 static void do_intel_finish_page_flip(struct drm_device *dev,
9293 struct drm_crtc *crtc)
9294 {
9295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9296 struct intel_unpin_work *work;
9297 unsigned long flags;
9298
9299 /* Ignore early vblank irqs */
9300 if (intel_crtc == NULL)
9301 return;
9302
9303 /*
9304 * This is called both by irq handlers and the reset code (to complete
9305 * lost pageflips) so needs the full irqsave spinlocks.
9306 */
9307 spin_lock_irqsave(&dev->event_lock, flags);
9308 work = intel_crtc->unpin_work;
9309
9310 /* Ensure we don't miss a work->pending update ... */
9311 smp_rmb();
9312
9313 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9314 spin_unlock_irqrestore(&dev->event_lock, flags);
9315 return;
9316 }
9317
9318 page_flip_completed(intel_crtc);
9319
9320 spin_unlock_irqrestore(&dev->event_lock, flags);
9321 }
9322
9323 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9324 {
9325 struct drm_i915_private *dev_priv = dev->dev_private;
9326 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9327
9328 do_intel_finish_page_flip(dev, crtc);
9329 }
9330
9331 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9332 {
9333 struct drm_i915_private *dev_priv = dev->dev_private;
9334 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9335
9336 do_intel_finish_page_flip(dev, crtc);
9337 }
9338
9339 /* Is 'a' after or equal to 'b'? */
9340 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9341 {
9342 return !((a - b) & 0x80000000);
9343 }
9344
9345 static bool page_flip_finished(struct intel_crtc *crtc)
9346 {
9347 struct drm_device *dev = crtc->base.dev;
9348 struct drm_i915_private *dev_priv = dev->dev_private;
9349
9350 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9351 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9352 return true;
9353
9354 /*
9355 * The relevant registers doen't exist on pre-ctg.
9356 * As the flip done interrupt doesn't trigger for mmio
9357 * flips on gmch platforms, a flip count check isn't
9358 * really needed there. But since ctg has the registers,
9359 * include it in the check anyway.
9360 */
9361 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9362 return true;
9363
9364 /*
9365 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9366 * used the same base address. In that case the mmio flip might
9367 * have completed, but the CS hasn't even executed the flip yet.
9368 *
9369 * A flip count check isn't enough as the CS might have updated
9370 * the base address just after start of vblank, but before we
9371 * managed to process the interrupt. This means we'd complete the
9372 * CS flip too soon.
9373 *
9374 * Combining both checks should get us a good enough result. It may
9375 * still happen that the CS flip has been executed, but has not
9376 * yet actually completed. But in case the base address is the same
9377 * anyway, we don't really care.
9378 */
9379 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9380 crtc->unpin_work->gtt_offset &&
9381 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9382 crtc->unpin_work->flip_count);
9383 }
9384
9385 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9386 {
9387 struct drm_i915_private *dev_priv = dev->dev_private;
9388 struct intel_crtc *intel_crtc =
9389 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9390 unsigned long flags;
9391
9392
9393 /*
9394 * This is called both by irq handlers and the reset code (to complete
9395 * lost pageflips) so needs the full irqsave spinlocks.
9396 *
9397 * NB: An MMIO update of the plane base pointer will also
9398 * generate a page-flip completion irq, i.e. every modeset
9399 * is also accompanied by a spurious intel_prepare_page_flip().
9400 */
9401 spin_lock_irqsave(&dev->event_lock, flags);
9402 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9403 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9404 spin_unlock_irqrestore(&dev->event_lock, flags);
9405 }
9406
9407 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9408 {
9409 /* Ensure that the work item is consistent when activating it ... */
9410 smp_wmb();
9411 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9412 /* and that it is marked active as soon as the irq could fire. */
9413 smp_wmb();
9414 }
9415
9416 static int intel_gen2_queue_flip(struct drm_device *dev,
9417 struct drm_crtc *crtc,
9418 struct drm_framebuffer *fb,
9419 struct drm_i915_gem_object *obj,
9420 struct intel_engine_cs *ring,
9421 uint32_t flags)
9422 {
9423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9424 u32 flip_mask;
9425 int ret;
9426
9427 ret = intel_ring_begin(ring, 6);
9428 if (ret)
9429 return ret;
9430
9431 /* Can't queue multiple flips, so wait for the previous
9432 * one to finish before executing the next.
9433 */
9434 if (intel_crtc->plane)
9435 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9436 else
9437 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9438 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9439 intel_ring_emit(ring, MI_NOOP);
9440 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9441 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9442 intel_ring_emit(ring, fb->pitches[0]);
9443 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9444 intel_ring_emit(ring, 0); /* aux display base address, unused */
9445
9446 intel_mark_page_flip_active(intel_crtc);
9447 __intel_ring_advance(ring);
9448 return 0;
9449 }
9450
9451 static int intel_gen3_queue_flip(struct drm_device *dev,
9452 struct drm_crtc *crtc,
9453 struct drm_framebuffer *fb,
9454 struct drm_i915_gem_object *obj,
9455 struct intel_engine_cs *ring,
9456 uint32_t flags)
9457 {
9458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9459 u32 flip_mask;
9460 int ret;
9461
9462 ret = intel_ring_begin(ring, 6);
9463 if (ret)
9464 return ret;
9465
9466 if (intel_crtc->plane)
9467 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9468 else
9469 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9470 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9471 intel_ring_emit(ring, MI_NOOP);
9472 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9473 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9474 intel_ring_emit(ring, fb->pitches[0]);
9475 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9476 intel_ring_emit(ring, MI_NOOP);
9477
9478 intel_mark_page_flip_active(intel_crtc);
9479 __intel_ring_advance(ring);
9480 return 0;
9481 }
9482
9483 static int intel_gen4_queue_flip(struct drm_device *dev,
9484 struct drm_crtc *crtc,
9485 struct drm_framebuffer *fb,
9486 struct drm_i915_gem_object *obj,
9487 struct intel_engine_cs *ring,
9488 uint32_t flags)
9489 {
9490 struct drm_i915_private *dev_priv = dev->dev_private;
9491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9492 uint32_t pf, pipesrc;
9493 int ret;
9494
9495 ret = intel_ring_begin(ring, 4);
9496 if (ret)
9497 return ret;
9498
9499 /* i965+ uses the linear or tiled offsets from the
9500 * Display Registers (which do not change across a page-flip)
9501 * so we need only reprogram the base address.
9502 */
9503 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9504 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9505 intel_ring_emit(ring, fb->pitches[0]);
9506 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9507 obj->tiling_mode);
9508
9509 /* XXX Enabling the panel-fitter across page-flip is so far
9510 * untested on non-native modes, so ignore it for now.
9511 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9512 */
9513 pf = 0;
9514 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9515 intel_ring_emit(ring, pf | pipesrc);
9516
9517 intel_mark_page_flip_active(intel_crtc);
9518 __intel_ring_advance(ring);
9519 return 0;
9520 }
9521
9522 static int intel_gen6_queue_flip(struct drm_device *dev,
9523 struct drm_crtc *crtc,
9524 struct drm_framebuffer *fb,
9525 struct drm_i915_gem_object *obj,
9526 struct intel_engine_cs *ring,
9527 uint32_t flags)
9528 {
9529 struct drm_i915_private *dev_priv = dev->dev_private;
9530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9531 uint32_t pf, pipesrc;
9532 int ret;
9533
9534 ret = intel_ring_begin(ring, 4);
9535 if (ret)
9536 return ret;
9537
9538 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9539 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9540 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9541 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9542
9543 /* Contrary to the suggestions in the documentation,
9544 * "Enable Panel Fitter" does not seem to be required when page
9545 * flipping with a non-native mode, and worse causes a normal
9546 * modeset to fail.
9547 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9548 */
9549 pf = 0;
9550 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9551 intel_ring_emit(ring, pf | pipesrc);
9552
9553 intel_mark_page_flip_active(intel_crtc);
9554 __intel_ring_advance(ring);
9555 return 0;
9556 }
9557
9558 static int intel_gen7_queue_flip(struct drm_device *dev,
9559 struct drm_crtc *crtc,
9560 struct drm_framebuffer *fb,
9561 struct drm_i915_gem_object *obj,
9562 struct intel_engine_cs *ring,
9563 uint32_t flags)
9564 {
9565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9566 uint32_t plane_bit = 0;
9567 int len, ret;
9568
9569 switch (intel_crtc->plane) {
9570 case PLANE_A:
9571 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9572 break;
9573 case PLANE_B:
9574 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9575 break;
9576 case PLANE_C:
9577 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9578 break;
9579 default:
9580 WARN_ONCE(1, "unknown plane in flip command\n");
9581 return -ENODEV;
9582 }
9583
9584 len = 4;
9585 if (ring->id == RCS) {
9586 len += 6;
9587 /*
9588 * On Gen 8, SRM is now taking an extra dword to accommodate
9589 * 48bits addresses, and we need a NOOP for the batch size to
9590 * stay even.
9591 */
9592 if (IS_GEN8(dev))
9593 len += 2;
9594 }
9595
9596 /*
9597 * BSpec MI_DISPLAY_FLIP for IVB:
9598 * "The full packet must be contained within the same cache line."
9599 *
9600 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9601 * cacheline, if we ever start emitting more commands before
9602 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9603 * then do the cacheline alignment, and finally emit the
9604 * MI_DISPLAY_FLIP.
9605 */
9606 ret = intel_ring_cacheline_align(ring);
9607 if (ret)
9608 return ret;
9609
9610 ret = intel_ring_begin(ring, len);
9611 if (ret)
9612 return ret;
9613
9614 /* Unmask the flip-done completion message. Note that the bspec says that
9615 * we should do this for both the BCS and RCS, and that we must not unmask
9616 * more than one flip event at any time (or ensure that one flip message
9617 * can be sent by waiting for flip-done prior to queueing new flips).
9618 * Experimentation says that BCS works despite DERRMR masking all
9619 * flip-done completion events and that unmasking all planes at once
9620 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9621 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9622 */
9623 if (ring->id == RCS) {
9624 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9625 intel_ring_emit(ring, DERRMR);
9626 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9627 DERRMR_PIPEB_PRI_FLIP_DONE |
9628 DERRMR_PIPEC_PRI_FLIP_DONE));
9629 if (IS_GEN8(dev))
9630 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9631 MI_SRM_LRM_GLOBAL_GTT);
9632 else
9633 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9634 MI_SRM_LRM_GLOBAL_GTT);
9635 intel_ring_emit(ring, DERRMR);
9636 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9637 if (IS_GEN8(dev)) {
9638 intel_ring_emit(ring, 0);
9639 intel_ring_emit(ring, MI_NOOP);
9640 }
9641 }
9642
9643 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9644 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9645 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9646 intel_ring_emit(ring, (MI_NOOP));
9647
9648 intel_mark_page_flip_active(intel_crtc);
9649 __intel_ring_advance(ring);
9650 return 0;
9651 }
9652
9653 static bool use_mmio_flip(struct intel_engine_cs *ring,
9654 struct drm_i915_gem_object *obj)
9655 {
9656 /*
9657 * This is not being used for older platforms, because
9658 * non-availability of flip done interrupt forces us to use
9659 * CS flips. Older platforms derive flip done using some clever
9660 * tricks involving the flip_pending status bits and vblank irqs.
9661 * So using MMIO flips there would disrupt this mechanism.
9662 */
9663
9664 if (ring == NULL)
9665 return true;
9666
9667 if (INTEL_INFO(ring->dev)->gen < 5)
9668 return false;
9669
9670 if (i915.use_mmio_flip < 0)
9671 return false;
9672 else if (i915.use_mmio_flip > 0)
9673 return true;
9674 else if (i915.enable_execlists)
9675 return true;
9676 else
9677 return ring != i915_gem_request_get_ring(obj->last_read_req);
9678 }
9679
9680 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9681 {
9682 struct drm_device *dev = intel_crtc->base.dev;
9683 struct drm_i915_private *dev_priv = dev->dev_private;
9684 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9685 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9686 struct drm_i915_gem_object *obj = intel_fb->obj;
9687 const enum pipe pipe = intel_crtc->pipe;
9688 u32 ctl, stride;
9689
9690 ctl = I915_READ(PLANE_CTL(pipe, 0));
9691 ctl &= ~PLANE_CTL_TILED_MASK;
9692 if (obj->tiling_mode == I915_TILING_X)
9693 ctl |= PLANE_CTL_TILED_X;
9694
9695 /*
9696 * The stride is either expressed as a multiple of 64 bytes chunks for
9697 * linear buffers or in number of tiles for tiled buffers.
9698 */
9699 stride = fb->pitches[0] >> 6;
9700 if (obj->tiling_mode == I915_TILING_X)
9701 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9702
9703 /*
9704 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9705 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9706 */
9707 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9708 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9709
9710 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9711 POSTING_READ(PLANE_SURF(pipe, 0));
9712 }
9713
9714 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9715 {
9716 struct drm_device *dev = intel_crtc->base.dev;
9717 struct drm_i915_private *dev_priv = dev->dev_private;
9718 struct intel_framebuffer *intel_fb =
9719 to_intel_framebuffer(intel_crtc->base.primary->fb);
9720 struct drm_i915_gem_object *obj = intel_fb->obj;
9721 u32 dspcntr;
9722 u32 reg;
9723
9724 reg = DSPCNTR(intel_crtc->plane);
9725 dspcntr = I915_READ(reg);
9726
9727 if (obj->tiling_mode != I915_TILING_NONE)
9728 dspcntr |= DISPPLANE_TILED;
9729 else
9730 dspcntr &= ~DISPPLANE_TILED;
9731
9732 I915_WRITE(reg, dspcntr);
9733
9734 I915_WRITE(DSPSURF(intel_crtc->plane),
9735 intel_crtc->unpin_work->gtt_offset);
9736 POSTING_READ(DSPSURF(intel_crtc->plane));
9737
9738 }
9739
9740 /*
9741 * XXX: This is the temporary way to update the plane registers until we get
9742 * around to using the usual plane update functions for MMIO flips
9743 */
9744 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9745 {
9746 struct drm_device *dev = intel_crtc->base.dev;
9747 bool atomic_update;
9748 u32 start_vbl_count;
9749
9750 intel_mark_page_flip_active(intel_crtc);
9751
9752 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9753
9754 if (INTEL_INFO(dev)->gen >= 9)
9755 skl_do_mmio_flip(intel_crtc);
9756 else
9757 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9758 ilk_do_mmio_flip(intel_crtc);
9759
9760 if (atomic_update)
9761 intel_pipe_update_end(intel_crtc, start_vbl_count);
9762 }
9763
9764 static void intel_mmio_flip_work_func(struct work_struct *work)
9765 {
9766 struct intel_crtc *crtc =
9767 container_of(work, struct intel_crtc, mmio_flip.work);
9768 struct intel_mmio_flip *mmio_flip;
9769
9770 mmio_flip = &crtc->mmio_flip;
9771 if (mmio_flip->req)
9772 WARN_ON(__i915_wait_request(mmio_flip->req,
9773 crtc->reset_counter,
9774 false, NULL, NULL) != 0);
9775
9776 intel_do_mmio_flip(crtc);
9777 if (mmio_flip->req) {
9778 mutex_lock(&crtc->base.dev->struct_mutex);
9779 i915_gem_request_assign(&mmio_flip->req, NULL);
9780 mutex_unlock(&crtc->base.dev->struct_mutex);
9781 }
9782 }
9783
9784 static int intel_queue_mmio_flip(struct drm_device *dev,
9785 struct drm_crtc *crtc,
9786 struct drm_framebuffer *fb,
9787 struct drm_i915_gem_object *obj,
9788 struct intel_engine_cs *ring,
9789 uint32_t flags)
9790 {
9791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9792
9793 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9794 obj->last_write_req);
9795
9796 schedule_work(&intel_crtc->mmio_flip.work);
9797
9798 return 0;
9799 }
9800
9801 static int intel_default_queue_flip(struct drm_device *dev,
9802 struct drm_crtc *crtc,
9803 struct drm_framebuffer *fb,
9804 struct drm_i915_gem_object *obj,
9805 struct intel_engine_cs *ring,
9806 uint32_t flags)
9807 {
9808 return -ENODEV;
9809 }
9810
9811 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9812 struct drm_crtc *crtc)
9813 {
9814 struct drm_i915_private *dev_priv = dev->dev_private;
9815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9816 struct intel_unpin_work *work = intel_crtc->unpin_work;
9817 u32 addr;
9818
9819 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9820 return true;
9821
9822 if (!work->enable_stall_check)
9823 return false;
9824
9825 if (work->flip_ready_vblank == 0) {
9826 if (work->flip_queued_req &&
9827 !i915_gem_request_completed(work->flip_queued_req, true))
9828 return false;
9829
9830 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9831 }
9832
9833 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9834 return false;
9835
9836 /* Potential stall - if we see that the flip has happened,
9837 * assume a missed interrupt. */
9838 if (INTEL_INFO(dev)->gen >= 4)
9839 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9840 else
9841 addr = I915_READ(DSPADDR(intel_crtc->plane));
9842
9843 /* There is a potential issue here with a false positive after a flip
9844 * to the same address. We could address this by checking for a
9845 * non-incrementing frame counter.
9846 */
9847 return addr == work->gtt_offset;
9848 }
9849
9850 void intel_check_page_flip(struct drm_device *dev, int pipe)
9851 {
9852 struct drm_i915_private *dev_priv = dev->dev_private;
9853 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9855
9856 WARN_ON(!in_interrupt());
9857
9858 if (crtc == NULL)
9859 return;
9860
9861 spin_lock(&dev->event_lock);
9862 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9863 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9864 intel_crtc->unpin_work->flip_queued_vblank,
9865 drm_vblank_count(dev, pipe));
9866 page_flip_completed(intel_crtc);
9867 }
9868 spin_unlock(&dev->event_lock);
9869 }
9870
9871 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9872 struct drm_framebuffer *fb,
9873 struct drm_pending_vblank_event *event,
9874 uint32_t page_flip_flags)
9875 {
9876 struct drm_device *dev = crtc->dev;
9877 struct drm_i915_private *dev_priv = dev->dev_private;
9878 struct drm_framebuffer *old_fb = crtc->primary->fb;
9879 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9881 struct drm_plane *primary = crtc->primary;
9882 enum pipe pipe = intel_crtc->pipe;
9883 struct intel_unpin_work *work;
9884 struct intel_engine_cs *ring;
9885 int ret;
9886
9887 /*
9888 * drm_mode_page_flip_ioctl() should already catch this, but double
9889 * check to be safe. In the future we may enable pageflipping from
9890 * a disabled primary plane.
9891 */
9892 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9893 return -EBUSY;
9894
9895 /* Can't change pixel format via MI display flips. */
9896 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9897 return -EINVAL;
9898
9899 /*
9900 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9901 * Note that pitch changes could also affect these register.
9902 */
9903 if (INTEL_INFO(dev)->gen > 3 &&
9904 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9905 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9906 return -EINVAL;
9907
9908 if (i915_terminally_wedged(&dev_priv->gpu_error))
9909 goto out_hang;
9910
9911 work = kzalloc(sizeof(*work), GFP_KERNEL);
9912 if (work == NULL)
9913 return -ENOMEM;
9914
9915 work->event = event;
9916 work->crtc = crtc;
9917 work->old_fb = old_fb;
9918 INIT_WORK(&work->work, intel_unpin_work_fn);
9919
9920 ret = drm_crtc_vblank_get(crtc);
9921 if (ret)
9922 goto free_work;
9923
9924 /* We borrow the event spin lock for protecting unpin_work */
9925 spin_lock_irq(&dev->event_lock);
9926 if (intel_crtc->unpin_work) {
9927 /* Before declaring the flip queue wedged, check if
9928 * the hardware completed the operation behind our backs.
9929 */
9930 if (__intel_pageflip_stall_check(dev, crtc)) {
9931 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9932 page_flip_completed(intel_crtc);
9933 } else {
9934 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9935 spin_unlock_irq(&dev->event_lock);
9936
9937 drm_crtc_vblank_put(crtc);
9938 kfree(work);
9939 return -EBUSY;
9940 }
9941 }
9942 intel_crtc->unpin_work = work;
9943 spin_unlock_irq(&dev->event_lock);
9944
9945 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9946 flush_workqueue(dev_priv->wq);
9947
9948 /* Reference the objects for the scheduled work. */
9949 drm_framebuffer_reference(work->old_fb);
9950 drm_gem_object_reference(&obj->base);
9951
9952 crtc->primary->fb = fb;
9953 update_state_fb(crtc->primary);
9954
9955 work->pending_flip_obj = obj;
9956
9957 ret = i915_mutex_lock_interruptible(dev);
9958 if (ret)
9959 goto cleanup;
9960
9961 atomic_inc(&intel_crtc->unpin_work_count);
9962 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9963
9964 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9965 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9966
9967 if (IS_VALLEYVIEW(dev)) {
9968 ring = &dev_priv->ring[BCS];
9969 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9970 /* vlv: DISPLAY_FLIP fails to change tiling */
9971 ring = NULL;
9972 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9973 ring = &dev_priv->ring[BCS];
9974 } else if (INTEL_INFO(dev)->gen >= 7) {
9975 ring = i915_gem_request_get_ring(obj->last_read_req);
9976 if (ring == NULL || ring->id != RCS)
9977 ring = &dev_priv->ring[BCS];
9978 } else {
9979 ring = &dev_priv->ring[RCS];
9980 }
9981
9982 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9983 if (ret)
9984 goto cleanup_pending;
9985
9986 work->gtt_offset =
9987 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9988
9989 if (use_mmio_flip(ring, obj)) {
9990 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9991 page_flip_flags);
9992 if (ret)
9993 goto cleanup_unpin;
9994
9995 i915_gem_request_assign(&work->flip_queued_req,
9996 obj->last_write_req);
9997 } else {
9998 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9999 page_flip_flags);
10000 if (ret)
10001 goto cleanup_unpin;
10002
10003 i915_gem_request_assign(&work->flip_queued_req,
10004 intel_ring_get_request(ring));
10005 }
10006
10007 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10008 work->enable_stall_check = true;
10009
10010 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10011 INTEL_FRONTBUFFER_PRIMARY(pipe));
10012
10013 intel_fbc_disable(dev);
10014 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10015 mutex_unlock(&dev->struct_mutex);
10016
10017 trace_i915_flip_request(intel_crtc->plane, obj);
10018
10019 return 0;
10020
10021 cleanup_unpin:
10022 intel_unpin_fb_obj(obj);
10023 cleanup_pending:
10024 atomic_dec(&intel_crtc->unpin_work_count);
10025 mutex_unlock(&dev->struct_mutex);
10026 cleanup:
10027 crtc->primary->fb = old_fb;
10028 update_state_fb(crtc->primary);
10029
10030 drm_gem_object_unreference_unlocked(&obj->base);
10031 drm_framebuffer_unreference(work->old_fb);
10032
10033 spin_lock_irq(&dev->event_lock);
10034 intel_crtc->unpin_work = NULL;
10035 spin_unlock_irq(&dev->event_lock);
10036
10037 drm_crtc_vblank_put(crtc);
10038 free_work:
10039 kfree(work);
10040
10041 if (ret == -EIO) {
10042 out_hang:
10043 ret = intel_plane_restore(primary);
10044 if (ret == 0 && event) {
10045 spin_lock_irq(&dev->event_lock);
10046 drm_send_vblank_event(dev, pipe, event);
10047 spin_unlock_irq(&dev->event_lock);
10048 }
10049 }
10050 return ret;
10051 }
10052
10053 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10054 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10055 .load_lut = intel_crtc_load_lut,
10056 .atomic_begin = intel_begin_crtc_commit,
10057 .atomic_flush = intel_finish_crtc_commit,
10058 };
10059
10060 /**
10061 * intel_modeset_update_staged_output_state
10062 *
10063 * Updates the staged output configuration state, e.g. after we've read out the
10064 * current hw state.
10065 */
10066 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10067 {
10068 struct intel_crtc *crtc;
10069 struct intel_encoder *encoder;
10070 struct intel_connector *connector;
10071
10072 for_each_intel_connector(dev, connector) {
10073 connector->new_encoder =
10074 to_intel_encoder(connector->base.encoder);
10075 }
10076
10077 for_each_intel_encoder(dev, encoder) {
10078 encoder->new_crtc =
10079 to_intel_crtc(encoder->base.crtc);
10080 }
10081
10082 for_each_intel_crtc(dev, crtc) {
10083 crtc->new_enabled = crtc->base.state->enable;
10084
10085 if (crtc->new_enabled)
10086 crtc->new_config = crtc->config;
10087 else
10088 crtc->new_config = NULL;
10089 }
10090 }
10091
10092 /**
10093 * intel_modeset_commit_output_state
10094 *
10095 * This function copies the stage display pipe configuration to the real one.
10096 */
10097 static void intel_modeset_commit_output_state(struct drm_device *dev)
10098 {
10099 struct intel_crtc *crtc;
10100 struct intel_encoder *encoder;
10101 struct intel_connector *connector;
10102
10103 for_each_intel_connector(dev, connector) {
10104 connector->base.encoder = &connector->new_encoder->base;
10105 }
10106
10107 for_each_intel_encoder(dev, encoder) {
10108 encoder->base.crtc = &encoder->new_crtc->base;
10109 }
10110
10111 for_each_intel_crtc(dev, crtc) {
10112 crtc->base.state->enable = crtc->new_enabled;
10113 crtc->base.enabled = crtc->new_enabled;
10114 }
10115 }
10116
10117 static void
10118 connected_sink_compute_bpp(struct intel_connector *connector,
10119 struct intel_crtc_state *pipe_config)
10120 {
10121 int bpp = pipe_config->pipe_bpp;
10122
10123 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10124 connector->base.base.id,
10125 connector->base.name);
10126
10127 /* Don't use an invalid EDID bpc value */
10128 if (connector->base.display_info.bpc &&
10129 connector->base.display_info.bpc * 3 < bpp) {
10130 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10131 bpp, connector->base.display_info.bpc*3);
10132 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10133 }
10134
10135 /* Clamp bpp to 8 on screens without EDID 1.4 */
10136 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10137 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10138 bpp);
10139 pipe_config->pipe_bpp = 24;
10140 }
10141 }
10142
10143 static int
10144 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10145 struct drm_framebuffer *fb,
10146 struct intel_crtc_state *pipe_config)
10147 {
10148 struct drm_device *dev = crtc->base.dev;
10149 struct intel_connector *connector;
10150 int bpp;
10151
10152 switch (fb->pixel_format) {
10153 case DRM_FORMAT_C8:
10154 bpp = 8*3; /* since we go through a colormap */
10155 break;
10156 case DRM_FORMAT_XRGB1555:
10157 case DRM_FORMAT_ARGB1555:
10158 /* checked in intel_framebuffer_init already */
10159 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10160 return -EINVAL;
10161 case DRM_FORMAT_RGB565:
10162 bpp = 6*3; /* min is 18bpp */
10163 break;
10164 case DRM_FORMAT_XBGR8888:
10165 case DRM_FORMAT_ABGR8888:
10166 /* checked in intel_framebuffer_init already */
10167 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10168 return -EINVAL;
10169 case DRM_FORMAT_XRGB8888:
10170 case DRM_FORMAT_ARGB8888:
10171 bpp = 8*3;
10172 break;
10173 case DRM_FORMAT_XRGB2101010:
10174 case DRM_FORMAT_ARGB2101010:
10175 case DRM_FORMAT_XBGR2101010:
10176 case DRM_FORMAT_ABGR2101010:
10177 /* checked in intel_framebuffer_init already */
10178 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10179 return -EINVAL;
10180 bpp = 10*3;
10181 break;
10182 /* TODO: gen4+ supports 16 bpc floating point, too. */
10183 default:
10184 DRM_DEBUG_KMS("unsupported depth\n");
10185 return -EINVAL;
10186 }
10187
10188 pipe_config->pipe_bpp = bpp;
10189
10190 /* Clamp display bpp to EDID value */
10191 for_each_intel_connector(dev, connector) {
10192 if (!connector->new_encoder ||
10193 connector->new_encoder->new_crtc != crtc)
10194 continue;
10195
10196 connected_sink_compute_bpp(connector, pipe_config);
10197 }
10198
10199 return bpp;
10200 }
10201
10202 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10203 {
10204 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10205 "type: 0x%x flags: 0x%x\n",
10206 mode->crtc_clock,
10207 mode->crtc_hdisplay, mode->crtc_hsync_start,
10208 mode->crtc_hsync_end, mode->crtc_htotal,
10209 mode->crtc_vdisplay, mode->crtc_vsync_start,
10210 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10211 }
10212
10213 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10214 struct intel_crtc_state *pipe_config,
10215 const char *context)
10216 {
10217 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10218 context, pipe_name(crtc->pipe));
10219
10220 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10221 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10222 pipe_config->pipe_bpp, pipe_config->dither);
10223 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10224 pipe_config->has_pch_encoder,
10225 pipe_config->fdi_lanes,
10226 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10227 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10228 pipe_config->fdi_m_n.tu);
10229 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10230 pipe_config->has_dp_encoder,
10231 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10232 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10233 pipe_config->dp_m_n.tu);
10234
10235 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10236 pipe_config->has_dp_encoder,
10237 pipe_config->dp_m2_n2.gmch_m,
10238 pipe_config->dp_m2_n2.gmch_n,
10239 pipe_config->dp_m2_n2.link_m,
10240 pipe_config->dp_m2_n2.link_n,
10241 pipe_config->dp_m2_n2.tu);
10242
10243 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10244 pipe_config->has_audio,
10245 pipe_config->has_infoframe);
10246
10247 DRM_DEBUG_KMS("requested mode:\n");
10248 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10249 DRM_DEBUG_KMS("adjusted mode:\n");
10250 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10251 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10252 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10253 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10254 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10255 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10256 pipe_config->gmch_pfit.control,
10257 pipe_config->gmch_pfit.pgm_ratios,
10258 pipe_config->gmch_pfit.lvds_border_bits);
10259 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10260 pipe_config->pch_pfit.pos,
10261 pipe_config->pch_pfit.size,
10262 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10263 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10264 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10265 }
10266
10267 static bool encoders_cloneable(const struct intel_encoder *a,
10268 const struct intel_encoder *b)
10269 {
10270 /* masks could be asymmetric, so check both ways */
10271 return a == b || (a->cloneable & (1 << b->type) &&
10272 b->cloneable & (1 << a->type));
10273 }
10274
10275 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10276 struct intel_encoder *encoder)
10277 {
10278 struct drm_device *dev = crtc->base.dev;
10279 struct intel_encoder *source_encoder;
10280
10281 for_each_intel_encoder(dev, source_encoder) {
10282 if (source_encoder->new_crtc != crtc)
10283 continue;
10284
10285 if (!encoders_cloneable(encoder, source_encoder))
10286 return false;
10287 }
10288
10289 return true;
10290 }
10291
10292 static bool check_encoder_cloning(struct intel_crtc *crtc)
10293 {
10294 struct drm_device *dev = crtc->base.dev;
10295 struct intel_encoder *encoder;
10296
10297 for_each_intel_encoder(dev, encoder) {
10298 if (encoder->new_crtc != crtc)
10299 continue;
10300
10301 if (!check_single_encoder_cloning(crtc, encoder))
10302 return false;
10303 }
10304
10305 return true;
10306 }
10307
10308 static bool check_digital_port_conflicts(struct drm_device *dev)
10309 {
10310 struct intel_connector *connector;
10311 unsigned int used_ports = 0;
10312
10313 /*
10314 * Walk the connector list instead of the encoder
10315 * list to detect the problem on ddi platforms
10316 * where there's just one encoder per digital port.
10317 */
10318 for_each_intel_connector(dev, connector) {
10319 struct intel_encoder *encoder = connector->new_encoder;
10320
10321 if (!encoder)
10322 continue;
10323
10324 WARN_ON(!encoder->new_crtc);
10325
10326 switch (encoder->type) {
10327 unsigned int port_mask;
10328 case INTEL_OUTPUT_UNKNOWN:
10329 if (WARN_ON(!HAS_DDI(dev)))
10330 break;
10331 case INTEL_OUTPUT_DISPLAYPORT:
10332 case INTEL_OUTPUT_HDMI:
10333 case INTEL_OUTPUT_EDP:
10334 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10335
10336 /* the same port mustn't appear more than once */
10337 if (used_ports & port_mask)
10338 return false;
10339
10340 used_ports |= port_mask;
10341 default:
10342 break;
10343 }
10344 }
10345
10346 return true;
10347 }
10348
10349 static struct intel_crtc_state *
10350 intel_modeset_pipe_config(struct drm_crtc *crtc,
10351 struct drm_framebuffer *fb,
10352 struct drm_display_mode *mode)
10353 {
10354 struct drm_device *dev = crtc->dev;
10355 struct intel_encoder *encoder;
10356 struct intel_crtc_state *pipe_config;
10357 int plane_bpp, ret = -EINVAL;
10358 bool retry = true;
10359
10360 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10361 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10362 return ERR_PTR(-EINVAL);
10363 }
10364
10365 if (!check_digital_port_conflicts(dev)) {
10366 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10367 return ERR_PTR(-EINVAL);
10368 }
10369
10370 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10371 if (!pipe_config)
10372 return ERR_PTR(-ENOMEM);
10373
10374 pipe_config->base.crtc = crtc;
10375 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10376 drm_mode_copy(&pipe_config->base.mode, mode);
10377
10378 pipe_config->cpu_transcoder =
10379 (enum transcoder) to_intel_crtc(crtc)->pipe;
10380 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10381
10382 /*
10383 * Sanitize sync polarity flags based on requested ones. If neither
10384 * positive or negative polarity is requested, treat this as meaning
10385 * negative polarity.
10386 */
10387 if (!(pipe_config->base.adjusted_mode.flags &
10388 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10389 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10390
10391 if (!(pipe_config->base.adjusted_mode.flags &
10392 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10393 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10394
10395 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10396 * plane pixel format and any sink constraints into account. Returns the
10397 * source plane bpp so that dithering can be selected on mismatches
10398 * after encoders and crtc also have had their say. */
10399 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10400 fb, pipe_config);
10401 if (plane_bpp < 0)
10402 goto fail;
10403
10404 /*
10405 * Determine the real pipe dimensions. Note that stereo modes can
10406 * increase the actual pipe size due to the frame doubling and
10407 * insertion of additional space for blanks between the frame. This
10408 * is stored in the crtc timings. We use the requested mode to do this
10409 * computation to clearly distinguish it from the adjusted mode, which
10410 * can be changed by the connectors in the below retry loop.
10411 */
10412 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10413 &pipe_config->pipe_src_w,
10414 &pipe_config->pipe_src_h);
10415
10416 encoder_retry:
10417 /* Ensure the port clock defaults are reset when retrying. */
10418 pipe_config->port_clock = 0;
10419 pipe_config->pixel_multiplier = 1;
10420
10421 /* Fill in default crtc timings, allow encoders to overwrite them. */
10422 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10423 CRTC_STEREO_DOUBLE);
10424
10425 /* Pass our mode to the connectors and the CRTC to give them a chance to
10426 * adjust it according to limitations or connector properties, and also
10427 * a chance to reject the mode entirely.
10428 */
10429 for_each_intel_encoder(dev, encoder) {
10430
10431 if (&encoder->new_crtc->base != crtc)
10432 continue;
10433
10434 if (!(encoder->compute_config(encoder, pipe_config))) {
10435 DRM_DEBUG_KMS("Encoder config failure\n");
10436 goto fail;
10437 }
10438 }
10439
10440 /* Set default port clock if not overwritten by the encoder. Needs to be
10441 * done afterwards in case the encoder adjusts the mode. */
10442 if (!pipe_config->port_clock)
10443 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10444 * pipe_config->pixel_multiplier;
10445
10446 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10447 if (ret < 0) {
10448 DRM_DEBUG_KMS("CRTC fixup failed\n");
10449 goto fail;
10450 }
10451
10452 if (ret == RETRY) {
10453 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10454 ret = -EINVAL;
10455 goto fail;
10456 }
10457
10458 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10459 retry = false;
10460 goto encoder_retry;
10461 }
10462
10463 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10464 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10465 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10466
10467 return pipe_config;
10468 fail:
10469 kfree(pipe_config);
10470 return ERR_PTR(ret);
10471 }
10472
10473 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10474 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10475 static void
10476 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10477 unsigned *prepare_pipes, unsigned *disable_pipes)
10478 {
10479 struct intel_crtc *intel_crtc;
10480 struct drm_device *dev = crtc->dev;
10481 struct intel_encoder *encoder;
10482 struct intel_connector *connector;
10483 struct drm_crtc *tmp_crtc;
10484
10485 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10486
10487 /* Check which crtcs have changed outputs connected to them, these need
10488 * to be part of the prepare_pipes mask. We don't (yet) support global
10489 * modeset across multiple crtcs, so modeset_pipes will only have one
10490 * bit set at most. */
10491 for_each_intel_connector(dev, connector) {
10492 if (connector->base.encoder == &connector->new_encoder->base)
10493 continue;
10494
10495 if (connector->base.encoder) {
10496 tmp_crtc = connector->base.encoder->crtc;
10497
10498 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10499 }
10500
10501 if (connector->new_encoder)
10502 *prepare_pipes |=
10503 1 << connector->new_encoder->new_crtc->pipe;
10504 }
10505
10506 for_each_intel_encoder(dev, encoder) {
10507 if (encoder->base.crtc == &encoder->new_crtc->base)
10508 continue;
10509
10510 if (encoder->base.crtc) {
10511 tmp_crtc = encoder->base.crtc;
10512
10513 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10514 }
10515
10516 if (encoder->new_crtc)
10517 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10518 }
10519
10520 /* Check for pipes that will be enabled/disabled ... */
10521 for_each_intel_crtc(dev, intel_crtc) {
10522 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10523 continue;
10524
10525 if (!intel_crtc->new_enabled)
10526 *disable_pipes |= 1 << intel_crtc->pipe;
10527 else
10528 *prepare_pipes |= 1 << intel_crtc->pipe;
10529 }
10530
10531
10532 /* set_mode is also used to update properties on life display pipes. */
10533 intel_crtc = to_intel_crtc(crtc);
10534 if (intel_crtc->new_enabled)
10535 *prepare_pipes |= 1 << intel_crtc->pipe;
10536
10537 /*
10538 * For simplicity do a full modeset on any pipe where the output routing
10539 * changed. We could be more clever, but that would require us to be
10540 * more careful with calling the relevant encoder->mode_set functions.
10541 */
10542 if (*prepare_pipes)
10543 *modeset_pipes = *prepare_pipes;
10544
10545 /* ... and mask these out. */
10546 *modeset_pipes &= ~(*disable_pipes);
10547 *prepare_pipes &= ~(*disable_pipes);
10548
10549 /*
10550 * HACK: We don't (yet) fully support global modesets. intel_set_config
10551 * obies this rule, but the modeset restore mode of
10552 * intel_modeset_setup_hw_state does not.
10553 */
10554 *modeset_pipes &= 1 << intel_crtc->pipe;
10555 *prepare_pipes &= 1 << intel_crtc->pipe;
10556
10557 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10558 *modeset_pipes, *prepare_pipes, *disable_pipes);
10559 }
10560
10561 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10562 {
10563 struct drm_encoder *encoder;
10564 struct drm_device *dev = crtc->dev;
10565
10566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10567 if (encoder->crtc == crtc)
10568 return true;
10569
10570 return false;
10571 }
10572
10573 static void
10574 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10575 {
10576 struct drm_i915_private *dev_priv = dev->dev_private;
10577 struct intel_encoder *intel_encoder;
10578 struct intel_crtc *intel_crtc;
10579 struct drm_connector *connector;
10580
10581 intel_shared_dpll_commit(dev_priv);
10582
10583 for_each_intel_encoder(dev, intel_encoder) {
10584 if (!intel_encoder->base.crtc)
10585 continue;
10586
10587 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10588
10589 if (prepare_pipes & (1 << intel_crtc->pipe))
10590 intel_encoder->connectors_active = false;
10591 }
10592
10593 intel_modeset_commit_output_state(dev);
10594
10595 /* Double check state. */
10596 for_each_intel_crtc(dev, intel_crtc) {
10597 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10598 WARN_ON(intel_crtc->new_config &&
10599 intel_crtc->new_config != intel_crtc->config);
10600 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10601 }
10602
10603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10604 if (!connector->encoder || !connector->encoder->crtc)
10605 continue;
10606
10607 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10608
10609 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10610 struct drm_property *dpms_property =
10611 dev->mode_config.dpms_property;
10612
10613 connector->dpms = DRM_MODE_DPMS_ON;
10614 drm_object_property_set_value(&connector->base,
10615 dpms_property,
10616 DRM_MODE_DPMS_ON);
10617
10618 intel_encoder = to_intel_encoder(connector->encoder);
10619 intel_encoder->connectors_active = true;
10620 }
10621 }
10622
10623 }
10624
10625 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10626 {
10627 int diff;
10628
10629 if (clock1 == clock2)
10630 return true;
10631
10632 if (!clock1 || !clock2)
10633 return false;
10634
10635 diff = abs(clock1 - clock2);
10636
10637 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10638 return true;
10639
10640 return false;
10641 }
10642
10643 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10644 list_for_each_entry((intel_crtc), \
10645 &(dev)->mode_config.crtc_list, \
10646 base.head) \
10647 if (mask & (1 <<(intel_crtc)->pipe))
10648
10649 static bool
10650 intel_pipe_config_compare(struct drm_device *dev,
10651 struct intel_crtc_state *current_config,
10652 struct intel_crtc_state *pipe_config)
10653 {
10654 #define PIPE_CONF_CHECK_X(name) \
10655 if (current_config->name != pipe_config->name) { \
10656 DRM_ERROR("mismatch in " #name " " \
10657 "(expected 0x%08x, found 0x%08x)\n", \
10658 current_config->name, \
10659 pipe_config->name); \
10660 return false; \
10661 }
10662
10663 #define PIPE_CONF_CHECK_I(name) \
10664 if (current_config->name != pipe_config->name) { \
10665 DRM_ERROR("mismatch in " #name " " \
10666 "(expected %i, found %i)\n", \
10667 current_config->name, \
10668 pipe_config->name); \
10669 return false; \
10670 }
10671
10672 /* This is required for BDW+ where there is only one set of registers for
10673 * switching between high and low RR.
10674 * This macro can be used whenever a comparison has to be made between one
10675 * hw state and multiple sw state variables.
10676 */
10677 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10678 if ((current_config->name != pipe_config->name) && \
10679 (current_config->alt_name != pipe_config->name)) { \
10680 DRM_ERROR("mismatch in " #name " " \
10681 "(expected %i or %i, found %i)\n", \
10682 current_config->name, \
10683 current_config->alt_name, \
10684 pipe_config->name); \
10685 return false; \
10686 }
10687
10688 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10689 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10690 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10691 "(expected %i, found %i)\n", \
10692 current_config->name & (mask), \
10693 pipe_config->name & (mask)); \
10694 return false; \
10695 }
10696
10697 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10698 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10699 DRM_ERROR("mismatch in " #name " " \
10700 "(expected %i, found %i)\n", \
10701 current_config->name, \
10702 pipe_config->name); \
10703 return false; \
10704 }
10705
10706 #define PIPE_CONF_QUIRK(quirk) \
10707 ((current_config->quirks | pipe_config->quirks) & (quirk))
10708
10709 PIPE_CONF_CHECK_I(cpu_transcoder);
10710
10711 PIPE_CONF_CHECK_I(has_pch_encoder);
10712 PIPE_CONF_CHECK_I(fdi_lanes);
10713 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10714 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10715 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10716 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10717 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10718
10719 PIPE_CONF_CHECK_I(has_dp_encoder);
10720
10721 if (INTEL_INFO(dev)->gen < 8) {
10722 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10723 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10724 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10725 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10726 PIPE_CONF_CHECK_I(dp_m_n.tu);
10727
10728 if (current_config->has_drrs) {
10729 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10730 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10731 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10732 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10733 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10734 }
10735 } else {
10736 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10737 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10738 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10739 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10740 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10741 }
10742
10743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10745 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10746 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10747 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10748 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10749
10750 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10751 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10752 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10753 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10754 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10755 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10756
10757 PIPE_CONF_CHECK_I(pixel_multiplier);
10758 PIPE_CONF_CHECK_I(has_hdmi_sink);
10759 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10760 IS_VALLEYVIEW(dev))
10761 PIPE_CONF_CHECK_I(limited_color_range);
10762 PIPE_CONF_CHECK_I(has_infoframe);
10763
10764 PIPE_CONF_CHECK_I(has_audio);
10765
10766 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10767 DRM_MODE_FLAG_INTERLACE);
10768
10769 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10770 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10771 DRM_MODE_FLAG_PHSYNC);
10772 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10773 DRM_MODE_FLAG_NHSYNC);
10774 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10775 DRM_MODE_FLAG_PVSYNC);
10776 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10777 DRM_MODE_FLAG_NVSYNC);
10778 }
10779
10780 PIPE_CONF_CHECK_I(pipe_src_w);
10781 PIPE_CONF_CHECK_I(pipe_src_h);
10782
10783 /*
10784 * FIXME: BIOS likes to set up a cloned config with lvds+external
10785 * screen. Since we don't yet re-compute the pipe config when moving
10786 * just the lvds port away to another pipe the sw tracking won't match.
10787 *
10788 * Proper atomic modesets with recomputed global state will fix this.
10789 * Until then just don't check gmch state for inherited modes.
10790 */
10791 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10792 PIPE_CONF_CHECK_I(gmch_pfit.control);
10793 /* pfit ratios are autocomputed by the hw on gen4+ */
10794 if (INTEL_INFO(dev)->gen < 4)
10795 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10796 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10797 }
10798
10799 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10800 if (current_config->pch_pfit.enabled) {
10801 PIPE_CONF_CHECK_I(pch_pfit.pos);
10802 PIPE_CONF_CHECK_I(pch_pfit.size);
10803 }
10804
10805 /* BDW+ don't expose a synchronous way to read the state */
10806 if (IS_HASWELL(dev))
10807 PIPE_CONF_CHECK_I(ips_enabled);
10808
10809 PIPE_CONF_CHECK_I(double_wide);
10810
10811 PIPE_CONF_CHECK_X(ddi_pll_sel);
10812
10813 PIPE_CONF_CHECK_I(shared_dpll);
10814 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10815 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10816 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10817 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10818 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10819 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10820 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10821 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10822
10823 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10824 PIPE_CONF_CHECK_I(pipe_bpp);
10825
10826 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10827 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10828
10829 #undef PIPE_CONF_CHECK_X
10830 #undef PIPE_CONF_CHECK_I
10831 #undef PIPE_CONF_CHECK_I_ALT
10832 #undef PIPE_CONF_CHECK_FLAGS
10833 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10834 #undef PIPE_CONF_QUIRK
10835
10836 return true;
10837 }
10838
10839 static void check_wm_state(struct drm_device *dev)
10840 {
10841 struct drm_i915_private *dev_priv = dev->dev_private;
10842 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10843 struct intel_crtc *intel_crtc;
10844 int plane;
10845
10846 if (INTEL_INFO(dev)->gen < 9)
10847 return;
10848
10849 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10850 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10851
10852 for_each_intel_crtc(dev, intel_crtc) {
10853 struct skl_ddb_entry *hw_entry, *sw_entry;
10854 const enum pipe pipe = intel_crtc->pipe;
10855
10856 if (!intel_crtc->active)
10857 continue;
10858
10859 /* planes */
10860 for_each_plane(dev_priv, pipe, plane) {
10861 hw_entry = &hw_ddb.plane[pipe][plane];
10862 sw_entry = &sw_ddb->plane[pipe][plane];
10863
10864 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10865 continue;
10866
10867 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10868 "(expected (%u,%u), found (%u,%u))\n",
10869 pipe_name(pipe), plane + 1,
10870 sw_entry->start, sw_entry->end,
10871 hw_entry->start, hw_entry->end);
10872 }
10873
10874 /* cursor */
10875 hw_entry = &hw_ddb.cursor[pipe];
10876 sw_entry = &sw_ddb->cursor[pipe];
10877
10878 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10879 continue;
10880
10881 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10882 "(expected (%u,%u), found (%u,%u))\n",
10883 pipe_name(pipe),
10884 sw_entry->start, sw_entry->end,
10885 hw_entry->start, hw_entry->end);
10886 }
10887 }
10888
10889 static void
10890 check_connector_state(struct drm_device *dev)
10891 {
10892 struct intel_connector *connector;
10893
10894 for_each_intel_connector(dev, connector) {
10895 /* This also checks the encoder/connector hw state with the
10896 * ->get_hw_state callbacks. */
10897 intel_connector_check_state(connector);
10898
10899 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10900 "connector's staged encoder doesn't match current encoder\n");
10901 }
10902 }
10903
10904 static void
10905 check_encoder_state(struct drm_device *dev)
10906 {
10907 struct intel_encoder *encoder;
10908 struct intel_connector *connector;
10909
10910 for_each_intel_encoder(dev, encoder) {
10911 bool enabled = false;
10912 bool active = false;
10913 enum pipe pipe, tracked_pipe;
10914
10915 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10916 encoder->base.base.id,
10917 encoder->base.name);
10918
10919 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10920 "encoder's stage crtc doesn't match current crtc\n");
10921 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10922 "encoder's active_connectors set, but no crtc\n");
10923
10924 for_each_intel_connector(dev, connector) {
10925 if (connector->base.encoder != &encoder->base)
10926 continue;
10927 enabled = true;
10928 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10929 active = true;
10930 }
10931 /*
10932 * for MST connectors if we unplug the connector is gone
10933 * away but the encoder is still connected to a crtc
10934 * until a modeset happens in response to the hotplug.
10935 */
10936 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10937 continue;
10938
10939 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10940 "encoder's enabled state mismatch "
10941 "(expected %i, found %i)\n",
10942 !!encoder->base.crtc, enabled);
10943 I915_STATE_WARN(active && !encoder->base.crtc,
10944 "active encoder with no crtc\n");
10945
10946 I915_STATE_WARN(encoder->connectors_active != active,
10947 "encoder's computed active state doesn't match tracked active state "
10948 "(expected %i, found %i)\n", active, encoder->connectors_active);
10949
10950 active = encoder->get_hw_state(encoder, &pipe);
10951 I915_STATE_WARN(active != encoder->connectors_active,
10952 "encoder's hw state doesn't match sw tracking "
10953 "(expected %i, found %i)\n",
10954 encoder->connectors_active, active);
10955
10956 if (!encoder->base.crtc)
10957 continue;
10958
10959 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10960 I915_STATE_WARN(active && pipe != tracked_pipe,
10961 "active encoder's pipe doesn't match"
10962 "(expected %i, found %i)\n",
10963 tracked_pipe, pipe);
10964
10965 }
10966 }
10967
10968 static void
10969 check_crtc_state(struct drm_device *dev)
10970 {
10971 struct drm_i915_private *dev_priv = dev->dev_private;
10972 struct intel_crtc *crtc;
10973 struct intel_encoder *encoder;
10974 struct intel_crtc_state pipe_config;
10975
10976 for_each_intel_crtc(dev, crtc) {
10977 bool enabled = false;
10978 bool active = false;
10979
10980 memset(&pipe_config, 0, sizeof(pipe_config));
10981
10982 DRM_DEBUG_KMS("[CRTC:%d]\n",
10983 crtc->base.base.id);
10984
10985 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
10986 "active crtc, but not enabled in sw tracking\n");
10987
10988 for_each_intel_encoder(dev, encoder) {
10989 if (encoder->base.crtc != &crtc->base)
10990 continue;
10991 enabled = true;
10992 if (encoder->connectors_active)
10993 active = true;
10994 }
10995
10996 I915_STATE_WARN(active != crtc->active,
10997 "crtc's computed active state doesn't match tracked active state "
10998 "(expected %i, found %i)\n", active, crtc->active);
10999 I915_STATE_WARN(enabled != crtc->base.state->enable,
11000 "crtc's computed enabled state doesn't match tracked enabled state "
11001 "(expected %i, found %i)\n", enabled,
11002 crtc->base.state->enable);
11003
11004 active = dev_priv->display.get_pipe_config(crtc,
11005 &pipe_config);
11006
11007 /* hw state is inconsistent with the pipe quirk */
11008 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11009 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11010 active = crtc->active;
11011
11012 for_each_intel_encoder(dev, encoder) {
11013 enum pipe pipe;
11014 if (encoder->base.crtc != &crtc->base)
11015 continue;
11016 if (encoder->get_hw_state(encoder, &pipe))
11017 encoder->get_config(encoder, &pipe_config);
11018 }
11019
11020 I915_STATE_WARN(crtc->active != active,
11021 "crtc active state doesn't match with hw state "
11022 "(expected %i, found %i)\n", crtc->active, active);
11023
11024 if (active &&
11025 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11026 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11027 intel_dump_pipe_config(crtc, &pipe_config,
11028 "[hw state]");
11029 intel_dump_pipe_config(crtc, crtc->config,
11030 "[sw state]");
11031 }
11032 }
11033 }
11034
11035 static void
11036 check_shared_dpll_state(struct drm_device *dev)
11037 {
11038 struct drm_i915_private *dev_priv = dev->dev_private;
11039 struct intel_crtc *crtc;
11040 struct intel_dpll_hw_state dpll_hw_state;
11041 int i;
11042
11043 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11044 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11045 int enabled_crtcs = 0, active_crtcs = 0;
11046 bool active;
11047
11048 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11049
11050 DRM_DEBUG_KMS("%s\n", pll->name);
11051
11052 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11053
11054 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11055 "more active pll users than references: %i vs %i\n",
11056 pll->active, hweight32(pll->config.crtc_mask));
11057 I915_STATE_WARN(pll->active && !pll->on,
11058 "pll in active use but not on in sw tracking\n");
11059 I915_STATE_WARN(pll->on && !pll->active,
11060 "pll in on but not on in use in sw tracking\n");
11061 I915_STATE_WARN(pll->on != active,
11062 "pll on state mismatch (expected %i, found %i)\n",
11063 pll->on, active);
11064
11065 for_each_intel_crtc(dev, crtc) {
11066 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11067 enabled_crtcs++;
11068 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11069 active_crtcs++;
11070 }
11071 I915_STATE_WARN(pll->active != active_crtcs,
11072 "pll active crtcs mismatch (expected %i, found %i)\n",
11073 pll->active, active_crtcs);
11074 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11075 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11076 hweight32(pll->config.crtc_mask), enabled_crtcs);
11077
11078 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11079 sizeof(dpll_hw_state)),
11080 "pll hw state mismatch\n");
11081 }
11082 }
11083
11084 void
11085 intel_modeset_check_state(struct drm_device *dev)
11086 {
11087 check_wm_state(dev);
11088 check_connector_state(dev);
11089 check_encoder_state(dev);
11090 check_crtc_state(dev);
11091 check_shared_dpll_state(dev);
11092 }
11093
11094 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11095 int dotclock)
11096 {
11097 /*
11098 * FDI already provided one idea for the dotclock.
11099 * Yell if the encoder disagrees.
11100 */
11101 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11102 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11103 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11104 }
11105
11106 static void update_scanline_offset(struct intel_crtc *crtc)
11107 {
11108 struct drm_device *dev = crtc->base.dev;
11109
11110 /*
11111 * The scanline counter increments at the leading edge of hsync.
11112 *
11113 * On most platforms it starts counting from vtotal-1 on the
11114 * first active line. That means the scanline counter value is
11115 * always one less than what we would expect. Ie. just after
11116 * start of vblank, which also occurs at start of hsync (on the
11117 * last active line), the scanline counter will read vblank_start-1.
11118 *
11119 * On gen2 the scanline counter starts counting from 1 instead
11120 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11121 * to keep the value positive), instead of adding one.
11122 *
11123 * On HSW+ the behaviour of the scanline counter depends on the output
11124 * type. For DP ports it behaves like most other platforms, but on HDMI
11125 * there's an extra 1 line difference. So we need to add two instead of
11126 * one to the value.
11127 */
11128 if (IS_GEN2(dev)) {
11129 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11130 int vtotal;
11131
11132 vtotal = mode->crtc_vtotal;
11133 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11134 vtotal /= 2;
11135
11136 crtc->scanline_offset = vtotal - 1;
11137 } else if (HAS_DDI(dev) &&
11138 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11139 crtc->scanline_offset = 2;
11140 } else
11141 crtc->scanline_offset = 1;
11142 }
11143
11144 static struct intel_crtc_state *
11145 intel_modeset_compute_config(struct drm_crtc *crtc,
11146 struct drm_display_mode *mode,
11147 struct drm_framebuffer *fb,
11148 unsigned *modeset_pipes,
11149 unsigned *prepare_pipes,
11150 unsigned *disable_pipes)
11151 {
11152 struct intel_crtc_state *pipe_config = NULL;
11153
11154 intel_modeset_affected_pipes(crtc, modeset_pipes,
11155 prepare_pipes, disable_pipes);
11156
11157 if ((*modeset_pipes) == 0)
11158 goto out;
11159
11160 /*
11161 * Note this needs changes when we start tracking multiple modes
11162 * and crtcs. At that point we'll need to compute the whole config
11163 * (i.e. one pipe_config for each crtc) rather than just the one
11164 * for this crtc.
11165 */
11166 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11167 if (IS_ERR(pipe_config)) {
11168 goto out;
11169 }
11170 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11171 "[modeset]");
11172
11173 out:
11174 return pipe_config;
11175 }
11176
11177 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11178 unsigned modeset_pipes,
11179 unsigned disable_pipes)
11180 {
11181 struct drm_i915_private *dev_priv = to_i915(dev);
11182 unsigned clear_pipes = modeset_pipes | disable_pipes;
11183 struct intel_crtc *intel_crtc;
11184 int ret = 0;
11185
11186 if (!dev_priv->display.crtc_compute_clock)
11187 return 0;
11188
11189 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11190 if (ret)
11191 goto done;
11192
11193 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11194 struct intel_crtc_state *state = intel_crtc->new_config;
11195 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11196 state);
11197 if (ret) {
11198 intel_shared_dpll_abort_config(dev_priv);
11199 goto done;
11200 }
11201 }
11202
11203 done:
11204 return ret;
11205 }
11206
11207 static int __intel_set_mode(struct drm_crtc *crtc,
11208 struct drm_display_mode *mode,
11209 int x, int y, struct drm_framebuffer *fb,
11210 struct intel_crtc_state *pipe_config,
11211 unsigned modeset_pipes,
11212 unsigned prepare_pipes,
11213 unsigned disable_pipes)
11214 {
11215 struct drm_device *dev = crtc->dev;
11216 struct drm_i915_private *dev_priv = dev->dev_private;
11217 struct drm_display_mode *saved_mode;
11218 struct intel_crtc *intel_crtc;
11219 int ret = 0;
11220
11221 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11222 if (!saved_mode)
11223 return -ENOMEM;
11224
11225 *saved_mode = crtc->mode;
11226
11227 if (modeset_pipes)
11228 to_intel_crtc(crtc)->new_config = pipe_config;
11229
11230 /*
11231 * See if the config requires any additional preparation, e.g.
11232 * to adjust global state with pipes off. We need to do this
11233 * here so we can get the modeset_pipe updated config for the new
11234 * mode set on this crtc. For other crtcs we need to use the
11235 * adjusted_mode bits in the crtc directly.
11236 */
11237 if (IS_VALLEYVIEW(dev)) {
11238 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11239
11240 /* may have added more to prepare_pipes than we should */
11241 prepare_pipes &= ~disable_pipes;
11242 }
11243
11244 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11245 if (ret)
11246 goto done;
11247
11248 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11249 intel_crtc_disable(&intel_crtc->base);
11250
11251 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11252 if (intel_crtc->base.state->enable)
11253 dev_priv->display.crtc_disable(&intel_crtc->base);
11254 }
11255
11256 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11257 * to set it here already despite that we pass it down the callchain.
11258 *
11259 * Note we'll need to fix this up when we start tracking multiple
11260 * pipes; here we assume a single modeset_pipe and only track the
11261 * single crtc and mode.
11262 */
11263 if (modeset_pipes) {
11264 crtc->mode = *mode;
11265 /* mode_set/enable/disable functions rely on a correct pipe
11266 * config. */
11267 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11268
11269 /*
11270 * Calculate and store various constants which
11271 * are later needed by vblank and swap-completion
11272 * timestamping. They are derived from true hwmode.
11273 */
11274 drm_calc_timestamping_constants(crtc,
11275 &pipe_config->base.adjusted_mode);
11276 }
11277
11278 /* Only after disabling all output pipelines that will be changed can we
11279 * update the the output configuration. */
11280 intel_modeset_update_state(dev, prepare_pipes);
11281
11282 modeset_update_crtc_power_domains(dev);
11283
11284 /* Set up the DPLL and any encoders state that needs to adjust or depend
11285 * on the DPLL.
11286 */
11287 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11288 struct drm_plane *primary = intel_crtc->base.primary;
11289 int vdisplay, hdisplay;
11290
11291 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11292 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11293 fb, 0, 0,
11294 hdisplay, vdisplay,
11295 x << 16, y << 16,
11296 hdisplay << 16, vdisplay << 16);
11297 }
11298
11299 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11300 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11301 update_scanline_offset(intel_crtc);
11302
11303 dev_priv->display.crtc_enable(&intel_crtc->base);
11304 }
11305
11306 /* FIXME: add subpixel order */
11307 done:
11308 if (ret && crtc->state->enable)
11309 crtc->mode = *saved_mode;
11310
11311 kfree(saved_mode);
11312 return ret;
11313 }
11314
11315 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11316 struct drm_display_mode *mode,
11317 int x, int y, struct drm_framebuffer *fb,
11318 struct intel_crtc_state *pipe_config,
11319 unsigned modeset_pipes,
11320 unsigned prepare_pipes,
11321 unsigned disable_pipes)
11322 {
11323 int ret;
11324
11325 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11326 prepare_pipes, disable_pipes);
11327
11328 if (ret == 0)
11329 intel_modeset_check_state(crtc->dev);
11330
11331 return ret;
11332 }
11333
11334 static int intel_set_mode(struct drm_crtc *crtc,
11335 struct drm_display_mode *mode,
11336 int x, int y, struct drm_framebuffer *fb)
11337 {
11338 struct intel_crtc_state *pipe_config;
11339 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11340
11341 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11342 &modeset_pipes,
11343 &prepare_pipes,
11344 &disable_pipes);
11345
11346 if (IS_ERR(pipe_config))
11347 return PTR_ERR(pipe_config);
11348
11349 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11350 modeset_pipes, prepare_pipes,
11351 disable_pipes);
11352 }
11353
11354 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11355 {
11356 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11357 }
11358
11359 #undef for_each_intel_crtc_masked
11360
11361 static void intel_set_config_free(struct intel_set_config *config)
11362 {
11363 if (!config)
11364 return;
11365
11366 kfree(config->save_connector_encoders);
11367 kfree(config->save_encoder_crtcs);
11368 kfree(config->save_crtc_enabled);
11369 kfree(config);
11370 }
11371
11372 static int intel_set_config_save_state(struct drm_device *dev,
11373 struct intel_set_config *config)
11374 {
11375 struct drm_crtc *crtc;
11376 struct drm_encoder *encoder;
11377 struct drm_connector *connector;
11378 int count;
11379
11380 config->save_crtc_enabled =
11381 kcalloc(dev->mode_config.num_crtc,
11382 sizeof(bool), GFP_KERNEL);
11383 if (!config->save_crtc_enabled)
11384 return -ENOMEM;
11385
11386 config->save_encoder_crtcs =
11387 kcalloc(dev->mode_config.num_encoder,
11388 sizeof(struct drm_crtc *), GFP_KERNEL);
11389 if (!config->save_encoder_crtcs)
11390 return -ENOMEM;
11391
11392 config->save_connector_encoders =
11393 kcalloc(dev->mode_config.num_connector,
11394 sizeof(struct drm_encoder *), GFP_KERNEL);
11395 if (!config->save_connector_encoders)
11396 return -ENOMEM;
11397
11398 /* Copy data. Note that driver private data is not affected.
11399 * Should anything bad happen only the expected state is
11400 * restored, not the drivers personal bookkeeping.
11401 */
11402 count = 0;
11403 for_each_crtc(dev, crtc) {
11404 config->save_crtc_enabled[count++] = crtc->state->enable;
11405 }
11406
11407 count = 0;
11408 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11409 config->save_encoder_crtcs[count++] = encoder->crtc;
11410 }
11411
11412 count = 0;
11413 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11414 config->save_connector_encoders[count++] = connector->encoder;
11415 }
11416
11417 return 0;
11418 }
11419
11420 static void intel_set_config_restore_state(struct drm_device *dev,
11421 struct intel_set_config *config)
11422 {
11423 struct intel_crtc *crtc;
11424 struct intel_encoder *encoder;
11425 struct intel_connector *connector;
11426 int count;
11427
11428 count = 0;
11429 for_each_intel_crtc(dev, crtc) {
11430 crtc->new_enabled = config->save_crtc_enabled[count++];
11431
11432 if (crtc->new_enabled)
11433 crtc->new_config = crtc->config;
11434 else
11435 crtc->new_config = NULL;
11436 }
11437
11438 count = 0;
11439 for_each_intel_encoder(dev, encoder) {
11440 encoder->new_crtc =
11441 to_intel_crtc(config->save_encoder_crtcs[count++]);
11442 }
11443
11444 count = 0;
11445 for_each_intel_connector(dev, connector) {
11446 connector->new_encoder =
11447 to_intel_encoder(config->save_connector_encoders[count++]);
11448 }
11449 }
11450
11451 static bool
11452 is_crtc_connector_off(struct drm_mode_set *set)
11453 {
11454 int i;
11455
11456 if (set->num_connectors == 0)
11457 return false;
11458
11459 if (WARN_ON(set->connectors == NULL))
11460 return false;
11461
11462 for (i = 0; i < set->num_connectors; i++)
11463 if (set->connectors[i]->encoder &&
11464 set->connectors[i]->encoder->crtc == set->crtc &&
11465 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11466 return true;
11467
11468 return false;
11469 }
11470
11471 static void
11472 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11473 struct intel_set_config *config)
11474 {
11475
11476 /* We should be able to check here if the fb has the same properties
11477 * and then just flip_or_move it */
11478 if (is_crtc_connector_off(set)) {
11479 config->mode_changed = true;
11480 } else if (set->crtc->primary->fb != set->fb) {
11481 /*
11482 * If we have no fb, we can only flip as long as the crtc is
11483 * active, otherwise we need a full mode set. The crtc may
11484 * be active if we've only disabled the primary plane, or
11485 * in fastboot situations.
11486 */
11487 if (set->crtc->primary->fb == NULL) {
11488 struct intel_crtc *intel_crtc =
11489 to_intel_crtc(set->crtc);
11490
11491 if (intel_crtc->active) {
11492 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11493 config->fb_changed = true;
11494 } else {
11495 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11496 config->mode_changed = true;
11497 }
11498 } else if (set->fb == NULL) {
11499 config->mode_changed = true;
11500 } else if (set->fb->pixel_format !=
11501 set->crtc->primary->fb->pixel_format) {
11502 config->mode_changed = true;
11503 } else {
11504 config->fb_changed = true;
11505 }
11506 }
11507
11508 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11509 config->fb_changed = true;
11510
11511 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11512 DRM_DEBUG_KMS("modes are different, full mode set\n");
11513 drm_mode_debug_printmodeline(&set->crtc->mode);
11514 drm_mode_debug_printmodeline(set->mode);
11515 config->mode_changed = true;
11516 }
11517
11518 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11519 set->crtc->base.id, config->mode_changed, config->fb_changed);
11520 }
11521
11522 static int
11523 intel_modeset_stage_output_state(struct drm_device *dev,
11524 struct drm_mode_set *set,
11525 struct intel_set_config *config)
11526 {
11527 struct intel_connector *connector;
11528 struct intel_encoder *encoder;
11529 struct intel_crtc *crtc;
11530 int ro;
11531
11532 /* The upper layers ensure that we either disable a crtc or have a list
11533 * of connectors. For paranoia, double-check this. */
11534 WARN_ON(!set->fb && (set->num_connectors != 0));
11535 WARN_ON(set->fb && (set->num_connectors == 0));
11536
11537 for_each_intel_connector(dev, connector) {
11538 /* Otherwise traverse passed in connector list and get encoders
11539 * for them. */
11540 for (ro = 0; ro < set->num_connectors; ro++) {
11541 if (set->connectors[ro] == &connector->base) {
11542 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11543 break;
11544 }
11545 }
11546
11547 /* If we disable the crtc, disable all its connectors. Also, if
11548 * the connector is on the changing crtc but not on the new
11549 * connector list, disable it. */
11550 if ((!set->fb || ro == set->num_connectors) &&
11551 connector->base.encoder &&
11552 connector->base.encoder->crtc == set->crtc) {
11553 connector->new_encoder = NULL;
11554
11555 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11556 connector->base.base.id,
11557 connector->base.name);
11558 }
11559
11560
11561 if (&connector->new_encoder->base != connector->base.encoder) {
11562 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11563 connector->base.base.id,
11564 connector->base.name);
11565 config->mode_changed = true;
11566 }
11567 }
11568 /* connector->new_encoder is now updated for all connectors. */
11569
11570 /* Update crtc of enabled connectors. */
11571 for_each_intel_connector(dev, connector) {
11572 struct drm_crtc *new_crtc;
11573
11574 if (!connector->new_encoder)
11575 continue;
11576
11577 new_crtc = connector->new_encoder->base.crtc;
11578
11579 for (ro = 0; ro < set->num_connectors; ro++) {
11580 if (set->connectors[ro] == &connector->base)
11581 new_crtc = set->crtc;
11582 }
11583
11584 /* Make sure the new CRTC will work with the encoder */
11585 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11586 new_crtc)) {
11587 return -EINVAL;
11588 }
11589 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11590
11591 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11592 connector->base.base.id,
11593 connector->base.name,
11594 new_crtc->base.id);
11595 }
11596
11597 /* Check for any encoders that needs to be disabled. */
11598 for_each_intel_encoder(dev, encoder) {
11599 int num_connectors = 0;
11600 for_each_intel_connector(dev, connector) {
11601 if (connector->new_encoder == encoder) {
11602 WARN_ON(!connector->new_encoder->new_crtc);
11603 num_connectors++;
11604 }
11605 }
11606
11607 if (num_connectors == 0)
11608 encoder->new_crtc = NULL;
11609 else if (num_connectors > 1)
11610 return -EINVAL;
11611
11612 /* Only now check for crtc changes so we don't miss encoders
11613 * that will be disabled. */
11614 if (&encoder->new_crtc->base != encoder->base.crtc) {
11615 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11616 encoder->base.base.id,
11617 encoder->base.name);
11618 config->mode_changed = true;
11619 }
11620 }
11621 /* Now we've also updated encoder->new_crtc for all encoders. */
11622 for_each_intel_connector(dev, connector) {
11623 if (connector->new_encoder)
11624 if (connector->new_encoder != connector->encoder)
11625 connector->encoder = connector->new_encoder;
11626 }
11627 for_each_intel_crtc(dev, crtc) {
11628 crtc->new_enabled = false;
11629
11630 for_each_intel_encoder(dev, encoder) {
11631 if (encoder->new_crtc == crtc) {
11632 crtc->new_enabled = true;
11633 break;
11634 }
11635 }
11636
11637 if (crtc->new_enabled != crtc->base.state->enable) {
11638 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11639 crtc->base.base.id,
11640 crtc->new_enabled ? "en" : "dis");
11641 config->mode_changed = true;
11642 }
11643
11644 if (crtc->new_enabled)
11645 crtc->new_config = crtc->config;
11646 else
11647 crtc->new_config = NULL;
11648 }
11649
11650 return 0;
11651 }
11652
11653 static void disable_crtc_nofb(struct intel_crtc *crtc)
11654 {
11655 struct drm_device *dev = crtc->base.dev;
11656 struct intel_encoder *encoder;
11657 struct intel_connector *connector;
11658
11659 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11660 pipe_name(crtc->pipe));
11661
11662 for_each_intel_connector(dev, connector) {
11663 if (connector->new_encoder &&
11664 connector->new_encoder->new_crtc == crtc)
11665 connector->new_encoder = NULL;
11666 }
11667
11668 for_each_intel_encoder(dev, encoder) {
11669 if (encoder->new_crtc == crtc)
11670 encoder->new_crtc = NULL;
11671 }
11672
11673 crtc->new_enabled = false;
11674 crtc->new_config = NULL;
11675 }
11676
11677 static int intel_crtc_set_config(struct drm_mode_set *set)
11678 {
11679 struct drm_device *dev;
11680 struct drm_mode_set save_set;
11681 struct intel_set_config *config;
11682 struct intel_crtc_state *pipe_config;
11683 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11684 int ret;
11685
11686 BUG_ON(!set);
11687 BUG_ON(!set->crtc);
11688 BUG_ON(!set->crtc->helper_private);
11689
11690 /* Enforce sane interface api - has been abused by the fb helper. */
11691 BUG_ON(!set->mode && set->fb);
11692 BUG_ON(set->fb && set->num_connectors == 0);
11693
11694 if (set->fb) {
11695 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11696 set->crtc->base.id, set->fb->base.id,
11697 (int)set->num_connectors, set->x, set->y);
11698 } else {
11699 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11700 }
11701
11702 dev = set->crtc->dev;
11703
11704 ret = -ENOMEM;
11705 config = kzalloc(sizeof(*config), GFP_KERNEL);
11706 if (!config)
11707 goto out_config;
11708
11709 ret = intel_set_config_save_state(dev, config);
11710 if (ret)
11711 goto out_config;
11712
11713 save_set.crtc = set->crtc;
11714 save_set.mode = &set->crtc->mode;
11715 save_set.x = set->crtc->x;
11716 save_set.y = set->crtc->y;
11717 save_set.fb = set->crtc->primary->fb;
11718
11719 /* Compute whether we need a full modeset, only an fb base update or no
11720 * change at all. In the future we might also check whether only the
11721 * mode changed, e.g. for LVDS where we only change the panel fitter in
11722 * such cases. */
11723 intel_set_config_compute_mode_changes(set, config);
11724
11725 ret = intel_modeset_stage_output_state(dev, set, config);
11726 if (ret)
11727 goto fail;
11728
11729 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11730 set->fb,
11731 &modeset_pipes,
11732 &prepare_pipes,
11733 &disable_pipes);
11734 if (IS_ERR(pipe_config)) {
11735 ret = PTR_ERR(pipe_config);
11736 goto fail;
11737 } else if (pipe_config) {
11738 if (pipe_config->has_audio !=
11739 to_intel_crtc(set->crtc)->config->has_audio)
11740 config->mode_changed = true;
11741
11742 /*
11743 * Note we have an issue here with infoframes: current code
11744 * only updates them on the full mode set path per hw
11745 * requirements. So here we should be checking for any
11746 * required changes and forcing a mode set.
11747 */
11748 }
11749
11750 /* set_mode will free it in the mode_changed case */
11751 if (!config->mode_changed)
11752 kfree(pipe_config);
11753
11754 intel_update_pipe_size(to_intel_crtc(set->crtc));
11755
11756 if (config->mode_changed) {
11757 ret = intel_set_mode_pipes(set->crtc, set->mode,
11758 set->x, set->y, set->fb, pipe_config,
11759 modeset_pipes, prepare_pipes,
11760 disable_pipes);
11761 } else if (config->fb_changed) {
11762 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11763 struct drm_plane *primary = set->crtc->primary;
11764 int vdisplay, hdisplay;
11765
11766 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11767 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11768 0, 0, hdisplay, vdisplay,
11769 set->x << 16, set->y << 16,
11770 hdisplay << 16, vdisplay << 16);
11771
11772 /*
11773 * We need to make sure the primary plane is re-enabled if it
11774 * has previously been turned off.
11775 */
11776 if (!intel_crtc->primary_enabled && ret == 0) {
11777 WARN_ON(!intel_crtc->active);
11778 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11779 }
11780
11781 /*
11782 * In the fastboot case this may be our only check of the
11783 * state after boot. It would be better to only do it on
11784 * the first update, but we don't have a nice way of doing that
11785 * (and really, set_config isn't used much for high freq page
11786 * flipping, so increasing its cost here shouldn't be a big
11787 * deal).
11788 */
11789 if (i915.fastboot && ret == 0)
11790 intel_modeset_check_state(set->crtc->dev);
11791 }
11792
11793 if (ret) {
11794 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11795 set->crtc->base.id, ret);
11796 fail:
11797 intel_set_config_restore_state(dev, config);
11798
11799 /*
11800 * HACK: if the pipe was on, but we didn't have a framebuffer,
11801 * force the pipe off to avoid oopsing in the modeset code
11802 * due to fb==NULL. This should only happen during boot since
11803 * we don't yet reconstruct the FB from the hardware state.
11804 */
11805 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11806 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11807
11808 /* Try to restore the config */
11809 if (config->mode_changed &&
11810 intel_set_mode(save_set.crtc, save_set.mode,
11811 save_set.x, save_set.y, save_set.fb))
11812 DRM_ERROR("failed to restore config after modeset failure\n");
11813 }
11814
11815 out_config:
11816 intel_set_config_free(config);
11817 return ret;
11818 }
11819
11820 static const struct drm_crtc_funcs intel_crtc_funcs = {
11821 .gamma_set = intel_crtc_gamma_set,
11822 .set_config = intel_crtc_set_config,
11823 .destroy = intel_crtc_destroy,
11824 .page_flip = intel_crtc_page_flip,
11825 .atomic_duplicate_state = intel_crtc_duplicate_state,
11826 .atomic_destroy_state = intel_crtc_destroy_state,
11827 };
11828
11829 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11830 struct intel_shared_dpll *pll,
11831 struct intel_dpll_hw_state *hw_state)
11832 {
11833 uint32_t val;
11834
11835 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11836 return false;
11837
11838 val = I915_READ(PCH_DPLL(pll->id));
11839 hw_state->dpll = val;
11840 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11841 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11842
11843 return val & DPLL_VCO_ENABLE;
11844 }
11845
11846 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11847 struct intel_shared_dpll *pll)
11848 {
11849 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11850 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11851 }
11852
11853 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11854 struct intel_shared_dpll *pll)
11855 {
11856 /* PCH refclock must be enabled first */
11857 ibx_assert_pch_refclk_enabled(dev_priv);
11858
11859 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11860
11861 /* Wait for the clocks to stabilize. */
11862 POSTING_READ(PCH_DPLL(pll->id));
11863 udelay(150);
11864
11865 /* The pixel multiplier can only be updated once the
11866 * DPLL is enabled and the clocks are stable.
11867 *
11868 * So write it again.
11869 */
11870 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11871 POSTING_READ(PCH_DPLL(pll->id));
11872 udelay(200);
11873 }
11874
11875 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11876 struct intel_shared_dpll *pll)
11877 {
11878 struct drm_device *dev = dev_priv->dev;
11879 struct intel_crtc *crtc;
11880
11881 /* Make sure no transcoder isn't still depending on us. */
11882 for_each_intel_crtc(dev, crtc) {
11883 if (intel_crtc_to_shared_dpll(crtc) == pll)
11884 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11885 }
11886
11887 I915_WRITE(PCH_DPLL(pll->id), 0);
11888 POSTING_READ(PCH_DPLL(pll->id));
11889 udelay(200);
11890 }
11891
11892 static char *ibx_pch_dpll_names[] = {
11893 "PCH DPLL A",
11894 "PCH DPLL B",
11895 };
11896
11897 static void ibx_pch_dpll_init(struct drm_device *dev)
11898 {
11899 struct drm_i915_private *dev_priv = dev->dev_private;
11900 int i;
11901
11902 dev_priv->num_shared_dpll = 2;
11903
11904 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11905 dev_priv->shared_dplls[i].id = i;
11906 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11907 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11908 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11909 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11910 dev_priv->shared_dplls[i].get_hw_state =
11911 ibx_pch_dpll_get_hw_state;
11912 }
11913 }
11914
11915 static void intel_shared_dpll_init(struct drm_device *dev)
11916 {
11917 struct drm_i915_private *dev_priv = dev->dev_private;
11918
11919 if (HAS_DDI(dev))
11920 intel_ddi_pll_init(dev);
11921 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11922 ibx_pch_dpll_init(dev);
11923 else
11924 dev_priv->num_shared_dpll = 0;
11925
11926 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11927 }
11928
11929 /**
11930 * intel_prepare_plane_fb - Prepare fb for usage on plane
11931 * @plane: drm plane to prepare for
11932 * @fb: framebuffer to prepare for presentation
11933 *
11934 * Prepares a framebuffer for usage on a display plane. Generally this
11935 * involves pinning the underlying object and updating the frontbuffer tracking
11936 * bits. Some older platforms need special physical address handling for
11937 * cursor planes.
11938 *
11939 * Returns 0 on success, negative error code on failure.
11940 */
11941 int
11942 intel_prepare_plane_fb(struct drm_plane *plane,
11943 struct drm_framebuffer *fb,
11944 const struct drm_plane_state *new_state)
11945 {
11946 struct drm_device *dev = plane->dev;
11947 struct intel_plane *intel_plane = to_intel_plane(plane);
11948 enum pipe pipe = intel_plane->pipe;
11949 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11950 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11951 unsigned frontbuffer_bits = 0;
11952 int ret = 0;
11953
11954 if (!obj)
11955 return 0;
11956
11957 switch (plane->type) {
11958 case DRM_PLANE_TYPE_PRIMARY:
11959 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11960 break;
11961 case DRM_PLANE_TYPE_CURSOR:
11962 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11963 break;
11964 case DRM_PLANE_TYPE_OVERLAY:
11965 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11966 break;
11967 }
11968
11969 mutex_lock(&dev->struct_mutex);
11970
11971 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11972 INTEL_INFO(dev)->cursor_needs_physical) {
11973 int align = IS_I830(dev) ? 16 * 1024 : 256;
11974 ret = i915_gem_object_attach_phys(obj, align);
11975 if (ret)
11976 DRM_DEBUG_KMS("failed to attach phys object\n");
11977 } else {
11978 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11979 }
11980
11981 if (ret == 0)
11982 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
11983
11984 mutex_unlock(&dev->struct_mutex);
11985
11986 return ret;
11987 }
11988
11989 /**
11990 * intel_cleanup_plane_fb - Cleans up an fb after plane use
11991 * @plane: drm plane to clean up for
11992 * @fb: old framebuffer that was on plane
11993 *
11994 * Cleans up a framebuffer that has just been removed from a plane.
11995 */
11996 void
11997 intel_cleanup_plane_fb(struct drm_plane *plane,
11998 struct drm_framebuffer *fb,
11999 const struct drm_plane_state *old_state)
12000 {
12001 struct drm_device *dev = plane->dev;
12002 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12003
12004 if (WARN_ON(!obj))
12005 return;
12006
12007 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12008 !INTEL_INFO(dev)->cursor_needs_physical) {
12009 mutex_lock(&dev->struct_mutex);
12010 intel_unpin_fb_obj(obj);
12011 mutex_unlock(&dev->struct_mutex);
12012 }
12013 }
12014
12015 static int
12016 intel_check_primary_plane(struct drm_plane *plane,
12017 struct intel_plane_state *state)
12018 {
12019 struct drm_device *dev = plane->dev;
12020 struct drm_i915_private *dev_priv = dev->dev_private;
12021 struct drm_crtc *crtc = state->base.crtc;
12022 struct intel_crtc *intel_crtc;
12023 struct drm_framebuffer *fb = state->base.fb;
12024 struct drm_rect *dest = &state->dst;
12025 struct drm_rect *src = &state->src;
12026 const struct drm_rect *clip = &state->clip;
12027 int ret;
12028
12029 crtc = crtc ? crtc : plane->crtc;
12030 intel_crtc = to_intel_crtc(crtc);
12031
12032 ret = drm_plane_helper_check_update(plane, crtc, fb,
12033 src, dest, clip,
12034 DRM_PLANE_HELPER_NO_SCALING,
12035 DRM_PLANE_HELPER_NO_SCALING,
12036 false, true, &state->visible);
12037 if (ret)
12038 return ret;
12039
12040 if (intel_crtc->active) {
12041 intel_crtc->atomic.wait_for_flips = true;
12042
12043 /*
12044 * FBC does not work on some platforms for rotated
12045 * planes, so disable it when rotation is not 0 and
12046 * update it when rotation is set back to 0.
12047 *
12048 * FIXME: This is redundant with the fbc update done in
12049 * the primary plane enable function except that that
12050 * one is done too late. We eventually need to unify
12051 * this.
12052 */
12053 if (intel_crtc->primary_enabled &&
12054 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12055 dev_priv->fbc.crtc == intel_crtc &&
12056 state->base.rotation != BIT(DRM_ROTATE_0)) {
12057 intel_crtc->atomic.disable_fbc = true;
12058 }
12059
12060 if (state->visible) {
12061 /*
12062 * BDW signals flip done immediately if the plane
12063 * is disabled, even if the plane enable is already
12064 * armed to occur at the next vblank :(
12065 */
12066 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12067 intel_crtc->atomic.wait_vblank = true;
12068 }
12069
12070 intel_crtc->atomic.fb_bits |=
12071 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12072
12073 intel_crtc->atomic.update_fbc = true;
12074
12075 /* Update watermarks on tiling changes. */
12076 if (!plane->state->fb || !state->base.fb ||
12077 plane->state->fb->modifier[0] !=
12078 state->base.fb->modifier[0])
12079 intel_crtc->atomic.update_wm = true;
12080 }
12081
12082 return 0;
12083 }
12084
12085 static void
12086 intel_commit_primary_plane(struct drm_plane *plane,
12087 struct intel_plane_state *state)
12088 {
12089 struct drm_crtc *crtc = state->base.crtc;
12090 struct drm_framebuffer *fb = state->base.fb;
12091 struct drm_device *dev = plane->dev;
12092 struct drm_i915_private *dev_priv = dev->dev_private;
12093 struct intel_crtc *intel_crtc;
12094 struct drm_rect *src = &state->src;
12095
12096 crtc = crtc ? crtc : plane->crtc;
12097 intel_crtc = to_intel_crtc(crtc);
12098
12099 plane->fb = fb;
12100 crtc->x = src->x1 >> 16;
12101 crtc->y = src->y1 >> 16;
12102
12103 if (intel_crtc->active) {
12104 if (state->visible) {
12105 /* FIXME: kill this fastboot hack */
12106 intel_update_pipe_size(intel_crtc);
12107
12108 intel_crtc->primary_enabled = true;
12109
12110 dev_priv->display.update_primary_plane(crtc, plane->fb,
12111 crtc->x, crtc->y);
12112 } else {
12113 /*
12114 * If clipping results in a non-visible primary plane,
12115 * we'll disable the primary plane. Note that this is
12116 * a bit different than what happens if userspace
12117 * explicitly disables the plane by passing fb=0
12118 * because plane->fb still gets set and pinned.
12119 */
12120 intel_disable_primary_hw_plane(plane, crtc);
12121 }
12122 }
12123 }
12124
12125 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12126 {
12127 struct drm_device *dev = crtc->dev;
12128 struct drm_i915_private *dev_priv = dev->dev_private;
12129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12130 struct intel_plane *intel_plane;
12131 struct drm_plane *p;
12132 unsigned fb_bits = 0;
12133
12134 /* Track fb's for any planes being disabled */
12135 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12136 intel_plane = to_intel_plane(p);
12137
12138 if (intel_crtc->atomic.disabled_planes &
12139 (1 << drm_plane_index(p))) {
12140 switch (p->type) {
12141 case DRM_PLANE_TYPE_PRIMARY:
12142 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12143 break;
12144 case DRM_PLANE_TYPE_CURSOR:
12145 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12146 break;
12147 case DRM_PLANE_TYPE_OVERLAY:
12148 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12149 break;
12150 }
12151
12152 mutex_lock(&dev->struct_mutex);
12153 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12154 mutex_unlock(&dev->struct_mutex);
12155 }
12156 }
12157
12158 if (intel_crtc->atomic.wait_for_flips)
12159 intel_crtc_wait_for_pending_flips(crtc);
12160
12161 if (intel_crtc->atomic.disable_fbc)
12162 intel_fbc_disable(dev);
12163
12164 if (intel_crtc->atomic.pre_disable_primary)
12165 intel_pre_disable_primary(crtc);
12166
12167 if (intel_crtc->atomic.update_wm)
12168 intel_update_watermarks(crtc);
12169
12170 intel_runtime_pm_get(dev_priv);
12171
12172 /* Perform vblank evasion around commit operation */
12173 if (intel_crtc->active)
12174 intel_crtc->atomic.evade =
12175 intel_pipe_update_start(intel_crtc,
12176 &intel_crtc->atomic.start_vbl_count);
12177 }
12178
12179 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12180 {
12181 struct drm_device *dev = crtc->dev;
12182 struct drm_i915_private *dev_priv = dev->dev_private;
12183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12184 struct drm_plane *p;
12185
12186 if (intel_crtc->atomic.evade)
12187 intel_pipe_update_end(intel_crtc,
12188 intel_crtc->atomic.start_vbl_count);
12189
12190 intel_runtime_pm_put(dev_priv);
12191
12192 if (intel_crtc->atomic.wait_vblank)
12193 intel_wait_for_vblank(dev, intel_crtc->pipe);
12194
12195 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12196
12197 if (intel_crtc->atomic.update_fbc) {
12198 mutex_lock(&dev->struct_mutex);
12199 intel_fbc_update(dev);
12200 mutex_unlock(&dev->struct_mutex);
12201 }
12202
12203 if (intel_crtc->atomic.post_enable_primary)
12204 intel_post_enable_primary(crtc);
12205
12206 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12207 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12208 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12209 false, false);
12210
12211 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12212 }
12213
12214 /**
12215 * intel_plane_destroy - destroy a plane
12216 * @plane: plane to destroy
12217 *
12218 * Common destruction function for all types of planes (primary, cursor,
12219 * sprite).
12220 */
12221 void intel_plane_destroy(struct drm_plane *plane)
12222 {
12223 struct intel_plane *intel_plane = to_intel_plane(plane);
12224 drm_plane_cleanup(plane);
12225 kfree(intel_plane);
12226 }
12227
12228 const struct drm_plane_funcs intel_plane_funcs = {
12229 .update_plane = drm_plane_helper_update,
12230 .disable_plane = drm_plane_helper_disable,
12231 .destroy = intel_plane_destroy,
12232 .set_property = drm_atomic_helper_plane_set_property,
12233 .atomic_get_property = intel_plane_atomic_get_property,
12234 .atomic_set_property = intel_plane_atomic_set_property,
12235 .atomic_duplicate_state = intel_plane_duplicate_state,
12236 .atomic_destroy_state = intel_plane_destroy_state,
12237
12238 };
12239
12240 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12241 int pipe)
12242 {
12243 struct intel_plane *primary;
12244 struct intel_plane_state *state;
12245 const uint32_t *intel_primary_formats;
12246 int num_formats;
12247
12248 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12249 if (primary == NULL)
12250 return NULL;
12251
12252 state = intel_create_plane_state(&primary->base);
12253 if (!state) {
12254 kfree(primary);
12255 return NULL;
12256 }
12257 primary->base.state = &state->base;
12258
12259 primary->can_scale = false;
12260 primary->max_downscale = 1;
12261 primary->pipe = pipe;
12262 primary->plane = pipe;
12263 primary->check_plane = intel_check_primary_plane;
12264 primary->commit_plane = intel_commit_primary_plane;
12265 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12266 primary->plane = !pipe;
12267
12268 if (INTEL_INFO(dev)->gen <= 3) {
12269 intel_primary_formats = intel_primary_formats_gen2;
12270 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12271 } else {
12272 intel_primary_formats = intel_primary_formats_gen4;
12273 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12274 }
12275
12276 drm_universal_plane_init(dev, &primary->base, 0,
12277 &intel_plane_funcs,
12278 intel_primary_formats, num_formats,
12279 DRM_PLANE_TYPE_PRIMARY);
12280
12281 if (INTEL_INFO(dev)->gen >= 4) {
12282 if (!dev->mode_config.rotation_property)
12283 dev->mode_config.rotation_property =
12284 drm_mode_create_rotation_property(dev,
12285 BIT(DRM_ROTATE_0) |
12286 BIT(DRM_ROTATE_180));
12287 if (dev->mode_config.rotation_property)
12288 drm_object_attach_property(&primary->base.base,
12289 dev->mode_config.rotation_property,
12290 state->base.rotation);
12291 }
12292
12293 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12294
12295 return &primary->base;
12296 }
12297
12298 static int
12299 intel_check_cursor_plane(struct drm_plane *plane,
12300 struct intel_plane_state *state)
12301 {
12302 struct drm_crtc *crtc = state->base.crtc;
12303 struct drm_device *dev = plane->dev;
12304 struct drm_framebuffer *fb = state->base.fb;
12305 struct drm_rect *dest = &state->dst;
12306 struct drm_rect *src = &state->src;
12307 const struct drm_rect *clip = &state->clip;
12308 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12309 struct intel_crtc *intel_crtc;
12310 unsigned stride;
12311 int ret;
12312
12313 crtc = crtc ? crtc : plane->crtc;
12314 intel_crtc = to_intel_crtc(crtc);
12315
12316 ret = drm_plane_helper_check_update(plane, crtc, fb,
12317 src, dest, clip,
12318 DRM_PLANE_HELPER_NO_SCALING,
12319 DRM_PLANE_HELPER_NO_SCALING,
12320 true, true, &state->visible);
12321 if (ret)
12322 return ret;
12323
12324
12325 /* if we want to turn off the cursor ignore width and height */
12326 if (!obj)
12327 goto finish;
12328
12329 /* Check for which cursor types we support */
12330 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12331 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12332 state->base.crtc_w, state->base.crtc_h);
12333 return -EINVAL;
12334 }
12335
12336 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12337 if (obj->base.size < stride * state->base.crtc_h) {
12338 DRM_DEBUG_KMS("buffer is too small\n");
12339 return -ENOMEM;
12340 }
12341
12342 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12343 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12344 ret = -EINVAL;
12345 }
12346
12347 finish:
12348 if (intel_crtc->active) {
12349 if (plane->state->crtc_w != state->base.crtc_w)
12350 intel_crtc->atomic.update_wm = true;
12351
12352 intel_crtc->atomic.fb_bits |=
12353 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12354 }
12355
12356 return ret;
12357 }
12358
12359 static void
12360 intel_commit_cursor_plane(struct drm_plane *plane,
12361 struct intel_plane_state *state)
12362 {
12363 struct drm_crtc *crtc = state->base.crtc;
12364 struct drm_device *dev = plane->dev;
12365 struct intel_crtc *intel_crtc;
12366 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12367 uint32_t addr;
12368
12369 crtc = crtc ? crtc : plane->crtc;
12370 intel_crtc = to_intel_crtc(crtc);
12371
12372 plane->fb = state->base.fb;
12373 crtc->cursor_x = state->base.crtc_x;
12374 crtc->cursor_y = state->base.crtc_y;
12375
12376 if (intel_crtc->cursor_bo == obj)
12377 goto update;
12378
12379 if (!obj)
12380 addr = 0;
12381 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12382 addr = i915_gem_obj_ggtt_offset(obj);
12383 else
12384 addr = obj->phys_handle->busaddr;
12385
12386 intel_crtc->cursor_addr = addr;
12387 intel_crtc->cursor_bo = obj;
12388 update:
12389
12390 if (intel_crtc->active)
12391 intel_crtc_update_cursor(crtc, state->visible);
12392 }
12393
12394 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12395 int pipe)
12396 {
12397 struct intel_plane *cursor;
12398 struct intel_plane_state *state;
12399
12400 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12401 if (cursor == NULL)
12402 return NULL;
12403
12404 state = intel_create_plane_state(&cursor->base);
12405 if (!state) {
12406 kfree(cursor);
12407 return NULL;
12408 }
12409 cursor->base.state = &state->base;
12410
12411 cursor->can_scale = false;
12412 cursor->max_downscale = 1;
12413 cursor->pipe = pipe;
12414 cursor->plane = pipe;
12415 cursor->check_plane = intel_check_cursor_plane;
12416 cursor->commit_plane = intel_commit_cursor_plane;
12417
12418 drm_universal_plane_init(dev, &cursor->base, 0,
12419 &intel_plane_funcs,
12420 intel_cursor_formats,
12421 ARRAY_SIZE(intel_cursor_formats),
12422 DRM_PLANE_TYPE_CURSOR);
12423
12424 if (INTEL_INFO(dev)->gen >= 4) {
12425 if (!dev->mode_config.rotation_property)
12426 dev->mode_config.rotation_property =
12427 drm_mode_create_rotation_property(dev,
12428 BIT(DRM_ROTATE_0) |
12429 BIT(DRM_ROTATE_180));
12430 if (dev->mode_config.rotation_property)
12431 drm_object_attach_property(&cursor->base.base,
12432 dev->mode_config.rotation_property,
12433 state->base.rotation);
12434 }
12435
12436 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12437
12438 return &cursor->base;
12439 }
12440
12441 static void intel_crtc_init(struct drm_device *dev, int pipe)
12442 {
12443 struct drm_i915_private *dev_priv = dev->dev_private;
12444 struct intel_crtc *intel_crtc;
12445 struct intel_crtc_state *crtc_state = NULL;
12446 struct drm_plane *primary = NULL;
12447 struct drm_plane *cursor = NULL;
12448 int i, ret;
12449
12450 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12451 if (intel_crtc == NULL)
12452 return;
12453
12454 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12455 if (!crtc_state)
12456 goto fail;
12457 intel_crtc_set_state(intel_crtc, crtc_state);
12458 crtc_state->base.crtc = &intel_crtc->base;
12459
12460 primary = intel_primary_plane_create(dev, pipe);
12461 if (!primary)
12462 goto fail;
12463
12464 cursor = intel_cursor_plane_create(dev, pipe);
12465 if (!cursor)
12466 goto fail;
12467
12468 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12469 cursor, &intel_crtc_funcs);
12470 if (ret)
12471 goto fail;
12472
12473 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12474 for (i = 0; i < 256; i++) {
12475 intel_crtc->lut_r[i] = i;
12476 intel_crtc->lut_g[i] = i;
12477 intel_crtc->lut_b[i] = i;
12478 }
12479
12480 /*
12481 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12482 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12483 */
12484 intel_crtc->pipe = pipe;
12485 intel_crtc->plane = pipe;
12486 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12487 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12488 intel_crtc->plane = !pipe;
12489 }
12490
12491 intel_crtc->cursor_base = ~0;
12492 intel_crtc->cursor_cntl = ~0;
12493 intel_crtc->cursor_size = ~0;
12494
12495 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12496 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12497 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12498 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12499
12500 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12501
12502 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12503
12504 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12505 return;
12506
12507 fail:
12508 if (primary)
12509 drm_plane_cleanup(primary);
12510 if (cursor)
12511 drm_plane_cleanup(cursor);
12512 kfree(crtc_state);
12513 kfree(intel_crtc);
12514 }
12515
12516 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12517 {
12518 struct drm_encoder *encoder = connector->base.encoder;
12519 struct drm_device *dev = connector->base.dev;
12520
12521 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12522
12523 if (!encoder || WARN_ON(!encoder->crtc))
12524 return INVALID_PIPE;
12525
12526 return to_intel_crtc(encoder->crtc)->pipe;
12527 }
12528
12529 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12530 struct drm_file *file)
12531 {
12532 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12533 struct drm_crtc *drmmode_crtc;
12534 struct intel_crtc *crtc;
12535
12536 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12537
12538 if (!drmmode_crtc) {
12539 DRM_ERROR("no such CRTC id\n");
12540 return -ENOENT;
12541 }
12542
12543 crtc = to_intel_crtc(drmmode_crtc);
12544 pipe_from_crtc_id->pipe = crtc->pipe;
12545
12546 return 0;
12547 }
12548
12549 static int intel_encoder_clones(struct intel_encoder *encoder)
12550 {
12551 struct drm_device *dev = encoder->base.dev;
12552 struct intel_encoder *source_encoder;
12553 int index_mask = 0;
12554 int entry = 0;
12555
12556 for_each_intel_encoder(dev, source_encoder) {
12557 if (encoders_cloneable(encoder, source_encoder))
12558 index_mask |= (1 << entry);
12559
12560 entry++;
12561 }
12562
12563 return index_mask;
12564 }
12565
12566 static bool has_edp_a(struct drm_device *dev)
12567 {
12568 struct drm_i915_private *dev_priv = dev->dev_private;
12569
12570 if (!IS_MOBILE(dev))
12571 return false;
12572
12573 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12574 return false;
12575
12576 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12577 return false;
12578
12579 return true;
12580 }
12581
12582 static bool intel_crt_present(struct drm_device *dev)
12583 {
12584 struct drm_i915_private *dev_priv = dev->dev_private;
12585
12586 if (INTEL_INFO(dev)->gen >= 9)
12587 return false;
12588
12589 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12590 return false;
12591
12592 if (IS_CHERRYVIEW(dev))
12593 return false;
12594
12595 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12596 return false;
12597
12598 return true;
12599 }
12600
12601 static void intel_setup_outputs(struct drm_device *dev)
12602 {
12603 struct drm_i915_private *dev_priv = dev->dev_private;
12604 struct intel_encoder *encoder;
12605 struct drm_connector *connector;
12606 bool dpd_is_edp = false;
12607
12608 intel_lvds_init(dev);
12609
12610 if (intel_crt_present(dev))
12611 intel_crt_init(dev);
12612
12613 if (HAS_DDI(dev)) {
12614 int found;
12615
12616 /*
12617 * Haswell uses DDI functions to detect digital outputs.
12618 * On SKL pre-D0 the strap isn't connected, so we assume
12619 * it's there.
12620 */
12621 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12622 /* WaIgnoreDDIAStrap: skl */
12623 if (found ||
12624 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12625 intel_ddi_init(dev, PORT_A);
12626
12627 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12628 * register */
12629 found = I915_READ(SFUSE_STRAP);
12630
12631 if (found & SFUSE_STRAP_DDIB_DETECTED)
12632 intel_ddi_init(dev, PORT_B);
12633 if (found & SFUSE_STRAP_DDIC_DETECTED)
12634 intel_ddi_init(dev, PORT_C);
12635 if (found & SFUSE_STRAP_DDID_DETECTED)
12636 intel_ddi_init(dev, PORT_D);
12637 } else if (HAS_PCH_SPLIT(dev)) {
12638 int found;
12639 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12640
12641 if (has_edp_a(dev))
12642 intel_dp_init(dev, DP_A, PORT_A);
12643
12644 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12645 /* PCH SDVOB multiplex with HDMIB */
12646 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12647 if (!found)
12648 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12649 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12650 intel_dp_init(dev, PCH_DP_B, PORT_B);
12651 }
12652
12653 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12654 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12655
12656 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12657 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12658
12659 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12660 intel_dp_init(dev, PCH_DP_C, PORT_C);
12661
12662 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12663 intel_dp_init(dev, PCH_DP_D, PORT_D);
12664 } else if (IS_VALLEYVIEW(dev)) {
12665 /*
12666 * The DP_DETECTED bit is the latched state of the DDC
12667 * SDA pin at boot. However since eDP doesn't require DDC
12668 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12669 * eDP ports may have been muxed to an alternate function.
12670 * Thus we can't rely on the DP_DETECTED bit alone to detect
12671 * eDP ports. Consult the VBT as well as DP_DETECTED to
12672 * detect eDP ports.
12673 */
12674 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12675 !intel_dp_is_edp(dev, PORT_B))
12676 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12677 PORT_B);
12678 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12679 intel_dp_is_edp(dev, PORT_B))
12680 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12681
12682 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12683 !intel_dp_is_edp(dev, PORT_C))
12684 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12685 PORT_C);
12686 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12687 intel_dp_is_edp(dev, PORT_C))
12688 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12689
12690 if (IS_CHERRYVIEW(dev)) {
12691 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12692 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12693 PORT_D);
12694 /* eDP not supported on port D, so don't check VBT */
12695 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12696 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12697 }
12698
12699 intel_dsi_init(dev);
12700 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12701 bool found = false;
12702
12703 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12704 DRM_DEBUG_KMS("probing SDVOB\n");
12705 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12706 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12707 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12708 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12709 }
12710
12711 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12712 intel_dp_init(dev, DP_B, PORT_B);
12713 }
12714
12715 /* Before G4X SDVOC doesn't have its own detect register */
12716
12717 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12718 DRM_DEBUG_KMS("probing SDVOC\n");
12719 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12720 }
12721
12722 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12723
12724 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12725 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12726 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12727 }
12728 if (SUPPORTS_INTEGRATED_DP(dev))
12729 intel_dp_init(dev, DP_C, PORT_C);
12730 }
12731
12732 if (SUPPORTS_INTEGRATED_DP(dev) &&
12733 (I915_READ(DP_D) & DP_DETECTED))
12734 intel_dp_init(dev, DP_D, PORT_D);
12735 } else if (IS_GEN2(dev))
12736 intel_dvo_init(dev);
12737
12738 if (SUPPORTS_TV(dev))
12739 intel_tv_init(dev);
12740
12741 /*
12742 * FIXME: We don't have full atomic support yet, but we want to be
12743 * able to enable/test plane updates via the atomic interface in the
12744 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12745 * will take some atomic codepaths to lookup properties during
12746 * drmModeGetConnector() that unconditionally dereference
12747 * connector->state.
12748 *
12749 * We create a dummy connector state here for each connector to ensure
12750 * the DRM core doesn't try to dereference a NULL connector->state.
12751 * The actual connector properties will never be updated or contain
12752 * useful information, but since we're doing this specifically for
12753 * testing/debug of the plane operations (and only when a specific
12754 * kernel module option is given), that shouldn't really matter.
12755 *
12756 * Once atomic support for crtc's + connectors lands, this loop should
12757 * be removed since we'll be setting up real connector state, which
12758 * will contain Intel-specific properties.
12759 */
12760 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12761 list_for_each_entry(connector,
12762 &dev->mode_config.connector_list,
12763 head) {
12764 if (!WARN_ON(connector->state)) {
12765 connector->state =
12766 kzalloc(sizeof(*connector->state),
12767 GFP_KERNEL);
12768 }
12769 }
12770 }
12771
12772 intel_psr_init(dev);
12773
12774 for_each_intel_encoder(dev, encoder) {
12775 encoder->base.possible_crtcs = encoder->crtc_mask;
12776 encoder->base.possible_clones =
12777 intel_encoder_clones(encoder);
12778 }
12779
12780 intel_init_pch_refclk(dev);
12781
12782 drm_helper_move_panel_connectors_to_head(dev);
12783 }
12784
12785 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12786 {
12787 struct drm_device *dev = fb->dev;
12788 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12789
12790 drm_framebuffer_cleanup(fb);
12791 mutex_lock(&dev->struct_mutex);
12792 WARN_ON(!intel_fb->obj->framebuffer_references--);
12793 drm_gem_object_unreference(&intel_fb->obj->base);
12794 mutex_unlock(&dev->struct_mutex);
12795 kfree(intel_fb);
12796 }
12797
12798 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12799 struct drm_file *file,
12800 unsigned int *handle)
12801 {
12802 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12803 struct drm_i915_gem_object *obj = intel_fb->obj;
12804
12805 return drm_gem_handle_create(file, &obj->base, handle);
12806 }
12807
12808 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12809 .destroy = intel_user_framebuffer_destroy,
12810 .create_handle = intel_user_framebuffer_create_handle,
12811 };
12812
12813 static
12814 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12815 uint32_t pixel_format)
12816 {
12817 u32 gen = INTEL_INFO(dev)->gen;
12818
12819 if (gen >= 9) {
12820 /* "The stride in bytes must not exceed the of the size of 8K
12821 * pixels and 32K bytes."
12822 */
12823 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12824 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12825 return 32*1024;
12826 } else if (gen >= 4) {
12827 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12828 return 16*1024;
12829 else
12830 return 32*1024;
12831 } else if (gen >= 3) {
12832 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12833 return 8*1024;
12834 else
12835 return 16*1024;
12836 } else {
12837 /* XXX DSPC is limited to 4k tiled */
12838 return 8*1024;
12839 }
12840 }
12841
12842 static int intel_framebuffer_init(struct drm_device *dev,
12843 struct intel_framebuffer *intel_fb,
12844 struct drm_mode_fb_cmd2 *mode_cmd,
12845 struct drm_i915_gem_object *obj)
12846 {
12847 int aligned_height;
12848 int ret;
12849 u32 pitch_limit, stride_alignment;
12850
12851 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12852
12853 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12854 /* Enforce that fb modifier and tiling mode match, but only for
12855 * X-tiled. This is needed for FBC. */
12856 if (!!(obj->tiling_mode == I915_TILING_X) !=
12857 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12858 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12859 return -EINVAL;
12860 }
12861 } else {
12862 if (obj->tiling_mode == I915_TILING_X)
12863 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12864 else if (obj->tiling_mode == I915_TILING_Y) {
12865 DRM_DEBUG("No Y tiling for legacy addfb\n");
12866 return -EINVAL;
12867 }
12868 }
12869
12870 /* Passed in modifier sanity checking. */
12871 switch (mode_cmd->modifier[0]) {
12872 case I915_FORMAT_MOD_Y_TILED:
12873 case I915_FORMAT_MOD_Yf_TILED:
12874 if (INTEL_INFO(dev)->gen < 9) {
12875 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12876 mode_cmd->modifier[0]);
12877 return -EINVAL;
12878 }
12879 case DRM_FORMAT_MOD_NONE:
12880 case I915_FORMAT_MOD_X_TILED:
12881 break;
12882 default:
12883 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12884 mode_cmd->modifier[0]);
12885 return -EINVAL;
12886 }
12887
12888 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12889 mode_cmd->pixel_format);
12890 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12891 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12892 mode_cmd->pitches[0], stride_alignment);
12893 return -EINVAL;
12894 }
12895
12896 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12897 mode_cmd->pixel_format);
12898 if (mode_cmd->pitches[0] > pitch_limit) {
12899 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12900 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12901 "tiled" : "linear",
12902 mode_cmd->pitches[0], pitch_limit);
12903 return -EINVAL;
12904 }
12905
12906 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12907 mode_cmd->pitches[0] != obj->stride) {
12908 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12909 mode_cmd->pitches[0], obj->stride);
12910 return -EINVAL;
12911 }
12912
12913 /* Reject formats not supported by any plane early. */
12914 switch (mode_cmd->pixel_format) {
12915 case DRM_FORMAT_C8:
12916 case DRM_FORMAT_RGB565:
12917 case DRM_FORMAT_XRGB8888:
12918 case DRM_FORMAT_ARGB8888:
12919 break;
12920 case DRM_FORMAT_XRGB1555:
12921 case DRM_FORMAT_ARGB1555:
12922 if (INTEL_INFO(dev)->gen > 3) {
12923 DRM_DEBUG("unsupported pixel format: %s\n",
12924 drm_get_format_name(mode_cmd->pixel_format));
12925 return -EINVAL;
12926 }
12927 break;
12928 case DRM_FORMAT_XBGR8888:
12929 case DRM_FORMAT_ABGR8888:
12930 case DRM_FORMAT_XRGB2101010:
12931 case DRM_FORMAT_ARGB2101010:
12932 case DRM_FORMAT_XBGR2101010:
12933 case DRM_FORMAT_ABGR2101010:
12934 if (INTEL_INFO(dev)->gen < 4) {
12935 DRM_DEBUG("unsupported pixel format: %s\n",
12936 drm_get_format_name(mode_cmd->pixel_format));
12937 return -EINVAL;
12938 }
12939 break;
12940 case DRM_FORMAT_YUYV:
12941 case DRM_FORMAT_UYVY:
12942 case DRM_FORMAT_YVYU:
12943 case DRM_FORMAT_VYUY:
12944 if (INTEL_INFO(dev)->gen < 5) {
12945 DRM_DEBUG("unsupported pixel format: %s\n",
12946 drm_get_format_name(mode_cmd->pixel_format));
12947 return -EINVAL;
12948 }
12949 break;
12950 default:
12951 DRM_DEBUG("unsupported pixel format: %s\n",
12952 drm_get_format_name(mode_cmd->pixel_format));
12953 return -EINVAL;
12954 }
12955
12956 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12957 if (mode_cmd->offsets[0] != 0)
12958 return -EINVAL;
12959
12960 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12961 mode_cmd->pixel_format,
12962 mode_cmd->modifier[0]);
12963 /* FIXME drm helper for size checks (especially planar formats)? */
12964 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12965 return -EINVAL;
12966
12967 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12968 intel_fb->obj = obj;
12969 intel_fb->obj->framebuffer_references++;
12970
12971 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12972 if (ret) {
12973 DRM_ERROR("framebuffer init failed %d\n", ret);
12974 return ret;
12975 }
12976
12977 return 0;
12978 }
12979
12980 static struct drm_framebuffer *
12981 intel_user_framebuffer_create(struct drm_device *dev,
12982 struct drm_file *filp,
12983 struct drm_mode_fb_cmd2 *mode_cmd)
12984 {
12985 struct drm_i915_gem_object *obj;
12986
12987 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12988 mode_cmd->handles[0]));
12989 if (&obj->base == NULL)
12990 return ERR_PTR(-ENOENT);
12991
12992 return intel_framebuffer_create(dev, mode_cmd, obj);
12993 }
12994
12995 #ifndef CONFIG_DRM_I915_FBDEV
12996 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12997 {
12998 }
12999 #endif
13000
13001 static const struct drm_mode_config_funcs intel_mode_funcs = {
13002 .fb_create = intel_user_framebuffer_create,
13003 .output_poll_changed = intel_fbdev_output_poll_changed,
13004 .atomic_check = intel_atomic_check,
13005 .atomic_commit = intel_atomic_commit,
13006 };
13007
13008 /* Set up chip specific display functions */
13009 static void intel_init_display(struct drm_device *dev)
13010 {
13011 struct drm_i915_private *dev_priv = dev->dev_private;
13012
13013 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13014 dev_priv->display.find_dpll = g4x_find_best_dpll;
13015 else if (IS_CHERRYVIEW(dev))
13016 dev_priv->display.find_dpll = chv_find_best_dpll;
13017 else if (IS_VALLEYVIEW(dev))
13018 dev_priv->display.find_dpll = vlv_find_best_dpll;
13019 else if (IS_PINEVIEW(dev))
13020 dev_priv->display.find_dpll = pnv_find_best_dpll;
13021 else
13022 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13023
13024 if (INTEL_INFO(dev)->gen >= 9) {
13025 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13026 dev_priv->display.get_initial_plane_config =
13027 skylake_get_initial_plane_config;
13028 dev_priv->display.crtc_compute_clock =
13029 haswell_crtc_compute_clock;
13030 dev_priv->display.crtc_enable = haswell_crtc_enable;
13031 dev_priv->display.crtc_disable = haswell_crtc_disable;
13032 dev_priv->display.off = ironlake_crtc_off;
13033 dev_priv->display.update_primary_plane =
13034 skylake_update_primary_plane;
13035 } else if (HAS_DDI(dev)) {
13036 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13037 dev_priv->display.get_initial_plane_config =
13038 ironlake_get_initial_plane_config;
13039 dev_priv->display.crtc_compute_clock =
13040 haswell_crtc_compute_clock;
13041 dev_priv->display.crtc_enable = haswell_crtc_enable;
13042 dev_priv->display.crtc_disable = haswell_crtc_disable;
13043 dev_priv->display.off = ironlake_crtc_off;
13044 dev_priv->display.update_primary_plane =
13045 ironlake_update_primary_plane;
13046 } else if (HAS_PCH_SPLIT(dev)) {
13047 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13048 dev_priv->display.get_initial_plane_config =
13049 ironlake_get_initial_plane_config;
13050 dev_priv->display.crtc_compute_clock =
13051 ironlake_crtc_compute_clock;
13052 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13053 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13054 dev_priv->display.off = ironlake_crtc_off;
13055 dev_priv->display.update_primary_plane =
13056 ironlake_update_primary_plane;
13057 } else if (IS_VALLEYVIEW(dev)) {
13058 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13059 dev_priv->display.get_initial_plane_config =
13060 i9xx_get_initial_plane_config;
13061 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13062 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13063 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13064 dev_priv->display.off = i9xx_crtc_off;
13065 dev_priv->display.update_primary_plane =
13066 i9xx_update_primary_plane;
13067 } else {
13068 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13069 dev_priv->display.get_initial_plane_config =
13070 i9xx_get_initial_plane_config;
13071 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13072 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13073 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13074 dev_priv->display.off = i9xx_crtc_off;
13075 dev_priv->display.update_primary_plane =
13076 i9xx_update_primary_plane;
13077 }
13078
13079 /* Returns the core display clock speed */
13080 if (IS_VALLEYVIEW(dev))
13081 dev_priv->display.get_display_clock_speed =
13082 valleyview_get_display_clock_speed;
13083 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13084 dev_priv->display.get_display_clock_speed =
13085 i945_get_display_clock_speed;
13086 else if (IS_I915G(dev))
13087 dev_priv->display.get_display_clock_speed =
13088 i915_get_display_clock_speed;
13089 else if (IS_I945GM(dev) || IS_845G(dev))
13090 dev_priv->display.get_display_clock_speed =
13091 i9xx_misc_get_display_clock_speed;
13092 else if (IS_PINEVIEW(dev))
13093 dev_priv->display.get_display_clock_speed =
13094 pnv_get_display_clock_speed;
13095 else if (IS_I915GM(dev))
13096 dev_priv->display.get_display_clock_speed =
13097 i915gm_get_display_clock_speed;
13098 else if (IS_I865G(dev))
13099 dev_priv->display.get_display_clock_speed =
13100 i865_get_display_clock_speed;
13101 else if (IS_I85X(dev))
13102 dev_priv->display.get_display_clock_speed =
13103 i855_get_display_clock_speed;
13104 else /* 852, 830 */
13105 dev_priv->display.get_display_clock_speed =
13106 i830_get_display_clock_speed;
13107
13108 if (IS_GEN5(dev)) {
13109 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13110 } else if (IS_GEN6(dev)) {
13111 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13112 } else if (IS_IVYBRIDGE(dev)) {
13113 /* FIXME: detect B0+ stepping and use auto training */
13114 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13115 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13116 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13117 } else if (IS_VALLEYVIEW(dev)) {
13118 dev_priv->display.modeset_global_resources =
13119 valleyview_modeset_global_resources;
13120 }
13121
13122 switch (INTEL_INFO(dev)->gen) {
13123 case 2:
13124 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13125 break;
13126
13127 case 3:
13128 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13129 break;
13130
13131 case 4:
13132 case 5:
13133 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13134 break;
13135
13136 case 6:
13137 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13138 break;
13139 case 7:
13140 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13141 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13142 break;
13143 case 9:
13144 /* Drop through - unsupported since execlist only. */
13145 default:
13146 /* Default just returns -ENODEV to indicate unsupported */
13147 dev_priv->display.queue_flip = intel_default_queue_flip;
13148 }
13149
13150 intel_panel_init_backlight_funcs(dev);
13151
13152 mutex_init(&dev_priv->pps_mutex);
13153 }
13154
13155 /*
13156 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13157 * resume, or other times. This quirk makes sure that's the case for
13158 * affected systems.
13159 */
13160 static void quirk_pipea_force(struct drm_device *dev)
13161 {
13162 struct drm_i915_private *dev_priv = dev->dev_private;
13163
13164 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13165 DRM_INFO("applying pipe a force quirk\n");
13166 }
13167
13168 static void quirk_pipeb_force(struct drm_device *dev)
13169 {
13170 struct drm_i915_private *dev_priv = dev->dev_private;
13171
13172 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13173 DRM_INFO("applying pipe b force quirk\n");
13174 }
13175
13176 /*
13177 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13178 */
13179 static void quirk_ssc_force_disable(struct drm_device *dev)
13180 {
13181 struct drm_i915_private *dev_priv = dev->dev_private;
13182 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13183 DRM_INFO("applying lvds SSC disable quirk\n");
13184 }
13185
13186 /*
13187 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13188 * brightness value
13189 */
13190 static void quirk_invert_brightness(struct drm_device *dev)
13191 {
13192 struct drm_i915_private *dev_priv = dev->dev_private;
13193 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13194 DRM_INFO("applying inverted panel brightness quirk\n");
13195 }
13196
13197 /* Some VBT's incorrectly indicate no backlight is present */
13198 static void quirk_backlight_present(struct drm_device *dev)
13199 {
13200 struct drm_i915_private *dev_priv = dev->dev_private;
13201 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13202 DRM_INFO("applying backlight present quirk\n");
13203 }
13204
13205 struct intel_quirk {
13206 int device;
13207 int subsystem_vendor;
13208 int subsystem_device;
13209 void (*hook)(struct drm_device *dev);
13210 };
13211
13212 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13213 struct intel_dmi_quirk {
13214 void (*hook)(struct drm_device *dev);
13215 const struct dmi_system_id (*dmi_id_list)[];
13216 };
13217
13218 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13219 {
13220 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13221 return 1;
13222 }
13223
13224 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13225 {
13226 .dmi_id_list = &(const struct dmi_system_id[]) {
13227 {
13228 .callback = intel_dmi_reverse_brightness,
13229 .ident = "NCR Corporation",
13230 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13231 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13232 },
13233 },
13234 { } /* terminating entry */
13235 },
13236 .hook = quirk_invert_brightness,
13237 },
13238 };
13239
13240 static struct intel_quirk intel_quirks[] = {
13241 /* HP Mini needs pipe A force quirk (LP: #322104) */
13242 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13243
13244 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13245 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13246
13247 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13248 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13249
13250 /* 830 needs to leave pipe A & dpll A up */
13251 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13252
13253 /* 830 needs to leave pipe B & dpll B up */
13254 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13255
13256 /* Lenovo U160 cannot use SSC on LVDS */
13257 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13258
13259 /* Sony Vaio Y cannot use SSC on LVDS */
13260 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13261
13262 /* Acer Aspire 5734Z must invert backlight brightness */
13263 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13264
13265 /* Acer/eMachines G725 */
13266 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13267
13268 /* Acer/eMachines e725 */
13269 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13270
13271 /* Acer/Packard Bell NCL20 */
13272 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13273
13274 /* Acer Aspire 4736Z */
13275 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13276
13277 /* Acer Aspire 5336 */
13278 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13279
13280 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13281 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13282
13283 /* Acer C720 Chromebook (Core i3 4005U) */
13284 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13285
13286 /* Apple Macbook 2,1 (Core 2 T7400) */
13287 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13288
13289 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13290 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13291
13292 /* HP Chromebook 14 (Celeron 2955U) */
13293 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13294
13295 /* Dell Chromebook 11 */
13296 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13297 };
13298
13299 static void intel_init_quirks(struct drm_device *dev)
13300 {
13301 struct pci_dev *d = dev->pdev;
13302 int i;
13303
13304 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13305 struct intel_quirk *q = &intel_quirks[i];
13306
13307 if (d->device == q->device &&
13308 (d->subsystem_vendor == q->subsystem_vendor ||
13309 q->subsystem_vendor == PCI_ANY_ID) &&
13310 (d->subsystem_device == q->subsystem_device ||
13311 q->subsystem_device == PCI_ANY_ID))
13312 q->hook(dev);
13313 }
13314 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13315 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13316 intel_dmi_quirks[i].hook(dev);
13317 }
13318 }
13319
13320 /* Disable the VGA plane that we never use */
13321 static void i915_disable_vga(struct drm_device *dev)
13322 {
13323 struct drm_i915_private *dev_priv = dev->dev_private;
13324 u8 sr1;
13325 u32 vga_reg = i915_vgacntrl_reg(dev);
13326
13327 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13328 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13329 outb(SR01, VGA_SR_INDEX);
13330 sr1 = inb(VGA_SR_DATA);
13331 outb(sr1 | 1<<5, VGA_SR_DATA);
13332 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13333 udelay(300);
13334
13335 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13336 POSTING_READ(vga_reg);
13337 }
13338
13339 void intel_modeset_init_hw(struct drm_device *dev)
13340 {
13341 intel_prepare_ddi(dev);
13342
13343 if (IS_VALLEYVIEW(dev))
13344 vlv_update_cdclk(dev);
13345
13346 intel_init_clock_gating(dev);
13347
13348 intel_enable_gt_powersave(dev);
13349 }
13350
13351 void intel_modeset_init(struct drm_device *dev)
13352 {
13353 struct drm_i915_private *dev_priv = dev->dev_private;
13354 int sprite, ret;
13355 enum pipe pipe;
13356 struct intel_crtc *crtc;
13357
13358 drm_mode_config_init(dev);
13359
13360 dev->mode_config.min_width = 0;
13361 dev->mode_config.min_height = 0;
13362
13363 dev->mode_config.preferred_depth = 24;
13364 dev->mode_config.prefer_shadow = 1;
13365
13366 dev->mode_config.allow_fb_modifiers = true;
13367
13368 dev->mode_config.funcs = &intel_mode_funcs;
13369
13370 intel_init_quirks(dev);
13371
13372 intel_init_pm(dev);
13373
13374 if (INTEL_INFO(dev)->num_pipes == 0)
13375 return;
13376
13377 intel_init_display(dev);
13378 intel_init_audio(dev);
13379
13380 if (IS_GEN2(dev)) {
13381 dev->mode_config.max_width = 2048;
13382 dev->mode_config.max_height = 2048;
13383 } else if (IS_GEN3(dev)) {
13384 dev->mode_config.max_width = 4096;
13385 dev->mode_config.max_height = 4096;
13386 } else {
13387 dev->mode_config.max_width = 8192;
13388 dev->mode_config.max_height = 8192;
13389 }
13390
13391 if (IS_845G(dev) || IS_I865G(dev)) {
13392 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13393 dev->mode_config.cursor_height = 1023;
13394 } else if (IS_GEN2(dev)) {
13395 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13396 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13397 } else {
13398 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13399 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13400 }
13401
13402 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13403
13404 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13405 INTEL_INFO(dev)->num_pipes,
13406 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13407
13408 for_each_pipe(dev_priv, pipe) {
13409 intel_crtc_init(dev, pipe);
13410 for_each_sprite(dev_priv, pipe, sprite) {
13411 ret = intel_plane_init(dev, pipe, sprite);
13412 if (ret)
13413 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13414 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13415 }
13416 }
13417
13418 intel_init_dpio(dev);
13419
13420 intel_shared_dpll_init(dev);
13421
13422 /* Just disable it once at startup */
13423 i915_disable_vga(dev);
13424 intel_setup_outputs(dev);
13425
13426 /* Just in case the BIOS is doing something questionable. */
13427 intel_fbc_disable(dev);
13428
13429 drm_modeset_lock_all(dev);
13430 intel_modeset_setup_hw_state(dev, false);
13431 drm_modeset_unlock_all(dev);
13432
13433 for_each_intel_crtc(dev, crtc) {
13434 if (!crtc->active)
13435 continue;
13436
13437 /*
13438 * Note that reserving the BIOS fb up front prevents us
13439 * from stuffing other stolen allocations like the ring
13440 * on top. This prevents some ugliness at boot time, and
13441 * can even allow for smooth boot transitions if the BIOS
13442 * fb is large enough for the active pipe configuration.
13443 */
13444 if (dev_priv->display.get_initial_plane_config) {
13445 dev_priv->display.get_initial_plane_config(crtc,
13446 &crtc->plane_config);
13447 /*
13448 * If the fb is shared between multiple heads, we'll
13449 * just get the first one.
13450 */
13451 intel_find_plane_obj(crtc, &crtc->plane_config);
13452 }
13453 }
13454 }
13455
13456 static void intel_enable_pipe_a(struct drm_device *dev)
13457 {
13458 struct intel_connector *connector;
13459 struct drm_connector *crt = NULL;
13460 struct intel_load_detect_pipe load_detect_temp;
13461 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13462
13463 /* We can't just switch on the pipe A, we need to set things up with a
13464 * proper mode and output configuration. As a gross hack, enable pipe A
13465 * by enabling the load detect pipe once. */
13466 for_each_intel_connector(dev, connector) {
13467 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13468 crt = &connector->base;
13469 break;
13470 }
13471 }
13472
13473 if (!crt)
13474 return;
13475
13476 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13477 intel_release_load_detect_pipe(crt, &load_detect_temp);
13478 }
13479
13480 static bool
13481 intel_check_plane_mapping(struct intel_crtc *crtc)
13482 {
13483 struct drm_device *dev = crtc->base.dev;
13484 struct drm_i915_private *dev_priv = dev->dev_private;
13485 u32 reg, val;
13486
13487 if (INTEL_INFO(dev)->num_pipes == 1)
13488 return true;
13489
13490 reg = DSPCNTR(!crtc->plane);
13491 val = I915_READ(reg);
13492
13493 if ((val & DISPLAY_PLANE_ENABLE) &&
13494 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13495 return false;
13496
13497 return true;
13498 }
13499
13500 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13501 {
13502 struct drm_device *dev = crtc->base.dev;
13503 struct drm_i915_private *dev_priv = dev->dev_private;
13504 u32 reg;
13505
13506 /* Clear any frame start delays used for debugging left by the BIOS */
13507 reg = PIPECONF(crtc->config->cpu_transcoder);
13508 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13509
13510 /* restore vblank interrupts to correct state */
13511 drm_crtc_vblank_reset(&crtc->base);
13512 if (crtc->active) {
13513 update_scanline_offset(crtc);
13514 drm_crtc_vblank_on(&crtc->base);
13515 }
13516
13517 /* We need to sanitize the plane -> pipe mapping first because this will
13518 * disable the crtc (and hence change the state) if it is wrong. Note
13519 * that gen4+ has a fixed plane -> pipe mapping. */
13520 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13521 struct intel_connector *connector;
13522 bool plane;
13523
13524 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13525 crtc->base.base.id);
13526
13527 /* Pipe has the wrong plane attached and the plane is active.
13528 * Temporarily change the plane mapping and disable everything
13529 * ... */
13530 plane = crtc->plane;
13531 crtc->plane = !plane;
13532 crtc->primary_enabled = true;
13533 dev_priv->display.crtc_disable(&crtc->base);
13534 crtc->plane = plane;
13535
13536 /* ... and break all links. */
13537 for_each_intel_connector(dev, connector) {
13538 if (connector->encoder->base.crtc != &crtc->base)
13539 continue;
13540
13541 connector->base.dpms = DRM_MODE_DPMS_OFF;
13542 connector->base.encoder = NULL;
13543 }
13544 /* multiple connectors may have the same encoder:
13545 * handle them and break crtc link separately */
13546 for_each_intel_connector(dev, connector)
13547 if (connector->encoder->base.crtc == &crtc->base) {
13548 connector->encoder->base.crtc = NULL;
13549 connector->encoder->connectors_active = false;
13550 }
13551
13552 WARN_ON(crtc->active);
13553 crtc->base.state->enable = false;
13554 crtc->base.enabled = false;
13555 }
13556
13557 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13558 crtc->pipe == PIPE_A && !crtc->active) {
13559 /* BIOS forgot to enable pipe A, this mostly happens after
13560 * resume. Force-enable the pipe to fix this, the update_dpms
13561 * call below we restore the pipe to the right state, but leave
13562 * the required bits on. */
13563 intel_enable_pipe_a(dev);
13564 }
13565
13566 /* Adjust the state of the output pipe according to whether we
13567 * have active connectors/encoders. */
13568 intel_crtc_update_dpms(&crtc->base);
13569
13570 if (crtc->active != crtc->base.state->enable) {
13571 struct intel_encoder *encoder;
13572
13573 /* This can happen either due to bugs in the get_hw_state
13574 * functions or because the pipe is force-enabled due to the
13575 * pipe A quirk. */
13576 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13577 crtc->base.base.id,
13578 crtc->base.state->enable ? "enabled" : "disabled",
13579 crtc->active ? "enabled" : "disabled");
13580
13581 crtc->base.state->enable = crtc->active;
13582 crtc->base.enabled = crtc->active;
13583
13584 /* Because we only establish the connector -> encoder ->
13585 * crtc links if something is active, this means the
13586 * crtc is now deactivated. Break the links. connector
13587 * -> encoder links are only establish when things are
13588 * actually up, hence no need to break them. */
13589 WARN_ON(crtc->active);
13590
13591 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13592 WARN_ON(encoder->connectors_active);
13593 encoder->base.crtc = NULL;
13594 }
13595 }
13596
13597 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13598 /*
13599 * We start out with underrun reporting disabled to avoid races.
13600 * For correct bookkeeping mark this on active crtcs.
13601 *
13602 * Also on gmch platforms we dont have any hardware bits to
13603 * disable the underrun reporting. Which means we need to start
13604 * out with underrun reporting disabled also on inactive pipes,
13605 * since otherwise we'll complain about the garbage we read when
13606 * e.g. coming up after runtime pm.
13607 *
13608 * No protection against concurrent access is required - at
13609 * worst a fifo underrun happens which also sets this to false.
13610 */
13611 crtc->cpu_fifo_underrun_disabled = true;
13612 crtc->pch_fifo_underrun_disabled = true;
13613 }
13614 }
13615
13616 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13617 {
13618 struct intel_connector *connector;
13619 struct drm_device *dev = encoder->base.dev;
13620
13621 /* We need to check both for a crtc link (meaning that the
13622 * encoder is active and trying to read from a pipe) and the
13623 * pipe itself being active. */
13624 bool has_active_crtc = encoder->base.crtc &&
13625 to_intel_crtc(encoder->base.crtc)->active;
13626
13627 if (encoder->connectors_active && !has_active_crtc) {
13628 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13629 encoder->base.base.id,
13630 encoder->base.name);
13631
13632 /* Connector is active, but has no active pipe. This is
13633 * fallout from our resume register restoring. Disable
13634 * the encoder manually again. */
13635 if (encoder->base.crtc) {
13636 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13637 encoder->base.base.id,
13638 encoder->base.name);
13639 encoder->disable(encoder);
13640 if (encoder->post_disable)
13641 encoder->post_disable(encoder);
13642 }
13643 encoder->base.crtc = NULL;
13644 encoder->connectors_active = false;
13645
13646 /* Inconsistent output/port/pipe state happens presumably due to
13647 * a bug in one of the get_hw_state functions. Or someplace else
13648 * in our code, like the register restore mess on resume. Clamp
13649 * things to off as a safer default. */
13650 for_each_intel_connector(dev, connector) {
13651 if (connector->encoder != encoder)
13652 continue;
13653 connector->base.dpms = DRM_MODE_DPMS_OFF;
13654 connector->base.encoder = NULL;
13655 }
13656 }
13657 /* Enabled encoders without active connectors will be fixed in
13658 * the crtc fixup. */
13659 }
13660
13661 void i915_redisable_vga_power_on(struct drm_device *dev)
13662 {
13663 struct drm_i915_private *dev_priv = dev->dev_private;
13664 u32 vga_reg = i915_vgacntrl_reg(dev);
13665
13666 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13667 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13668 i915_disable_vga(dev);
13669 }
13670 }
13671
13672 void i915_redisable_vga(struct drm_device *dev)
13673 {
13674 struct drm_i915_private *dev_priv = dev->dev_private;
13675
13676 /* This function can be called both from intel_modeset_setup_hw_state or
13677 * at a very early point in our resume sequence, where the power well
13678 * structures are not yet restored. Since this function is at a very
13679 * paranoid "someone might have enabled VGA while we were not looking"
13680 * level, just check if the power well is enabled instead of trying to
13681 * follow the "don't touch the power well if we don't need it" policy
13682 * the rest of the driver uses. */
13683 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13684 return;
13685
13686 i915_redisable_vga_power_on(dev);
13687 }
13688
13689 static bool primary_get_hw_state(struct intel_crtc *crtc)
13690 {
13691 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13692
13693 if (!crtc->active)
13694 return false;
13695
13696 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13697 }
13698
13699 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13700 {
13701 struct drm_i915_private *dev_priv = dev->dev_private;
13702 enum pipe pipe;
13703 struct intel_crtc *crtc;
13704 struct intel_encoder *encoder;
13705 struct intel_connector *connector;
13706 int i;
13707
13708 for_each_intel_crtc(dev, crtc) {
13709 memset(crtc->config, 0, sizeof(*crtc->config));
13710
13711 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13712
13713 crtc->active = dev_priv->display.get_pipe_config(crtc,
13714 crtc->config);
13715
13716 crtc->base.state->enable = crtc->active;
13717 crtc->base.enabled = crtc->active;
13718 crtc->primary_enabled = primary_get_hw_state(crtc);
13719
13720 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13721 crtc->base.base.id,
13722 crtc->active ? "enabled" : "disabled");
13723 }
13724
13725 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13726 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13727
13728 pll->on = pll->get_hw_state(dev_priv, pll,
13729 &pll->config.hw_state);
13730 pll->active = 0;
13731 pll->config.crtc_mask = 0;
13732 for_each_intel_crtc(dev, crtc) {
13733 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13734 pll->active++;
13735 pll->config.crtc_mask |= 1 << crtc->pipe;
13736 }
13737 }
13738
13739 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13740 pll->name, pll->config.crtc_mask, pll->on);
13741
13742 if (pll->config.crtc_mask)
13743 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13744 }
13745
13746 for_each_intel_encoder(dev, encoder) {
13747 pipe = 0;
13748
13749 if (encoder->get_hw_state(encoder, &pipe)) {
13750 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13751 encoder->base.crtc = &crtc->base;
13752 encoder->get_config(encoder, crtc->config);
13753 } else {
13754 encoder->base.crtc = NULL;
13755 }
13756
13757 encoder->connectors_active = false;
13758 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13759 encoder->base.base.id,
13760 encoder->base.name,
13761 encoder->base.crtc ? "enabled" : "disabled",
13762 pipe_name(pipe));
13763 }
13764
13765 for_each_intel_connector(dev, connector) {
13766 if (connector->get_hw_state(connector)) {
13767 connector->base.dpms = DRM_MODE_DPMS_ON;
13768 connector->encoder->connectors_active = true;
13769 connector->base.encoder = &connector->encoder->base;
13770 } else {
13771 connector->base.dpms = DRM_MODE_DPMS_OFF;
13772 connector->base.encoder = NULL;
13773 }
13774 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13775 connector->base.base.id,
13776 connector->base.name,
13777 connector->base.encoder ? "enabled" : "disabled");
13778 }
13779 }
13780
13781 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13782 * and i915 state tracking structures. */
13783 void intel_modeset_setup_hw_state(struct drm_device *dev,
13784 bool force_restore)
13785 {
13786 struct drm_i915_private *dev_priv = dev->dev_private;
13787 enum pipe pipe;
13788 struct intel_crtc *crtc;
13789 struct intel_encoder *encoder;
13790 int i;
13791
13792 intel_modeset_readout_hw_state(dev);
13793
13794 /*
13795 * Now that we have the config, copy it to each CRTC struct
13796 * Note that this could go away if we move to using crtc_config
13797 * checking everywhere.
13798 */
13799 for_each_intel_crtc(dev, crtc) {
13800 if (crtc->active && i915.fastboot) {
13801 intel_mode_from_pipe_config(&crtc->base.mode,
13802 crtc->config);
13803 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13804 crtc->base.base.id);
13805 drm_mode_debug_printmodeline(&crtc->base.mode);
13806 }
13807 }
13808
13809 /* HW state is read out, now we need to sanitize this mess. */
13810 for_each_intel_encoder(dev, encoder) {
13811 intel_sanitize_encoder(encoder);
13812 }
13813
13814 for_each_pipe(dev_priv, pipe) {
13815 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13816 intel_sanitize_crtc(crtc);
13817 intel_dump_pipe_config(crtc, crtc->config,
13818 "[setup_hw_state]");
13819 }
13820
13821 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13822 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13823
13824 if (!pll->on || pll->active)
13825 continue;
13826
13827 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13828
13829 pll->disable(dev_priv, pll);
13830 pll->on = false;
13831 }
13832
13833 if (IS_GEN9(dev))
13834 skl_wm_get_hw_state(dev);
13835 else if (HAS_PCH_SPLIT(dev))
13836 ilk_wm_get_hw_state(dev);
13837
13838 if (force_restore) {
13839 i915_redisable_vga(dev);
13840
13841 /*
13842 * We need to use raw interfaces for restoring state to avoid
13843 * checking (bogus) intermediate states.
13844 */
13845 for_each_pipe(dev_priv, pipe) {
13846 struct drm_crtc *crtc =
13847 dev_priv->pipe_to_crtc_mapping[pipe];
13848
13849 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13850 crtc->primary->fb);
13851 }
13852 } else {
13853 intel_modeset_update_staged_output_state(dev);
13854 }
13855
13856 intel_modeset_check_state(dev);
13857 }
13858
13859 void intel_modeset_gem_init(struct drm_device *dev)
13860 {
13861 struct drm_i915_private *dev_priv = dev->dev_private;
13862 struct drm_crtc *c;
13863 struct drm_i915_gem_object *obj;
13864
13865 mutex_lock(&dev->struct_mutex);
13866 intel_init_gt_powersave(dev);
13867 mutex_unlock(&dev->struct_mutex);
13868
13869 /*
13870 * There may be no VBT; and if the BIOS enabled SSC we can
13871 * just keep using it to avoid unnecessary flicker. Whereas if the
13872 * BIOS isn't using it, don't assume it will work even if the VBT
13873 * indicates as much.
13874 */
13875 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13876 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13877 DREF_SSC1_ENABLE);
13878
13879 intel_modeset_init_hw(dev);
13880
13881 intel_setup_overlay(dev);
13882
13883 /*
13884 * Make sure any fbs we allocated at startup are properly
13885 * pinned & fenced. When we do the allocation it's too early
13886 * for this.
13887 */
13888 mutex_lock(&dev->struct_mutex);
13889 for_each_crtc(dev, c) {
13890 obj = intel_fb_obj(c->primary->fb);
13891 if (obj == NULL)
13892 continue;
13893
13894 if (intel_pin_and_fence_fb_obj(c->primary,
13895 c->primary->fb,
13896 NULL)) {
13897 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13898 to_intel_crtc(c)->pipe);
13899 drm_framebuffer_unreference(c->primary->fb);
13900 c->primary->fb = NULL;
13901 update_state_fb(c->primary);
13902 }
13903 }
13904 mutex_unlock(&dev->struct_mutex);
13905
13906 intel_backlight_register(dev);
13907 }
13908
13909 void intel_connector_unregister(struct intel_connector *intel_connector)
13910 {
13911 struct drm_connector *connector = &intel_connector->base;
13912
13913 intel_panel_destroy_backlight(connector);
13914 drm_connector_unregister(connector);
13915 }
13916
13917 void intel_modeset_cleanup(struct drm_device *dev)
13918 {
13919 struct drm_i915_private *dev_priv = dev->dev_private;
13920 struct drm_connector *connector;
13921
13922 intel_disable_gt_powersave(dev);
13923
13924 intel_backlight_unregister(dev);
13925
13926 /*
13927 * Interrupts and polling as the first thing to avoid creating havoc.
13928 * Too much stuff here (turning of connectors, ...) would
13929 * experience fancy races otherwise.
13930 */
13931 intel_irq_uninstall(dev_priv);
13932
13933 /*
13934 * Due to the hpd irq storm handling the hotplug work can re-arm the
13935 * poll handlers. Hence disable polling after hpd handling is shut down.
13936 */
13937 drm_kms_helper_poll_fini(dev);
13938
13939 mutex_lock(&dev->struct_mutex);
13940
13941 intel_unregister_dsm_handler();
13942
13943 intel_fbc_disable(dev);
13944
13945 mutex_unlock(&dev->struct_mutex);
13946
13947 /* flush any delayed tasks or pending work */
13948 flush_scheduled_work();
13949
13950 /* destroy the backlight and sysfs files before encoders/connectors */
13951 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13952 struct intel_connector *intel_connector;
13953
13954 intel_connector = to_intel_connector(connector);
13955 intel_connector->unregister(intel_connector);
13956 }
13957
13958 drm_mode_config_cleanup(dev);
13959
13960 intel_cleanup_overlay(dev);
13961
13962 mutex_lock(&dev->struct_mutex);
13963 intel_cleanup_gt_powersave(dev);
13964 mutex_unlock(&dev->struct_mutex);
13965 }
13966
13967 /*
13968 * Return which encoder is currently attached for connector.
13969 */
13970 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13971 {
13972 return &intel_attached_encoder(connector)->base;
13973 }
13974
13975 void intel_connector_attach_encoder(struct intel_connector *connector,
13976 struct intel_encoder *encoder)
13977 {
13978 connector->encoder = encoder;
13979 drm_mode_connector_attach_encoder(&connector->base,
13980 &encoder->base);
13981 }
13982
13983 /*
13984 * set vga decode state - true == enable VGA decode
13985 */
13986 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13987 {
13988 struct drm_i915_private *dev_priv = dev->dev_private;
13989 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13990 u16 gmch_ctrl;
13991
13992 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13993 DRM_ERROR("failed to read control word\n");
13994 return -EIO;
13995 }
13996
13997 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13998 return 0;
13999
14000 if (state)
14001 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14002 else
14003 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14004
14005 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14006 DRM_ERROR("failed to write control word\n");
14007 return -EIO;
14008 }
14009
14010 return 0;
14011 }
14012
14013 struct intel_display_error_state {
14014
14015 u32 power_well_driver;
14016
14017 int num_transcoders;
14018
14019 struct intel_cursor_error_state {
14020 u32 control;
14021 u32 position;
14022 u32 base;
14023 u32 size;
14024 } cursor[I915_MAX_PIPES];
14025
14026 struct intel_pipe_error_state {
14027 bool power_domain_on;
14028 u32 source;
14029 u32 stat;
14030 } pipe[I915_MAX_PIPES];
14031
14032 struct intel_plane_error_state {
14033 u32 control;
14034 u32 stride;
14035 u32 size;
14036 u32 pos;
14037 u32 addr;
14038 u32 surface;
14039 u32 tile_offset;
14040 } plane[I915_MAX_PIPES];
14041
14042 struct intel_transcoder_error_state {
14043 bool power_domain_on;
14044 enum transcoder cpu_transcoder;
14045
14046 u32 conf;
14047
14048 u32 htotal;
14049 u32 hblank;
14050 u32 hsync;
14051 u32 vtotal;
14052 u32 vblank;
14053 u32 vsync;
14054 } transcoder[4];
14055 };
14056
14057 struct intel_display_error_state *
14058 intel_display_capture_error_state(struct drm_device *dev)
14059 {
14060 struct drm_i915_private *dev_priv = dev->dev_private;
14061 struct intel_display_error_state *error;
14062 int transcoders[] = {
14063 TRANSCODER_A,
14064 TRANSCODER_B,
14065 TRANSCODER_C,
14066 TRANSCODER_EDP,
14067 };
14068 int i;
14069
14070 if (INTEL_INFO(dev)->num_pipes == 0)
14071 return NULL;
14072
14073 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14074 if (error == NULL)
14075 return NULL;
14076
14077 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14078 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14079
14080 for_each_pipe(dev_priv, i) {
14081 error->pipe[i].power_domain_on =
14082 __intel_display_power_is_enabled(dev_priv,
14083 POWER_DOMAIN_PIPE(i));
14084 if (!error->pipe[i].power_domain_on)
14085 continue;
14086
14087 error->cursor[i].control = I915_READ(CURCNTR(i));
14088 error->cursor[i].position = I915_READ(CURPOS(i));
14089 error->cursor[i].base = I915_READ(CURBASE(i));
14090
14091 error->plane[i].control = I915_READ(DSPCNTR(i));
14092 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14093 if (INTEL_INFO(dev)->gen <= 3) {
14094 error->plane[i].size = I915_READ(DSPSIZE(i));
14095 error->plane[i].pos = I915_READ(DSPPOS(i));
14096 }
14097 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14098 error->plane[i].addr = I915_READ(DSPADDR(i));
14099 if (INTEL_INFO(dev)->gen >= 4) {
14100 error->plane[i].surface = I915_READ(DSPSURF(i));
14101 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14102 }
14103
14104 error->pipe[i].source = I915_READ(PIPESRC(i));
14105
14106 if (HAS_GMCH_DISPLAY(dev))
14107 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14108 }
14109
14110 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14111 if (HAS_DDI(dev_priv->dev))
14112 error->num_transcoders++; /* Account for eDP. */
14113
14114 for (i = 0; i < error->num_transcoders; i++) {
14115 enum transcoder cpu_transcoder = transcoders[i];
14116
14117 error->transcoder[i].power_domain_on =
14118 __intel_display_power_is_enabled(dev_priv,
14119 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14120 if (!error->transcoder[i].power_domain_on)
14121 continue;
14122
14123 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14124
14125 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14126 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14127 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14128 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14129 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14130 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14131 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14132 }
14133
14134 return error;
14135 }
14136
14137 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14138
14139 void
14140 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14141 struct drm_device *dev,
14142 struct intel_display_error_state *error)
14143 {
14144 struct drm_i915_private *dev_priv = dev->dev_private;
14145 int i;
14146
14147 if (!error)
14148 return;
14149
14150 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14151 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14152 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14153 error->power_well_driver);
14154 for_each_pipe(dev_priv, i) {
14155 err_printf(m, "Pipe [%d]:\n", i);
14156 err_printf(m, " Power: %s\n",
14157 error->pipe[i].power_domain_on ? "on" : "off");
14158 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14159 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14160
14161 err_printf(m, "Plane [%d]:\n", i);
14162 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14163 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14164 if (INTEL_INFO(dev)->gen <= 3) {
14165 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14166 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14167 }
14168 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14169 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14170 if (INTEL_INFO(dev)->gen >= 4) {
14171 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14172 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14173 }
14174
14175 err_printf(m, "Cursor [%d]:\n", i);
14176 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14177 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14178 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14179 }
14180
14181 for (i = 0; i < error->num_transcoders; i++) {
14182 err_printf(m, "CPU transcoder: %c\n",
14183 transcoder_name(error->transcoder[i].cpu_transcoder));
14184 err_printf(m, " Power: %s\n",
14185 error->transcoder[i].power_domain_on ? "on" : "off");
14186 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14187 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14188 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14189 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14190 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14191 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14192 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14193 }
14194 }
14195
14196 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14197 {
14198 struct intel_crtc *crtc;
14199
14200 for_each_intel_crtc(dev, crtc) {
14201 struct intel_unpin_work *work;
14202
14203 spin_lock_irq(&dev->event_lock);
14204
14205 work = crtc->unpin_work;
14206
14207 if (work && work->event &&
14208 work->event->base.file_priv == file) {
14209 kfree(work->event);
14210 work->event = NULL;
14211 }
14212
14213 spin_unlock_irq(&dev->event_lock);
14214 }
14215 }
Linux kernel - Deliverables
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