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drm/i915/bdw: BDW Software Turbo
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103 static void chv_prepare_pll(struct intel_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4860000, .max = 6700000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
415 {
416 struct drm_device *dev = crtc->dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, crtc, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
427 int refclk)
428 {
429 struct drm_device *dev = crtc->dev;
430 const intel_limit_t *limit;
431
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
433 if (intel_is_dual_link_lvds(dev)) {
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_dual_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_dual_lvds;
438 } else {
439 if (refclk == 100000)
440 limit = &intel_limits_ironlake_single_lvds_100m;
441 else
442 limit = &intel_limits_ironlake_single_lvds;
443 }
444 } else
445 limit = &intel_limits_ironlake_dac;
446
447 return limit;
448 }
449
450 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
451 {
452 struct drm_device *dev = crtc->dev;
453 const intel_limit_t *limit;
454
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
456 if (intel_is_dual_link_lvds(dev))
457 limit = &intel_limits_g4x_dual_channel_lvds;
458 else
459 limit = &intel_limits_g4x_single_channel_lvds;
460 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
461 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
462 limit = &intel_limits_g4x_hdmi;
463 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
464 limit = &intel_limits_g4x_sdvo;
465 } else /* The option is for other outputs */
466 limit = &intel_limits_i9xx_sdvo;
467
468 return limit;
469 }
470
471 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
472 {
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
475
476 if (HAS_PCH_SPLIT(dev))
477 limit = intel_ironlake_limit(crtc, refclk);
478 else if (IS_G4X(dev)) {
479 limit = intel_g4x_limit(crtc);
480 } else if (IS_PINEVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_pineview_lvds;
483 else
484 limit = &intel_limits_pineview_sdvo;
485 } else if (IS_CHERRYVIEW(dev)) {
486 limit = &intel_limits_chv;
487 } else if (IS_VALLEYVIEW(dev)) {
488 limit = &intel_limits_vlv;
489 } else if (!IS_GEN2(dev)) {
490 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
491 limit = &intel_limits_i9xx_lvds;
492 else
493 limit = &intel_limits_i9xx_sdvo;
494 } else {
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
496 limit = &intel_limits_i8xx_lvds;
497 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
498 limit = &intel_limits_i8xx_dvo;
499 else
500 limit = &intel_limits_i8xx_dac;
501 }
502 return limit;
503 }
504
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk, intel_clock_t *clock)
507 {
508 clock->m = clock->m2 + 2;
509 clock->p = clock->p1 * clock->p2;
510 if (WARN_ON(clock->n == 0 || clock->p == 0))
511 return;
512 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
513 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
514 }
515
516 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
517 {
518 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
519 }
520
521 static void i9xx_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = i9xx_dpll_compute_m(clock);
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static void chv_clock(int refclk, intel_clock_t *clock)
532 {
533 clock->m = clock->m1 * clock->m2;
534 clock->p = clock->p1 * clock->p2;
535 if (WARN_ON(clock->n == 0 || clock->p == 0))
536 return;
537 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
538 clock->n << 22);
539 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
540 }
541
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
543 /**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
551 {
552 if (clock->n < limit->n.min || limit->n.max < clock->n)
553 INTELPllInvalid("n out of range\n");
554 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560
561 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
562 if (clock->m1 <= clock->m2)
563 INTELPllInvalid("m1 <= m2\n");
564
565 if (!IS_VALLEYVIEW(dev)) {
566 if (clock->p < limit->p.min || limit->p.max < clock->p)
567 INTELPllInvalid("p out of range\n");
568 if (clock->m < limit->m.min || limit->m.max < clock->m)
569 INTELPllInvalid("m out of range\n");
570 }
571
572 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
576 */
577 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
578 INTELPllInvalid("dot out of range\n");
579
580 return true;
581 }
582
583 static bool
584 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
585 int target, int refclk, intel_clock_t *match_clock,
586 intel_clock_t *best_clock)
587 {
588 struct drm_device *dev = crtc->dev;
589 intel_clock_t clock;
590 int err = target;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
593 /*
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
597 */
598 if (intel_is_dual_link_lvds(dev))
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610
611 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
612 clock.m1++) {
613 for (clock.m2 = limit->m2.min;
614 clock.m2 <= limit->m2.max; clock.m2++) {
615 if (clock.m2 >= clock.m1)
616 break;
617 for (clock.n = limit->n.min;
618 clock.n <= limit->n.max; clock.n++) {
619 for (clock.p1 = limit->p1.min;
620 clock.p1 <= limit->p1.max; clock.p1++) {
621 int this_err;
622
623 i9xx_clock(refclk, &clock);
624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
626 continue;
627 if (match_clock &&
628 clock.p != match_clock->p)
629 continue;
630
631 this_err = abs(clock.dot - target);
632 if (this_err < err) {
633 *best_clock = clock;
634 err = this_err;
635 }
636 }
637 }
638 }
639 }
640
641 return (err != target);
642 }
643
644 static bool
645 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
646 int target, int refclk, intel_clock_t *match_clock,
647 intel_clock_t *best_clock)
648 {
649 struct drm_device *dev = crtc->dev;
650 intel_clock_t clock;
651 int err = target;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 /*
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
658 */
659 if (intel_is_dual_link_lvds(dev))
660 clock.p2 = limit->p2.p2_fast;
661 else
662 clock.p2 = limit->p2.p2_slow;
663 } else {
664 if (target < limit->p2.dot_limit)
665 clock.p2 = limit->p2.p2_slow;
666 else
667 clock.p2 = limit->p2.p2_fast;
668 }
669
670 memset(best_clock, 0, sizeof(*best_clock));
671
672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
673 clock.m1++) {
674 for (clock.m2 = limit->m2.min;
675 clock.m2 <= limit->m2.max; clock.m2++) {
676 for (clock.n = limit->n.min;
677 clock.n <= limit->n.max; clock.n++) {
678 for (clock.p1 = limit->p1.min;
679 clock.p1 <= limit->p1.max; clock.p1++) {
680 int this_err;
681
682 pineview_clock(refclk, &clock);
683 if (!intel_PLL_is_valid(dev, limit,
684 &clock))
685 continue;
686 if (match_clock &&
687 clock.p != match_clock->p)
688 continue;
689
690 this_err = abs(clock.dot - target);
691 if (this_err < err) {
692 *best_clock = clock;
693 err = this_err;
694 }
695 }
696 }
697 }
698 }
699
700 return (err != target);
701 }
702
703 static bool
704 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707 {
708 struct drm_device *dev = crtc->dev;
709 intel_clock_t clock;
710 int max_n;
711 bool found;
712 /* approximately equals target * 0.00585 */
713 int err_most = (target >> 8) + (target >> 9);
714 found = false;
715
716 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
741 i9xx_clock(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745
746 this_err = abs(clock.dot - target);
747 if (this_err < err_most) {
748 *best_clock = clock;
749 err_most = this_err;
750 max_n = clock.n;
751 found = true;
752 }
753 }
754 }
755 }
756 }
757 return found;
758 }
759
760 static bool
761 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
764 {
765 struct drm_device *dev = crtc->dev;
766 intel_clock_t clock;
767 unsigned int bestppm = 1000000;
768 /* min update 19.2 MHz */
769 int max_n = min(limit->n.max, refclk / 19200);
770 bool found = false;
771
772 target *= 5; /* fast clock */
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
778 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
779 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
780 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
781 clock.p = clock.p1 * clock.p2;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
784 unsigned int ppm, diff;
785
786 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
787 refclk * clock.m1);
788
789 vlv_clock(refclk, &clock);
790
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794
795 diff = abs(clock.dot - target);
796 ppm = div_u64(1000000ULL * diff, target);
797
798 if (ppm < 100 && clock.p > best_clock->p) {
799 bestppm = 0;
800 *best_clock = clock;
801 found = true;
802 }
803
804 if (bestppm >= 10 && ppm < bestppm - 10) {
805 bestppm = ppm;
806 *best_clock = clock;
807 found = true;
808 }
809 }
810 }
811 }
812 }
813
814 return found;
815 }
816
817 static bool
818 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
819 int target, int refclk, intel_clock_t *match_clock,
820 intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824 uint64_t m2;
825 int found = false;
826
827 memset(best_clock, 0, sizeof(*best_clock));
828
829 /*
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
833 */
834 clock.n = 1, clock.m1 = 2;
835 target *= 5; /* fast clock */
836
837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
838 for (clock.p2 = limit->p2.p2_fast;
839 clock.p2 >= limit->p2.p2_slow;
840 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
841
842 clock.p = clock.p1 * clock.p2;
843
844 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
845 clock.n) << 22, refclk * clock.m1);
846
847 if (m2 > INT_MAX/clock.m1)
848 continue;
849
850 clock.m2 = m2;
851
852 chv_clock(refclk, &clock);
853
854 if (!intel_PLL_is_valid(dev, limit, &clock))
855 continue;
856
857 /* based on hardware requirement, prefer bigger p
858 */
859 if (clock.p > best_clock->p) {
860 *best_clock = clock;
861 found = true;
862 }
863 }
864 }
865
866 return found;
867 }
868
869 bool intel_crtc_active(struct drm_crtc *crtc)
870 {
871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
872
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
875 *
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
878 *
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
881 */
882 return intel_crtc->active && crtc->primary->fb &&
883 intel_crtc->config.adjusted_mode.crtc_clock;
884 }
885
886 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
887 enum pipe pipe)
888 {
889 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
891
892 return intel_crtc->config.cpu_transcoder;
893 }
894
895 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
896 {
897 struct drm_i915_private *dev_priv = dev->dev_private;
898 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
899
900 frame = I915_READ(frame_reg);
901
902 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
904 pipe_name(pipe));
905 }
906
907 /**
908 * intel_wait_for_vblank - wait for vblank on a given pipe
909 * @dev: drm device
910 * @pipe: pipe to wait for
911 *
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
913 * mode setting code.
914 */
915 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
916 {
917 struct drm_i915_private *dev_priv = dev->dev_private;
918 int pipestat_reg = PIPESTAT(pipe);
919
920 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
921 g4x_wait_for_vblank(dev, pipe);
922 return;
923 }
924
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
927 *
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
934 * vblanks...
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
937 */
938 I915_WRITE(pipestat_reg,
939 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
940
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg) &
943 PIPE_VBLANK_INTERRUPT_STATUS,
944 50))
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
946 pipe_name(pipe));
947 }
948
949 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 reg = PIPEDSL(pipe);
953 u32 line1, line2;
954 u32 line_mask;
955
956 if (IS_GEN2(dev))
957 line_mask = DSL_LINEMASK_GEN2;
958 else
959 line_mask = DSL_LINEMASK_GEN3;
960
961 line1 = I915_READ(reg) & line_mask;
962 mdelay(5);
963 line2 = I915_READ(reg) & line_mask;
964
965 return line1 == line2;
966 }
967
968 /*
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @dev: drm device
971 * @pipe: pipe to wait for
972 *
973 * After disabling a pipe, we can't wait for vblank in the usual way,
974 * spinning on the vblank interrupt status bit, since we won't actually
975 * see an interrupt when the pipe is disabled.
976 *
977 * On Gen4 and above:
978 * wait for the pipe register state bit to turn off
979 *
980 * Otherwise:
981 * wait for the display line value to settle (it usually
982 * ends up stopping at the start of the next frame).
983 *
984 */
985 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
986 {
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
989 pipe);
990
991 if (INTEL_INFO(dev)->gen >= 4) {
992 int reg = PIPECONF(cpu_transcoder);
993
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
996 100))
997 WARN(1, "pipe_off wait timed out\n");
998 } else {
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1002 }
1003 }
1004
1005 /*
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1009 *
1010 * Returns true if @port is connected, false otherwise.
1011 */
1012 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1013 struct intel_digital_port *port)
1014 {
1015 u32 bit;
1016
1017 if (HAS_PCH_IBX(dev_priv->dev)) {
1018 switch (port->port) {
1019 case PORT_B:
1020 bit = SDE_PORTB_HOTPLUG;
1021 break;
1022 case PORT_C:
1023 bit = SDE_PORTC_HOTPLUG;
1024 break;
1025 case PORT_D:
1026 bit = SDE_PORTD_HOTPLUG;
1027 break;
1028 default:
1029 return true;
1030 }
1031 } else {
1032 switch (port->port) {
1033 case PORT_B:
1034 bit = SDE_PORTB_HOTPLUG_CPT;
1035 break;
1036 case PORT_C:
1037 bit = SDE_PORTC_HOTPLUG_CPT;
1038 break;
1039 case PORT_D:
1040 bit = SDE_PORTD_HOTPLUG_CPT;
1041 break;
1042 default:
1043 return true;
1044 }
1045 }
1046
1047 return I915_READ(SDEISR) & bit;
1048 }
1049
1050 static const char *state_string(bool enabled)
1051 {
1052 return enabled ? "on" : "off";
1053 }
1054
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private *dev_priv,
1057 enum pipe pipe, bool state)
1058 {
1059 int reg;
1060 u32 val;
1061 bool cur_state;
1062
1063 reg = DPLL(pipe);
1064 val = I915_READ(reg);
1065 cur_state = !!(val & DPLL_VCO_ENABLE);
1066 WARN(cur_state != state,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state), state_string(cur_state));
1069 }
1070
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1073 {
1074 u32 val;
1075 bool cur_state;
1076
1077 mutex_lock(&dev_priv->dpio_lock);
1078 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1079 mutex_unlock(&dev_priv->dpio_lock);
1080
1081 cur_state = val & DSI_PLL_VCO_EN;
1082 WARN(cur_state != state,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state), state_string(cur_state));
1085 }
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1088
1089 struct intel_shared_dpll *
1090 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1091 {
1092 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1093
1094 if (crtc->config.shared_dpll < 0)
1095 return NULL;
1096
1097 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1098 }
1099
1100 /* For ILK+ */
1101 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1102 struct intel_shared_dpll *pll,
1103 bool state)
1104 {
1105 bool cur_state;
1106 struct intel_dpll_hw_state hw_state;
1107
1108 if (WARN (!pll,
1109 "asserting DPLL %s with no DPLL\n", state_string(state)))
1110 return;
1111
1112 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1113 WARN(cur_state != state,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll->name, state_string(state), state_string(cur_state));
1116 }
1117
1118 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1125 pipe);
1126
1127 if (HAS_DDI(dev_priv->dev)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1132 } else {
1133 reg = FDI_TX_CTL(pipe);
1134 val = I915_READ(reg);
1135 cur_state = !!(val & FDI_TX_ENABLE);
1136 }
1137 WARN(cur_state != state,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140 }
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1143
1144 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1145 enum pipe pipe, bool state)
1146 {
1147 int reg;
1148 u32 val;
1149 bool cur_state;
1150
1151 reg = FDI_RX_CTL(pipe);
1152 val = I915_READ(reg);
1153 cur_state = !!(val & FDI_RX_ENABLE);
1154 WARN(cur_state != state,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state), state_string(cur_state));
1157 }
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1162 enum pipe pipe)
1163 {
1164 int reg;
1165 u32 val;
1166
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1169 return;
1170
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv->dev))
1173 return;
1174
1175 reg = FDI_TX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186
1187 reg = FDI_RX_CTL(pipe);
1188 val = I915_READ(reg);
1189 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1190 WARN(cur_state != state,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state), state_string(cur_state));
1193 }
1194
1195 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1196 enum pipe pipe)
1197 {
1198 struct drm_device *dev = dev_priv->dev;
1199 int pp_reg;
1200 u32 val;
1201 enum pipe panel_pipe = PIPE_A;
1202 bool locked = true;
1203
1204 if (WARN_ON(HAS_DDI(dev)))
1205 return;
1206
1207 if (HAS_PCH_SPLIT(dev)) {
1208 u32 port_sel;
1209
1210 pp_reg = PCH_PP_CONTROL;
1211 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1212
1213 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1214 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1215 panel_pipe = PIPE_B;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1220 panel_pipe = pipe;
1221 } else {
1222 pp_reg = PP_CONTROL;
1223 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1224 panel_pipe = PIPE_B;
1225 }
1226
1227 val = I915_READ(pp_reg);
1228 if (!(val & PANEL_POWER_ON) ||
1229 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1230 locked = false;
1231
1232 WARN(panel_pipe == pipe && locked,
1233 "panel assertion failure, pipe %c regs locked\n",
1234 pipe_name(pipe));
1235 }
1236
1237 static void assert_cursor(struct drm_i915_private *dev_priv,
1238 enum pipe pipe, bool state)
1239 {
1240 struct drm_device *dev = dev_priv->dev;
1241 bool cur_state;
1242
1243 if (IS_845G(dev) || IS_I865G(dev))
1244 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1245 else
1246 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1247
1248 WARN(cur_state != state,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1254
1255 void assert_pipe(struct drm_i915_private *dev_priv,
1256 enum pipe pipe, bool state)
1257 {
1258 int reg;
1259 u32 val;
1260 bool cur_state;
1261 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1262 pipe);
1263
1264 /* if we need the pipe A quirk it must be always on */
1265 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1266 state = true;
1267
1268 if (!intel_display_power_enabled(dev_priv,
1269 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1270 cur_state = false;
1271 } else {
1272 reg = PIPECONF(cpu_transcoder);
1273 val = I915_READ(reg);
1274 cur_state = !!(val & PIPECONF_ENABLE);
1275 }
1276
1277 WARN(cur_state != state,
1278 "pipe %c assertion failure (expected %s, current %s)\n",
1279 pipe_name(pipe), state_string(state), state_string(cur_state));
1280 }
1281
1282 static void assert_plane(struct drm_i915_private *dev_priv,
1283 enum plane plane, bool state)
1284 {
1285 int reg;
1286 u32 val;
1287 bool cur_state;
1288
1289 reg = DSPCNTR(plane);
1290 val = I915_READ(reg);
1291 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1292 WARN(cur_state != state,
1293 "plane %c assertion failure (expected %s, current %s)\n",
1294 plane_name(plane), state_string(state), state_string(cur_state));
1295 }
1296
1297 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1298 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1299
1300 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1301 enum pipe pipe)
1302 {
1303 struct drm_device *dev = dev_priv->dev;
1304 int reg, i;
1305 u32 val;
1306 int cur_pipe;
1307
1308 /* Primary planes are fixed to pipes on gen4+ */
1309 if (INTEL_INFO(dev)->gen >= 4) {
1310 reg = DSPCNTR(pipe);
1311 val = I915_READ(reg);
1312 WARN(val & DISPLAY_PLANE_ENABLE,
1313 "plane %c assertion failure, should be disabled but not\n",
1314 plane_name(pipe));
1315 return;
1316 }
1317
1318 /* Need to check both planes against the pipe */
1319 for_each_pipe(dev_priv, i) {
1320 reg = DSPCNTR(i);
1321 val = I915_READ(reg);
1322 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1323 DISPPLANE_SEL_PIPE_SHIFT;
1324 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1325 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(i), pipe_name(pipe));
1327 }
1328 }
1329
1330 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332 {
1333 struct drm_device *dev = dev_priv->dev;
1334 int reg, sprite;
1335 u32 val;
1336
1337 if (IS_VALLEYVIEW(dev)) {
1338 for_each_sprite(pipe, sprite) {
1339 reg = SPCNTR(pipe, sprite);
1340 val = I915_READ(reg);
1341 WARN(val & SP_ENABLE,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 sprite_name(pipe, sprite), pipe_name(pipe));
1344 }
1345 } else if (INTEL_INFO(dev)->gen >= 7) {
1346 reg = SPRCTL(pipe);
1347 val = I915_READ(reg);
1348 WARN(val & SPRITE_ENABLE,
1349 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1350 plane_name(pipe), pipe_name(pipe));
1351 } else if (INTEL_INFO(dev)->gen >= 5) {
1352 reg = DVSCNTR(pipe);
1353 val = I915_READ(reg);
1354 WARN(val & DVS_ENABLE,
1355 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(pipe), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1361 {
1362 u32 val;
1363 bool enabled;
1364
1365 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1366
1367 val = I915_READ(PCH_DREF_CONTROL);
1368 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1369 DREF_SUPERSPREAD_SOURCE_MASK));
1370 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1371 }
1372
1373 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1374 enum pipe pipe)
1375 {
1376 int reg;
1377 u32 val;
1378 bool enabled;
1379
1380 reg = PCH_TRANSCONF(pipe);
1381 val = I915_READ(reg);
1382 enabled = !!(val & TRANS_ENABLE);
1383 WARN(enabled,
1384 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1385 pipe_name(pipe));
1386 }
1387
1388 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1389 enum pipe pipe, u32 port_sel, u32 val)
1390 {
1391 if ((val & DP_PORT_EN) == 0)
1392 return false;
1393
1394 if (HAS_PCH_CPT(dev_priv->dev)) {
1395 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1396 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1397 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1398 return false;
1399 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1400 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1401 return false;
1402 } else {
1403 if ((val & DP_PIPE_MASK) != (pipe << 30))
1404 return false;
1405 }
1406 return true;
1407 }
1408
1409 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, u32 val)
1411 {
1412 if ((val & SDVO_ENABLE) == 0)
1413 return false;
1414
1415 if (HAS_PCH_CPT(dev_priv->dev)) {
1416 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1417 return false;
1418 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1419 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1420 return false;
1421 } else {
1422 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1423 return false;
1424 }
1425 return true;
1426 }
1427
1428 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1429 enum pipe pipe, u32 val)
1430 {
1431 if ((val & LVDS_PORT_EN) == 0)
1432 return false;
1433
1434 if (HAS_PCH_CPT(dev_priv->dev)) {
1435 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 return false;
1437 } else {
1438 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1439 return false;
1440 }
1441 return true;
1442 }
1443
1444 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, u32 val)
1446 {
1447 if ((val & ADPA_DAC_ENABLE) == 0)
1448 return false;
1449 if (HAS_PCH_CPT(dev_priv->dev)) {
1450 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1451 return false;
1452 } else {
1453 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1454 return false;
1455 }
1456 return true;
1457 }
1458
1459 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe, int reg, u32 port_sel)
1461 {
1462 u32 val = I915_READ(reg);
1463 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1464 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1465 reg, pipe_name(pipe));
1466
1467 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1468 && (val & DP_PIPEB_SELECT),
1469 "IBX PCH dp port still using transcoder B\n");
1470 }
1471
1472 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, int reg)
1474 {
1475 u32 val = I915_READ(reg);
1476 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1477 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1478 reg, pipe_name(pipe));
1479
1480 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1481 && (val & SDVO_PIPE_B_SELECT),
1482 "IBX PCH hdmi port still using transcoder B\n");
1483 }
1484
1485 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487 {
1488 int reg;
1489 u32 val;
1490
1491 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1492 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1493 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1494
1495 reg = PCH_ADPA;
1496 val = I915_READ(reg);
1497 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1498 "PCH VGA enabled on transcoder %c, should be disabled\n",
1499 pipe_name(pipe));
1500
1501 reg = PCH_LVDS;
1502 val = I915_READ(reg);
1503 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1504 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1505 pipe_name(pipe));
1506
1507 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1508 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1509 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1510 }
1511
1512 static void intel_init_dpio(struct drm_device *dev)
1513 {
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (!IS_VALLEYVIEW(dev))
1517 return;
1518
1519 /*
1520 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1521 * CHV x1 PHY (DP/HDMI D)
1522 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1523 */
1524 if (IS_CHERRYVIEW(dev)) {
1525 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1527 } else {
1528 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1529 }
1530 }
1531
1532 static void vlv_enable_pll(struct intel_crtc *crtc)
1533 {
1534 struct drm_device *dev = crtc->base.dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
1536 int reg = DPLL(crtc->pipe);
1537 u32 dpll = crtc->config.dpll_hw_state.dpll;
1538
1539 assert_pipe_disabled(dev_priv, crtc->pipe);
1540
1541 /* No really, not for ILK+ */
1542 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1543
1544 /* PLL is protected by panel, make sure we can write it */
1545 if (IS_MOBILE(dev_priv->dev))
1546 assert_panel_unlocked(dev_priv, crtc->pipe);
1547
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150);
1551
1552 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1554
1555 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1556 POSTING_READ(DPLL_MD(crtc->pipe));
1557
1558 /* We do this three times for luck */
1559 I915_WRITE(reg, dpll);
1560 POSTING_READ(reg);
1561 udelay(150); /* wait for warmup */
1562 I915_WRITE(reg, dpll);
1563 POSTING_READ(reg);
1564 udelay(150); /* wait for warmup */
1565 I915_WRITE(reg, dpll);
1566 POSTING_READ(reg);
1567 udelay(150); /* wait for warmup */
1568 }
1569
1570 static void chv_enable_pll(struct intel_crtc *crtc)
1571 {
1572 struct drm_device *dev = crtc->base.dev;
1573 struct drm_i915_private *dev_priv = dev->dev_private;
1574 int pipe = crtc->pipe;
1575 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1576 u32 tmp;
1577
1578 assert_pipe_disabled(dev_priv, crtc->pipe);
1579
1580 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1581
1582 mutex_lock(&dev_priv->dpio_lock);
1583
1584 /* Enable back the 10bit clock to display controller */
1585 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1586 tmp |= DPIO_DCLKP_EN;
1587 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1588
1589 /*
1590 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1591 */
1592 udelay(1);
1593
1594 /* Enable PLL */
1595 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1596
1597 /* Check PLL is locked */
1598 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1599 DRM_ERROR("PLL %d failed to lock\n", pipe);
1600
1601 /* not sure when this should be written */
1602 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1603 POSTING_READ(DPLL_MD(pipe));
1604
1605 mutex_unlock(&dev_priv->dpio_lock);
1606 }
1607
1608 static void i9xx_enable_pll(struct intel_crtc *crtc)
1609 {
1610 struct drm_device *dev = crtc->base.dev;
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612 int reg = DPLL(crtc->pipe);
1613 u32 dpll = crtc->config.dpll_hw_state.dpll;
1614
1615 assert_pipe_disabled(dev_priv, crtc->pipe);
1616
1617 /* No really, not for ILK+ */
1618 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1619
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev) && !IS_I830(dev))
1622 assert_panel_unlocked(dev_priv, crtc->pipe);
1623
1624 I915_WRITE(reg, dpll);
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1664 {
1665 /* Don't disable pipe A or pipe A PLLs if needed */
1666 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1667 return;
1668
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv, pipe);
1671
1672 I915_WRITE(DPLL(pipe), 0);
1673 POSTING_READ(DPLL(pipe));
1674 }
1675
1676 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1677 {
1678 u32 val = 0;
1679
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv, pipe);
1682
1683 /*
1684 * Leave integrated clock source and reference clock enabled for pipe B.
1685 * The latter is needed for VGA hotplug / manual detection.
1686 */
1687 if (pipe == PIPE_B)
1688 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1689 I915_WRITE(DPLL(pipe), val);
1690 POSTING_READ(DPLL(pipe));
1691
1692 }
1693
1694 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1697 u32 val;
1698
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv, pipe);
1701
1702 /* Set PLL en = 0 */
1703 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1704 if (pipe != PIPE_A)
1705 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1706 I915_WRITE(DPLL(pipe), val);
1707 POSTING_READ(DPLL(pipe));
1708
1709 mutex_lock(&dev_priv->dpio_lock);
1710
1711 /* Disable 10bit clock to display controller */
1712 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1713 val &= ~DPIO_DCLKP_EN;
1714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1715
1716 /* disable left/right clock distribution */
1717 if (pipe != PIPE_B) {
1718 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1719 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1720 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1721 } else {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1723 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1725 }
1726
1727 mutex_unlock(&dev_priv->dpio_lock);
1728 }
1729
1730 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1731 struct intel_digital_port *dport)
1732 {
1733 u32 port_mask;
1734 int dpll_reg;
1735
1736 switch (dport->port) {
1737 case PORT_B:
1738 port_mask = DPLL_PORTB_READY_MASK;
1739 dpll_reg = DPLL(0);
1740 break;
1741 case PORT_C:
1742 port_mask = DPLL_PORTC_READY_MASK;
1743 dpll_reg = DPLL(0);
1744 break;
1745 case PORT_D:
1746 port_mask = DPLL_PORTD_READY_MASK;
1747 dpll_reg = DPIO_PHY_STATUS;
1748 break;
1749 default:
1750 BUG();
1751 }
1752
1753 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1754 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1755 port_name(dport->port), I915_READ(dpll_reg));
1756 }
1757
1758 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1759 {
1760 struct drm_device *dev = crtc->base.dev;
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1763
1764 if (WARN_ON(pll == NULL))
1765 return;
1766
1767 WARN_ON(!pll->refcount);
1768 if (pll->active == 0) {
1769 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1770 WARN_ON(pll->on);
1771 assert_shared_dpll_disabled(dev_priv, pll);
1772
1773 pll->mode_set(dev_priv, pll);
1774 }
1775 }
1776
1777 /**
1778 * intel_enable_shared_dpll - enable PCH PLL
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe PLL to enable
1781 *
1782 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1783 * drives the transcoder clock.
1784 */
1785 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1786 {
1787 struct drm_device *dev = crtc->base.dev;
1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1790
1791 if (WARN_ON(pll == NULL))
1792 return;
1793
1794 if (WARN_ON(pll->refcount == 0))
1795 return;
1796
1797 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1798 pll->name, pll->active, pll->on,
1799 crtc->base.base.id);
1800
1801 if (pll->active++) {
1802 WARN_ON(!pll->on);
1803 assert_shared_dpll_enabled(dev_priv, pll);
1804 return;
1805 }
1806 WARN_ON(pll->on);
1807
1808 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1809
1810 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1811 pll->enable(dev_priv, pll);
1812 pll->on = true;
1813 }
1814
1815 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1816 {
1817 struct drm_device *dev = crtc->base.dev;
1818 struct drm_i915_private *dev_priv = dev->dev_private;
1819 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1820
1821 /* PCH only available on ILK+ */
1822 BUG_ON(INTEL_INFO(dev)->gen < 5);
1823 if (WARN_ON(pll == NULL))
1824 return;
1825
1826 if (WARN_ON(pll->refcount == 0))
1827 return;
1828
1829 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1830 pll->name, pll->active, pll->on,
1831 crtc->base.base.id);
1832
1833 if (WARN_ON(pll->active == 0)) {
1834 assert_shared_dpll_disabled(dev_priv, pll);
1835 return;
1836 }
1837
1838 assert_shared_dpll_enabled(dev_priv, pll);
1839 WARN_ON(!pll->on);
1840 if (--pll->active)
1841 return;
1842
1843 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1844 pll->disable(dev_priv, pll);
1845 pll->on = false;
1846
1847 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1848 }
1849
1850 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1851 enum pipe pipe)
1852 {
1853 struct drm_device *dev = dev_priv->dev;
1854 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1856 uint32_t reg, val, pipeconf_val;
1857
1858 /* PCH only available on ILK+ */
1859 BUG_ON(INTEL_INFO(dev)->gen < 5);
1860
1861 /* Make sure PCH DPLL is enabled */
1862 assert_shared_dpll_enabled(dev_priv,
1863 intel_crtc_to_shared_dpll(intel_crtc));
1864
1865 /* FDI must be feeding us bits for PCH ports */
1866 assert_fdi_tx_enabled(dev_priv, pipe);
1867 assert_fdi_rx_enabled(dev_priv, pipe);
1868
1869 if (HAS_PCH_CPT(dev)) {
1870 /* Workaround: Set the timing override bit before enabling the
1871 * pch transcoder. */
1872 reg = TRANS_CHICKEN2(pipe);
1873 val = I915_READ(reg);
1874 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1875 I915_WRITE(reg, val);
1876 }
1877
1878 reg = PCH_TRANSCONF(pipe);
1879 val = I915_READ(reg);
1880 pipeconf_val = I915_READ(PIPECONF(pipe));
1881
1882 if (HAS_PCH_IBX(dev_priv->dev)) {
1883 /*
1884 * make the BPC in transcoder be consistent with
1885 * that in pipeconf reg.
1886 */
1887 val &= ~PIPECONF_BPC_MASK;
1888 val |= pipeconf_val & PIPECONF_BPC_MASK;
1889 }
1890
1891 val &= ~TRANS_INTERLACE_MASK;
1892 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1893 if (HAS_PCH_IBX(dev_priv->dev) &&
1894 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1895 val |= TRANS_LEGACY_INTERLACED_ILK;
1896 else
1897 val |= TRANS_INTERLACED;
1898 else
1899 val |= TRANS_PROGRESSIVE;
1900
1901 I915_WRITE(reg, val | TRANS_ENABLE);
1902 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1903 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1904 }
1905
1906 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1907 enum transcoder cpu_transcoder)
1908 {
1909 u32 val, pipeconf_val;
1910
1911 /* PCH only available on ILK+ */
1912 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1913
1914 /* FDI must be feeding us bits for PCH ports */
1915 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1916 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1917
1918 /* Workaround: set timing override bit. */
1919 val = I915_READ(_TRANSA_CHICKEN2);
1920 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1921 I915_WRITE(_TRANSA_CHICKEN2, val);
1922
1923 val = TRANS_ENABLE;
1924 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1925
1926 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1927 PIPECONF_INTERLACED_ILK)
1928 val |= TRANS_INTERLACED;
1929 else
1930 val |= TRANS_PROGRESSIVE;
1931
1932 I915_WRITE(LPT_TRANSCONF, val);
1933 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1934 DRM_ERROR("Failed to enable PCH transcoder\n");
1935 }
1936
1937 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1938 enum pipe pipe)
1939 {
1940 struct drm_device *dev = dev_priv->dev;
1941 uint32_t reg, val;
1942
1943 /* FDI relies on the transcoder */
1944 assert_fdi_tx_disabled(dev_priv, pipe);
1945 assert_fdi_rx_disabled(dev_priv, pipe);
1946
1947 /* Ports must be off as well */
1948 assert_pch_ports_disabled(dev_priv, pipe);
1949
1950 reg = PCH_TRANSCONF(pipe);
1951 val = I915_READ(reg);
1952 val &= ~TRANS_ENABLE;
1953 I915_WRITE(reg, val);
1954 /* wait for PCH transcoder off, transcoder state */
1955 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1956 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1957
1958 if (!HAS_PCH_IBX(dev)) {
1959 /* Workaround: Clear the timing override chicken bit again. */
1960 reg = TRANS_CHICKEN2(pipe);
1961 val = I915_READ(reg);
1962 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1963 I915_WRITE(reg, val);
1964 }
1965 }
1966
1967 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1968 {
1969 u32 val;
1970
1971 val = I915_READ(LPT_TRANSCONF);
1972 val &= ~TRANS_ENABLE;
1973 I915_WRITE(LPT_TRANSCONF, val);
1974 /* wait for PCH transcoder off, transcoder state */
1975 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1976 DRM_ERROR("Failed to disable PCH transcoder\n");
1977
1978 /* Workaround: clear timing override bit. */
1979 val = I915_READ(_TRANSA_CHICKEN2);
1980 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1981 I915_WRITE(_TRANSA_CHICKEN2, val);
1982 }
1983
1984 /**
1985 * intel_enable_pipe - enable a pipe, asserting requirements
1986 * @crtc: crtc responsible for the pipe
1987 *
1988 * Enable @crtc's pipe, making sure that various hardware specific requirements
1989 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1990 */
1991 static void intel_enable_pipe(struct intel_crtc *crtc)
1992 {
1993 struct drm_device *dev = crtc->base.dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 enum pipe pipe = crtc->pipe;
1996 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1997 pipe);
1998 enum pipe pch_transcoder;
1999 int reg;
2000 u32 val;
2001
2002 assert_planes_disabled(dev_priv, pipe);
2003 assert_cursor_disabled(dev_priv, pipe);
2004 assert_sprites_disabled(dev_priv, pipe);
2005
2006 if (HAS_PCH_LPT(dev_priv->dev))
2007 pch_transcoder = TRANSCODER_A;
2008 else
2009 pch_transcoder = pipe;
2010
2011 /*
2012 * A pipe without a PLL won't actually be able to drive bits from
2013 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2014 * need the check.
2015 */
2016 if (!HAS_PCH_SPLIT(dev_priv->dev))
2017 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2018 assert_dsi_pll_enabled(dev_priv);
2019 else
2020 assert_pll_enabled(dev_priv, pipe);
2021 else {
2022 if (crtc->config.has_pch_encoder) {
2023 /* if driving the PCH, we need FDI enabled */
2024 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2025 assert_fdi_tx_pll_enabled(dev_priv,
2026 (enum pipe) cpu_transcoder);
2027 }
2028 /* FIXME: assert CPU port conditions for SNB+ */
2029 }
2030
2031 reg = PIPECONF(cpu_transcoder);
2032 val = I915_READ(reg);
2033 if (val & PIPECONF_ENABLE) {
2034 WARN_ON(!(pipe == PIPE_A &&
2035 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2036 return;
2037 }
2038
2039 I915_WRITE(reg, val | PIPECONF_ENABLE);
2040 POSTING_READ(reg);
2041 }
2042
2043 /**
2044 * intel_disable_pipe - disable a pipe, asserting requirements
2045 * @dev_priv: i915 private structure
2046 * @pipe: pipe to disable
2047 *
2048 * Disable @pipe, making sure that various hardware specific requirements
2049 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2050 *
2051 * @pipe should be %PIPE_A or %PIPE_B.
2052 *
2053 * Will wait until the pipe has shut down before returning.
2054 */
2055 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
2057 {
2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
2060 int reg;
2061 u32 val;
2062
2063 /*
2064 * Make sure planes won't keep trying to pump pixels to us,
2065 * or we might hang the display.
2066 */
2067 assert_planes_disabled(dev_priv, pipe);
2068 assert_cursor_disabled(dev_priv, pipe);
2069 assert_sprites_disabled(dev_priv, pipe);
2070
2071 /* Don't disable pipe A or pipe A PLLs if needed */
2072 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2073 return;
2074
2075 reg = PIPECONF(cpu_transcoder);
2076 val = I915_READ(reg);
2077 if ((val & PIPECONF_ENABLE) == 0)
2078 return;
2079
2080 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2081 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2082 }
2083
2084 /*
2085 * Plane regs are double buffered, going from enabled->disabled needs a
2086 * trigger in order to latch. The display address reg provides this.
2087 */
2088 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2089 enum plane plane)
2090 {
2091 struct drm_device *dev = dev_priv->dev;
2092 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2093
2094 I915_WRITE(reg, I915_READ(reg));
2095 POSTING_READ(reg);
2096 }
2097
2098 /**
2099 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100 * @plane: plane to be enabled
2101 * @crtc: crtc for the plane
2102 *
2103 * Enable @plane on @crtc, making sure that the pipe is running first.
2104 */
2105 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2106 struct drm_crtc *crtc)
2107 {
2108 struct drm_device *dev = plane->dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2111
2112 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2114
2115 if (intel_crtc->primary_enabled)
2116 return;
2117
2118 intel_crtc->primary_enabled = true;
2119
2120 dev_priv->display.update_primary_plane(crtc, plane->fb,
2121 crtc->x, crtc->y);
2122
2123 /*
2124 * BDW signals flip done immediately if the plane
2125 * is disabled, even if the plane enable is already
2126 * armed to occur at the next vblank :(
2127 */
2128 if (IS_BROADWELL(dev))
2129 intel_wait_for_vblank(dev, intel_crtc->pipe);
2130 }
2131
2132 /**
2133 * intel_disable_primary_hw_plane - disable the primary hardware plane
2134 * @plane: plane to be disabled
2135 * @crtc: crtc for the plane
2136 *
2137 * Disable @plane on @crtc, making sure that the pipe is running first.
2138 */
2139 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2140 struct drm_crtc *crtc)
2141 {
2142 struct drm_device *dev = plane->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2145
2146 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2147
2148 if (!intel_crtc->primary_enabled)
2149 return;
2150
2151 intel_crtc->primary_enabled = false;
2152
2153 dev_priv->display.update_primary_plane(crtc, plane->fb,
2154 crtc->x, crtc->y);
2155 }
2156
2157 static bool need_vtd_wa(struct drm_device *dev)
2158 {
2159 #ifdef CONFIG_INTEL_IOMMU
2160 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2161 return true;
2162 #endif
2163 return false;
2164 }
2165
2166 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2167 {
2168 int tile_height;
2169
2170 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2171 return ALIGN(height, tile_height);
2172 }
2173
2174 int
2175 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2176 struct drm_i915_gem_object *obj,
2177 struct intel_engine_cs *pipelined)
2178 {
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 u32 alignment;
2181 int ret;
2182
2183 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2184
2185 switch (obj->tiling_mode) {
2186 case I915_TILING_NONE:
2187 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2188 alignment = 128 * 1024;
2189 else if (INTEL_INFO(dev)->gen >= 4)
2190 alignment = 4 * 1024;
2191 else
2192 alignment = 64 * 1024;
2193 break;
2194 case I915_TILING_X:
2195 /* pin() will align the object as required by fence */
2196 alignment = 0;
2197 break;
2198 case I915_TILING_Y:
2199 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2200 return -EINVAL;
2201 default:
2202 BUG();
2203 }
2204
2205 /* Note that the w/a also requires 64 PTE of padding following the
2206 * bo. We currently fill all unused PTE with the shadow page and so
2207 * we should always have valid PTE following the scanout preventing
2208 * the VT-d warning.
2209 */
2210 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2211 alignment = 256 * 1024;
2212
2213 dev_priv->mm.interruptible = false;
2214 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2215 if (ret)
2216 goto err_interruptible;
2217
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always install
2221 * a fence as the cost is not that onerous.
2222 */
2223 ret = i915_gem_object_get_fence(obj);
2224 if (ret)
2225 goto err_unpin;
2226
2227 i915_gem_object_pin_fence(obj);
2228
2229 dev_priv->mm.interruptible = true;
2230 return 0;
2231
2232 err_unpin:
2233 i915_gem_object_unpin_from_display_plane(obj);
2234 err_interruptible:
2235 dev_priv->mm.interruptible = true;
2236 return ret;
2237 }
2238
2239 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2240 {
2241 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2242
2243 i915_gem_object_unpin_fence(obj);
2244 i915_gem_object_unpin_from_display_plane(obj);
2245 }
2246
2247 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2248 * is assumed to be a power-of-two. */
2249 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2250 unsigned int tiling_mode,
2251 unsigned int cpp,
2252 unsigned int pitch)
2253 {
2254 if (tiling_mode != I915_TILING_NONE) {
2255 unsigned int tile_rows, tiles;
2256
2257 tile_rows = *y / 8;
2258 *y %= 8;
2259
2260 tiles = *x / (512/cpp);
2261 *x %= 512/cpp;
2262
2263 return tile_rows * pitch * 8 + tiles * 4096;
2264 } else {
2265 unsigned int offset;
2266
2267 offset = *y * pitch + *x * cpp;
2268 *y = 0;
2269 *x = (offset & 4095) / cpp;
2270 return offset & -4096;
2271 }
2272 }
2273
2274 int intel_format_to_fourcc(int format)
2275 {
2276 switch (format) {
2277 case DISPPLANE_8BPP:
2278 return DRM_FORMAT_C8;
2279 case DISPPLANE_BGRX555:
2280 return DRM_FORMAT_XRGB1555;
2281 case DISPPLANE_BGRX565:
2282 return DRM_FORMAT_RGB565;
2283 default:
2284 case DISPPLANE_BGRX888:
2285 return DRM_FORMAT_XRGB8888;
2286 case DISPPLANE_RGBX888:
2287 return DRM_FORMAT_XBGR8888;
2288 case DISPPLANE_BGRX101010:
2289 return DRM_FORMAT_XRGB2101010;
2290 case DISPPLANE_RGBX101010:
2291 return DRM_FORMAT_XBGR2101010;
2292 }
2293 }
2294
2295 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2296 struct intel_plane_config *plane_config)
2297 {
2298 struct drm_device *dev = crtc->base.dev;
2299 struct drm_i915_gem_object *obj = NULL;
2300 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2301 u32 base = plane_config->base;
2302
2303 if (plane_config->size == 0)
2304 return false;
2305
2306 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2307 plane_config->size);
2308 if (!obj)
2309 return false;
2310
2311 if (plane_config->tiled) {
2312 obj->tiling_mode = I915_TILING_X;
2313 obj->stride = crtc->base.primary->fb->pitches[0];
2314 }
2315
2316 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2317 mode_cmd.width = crtc->base.primary->fb->width;
2318 mode_cmd.height = crtc->base.primary->fb->height;
2319 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2320
2321 mutex_lock(&dev->struct_mutex);
2322
2323 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2324 &mode_cmd, obj)) {
2325 DRM_DEBUG_KMS("intel fb init failed\n");
2326 goto out_unref_obj;
2327 }
2328
2329 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2330 mutex_unlock(&dev->struct_mutex);
2331
2332 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2333 return true;
2334
2335 out_unref_obj:
2336 drm_gem_object_unreference(&obj->base);
2337 mutex_unlock(&dev->struct_mutex);
2338 return false;
2339 }
2340
2341 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2342 struct intel_plane_config *plane_config)
2343 {
2344 struct drm_device *dev = intel_crtc->base.dev;
2345 struct drm_crtc *c;
2346 struct intel_crtc *i;
2347 struct drm_i915_gem_object *obj;
2348
2349 if (!intel_crtc->base.primary->fb)
2350 return;
2351
2352 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2353 return;
2354
2355 kfree(intel_crtc->base.primary->fb);
2356 intel_crtc->base.primary->fb = NULL;
2357
2358 /*
2359 * Failed to alloc the obj, check to see if we should share
2360 * an fb with another CRTC instead
2361 */
2362 for_each_crtc(dev, c) {
2363 i = to_intel_crtc(c);
2364
2365 if (c == &intel_crtc->base)
2366 continue;
2367
2368 if (!i->active)
2369 continue;
2370
2371 obj = intel_fb_obj(c->primary->fb);
2372 if (obj == NULL)
2373 continue;
2374
2375 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2376 drm_framebuffer_reference(c->primary->fb);
2377 intel_crtc->base.primary->fb = c->primary->fb;
2378 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2379 break;
2380 }
2381 }
2382 }
2383
2384 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2385 struct drm_framebuffer *fb,
2386 int x, int y)
2387 {
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 struct drm_i915_gem_object *obj;
2392 int plane = intel_crtc->plane;
2393 unsigned long linear_offset;
2394 u32 dspcntr;
2395 u32 reg = DSPCNTR(plane);
2396 int pixel_size;
2397
2398 if (!intel_crtc->primary_enabled) {
2399 I915_WRITE(reg, 0);
2400 if (INTEL_INFO(dev)->gen >= 4)
2401 I915_WRITE(DSPSURF(plane), 0);
2402 else
2403 I915_WRITE(DSPADDR(plane), 0);
2404 POSTING_READ(reg);
2405 return;
2406 }
2407
2408 obj = intel_fb_obj(fb);
2409 if (WARN_ON(obj == NULL))
2410 return;
2411
2412 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2413
2414 dspcntr = DISPPLANE_GAMMA_ENABLE;
2415
2416 dspcntr |= DISPLAY_PLANE_ENABLE;
2417
2418 if (INTEL_INFO(dev)->gen < 4) {
2419 if (intel_crtc->pipe == PIPE_B)
2420 dspcntr |= DISPPLANE_SEL_PIPE_B;
2421
2422 /* pipesrc and dspsize control the size that is scaled from,
2423 * which should always be the user's requested size.
2424 */
2425 I915_WRITE(DSPSIZE(plane),
2426 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2427 (intel_crtc->config.pipe_src_w - 1));
2428 I915_WRITE(DSPPOS(plane), 0);
2429 }
2430
2431 switch (fb->pixel_format) {
2432 case DRM_FORMAT_C8:
2433 dspcntr |= DISPPLANE_8BPP;
2434 break;
2435 case DRM_FORMAT_XRGB1555:
2436 case DRM_FORMAT_ARGB1555:
2437 dspcntr |= DISPPLANE_BGRX555;
2438 break;
2439 case DRM_FORMAT_RGB565:
2440 dspcntr |= DISPPLANE_BGRX565;
2441 break;
2442 case DRM_FORMAT_XRGB8888:
2443 case DRM_FORMAT_ARGB8888:
2444 dspcntr |= DISPPLANE_BGRX888;
2445 break;
2446 case DRM_FORMAT_XBGR8888:
2447 case DRM_FORMAT_ABGR8888:
2448 dspcntr |= DISPPLANE_RGBX888;
2449 break;
2450 case DRM_FORMAT_XRGB2101010:
2451 case DRM_FORMAT_ARGB2101010:
2452 dspcntr |= DISPPLANE_BGRX101010;
2453 break;
2454 case DRM_FORMAT_XBGR2101010:
2455 case DRM_FORMAT_ABGR2101010:
2456 dspcntr |= DISPPLANE_RGBX101010;
2457 break;
2458 default:
2459 BUG();
2460 }
2461
2462 if (INTEL_INFO(dev)->gen >= 4 &&
2463 obj->tiling_mode != I915_TILING_NONE)
2464 dspcntr |= DISPPLANE_TILED;
2465
2466 if (IS_G4X(dev))
2467 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2468
2469 linear_offset = y * fb->pitches[0] + x * pixel_size;
2470
2471 if (INTEL_INFO(dev)->gen >= 4) {
2472 intel_crtc->dspaddr_offset =
2473 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2474 pixel_size,
2475 fb->pitches[0]);
2476 linear_offset -= intel_crtc->dspaddr_offset;
2477 } else {
2478 intel_crtc->dspaddr_offset = linear_offset;
2479 }
2480
2481 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2482 dspcntr |= DISPPLANE_ROTATE_180;
2483
2484 x += (intel_crtc->config.pipe_src_w - 1);
2485 y += (intel_crtc->config.pipe_src_h - 1);
2486
2487 /* Finding the last pixel of the last line of the display
2488 data and adding to linear_offset*/
2489 linear_offset +=
2490 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2491 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2492 }
2493
2494 I915_WRITE(reg, dspcntr);
2495
2496 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2497 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2498 fb->pitches[0]);
2499 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2500 if (INTEL_INFO(dev)->gen >= 4) {
2501 I915_WRITE(DSPSURF(plane),
2502 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2503 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2504 I915_WRITE(DSPLINOFF(plane), linear_offset);
2505 } else
2506 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2507 POSTING_READ(reg);
2508 }
2509
2510 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2511 struct drm_framebuffer *fb,
2512 int x, int y)
2513 {
2514 struct drm_device *dev = crtc->dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517 struct drm_i915_gem_object *obj;
2518 int plane = intel_crtc->plane;
2519 unsigned long linear_offset;
2520 u32 dspcntr;
2521 u32 reg = DSPCNTR(plane);
2522 int pixel_size;
2523
2524 if (!intel_crtc->primary_enabled) {
2525 I915_WRITE(reg, 0);
2526 I915_WRITE(DSPSURF(plane), 0);
2527 POSTING_READ(reg);
2528 return;
2529 }
2530
2531 obj = intel_fb_obj(fb);
2532 if (WARN_ON(obj == NULL))
2533 return;
2534
2535 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2536
2537 dspcntr = DISPPLANE_GAMMA_ENABLE;
2538
2539 dspcntr |= DISPLAY_PLANE_ENABLE;
2540
2541 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2543
2544 switch (fb->pixel_format) {
2545 case DRM_FORMAT_C8:
2546 dspcntr |= DISPPLANE_8BPP;
2547 break;
2548 case DRM_FORMAT_RGB565:
2549 dspcntr |= DISPPLANE_BGRX565;
2550 break;
2551 case DRM_FORMAT_XRGB8888:
2552 case DRM_FORMAT_ARGB8888:
2553 dspcntr |= DISPPLANE_BGRX888;
2554 break;
2555 case DRM_FORMAT_XBGR8888:
2556 case DRM_FORMAT_ABGR8888:
2557 dspcntr |= DISPPLANE_RGBX888;
2558 break;
2559 case DRM_FORMAT_XRGB2101010:
2560 case DRM_FORMAT_ARGB2101010:
2561 dspcntr |= DISPPLANE_BGRX101010;
2562 break;
2563 case DRM_FORMAT_XBGR2101010:
2564 case DRM_FORMAT_ABGR2101010:
2565 dspcntr |= DISPPLANE_RGBX101010;
2566 break;
2567 default:
2568 BUG();
2569 }
2570
2571 if (obj->tiling_mode != I915_TILING_NONE)
2572 dspcntr |= DISPPLANE_TILED;
2573
2574 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2575 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2576
2577 linear_offset = y * fb->pitches[0] + x * pixel_size;
2578 intel_crtc->dspaddr_offset =
2579 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2580 pixel_size,
2581 fb->pitches[0]);
2582 linear_offset -= intel_crtc->dspaddr_offset;
2583 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2584 dspcntr |= DISPPLANE_ROTATE_180;
2585
2586 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2587 x += (intel_crtc->config.pipe_src_w - 1);
2588 y += (intel_crtc->config.pipe_src_h - 1);
2589
2590 /* Finding the last pixel of the last line of the display
2591 data and adding to linear_offset*/
2592 linear_offset +=
2593 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2594 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2595 }
2596 }
2597
2598 I915_WRITE(reg, dspcntr);
2599
2600 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2601 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2602 fb->pitches[0]);
2603 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2604 I915_WRITE(DSPSURF(plane),
2605 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2606 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2607 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2608 } else {
2609 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2610 I915_WRITE(DSPLINOFF(plane), linear_offset);
2611 }
2612 POSTING_READ(reg);
2613 }
2614
2615 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2616 static int
2617 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2618 int x, int y, enum mode_set_atomic state)
2619 {
2620 struct drm_device *dev = crtc->dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622
2623 if (dev_priv->display.disable_fbc)
2624 dev_priv->display.disable_fbc(dev);
2625 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2626
2627 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2628
2629 return 0;
2630 }
2631
2632 void intel_display_handle_reset(struct drm_device *dev)
2633 {
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 struct drm_crtc *crtc;
2636
2637 /*
2638 * Flips in the rings have been nuked by the reset,
2639 * so complete all pending flips so that user space
2640 * will get its events and not get stuck.
2641 *
2642 * Also update the base address of all primary
2643 * planes to the the last fb to make sure we're
2644 * showing the correct fb after a reset.
2645 *
2646 * Need to make two loops over the crtcs so that we
2647 * don't try to grab a crtc mutex before the
2648 * pending_flip_queue really got woken up.
2649 */
2650
2651 for_each_crtc(dev, crtc) {
2652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 enum plane plane = intel_crtc->plane;
2654
2655 intel_prepare_page_flip(dev, plane);
2656 intel_finish_page_flip_plane(dev, plane);
2657 }
2658
2659 for_each_crtc(dev, crtc) {
2660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2661
2662 drm_modeset_lock(&crtc->mutex, NULL);
2663 /*
2664 * FIXME: Once we have proper support for primary planes (and
2665 * disabling them without disabling the entire crtc) allow again
2666 * a NULL crtc->primary->fb.
2667 */
2668 if (intel_crtc->active && crtc->primary->fb)
2669 dev_priv->display.update_primary_plane(crtc,
2670 crtc->primary->fb,
2671 crtc->x,
2672 crtc->y);
2673 drm_modeset_unlock(&crtc->mutex);
2674 }
2675 }
2676
2677 static int
2678 intel_finish_fb(struct drm_framebuffer *old_fb)
2679 {
2680 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2681 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2682 bool was_interruptible = dev_priv->mm.interruptible;
2683 int ret;
2684
2685 /* Big Hammer, we also need to ensure that any pending
2686 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2687 * current scanout is retired before unpinning the old
2688 * framebuffer.
2689 *
2690 * This should only fail upon a hung GPU, in which case we
2691 * can safely continue.
2692 */
2693 dev_priv->mm.interruptible = false;
2694 ret = i915_gem_object_finish_gpu(obj);
2695 dev_priv->mm.interruptible = was_interruptible;
2696
2697 return ret;
2698 }
2699
2700 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2701 {
2702 struct drm_device *dev = crtc->dev;
2703 struct drm_i915_private *dev_priv = dev->dev_private;
2704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2705 unsigned long flags;
2706 bool pending;
2707
2708 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2709 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2710 return false;
2711
2712 spin_lock_irqsave(&dev->event_lock, flags);
2713 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2714 spin_unlock_irqrestore(&dev->event_lock, flags);
2715
2716 return pending;
2717 }
2718
2719 static int
2720 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2721 struct drm_framebuffer *fb)
2722 {
2723 struct drm_device *dev = crtc->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726 enum pipe pipe = intel_crtc->pipe;
2727 struct drm_framebuffer *old_fb = crtc->primary->fb;
2728 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2729 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2730 int ret;
2731
2732 if (intel_crtc_has_pending_flip(crtc)) {
2733 DRM_ERROR("pipe is still busy with an old pageflip\n");
2734 return -EBUSY;
2735 }
2736
2737 /* no fb bound */
2738 if (!fb) {
2739 DRM_ERROR("No FB bound\n");
2740 return 0;
2741 }
2742
2743 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2744 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2745 plane_name(intel_crtc->plane),
2746 INTEL_INFO(dev)->num_pipes);
2747 return -EINVAL;
2748 }
2749
2750 mutex_lock(&dev->struct_mutex);
2751 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2752 if (ret == 0)
2753 i915_gem_track_fb(old_obj, obj,
2754 INTEL_FRONTBUFFER_PRIMARY(pipe));
2755 mutex_unlock(&dev->struct_mutex);
2756 if (ret != 0) {
2757 DRM_ERROR("pin & fence failed\n");
2758 return ret;
2759 }
2760
2761 /*
2762 * Update pipe size and adjust fitter if needed: the reason for this is
2763 * that in compute_mode_changes we check the native mode (not the pfit
2764 * mode) to see if we can flip rather than do a full mode set. In the
2765 * fastboot case, we'll flip, but if we don't update the pipesrc and
2766 * pfit state, we'll end up with a big fb scanned out into the wrong
2767 * sized surface.
2768 *
2769 * To fix this properly, we need to hoist the checks up into
2770 * compute_mode_changes (or above), check the actual pfit state and
2771 * whether the platform allows pfit disable with pipe active, and only
2772 * then update the pipesrc and pfit state, even on the flip path.
2773 */
2774 if (i915.fastboot) {
2775 const struct drm_display_mode *adjusted_mode =
2776 &intel_crtc->config.adjusted_mode;
2777
2778 I915_WRITE(PIPESRC(intel_crtc->pipe),
2779 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2780 (adjusted_mode->crtc_vdisplay - 1));
2781 if (!intel_crtc->config.pch_pfit.enabled &&
2782 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2783 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2784 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2785 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2786 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2787 }
2788 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2789 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2790 }
2791
2792 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2793
2794 if (intel_crtc->active)
2795 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2796
2797 crtc->primary->fb = fb;
2798 crtc->x = x;
2799 crtc->y = y;
2800
2801 if (old_fb) {
2802 if (intel_crtc->active && old_fb != fb)
2803 intel_wait_for_vblank(dev, intel_crtc->pipe);
2804 mutex_lock(&dev->struct_mutex);
2805 intel_unpin_fb_obj(old_obj);
2806 mutex_unlock(&dev->struct_mutex);
2807 }
2808
2809 mutex_lock(&dev->struct_mutex);
2810 intel_update_fbc(dev);
2811 mutex_unlock(&dev->struct_mutex);
2812
2813 return 0;
2814 }
2815
2816 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2817 {
2818 struct drm_device *dev = crtc->dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 int pipe = intel_crtc->pipe;
2822 u32 reg, temp;
2823
2824 /* enable normal train */
2825 reg = FDI_TX_CTL(pipe);
2826 temp = I915_READ(reg);
2827 if (IS_IVYBRIDGE(dev)) {
2828 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2829 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2830 } else {
2831 temp &= ~FDI_LINK_TRAIN_NONE;
2832 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2833 }
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_NONE;
2844 }
2845 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2846
2847 /* wait one idle pattern time */
2848 POSTING_READ(reg);
2849 udelay(1000);
2850
2851 /* IVB wants error correction enabled */
2852 if (IS_IVYBRIDGE(dev))
2853 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2854 FDI_FE_ERRC_ENABLE);
2855 }
2856
2857 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2858 {
2859 return crtc->base.enabled && crtc->active &&
2860 crtc->config.has_pch_encoder;
2861 }
2862
2863 static void ivb_modeset_global_resources(struct drm_device *dev)
2864 {
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 struct intel_crtc *pipe_B_crtc =
2867 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2868 struct intel_crtc *pipe_C_crtc =
2869 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2870 uint32_t temp;
2871
2872 /*
2873 * When everything is off disable fdi C so that we could enable fdi B
2874 * with all lanes. Note that we don't care about enabled pipes without
2875 * an enabled pch encoder.
2876 */
2877 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2878 !pipe_has_enabled_pch(pipe_C_crtc)) {
2879 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2880 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2881
2882 temp = I915_READ(SOUTH_CHICKEN1);
2883 temp &= ~FDI_BC_BIFURCATION_SELECT;
2884 DRM_DEBUG_KMS("disabling fdi C rx\n");
2885 I915_WRITE(SOUTH_CHICKEN1, temp);
2886 }
2887 }
2888
2889 /* The FDI link training functions for ILK/Ibexpeak. */
2890 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2891 {
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
2896 u32 reg, temp, tries;
2897
2898 /* FDI needs bits from pipe first */
2899 assert_pipe_enabled(dev_priv, pipe);
2900
2901 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2902 for train result */
2903 reg = FDI_RX_IMR(pipe);
2904 temp = I915_READ(reg);
2905 temp &= ~FDI_RX_SYMBOL_LOCK;
2906 temp &= ~FDI_RX_BIT_LOCK;
2907 I915_WRITE(reg, temp);
2908 I915_READ(reg);
2909 udelay(150);
2910
2911 /* enable CPU FDI TX and PCH FDI RX */
2912 reg = FDI_TX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2915 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2916 temp &= ~FDI_LINK_TRAIN_NONE;
2917 temp |= FDI_LINK_TRAIN_PATTERN_1;
2918 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2919
2920 reg = FDI_RX_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~FDI_LINK_TRAIN_NONE;
2923 temp |= FDI_LINK_TRAIN_PATTERN_1;
2924 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2925
2926 POSTING_READ(reg);
2927 udelay(150);
2928
2929 /* Ironlake workaround, enable clock pointer after FDI enable*/
2930 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2931 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2932 FDI_RX_PHASE_SYNC_POINTER_EN);
2933
2934 reg = FDI_RX_IIR(pipe);
2935 for (tries = 0; tries < 5; tries++) {
2936 temp = I915_READ(reg);
2937 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2938
2939 if ((temp & FDI_RX_BIT_LOCK)) {
2940 DRM_DEBUG_KMS("FDI train 1 done.\n");
2941 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2942 break;
2943 }
2944 }
2945 if (tries == 5)
2946 DRM_ERROR("FDI train 1 fail!\n");
2947
2948 /* Train 2 */
2949 reg = FDI_TX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_LINK_TRAIN_NONE;
2952 temp |= FDI_LINK_TRAIN_PATTERN_2;
2953 I915_WRITE(reg, temp);
2954
2955 reg = FDI_RX_CTL(pipe);
2956 temp = I915_READ(reg);
2957 temp &= ~FDI_LINK_TRAIN_NONE;
2958 temp |= FDI_LINK_TRAIN_PATTERN_2;
2959 I915_WRITE(reg, temp);
2960
2961 POSTING_READ(reg);
2962 udelay(150);
2963
2964 reg = FDI_RX_IIR(pipe);
2965 for (tries = 0; tries < 5; tries++) {
2966 temp = I915_READ(reg);
2967 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2968
2969 if (temp & FDI_RX_SYMBOL_LOCK) {
2970 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2971 DRM_DEBUG_KMS("FDI train 2 done.\n");
2972 break;
2973 }
2974 }
2975 if (tries == 5)
2976 DRM_ERROR("FDI train 2 fail!\n");
2977
2978 DRM_DEBUG_KMS("FDI train done\n");
2979
2980 }
2981
2982 static const int snb_b_fdi_train_param[] = {
2983 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2984 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2985 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2986 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2987 };
2988
2989 /* The FDI link training functions for SNB/Cougarpoint. */
2990 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2991 {
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995 int pipe = intel_crtc->pipe;
2996 u32 reg, temp, i, retry;
2997
2998 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2999 for train result */
3000 reg = FDI_RX_IMR(pipe);
3001 temp = I915_READ(reg);
3002 temp &= ~FDI_RX_SYMBOL_LOCK;
3003 temp &= ~FDI_RX_BIT_LOCK;
3004 I915_WRITE(reg, temp);
3005
3006 POSTING_READ(reg);
3007 udelay(150);
3008
3009 /* enable CPU FDI TX and PCH FDI RX */
3010 reg = FDI_TX_CTL(pipe);
3011 temp = I915_READ(reg);
3012 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3013 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3014 temp &= ~FDI_LINK_TRAIN_NONE;
3015 temp |= FDI_LINK_TRAIN_PATTERN_1;
3016 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3017 /* SNB-B */
3018 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3019 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3020
3021 I915_WRITE(FDI_RX_MISC(pipe),
3022 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3023
3024 reg = FDI_RX_CTL(pipe);
3025 temp = I915_READ(reg);
3026 if (HAS_PCH_CPT(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3028 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3029 } else {
3030 temp &= ~FDI_LINK_TRAIN_NONE;
3031 temp |= FDI_LINK_TRAIN_PATTERN_1;
3032 }
3033 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3034
3035 POSTING_READ(reg);
3036 udelay(150);
3037
3038 for (i = 0; i < 4; i++) {
3039 reg = FDI_TX_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3042 temp |= snb_b_fdi_train_param[i];
3043 I915_WRITE(reg, temp);
3044
3045 POSTING_READ(reg);
3046 udelay(500);
3047
3048 for (retry = 0; retry < 5; retry++) {
3049 reg = FDI_RX_IIR(pipe);
3050 temp = I915_READ(reg);
3051 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3052 if (temp & FDI_RX_BIT_LOCK) {
3053 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3054 DRM_DEBUG_KMS("FDI train 1 done.\n");
3055 break;
3056 }
3057 udelay(50);
3058 }
3059 if (retry < 5)
3060 break;
3061 }
3062 if (i == 4)
3063 DRM_ERROR("FDI train 1 fail!\n");
3064
3065 /* Train 2 */
3066 reg = FDI_TX_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~FDI_LINK_TRAIN_NONE;
3069 temp |= FDI_LINK_TRAIN_PATTERN_2;
3070 if (IS_GEN6(dev)) {
3071 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3072 /* SNB-B */
3073 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3074 }
3075 I915_WRITE(reg, temp);
3076
3077 reg = FDI_RX_CTL(pipe);
3078 temp = I915_READ(reg);
3079 if (HAS_PCH_CPT(dev)) {
3080 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3081 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3082 } else {
3083 temp &= ~FDI_LINK_TRAIN_NONE;
3084 temp |= FDI_LINK_TRAIN_PATTERN_2;
3085 }
3086 I915_WRITE(reg, temp);
3087
3088 POSTING_READ(reg);
3089 udelay(150);
3090
3091 for (i = 0; i < 4; i++) {
3092 reg = FDI_TX_CTL(pipe);
3093 temp = I915_READ(reg);
3094 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3095 temp |= snb_b_fdi_train_param[i];
3096 I915_WRITE(reg, temp);
3097
3098 POSTING_READ(reg);
3099 udelay(500);
3100
3101 for (retry = 0; retry < 5; retry++) {
3102 reg = FDI_RX_IIR(pipe);
3103 temp = I915_READ(reg);
3104 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3105 if (temp & FDI_RX_SYMBOL_LOCK) {
3106 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3107 DRM_DEBUG_KMS("FDI train 2 done.\n");
3108 break;
3109 }
3110 udelay(50);
3111 }
3112 if (retry < 5)
3113 break;
3114 }
3115 if (i == 4)
3116 DRM_ERROR("FDI train 2 fail!\n");
3117
3118 DRM_DEBUG_KMS("FDI train done.\n");
3119 }
3120
3121 /* Manual link training for Ivy Bridge A0 parts */
3122 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3123 {
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 int pipe = intel_crtc->pipe;
3128 u32 reg, temp, i, j;
3129
3130 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3131 for train result */
3132 reg = FDI_RX_IMR(pipe);
3133 temp = I915_READ(reg);
3134 temp &= ~FDI_RX_SYMBOL_LOCK;
3135 temp &= ~FDI_RX_BIT_LOCK;
3136 I915_WRITE(reg, temp);
3137
3138 POSTING_READ(reg);
3139 udelay(150);
3140
3141 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3142 I915_READ(FDI_RX_IIR(pipe)));
3143
3144 /* Try each vswing and preemphasis setting twice before moving on */
3145 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3146 /* disable first in case we need to retry */
3147 reg = FDI_TX_CTL(pipe);
3148 temp = I915_READ(reg);
3149 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3150 temp &= ~FDI_TX_ENABLE;
3151 I915_WRITE(reg, temp);
3152
3153 reg = FDI_RX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 temp &= ~FDI_LINK_TRAIN_AUTO;
3156 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3157 temp &= ~FDI_RX_ENABLE;
3158 I915_WRITE(reg, temp);
3159
3160 /* enable CPU FDI TX and PCH FDI RX */
3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3164 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3165 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3166 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3167 temp |= snb_b_fdi_train_param[j/2];
3168 temp |= FDI_COMPOSITE_SYNC;
3169 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3170
3171 I915_WRITE(FDI_RX_MISC(pipe),
3172 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3173
3174 reg = FDI_RX_CTL(pipe);
3175 temp = I915_READ(reg);
3176 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3177 temp |= FDI_COMPOSITE_SYNC;
3178 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3179
3180 POSTING_READ(reg);
3181 udelay(1); /* should be 0.5us */
3182
3183 for (i = 0; i < 4; i++) {
3184 reg = FDI_RX_IIR(pipe);
3185 temp = I915_READ(reg);
3186 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3187
3188 if (temp & FDI_RX_BIT_LOCK ||
3189 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3190 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3191 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3192 i);
3193 break;
3194 }
3195 udelay(1); /* should be 0.5us */
3196 }
3197 if (i == 4) {
3198 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3199 continue;
3200 }
3201
3202 /* Train 2 */
3203 reg = FDI_TX_CTL(pipe);
3204 temp = I915_READ(reg);
3205 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3206 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3207 I915_WRITE(reg, temp);
3208
3209 reg = FDI_RX_CTL(pipe);
3210 temp = I915_READ(reg);
3211 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3212 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3213 I915_WRITE(reg, temp);
3214
3215 POSTING_READ(reg);
3216 udelay(2); /* should be 1.5us */
3217
3218 for (i = 0; i < 4; i++) {
3219 reg = FDI_RX_IIR(pipe);
3220 temp = I915_READ(reg);
3221 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3222
3223 if (temp & FDI_RX_SYMBOL_LOCK ||
3224 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3225 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3226 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3227 i);
3228 goto train_done;
3229 }
3230 udelay(2); /* should be 1.5us */
3231 }
3232 if (i == 4)
3233 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3234 }
3235
3236 train_done:
3237 DRM_DEBUG_KMS("FDI train done.\n");
3238 }
3239
3240 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3241 {
3242 struct drm_device *dev = intel_crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = intel_crtc->pipe;
3245 u32 reg, temp;
3246
3247
3248 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3249 reg = FDI_RX_CTL(pipe);
3250 temp = I915_READ(reg);
3251 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3252 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3253 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3254 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3255
3256 POSTING_READ(reg);
3257 udelay(200);
3258
3259 /* Switch from Rawclk to PCDclk */
3260 temp = I915_READ(reg);
3261 I915_WRITE(reg, temp | FDI_PCDCLK);
3262
3263 POSTING_READ(reg);
3264 udelay(200);
3265
3266 /* Enable CPU FDI TX PLL, always on for Ironlake */
3267 reg = FDI_TX_CTL(pipe);
3268 temp = I915_READ(reg);
3269 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3270 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3271
3272 POSTING_READ(reg);
3273 udelay(100);
3274 }
3275 }
3276
3277 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3278 {
3279 struct drm_device *dev = intel_crtc->base.dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 int pipe = intel_crtc->pipe;
3282 u32 reg, temp;
3283
3284 /* Switch from PCDclk to Rawclk */
3285 reg = FDI_RX_CTL(pipe);
3286 temp = I915_READ(reg);
3287 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3288
3289 /* Disable CPU FDI TX PLL */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3293
3294 POSTING_READ(reg);
3295 udelay(100);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3300
3301 /* Wait for the clocks to turn off. */
3302 POSTING_READ(reg);
3303 udelay(100);
3304 }
3305
3306 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3307 {
3308 struct drm_device *dev = crtc->dev;
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3311 int pipe = intel_crtc->pipe;
3312 u32 reg, temp;
3313
3314 /* disable CPU FDI tx and PCH FDI rx */
3315 reg = FDI_TX_CTL(pipe);
3316 temp = I915_READ(reg);
3317 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3318 POSTING_READ(reg);
3319
3320 reg = FDI_RX_CTL(pipe);
3321 temp = I915_READ(reg);
3322 temp &= ~(0x7 << 16);
3323 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3324 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3325
3326 POSTING_READ(reg);
3327 udelay(100);
3328
3329 /* Ironlake workaround, disable clock pointer after downing FDI */
3330 if (HAS_PCH_IBX(dev))
3331 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3332
3333 /* still set train pattern 1 */
3334 reg = FDI_TX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 temp &= ~FDI_LINK_TRAIN_NONE;
3337 temp |= FDI_LINK_TRAIN_PATTERN_1;
3338 I915_WRITE(reg, temp);
3339
3340 reg = FDI_RX_CTL(pipe);
3341 temp = I915_READ(reg);
3342 if (HAS_PCH_CPT(dev)) {
3343 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3344 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3345 } else {
3346 temp &= ~FDI_LINK_TRAIN_NONE;
3347 temp |= FDI_LINK_TRAIN_PATTERN_1;
3348 }
3349 /* BPC in FDI rx is consistent with that in PIPECONF */
3350 temp &= ~(0x07 << 16);
3351 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3352 I915_WRITE(reg, temp);
3353
3354 POSTING_READ(reg);
3355 udelay(100);
3356 }
3357
3358 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3359 {
3360 struct intel_crtc *crtc;
3361
3362 /* Note that we don't need to be called with mode_config.lock here
3363 * as our list of CRTC objects is static for the lifetime of the
3364 * device and so cannot disappear as we iterate. Similarly, we can
3365 * happily treat the predicates as racy, atomic checks as userspace
3366 * cannot claim and pin a new fb without at least acquring the
3367 * struct_mutex and so serialising with us.
3368 */
3369 for_each_intel_crtc(dev, crtc) {
3370 if (atomic_read(&crtc->unpin_work_count) == 0)
3371 continue;
3372
3373 if (crtc->unpin_work)
3374 intel_wait_for_vblank(dev, crtc->pipe);
3375
3376 return true;
3377 }
3378
3379 return false;
3380 }
3381
3382 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3383 {
3384 struct drm_device *dev = crtc->dev;
3385 struct drm_i915_private *dev_priv = dev->dev_private;
3386
3387 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3388 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3389 !intel_crtc_has_pending_flip(crtc),
3390 60*HZ) == 0);
3391
3392 if (crtc->primary->fb) {
3393 mutex_lock(&dev->struct_mutex);
3394 intel_finish_fb(crtc->primary->fb);
3395 mutex_unlock(&dev->struct_mutex);
3396 }
3397 }
3398
3399 /* Program iCLKIP clock to the desired frequency */
3400 static void lpt_program_iclkip(struct drm_crtc *crtc)
3401 {
3402 struct drm_device *dev = crtc->dev;
3403 struct drm_i915_private *dev_priv = dev->dev_private;
3404 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3405 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3406 u32 temp;
3407
3408 mutex_lock(&dev_priv->dpio_lock);
3409
3410 /* It is necessary to ungate the pixclk gate prior to programming
3411 * the divisors, and gate it back when it is done.
3412 */
3413 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3414
3415 /* Disable SSCCTL */
3416 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3417 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3418 SBI_SSCCTL_DISABLE,
3419 SBI_ICLK);
3420
3421 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3422 if (clock == 20000) {
3423 auxdiv = 1;
3424 divsel = 0x41;
3425 phaseinc = 0x20;
3426 } else {
3427 /* The iCLK virtual clock root frequency is in MHz,
3428 * but the adjusted_mode->crtc_clock in in KHz. To get the
3429 * divisors, it is necessary to divide one by another, so we
3430 * convert the virtual clock precision to KHz here for higher
3431 * precision.
3432 */
3433 u32 iclk_virtual_root_freq = 172800 * 1000;
3434 u32 iclk_pi_range = 64;
3435 u32 desired_divisor, msb_divisor_value, pi_value;
3436
3437 desired_divisor = (iclk_virtual_root_freq / clock);
3438 msb_divisor_value = desired_divisor / iclk_pi_range;
3439 pi_value = desired_divisor % iclk_pi_range;
3440
3441 auxdiv = 0;
3442 divsel = msb_divisor_value - 2;
3443 phaseinc = pi_value;
3444 }
3445
3446 /* This should not happen with any sane values */
3447 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3448 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3449 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3450 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3451
3452 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3453 clock,
3454 auxdiv,
3455 divsel,
3456 phasedir,
3457 phaseinc);
3458
3459 /* Program SSCDIVINTPHASE6 */
3460 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3461 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3462 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3463 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3464 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3465 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3466 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3467 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3468
3469 /* Program SSCAUXDIV */
3470 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3471 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3472 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3473 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3474
3475 /* Enable modulator and associated divider */
3476 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3477 temp &= ~SBI_SSCCTL_DISABLE;
3478 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3479
3480 /* Wait for initialization time */
3481 udelay(24);
3482
3483 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3484
3485 mutex_unlock(&dev_priv->dpio_lock);
3486 }
3487
3488 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3489 enum pipe pch_transcoder)
3490 {
3491 struct drm_device *dev = crtc->base.dev;
3492 struct drm_i915_private *dev_priv = dev->dev_private;
3493 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3494
3495 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3496 I915_READ(HTOTAL(cpu_transcoder)));
3497 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3498 I915_READ(HBLANK(cpu_transcoder)));
3499 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3500 I915_READ(HSYNC(cpu_transcoder)));
3501
3502 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3503 I915_READ(VTOTAL(cpu_transcoder)));
3504 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3505 I915_READ(VBLANK(cpu_transcoder)));
3506 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3507 I915_READ(VSYNC(cpu_transcoder)));
3508 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3509 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3510 }
3511
3512 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3513 {
3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 uint32_t temp;
3516
3517 temp = I915_READ(SOUTH_CHICKEN1);
3518 if (temp & FDI_BC_BIFURCATION_SELECT)
3519 return;
3520
3521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3522 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3523
3524 temp |= FDI_BC_BIFURCATION_SELECT;
3525 DRM_DEBUG_KMS("enabling fdi C rx\n");
3526 I915_WRITE(SOUTH_CHICKEN1, temp);
3527 POSTING_READ(SOUTH_CHICKEN1);
3528 }
3529
3530 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3531 {
3532 struct drm_device *dev = intel_crtc->base.dev;
3533 struct drm_i915_private *dev_priv = dev->dev_private;
3534
3535 switch (intel_crtc->pipe) {
3536 case PIPE_A:
3537 break;
3538 case PIPE_B:
3539 if (intel_crtc->config.fdi_lanes > 2)
3540 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3541 else
3542 cpt_enable_fdi_bc_bifurcation(dev);
3543
3544 break;
3545 case PIPE_C:
3546 cpt_enable_fdi_bc_bifurcation(dev);
3547
3548 break;
3549 default:
3550 BUG();
3551 }
3552 }
3553
3554 /*
3555 * Enable PCH resources required for PCH ports:
3556 * - PCH PLLs
3557 * - FDI training & RX/TX
3558 * - update transcoder timings
3559 * - DP transcoding bits
3560 * - transcoder
3561 */
3562 static void ironlake_pch_enable(struct drm_crtc *crtc)
3563 {
3564 struct drm_device *dev = crtc->dev;
3565 struct drm_i915_private *dev_priv = dev->dev_private;
3566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567 int pipe = intel_crtc->pipe;
3568 u32 reg, temp;
3569
3570 assert_pch_transcoder_disabled(dev_priv, pipe);
3571
3572 if (IS_IVYBRIDGE(dev))
3573 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3574
3575 /* Write the TU size bits before fdi link training, so that error
3576 * detection works. */
3577 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3578 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3579
3580 /* For PCH output, training FDI link */
3581 dev_priv->display.fdi_link_train(crtc);
3582
3583 /* We need to program the right clock selection before writing the pixel
3584 * mutliplier into the DPLL. */
3585 if (HAS_PCH_CPT(dev)) {
3586 u32 sel;
3587
3588 temp = I915_READ(PCH_DPLL_SEL);
3589 temp |= TRANS_DPLL_ENABLE(pipe);
3590 sel = TRANS_DPLLB_SEL(pipe);
3591 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3592 temp |= sel;
3593 else
3594 temp &= ~sel;
3595 I915_WRITE(PCH_DPLL_SEL, temp);
3596 }
3597
3598 /* XXX: pch pll's can be enabled any time before we enable the PCH
3599 * transcoder, and we actually should do this to not upset any PCH
3600 * transcoder that already use the clock when we share it.
3601 *
3602 * Note that enable_shared_dpll tries to do the right thing, but
3603 * get_shared_dpll unconditionally resets the pll - we need that to have
3604 * the right LVDS enable sequence. */
3605 intel_enable_shared_dpll(intel_crtc);
3606
3607 /* set transcoder timing, panel must allow it */
3608 assert_panel_unlocked(dev_priv, pipe);
3609 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3610
3611 intel_fdi_normal_train(crtc);
3612
3613 /* For PCH DP, enable TRANS_DP_CTL */
3614 if (HAS_PCH_CPT(dev) &&
3615 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3616 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3617 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3618 reg = TRANS_DP_CTL(pipe);
3619 temp = I915_READ(reg);
3620 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3621 TRANS_DP_SYNC_MASK |
3622 TRANS_DP_BPC_MASK);
3623 temp |= (TRANS_DP_OUTPUT_ENABLE |
3624 TRANS_DP_ENH_FRAMING);
3625 temp |= bpc << 9; /* same format but at 11:9 */
3626
3627 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3628 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3629 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3630 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3631
3632 switch (intel_trans_dp_port_sel(crtc)) {
3633 case PCH_DP_B:
3634 temp |= TRANS_DP_PORT_SEL_B;
3635 break;
3636 case PCH_DP_C:
3637 temp |= TRANS_DP_PORT_SEL_C;
3638 break;
3639 case PCH_DP_D:
3640 temp |= TRANS_DP_PORT_SEL_D;
3641 break;
3642 default:
3643 BUG();
3644 }
3645
3646 I915_WRITE(reg, temp);
3647 }
3648
3649 ironlake_enable_pch_transcoder(dev_priv, pipe);
3650 }
3651
3652 static void lpt_pch_enable(struct drm_crtc *crtc)
3653 {
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3658
3659 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3660
3661 lpt_program_iclkip(crtc);
3662
3663 /* Set transcoder timing. */
3664 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3665
3666 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3667 }
3668
3669 void intel_put_shared_dpll(struct intel_crtc *crtc)
3670 {
3671 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3672
3673 if (pll == NULL)
3674 return;
3675
3676 if (pll->refcount == 0) {
3677 WARN(1, "bad %s refcount\n", pll->name);
3678 return;
3679 }
3680
3681 if (--pll->refcount == 0) {
3682 WARN_ON(pll->on);
3683 WARN_ON(pll->active);
3684 }
3685
3686 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3687 }
3688
3689 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3690 {
3691 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3692 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3693 enum intel_dpll_id i;
3694
3695 if (pll) {
3696 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3697 crtc->base.base.id, pll->name);
3698 intel_put_shared_dpll(crtc);
3699 }
3700
3701 if (HAS_PCH_IBX(dev_priv->dev)) {
3702 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3703 i = (enum intel_dpll_id) crtc->pipe;
3704 pll = &dev_priv->shared_dplls[i];
3705
3706 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3707 crtc->base.base.id, pll->name);
3708
3709 WARN_ON(pll->refcount);
3710
3711 goto found;
3712 }
3713
3714 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3715 pll = &dev_priv->shared_dplls[i];
3716
3717 /* Only want to check enabled timings first */
3718 if (pll->refcount == 0)
3719 continue;
3720
3721 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3722 sizeof(pll->hw_state)) == 0) {
3723 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3724 crtc->base.base.id,
3725 pll->name, pll->refcount, pll->active);
3726
3727 goto found;
3728 }
3729 }
3730
3731 /* Ok no matching timings, maybe there's a free one? */
3732 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3733 pll = &dev_priv->shared_dplls[i];
3734 if (pll->refcount == 0) {
3735 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3736 crtc->base.base.id, pll->name);
3737 goto found;
3738 }
3739 }
3740
3741 return NULL;
3742
3743 found:
3744 if (pll->refcount == 0)
3745 pll->hw_state = crtc->config.dpll_hw_state;
3746
3747 crtc->config.shared_dpll = i;
3748 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3749 pipe_name(crtc->pipe));
3750
3751 pll->refcount++;
3752
3753 return pll;
3754 }
3755
3756 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3757 {
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 int dslreg = PIPEDSL(pipe);
3760 u32 temp;
3761
3762 temp = I915_READ(dslreg);
3763 udelay(500);
3764 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3765 if (wait_for(I915_READ(dslreg) != temp, 5))
3766 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3767 }
3768 }
3769
3770 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3771 {
3772 struct drm_device *dev = crtc->base.dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 int pipe = crtc->pipe;
3775
3776 if (crtc->config.pch_pfit.enabled) {
3777 /* Force use of hard-coded filter coefficients
3778 * as some pre-programmed values are broken,
3779 * e.g. x201.
3780 */
3781 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3782 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3783 PF_PIPE_SEL_IVB(pipe));
3784 else
3785 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3786 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3787 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3788 }
3789 }
3790
3791 static void intel_enable_planes(struct drm_crtc *crtc)
3792 {
3793 struct drm_device *dev = crtc->dev;
3794 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3795 struct drm_plane *plane;
3796 struct intel_plane *intel_plane;
3797
3798 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3799 intel_plane = to_intel_plane(plane);
3800 if (intel_plane->pipe == pipe)
3801 intel_plane_restore(&intel_plane->base);
3802 }
3803 }
3804
3805 static void intel_disable_planes(struct drm_crtc *crtc)
3806 {
3807 struct drm_device *dev = crtc->dev;
3808 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3809 struct drm_plane *plane;
3810 struct intel_plane *intel_plane;
3811
3812 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3813 intel_plane = to_intel_plane(plane);
3814 if (intel_plane->pipe == pipe)
3815 intel_plane_disable(&intel_plane->base);
3816 }
3817 }
3818
3819 void hsw_enable_ips(struct intel_crtc *crtc)
3820 {
3821 struct drm_device *dev = crtc->base.dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823
3824 if (!crtc->config.ips_enabled)
3825 return;
3826
3827 /* We can only enable IPS after we enable a plane and wait for a vblank */
3828 intel_wait_for_vblank(dev, crtc->pipe);
3829
3830 assert_plane_enabled(dev_priv, crtc->plane);
3831 if (IS_BROADWELL(dev)) {
3832 mutex_lock(&dev_priv->rps.hw_lock);
3833 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3834 mutex_unlock(&dev_priv->rps.hw_lock);
3835 /* Quoting Art Runyan: "its not safe to expect any particular
3836 * value in IPS_CTL bit 31 after enabling IPS through the
3837 * mailbox." Moreover, the mailbox may return a bogus state,
3838 * so we need to just enable it and continue on.
3839 */
3840 } else {
3841 I915_WRITE(IPS_CTL, IPS_ENABLE);
3842 /* The bit only becomes 1 in the next vblank, so this wait here
3843 * is essentially intel_wait_for_vblank. If we don't have this
3844 * and don't wait for vblanks until the end of crtc_enable, then
3845 * the HW state readout code will complain that the expected
3846 * IPS_CTL value is not the one we read. */
3847 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3848 DRM_ERROR("Timed out waiting for IPS enable\n");
3849 }
3850 }
3851
3852 void hsw_disable_ips(struct intel_crtc *crtc)
3853 {
3854 struct drm_device *dev = crtc->base.dev;
3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856
3857 if (!crtc->config.ips_enabled)
3858 return;
3859
3860 assert_plane_enabled(dev_priv, crtc->plane);
3861 if (IS_BROADWELL(dev)) {
3862 mutex_lock(&dev_priv->rps.hw_lock);
3863 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3864 mutex_unlock(&dev_priv->rps.hw_lock);
3865 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3866 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3867 DRM_ERROR("Timed out waiting for IPS disable\n");
3868 } else {
3869 I915_WRITE(IPS_CTL, 0);
3870 POSTING_READ(IPS_CTL);
3871 }
3872
3873 /* We need to wait for a vblank before we can disable the plane. */
3874 intel_wait_for_vblank(dev, crtc->pipe);
3875 }
3876
3877 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3878 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3879 {
3880 struct drm_device *dev = crtc->dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883 enum pipe pipe = intel_crtc->pipe;
3884 int palreg = PALETTE(pipe);
3885 int i;
3886 bool reenable_ips = false;
3887
3888 /* The clocks have to be on to load the palette. */
3889 if (!crtc->enabled || !intel_crtc->active)
3890 return;
3891
3892 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3893 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3894 assert_dsi_pll_enabled(dev_priv);
3895 else
3896 assert_pll_enabled(dev_priv, pipe);
3897 }
3898
3899 /* use legacy palette for Ironlake */
3900 if (!HAS_GMCH_DISPLAY(dev))
3901 palreg = LGC_PALETTE(pipe);
3902
3903 /* Workaround : Do not read or write the pipe palette/gamma data while
3904 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3905 */
3906 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3907 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3908 GAMMA_MODE_MODE_SPLIT)) {
3909 hsw_disable_ips(intel_crtc);
3910 reenable_ips = true;
3911 }
3912
3913 for (i = 0; i < 256; i++) {
3914 I915_WRITE(palreg + 4 * i,
3915 (intel_crtc->lut_r[i] << 16) |
3916 (intel_crtc->lut_g[i] << 8) |
3917 intel_crtc->lut_b[i]);
3918 }
3919
3920 if (reenable_ips)
3921 hsw_enable_ips(intel_crtc);
3922 }
3923
3924 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3925 {
3926 if (!enable && intel_crtc->overlay) {
3927 struct drm_device *dev = intel_crtc->base.dev;
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929
3930 mutex_lock(&dev->struct_mutex);
3931 dev_priv->mm.interruptible = false;
3932 (void) intel_overlay_switch_off(intel_crtc->overlay);
3933 dev_priv->mm.interruptible = true;
3934 mutex_unlock(&dev->struct_mutex);
3935 }
3936
3937 /* Let userspace switch the overlay on again. In most cases userspace
3938 * has to recompute where to put it anyway.
3939 */
3940 }
3941
3942 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3943 {
3944 struct drm_device *dev = crtc->dev;
3945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3946 int pipe = intel_crtc->pipe;
3947
3948 drm_vblank_on(dev, pipe);
3949
3950 intel_enable_primary_hw_plane(crtc->primary, crtc);
3951 intel_enable_planes(crtc);
3952 intel_crtc_update_cursor(crtc, true);
3953 intel_crtc_dpms_overlay(intel_crtc, true);
3954
3955 hsw_enable_ips(intel_crtc);
3956
3957 mutex_lock(&dev->struct_mutex);
3958 intel_update_fbc(dev);
3959 mutex_unlock(&dev->struct_mutex);
3960
3961 /*
3962 * FIXME: Once we grow proper nuclear flip support out of this we need
3963 * to compute the mask of flip planes precisely. For the time being
3964 * consider this a flip from a NULL plane.
3965 */
3966 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3967 }
3968
3969 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3970 {
3971 struct drm_device *dev = crtc->dev;
3972 struct drm_i915_private *dev_priv = dev->dev_private;
3973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974 int pipe = intel_crtc->pipe;
3975 int plane = intel_crtc->plane;
3976
3977 intel_crtc_wait_for_pending_flips(crtc);
3978
3979 if (dev_priv->fbc.plane == plane)
3980 intel_disable_fbc(dev);
3981
3982 hsw_disable_ips(intel_crtc);
3983
3984 intel_crtc_dpms_overlay(intel_crtc, false);
3985 intel_crtc_update_cursor(crtc, false);
3986 intel_disable_planes(crtc);
3987 intel_disable_primary_hw_plane(crtc->primary, crtc);
3988
3989 /*
3990 * FIXME: Once we grow proper nuclear flip support out of this we need
3991 * to compute the mask of flip planes precisely. For the time being
3992 * consider this a flip to a NULL plane.
3993 */
3994 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3995
3996 drm_vblank_off(dev, pipe);
3997 }
3998
3999 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4000 {
4001 struct drm_device *dev = crtc->dev;
4002 struct drm_i915_private *dev_priv = dev->dev_private;
4003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4004 struct intel_encoder *encoder;
4005 int pipe = intel_crtc->pipe;
4006
4007 WARN_ON(!crtc->enabled);
4008
4009 if (intel_crtc->active)
4010 return;
4011
4012 if (intel_crtc->config.has_pch_encoder)
4013 intel_prepare_shared_dpll(intel_crtc);
4014
4015 if (intel_crtc->config.has_dp_encoder)
4016 intel_dp_set_m_n(intel_crtc);
4017
4018 intel_set_pipe_timings(intel_crtc);
4019
4020 if (intel_crtc->config.has_pch_encoder) {
4021 intel_cpu_transcoder_set_m_n(intel_crtc,
4022 &intel_crtc->config.fdi_m_n, NULL);
4023 }
4024
4025 ironlake_set_pipeconf(crtc);
4026
4027 intel_crtc->active = true;
4028
4029 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4030 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4031
4032 for_each_encoder_on_crtc(dev, crtc, encoder)
4033 if (encoder->pre_enable)
4034 encoder->pre_enable(encoder);
4035
4036 if (intel_crtc->config.has_pch_encoder) {
4037 /* Note: FDI PLL enabling _must_ be done before we enable the
4038 * cpu pipes, hence this is separate from all the other fdi/pch
4039 * enabling. */
4040 ironlake_fdi_pll_enable(intel_crtc);
4041 } else {
4042 assert_fdi_tx_disabled(dev_priv, pipe);
4043 assert_fdi_rx_disabled(dev_priv, pipe);
4044 }
4045
4046 ironlake_pfit_enable(intel_crtc);
4047
4048 /*
4049 * On ILK+ LUT must be loaded before the pipe is running but with
4050 * clocks enabled
4051 */
4052 intel_crtc_load_lut(crtc);
4053
4054 intel_update_watermarks(crtc);
4055 intel_enable_pipe(intel_crtc);
4056
4057 if (intel_crtc->config.has_pch_encoder)
4058 ironlake_pch_enable(crtc);
4059
4060 for_each_encoder_on_crtc(dev, crtc, encoder)
4061 encoder->enable(encoder);
4062
4063 if (HAS_PCH_CPT(dev))
4064 cpt_verify_modeset(dev, intel_crtc->pipe);
4065
4066 intel_crtc_enable_planes(crtc);
4067 }
4068
4069 /* IPS only exists on ULT machines and is tied to pipe A. */
4070 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4071 {
4072 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4073 }
4074
4075 /*
4076 * This implements the workaround described in the "notes" section of the mode
4077 * set sequence documentation. When going from no pipes or single pipe to
4078 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4079 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4080 */
4081 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4082 {
4083 struct drm_device *dev = crtc->base.dev;
4084 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4085
4086 /* We want to get the other_active_crtc only if there's only 1 other
4087 * active crtc. */
4088 for_each_intel_crtc(dev, crtc_it) {
4089 if (!crtc_it->active || crtc_it == crtc)
4090 continue;
4091
4092 if (other_active_crtc)
4093 return;
4094
4095 other_active_crtc = crtc_it;
4096 }
4097 if (!other_active_crtc)
4098 return;
4099
4100 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4101 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4102 }
4103
4104 static void haswell_crtc_enable(struct drm_crtc *crtc)
4105 {
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4109 struct intel_encoder *encoder;
4110 int pipe = intel_crtc->pipe;
4111
4112 WARN_ON(!crtc->enabled);
4113
4114 if (intel_crtc->active)
4115 return;
4116
4117 if (intel_crtc_to_shared_dpll(intel_crtc))
4118 intel_enable_shared_dpll(intel_crtc);
4119
4120 if (intel_crtc->config.has_dp_encoder)
4121 intel_dp_set_m_n(intel_crtc);
4122
4123 intel_set_pipe_timings(intel_crtc);
4124
4125 if (intel_crtc->config.has_pch_encoder) {
4126 intel_cpu_transcoder_set_m_n(intel_crtc,
4127 &intel_crtc->config.fdi_m_n, NULL);
4128 }
4129
4130 haswell_set_pipeconf(crtc);
4131
4132 intel_set_pipe_csc(crtc);
4133
4134 intel_crtc->active = true;
4135
4136 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4137 for_each_encoder_on_crtc(dev, crtc, encoder)
4138 if (encoder->pre_enable)
4139 encoder->pre_enable(encoder);
4140
4141 if (intel_crtc->config.has_pch_encoder) {
4142 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4143 dev_priv->display.fdi_link_train(crtc);
4144 }
4145
4146 intel_ddi_enable_pipe_clock(intel_crtc);
4147
4148 ironlake_pfit_enable(intel_crtc);
4149
4150 /*
4151 * On ILK+ LUT must be loaded before the pipe is running but with
4152 * clocks enabled
4153 */
4154 intel_crtc_load_lut(crtc);
4155
4156 intel_ddi_set_pipe_settings(crtc);
4157 intel_ddi_enable_transcoder_func(crtc);
4158
4159 intel_update_watermarks(crtc);
4160 intel_enable_pipe(intel_crtc);
4161
4162 if (intel_crtc->config.has_pch_encoder)
4163 lpt_pch_enable(crtc);
4164
4165 if (intel_crtc->config.dp_encoder_is_mst)
4166 intel_ddi_set_vc_payload_alloc(crtc, true);
4167
4168 for_each_encoder_on_crtc(dev, crtc, encoder) {
4169 encoder->enable(encoder);
4170 intel_opregion_notify_encoder(encoder, true);
4171 }
4172
4173 /* If we change the relative order between pipe/planes enabling, we need
4174 * to change the workaround. */
4175 haswell_mode_set_planes_workaround(intel_crtc);
4176 intel_crtc_enable_planes(crtc);
4177 }
4178
4179 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4180 {
4181 struct drm_device *dev = crtc->base.dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 int pipe = crtc->pipe;
4184
4185 /* To avoid upsetting the power well on haswell only disable the pfit if
4186 * it's in use. The hw state code will make sure we get this right. */
4187 if (crtc->config.pch_pfit.enabled) {
4188 I915_WRITE(PF_CTL(pipe), 0);
4189 I915_WRITE(PF_WIN_POS(pipe), 0);
4190 I915_WRITE(PF_WIN_SZ(pipe), 0);
4191 }
4192 }
4193
4194 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199 struct intel_encoder *encoder;
4200 int pipe = intel_crtc->pipe;
4201 u32 reg, temp;
4202
4203 if (!intel_crtc->active)
4204 return;
4205
4206 intel_crtc_disable_planes(crtc);
4207
4208 for_each_encoder_on_crtc(dev, crtc, encoder)
4209 encoder->disable(encoder);
4210
4211 if (intel_crtc->config.has_pch_encoder)
4212 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4213
4214 intel_disable_pipe(dev_priv, pipe);
4215
4216 if (intel_crtc->config.dp_encoder_is_mst)
4217 intel_ddi_set_vc_payload_alloc(crtc, false);
4218
4219 ironlake_pfit_disable(intel_crtc);
4220
4221 for_each_encoder_on_crtc(dev, crtc, encoder)
4222 if (encoder->post_disable)
4223 encoder->post_disable(encoder);
4224
4225 if (intel_crtc->config.has_pch_encoder) {
4226 ironlake_fdi_disable(crtc);
4227
4228 ironlake_disable_pch_transcoder(dev_priv, pipe);
4229 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4230
4231 if (HAS_PCH_CPT(dev)) {
4232 /* disable TRANS_DP_CTL */
4233 reg = TRANS_DP_CTL(pipe);
4234 temp = I915_READ(reg);
4235 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4236 TRANS_DP_PORT_SEL_MASK);
4237 temp |= TRANS_DP_PORT_SEL_NONE;
4238 I915_WRITE(reg, temp);
4239
4240 /* disable DPLL_SEL */
4241 temp = I915_READ(PCH_DPLL_SEL);
4242 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4243 I915_WRITE(PCH_DPLL_SEL, temp);
4244 }
4245
4246 /* disable PCH DPLL */
4247 intel_disable_shared_dpll(intel_crtc);
4248
4249 ironlake_fdi_pll_disable(intel_crtc);
4250 }
4251
4252 intel_crtc->active = false;
4253 intel_update_watermarks(crtc);
4254
4255 mutex_lock(&dev->struct_mutex);
4256 intel_update_fbc(dev);
4257 mutex_unlock(&dev->struct_mutex);
4258 }
4259
4260 static void haswell_crtc_disable(struct drm_crtc *crtc)
4261 {
4262 struct drm_device *dev = crtc->dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4265 struct intel_encoder *encoder;
4266 int pipe = intel_crtc->pipe;
4267 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4268
4269 if (!intel_crtc->active)
4270 return;
4271
4272 intel_crtc_disable_planes(crtc);
4273
4274 for_each_encoder_on_crtc(dev, crtc, encoder) {
4275 intel_opregion_notify_encoder(encoder, false);
4276 encoder->disable(encoder);
4277 }
4278
4279 if (intel_crtc->config.has_pch_encoder)
4280 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4281 intel_disable_pipe(dev_priv, pipe);
4282
4283 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4284
4285 ironlake_pfit_disable(intel_crtc);
4286
4287 intel_ddi_disable_pipe_clock(intel_crtc);
4288
4289 if (intel_crtc->config.has_pch_encoder) {
4290 lpt_disable_pch_transcoder(dev_priv);
4291 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4292 intel_ddi_fdi_disable(crtc);
4293 }
4294
4295 for_each_encoder_on_crtc(dev, crtc, encoder)
4296 if (encoder->post_disable)
4297 encoder->post_disable(encoder);
4298
4299 intel_crtc->active = false;
4300 intel_update_watermarks(crtc);
4301
4302 mutex_lock(&dev->struct_mutex);
4303 intel_update_fbc(dev);
4304 mutex_unlock(&dev->struct_mutex);
4305
4306 if (intel_crtc_to_shared_dpll(intel_crtc))
4307 intel_disable_shared_dpll(intel_crtc);
4308 }
4309
4310 static void ironlake_crtc_off(struct drm_crtc *crtc)
4311 {
4312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4313 intel_put_shared_dpll(intel_crtc);
4314 }
4315
4316
4317 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4318 {
4319 struct drm_device *dev = crtc->base.dev;
4320 struct drm_i915_private *dev_priv = dev->dev_private;
4321 struct intel_crtc_config *pipe_config = &crtc->config;
4322
4323 if (!crtc->config.gmch_pfit.control)
4324 return;
4325
4326 /*
4327 * The panel fitter should only be adjusted whilst the pipe is disabled,
4328 * according to register description and PRM.
4329 */
4330 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4331 assert_pipe_disabled(dev_priv, crtc->pipe);
4332
4333 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4334 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4335
4336 /* Border color in case we don't scale up to the full screen. Black by
4337 * default, change to something else for debugging. */
4338 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4339 }
4340
4341 static enum intel_display_power_domain port_to_power_domain(enum port port)
4342 {
4343 switch (port) {
4344 case PORT_A:
4345 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4346 case PORT_B:
4347 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4348 case PORT_C:
4349 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4350 case PORT_D:
4351 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4352 default:
4353 WARN_ON_ONCE(1);
4354 return POWER_DOMAIN_PORT_OTHER;
4355 }
4356 }
4357
4358 #define for_each_power_domain(domain, mask) \
4359 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4360 if ((1 << (domain)) & (mask))
4361
4362 enum intel_display_power_domain
4363 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4364 {
4365 struct drm_device *dev = intel_encoder->base.dev;
4366 struct intel_digital_port *intel_dig_port;
4367
4368 switch (intel_encoder->type) {
4369 case INTEL_OUTPUT_UNKNOWN:
4370 /* Only DDI platforms should ever use this output type */
4371 WARN_ON_ONCE(!HAS_DDI(dev));
4372 case INTEL_OUTPUT_DISPLAYPORT:
4373 case INTEL_OUTPUT_HDMI:
4374 case INTEL_OUTPUT_EDP:
4375 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4376 return port_to_power_domain(intel_dig_port->port);
4377 case INTEL_OUTPUT_DP_MST:
4378 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4379 return port_to_power_domain(intel_dig_port->port);
4380 case INTEL_OUTPUT_ANALOG:
4381 return POWER_DOMAIN_PORT_CRT;
4382 case INTEL_OUTPUT_DSI:
4383 return POWER_DOMAIN_PORT_DSI;
4384 default:
4385 return POWER_DOMAIN_PORT_OTHER;
4386 }
4387 }
4388
4389 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4390 {
4391 struct drm_device *dev = crtc->dev;
4392 struct intel_encoder *intel_encoder;
4393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4394 enum pipe pipe = intel_crtc->pipe;
4395 unsigned long mask;
4396 enum transcoder transcoder;
4397
4398 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4399
4400 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4401 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4402 if (intel_crtc->config.pch_pfit.enabled ||
4403 intel_crtc->config.pch_pfit.force_thru)
4404 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4405
4406 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4407 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4408
4409 return mask;
4410 }
4411
4412 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4413 bool enable)
4414 {
4415 if (dev_priv->power_domains.init_power_on == enable)
4416 return;
4417
4418 if (enable)
4419 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4420 else
4421 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4422
4423 dev_priv->power_domains.init_power_on = enable;
4424 }
4425
4426 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4427 {
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4430 struct intel_crtc *crtc;
4431
4432 /*
4433 * First get all needed power domains, then put all unneeded, to avoid
4434 * any unnecessary toggling of the power wells.
4435 */
4436 for_each_intel_crtc(dev, crtc) {
4437 enum intel_display_power_domain domain;
4438
4439 if (!crtc->base.enabled)
4440 continue;
4441
4442 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4443
4444 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4445 intel_display_power_get(dev_priv, domain);
4446 }
4447
4448 for_each_intel_crtc(dev, crtc) {
4449 enum intel_display_power_domain domain;
4450
4451 for_each_power_domain(domain, crtc->enabled_power_domains)
4452 intel_display_power_put(dev_priv, domain);
4453
4454 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4455 }
4456
4457 intel_display_set_init_power(dev_priv, false);
4458 }
4459
4460 /* returns HPLL frequency in kHz */
4461 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4462 {
4463 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4464
4465 /* Obtain SKU information */
4466 mutex_lock(&dev_priv->dpio_lock);
4467 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4468 CCK_FUSE_HPLL_FREQ_MASK;
4469 mutex_unlock(&dev_priv->dpio_lock);
4470
4471 return vco_freq[hpll_freq] * 1000;
4472 }
4473
4474 static void vlv_update_cdclk(struct drm_device *dev)
4475 {
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
4478 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4479 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4480 dev_priv->vlv_cdclk_freq);
4481
4482 /*
4483 * Program the gmbus_freq based on the cdclk frequency.
4484 * BSpec erroneously claims we should aim for 4MHz, but
4485 * in fact 1MHz is the correct frequency.
4486 */
4487 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4488 }
4489
4490 /* Adjust CDclk dividers to allow high res or save power if possible */
4491 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4492 {
4493 struct drm_i915_private *dev_priv = dev->dev_private;
4494 u32 val, cmd;
4495
4496 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4497
4498 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4499 cmd = 2;
4500 else if (cdclk == 266667)
4501 cmd = 1;
4502 else
4503 cmd = 0;
4504
4505 mutex_lock(&dev_priv->rps.hw_lock);
4506 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4507 val &= ~DSPFREQGUAR_MASK;
4508 val |= (cmd << DSPFREQGUAR_SHIFT);
4509 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4510 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4511 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4512 50)) {
4513 DRM_ERROR("timed out waiting for CDclk change\n");
4514 }
4515 mutex_unlock(&dev_priv->rps.hw_lock);
4516
4517 if (cdclk == 400000) {
4518 u32 divider, vco;
4519
4520 vco = valleyview_get_vco(dev_priv);
4521 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4522
4523 mutex_lock(&dev_priv->dpio_lock);
4524 /* adjust cdclk divider */
4525 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4526 val &= ~DISPLAY_FREQUENCY_VALUES;
4527 val |= divider;
4528 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4529
4530 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4531 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4532 50))
4533 DRM_ERROR("timed out waiting for CDclk change\n");
4534 mutex_unlock(&dev_priv->dpio_lock);
4535 }
4536
4537 mutex_lock(&dev_priv->dpio_lock);
4538 /* adjust self-refresh exit latency value */
4539 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4540 val &= ~0x7f;
4541
4542 /*
4543 * For high bandwidth configs, we set a higher latency in the bunit
4544 * so that the core display fetch happens in time to avoid underruns.
4545 */
4546 if (cdclk == 400000)
4547 val |= 4500 / 250; /* 4.5 usec */
4548 else
4549 val |= 3000 / 250; /* 3.0 usec */
4550 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4551 mutex_unlock(&dev_priv->dpio_lock);
4552
4553 vlv_update_cdclk(dev);
4554 }
4555
4556 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4557 {
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 u32 val, cmd;
4560
4561 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4562
4563 switch (cdclk) {
4564 case 400000:
4565 cmd = 3;
4566 break;
4567 case 333333:
4568 case 320000:
4569 cmd = 2;
4570 break;
4571 case 266667:
4572 cmd = 1;
4573 break;
4574 case 200000:
4575 cmd = 0;
4576 break;
4577 default:
4578 WARN_ON(1);
4579 return;
4580 }
4581
4582 mutex_lock(&dev_priv->rps.hw_lock);
4583 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4584 val &= ~DSPFREQGUAR_MASK_CHV;
4585 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4586 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4587 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4588 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4589 50)) {
4590 DRM_ERROR("timed out waiting for CDclk change\n");
4591 }
4592 mutex_unlock(&dev_priv->rps.hw_lock);
4593
4594 vlv_update_cdclk(dev);
4595 }
4596
4597 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4598 int max_pixclk)
4599 {
4600 int vco = valleyview_get_vco(dev_priv);
4601 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4602
4603 /* FIXME: Punit isn't quite ready yet */
4604 if (IS_CHERRYVIEW(dev_priv->dev))
4605 return 400000;
4606
4607 /*
4608 * Really only a few cases to deal with, as only 4 CDclks are supported:
4609 * 200MHz
4610 * 267MHz
4611 * 320/333MHz (depends on HPLL freq)
4612 * 400MHz
4613 * So we check to see whether we're above 90% of the lower bin and
4614 * adjust if needed.
4615 *
4616 * We seem to get an unstable or solid color picture at 200MHz.
4617 * Not sure what's wrong. For now use 200MHz only when all pipes
4618 * are off.
4619 */
4620 if (max_pixclk > freq_320*9/10)
4621 return 400000;
4622 else if (max_pixclk > 266667*9/10)
4623 return freq_320;
4624 else if (max_pixclk > 0)
4625 return 266667;
4626 else
4627 return 200000;
4628 }
4629
4630 /* compute the max pixel clock for new configuration */
4631 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4632 {
4633 struct drm_device *dev = dev_priv->dev;
4634 struct intel_crtc *intel_crtc;
4635 int max_pixclk = 0;
4636
4637 for_each_intel_crtc(dev, intel_crtc) {
4638 if (intel_crtc->new_enabled)
4639 max_pixclk = max(max_pixclk,
4640 intel_crtc->new_config->adjusted_mode.crtc_clock);
4641 }
4642
4643 return max_pixclk;
4644 }
4645
4646 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4647 unsigned *prepare_pipes)
4648 {
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct intel_crtc *intel_crtc;
4651 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4652
4653 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4654 dev_priv->vlv_cdclk_freq)
4655 return;
4656
4657 /* disable/enable all currently active pipes while we change cdclk */
4658 for_each_intel_crtc(dev, intel_crtc)
4659 if (intel_crtc->base.enabled)
4660 *prepare_pipes |= (1 << intel_crtc->pipe);
4661 }
4662
4663 static void valleyview_modeset_global_resources(struct drm_device *dev)
4664 {
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4667 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4668
4669 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4670 if (IS_CHERRYVIEW(dev))
4671 cherryview_set_cdclk(dev, req_cdclk);
4672 else
4673 valleyview_set_cdclk(dev, req_cdclk);
4674 }
4675
4676 modeset_update_crtc_power_domains(dev);
4677 }
4678
4679 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4680 {
4681 struct drm_device *dev = crtc->dev;
4682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4683 struct intel_encoder *encoder;
4684 int pipe = intel_crtc->pipe;
4685 bool is_dsi;
4686
4687 WARN_ON(!crtc->enabled);
4688
4689 if (intel_crtc->active)
4690 return;
4691
4692 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4693
4694 if (!is_dsi) {
4695 if (IS_CHERRYVIEW(dev))
4696 chv_prepare_pll(intel_crtc);
4697 else
4698 vlv_prepare_pll(intel_crtc);
4699 }
4700
4701 if (intel_crtc->config.has_dp_encoder)
4702 intel_dp_set_m_n(intel_crtc);
4703
4704 intel_set_pipe_timings(intel_crtc);
4705
4706 i9xx_set_pipeconf(intel_crtc);
4707
4708 intel_crtc->active = true;
4709
4710 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4711
4712 for_each_encoder_on_crtc(dev, crtc, encoder)
4713 if (encoder->pre_pll_enable)
4714 encoder->pre_pll_enable(encoder);
4715
4716 if (!is_dsi) {
4717 if (IS_CHERRYVIEW(dev))
4718 chv_enable_pll(intel_crtc);
4719 else
4720 vlv_enable_pll(intel_crtc);
4721 }
4722
4723 for_each_encoder_on_crtc(dev, crtc, encoder)
4724 if (encoder->pre_enable)
4725 encoder->pre_enable(encoder);
4726
4727 i9xx_pfit_enable(intel_crtc);
4728
4729 intel_crtc_load_lut(crtc);
4730
4731 intel_update_watermarks(crtc);
4732 intel_enable_pipe(intel_crtc);
4733
4734 for_each_encoder_on_crtc(dev, crtc, encoder)
4735 encoder->enable(encoder);
4736
4737 intel_crtc_enable_planes(crtc);
4738
4739 /* Underruns don't raise interrupts, so check manually. */
4740 i9xx_check_fifo_underruns(dev);
4741 }
4742
4743 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->base.dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747
4748 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4749 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4750 }
4751
4752 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4753 {
4754 struct drm_device *dev = crtc->dev;
4755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756 struct intel_encoder *encoder;
4757 int pipe = intel_crtc->pipe;
4758
4759 WARN_ON(!crtc->enabled);
4760
4761 if (intel_crtc->active)
4762 return;
4763
4764 i9xx_set_pll_dividers(intel_crtc);
4765
4766 if (intel_crtc->config.has_dp_encoder)
4767 intel_dp_set_m_n(intel_crtc);
4768
4769 intel_set_pipe_timings(intel_crtc);
4770
4771 i9xx_set_pipeconf(intel_crtc);
4772
4773 intel_crtc->active = true;
4774
4775 if (!IS_GEN2(dev))
4776 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4777
4778 for_each_encoder_on_crtc(dev, crtc, encoder)
4779 if (encoder->pre_enable)
4780 encoder->pre_enable(encoder);
4781
4782 i9xx_enable_pll(intel_crtc);
4783
4784 i9xx_pfit_enable(intel_crtc);
4785
4786 intel_crtc_load_lut(crtc);
4787
4788 intel_update_watermarks(crtc);
4789 intel_enable_pipe(intel_crtc);
4790
4791 for_each_encoder_on_crtc(dev, crtc, encoder)
4792 encoder->enable(encoder);
4793
4794 intel_crtc_enable_planes(crtc);
4795
4796 /*
4797 * Gen2 reports pipe underruns whenever all planes are disabled.
4798 * So don't enable underrun reporting before at least some planes
4799 * are enabled.
4800 * FIXME: Need to fix the logic to work when we turn off all planes
4801 * but leave the pipe running.
4802 */
4803 if (IS_GEN2(dev))
4804 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4805
4806 /* Underruns don't raise interrupts, so check manually. */
4807 i9xx_check_fifo_underruns(dev);
4808 }
4809
4810 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4811 {
4812 struct drm_device *dev = crtc->base.dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814
4815 if (!crtc->config.gmch_pfit.control)
4816 return;
4817
4818 assert_pipe_disabled(dev_priv, crtc->pipe);
4819
4820 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4821 I915_READ(PFIT_CONTROL));
4822 I915_WRITE(PFIT_CONTROL, 0);
4823 }
4824
4825 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4826 {
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4830 struct intel_encoder *encoder;
4831 int pipe = intel_crtc->pipe;
4832
4833 if (!intel_crtc->active)
4834 return;
4835
4836 /*
4837 * Gen2 reports pipe underruns whenever all planes are disabled.
4838 * So diasble underrun reporting before all the planes get disabled.
4839 * FIXME: Need to fix the logic to work when we turn off all planes
4840 * but leave the pipe running.
4841 */
4842 if (IS_GEN2(dev))
4843 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4844
4845 /*
4846 * Vblank time updates from the shadow to live plane control register
4847 * are blocked if the memory self-refresh mode is active at that
4848 * moment. So to make sure the plane gets truly disabled, disable
4849 * first the self-refresh mode. The self-refresh enable bit in turn
4850 * will be checked/applied by the HW only at the next frame start
4851 * event which is after the vblank start event, so we need to have a
4852 * wait-for-vblank between disabling the plane and the pipe.
4853 */
4854 intel_set_memory_cxsr(dev_priv, false);
4855 intel_crtc_disable_planes(crtc);
4856
4857 for_each_encoder_on_crtc(dev, crtc, encoder)
4858 encoder->disable(encoder);
4859
4860 /*
4861 * On gen2 planes are double buffered but the pipe isn't, so we must
4862 * wait for planes to fully turn off before disabling the pipe.
4863 * We also need to wait on all gmch platforms because of the
4864 * self-refresh mode constraint explained above.
4865 */
4866 intel_wait_for_vblank(dev, pipe);
4867
4868 intel_disable_pipe(dev_priv, pipe);
4869
4870 i9xx_pfit_disable(intel_crtc);
4871
4872 for_each_encoder_on_crtc(dev, crtc, encoder)
4873 if (encoder->post_disable)
4874 encoder->post_disable(encoder);
4875
4876 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4877 if (IS_CHERRYVIEW(dev))
4878 chv_disable_pll(dev_priv, pipe);
4879 else if (IS_VALLEYVIEW(dev))
4880 vlv_disable_pll(dev_priv, pipe);
4881 else
4882 i9xx_disable_pll(dev_priv, pipe);
4883 }
4884
4885 if (!IS_GEN2(dev))
4886 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4887
4888 intel_crtc->active = false;
4889 intel_update_watermarks(crtc);
4890
4891 mutex_lock(&dev->struct_mutex);
4892 intel_update_fbc(dev);
4893 mutex_unlock(&dev->struct_mutex);
4894 }
4895
4896 static void i9xx_crtc_off(struct drm_crtc *crtc)
4897 {
4898 }
4899
4900 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4901 bool enabled)
4902 {
4903 struct drm_device *dev = crtc->dev;
4904 struct drm_i915_master_private *master_priv;
4905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4906 int pipe = intel_crtc->pipe;
4907
4908 if (!dev->primary->master)
4909 return;
4910
4911 master_priv = dev->primary->master->driver_priv;
4912 if (!master_priv->sarea_priv)
4913 return;
4914
4915 switch (pipe) {
4916 case 0:
4917 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4918 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4919 break;
4920 case 1:
4921 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4922 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4923 break;
4924 default:
4925 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4926 break;
4927 }
4928 }
4929
4930 /* Master function to enable/disable CRTC and corresponding power wells */
4931 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
4932 {
4933 struct drm_device *dev = crtc->dev;
4934 struct drm_i915_private *dev_priv = dev->dev_private;
4935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4936 enum intel_display_power_domain domain;
4937 unsigned long domains;
4938
4939 if (enable) {
4940 if (!intel_crtc->active) {
4941 domains = get_crtc_power_domains(crtc);
4942 for_each_power_domain(domain, domains)
4943 intel_display_power_get(dev_priv, domain);
4944 intel_crtc->enabled_power_domains = domains;
4945
4946 dev_priv->display.crtc_enable(crtc);
4947 }
4948 } else {
4949 if (intel_crtc->active) {
4950 dev_priv->display.crtc_disable(crtc);
4951
4952 domains = intel_crtc->enabled_power_domains;
4953 for_each_power_domain(domain, domains)
4954 intel_display_power_put(dev_priv, domain);
4955 intel_crtc->enabled_power_domains = 0;
4956 }
4957 }
4958 }
4959
4960 /**
4961 * Sets the power management mode of the pipe and plane.
4962 */
4963 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4964 {
4965 struct drm_device *dev = crtc->dev;
4966 struct intel_encoder *intel_encoder;
4967 bool enable = false;
4968
4969 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4970 enable |= intel_encoder->connectors_active;
4971
4972 intel_crtc_control(crtc, enable);
4973
4974 intel_crtc_update_sarea(crtc, enable);
4975 }
4976
4977 static void intel_crtc_disable(struct drm_crtc *crtc)
4978 {
4979 struct drm_device *dev = crtc->dev;
4980 struct drm_connector *connector;
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4983 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4984
4985 /* crtc should still be enabled when we disable it. */
4986 WARN_ON(!crtc->enabled);
4987
4988 dev_priv->display.crtc_disable(crtc);
4989 intel_crtc_update_sarea(crtc, false);
4990 dev_priv->display.off(crtc);
4991
4992 if (crtc->primary->fb) {
4993 mutex_lock(&dev->struct_mutex);
4994 intel_unpin_fb_obj(old_obj);
4995 i915_gem_track_fb(old_obj, NULL,
4996 INTEL_FRONTBUFFER_PRIMARY(pipe));
4997 mutex_unlock(&dev->struct_mutex);
4998 crtc->primary->fb = NULL;
4999 }
5000
5001 /* Update computed state. */
5002 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5003 if (!connector->encoder || !connector->encoder->crtc)
5004 continue;
5005
5006 if (connector->encoder->crtc != crtc)
5007 continue;
5008
5009 connector->dpms = DRM_MODE_DPMS_OFF;
5010 to_intel_encoder(connector->encoder)->connectors_active = false;
5011 }
5012 }
5013
5014 void intel_encoder_destroy(struct drm_encoder *encoder)
5015 {
5016 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5017
5018 drm_encoder_cleanup(encoder);
5019 kfree(intel_encoder);
5020 }
5021
5022 /* Simple dpms helper for encoders with just one connector, no cloning and only
5023 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5024 * state of the entire output pipe. */
5025 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5026 {
5027 if (mode == DRM_MODE_DPMS_ON) {
5028 encoder->connectors_active = true;
5029
5030 intel_crtc_update_dpms(encoder->base.crtc);
5031 } else {
5032 encoder->connectors_active = false;
5033
5034 intel_crtc_update_dpms(encoder->base.crtc);
5035 }
5036 }
5037
5038 /* Cross check the actual hw state with our own modeset state tracking (and it's
5039 * internal consistency). */
5040 static void intel_connector_check_state(struct intel_connector *connector)
5041 {
5042 if (connector->get_hw_state(connector)) {
5043 struct intel_encoder *encoder = connector->encoder;
5044 struct drm_crtc *crtc;
5045 bool encoder_enabled;
5046 enum pipe pipe;
5047
5048 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5049 connector->base.base.id,
5050 connector->base.name);
5051
5052 /* there is no real hw state for MST connectors */
5053 if (connector->mst_port)
5054 return;
5055
5056 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5057 "wrong connector dpms state\n");
5058 WARN(connector->base.encoder != &encoder->base,
5059 "active connector not linked to encoder\n");
5060
5061 if (encoder) {
5062 WARN(!encoder->connectors_active,
5063 "encoder->connectors_active not set\n");
5064
5065 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5066 WARN(!encoder_enabled, "encoder not enabled\n");
5067 if (WARN_ON(!encoder->base.crtc))
5068 return;
5069
5070 crtc = encoder->base.crtc;
5071
5072 WARN(!crtc->enabled, "crtc not enabled\n");
5073 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5074 WARN(pipe != to_intel_crtc(crtc)->pipe,
5075 "encoder active on the wrong pipe\n");
5076 }
5077 }
5078 }
5079
5080 /* Even simpler default implementation, if there's really no special case to
5081 * consider. */
5082 void intel_connector_dpms(struct drm_connector *connector, int mode)
5083 {
5084 /* All the simple cases only support two dpms states. */
5085 if (mode != DRM_MODE_DPMS_ON)
5086 mode = DRM_MODE_DPMS_OFF;
5087
5088 if (mode == connector->dpms)
5089 return;
5090
5091 connector->dpms = mode;
5092
5093 /* Only need to change hw state when actually enabled */
5094 if (connector->encoder)
5095 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5096
5097 intel_modeset_check_state(connector->dev);
5098 }
5099
5100 /* Simple connector->get_hw_state implementation for encoders that support only
5101 * one connector and no cloning and hence the encoder state determines the state
5102 * of the connector. */
5103 bool intel_connector_get_hw_state(struct intel_connector *connector)
5104 {
5105 enum pipe pipe = 0;
5106 struct intel_encoder *encoder = connector->encoder;
5107
5108 return encoder->get_hw_state(encoder, &pipe);
5109 }
5110
5111 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5112 struct intel_crtc_config *pipe_config)
5113 {
5114 struct drm_i915_private *dev_priv = dev->dev_private;
5115 struct intel_crtc *pipe_B_crtc =
5116 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5117
5118 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5119 pipe_name(pipe), pipe_config->fdi_lanes);
5120 if (pipe_config->fdi_lanes > 4) {
5121 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5122 pipe_name(pipe), pipe_config->fdi_lanes);
5123 return false;
5124 }
5125
5126 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5127 if (pipe_config->fdi_lanes > 2) {
5128 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5129 pipe_config->fdi_lanes);
5130 return false;
5131 } else {
5132 return true;
5133 }
5134 }
5135
5136 if (INTEL_INFO(dev)->num_pipes == 2)
5137 return true;
5138
5139 /* Ivybridge 3 pipe is really complicated */
5140 switch (pipe) {
5141 case PIPE_A:
5142 return true;
5143 case PIPE_B:
5144 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5145 pipe_config->fdi_lanes > 2) {
5146 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5147 pipe_name(pipe), pipe_config->fdi_lanes);
5148 return false;
5149 }
5150 return true;
5151 case PIPE_C:
5152 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5153 pipe_B_crtc->config.fdi_lanes <= 2) {
5154 if (pipe_config->fdi_lanes > 2) {
5155 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5156 pipe_name(pipe), pipe_config->fdi_lanes);
5157 return false;
5158 }
5159 } else {
5160 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5161 return false;
5162 }
5163 return true;
5164 default:
5165 BUG();
5166 }
5167 }
5168
5169 #define RETRY 1
5170 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5171 struct intel_crtc_config *pipe_config)
5172 {
5173 struct drm_device *dev = intel_crtc->base.dev;
5174 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5175 int lane, link_bw, fdi_dotclock;
5176 bool setup_ok, needs_recompute = false;
5177
5178 retry:
5179 /* FDI is a binary signal running at ~2.7GHz, encoding
5180 * each output octet as 10 bits. The actual frequency
5181 * is stored as a divider into a 100MHz clock, and the
5182 * mode pixel clock is stored in units of 1KHz.
5183 * Hence the bw of each lane in terms of the mode signal
5184 * is:
5185 */
5186 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5187
5188 fdi_dotclock = adjusted_mode->crtc_clock;
5189
5190 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5191 pipe_config->pipe_bpp);
5192
5193 pipe_config->fdi_lanes = lane;
5194
5195 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5196 link_bw, &pipe_config->fdi_m_n);
5197
5198 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5199 intel_crtc->pipe, pipe_config);
5200 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5201 pipe_config->pipe_bpp -= 2*3;
5202 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5203 pipe_config->pipe_bpp);
5204 needs_recompute = true;
5205 pipe_config->bw_constrained = true;
5206
5207 goto retry;
5208 }
5209
5210 if (needs_recompute)
5211 return RETRY;
5212
5213 return setup_ok ? 0 : -EINVAL;
5214 }
5215
5216 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5217 struct intel_crtc_config *pipe_config)
5218 {
5219 pipe_config->ips_enabled = i915.enable_ips &&
5220 hsw_crtc_supports_ips(crtc) &&
5221 pipe_config->pipe_bpp <= 24;
5222 }
5223
5224 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5225 struct intel_crtc_config *pipe_config)
5226 {
5227 struct drm_device *dev = crtc->base.dev;
5228 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5229
5230 /* FIXME should check pixel clock limits on all platforms */
5231 if (INTEL_INFO(dev)->gen < 4) {
5232 struct drm_i915_private *dev_priv = dev->dev_private;
5233 int clock_limit =
5234 dev_priv->display.get_display_clock_speed(dev);
5235
5236 /*
5237 * Enable pixel doubling when the dot clock
5238 * is > 90% of the (display) core speed.
5239 *
5240 * GDG double wide on either pipe,
5241 * otherwise pipe A only.
5242 */
5243 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5244 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5245 clock_limit *= 2;
5246 pipe_config->double_wide = true;
5247 }
5248
5249 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5250 return -EINVAL;
5251 }
5252
5253 /*
5254 * Pipe horizontal size must be even in:
5255 * - DVO ganged mode
5256 * - LVDS dual channel mode
5257 * - Double wide pipe
5258 */
5259 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5260 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5261 pipe_config->pipe_src_w &= ~1;
5262
5263 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5264 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5265 */
5266 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5267 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5268 return -EINVAL;
5269
5270 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5271 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5272 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5273 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5274 * for lvds. */
5275 pipe_config->pipe_bpp = 8*3;
5276 }
5277
5278 if (HAS_IPS(dev))
5279 hsw_compute_ips_config(crtc, pipe_config);
5280
5281 /*
5282 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5283 * old clock survives for now.
5284 */
5285 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5286 pipe_config->shared_dpll = crtc->config.shared_dpll;
5287
5288 if (pipe_config->has_pch_encoder)
5289 return ironlake_fdi_compute_config(crtc, pipe_config);
5290
5291 return 0;
5292 }
5293
5294 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5295 {
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 int vco = valleyview_get_vco(dev_priv);
5298 u32 val;
5299 int divider;
5300
5301 /* FIXME: Punit isn't quite ready yet */
5302 if (IS_CHERRYVIEW(dev))
5303 return 400000;
5304
5305 mutex_lock(&dev_priv->dpio_lock);
5306 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5307 mutex_unlock(&dev_priv->dpio_lock);
5308
5309 divider = val & DISPLAY_FREQUENCY_VALUES;
5310
5311 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5312 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5313 "cdclk change in progress\n");
5314
5315 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5316 }
5317
5318 static int i945_get_display_clock_speed(struct drm_device *dev)
5319 {
5320 return 400000;
5321 }
5322
5323 static int i915_get_display_clock_speed(struct drm_device *dev)
5324 {
5325 return 333000;
5326 }
5327
5328 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5329 {
5330 return 200000;
5331 }
5332
5333 static int pnv_get_display_clock_speed(struct drm_device *dev)
5334 {
5335 u16 gcfgc = 0;
5336
5337 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5338
5339 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5340 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5341 return 267000;
5342 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5343 return 333000;
5344 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5345 return 444000;
5346 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5347 return 200000;
5348 default:
5349 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5350 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5351 return 133000;
5352 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5353 return 167000;
5354 }
5355 }
5356
5357 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5358 {
5359 u16 gcfgc = 0;
5360
5361 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5362
5363 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5364 return 133000;
5365 else {
5366 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5367 case GC_DISPLAY_CLOCK_333_MHZ:
5368 return 333000;
5369 default:
5370 case GC_DISPLAY_CLOCK_190_200_MHZ:
5371 return 190000;
5372 }
5373 }
5374 }
5375
5376 static int i865_get_display_clock_speed(struct drm_device *dev)
5377 {
5378 return 266000;
5379 }
5380
5381 static int i855_get_display_clock_speed(struct drm_device *dev)
5382 {
5383 u16 hpllcc = 0;
5384 /* Assume that the hardware is in the high speed state. This
5385 * should be the default.
5386 */
5387 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5388 case GC_CLOCK_133_200:
5389 case GC_CLOCK_100_200:
5390 return 200000;
5391 case GC_CLOCK_166_250:
5392 return 250000;
5393 case GC_CLOCK_100_133:
5394 return 133000;
5395 }
5396
5397 /* Shouldn't happen */
5398 return 0;
5399 }
5400
5401 static int i830_get_display_clock_speed(struct drm_device *dev)
5402 {
5403 return 133000;
5404 }
5405
5406 static void
5407 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5408 {
5409 while (*num > DATA_LINK_M_N_MASK ||
5410 *den > DATA_LINK_M_N_MASK) {
5411 *num >>= 1;
5412 *den >>= 1;
5413 }
5414 }
5415
5416 static void compute_m_n(unsigned int m, unsigned int n,
5417 uint32_t *ret_m, uint32_t *ret_n)
5418 {
5419 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5420 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5421 intel_reduce_m_n_ratio(ret_m, ret_n);
5422 }
5423
5424 void
5425 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5426 int pixel_clock, int link_clock,
5427 struct intel_link_m_n *m_n)
5428 {
5429 m_n->tu = 64;
5430
5431 compute_m_n(bits_per_pixel * pixel_clock,
5432 link_clock * nlanes * 8,
5433 &m_n->gmch_m, &m_n->gmch_n);
5434
5435 compute_m_n(pixel_clock, link_clock,
5436 &m_n->link_m, &m_n->link_n);
5437 }
5438
5439 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5440 {
5441 if (i915.panel_use_ssc >= 0)
5442 return i915.panel_use_ssc != 0;
5443 return dev_priv->vbt.lvds_use_ssc
5444 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5445 }
5446
5447 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5448 {
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 int refclk;
5452
5453 if (IS_VALLEYVIEW(dev)) {
5454 refclk = 100000;
5455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5456 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5457 refclk = dev_priv->vbt.lvds_ssc_freq;
5458 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5459 } else if (!IS_GEN2(dev)) {
5460 refclk = 96000;
5461 } else {
5462 refclk = 48000;
5463 }
5464
5465 return refclk;
5466 }
5467
5468 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5469 {
5470 return (1 << dpll->n) << 16 | dpll->m2;
5471 }
5472
5473 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5474 {
5475 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5476 }
5477
5478 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5479 intel_clock_t *reduced_clock)
5480 {
5481 struct drm_device *dev = crtc->base.dev;
5482 u32 fp, fp2 = 0;
5483
5484 if (IS_PINEVIEW(dev)) {
5485 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5486 if (reduced_clock)
5487 fp2 = pnv_dpll_compute_fp(reduced_clock);
5488 } else {
5489 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5490 if (reduced_clock)
5491 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5492 }
5493
5494 crtc->config.dpll_hw_state.fp0 = fp;
5495
5496 crtc->lowfreq_avail = false;
5497 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5498 reduced_clock && i915.powersave) {
5499 crtc->config.dpll_hw_state.fp1 = fp2;
5500 crtc->lowfreq_avail = true;
5501 } else {
5502 crtc->config.dpll_hw_state.fp1 = fp;
5503 }
5504 }
5505
5506 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5507 pipe)
5508 {
5509 u32 reg_val;
5510
5511 /*
5512 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5513 * and set it to a reasonable value instead.
5514 */
5515 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5516 reg_val &= 0xffffff00;
5517 reg_val |= 0x00000030;
5518 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5519
5520 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5521 reg_val &= 0x8cffffff;
5522 reg_val = 0x8c000000;
5523 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5524
5525 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5526 reg_val &= 0xffffff00;
5527 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5528
5529 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5530 reg_val &= 0x00ffffff;
5531 reg_val |= 0xb0000000;
5532 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5533 }
5534
5535 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5536 struct intel_link_m_n *m_n)
5537 {
5538 struct drm_device *dev = crtc->base.dev;
5539 struct drm_i915_private *dev_priv = dev->dev_private;
5540 int pipe = crtc->pipe;
5541
5542 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5543 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5544 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5545 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5546 }
5547
5548 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5549 struct intel_link_m_n *m_n,
5550 struct intel_link_m_n *m2_n2)
5551 {
5552 struct drm_device *dev = crtc->base.dev;
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 int pipe = crtc->pipe;
5555 enum transcoder transcoder = crtc->config.cpu_transcoder;
5556
5557 if (INTEL_INFO(dev)->gen >= 5) {
5558 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5559 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5560 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5561 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5562 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5563 * for gen < 8) and if DRRS is supported (to make sure the
5564 * registers are not unnecessarily accessed).
5565 */
5566 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5567 crtc->config.has_drrs) {
5568 I915_WRITE(PIPE_DATA_M2(transcoder),
5569 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5570 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5571 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5572 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5573 }
5574 } else {
5575 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5576 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5577 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5578 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5579 }
5580 }
5581
5582 void intel_dp_set_m_n(struct intel_crtc *crtc)
5583 {
5584 if (crtc->config.has_pch_encoder)
5585 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5586 else
5587 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5588 &crtc->config.dp_m2_n2);
5589 }
5590
5591 static void vlv_update_pll(struct intel_crtc *crtc)
5592 {
5593 u32 dpll, dpll_md;
5594
5595 /*
5596 * Enable DPIO clock input. We should never disable the reference
5597 * clock for pipe B, since VGA hotplug / manual detection depends
5598 * on it.
5599 */
5600 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5601 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5602 /* We should never disable this, set it here for state tracking */
5603 if (crtc->pipe == PIPE_B)
5604 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5605 dpll |= DPLL_VCO_ENABLE;
5606 crtc->config.dpll_hw_state.dpll = dpll;
5607
5608 dpll_md = (crtc->config.pixel_multiplier - 1)
5609 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5610 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5611 }
5612
5613 static void vlv_prepare_pll(struct intel_crtc *crtc)
5614 {
5615 struct drm_device *dev = crtc->base.dev;
5616 struct drm_i915_private *dev_priv = dev->dev_private;
5617 int pipe = crtc->pipe;
5618 u32 mdiv;
5619 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5620 u32 coreclk, reg_val;
5621
5622 mutex_lock(&dev_priv->dpio_lock);
5623
5624 bestn = crtc->config.dpll.n;
5625 bestm1 = crtc->config.dpll.m1;
5626 bestm2 = crtc->config.dpll.m2;
5627 bestp1 = crtc->config.dpll.p1;
5628 bestp2 = crtc->config.dpll.p2;
5629
5630 /* See eDP HDMI DPIO driver vbios notes doc */
5631
5632 /* PLL B needs special handling */
5633 if (pipe == PIPE_B)
5634 vlv_pllb_recal_opamp(dev_priv, pipe);
5635
5636 /* Set up Tx target for periodic Rcomp update */
5637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5638
5639 /* Disable target IRef on PLL */
5640 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5641 reg_val &= 0x00ffffff;
5642 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5643
5644 /* Disable fast lock */
5645 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5646
5647 /* Set idtafcrecal before PLL is enabled */
5648 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5649 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5650 mdiv |= ((bestn << DPIO_N_SHIFT));
5651 mdiv |= (1 << DPIO_K_SHIFT);
5652
5653 /*
5654 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5655 * but we don't support that).
5656 * Note: don't use the DAC post divider as it seems unstable.
5657 */
5658 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5660
5661 mdiv |= DPIO_ENABLE_CALIBRATION;
5662 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5663
5664 /* Set HBR and RBR LPF coefficients */
5665 if (crtc->config.port_clock == 162000 ||
5666 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5667 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5668 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5669 0x009f0003);
5670 else
5671 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5672 0x00d0000f);
5673
5674 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5675 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5676 /* Use SSC source */
5677 if (pipe == PIPE_A)
5678 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5679 0x0df40000);
5680 else
5681 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5682 0x0df70000);
5683 } else { /* HDMI or VGA */
5684 /* Use bend source */
5685 if (pipe == PIPE_A)
5686 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5687 0x0df70000);
5688 else
5689 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5690 0x0df40000);
5691 }
5692
5693 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5694 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5695 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5696 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5697 coreclk |= 0x01000000;
5698 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5699
5700 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5701 mutex_unlock(&dev_priv->dpio_lock);
5702 }
5703
5704 static void chv_update_pll(struct intel_crtc *crtc)
5705 {
5706 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5707 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5708 DPLL_VCO_ENABLE;
5709 if (crtc->pipe != PIPE_A)
5710 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5711
5712 crtc->config.dpll_hw_state.dpll_md =
5713 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5714 }
5715
5716 static void chv_prepare_pll(struct intel_crtc *crtc)
5717 {
5718 struct drm_device *dev = crtc->base.dev;
5719 struct drm_i915_private *dev_priv = dev->dev_private;
5720 int pipe = crtc->pipe;
5721 int dpll_reg = DPLL(crtc->pipe);
5722 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5723 u32 loopfilter, intcoeff;
5724 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5725 int refclk;
5726
5727 bestn = crtc->config.dpll.n;
5728 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5729 bestm1 = crtc->config.dpll.m1;
5730 bestm2 = crtc->config.dpll.m2 >> 22;
5731 bestp1 = crtc->config.dpll.p1;
5732 bestp2 = crtc->config.dpll.p2;
5733
5734 /*
5735 * Enable Refclk and SSC
5736 */
5737 I915_WRITE(dpll_reg,
5738 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5739
5740 mutex_lock(&dev_priv->dpio_lock);
5741
5742 /* p1 and p2 divider */
5743 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5744 5 << DPIO_CHV_S1_DIV_SHIFT |
5745 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5746 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5747 1 << DPIO_CHV_K_DIV_SHIFT);
5748
5749 /* Feedback post-divider - m2 */
5750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5751
5752 /* Feedback refclk divider - n and m1 */
5753 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5754 DPIO_CHV_M1_DIV_BY_2 |
5755 1 << DPIO_CHV_N_DIV_SHIFT);
5756
5757 /* M2 fraction division */
5758 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5759
5760 /* M2 fraction division enable */
5761 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5762 DPIO_CHV_FRAC_DIV_EN |
5763 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5764
5765 /* Loop filter */
5766 refclk = i9xx_get_refclk(&crtc->base, 0);
5767 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5768 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5769 if (refclk == 100000)
5770 intcoeff = 11;
5771 else if (refclk == 38400)
5772 intcoeff = 10;
5773 else
5774 intcoeff = 9;
5775 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5776 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5777
5778 /* AFC Recal */
5779 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5780 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5781 DPIO_AFC_RECAL);
5782
5783 mutex_unlock(&dev_priv->dpio_lock);
5784 }
5785
5786 static void i9xx_update_pll(struct intel_crtc *crtc,
5787 intel_clock_t *reduced_clock,
5788 int num_connectors)
5789 {
5790 struct drm_device *dev = crtc->base.dev;
5791 struct drm_i915_private *dev_priv = dev->dev_private;
5792 u32 dpll;
5793 bool is_sdvo;
5794 struct dpll *clock = &crtc->config.dpll;
5795
5796 i9xx_update_pll_dividers(crtc, reduced_clock);
5797
5798 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5799 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5800
5801 dpll = DPLL_VGA_MODE_DIS;
5802
5803 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5804 dpll |= DPLLB_MODE_LVDS;
5805 else
5806 dpll |= DPLLB_MODE_DAC_SERIAL;
5807
5808 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5809 dpll |= (crtc->config.pixel_multiplier - 1)
5810 << SDVO_MULTIPLIER_SHIFT_HIRES;
5811 }
5812
5813 if (is_sdvo)
5814 dpll |= DPLL_SDVO_HIGH_SPEED;
5815
5816 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5817 dpll |= DPLL_SDVO_HIGH_SPEED;
5818
5819 /* compute bitmask from p1 value */
5820 if (IS_PINEVIEW(dev))
5821 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5822 else {
5823 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5824 if (IS_G4X(dev) && reduced_clock)
5825 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5826 }
5827 switch (clock->p2) {
5828 case 5:
5829 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5830 break;
5831 case 7:
5832 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5833 break;
5834 case 10:
5835 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5836 break;
5837 case 14:
5838 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5839 break;
5840 }
5841 if (INTEL_INFO(dev)->gen >= 4)
5842 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5843
5844 if (crtc->config.sdvo_tv_clock)
5845 dpll |= PLL_REF_INPUT_TVCLKINBC;
5846 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5847 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5848 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5849 else
5850 dpll |= PLL_REF_INPUT_DREFCLK;
5851
5852 dpll |= DPLL_VCO_ENABLE;
5853 crtc->config.dpll_hw_state.dpll = dpll;
5854
5855 if (INTEL_INFO(dev)->gen >= 4) {
5856 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5857 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5858 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5859 }
5860 }
5861
5862 static void i8xx_update_pll(struct intel_crtc *crtc,
5863 intel_clock_t *reduced_clock,
5864 int num_connectors)
5865 {
5866 struct drm_device *dev = crtc->base.dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 u32 dpll;
5869 struct dpll *clock = &crtc->config.dpll;
5870
5871 i9xx_update_pll_dividers(crtc, reduced_clock);
5872
5873 dpll = DPLL_VGA_MODE_DIS;
5874
5875 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5876 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5877 } else {
5878 if (clock->p1 == 2)
5879 dpll |= PLL_P1_DIVIDE_BY_TWO;
5880 else
5881 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5882 if (clock->p2 == 4)
5883 dpll |= PLL_P2_DIVIDE_BY_4;
5884 }
5885
5886 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5887 dpll |= DPLL_DVO_2X_MODE;
5888
5889 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5890 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5891 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5892 else
5893 dpll |= PLL_REF_INPUT_DREFCLK;
5894
5895 dpll |= DPLL_VCO_ENABLE;
5896 crtc->config.dpll_hw_state.dpll = dpll;
5897 }
5898
5899 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5900 {
5901 struct drm_device *dev = intel_crtc->base.dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903 enum pipe pipe = intel_crtc->pipe;
5904 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5905 struct drm_display_mode *adjusted_mode =
5906 &intel_crtc->config.adjusted_mode;
5907 uint32_t crtc_vtotal, crtc_vblank_end;
5908 int vsyncshift = 0;
5909
5910 /* We need to be careful not to changed the adjusted mode, for otherwise
5911 * the hw state checker will get angry at the mismatch. */
5912 crtc_vtotal = adjusted_mode->crtc_vtotal;
5913 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5914
5915 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5916 /* the chip adds 2 halflines automatically */
5917 crtc_vtotal -= 1;
5918 crtc_vblank_end -= 1;
5919
5920 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5921 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5922 else
5923 vsyncshift = adjusted_mode->crtc_hsync_start -
5924 adjusted_mode->crtc_htotal / 2;
5925 if (vsyncshift < 0)
5926 vsyncshift += adjusted_mode->crtc_htotal;
5927 }
5928
5929 if (INTEL_INFO(dev)->gen > 3)
5930 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5931
5932 I915_WRITE(HTOTAL(cpu_transcoder),
5933 (adjusted_mode->crtc_hdisplay - 1) |
5934 ((adjusted_mode->crtc_htotal - 1) << 16));
5935 I915_WRITE(HBLANK(cpu_transcoder),
5936 (adjusted_mode->crtc_hblank_start - 1) |
5937 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5938 I915_WRITE(HSYNC(cpu_transcoder),
5939 (adjusted_mode->crtc_hsync_start - 1) |
5940 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5941
5942 I915_WRITE(VTOTAL(cpu_transcoder),
5943 (adjusted_mode->crtc_vdisplay - 1) |
5944 ((crtc_vtotal - 1) << 16));
5945 I915_WRITE(VBLANK(cpu_transcoder),
5946 (adjusted_mode->crtc_vblank_start - 1) |
5947 ((crtc_vblank_end - 1) << 16));
5948 I915_WRITE(VSYNC(cpu_transcoder),
5949 (adjusted_mode->crtc_vsync_start - 1) |
5950 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5951
5952 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5953 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5954 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5955 * bits. */
5956 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5957 (pipe == PIPE_B || pipe == PIPE_C))
5958 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5959
5960 /* pipesrc controls the size that is scaled from, which should
5961 * always be the user's requested size.
5962 */
5963 I915_WRITE(PIPESRC(pipe),
5964 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5965 (intel_crtc->config.pipe_src_h - 1));
5966 }
5967
5968 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5969 struct intel_crtc_config *pipe_config)
5970 {
5971 struct drm_device *dev = crtc->base.dev;
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5974 uint32_t tmp;
5975
5976 tmp = I915_READ(HTOTAL(cpu_transcoder));
5977 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5978 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5979 tmp = I915_READ(HBLANK(cpu_transcoder));
5980 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5981 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5982 tmp = I915_READ(HSYNC(cpu_transcoder));
5983 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5984 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5985
5986 tmp = I915_READ(VTOTAL(cpu_transcoder));
5987 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5988 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5989 tmp = I915_READ(VBLANK(cpu_transcoder));
5990 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5991 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5992 tmp = I915_READ(VSYNC(cpu_transcoder));
5993 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5994 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5995
5996 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5997 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5998 pipe_config->adjusted_mode.crtc_vtotal += 1;
5999 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6000 }
6001
6002 tmp = I915_READ(PIPESRC(crtc->pipe));
6003 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6004 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6005
6006 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6007 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6008 }
6009
6010 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6011 struct intel_crtc_config *pipe_config)
6012 {
6013 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6014 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6015 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6016 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6017
6018 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6019 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6020 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6021 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6022
6023 mode->flags = pipe_config->adjusted_mode.flags;
6024
6025 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6026 mode->flags |= pipe_config->adjusted_mode.flags;
6027 }
6028
6029 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6030 {
6031 struct drm_device *dev = intel_crtc->base.dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033 uint32_t pipeconf;
6034
6035 pipeconf = 0;
6036
6037 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
6038 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
6039 pipeconf |= PIPECONF_ENABLE;
6040
6041 if (intel_crtc->config.double_wide)
6042 pipeconf |= PIPECONF_DOUBLE_WIDE;
6043
6044 /* only g4x and later have fancy bpc/dither controls */
6045 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6046 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6047 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6048 pipeconf |= PIPECONF_DITHER_EN |
6049 PIPECONF_DITHER_TYPE_SP;
6050
6051 switch (intel_crtc->config.pipe_bpp) {
6052 case 18:
6053 pipeconf |= PIPECONF_6BPC;
6054 break;
6055 case 24:
6056 pipeconf |= PIPECONF_8BPC;
6057 break;
6058 case 30:
6059 pipeconf |= PIPECONF_10BPC;
6060 break;
6061 default:
6062 /* Case prevented by intel_choose_pipe_bpp_dither. */
6063 BUG();
6064 }
6065 }
6066
6067 if (HAS_PIPE_CXSR(dev)) {
6068 if (intel_crtc->lowfreq_avail) {
6069 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6070 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6071 } else {
6072 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6073 }
6074 }
6075
6076 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6077 if (INTEL_INFO(dev)->gen < 4 ||
6078 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
6079 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6080 else
6081 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6082 } else
6083 pipeconf |= PIPECONF_PROGRESSIVE;
6084
6085 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6086 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6087
6088 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6089 POSTING_READ(PIPECONF(intel_crtc->pipe));
6090 }
6091
6092 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6093 int x, int y,
6094 struct drm_framebuffer *fb)
6095 {
6096 struct drm_device *dev = crtc->dev;
6097 struct drm_i915_private *dev_priv = dev->dev_private;
6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6099 int refclk, num_connectors = 0;
6100 intel_clock_t clock, reduced_clock;
6101 bool ok, has_reduced_clock = false;
6102 bool is_lvds = false, is_dsi = false;
6103 struct intel_encoder *encoder;
6104 const intel_limit_t *limit;
6105
6106 for_each_encoder_on_crtc(dev, crtc, encoder) {
6107 switch (encoder->type) {
6108 case INTEL_OUTPUT_LVDS:
6109 is_lvds = true;
6110 break;
6111 case INTEL_OUTPUT_DSI:
6112 is_dsi = true;
6113 break;
6114 }
6115
6116 num_connectors++;
6117 }
6118
6119 if (is_dsi)
6120 return 0;
6121
6122 if (!intel_crtc->config.clock_set) {
6123 refclk = i9xx_get_refclk(crtc, num_connectors);
6124
6125 /*
6126 * Returns a set of divisors for the desired target clock with
6127 * the given refclk, or FALSE. The returned values represent
6128 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6129 * 2) / p1 / p2.
6130 */
6131 limit = intel_limit(crtc, refclk);
6132 ok = dev_priv->display.find_dpll(limit, crtc,
6133 intel_crtc->config.port_clock,
6134 refclk, NULL, &clock);
6135 if (!ok) {
6136 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6137 return -EINVAL;
6138 }
6139
6140 if (is_lvds && dev_priv->lvds_downclock_avail) {
6141 /*
6142 * Ensure we match the reduced clock's P to the target
6143 * clock. If the clocks don't match, we can't switch
6144 * the display clock by using the FP0/FP1. In such case
6145 * we will disable the LVDS downclock feature.
6146 */
6147 has_reduced_clock =
6148 dev_priv->display.find_dpll(limit, crtc,
6149 dev_priv->lvds_downclock,
6150 refclk, &clock,
6151 &reduced_clock);
6152 }
6153 /* Compat-code for transition, will disappear. */
6154 intel_crtc->config.dpll.n = clock.n;
6155 intel_crtc->config.dpll.m1 = clock.m1;
6156 intel_crtc->config.dpll.m2 = clock.m2;
6157 intel_crtc->config.dpll.p1 = clock.p1;
6158 intel_crtc->config.dpll.p2 = clock.p2;
6159 }
6160
6161 if (IS_GEN2(dev)) {
6162 i8xx_update_pll(intel_crtc,
6163 has_reduced_clock ? &reduced_clock : NULL,
6164 num_connectors);
6165 } else if (IS_CHERRYVIEW(dev)) {
6166 chv_update_pll(intel_crtc);
6167 } else if (IS_VALLEYVIEW(dev)) {
6168 vlv_update_pll(intel_crtc);
6169 } else {
6170 i9xx_update_pll(intel_crtc,
6171 has_reduced_clock ? &reduced_clock : NULL,
6172 num_connectors);
6173 }
6174
6175 return 0;
6176 }
6177
6178 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6179 struct intel_crtc_config *pipe_config)
6180 {
6181 struct drm_device *dev = crtc->base.dev;
6182 struct drm_i915_private *dev_priv = dev->dev_private;
6183 uint32_t tmp;
6184
6185 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6186 return;
6187
6188 tmp = I915_READ(PFIT_CONTROL);
6189 if (!(tmp & PFIT_ENABLE))
6190 return;
6191
6192 /* Check whether the pfit is attached to our pipe. */
6193 if (INTEL_INFO(dev)->gen < 4) {
6194 if (crtc->pipe != PIPE_B)
6195 return;
6196 } else {
6197 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6198 return;
6199 }
6200
6201 pipe_config->gmch_pfit.control = tmp;
6202 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6203 if (INTEL_INFO(dev)->gen < 5)
6204 pipe_config->gmch_pfit.lvds_border_bits =
6205 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6206 }
6207
6208 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6209 struct intel_crtc_config *pipe_config)
6210 {
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 int pipe = pipe_config->cpu_transcoder;
6214 intel_clock_t clock;
6215 u32 mdiv;
6216 int refclk = 100000;
6217
6218 /* In case of MIPI DPLL will not even be used */
6219 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6220 return;
6221
6222 mutex_lock(&dev_priv->dpio_lock);
6223 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6224 mutex_unlock(&dev_priv->dpio_lock);
6225
6226 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6227 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6228 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6229 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6230 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6231
6232 vlv_clock(refclk, &clock);
6233
6234 /* clock.dot is the fast clock */
6235 pipe_config->port_clock = clock.dot / 5;
6236 }
6237
6238 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6239 struct intel_plane_config *plane_config)
6240 {
6241 struct drm_device *dev = crtc->base.dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 u32 val, base, offset;
6244 int pipe = crtc->pipe, plane = crtc->plane;
6245 int fourcc, pixel_format;
6246 int aligned_height;
6247
6248 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6249 if (!crtc->base.primary->fb) {
6250 DRM_DEBUG_KMS("failed to alloc fb\n");
6251 return;
6252 }
6253
6254 val = I915_READ(DSPCNTR(plane));
6255
6256 if (INTEL_INFO(dev)->gen >= 4)
6257 if (val & DISPPLANE_TILED)
6258 plane_config->tiled = true;
6259
6260 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6261 fourcc = intel_format_to_fourcc(pixel_format);
6262 crtc->base.primary->fb->pixel_format = fourcc;
6263 crtc->base.primary->fb->bits_per_pixel =
6264 drm_format_plane_cpp(fourcc, 0) * 8;
6265
6266 if (INTEL_INFO(dev)->gen >= 4) {
6267 if (plane_config->tiled)
6268 offset = I915_READ(DSPTILEOFF(plane));
6269 else
6270 offset = I915_READ(DSPLINOFF(plane));
6271 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6272 } else {
6273 base = I915_READ(DSPADDR(plane));
6274 }
6275 plane_config->base = base;
6276
6277 val = I915_READ(PIPESRC(pipe));
6278 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6279 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6280
6281 val = I915_READ(DSPSTRIDE(pipe));
6282 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6283
6284 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6285 plane_config->tiled);
6286
6287 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6288 aligned_height);
6289
6290 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6291 pipe, plane, crtc->base.primary->fb->width,
6292 crtc->base.primary->fb->height,
6293 crtc->base.primary->fb->bits_per_pixel, base,
6294 crtc->base.primary->fb->pitches[0],
6295 plane_config->size);
6296
6297 }
6298
6299 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6300 struct intel_crtc_config *pipe_config)
6301 {
6302 struct drm_device *dev = crtc->base.dev;
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 int pipe = pipe_config->cpu_transcoder;
6305 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6306 intel_clock_t clock;
6307 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6308 int refclk = 100000;
6309
6310 mutex_lock(&dev_priv->dpio_lock);
6311 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6312 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6313 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6314 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6315 mutex_unlock(&dev_priv->dpio_lock);
6316
6317 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6318 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6319 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6320 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6321 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6322
6323 chv_clock(refclk, &clock);
6324
6325 /* clock.dot is the fast clock */
6326 pipe_config->port_clock = clock.dot / 5;
6327 }
6328
6329 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6330 struct intel_crtc_config *pipe_config)
6331 {
6332 struct drm_device *dev = crtc->base.dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 uint32_t tmp;
6335
6336 if (!intel_display_power_enabled(dev_priv,
6337 POWER_DOMAIN_PIPE(crtc->pipe)))
6338 return false;
6339
6340 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6341 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6342
6343 tmp = I915_READ(PIPECONF(crtc->pipe));
6344 if (!(tmp & PIPECONF_ENABLE))
6345 return false;
6346
6347 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6348 switch (tmp & PIPECONF_BPC_MASK) {
6349 case PIPECONF_6BPC:
6350 pipe_config->pipe_bpp = 18;
6351 break;
6352 case PIPECONF_8BPC:
6353 pipe_config->pipe_bpp = 24;
6354 break;
6355 case PIPECONF_10BPC:
6356 pipe_config->pipe_bpp = 30;
6357 break;
6358 default:
6359 break;
6360 }
6361 }
6362
6363 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6364 pipe_config->limited_color_range = true;
6365
6366 if (INTEL_INFO(dev)->gen < 4)
6367 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6368
6369 intel_get_pipe_timings(crtc, pipe_config);
6370
6371 i9xx_get_pfit_config(crtc, pipe_config);
6372
6373 if (INTEL_INFO(dev)->gen >= 4) {
6374 tmp = I915_READ(DPLL_MD(crtc->pipe));
6375 pipe_config->pixel_multiplier =
6376 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6377 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6378 pipe_config->dpll_hw_state.dpll_md = tmp;
6379 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6380 tmp = I915_READ(DPLL(crtc->pipe));
6381 pipe_config->pixel_multiplier =
6382 ((tmp & SDVO_MULTIPLIER_MASK)
6383 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6384 } else {
6385 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6386 * port and will be fixed up in the encoder->get_config
6387 * function. */
6388 pipe_config->pixel_multiplier = 1;
6389 }
6390 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6391 if (!IS_VALLEYVIEW(dev)) {
6392 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6393 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6394 } else {
6395 /* Mask out read-only status bits. */
6396 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6397 DPLL_PORTC_READY_MASK |
6398 DPLL_PORTB_READY_MASK);
6399 }
6400
6401 if (IS_CHERRYVIEW(dev))
6402 chv_crtc_clock_get(crtc, pipe_config);
6403 else if (IS_VALLEYVIEW(dev))
6404 vlv_crtc_clock_get(crtc, pipe_config);
6405 else
6406 i9xx_crtc_clock_get(crtc, pipe_config);
6407
6408 return true;
6409 }
6410
6411 static void ironlake_init_pch_refclk(struct drm_device *dev)
6412 {
6413 struct drm_i915_private *dev_priv = dev->dev_private;
6414 struct intel_encoder *encoder;
6415 u32 val, final;
6416 bool has_lvds = false;
6417 bool has_cpu_edp = false;
6418 bool has_panel = false;
6419 bool has_ck505 = false;
6420 bool can_ssc = false;
6421
6422 /* We need to take the global config into account */
6423 for_each_intel_encoder(dev, encoder) {
6424 switch (encoder->type) {
6425 case INTEL_OUTPUT_LVDS:
6426 has_panel = true;
6427 has_lvds = true;
6428 break;
6429 case INTEL_OUTPUT_EDP:
6430 has_panel = true;
6431 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6432 has_cpu_edp = true;
6433 break;
6434 }
6435 }
6436
6437 if (HAS_PCH_IBX(dev)) {
6438 has_ck505 = dev_priv->vbt.display_clock_mode;
6439 can_ssc = has_ck505;
6440 } else {
6441 has_ck505 = false;
6442 can_ssc = true;
6443 }
6444
6445 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6446 has_panel, has_lvds, has_ck505);
6447
6448 /* Ironlake: try to setup display ref clock before DPLL
6449 * enabling. This is only under driver's control after
6450 * PCH B stepping, previous chipset stepping should be
6451 * ignoring this setting.
6452 */
6453 val = I915_READ(PCH_DREF_CONTROL);
6454
6455 /* As we must carefully and slowly disable/enable each source in turn,
6456 * compute the final state we want first and check if we need to
6457 * make any changes at all.
6458 */
6459 final = val;
6460 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6461 if (has_ck505)
6462 final |= DREF_NONSPREAD_CK505_ENABLE;
6463 else
6464 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6465
6466 final &= ~DREF_SSC_SOURCE_MASK;
6467 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6468 final &= ~DREF_SSC1_ENABLE;
6469
6470 if (has_panel) {
6471 final |= DREF_SSC_SOURCE_ENABLE;
6472
6473 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6474 final |= DREF_SSC1_ENABLE;
6475
6476 if (has_cpu_edp) {
6477 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6478 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6479 else
6480 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6481 } else
6482 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6483 } else {
6484 final |= DREF_SSC_SOURCE_DISABLE;
6485 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6486 }
6487
6488 if (final == val)
6489 return;
6490
6491 /* Always enable nonspread source */
6492 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6493
6494 if (has_ck505)
6495 val |= DREF_NONSPREAD_CK505_ENABLE;
6496 else
6497 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6498
6499 if (has_panel) {
6500 val &= ~DREF_SSC_SOURCE_MASK;
6501 val |= DREF_SSC_SOURCE_ENABLE;
6502
6503 /* SSC must be turned on before enabling the CPU output */
6504 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6505 DRM_DEBUG_KMS("Using SSC on panel\n");
6506 val |= DREF_SSC1_ENABLE;
6507 } else
6508 val &= ~DREF_SSC1_ENABLE;
6509
6510 /* Get SSC going before enabling the outputs */
6511 I915_WRITE(PCH_DREF_CONTROL, val);
6512 POSTING_READ(PCH_DREF_CONTROL);
6513 udelay(200);
6514
6515 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6516
6517 /* Enable CPU source on CPU attached eDP */
6518 if (has_cpu_edp) {
6519 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6520 DRM_DEBUG_KMS("Using SSC on eDP\n");
6521 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6522 } else
6523 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6524 } else
6525 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6526
6527 I915_WRITE(PCH_DREF_CONTROL, val);
6528 POSTING_READ(PCH_DREF_CONTROL);
6529 udelay(200);
6530 } else {
6531 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6532
6533 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6534
6535 /* Turn off CPU output */
6536 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6537
6538 I915_WRITE(PCH_DREF_CONTROL, val);
6539 POSTING_READ(PCH_DREF_CONTROL);
6540 udelay(200);
6541
6542 /* Turn off the SSC source */
6543 val &= ~DREF_SSC_SOURCE_MASK;
6544 val |= DREF_SSC_SOURCE_DISABLE;
6545
6546 /* Turn off SSC1 */
6547 val &= ~DREF_SSC1_ENABLE;
6548
6549 I915_WRITE(PCH_DREF_CONTROL, val);
6550 POSTING_READ(PCH_DREF_CONTROL);
6551 udelay(200);
6552 }
6553
6554 BUG_ON(val != final);
6555 }
6556
6557 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6558 {
6559 uint32_t tmp;
6560
6561 tmp = I915_READ(SOUTH_CHICKEN2);
6562 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6563 I915_WRITE(SOUTH_CHICKEN2, tmp);
6564
6565 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6566 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6567 DRM_ERROR("FDI mPHY reset assert timeout\n");
6568
6569 tmp = I915_READ(SOUTH_CHICKEN2);
6570 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6571 I915_WRITE(SOUTH_CHICKEN2, tmp);
6572
6573 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6574 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6575 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6576 }
6577
6578 /* WaMPhyProgramming:hsw */
6579 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6580 {
6581 uint32_t tmp;
6582
6583 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6584 tmp &= ~(0xFF << 24);
6585 tmp |= (0x12 << 24);
6586 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6587
6588 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6589 tmp |= (1 << 11);
6590 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6591
6592 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6593 tmp |= (1 << 11);
6594 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6595
6596 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6597 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6598 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6599
6600 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6601 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6602 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6603
6604 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6605 tmp &= ~(7 << 13);
6606 tmp |= (5 << 13);
6607 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6608
6609 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6610 tmp &= ~(7 << 13);
6611 tmp |= (5 << 13);
6612 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6613
6614 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6615 tmp &= ~0xFF;
6616 tmp |= 0x1C;
6617 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6618
6619 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6620 tmp &= ~0xFF;
6621 tmp |= 0x1C;
6622 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6623
6624 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6625 tmp &= ~(0xFF << 16);
6626 tmp |= (0x1C << 16);
6627 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6628
6629 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6630 tmp &= ~(0xFF << 16);
6631 tmp |= (0x1C << 16);
6632 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6633
6634 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6635 tmp |= (1 << 27);
6636 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6637
6638 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6639 tmp |= (1 << 27);
6640 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6641
6642 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6643 tmp &= ~(0xF << 28);
6644 tmp |= (4 << 28);
6645 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6646
6647 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6648 tmp &= ~(0xF << 28);
6649 tmp |= (4 << 28);
6650 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6651 }
6652
6653 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6654 * Programming" based on the parameters passed:
6655 * - Sequence to enable CLKOUT_DP
6656 * - Sequence to enable CLKOUT_DP without spread
6657 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6658 */
6659 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6660 bool with_fdi)
6661 {
6662 struct drm_i915_private *dev_priv = dev->dev_private;
6663 uint32_t reg, tmp;
6664
6665 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6666 with_spread = true;
6667 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6668 with_fdi, "LP PCH doesn't have FDI\n"))
6669 with_fdi = false;
6670
6671 mutex_lock(&dev_priv->dpio_lock);
6672
6673 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6674 tmp &= ~SBI_SSCCTL_DISABLE;
6675 tmp |= SBI_SSCCTL_PATHALT;
6676 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6677
6678 udelay(24);
6679
6680 if (with_spread) {
6681 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6682 tmp &= ~SBI_SSCCTL_PATHALT;
6683 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6684
6685 if (with_fdi) {
6686 lpt_reset_fdi_mphy(dev_priv);
6687 lpt_program_fdi_mphy(dev_priv);
6688 }
6689 }
6690
6691 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6692 SBI_GEN0 : SBI_DBUFF0;
6693 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6694 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6695 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6696
6697 mutex_unlock(&dev_priv->dpio_lock);
6698 }
6699
6700 /* Sequence to disable CLKOUT_DP */
6701 static void lpt_disable_clkout_dp(struct drm_device *dev)
6702 {
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 uint32_t reg, tmp;
6705
6706 mutex_lock(&dev_priv->dpio_lock);
6707
6708 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6709 SBI_GEN0 : SBI_DBUFF0;
6710 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6711 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6712 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6713
6714 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6715 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6716 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6717 tmp |= SBI_SSCCTL_PATHALT;
6718 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6719 udelay(32);
6720 }
6721 tmp |= SBI_SSCCTL_DISABLE;
6722 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6723 }
6724
6725 mutex_unlock(&dev_priv->dpio_lock);
6726 }
6727
6728 static void lpt_init_pch_refclk(struct drm_device *dev)
6729 {
6730 struct intel_encoder *encoder;
6731 bool has_vga = false;
6732
6733 for_each_intel_encoder(dev, encoder) {
6734 switch (encoder->type) {
6735 case INTEL_OUTPUT_ANALOG:
6736 has_vga = true;
6737 break;
6738 }
6739 }
6740
6741 if (has_vga)
6742 lpt_enable_clkout_dp(dev, true, true);
6743 else
6744 lpt_disable_clkout_dp(dev);
6745 }
6746
6747 /*
6748 * Initialize reference clocks when the driver loads
6749 */
6750 void intel_init_pch_refclk(struct drm_device *dev)
6751 {
6752 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6753 ironlake_init_pch_refclk(dev);
6754 else if (HAS_PCH_LPT(dev))
6755 lpt_init_pch_refclk(dev);
6756 }
6757
6758 static int ironlake_get_refclk(struct drm_crtc *crtc)
6759 {
6760 struct drm_device *dev = crtc->dev;
6761 struct drm_i915_private *dev_priv = dev->dev_private;
6762 struct intel_encoder *encoder;
6763 int num_connectors = 0;
6764 bool is_lvds = false;
6765
6766 for_each_encoder_on_crtc(dev, crtc, encoder) {
6767 switch (encoder->type) {
6768 case INTEL_OUTPUT_LVDS:
6769 is_lvds = true;
6770 break;
6771 }
6772 num_connectors++;
6773 }
6774
6775 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6776 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6777 dev_priv->vbt.lvds_ssc_freq);
6778 return dev_priv->vbt.lvds_ssc_freq;
6779 }
6780
6781 return 120000;
6782 }
6783
6784 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6785 {
6786 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788 int pipe = intel_crtc->pipe;
6789 uint32_t val;
6790
6791 val = 0;
6792
6793 switch (intel_crtc->config.pipe_bpp) {
6794 case 18:
6795 val |= PIPECONF_6BPC;
6796 break;
6797 case 24:
6798 val |= PIPECONF_8BPC;
6799 break;
6800 case 30:
6801 val |= PIPECONF_10BPC;
6802 break;
6803 case 36:
6804 val |= PIPECONF_12BPC;
6805 break;
6806 default:
6807 /* Case prevented by intel_choose_pipe_bpp_dither. */
6808 BUG();
6809 }
6810
6811 if (intel_crtc->config.dither)
6812 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6813
6814 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6815 val |= PIPECONF_INTERLACED_ILK;
6816 else
6817 val |= PIPECONF_PROGRESSIVE;
6818
6819 if (intel_crtc->config.limited_color_range)
6820 val |= PIPECONF_COLOR_RANGE_SELECT;
6821
6822 I915_WRITE(PIPECONF(pipe), val);
6823 POSTING_READ(PIPECONF(pipe));
6824 }
6825
6826 /*
6827 * Set up the pipe CSC unit.
6828 *
6829 * Currently only full range RGB to limited range RGB conversion
6830 * is supported, but eventually this should handle various
6831 * RGB<->YCbCr scenarios as well.
6832 */
6833 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6834 {
6835 struct drm_device *dev = crtc->dev;
6836 struct drm_i915_private *dev_priv = dev->dev_private;
6837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6838 int pipe = intel_crtc->pipe;
6839 uint16_t coeff = 0x7800; /* 1.0 */
6840
6841 /*
6842 * TODO: Check what kind of values actually come out of the pipe
6843 * with these coeff/postoff values and adjust to get the best
6844 * accuracy. Perhaps we even need to take the bpc value into
6845 * consideration.
6846 */
6847
6848 if (intel_crtc->config.limited_color_range)
6849 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6850
6851 /*
6852 * GY/GU and RY/RU should be the other way around according
6853 * to BSpec, but reality doesn't agree. Just set them up in
6854 * a way that results in the correct picture.
6855 */
6856 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6857 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6858
6859 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6860 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6861
6862 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6863 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6864
6865 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6866 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6867 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6868
6869 if (INTEL_INFO(dev)->gen > 6) {
6870 uint16_t postoff = 0;
6871
6872 if (intel_crtc->config.limited_color_range)
6873 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6874
6875 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6876 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6877 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6878
6879 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6880 } else {
6881 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6882
6883 if (intel_crtc->config.limited_color_range)
6884 mode |= CSC_BLACK_SCREEN_OFFSET;
6885
6886 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6887 }
6888 }
6889
6890 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6891 {
6892 struct drm_device *dev = crtc->dev;
6893 struct drm_i915_private *dev_priv = dev->dev_private;
6894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6895 enum pipe pipe = intel_crtc->pipe;
6896 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6897 uint32_t val;
6898
6899 val = 0;
6900
6901 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6902 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6903
6904 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6905 val |= PIPECONF_INTERLACED_ILK;
6906 else
6907 val |= PIPECONF_PROGRESSIVE;
6908
6909 I915_WRITE(PIPECONF(cpu_transcoder), val);
6910 POSTING_READ(PIPECONF(cpu_transcoder));
6911
6912 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6913 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6914
6915 if (IS_BROADWELL(dev)) {
6916 val = 0;
6917
6918 switch (intel_crtc->config.pipe_bpp) {
6919 case 18:
6920 val |= PIPEMISC_DITHER_6_BPC;
6921 break;
6922 case 24:
6923 val |= PIPEMISC_DITHER_8_BPC;
6924 break;
6925 case 30:
6926 val |= PIPEMISC_DITHER_10_BPC;
6927 break;
6928 case 36:
6929 val |= PIPEMISC_DITHER_12_BPC;
6930 break;
6931 default:
6932 /* Case prevented by pipe_config_set_bpp. */
6933 BUG();
6934 }
6935
6936 if (intel_crtc->config.dither)
6937 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6938
6939 I915_WRITE(PIPEMISC(pipe), val);
6940 }
6941 }
6942
6943 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6944 intel_clock_t *clock,
6945 bool *has_reduced_clock,
6946 intel_clock_t *reduced_clock)
6947 {
6948 struct drm_device *dev = crtc->dev;
6949 struct drm_i915_private *dev_priv = dev->dev_private;
6950 struct intel_encoder *intel_encoder;
6951 int refclk;
6952 const intel_limit_t *limit;
6953 bool ret, is_lvds = false;
6954
6955 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6956 switch (intel_encoder->type) {
6957 case INTEL_OUTPUT_LVDS:
6958 is_lvds = true;
6959 break;
6960 }
6961 }
6962
6963 refclk = ironlake_get_refclk(crtc);
6964
6965 /*
6966 * Returns a set of divisors for the desired target clock with the given
6967 * refclk, or FALSE. The returned values represent the clock equation:
6968 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6969 */
6970 limit = intel_limit(crtc, refclk);
6971 ret = dev_priv->display.find_dpll(limit, crtc,
6972 to_intel_crtc(crtc)->config.port_clock,
6973 refclk, NULL, clock);
6974 if (!ret)
6975 return false;
6976
6977 if (is_lvds && dev_priv->lvds_downclock_avail) {
6978 /*
6979 * Ensure we match the reduced clock's P to the target clock.
6980 * If the clocks don't match, we can't switch the display clock
6981 * by using the FP0/FP1. In such case we will disable the LVDS
6982 * downclock feature.
6983 */
6984 *has_reduced_clock =
6985 dev_priv->display.find_dpll(limit, crtc,
6986 dev_priv->lvds_downclock,
6987 refclk, clock,
6988 reduced_clock);
6989 }
6990
6991 return true;
6992 }
6993
6994 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6995 {
6996 /*
6997 * Account for spread spectrum to avoid
6998 * oversubscribing the link. Max center spread
6999 * is 2.5%; use 5% for safety's sake.
7000 */
7001 u32 bps = target_clock * bpp * 21 / 20;
7002 return DIV_ROUND_UP(bps, link_bw * 8);
7003 }
7004
7005 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7006 {
7007 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7008 }
7009
7010 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7011 u32 *fp,
7012 intel_clock_t *reduced_clock, u32 *fp2)
7013 {
7014 struct drm_crtc *crtc = &intel_crtc->base;
7015 struct drm_device *dev = crtc->dev;
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 struct intel_encoder *intel_encoder;
7018 uint32_t dpll;
7019 int factor, num_connectors = 0;
7020 bool is_lvds = false, is_sdvo = false;
7021
7022 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
7023 switch (intel_encoder->type) {
7024 case INTEL_OUTPUT_LVDS:
7025 is_lvds = true;
7026 break;
7027 case INTEL_OUTPUT_SDVO:
7028 case INTEL_OUTPUT_HDMI:
7029 is_sdvo = true;
7030 break;
7031 }
7032
7033 num_connectors++;
7034 }
7035
7036 /* Enable autotuning of the PLL clock (if permissible) */
7037 factor = 21;
7038 if (is_lvds) {
7039 if ((intel_panel_use_ssc(dev_priv) &&
7040 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7041 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7042 factor = 25;
7043 } else if (intel_crtc->config.sdvo_tv_clock)
7044 factor = 20;
7045
7046 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7047 *fp |= FP_CB_TUNE;
7048
7049 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7050 *fp2 |= FP_CB_TUNE;
7051
7052 dpll = 0;
7053
7054 if (is_lvds)
7055 dpll |= DPLLB_MODE_LVDS;
7056 else
7057 dpll |= DPLLB_MODE_DAC_SERIAL;
7058
7059 dpll |= (intel_crtc->config.pixel_multiplier - 1)
7060 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7061
7062 if (is_sdvo)
7063 dpll |= DPLL_SDVO_HIGH_SPEED;
7064 if (intel_crtc->config.has_dp_encoder)
7065 dpll |= DPLL_SDVO_HIGH_SPEED;
7066
7067 /* compute bitmask from p1 value */
7068 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7069 /* also FPA1 */
7070 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7071
7072 switch (intel_crtc->config.dpll.p2) {
7073 case 5:
7074 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7075 break;
7076 case 7:
7077 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7078 break;
7079 case 10:
7080 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7081 break;
7082 case 14:
7083 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7084 break;
7085 }
7086
7087 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7088 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7089 else
7090 dpll |= PLL_REF_INPUT_DREFCLK;
7091
7092 return dpll | DPLL_VCO_ENABLE;
7093 }
7094
7095 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7096 int x, int y,
7097 struct drm_framebuffer *fb)
7098 {
7099 struct drm_device *dev = crtc->dev;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101 int num_connectors = 0;
7102 intel_clock_t clock, reduced_clock;
7103 u32 dpll = 0, fp = 0, fp2 = 0;
7104 bool ok, has_reduced_clock = false;
7105 bool is_lvds = false;
7106 struct intel_encoder *encoder;
7107 struct intel_shared_dpll *pll;
7108
7109 for_each_encoder_on_crtc(dev, crtc, encoder) {
7110 switch (encoder->type) {
7111 case INTEL_OUTPUT_LVDS:
7112 is_lvds = true;
7113 break;
7114 }
7115
7116 num_connectors++;
7117 }
7118
7119 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7120 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7121
7122 ok = ironlake_compute_clocks(crtc, &clock,
7123 &has_reduced_clock, &reduced_clock);
7124 if (!ok && !intel_crtc->config.clock_set) {
7125 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7126 return -EINVAL;
7127 }
7128 /* Compat-code for transition, will disappear. */
7129 if (!intel_crtc->config.clock_set) {
7130 intel_crtc->config.dpll.n = clock.n;
7131 intel_crtc->config.dpll.m1 = clock.m1;
7132 intel_crtc->config.dpll.m2 = clock.m2;
7133 intel_crtc->config.dpll.p1 = clock.p1;
7134 intel_crtc->config.dpll.p2 = clock.p2;
7135 }
7136
7137 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7138 if (intel_crtc->config.has_pch_encoder) {
7139 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7140 if (has_reduced_clock)
7141 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7142
7143 dpll = ironlake_compute_dpll(intel_crtc,
7144 &fp, &reduced_clock,
7145 has_reduced_clock ? &fp2 : NULL);
7146
7147 intel_crtc->config.dpll_hw_state.dpll = dpll;
7148 intel_crtc->config.dpll_hw_state.fp0 = fp;
7149 if (has_reduced_clock)
7150 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7151 else
7152 intel_crtc->config.dpll_hw_state.fp1 = fp;
7153
7154 pll = intel_get_shared_dpll(intel_crtc);
7155 if (pll == NULL) {
7156 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7157 pipe_name(intel_crtc->pipe));
7158 return -EINVAL;
7159 }
7160 } else
7161 intel_put_shared_dpll(intel_crtc);
7162
7163 if (is_lvds && has_reduced_clock && i915.powersave)
7164 intel_crtc->lowfreq_avail = true;
7165 else
7166 intel_crtc->lowfreq_avail = false;
7167
7168 return 0;
7169 }
7170
7171 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7172 struct intel_link_m_n *m_n)
7173 {
7174 struct drm_device *dev = crtc->base.dev;
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 enum pipe pipe = crtc->pipe;
7177
7178 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7179 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7180 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7181 & ~TU_SIZE_MASK;
7182 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7183 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7184 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7185 }
7186
7187 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7188 enum transcoder transcoder,
7189 struct intel_link_m_n *m_n,
7190 struct intel_link_m_n *m2_n2)
7191 {
7192 struct drm_device *dev = crtc->base.dev;
7193 struct drm_i915_private *dev_priv = dev->dev_private;
7194 enum pipe pipe = crtc->pipe;
7195
7196 if (INTEL_INFO(dev)->gen >= 5) {
7197 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7198 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7199 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7200 & ~TU_SIZE_MASK;
7201 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7202 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7203 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7204 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7205 * gen < 8) and if DRRS is supported (to make sure the
7206 * registers are not unnecessarily read).
7207 */
7208 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7209 crtc->config.has_drrs) {
7210 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7211 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7212 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7213 & ~TU_SIZE_MASK;
7214 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7215 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7216 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7217 }
7218 } else {
7219 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7220 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7221 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7222 & ~TU_SIZE_MASK;
7223 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7224 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7225 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7226 }
7227 }
7228
7229 void intel_dp_get_m_n(struct intel_crtc *crtc,
7230 struct intel_crtc_config *pipe_config)
7231 {
7232 if (crtc->config.has_pch_encoder)
7233 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7234 else
7235 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7236 &pipe_config->dp_m_n,
7237 &pipe_config->dp_m2_n2);
7238 }
7239
7240 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7241 struct intel_crtc_config *pipe_config)
7242 {
7243 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7244 &pipe_config->fdi_m_n, NULL);
7245 }
7246
7247 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7248 struct intel_crtc_config *pipe_config)
7249 {
7250 struct drm_device *dev = crtc->base.dev;
7251 struct drm_i915_private *dev_priv = dev->dev_private;
7252 uint32_t tmp;
7253
7254 tmp = I915_READ(PF_CTL(crtc->pipe));
7255
7256 if (tmp & PF_ENABLE) {
7257 pipe_config->pch_pfit.enabled = true;
7258 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7259 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7260
7261 /* We currently do not free assignements of panel fitters on
7262 * ivb/hsw (since we don't use the higher upscaling modes which
7263 * differentiates them) so just WARN about this case for now. */
7264 if (IS_GEN7(dev)) {
7265 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7266 PF_PIPE_SEL_IVB(crtc->pipe));
7267 }
7268 }
7269 }
7270
7271 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7272 struct intel_plane_config *plane_config)
7273 {
7274 struct drm_device *dev = crtc->base.dev;
7275 struct drm_i915_private *dev_priv = dev->dev_private;
7276 u32 val, base, offset;
7277 int pipe = crtc->pipe, plane = crtc->plane;
7278 int fourcc, pixel_format;
7279 int aligned_height;
7280
7281 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7282 if (!crtc->base.primary->fb) {
7283 DRM_DEBUG_KMS("failed to alloc fb\n");
7284 return;
7285 }
7286
7287 val = I915_READ(DSPCNTR(plane));
7288
7289 if (INTEL_INFO(dev)->gen >= 4)
7290 if (val & DISPPLANE_TILED)
7291 plane_config->tiled = true;
7292
7293 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7294 fourcc = intel_format_to_fourcc(pixel_format);
7295 crtc->base.primary->fb->pixel_format = fourcc;
7296 crtc->base.primary->fb->bits_per_pixel =
7297 drm_format_plane_cpp(fourcc, 0) * 8;
7298
7299 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7300 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7301 offset = I915_READ(DSPOFFSET(plane));
7302 } else {
7303 if (plane_config->tiled)
7304 offset = I915_READ(DSPTILEOFF(plane));
7305 else
7306 offset = I915_READ(DSPLINOFF(plane));
7307 }
7308 plane_config->base = base;
7309
7310 val = I915_READ(PIPESRC(pipe));
7311 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7312 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7313
7314 val = I915_READ(DSPSTRIDE(pipe));
7315 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7316
7317 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7318 plane_config->tiled);
7319
7320 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7321 aligned_height);
7322
7323 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7324 pipe, plane, crtc->base.primary->fb->width,
7325 crtc->base.primary->fb->height,
7326 crtc->base.primary->fb->bits_per_pixel, base,
7327 crtc->base.primary->fb->pitches[0],
7328 plane_config->size);
7329 }
7330
7331 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7332 struct intel_crtc_config *pipe_config)
7333 {
7334 struct drm_device *dev = crtc->base.dev;
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 uint32_t tmp;
7337
7338 if (!intel_display_power_enabled(dev_priv,
7339 POWER_DOMAIN_PIPE(crtc->pipe)))
7340 return false;
7341
7342 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7343 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7344
7345 tmp = I915_READ(PIPECONF(crtc->pipe));
7346 if (!(tmp & PIPECONF_ENABLE))
7347 return false;
7348
7349 switch (tmp & PIPECONF_BPC_MASK) {
7350 case PIPECONF_6BPC:
7351 pipe_config->pipe_bpp = 18;
7352 break;
7353 case PIPECONF_8BPC:
7354 pipe_config->pipe_bpp = 24;
7355 break;
7356 case PIPECONF_10BPC:
7357 pipe_config->pipe_bpp = 30;
7358 break;
7359 case PIPECONF_12BPC:
7360 pipe_config->pipe_bpp = 36;
7361 break;
7362 default:
7363 break;
7364 }
7365
7366 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7367 pipe_config->limited_color_range = true;
7368
7369 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7370 struct intel_shared_dpll *pll;
7371
7372 pipe_config->has_pch_encoder = true;
7373
7374 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7375 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7376 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7377
7378 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7379
7380 if (HAS_PCH_IBX(dev_priv->dev)) {
7381 pipe_config->shared_dpll =
7382 (enum intel_dpll_id) crtc->pipe;
7383 } else {
7384 tmp = I915_READ(PCH_DPLL_SEL);
7385 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7386 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7387 else
7388 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7389 }
7390
7391 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7392
7393 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7394 &pipe_config->dpll_hw_state));
7395
7396 tmp = pipe_config->dpll_hw_state.dpll;
7397 pipe_config->pixel_multiplier =
7398 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7399 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7400
7401 ironlake_pch_clock_get(crtc, pipe_config);
7402 } else {
7403 pipe_config->pixel_multiplier = 1;
7404 }
7405
7406 intel_get_pipe_timings(crtc, pipe_config);
7407
7408 ironlake_get_pfit_config(crtc, pipe_config);
7409
7410 return true;
7411 }
7412
7413 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7414 {
7415 struct drm_device *dev = dev_priv->dev;
7416 struct intel_crtc *crtc;
7417
7418 for_each_intel_crtc(dev, crtc)
7419 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7420 pipe_name(crtc->pipe));
7421
7422 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7423 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7424 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7425 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7426 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7427 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7428 "CPU PWM1 enabled\n");
7429 if (IS_HASWELL(dev))
7430 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7431 "CPU PWM2 enabled\n");
7432 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7433 "PCH PWM1 enabled\n");
7434 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7435 "Utility pin enabled\n");
7436 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7437
7438 /*
7439 * In theory we can still leave IRQs enabled, as long as only the HPD
7440 * interrupts remain enabled. We used to check for that, but since it's
7441 * gen-specific and since we only disable LCPLL after we fully disable
7442 * the interrupts, the check below should be enough.
7443 */
7444 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7445 }
7446
7447 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7448 {
7449 struct drm_device *dev = dev_priv->dev;
7450
7451 if (IS_HASWELL(dev))
7452 return I915_READ(D_COMP_HSW);
7453 else
7454 return I915_READ(D_COMP_BDW);
7455 }
7456
7457 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7458 {
7459 struct drm_device *dev = dev_priv->dev;
7460
7461 if (IS_HASWELL(dev)) {
7462 mutex_lock(&dev_priv->rps.hw_lock);
7463 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7464 val))
7465 DRM_ERROR("Failed to write to D_COMP\n");
7466 mutex_unlock(&dev_priv->rps.hw_lock);
7467 } else {
7468 I915_WRITE(D_COMP_BDW, val);
7469 POSTING_READ(D_COMP_BDW);
7470 }
7471 }
7472
7473 /*
7474 * This function implements pieces of two sequences from BSpec:
7475 * - Sequence for display software to disable LCPLL
7476 * - Sequence for display software to allow package C8+
7477 * The steps implemented here are just the steps that actually touch the LCPLL
7478 * register. Callers should take care of disabling all the display engine
7479 * functions, doing the mode unset, fixing interrupts, etc.
7480 */
7481 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7482 bool switch_to_fclk, bool allow_power_down)
7483 {
7484 uint32_t val;
7485
7486 assert_can_disable_lcpll(dev_priv);
7487
7488 val = I915_READ(LCPLL_CTL);
7489
7490 if (switch_to_fclk) {
7491 val |= LCPLL_CD_SOURCE_FCLK;
7492 I915_WRITE(LCPLL_CTL, val);
7493
7494 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7495 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7496 DRM_ERROR("Switching to FCLK failed\n");
7497
7498 val = I915_READ(LCPLL_CTL);
7499 }
7500
7501 val |= LCPLL_PLL_DISABLE;
7502 I915_WRITE(LCPLL_CTL, val);
7503 POSTING_READ(LCPLL_CTL);
7504
7505 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7506 DRM_ERROR("LCPLL still locked\n");
7507
7508 val = hsw_read_dcomp(dev_priv);
7509 val |= D_COMP_COMP_DISABLE;
7510 hsw_write_dcomp(dev_priv, val);
7511 ndelay(100);
7512
7513 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7514 1))
7515 DRM_ERROR("D_COMP RCOMP still in progress\n");
7516
7517 if (allow_power_down) {
7518 val = I915_READ(LCPLL_CTL);
7519 val |= LCPLL_POWER_DOWN_ALLOW;
7520 I915_WRITE(LCPLL_CTL, val);
7521 POSTING_READ(LCPLL_CTL);
7522 }
7523 }
7524
7525 /*
7526 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7527 * source.
7528 */
7529 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7530 {
7531 uint32_t val;
7532 unsigned long irqflags;
7533
7534 val = I915_READ(LCPLL_CTL);
7535
7536 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7537 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7538 return;
7539
7540 /*
7541 * Make sure we're not on PC8 state before disabling PC8, otherwise
7542 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7543 *
7544 * The other problem is that hsw_restore_lcpll() is called as part of
7545 * the runtime PM resume sequence, so we can't just call
7546 * gen6_gt_force_wake_get() because that function calls
7547 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7548 * while we are on the resume sequence. So to solve this problem we have
7549 * to call special forcewake code that doesn't touch runtime PM and
7550 * doesn't enable the forcewake delayed work.
7551 */
7552 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7553 if (dev_priv->uncore.forcewake_count++ == 0)
7554 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7555 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7556
7557 if (val & LCPLL_POWER_DOWN_ALLOW) {
7558 val &= ~LCPLL_POWER_DOWN_ALLOW;
7559 I915_WRITE(LCPLL_CTL, val);
7560 POSTING_READ(LCPLL_CTL);
7561 }
7562
7563 val = hsw_read_dcomp(dev_priv);
7564 val |= D_COMP_COMP_FORCE;
7565 val &= ~D_COMP_COMP_DISABLE;
7566 hsw_write_dcomp(dev_priv, val);
7567
7568 val = I915_READ(LCPLL_CTL);
7569 val &= ~LCPLL_PLL_DISABLE;
7570 I915_WRITE(LCPLL_CTL, val);
7571
7572 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7573 DRM_ERROR("LCPLL not locked yet\n");
7574
7575 if (val & LCPLL_CD_SOURCE_FCLK) {
7576 val = I915_READ(LCPLL_CTL);
7577 val &= ~LCPLL_CD_SOURCE_FCLK;
7578 I915_WRITE(LCPLL_CTL, val);
7579
7580 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7581 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7582 DRM_ERROR("Switching back to LCPLL failed\n");
7583 }
7584
7585 /* See the big comment above. */
7586 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7587 if (--dev_priv->uncore.forcewake_count == 0)
7588 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7589 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7590 }
7591
7592 /*
7593 * Package states C8 and deeper are really deep PC states that can only be
7594 * reached when all the devices on the system allow it, so even if the graphics
7595 * device allows PC8+, it doesn't mean the system will actually get to these
7596 * states. Our driver only allows PC8+ when going into runtime PM.
7597 *
7598 * The requirements for PC8+ are that all the outputs are disabled, the power
7599 * well is disabled and most interrupts are disabled, and these are also
7600 * requirements for runtime PM. When these conditions are met, we manually do
7601 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7602 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7603 * hang the machine.
7604 *
7605 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7606 * the state of some registers, so when we come back from PC8+ we need to
7607 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7608 * need to take care of the registers kept by RC6. Notice that this happens even
7609 * if we don't put the device in PCI D3 state (which is what currently happens
7610 * because of the runtime PM support).
7611 *
7612 * For more, read "Display Sequences for Package C8" on the hardware
7613 * documentation.
7614 */
7615 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7616 {
7617 struct drm_device *dev = dev_priv->dev;
7618 uint32_t val;
7619
7620 DRM_DEBUG_KMS("Enabling package C8+\n");
7621
7622 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7623 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7624 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7625 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7626 }
7627
7628 lpt_disable_clkout_dp(dev);
7629 hsw_disable_lcpll(dev_priv, true, true);
7630 }
7631
7632 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7633 {
7634 struct drm_device *dev = dev_priv->dev;
7635 uint32_t val;
7636
7637 DRM_DEBUG_KMS("Disabling package C8+\n");
7638
7639 hsw_restore_lcpll(dev_priv);
7640 lpt_init_pch_refclk(dev);
7641
7642 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7643 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7644 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7645 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7646 }
7647
7648 intel_prepare_ddi(dev);
7649 }
7650
7651 static void snb_modeset_global_resources(struct drm_device *dev)
7652 {
7653 modeset_update_crtc_power_domains(dev);
7654 }
7655
7656 static void haswell_modeset_global_resources(struct drm_device *dev)
7657 {
7658 modeset_update_crtc_power_domains(dev);
7659 }
7660
7661 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7662 int x, int y,
7663 struct drm_framebuffer *fb)
7664 {
7665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7666
7667 if (!intel_ddi_pll_select(intel_crtc))
7668 return -EINVAL;
7669
7670 intel_crtc->lowfreq_avail = false;
7671
7672 return 0;
7673 }
7674
7675 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7676 enum port port,
7677 struct intel_crtc_config *pipe_config)
7678 {
7679 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7680
7681 switch (pipe_config->ddi_pll_sel) {
7682 case PORT_CLK_SEL_WRPLL1:
7683 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7684 break;
7685 case PORT_CLK_SEL_WRPLL2:
7686 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7687 break;
7688 }
7689 }
7690
7691 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7692 struct intel_crtc_config *pipe_config)
7693 {
7694 struct drm_device *dev = crtc->base.dev;
7695 struct drm_i915_private *dev_priv = dev->dev_private;
7696 struct intel_shared_dpll *pll;
7697 enum port port;
7698 uint32_t tmp;
7699
7700 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7701
7702 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7703
7704 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7705
7706 if (pipe_config->shared_dpll >= 0) {
7707 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7708
7709 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7710 &pipe_config->dpll_hw_state));
7711 }
7712
7713 /*
7714 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7715 * DDI E. So just check whether this pipe is wired to DDI E and whether
7716 * the PCH transcoder is on.
7717 */
7718 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7719 pipe_config->has_pch_encoder = true;
7720
7721 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7722 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7723 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7724
7725 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7726 }
7727 }
7728
7729 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7730 struct intel_crtc_config *pipe_config)
7731 {
7732 struct drm_device *dev = crtc->base.dev;
7733 struct drm_i915_private *dev_priv = dev->dev_private;
7734 enum intel_display_power_domain pfit_domain;
7735 uint32_t tmp;
7736
7737 if (!intel_display_power_enabled(dev_priv,
7738 POWER_DOMAIN_PIPE(crtc->pipe)))
7739 return false;
7740
7741 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7742 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7743
7744 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7745 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7746 enum pipe trans_edp_pipe;
7747 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7748 default:
7749 WARN(1, "unknown pipe linked to edp transcoder\n");
7750 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7751 case TRANS_DDI_EDP_INPUT_A_ON:
7752 trans_edp_pipe = PIPE_A;
7753 break;
7754 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7755 trans_edp_pipe = PIPE_B;
7756 break;
7757 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7758 trans_edp_pipe = PIPE_C;
7759 break;
7760 }
7761
7762 if (trans_edp_pipe == crtc->pipe)
7763 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7764 }
7765
7766 if (!intel_display_power_enabled(dev_priv,
7767 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7768 return false;
7769
7770 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7771 if (!(tmp & PIPECONF_ENABLE))
7772 return false;
7773
7774 haswell_get_ddi_port_state(crtc, pipe_config);
7775
7776 intel_get_pipe_timings(crtc, pipe_config);
7777
7778 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7779 if (intel_display_power_enabled(dev_priv, pfit_domain))
7780 ironlake_get_pfit_config(crtc, pipe_config);
7781
7782 if (IS_HASWELL(dev))
7783 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7784 (I915_READ(IPS_CTL) & IPS_ENABLE);
7785
7786 pipe_config->pixel_multiplier = 1;
7787
7788 return true;
7789 }
7790
7791 static struct {
7792 int clock;
7793 u32 config;
7794 } hdmi_audio_clock[] = {
7795 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7796 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7797 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7798 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7799 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7800 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7801 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7802 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7803 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7804 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7805 };
7806
7807 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7808 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7809 {
7810 int i;
7811
7812 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7813 if (mode->clock == hdmi_audio_clock[i].clock)
7814 break;
7815 }
7816
7817 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7818 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7819 i = 1;
7820 }
7821
7822 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7823 hdmi_audio_clock[i].clock,
7824 hdmi_audio_clock[i].config);
7825
7826 return hdmi_audio_clock[i].config;
7827 }
7828
7829 static bool intel_eld_uptodate(struct drm_connector *connector,
7830 int reg_eldv, uint32_t bits_eldv,
7831 int reg_elda, uint32_t bits_elda,
7832 int reg_edid)
7833 {
7834 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7835 uint8_t *eld = connector->eld;
7836 uint32_t i;
7837
7838 i = I915_READ(reg_eldv);
7839 i &= bits_eldv;
7840
7841 if (!eld[0])
7842 return !i;
7843
7844 if (!i)
7845 return false;
7846
7847 i = I915_READ(reg_elda);
7848 i &= ~bits_elda;
7849 I915_WRITE(reg_elda, i);
7850
7851 for (i = 0; i < eld[2]; i++)
7852 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7853 return false;
7854
7855 return true;
7856 }
7857
7858 static void g4x_write_eld(struct drm_connector *connector,
7859 struct drm_crtc *crtc,
7860 struct drm_display_mode *mode)
7861 {
7862 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7863 uint8_t *eld = connector->eld;
7864 uint32_t eldv;
7865 uint32_t len;
7866 uint32_t i;
7867
7868 i = I915_READ(G4X_AUD_VID_DID);
7869
7870 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7871 eldv = G4X_ELDV_DEVCL_DEVBLC;
7872 else
7873 eldv = G4X_ELDV_DEVCTG;
7874
7875 if (intel_eld_uptodate(connector,
7876 G4X_AUD_CNTL_ST, eldv,
7877 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7878 G4X_HDMIW_HDMIEDID))
7879 return;
7880
7881 i = I915_READ(G4X_AUD_CNTL_ST);
7882 i &= ~(eldv | G4X_ELD_ADDR);
7883 len = (i >> 9) & 0x1f; /* ELD buffer size */
7884 I915_WRITE(G4X_AUD_CNTL_ST, i);
7885
7886 if (!eld[0])
7887 return;
7888
7889 len = min_t(uint8_t, eld[2], len);
7890 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7891 for (i = 0; i < len; i++)
7892 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7893
7894 i = I915_READ(G4X_AUD_CNTL_ST);
7895 i |= eldv;
7896 I915_WRITE(G4X_AUD_CNTL_ST, i);
7897 }
7898
7899 static void haswell_write_eld(struct drm_connector *connector,
7900 struct drm_crtc *crtc,
7901 struct drm_display_mode *mode)
7902 {
7903 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7904 uint8_t *eld = connector->eld;
7905 uint32_t eldv;
7906 uint32_t i;
7907 int len;
7908 int pipe = to_intel_crtc(crtc)->pipe;
7909 int tmp;
7910
7911 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7912 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7913 int aud_config = HSW_AUD_CFG(pipe);
7914 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7915
7916 /* Audio output enable */
7917 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7918 tmp = I915_READ(aud_cntrl_st2);
7919 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7920 I915_WRITE(aud_cntrl_st2, tmp);
7921 POSTING_READ(aud_cntrl_st2);
7922
7923 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7924
7925 /* Set ELD valid state */
7926 tmp = I915_READ(aud_cntrl_st2);
7927 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7928 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7929 I915_WRITE(aud_cntrl_st2, tmp);
7930 tmp = I915_READ(aud_cntrl_st2);
7931 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7932
7933 /* Enable HDMI mode */
7934 tmp = I915_READ(aud_config);
7935 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7936 /* clear N_programing_enable and N_value_index */
7937 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7938 I915_WRITE(aud_config, tmp);
7939
7940 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7941
7942 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7943
7944 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7945 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7946 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7947 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7948 } else {
7949 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7950 }
7951
7952 if (intel_eld_uptodate(connector,
7953 aud_cntrl_st2, eldv,
7954 aud_cntl_st, IBX_ELD_ADDRESS,
7955 hdmiw_hdmiedid))
7956 return;
7957
7958 i = I915_READ(aud_cntrl_st2);
7959 i &= ~eldv;
7960 I915_WRITE(aud_cntrl_st2, i);
7961
7962 if (!eld[0])
7963 return;
7964
7965 i = I915_READ(aud_cntl_st);
7966 i &= ~IBX_ELD_ADDRESS;
7967 I915_WRITE(aud_cntl_st, i);
7968 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7969 DRM_DEBUG_DRIVER("port num:%d\n", i);
7970
7971 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7972 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7973 for (i = 0; i < len; i++)
7974 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7975
7976 i = I915_READ(aud_cntrl_st2);
7977 i |= eldv;
7978 I915_WRITE(aud_cntrl_st2, i);
7979
7980 }
7981
7982 static void ironlake_write_eld(struct drm_connector *connector,
7983 struct drm_crtc *crtc,
7984 struct drm_display_mode *mode)
7985 {
7986 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7987 uint8_t *eld = connector->eld;
7988 uint32_t eldv;
7989 uint32_t i;
7990 int len;
7991 int hdmiw_hdmiedid;
7992 int aud_config;
7993 int aud_cntl_st;
7994 int aud_cntrl_st2;
7995 int pipe = to_intel_crtc(crtc)->pipe;
7996
7997 if (HAS_PCH_IBX(connector->dev)) {
7998 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7999 aud_config = IBX_AUD_CFG(pipe);
8000 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
8001 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
8002 } else if (IS_VALLEYVIEW(connector->dev)) {
8003 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
8004 aud_config = VLV_AUD_CFG(pipe);
8005 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
8006 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
8007 } else {
8008 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
8009 aud_config = CPT_AUD_CFG(pipe);
8010 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
8011 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
8012 }
8013
8014 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
8015
8016 if (IS_VALLEYVIEW(connector->dev)) {
8017 struct intel_encoder *intel_encoder;
8018 struct intel_digital_port *intel_dig_port;
8019
8020 intel_encoder = intel_attached_encoder(connector);
8021 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
8022 i = intel_dig_port->port;
8023 } else {
8024 i = I915_READ(aud_cntl_st);
8025 i = (i >> 29) & DIP_PORT_SEL_MASK;
8026 /* DIP_Port_Select, 0x1 = PortB */
8027 }
8028
8029 if (!i) {
8030 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8031 /* operate blindly on all ports */
8032 eldv = IBX_ELD_VALIDB;
8033 eldv |= IBX_ELD_VALIDB << 4;
8034 eldv |= IBX_ELD_VALIDB << 8;
8035 } else {
8036 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
8037 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
8038 }
8039
8040 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
8041 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8042 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8043 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
8044 } else {
8045 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
8046 }
8047
8048 if (intel_eld_uptodate(connector,
8049 aud_cntrl_st2, eldv,
8050 aud_cntl_st, IBX_ELD_ADDRESS,
8051 hdmiw_hdmiedid))
8052 return;
8053
8054 i = I915_READ(aud_cntrl_st2);
8055 i &= ~eldv;
8056 I915_WRITE(aud_cntrl_st2, i);
8057
8058 if (!eld[0])
8059 return;
8060
8061 i = I915_READ(aud_cntl_st);
8062 i &= ~IBX_ELD_ADDRESS;
8063 I915_WRITE(aud_cntl_st, i);
8064
8065 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
8066 DRM_DEBUG_DRIVER("ELD size %d\n", len);
8067 for (i = 0; i < len; i++)
8068 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
8069
8070 i = I915_READ(aud_cntrl_st2);
8071 i |= eldv;
8072 I915_WRITE(aud_cntrl_st2, i);
8073 }
8074
8075 void intel_write_eld(struct drm_encoder *encoder,
8076 struct drm_display_mode *mode)
8077 {
8078 struct drm_crtc *crtc = encoder->crtc;
8079 struct drm_connector *connector;
8080 struct drm_device *dev = encoder->dev;
8081 struct drm_i915_private *dev_priv = dev->dev_private;
8082
8083 connector = drm_select_eld(encoder, mode);
8084 if (!connector)
8085 return;
8086
8087 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8088 connector->base.id,
8089 connector->name,
8090 connector->encoder->base.id,
8091 connector->encoder->name);
8092
8093 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
8094
8095 if (dev_priv->display.write_eld)
8096 dev_priv->display.write_eld(connector, crtc, mode);
8097 }
8098
8099 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8100 {
8101 struct drm_device *dev = crtc->dev;
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8104 uint32_t cntl = 0, size = 0;
8105
8106 if (base) {
8107 unsigned int width = intel_crtc->cursor_width;
8108 unsigned int height = intel_crtc->cursor_height;
8109 unsigned int stride = roundup_pow_of_two(width) * 4;
8110
8111 switch (stride) {
8112 default:
8113 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8114 width, stride);
8115 stride = 256;
8116 /* fallthrough */
8117 case 256:
8118 case 512:
8119 case 1024:
8120 case 2048:
8121 break;
8122 }
8123
8124 cntl |= CURSOR_ENABLE |
8125 CURSOR_GAMMA_ENABLE |
8126 CURSOR_FORMAT_ARGB |
8127 CURSOR_STRIDE(stride);
8128
8129 size = (height << 12) | width;
8130 }
8131
8132 if (intel_crtc->cursor_cntl != 0 &&
8133 (intel_crtc->cursor_base != base ||
8134 intel_crtc->cursor_size != size ||
8135 intel_crtc->cursor_cntl != cntl)) {
8136 /* On these chipsets we can only modify the base/size/stride
8137 * whilst the cursor is disabled.
8138 */
8139 I915_WRITE(_CURACNTR, 0);
8140 POSTING_READ(_CURACNTR);
8141 intel_crtc->cursor_cntl = 0;
8142 }
8143
8144 if (intel_crtc->cursor_base != base)
8145 I915_WRITE(_CURABASE, base);
8146
8147 if (intel_crtc->cursor_size != size) {
8148 I915_WRITE(CURSIZE, size);
8149 intel_crtc->cursor_size = size;
8150 }
8151
8152 if (intel_crtc->cursor_cntl != cntl) {
8153 I915_WRITE(_CURACNTR, cntl);
8154 POSTING_READ(_CURACNTR);
8155 intel_crtc->cursor_cntl = cntl;
8156 }
8157 }
8158
8159 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8160 {
8161 struct drm_device *dev = crtc->dev;
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8164 int pipe = intel_crtc->pipe;
8165 uint32_t cntl;
8166
8167 cntl = 0;
8168 if (base) {
8169 cntl = MCURSOR_GAMMA_ENABLE;
8170 switch (intel_crtc->cursor_width) {
8171 case 64:
8172 cntl |= CURSOR_MODE_64_ARGB_AX;
8173 break;
8174 case 128:
8175 cntl |= CURSOR_MODE_128_ARGB_AX;
8176 break;
8177 case 256:
8178 cntl |= CURSOR_MODE_256_ARGB_AX;
8179 break;
8180 default:
8181 WARN_ON(1);
8182 return;
8183 }
8184 cntl |= pipe << 28; /* Connect to correct pipe */
8185 }
8186 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8187 cntl |= CURSOR_PIPE_CSC_ENABLE;
8188
8189 if (intel_crtc->cursor_cntl != cntl) {
8190 I915_WRITE(CURCNTR(pipe), cntl);
8191 POSTING_READ(CURCNTR(pipe));
8192 intel_crtc->cursor_cntl = cntl;
8193 }
8194
8195 /* and commit changes on next vblank */
8196 I915_WRITE(CURBASE(pipe), base);
8197 POSTING_READ(CURBASE(pipe));
8198 }
8199
8200 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8201 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8202 bool on)
8203 {
8204 struct drm_device *dev = crtc->dev;
8205 struct drm_i915_private *dev_priv = dev->dev_private;
8206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8207 int pipe = intel_crtc->pipe;
8208 int x = crtc->cursor_x;
8209 int y = crtc->cursor_y;
8210 u32 base = 0, pos = 0;
8211
8212 if (on)
8213 base = intel_crtc->cursor_addr;
8214
8215 if (x >= intel_crtc->config.pipe_src_w)
8216 base = 0;
8217
8218 if (y >= intel_crtc->config.pipe_src_h)
8219 base = 0;
8220
8221 if (x < 0) {
8222 if (x + intel_crtc->cursor_width <= 0)
8223 base = 0;
8224
8225 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8226 x = -x;
8227 }
8228 pos |= x << CURSOR_X_SHIFT;
8229
8230 if (y < 0) {
8231 if (y + intel_crtc->cursor_height <= 0)
8232 base = 0;
8233
8234 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8235 y = -y;
8236 }
8237 pos |= y << CURSOR_Y_SHIFT;
8238
8239 if (base == 0 && intel_crtc->cursor_base == 0)
8240 return;
8241
8242 I915_WRITE(CURPOS(pipe), pos);
8243
8244 if (IS_845G(dev) || IS_I865G(dev))
8245 i845_update_cursor(crtc, base);
8246 else
8247 i9xx_update_cursor(crtc, base);
8248 intel_crtc->cursor_base = base;
8249 }
8250
8251 static bool cursor_size_ok(struct drm_device *dev,
8252 uint32_t width, uint32_t height)
8253 {
8254 if (width == 0 || height == 0)
8255 return false;
8256
8257 /*
8258 * 845g/865g are special in that they are only limited by
8259 * the width of their cursors, the height is arbitrary up to
8260 * the precision of the register. Everything else requires
8261 * square cursors, limited to a few power-of-two sizes.
8262 */
8263 if (IS_845G(dev) || IS_I865G(dev)) {
8264 if ((width & 63) != 0)
8265 return false;
8266
8267 if (width > (IS_845G(dev) ? 64 : 512))
8268 return false;
8269
8270 if (height > 1023)
8271 return false;
8272 } else {
8273 switch (width | height) {
8274 case 256:
8275 case 128:
8276 if (IS_GEN2(dev))
8277 return false;
8278 case 64:
8279 break;
8280 default:
8281 return false;
8282 }
8283 }
8284
8285 return true;
8286 }
8287
8288 /*
8289 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8290 *
8291 * Note that the object's reference will be consumed if the update fails. If
8292 * the update succeeds, the reference of the old object (if any) will be
8293 * consumed.
8294 */
8295 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8296 struct drm_i915_gem_object *obj,
8297 uint32_t width, uint32_t height)
8298 {
8299 struct drm_device *dev = crtc->dev;
8300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8301 enum pipe pipe = intel_crtc->pipe;
8302 unsigned old_width, stride;
8303 uint32_t addr;
8304 int ret;
8305
8306 /* if we want to turn off the cursor ignore width and height */
8307 if (!obj) {
8308 DRM_DEBUG_KMS("cursor off\n");
8309 addr = 0;
8310 obj = NULL;
8311 mutex_lock(&dev->struct_mutex);
8312 goto finish;
8313 }
8314
8315 /* Check for which cursor types we support */
8316 if (!cursor_size_ok(dev, width, height)) {
8317 DRM_DEBUG("Cursor dimension not supported\n");
8318 return -EINVAL;
8319 }
8320
8321 stride = roundup_pow_of_two(width) * 4;
8322 if (obj->base.size < stride * height) {
8323 DRM_DEBUG_KMS("buffer is too small\n");
8324 ret = -ENOMEM;
8325 goto fail;
8326 }
8327
8328 /* we only need to pin inside GTT if cursor is non-phy */
8329 mutex_lock(&dev->struct_mutex);
8330 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8331 unsigned alignment;
8332
8333 if (obj->tiling_mode) {
8334 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8335 ret = -EINVAL;
8336 goto fail_locked;
8337 }
8338
8339 /* Note that the w/a also requires 2 PTE of padding following
8340 * the bo. We currently fill all unused PTE with the shadow
8341 * page and so we should always have valid PTE following the
8342 * cursor preventing the VT-d warning.
8343 */
8344 alignment = 0;
8345 if (need_vtd_wa(dev))
8346 alignment = 64*1024;
8347
8348 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8349 if (ret) {
8350 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8351 goto fail_locked;
8352 }
8353
8354 ret = i915_gem_object_put_fence(obj);
8355 if (ret) {
8356 DRM_DEBUG_KMS("failed to release fence for cursor");
8357 goto fail_unpin;
8358 }
8359
8360 addr = i915_gem_obj_ggtt_offset(obj);
8361 } else {
8362 int align = IS_I830(dev) ? 16 * 1024 : 256;
8363 ret = i915_gem_object_attach_phys(obj, align);
8364 if (ret) {
8365 DRM_DEBUG_KMS("failed to attach phys object\n");
8366 goto fail_locked;
8367 }
8368 addr = obj->phys_handle->busaddr;
8369 }
8370
8371 finish:
8372 if (intel_crtc->cursor_bo) {
8373 if (!INTEL_INFO(dev)->cursor_needs_physical)
8374 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8375 }
8376
8377 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8378 INTEL_FRONTBUFFER_CURSOR(pipe));
8379 mutex_unlock(&dev->struct_mutex);
8380
8381 old_width = intel_crtc->cursor_width;
8382
8383 intel_crtc->cursor_addr = addr;
8384 intel_crtc->cursor_bo = obj;
8385 intel_crtc->cursor_width = width;
8386 intel_crtc->cursor_height = height;
8387
8388 if (intel_crtc->active) {
8389 if (old_width != width)
8390 intel_update_watermarks(crtc);
8391 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8392 }
8393
8394 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8395
8396 return 0;
8397 fail_unpin:
8398 i915_gem_object_unpin_from_display_plane(obj);
8399 fail_locked:
8400 mutex_unlock(&dev->struct_mutex);
8401 fail:
8402 drm_gem_object_unreference_unlocked(&obj->base);
8403 return ret;
8404 }
8405
8406 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8407 u16 *blue, uint32_t start, uint32_t size)
8408 {
8409 int end = (start + size > 256) ? 256 : start + size, i;
8410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8411
8412 for (i = start; i < end; i++) {
8413 intel_crtc->lut_r[i] = red[i] >> 8;
8414 intel_crtc->lut_g[i] = green[i] >> 8;
8415 intel_crtc->lut_b[i] = blue[i] >> 8;
8416 }
8417
8418 intel_crtc_load_lut(crtc);
8419 }
8420
8421 /* VESA 640x480x72Hz mode to set on the pipe */
8422 static struct drm_display_mode load_detect_mode = {
8423 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8424 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8425 };
8426
8427 struct drm_framebuffer *
8428 __intel_framebuffer_create(struct drm_device *dev,
8429 struct drm_mode_fb_cmd2 *mode_cmd,
8430 struct drm_i915_gem_object *obj)
8431 {
8432 struct intel_framebuffer *intel_fb;
8433 int ret;
8434
8435 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8436 if (!intel_fb) {
8437 drm_gem_object_unreference_unlocked(&obj->base);
8438 return ERR_PTR(-ENOMEM);
8439 }
8440
8441 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8442 if (ret)
8443 goto err;
8444
8445 return &intel_fb->base;
8446 err:
8447 drm_gem_object_unreference_unlocked(&obj->base);
8448 kfree(intel_fb);
8449
8450 return ERR_PTR(ret);
8451 }
8452
8453 static struct drm_framebuffer *
8454 intel_framebuffer_create(struct drm_device *dev,
8455 struct drm_mode_fb_cmd2 *mode_cmd,
8456 struct drm_i915_gem_object *obj)
8457 {
8458 struct drm_framebuffer *fb;
8459 int ret;
8460
8461 ret = i915_mutex_lock_interruptible(dev);
8462 if (ret)
8463 return ERR_PTR(ret);
8464 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8465 mutex_unlock(&dev->struct_mutex);
8466
8467 return fb;
8468 }
8469
8470 static u32
8471 intel_framebuffer_pitch_for_width(int width, int bpp)
8472 {
8473 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8474 return ALIGN(pitch, 64);
8475 }
8476
8477 static u32
8478 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8479 {
8480 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8481 return PAGE_ALIGN(pitch * mode->vdisplay);
8482 }
8483
8484 static struct drm_framebuffer *
8485 intel_framebuffer_create_for_mode(struct drm_device *dev,
8486 struct drm_display_mode *mode,
8487 int depth, int bpp)
8488 {
8489 struct drm_i915_gem_object *obj;
8490 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8491
8492 obj = i915_gem_alloc_object(dev,
8493 intel_framebuffer_size_for_mode(mode, bpp));
8494 if (obj == NULL)
8495 return ERR_PTR(-ENOMEM);
8496
8497 mode_cmd.width = mode->hdisplay;
8498 mode_cmd.height = mode->vdisplay;
8499 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8500 bpp);
8501 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8502
8503 return intel_framebuffer_create(dev, &mode_cmd, obj);
8504 }
8505
8506 static struct drm_framebuffer *
8507 mode_fits_in_fbdev(struct drm_device *dev,
8508 struct drm_display_mode *mode)
8509 {
8510 #ifdef CONFIG_DRM_I915_FBDEV
8511 struct drm_i915_private *dev_priv = dev->dev_private;
8512 struct drm_i915_gem_object *obj;
8513 struct drm_framebuffer *fb;
8514
8515 if (!dev_priv->fbdev)
8516 return NULL;
8517
8518 if (!dev_priv->fbdev->fb)
8519 return NULL;
8520
8521 obj = dev_priv->fbdev->fb->obj;
8522 BUG_ON(!obj);
8523
8524 fb = &dev_priv->fbdev->fb->base;
8525 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8526 fb->bits_per_pixel))
8527 return NULL;
8528
8529 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8530 return NULL;
8531
8532 return fb;
8533 #else
8534 return NULL;
8535 #endif
8536 }
8537
8538 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8539 struct drm_display_mode *mode,
8540 struct intel_load_detect_pipe *old,
8541 struct drm_modeset_acquire_ctx *ctx)
8542 {
8543 struct intel_crtc *intel_crtc;
8544 struct intel_encoder *intel_encoder =
8545 intel_attached_encoder(connector);
8546 struct drm_crtc *possible_crtc;
8547 struct drm_encoder *encoder = &intel_encoder->base;
8548 struct drm_crtc *crtc = NULL;
8549 struct drm_device *dev = encoder->dev;
8550 struct drm_framebuffer *fb;
8551 struct drm_mode_config *config = &dev->mode_config;
8552 int ret, i = -1;
8553
8554 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8555 connector->base.id, connector->name,
8556 encoder->base.id, encoder->name);
8557
8558 retry:
8559 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8560 if (ret)
8561 goto fail_unlock;
8562
8563 /*
8564 * Algorithm gets a little messy:
8565 *
8566 * - if the connector already has an assigned crtc, use it (but make
8567 * sure it's on first)
8568 *
8569 * - try to find the first unused crtc that can drive this connector,
8570 * and use that if we find one
8571 */
8572
8573 /* See if we already have a CRTC for this connector */
8574 if (encoder->crtc) {
8575 crtc = encoder->crtc;
8576
8577 ret = drm_modeset_lock(&crtc->mutex, ctx);
8578 if (ret)
8579 goto fail_unlock;
8580
8581 old->dpms_mode = connector->dpms;
8582 old->load_detect_temp = false;
8583
8584 /* Make sure the crtc and connector are running */
8585 if (connector->dpms != DRM_MODE_DPMS_ON)
8586 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8587
8588 return true;
8589 }
8590
8591 /* Find an unused one (if possible) */
8592 for_each_crtc(dev, possible_crtc) {
8593 i++;
8594 if (!(encoder->possible_crtcs & (1 << i)))
8595 continue;
8596 if (possible_crtc->enabled)
8597 continue;
8598 /* This can occur when applying the pipe A quirk on resume. */
8599 if (to_intel_crtc(possible_crtc)->new_enabled)
8600 continue;
8601
8602 crtc = possible_crtc;
8603 break;
8604 }
8605
8606 /*
8607 * If we didn't find an unused CRTC, don't use any.
8608 */
8609 if (!crtc) {
8610 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8611 goto fail_unlock;
8612 }
8613
8614 ret = drm_modeset_lock(&crtc->mutex, ctx);
8615 if (ret)
8616 goto fail_unlock;
8617 intel_encoder->new_crtc = to_intel_crtc(crtc);
8618 to_intel_connector(connector)->new_encoder = intel_encoder;
8619
8620 intel_crtc = to_intel_crtc(crtc);
8621 intel_crtc->new_enabled = true;
8622 intel_crtc->new_config = &intel_crtc->config;
8623 old->dpms_mode = connector->dpms;
8624 old->load_detect_temp = true;
8625 old->release_fb = NULL;
8626
8627 if (!mode)
8628 mode = &load_detect_mode;
8629
8630 /* We need a framebuffer large enough to accommodate all accesses
8631 * that the plane may generate whilst we perform load detection.
8632 * We can not rely on the fbcon either being present (we get called
8633 * during its initialisation to detect all boot displays, or it may
8634 * not even exist) or that it is large enough to satisfy the
8635 * requested mode.
8636 */
8637 fb = mode_fits_in_fbdev(dev, mode);
8638 if (fb == NULL) {
8639 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8640 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8641 old->release_fb = fb;
8642 } else
8643 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8644 if (IS_ERR(fb)) {
8645 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8646 goto fail;
8647 }
8648
8649 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8650 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8651 if (old->release_fb)
8652 old->release_fb->funcs->destroy(old->release_fb);
8653 goto fail;
8654 }
8655
8656 /* let the connector get through one full cycle before testing */
8657 intel_wait_for_vblank(dev, intel_crtc->pipe);
8658 return true;
8659
8660 fail:
8661 intel_crtc->new_enabled = crtc->enabled;
8662 if (intel_crtc->new_enabled)
8663 intel_crtc->new_config = &intel_crtc->config;
8664 else
8665 intel_crtc->new_config = NULL;
8666 fail_unlock:
8667 if (ret == -EDEADLK) {
8668 drm_modeset_backoff(ctx);
8669 goto retry;
8670 }
8671
8672 return false;
8673 }
8674
8675 void intel_release_load_detect_pipe(struct drm_connector *connector,
8676 struct intel_load_detect_pipe *old)
8677 {
8678 struct intel_encoder *intel_encoder =
8679 intel_attached_encoder(connector);
8680 struct drm_encoder *encoder = &intel_encoder->base;
8681 struct drm_crtc *crtc = encoder->crtc;
8682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8683
8684 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8685 connector->base.id, connector->name,
8686 encoder->base.id, encoder->name);
8687
8688 if (old->load_detect_temp) {
8689 to_intel_connector(connector)->new_encoder = NULL;
8690 intel_encoder->new_crtc = NULL;
8691 intel_crtc->new_enabled = false;
8692 intel_crtc->new_config = NULL;
8693 intel_set_mode(crtc, NULL, 0, 0, NULL);
8694
8695 if (old->release_fb) {
8696 drm_framebuffer_unregister_private(old->release_fb);
8697 drm_framebuffer_unreference(old->release_fb);
8698 }
8699
8700 return;
8701 }
8702
8703 /* Switch crtc and encoder back off if necessary */
8704 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8705 connector->funcs->dpms(connector, old->dpms_mode);
8706 }
8707
8708 static int i9xx_pll_refclk(struct drm_device *dev,
8709 const struct intel_crtc_config *pipe_config)
8710 {
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712 u32 dpll = pipe_config->dpll_hw_state.dpll;
8713
8714 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8715 return dev_priv->vbt.lvds_ssc_freq;
8716 else if (HAS_PCH_SPLIT(dev))
8717 return 120000;
8718 else if (!IS_GEN2(dev))
8719 return 96000;
8720 else
8721 return 48000;
8722 }
8723
8724 /* Returns the clock of the currently programmed mode of the given pipe. */
8725 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8726 struct intel_crtc_config *pipe_config)
8727 {
8728 struct drm_device *dev = crtc->base.dev;
8729 struct drm_i915_private *dev_priv = dev->dev_private;
8730 int pipe = pipe_config->cpu_transcoder;
8731 u32 dpll = pipe_config->dpll_hw_state.dpll;
8732 u32 fp;
8733 intel_clock_t clock;
8734 int refclk = i9xx_pll_refclk(dev, pipe_config);
8735
8736 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8737 fp = pipe_config->dpll_hw_state.fp0;
8738 else
8739 fp = pipe_config->dpll_hw_state.fp1;
8740
8741 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8742 if (IS_PINEVIEW(dev)) {
8743 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8744 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8745 } else {
8746 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8747 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8748 }
8749
8750 if (!IS_GEN2(dev)) {
8751 if (IS_PINEVIEW(dev))
8752 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8753 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8754 else
8755 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8756 DPLL_FPA01_P1_POST_DIV_SHIFT);
8757
8758 switch (dpll & DPLL_MODE_MASK) {
8759 case DPLLB_MODE_DAC_SERIAL:
8760 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8761 5 : 10;
8762 break;
8763 case DPLLB_MODE_LVDS:
8764 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8765 7 : 14;
8766 break;
8767 default:
8768 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8769 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8770 return;
8771 }
8772
8773 if (IS_PINEVIEW(dev))
8774 pineview_clock(refclk, &clock);
8775 else
8776 i9xx_clock(refclk, &clock);
8777 } else {
8778 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8779 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8780
8781 if (is_lvds) {
8782 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8783 DPLL_FPA01_P1_POST_DIV_SHIFT);
8784
8785 if (lvds & LVDS_CLKB_POWER_UP)
8786 clock.p2 = 7;
8787 else
8788 clock.p2 = 14;
8789 } else {
8790 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8791 clock.p1 = 2;
8792 else {
8793 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8794 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8795 }
8796 if (dpll & PLL_P2_DIVIDE_BY_4)
8797 clock.p2 = 4;
8798 else
8799 clock.p2 = 2;
8800 }
8801
8802 i9xx_clock(refclk, &clock);
8803 }
8804
8805 /*
8806 * This value includes pixel_multiplier. We will use
8807 * port_clock to compute adjusted_mode.crtc_clock in the
8808 * encoder's get_config() function.
8809 */
8810 pipe_config->port_clock = clock.dot;
8811 }
8812
8813 int intel_dotclock_calculate(int link_freq,
8814 const struct intel_link_m_n *m_n)
8815 {
8816 /*
8817 * The calculation for the data clock is:
8818 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8819 * But we want to avoid losing precison if possible, so:
8820 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8821 *
8822 * and the link clock is simpler:
8823 * link_clock = (m * link_clock) / n
8824 */
8825
8826 if (!m_n->link_n)
8827 return 0;
8828
8829 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8830 }
8831
8832 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8833 struct intel_crtc_config *pipe_config)
8834 {
8835 struct drm_device *dev = crtc->base.dev;
8836
8837 /* read out port_clock from the DPLL */
8838 i9xx_crtc_clock_get(crtc, pipe_config);
8839
8840 /*
8841 * This value does not include pixel_multiplier.
8842 * We will check that port_clock and adjusted_mode.crtc_clock
8843 * agree once we know their relationship in the encoder's
8844 * get_config() function.
8845 */
8846 pipe_config->adjusted_mode.crtc_clock =
8847 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8848 &pipe_config->fdi_m_n);
8849 }
8850
8851 /** Returns the currently programmed mode of the given pipe. */
8852 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8853 struct drm_crtc *crtc)
8854 {
8855 struct drm_i915_private *dev_priv = dev->dev_private;
8856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8857 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8858 struct drm_display_mode *mode;
8859 struct intel_crtc_config pipe_config;
8860 int htot = I915_READ(HTOTAL(cpu_transcoder));
8861 int hsync = I915_READ(HSYNC(cpu_transcoder));
8862 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8863 int vsync = I915_READ(VSYNC(cpu_transcoder));
8864 enum pipe pipe = intel_crtc->pipe;
8865
8866 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8867 if (!mode)
8868 return NULL;
8869
8870 /*
8871 * Construct a pipe_config sufficient for getting the clock info
8872 * back out of crtc_clock_get.
8873 *
8874 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8875 * to use a real value here instead.
8876 */
8877 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8878 pipe_config.pixel_multiplier = 1;
8879 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8880 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8881 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8882 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8883
8884 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8885 mode->hdisplay = (htot & 0xffff) + 1;
8886 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8887 mode->hsync_start = (hsync & 0xffff) + 1;
8888 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8889 mode->vdisplay = (vtot & 0xffff) + 1;
8890 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8891 mode->vsync_start = (vsync & 0xffff) + 1;
8892 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8893
8894 drm_mode_set_name(mode);
8895
8896 return mode;
8897 }
8898
8899 static void intel_increase_pllclock(struct drm_device *dev,
8900 enum pipe pipe)
8901 {
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903 int dpll_reg = DPLL(pipe);
8904 int dpll;
8905
8906 if (!HAS_GMCH_DISPLAY(dev))
8907 return;
8908
8909 if (!dev_priv->lvds_downclock_avail)
8910 return;
8911
8912 dpll = I915_READ(dpll_reg);
8913 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8914 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8915
8916 assert_panel_unlocked(dev_priv, pipe);
8917
8918 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8919 I915_WRITE(dpll_reg, dpll);
8920 intel_wait_for_vblank(dev, pipe);
8921
8922 dpll = I915_READ(dpll_reg);
8923 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8924 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8925 }
8926 }
8927
8928 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8929 {
8930 struct drm_device *dev = crtc->dev;
8931 struct drm_i915_private *dev_priv = dev->dev_private;
8932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8933
8934 if (!HAS_GMCH_DISPLAY(dev))
8935 return;
8936
8937 if (!dev_priv->lvds_downclock_avail)
8938 return;
8939
8940 /*
8941 * Since this is called by a timer, we should never get here in
8942 * the manual case.
8943 */
8944 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8945 int pipe = intel_crtc->pipe;
8946 int dpll_reg = DPLL(pipe);
8947 int dpll;
8948
8949 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8950
8951 assert_panel_unlocked(dev_priv, pipe);
8952
8953 dpll = I915_READ(dpll_reg);
8954 dpll |= DISPLAY_RATE_SELECT_FPA1;
8955 I915_WRITE(dpll_reg, dpll);
8956 intel_wait_for_vblank(dev, pipe);
8957 dpll = I915_READ(dpll_reg);
8958 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8959 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8960 }
8961
8962 }
8963
8964 void intel_mark_busy(struct drm_device *dev)
8965 {
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967
8968 if (dev_priv->mm.busy)
8969 return;
8970
8971 intel_runtime_pm_get(dev_priv);
8972 i915_update_gfx_val(dev_priv);
8973 dev_priv->mm.busy = true;
8974 }
8975
8976 void intel_mark_idle(struct drm_device *dev)
8977 {
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 struct drm_crtc *crtc;
8980
8981 if (!dev_priv->mm.busy)
8982 return;
8983
8984 dev_priv->mm.busy = false;
8985
8986 if (!i915.powersave)
8987 goto out;
8988
8989 for_each_crtc(dev, crtc) {
8990 if (!crtc->primary->fb)
8991 continue;
8992
8993 intel_decrease_pllclock(crtc);
8994 }
8995
8996 if (INTEL_INFO(dev)->gen >= 6)
8997 gen6_rps_idle(dev->dev_private);
8998
8999 out:
9000 intel_runtime_pm_put(dev_priv);
9001 }
9002
9003
9004 /**
9005 * intel_mark_fb_busy - mark given planes as busy
9006 * @dev: DRM device
9007 * @frontbuffer_bits: bits for the affected planes
9008 * @ring: optional ring for asynchronous commands
9009 *
9010 * This function gets called every time the screen contents change. It can be
9011 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9012 */
9013 static void intel_mark_fb_busy(struct drm_device *dev,
9014 unsigned frontbuffer_bits,
9015 struct intel_engine_cs *ring)
9016 {
9017 struct drm_i915_private *dev_priv = dev->dev_private;
9018 enum pipe pipe;
9019
9020 if (!i915.powersave)
9021 return;
9022
9023 for_each_pipe(dev_priv, pipe) {
9024 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
9025 continue;
9026
9027 intel_increase_pllclock(dev, pipe);
9028 if (ring && intel_fbc_enabled(dev))
9029 ring->fbc_dirty = true;
9030 }
9031 }
9032
9033 /**
9034 * intel_fb_obj_invalidate - invalidate frontbuffer object
9035 * @obj: GEM object to invalidate
9036 * @ring: set for asynchronous rendering
9037 *
9038 * This function gets called every time rendering on the given object starts and
9039 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9040 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9041 * until the rendering completes or a flip on this frontbuffer plane is
9042 * scheduled.
9043 */
9044 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
9045 struct intel_engine_cs *ring)
9046 {
9047 struct drm_device *dev = obj->base.dev;
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049
9050 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9051
9052 if (!obj->frontbuffer_bits)
9053 return;
9054
9055 if (ring) {
9056 mutex_lock(&dev_priv->fb_tracking.lock);
9057 dev_priv->fb_tracking.busy_bits
9058 |= obj->frontbuffer_bits;
9059 dev_priv->fb_tracking.flip_bits
9060 &= ~obj->frontbuffer_bits;
9061 mutex_unlock(&dev_priv->fb_tracking.lock);
9062 }
9063
9064 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
9065
9066 intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
9067 }
9068
9069 /**
9070 * intel_frontbuffer_flush - flush frontbuffer
9071 * @dev: DRM device
9072 * @frontbuffer_bits: frontbuffer plane tracking bits
9073 *
9074 * This function gets called every time rendering on the given planes has
9075 * completed and frontbuffer caching can be started again. Flushes will get
9076 * delayed if they're blocked by some oustanding asynchronous rendering.
9077 *
9078 * Can be called without any locks held.
9079 */
9080 void intel_frontbuffer_flush(struct drm_device *dev,
9081 unsigned frontbuffer_bits)
9082 {
9083 struct drm_i915_private *dev_priv = dev->dev_private;
9084
9085 /* Delay flushing when rings are still busy.*/
9086 mutex_lock(&dev_priv->fb_tracking.lock);
9087 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
9088 mutex_unlock(&dev_priv->fb_tracking.lock);
9089
9090 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
9091
9092 intel_edp_psr_flush(dev, frontbuffer_bits);
9093
9094 if (IS_GEN8(dev))
9095 gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN);
9096 }
9097
9098 /**
9099 * intel_fb_obj_flush - flush frontbuffer object
9100 * @obj: GEM object to flush
9101 * @retire: set when retiring asynchronous rendering
9102 *
9103 * This function gets called every time rendering on the given object has
9104 * completed and frontbuffer caching can be started again. If @retire is true
9105 * then any delayed flushes will be unblocked.
9106 */
9107 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
9108 bool retire)
9109 {
9110 struct drm_device *dev = obj->base.dev;
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 unsigned frontbuffer_bits;
9113
9114 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
9115
9116 if (!obj->frontbuffer_bits)
9117 return;
9118
9119 frontbuffer_bits = obj->frontbuffer_bits;
9120
9121 if (retire) {
9122 mutex_lock(&dev_priv->fb_tracking.lock);
9123 /* Filter out new bits since rendering started. */
9124 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
9125
9126 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
9127 mutex_unlock(&dev_priv->fb_tracking.lock);
9128 }
9129
9130 intel_frontbuffer_flush(dev, frontbuffer_bits);
9131 }
9132
9133 /**
9134 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9135 * @dev: DRM device
9136 * @frontbuffer_bits: frontbuffer plane tracking bits
9137 *
9138 * This function gets called after scheduling a flip on @obj. The actual
9139 * frontbuffer flushing will be delayed until completion is signalled with
9140 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9141 * flush will be cancelled.
9142 *
9143 * Can be called without any locks held.
9144 */
9145 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9146 unsigned frontbuffer_bits)
9147 {
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149
9150 mutex_lock(&dev_priv->fb_tracking.lock);
9151 dev_priv->fb_tracking.flip_bits
9152 |= frontbuffer_bits;
9153 mutex_unlock(&dev_priv->fb_tracking.lock);
9154 }
9155
9156 /**
9157 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9158 * @dev: DRM device
9159 * @frontbuffer_bits: frontbuffer plane tracking bits
9160 *
9161 * This function gets called after the flip has been latched and will complete
9162 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9163 *
9164 * Can be called without any locks held.
9165 */
9166 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9167 unsigned frontbuffer_bits)
9168 {
9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170
9171 mutex_lock(&dev_priv->fb_tracking.lock);
9172 /* Mask any cancelled flips. */
9173 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9174 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9175 mutex_unlock(&dev_priv->fb_tracking.lock);
9176
9177 intel_frontbuffer_flush(dev, frontbuffer_bits);
9178 }
9179
9180 static void intel_crtc_destroy(struct drm_crtc *crtc)
9181 {
9182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9183 struct drm_device *dev = crtc->dev;
9184 struct intel_unpin_work *work;
9185 unsigned long flags;
9186
9187 spin_lock_irqsave(&dev->event_lock, flags);
9188 work = intel_crtc->unpin_work;
9189 intel_crtc->unpin_work = NULL;
9190 spin_unlock_irqrestore(&dev->event_lock, flags);
9191
9192 if (work) {
9193 cancel_work_sync(&work->work);
9194 kfree(work);
9195 }
9196
9197 drm_crtc_cleanup(crtc);
9198
9199 kfree(intel_crtc);
9200 }
9201
9202 static void intel_unpin_work_fn(struct work_struct *__work)
9203 {
9204 struct intel_unpin_work *work =
9205 container_of(__work, struct intel_unpin_work, work);
9206 struct drm_device *dev = work->crtc->dev;
9207 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9208
9209 mutex_lock(&dev->struct_mutex);
9210 intel_unpin_fb_obj(work->old_fb_obj);
9211 drm_gem_object_unreference(&work->pending_flip_obj->base);
9212 drm_gem_object_unreference(&work->old_fb_obj->base);
9213
9214 intel_update_fbc(dev);
9215 mutex_unlock(&dev->struct_mutex);
9216
9217 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9218
9219 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9220 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9221
9222 kfree(work);
9223 }
9224
9225 static void do_intel_finish_page_flip(struct drm_device *dev,
9226 struct drm_crtc *crtc)
9227 {
9228 struct drm_i915_private *dev_priv = dev->dev_private;
9229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9230 struct intel_unpin_work *work;
9231 unsigned long flags;
9232
9233 /* Ignore early vblank irqs */
9234 if (intel_crtc == NULL)
9235 return;
9236
9237 spin_lock_irqsave(&dev->event_lock, flags);
9238 work = intel_crtc->unpin_work;
9239
9240 /* Ensure we don't miss a work->pending update ... */
9241 smp_rmb();
9242
9243 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9244 spin_unlock_irqrestore(&dev->event_lock, flags);
9245 return;
9246 }
9247
9248 /* and that the unpin work is consistent wrt ->pending. */
9249 smp_rmb();
9250
9251 intel_crtc->unpin_work = NULL;
9252
9253 if (work->event)
9254 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9255
9256 drm_crtc_vblank_put(crtc);
9257
9258 spin_unlock_irqrestore(&dev->event_lock, flags);
9259
9260 wake_up_all(&dev_priv->pending_flip_queue);
9261
9262 queue_work(dev_priv->wq, &work->work);
9263
9264 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9265 }
9266
9267 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9268 {
9269 struct drm_i915_private *dev_priv = dev->dev_private;
9270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9271
9272 do_intel_finish_page_flip(dev, crtc);
9273 }
9274
9275 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9276 {
9277 struct drm_i915_private *dev_priv = dev->dev_private;
9278 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9279
9280 do_intel_finish_page_flip(dev, crtc);
9281 }
9282
9283 /* Is 'a' after or equal to 'b'? */
9284 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9285 {
9286 return !((a - b) & 0x80000000);
9287 }
9288
9289 static bool page_flip_finished(struct intel_crtc *crtc)
9290 {
9291 struct drm_device *dev = crtc->base.dev;
9292 struct drm_i915_private *dev_priv = dev->dev_private;
9293
9294 /*
9295 * The relevant registers doen't exist on pre-ctg.
9296 * As the flip done interrupt doesn't trigger for mmio
9297 * flips on gmch platforms, a flip count check isn't
9298 * really needed there. But since ctg has the registers,
9299 * include it in the check anyway.
9300 */
9301 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9302 return true;
9303
9304 /*
9305 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9306 * used the same base address. In that case the mmio flip might
9307 * have completed, but the CS hasn't even executed the flip yet.
9308 *
9309 * A flip count check isn't enough as the CS might have updated
9310 * the base address just after start of vblank, but before we
9311 * managed to process the interrupt. This means we'd complete the
9312 * CS flip too soon.
9313 *
9314 * Combining both checks should get us a good enough result. It may
9315 * still happen that the CS flip has been executed, but has not
9316 * yet actually completed. But in case the base address is the same
9317 * anyway, we don't really care.
9318 */
9319 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9320 crtc->unpin_work->gtt_offset &&
9321 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9322 crtc->unpin_work->flip_count);
9323 }
9324
9325 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9326 {
9327 struct drm_i915_private *dev_priv = dev->dev_private;
9328 struct intel_crtc *intel_crtc =
9329 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9330 unsigned long flags;
9331
9332 /* NB: An MMIO update of the plane base pointer will also
9333 * generate a page-flip completion irq, i.e. every modeset
9334 * is also accompanied by a spurious intel_prepare_page_flip().
9335 */
9336 spin_lock_irqsave(&dev->event_lock, flags);
9337 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9338 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9339 spin_unlock_irqrestore(&dev->event_lock, flags);
9340 }
9341
9342 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9343 {
9344 /* Ensure that the work item is consistent when activating it ... */
9345 smp_wmb();
9346 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9347 /* and that it is marked active as soon as the irq could fire. */
9348 smp_wmb();
9349 }
9350
9351 static int intel_gen2_queue_flip(struct drm_device *dev,
9352 struct drm_crtc *crtc,
9353 struct drm_framebuffer *fb,
9354 struct drm_i915_gem_object *obj,
9355 struct intel_engine_cs *ring,
9356 uint32_t flags)
9357 {
9358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9359 u32 flip_mask;
9360 int ret;
9361
9362 ret = intel_ring_begin(ring, 6);
9363 if (ret)
9364 return ret;
9365
9366 /* Can't queue multiple flips, so wait for the previous
9367 * one to finish before executing the next.
9368 */
9369 if (intel_crtc->plane)
9370 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9371 else
9372 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9373 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9374 intel_ring_emit(ring, MI_NOOP);
9375 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9377 intel_ring_emit(ring, fb->pitches[0]);
9378 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9379 intel_ring_emit(ring, 0); /* aux display base address, unused */
9380
9381 intel_mark_page_flip_active(intel_crtc);
9382 __intel_ring_advance(ring);
9383 return 0;
9384 }
9385
9386 static int intel_gen3_queue_flip(struct drm_device *dev,
9387 struct drm_crtc *crtc,
9388 struct drm_framebuffer *fb,
9389 struct drm_i915_gem_object *obj,
9390 struct intel_engine_cs *ring,
9391 uint32_t flags)
9392 {
9393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9394 u32 flip_mask;
9395 int ret;
9396
9397 ret = intel_ring_begin(ring, 6);
9398 if (ret)
9399 return ret;
9400
9401 if (intel_crtc->plane)
9402 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9403 else
9404 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9405 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9406 intel_ring_emit(ring, MI_NOOP);
9407 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9408 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9409 intel_ring_emit(ring, fb->pitches[0]);
9410 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9411 intel_ring_emit(ring, MI_NOOP);
9412
9413 intel_mark_page_flip_active(intel_crtc);
9414 __intel_ring_advance(ring);
9415 return 0;
9416 }
9417
9418 static int intel_gen4_queue_flip(struct drm_device *dev,
9419 struct drm_crtc *crtc,
9420 struct drm_framebuffer *fb,
9421 struct drm_i915_gem_object *obj,
9422 struct intel_engine_cs *ring,
9423 uint32_t flags)
9424 {
9425 struct drm_i915_private *dev_priv = dev->dev_private;
9426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9427 uint32_t pf, pipesrc;
9428 int ret;
9429
9430 ret = intel_ring_begin(ring, 4);
9431 if (ret)
9432 return ret;
9433
9434 /* i965+ uses the linear or tiled offsets from the
9435 * Display Registers (which do not change across a page-flip)
9436 * so we need only reprogram the base address.
9437 */
9438 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9439 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9440 intel_ring_emit(ring, fb->pitches[0]);
9441 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9442 obj->tiling_mode);
9443
9444 /* XXX Enabling the panel-fitter across page-flip is so far
9445 * untested on non-native modes, so ignore it for now.
9446 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9447 */
9448 pf = 0;
9449 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9450 intel_ring_emit(ring, pf | pipesrc);
9451
9452 intel_mark_page_flip_active(intel_crtc);
9453 __intel_ring_advance(ring);
9454 return 0;
9455 }
9456
9457 static int intel_gen6_queue_flip(struct drm_device *dev,
9458 struct drm_crtc *crtc,
9459 struct drm_framebuffer *fb,
9460 struct drm_i915_gem_object *obj,
9461 struct intel_engine_cs *ring,
9462 uint32_t flags)
9463 {
9464 struct drm_i915_private *dev_priv = dev->dev_private;
9465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9466 uint32_t pf, pipesrc;
9467 int ret;
9468
9469 ret = intel_ring_begin(ring, 4);
9470 if (ret)
9471 return ret;
9472
9473 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9474 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9475 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9476 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9477
9478 /* Contrary to the suggestions in the documentation,
9479 * "Enable Panel Fitter" does not seem to be required when page
9480 * flipping with a non-native mode, and worse causes a normal
9481 * modeset to fail.
9482 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9483 */
9484 pf = 0;
9485 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9486 intel_ring_emit(ring, pf | pipesrc);
9487
9488 intel_mark_page_flip_active(intel_crtc);
9489 __intel_ring_advance(ring);
9490 return 0;
9491 }
9492
9493 static int intel_gen7_queue_flip(struct drm_device *dev,
9494 struct drm_crtc *crtc,
9495 struct drm_framebuffer *fb,
9496 struct drm_i915_gem_object *obj,
9497 struct intel_engine_cs *ring,
9498 uint32_t flags)
9499 {
9500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9501 uint32_t plane_bit = 0;
9502 int len, ret;
9503
9504 switch (intel_crtc->plane) {
9505 case PLANE_A:
9506 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9507 break;
9508 case PLANE_B:
9509 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9510 break;
9511 case PLANE_C:
9512 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9513 break;
9514 default:
9515 WARN_ONCE(1, "unknown plane in flip command\n");
9516 return -ENODEV;
9517 }
9518
9519 len = 4;
9520 if (ring->id == RCS) {
9521 len += 6;
9522 /*
9523 * On Gen 8, SRM is now taking an extra dword to accommodate
9524 * 48bits addresses, and we need a NOOP for the batch size to
9525 * stay even.
9526 */
9527 if (IS_GEN8(dev))
9528 len += 2;
9529 }
9530
9531 /*
9532 * BSpec MI_DISPLAY_FLIP for IVB:
9533 * "The full packet must be contained within the same cache line."
9534 *
9535 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9536 * cacheline, if we ever start emitting more commands before
9537 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9538 * then do the cacheline alignment, and finally emit the
9539 * MI_DISPLAY_FLIP.
9540 */
9541 ret = intel_ring_cacheline_align(ring);
9542 if (ret)
9543 return ret;
9544
9545 ret = intel_ring_begin(ring, len);
9546 if (ret)
9547 return ret;
9548
9549 /* Unmask the flip-done completion message. Note that the bspec says that
9550 * we should do this for both the BCS and RCS, and that we must not unmask
9551 * more than one flip event at any time (or ensure that one flip message
9552 * can be sent by waiting for flip-done prior to queueing new flips).
9553 * Experimentation says that BCS works despite DERRMR masking all
9554 * flip-done completion events and that unmasking all planes at once
9555 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9556 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9557 */
9558 if (ring->id == RCS) {
9559 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9560 intel_ring_emit(ring, DERRMR);
9561 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9562 DERRMR_PIPEB_PRI_FLIP_DONE |
9563 DERRMR_PIPEC_PRI_FLIP_DONE));
9564 if (IS_GEN8(dev))
9565 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9566 MI_SRM_LRM_GLOBAL_GTT);
9567 else
9568 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9569 MI_SRM_LRM_GLOBAL_GTT);
9570 intel_ring_emit(ring, DERRMR);
9571 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9572 if (IS_GEN8(dev)) {
9573 intel_ring_emit(ring, 0);
9574 intel_ring_emit(ring, MI_NOOP);
9575 }
9576 }
9577
9578 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9579 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9580 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9581 intel_ring_emit(ring, (MI_NOOP));
9582
9583 intel_mark_page_flip_active(intel_crtc);
9584 __intel_ring_advance(ring);
9585 return 0;
9586 }
9587
9588 static bool use_mmio_flip(struct intel_engine_cs *ring,
9589 struct drm_i915_gem_object *obj)
9590 {
9591 /*
9592 * This is not being used for older platforms, because
9593 * non-availability of flip done interrupt forces us to use
9594 * CS flips. Older platforms derive flip done using some clever
9595 * tricks involving the flip_pending status bits and vblank irqs.
9596 * So using MMIO flips there would disrupt this mechanism.
9597 */
9598
9599 if (ring == NULL)
9600 return true;
9601
9602 if (INTEL_INFO(ring->dev)->gen < 5)
9603 return false;
9604
9605 if (i915.use_mmio_flip < 0)
9606 return false;
9607 else if (i915.use_mmio_flip > 0)
9608 return true;
9609 else if (i915.enable_execlists)
9610 return true;
9611 else
9612 return ring != obj->ring;
9613 }
9614
9615 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9616 {
9617 struct drm_device *dev = intel_crtc->base.dev;
9618 struct drm_i915_private *dev_priv = dev->dev_private;
9619 struct intel_framebuffer *intel_fb =
9620 to_intel_framebuffer(intel_crtc->base.primary->fb);
9621 struct drm_i915_gem_object *obj = intel_fb->obj;
9622 u32 dspcntr;
9623 u32 reg;
9624
9625 intel_mark_page_flip_active(intel_crtc);
9626
9627 reg = DSPCNTR(intel_crtc->plane);
9628 dspcntr = I915_READ(reg);
9629
9630 if (INTEL_INFO(dev)->gen >= 4) {
9631 if (obj->tiling_mode != I915_TILING_NONE)
9632 dspcntr |= DISPPLANE_TILED;
9633 else
9634 dspcntr &= ~DISPPLANE_TILED;
9635 }
9636 I915_WRITE(reg, dspcntr);
9637
9638 I915_WRITE(DSPSURF(intel_crtc->plane),
9639 intel_crtc->unpin_work->gtt_offset);
9640 POSTING_READ(DSPSURF(intel_crtc->plane));
9641 }
9642
9643 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9644 {
9645 struct intel_engine_cs *ring;
9646 int ret;
9647
9648 lockdep_assert_held(&obj->base.dev->struct_mutex);
9649
9650 if (!obj->last_write_seqno)
9651 return 0;
9652
9653 ring = obj->ring;
9654
9655 if (i915_seqno_passed(ring->get_seqno(ring, true),
9656 obj->last_write_seqno))
9657 return 0;
9658
9659 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9660 if (ret)
9661 return ret;
9662
9663 if (WARN_ON(!ring->irq_get(ring)))
9664 return 0;
9665
9666 return 1;
9667 }
9668
9669 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9670 {
9671 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9672 struct intel_crtc *intel_crtc;
9673 unsigned long irq_flags;
9674 u32 seqno;
9675
9676 seqno = ring->get_seqno(ring, false);
9677
9678 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9679 for_each_intel_crtc(ring->dev, intel_crtc) {
9680 struct intel_mmio_flip *mmio_flip;
9681
9682 mmio_flip = &intel_crtc->mmio_flip;
9683 if (mmio_flip->seqno == 0)
9684 continue;
9685
9686 if (ring->id != mmio_flip->ring_id)
9687 continue;
9688
9689 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9690 intel_do_mmio_flip(intel_crtc);
9691 mmio_flip->seqno = 0;
9692 ring->irq_put(ring);
9693 }
9694 }
9695 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9696 }
9697
9698 static int intel_queue_mmio_flip(struct drm_device *dev,
9699 struct drm_crtc *crtc,
9700 struct drm_framebuffer *fb,
9701 struct drm_i915_gem_object *obj,
9702 struct intel_engine_cs *ring,
9703 uint32_t flags)
9704 {
9705 struct drm_i915_private *dev_priv = dev->dev_private;
9706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9707 unsigned long irq_flags;
9708 int ret;
9709
9710 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9711 return -EBUSY;
9712
9713 ret = intel_postpone_flip(obj);
9714 if (ret < 0)
9715 return ret;
9716 if (ret == 0) {
9717 intel_do_mmio_flip(intel_crtc);
9718 return 0;
9719 }
9720
9721 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9722 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9723 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9724 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9725
9726 /*
9727 * Double check to catch cases where irq fired before
9728 * mmio flip data was ready
9729 */
9730 intel_notify_mmio_flip(obj->ring);
9731 return 0;
9732 }
9733
9734 static int intel_default_queue_flip(struct drm_device *dev,
9735 struct drm_crtc *crtc,
9736 struct drm_framebuffer *fb,
9737 struct drm_i915_gem_object *obj,
9738 struct intel_engine_cs *ring,
9739 uint32_t flags)
9740 {
9741 return -ENODEV;
9742 }
9743
9744 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9745 struct drm_framebuffer *fb,
9746 struct drm_pending_vblank_event *event,
9747 uint32_t page_flip_flags)
9748 {
9749 struct drm_device *dev = crtc->dev;
9750 struct drm_i915_private *dev_priv = dev->dev_private;
9751 struct drm_framebuffer *old_fb = crtc->primary->fb;
9752 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9754 enum pipe pipe = intel_crtc->pipe;
9755 struct intel_unpin_work *work;
9756 struct intel_engine_cs *ring;
9757 unsigned long flags;
9758 int ret;
9759
9760 //trigger software GT busyness calculation
9761 gen8_flip_interrupt(dev);
9762
9763 /*
9764 * drm_mode_page_flip_ioctl() should already catch this, but double
9765 * check to be safe. In the future we may enable pageflipping from
9766 * a disabled primary plane.
9767 */
9768 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9769 return -EBUSY;
9770
9771 /* Can't change pixel format via MI display flips. */
9772 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9773 return -EINVAL;
9774
9775 /*
9776 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9777 * Note that pitch changes could also affect these register.
9778 */
9779 if (INTEL_INFO(dev)->gen > 3 &&
9780 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9781 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9782 return -EINVAL;
9783
9784 if (i915_terminally_wedged(&dev_priv->gpu_error))
9785 goto out_hang;
9786
9787 work = kzalloc(sizeof(*work), GFP_KERNEL);
9788 if (work == NULL)
9789 return -ENOMEM;
9790
9791 work->event = event;
9792 work->crtc = crtc;
9793 work->old_fb_obj = intel_fb_obj(old_fb);
9794 INIT_WORK(&work->work, intel_unpin_work_fn);
9795
9796 ret = drm_crtc_vblank_get(crtc);
9797 if (ret)
9798 goto free_work;
9799
9800 /* We borrow the event spin lock for protecting unpin_work */
9801 spin_lock_irqsave(&dev->event_lock, flags);
9802 if (intel_crtc->unpin_work) {
9803 spin_unlock_irqrestore(&dev->event_lock, flags);
9804 kfree(work);
9805 drm_crtc_vblank_put(crtc);
9806
9807 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9808 return -EBUSY;
9809 }
9810 intel_crtc->unpin_work = work;
9811 spin_unlock_irqrestore(&dev->event_lock, flags);
9812
9813 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9814 flush_workqueue(dev_priv->wq);
9815
9816 ret = i915_mutex_lock_interruptible(dev);
9817 if (ret)
9818 goto cleanup;
9819
9820 /* Reference the objects for the scheduled work. */
9821 drm_gem_object_reference(&work->old_fb_obj->base);
9822 drm_gem_object_reference(&obj->base);
9823
9824 crtc->primary->fb = fb;
9825
9826 work->pending_flip_obj = obj;
9827
9828 work->enable_stall_check = true;
9829
9830 atomic_inc(&intel_crtc->unpin_work_count);
9831 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9832
9833 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9834 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9835
9836 if (IS_VALLEYVIEW(dev)) {
9837 ring = &dev_priv->ring[BCS];
9838 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9839 /* vlv: DISPLAY_FLIP fails to change tiling */
9840 ring = NULL;
9841 } else if (IS_IVYBRIDGE(dev)) {
9842 ring = &dev_priv->ring[BCS];
9843 } else if (INTEL_INFO(dev)->gen >= 7) {
9844 ring = obj->ring;
9845 if (ring == NULL || ring->id != RCS)
9846 ring = &dev_priv->ring[BCS];
9847 } else {
9848 ring = &dev_priv->ring[RCS];
9849 }
9850
9851 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9852 if (ret)
9853 goto cleanup_pending;
9854
9855 work->gtt_offset =
9856 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9857
9858 if (use_mmio_flip(ring, obj))
9859 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9860 page_flip_flags);
9861 else
9862 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9863 page_flip_flags);
9864 if (ret)
9865 goto cleanup_unpin;
9866
9867 i915_gem_track_fb(work->old_fb_obj, obj,
9868 INTEL_FRONTBUFFER_PRIMARY(pipe));
9869
9870 intel_disable_fbc(dev);
9871 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9872 mutex_unlock(&dev->struct_mutex);
9873
9874 trace_i915_flip_request(intel_crtc->plane, obj);
9875
9876 return 0;
9877
9878 cleanup_unpin:
9879 intel_unpin_fb_obj(obj);
9880 cleanup_pending:
9881 atomic_dec(&intel_crtc->unpin_work_count);
9882 crtc->primary->fb = old_fb;
9883 drm_gem_object_unreference(&work->old_fb_obj->base);
9884 drm_gem_object_unreference(&obj->base);
9885 mutex_unlock(&dev->struct_mutex);
9886
9887 cleanup:
9888 spin_lock_irqsave(&dev->event_lock, flags);
9889 intel_crtc->unpin_work = NULL;
9890 spin_unlock_irqrestore(&dev->event_lock, flags);
9891
9892 drm_crtc_vblank_put(crtc);
9893 free_work:
9894 kfree(work);
9895
9896 if (ret == -EIO) {
9897 out_hang:
9898 intel_crtc_wait_for_pending_flips(crtc);
9899 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9900 if (ret == 0 && event)
9901 drm_send_vblank_event(dev, pipe, event);
9902 }
9903 return ret;
9904 }
9905
9906 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9907 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9908 .load_lut = intel_crtc_load_lut,
9909 };
9910
9911 /**
9912 * intel_modeset_update_staged_output_state
9913 *
9914 * Updates the staged output configuration state, e.g. after we've read out the
9915 * current hw state.
9916 */
9917 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9918 {
9919 struct intel_crtc *crtc;
9920 struct intel_encoder *encoder;
9921 struct intel_connector *connector;
9922
9923 list_for_each_entry(connector, &dev->mode_config.connector_list,
9924 base.head) {
9925 connector->new_encoder =
9926 to_intel_encoder(connector->base.encoder);
9927 }
9928
9929 for_each_intel_encoder(dev, encoder) {
9930 encoder->new_crtc =
9931 to_intel_crtc(encoder->base.crtc);
9932 }
9933
9934 for_each_intel_crtc(dev, crtc) {
9935 crtc->new_enabled = crtc->base.enabled;
9936
9937 if (crtc->new_enabled)
9938 crtc->new_config = &crtc->config;
9939 else
9940 crtc->new_config = NULL;
9941 }
9942 }
9943
9944 /**
9945 * intel_modeset_commit_output_state
9946 *
9947 * This function copies the stage display pipe configuration to the real one.
9948 */
9949 static void intel_modeset_commit_output_state(struct drm_device *dev)
9950 {
9951 struct intel_crtc *crtc;
9952 struct intel_encoder *encoder;
9953 struct intel_connector *connector;
9954
9955 list_for_each_entry(connector, &dev->mode_config.connector_list,
9956 base.head) {
9957 connector->base.encoder = &connector->new_encoder->base;
9958 }
9959
9960 for_each_intel_encoder(dev, encoder) {
9961 encoder->base.crtc = &encoder->new_crtc->base;
9962 }
9963
9964 for_each_intel_crtc(dev, crtc) {
9965 crtc->base.enabled = crtc->new_enabled;
9966 }
9967 }
9968
9969 static void
9970 connected_sink_compute_bpp(struct intel_connector *connector,
9971 struct intel_crtc_config *pipe_config)
9972 {
9973 int bpp = pipe_config->pipe_bpp;
9974
9975 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9976 connector->base.base.id,
9977 connector->base.name);
9978
9979 /* Don't use an invalid EDID bpc value */
9980 if (connector->base.display_info.bpc &&
9981 connector->base.display_info.bpc * 3 < bpp) {
9982 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9983 bpp, connector->base.display_info.bpc*3);
9984 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9985 }
9986
9987 /* Clamp bpp to 8 on screens without EDID 1.4 */
9988 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9989 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9990 bpp);
9991 pipe_config->pipe_bpp = 24;
9992 }
9993 }
9994
9995 static int
9996 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9997 struct drm_framebuffer *fb,
9998 struct intel_crtc_config *pipe_config)
9999 {
10000 struct drm_device *dev = crtc->base.dev;
10001 struct intel_connector *connector;
10002 int bpp;
10003
10004 switch (fb->pixel_format) {
10005 case DRM_FORMAT_C8:
10006 bpp = 8*3; /* since we go through a colormap */
10007 break;
10008 case DRM_FORMAT_XRGB1555:
10009 case DRM_FORMAT_ARGB1555:
10010 /* checked in intel_framebuffer_init already */
10011 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10012 return -EINVAL;
10013 case DRM_FORMAT_RGB565:
10014 bpp = 6*3; /* min is 18bpp */
10015 break;
10016 case DRM_FORMAT_XBGR8888:
10017 case DRM_FORMAT_ABGR8888:
10018 /* checked in intel_framebuffer_init already */
10019 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10020 return -EINVAL;
10021 case DRM_FORMAT_XRGB8888:
10022 case DRM_FORMAT_ARGB8888:
10023 bpp = 8*3;
10024 break;
10025 case DRM_FORMAT_XRGB2101010:
10026 case DRM_FORMAT_ARGB2101010:
10027 case DRM_FORMAT_XBGR2101010:
10028 case DRM_FORMAT_ABGR2101010:
10029 /* checked in intel_framebuffer_init already */
10030 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10031 return -EINVAL;
10032 bpp = 10*3;
10033 break;
10034 /* TODO: gen4+ supports 16 bpc floating point, too. */
10035 default:
10036 DRM_DEBUG_KMS("unsupported depth\n");
10037 return -EINVAL;
10038 }
10039
10040 pipe_config->pipe_bpp = bpp;
10041
10042 /* Clamp display bpp to EDID value */
10043 list_for_each_entry(connector, &dev->mode_config.connector_list,
10044 base.head) {
10045 if (!connector->new_encoder ||
10046 connector->new_encoder->new_crtc != crtc)
10047 continue;
10048
10049 connected_sink_compute_bpp(connector, pipe_config);
10050 }
10051
10052 return bpp;
10053 }
10054
10055 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10056 {
10057 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10058 "type: 0x%x flags: 0x%x\n",
10059 mode->crtc_clock,
10060 mode->crtc_hdisplay, mode->crtc_hsync_start,
10061 mode->crtc_hsync_end, mode->crtc_htotal,
10062 mode->crtc_vdisplay, mode->crtc_vsync_start,
10063 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10064 }
10065
10066 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10067 struct intel_crtc_config *pipe_config,
10068 const char *context)
10069 {
10070 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10071 context, pipe_name(crtc->pipe));
10072
10073 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10074 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10075 pipe_config->pipe_bpp, pipe_config->dither);
10076 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10077 pipe_config->has_pch_encoder,
10078 pipe_config->fdi_lanes,
10079 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10080 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10081 pipe_config->fdi_m_n.tu);
10082 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10083 pipe_config->has_dp_encoder,
10084 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10085 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10086 pipe_config->dp_m_n.tu);
10087
10088 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10089 pipe_config->has_dp_encoder,
10090 pipe_config->dp_m2_n2.gmch_m,
10091 pipe_config->dp_m2_n2.gmch_n,
10092 pipe_config->dp_m2_n2.link_m,
10093 pipe_config->dp_m2_n2.link_n,
10094 pipe_config->dp_m2_n2.tu);
10095
10096 DRM_DEBUG_KMS("requested mode:\n");
10097 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
10098 DRM_DEBUG_KMS("adjusted mode:\n");
10099 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
10100 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
10101 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10102 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10103 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10104 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10105 pipe_config->gmch_pfit.control,
10106 pipe_config->gmch_pfit.pgm_ratios,
10107 pipe_config->gmch_pfit.lvds_border_bits);
10108 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10109 pipe_config->pch_pfit.pos,
10110 pipe_config->pch_pfit.size,
10111 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10112 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10113 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10114 }
10115
10116 static bool encoders_cloneable(const struct intel_encoder *a,
10117 const struct intel_encoder *b)
10118 {
10119 /* masks could be asymmetric, so check both ways */
10120 return a == b || (a->cloneable & (1 << b->type) &&
10121 b->cloneable & (1 << a->type));
10122 }
10123
10124 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10125 struct intel_encoder *encoder)
10126 {
10127 struct drm_device *dev = crtc->base.dev;
10128 struct intel_encoder *source_encoder;
10129
10130 for_each_intel_encoder(dev, source_encoder) {
10131 if (source_encoder->new_crtc != crtc)
10132 continue;
10133
10134 if (!encoders_cloneable(encoder, source_encoder))
10135 return false;
10136 }
10137
10138 return true;
10139 }
10140
10141 static bool check_encoder_cloning(struct intel_crtc *crtc)
10142 {
10143 struct drm_device *dev = crtc->base.dev;
10144 struct intel_encoder *encoder;
10145
10146 for_each_intel_encoder(dev, encoder) {
10147 if (encoder->new_crtc != crtc)
10148 continue;
10149
10150 if (!check_single_encoder_cloning(crtc, encoder))
10151 return false;
10152 }
10153
10154 return true;
10155 }
10156
10157 static struct intel_crtc_config *
10158 intel_modeset_pipe_config(struct drm_crtc *crtc,
10159 struct drm_framebuffer *fb,
10160 struct drm_display_mode *mode)
10161 {
10162 struct drm_device *dev = crtc->dev;
10163 struct intel_encoder *encoder;
10164 struct intel_crtc_config *pipe_config;
10165 int plane_bpp, ret = -EINVAL;
10166 bool retry = true;
10167
10168 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10169 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10170 return ERR_PTR(-EINVAL);
10171 }
10172
10173 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10174 if (!pipe_config)
10175 return ERR_PTR(-ENOMEM);
10176
10177 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10178 drm_mode_copy(&pipe_config->requested_mode, mode);
10179
10180 pipe_config->cpu_transcoder =
10181 (enum transcoder) to_intel_crtc(crtc)->pipe;
10182 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10183
10184 /*
10185 * Sanitize sync polarity flags based on requested ones. If neither
10186 * positive or negative polarity is requested, treat this as meaning
10187 * negative polarity.
10188 */
10189 if (!(pipe_config->adjusted_mode.flags &
10190 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10191 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10192
10193 if (!(pipe_config->adjusted_mode.flags &
10194 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10195 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10196
10197 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10198 * plane pixel format and any sink constraints into account. Returns the
10199 * source plane bpp so that dithering can be selected on mismatches
10200 * after encoders and crtc also have had their say. */
10201 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10202 fb, pipe_config);
10203 if (plane_bpp < 0)
10204 goto fail;
10205
10206 /*
10207 * Determine the real pipe dimensions. Note that stereo modes can
10208 * increase the actual pipe size due to the frame doubling and
10209 * insertion of additional space for blanks between the frame. This
10210 * is stored in the crtc timings. We use the requested mode to do this
10211 * computation to clearly distinguish it from the adjusted mode, which
10212 * can be changed by the connectors in the below retry loop.
10213 */
10214 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10215 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10216 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10217
10218 encoder_retry:
10219 /* Ensure the port clock defaults are reset when retrying. */
10220 pipe_config->port_clock = 0;
10221 pipe_config->pixel_multiplier = 1;
10222
10223 /* Fill in default crtc timings, allow encoders to overwrite them. */
10224 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10225
10226 /* Pass our mode to the connectors and the CRTC to give them a chance to
10227 * adjust it according to limitations or connector properties, and also
10228 * a chance to reject the mode entirely.
10229 */
10230 for_each_intel_encoder(dev, encoder) {
10231
10232 if (&encoder->new_crtc->base != crtc)
10233 continue;
10234
10235 if (!(encoder->compute_config(encoder, pipe_config))) {
10236 DRM_DEBUG_KMS("Encoder config failure\n");
10237 goto fail;
10238 }
10239 }
10240
10241 /* Set default port clock if not overwritten by the encoder. Needs to be
10242 * done afterwards in case the encoder adjusts the mode. */
10243 if (!pipe_config->port_clock)
10244 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10245 * pipe_config->pixel_multiplier;
10246
10247 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10248 if (ret < 0) {
10249 DRM_DEBUG_KMS("CRTC fixup failed\n");
10250 goto fail;
10251 }
10252
10253 if (ret == RETRY) {
10254 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10255 ret = -EINVAL;
10256 goto fail;
10257 }
10258
10259 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10260 retry = false;
10261 goto encoder_retry;
10262 }
10263
10264 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10265 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10266 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10267
10268 return pipe_config;
10269 fail:
10270 kfree(pipe_config);
10271 return ERR_PTR(ret);
10272 }
10273
10274 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10275 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10276 static void
10277 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10278 unsigned *prepare_pipes, unsigned *disable_pipes)
10279 {
10280 struct intel_crtc *intel_crtc;
10281 struct drm_device *dev = crtc->dev;
10282 struct intel_encoder *encoder;
10283 struct intel_connector *connector;
10284 struct drm_crtc *tmp_crtc;
10285
10286 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10287
10288 /* Check which crtcs have changed outputs connected to them, these need
10289 * to be part of the prepare_pipes mask. We don't (yet) support global
10290 * modeset across multiple crtcs, so modeset_pipes will only have one
10291 * bit set at most. */
10292 list_for_each_entry(connector, &dev->mode_config.connector_list,
10293 base.head) {
10294 if (connector->base.encoder == &connector->new_encoder->base)
10295 continue;
10296
10297 if (connector->base.encoder) {
10298 tmp_crtc = connector->base.encoder->crtc;
10299
10300 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10301 }
10302
10303 if (connector->new_encoder)
10304 *prepare_pipes |=
10305 1 << connector->new_encoder->new_crtc->pipe;
10306 }
10307
10308 for_each_intel_encoder(dev, encoder) {
10309 if (encoder->base.crtc == &encoder->new_crtc->base)
10310 continue;
10311
10312 if (encoder->base.crtc) {
10313 tmp_crtc = encoder->base.crtc;
10314
10315 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10316 }
10317
10318 if (encoder->new_crtc)
10319 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10320 }
10321
10322 /* Check for pipes that will be enabled/disabled ... */
10323 for_each_intel_crtc(dev, intel_crtc) {
10324 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10325 continue;
10326
10327 if (!intel_crtc->new_enabled)
10328 *disable_pipes |= 1 << intel_crtc->pipe;
10329 else
10330 *prepare_pipes |= 1 << intel_crtc->pipe;
10331 }
10332
10333
10334 /* set_mode is also used to update properties on life display pipes. */
10335 intel_crtc = to_intel_crtc(crtc);
10336 if (intel_crtc->new_enabled)
10337 *prepare_pipes |= 1 << intel_crtc->pipe;
10338
10339 /*
10340 * For simplicity do a full modeset on any pipe where the output routing
10341 * changed. We could be more clever, but that would require us to be
10342 * more careful with calling the relevant encoder->mode_set functions.
10343 */
10344 if (*prepare_pipes)
10345 *modeset_pipes = *prepare_pipes;
10346
10347 /* ... and mask these out. */
10348 *modeset_pipes &= ~(*disable_pipes);
10349 *prepare_pipes &= ~(*disable_pipes);
10350
10351 /*
10352 * HACK: We don't (yet) fully support global modesets. intel_set_config
10353 * obies this rule, but the modeset restore mode of
10354 * intel_modeset_setup_hw_state does not.
10355 */
10356 *modeset_pipes &= 1 << intel_crtc->pipe;
10357 *prepare_pipes &= 1 << intel_crtc->pipe;
10358
10359 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10360 *modeset_pipes, *prepare_pipes, *disable_pipes);
10361 }
10362
10363 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10364 {
10365 struct drm_encoder *encoder;
10366 struct drm_device *dev = crtc->dev;
10367
10368 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10369 if (encoder->crtc == crtc)
10370 return true;
10371
10372 return false;
10373 }
10374
10375 static void
10376 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10377 {
10378 struct intel_encoder *intel_encoder;
10379 struct intel_crtc *intel_crtc;
10380 struct drm_connector *connector;
10381
10382 for_each_intel_encoder(dev, intel_encoder) {
10383 if (!intel_encoder->base.crtc)
10384 continue;
10385
10386 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10387
10388 if (prepare_pipes & (1 << intel_crtc->pipe))
10389 intel_encoder->connectors_active = false;
10390 }
10391
10392 intel_modeset_commit_output_state(dev);
10393
10394 /* Double check state. */
10395 for_each_intel_crtc(dev, intel_crtc) {
10396 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10397 WARN_ON(intel_crtc->new_config &&
10398 intel_crtc->new_config != &intel_crtc->config);
10399 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10400 }
10401
10402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10403 if (!connector->encoder || !connector->encoder->crtc)
10404 continue;
10405
10406 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10407
10408 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10409 struct drm_property *dpms_property =
10410 dev->mode_config.dpms_property;
10411
10412 connector->dpms = DRM_MODE_DPMS_ON;
10413 drm_object_property_set_value(&connector->base,
10414 dpms_property,
10415 DRM_MODE_DPMS_ON);
10416
10417 intel_encoder = to_intel_encoder(connector->encoder);
10418 intel_encoder->connectors_active = true;
10419 }
10420 }
10421
10422 }
10423
10424 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10425 {
10426 int diff;
10427
10428 if (clock1 == clock2)
10429 return true;
10430
10431 if (!clock1 || !clock2)
10432 return false;
10433
10434 diff = abs(clock1 - clock2);
10435
10436 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10437 return true;
10438
10439 return false;
10440 }
10441
10442 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10443 list_for_each_entry((intel_crtc), \
10444 &(dev)->mode_config.crtc_list, \
10445 base.head) \
10446 if (mask & (1 <<(intel_crtc)->pipe))
10447
10448 static bool
10449 intel_pipe_config_compare(struct drm_device *dev,
10450 struct intel_crtc_config *current_config,
10451 struct intel_crtc_config *pipe_config)
10452 {
10453 #define PIPE_CONF_CHECK_X(name) \
10454 if (current_config->name != pipe_config->name) { \
10455 DRM_ERROR("mismatch in " #name " " \
10456 "(expected 0x%08x, found 0x%08x)\n", \
10457 current_config->name, \
10458 pipe_config->name); \
10459 return false; \
10460 }
10461
10462 #define PIPE_CONF_CHECK_I(name) \
10463 if (current_config->name != pipe_config->name) { \
10464 DRM_ERROR("mismatch in " #name " " \
10465 "(expected %i, found %i)\n", \
10466 current_config->name, \
10467 pipe_config->name); \
10468 return false; \
10469 }
10470
10471 /* This is required for BDW+ where there is only one set of registers for
10472 * switching between high and low RR.
10473 * This macro can be used whenever a comparison has to be made between one
10474 * hw state and multiple sw state variables.
10475 */
10476 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10477 if ((current_config->name != pipe_config->name) && \
10478 (current_config->alt_name != pipe_config->name)) { \
10479 DRM_ERROR("mismatch in " #name " " \
10480 "(expected %i or %i, found %i)\n", \
10481 current_config->name, \
10482 current_config->alt_name, \
10483 pipe_config->name); \
10484 return false; \
10485 }
10486
10487 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10488 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10489 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10490 "(expected %i, found %i)\n", \
10491 current_config->name & (mask), \
10492 pipe_config->name & (mask)); \
10493 return false; \
10494 }
10495
10496 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10497 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10498 DRM_ERROR("mismatch in " #name " " \
10499 "(expected %i, found %i)\n", \
10500 current_config->name, \
10501 pipe_config->name); \
10502 return false; \
10503 }
10504
10505 #define PIPE_CONF_QUIRK(quirk) \
10506 ((current_config->quirks | pipe_config->quirks) & (quirk))
10507
10508 PIPE_CONF_CHECK_I(cpu_transcoder);
10509
10510 PIPE_CONF_CHECK_I(has_pch_encoder);
10511 PIPE_CONF_CHECK_I(fdi_lanes);
10512 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10513 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10514 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10515 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10516 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10517
10518 PIPE_CONF_CHECK_I(has_dp_encoder);
10519
10520 if (INTEL_INFO(dev)->gen < 8) {
10521 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10522 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10523 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10524 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10525 PIPE_CONF_CHECK_I(dp_m_n.tu);
10526
10527 if (current_config->has_drrs) {
10528 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10529 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10530 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10531 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10532 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10533 }
10534 } else {
10535 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10536 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10537 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10538 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10539 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10540 }
10541
10542 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10543 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10544 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10545 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10546 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10547 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10548
10549 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10550 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10551 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10552 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10553 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10554 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10555
10556 PIPE_CONF_CHECK_I(pixel_multiplier);
10557 PIPE_CONF_CHECK_I(has_hdmi_sink);
10558 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10559 IS_VALLEYVIEW(dev))
10560 PIPE_CONF_CHECK_I(limited_color_range);
10561
10562 PIPE_CONF_CHECK_I(has_audio);
10563
10564 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10565 DRM_MODE_FLAG_INTERLACE);
10566
10567 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10568 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10569 DRM_MODE_FLAG_PHSYNC);
10570 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10571 DRM_MODE_FLAG_NHSYNC);
10572 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10573 DRM_MODE_FLAG_PVSYNC);
10574 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10575 DRM_MODE_FLAG_NVSYNC);
10576 }
10577
10578 PIPE_CONF_CHECK_I(pipe_src_w);
10579 PIPE_CONF_CHECK_I(pipe_src_h);
10580
10581 /*
10582 * FIXME: BIOS likes to set up a cloned config with lvds+external
10583 * screen. Since we don't yet re-compute the pipe config when moving
10584 * just the lvds port away to another pipe the sw tracking won't match.
10585 *
10586 * Proper atomic modesets with recomputed global state will fix this.
10587 * Until then just don't check gmch state for inherited modes.
10588 */
10589 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10590 PIPE_CONF_CHECK_I(gmch_pfit.control);
10591 /* pfit ratios are autocomputed by the hw on gen4+ */
10592 if (INTEL_INFO(dev)->gen < 4)
10593 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10594 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10595 }
10596
10597 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10598 if (current_config->pch_pfit.enabled) {
10599 PIPE_CONF_CHECK_I(pch_pfit.pos);
10600 PIPE_CONF_CHECK_I(pch_pfit.size);
10601 }
10602
10603 /* BDW+ don't expose a synchronous way to read the state */
10604 if (IS_HASWELL(dev))
10605 PIPE_CONF_CHECK_I(ips_enabled);
10606
10607 PIPE_CONF_CHECK_I(double_wide);
10608
10609 PIPE_CONF_CHECK_X(ddi_pll_sel);
10610
10611 PIPE_CONF_CHECK_I(shared_dpll);
10612 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10613 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10614 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10615 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10616 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10617
10618 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10619 PIPE_CONF_CHECK_I(pipe_bpp);
10620
10621 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10622 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10623
10624 #undef PIPE_CONF_CHECK_X
10625 #undef PIPE_CONF_CHECK_I
10626 #undef PIPE_CONF_CHECK_I_ALT
10627 #undef PIPE_CONF_CHECK_FLAGS
10628 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10629 #undef PIPE_CONF_QUIRK
10630
10631 return true;
10632 }
10633
10634 static void
10635 check_connector_state(struct drm_device *dev)
10636 {
10637 struct intel_connector *connector;
10638
10639 list_for_each_entry(connector, &dev->mode_config.connector_list,
10640 base.head) {
10641 /* This also checks the encoder/connector hw state with the
10642 * ->get_hw_state callbacks. */
10643 intel_connector_check_state(connector);
10644
10645 WARN(&connector->new_encoder->base != connector->base.encoder,
10646 "connector's staged encoder doesn't match current encoder\n");
10647 }
10648 }
10649
10650 static void
10651 check_encoder_state(struct drm_device *dev)
10652 {
10653 struct intel_encoder *encoder;
10654 struct intel_connector *connector;
10655
10656 for_each_intel_encoder(dev, encoder) {
10657 bool enabled = false;
10658 bool active = false;
10659 enum pipe pipe, tracked_pipe;
10660
10661 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10662 encoder->base.base.id,
10663 encoder->base.name);
10664
10665 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10666 "encoder's stage crtc doesn't match current crtc\n");
10667 WARN(encoder->connectors_active && !encoder->base.crtc,
10668 "encoder's active_connectors set, but no crtc\n");
10669
10670 list_for_each_entry(connector, &dev->mode_config.connector_list,
10671 base.head) {
10672 if (connector->base.encoder != &encoder->base)
10673 continue;
10674 enabled = true;
10675 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10676 active = true;
10677 }
10678 /*
10679 * for MST connectors if we unplug the connector is gone
10680 * away but the encoder is still connected to a crtc
10681 * until a modeset happens in response to the hotplug.
10682 */
10683 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10684 continue;
10685
10686 WARN(!!encoder->base.crtc != enabled,
10687 "encoder's enabled state mismatch "
10688 "(expected %i, found %i)\n",
10689 !!encoder->base.crtc, enabled);
10690 WARN(active && !encoder->base.crtc,
10691 "active encoder with no crtc\n");
10692
10693 WARN(encoder->connectors_active != active,
10694 "encoder's computed active state doesn't match tracked active state "
10695 "(expected %i, found %i)\n", active, encoder->connectors_active);
10696
10697 active = encoder->get_hw_state(encoder, &pipe);
10698 WARN(active != encoder->connectors_active,
10699 "encoder's hw state doesn't match sw tracking "
10700 "(expected %i, found %i)\n",
10701 encoder->connectors_active, active);
10702
10703 if (!encoder->base.crtc)
10704 continue;
10705
10706 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10707 WARN(active && pipe != tracked_pipe,
10708 "active encoder's pipe doesn't match"
10709 "(expected %i, found %i)\n",
10710 tracked_pipe, pipe);
10711
10712 }
10713 }
10714
10715 static void
10716 check_crtc_state(struct drm_device *dev)
10717 {
10718 struct drm_i915_private *dev_priv = dev->dev_private;
10719 struct intel_crtc *crtc;
10720 struct intel_encoder *encoder;
10721 struct intel_crtc_config pipe_config;
10722
10723 for_each_intel_crtc(dev, crtc) {
10724 bool enabled = false;
10725 bool active = false;
10726
10727 memset(&pipe_config, 0, sizeof(pipe_config));
10728
10729 DRM_DEBUG_KMS("[CRTC:%d]\n",
10730 crtc->base.base.id);
10731
10732 WARN(crtc->active && !crtc->base.enabled,
10733 "active crtc, but not enabled in sw tracking\n");
10734
10735 for_each_intel_encoder(dev, encoder) {
10736 if (encoder->base.crtc != &crtc->base)
10737 continue;
10738 enabled = true;
10739 if (encoder->connectors_active)
10740 active = true;
10741 }
10742
10743 WARN(active != crtc->active,
10744 "crtc's computed active state doesn't match tracked active state "
10745 "(expected %i, found %i)\n", active, crtc->active);
10746 WARN(enabled != crtc->base.enabled,
10747 "crtc's computed enabled state doesn't match tracked enabled state "
10748 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10749
10750 active = dev_priv->display.get_pipe_config(crtc,
10751 &pipe_config);
10752
10753 /* hw state is inconsistent with the pipe A quirk */
10754 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10755 active = crtc->active;
10756
10757 for_each_intel_encoder(dev, encoder) {
10758 enum pipe pipe;
10759 if (encoder->base.crtc != &crtc->base)
10760 continue;
10761 if (encoder->get_hw_state(encoder, &pipe))
10762 encoder->get_config(encoder, &pipe_config);
10763 }
10764
10765 WARN(crtc->active != active,
10766 "crtc active state doesn't match with hw state "
10767 "(expected %i, found %i)\n", crtc->active, active);
10768
10769 if (active &&
10770 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10771 WARN(1, "pipe state doesn't match!\n");
10772 intel_dump_pipe_config(crtc, &pipe_config,
10773 "[hw state]");
10774 intel_dump_pipe_config(crtc, &crtc->config,
10775 "[sw state]");
10776 }
10777 }
10778 }
10779
10780 static void
10781 check_shared_dpll_state(struct drm_device *dev)
10782 {
10783 struct drm_i915_private *dev_priv = dev->dev_private;
10784 struct intel_crtc *crtc;
10785 struct intel_dpll_hw_state dpll_hw_state;
10786 int i;
10787
10788 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10789 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10790 int enabled_crtcs = 0, active_crtcs = 0;
10791 bool active;
10792
10793 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10794
10795 DRM_DEBUG_KMS("%s\n", pll->name);
10796
10797 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10798
10799 WARN(pll->active > pll->refcount,
10800 "more active pll users than references: %i vs %i\n",
10801 pll->active, pll->refcount);
10802 WARN(pll->active && !pll->on,
10803 "pll in active use but not on in sw tracking\n");
10804 WARN(pll->on && !pll->active,
10805 "pll in on but not on in use in sw tracking\n");
10806 WARN(pll->on != active,
10807 "pll on state mismatch (expected %i, found %i)\n",
10808 pll->on, active);
10809
10810 for_each_intel_crtc(dev, crtc) {
10811 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10812 enabled_crtcs++;
10813 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10814 active_crtcs++;
10815 }
10816 WARN(pll->active != active_crtcs,
10817 "pll active crtcs mismatch (expected %i, found %i)\n",
10818 pll->active, active_crtcs);
10819 WARN(pll->refcount != enabled_crtcs,
10820 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10821 pll->refcount, enabled_crtcs);
10822
10823 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10824 sizeof(dpll_hw_state)),
10825 "pll hw state mismatch\n");
10826 }
10827 }
10828
10829 void
10830 intel_modeset_check_state(struct drm_device *dev)
10831 {
10832 check_connector_state(dev);
10833 check_encoder_state(dev);
10834 check_crtc_state(dev);
10835 check_shared_dpll_state(dev);
10836 }
10837
10838 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10839 int dotclock)
10840 {
10841 /*
10842 * FDI already provided one idea for the dotclock.
10843 * Yell if the encoder disagrees.
10844 */
10845 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10846 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10847 pipe_config->adjusted_mode.crtc_clock, dotclock);
10848 }
10849
10850 static void update_scanline_offset(struct intel_crtc *crtc)
10851 {
10852 struct drm_device *dev = crtc->base.dev;
10853
10854 /*
10855 * The scanline counter increments at the leading edge of hsync.
10856 *
10857 * On most platforms it starts counting from vtotal-1 on the
10858 * first active line. That means the scanline counter value is
10859 * always one less than what we would expect. Ie. just after
10860 * start of vblank, which also occurs at start of hsync (on the
10861 * last active line), the scanline counter will read vblank_start-1.
10862 *
10863 * On gen2 the scanline counter starts counting from 1 instead
10864 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10865 * to keep the value positive), instead of adding one.
10866 *
10867 * On HSW+ the behaviour of the scanline counter depends on the output
10868 * type. For DP ports it behaves like most other platforms, but on HDMI
10869 * there's an extra 1 line difference. So we need to add two instead of
10870 * one to the value.
10871 */
10872 if (IS_GEN2(dev)) {
10873 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10874 int vtotal;
10875
10876 vtotal = mode->crtc_vtotal;
10877 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10878 vtotal /= 2;
10879
10880 crtc->scanline_offset = vtotal - 1;
10881 } else if (HAS_DDI(dev) &&
10882 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10883 crtc->scanline_offset = 2;
10884 } else
10885 crtc->scanline_offset = 1;
10886 }
10887
10888 static int __intel_set_mode(struct drm_crtc *crtc,
10889 struct drm_display_mode *mode,
10890 int x, int y, struct drm_framebuffer *fb)
10891 {
10892 struct drm_device *dev = crtc->dev;
10893 struct drm_i915_private *dev_priv = dev->dev_private;
10894 struct drm_display_mode *saved_mode;
10895 struct intel_crtc_config *pipe_config = NULL;
10896 struct intel_crtc *intel_crtc;
10897 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10898 int ret = 0;
10899
10900 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10901 if (!saved_mode)
10902 return -ENOMEM;
10903
10904 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10905 &prepare_pipes, &disable_pipes);
10906
10907 *saved_mode = crtc->mode;
10908
10909 /* Hack: Because we don't (yet) support global modeset on multiple
10910 * crtcs, we don't keep track of the new mode for more than one crtc.
10911 * Hence simply check whether any bit is set in modeset_pipes in all the
10912 * pieces of code that are not yet converted to deal with mutliple crtcs
10913 * changing their mode at the same time. */
10914 if (modeset_pipes) {
10915 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10916 if (IS_ERR(pipe_config)) {
10917 ret = PTR_ERR(pipe_config);
10918 pipe_config = NULL;
10919
10920 goto out;
10921 }
10922 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10923 "[modeset]");
10924 to_intel_crtc(crtc)->new_config = pipe_config;
10925 }
10926
10927 /*
10928 * See if the config requires any additional preparation, e.g.
10929 * to adjust global state with pipes off. We need to do this
10930 * here so we can get the modeset_pipe updated config for the new
10931 * mode set on this crtc. For other crtcs we need to use the
10932 * adjusted_mode bits in the crtc directly.
10933 */
10934 if (IS_VALLEYVIEW(dev)) {
10935 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10936
10937 /* may have added more to prepare_pipes than we should */
10938 prepare_pipes &= ~disable_pipes;
10939 }
10940
10941 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10942 intel_crtc_disable(&intel_crtc->base);
10943
10944 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10945 if (intel_crtc->base.enabled)
10946 dev_priv->display.crtc_disable(&intel_crtc->base);
10947 }
10948
10949 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10950 * to set it here already despite that we pass it down the callchain.
10951 */
10952 if (modeset_pipes) {
10953 crtc->mode = *mode;
10954 /* mode_set/enable/disable functions rely on a correct pipe
10955 * config. */
10956 to_intel_crtc(crtc)->config = *pipe_config;
10957 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10958
10959 /*
10960 * Calculate and store various constants which
10961 * are later needed by vblank and swap-completion
10962 * timestamping. They are derived from true hwmode.
10963 */
10964 drm_calc_timestamping_constants(crtc,
10965 &pipe_config->adjusted_mode);
10966 }
10967
10968 /* Only after disabling all output pipelines that will be changed can we
10969 * update the the output configuration. */
10970 intel_modeset_update_state(dev, prepare_pipes);
10971
10972 if (dev_priv->display.modeset_global_resources)
10973 dev_priv->display.modeset_global_resources(dev);
10974
10975 /* Set up the DPLL and any encoders state that needs to adjust or depend
10976 * on the DPLL.
10977 */
10978 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10979 struct drm_framebuffer *old_fb = crtc->primary->fb;
10980 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10981 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10982
10983 mutex_lock(&dev->struct_mutex);
10984 ret = intel_pin_and_fence_fb_obj(dev,
10985 obj,
10986 NULL);
10987 if (ret != 0) {
10988 DRM_ERROR("pin & fence failed\n");
10989 mutex_unlock(&dev->struct_mutex);
10990 goto done;
10991 }
10992 if (old_fb)
10993 intel_unpin_fb_obj(old_obj);
10994 i915_gem_track_fb(old_obj, obj,
10995 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10996 mutex_unlock(&dev->struct_mutex);
10997
10998 crtc->primary->fb = fb;
10999 crtc->x = x;
11000 crtc->y = y;
11001
11002 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
11003 x, y, fb);
11004 if (ret)
11005 goto done;
11006 }
11007
11008 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11009 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11010 update_scanline_offset(intel_crtc);
11011
11012 dev_priv->display.crtc_enable(&intel_crtc->base);
11013 }
11014
11015 /* FIXME: add subpixel order */
11016 done:
11017 if (ret && crtc->enabled)
11018 crtc->mode = *saved_mode;
11019
11020 out:
11021 kfree(pipe_config);
11022 kfree(saved_mode);
11023 return ret;
11024 }
11025
11026 static int intel_set_mode(struct drm_crtc *crtc,
11027 struct drm_display_mode *mode,
11028 int x, int y, struct drm_framebuffer *fb)
11029 {
11030 int ret;
11031
11032 ret = __intel_set_mode(crtc, mode, x, y, fb);
11033
11034 if (ret == 0)
11035 intel_modeset_check_state(crtc->dev);
11036
11037 return ret;
11038 }
11039
11040 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11041 {
11042 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11043 }
11044
11045 #undef for_each_intel_crtc_masked
11046
11047 static void intel_set_config_free(struct intel_set_config *config)
11048 {
11049 if (!config)
11050 return;
11051
11052 kfree(config->save_connector_encoders);
11053 kfree(config->save_encoder_crtcs);
11054 kfree(config->save_crtc_enabled);
11055 kfree(config);
11056 }
11057
11058 static int intel_set_config_save_state(struct drm_device *dev,
11059 struct intel_set_config *config)
11060 {
11061 struct drm_crtc *crtc;
11062 struct drm_encoder *encoder;
11063 struct drm_connector *connector;
11064 int count;
11065
11066 config->save_crtc_enabled =
11067 kcalloc(dev->mode_config.num_crtc,
11068 sizeof(bool), GFP_KERNEL);
11069 if (!config->save_crtc_enabled)
11070 return -ENOMEM;
11071
11072 config->save_encoder_crtcs =
11073 kcalloc(dev->mode_config.num_encoder,
11074 sizeof(struct drm_crtc *), GFP_KERNEL);
11075 if (!config->save_encoder_crtcs)
11076 return -ENOMEM;
11077
11078 config->save_connector_encoders =
11079 kcalloc(dev->mode_config.num_connector,
11080 sizeof(struct drm_encoder *), GFP_KERNEL);
11081 if (!config->save_connector_encoders)
11082 return -ENOMEM;
11083
11084 /* Copy data. Note that driver private data is not affected.
11085 * Should anything bad happen only the expected state is
11086 * restored, not the drivers personal bookkeeping.
11087 */
11088 count = 0;
11089 for_each_crtc(dev, crtc) {
11090 config->save_crtc_enabled[count++] = crtc->enabled;
11091 }
11092
11093 count = 0;
11094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11095 config->save_encoder_crtcs[count++] = encoder->crtc;
11096 }
11097
11098 count = 0;
11099 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11100 config->save_connector_encoders[count++] = connector->encoder;
11101 }
11102
11103 return 0;
11104 }
11105
11106 static void intel_set_config_restore_state(struct drm_device *dev,
11107 struct intel_set_config *config)
11108 {
11109 struct intel_crtc *crtc;
11110 struct intel_encoder *encoder;
11111 struct intel_connector *connector;
11112 int count;
11113
11114 count = 0;
11115 for_each_intel_crtc(dev, crtc) {
11116 crtc->new_enabled = config->save_crtc_enabled[count++];
11117
11118 if (crtc->new_enabled)
11119 crtc->new_config = &crtc->config;
11120 else
11121 crtc->new_config = NULL;
11122 }
11123
11124 count = 0;
11125 for_each_intel_encoder(dev, encoder) {
11126 encoder->new_crtc =
11127 to_intel_crtc(config->save_encoder_crtcs[count++]);
11128 }
11129
11130 count = 0;
11131 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11132 connector->new_encoder =
11133 to_intel_encoder(config->save_connector_encoders[count++]);
11134 }
11135 }
11136
11137 static bool
11138 is_crtc_connector_off(struct drm_mode_set *set)
11139 {
11140 int i;
11141
11142 if (set->num_connectors == 0)
11143 return false;
11144
11145 if (WARN_ON(set->connectors == NULL))
11146 return false;
11147
11148 for (i = 0; i < set->num_connectors; i++)
11149 if (set->connectors[i]->encoder &&
11150 set->connectors[i]->encoder->crtc == set->crtc &&
11151 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11152 return true;
11153
11154 return false;
11155 }
11156
11157 static void
11158 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11159 struct intel_set_config *config)
11160 {
11161
11162 /* We should be able to check here if the fb has the same properties
11163 * and then just flip_or_move it */
11164 if (is_crtc_connector_off(set)) {
11165 config->mode_changed = true;
11166 } else if (set->crtc->primary->fb != set->fb) {
11167 /*
11168 * If we have no fb, we can only flip as long as the crtc is
11169 * active, otherwise we need a full mode set. The crtc may
11170 * be active if we've only disabled the primary plane, or
11171 * in fastboot situations.
11172 */
11173 if (set->crtc->primary->fb == NULL) {
11174 struct intel_crtc *intel_crtc =
11175 to_intel_crtc(set->crtc);
11176
11177 if (intel_crtc->active) {
11178 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11179 config->fb_changed = true;
11180 } else {
11181 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11182 config->mode_changed = true;
11183 }
11184 } else if (set->fb == NULL) {
11185 config->mode_changed = true;
11186 } else if (set->fb->pixel_format !=
11187 set->crtc->primary->fb->pixel_format) {
11188 config->mode_changed = true;
11189 } else {
11190 config->fb_changed = true;
11191 }
11192 }
11193
11194 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11195 config->fb_changed = true;
11196
11197 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11198 DRM_DEBUG_KMS("modes are different, full mode set\n");
11199 drm_mode_debug_printmodeline(&set->crtc->mode);
11200 drm_mode_debug_printmodeline(set->mode);
11201 config->mode_changed = true;
11202 }
11203
11204 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11205 set->crtc->base.id, config->mode_changed, config->fb_changed);
11206 }
11207
11208 static int
11209 intel_modeset_stage_output_state(struct drm_device *dev,
11210 struct drm_mode_set *set,
11211 struct intel_set_config *config)
11212 {
11213 struct intel_connector *connector;
11214 struct intel_encoder *encoder;
11215 struct intel_crtc *crtc;
11216 int ro;
11217
11218 /* The upper layers ensure that we either disable a crtc or have a list
11219 * of connectors. For paranoia, double-check this. */
11220 WARN_ON(!set->fb && (set->num_connectors != 0));
11221 WARN_ON(set->fb && (set->num_connectors == 0));
11222
11223 list_for_each_entry(connector, &dev->mode_config.connector_list,
11224 base.head) {
11225 /* Otherwise traverse passed in connector list and get encoders
11226 * for them. */
11227 for (ro = 0; ro < set->num_connectors; ro++) {
11228 if (set->connectors[ro] == &connector->base) {
11229 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11230 break;
11231 }
11232 }
11233
11234 /* If we disable the crtc, disable all its connectors. Also, if
11235 * the connector is on the changing crtc but not on the new
11236 * connector list, disable it. */
11237 if ((!set->fb || ro == set->num_connectors) &&
11238 connector->base.encoder &&
11239 connector->base.encoder->crtc == set->crtc) {
11240 connector->new_encoder = NULL;
11241
11242 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11243 connector->base.base.id,
11244 connector->base.name);
11245 }
11246
11247
11248 if (&connector->new_encoder->base != connector->base.encoder) {
11249 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11250 config->mode_changed = true;
11251 }
11252 }
11253 /* connector->new_encoder is now updated for all connectors. */
11254
11255 /* Update crtc of enabled connectors. */
11256 list_for_each_entry(connector, &dev->mode_config.connector_list,
11257 base.head) {
11258 struct drm_crtc *new_crtc;
11259
11260 if (!connector->new_encoder)
11261 continue;
11262
11263 new_crtc = connector->new_encoder->base.crtc;
11264
11265 for (ro = 0; ro < set->num_connectors; ro++) {
11266 if (set->connectors[ro] == &connector->base)
11267 new_crtc = set->crtc;
11268 }
11269
11270 /* Make sure the new CRTC will work with the encoder */
11271 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11272 new_crtc)) {
11273 return -EINVAL;
11274 }
11275 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11276
11277 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11278 connector->base.base.id,
11279 connector->base.name,
11280 new_crtc->base.id);
11281 }
11282
11283 /* Check for any encoders that needs to be disabled. */
11284 for_each_intel_encoder(dev, encoder) {
11285 int num_connectors = 0;
11286 list_for_each_entry(connector,
11287 &dev->mode_config.connector_list,
11288 base.head) {
11289 if (connector->new_encoder == encoder) {
11290 WARN_ON(!connector->new_encoder->new_crtc);
11291 num_connectors++;
11292 }
11293 }
11294
11295 if (num_connectors == 0)
11296 encoder->new_crtc = NULL;
11297 else if (num_connectors > 1)
11298 return -EINVAL;
11299
11300 /* Only now check for crtc changes so we don't miss encoders
11301 * that will be disabled. */
11302 if (&encoder->new_crtc->base != encoder->base.crtc) {
11303 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11304 config->mode_changed = true;
11305 }
11306 }
11307 /* Now we've also updated encoder->new_crtc for all encoders. */
11308 list_for_each_entry(connector, &dev->mode_config.connector_list,
11309 base.head) {
11310 if (connector->new_encoder)
11311 if (connector->new_encoder != connector->encoder)
11312 connector->encoder = connector->new_encoder;
11313 }
11314 for_each_intel_crtc(dev, crtc) {
11315 crtc->new_enabled = false;
11316
11317 for_each_intel_encoder(dev, encoder) {
11318 if (encoder->new_crtc == crtc) {
11319 crtc->new_enabled = true;
11320 break;
11321 }
11322 }
11323
11324 if (crtc->new_enabled != crtc->base.enabled) {
11325 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11326 crtc->new_enabled ? "en" : "dis");
11327 config->mode_changed = true;
11328 }
11329
11330 if (crtc->new_enabled)
11331 crtc->new_config = &crtc->config;
11332 else
11333 crtc->new_config = NULL;
11334 }
11335
11336 return 0;
11337 }
11338
11339 static void disable_crtc_nofb(struct intel_crtc *crtc)
11340 {
11341 struct drm_device *dev = crtc->base.dev;
11342 struct intel_encoder *encoder;
11343 struct intel_connector *connector;
11344
11345 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11346 pipe_name(crtc->pipe));
11347
11348 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11349 if (connector->new_encoder &&
11350 connector->new_encoder->new_crtc == crtc)
11351 connector->new_encoder = NULL;
11352 }
11353
11354 for_each_intel_encoder(dev, encoder) {
11355 if (encoder->new_crtc == crtc)
11356 encoder->new_crtc = NULL;
11357 }
11358
11359 crtc->new_enabled = false;
11360 crtc->new_config = NULL;
11361 }
11362
11363 static int intel_crtc_set_config(struct drm_mode_set *set)
11364 {
11365 struct drm_device *dev;
11366 struct drm_mode_set save_set;
11367 struct intel_set_config *config;
11368 int ret;
11369
11370 BUG_ON(!set);
11371 BUG_ON(!set->crtc);
11372 BUG_ON(!set->crtc->helper_private);
11373
11374 /* Enforce sane interface api - has been abused by the fb helper. */
11375 BUG_ON(!set->mode && set->fb);
11376 BUG_ON(set->fb && set->num_connectors == 0);
11377
11378 if (set->fb) {
11379 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11380 set->crtc->base.id, set->fb->base.id,
11381 (int)set->num_connectors, set->x, set->y);
11382 } else {
11383 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11384 }
11385
11386 dev = set->crtc->dev;
11387
11388 ret = -ENOMEM;
11389 config = kzalloc(sizeof(*config), GFP_KERNEL);
11390 if (!config)
11391 goto out_config;
11392
11393 ret = intel_set_config_save_state(dev, config);
11394 if (ret)
11395 goto out_config;
11396
11397 save_set.crtc = set->crtc;
11398 save_set.mode = &set->crtc->mode;
11399 save_set.x = set->crtc->x;
11400 save_set.y = set->crtc->y;
11401 save_set.fb = set->crtc->primary->fb;
11402
11403 /* Compute whether we need a full modeset, only an fb base update or no
11404 * change at all. In the future we might also check whether only the
11405 * mode changed, e.g. for LVDS where we only change the panel fitter in
11406 * such cases. */
11407 intel_set_config_compute_mode_changes(set, config);
11408
11409 ret = intel_modeset_stage_output_state(dev, set, config);
11410 if (ret)
11411 goto fail;
11412
11413 if (config->mode_changed) {
11414 ret = intel_set_mode(set->crtc, set->mode,
11415 set->x, set->y, set->fb);
11416 } else if (config->fb_changed) {
11417 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11418
11419 intel_crtc_wait_for_pending_flips(set->crtc);
11420
11421 ret = intel_pipe_set_base(set->crtc,
11422 set->x, set->y, set->fb);
11423
11424 /*
11425 * We need to make sure the primary plane is re-enabled if it
11426 * has previously been turned off.
11427 */
11428 if (!intel_crtc->primary_enabled && ret == 0) {
11429 WARN_ON(!intel_crtc->active);
11430 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11431 }
11432
11433 /*
11434 * In the fastboot case this may be our only check of the
11435 * state after boot. It would be better to only do it on
11436 * the first update, but we don't have a nice way of doing that
11437 * (and really, set_config isn't used much for high freq page
11438 * flipping, so increasing its cost here shouldn't be a big
11439 * deal).
11440 */
11441 if (i915.fastboot && ret == 0)
11442 intel_modeset_check_state(set->crtc->dev);
11443 }
11444
11445 if (ret) {
11446 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11447 set->crtc->base.id, ret);
11448 fail:
11449 intel_set_config_restore_state(dev, config);
11450
11451 /*
11452 * HACK: if the pipe was on, but we didn't have a framebuffer,
11453 * force the pipe off to avoid oopsing in the modeset code
11454 * due to fb==NULL. This should only happen during boot since
11455 * we don't yet reconstruct the FB from the hardware state.
11456 */
11457 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11458 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11459
11460 /* Try to restore the config */
11461 if (config->mode_changed &&
11462 intel_set_mode(save_set.crtc, save_set.mode,
11463 save_set.x, save_set.y, save_set.fb))
11464 DRM_ERROR("failed to restore config after modeset failure\n");
11465 }
11466
11467 out_config:
11468 intel_set_config_free(config);
11469 return ret;
11470 }
11471
11472 static const struct drm_crtc_funcs intel_crtc_funcs = {
11473 .gamma_set = intel_crtc_gamma_set,
11474 .set_config = intel_crtc_set_config,
11475 .destroy = intel_crtc_destroy,
11476 .page_flip = intel_crtc_page_flip,
11477 };
11478
11479 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11480 struct intel_shared_dpll *pll,
11481 struct intel_dpll_hw_state *hw_state)
11482 {
11483 uint32_t val;
11484
11485 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11486 return false;
11487
11488 val = I915_READ(PCH_DPLL(pll->id));
11489 hw_state->dpll = val;
11490 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11491 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11492
11493 return val & DPLL_VCO_ENABLE;
11494 }
11495
11496 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11497 struct intel_shared_dpll *pll)
11498 {
11499 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11500 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11501 }
11502
11503 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11504 struct intel_shared_dpll *pll)
11505 {
11506 /* PCH refclock must be enabled first */
11507 ibx_assert_pch_refclk_enabled(dev_priv);
11508
11509 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11510
11511 /* Wait for the clocks to stabilize. */
11512 POSTING_READ(PCH_DPLL(pll->id));
11513 udelay(150);
11514
11515 /* The pixel multiplier can only be updated once the
11516 * DPLL is enabled and the clocks are stable.
11517 *
11518 * So write it again.
11519 */
11520 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11521 POSTING_READ(PCH_DPLL(pll->id));
11522 udelay(200);
11523 }
11524
11525 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11526 struct intel_shared_dpll *pll)
11527 {
11528 struct drm_device *dev = dev_priv->dev;
11529 struct intel_crtc *crtc;
11530
11531 /* Make sure no transcoder isn't still depending on us. */
11532 for_each_intel_crtc(dev, crtc) {
11533 if (intel_crtc_to_shared_dpll(crtc) == pll)
11534 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11535 }
11536
11537 I915_WRITE(PCH_DPLL(pll->id), 0);
11538 POSTING_READ(PCH_DPLL(pll->id));
11539 udelay(200);
11540 }
11541
11542 static char *ibx_pch_dpll_names[] = {
11543 "PCH DPLL A",
11544 "PCH DPLL B",
11545 };
11546
11547 static void ibx_pch_dpll_init(struct drm_device *dev)
11548 {
11549 struct drm_i915_private *dev_priv = dev->dev_private;
11550 int i;
11551
11552 dev_priv->num_shared_dpll = 2;
11553
11554 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11555 dev_priv->shared_dplls[i].id = i;
11556 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11557 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11558 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11559 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11560 dev_priv->shared_dplls[i].get_hw_state =
11561 ibx_pch_dpll_get_hw_state;
11562 }
11563 }
11564
11565 static void intel_shared_dpll_init(struct drm_device *dev)
11566 {
11567 struct drm_i915_private *dev_priv = dev->dev_private;
11568
11569 if (HAS_DDI(dev))
11570 intel_ddi_pll_init(dev);
11571 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11572 ibx_pch_dpll_init(dev);
11573 else
11574 dev_priv->num_shared_dpll = 0;
11575
11576 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11577 }
11578
11579 static int
11580 intel_primary_plane_disable(struct drm_plane *plane)
11581 {
11582 struct drm_device *dev = plane->dev;
11583 struct intel_crtc *intel_crtc;
11584
11585 if (!plane->fb)
11586 return 0;
11587
11588 BUG_ON(!plane->crtc);
11589
11590 intel_crtc = to_intel_crtc(plane->crtc);
11591
11592 /*
11593 * Even though we checked plane->fb above, it's still possible that
11594 * the primary plane has been implicitly disabled because the crtc
11595 * coordinates given weren't visible, or because we detected
11596 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11597 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11598 * In either case, we need to unpin the FB and let the fb pointer get
11599 * updated, but otherwise we don't need to touch the hardware.
11600 */
11601 if (!intel_crtc->primary_enabled)
11602 goto disable_unpin;
11603
11604 intel_crtc_wait_for_pending_flips(plane->crtc);
11605 intel_disable_primary_hw_plane(plane, plane->crtc);
11606
11607 disable_unpin:
11608 mutex_lock(&dev->struct_mutex);
11609 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11610 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11611 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11612 mutex_unlock(&dev->struct_mutex);
11613 plane->fb = NULL;
11614
11615 return 0;
11616 }
11617
11618 static int
11619 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11620 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11621 unsigned int crtc_w, unsigned int crtc_h,
11622 uint32_t src_x, uint32_t src_y,
11623 uint32_t src_w, uint32_t src_h)
11624 {
11625 struct drm_device *dev = crtc->dev;
11626 struct drm_i915_private *dev_priv = dev->dev_private;
11627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11628 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11629 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11630 struct drm_rect dest = {
11631 /* integer pixels */
11632 .x1 = crtc_x,
11633 .y1 = crtc_y,
11634 .x2 = crtc_x + crtc_w,
11635 .y2 = crtc_y + crtc_h,
11636 };
11637 struct drm_rect src = {
11638 /* 16.16 fixed point */
11639 .x1 = src_x,
11640 .y1 = src_y,
11641 .x2 = src_x + src_w,
11642 .y2 = src_y + src_h,
11643 };
11644 const struct drm_rect clip = {
11645 /* integer pixels */
11646 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11647 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11648 };
11649 const struct {
11650 int crtc_x, crtc_y;
11651 unsigned int crtc_w, crtc_h;
11652 uint32_t src_x, src_y, src_w, src_h;
11653 } orig = {
11654 .crtc_x = crtc_x,
11655 .crtc_y = crtc_y,
11656 .crtc_w = crtc_w,
11657 .crtc_h = crtc_h,
11658 .src_x = src_x,
11659 .src_y = src_y,
11660 .src_w = src_w,
11661 .src_h = src_h,
11662 };
11663 struct intel_plane *intel_plane = to_intel_plane(plane);
11664 bool visible;
11665 int ret;
11666
11667 ret = drm_plane_helper_check_update(plane, crtc, fb,
11668 &src, &dest, &clip,
11669 DRM_PLANE_HELPER_NO_SCALING,
11670 DRM_PLANE_HELPER_NO_SCALING,
11671 false, true, &visible);
11672
11673 if (ret)
11674 return ret;
11675
11676 /*
11677 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11678 * updating the fb pointer, and returning without touching the
11679 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11680 * turn on the display with all planes setup as desired.
11681 */
11682 if (!crtc->enabled) {
11683 mutex_lock(&dev->struct_mutex);
11684
11685 /*
11686 * If we already called setplane while the crtc was disabled,
11687 * we may have an fb pinned; unpin it.
11688 */
11689 if (plane->fb)
11690 intel_unpin_fb_obj(old_obj);
11691
11692 i915_gem_track_fb(old_obj, obj,
11693 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11694
11695 /* Pin and return without programming hardware */
11696 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11697 mutex_unlock(&dev->struct_mutex);
11698
11699 return ret;
11700 }
11701
11702 intel_crtc_wait_for_pending_flips(crtc);
11703
11704 /*
11705 * If clipping results in a non-visible primary plane, we'll disable
11706 * the primary plane. Note that this is a bit different than what
11707 * happens if userspace explicitly disables the plane by passing fb=0
11708 * because plane->fb still gets set and pinned.
11709 */
11710 if (!visible) {
11711 mutex_lock(&dev->struct_mutex);
11712
11713 /*
11714 * Try to pin the new fb first so that we can bail out if we
11715 * fail.
11716 */
11717 if (plane->fb != fb) {
11718 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11719 if (ret) {
11720 mutex_unlock(&dev->struct_mutex);
11721 return ret;
11722 }
11723 }
11724
11725 i915_gem_track_fb(old_obj, obj,
11726 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11727
11728 if (intel_crtc->primary_enabled)
11729 intel_disable_primary_hw_plane(plane, crtc);
11730
11731
11732 if (plane->fb != fb)
11733 if (plane->fb)
11734 intel_unpin_fb_obj(old_obj);
11735
11736 mutex_unlock(&dev->struct_mutex);
11737
11738 } else {
11739 if (intel_crtc && intel_crtc->active &&
11740 intel_crtc->primary_enabled) {
11741 /*
11742 * FBC does not work on some platforms for rotated
11743 * planes, so disable it when rotation is not 0 and
11744 * update it when rotation is set back to 0.
11745 *
11746 * FIXME: This is redundant with the fbc update done in
11747 * the primary plane enable function except that that
11748 * one is done too late. We eventually need to unify
11749 * this.
11750 */
11751 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11752 dev_priv->fbc.plane == intel_crtc->plane &&
11753 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11754 intel_disable_fbc(dev);
11755 }
11756 }
11757 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11758 if (ret)
11759 return ret;
11760
11761 if (!intel_crtc->primary_enabled)
11762 intel_enable_primary_hw_plane(plane, crtc);
11763 }
11764
11765 intel_plane->crtc_x = orig.crtc_x;
11766 intel_plane->crtc_y = orig.crtc_y;
11767 intel_plane->crtc_w = orig.crtc_w;
11768 intel_plane->crtc_h = orig.crtc_h;
11769 intel_plane->src_x = orig.src_x;
11770 intel_plane->src_y = orig.src_y;
11771 intel_plane->src_w = orig.src_w;
11772 intel_plane->src_h = orig.src_h;
11773 intel_plane->obj = obj;
11774
11775 return 0;
11776 }
11777
11778 /* Common destruction function for both primary and cursor planes */
11779 static void intel_plane_destroy(struct drm_plane *plane)
11780 {
11781 struct intel_plane *intel_plane = to_intel_plane(plane);
11782 drm_plane_cleanup(plane);
11783 kfree(intel_plane);
11784 }
11785
11786 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11787 .update_plane = intel_primary_plane_setplane,
11788 .disable_plane = intel_primary_plane_disable,
11789 .destroy = intel_plane_destroy,
11790 .set_property = intel_plane_set_property
11791 };
11792
11793 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11794 int pipe)
11795 {
11796 struct intel_plane *primary;
11797 const uint32_t *intel_primary_formats;
11798 int num_formats;
11799
11800 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11801 if (primary == NULL)
11802 return NULL;
11803
11804 primary->can_scale = false;
11805 primary->max_downscale = 1;
11806 primary->pipe = pipe;
11807 primary->plane = pipe;
11808 primary->rotation = BIT(DRM_ROTATE_0);
11809 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11810 primary->plane = !pipe;
11811
11812 if (INTEL_INFO(dev)->gen <= 3) {
11813 intel_primary_formats = intel_primary_formats_gen2;
11814 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11815 } else {
11816 intel_primary_formats = intel_primary_formats_gen4;
11817 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11818 }
11819
11820 drm_universal_plane_init(dev, &primary->base, 0,
11821 &intel_primary_plane_funcs,
11822 intel_primary_formats, num_formats,
11823 DRM_PLANE_TYPE_PRIMARY);
11824
11825 if (INTEL_INFO(dev)->gen >= 4) {
11826 if (!dev->mode_config.rotation_property)
11827 dev->mode_config.rotation_property =
11828 drm_mode_create_rotation_property(dev,
11829 BIT(DRM_ROTATE_0) |
11830 BIT(DRM_ROTATE_180));
11831 if (dev->mode_config.rotation_property)
11832 drm_object_attach_property(&primary->base.base,
11833 dev->mode_config.rotation_property,
11834 primary->rotation);
11835 }
11836
11837 return &primary->base;
11838 }
11839
11840 static int
11841 intel_cursor_plane_disable(struct drm_plane *plane)
11842 {
11843 if (!plane->fb)
11844 return 0;
11845
11846 BUG_ON(!plane->crtc);
11847
11848 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11849 }
11850
11851 static int
11852 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11853 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11854 unsigned int crtc_w, unsigned int crtc_h,
11855 uint32_t src_x, uint32_t src_y,
11856 uint32_t src_w, uint32_t src_h)
11857 {
11858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11859 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11860 struct drm_i915_gem_object *obj = intel_fb->obj;
11861 struct drm_rect dest = {
11862 /* integer pixels */
11863 .x1 = crtc_x,
11864 .y1 = crtc_y,
11865 .x2 = crtc_x + crtc_w,
11866 .y2 = crtc_y + crtc_h,
11867 };
11868 struct drm_rect src = {
11869 /* 16.16 fixed point */
11870 .x1 = src_x,
11871 .y1 = src_y,
11872 .x2 = src_x + src_w,
11873 .y2 = src_y + src_h,
11874 };
11875 const struct drm_rect clip = {
11876 /* integer pixels */
11877 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11878 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11879 };
11880 bool visible;
11881 int ret;
11882
11883 ret = drm_plane_helper_check_update(plane, crtc, fb,
11884 &src, &dest, &clip,
11885 DRM_PLANE_HELPER_NO_SCALING,
11886 DRM_PLANE_HELPER_NO_SCALING,
11887 true, true, &visible);
11888 if (ret)
11889 return ret;
11890
11891 crtc->cursor_x = crtc_x;
11892 crtc->cursor_y = crtc_y;
11893 if (fb != crtc->cursor->fb) {
11894 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11895 } else {
11896 intel_crtc_update_cursor(crtc, visible);
11897
11898 intel_frontbuffer_flip(crtc->dev,
11899 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11900
11901 return 0;
11902 }
11903 }
11904 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11905 .update_plane = intel_cursor_plane_update,
11906 .disable_plane = intel_cursor_plane_disable,
11907 .destroy = intel_plane_destroy,
11908 };
11909
11910 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11911 int pipe)
11912 {
11913 struct intel_plane *cursor;
11914
11915 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11916 if (cursor == NULL)
11917 return NULL;
11918
11919 cursor->can_scale = false;
11920 cursor->max_downscale = 1;
11921 cursor->pipe = pipe;
11922 cursor->plane = pipe;
11923
11924 drm_universal_plane_init(dev, &cursor->base, 0,
11925 &intel_cursor_plane_funcs,
11926 intel_cursor_formats,
11927 ARRAY_SIZE(intel_cursor_formats),
11928 DRM_PLANE_TYPE_CURSOR);
11929 return &cursor->base;
11930 }
11931
11932 static void intel_crtc_init(struct drm_device *dev, int pipe)
11933 {
11934 struct drm_i915_private *dev_priv = dev->dev_private;
11935 struct intel_crtc *intel_crtc;
11936 struct drm_plane *primary = NULL;
11937 struct drm_plane *cursor = NULL;
11938 int i, ret;
11939
11940 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11941 if (intel_crtc == NULL)
11942 return;
11943
11944 primary = intel_primary_plane_create(dev, pipe);
11945 if (!primary)
11946 goto fail;
11947
11948 cursor = intel_cursor_plane_create(dev, pipe);
11949 if (!cursor)
11950 goto fail;
11951
11952 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11953 cursor, &intel_crtc_funcs);
11954 if (ret)
11955 goto fail;
11956
11957 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11958 for (i = 0; i < 256; i++) {
11959 intel_crtc->lut_r[i] = i;
11960 intel_crtc->lut_g[i] = i;
11961 intel_crtc->lut_b[i] = i;
11962 }
11963
11964 /*
11965 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11966 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11967 */
11968 intel_crtc->pipe = pipe;
11969 intel_crtc->plane = pipe;
11970 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11971 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11972 intel_crtc->plane = !pipe;
11973 }
11974
11975 intel_crtc->cursor_base = ~0;
11976 intel_crtc->cursor_cntl = ~0;
11977 intel_crtc->cursor_size = ~0;
11978
11979 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11980 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11981 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11982 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11983
11984 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11985
11986 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11987 return;
11988
11989 fail:
11990 if (primary)
11991 drm_plane_cleanup(primary);
11992 if (cursor)
11993 drm_plane_cleanup(cursor);
11994 kfree(intel_crtc);
11995 }
11996
11997 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11998 {
11999 struct drm_encoder *encoder = connector->base.encoder;
12000 struct drm_device *dev = connector->base.dev;
12001
12002 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12003
12004 if (!encoder)
12005 return INVALID_PIPE;
12006
12007 return to_intel_crtc(encoder->crtc)->pipe;
12008 }
12009
12010 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12011 struct drm_file *file)
12012 {
12013 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12014 struct drm_crtc *drmmode_crtc;
12015 struct intel_crtc *crtc;
12016
12017 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12018 return -ENODEV;
12019
12020 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12021
12022 if (!drmmode_crtc) {
12023 DRM_ERROR("no such CRTC id\n");
12024 return -ENOENT;
12025 }
12026
12027 crtc = to_intel_crtc(drmmode_crtc);
12028 pipe_from_crtc_id->pipe = crtc->pipe;
12029
12030 return 0;
12031 }
12032
12033 static int intel_encoder_clones(struct intel_encoder *encoder)
12034 {
12035 struct drm_device *dev = encoder->base.dev;
12036 struct intel_encoder *source_encoder;
12037 int index_mask = 0;
12038 int entry = 0;
12039
12040 for_each_intel_encoder(dev, source_encoder) {
12041 if (encoders_cloneable(encoder, source_encoder))
12042 index_mask |= (1 << entry);
12043
12044 entry++;
12045 }
12046
12047 return index_mask;
12048 }
12049
12050 static bool has_edp_a(struct drm_device *dev)
12051 {
12052 struct drm_i915_private *dev_priv = dev->dev_private;
12053
12054 if (!IS_MOBILE(dev))
12055 return false;
12056
12057 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12058 return false;
12059
12060 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12061 return false;
12062
12063 return true;
12064 }
12065
12066 const char *intel_output_name(int output)
12067 {
12068 static const char *names[] = {
12069 [INTEL_OUTPUT_UNUSED] = "Unused",
12070 [INTEL_OUTPUT_ANALOG] = "Analog",
12071 [INTEL_OUTPUT_DVO] = "DVO",
12072 [INTEL_OUTPUT_SDVO] = "SDVO",
12073 [INTEL_OUTPUT_LVDS] = "LVDS",
12074 [INTEL_OUTPUT_TVOUT] = "TV",
12075 [INTEL_OUTPUT_HDMI] = "HDMI",
12076 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12077 [INTEL_OUTPUT_EDP] = "eDP",
12078 [INTEL_OUTPUT_DSI] = "DSI",
12079 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12080 };
12081
12082 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12083 return "Invalid";
12084
12085 return names[output];
12086 }
12087
12088 static bool intel_crt_present(struct drm_device *dev)
12089 {
12090 struct drm_i915_private *dev_priv = dev->dev_private;
12091
12092 if (IS_ULT(dev))
12093 return false;
12094
12095 if (IS_CHERRYVIEW(dev))
12096 return false;
12097
12098 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12099 return false;
12100
12101 return true;
12102 }
12103
12104 static void intel_setup_outputs(struct drm_device *dev)
12105 {
12106 struct drm_i915_private *dev_priv = dev->dev_private;
12107 struct intel_encoder *encoder;
12108 bool dpd_is_edp = false;
12109
12110 intel_lvds_init(dev);
12111
12112 if (intel_crt_present(dev))
12113 intel_crt_init(dev);
12114
12115 if (HAS_DDI(dev)) {
12116 int found;
12117
12118 /* Haswell uses DDI functions to detect digital outputs */
12119 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12120 /* DDI A only supports eDP */
12121 if (found)
12122 intel_ddi_init(dev, PORT_A);
12123
12124 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12125 * register */
12126 found = I915_READ(SFUSE_STRAP);
12127
12128 if (found & SFUSE_STRAP_DDIB_DETECTED)
12129 intel_ddi_init(dev, PORT_B);
12130 if (found & SFUSE_STRAP_DDIC_DETECTED)
12131 intel_ddi_init(dev, PORT_C);
12132 if (found & SFUSE_STRAP_DDID_DETECTED)
12133 intel_ddi_init(dev, PORT_D);
12134 } else if (HAS_PCH_SPLIT(dev)) {
12135 int found;
12136 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12137
12138 if (has_edp_a(dev))
12139 intel_dp_init(dev, DP_A, PORT_A);
12140
12141 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12142 /* PCH SDVOB multiplex with HDMIB */
12143 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12144 if (!found)
12145 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12146 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12147 intel_dp_init(dev, PCH_DP_B, PORT_B);
12148 }
12149
12150 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12151 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12152
12153 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12154 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12155
12156 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12157 intel_dp_init(dev, PCH_DP_C, PORT_C);
12158
12159 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12160 intel_dp_init(dev, PCH_DP_D, PORT_D);
12161 } else if (IS_VALLEYVIEW(dev)) {
12162 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
12163 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12164 PORT_B);
12165 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
12166 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12167 }
12168
12169 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
12170 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12171 PORT_C);
12172 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
12173 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12174 }
12175
12176 if (IS_CHERRYVIEW(dev)) {
12177 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
12178 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12179 PORT_D);
12180 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12181 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12182 }
12183 }
12184
12185 intel_dsi_init(dev);
12186 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12187 bool found = false;
12188
12189 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12190 DRM_DEBUG_KMS("probing SDVOB\n");
12191 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12192 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12193 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12194 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12195 }
12196
12197 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12198 intel_dp_init(dev, DP_B, PORT_B);
12199 }
12200
12201 /* Before G4X SDVOC doesn't have its own detect register */
12202
12203 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12204 DRM_DEBUG_KMS("probing SDVOC\n");
12205 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12206 }
12207
12208 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12209
12210 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12211 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12212 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12213 }
12214 if (SUPPORTS_INTEGRATED_DP(dev))
12215 intel_dp_init(dev, DP_C, PORT_C);
12216 }
12217
12218 if (SUPPORTS_INTEGRATED_DP(dev) &&
12219 (I915_READ(DP_D) & DP_DETECTED))
12220 intel_dp_init(dev, DP_D, PORT_D);
12221 } else if (IS_GEN2(dev))
12222 intel_dvo_init(dev);
12223
12224 if (SUPPORTS_TV(dev))
12225 intel_tv_init(dev);
12226
12227 intel_edp_psr_init(dev);
12228
12229 for_each_intel_encoder(dev, encoder) {
12230 encoder->base.possible_crtcs = encoder->crtc_mask;
12231 encoder->base.possible_clones =
12232 intel_encoder_clones(encoder);
12233 }
12234
12235 intel_init_pch_refclk(dev);
12236
12237 drm_helper_move_panel_connectors_to_head(dev);
12238 }
12239
12240 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12241 {
12242 struct drm_device *dev = fb->dev;
12243 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12244
12245 drm_framebuffer_cleanup(fb);
12246 mutex_lock(&dev->struct_mutex);
12247 WARN_ON(!intel_fb->obj->framebuffer_references--);
12248 drm_gem_object_unreference(&intel_fb->obj->base);
12249 mutex_unlock(&dev->struct_mutex);
12250 kfree(intel_fb);
12251 }
12252
12253 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12254 struct drm_file *file,
12255 unsigned int *handle)
12256 {
12257 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12258 struct drm_i915_gem_object *obj = intel_fb->obj;
12259
12260 return drm_gem_handle_create(file, &obj->base, handle);
12261 }
12262
12263 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12264 .destroy = intel_user_framebuffer_destroy,
12265 .create_handle = intel_user_framebuffer_create_handle,
12266 };
12267
12268 static int intel_framebuffer_init(struct drm_device *dev,
12269 struct intel_framebuffer *intel_fb,
12270 struct drm_mode_fb_cmd2 *mode_cmd,
12271 struct drm_i915_gem_object *obj)
12272 {
12273 int aligned_height;
12274 int pitch_limit;
12275 int ret;
12276
12277 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12278
12279 if (obj->tiling_mode == I915_TILING_Y) {
12280 DRM_DEBUG("hardware does not support tiling Y\n");
12281 return -EINVAL;
12282 }
12283
12284 if (mode_cmd->pitches[0] & 63) {
12285 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12286 mode_cmd->pitches[0]);
12287 return -EINVAL;
12288 }
12289
12290 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12291 pitch_limit = 32*1024;
12292 } else if (INTEL_INFO(dev)->gen >= 4) {
12293 if (obj->tiling_mode)
12294 pitch_limit = 16*1024;
12295 else
12296 pitch_limit = 32*1024;
12297 } else if (INTEL_INFO(dev)->gen >= 3) {
12298 if (obj->tiling_mode)
12299 pitch_limit = 8*1024;
12300 else
12301 pitch_limit = 16*1024;
12302 } else
12303 /* XXX DSPC is limited to 4k tiled */
12304 pitch_limit = 8*1024;
12305
12306 if (mode_cmd->pitches[0] > pitch_limit) {
12307 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12308 obj->tiling_mode ? "tiled" : "linear",
12309 mode_cmd->pitches[0], pitch_limit);
12310 return -EINVAL;
12311 }
12312
12313 if (obj->tiling_mode != I915_TILING_NONE &&
12314 mode_cmd->pitches[0] != obj->stride) {
12315 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12316 mode_cmd->pitches[0], obj->stride);
12317 return -EINVAL;
12318 }
12319
12320 /* Reject formats not supported by any plane early. */
12321 switch (mode_cmd->pixel_format) {
12322 case DRM_FORMAT_C8:
12323 case DRM_FORMAT_RGB565:
12324 case DRM_FORMAT_XRGB8888:
12325 case DRM_FORMAT_ARGB8888:
12326 break;
12327 case DRM_FORMAT_XRGB1555:
12328 case DRM_FORMAT_ARGB1555:
12329 if (INTEL_INFO(dev)->gen > 3) {
12330 DRM_DEBUG("unsupported pixel format: %s\n",
12331 drm_get_format_name(mode_cmd->pixel_format));
12332 return -EINVAL;
12333 }
12334 break;
12335 case DRM_FORMAT_XBGR8888:
12336 case DRM_FORMAT_ABGR8888:
12337 case DRM_FORMAT_XRGB2101010:
12338 case DRM_FORMAT_ARGB2101010:
12339 case DRM_FORMAT_XBGR2101010:
12340 case DRM_FORMAT_ABGR2101010:
12341 if (INTEL_INFO(dev)->gen < 4) {
12342 DRM_DEBUG("unsupported pixel format: %s\n",
12343 drm_get_format_name(mode_cmd->pixel_format));
12344 return -EINVAL;
12345 }
12346 break;
12347 case DRM_FORMAT_YUYV:
12348 case DRM_FORMAT_UYVY:
12349 case DRM_FORMAT_YVYU:
12350 case DRM_FORMAT_VYUY:
12351 if (INTEL_INFO(dev)->gen < 5) {
12352 DRM_DEBUG("unsupported pixel format: %s\n",
12353 drm_get_format_name(mode_cmd->pixel_format));
12354 return -EINVAL;
12355 }
12356 break;
12357 default:
12358 DRM_DEBUG("unsupported pixel format: %s\n",
12359 drm_get_format_name(mode_cmd->pixel_format));
12360 return -EINVAL;
12361 }
12362
12363 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12364 if (mode_cmd->offsets[0] != 0)
12365 return -EINVAL;
12366
12367 aligned_height = intel_align_height(dev, mode_cmd->height,
12368 obj->tiling_mode);
12369 /* FIXME drm helper for size checks (especially planar formats)? */
12370 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12371 return -EINVAL;
12372
12373 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12374 intel_fb->obj = obj;
12375 intel_fb->obj->framebuffer_references++;
12376
12377 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12378 if (ret) {
12379 DRM_ERROR("framebuffer init failed %d\n", ret);
12380 return ret;
12381 }
12382
12383 return 0;
12384 }
12385
12386 static struct drm_framebuffer *
12387 intel_user_framebuffer_create(struct drm_device *dev,
12388 struct drm_file *filp,
12389 struct drm_mode_fb_cmd2 *mode_cmd)
12390 {
12391 struct drm_i915_gem_object *obj;
12392
12393 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12394 mode_cmd->handles[0]));
12395 if (&obj->base == NULL)
12396 return ERR_PTR(-ENOENT);
12397
12398 return intel_framebuffer_create(dev, mode_cmd, obj);
12399 }
12400
12401 #ifndef CONFIG_DRM_I915_FBDEV
12402 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12403 {
12404 }
12405 #endif
12406
12407 static const struct drm_mode_config_funcs intel_mode_funcs = {
12408 .fb_create = intel_user_framebuffer_create,
12409 .output_poll_changed = intel_fbdev_output_poll_changed,
12410 };
12411
12412 /* Set up chip specific display functions */
12413 static void intel_init_display(struct drm_device *dev)
12414 {
12415 struct drm_i915_private *dev_priv = dev->dev_private;
12416
12417 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12418 dev_priv->display.find_dpll = g4x_find_best_dpll;
12419 else if (IS_CHERRYVIEW(dev))
12420 dev_priv->display.find_dpll = chv_find_best_dpll;
12421 else if (IS_VALLEYVIEW(dev))
12422 dev_priv->display.find_dpll = vlv_find_best_dpll;
12423 else if (IS_PINEVIEW(dev))
12424 dev_priv->display.find_dpll = pnv_find_best_dpll;
12425 else
12426 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12427
12428 if (HAS_DDI(dev)) {
12429 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12430 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12431 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12432 dev_priv->display.crtc_enable = haswell_crtc_enable;
12433 dev_priv->display.crtc_disable = haswell_crtc_disable;
12434 dev_priv->display.off = ironlake_crtc_off;
12435 dev_priv->display.update_primary_plane =
12436 ironlake_update_primary_plane;
12437 } else if (HAS_PCH_SPLIT(dev)) {
12438 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12439 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12440 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12441 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12442 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12443 dev_priv->display.off = ironlake_crtc_off;
12444 dev_priv->display.update_primary_plane =
12445 ironlake_update_primary_plane;
12446 } else if (IS_VALLEYVIEW(dev)) {
12447 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12448 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12449 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12450 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12451 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12452 dev_priv->display.off = i9xx_crtc_off;
12453 dev_priv->display.update_primary_plane =
12454 i9xx_update_primary_plane;
12455 } else {
12456 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12457 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12458 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12459 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12460 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12461 dev_priv->display.off = i9xx_crtc_off;
12462 dev_priv->display.update_primary_plane =
12463 i9xx_update_primary_plane;
12464 }
12465
12466 /* Returns the core display clock speed */
12467 if (IS_VALLEYVIEW(dev))
12468 dev_priv->display.get_display_clock_speed =
12469 valleyview_get_display_clock_speed;
12470 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12471 dev_priv->display.get_display_clock_speed =
12472 i945_get_display_clock_speed;
12473 else if (IS_I915G(dev))
12474 dev_priv->display.get_display_clock_speed =
12475 i915_get_display_clock_speed;
12476 else if (IS_I945GM(dev) || IS_845G(dev))
12477 dev_priv->display.get_display_clock_speed =
12478 i9xx_misc_get_display_clock_speed;
12479 else if (IS_PINEVIEW(dev))
12480 dev_priv->display.get_display_clock_speed =
12481 pnv_get_display_clock_speed;
12482 else if (IS_I915GM(dev))
12483 dev_priv->display.get_display_clock_speed =
12484 i915gm_get_display_clock_speed;
12485 else if (IS_I865G(dev))
12486 dev_priv->display.get_display_clock_speed =
12487 i865_get_display_clock_speed;
12488 else if (IS_I85X(dev))
12489 dev_priv->display.get_display_clock_speed =
12490 i855_get_display_clock_speed;
12491 else /* 852, 830 */
12492 dev_priv->display.get_display_clock_speed =
12493 i830_get_display_clock_speed;
12494
12495 if (IS_G4X(dev)) {
12496 dev_priv->display.write_eld = g4x_write_eld;
12497 } else if (IS_GEN5(dev)) {
12498 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12499 dev_priv->display.write_eld = ironlake_write_eld;
12500 } else if (IS_GEN6(dev)) {
12501 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12502 dev_priv->display.write_eld = ironlake_write_eld;
12503 dev_priv->display.modeset_global_resources =
12504 snb_modeset_global_resources;
12505 } else if (IS_IVYBRIDGE(dev)) {
12506 /* FIXME: detect B0+ stepping and use auto training */
12507 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12508 dev_priv->display.write_eld = ironlake_write_eld;
12509 dev_priv->display.modeset_global_resources =
12510 ivb_modeset_global_resources;
12511 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12512 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12513 dev_priv->display.write_eld = haswell_write_eld;
12514 dev_priv->display.modeset_global_resources =
12515 haswell_modeset_global_resources;
12516 } else if (IS_VALLEYVIEW(dev)) {
12517 dev_priv->display.modeset_global_resources =
12518 valleyview_modeset_global_resources;
12519 dev_priv->display.write_eld = ironlake_write_eld;
12520 }
12521
12522 /* Default just returns -ENODEV to indicate unsupported */
12523 dev_priv->display.queue_flip = intel_default_queue_flip;
12524
12525 switch (INTEL_INFO(dev)->gen) {
12526 case 2:
12527 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12528 break;
12529
12530 case 3:
12531 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12532 break;
12533
12534 case 4:
12535 case 5:
12536 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12537 break;
12538
12539 case 6:
12540 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12541 break;
12542 case 7:
12543 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12544 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12545 break;
12546 }
12547
12548 intel_panel_init_backlight_funcs(dev);
12549 }
12550
12551 /*
12552 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12553 * resume, or other times. This quirk makes sure that's the case for
12554 * affected systems.
12555 */
12556 static void quirk_pipea_force(struct drm_device *dev)
12557 {
12558 struct drm_i915_private *dev_priv = dev->dev_private;
12559
12560 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12561 DRM_INFO("applying pipe a force quirk\n");
12562 }
12563
12564 /*
12565 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12566 */
12567 static void quirk_ssc_force_disable(struct drm_device *dev)
12568 {
12569 struct drm_i915_private *dev_priv = dev->dev_private;
12570 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12571 DRM_INFO("applying lvds SSC disable quirk\n");
12572 }
12573
12574 /*
12575 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12576 * brightness value
12577 */
12578 static void quirk_invert_brightness(struct drm_device *dev)
12579 {
12580 struct drm_i915_private *dev_priv = dev->dev_private;
12581 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12582 DRM_INFO("applying inverted panel brightness quirk\n");
12583 }
12584
12585 /* Some VBT's incorrectly indicate no backlight is present */
12586 static void quirk_backlight_present(struct drm_device *dev)
12587 {
12588 struct drm_i915_private *dev_priv = dev->dev_private;
12589 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12590 DRM_INFO("applying backlight present quirk\n");
12591 }
12592
12593 struct intel_quirk {
12594 int device;
12595 int subsystem_vendor;
12596 int subsystem_device;
12597 void (*hook)(struct drm_device *dev);
12598 };
12599
12600 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12601 struct intel_dmi_quirk {
12602 void (*hook)(struct drm_device *dev);
12603 const struct dmi_system_id (*dmi_id_list)[];
12604 };
12605
12606 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12607 {
12608 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12609 return 1;
12610 }
12611
12612 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12613 {
12614 .dmi_id_list = &(const struct dmi_system_id[]) {
12615 {
12616 .callback = intel_dmi_reverse_brightness,
12617 .ident = "NCR Corporation",
12618 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12619 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12620 },
12621 },
12622 { } /* terminating entry */
12623 },
12624 .hook = quirk_invert_brightness,
12625 },
12626 };
12627
12628 static struct intel_quirk intel_quirks[] = {
12629 /* HP Mini needs pipe A force quirk (LP: #322104) */
12630 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12631
12632 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12633 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12634
12635 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12636 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12637
12638 /* Lenovo U160 cannot use SSC on LVDS */
12639 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12640
12641 /* Sony Vaio Y cannot use SSC on LVDS */
12642 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12643
12644 /* Acer Aspire 5734Z must invert backlight brightness */
12645 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12646
12647 /* Acer/eMachines G725 */
12648 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12649
12650 /* Acer/eMachines e725 */
12651 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12652
12653 /* Acer/Packard Bell NCL20 */
12654 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12655
12656 /* Acer Aspire 4736Z */
12657 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12658
12659 /* Acer Aspire 5336 */
12660 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12661
12662 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12663 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12664
12665 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12666 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12667
12668 /* HP Chromebook 14 (Celeron 2955U) */
12669 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12670 };
12671
12672 static void intel_init_quirks(struct drm_device *dev)
12673 {
12674 struct pci_dev *d = dev->pdev;
12675 int i;
12676
12677 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12678 struct intel_quirk *q = &intel_quirks[i];
12679
12680 if (d->device == q->device &&
12681 (d->subsystem_vendor == q->subsystem_vendor ||
12682 q->subsystem_vendor == PCI_ANY_ID) &&
12683 (d->subsystem_device == q->subsystem_device ||
12684 q->subsystem_device == PCI_ANY_ID))
12685 q->hook(dev);
12686 }
12687 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12688 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12689 intel_dmi_quirks[i].hook(dev);
12690 }
12691 }
12692
12693 /* Disable the VGA plane that we never use */
12694 static void i915_disable_vga(struct drm_device *dev)
12695 {
12696 struct drm_i915_private *dev_priv = dev->dev_private;
12697 u8 sr1;
12698 u32 vga_reg = i915_vgacntrl_reg(dev);
12699
12700 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12701 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12702 outb(SR01, VGA_SR_INDEX);
12703 sr1 = inb(VGA_SR_DATA);
12704 outb(sr1 | 1<<5, VGA_SR_DATA);
12705 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12706 udelay(300);
12707
12708 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12709 POSTING_READ(vga_reg);
12710 }
12711
12712 void intel_modeset_init_hw(struct drm_device *dev)
12713 {
12714 intel_prepare_ddi(dev);
12715
12716 if (IS_VALLEYVIEW(dev))
12717 vlv_update_cdclk(dev);
12718
12719 intel_init_clock_gating(dev);
12720
12721 intel_enable_gt_powersave(dev);
12722 }
12723
12724 void intel_modeset_suspend_hw(struct drm_device *dev)
12725 {
12726 intel_suspend_hw(dev);
12727 }
12728
12729 void intel_modeset_init(struct drm_device *dev)
12730 {
12731 struct drm_i915_private *dev_priv = dev->dev_private;
12732 int sprite, ret;
12733 enum pipe pipe;
12734 struct intel_crtc *crtc;
12735
12736 drm_mode_config_init(dev);
12737
12738 dev->mode_config.min_width = 0;
12739 dev->mode_config.min_height = 0;
12740
12741 dev->mode_config.preferred_depth = 24;
12742 dev->mode_config.prefer_shadow = 1;
12743
12744 dev->mode_config.funcs = &intel_mode_funcs;
12745
12746 intel_init_quirks(dev);
12747
12748 intel_init_pm(dev);
12749
12750 if (INTEL_INFO(dev)->num_pipes == 0)
12751 return;
12752
12753 intel_init_display(dev);
12754
12755 if (IS_GEN2(dev)) {
12756 dev->mode_config.max_width = 2048;
12757 dev->mode_config.max_height = 2048;
12758 } else if (IS_GEN3(dev)) {
12759 dev->mode_config.max_width = 4096;
12760 dev->mode_config.max_height = 4096;
12761 } else {
12762 dev->mode_config.max_width = 8192;
12763 dev->mode_config.max_height = 8192;
12764 }
12765
12766 if (IS_845G(dev) || IS_I865G(dev)) {
12767 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12768 dev->mode_config.cursor_height = 1023;
12769 } else if (IS_GEN2(dev)) {
12770 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12771 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12772 } else {
12773 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12774 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12775 }
12776
12777 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12778
12779 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12780 INTEL_INFO(dev)->num_pipes,
12781 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12782
12783 for_each_pipe(dev_priv, pipe) {
12784 intel_crtc_init(dev, pipe);
12785 for_each_sprite(pipe, sprite) {
12786 ret = intel_plane_init(dev, pipe, sprite);
12787 if (ret)
12788 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12789 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12790 }
12791 }
12792
12793 intel_init_dpio(dev);
12794
12795 intel_shared_dpll_init(dev);
12796
12797 /* Just disable it once at startup */
12798 i915_disable_vga(dev);
12799 intel_setup_outputs(dev);
12800
12801 /* Just in case the BIOS is doing something questionable. */
12802 intel_disable_fbc(dev);
12803
12804 drm_modeset_lock_all(dev);
12805 intel_modeset_setup_hw_state(dev, false);
12806 drm_modeset_unlock_all(dev);
12807
12808 for_each_intel_crtc(dev, crtc) {
12809 if (!crtc->active)
12810 continue;
12811
12812 /*
12813 * Note that reserving the BIOS fb up front prevents us
12814 * from stuffing other stolen allocations like the ring
12815 * on top. This prevents some ugliness at boot time, and
12816 * can even allow for smooth boot transitions if the BIOS
12817 * fb is large enough for the active pipe configuration.
12818 */
12819 if (dev_priv->display.get_plane_config) {
12820 dev_priv->display.get_plane_config(crtc,
12821 &crtc->plane_config);
12822 /*
12823 * If the fb is shared between multiple heads, we'll
12824 * just get the first one.
12825 */
12826 intel_find_plane_obj(crtc, &crtc->plane_config);
12827 }
12828 }
12829 }
12830
12831 static void intel_enable_pipe_a(struct drm_device *dev)
12832 {
12833 struct intel_connector *connector;
12834 struct drm_connector *crt = NULL;
12835 struct intel_load_detect_pipe load_detect_temp;
12836 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12837
12838 /* We can't just switch on the pipe A, we need to set things up with a
12839 * proper mode and output configuration. As a gross hack, enable pipe A
12840 * by enabling the load detect pipe once. */
12841 list_for_each_entry(connector,
12842 &dev->mode_config.connector_list,
12843 base.head) {
12844 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12845 crt = &connector->base;
12846 break;
12847 }
12848 }
12849
12850 if (!crt)
12851 return;
12852
12853 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12854 intel_release_load_detect_pipe(crt, &load_detect_temp);
12855 }
12856
12857 static bool
12858 intel_check_plane_mapping(struct intel_crtc *crtc)
12859 {
12860 struct drm_device *dev = crtc->base.dev;
12861 struct drm_i915_private *dev_priv = dev->dev_private;
12862 u32 reg, val;
12863
12864 if (INTEL_INFO(dev)->num_pipes == 1)
12865 return true;
12866
12867 reg = DSPCNTR(!crtc->plane);
12868 val = I915_READ(reg);
12869
12870 if ((val & DISPLAY_PLANE_ENABLE) &&
12871 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12872 return false;
12873
12874 return true;
12875 }
12876
12877 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12878 {
12879 struct drm_device *dev = crtc->base.dev;
12880 struct drm_i915_private *dev_priv = dev->dev_private;
12881 u32 reg;
12882
12883 /* Clear any frame start delays used for debugging left by the BIOS */
12884 reg = PIPECONF(crtc->config.cpu_transcoder);
12885 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12886
12887 /* restore vblank interrupts to correct state */
12888 if (crtc->active)
12889 drm_vblank_on(dev, crtc->pipe);
12890 else
12891 drm_vblank_off(dev, crtc->pipe);
12892
12893 /* We need to sanitize the plane -> pipe mapping first because this will
12894 * disable the crtc (and hence change the state) if it is wrong. Note
12895 * that gen4+ has a fixed plane -> pipe mapping. */
12896 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12897 struct intel_connector *connector;
12898 bool plane;
12899
12900 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12901 crtc->base.base.id);
12902
12903 /* Pipe has the wrong plane attached and the plane is active.
12904 * Temporarily change the plane mapping and disable everything
12905 * ... */
12906 plane = crtc->plane;
12907 crtc->plane = !plane;
12908 crtc->primary_enabled = true;
12909 dev_priv->display.crtc_disable(&crtc->base);
12910 crtc->plane = plane;
12911
12912 /* ... and break all links. */
12913 list_for_each_entry(connector, &dev->mode_config.connector_list,
12914 base.head) {
12915 if (connector->encoder->base.crtc != &crtc->base)
12916 continue;
12917
12918 connector->base.dpms = DRM_MODE_DPMS_OFF;
12919 connector->base.encoder = NULL;
12920 }
12921 /* multiple connectors may have the same encoder:
12922 * handle them and break crtc link separately */
12923 list_for_each_entry(connector, &dev->mode_config.connector_list,
12924 base.head)
12925 if (connector->encoder->base.crtc == &crtc->base) {
12926 connector->encoder->base.crtc = NULL;
12927 connector->encoder->connectors_active = false;
12928 }
12929
12930 WARN_ON(crtc->active);
12931 crtc->base.enabled = false;
12932 }
12933
12934 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12935 crtc->pipe == PIPE_A && !crtc->active) {
12936 /* BIOS forgot to enable pipe A, this mostly happens after
12937 * resume. Force-enable the pipe to fix this, the update_dpms
12938 * call below we restore the pipe to the right state, but leave
12939 * the required bits on. */
12940 intel_enable_pipe_a(dev);
12941 }
12942
12943 /* Adjust the state of the output pipe according to whether we
12944 * have active connectors/encoders. */
12945 intel_crtc_update_dpms(&crtc->base);
12946
12947 if (crtc->active != crtc->base.enabled) {
12948 struct intel_encoder *encoder;
12949
12950 /* This can happen either due to bugs in the get_hw_state
12951 * functions or because the pipe is force-enabled due to the
12952 * pipe A quirk. */
12953 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12954 crtc->base.base.id,
12955 crtc->base.enabled ? "enabled" : "disabled",
12956 crtc->active ? "enabled" : "disabled");
12957
12958 crtc->base.enabled = crtc->active;
12959
12960 /* Because we only establish the connector -> encoder ->
12961 * crtc links if something is active, this means the
12962 * crtc is now deactivated. Break the links. connector
12963 * -> encoder links are only establish when things are
12964 * actually up, hence no need to break them. */
12965 WARN_ON(crtc->active);
12966
12967 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12968 WARN_ON(encoder->connectors_active);
12969 encoder->base.crtc = NULL;
12970 }
12971 }
12972
12973 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12974 /*
12975 * We start out with underrun reporting disabled to avoid races.
12976 * For correct bookkeeping mark this on active crtcs.
12977 *
12978 * Also on gmch platforms we dont have any hardware bits to
12979 * disable the underrun reporting. Which means we need to start
12980 * out with underrun reporting disabled also on inactive pipes,
12981 * since otherwise we'll complain about the garbage we read when
12982 * e.g. coming up after runtime pm.
12983 *
12984 * No protection against concurrent access is required - at
12985 * worst a fifo underrun happens which also sets this to false.
12986 */
12987 crtc->cpu_fifo_underrun_disabled = true;
12988 crtc->pch_fifo_underrun_disabled = true;
12989
12990 update_scanline_offset(crtc);
12991 }
12992 }
12993
12994 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12995 {
12996 struct intel_connector *connector;
12997 struct drm_device *dev = encoder->base.dev;
12998
12999 /* We need to check both for a crtc link (meaning that the
13000 * encoder is active and trying to read from a pipe) and the
13001 * pipe itself being active. */
13002 bool has_active_crtc = encoder->base.crtc &&
13003 to_intel_crtc(encoder->base.crtc)->active;
13004
13005 if (encoder->connectors_active && !has_active_crtc) {
13006 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13007 encoder->base.base.id,
13008 encoder->base.name);
13009
13010 /* Connector is active, but has no active pipe. This is
13011 * fallout from our resume register restoring. Disable
13012 * the encoder manually again. */
13013 if (encoder->base.crtc) {
13014 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13015 encoder->base.base.id,
13016 encoder->base.name);
13017 encoder->disable(encoder);
13018 if (encoder->post_disable)
13019 encoder->post_disable(encoder);
13020 }
13021 encoder->base.crtc = NULL;
13022 encoder->connectors_active = false;
13023
13024 /* Inconsistent output/port/pipe state happens presumably due to
13025 * a bug in one of the get_hw_state functions. Or someplace else
13026 * in our code, like the register restore mess on resume. Clamp
13027 * things to off as a safer default. */
13028 list_for_each_entry(connector,
13029 &dev->mode_config.connector_list,
13030 base.head) {
13031 if (connector->encoder != encoder)
13032 continue;
13033 connector->base.dpms = DRM_MODE_DPMS_OFF;
13034 connector->base.encoder = NULL;
13035 }
13036 }
13037 /* Enabled encoders without active connectors will be fixed in
13038 * the crtc fixup. */
13039 }
13040
13041 void i915_redisable_vga_power_on(struct drm_device *dev)
13042 {
13043 struct drm_i915_private *dev_priv = dev->dev_private;
13044 u32 vga_reg = i915_vgacntrl_reg(dev);
13045
13046 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13047 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13048 i915_disable_vga(dev);
13049 }
13050 }
13051
13052 void i915_redisable_vga(struct drm_device *dev)
13053 {
13054 struct drm_i915_private *dev_priv = dev->dev_private;
13055
13056 /* This function can be called both from intel_modeset_setup_hw_state or
13057 * at a very early point in our resume sequence, where the power well
13058 * structures are not yet restored. Since this function is at a very
13059 * paranoid "someone might have enabled VGA while we were not looking"
13060 * level, just check if the power well is enabled instead of trying to
13061 * follow the "don't touch the power well if we don't need it" policy
13062 * the rest of the driver uses. */
13063 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
13064 return;
13065
13066 i915_redisable_vga_power_on(dev);
13067 }
13068
13069 static bool primary_get_hw_state(struct intel_crtc *crtc)
13070 {
13071 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13072
13073 if (!crtc->active)
13074 return false;
13075
13076 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13077 }
13078
13079 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13080 {
13081 struct drm_i915_private *dev_priv = dev->dev_private;
13082 enum pipe pipe;
13083 struct intel_crtc *crtc;
13084 struct intel_encoder *encoder;
13085 struct intel_connector *connector;
13086 int i;
13087
13088 for_each_intel_crtc(dev, crtc) {
13089 memset(&crtc->config, 0, sizeof(crtc->config));
13090
13091 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13092
13093 crtc->active = dev_priv->display.get_pipe_config(crtc,
13094 &crtc->config);
13095
13096 crtc->base.enabled = crtc->active;
13097 crtc->primary_enabled = primary_get_hw_state(crtc);
13098
13099 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13100 crtc->base.base.id,
13101 crtc->active ? "enabled" : "disabled");
13102 }
13103
13104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13105 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13106
13107 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
13108 pll->active = 0;
13109 for_each_intel_crtc(dev, crtc) {
13110 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13111 pll->active++;
13112 }
13113 pll->refcount = pll->active;
13114
13115 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13116 pll->name, pll->refcount, pll->on);
13117
13118 if (pll->refcount)
13119 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13120 }
13121
13122 for_each_intel_encoder(dev, encoder) {
13123 pipe = 0;
13124
13125 if (encoder->get_hw_state(encoder, &pipe)) {
13126 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13127 encoder->base.crtc = &crtc->base;
13128 encoder->get_config(encoder, &crtc->config);
13129 } else {
13130 encoder->base.crtc = NULL;
13131 }
13132
13133 encoder->connectors_active = false;
13134 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13135 encoder->base.base.id,
13136 encoder->base.name,
13137 encoder->base.crtc ? "enabled" : "disabled",
13138 pipe_name(pipe));
13139 }
13140
13141 list_for_each_entry(connector, &dev->mode_config.connector_list,
13142 base.head) {
13143 if (connector->get_hw_state(connector)) {
13144 connector->base.dpms = DRM_MODE_DPMS_ON;
13145 connector->encoder->connectors_active = true;
13146 connector->base.encoder = &connector->encoder->base;
13147 } else {
13148 connector->base.dpms = DRM_MODE_DPMS_OFF;
13149 connector->base.encoder = NULL;
13150 }
13151 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13152 connector->base.base.id,
13153 connector->base.name,
13154 connector->base.encoder ? "enabled" : "disabled");
13155 }
13156 }
13157
13158 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13159 * and i915 state tracking structures. */
13160 void intel_modeset_setup_hw_state(struct drm_device *dev,
13161 bool force_restore)
13162 {
13163 struct drm_i915_private *dev_priv = dev->dev_private;
13164 enum pipe pipe;
13165 struct intel_crtc *crtc;
13166 struct intel_encoder *encoder;
13167 int i;
13168
13169 intel_modeset_readout_hw_state(dev);
13170
13171 /*
13172 * Now that we have the config, copy it to each CRTC struct
13173 * Note that this could go away if we move to using crtc_config
13174 * checking everywhere.
13175 */
13176 for_each_intel_crtc(dev, crtc) {
13177 if (crtc->active && i915.fastboot) {
13178 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13179 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13180 crtc->base.base.id);
13181 drm_mode_debug_printmodeline(&crtc->base.mode);
13182 }
13183 }
13184
13185 /* HW state is read out, now we need to sanitize this mess. */
13186 for_each_intel_encoder(dev, encoder) {
13187 intel_sanitize_encoder(encoder);
13188 }
13189
13190 for_each_pipe(dev_priv, pipe) {
13191 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13192 intel_sanitize_crtc(crtc);
13193 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13194 }
13195
13196 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13197 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13198
13199 if (!pll->on || pll->active)
13200 continue;
13201
13202 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13203
13204 pll->disable(dev_priv, pll);
13205 pll->on = false;
13206 }
13207
13208 if (HAS_PCH_SPLIT(dev))
13209 ilk_wm_get_hw_state(dev);
13210
13211 if (force_restore) {
13212 i915_redisable_vga(dev);
13213
13214 /*
13215 * We need to use raw interfaces for restoring state to avoid
13216 * checking (bogus) intermediate states.
13217 */
13218 for_each_pipe(dev_priv, pipe) {
13219 struct drm_crtc *crtc =
13220 dev_priv->pipe_to_crtc_mapping[pipe];
13221
13222 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13223 crtc->primary->fb);
13224 }
13225 } else {
13226 intel_modeset_update_staged_output_state(dev);
13227 }
13228
13229 intel_modeset_check_state(dev);
13230 }
13231
13232 void intel_modeset_gem_init(struct drm_device *dev)
13233 {
13234 struct drm_crtc *c;
13235 struct drm_i915_gem_object *obj;
13236
13237 mutex_lock(&dev->struct_mutex);
13238 intel_init_gt_powersave(dev);
13239 mutex_unlock(&dev->struct_mutex);
13240
13241 intel_modeset_init_hw(dev);
13242
13243 intel_setup_overlay(dev);
13244
13245 /*
13246 * Make sure any fbs we allocated at startup are properly
13247 * pinned & fenced. When we do the allocation it's too early
13248 * for this.
13249 */
13250 mutex_lock(&dev->struct_mutex);
13251 for_each_crtc(dev, c) {
13252 obj = intel_fb_obj(c->primary->fb);
13253 if (obj == NULL)
13254 continue;
13255
13256 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13257 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13258 to_intel_crtc(c)->pipe);
13259 drm_framebuffer_unreference(c->primary->fb);
13260 c->primary->fb = NULL;
13261 }
13262 }
13263 mutex_unlock(&dev->struct_mutex);
13264 }
13265
13266 void intel_connector_unregister(struct intel_connector *intel_connector)
13267 {
13268 struct drm_connector *connector = &intel_connector->base;
13269
13270 intel_panel_destroy_backlight(connector);
13271 drm_connector_unregister(connector);
13272 }
13273
13274 void intel_modeset_cleanup(struct drm_device *dev)
13275 {
13276 struct drm_i915_private *dev_priv = dev->dev_private;
13277 struct drm_connector *connector;
13278
13279 /*
13280 * Interrupts and polling as the first thing to avoid creating havoc.
13281 * Too much stuff here (turning of rps, connectors, ...) would
13282 * experience fancy races otherwise.
13283 */
13284 drm_irq_uninstall(dev);
13285 intel_hpd_cancel_work(dev_priv);
13286 dev_priv->pm._irqs_disabled = true;
13287
13288 /*
13289 * Due to the hpd irq storm handling the hotplug work can re-arm the
13290 * poll handlers. Hence disable polling after hpd handling is shut down.
13291 */
13292 drm_kms_helper_poll_fini(dev);
13293
13294 mutex_lock(&dev->struct_mutex);
13295
13296 intel_unregister_dsm_handler();
13297
13298 intel_disable_fbc(dev);
13299
13300 intel_disable_gt_powersave(dev);
13301
13302 ironlake_teardown_rc6(dev);
13303
13304 mutex_unlock(&dev->struct_mutex);
13305
13306 /* flush any delayed tasks or pending work */
13307 flush_scheduled_work();
13308
13309 /* destroy the backlight and sysfs files before encoders/connectors */
13310 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13311 struct intel_connector *intel_connector;
13312
13313 intel_connector = to_intel_connector(connector);
13314 intel_connector->unregister(intel_connector);
13315 }
13316
13317 drm_mode_config_cleanup(dev);
13318
13319 intel_cleanup_overlay(dev);
13320
13321 mutex_lock(&dev->struct_mutex);
13322 intel_cleanup_gt_powersave(dev);
13323 mutex_unlock(&dev->struct_mutex);
13324 }
13325
13326 /*
13327 * Return which encoder is currently attached for connector.
13328 */
13329 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13330 {
13331 return &intel_attached_encoder(connector)->base;
13332 }
13333
13334 void intel_connector_attach_encoder(struct intel_connector *connector,
13335 struct intel_encoder *encoder)
13336 {
13337 connector->encoder = encoder;
13338 drm_mode_connector_attach_encoder(&connector->base,
13339 &encoder->base);
13340 }
13341
13342 /*
13343 * set vga decode state - true == enable VGA decode
13344 */
13345 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13346 {
13347 struct drm_i915_private *dev_priv = dev->dev_private;
13348 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13349 u16 gmch_ctrl;
13350
13351 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13352 DRM_ERROR("failed to read control word\n");
13353 return -EIO;
13354 }
13355
13356 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13357 return 0;
13358
13359 if (state)
13360 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13361 else
13362 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13363
13364 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13365 DRM_ERROR("failed to write control word\n");
13366 return -EIO;
13367 }
13368
13369 return 0;
13370 }
13371
13372 struct intel_display_error_state {
13373
13374 u32 power_well_driver;
13375
13376 int num_transcoders;
13377
13378 struct intel_cursor_error_state {
13379 u32 control;
13380 u32 position;
13381 u32 base;
13382 u32 size;
13383 } cursor[I915_MAX_PIPES];
13384
13385 struct intel_pipe_error_state {
13386 bool power_domain_on;
13387 u32 source;
13388 u32 stat;
13389 } pipe[I915_MAX_PIPES];
13390
13391 struct intel_plane_error_state {
13392 u32 control;
13393 u32 stride;
13394 u32 size;
13395 u32 pos;
13396 u32 addr;
13397 u32 surface;
13398 u32 tile_offset;
13399 } plane[I915_MAX_PIPES];
13400
13401 struct intel_transcoder_error_state {
13402 bool power_domain_on;
13403 enum transcoder cpu_transcoder;
13404
13405 u32 conf;
13406
13407 u32 htotal;
13408 u32 hblank;
13409 u32 hsync;
13410 u32 vtotal;
13411 u32 vblank;
13412 u32 vsync;
13413 } transcoder[4];
13414 };
13415
13416 struct intel_display_error_state *
13417 intel_display_capture_error_state(struct drm_device *dev)
13418 {
13419 struct drm_i915_private *dev_priv = dev->dev_private;
13420 struct intel_display_error_state *error;
13421 int transcoders[] = {
13422 TRANSCODER_A,
13423 TRANSCODER_B,
13424 TRANSCODER_C,
13425 TRANSCODER_EDP,
13426 };
13427 int i;
13428
13429 if (INTEL_INFO(dev)->num_pipes == 0)
13430 return NULL;
13431
13432 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13433 if (error == NULL)
13434 return NULL;
13435
13436 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13437 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13438
13439 for_each_pipe(dev_priv, i) {
13440 error->pipe[i].power_domain_on =
13441 intel_display_power_enabled_unlocked(dev_priv,
13442 POWER_DOMAIN_PIPE(i));
13443 if (!error->pipe[i].power_domain_on)
13444 continue;
13445
13446 error->cursor[i].control = I915_READ(CURCNTR(i));
13447 error->cursor[i].position = I915_READ(CURPOS(i));
13448 error->cursor[i].base = I915_READ(CURBASE(i));
13449
13450 error->plane[i].control = I915_READ(DSPCNTR(i));
13451 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13452 if (INTEL_INFO(dev)->gen <= 3) {
13453 error->plane[i].size = I915_READ(DSPSIZE(i));
13454 error->plane[i].pos = I915_READ(DSPPOS(i));
13455 }
13456 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13457 error->plane[i].addr = I915_READ(DSPADDR(i));
13458 if (INTEL_INFO(dev)->gen >= 4) {
13459 error->plane[i].surface = I915_READ(DSPSURF(i));
13460 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13461 }
13462
13463 error->pipe[i].source = I915_READ(PIPESRC(i));
13464
13465 if (HAS_GMCH_DISPLAY(dev))
13466 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13467 }
13468
13469 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13470 if (HAS_DDI(dev_priv->dev))
13471 error->num_transcoders++; /* Account for eDP. */
13472
13473 for (i = 0; i < error->num_transcoders; i++) {
13474 enum transcoder cpu_transcoder = transcoders[i];
13475
13476 error->transcoder[i].power_domain_on =
13477 intel_display_power_enabled_unlocked(dev_priv,
13478 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13479 if (!error->transcoder[i].power_domain_on)
13480 continue;
13481
13482 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13483
13484 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13485 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13486 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13487 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13488 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13489 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13490 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13491 }
13492
13493 return error;
13494 }
13495
13496 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13497
13498 void
13499 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13500 struct drm_device *dev,
13501 struct intel_display_error_state *error)
13502 {
13503 struct drm_i915_private *dev_priv = dev->dev_private;
13504 int i;
13505
13506 if (!error)
13507 return;
13508
13509 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13510 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13511 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13512 error->power_well_driver);
13513 for_each_pipe(dev_priv, i) {
13514 err_printf(m, "Pipe [%d]:\n", i);
13515 err_printf(m, " Power: %s\n",
13516 error->pipe[i].power_domain_on ? "on" : "off");
13517 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13518 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13519
13520 err_printf(m, "Plane [%d]:\n", i);
13521 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13522 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13523 if (INTEL_INFO(dev)->gen <= 3) {
13524 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13525 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13526 }
13527 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13528 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13529 if (INTEL_INFO(dev)->gen >= 4) {
13530 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13531 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13532 }
13533
13534 err_printf(m, "Cursor [%d]:\n", i);
13535 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13536 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13537 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13538 }
13539
13540 for (i = 0; i < error->num_transcoders; i++) {
13541 err_printf(m, "CPU transcoder: %c\n",
13542 transcoder_name(error->transcoder[i].cpu_transcoder));
13543 err_printf(m, " Power: %s\n",
13544 error->transcoder[i].power_domain_on ? "on" : "off");
13545 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13546 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13547 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13548 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13549 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13550 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13551 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13552 }
13553 }
13554
13555 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13556 {
13557 struct intel_crtc *crtc;
13558
13559 for_each_intel_crtc(dev, crtc) {
13560 struct intel_unpin_work *work;
13561 unsigned long irqflags;
13562
13563 spin_lock_irqsave(&dev->event_lock, irqflags);
13564
13565 work = crtc->unpin_work;
13566
13567 if (work && work->event &&
13568 work->event->base.file_priv == file) {
13569 kfree(work->event);
13570 work->event = NULL;
13571 }
13572
13573 spin_unlock_irqrestore(&dev->event_lock, irqflags);
13574 }
13575 }
Linux kernel - Deliverables
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