2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_pch_rawclk(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
88 WARN_ON(!HAS_PCH_SPLIT(dev
));
90 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
94 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
95 int target
, int refclk
, intel_clock_t
*match_clock
,
96 intel_clock_t
*best_clock
);
98 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
99 int target
, int refclk
, intel_clock_t
*match_clock
,
100 intel_clock_t
*best_clock
);
103 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
104 int target
, int refclk
, intel_clock_t
*match_clock
,
105 intel_clock_t
*best_clock
);
107 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
108 int target
, int refclk
, intel_clock_t
*match_clock
,
109 intel_clock_t
*best_clock
);
112 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
116 static inline u32
/* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device
*dev
)
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
121 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
126 static const intel_limit_t intel_limits_i8xx_dvo
= {
127 .dot
= { .min
= 25000, .max
= 350000 },
128 .vco
= { .min
= 930000, .max
= 1400000 },
129 .n
= { .min
= 3, .max
= 16 },
130 .m
= { .min
= 96, .max
= 140 },
131 .m1
= { .min
= 18, .max
= 26 },
132 .m2
= { .min
= 6, .max
= 16 },
133 .p
= { .min
= 4, .max
= 128 },
134 .p1
= { .min
= 2, .max
= 33 },
135 .p2
= { .dot_limit
= 165000,
136 .p2_slow
= 4, .p2_fast
= 2 },
137 .find_pll
= intel_find_best_PLL
,
140 static const intel_limit_t intel_limits_i8xx_lvds
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 1, .max
= 6 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 14, .p2_fast
= 7 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i9xx_sdvo
= {
155 .dot
= { .min
= 20000, .max
= 400000 },
156 .vco
= { .min
= 1400000, .max
= 2800000 },
157 .n
= { .min
= 1, .max
= 6 },
158 .m
= { .min
= 70, .max
= 120 },
159 .m1
= { .min
= 10, .max
= 22 },
160 .m2
= { .min
= 5, .max
= 9 },
161 .p
= { .min
= 5, .max
= 80 },
162 .p1
= { .min
= 1, .max
= 8 },
163 .p2
= { .dot_limit
= 200000,
164 .p2_slow
= 10, .p2_fast
= 5 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_lvds
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 10, .max
= 22 },
174 .m2
= { .min
= 5, .max
= 9 },
175 .p
= { .min
= 7, .max
= 98 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 112000,
178 .p2_slow
= 14, .p2_fast
= 7 },
179 .find_pll
= intel_find_best_PLL
,
183 static const intel_limit_t intel_limits_g4x_sdvo
= {
184 .dot
= { .min
= 25000, .max
= 270000 },
185 .vco
= { .min
= 1750000, .max
= 3500000},
186 .n
= { .min
= 1, .max
= 4 },
187 .m
= { .min
= 104, .max
= 138 },
188 .m1
= { .min
= 17, .max
= 23 },
189 .m2
= { .min
= 5, .max
= 11 },
190 .p
= { .min
= 10, .max
= 30 },
191 .p1
= { .min
= 1, .max
= 3},
192 .p2
= { .dot_limit
= 270000,
196 .find_pll
= intel_g4x_find_best_PLL
,
199 static const intel_limit_t intel_limits_g4x_hdmi
= {
200 .dot
= { .min
= 22000, .max
= 400000 },
201 .vco
= { .min
= 1750000, .max
= 3500000},
202 .n
= { .min
= 1, .max
= 4 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 16, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 5, .max
= 80 },
207 .p1
= { .min
= 1, .max
= 8},
208 .p2
= { .dot_limit
= 165000,
209 .p2_slow
= 10, .p2_fast
= 5 },
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
214 .dot
= { .min
= 20000, .max
= 115000 },
215 .vco
= { .min
= 1750000, .max
= 3500000 },
216 .n
= { .min
= 1, .max
= 3 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 28, .max
= 112 },
221 .p1
= { .min
= 2, .max
= 8 },
222 .p2
= { .dot_limit
= 0,
223 .p2_slow
= 14, .p2_fast
= 14
225 .find_pll
= intel_g4x_find_best_PLL
,
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
229 .dot
= { .min
= 80000, .max
= 224000 },
230 .vco
= { .min
= 1750000, .max
= 3500000 },
231 .n
= { .min
= 1, .max
= 3 },
232 .m
= { .min
= 104, .max
= 138 },
233 .m1
= { .min
= 17, .max
= 23 },
234 .m2
= { .min
= 5, .max
= 11 },
235 .p
= { .min
= 14, .max
= 42 },
236 .p1
= { .min
= 2, .max
= 6 },
237 .p2
= { .dot_limit
= 0,
238 .p2_slow
= 7, .p2_fast
= 7
240 .find_pll
= intel_g4x_find_best_PLL
,
243 static const intel_limit_t intel_limits_g4x_display_port
= {
244 .dot
= { .min
= 161670, .max
= 227000 },
245 .vco
= { .min
= 1750000, .max
= 3500000},
246 .n
= { .min
= 1, .max
= 2 },
247 .m
= { .min
= 97, .max
= 108 },
248 .m1
= { .min
= 0x10, .max
= 0x12 },
249 .m2
= { .min
= 0x05, .max
= 0x06 },
250 .p
= { .min
= 10, .max
= 20 },
251 .p1
= { .min
= 1, .max
= 2},
252 .p2
= { .dot_limit
= 0,
253 .p2_slow
= 10, .p2_fast
= 10 },
254 .find_pll
= intel_find_pll_g4x_dp
,
257 static const intel_limit_t intel_limits_pineview_sdvo
= {
258 .dot
= { .min
= 20000, .max
= 400000},
259 .vco
= { .min
= 1700000, .max
= 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n
= { .min
= 3, .max
= 6 },
262 .m
= { .min
= 2, .max
= 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1
= { .min
= 0, .max
= 0 },
265 .m2
= { .min
= 0, .max
= 254 },
266 .p
= { .min
= 5, .max
= 80 },
267 .p1
= { .min
= 1, .max
= 8 },
268 .p2
= { .dot_limit
= 200000,
269 .p2_slow
= 10, .p2_fast
= 5 },
270 .find_pll
= intel_find_best_PLL
,
273 static const intel_limit_t intel_limits_pineview_lvds
= {
274 .dot
= { .min
= 20000, .max
= 400000 },
275 .vco
= { .min
= 1700000, .max
= 3500000 },
276 .n
= { .min
= 3, .max
= 6 },
277 .m
= { .min
= 2, .max
= 256 },
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 7, .max
= 112 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 112000,
283 .p2_slow
= 14, .p2_fast
= 14 },
284 .find_pll
= intel_find_best_PLL
,
287 /* Ironlake / Sandybridge
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
292 static const intel_limit_t intel_limits_ironlake_dac
= {
293 .dot
= { .min
= 25000, .max
= 350000 },
294 .vco
= { .min
= 1760000, .max
= 3510000 },
295 .n
= { .min
= 1, .max
= 5 },
296 .m
= { .min
= 79, .max
= 127 },
297 .m1
= { .min
= 12, .max
= 22 },
298 .m2
= { .min
= 5, .max
= 9 },
299 .p
= { .min
= 5, .max
= 80 },
300 .p1
= { .min
= 1, .max
= 8 },
301 .p2
= { .dot_limit
= 225000,
302 .p2_slow
= 10, .p2_fast
= 5 },
303 .find_pll
= intel_g4x_find_best_PLL
,
306 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 3 },
310 .m
= { .min
= 79, .max
= 118 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 28, .max
= 112 },
314 .p1
= { .min
= 2, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 14, .p2_fast
= 14 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 127 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 14, .max
= 56 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 7, .p2_fast
= 7 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
336 .dot
= { .min
= 25000, .max
= 350000 },
337 .vco
= { .min
= 1760000, .max
= 3510000 },
338 .n
= { .min
= 1, .max
= 2 },
339 .m
= { .min
= 79, .max
= 126 },
340 .m1
= { .min
= 12, .max
= 22 },
341 .m2
= { .min
= 5, .max
= 9 },
342 .p
= { .min
= 28, .max
= 112 },
343 .p1
= { .min
= 2, .max
= 8 },
344 .p2
= { .dot_limit
= 225000,
345 .p2_slow
= 14, .p2_fast
= 14 },
346 .find_pll
= intel_g4x_find_best_PLL
,
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 3 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 14, .max
= 42 },
357 .p1
= { .min
= 2, .max
= 6 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 7, .p2_fast
= 7 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_display_port
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000},
366 .n
= { .min
= 1, .max
= 2 },
367 .m
= { .min
= 81, .max
= 90 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 10, .max
= 20 },
371 .p1
= { .min
= 1, .max
= 2},
372 .p2
= { .dot_limit
= 0,
373 .p2_slow
= 10, .p2_fast
= 10 },
374 .find_pll
= intel_find_pll_ironlake_dp
,
377 static const intel_limit_t intel_limits_vlv_dac
= {
378 .dot
= { .min
= 25000, .max
= 270000 },
379 .vco
= { .min
= 4000000, .max
= 6000000 },
380 .n
= { .min
= 1, .max
= 7 },
381 .m
= { .min
= 22, .max
= 450 }, /* guess */
382 .m1
= { .min
= 2, .max
= 3 },
383 .m2
= { .min
= 11, .max
= 156 },
384 .p
= { .min
= 10, .max
= 30 },
385 .p1
= { .min
= 2, .max
= 3 },
386 .p2
= { .dot_limit
= 270000,
387 .p2_slow
= 2, .p2_fast
= 20 },
388 .find_pll
= intel_vlv_find_best_pll
,
391 static const intel_limit_t intel_limits_vlv_hdmi
= {
392 .dot
= { .min
= 20000, .max
= 165000 },
393 .vco
= { .min
= 4000000, .max
= 5994000},
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 60, .max
= 300 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_dp
= {
406 .dot
= { .min
= 25000, .max
= 270000 },
407 .vco
= { .min
= 4000000, .max
= 6000000 },
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 22, .max
= 450 },
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
424 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
430 I915_WRITE(DPIO_REG
, reg
);
431 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
437 val
= I915_READ(DPIO_DATA
);
440 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
444 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
449 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
455 I915_WRITE(DPIO_DATA
, val
);
456 I915_WRITE(DPIO_REG
, reg
);
457 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
463 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
466 static void vlv_init_dpio(struct drm_device
*dev
)
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL
, 0);
472 POSTING_READ(DPIO_CTL
);
473 I915_WRITE(DPIO_CTL
, 1);
474 POSTING_READ(DPIO_CTL
);
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
483 static const struct dmi_system_id intel_dual_link_lvds
[] = {
485 .callback
= intel_dual_link_lvds_callback
,
486 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
488 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
492 { } /* terminating entry */
495 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode
> 0)
502 return i915_lvds_channel_mode
== 2;
504 if (dmi_check_system(intel_dual_link_lvds
))
507 if (dev_priv
->lvds_val
)
508 val
= dev_priv
->lvds_val
;
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
515 val
= I915_READ(reg
);
516 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
517 val
= dev_priv
->bios_lvds_val
;
518 dev_priv
->lvds_val
= val
;
520 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
523 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
526 struct drm_device
*dev
= crtc
->dev
;
527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
528 const intel_limit_t
*limit
;
530 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
531 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
532 /* LVDS dual channel */
533 if (refclk
== 100000)
534 limit
= &intel_limits_ironlake_dual_lvds_100m
;
536 limit
= &intel_limits_ironlake_dual_lvds
;
538 if (refclk
== 100000)
539 limit
= &intel_limits_ironlake_single_lvds_100m
;
541 limit
= &intel_limits_ironlake_single_lvds
;
543 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
545 limit
= &intel_limits_ironlake_display_port
;
547 limit
= &intel_limits_ironlake_dac
;
552 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
554 struct drm_device
*dev
= crtc
->dev
;
555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
556 const intel_limit_t
*limit
;
558 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
559 if (is_dual_link_lvds(dev_priv
, LVDS
))
560 /* LVDS with dual channel */
561 limit
= &intel_limits_g4x_dual_channel_lvds
;
563 /* LVDS with dual channel */
564 limit
= &intel_limits_g4x_single_channel_lvds
;
565 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
566 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
567 limit
= &intel_limits_g4x_hdmi
;
568 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
569 limit
= &intel_limits_g4x_sdvo
;
570 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
571 limit
= &intel_limits_g4x_display_port
;
572 } else /* The option is for other outputs */
573 limit
= &intel_limits_i9xx_sdvo
;
578 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
580 struct drm_device
*dev
= crtc
->dev
;
581 const intel_limit_t
*limit
;
583 if (HAS_PCH_SPLIT(dev
))
584 limit
= intel_ironlake_limit(crtc
, refclk
);
585 else if (IS_G4X(dev
)) {
586 limit
= intel_g4x_limit(crtc
);
587 } else if (IS_PINEVIEW(dev
)) {
588 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
589 limit
= &intel_limits_pineview_lvds
;
591 limit
= &intel_limits_pineview_sdvo
;
592 } else if (IS_VALLEYVIEW(dev
)) {
593 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
594 limit
= &intel_limits_vlv_dac
;
595 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
596 limit
= &intel_limits_vlv_hdmi
;
598 limit
= &intel_limits_vlv_dp
;
599 } else if (!IS_GEN2(dev
)) {
600 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
601 limit
= &intel_limits_i9xx_lvds
;
603 limit
= &intel_limits_i9xx_sdvo
;
605 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
606 limit
= &intel_limits_i8xx_lvds
;
608 limit
= &intel_limits_i8xx_dvo
;
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
616 clock
->m
= clock
->m2
+ 2;
617 clock
->p
= clock
->p1
* clock
->p2
;
618 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
619 clock
->dot
= clock
->vco
/ clock
->p
;
622 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
624 if (IS_PINEVIEW(dev
)) {
625 pineview_clock(refclk
, clock
);
628 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
629 clock
->p
= clock
->p1
* clock
->p2
;
630 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
631 clock
->dot
= clock
->vco
/ clock
->p
;
635 * Returns whether any output on the specified pipe is of the specified type
637 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
639 struct drm_device
*dev
= crtc
->dev
;
640 struct intel_encoder
*encoder
;
642 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
643 if (encoder
->type
== type
)
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
655 static bool intel_PLL_is_valid(struct drm_device
*dev
,
656 const intel_limit_t
*limit
,
657 const intel_clock_t
*clock
)
659 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
662 INTELPllInvalid("p out of range\n");
663 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
670 INTELPllInvalid("m out of range\n");
671 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
672 INTELPllInvalid("n out of range\n");
673 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
678 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
679 INTELPllInvalid("dot out of range\n");
685 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
686 int target
, int refclk
, intel_clock_t
*match_clock
,
687 intel_clock_t
*best_clock
)
690 struct drm_device
*dev
= crtc
->dev
;
691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
695 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
696 (I915_READ(LVDS
)) != 0) {
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
703 if (is_dual_link_lvds(dev_priv
, LVDS
))
704 clock
.p2
= limit
->p2
.p2_fast
;
706 clock
.p2
= limit
->p2
.p2_slow
;
708 if (target
< limit
->p2
.dot_limit
)
709 clock
.p2
= limit
->p2
.p2_slow
;
711 clock
.p2
= limit
->p2
.p2_fast
;
714 memset(best_clock
, 0, sizeof(*best_clock
));
716 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
718 for (clock
.m2
= limit
->m2
.min
;
719 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
720 /* m1 is always 0 in Pineview */
721 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
723 for (clock
.n
= limit
->n
.min
;
724 clock
.n
<= limit
->n
.max
; clock
.n
++) {
725 for (clock
.p1
= limit
->p1
.min
;
726 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
729 intel_clock(dev
, refclk
, &clock
);
730 if (!intel_PLL_is_valid(dev
, limit
,
734 clock
.p
!= match_clock
->p
)
737 this_err
= abs(clock
.dot
- target
);
738 if (this_err
< err
) {
747 return (err
!= target
);
751 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
752 int target
, int refclk
, intel_clock_t
*match_clock
,
753 intel_clock_t
*best_clock
)
755 struct drm_device
*dev
= crtc
->dev
;
756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
760 /* approximately equals target * 0.00585 */
761 int err_most
= (target
>> 8) + (target
>> 9);
764 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
767 if (HAS_PCH_SPLIT(dev
))
771 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
773 clock
.p2
= limit
->p2
.p2_fast
;
775 clock
.p2
= limit
->p2
.p2_slow
;
777 if (target
< limit
->p2
.dot_limit
)
778 clock
.p2
= limit
->p2
.p2_slow
;
780 clock
.p2
= limit
->p2
.p2_fast
;
783 memset(best_clock
, 0, sizeof(*best_clock
));
784 max_n
= limit
->n
.max
;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock
.m1
= limit
->m1
.max
;
789 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
790 for (clock
.m2
= limit
->m2
.max
;
791 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
792 for (clock
.p1
= limit
->p1
.max
;
793 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
796 intel_clock(dev
, refclk
, &clock
);
797 if (!intel_PLL_is_valid(dev
, limit
,
801 clock
.p
!= match_clock
->p
)
804 this_err
= abs(clock
.dot
- target
);
805 if (this_err
< err_most
) {
819 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
820 int target
, int refclk
, intel_clock_t
*match_clock
,
821 intel_clock_t
*best_clock
)
823 struct drm_device
*dev
= crtc
->dev
;
826 if (target
< 200000) {
839 intel_clock(dev
, refclk
, &clock
);
840 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
846 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
847 int target
, int refclk
, intel_clock_t
*match_clock
,
848 intel_clock_t
*best_clock
)
851 if (target
< 200000) {
864 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
865 clock
.p
= (clock
.p1
* clock
.p2
);
866 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
868 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
872 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
873 int target
, int refclk
, intel_clock_t
*match_clock
,
874 intel_clock_t
*best_clock
)
876 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
878 u32 updrate
, minupdate
, fracbits
, p
;
879 unsigned long bestppm
, ppm
, absppm
;
883 dotclk
= target
* 1000;
886 fastclk
= dotclk
/ (2*100);
890 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
891 bestm1
= bestm2
= bestp1
= bestp2
= 0;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
895 updrate
= refclk
/ n
;
896 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
897 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
903 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
904 refclk
) / (2*refclk
));
907 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
908 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
909 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
910 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
914 if (absppm
< bestppm
- 10) {
931 best_clock
->n
= bestn
;
932 best_clock
->m1
= bestm1
;
933 best_clock
->m2
= bestm2
;
934 best_clock
->p1
= bestp1
;
935 best_clock
->p2
= bestp2
;
940 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
943 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
946 return intel_crtc
->cpu_transcoder
;
949 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
954 frame
= I915_READ(frame_reg
);
956 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
961 * intel_wait_for_vblank - wait for vblank on a given pipe
963 * @pipe: pipe to wait for
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
968 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
971 int pipestat_reg
= PIPESTAT(pipe
);
973 if (INTEL_INFO(dev
)->gen
>= 5) {
974 ironlake_wait_for_vblank(dev
, pipe
);
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
991 I915_WRITE(pipestat_reg
,
992 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg
) &
996 PIPE_VBLANK_INTERRUPT_STATUS
,
998 DRM_DEBUG_KMS("vblank wait timed out\n");
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1004 * @pipe: pipe to wait for
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1018 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1024 if (INTEL_INFO(dev
)->gen
>= 4) {
1025 int reg
= PIPECONF(cpu_transcoder
);
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1030 WARN(1, "pipe_off wait timed out\n");
1032 u32 last_line
, line_mask
;
1033 int reg
= PIPEDSL(pipe
);
1034 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1037 line_mask
= DSL_LINEMASK_GEN2
;
1039 line_mask
= DSL_LINEMASK_GEN3
;
1041 /* Wait for the display line to settle */
1043 last_line
= I915_READ(reg
) & line_mask
;
1045 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1046 time_after(timeout
, jiffies
));
1047 if (time_after(jiffies
, timeout
))
1048 WARN(1, "pipe_off wait timed out\n");
1052 static const char *state_string(bool enabled
)
1054 return enabled
? "on" : "off";
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private
*dev_priv
,
1059 enum pipe pipe
, bool state
)
1066 val
= I915_READ(reg
);
1067 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1068 WARN(cur_state
!= state
,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state
), state_string(cur_state
));
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1076 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1077 struct intel_pch_pll
*pll
,
1078 struct intel_crtc
*crtc
,
1084 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1090 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1093 val
= I915_READ(pll
->pll_reg
);
1094 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1095 WARN(cur_state
!= state
,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1103 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1104 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1105 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state
, crtc
->pipe
, pch_dpll
)) {
1108 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1109 WARN(cur_state
!= state
,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll
->pll_reg
== _PCH_DPLL_B
,
1112 state_string(state
),
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1121 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1122 enum pipe pipe
, bool state
)
1127 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1130 if (IS_HASWELL(dev_priv
->dev
)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1133 val
= I915_READ(reg
);
1134 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 cur_state
= !!(val
& FDI_TX_ENABLE
);
1140 WARN(cur_state
!= state
,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state
), state_string(cur_state
));
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1147 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1148 enum pipe pipe
, bool state
)
1154 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1158 reg
= FDI_RX_CTL(pipe
);
1159 val
= I915_READ(reg
);
1160 cur_state
= !!(val
& FDI_RX_ENABLE
);
1162 WARN(cur_state
!= state
,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state
), state_string(cur_state
));
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv
->info
->gen
== 5)
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv
->dev
))
1183 reg
= FDI_TX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1194 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1198 reg
= FDI_RX_CTL(pipe
);
1199 val
= I915_READ(reg
);
1200 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1203 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1206 int pp_reg
, lvds_reg
;
1208 enum pipe panel_pipe
= PIPE_A
;
1211 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1212 pp_reg
= PCH_PP_CONTROL
;
1213 lvds_reg
= PCH_LVDS
;
1215 pp_reg
= PP_CONTROL
;
1219 val
= I915_READ(pp_reg
);
1220 if (!(val
& PANEL_POWER_ON
) ||
1221 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1224 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1225 panel_pipe
= PIPE_B
;
1227 WARN(panel_pipe
== pipe
&& locked
,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 void assert_pipe(struct drm_i915_private
*dev_priv
,
1233 enum pipe pipe
, bool state
)
1238 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1245 reg
= PIPECONF(cpu_transcoder
);
1246 val
= I915_READ(reg
);
1247 cur_state
= !!(val
& PIPECONF_ENABLE
);
1248 WARN(cur_state
!= state
,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1253 static void assert_plane(struct drm_i915_private
*dev_priv
,
1254 enum plane plane
, bool state
)
1260 reg
= DSPCNTR(plane
);
1261 val
= I915_READ(reg
);
1262 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1263 WARN(cur_state
!= state
,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane
), state_string(state
), state_string(cur_state
));
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1271 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1280 reg
= DSPCNTR(pipe
);
1281 val
= I915_READ(reg
);
1282 WARN((val
& DISPLAY_PLANE_ENABLE
),
1283 "plane %c assertion failure, should be disabled but not\n",
1288 /* Need to check both planes against the pipe */
1289 for (i
= 0; i
< 2; i
++) {
1291 val
= I915_READ(reg
);
1292 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1293 DISPPLANE_SEL_PIPE_SHIFT
;
1294 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i
), pipe_name(pipe
));
1300 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1305 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1310 val
= I915_READ(PCH_DREF_CONTROL
);
1311 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1312 DREF_SUPERSPREAD_SOURCE_MASK
));
1313 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1316 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1323 reg
= TRANSCONF(pipe
);
1324 val
= I915_READ(reg
);
1325 enabled
= !!(val
& TRANS_ENABLE
);
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1332 enum pipe pipe
, u32 port_sel
, u32 val
)
1334 if ((val
& DP_PORT_EN
) == 0)
1337 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1338 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1339 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1340 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1343 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1349 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1350 enum pipe pipe
, u32 val
)
1352 if ((val
& PORT_ENABLE
) == 0)
1355 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1356 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1359 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1365 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1366 enum pipe pipe
, u32 val
)
1368 if ((val
& LVDS_PORT_EN
) == 0)
1371 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1372 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1375 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1381 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1382 enum pipe pipe
, u32 val
)
1384 if ((val
& ADPA_DAC_ENABLE
) == 0)
1386 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1387 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1390 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1396 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1397 enum pipe pipe
, int reg
, u32 port_sel
)
1399 u32 val
= I915_READ(reg
);
1400 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg
, pipe_name(pipe
));
1404 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1405 && (val
& DP_PIPEB_SELECT
),
1406 "IBX PCH dp port still using transcoder B\n");
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1410 enum pipe pipe
, int reg
)
1412 u32 val
= I915_READ(reg
);
1413 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg
, pipe_name(pipe
));
1417 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1418 && (val
& SDVO_PIPE_B_SELECT
),
1419 "IBX PCH hdmi port still using transcoder B\n");
1422 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1428 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1429 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1430 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1433 val
= I915_READ(reg
);
1434 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1439 val
= I915_READ(reg
);
1440 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1444 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1445 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1446 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1458 * Note! This is for pre-ILK only.
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1462 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1472 assert_panel_unlocked(dev_priv
, pipe
);
1475 val
= I915_READ(reg
);
1476 val
|= DPLL_VCO_ENABLE
;
1478 /* We do this three times for luck */
1479 I915_WRITE(reg
, val
);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg
, val
);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg
, val
);
1487 udelay(150); /* wait for warmup */
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1497 * Note! This is for pre-ILK only.
1499 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv
, pipe
);
1512 val
= I915_READ(reg
);
1513 val
&= ~DPLL_VCO_ENABLE
;
1514 I915_WRITE(reg
, val
);
1520 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1522 unsigned long flags
;
1524 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1525 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 I915_WRITE(SBI_ADDR
,
1533 I915_WRITE(SBI_DATA
,
1535 I915_WRITE(SBI_CTL_STAT
,
1539 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1546 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1550 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1552 unsigned long flags
;
1555 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1556 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1562 I915_WRITE(SBI_ADDR
,
1564 I915_WRITE(SBI_CTL_STAT
,
1568 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1574 value
= I915_READ(SBI_DATA
);
1577 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1589 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1591 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1592 struct intel_pch_pll
*pll
;
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv
->info
->gen
< 5);
1598 pll
= intel_crtc
->pch_pll
;
1602 if (WARN_ON(pll
->refcount
== 0))
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll
->pll_reg
, pll
->active
, pll
->on
,
1607 intel_crtc
->base
.base
.id
);
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv
);
1612 if (pll
->active
++ && pll
->on
) {
1613 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1620 val
= I915_READ(reg
);
1621 val
|= DPLL_VCO_ENABLE
;
1622 I915_WRITE(reg
, val
);
1629 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1631 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1632 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv
->info
->gen
< 5);
1641 if (WARN_ON(pll
->refcount
== 0))
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll
->pll_reg
, pll
->active
, pll
->on
,
1646 intel_crtc
->base
.base
.id
);
1648 if (WARN_ON(pll
->active
== 0)) {
1649 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1653 if (--pll
->active
) {
1654 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1664 val
= I915_READ(reg
);
1665 val
&= ~DPLL_VCO_ENABLE
;
1666 I915_WRITE(reg
, val
);
1673 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1677 u32 val
, pipeconf_val
;
1678 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv
->info
->gen
< 5);
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv
,
1685 to_intel_crtc(crtc
)->pch_pll
,
1686 to_intel_crtc(crtc
));
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv
, pipe
);
1690 assert_fdi_rx_enabled(dev_priv
, pipe
);
1692 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1696 reg
= TRANSCONF(pipe
);
1697 val
= I915_READ(reg
);
1698 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1700 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1705 val
&= ~PIPE_BPC_MASK
;
1706 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1709 val
&= ~TRANS_INTERLACE_MASK
;
1710 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1711 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1712 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1713 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1715 val
|= TRANS_INTERLACED
;
1717 val
|= TRANS_PROGRESSIVE
;
1719 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1720 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1724 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv
, pipe
);
1732 assert_fdi_rx_disabled(dev_priv
, pipe
);
1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv
, pipe
);
1737 reg
= TRANSCONF(pipe
);
1738 val
= I915_READ(reg
);
1739 val
&= ~TRANS_ENABLE
;
1740 I915_WRITE(reg
, val
);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1743 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1747 * intel_enable_pipe - enable a pipe, asserting requirements
1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1755 * @pipe should be %PIPE_A or %PIPE_B.
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1760 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1763 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1773 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1774 assert_pll_enabled(dev_priv
, pipe
);
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1779 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1781 /* FIXME: assert CPU port conditions for SNB+ */
1784 reg
= PIPECONF(cpu_transcoder
);
1785 val
= I915_READ(reg
);
1786 if (val
& PIPECONF_ENABLE
)
1789 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1790 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1794 * intel_disable_pipe - disable a pipe, asserting requirements
1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1801 * @pipe should be %PIPE_A or %PIPE_B.
1803 * Will wait until the pipe has shut down before returning.
1805 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1808 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1817 assert_planes_disabled(dev_priv
, pipe
);
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1823 reg
= PIPECONF(cpu_transcoder
);
1824 val
= I915_READ(reg
);
1825 if ((val
& PIPECONF_ENABLE
) == 0)
1828 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1829 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1836 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1839 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1840 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1844 * intel_enable_plane - enable a display plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1851 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1852 enum plane plane
, enum pipe pipe
)
1857 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858 assert_pipe_enabled(dev_priv
, pipe
);
1860 reg
= DSPCNTR(plane
);
1861 val
= I915_READ(reg
);
1862 if (val
& DISPLAY_PLANE_ENABLE
)
1865 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1866 intel_flush_display_plane(dev_priv
, plane
);
1867 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1871 * intel_disable_plane - disable a display plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1876 * Disable @plane; should be an independent operation.
1878 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1879 enum plane plane
, enum pipe pipe
)
1884 reg
= DSPCNTR(plane
);
1885 val
= I915_READ(reg
);
1886 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1889 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1890 intel_flush_display_plane(dev_priv
, plane
);
1891 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1895 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1896 struct drm_i915_gem_object
*obj
,
1897 struct intel_ring_buffer
*pipelined
)
1899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1903 switch (obj
->tiling_mode
) {
1904 case I915_TILING_NONE
:
1905 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1906 alignment
= 128 * 1024;
1907 else if (INTEL_INFO(dev
)->gen
>= 4)
1908 alignment
= 4 * 1024;
1910 alignment
= 64 * 1024;
1913 /* pin() will align the object as required by fence */
1917 /* FIXME: Is this true? */
1918 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1924 dev_priv
->mm
.interruptible
= false;
1925 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1927 goto err_interruptible
;
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1934 ret
= i915_gem_object_get_fence(obj
);
1938 i915_gem_object_pin_fence(obj
);
1940 dev_priv
->mm
.interruptible
= true;
1944 i915_gem_object_unpin(obj
);
1946 dev_priv
->mm
.interruptible
= true;
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1952 i915_gem_object_unpin_fence(obj
);
1953 i915_gem_object_unpin(obj
);
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x
, int *y
,
1962 int tile_rows
, tiles
;
1966 tiles
= *x
/ (512/bpp
);
1969 return tile_rows
* pitch
* 8 + tiles
* 4096;
1972 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1975 struct drm_device
*dev
= crtc
->dev
;
1976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1977 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1978 struct intel_framebuffer
*intel_fb
;
1979 struct drm_i915_gem_object
*obj
;
1980 int plane
= intel_crtc
->plane
;
1981 unsigned long linear_offset
;
1990 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1994 intel_fb
= to_intel_framebuffer(fb
);
1995 obj
= intel_fb
->obj
;
1997 reg
= DSPCNTR(plane
);
1998 dspcntr
= I915_READ(reg
);
1999 /* Mask out pixel format bits in case we change it */
2000 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2001 switch (fb
->bits_per_pixel
) {
2003 dspcntr
|= DISPPLANE_8BPP
;
2006 if (fb
->depth
== 15)
2007 dspcntr
|= DISPPLANE_15_16BPP
;
2009 dspcntr
|= DISPPLANE_16BPP
;
2013 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2016 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2019 if (INTEL_INFO(dev
)->gen
>= 4) {
2020 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2021 dspcntr
|= DISPPLANE_TILED
;
2023 dspcntr
&= ~DISPPLANE_TILED
;
2026 I915_WRITE(reg
, dspcntr
);
2028 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2030 if (INTEL_INFO(dev
)->gen
>= 4) {
2031 intel_crtc
->dspaddr_offset
=
2032 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2033 fb
->bits_per_pixel
/ 8,
2035 linear_offset
-= intel_crtc
->dspaddr_offset
;
2037 intel_crtc
->dspaddr_offset
= linear_offset
;
2040 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2042 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2043 if (INTEL_INFO(dev
)->gen
>= 4) {
2044 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2045 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2046 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2047 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2049 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2055 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2056 struct drm_framebuffer
*fb
, int x
, int y
)
2058 struct drm_device
*dev
= crtc
->dev
;
2059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2060 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2061 struct intel_framebuffer
*intel_fb
;
2062 struct drm_i915_gem_object
*obj
;
2063 int plane
= intel_crtc
->plane
;
2064 unsigned long linear_offset
;
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2078 intel_fb
= to_intel_framebuffer(fb
);
2079 obj
= intel_fb
->obj
;
2081 reg
= DSPCNTR(plane
);
2082 dspcntr
= I915_READ(reg
);
2083 /* Mask out pixel format bits in case we change it */
2084 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2085 switch (fb
->bits_per_pixel
) {
2087 dspcntr
|= DISPPLANE_8BPP
;
2090 if (fb
->depth
!= 16)
2093 dspcntr
|= DISPPLANE_16BPP
;
2097 if (fb
->depth
== 24)
2098 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2099 else if (fb
->depth
== 30)
2100 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2105 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2109 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2110 dspcntr
|= DISPPLANE_TILED
;
2112 dspcntr
&= ~DISPPLANE_TILED
;
2115 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2117 I915_WRITE(reg
, dspcntr
);
2119 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2120 intel_crtc
->dspaddr_offset
=
2121 gen4_compute_dspaddr_offset_xtiled(&x
, &y
,
2122 fb
->bits_per_pixel
/ 8,
2124 linear_offset
-= intel_crtc
->dspaddr_offset
;
2126 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2128 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2129 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2130 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2131 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2132 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2138 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2140 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2141 int x
, int y
, enum mode_set_atomic state
)
2143 struct drm_device
*dev
= crtc
->dev
;
2144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2146 if (dev_priv
->display
.disable_fbc
)
2147 dev_priv
->display
.disable_fbc(dev
);
2148 intel_increase_pllclock(crtc
);
2150 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2154 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2156 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2157 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2158 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2161 wait_event(dev_priv
->pending_flip_queue
,
2162 atomic_read(&dev_priv
->mm
.wedged
) ||
2163 atomic_read(&obj
->pending_flip
) == 0);
2165 /* Big Hammer, we also need to ensure that any pending
2166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167 * current scanout is retired before unpinning the old
2170 * This should only fail upon a hung GPU, in which case we
2171 * can safely continue.
2173 dev_priv
->mm
.interruptible
= false;
2174 ret
= i915_gem_object_finish_gpu(obj
);
2175 dev_priv
->mm
.interruptible
= was_interruptible
;
2181 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2182 struct drm_framebuffer
*fb
)
2184 struct drm_device
*dev
= crtc
->dev
;
2185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2186 struct drm_i915_master_private
*master_priv
;
2187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2188 struct drm_framebuffer
*old_fb
;
2193 DRM_ERROR("No FB bound\n");
2197 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2198 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2200 dev_priv
->num_pipe
);
2204 mutex_lock(&dev
->struct_mutex
);
2205 ret
= intel_pin_and_fence_fb_obj(dev
,
2206 to_intel_framebuffer(fb
)->obj
,
2209 mutex_unlock(&dev
->struct_mutex
);
2210 DRM_ERROR("pin & fence failed\n");
2215 intel_finish_fb(crtc
->fb
);
2217 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2219 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2220 mutex_unlock(&dev
->struct_mutex
);
2221 DRM_ERROR("failed to update base address\n");
2231 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2232 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2235 intel_update_fbc(dev
);
2236 mutex_unlock(&dev
->struct_mutex
);
2238 if (!dev
->primary
->master
)
2241 master_priv
= dev
->primary
->master
->driver_priv
;
2242 if (!master_priv
->sarea_priv
)
2245 if (intel_crtc
->pipe
) {
2246 master_priv
->sarea_priv
->pipeB_x
= x
;
2247 master_priv
->sarea_priv
->pipeB_y
= y
;
2249 master_priv
->sarea_priv
->pipeA_x
= x
;
2250 master_priv
->sarea_priv
->pipeA_y
= y
;
2256 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2258 struct drm_device
*dev
= crtc
->dev
;
2259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2263 dpa_ctl
= I915_READ(DP_A
);
2264 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2266 if (clock
< 200000) {
2268 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2275 temp
= I915_READ(0x4600c);
2277 I915_WRITE(0x4600c, temp
| 0x8124);
2279 temp
= I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp
| 1);
2282 temp
= I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp
| (1 << 24));
2285 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2287 I915_WRITE(DP_A
, dpa_ctl
);
2293 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2295 struct drm_device
*dev
= crtc
->dev
;
2296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2298 int pipe
= intel_crtc
->pipe
;
2301 /* enable normal train */
2302 reg
= FDI_TX_CTL(pipe
);
2303 temp
= I915_READ(reg
);
2304 if (IS_IVYBRIDGE(dev
)) {
2305 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2306 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2308 temp
&= ~FDI_LINK_TRAIN_NONE
;
2309 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2311 I915_WRITE(reg
, temp
);
2313 reg
= FDI_RX_CTL(pipe
);
2314 temp
= I915_READ(reg
);
2315 if (HAS_PCH_CPT(dev
)) {
2316 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2317 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2319 temp
&= ~FDI_LINK_TRAIN_NONE
;
2320 temp
|= FDI_LINK_TRAIN_NONE
;
2322 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2324 /* wait one idle pattern time */
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev
))
2330 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2331 FDI_FE_ERRC_ENABLE
);
2334 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2337 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2339 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2340 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2341 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2342 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1
);
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2349 struct drm_device
*dev
= crtc
->dev
;
2350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2351 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2352 int pipe
= intel_crtc
->pipe
;
2353 int plane
= intel_crtc
->plane
;
2354 u32 reg
, temp
, tries
;
2356 /* FDI needs bits from pipe & plane first */
2357 assert_pipe_enabled(dev_priv
, pipe
);
2358 assert_plane_enabled(dev_priv
, plane
);
2360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2362 reg
= FDI_RX_IMR(pipe
);
2363 temp
= I915_READ(reg
);
2364 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2365 temp
&= ~FDI_RX_BIT_LOCK
;
2366 I915_WRITE(reg
, temp
);
2370 /* enable CPU FDI TX and PCH FDI RX */
2371 reg
= FDI_TX_CTL(pipe
);
2372 temp
= I915_READ(reg
);
2374 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2375 temp
&= ~FDI_LINK_TRAIN_NONE
;
2376 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2377 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2379 reg
= FDI_RX_CTL(pipe
);
2380 temp
= I915_READ(reg
);
2381 temp
&= ~FDI_LINK_TRAIN_NONE
;
2382 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2383 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2388 /* Ironlake workaround, enable clock pointer after FDI enable*/
2389 if (HAS_PCH_IBX(dev
)) {
2390 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2391 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2392 FDI_RX_PHASE_SYNC_POINTER_EN
);
2395 reg
= FDI_RX_IIR(pipe
);
2396 for (tries
= 0; tries
< 5; tries
++) {
2397 temp
= I915_READ(reg
);
2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2400 if ((temp
& FDI_RX_BIT_LOCK
)) {
2401 DRM_DEBUG_KMS("FDI train 1 done.\n");
2402 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2407 DRM_ERROR("FDI train 1 fail!\n");
2410 reg
= FDI_TX_CTL(pipe
);
2411 temp
= I915_READ(reg
);
2412 temp
&= ~FDI_LINK_TRAIN_NONE
;
2413 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2414 I915_WRITE(reg
, temp
);
2416 reg
= FDI_RX_CTL(pipe
);
2417 temp
= I915_READ(reg
);
2418 temp
&= ~FDI_LINK_TRAIN_NONE
;
2419 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2420 I915_WRITE(reg
, temp
);
2425 reg
= FDI_RX_IIR(pipe
);
2426 for (tries
= 0; tries
< 5; tries
++) {
2427 temp
= I915_READ(reg
);
2428 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2430 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2431 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2432 DRM_DEBUG_KMS("FDI train 2 done.\n");
2437 DRM_ERROR("FDI train 2 fail!\n");
2439 DRM_DEBUG_KMS("FDI train done\n");
2443 static const int snb_b_fdi_train_param
[] = {
2444 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2445 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2446 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2447 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2453 struct drm_device
*dev
= crtc
->dev
;
2454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2455 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2456 int pipe
= intel_crtc
->pipe
;
2457 u32 reg
, temp
, i
, retry
;
2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2461 reg
= FDI_RX_IMR(pipe
);
2462 temp
= I915_READ(reg
);
2463 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2464 temp
&= ~FDI_RX_BIT_LOCK
;
2465 I915_WRITE(reg
, temp
);
2470 /* enable CPU FDI TX and PCH FDI RX */
2471 reg
= FDI_TX_CTL(pipe
);
2472 temp
= I915_READ(reg
);
2474 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2475 temp
&= ~FDI_LINK_TRAIN_NONE
;
2476 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2477 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2479 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2480 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2482 reg
= FDI_RX_CTL(pipe
);
2483 temp
= I915_READ(reg
);
2484 if (HAS_PCH_CPT(dev
)) {
2485 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2486 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2488 temp
&= ~FDI_LINK_TRAIN_NONE
;
2489 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2491 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2496 if (HAS_PCH_CPT(dev
))
2497 cpt_phase_pointer_enable(dev
, pipe
);
2499 for (i
= 0; i
< 4; i
++) {
2500 reg
= FDI_TX_CTL(pipe
);
2501 temp
= I915_READ(reg
);
2502 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2503 temp
|= snb_b_fdi_train_param
[i
];
2504 I915_WRITE(reg
, temp
);
2509 for (retry
= 0; retry
< 5; retry
++) {
2510 reg
= FDI_RX_IIR(pipe
);
2511 temp
= I915_READ(reg
);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2513 if (temp
& FDI_RX_BIT_LOCK
) {
2514 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
2524 DRM_ERROR("FDI train 1 fail!\n");
2527 reg
= FDI_TX_CTL(pipe
);
2528 temp
= I915_READ(reg
);
2529 temp
&= ~FDI_LINK_TRAIN_NONE
;
2530 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2532 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2534 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2536 I915_WRITE(reg
, temp
);
2538 reg
= FDI_RX_CTL(pipe
);
2539 temp
= I915_READ(reg
);
2540 if (HAS_PCH_CPT(dev
)) {
2541 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2542 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2544 temp
&= ~FDI_LINK_TRAIN_NONE
;
2545 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2547 I915_WRITE(reg
, temp
);
2552 for (i
= 0; i
< 4; i
++) {
2553 reg
= FDI_TX_CTL(pipe
);
2554 temp
= I915_READ(reg
);
2555 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2556 temp
|= snb_b_fdi_train_param
[i
];
2557 I915_WRITE(reg
, temp
);
2562 for (retry
= 0; retry
< 5; retry
++) {
2563 reg
= FDI_RX_IIR(pipe
);
2564 temp
= I915_READ(reg
);
2565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2566 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2567 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2568 DRM_DEBUG_KMS("FDI train 2 done.\n");
2577 DRM_ERROR("FDI train 2 fail!\n");
2579 DRM_DEBUG_KMS("FDI train done.\n");
2582 /* Manual link training for Ivy Bridge A0 parts */
2583 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2585 struct drm_device
*dev
= crtc
->dev
;
2586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2587 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2588 int pipe
= intel_crtc
->pipe
;
2591 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2593 reg
= FDI_RX_IMR(pipe
);
2594 temp
= I915_READ(reg
);
2595 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2596 temp
&= ~FDI_RX_BIT_LOCK
;
2597 I915_WRITE(reg
, temp
);
2602 /* enable CPU FDI TX and PCH FDI RX */
2603 reg
= FDI_TX_CTL(pipe
);
2604 temp
= I915_READ(reg
);
2606 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2607 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2608 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2609 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2610 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2611 temp
|= FDI_COMPOSITE_SYNC
;
2612 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2614 reg
= FDI_RX_CTL(pipe
);
2615 temp
= I915_READ(reg
);
2616 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2617 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2618 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2619 temp
|= FDI_COMPOSITE_SYNC
;
2620 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2625 if (HAS_PCH_CPT(dev
))
2626 cpt_phase_pointer_enable(dev
, pipe
);
2628 for (i
= 0; i
< 4; i
++) {
2629 reg
= FDI_TX_CTL(pipe
);
2630 temp
= I915_READ(reg
);
2631 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2632 temp
|= snb_b_fdi_train_param
[i
];
2633 I915_WRITE(reg
, temp
);
2638 reg
= FDI_RX_IIR(pipe
);
2639 temp
= I915_READ(reg
);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2642 if (temp
& FDI_RX_BIT_LOCK
||
2643 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2644 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2645 DRM_DEBUG_KMS("FDI train 1 done.\n");
2650 DRM_ERROR("FDI train 1 fail!\n");
2653 reg
= FDI_TX_CTL(pipe
);
2654 temp
= I915_READ(reg
);
2655 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2656 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2657 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2658 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2659 I915_WRITE(reg
, temp
);
2661 reg
= FDI_RX_CTL(pipe
);
2662 temp
= I915_READ(reg
);
2663 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2664 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2665 I915_WRITE(reg
, temp
);
2670 for (i
= 0; i
< 4; i
++) {
2671 reg
= FDI_TX_CTL(pipe
);
2672 temp
= I915_READ(reg
);
2673 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2674 temp
|= snb_b_fdi_train_param
[i
];
2675 I915_WRITE(reg
, temp
);
2680 reg
= FDI_RX_IIR(pipe
);
2681 temp
= I915_READ(reg
);
2682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2684 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2685 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2686 DRM_DEBUG_KMS("FDI train 2 done.\n");
2691 DRM_ERROR("FDI train 2 fail!\n");
2693 DRM_DEBUG_KMS("FDI train done.\n");
2696 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2698 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2700 int pipe
= intel_crtc
->pipe
;
2703 /* Write the TU size bits so error detection works */
2704 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2705 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2707 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2708 reg
= FDI_RX_CTL(pipe
);
2709 temp
= I915_READ(reg
);
2710 temp
&= ~((0x7 << 19) | (0x7 << 16));
2711 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2712 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2713 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2718 /* Switch from Rawclk to PCDclk */
2719 temp
= I915_READ(reg
);
2720 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2725 /* On Haswell, the PLL configuration for ports and pipes is handled
2726 * separately, as part of DDI setup */
2727 if (!IS_HASWELL(dev
)) {
2728 /* Enable CPU FDI TX PLL, always on for Ironlake */
2729 reg
= FDI_TX_CTL(pipe
);
2730 temp
= I915_READ(reg
);
2731 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2732 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2740 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2742 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2744 int pipe
= intel_crtc
->pipe
;
2747 /* Switch from PCDclk to Rawclk */
2748 reg
= FDI_RX_CTL(pipe
);
2749 temp
= I915_READ(reg
);
2750 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2752 /* Disable CPU FDI TX PLL */
2753 reg
= FDI_TX_CTL(pipe
);
2754 temp
= I915_READ(reg
);
2755 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2760 reg
= FDI_RX_CTL(pipe
);
2761 temp
= I915_READ(reg
);
2762 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2764 /* Wait for the clocks to turn off. */
2769 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2772 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2774 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2775 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2776 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2777 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2778 POSTING_READ(SOUTH_CHICKEN1
);
2780 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2782 struct drm_device
*dev
= crtc
->dev
;
2783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2784 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2785 int pipe
= intel_crtc
->pipe
;
2788 /* disable CPU FDI tx and PCH FDI rx */
2789 reg
= FDI_TX_CTL(pipe
);
2790 temp
= I915_READ(reg
);
2791 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2794 reg
= FDI_RX_CTL(pipe
);
2795 temp
= I915_READ(reg
);
2796 temp
&= ~(0x7 << 16);
2797 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2798 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2803 /* Ironlake workaround, disable clock pointer after downing FDI */
2804 if (HAS_PCH_IBX(dev
)) {
2805 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2806 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2807 I915_READ(FDI_RX_CHICKEN(pipe
) &
2808 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2809 } else if (HAS_PCH_CPT(dev
)) {
2810 cpt_phase_pointer_disable(dev
, pipe
);
2813 /* still set train pattern 1 */
2814 reg
= FDI_TX_CTL(pipe
);
2815 temp
= I915_READ(reg
);
2816 temp
&= ~FDI_LINK_TRAIN_NONE
;
2817 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2818 I915_WRITE(reg
, temp
);
2820 reg
= FDI_RX_CTL(pipe
);
2821 temp
= I915_READ(reg
);
2822 if (HAS_PCH_CPT(dev
)) {
2823 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2824 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2826 temp
&= ~FDI_LINK_TRAIN_NONE
;
2827 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2829 /* BPC in FDI rx is consistent with that in PIPECONF */
2830 temp
&= ~(0x07 << 16);
2831 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2832 I915_WRITE(reg
, temp
);
2838 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2840 struct drm_device
*dev
= crtc
->dev
;
2841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2842 unsigned long flags
;
2845 if (atomic_read(&dev_priv
->mm
.wedged
))
2848 spin_lock_irqsave(&dev
->event_lock
, flags
);
2849 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2850 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2855 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2857 struct drm_device
*dev
= crtc
->dev
;
2858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2860 if (crtc
->fb
== NULL
)
2863 wait_event(dev_priv
->pending_flip_queue
,
2864 !intel_crtc_has_pending_flip(crtc
));
2866 mutex_lock(&dev
->struct_mutex
);
2867 intel_finish_fb(crtc
->fb
);
2868 mutex_unlock(&dev
->struct_mutex
);
2871 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2873 struct drm_device
*dev
= crtc
->dev
;
2874 struct intel_encoder
*intel_encoder
;
2877 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2878 * must be driven by its own crtc; no sharing is possible.
2880 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2881 switch (intel_encoder
->type
) {
2882 case INTEL_OUTPUT_EDP
:
2883 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2892 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2894 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2897 /* Program iCLKIP clock to the desired frequency */
2898 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2900 struct drm_device
*dev
= crtc
->dev
;
2901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2902 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2905 /* It is necessary to ungate the pixclk gate prior to programming
2906 * the divisors, and gate it back when it is done.
2908 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2910 /* Disable SSCCTL */
2911 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2912 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2913 SBI_SSCCTL_DISABLE
);
2915 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2916 if (crtc
->mode
.clock
== 20000) {
2921 /* The iCLK virtual clock root frequency is in MHz,
2922 * but the crtc->mode.clock in in KHz. To get the divisors,
2923 * it is necessary to divide one by another, so we
2924 * convert the virtual clock precision to KHz here for higher
2927 u32 iclk_virtual_root_freq
= 172800 * 1000;
2928 u32 iclk_pi_range
= 64;
2929 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2931 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2932 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2933 pi_value
= desired_divisor
% iclk_pi_range
;
2936 divsel
= msb_divisor_value
- 2;
2937 phaseinc
= pi_value
;
2940 /* This should not happen with any sane values */
2941 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2942 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2943 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2944 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2946 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2953 /* Program SSCDIVINTPHASE6 */
2954 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2955 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2956 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2957 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2958 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2959 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2960 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2962 intel_sbi_write(dev_priv
,
2963 SBI_SSCDIVINTPHASE6
,
2966 /* Program SSCAUXDIV */
2967 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2968 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2969 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2970 intel_sbi_write(dev_priv
,
2975 /* Enable modulator and associated divider */
2976 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2977 temp
&= ~SBI_SSCCTL_DISABLE
;
2978 intel_sbi_write(dev_priv
,
2982 /* Wait for initialization time */
2985 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2989 * Enable PCH resources required for PCH ports:
2991 * - FDI training & RX/TX
2992 * - update transcoder timings
2993 * - DP transcoding bits
2996 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2998 struct drm_device
*dev
= crtc
->dev
;
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3001 int pipe
= intel_crtc
->pipe
;
3004 assert_transcoder_disabled(dev_priv
, pipe
);
3006 /* For PCH output, training FDI link */
3007 dev_priv
->display
.fdi_link_train(crtc
);
3009 intel_enable_pch_pll(intel_crtc
);
3011 if (HAS_PCH_LPT(dev
)) {
3012 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3013 lpt_program_iclkip(crtc
);
3014 } else if (HAS_PCH_CPT(dev
)) {
3017 temp
= I915_READ(PCH_DPLL_SEL
);
3021 temp
|= TRANSA_DPLL_ENABLE
;
3022 sel
= TRANSA_DPLLB_SEL
;
3025 temp
|= TRANSB_DPLL_ENABLE
;
3026 sel
= TRANSB_DPLLB_SEL
;
3029 temp
|= TRANSC_DPLL_ENABLE
;
3030 sel
= TRANSC_DPLLB_SEL
;
3033 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3037 I915_WRITE(PCH_DPLL_SEL
, temp
);
3040 /* set transcoder timing, panel must allow it */
3041 assert_panel_unlocked(dev_priv
, pipe
);
3042 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3043 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3044 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3046 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3047 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3048 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3049 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3051 if (!IS_HASWELL(dev
))
3052 intel_fdi_normal_train(crtc
);
3054 /* For PCH DP, enable TRANS_DP_CTL */
3055 if (HAS_PCH_CPT(dev
) &&
3056 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3057 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3058 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3059 reg
= TRANS_DP_CTL(pipe
);
3060 temp
= I915_READ(reg
);
3061 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3062 TRANS_DP_SYNC_MASK
|
3064 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3065 TRANS_DP_ENH_FRAMING
);
3066 temp
|= bpc
<< 9; /* same format but at 11:9 */
3068 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3069 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3070 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3071 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3073 switch (intel_trans_dp_port_sel(crtc
)) {
3075 temp
|= TRANS_DP_PORT_SEL_B
;
3078 temp
|= TRANS_DP_PORT_SEL_C
;
3081 temp
|= TRANS_DP_PORT_SEL_D
;
3084 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3085 temp
|= TRANS_DP_PORT_SEL_B
;
3089 I915_WRITE(reg
, temp
);
3092 intel_enable_transcoder(dev_priv
, pipe
);
3095 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3097 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3102 if (pll
->refcount
== 0) {
3103 WARN(1, "bad PCH PLL refcount\n");
3108 intel_crtc
->pch_pll
= NULL
;
3111 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3113 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3114 struct intel_pch_pll
*pll
;
3117 pll
= intel_crtc
->pch_pll
;
3119 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3120 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3124 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3125 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3126 i
= intel_crtc
->pipe
;
3127 pll
= &dev_priv
->pch_plls
[i
];
3129 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3130 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3135 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3136 pll
= &dev_priv
->pch_plls
[i
];
3138 /* Only want to check enabled timings first */
3139 if (pll
->refcount
== 0)
3142 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3143 fp
== I915_READ(pll
->fp0_reg
)) {
3144 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3145 intel_crtc
->base
.base
.id
,
3146 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3152 /* Ok no matching timings, maybe there's a free one? */
3153 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3154 pll
= &dev_priv
->pch_plls
[i
];
3155 if (pll
->refcount
== 0) {
3156 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3157 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3165 intel_crtc
->pch_pll
= pll
;
3167 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3168 prepare
: /* separate function? */
3169 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3171 /* Wait for the clocks to stabilize before rewriting the regs */
3172 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3173 POSTING_READ(pll
->pll_reg
);
3176 I915_WRITE(pll
->fp0_reg
, fp
);
3177 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3182 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3185 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3188 temp
= I915_READ(dslreg
);
3190 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3191 /* Without this, mode sets may fail silently on FDI */
3192 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3194 I915_WRITE(tc2reg
, 0);
3195 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3196 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3200 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3202 struct drm_device
*dev
= crtc
->dev
;
3203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3204 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3205 struct intel_encoder
*encoder
;
3206 int pipe
= intel_crtc
->pipe
;
3207 int plane
= intel_crtc
->plane
;
3211 WARN_ON(!crtc
->enabled
);
3213 if (intel_crtc
->active
)
3216 intel_crtc
->active
= true;
3217 intel_update_watermarks(dev
);
3219 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3220 temp
= I915_READ(PCH_LVDS
);
3221 if ((temp
& LVDS_PORT_EN
) == 0)
3222 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3225 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3228 ironlake_fdi_pll_enable(intel_crtc
);
3230 assert_fdi_tx_disabled(dev_priv
, pipe
);
3231 assert_fdi_rx_disabled(dev_priv
, pipe
);
3234 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3235 if (encoder
->pre_enable
)
3236 encoder
->pre_enable(encoder
);
3238 /* Enable panel fitting for LVDS */
3239 if (dev_priv
->pch_pf_size
&&
3240 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3241 /* Force use of hard-coded filter coefficients
3242 * as some pre-programmed values are broken,
3245 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3246 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3247 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3251 * On ILK+ LUT must be loaded before the pipe is running but with
3254 intel_crtc_load_lut(crtc
);
3256 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3257 intel_enable_plane(dev_priv
, plane
, pipe
);
3260 ironlake_pch_enable(crtc
);
3262 mutex_lock(&dev
->struct_mutex
);
3263 intel_update_fbc(dev
);
3264 mutex_unlock(&dev
->struct_mutex
);
3266 intel_crtc_update_cursor(crtc
, true);
3268 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3269 encoder
->enable(encoder
);
3271 if (HAS_PCH_CPT(dev
))
3272 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3275 * There seems to be a race in PCH platform hw (at least on some
3276 * outputs) where an enabled pipe still completes any pageflip right
3277 * away (as if the pipe is off) instead of waiting for vblank. As soon
3278 * as the first vblank happend, everything works as expected. Hence just
3279 * wait for one vblank before returning to avoid strange things
3282 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3285 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3287 struct drm_device
*dev
= crtc
->dev
;
3288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3290 struct intel_encoder
*encoder
;
3291 int pipe
= intel_crtc
->pipe
;
3292 int plane
= intel_crtc
->plane
;
3295 WARN_ON(!crtc
->enabled
);
3297 if (intel_crtc
->active
)
3300 intel_crtc
->active
= true;
3301 intel_update_watermarks(dev
);
3303 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3306 ironlake_fdi_pll_enable(intel_crtc
);
3308 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3309 if (encoder
->pre_enable
)
3310 encoder
->pre_enable(encoder
);
3312 intel_ddi_enable_pipe_clock(intel_crtc
);
3314 /* Enable panel fitting for eDP */
3315 if (dev_priv
->pch_pf_size
&& HAS_eDP
) {
3316 /* Force use of hard-coded filter coefficients
3317 * as some pre-programmed values are broken,
3320 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3321 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3322 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3326 * On ILK+ LUT must be loaded before the pipe is running but with
3329 intel_crtc_load_lut(crtc
);
3331 intel_ddi_set_pipe_settings(crtc
);
3332 intel_ddi_enable_pipe_func(crtc
);
3334 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3335 intel_enable_plane(dev_priv
, plane
, pipe
);
3338 ironlake_pch_enable(crtc
);
3340 mutex_lock(&dev
->struct_mutex
);
3341 intel_update_fbc(dev
);
3342 mutex_unlock(&dev
->struct_mutex
);
3344 intel_crtc_update_cursor(crtc
, true);
3346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3347 encoder
->enable(encoder
);
3350 * There seems to be a race in PCH platform hw (at least on some
3351 * outputs) where an enabled pipe still completes any pageflip right
3352 * away (as if the pipe is off) instead of waiting for vblank. As soon
3353 * as the first vblank happend, everything works as expected. Hence just
3354 * wait for one vblank before returning to avoid strange things
3357 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3360 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3362 struct drm_device
*dev
= crtc
->dev
;
3363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3364 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3365 struct intel_encoder
*encoder
;
3366 int pipe
= intel_crtc
->pipe
;
3367 int plane
= intel_crtc
->plane
;
3371 if (!intel_crtc
->active
)
3374 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3375 encoder
->disable(encoder
);
3377 intel_crtc_wait_for_pending_flips(crtc
);
3378 drm_vblank_off(dev
, pipe
);
3379 intel_crtc_update_cursor(crtc
, false);
3381 intel_disable_plane(dev_priv
, plane
, pipe
);
3383 if (dev_priv
->cfb_plane
== plane
)
3384 intel_disable_fbc(dev
);
3386 intel_disable_pipe(dev_priv
, pipe
);
3389 I915_WRITE(PF_CTL(pipe
), 0);
3390 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3392 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3393 if (encoder
->post_disable
)
3394 encoder
->post_disable(encoder
);
3396 ironlake_fdi_disable(crtc
);
3398 intel_disable_transcoder(dev_priv
, pipe
);
3400 if (HAS_PCH_CPT(dev
)) {
3401 /* disable TRANS_DP_CTL */
3402 reg
= TRANS_DP_CTL(pipe
);
3403 temp
= I915_READ(reg
);
3404 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3405 temp
|= TRANS_DP_PORT_SEL_NONE
;
3406 I915_WRITE(reg
, temp
);
3408 /* disable DPLL_SEL */
3409 temp
= I915_READ(PCH_DPLL_SEL
);
3412 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3415 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3418 /* C shares PLL A or B */
3419 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3424 I915_WRITE(PCH_DPLL_SEL
, temp
);
3427 /* disable PCH DPLL */
3428 intel_disable_pch_pll(intel_crtc
);
3430 ironlake_fdi_pll_disable(intel_crtc
);
3432 intel_crtc
->active
= false;
3433 intel_update_watermarks(dev
);
3435 mutex_lock(&dev
->struct_mutex
);
3436 intel_update_fbc(dev
);
3437 mutex_unlock(&dev
->struct_mutex
);
3440 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3442 struct drm_device
*dev
= crtc
->dev
;
3443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3445 struct intel_encoder
*encoder
;
3446 int pipe
= intel_crtc
->pipe
;
3447 int plane
= intel_crtc
->plane
;
3448 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3451 if (!intel_crtc
->active
)
3454 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3456 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3457 encoder
->disable(encoder
);
3459 intel_crtc_wait_for_pending_flips(crtc
);
3460 drm_vblank_off(dev
, pipe
);
3461 intel_crtc_update_cursor(crtc
, false);
3463 intel_disable_plane(dev_priv
, plane
, pipe
);
3465 if (dev_priv
->cfb_plane
== plane
)
3466 intel_disable_fbc(dev
);
3468 intel_disable_pipe(dev_priv
, pipe
);
3470 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3473 I915_WRITE(PF_CTL(pipe
), 0);
3474 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3476 intel_ddi_disable_pipe_clock(intel_crtc
);
3478 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3479 if (encoder
->post_disable
)
3480 encoder
->post_disable(encoder
);
3483 ironlake_fdi_disable(crtc
);
3484 intel_disable_transcoder(dev_priv
, pipe
);
3485 intel_disable_pch_pll(intel_crtc
);
3486 ironlake_fdi_pll_disable(intel_crtc
);
3489 intel_crtc
->active
= false;
3490 intel_update_watermarks(dev
);
3492 mutex_lock(&dev
->struct_mutex
);
3493 intel_update_fbc(dev
);
3494 mutex_unlock(&dev
->struct_mutex
);
3497 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3500 intel_put_pch_pll(intel_crtc
);
3503 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3505 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3507 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3508 * start using it. */
3509 intel_crtc
->cpu_transcoder
= intel_crtc
->pipe
;
3511 intel_ddi_put_crtc_pll(crtc
);
3514 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3516 if (!enable
&& intel_crtc
->overlay
) {
3517 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3520 mutex_lock(&dev
->struct_mutex
);
3521 dev_priv
->mm
.interruptible
= false;
3522 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3523 dev_priv
->mm
.interruptible
= true;
3524 mutex_unlock(&dev
->struct_mutex
);
3527 /* Let userspace switch the overlay on again. In most cases userspace
3528 * has to recompute where to put it anyway.
3532 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3534 struct drm_device
*dev
= crtc
->dev
;
3535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3536 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3537 struct intel_encoder
*encoder
;
3538 int pipe
= intel_crtc
->pipe
;
3539 int plane
= intel_crtc
->plane
;
3541 WARN_ON(!crtc
->enabled
);
3543 if (intel_crtc
->active
)
3546 intel_crtc
->active
= true;
3547 intel_update_watermarks(dev
);
3549 intel_enable_pll(dev_priv
, pipe
);
3550 intel_enable_pipe(dev_priv
, pipe
, false);
3551 intel_enable_plane(dev_priv
, plane
, pipe
);
3553 intel_crtc_load_lut(crtc
);
3554 intel_update_fbc(dev
);
3556 /* Give the overlay scaler a chance to enable if it's on this pipe */
3557 intel_crtc_dpms_overlay(intel_crtc
, true);
3558 intel_crtc_update_cursor(crtc
, true);
3560 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3561 encoder
->enable(encoder
);
3564 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3566 struct drm_device
*dev
= crtc
->dev
;
3567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3568 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3569 struct intel_encoder
*encoder
;
3570 int pipe
= intel_crtc
->pipe
;
3571 int plane
= intel_crtc
->plane
;
3574 if (!intel_crtc
->active
)
3577 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3578 encoder
->disable(encoder
);
3580 /* Give the overlay scaler a chance to disable if it's on this pipe */
3581 intel_crtc_wait_for_pending_flips(crtc
);
3582 drm_vblank_off(dev
, pipe
);
3583 intel_crtc_dpms_overlay(intel_crtc
, false);
3584 intel_crtc_update_cursor(crtc
, false);
3586 if (dev_priv
->cfb_plane
== plane
)
3587 intel_disable_fbc(dev
);
3589 intel_disable_plane(dev_priv
, plane
, pipe
);
3590 intel_disable_pipe(dev_priv
, pipe
);
3591 intel_disable_pll(dev_priv
, pipe
);
3593 intel_crtc
->active
= false;
3594 intel_update_fbc(dev
);
3595 intel_update_watermarks(dev
);
3598 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3602 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3605 struct drm_device
*dev
= crtc
->dev
;
3606 struct drm_i915_master_private
*master_priv
;
3607 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3608 int pipe
= intel_crtc
->pipe
;
3610 if (!dev
->primary
->master
)
3613 master_priv
= dev
->primary
->master
->driver_priv
;
3614 if (!master_priv
->sarea_priv
)
3619 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3620 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3623 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3624 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3627 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3633 * Sets the power management mode of the pipe and plane.
3635 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3637 struct drm_device
*dev
= crtc
->dev
;
3638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3639 struct intel_encoder
*intel_encoder
;
3640 bool enable
= false;
3642 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3643 enable
|= intel_encoder
->connectors_active
;
3646 dev_priv
->display
.crtc_enable(crtc
);
3648 dev_priv
->display
.crtc_disable(crtc
);
3650 intel_crtc_update_sarea(crtc
, enable
);
3653 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3657 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3659 struct drm_device
*dev
= crtc
->dev
;
3660 struct drm_connector
*connector
;
3661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3663 /* crtc should still be enabled when we disable it. */
3664 WARN_ON(!crtc
->enabled
);
3666 dev_priv
->display
.crtc_disable(crtc
);
3667 intel_crtc_update_sarea(crtc
, false);
3668 dev_priv
->display
.off(crtc
);
3670 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3671 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3674 mutex_lock(&dev
->struct_mutex
);
3675 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3676 mutex_unlock(&dev
->struct_mutex
);
3680 /* Update computed state. */
3681 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3682 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3685 if (connector
->encoder
->crtc
!= crtc
)
3688 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3689 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3693 void intel_modeset_disable(struct drm_device
*dev
)
3695 struct drm_crtc
*crtc
;
3697 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3699 intel_crtc_disable(crtc
);
3703 void intel_encoder_noop(struct drm_encoder
*encoder
)
3707 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3709 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3711 drm_encoder_cleanup(encoder
);
3712 kfree(intel_encoder
);
3715 /* Simple dpms helper for encodres with just one connector, no cloning and only
3716 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3717 * state of the entire output pipe. */
3718 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3720 if (mode
== DRM_MODE_DPMS_ON
) {
3721 encoder
->connectors_active
= true;
3723 intel_crtc_update_dpms(encoder
->base
.crtc
);
3725 encoder
->connectors_active
= false;
3727 intel_crtc_update_dpms(encoder
->base
.crtc
);
3731 /* Cross check the actual hw state with our own modeset state tracking (and it's
3732 * internal consistency). */
3733 static void intel_connector_check_state(struct intel_connector
*connector
)
3735 if (connector
->get_hw_state(connector
)) {
3736 struct intel_encoder
*encoder
= connector
->encoder
;
3737 struct drm_crtc
*crtc
;
3738 bool encoder_enabled
;
3741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3742 connector
->base
.base
.id
,
3743 drm_get_connector_name(&connector
->base
));
3745 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3746 "wrong connector dpms state\n");
3747 WARN(connector
->base
.encoder
!= &encoder
->base
,
3748 "active connector not linked to encoder\n");
3749 WARN(!encoder
->connectors_active
,
3750 "encoder->connectors_active not set\n");
3752 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3753 WARN(!encoder_enabled
, "encoder not enabled\n");
3754 if (WARN_ON(!encoder
->base
.crtc
))
3757 crtc
= encoder
->base
.crtc
;
3759 WARN(!crtc
->enabled
, "crtc not enabled\n");
3760 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3761 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3762 "encoder active on the wrong pipe\n");
3766 /* Even simpler default implementation, if there's really no special case to
3768 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3770 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3772 /* All the simple cases only support two dpms states. */
3773 if (mode
!= DRM_MODE_DPMS_ON
)
3774 mode
= DRM_MODE_DPMS_OFF
;
3776 if (mode
== connector
->dpms
)
3779 connector
->dpms
= mode
;
3781 /* Only need to change hw state when actually enabled */
3782 if (encoder
->base
.crtc
)
3783 intel_encoder_dpms(encoder
, mode
);
3785 WARN_ON(encoder
->connectors_active
!= false);
3787 intel_modeset_check_state(connector
->dev
);
3790 /* Simple connector->get_hw_state implementation for encoders that support only
3791 * one connector and no cloning and hence the encoder state determines the state
3792 * of the connector. */
3793 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3796 struct intel_encoder
*encoder
= connector
->encoder
;
3798 return encoder
->get_hw_state(encoder
, &pipe
);
3801 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3802 const struct drm_display_mode
*mode
,
3803 struct drm_display_mode
*adjusted_mode
)
3805 struct drm_device
*dev
= crtc
->dev
;
3807 if (HAS_PCH_SPLIT(dev
)) {
3808 /* FDI link clock is fixed at 2.7G */
3809 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3813 /* All interlaced capable intel hw wants timings in frames. Note though
3814 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3815 * timings, so we need to be careful not to clobber these.*/
3816 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3817 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3819 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3820 * with a hsync front porch of 0.
3822 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3823 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3829 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3831 return 400000; /* FIXME */
3834 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3839 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3844 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3849 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3853 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3855 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3858 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3859 case GC_DISPLAY_CLOCK_333_MHZ
:
3862 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3868 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3873 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3876 /* Assume that the hardware is in the high speed state. This
3877 * should be the default.
3879 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3880 case GC_CLOCK_133_200
:
3881 case GC_CLOCK_100_200
:
3883 case GC_CLOCK_166_250
:
3885 case GC_CLOCK_100_133
:
3889 /* Shouldn't happen */
3893 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3907 fdi_reduce_ratio(u32
*num
, u32
*den
)
3909 while (*num
> 0xffffff || *den
> 0xffffff) {
3916 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3917 int link_clock
, struct fdi_m_n
*m_n
)
3919 m_n
->tu
= 64; /* default size */
3921 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3922 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3923 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3924 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3926 m_n
->link_m
= pixel_clock
;
3927 m_n
->link_n
= link_clock
;
3928 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3931 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3933 if (i915_panel_use_ssc
>= 0)
3934 return i915_panel_use_ssc
!= 0;
3935 return dev_priv
->lvds_use_ssc
3936 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3940 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3941 * @crtc: CRTC structure
3942 * @mode: requested mode
3944 * A pipe may be connected to one or more outputs. Based on the depth of the
3945 * attached framebuffer, choose a good color depth to use on the pipe.
3947 * If possible, match the pipe depth to the fb depth. In some cases, this
3948 * isn't ideal, because the connected output supports a lesser or restricted
3949 * set of depths. Resolve that here:
3950 * LVDS typically supports only 6bpc, so clamp down in that case
3951 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3952 * Displays may support a restricted set as well, check EDID and clamp as
3954 * DP may want to dither down to 6bpc to fit larger modes
3957 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3958 * true if they don't match).
3960 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3961 struct drm_framebuffer
*fb
,
3962 unsigned int *pipe_bpp
,
3963 struct drm_display_mode
*mode
)
3965 struct drm_device
*dev
= crtc
->dev
;
3966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3967 struct drm_connector
*connector
;
3968 struct intel_encoder
*intel_encoder
;
3969 unsigned int display_bpc
= UINT_MAX
, bpc
;
3971 /* Walk the encoders & connectors on this crtc, get min bpc */
3972 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
3974 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3975 unsigned int lvds_bpc
;
3977 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3983 if (lvds_bpc
< display_bpc
) {
3984 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3985 display_bpc
= lvds_bpc
;
3990 /* Not one of the known troublemakers, check the EDID */
3991 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3993 if (connector
->encoder
!= &intel_encoder
->base
)
3996 /* Don't use an invalid EDID bpc value */
3997 if (connector
->display_info
.bpc
&&
3998 connector
->display_info
.bpc
< display_bpc
) {
3999 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4000 display_bpc
= connector
->display_info
.bpc
;
4005 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4006 * through, clamp it down. (Note: >12bpc will be caught below.)
4008 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4009 if (display_bpc
> 8 && display_bpc
< 12) {
4010 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4013 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4019 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4020 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4025 * We could just drive the pipe at the highest bpc all the time and
4026 * enable dithering as needed, but that costs bandwidth. So choose
4027 * the minimum value that expresses the full color range of the fb but
4028 * also stays within the max display bpc discovered above.
4031 switch (fb
->depth
) {
4033 bpc
= 8; /* since we go through a colormap */
4037 bpc
= 6; /* min is 18bpp */
4049 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4050 bpc
= min((unsigned int)8, display_bpc
);
4054 display_bpc
= min(display_bpc
, bpc
);
4056 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4059 *pipe_bpp
= display_bpc
* 3;
4061 return display_bpc
!= bpc
;
4064 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4066 struct drm_device
*dev
= crtc
->dev
;
4067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4068 int refclk
= 27000; /* for DP & HDMI */
4070 return 100000; /* only one validated so far */
4072 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4074 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4075 if (intel_panel_use_ssc(dev_priv
))
4079 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4086 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4088 struct drm_device
*dev
= crtc
->dev
;
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4092 if (IS_VALLEYVIEW(dev
)) {
4093 refclk
= vlv_get_refclk(crtc
);
4094 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4095 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4096 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4097 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4099 } else if (!IS_GEN2(dev
)) {
4108 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4109 intel_clock_t
*clock
)
4111 /* SDVO TV has fixed PLL values depend on its clock range,
4112 this mirrors vbios setting. */
4113 if (adjusted_mode
->clock
>= 100000
4114 && adjusted_mode
->clock
< 140500) {
4120 } else if (adjusted_mode
->clock
>= 140500
4121 && adjusted_mode
->clock
<= 200000) {
4130 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4131 intel_clock_t
*clock
,
4132 intel_clock_t
*reduced_clock
)
4134 struct drm_device
*dev
= crtc
->dev
;
4135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4137 int pipe
= intel_crtc
->pipe
;
4140 if (IS_PINEVIEW(dev
)) {
4141 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4143 fp2
= (1 << reduced_clock
->n
) << 16 |
4144 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4146 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4148 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4152 I915_WRITE(FP0(pipe
), fp
);
4154 intel_crtc
->lowfreq_avail
= false;
4155 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4156 reduced_clock
&& i915_powersave
) {
4157 I915_WRITE(FP1(pipe
), fp2
);
4158 intel_crtc
->lowfreq_avail
= true;
4160 I915_WRITE(FP1(pipe
), fp
);
4164 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
4165 struct drm_display_mode
*adjusted_mode
)
4167 struct drm_device
*dev
= crtc
->dev
;
4168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4169 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4170 int pipe
= intel_crtc
->pipe
;
4173 temp
= I915_READ(LVDS
);
4174 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4176 temp
|= LVDS_PIPEB_SELECT
;
4178 temp
&= ~LVDS_PIPEB_SELECT
;
4180 /* set the corresponsding LVDS_BORDER bit */
4181 temp
|= dev_priv
->lvds_border_bits
;
4182 /* Set the B0-B3 data pairs corresponding to whether we're going to
4183 * set the DPLLs for dual-channel mode or not.
4186 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4188 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4190 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4191 * appropriately here, but we need to look more thoroughly into how
4192 * panels behave in the two modes.
4194 /* set the dithering flag on LVDS as needed */
4195 if (INTEL_INFO(dev
)->gen
>= 4) {
4196 if (dev_priv
->lvds_dither
)
4197 temp
|= LVDS_ENABLE_DITHER
;
4199 temp
&= ~LVDS_ENABLE_DITHER
;
4201 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4202 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4203 temp
|= LVDS_HSYNC_POLARITY
;
4204 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4205 temp
|= LVDS_VSYNC_POLARITY
;
4206 I915_WRITE(LVDS
, temp
);
4209 static void vlv_update_pll(struct drm_crtc
*crtc
,
4210 struct drm_display_mode
*mode
,
4211 struct drm_display_mode
*adjusted_mode
,
4212 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4215 struct drm_device
*dev
= crtc
->dev
;
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4218 int pipe
= intel_crtc
->pipe
;
4219 u32 dpll
, mdiv
, pdiv
;
4220 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4224 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4225 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4227 dpll
= DPLL_VGA_MODE_DIS
;
4228 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4229 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4230 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4232 I915_WRITE(DPLL(pipe
), dpll
);
4233 POSTING_READ(DPLL(pipe
));
4242 * In Valleyview PLL and program lane counter registers are exposed
4243 * through DPIO interface
4245 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4246 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4247 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4248 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4249 mdiv
|= (1 << DPIO_K_SHIFT
);
4250 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4251 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4253 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4255 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4256 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4257 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4258 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4259 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4261 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4263 dpll
|= DPLL_VCO_ENABLE
;
4264 I915_WRITE(DPLL(pipe
), dpll
);
4265 POSTING_READ(DPLL(pipe
));
4266 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4267 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4269 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4271 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4272 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4274 I915_WRITE(DPLL(pipe
), dpll
);
4276 /* Wait for the clocks to stabilize. */
4277 POSTING_READ(DPLL(pipe
));
4282 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4284 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4288 I915_WRITE(DPLL_MD(pipe
), temp
);
4289 POSTING_READ(DPLL_MD(pipe
));
4291 /* Now program lane control registers */
4292 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4293 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4298 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4300 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4305 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4309 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4310 struct drm_display_mode
*mode
,
4311 struct drm_display_mode
*adjusted_mode
,
4312 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4315 struct drm_device
*dev
= crtc
->dev
;
4316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4318 int pipe
= intel_crtc
->pipe
;
4322 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4324 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4325 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4327 dpll
= DPLL_VGA_MODE_DIS
;
4329 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4330 dpll
|= DPLLB_MODE_LVDS
;
4332 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4334 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4335 if (pixel_multiplier
> 1) {
4336 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4337 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4339 dpll
|= DPLL_DVO_HIGH_SPEED
;
4341 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4342 dpll
|= DPLL_DVO_HIGH_SPEED
;
4344 /* compute bitmask from p1 value */
4345 if (IS_PINEVIEW(dev
))
4346 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4348 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4349 if (IS_G4X(dev
) && reduced_clock
)
4350 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4352 switch (clock
->p2
) {
4354 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4357 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4360 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4363 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4366 if (INTEL_INFO(dev
)->gen
>= 4)
4367 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4369 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4370 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4371 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4372 /* XXX: just matching BIOS for now */
4373 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4375 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4376 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4377 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4379 dpll
|= PLL_REF_INPUT_DREFCLK
;
4381 dpll
|= DPLL_VCO_ENABLE
;
4382 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4383 POSTING_READ(DPLL(pipe
));
4386 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4387 * This is an exception to the general rule that mode_set doesn't turn
4390 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4391 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4393 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4394 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4396 I915_WRITE(DPLL(pipe
), dpll
);
4398 /* Wait for the clocks to stabilize. */
4399 POSTING_READ(DPLL(pipe
));
4402 if (INTEL_INFO(dev
)->gen
>= 4) {
4405 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4407 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4411 I915_WRITE(DPLL_MD(pipe
), temp
);
4413 /* The pixel multiplier can only be updated once the
4414 * DPLL is enabled and the clocks are stable.
4416 * So write it again.
4418 I915_WRITE(DPLL(pipe
), dpll
);
4422 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4423 struct drm_display_mode
*adjusted_mode
,
4424 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4427 struct drm_device
*dev
= crtc
->dev
;
4428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4430 int pipe
= intel_crtc
->pipe
;
4433 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4435 dpll
= DPLL_VGA_MODE_DIS
;
4437 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4438 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4441 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4443 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4445 dpll
|= PLL_P2_DIVIDE_BY_4
;
4448 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4449 /* XXX: just matching BIOS for now */
4450 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4452 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4453 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4454 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4456 dpll
|= PLL_REF_INPUT_DREFCLK
;
4458 dpll
|= DPLL_VCO_ENABLE
;
4459 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4460 POSTING_READ(DPLL(pipe
));
4463 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4464 * This is an exception to the general rule that mode_set doesn't turn
4467 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4468 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4470 I915_WRITE(DPLL(pipe
), dpll
);
4472 /* Wait for the clocks to stabilize. */
4473 POSTING_READ(DPLL(pipe
));
4476 /* The pixel multiplier can only be updated once the
4477 * DPLL is enabled and the clocks are stable.
4479 * So write it again.
4481 I915_WRITE(DPLL(pipe
), dpll
);
4484 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4485 struct drm_display_mode
*mode
,
4486 struct drm_display_mode
*adjusted_mode
)
4488 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 enum pipe pipe
= intel_crtc
->pipe
;
4491 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4492 uint32_t vsyncshift
;
4494 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4495 /* the chip adds 2 halflines automatically */
4496 adjusted_mode
->crtc_vtotal
-= 1;
4497 adjusted_mode
->crtc_vblank_end
-= 1;
4498 vsyncshift
= adjusted_mode
->crtc_hsync_start
4499 - adjusted_mode
->crtc_htotal
/ 2;
4504 if (INTEL_INFO(dev
)->gen
> 3)
4505 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4507 I915_WRITE(HTOTAL(cpu_transcoder
),
4508 (adjusted_mode
->crtc_hdisplay
- 1) |
4509 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4510 I915_WRITE(HBLANK(cpu_transcoder
),
4511 (adjusted_mode
->crtc_hblank_start
- 1) |
4512 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4513 I915_WRITE(HSYNC(cpu_transcoder
),
4514 (adjusted_mode
->crtc_hsync_start
- 1) |
4515 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4517 I915_WRITE(VTOTAL(cpu_transcoder
),
4518 (adjusted_mode
->crtc_vdisplay
- 1) |
4519 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4520 I915_WRITE(VBLANK(cpu_transcoder
),
4521 (adjusted_mode
->crtc_vblank_start
- 1) |
4522 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4523 I915_WRITE(VSYNC(cpu_transcoder
),
4524 (adjusted_mode
->crtc_vsync_start
- 1) |
4525 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4527 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4528 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4529 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4531 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4532 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4533 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4535 /* pipesrc controls the size that is scaled from, which should
4536 * always be the user's requested size.
4538 I915_WRITE(PIPESRC(pipe
),
4539 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4542 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4543 struct drm_display_mode
*mode
,
4544 struct drm_display_mode
*adjusted_mode
,
4546 struct drm_framebuffer
*fb
)
4548 struct drm_device
*dev
= crtc
->dev
;
4549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4550 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4551 int pipe
= intel_crtc
->pipe
;
4552 int plane
= intel_crtc
->plane
;
4553 int refclk
, num_connectors
= 0;
4554 intel_clock_t clock
, reduced_clock
;
4555 u32 dspcntr
, pipeconf
;
4556 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4557 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4558 struct intel_encoder
*encoder
;
4559 const intel_limit_t
*limit
;
4562 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4563 switch (encoder
->type
) {
4564 case INTEL_OUTPUT_LVDS
:
4567 case INTEL_OUTPUT_SDVO
:
4568 case INTEL_OUTPUT_HDMI
:
4570 if (encoder
->needs_tv_clock
)
4573 case INTEL_OUTPUT_TVOUT
:
4576 case INTEL_OUTPUT_DISPLAYPORT
:
4584 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4587 * Returns a set of divisors for the desired target clock with the given
4588 * refclk, or FALSE. The returned values represent the clock equation:
4589 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4591 limit
= intel_limit(crtc
, refclk
);
4592 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4595 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4599 /* Ensure that the cursor is valid for the new mode before changing... */
4600 intel_crtc_update_cursor(crtc
, true);
4602 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4604 * Ensure we match the reduced clock's P to the target clock.
4605 * If the clocks don't match, we can't switch the display clock
4606 * by using the FP0/FP1. In such case we will disable the LVDS
4607 * downclock feature.
4609 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4610 dev_priv
->lvds_downclock
,
4616 if (is_sdvo
&& is_tv
)
4617 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4620 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4621 has_reduced_clock
? &reduced_clock
: NULL
,
4623 else if (IS_VALLEYVIEW(dev
))
4624 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4625 has_reduced_clock
? &reduced_clock
: NULL
,
4628 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4629 has_reduced_clock
? &reduced_clock
: NULL
,
4632 /* setup pipeconf */
4633 pipeconf
= I915_READ(PIPECONF(pipe
));
4635 /* Set up the display plane register */
4636 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4639 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4641 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4643 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4644 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4647 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4651 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4652 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4654 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4657 /* default to 8bpc */
4658 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4660 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4661 pipeconf
|= PIPECONF_BPP_6
|
4662 PIPECONF_DITHER_EN
|
4663 PIPECONF_DITHER_TYPE_SP
;
4667 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4668 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4669 pipeconf
|= PIPECONF_BPP_6
|
4671 I965_PIPECONF_ACTIVE
;
4675 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4676 drm_mode_debug_printmodeline(mode
);
4678 if (HAS_PIPE_CXSR(dev
)) {
4679 if (intel_crtc
->lowfreq_avail
) {
4680 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4681 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4683 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4684 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4688 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4689 if (!IS_GEN2(dev
) &&
4690 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4691 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4693 pipeconf
|= PIPECONF_PROGRESSIVE
;
4695 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4697 /* pipesrc and dspsize control the size that is scaled from,
4698 * which should always be the user's requested size.
4700 I915_WRITE(DSPSIZE(plane
),
4701 ((mode
->vdisplay
- 1) << 16) |
4702 (mode
->hdisplay
- 1));
4703 I915_WRITE(DSPPOS(plane
), 0);
4705 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4706 POSTING_READ(PIPECONF(pipe
));
4707 intel_enable_pipe(dev_priv
, pipe
, false);
4709 intel_wait_for_vblank(dev
, pipe
);
4711 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4712 POSTING_READ(DSPCNTR(plane
));
4714 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4716 intel_update_watermarks(dev
);
4722 * Initialize reference clocks when the driver loads
4724 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4727 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4728 struct intel_encoder
*encoder
;
4730 bool has_lvds
= false;
4731 bool has_cpu_edp
= false;
4732 bool has_pch_edp
= false;
4733 bool has_panel
= false;
4734 bool has_ck505
= false;
4735 bool can_ssc
= false;
4737 /* We need to take the global config into account */
4738 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4740 switch (encoder
->type
) {
4741 case INTEL_OUTPUT_LVDS
:
4745 case INTEL_OUTPUT_EDP
:
4747 if (intel_encoder_is_pch_edp(&encoder
->base
))
4755 if (HAS_PCH_IBX(dev
)) {
4756 has_ck505
= dev_priv
->display_clock_mode
;
4757 can_ssc
= has_ck505
;
4763 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4764 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4767 /* Ironlake: try to setup display ref clock before DPLL
4768 * enabling. This is only under driver's control after
4769 * PCH B stepping, previous chipset stepping should be
4770 * ignoring this setting.
4772 temp
= I915_READ(PCH_DREF_CONTROL
);
4773 /* Always enable nonspread source */
4774 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4777 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4779 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4782 temp
&= ~DREF_SSC_SOURCE_MASK
;
4783 temp
|= DREF_SSC_SOURCE_ENABLE
;
4785 /* SSC must be turned on before enabling the CPU output */
4786 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4787 DRM_DEBUG_KMS("Using SSC on panel\n");
4788 temp
|= DREF_SSC1_ENABLE
;
4790 temp
&= ~DREF_SSC1_ENABLE
;
4792 /* Get SSC going before enabling the outputs */
4793 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4794 POSTING_READ(PCH_DREF_CONTROL
);
4797 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4799 /* Enable CPU source on CPU attached eDP */
4801 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4802 DRM_DEBUG_KMS("Using SSC on eDP\n");
4803 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4806 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4808 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4810 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4811 POSTING_READ(PCH_DREF_CONTROL
);
4814 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4816 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4818 /* Turn off CPU output */
4819 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4821 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4822 POSTING_READ(PCH_DREF_CONTROL
);
4825 /* Turn off the SSC source */
4826 temp
&= ~DREF_SSC_SOURCE_MASK
;
4827 temp
|= DREF_SSC_SOURCE_DISABLE
;
4830 temp
&= ~ DREF_SSC1_ENABLE
;
4832 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4833 POSTING_READ(PCH_DREF_CONTROL
);
4838 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4840 struct drm_device
*dev
= crtc
->dev
;
4841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4842 struct intel_encoder
*encoder
;
4843 struct intel_encoder
*edp_encoder
= NULL
;
4844 int num_connectors
= 0;
4845 bool is_lvds
= false;
4847 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4848 switch (encoder
->type
) {
4849 case INTEL_OUTPUT_LVDS
:
4852 case INTEL_OUTPUT_EDP
:
4853 edp_encoder
= encoder
;
4859 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4860 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4861 dev_priv
->lvds_ssc_freq
);
4862 return dev_priv
->lvds_ssc_freq
* 1000;
4868 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
4869 struct drm_display_mode
*adjusted_mode
,
4872 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4873 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4874 int pipe
= intel_crtc
->pipe
;
4877 val
= I915_READ(PIPECONF(pipe
));
4879 val
&= ~PIPE_BPC_MASK
;
4880 switch (intel_crtc
->bpp
) {
4894 /* Case prevented by intel_choose_pipe_bpp_dither. */
4898 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4900 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4902 val
&= ~PIPECONF_INTERLACE_MASK
;
4903 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4904 val
|= PIPECONF_INTERLACED_ILK
;
4906 val
|= PIPECONF_PROGRESSIVE
;
4908 I915_WRITE(PIPECONF(pipe
), val
);
4909 POSTING_READ(PIPECONF(pipe
));
4912 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
4913 struct drm_display_mode
*adjusted_mode
,
4916 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4918 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4921 val
= I915_READ(PIPECONF(cpu_transcoder
));
4923 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4925 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4927 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
4928 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4929 val
|= PIPECONF_INTERLACED_ILK
;
4931 val
|= PIPECONF_PROGRESSIVE
;
4933 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
4934 POSTING_READ(PIPECONF(cpu_transcoder
));
4937 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
4938 struct drm_display_mode
*adjusted_mode
,
4939 intel_clock_t
*clock
,
4940 bool *has_reduced_clock
,
4941 intel_clock_t
*reduced_clock
)
4943 struct drm_device
*dev
= crtc
->dev
;
4944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4945 struct intel_encoder
*intel_encoder
;
4947 const intel_limit_t
*limit
;
4948 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
4950 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4951 switch (intel_encoder
->type
) {
4952 case INTEL_OUTPUT_LVDS
:
4955 case INTEL_OUTPUT_SDVO
:
4956 case INTEL_OUTPUT_HDMI
:
4958 if (intel_encoder
->needs_tv_clock
)
4961 case INTEL_OUTPUT_TVOUT
:
4967 refclk
= ironlake_get_refclk(crtc
);
4970 * Returns a set of divisors for the desired target clock with the given
4971 * refclk, or FALSE. The returned values represent the clock equation:
4972 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4974 limit
= intel_limit(crtc
, refclk
);
4975 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4980 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4982 * Ensure we match the reduced clock's P to the target clock.
4983 * If the clocks don't match, we can't switch the display clock
4984 * by using the FP0/FP1. In such case we will disable the LVDS
4985 * downclock feature.
4987 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4988 dev_priv
->lvds_downclock
,
4994 if (is_sdvo
&& is_tv
)
4995 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5000 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5001 struct drm_display_mode
*mode
,
5002 struct drm_display_mode
*adjusted_mode
)
5004 struct drm_device
*dev
= crtc
->dev
;
5005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5006 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5007 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5008 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5009 struct fdi_m_n m_n
= {0};
5010 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5011 bool is_dp
= false, is_cpu_edp
= false;
5013 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5014 switch (intel_encoder
->type
) {
5015 case INTEL_OUTPUT_DISPLAYPORT
:
5018 case INTEL_OUTPUT_EDP
:
5020 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5022 edp_encoder
= intel_encoder
;
5028 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5030 /* CPU eDP doesn't require FDI link, so just set DP M/N
5031 according to current link config */
5033 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5035 /* FDI is a binary signal running at ~2.7GHz, encoding
5036 * each output octet as 10 bits. The actual frequency
5037 * is stored as a divider into a 100MHz clock, and the
5038 * mode pixel clock is stored in units of 1KHz.
5039 * Hence the bw of each lane in terms of the mode signal
5042 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5045 /* [e]DP over FDI requires target mode clock instead of link clock. */
5047 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5049 target_clock
= mode
->clock
;
5051 target_clock
= adjusted_mode
->clock
;
5055 * Account for spread spectrum to avoid
5056 * oversubscribing the link. Max center spread
5057 * is 2.5%; use 5% for safety's sake.
5059 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
5060 lane
= bps
/ (link_bw
* 8) + 1;
5063 intel_crtc
->fdi_lanes
= lane
;
5065 if (pixel_multiplier
> 1)
5066 link_bw
*= pixel_multiplier
;
5067 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
5070 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5071 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5072 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5073 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5076 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5077 struct drm_display_mode
*adjusted_mode
,
5078 intel_clock_t
*clock
, u32 fp
)
5080 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5081 struct drm_device
*dev
= crtc
->dev
;
5082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5083 struct intel_encoder
*intel_encoder
;
5085 int factor
, pixel_multiplier
, num_connectors
= 0;
5086 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5087 bool is_dp
= false, is_cpu_edp
= false;
5089 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5090 switch (intel_encoder
->type
) {
5091 case INTEL_OUTPUT_LVDS
:
5094 case INTEL_OUTPUT_SDVO
:
5095 case INTEL_OUTPUT_HDMI
:
5097 if (intel_encoder
->needs_tv_clock
)
5100 case INTEL_OUTPUT_TVOUT
:
5103 case INTEL_OUTPUT_DISPLAYPORT
:
5106 case INTEL_OUTPUT_EDP
:
5108 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5116 /* Enable autotuning of the PLL clock (if permissible) */
5119 if ((intel_panel_use_ssc(dev_priv
) &&
5120 dev_priv
->lvds_ssc_freq
== 100) ||
5121 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
5123 } else if (is_sdvo
&& is_tv
)
5126 if (clock
->m
< factor
* clock
->n
)
5132 dpll
|= DPLLB_MODE_LVDS
;
5134 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5136 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5137 if (pixel_multiplier
> 1) {
5138 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5140 dpll
|= DPLL_DVO_HIGH_SPEED
;
5142 if (is_dp
&& !is_cpu_edp
)
5143 dpll
|= DPLL_DVO_HIGH_SPEED
;
5145 /* compute bitmask from p1 value */
5146 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5148 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5150 switch (clock
->p2
) {
5152 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5155 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5158 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5161 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5165 if (is_sdvo
&& is_tv
)
5166 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5168 /* XXX: just matching BIOS for now */
5169 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5171 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5172 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5174 dpll
|= PLL_REF_INPUT_DREFCLK
;
5179 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5180 struct drm_display_mode
*mode
,
5181 struct drm_display_mode
*adjusted_mode
,
5183 struct drm_framebuffer
*fb
)
5185 struct drm_device
*dev
= crtc
->dev
;
5186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5188 int pipe
= intel_crtc
->pipe
;
5189 int plane
= intel_crtc
->plane
;
5190 int num_connectors
= 0;
5191 intel_clock_t clock
, reduced_clock
;
5192 u32 dpll
, fp
= 0, fp2
= 0;
5193 bool ok
, has_reduced_clock
= false;
5194 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5195 struct intel_encoder
*encoder
;
5200 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5201 switch (encoder
->type
) {
5202 case INTEL_OUTPUT_LVDS
:
5205 case INTEL_OUTPUT_DISPLAYPORT
:
5208 case INTEL_OUTPUT_EDP
:
5210 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5218 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5219 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5221 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5222 &has_reduced_clock
, &reduced_clock
);
5224 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5228 /* Ensure that the cursor is valid for the new mode before changing... */
5229 intel_crtc_update_cursor(crtc
, true);
5231 /* determine panel color depth */
5232 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5234 if (is_lvds
&& dev_priv
->lvds_dither
)
5237 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5238 if (has_reduced_clock
)
5239 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5242 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5244 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5245 drm_mode_debug_printmodeline(mode
);
5247 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5249 struct intel_pch_pll
*pll
;
5251 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5253 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5258 intel_put_pch_pll(intel_crtc
);
5260 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5261 * This is an exception to the general rule that mode_set doesn't turn
5265 temp
= I915_READ(PCH_LVDS
);
5266 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5267 if (HAS_PCH_CPT(dev
)) {
5268 temp
&= ~PORT_TRANS_SEL_MASK
;
5269 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5272 temp
|= LVDS_PIPEB_SELECT
;
5274 temp
&= ~LVDS_PIPEB_SELECT
;
5277 /* set the corresponsding LVDS_BORDER bit */
5278 temp
|= dev_priv
->lvds_border_bits
;
5279 /* Set the B0-B3 data pairs corresponding to whether we're going to
5280 * set the DPLLs for dual-channel mode or not.
5283 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5285 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5287 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5288 * appropriately here, but we need to look more thoroughly into how
5289 * panels behave in the two modes.
5291 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5292 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5293 temp
|= LVDS_HSYNC_POLARITY
;
5294 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5295 temp
|= LVDS_VSYNC_POLARITY
;
5296 I915_WRITE(PCH_LVDS
, temp
);
5299 if (is_dp
&& !is_cpu_edp
) {
5300 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5302 /* For non-DP output, clear any trans DP clock recovery setting.*/
5303 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5304 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5305 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5306 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5309 if (intel_crtc
->pch_pll
) {
5310 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5312 /* Wait for the clocks to stabilize. */
5313 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5316 /* The pixel multiplier can only be updated once the
5317 * DPLL is enabled and the clocks are stable.
5319 * So write it again.
5321 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5324 intel_crtc
->lowfreq_avail
= false;
5325 if (intel_crtc
->pch_pll
) {
5326 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5327 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5328 intel_crtc
->lowfreq_avail
= true;
5330 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5334 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5336 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5339 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5341 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5343 intel_wait_for_vblank(dev
, pipe
);
5345 /* Set up the display plane register */
5346 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5347 POSTING_READ(DSPCNTR(plane
));
5349 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5351 intel_update_watermarks(dev
);
5353 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5358 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5359 struct drm_display_mode
*mode
,
5360 struct drm_display_mode
*adjusted_mode
,
5362 struct drm_framebuffer
*fb
)
5364 struct drm_device
*dev
= crtc
->dev
;
5365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5366 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5367 int pipe
= intel_crtc
->pipe
;
5368 int plane
= intel_crtc
->plane
;
5369 int num_connectors
= 0;
5370 intel_clock_t clock
, reduced_clock
;
5371 u32 dpll
= 0, fp
= 0, fp2
= 0;
5372 bool ok
, has_reduced_clock
= false;
5373 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5374 struct intel_encoder
*encoder
;
5379 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5380 switch (encoder
->type
) {
5381 case INTEL_OUTPUT_LVDS
:
5384 case INTEL_OUTPUT_DISPLAYPORT
:
5387 case INTEL_OUTPUT_EDP
:
5389 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5398 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5400 intel_crtc
->cpu_transcoder
= pipe
;
5402 /* We are not sure yet this won't happen. */
5403 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5404 INTEL_PCH_TYPE(dev
));
5406 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5407 num_connectors
, pipe_name(pipe
));
5409 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5410 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5412 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5414 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5417 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5418 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5422 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5427 /* Ensure that the cursor is valid for the new mode before changing... */
5428 intel_crtc_update_cursor(crtc
, true);
5430 /* determine panel color depth */
5431 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5433 if (is_lvds
&& dev_priv
->lvds_dither
)
5436 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5437 drm_mode_debug_printmodeline(mode
);
5439 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5440 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5441 if (has_reduced_clock
)
5442 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5445 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
,
5448 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5449 * own on pre-Haswell/LPT generation */
5451 struct intel_pch_pll
*pll
;
5453 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5455 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5460 intel_put_pch_pll(intel_crtc
);
5462 /* The LVDS pin pair needs to be on before the DPLLs are
5463 * enabled. This is an exception to the general rule that
5464 * mode_set doesn't turn things on.
5467 temp
= I915_READ(PCH_LVDS
);
5468 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5469 if (HAS_PCH_CPT(dev
)) {
5470 temp
&= ~PORT_TRANS_SEL_MASK
;
5471 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5474 temp
|= LVDS_PIPEB_SELECT
;
5476 temp
&= ~LVDS_PIPEB_SELECT
;
5479 /* set the corresponsding LVDS_BORDER bit */
5480 temp
|= dev_priv
->lvds_border_bits
;
5481 /* Set the B0-B3 data pairs corresponding to whether
5482 * we're going to set the DPLLs for dual-channel mode or
5486 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5488 temp
&= ~(LVDS_B0B3_POWER_UP
|
5489 LVDS_CLKB_POWER_UP
);
5491 /* It would be nice to set 24 vs 18-bit mode
5492 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5493 * look more thoroughly into how panels behave in the
5496 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5497 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5498 temp
|= LVDS_HSYNC_POLARITY
;
5499 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5500 temp
|= LVDS_VSYNC_POLARITY
;
5501 I915_WRITE(PCH_LVDS
, temp
);
5505 if (is_dp
&& !is_cpu_edp
) {
5506 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5508 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5509 /* For non-DP output, clear any trans DP clock recovery
5511 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5512 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5513 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5514 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5518 intel_crtc
->lowfreq_avail
= false;
5519 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5520 if (intel_crtc
->pch_pll
) {
5521 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5523 /* Wait for the clocks to stabilize. */
5524 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5527 /* The pixel multiplier can only be updated once the
5528 * DPLL is enabled and the clocks are stable.
5530 * So write it again.
5532 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5535 if (intel_crtc
->pch_pll
) {
5536 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5537 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5538 intel_crtc
->lowfreq_avail
= true;
5540 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5545 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5547 if (!is_dp
|| is_cpu_edp
)
5548 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5550 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5552 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5554 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5556 /* Set up the display plane register */
5557 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5558 POSTING_READ(DSPCNTR(plane
));
5560 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5562 intel_update_watermarks(dev
);
5564 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5569 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5570 struct drm_display_mode
*mode
,
5571 struct drm_display_mode
*adjusted_mode
,
5573 struct drm_framebuffer
*fb
)
5575 struct drm_device
*dev
= crtc
->dev
;
5576 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5577 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5578 int pipe
= intel_crtc
->pipe
;
5581 drm_vblank_pre_modeset(dev
, pipe
);
5583 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5585 drm_vblank_post_modeset(dev
, pipe
);
5590 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5591 int reg_eldv
, uint32_t bits_eldv
,
5592 int reg_elda
, uint32_t bits_elda
,
5595 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5596 uint8_t *eld
= connector
->eld
;
5599 i
= I915_READ(reg_eldv
);
5608 i
= I915_READ(reg_elda
);
5610 I915_WRITE(reg_elda
, i
);
5612 for (i
= 0; i
< eld
[2]; i
++)
5613 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5619 static void g4x_write_eld(struct drm_connector
*connector
,
5620 struct drm_crtc
*crtc
)
5622 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5623 uint8_t *eld
= connector
->eld
;
5628 i
= I915_READ(G4X_AUD_VID_DID
);
5630 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5631 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5633 eldv
= G4X_ELDV_DEVCTG
;
5635 if (intel_eld_uptodate(connector
,
5636 G4X_AUD_CNTL_ST
, eldv
,
5637 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5638 G4X_HDMIW_HDMIEDID
))
5641 i
= I915_READ(G4X_AUD_CNTL_ST
);
5642 i
&= ~(eldv
| G4X_ELD_ADDR
);
5643 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5644 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5649 len
= min_t(uint8_t, eld
[2], len
);
5650 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5651 for (i
= 0; i
< len
; i
++)
5652 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5654 i
= I915_READ(G4X_AUD_CNTL_ST
);
5656 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5659 static void haswell_write_eld(struct drm_connector
*connector
,
5660 struct drm_crtc
*crtc
)
5662 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5663 uint8_t *eld
= connector
->eld
;
5664 struct drm_device
*dev
= crtc
->dev
;
5668 int pipe
= to_intel_crtc(crtc
)->pipe
;
5671 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5672 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5673 int aud_config
= HSW_AUD_CFG(pipe
);
5674 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5677 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5679 /* Audio output enable */
5680 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5681 tmp
= I915_READ(aud_cntrl_st2
);
5682 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5683 I915_WRITE(aud_cntrl_st2
, tmp
);
5685 /* Wait for 1 vertical blank */
5686 intel_wait_for_vblank(dev
, pipe
);
5688 /* Set ELD valid state */
5689 tmp
= I915_READ(aud_cntrl_st2
);
5690 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5691 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5692 I915_WRITE(aud_cntrl_st2
, tmp
);
5693 tmp
= I915_READ(aud_cntrl_st2
);
5694 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5696 /* Enable HDMI mode */
5697 tmp
= I915_READ(aud_config
);
5698 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5699 /* clear N_programing_enable and N_value_index */
5700 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5701 I915_WRITE(aud_config
, tmp
);
5703 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5705 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5707 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5708 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5709 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5710 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5712 I915_WRITE(aud_config
, 0);
5714 if (intel_eld_uptodate(connector
,
5715 aud_cntrl_st2
, eldv
,
5716 aud_cntl_st
, IBX_ELD_ADDRESS
,
5720 i
= I915_READ(aud_cntrl_st2
);
5722 I915_WRITE(aud_cntrl_st2
, i
);
5727 i
= I915_READ(aud_cntl_st
);
5728 i
&= ~IBX_ELD_ADDRESS
;
5729 I915_WRITE(aud_cntl_st
, i
);
5730 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5731 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5733 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5734 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5735 for (i
= 0; i
< len
; i
++)
5736 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5738 i
= I915_READ(aud_cntrl_st2
);
5740 I915_WRITE(aud_cntrl_st2
, i
);
5744 static void ironlake_write_eld(struct drm_connector
*connector
,
5745 struct drm_crtc
*crtc
)
5747 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5748 uint8_t *eld
= connector
->eld
;
5756 int pipe
= to_intel_crtc(crtc
)->pipe
;
5758 if (HAS_PCH_IBX(connector
->dev
)) {
5759 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5760 aud_config
= IBX_AUD_CFG(pipe
);
5761 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5762 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5764 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5765 aud_config
= CPT_AUD_CFG(pipe
);
5766 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5767 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5770 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5772 i
= I915_READ(aud_cntl_st
);
5773 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5775 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5776 /* operate blindly on all ports */
5777 eldv
= IBX_ELD_VALIDB
;
5778 eldv
|= IBX_ELD_VALIDB
<< 4;
5779 eldv
|= IBX_ELD_VALIDB
<< 8;
5781 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5782 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5785 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5786 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5787 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5788 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5790 I915_WRITE(aud_config
, 0);
5792 if (intel_eld_uptodate(connector
,
5793 aud_cntrl_st2
, eldv
,
5794 aud_cntl_st
, IBX_ELD_ADDRESS
,
5798 i
= I915_READ(aud_cntrl_st2
);
5800 I915_WRITE(aud_cntrl_st2
, i
);
5805 i
= I915_READ(aud_cntl_st
);
5806 i
&= ~IBX_ELD_ADDRESS
;
5807 I915_WRITE(aud_cntl_st
, i
);
5809 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5810 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5811 for (i
= 0; i
< len
; i
++)
5812 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5814 i
= I915_READ(aud_cntrl_st2
);
5816 I915_WRITE(aud_cntrl_st2
, i
);
5819 void intel_write_eld(struct drm_encoder
*encoder
,
5820 struct drm_display_mode
*mode
)
5822 struct drm_crtc
*crtc
= encoder
->crtc
;
5823 struct drm_connector
*connector
;
5824 struct drm_device
*dev
= encoder
->dev
;
5825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5827 connector
= drm_select_eld(encoder
, mode
);
5831 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5833 drm_get_connector_name(connector
),
5834 connector
->encoder
->base
.id
,
5835 drm_get_encoder_name(connector
->encoder
));
5837 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5839 if (dev_priv
->display
.write_eld
)
5840 dev_priv
->display
.write_eld(connector
, crtc
);
5843 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5844 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5846 struct drm_device
*dev
= crtc
->dev
;
5847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5849 int palreg
= PALETTE(intel_crtc
->pipe
);
5852 /* The clocks have to be on to load the palette. */
5853 if (!crtc
->enabled
|| !intel_crtc
->active
)
5856 /* use legacy palette for Ironlake */
5857 if (HAS_PCH_SPLIT(dev
))
5858 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5860 for (i
= 0; i
< 256; i
++) {
5861 I915_WRITE(palreg
+ 4 * i
,
5862 (intel_crtc
->lut_r
[i
] << 16) |
5863 (intel_crtc
->lut_g
[i
] << 8) |
5864 intel_crtc
->lut_b
[i
]);
5868 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5870 struct drm_device
*dev
= crtc
->dev
;
5871 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5873 bool visible
= base
!= 0;
5876 if (intel_crtc
->cursor_visible
== visible
)
5879 cntl
= I915_READ(_CURACNTR
);
5881 /* On these chipsets we can only modify the base whilst
5882 * the cursor is disabled.
5884 I915_WRITE(_CURABASE
, base
);
5886 cntl
&= ~(CURSOR_FORMAT_MASK
);
5887 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5888 cntl
|= CURSOR_ENABLE
|
5889 CURSOR_GAMMA_ENABLE
|
5892 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5893 I915_WRITE(_CURACNTR
, cntl
);
5895 intel_crtc
->cursor_visible
= visible
;
5898 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5900 struct drm_device
*dev
= crtc
->dev
;
5901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5902 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5903 int pipe
= intel_crtc
->pipe
;
5904 bool visible
= base
!= 0;
5906 if (intel_crtc
->cursor_visible
!= visible
) {
5907 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5909 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5910 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5911 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5913 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5914 cntl
|= CURSOR_MODE_DISABLE
;
5916 I915_WRITE(CURCNTR(pipe
), cntl
);
5918 intel_crtc
->cursor_visible
= visible
;
5920 /* and commit changes on next vblank */
5921 I915_WRITE(CURBASE(pipe
), base
);
5924 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5926 struct drm_device
*dev
= crtc
->dev
;
5927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5928 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5929 int pipe
= intel_crtc
->pipe
;
5930 bool visible
= base
!= 0;
5932 if (intel_crtc
->cursor_visible
!= visible
) {
5933 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5935 cntl
&= ~CURSOR_MODE
;
5936 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5938 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5939 cntl
|= CURSOR_MODE_DISABLE
;
5941 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5943 intel_crtc
->cursor_visible
= visible
;
5945 /* and commit changes on next vblank */
5946 I915_WRITE(CURBASE_IVB(pipe
), base
);
5949 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5950 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5953 struct drm_device
*dev
= crtc
->dev
;
5954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5955 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5956 int pipe
= intel_crtc
->pipe
;
5957 int x
= intel_crtc
->cursor_x
;
5958 int y
= intel_crtc
->cursor_y
;
5964 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5965 base
= intel_crtc
->cursor_addr
;
5966 if (x
> (int) crtc
->fb
->width
)
5969 if (y
> (int) crtc
->fb
->height
)
5975 if (x
+ intel_crtc
->cursor_width
< 0)
5978 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5981 pos
|= x
<< CURSOR_X_SHIFT
;
5984 if (y
+ intel_crtc
->cursor_height
< 0)
5987 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5990 pos
|= y
<< CURSOR_Y_SHIFT
;
5992 visible
= base
!= 0;
5993 if (!visible
&& !intel_crtc
->cursor_visible
)
5996 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5997 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5998 ivb_update_cursor(crtc
, base
);
6000 I915_WRITE(CURPOS(pipe
), pos
);
6001 if (IS_845G(dev
) || IS_I865G(dev
))
6002 i845_update_cursor(crtc
, base
);
6004 i9xx_update_cursor(crtc
, base
);
6008 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6009 struct drm_file
*file
,
6011 uint32_t width
, uint32_t height
)
6013 struct drm_device
*dev
= crtc
->dev
;
6014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6016 struct drm_i915_gem_object
*obj
;
6020 /* if we want to turn off the cursor ignore width and height */
6022 DRM_DEBUG_KMS("cursor off\n");
6025 mutex_lock(&dev
->struct_mutex
);
6029 /* Currently we only support 64x64 cursors */
6030 if (width
!= 64 || height
!= 64) {
6031 DRM_ERROR("we currently only support 64x64 cursors\n");
6035 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6036 if (&obj
->base
== NULL
)
6039 if (obj
->base
.size
< width
* height
* 4) {
6040 DRM_ERROR("buffer is to small\n");
6045 /* we only need to pin inside GTT if cursor is non-phy */
6046 mutex_lock(&dev
->struct_mutex
);
6047 if (!dev_priv
->info
->cursor_needs_physical
) {
6048 if (obj
->tiling_mode
) {
6049 DRM_ERROR("cursor cannot be tiled\n");
6054 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6056 DRM_ERROR("failed to move cursor bo into the GTT\n");
6060 ret
= i915_gem_object_put_fence(obj
);
6062 DRM_ERROR("failed to release fence for cursor");
6066 addr
= obj
->gtt_offset
;
6068 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6069 ret
= i915_gem_attach_phys_object(dev
, obj
,
6070 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6073 DRM_ERROR("failed to attach phys object\n");
6076 addr
= obj
->phys_obj
->handle
->busaddr
;
6080 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6083 if (intel_crtc
->cursor_bo
) {
6084 if (dev_priv
->info
->cursor_needs_physical
) {
6085 if (intel_crtc
->cursor_bo
!= obj
)
6086 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6088 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6089 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6092 mutex_unlock(&dev
->struct_mutex
);
6094 intel_crtc
->cursor_addr
= addr
;
6095 intel_crtc
->cursor_bo
= obj
;
6096 intel_crtc
->cursor_width
= width
;
6097 intel_crtc
->cursor_height
= height
;
6099 intel_crtc_update_cursor(crtc
, true);
6103 i915_gem_object_unpin(obj
);
6105 mutex_unlock(&dev
->struct_mutex
);
6107 drm_gem_object_unreference_unlocked(&obj
->base
);
6111 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6113 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6115 intel_crtc
->cursor_x
= x
;
6116 intel_crtc
->cursor_y
= y
;
6118 intel_crtc_update_cursor(crtc
, true);
6123 /** Sets the color ramps on behalf of RandR */
6124 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6125 u16 blue
, int regno
)
6127 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6129 intel_crtc
->lut_r
[regno
] = red
>> 8;
6130 intel_crtc
->lut_g
[regno
] = green
>> 8;
6131 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6134 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6135 u16
*blue
, int regno
)
6137 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6139 *red
= intel_crtc
->lut_r
[regno
] << 8;
6140 *green
= intel_crtc
->lut_g
[regno
] << 8;
6141 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6144 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6145 u16
*blue
, uint32_t start
, uint32_t size
)
6147 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6148 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6150 for (i
= start
; i
< end
; i
++) {
6151 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6152 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6153 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6156 intel_crtc_load_lut(crtc
);
6160 * Get a pipe with a simple mode set on it for doing load-based monitor
6163 * It will be up to the load-detect code to adjust the pipe as appropriate for
6164 * its requirements. The pipe will be connected to no other encoders.
6166 * Currently this code will only succeed if there is a pipe with no encoders
6167 * configured for it. In the future, it could choose to temporarily disable
6168 * some outputs to free up a pipe for its use.
6170 * \return crtc, or NULL if no pipes are available.
6173 /* VESA 640x480x72Hz mode to set on the pipe */
6174 static struct drm_display_mode load_detect_mode
= {
6175 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6176 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6179 static struct drm_framebuffer
*
6180 intel_framebuffer_create(struct drm_device
*dev
,
6181 struct drm_mode_fb_cmd2
*mode_cmd
,
6182 struct drm_i915_gem_object
*obj
)
6184 struct intel_framebuffer
*intel_fb
;
6187 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6189 drm_gem_object_unreference_unlocked(&obj
->base
);
6190 return ERR_PTR(-ENOMEM
);
6193 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6195 drm_gem_object_unreference_unlocked(&obj
->base
);
6197 return ERR_PTR(ret
);
6200 return &intel_fb
->base
;
6204 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6206 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6207 return ALIGN(pitch
, 64);
6211 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6213 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6214 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6217 static struct drm_framebuffer
*
6218 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6219 struct drm_display_mode
*mode
,
6222 struct drm_i915_gem_object
*obj
;
6223 struct drm_mode_fb_cmd2 mode_cmd
;
6225 obj
= i915_gem_alloc_object(dev
,
6226 intel_framebuffer_size_for_mode(mode
, bpp
));
6228 return ERR_PTR(-ENOMEM
);
6230 mode_cmd
.width
= mode
->hdisplay
;
6231 mode_cmd
.height
= mode
->vdisplay
;
6232 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6234 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6236 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6239 static struct drm_framebuffer
*
6240 mode_fits_in_fbdev(struct drm_device
*dev
,
6241 struct drm_display_mode
*mode
)
6243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6244 struct drm_i915_gem_object
*obj
;
6245 struct drm_framebuffer
*fb
;
6247 if (dev_priv
->fbdev
== NULL
)
6250 obj
= dev_priv
->fbdev
->ifb
.obj
;
6254 fb
= &dev_priv
->fbdev
->ifb
.base
;
6255 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6256 fb
->bits_per_pixel
))
6259 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6265 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6266 struct drm_display_mode
*mode
,
6267 struct intel_load_detect_pipe
*old
)
6269 struct intel_crtc
*intel_crtc
;
6270 struct intel_encoder
*intel_encoder
=
6271 intel_attached_encoder(connector
);
6272 struct drm_crtc
*possible_crtc
;
6273 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6274 struct drm_crtc
*crtc
= NULL
;
6275 struct drm_device
*dev
= encoder
->dev
;
6276 struct drm_framebuffer
*fb
;
6279 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6280 connector
->base
.id
, drm_get_connector_name(connector
),
6281 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6284 * Algorithm gets a little messy:
6286 * - if the connector already has an assigned crtc, use it (but make
6287 * sure it's on first)
6289 * - try to find the first unused crtc that can drive this connector,
6290 * and use that if we find one
6293 /* See if we already have a CRTC for this connector */
6294 if (encoder
->crtc
) {
6295 crtc
= encoder
->crtc
;
6297 old
->dpms_mode
= connector
->dpms
;
6298 old
->load_detect_temp
= false;
6300 /* Make sure the crtc and connector are running */
6301 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6302 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6307 /* Find an unused one (if possible) */
6308 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6310 if (!(encoder
->possible_crtcs
& (1 << i
)))
6312 if (!possible_crtc
->enabled
) {
6313 crtc
= possible_crtc
;
6319 * If we didn't find an unused CRTC, don't use any.
6322 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6326 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6327 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6329 intel_crtc
= to_intel_crtc(crtc
);
6330 old
->dpms_mode
= connector
->dpms
;
6331 old
->load_detect_temp
= true;
6332 old
->release_fb
= NULL
;
6335 mode
= &load_detect_mode
;
6337 /* We need a framebuffer large enough to accommodate all accesses
6338 * that the plane may generate whilst we perform load detection.
6339 * We can not rely on the fbcon either being present (we get called
6340 * during its initialisation to detect all boot displays, or it may
6341 * not even exist) or that it is large enough to satisfy the
6344 fb
= mode_fits_in_fbdev(dev
, mode
);
6346 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6347 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6348 old
->release_fb
= fb
;
6350 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6352 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6356 if (!intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6357 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6358 if (old
->release_fb
)
6359 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6363 /* let the connector get through one full cycle before testing */
6364 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6368 connector
->encoder
= NULL
;
6369 encoder
->crtc
= NULL
;
6373 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6374 struct intel_load_detect_pipe
*old
)
6376 struct intel_encoder
*intel_encoder
=
6377 intel_attached_encoder(connector
);
6378 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6381 connector
->base
.id
, drm_get_connector_name(connector
),
6382 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6384 if (old
->load_detect_temp
) {
6385 struct drm_crtc
*crtc
= encoder
->crtc
;
6387 to_intel_connector(connector
)->new_encoder
= NULL
;
6388 intel_encoder
->new_crtc
= NULL
;
6389 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6391 if (old
->release_fb
)
6392 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6397 /* Switch crtc and encoder back off if necessary */
6398 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6399 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6402 /* Returns the clock of the currently programmed mode of the given pipe. */
6403 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6406 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6407 int pipe
= intel_crtc
->pipe
;
6408 u32 dpll
= I915_READ(DPLL(pipe
));
6410 intel_clock_t clock
;
6412 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6413 fp
= I915_READ(FP0(pipe
));
6415 fp
= I915_READ(FP1(pipe
));
6417 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6418 if (IS_PINEVIEW(dev
)) {
6419 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6420 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6422 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6423 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6426 if (!IS_GEN2(dev
)) {
6427 if (IS_PINEVIEW(dev
))
6428 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6429 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6431 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6432 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6434 switch (dpll
& DPLL_MODE_MASK
) {
6435 case DPLLB_MODE_DAC_SERIAL
:
6436 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6439 case DPLLB_MODE_LVDS
:
6440 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6444 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6445 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6449 /* XXX: Handle the 100Mhz refclk */
6450 intel_clock(dev
, 96000, &clock
);
6452 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6455 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6456 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6459 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6460 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6461 /* XXX: might not be 66MHz */
6462 intel_clock(dev
, 66000, &clock
);
6464 intel_clock(dev
, 48000, &clock
);
6466 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6469 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6470 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6472 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6477 intel_clock(dev
, 48000, &clock
);
6481 /* XXX: It would be nice to validate the clocks, but we can't reuse
6482 * i830PllIsValid() because it relies on the xf86_config connector
6483 * configuration being accurate, which it isn't necessarily.
6489 /** Returns the currently programmed mode of the given pipe. */
6490 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6491 struct drm_crtc
*crtc
)
6493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6494 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6495 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6496 struct drm_display_mode
*mode
;
6497 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6498 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6499 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6500 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6502 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6506 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6507 mode
->hdisplay
= (htot
& 0xffff) + 1;
6508 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6509 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6510 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6511 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6512 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6513 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6514 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6516 drm_mode_set_name(mode
);
6521 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6523 struct drm_device
*dev
= crtc
->dev
;
6524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6525 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6526 int pipe
= intel_crtc
->pipe
;
6527 int dpll_reg
= DPLL(pipe
);
6530 if (HAS_PCH_SPLIT(dev
))
6533 if (!dev_priv
->lvds_downclock_avail
)
6536 dpll
= I915_READ(dpll_reg
);
6537 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6538 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6540 assert_panel_unlocked(dev_priv
, pipe
);
6542 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6543 I915_WRITE(dpll_reg
, dpll
);
6544 intel_wait_for_vblank(dev
, pipe
);
6546 dpll
= I915_READ(dpll_reg
);
6547 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6548 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6552 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6554 struct drm_device
*dev
= crtc
->dev
;
6555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6556 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6558 if (HAS_PCH_SPLIT(dev
))
6561 if (!dev_priv
->lvds_downclock_avail
)
6565 * Since this is called by a timer, we should never get here in
6568 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6569 int pipe
= intel_crtc
->pipe
;
6570 int dpll_reg
= DPLL(pipe
);
6573 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6575 assert_panel_unlocked(dev_priv
, pipe
);
6577 dpll
= I915_READ(dpll_reg
);
6578 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6579 I915_WRITE(dpll_reg
, dpll
);
6580 intel_wait_for_vblank(dev
, pipe
);
6581 dpll
= I915_READ(dpll_reg
);
6582 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6583 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6588 void intel_mark_busy(struct drm_device
*dev
)
6590 i915_update_gfx_val(dev
->dev_private
);
6593 void intel_mark_idle(struct drm_device
*dev
)
6597 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6599 struct drm_device
*dev
= obj
->base
.dev
;
6600 struct drm_crtc
*crtc
;
6602 if (!i915_powersave
)
6605 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6609 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6610 intel_increase_pllclock(crtc
);
6614 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6616 struct drm_device
*dev
= obj
->base
.dev
;
6617 struct drm_crtc
*crtc
;
6619 if (!i915_powersave
)
6622 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6626 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6627 intel_decrease_pllclock(crtc
);
6631 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6633 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6634 struct drm_device
*dev
= crtc
->dev
;
6635 struct intel_unpin_work
*work
;
6636 unsigned long flags
;
6638 spin_lock_irqsave(&dev
->event_lock
, flags
);
6639 work
= intel_crtc
->unpin_work
;
6640 intel_crtc
->unpin_work
= NULL
;
6641 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6644 cancel_work_sync(&work
->work
);
6648 drm_crtc_cleanup(crtc
);
6653 static void intel_unpin_work_fn(struct work_struct
*__work
)
6655 struct intel_unpin_work
*work
=
6656 container_of(__work
, struct intel_unpin_work
, work
);
6658 mutex_lock(&work
->dev
->struct_mutex
);
6659 intel_unpin_fb_obj(work
->old_fb_obj
);
6660 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6661 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6663 intel_update_fbc(work
->dev
);
6664 mutex_unlock(&work
->dev
->struct_mutex
);
6668 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6669 struct drm_crtc
*crtc
)
6671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6673 struct intel_unpin_work
*work
;
6674 struct drm_i915_gem_object
*obj
;
6675 struct drm_pending_vblank_event
*e
;
6676 struct timeval tvbl
;
6677 unsigned long flags
;
6679 /* Ignore early vblank irqs */
6680 if (intel_crtc
== NULL
)
6683 spin_lock_irqsave(&dev
->event_lock
, flags
);
6684 work
= intel_crtc
->unpin_work
;
6685 if (work
== NULL
|| !work
->pending
) {
6686 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6690 intel_crtc
->unpin_work
= NULL
;
6694 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6696 e
->event
.tv_sec
= tvbl
.tv_sec
;
6697 e
->event
.tv_usec
= tvbl
.tv_usec
;
6699 list_add_tail(&e
->base
.link
,
6700 &e
->base
.file_priv
->event_list
);
6701 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6704 drm_vblank_put(dev
, intel_crtc
->pipe
);
6706 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6708 obj
= work
->old_fb_obj
;
6710 atomic_clear_mask(1 << intel_crtc
->plane
,
6711 &obj
->pending_flip
.counter
);
6713 wake_up(&dev_priv
->pending_flip_queue
);
6714 schedule_work(&work
->work
);
6716 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6719 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6721 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6722 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6724 do_intel_finish_page_flip(dev
, crtc
);
6727 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6729 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6730 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6732 do_intel_finish_page_flip(dev
, crtc
);
6735 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6737 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6738 struct intel_crtc
*intel_crtc
=
6739 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6740 unsigned long flags
;
6742 spin_lock_irqsave(&dev
->event_lock
, flags
);
6743 if (intel_crtc
->unpin_work
) {
6744 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6745 DRM_ERROR("Prepared flip multiple times\n");
6747 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6749 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6752 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6753 struct drm_crtc
*crtc
,
6754 struct drm_framebuffer
*fb
,
6755 struct drm_i915_gem_object
*obj
)
6757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6760 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6763 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6767 ret
= intel_ring_begin(ring
, 6);
6771 /* Can't queue multiple flips, so wait for the previous
6772 * one to finish before executing the next.
6774 if (intel_crtc
->plane
)
6775 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6777 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6778 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6779 intel_ring_emit(ring
, MI_NOOP
);
6780 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6781 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6782 intel_ring_emit(ring
, fb
->pitches
[0]);
6783 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6784 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6785 intel_ring_advance(ring
);
6789 intel_unpin_fb_obj(obj
);
6794 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6795 struct drm_crtc
*crtc
,
6796 struct drm_framebuffer
*fb
,
6797 struct drm_i915_gem_object
*obj
)
6799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6800 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6802 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6805 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6809 ret
= intel_ring_begin(ring
, 6);
6813 if (intel_crtc
->plane
)
6814 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6816 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6817 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6818 intel_ring_emit(ring
, MI_NOOP
);
6819 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6820 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6821 intel_ring_emit(ring
, fb
->pitches
[0]);
6822 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6823 intel_ring_emit(ring
, MI_NOOP
);
6825 intel_ring_advance(ring
);
6829 intel_unpin_fb_obj(obj
);
6834 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6835 struct drm_crtc
*crtc
,
6836 struct drm_framebuffer
*fb
,
6837 struct drm_i915_gem_object
*obj
)
6839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6841 uint32_t pf
, pipesrc
;
6842 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6845 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6849 ret
= intel_ring_begin(ring
, 4);
6853 /* i965+ uses the linear or tiled offsets from the
6854 * Display Registers (which do not change across a page-flip)
6855 * so we need only reprogram the base address.
6857 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6858 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6859 intel_ring_emit(ring
, fb
->pitches
[0]);
6860 intel_ring_emit(ring
,
6861 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6864 /* XXX Enabling the panel-fitter across page-flip is so far
6865 * untested on non-native modes, so ignore it for now.
6866 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6869 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6870 intel_ring_emit(ring
, pf
| pipesrc
);
6871 intel_ring_advance(ring
);
6875 intel_unpin_fb_obj(obj
);
6880 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6881 struct drm_crtc
*crtc
,
6882 struct drm_framebuffer
*fb
,
6883 struct drm_i915_gem_object
*obj
)
6885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6887 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6888 uint32_t pf
, pipesrc
;
6891 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6895 ret
= intel_ring_begin(ring
, 4);
6899 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6900 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6901 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6902 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6904 /* Contrary to the suggestions in the documentation,
6905 * "Enable Panel Fitter" does not seem to be required when page
6906 * flipping with a non-native mode, and worse causes a normal
6908 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6911 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6912 intel_ring_emit(ring
, pf
| pipesrc
);
6913 intel_ring_advance(ring
);
6917 intel_unpin_fb_obj(obj
);
6923 * On gen7 we currently use the blit ring because (in early silicon at least)
6924 * the render ring doesn't give us interrpts for page flip completion, which
6925 * means clients will hang after the first flip is queued. Fortunately the
6926 * blit ring generates interrupts properly, so use it instead.
6928 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6929 struct drm_crtc
*crtc
,
6930 struct drm_framebuffer
*fb
,
6931 struct drm_i915_gem_object
*obj
)
6933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6935 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6936 uint32_t plane_bit
= 0;
6939 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6943 switch(intel_crtc
->plane
) {
6945 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6948 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6951 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6954 WARN_ONCE(1, "unknown plane in flip command\n");
6959 ret
= intel_ring_begin(ring
, 4);
6963 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6964 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6965 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6966 intel_ring_emit(ring
, (MI_NOOP
));
6967 intel_ring_advance(ring
);
6971 intel_unpin_fb_obj(obj
);
6976 static int intel_default_queue_flip(struct drm_device
*dev
,
6977 struct drm_crtc
*crtc
,
6978 struct drm_framebuffer
*fb
,
6979 struct drm_i915_gem_object
*obj
)
6984 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6985 struct drm_framebuffer
*fb
,
6986 struct drm_pending_vblank_event
*event
)
6988 struct drm_device
*dev
= crtc
->dev
;
6989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6990 struct intel_framebuffer
*intel_fb
;
6991 struct drm_i915_gem_object
*obj
;
6992 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6993 struct intel_unpin_work
*work
;
6994 unsigned long flags
;
6997 /* Can't change pixel format via MI display flips. */
6998 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7002 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7003 * Note that pitch changes could also affect these register.
7005 if (INTEL_INFO(dev
)->gen
> 3 &&
7006 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7007 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7010 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7014 work
->event
= event
;
7015 work
->dev
= crtc
->dev
;
7016 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7017 work
->old_fb_obj
= intel_fb
->obj
;
7018 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7020 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7024 /* We borrow the event spin lock for protecting unpin_work */
7025 spin_lock_irqsave(&dev
->event_lock
, flags
);
7026 if (intel_crtc
->unpin_work
) {
7027 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7029 drm_vblank_put(dev
, intel_crtc
->pipe
);
7031 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7034 intel_crtc
->unpin_work
= work
;
7035 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7037 intel_fb
= to_intel_framebuffer(fb
);
7038 obj
= intel_fb
->obj
;
7040 ret
= i915_mutex_lock_interruptible(dev
);
7044 /* Reference the objects for the scheduled work. */
7045 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7046 drm_gem_object_reference(&obj
->base
);
7050 work
->pending_flip_obj
= obj
;
7052 work
->enable_stall_check
= true;
7054 /* Block clients from rendering to the new back buffer until
7055 * the flip occurs and the object is no longer visible.
7057 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7059 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7061 goto cleanup_pending
;
7063 intel_disable_fbc(dev
);
7064 intel_mark_fb_busy(obj
);
7065 mutex_unlock(&dev
->struct_mutex
);
7067 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7072 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7073 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7074 drm_gem_object_unreference(&obj
->base
);
7075 mutex_unlock(&dev
->struct_mutex
);
7078 spin_lock_irqsave(&dev
->event_lock
, flags
);
7079 intel_crtc
->unpin_work
= NULL
;
7080 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7082 drm_vblank_put(dev
, intel_crtc
->pipe
);
7089 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7090 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7091 .load_lut
= intel_crtc_load_lut
,
7092 .disable
= intel_crtc_noop
,
7095 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7097 struct intel_encoder
*other_encoder
;
7098 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7103 list_for_each_entry(other_encoder
,
7104 &crtc
->dev
->mode_config
.encoder_list
,
7107 if (&other_encoder
->new_crtc
->base
!= crtc
||
7108 encoder
== other_encoder
)
7117 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7118 struct drm_crtc
*crtc
)
7120 struct drm_device
*dev
;
7121 struct drm_crtc
*tmp
;
7124 WARN(!crtc
, "checking null crtc?\n");
7128 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7134 if (encoder
->possible_crtcs
& crtc_mask
)
7140 * intel_modeset_update_staged_output_state
7142 * Updates the staged output configuration state, e.g. after we've read out the
7145 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7147 struct intel_encoder
*encoder
;
7148 struct intel_connector
*connector
;
7150 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7152 connector
->new_encoder
=
7153 to_intel_encoder(connector
->base
.encoder
);
7156 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7159 to_intel_crtc(encoder
->base
.crtc
);
7164 * intel_modeset_commit_output_state
7166 * This function copies the stage display pipe configuration to the real one.
7168 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7170 struct intel_encoder
*encoder
;
7171 struct intel_connector
*connector
;
7173 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7175 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7178 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7180 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7184 static struct drm_display_mode
*
7185 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7186 struct drm_display_mode
*mode
)
7188 struct drm_device
*dev
= crtc
->dev
;
7189 struct drm_display_mode
*adjusted_mode
;
7190 struct drm_encoder_helper_funcs
*encoder_funcs
;
7191 struct intel_encoder
*encoder
;
7193 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7195 return ERR_PTR(-ENOMEM
);
7197 /* Pass our mode to the connectors and the CRTC to give them a chance to
7198 * adjust it according to limitations or connector properties, and also
7199 * a chance to reject the mode entirely.
7201 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7204 if (&encoder
->new_crtc
->base
!= crtc
)
7206 encoder_funcs
= encoder
->base
.helper_private
;
7207 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7209 DRM_DEBUG_KMS("Encoder fixup failed\n");
7214 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7215 DRM_DEBUG_KMS("CRTC fixup failed\n");
7218 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7220 return adjusted_mode
;
7222 drm_mode_destroy(dev
, adjusted_mode
);
7223 return ERR_PTR(-EINVAL
);
7226 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7227 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7229 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7230 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7232 struct intel_crtc
*intel_crtc
;
7233 struct drm_device
*dev
= crtc
->dev
;
7234 struct intel_encoder
*encoder
;
7235 struct intel_connector
*connector
;
7236 struct drm_crtc
*tmp_crtc
;
7238 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7240 /* Check which crtcs have changed outputs connected to them, these need
7241 * to be part of the prepare_pipes mask. We don't (yet) support global
7242 * modeset across multiple crtcs, so modeset_pipes will only have one
7243 * bit set at most. */
7244 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7246 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7249 if (connector
->base
.encoder
) {
7250 tmp_crtc
= connector
->base
.encoder
->crtc
;
7252 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7255 if (connector
->new_encoder
)
7257 1 << connector
->new_encoder
->new_crtc
->pipe
;
7260 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7262 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7265 if (encoder
->base
.crtc
) {
7266 tmp_crtc
= encoder
->base
.crtc
;
7268 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7271 if (encoder
->new_crtc
)
7272 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7275 /* Check for any pipes that will be fully disabled ... */
7276 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7280 /* Don't try to disable disabled crtcs. */
7281 if (!intel_crtc
->base
.enabled
)
7284 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7286 if (encoder
->new_crtc
== intel_crtc
)
7291 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7295 /* set_mode is also used to update properties on life display pipes. */
7296 intel_crtc
= to_intel_crtc(crtc
);
7298 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7300 /* We only support modeset on one single crtc, hence we need to do that
7301 * only for the passed in crtc iff we change anything else than just
7304 * This is actually not true, to be fully compatible with the old crtc
7305 * helper we automatically disable _any_ output (i.e. doesn't need to be
7306 * connected to the crtc we're modesetting on) if it's disconnected.
7307 * Which is a rather nutty api (since changed the output configuration
7308 * without userspace's explicit request can lead to confusion), but
7309 * alas. Hence we currently need to modeset on all pipes we prepare. */
7311 *modeset_pipes
= *prepare_pipes
;
7313 /* ... and mask these out. */
7314 *modeset_pipes
&= ~(*disable_pipes
);
7315 *prepare_pipes
&= ~(*disable_pipes
);
7318 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7320 struct drm_encoder
*encoder
;
7321 struct drm_device
*dev
= crtc
->dev
;
7323 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7324 if (encoder
->crtc
== crtc
)
7331 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7333 struct intel_encoder
*intel_encoder
;
7334 struct intel_crtc
*intel_crtc
;
7335 struct drm_connector
*connector
;
7337 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7339 if (!intel_encoder
->base
.crtc
)
7342 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7344 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7345 intel_encoder
->connectors_active
= false;
7348 intel_modeset_commit_output_state(dev
);
7350 /* Update computed state. */
7351 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7353 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7356 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7357 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7360 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7362 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7363 struct drm_property
*dpms_property
=
7364 dev
->mode_config
.dpms_property
;
7366 connector
->dpms
= DRM_MODE_DPMS_ON
;
7367 drm_connector_property_set_value(connector
,
7371 intel_encoder
= to_intel_encoder(connector
->encoder
);
7372 intel_encoder
->connectors_active
= true;
7378 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7379 list_for_each_entry((intel_crtc), \
7380 &(dev)->mode_config.crtc_list, \
7382 if (mask & (1 <<(intel_crtc)->pipe)) \
7385 intel_modeset_check_state(struct drm_device
*dev
)
7387 struct intel_crtc
*crtc
;
7388 struct intel_encoder
*encoder
;
7389 struct intel_connector
*connector
;
7391 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7393 /* This also checks the encoder/connector hw state with the
7394 * ->get_hw_state callbacks. */
7395 intel_connector_check_state(connector
);
7397 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7398 "connector's staged encoder doesn't match current encoder\n");
7401 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7403 bool enabled
= false;
7404 bool active
= false;
7405 enum pipe pipe
, tracked_pipe
;
7407 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7408 encoder
->base
.base
.id
,
7409 drm_get_encoder_name(&encoder
->base
));
7411 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7412 "encoder's stage crtc doesn't match current crtc\n");
7413 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7414 "encoder's active_connectors set, but no crtc\n");
7416 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7418 if (connector
->base
.encoder
!= &encoder
->base
)
7421 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7424 WARN(!!encoder
->base
.crtc
!= enabled
,
7425 "encoder's enabled state mismatch "
7426 "(expected %i, found %i)\n",
7427 !!encoder
->base
.crtc
, enabled
);
7428 WARN(active
&& !encoder
->base
.crtc
,
7429 "active encoder with no crtc\n");
7431 WARN(encoder
->connectors_active
!= active
,
7432 "encoder's computed active state doesn't match tracked active state "
7433 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7435 active
= encoder
->get_hw_state(encoder
, &pipe
);
7436 WARN(active
!= encoder
->connectors_active
,
7437 "encoder's hw state doesn't match sw tracking "
7438 "(expected %i, found %i)\n",
7439 encoder
->connectors_active
, active
);
7441 if (!encoder
->base
.crtc
)
7444 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7445 WARN(active
&& pipe
!= tracked_pipe
,
7446 "active encoder's pipe doesn't match"
7447 "(expected %i, found %i)\n",
7448 tracked_pipe
, pipe
);
7452 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7454 bool enabled
= false;
7455 bool active
= false;
7457 DRM_DEBUG_KMS("[CRTC:%d]\n",
7458 crtc
->base
.base
.id
);
7460 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7461 "active crtc, but not enabled in sw tracking\n");
7463 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7465 if (encoder
->base
.crtc
!= &crtc
->base
)
7468 if (encoder
->connectors_active
)
7471 WARN(active
!= crtc
->active
,
7472 "crtc's computed active state doesn't match tracked active state "
7473 "(expected %i, found %i)\n", active
, crtc
->active
);
7474 WARN(enabled
!= crtc
->base
.enabled
,
7475 "crtc's computed enabled state doesn't match tracked enabled state "
7476 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7478 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7482 bool intel_set_mode(struct drm_crtc
*crtc
,
7483 struct drm_display_mode
*mode
,
7484 int x
, int y
, struct drm_framebuffer
*fb
)
7486 struct drm_device
*dev
= crtc
->dev
;
7487 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7488 struct drm_display_mode
*adjusted_mode
, saved_mode
, saved_hwmode
;
7489 struct drm_encoder_helper_funcs
*encoder_funcs
;
7490 struct drm_encoder
*encoder
;
7491 struct intel_crtc
*intel_crtc
;
7492 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7495 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7496 &prepare_pipes
, &disable_pipes
);
7498 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7499 modeset_pipes
, prepare_pipes
, disable_pipes
);
7501 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7502 intel_crtc_disable(&intel_crtc
->base
);
7504 saved_hwmode
= crtc
->hwmode
;
7505 saved_mode
= crtc
->mode
;
7507 /* Hack: Because we don't (yet) support global modeset on multiple
7508 * crtcs, we don't keep track of the new mode for more than one crtc.
7509 * Hence simply check whether any bit is set in modeset_pipes in all the
7510 * pieces of code that are not yet converted to deal with mutliple crtcs
7511 * changing their mode at the same time. */
7512 adjusted_mode
= NULL
;
7513 if (modeset_pipes
) {
7514 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7515 if (IS_ERR(adjusted_mode
)) {
7520 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7521 if (intel_crtc
->base
.enabled
)
7522 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7525 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7526 * to set it here already despite that we pass it down the callchain.
7531 /* Only after disabling all output pipelines that will be changed can we
7532 * update the the output configuration. */
7533 intel_modeset_update_state(dev
, prepare_pipes
);
7535 /* Set up the DPLL and any encoders state that needs to adjust or depend
7538 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7539 ret
= !intel_crtc_mode_set(&intel_crtc
->base
,
7540 mode
, adjusted_mode
,
7545 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7547 if (encoder
->crtc
!= &intel_crtc
->base
)
7550 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7551 encoder
->base
.id
, drm_get_encoder_name(encoder
),
7552 mode
->base
.id
, mode
->name
);
7553 encoder_funcs
= encoder
->helper_private
;
7554 encoder_funcs
->mode_set(encoder
, mode
, adjusted_mode
);
7558 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7559 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7560 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7562 if (modeset_pipes
) {
7563 /* Store real post-adjustment hardware mode. */
7564 crtc
->hwmode
= *adjusted_mode
;
7566 /* Calculate and store various constants which
7567 * are later needed by vblank and swap-completion
7568 * timestamping. They are derived from true hwmode.
7570 drm_calc_timestamping_constants(crtc
);
7573 /* FIXME: add subpixel order */
7575 drm_mode_destroy(dev
, adjusted_mode
);
7576 if (!ret
&& crtc
->enabled
) {
7577 crtc
->hwmode
= saved_hwmode
;
7578 crtc
->mode
= saved_mode
;
7580 intel_modeset_check_state(dev
);
7586 #undef for_each_intel_crtc_masked
7588 static void intel_set_config_free(struct intel_set_config
*config
)
7593 kfree(config
->save_connector_encoders
);
7594 kfree(config
->save_encoder_crtcs
);
7598 static int intel_set_config_save_state(struct drm_device
*dev
,
7599 struct intel_set_config
*config
)
7601 struct drm_encoder
*encoder
;
7602 struct drm_connector
*connector
;
7605 config
->save_encoder_crtcs
=
7606 kcalloc(dev
->mode_config
.num_encoder
,
7607 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7608 if (!config
->save_encoder_crtcs
)
7611 config
->save_connector_encoders
=
7612 kcalloc(dev
->mode_config
.num_connector
,
7613 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7614 if (!config
->save_connector_encoders
)
7617 /* Copy data. Note that driver private data is not affected.
7618 * Should anything bad happen only the expected state is
7619 * restored, not the drivers personal bookkeeping.
7622 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7623 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7627 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7628 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7634 static void intel_set_config_restore_state(struct drm_device
*dev
,
7635 struct intel_set_config
*config
)
7637 struct intel_encoder
*encoder
;
7638 struct intel_connector
*connector
;
7642 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7644 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7648 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7649 connector
->new_encoder
=
7650 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7655 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7656 struct intel_set_config
*config
)
7659 /* We should be able to check here if the fb has the same properties
7660 * and then just flip_or_move it */
7661 if (set
->crtc
->fb
!= set
->fb
) {
7662 /* If we have no fb then treat it as a full mode set */
7663 if (set
->crtc
->fb
== NULL
) {
7664 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7665 config
->mode_changed
= true;
7666 } else if (set
->fb
== NULL
) {
7667 config
->mode_changed
= true;
7668 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7669 config
->mode_changed
= true;
7670 } else if (set
->fb
->bits_per_pixel
!=
7671 set
->crtc
->fb
->bits_per_pixel
) {
7672 config
->mode_changed
= true;
7674 config
->fb_changed
= true;
7677 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7678 config
->fb_changed
= true;
7680 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7681 DRM_DEBUG_KMS("modes are different, full mode set\n");
7682 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7683 drm_mode_debug_printmodeline(set
->mode
);
7684 config
->mode_changed
= true;
7689 intel_modeset_stage_output_state(struct drm_device
*dev
,
7690 struct drm_mode_set
*set
,
7691 struct intel_set_config
*config
)
7693 struct drm_crtc
*new_crtc
;
7694 struct intel_connector
*connector
;
7695 struct intel_encoder
*encoder
;
7698 /* The upper layers ensure that we either disabl a crtc or have a list
7699 * of connectors. For paranoia, double-check this. */
7700 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7701 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7704 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7706 /* Otherwise traverse passed in connector list and get encoders
7708 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7709 if (set
->connectors
[ro
] == &connector
->base
) {
7710 connector
->new_encoder
= connector
->encoder
;
7715 /* If we disable the crtc, disable all its connectors. Also, if
7716 * the connector is on the changing crtc but not on the new
7717 * connector list, disable it. */
7718 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7719 connector
->base
.encoder
&&
7720 connector
->base
.encoder
->crtc
== set
->crtc
) {
7721 connector
->new_encoder
= NULL
;
7723 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7724 connector
->base
.base
.id
,
7725 drm_get_connector_name(&connector
->base
));
7729 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7730 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7731 config
->mode_changed
= true;
7734 /* Disable all disconnected encoders. */
7735 if (connector
->base
.status
== connector_status_disconnected
)
7736 connector
->new_encoder
= NULL
;
7738 /* connector->new_encoder is now updated for all connectors. */
7740 /* Update crtc of enabled connectors. */
7742 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7744 if (!connector
->new_encoder
)
7747 new_crtc
= connector
->new_encoder
->base
.crtc
;
7749 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7750 if (set
->connectors
[ro
] == &connector
->base
)
7751 new_crtc
= set
->crtc
;
7754 /* Make sure the new CRTC will work with the encoder */
7755 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7759 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7761 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7762 connector
->base
.base
.id
,
7763 drm_get_connector_name(&connector
->base
),
7767 /* Check for any encoders that needs to be disabled. */
7768 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7770 list_for_each_entry(connector
,
7771 &dev
->mode_config
.connector_list
,
7773 if (connector
->new_encoder
== encoder
) {
7774 WARN_ON(!connector
->new_encoder
->new_crtc
);
7779 encoder
->new_crtc
= NULL
;
7781 /* Only now check for crtc changes so we don't miss encoders
7782 * that will be disabled. */
7783 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
7784 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7785 config
->mode_changed
= true;
7788 /* Now we've also updated encoder->new_crtc for all encoders. */
7793 static int intel_crtc_set_config(struct drm_mode_set
*set
)
7795 struct drm_device
*dev
;
7796 struct drm_mode_set save_set
;
7797 struct intel_set_config
*config
;
7802 BUG_ON(!set
->crtc
->helper_private
);
7807 /* The fb helper likes to play gross jokes with ->mode_set_config.
7808 * Unfortunately the crtc helper doesn't do much at all for this case,
7809 * so we have to cope with this madness until the fb helper is fixed up. */
7810 if (set
->fb
&& set
->num_connectors
== 0)
7814 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7815 set
->crtc
->base
.id
, set
->fb
->base
.id
,
7816 (int)set
->num_connectors
, set
->x
, set
->y
);
7818 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
7821 dev
= set
->crtc
->dev
;
7824 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
7828 ret
= intel_set_config_save_state(dev
, config
);
7832 save_set
.crtc
= set
->crtc
;
7833 save_set
.mode
= &set
->crtc
->mode
;
7834 save_set
.x
= set
->crtc
->x
;
7835 save_set
.y
= set
->crtc
->y
;
7836 save_set
.fb
= set
->crtc
->fb
;
7838 /* Compute whether we need a full modeset, only an fb base update or no
7839 * change at all. In the future we might also check whether only the
7840 * mode changed, e.g. for LVDS where we only change the panel fitter in
7842 intel_set_config_compute_mode_changes(set
, config
);
7844 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
7848 if (config
->mode_changed
) {
7850 DRM_DEBUG_KMS("attempting to set mode from"
7852 drm_mode_debug_printmodeline(set
->mode
);
7855 if (!intel_set_mode(set
->crtc
, set
->mode
,
7856 set
->x
, set
->y
, set
->fb
)) {
7857 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7858 set
->crtc
->base
.id
);
7862 } else if (config
->fb_changed
) {
7863 ret
= intel_pipe_set_base(set
->crtc
,
7864 set
->x
, set
->y
, set
->fb
);
7867 intel_set_config_free(config
);
7872 intel_set_config_restore_state(dev
, config
);
7874 /* Try to restore the config */
7875 if (config
->mode_changed
&&
7876 !intel_set_mode(save_set
.crtc
, save_set
.mode
,
7877 save_set
.x
, save_set
.y
, save_set
.fb
))
7878 DRM_ERROR("failed to restore config after modeset failure\n");
7881 intel_set_config_free(config
);
7885 static const struct drm_crtc_funcs intel_crtc_funcs
= {
7886 .cursor_set
= intel_crtc_cursor_set
,
7887 .cursor_move
= intel_crtc_cursor_move
,
7888 .gamma_set
= intel_crtc_gamma_set
,
7889 .set_config
= intel_crtc_set_config
,
7890 .destroy
= intel_crtc_destroy
,
7891 .page_flip
= intel_crtc_page_flip
,
7894 static void intel_cpu_pll_init(struct drm_device
*dev
)
7896 if (IS_HASWELL(dev
))
7897 intel_ddi_pll_init(dev
);
7900 static void intel_pch_pll_init(struct drm_device
*dev
)
7902 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7905 if (dev_priv
->num_pch_pll
== 0) {
7906 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7910 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
7911 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
7912 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
7913 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
7917 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
7919 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7920 struct intel_crtc
*intel_crtc
;
7923 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
7924 if (intel_crtc
== NULL
)
7927 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
7929 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
7930 for (i
= 0; i
< 256; i
++) {
7931 intel_crtc
->lut_r
[i
] = i
;
7932 intel_crtc
->lut_g
[i
] = i
;
7933 intel_crtc
->lut_b
[i
] = i
;
7936 /* Swap pipes & planes for FBC on pre-965 */
7937 intel_crtc
->pipe
= pipe
;
7938 intel_crtc
->plane
= pipe
;
7939 intel_crtc
->cpu_transcoder
= pipe
;
7940 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
7941 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7942 intel_crtc
->plane
= !pipe
;
7945 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
7946 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
7947 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
7948 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
7950 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
7952 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
7955 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
7956 struct drm_file
*file
)
7958 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7959 struct drm_mode_object
*drmmode_obj
;
7960 struct intel_crtc
*crtc
;
7962 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
7965 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
7966 DRM_MODE_OBJECT_CRTC
);
7969 DRM_ERROR("no such CRTC id\n");
7973 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
7974 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7979 static int intel_encoder_clones(struct intel_encoder
*encoder
)
7981 struct drm_device
*dev
= encoder
->base
.dev
;
7982 struct intel_encoder
*source_encoder
;
7986 list_for_each_entry(source_encoder
,
7987 &dev
->mode_config
.encoder_list
, base
.head
) {
7989 if (encoder
== source_encoder
)
7990 index_mask
|= (1 << entry
);
7992 /* Intel hw has only one MUX where enocoders could be cloned. */
7993 if (encoder
->cloneable
&& source_encoder
->cloneable
)
7994 index_mask
|= (1 << entry
);
8002 static bool has_edp_a(struct drm_device
*dev
)
8004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8006 if (!IS_MOBILE(dev
))
8009 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8013 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8019 static void intel_setup_outputs(struct drm_device
*dev
)
8021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8022 struct intel_encoder
*encoder
;
8023 bool dpd_is_edp
= false;
8026 has_lvds
= intel_lvds_init(dev
);
8027 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8028 /* disable the panel fitter on everything but LVDS */
8029 I915_WRITE(PFIT_CONTROL
, 0);
8032 if (HAS_PCH_SPLIT(dev
)) {
8033 dpd_is_edp
= intel_dpd_is_edp(dev
);
8036 intel_dp_init(dev
, DP_A
, PORT_A
);
8038 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8039 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8042 intel_crt_init(dev
);
8044 if (IS_HASWELL(dev
)) {
8047 /* Haswell uses DDI functions to detect digital outputs */
8048 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8049 /* DDI A only supports eDP */
8051 intel_ddi_init(dev
, PORT_A
);
8053 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8055 found
= I915_READ(SFUSE_STRAP
);
8057 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8058 intel_ddi_init(dev
, PORT_B
);
8059 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8060 intel_ddi_init(dev
, PORT_C
);
8061 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8062 intel_ddi_init(dev
, PORT_D
);
8063 } else if (HAS_PCH_SPLIT(dev
)) {
8066 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
8067 /* PCH SDVOB multiplex with HDMIB */
8068 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8070 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
8071 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8072 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8075 if (I915_READ(HDMIC
) & PORT_DETECTED
)
8076 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
8078 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
8079 intel_hdmi_init(dev
, HDMID
, PORT_D
);
8081 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8082 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8084 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8085 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8086 } else if (IS_VALLEYVIEW(dev
)) {
8089 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8090 if (I915_READ(DP_C
) & DP_DETECTED
)
8091 intel_dp_init(dev
, DP_C
, PORT_C
);
8093 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
8094 /* SDVOB multiplex with HDMIB */
8095 found
= intel_sdvo_init(dev
, SDVOB
, true);
8097 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8098 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
8099 intel_dp_init(dev
, DP_B
, PORT_B
);
8102 if (I915_READ(SDVOC
) & PORT_DETECTED
)
8103 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8105 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8108 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8109 DRM_DEBUG_KMS("probing SDVOB\n");
8110 found
= intel_sdvo_init(dev
, SDVOB
, true);
8111 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8112 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8113 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8116 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8117 DRM_DEBUG_KMS("probing DP_B\n");
8118 intel_dp_init(dev
, DP_B
, PORT_B
);
8122 /* Before G4X SDVOC doesn't have its own detect register */
8124 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8125 DRM_DEBUG_KMS("probing SDVOC\n");
8126 found
= intel_sdvo_init(dev
, SDVOC
, false);
8129 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
8131 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8132 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8133 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8135 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8136 DRM_DEBUG_KMS("probing DP_C\n");
8137 intel_dp_init(dev
, DP_C
, PORT_C
);
8141 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8142 (I915_READ(DP_D
) & DP_DETECTED
)) {
8143 DRM_DEBUG_KMS("probing DP_D\n");
8144 intel_dp_init(dev
, DP_D
, PORT_D
);
8146 } else if (IS_GEN2(dev
))
8147 intel_dvo_init(dev
);
8149 if (SUPPORTS_TV(dev
))
8152 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8153 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8154 encoder
->base
.possible_clones
=
8155 intel_encoder_clones(encoder
);
8158 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8159 ironlake_init_pch_refclk(dev
);
8162 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8164 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8166 drm_framebuffer_cleanup(fb
);
8167 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8172 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8173 struct drm_file
*file
,
8174 unsigned int *handle
)
8176 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8177 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8179 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8182 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8183 .destroy
= intel_user_framebuffer_destroy
,
8184 .create_handle
= intel_user_framebuffer_create_handle
,
8187 int intel_framebuffer_init(struct drm_device
*dev
,
8188 struct intel_framebuffer
*intel_fb
,
8189 struct drm_mode_fb_cmd2
*mode_cmd
,
8190 struct drm_i915_gem_object
*obj
)
8194 if (obj
->tiling_mode
== I915_TILING_Y
)
8197 if (mode_cmd
->pitches
[0] & 63)
8200 switch (mode_cmd
->pixel_format
) {
8201 case DRM_FORMAT_RGB332
:
8202 case DRM_FORMAT_RGB565
:
8203 case DRM_FORMAT_XRGB8888
:
8204 case DRM_FORMAT_XBGR8888
:
8205 case DRM_FORMAT_ARGB8888
:
8206 case DRM_FORMAT_XRGB2101010
:
8207 case DRM_FORMAT_ARGB2101010
:
8208 /* RGB formats are common across chipsets */
8210 case DRM_FORMAT_YUYV
:
8211 case DRM_FORMAT_UYVY
:
8212 case DRM_FORMAT_YVYU
:
8213 case DRM_FORMAT_VYUY
:
8216 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8217 mode_cmd
->pixel_format
);
8221 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8223 DRM_ERROR("framebuffer init failed %d\n", ret
);
8227 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8228 intel_fb
->obj
= obj
;
8232 static struct drm_framebuffer
*
8233 intel_user_framebuffer_create(struct drm_device
*dev
,
8234 struct drm_file
*filp
,
8235 struct drm_mode_fb_cmd2
*mode_cmd
)
8237 struct drm_i915_gem_object
*obj
;
8239 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8240 mode_cmd
->handles
[0]));
8241 if (&obj
->base
== NULL
)
8242 return ERR_PTR(-ENOENT
);
8244 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8247 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8248 .fb_create
= intel_user_framebuffer_create
,
8249 .output_poll_changed
= intel_fb_output_poll_changed
,
8252 /* Set up chip specific display functions */
8253 static void intel_init_display(struct drm_device
*dev
)
8255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8257 /* We always want a DPMS function */
8258 if (IS_HASWELL(dev
)) {
8259 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8260 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8261 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8262 dev_priv
->display
.off
= haswell_crtc_off
;
8263 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8264 } else if (HAS_PCH_SPLIT(dev
)) {
8265 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8266 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8267 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8268 dev_priv
->display
.off
= ironlake_crtc_off
;
8269 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8271 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8272 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8273 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8274 dev_priv
->display
.off
= i9xx_crtc_off
;
8275 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8278 /* Returns the core display clock speed */
8279 if (IS_VALLEYVIEW(dev
))
8280 dev_priv
->display
.get_display_clock_speed
=
8281 valleyview_get_display_clock_speed
;
8282 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8283 dev_priv
->display
.get_display_clock_speed
=
8284 i945_get_display_clock_speed
;
8285 else if (IS_I915G(dev
))
8286 dev_priv
->display
.get_display_clock_speed
=
8287 i915_get_display_clock_speed
;
8288 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8289 dev_priv
->display
.get_display_clock_speed
=
8290 i9xx_misc_get_display_clock_speed
;
8291 else if (IS_I915GM(dev
))
8292 dev_priv
->display
.get_display_clock_speed
=
8293 i915gm_get_display_clock_speed
;
8294 else if (IS_I865G(dev
))
8295 dev_priv
->display
.get_display_clock_speed
=
8296 i865_get_display_clock_speed
;
8297 else if (IS_I85X(dev
))
8298 dev_priv
->display
.get_display_clock_speed
=
8299 i855_get_display_clock_speed
;
8301 dev_priv
->display
.get_display_clock_speed
=
8302 i830_get_display_clock_speed
;
8304 if (HAS_PCH_SPLIT(dev
)) {
8306 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8307 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8308 } else if (IS_GEN6(dev
)) {
8309 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8310 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8311 } else if (IS_IVYBRIDGE(dev
)) {
8312 /* FIXME: detect B0+ stepping and use auto training */
8313 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8314 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8315 } else if (IS_HASWELL(dev
)) {
8316 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8317 dev_priv
->display
.write_eld
= haswell_write_eld
;
8319 dev_priv
->display
.update_wm
= NULL
;
8320 } else if (IS_G4X(dev
)) {
8321 dev_priv
->display
.write_eld
= g4x_write_eld
;
8324 /* Default just returns -ENODEV to indicate unsupported */
8325 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8327 switch (INTEL_INFO(dev
)->gen
) {
8329 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8333 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8338 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8342 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8345 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8351 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8352 * resume, or other times. This quirk makes sure that's the case for
8355 static void quirk_pipea_force(struct drm_device
*dev
)
8357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8359 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8360 DRM_INFO("applying pipe a force quirk\n");
8364 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8366 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8369 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8370 DRM_INFO("applying lvds SSC disable quirk\n");
8374 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8377 static void quirk_invert_brightness(struct drm_device
*dev
)
8379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8380 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8381 DRM_INFO("applying inverted panel brightness quirk\n");
8384 struct intel_quirk
{
8386 int subsystem_vendor
;
8387 int subsystem_device
;
8388 void (*hook
)(struct drm_device
*dev
);
8391 static struct intel_quirk intel_quirks
[] = {
8392 /* HP Mini needs pipe A force quirk (LP: #322104) */
8393 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8395 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8396 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8398 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8399 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8401 /* 830/845 need to leave pipe A & dpll A up */
8402 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8403 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8405 /* Lenovo U160 cannot use SSC on LVDS */
8406 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8408 /* Sony Vaio Y cannot use SSC on LVDS */
8409 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8411 /* Acer Aspire 5734Z must invert backlight brightness */
8412 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8415 static void intel_init_quirks(struct drm_device
*dev
)
8417 struct pci_dev
*d
= dev
->pdev
;
8420 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8421 struct intel_quirk
*q
= &intel_quirks
[i
];
8423 if (d
->device
== q
->device
&&
8424 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8425 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8426 (d
->subsystem_device
== q
->subsystem_device
||
8427 q
->subsystem_device
== PCI_ANY_ID
))
8432 /* Disable the VGA plane that we never use */
8433 static void i915_disable_vga(struct drm_device
*dev
)
8435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8439 if (HAS_PCH_SPLIT(dev
))
8440 vga_reg
= CPU_VGACNTRL
;
8444 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8445 outb(SR01
, VGA_SR_INDEX
);
8446 sr1
= inb(VGA_SR_DATA
);
8447 outb(sr1
| 1<<5, VGA_SR_DATA
);
8448 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8451 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8452 POSTING_READ(vga_reg
);
8455 void intel_modeset_init_hw(struct drm_device
*dev
)
8457 /* We attempt to init the necessary power wells early in the initialization
8458 * time, so the subsystems that expect power to be enabled can work.
8460 intel_init_power_wells(dev
);
8462 intel_prepare_ddi(dev
);
8464 intel_init_clock_gating(dev
);
8466 mutex_lock(&dev
->struct_mutex
);
8467 intel_enable_gt_powersave(dev
);
8468 mutex_unlock(&dev
->struct_mutex
);
8471 void intel_modeset_init(struct drm_device
*dev
)
8473 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8476 drm_mode_config_init(dev
);
8478 dev
->mode_config
.min_width
= 0;
8479 dev
->mode_config
.min_height
= 0;
8481 dev
->mode_config
.preferred_depth
= 24;
8482 dev
->mode_config
.prefer_shadow
= 1;
8484 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8486 intel_init_quirks(dev
);
8490 intel_init_display(dev
);
8493 dev
->mode_config
.max_width
= 2048;
8494 dev
->mode_config
.max_height
= 2048;
8495 } else if (IS_GEN3(dev
)) {
8496 dev
->mode_config
.max_width
= 4096;
8497 dev
->mode_config
.max_height
= 4096;
8499 dev
->mode_config
.max_width
= 8192;
8500 dev
->mode_config
.max_height
= 8192;
8502 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8504 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8505 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8507 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8508 intel_crtc_init(dev
, i
);
8509 ret
= intel_plane_init(dev
, i
);
8511 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8514 intel_cpu_pll_init(dev
);
8515 intel_pch_pll_init(dev
);
8517 /* Just disable it once at startup */
8518 i915_disable_vga(dev
);
8519 intel_setup_outputs(dev
);
8523 intel_connector_break_all_links(struct intel_connector
*connector
)
8525 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8526 connector
->base
.encoder
= NULL
;
8527 connector
->encoder
->connectors_active
= false;
8528 connector
->encoder
->base
.crtc
= NULL
;
8531 static void intel_enable_pipe_a(struct drm_device
*dev
)
8533 struct intel_connector
*connector
;
8534 struct drm_connector
*crt
= NULL
;
8535 struct intel_load_detect_pipe load_detect_temp
;
8537 /* We can't just switch on the pipe A, we need to set things up with a
8538 * proper mode and output configuration. As a gross hack, enable pipe A
8539 * by enabling the load detect pipe once. */
8540 list_for_each_entry(connector
,
8541 &dev
->mode_config
.connector_list
,
8543 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8544 crt
= &connector
->base
;
8552 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8553 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8559 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8561 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
8564 if (dev_priv
->num_pipe
== 1)
8567 reg
= DSPCNTR(!crtc
->plane
);
8568 val
= I915_READ(reg
);
8570 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8571 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8577 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8579 struct drm_device
*dev
= crtc
->base
.dev
;
8580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8583 /* Clear any frame start delays used for debugging left by the BIOS */
8584 reg
= PIPECONF(crtc
->cpu_transcoder
);
8585 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8587 /* We need to sanitize the plane -> pipe mapping first because this will
8588 * disable the crtc (and hence change the state) if it is wrong. Note
8589 * that gen4+ has a fixed plane -> pipe mapping. */
8590 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8591 struct intel_connector
*connector
;
8594 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8595 crtc
->base
.base
.id
);
8597 /* Pipe has the wrong plane attached and the plane is active.
8598 * Temporarily change the plane mapping and disable everything
8600 plane
= crtc
->plane
;
8601 crtc
->plane
= !plane
;
8602 dev_priv
->display
.crtc_disable(&crtc
->base
);
8603 crtc
->plane
= plane
;
8605 /* ... and break all links. */
8606 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8608 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8611 intel_connector_break_all_links(connector
);
8614 WARN_ON(crtc
->active
);
8615 crtc
->base
.enabled
= false;
8618 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8619 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8620 /* BIOS forgot to enable pipe A, this mostly happens after
8621 * resume. Force-enable the pipe to fix this, the update_dpms
8622 * call below we restore the pipe to the right state, but leave
8623 * the required bits on. */
8624 intel_enable_pipe_a(dev
);
8627 /* Adjust the state of the output pipe according to whether we
8628 * have active connectors/encoders. */
8629 intel_crtc_update_dpms(&crtc
->base
);
8631 if (crtc
->active
!= crtc
->base
.enabled
) {
8632 struct intel_encoder
*encoder
;
8634 /* This can happen either due to bugs in the get_hw_state
8635 * functions or because the pipe is force-enabled due to the
8637 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8639 crtc
->base
.enabled
? "enabled" : "disabled",
8640 crtc
->active
? "enabled" : "disabled");
8642 crtc
->base
.enabled
= crtc
->active
;
8644 /* Because we only establish the connector -> encoder ->
8645 * crtc links if something is active, this means the
8646 * crtc is now deactivated. Break the links. connector
8647 * -> encoder links are only establish when things are
8648 * actually up, hence no need to break them. */
8649 WARN_ON(crtc
->active
);
8651 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8652 WARN_ON(encoder
->connectors_active
);
8653 encoder
->base
.crtc
= NULL
;
8658 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8660 struct intel_connector
*connector
;
8661 struct drm_device
*dev
= encoder
->base
.dev
;
8663 /* We need to check both for a crtc link (meaning that the
8664 * encoder is active and trying to read from a pipe) and the
8665 * pipe itself being active. */
8666 bool has_active_crtc
= encoder
->base
.crtc
&&
8667 to_intel_crtc(encoder
->base
.crtc
)->active
;
8669 if (encoder
->connectors_active
&& !has_active_crtc
) {
8670 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8671 encoder
->base
.base
.id
,
8672 drm_get_encoder_name(&encoder
->base
));
8674 /* Connector is active, but has no active pipe. This is
8675 * fallout from our resume register restoring. Disable
8676 * the encoder manually again. */
8677 if (encoder
->base
.crtc
) {
8678 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8679 encoder
->base
.base
.id
,
8680 drm_get_encoder_name(&encoder
->base
));
8681 encoder
->disable(encoder
);
8684 /* Inconsistent output/port/pipe state happens presumably due to
8685 * a bug in one of the get_hw_state functions. Or someplace else
8686 * in our code, like the register restore mess on resume. Clamp
8687 * things to off as a safer default. */
8688 list_for_each_entry(connector
,
8689 &dev
->mode_config
.connector_list
,
8691 if (connector
->encoder
!= encoder
)
8694 intel_connector_break_all_links(connector
);
8697 /* Enabled encoders without active connectors will be fixed in
8698 * the crtc fixup. */
8701 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8702 * and i915 state tracking structures. */
8703 void intel_modeset_setup_hw_state(struct drm_device
*dev
)
8705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8708 struct intel_crtc
*crtc
;
8709 struct intel_encoder
*encoder
;
8710 struct intel_connector
*connector
;
8712 if (IS_HASWELL(dev
)) {
8713 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8715 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8716 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8717 case TRANS_DDI_EDP_INPUT_A_ON
:
8718 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8721 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8724 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8729 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8730 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
8732 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8737 for_each_pipe(pipe
) {
8738 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8740 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
8741 if (tmp
& PIPECONF_ENABLE
)
8742 crtc
->active
= true;
8744 crtc
->active
= false;
8746 crtc
->base
.enabled
= crtc
->active
;
8748 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8750 crtc
->active
? "enabled" : "disabled");
8753 if (IS_HASWELL(dev
))
8754 intel_ddi_setup_hw_pll_state(dev
);
8756 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8760 if (encoder
->get_hw_state(encoder
, &pipe
)) {
8761 encoder
->base
.crtc
=
8762 dev_priv
->pipe_to_crtc_mapping
[pipe
];
8764 encoder
->base
.crtc
= NULL
;
8767 encoder
->connectors_active
= false;
8768 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8769 encoder
->base
.base
.id
,
8770 drm_get_encoder_name(&encoder
->base
),
8771 encoder
->base
.crtc
? "enabled" : "disabled",
8775 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8777 if (connector
->get_hw_state(connector
)) {
8778 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
8779 connector
->encoder
->connectors_active
= true;
8780 connector
->base
.encoder
= &connector
->encoder
->base
;
8782 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8783 connector
->base
.encoder
= NULL
;
8785 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8786 connector
->base
.base
.id
,
8787 drm_get_connector_name(&connector
->base
),
8788 connector
->base
.encoder
? "enabled" : "disabled");
8791 /* HW state is read out, now we need to sanitize this mess. */
8792 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8794 intel_sanitize_encoder(encoder
);
8797 for_each_pipe(pipe
) {
8798 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8799 intel_sanitize_crtc(crtc
);
8802 intel_modeset_update_staged_output_state(dev
);
8804 intel_modeset_check_state(dev
);
8806 drm_mode_config_reset(dev
);
8809 void intel_modeset_gem_init(struct drm_device
*dev
)
8811 intel_modeset_init_hw(dev
);
8813 intel_setup_overlay(dev
);
8815 intel_modeset_setup_hw_state(dev
);
8818 void intel_modeset_cleanup(struct drm_device
*dev
)
8820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8821 struct drm_crtc
*crtc
;
8822 struct intel_crtc
*intel_crtc
;
8824 drm_kms_helper_poll_fini(dev
);
8825 mutex_lock(&dev
->struct_mutex
);
8827 intel_unregister_dsm_handler();
8830 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8831 /* Skip inactive CRTCs */
8835 intel_crtc
= to_intel_crtc(crtc
);
8836 intel_increase_pllclock(crtc
);
8839 intel_disable_fbc(dev
);
8841 intel_disable_gt_powersave(dev
);
8843 ironlake_teardown_rc6(dev
);
8845 if (IS_VALLEYVIEW(dev
))
8848 mutex_unlock(&dev
->struct_mutex
);
8850 /* Disable the irq before mode object teardown, for the irq might
8851 * enqueue unpin/hotplug work. */
8852 drm_irq_uninstall(dev
);
8853 cancel_work_sync(&dev_priv
->hotplug_work
);
8854 cancel_work_sync(&dev_priv
->rps
.work
);
8856 /* flush any delayed tasks or pending work */
8857 flush_scheduled_work();
8859 drm_mode_config_cleanup(dev
);
8863 * Return which encoder is currently attached for connector.
8865 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
8867 return &intel_attached_encoder(connector
)->base
;
8870 void intel_connector_attach_encoder(struct intel_connector
*connector
,
8871 struct intel_encoder
*encoder
)
8873 connector
->encoder
= encoder
;
8874 drm_mode_connector_attach_encoder(&connector
->base
,
8879 * set vga decode state - true == enable VGA decode
8881 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
8883 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8886 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
8888 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
8890 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
8891 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
8895 #ifdef CONFIG_DEBUG_FS
8896 #include <linux/seq_file.h>
8898 struct intel_display_error_state
{
8899 struct intel_cursor_error_state
{
8904 } cursor
[I915_MAX_PIPES
];
8906 struct intel_pipe_error_state
{
8916 } pipe
[I915_MAX_PIPES
];
8918 struct intel_plane_error_state
{
8926 } plane
[I915_MAX_PIPES
];
8929 struct intel_display_error_state
*
8930 intel_display_capture_error_state(struct drm_device
*dev
)
8932 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8933 struct intel_display_error_state
*error
;
8934 enum transcoder cpu_transcoder
;
8937 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
8942 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
8944 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
8945 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
8946 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
8948 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
8949 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
8950 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
8951 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
8952 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
8953 if (INTEL_INFO(dev
)->gen
>= 4) {
8954 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
8955 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
8958 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
8959 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
8960 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
8961 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
8962 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
8963 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
8964 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
8965 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
8972 intel_display_print_error_state(struct seq_file
*m
,
8973 struct drm_device
*dev
,
8974 struct intel_display_error_state
*error
)
8976 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8979 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
8981 seq_printf(m
, "Pipe [%d]:\n", i
);
8982 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
8983 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
8984 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
8985 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
8986 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
8987 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
8988 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
8989 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
8991 seq_printf(m
, "Plane [%d]:\n", i
);
8992 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
8993 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
8994 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
8995 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
8996 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
8997 if (INTEL_INFO(dev
)->gen
>= 4) {
8998 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
8999 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9002 seq_printf(m
, "Cursor [%d]:\n", i
);
9003 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9004 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9005 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);