2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
74 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
75 int, int, intel_clock_t
*, intel_clock_t
*);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_pch_rawclk(struct drm_device
*dev
)
84 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 WARN_ON(!HAS_PCH_SPLIT(dev
));
88 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
92 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
93 int target
, int refclk
, intel_clock_t
*match_clock
,
94 intel_clock_t
*best_clock
);
96 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
97 int target
, int refclk
, intel_clock_t
*match_clock
,
98 intel_clock_t
*best_clock
);
101 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
102 int target
, int refclk
, intel_clock_t
*match_clock
,
103 intel_clock_t
*best_clock
);
105 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
106 int target
, int refclk
, intel_clock_t
*match_clock
,
107 intel_clock_t
*best_clock
);
110 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
111 int target
, int refclk
, intel_clock_t
*match_clock
,
112 intel_clock_t
*best_clock
);
114 static inline u32
/* units of 100MHz */
115 intel_fdi_link_freq(struct drm_device
*dev
)
118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
119 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
124 static const intel_limit_t intel_limits_i8xx_dvo
= {
125 .dot
= { .min
= 25000, .max
= 350000 },
126 .vco
= { .min
= 930000, .max
= 1400000 },
127 .n
= { .min
= 3, .max
= 16 },
128 .m
= { .min
= 96, .max
= 140 },
129 .m1
= { .min
= 18, .max
= 26 },
130 .m2
= { .min
= 6, .max
= 16 },
131 .p
= { .min
= 4, .max
= 128 },
132 .p1
= { .min
= 2, .max
= 33 },
133 .p2
= { .dot_limit
= 165000,
134 .p2_slow
= 4, .p2_fast
= 2 },
135 .find_pll
= intel_find_best_PLL
,
138 static const intel_limit_t intel_limits_i8xx_lvds
= {
139 .dot
= { .min
= 25000, .max
= 350000 },
140 .vco
= { .min
= 930000, .max
= 1400000 },
141 .n
= { .min
= 3, .max
= 16 },
142 .m
= { .min
= 96, .max
= 140 },
143 .m1
= { .min
= 18, .max
= 26 },
144 .m2
= { .min
= 6, .max
= 16 },
145 .p
= { .min
= 4, .max
= 128 },
146 .p1
= { .min
= 1, .max
= 6 },
147 .p2
= { .dot_limit
= 165000,
148 .p2_slow
= 14, .p2_fast
= 7 },
149 .find_pll
= intel_find_best_PLL
,
152 static const intel_limit_t intel_limits_i9xx_sdvo
= {
153 .dot
= { .min
= 20000, .max
= 400000 },
154 .vco
= { .min
= 1400000, .max
= 2800000 },
155 .n
= { .min
= 1, .max
= 6 },
156 .m
= { .min
= 70, .max
= 120 },
157 .m1
= { .min
= 10, .max
= 22 },
158 .m2
= { .min
= 5, .max
= 9 },
159 .p
= { .min
= 5, .max
= 80 },
160 .p1
= { .min
= 1, .max
= 8 },
161 .p2
= { .dot_limit
= 200000,
162 .p2_slow
= 10, .p2_fast
= 5 },
163 .find_pll
= intel_find_best_PLL
,
166 static const intel_limit_t intel_limits_i9xx_lvds
= {
167 .dot
= { .min
= 20000, .max
= 400000 },
168 .vco
= { .min
= 1400000, .max
= 2800000 },
169 .n
= { .min
= 1, .max
= 6 },
170 .m
= { .min
= 70, .max
= 120 },
171 .m1
= { .min
= 10, .max
= 22 },
172 .m2
= { .min
= 5, .max
= 9 },
173 .p
= { .min
= 7, .max
= 98 },
174 .p1
= { .min
= 1, .max
= 8 },
175 .p2
= { .dot_limit
= 112000,
176 .p2_slow
= 14, .p2_fast
= 7 },
177 .find_pll
= intel_find_best_PLL
,
181 static const intel_limit_t intel_limits_g4x_sdvo
= {
182 .dot
= { .min
= 25000, .max
= 270000 },
183 .vco
= { .min
= 1750000, .max
= 3500000},
184 .n
= { .min
= 1, .max
= 4 },
185 .m
= { .min
= 104, .max
= 138 },
186 .m1
= { .min
= 17, .max
= 23 },
187 .m2
= { .min
= 5, .max
= 11 },
188 .p
= { .min
= 10, .max
= 30 },
189 .p1
= { .min
= 1, .max
= 3},
190 .p2
= { .dot_limit
= 270000,
194 .find_pll
= intel_g4x_find_best_PLL
,
197 static const intel_limit_t intel_limits_g4x_hdmi
= {
198 .dot
= { .min
= 22000, .max
= 400000 },
199 .vco
= { .min
= 1750000, .max
= 3500000},
200 .n
= { .min
= 1, .max
= 4 },
201 .m
= { .min
= 104, .max
= 138 },
202 .m1
= { .min
= 16, .max
= 23 },
203 .m2
= { .min
= 5, .max
= 11 },
204 .p
= { .min
= 5, .max
= 80 },
205 .p1
= { .min
= 1, .max
= 8},
206 .p2
= { .dot_limit
= 165000,
207 .p2_slow
= 10, .p2_fast
= 5 },
208 .find_pll
= intel_g4x_find_best_PLL
,
211 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
212 .dot
= { .min
= 20000, .max
= 115000 },
213 .vco
= { .min
= 1750000, .max
= 3500000 },
214 .n
= { .min
= 1, .max
= 3 },
215 .m
= { .min
= 104, .max
= 138 },
216 .m1
= { .min
= 17, .max
= 23 },
217 .m2
= { .min
= 5, .max
= 11 },
218 .p
= { .min
= 28, .max
= 112 },
219 .p1
= { .min
= 2, .max
= 8 },
220 .p2
= { .dot_limit
= 0,
221 .p2_slow
= 14, .p2_fast
= 14
223 .find_pll
= intel_g4x_find_best_PLL
,
226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
227 .dot
= { .min
= 80000, .max
= 224000 },
228 .vco
= { .min
= 1750000, .max
= 3500000 },
229 .n
= { .min
= 1, .max
= 3 },
230 .m
= { .min
= 104, .max
= 138 },
231 .m1
= { .min
= 17, .max
= 23 },
232 .m2
= { .min
= 5, .max
= 11 },
233 .p
= { .min
= 14, .max
= 42 },
234 .p1
= { .min
= 2, .max
= 6 },
235 .p2
= { .dot_limit
= 0,
236 .p2_slow
= 7, .p2_fast
= 7
238 .find_pll
= intel_g4x_find_best_PLL
,
241 static const intel_limit_t intel_limits_g4x_display_port
= {
242 .dot
= { .min
= 161670, .max
= 227000 },
243 .vco
= { .min
= 1750000, .max
= 3500000},
244 .n
= { .min
= 1, .max
= 2 },
245 .m
= { .min
= 97, .max
= 108 },
246 .m1
= { .min
= 0x10, .max
= 0x12 },
247 .m2
= { .min
= 0x05, .max
= 0x06 },
248 .p
= { .min
= 10, .max
= 20 },
249 .p1
= { .min
= 1, .max
= 2},
250 .p2
= { .dot_limit
= 0,
251 .p2_slow
= 10, .p2_fast
= 10 },
252 .find_pll
= intel_find_pll_g4x_dp
,
255 static const intel_limit_t intel_limits_pineview_sdvo
= {
256 .dot
= { .min
= 20000, .max
= 400000},
257 .vco
= { .min
= 1700000, .max
= 3500000 },
258 /* Pineview's Ncounter is a ring counter */
259 .n
= { .min
= 3, .max
= 6 },
260 .m
= { .min
= 2, .max
= 256 },
261 /* Pineview only has one combined m divider, which we treat as m2. */
262 .m1
= { .min
= 0, .max
= 0 },
263 .m2
= { .min
= 0, .max
= 254 },
264 .p
= { .min
= 5, .max
= 80 },
265 .p1
= { .min
= 1, .max
= 8 },
266 .p2
= { .dot_limit
= 200000,
267 .p2_slow
= 10, .p2_fast
= 5 },
268 .find_pll
= intel_find_best_PLL
,
271 static const intel_limit_t intel_limits_pineview_lvds
= {
272 .dot
= { .min
= 20000, .max
= 400000 },
273 .vco
= { .min
= 1700000, .max
= 3500000 },
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 .m1
= { .min
= 0, .max
= 0 },
277 .m2
= { .min
= 0, .max
= 254 },
278 .p
= { .min
= 7, .max
= 112 },
279 .p1
= { .min
= 1, .max
= 8 },
280 .p2
= { .dot_limit
= 112000,
281 .p2_slow
= 14, .p2_fast
= 14 },
282 .find_pll
= intel_find_best_PLL
,
285 /* Ironlake / Sandybridge
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
290 static const intel_limit_t intel_limits_ironlake_dac
= {
291 .dot
= { .min
= 25000, .max
= 350000 },
292 .vco
= { .min
= 1760000, .max
= 3510000 },
293 .n
= { .min
= 1, .max
= 5 },
294 .m
= { .min
= 79, .max
= 127 },
295 .m1
= { .min
= 12, .max
= 22 },
296 .m2
= { .min
= 5, .max
= 9 },
297 .p
= { .min
= 5, .max
= 80 },
298 .p1
= { .min
= 1, .max
= 8 },
299 .p2
= { .dot_limit
= 225000,
300 .p2_slow
= 10, .p2_fast
= 5 },
301 .find_pll
= intel_g4x_find_best_PLL
,
304 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
305 .dot
= { .min
= 25000, .max
= 350000 },
306 .vco
= { .min
= 1760000, .max
= 3510000 },
307 .n
= { .min
= 1, .max
= 3 },
308 .m
= { .min
= 79, .max
= 118 },
309 .m1
= { .min
= 12, .max
= 22 },
310 .m2
= { .min
= 5, .max
= 9 },
311 .p
= { .min
= 28, .max
= 112 },
312 .p1
= { .min
= 2, .max
= 8 },
313 .p2
= { .dot_limit
= 225000,
314 .p2_slow
= 14, .p2_fast
= 14 },
315 .find_pll
= intel_g4x_find_best_PLL
,
318 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
319 .dot
= { .min
= 25000, .max
= 350000 },
320 .vco
= { .min
= 1760000, .max
= 3510000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 79, .max
= 127 },
323 .m1
= { .min
= 12, .max
= 22 },
324 .m2
= { .min
= 5, .max
= 9 },
325 .p
= { .min
= 14, .max
= 56 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 225000,
328 .p2_slow
= 7, .p2_fast
= 7 },
329 .find_pll
= intel_g4x_find_best_PLL
,
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
334 .dot
= { .min
= 25000, .max
= 350000 },
335 .vco
= { .min
= 1760000, .max
= 3510000 },
336 .n
= { .min
= 1, .max
= 2 },
337 .m
= { .min
= 79, .max
= 126 },
338 .m1
= { .min
= 12, .max
= 22 },
339 .m2
= { .min
= 5, .max
= 9 },
340 .p
= { .min
= 28, .max
= 112 },
341 .p1
= { .min
= 2, .max
= 8 },
342 .p2
= { .dot_limit
= 225000,
343 .p2_slow
= 14, .p2_fast
= 14 },
344 .find_pll
= intel_g4x_find_best_PLL
,
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
348 .dot
= { .min
= 25000, .max
= 350000 },
349 .vco
= { .min
= 1760000, .max
= 3510000 },
350 .n
= { .min
= 1, .max
= 3 },
351 .m
= { .min
= 79, .max
= 126 },
352 .m1
= { .min
= 12, .max
= 22 },
353 .m2
= { .min
= 5, .max
= 9 },
354 .p
= { .min
= 14, .max
= 42 },
355 .p1
= { .min
= 2, .max
= 6 },
356 .p2
= { .dot_limit
= 225000,
357 .p2_slow
= 7, .p2_fast
= 7 },
358 .find_pll
= intel_g4x_find_best_PLL
,
361 static const intel_limit_t intel_limits_ironlake_display_port
= {
362 .dot
= { .min
= 25000, .max
= 350000 },
363 .vco
= { .min
= 1760000, .max
= 3510000},
364 .n
= { .min
= 1, .max
= 2 },
365 .m
= { .min
= 81, .max
= 90 },
366 .m1
= { .min
= 12, .max
= 22 },
367 .m2
= { .min
= 5, .max
= 9 },
368 .p
= { .min
= 10, .max
= 20 },
369 .p1
= { .min
= 1, .max
= 2},
370 .p2
= { .dot_limit
= 0,
371 .p2_slow
= 10, .p2_fast
= 10 },
372 .find_pll
= intel_find_pll_ironlake_dp
,
375 static const intel_limit_t intel_limits_vlv_dac
= {
376 .dot
= { .min
= 25000, .max
= 270000 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m
= { .min
= 22, .max
= 450 }, /* guess */
380 .m1
= { .min
= 2, .max
= 3 },
381 .m2
= { .min
= 11, .max
= 156 },
382 .p
= { .min
= 10, .max
= 30 },
383 .p1
= { .min
= 2, .max
= 3 },
384 .p2
= { .dot_limit
= 270000,
385 .p2_slow
= 2, .p2_fast
= 20 },
386 .find_pll
= intel_vlv_find_best_pll
,
389 static const intel_limit_t intel_limits_vlv_hdmi
= {
390 .dot
= { .min
= 20000, .max
= 165000 },
391 .vco
= { .min
= 4000000, .max
= 5994000},
392 .n
= { .min
= 1, .max
= 7 },
393 .m
= { .min
= 60, .max
= 300 }, /* guess */
394 .m1
= { .min
= 2, .max
= 3 },
395 .m2
= { .min
= 11, .max
= 156 },
396 .p
= { .min
= 10, .max
= 30 },
397 .p1
= { .min
= 2, .max
= 3 },
398 .p2
= { .dot_limit
= 270000,
399 .p2_slow
= 2, .p2_fast
= 20 },
400 .find_pll
= intel_vlv_find_best_pll
,
403 static const intel_limit_t intel_limits_vlv_dp
= {
404 .dot
= { .min
= 25000, .max
= 270000 },
405 .vco
= { .min
= 4000000, .max
= 6000000 },
406 .n
= { .min
= 1, .max
= 7 },
407 .m
= { .min
= 22, .max
= 450 },
408 .m1
= { .min
= 2, .max
= 3 },
409 .m2
= { .min
= 11, .max
= 156 },
410 .p
= { .min
= 10, .max
= 30 },
411 .p1
= { .min
= 2, .max
= 3 },
412 .p2
= { .dot_limit
= 270000,
413 .p2_slow
= 2, .p2_fast
= 20 },
414 .find_pll
= intel_vlv_find_best_pll
,
417 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
422 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
428 I915_WRITE(DPIO_REG
, reg
);
429 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
435 val
= I915_READ(DPIO_DATA
);
438 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
442 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
447 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
453 I915_WRITE(DPIO_DATA
, val
);
454 I915_WRITE(DPIO_REG
, reg
);
455 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
461 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
464 static void vlv_init_dpio(struct drm_device
*dev
)
466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL
, 0);
470 POSTING_READ(DPIO_CTL
);
471 I915_WRITE(DPIO_CTL
, 1);
472 POSTING_READ(DPIO_CTL
);
475 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
481 static const struct dmi_system_id intel_dual_link_lvds
[] = {
483 .callback
= intel_dual_link_lvds_callback
,
484 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
486 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
490 { } /* terminating entry */
493 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode
> 0)
500 return i915_lvds_channel_mode
== 2;
502 if (dmi_check_system(intel_dual_link_lvds
))
505 if (dev_priv
->lvds_val
)
506 val
= dev_priv
->lvds_val
;
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
513 val
= I915_READ(reg
);
514 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
515 val
= dev_priv
->bios_lvds_val
;
516 dev_priv
->lvds_val
= val
;
518 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
521 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
524 struct drm_device
*dev
= crtc
->dev
;
525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
526 const intel_limit_t
*limit
;
528 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
529 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
530 /* LVDS dual channel */
531 if (refclk
== 100000)
532 limit
= &intel_limits_ironlake_dual_lvds_100m
;
534 limit
= &intel_limits_ironlake_dual_lvds
;
536 if (refclk
== 100000)
537 limit
= &intel_limits_ironlake_single_lvds_100m
;
539 limit
= &intel_limits_ironlake_single_lvds
;
541 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
542 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
543 limit
= &intel_limits_ironlake_display_port
;
545 limit
= &intel_limits_ironlake_dac
;
550 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
552 struct drm_device
*dev
= crtc
->dev
;
553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
554 const intel_limit_t
*limit
;
556 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
557 if (is_dual_link_lvds(dev_priv
, LVDS
))
558 /* LVDS with dual channel */
559 limit
= &intel_limits_g4x_dual_channel_lvds
;
561 /* LVDS with dual channel */
562 limit
= &intel_limits_g4x_single_channel_lvds
;
563 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
564 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
565 limit
= &intel_limits_g4x_hdmi
;
566 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
567 limit
= &intel_limits_g4x_sdvo
;
568 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
569 limit
= &intel_limits_g4x_display_port
;
570 } else /* The option is for other outputs */
571 limit
= &intel_limits_i9xx_sdvo
;
576 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
578 struct drm_device
*dev
= crtc
->dev
;
579 const intel_limit_t
*limit
;
581 if (HAS_PCH_SPLIT(dev
))
582 limit
= intel_ironlake_limit(crtc
, refclk
);
583 else if (IS_G4X(dev
)) {
584 limit
= intel_g4x_limit(crtc
);
585 } else if (IS_PINEVIEW(dev
)) {
586 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
587 limit
= &intel_limits_pineview_lvds
;
589 limit
= &intel_limits_pineview_sdvo
;
590 } else if (IS_VALLEYVIEW(dev
)) {
591 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
592 limit
= &intel_limits_vlv_dac
;
593 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
594 limit
= &intel_limits_vlv_hdmi
;
596 limit
= &intel_limits_vlv_dp
;
597 } else if (!IS_GEN2(dev
)) {
598 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
599 limit
= &intel_limits_i9xx_lvds
;
601 limit
= &intel_limits_i9xx_sdvo
;
603 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
604 limit
= &intel_limits_i8xx_lvds
;
606 limit
= &intel_limits_i8xx_dvo
;
611 /* m1 is reserved as 0 in Pineview, n is a ring counter */
612 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
614 clock
->m
= clock
->m2
+ 2;
615 clock
->p
= clock
->p1
* clock
->p2
;
616 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
617 clock
->dot
= clock
->vco
/ clock
->p
;
620 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
622 if (IS_PINEVIEW(dev
)) {
623 pineview_clock(refclk
, clock
);
626 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
627 clock
->p
= clock
->p1
* clock
->p2
;
628 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
629 clock
->dot
= clock
->vco
/ clock
->p
;
633 * Returns whether any output on the specified pipe is of the specified type
635 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
637 struct drm_device
*dev
= crtc
->dev
;
638 struct intel_encoder
*encoder
;
640 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
641 if (encoder
->type
== type
)
647 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
653 static bool intel_PLL_is_valid(struct drm_device
*dev
,
654 const intel_limit_t
*limit
,
655 const intel_clock_t
*clock
)
657 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
658 INTELPllInvalid("p1 out of range\n");
659 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
660 INTELPllInvalid("p out of range\n");
661 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
662 INTELPllInvalid("m2 out of range\n");
663 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
664 INTELPllInvalid("m1 out of range\n");
665 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
666 INTELPllInvalid("m1 <= m2\n");
667 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
668 INTELPllInvalid("m out of range\n");
669 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
670 INTELPllInvalid("n out of range\n");
671 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
672 INTELPllInvalid("vco out of range\n");
673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
676 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
677 INTELPllInvalid("dot out of range\n");
683 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
684 int target
, int refclk
, intel_clock_t
*match_clock
,
685 intel_clock_t
*best_clock
)
688 struct drm_device
*dev
= crtc
->dev
;
689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
693 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
694 (I915_READ(LVDS
)) != 0) {
696 * For LVDS, if the panel is on, just rely on its current
697 * settings for dual-channel. We haven't figured out how to
698 * reliably set up different single/dual channel state, if we
701 if (is_dual_link_lvds(dev_priv
, LVDS
))
702 clock
.p2
= limit
->p2
.p2_fast
;
704 clock
.p2
= limit
->p2
.p2_slow
;
706 if (target
< limit
->p2
.dot_limit
)
707 clock
.p2
= limit
->p2
.p2_slow
;
709 clock
.p2
= limit
->p2
.p2_fast
;
712 memset(best_clock
, 0, sizeof(*best_clock
));
714 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
716 for (clock
.m2
= limit
->m2
.min
;
717 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
718 /* m1 is always 0 in Pineview */
719 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
721 for (clock
.n
= limit
->n
.min
;
722 clock
.n
<= limit
->n
.max
; clock
.n
++) {
723 for (clock
.p1
= limit
->p1
.min
;
724 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
727 intel_clock(dev
, refclk
, &clock
);
728 if (!intel_PLL_is_valid(dev
, limit
,
732 clock
.p
!= match_clock
->p
)
735 this_err
= abs(clock
.dot
- target
);
736 if (this_err
< err
) {
745 return (err
!= target
);
749 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
750 int target
, int refclk
, intel_clock_t
*match_clock
,
751 intel_clock_t
*best_clock
)
753 struct drm_device
*dev
= crtc
->dev
;
754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
758 /* approximately equals target * 0.00585 */
759 int err_most
= (target
>> 8) + (target
>> 9);
762 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
765 if (HAS_PCH_SPLIT(dev
))
769 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
771 clock
.p2
= limit
->p2
.p2_fast
;
773 clock
.p2
= limit
->p2
.p2_slow
;
775 if (target
< limit
->p2
.dot_limit
)
776 clock
.p2
= limit
->p2
.p2_slow
;
778 clock
.p2
= limit
->p2
.p2_fast
;
781 memset(best_clock
, 0, sizeof(*best_clock
));
782 max_n
= limit
->n
.max
;
783 /* based on hardware requirement, prefer smaller n to precision */
784 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
785 /* based on hardware requirement, prefere larger m1,m2 */
786 for (clock
.m1
= limit
->m1
.max
;
787 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
788 for (clock
.m2
= limit
->m2
.max
;
789 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
790 for (clock
.p1
= limit
->p1
.max
;
791 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
794 intel_clock(dev
, refclk
, &clock
);
795 if (!intel_PLL_is_valid(dev
, limit
,
799 clock
.p
!= match_clock
->p
)
802 this_err
= abs(clock
.dot
- target
);
803 if (this_err
< err_most
) {
817 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
818 int target
, int refclk
, intel_clock_t
*match_clock
,
819 intel_clock_t
*best_clock
)
821 struct drm_device
*dev
= crtc
->dev
;
824 if (target
< 200000) {
837 intel_clock(dev
, refclk
, &clock
);
838 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
842 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
844 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
845 int target
, int refclk
, intel_clock_t
*match_clock
,
846 intel_clock_t
*best_clock
)
849 if (target
< 200000) {
862 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
863 clock
.p
= (clock
.p1
* clock
.p2
);
864 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
866 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
870 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
871 int target
, int refclk
, intel_clock_t
*match_clock
,
872 intel_clock_t
*best_clock
)
874 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
876 u32 updrate
, minupdate
, fracbits
, p
;
877 unsigned long bestppm
, ppm
, absppm
;
881 dotclk
= target
* 1000;
884 fastclk
= dotclk
/ (2*100);
888 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
889 bestm1
= bestm2
= bestp1
= bestp2
= 0;
891 /* based on hardware requirement, prefer smaller n to precision */
892 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
893 updrate
= refclk
/ n
;
894 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
895 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
899 /* based on hardware requirement, prefer bigger m1,m2 values */
900 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
901 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
902 refclk
) / (2*refclk
));
905 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
906 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
907 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
908 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
912 if (absppm
< bestppm
- 10) {
929 best_clock
->n
= bestn
;
930 best_clock
->m1
= bestm1
;
931 best_clock
->m2
= bestm2
;
932 best_clock
->p1
= bestp1
;
933 best_clock
->p2
= bestp2
;
938 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
941 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
942 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
944 return intel_crtc
->cpu_transcoder
;
947 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
950 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
952 frame
= I915_READ(frame_reg
);
954 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
955 DRM_DEBUG_KMS("vblank wait timed out\n");
959 * intel_wait_for_vblank - wait for vblank on a given pipe
961 * @pipe: pipe to wait for
963 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
968 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
969 int pipestat_reg
= PIPESTAT(pipe
);
971 if (INTEL_INFO(dev
)->gen
>= 5) {
972 ironlake_wait_for_vblank(dev
, pipe
);
976 /* Clear existing vblank status. Note this will clear any other
977 * sticky status fields as well.
979 * This races with i915_driver_irq_handler() with the result
980 * that either function could miss a vblank event. Here it is not
981 * fatal, as we will either wait upon the next vblank interrupt or
982 * timeout. Generally speaking intel_wait_for_vblank() is only
983 * called during modeset at which time the GPU should be idle and
984 * should *not* be performing page flips and thus not waiting on
986 * Currently, the result of us stealing a vblank from the irq
987 * handler is that a single frame will be skipped during swapbuffers.
989 I915_WRITE(pipestat_reg
,
990 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
992 /* Wait for vblank interrupt bit to set */
993 if (wait_for(I915_READ(pipestat_reg
) &
994 PIPE_VBLANK_INTERRUPT_STATUS
,
996 DRM_DEBUG_KMS("vblank wait timed out\n");
1000 * intel_wait_for_pipe_off - wait for pipe to turn off
1002 * @pipe: pipe to wait for
1004 * After disabling a pipe, we can't wait for vblank in the usual way,
1005 * spinning on the vblank interrupt status bit, since we won't actually
1006 * see an interrupt when the pipe is disabled.
1008 * On Gen4 and above:
1009 * wait for the pipe register state bit to turn off
1012 * wait for the display line value to settle (it usually
1013 * ends up stopping at the start of the next frame).
1016 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1019 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1022 if (INTEL_INFO(dev
)->gen
>= 4) {
1023 int reg
= PIPECONF(cpu_transcoder
);
1025 /* Wait for the Pipe State to go off */
1026 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1028 WARN(1, "pipe_off wait timed out\n");
1030 u32 last_line
, line_mask
;
1031 int reg
= PIPEDSL(pipe
);
1032 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1035 line_mask
= DSL_LINEMASK_GEN2
;
1037 line_mask
= DSL_LINEMASK_GEN3
;
1039 /* Wait for the display line to settle */
1041 last_line
= I915_READ(reg
) & line_mask
;
1043 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1044 time_after(timeout
, jiffies
));
1045 if (time_after(jiffies
, timeout
))
1046 WARN(1, "pipe_off wait timed out\n");
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 static void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1070 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1071 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1075 struct intel_pch_pll
*pll
,
1076 struct intel_crtc
*crtc
,
1082 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1083 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1088 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1091 val
= I915_READ(pll
->pll_reg
);
1092 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1093 WARN(cur_state
!= state
,
1094 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1095 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1097 /* Make sure the selected PLL is correctly attached to the transcoder */
1098 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1101 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1102 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1103 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1104 "PLL[%d] not attached to this transcoder %d: %08x\n",
1105 cur_state
, crtc
->pipe
, pch_dpll
)) {
1106 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1107 WARN(cur_state
!= state
,
1108 "PLL[%d] not %s on this transcoder %d: %08x\n",
1109 pll
->pll_reg
== _PCH_DPLL_B
,
1110 state_string(state
),
1116 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1117 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1119 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1120 enum pipe pipe
, bool state
)
1125 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1128 if (IS_HASWELL(dev_priv
->dev
)) {
1129 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1130 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1131 val
= I915_READ(reg
);
1132 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1134 reg
= FDI_TX_CTL(pipe
);
1135 val
= I915_READ(reg
);
1136 cur_state
= !!(val
& FDI_TX_ENABLE
);
1138 WARN(cur_state
!= state
,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 state_string(state
), state_string(cur_state
));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1146 enum pipe pipe
, bool state
)
1152 reg
= FDI_RX_CTL(pipe
);
1153 val
= I915_READ(reg
);
1154 cur_state
= !!(val
& FDI_RX_ENABLE
);
1155 WARN(cur_state
!= state
,
1156 "FDI RX state assertion failure (expected %s, current %s)\n",
1157 state_string(state
), state_string(cur_state
));
1159 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1160 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1162 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1168 /* ILK FDI PLL is always enabled */
1169 if (dev_priv
->info
->gen
== 5)
1172 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1173 if (IS_HASWELL(dev_priv
->dev
))
1176 reg
= FDI_TX_CTL(pipe
);
1177 val
= I915_READ(reg
);
1178 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1181 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1192 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1195 int pp_reg
, lvds_reg
;
1197 enum pipe panel_pipe
= PIPE_A
;
1200 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1201 pp_reg
= PCH_PP_CONTROL
;
1202 lvds_reg
= PCH_LVDS
;
1204 pp_reg
= PP_CONTROL
;
1208 val
= I915_READ(pp_reg
);
1209 if (!(val
& PANEL_POWER_ON
) ||
1210 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1213 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1214 panel_pipe
= PIPE_B
;
1216 WARN(panel_pipe
== pipe
&& locked
,
1217 "panel assertion failure, pipe %c regs locked\n",
1221 void assert_pipe(struct drm_i915_private
*dev_priv
,
1222 enum pipe pipe
, bool state
)
1227 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1230 /* if we need the pipe A quirk it must be always on */
1231 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1234 reg
= PIPECONF(cpu_transcoder
);
1235 val
= I915_READ(reg
);
1236 cur_state
= !!(val
& PIPECONF_ENABLE
);
1237 WARN(cur_state
!= state
,
1238 "pipe %c assertion failure (expected %s, current %s)\n",
1239 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1242 static void assert_plane(struct drm_i915_private
*dev_priv
,
1243 enum plane plane
, bool state
)
1249 reg
= DSPCNTR(plane
);
1250 val
= I915_READ(reg
);
1251 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1252 WARN(cur_state
!= state
,
1253 "plane %c assertion failure (expected %s, current %s)\n",
1254 plane_name(plane
), state_string(state
), state_string(cur_state
));
1257 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1258 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1260 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1267 /* Planes are fixed to pipes on ILK+ */
1268 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1269 reg
= DSPCNTR(pipe
);
1270 val
= I915_READ(reg
);
1271 WARN((val
& DISPLAY_PLANE_ENABLE
),
1272 "plane %c assertion failure, should be disabled but not\n",
1277 /* Need to check both planes against the pipe */
1278 for (i
= 0; i
< 2; i
++) {
1280 val
= I915_READ(reg
);
1281 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1282 DISPPLANE_SEL_PIPE_SHIFT
;
1283 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1284 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1285 plane_name(i
), pipe_name(pipe
));
1289 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1294 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1295 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1299 val
= I915_READ(PCH_DREF_CONTROL
);
1300 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1301 DREF_SUPERSPREAD_SOURCE_MASK
));
1302 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1305 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1312 reg
= TRANSCONF(pipe
);
1313 val
= I915_READ(reg
);
1314 enabled
= !!(val
& TRANS_ENABLE
);
1316 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1320 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1321 enum pipe pipe
, u32 port_sel
, u32 val
)
1323 if ((val
& DP_PORT_EN
) == 0)
1326 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1327 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1328 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1329 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1332 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1338 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1339 enum pipe pipe
, u32 val
)
1341 if ((val
& PORT_ENABLE
) == 0)
1344 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1345 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1348 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1354 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1355 enum pipe pipe
, u32 val
)
1357 if ((val
& LVDS_PORT_EN
) == 0)
1360 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1361 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1364 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1370 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1371 enum pipe pipe
, u32 val
)
1373 if ((val
& ADPA_DAC_ENABLE
) == 0)
1375 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1376 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1379 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1385 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1386 enum pipe pipe
, int reg
, u32 port_sel
)
1388 u32 val
= I915_READ(reg
);
1389 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1390 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1391 reg
, pipe_name(pipe
));
1393 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1394 && (val
& DP_PIPEB_SELECT
),
1395 "IBX PCH dp port still using transcoder B\n");
1398 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1399 enum pipe pipe
, int reg
)
1401 u32 val
= I915_READ(reg
);
1402 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1403 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1404 reg
, pipe_name(pipe
));
1406 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1407 && (val
& SDVO_PIPE_B_SELECT
),
1408 "IBX PCH hdmi port still using transcoder B\n");
1411 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1417 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1418 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1419 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1422 val
= I915_READ(reg
);
1423 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1424 "PCH VGA enabled on transcoder %c, should be disabled\n",
1428 val
= I915_READ(reg
);
1429 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1430 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1433 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1434 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1435 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1439 * intel_enable_pll - enable a PLL
1440 * @dev_priv: i915 private structure
1441 * @pipe: pipe PLL to enable
1443 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1444 * make sure the PLL reg is writable first though, since the panel write
1445 * protect mechanism may be enabled.
1447 * Note! This is for pre-ILK only.
1449 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1451 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1456 /* No really, not for ILK+ */
1457 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1459 /* PLL is protected by panel, make sure we can write it */
1460 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1461 assert_panel_unlocked(dev_priv
, pipe
);
1464 val
= I915_READ(reg
);
1465 val
|= DPLL_VCO_ENABLE
;
1467 /* We do this three times for luck */
1468 I915_WRITE(reg
, val
);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg
, val
);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg
, val
);
1476 udelay(150); /* wait for warmup */
1480 * intel_disable_pll - disable a PLL
1481 * @dev_priv: i915 private structure
1482 * @pipe: pipe PLL to disable
1484 * Disable the PLL for @pipe, making sure the pipe is off first.
1486 * Note! This is for pre-ILK only.
1488 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv
, pipe
);
1501 val
= I915_READ(reg
);
1502 val
&= ~DPLL_VCO_ENABLE
;
1503 I915_WRITE(reg
, val
);
1509 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1511 unsigned long flags
;
1513 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1514 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1516 DRM_ERROR("timeout waiting for SBI to become ready\n");
1520 I915_WRITE(SBI_ADDR
,
1522 I915_WRITE(SBI_DATA
,
1524 I915_WRITE(SBI_CTL_STAT
,
1528 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1530 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1535 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1539 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1541 unsigned long flags
;
1544 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1545 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1547 DRM_ERROR("timeout waiting for SBI to become ready\n");
1551 I915_WRITE(SBI_ADDR
,
1553 I915_WRITE(SBI_CTL_STAT
,
1557 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1559 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1563 value
= I915_READ(SBI_DATA
);
1566 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1571 * ironlake_enable_pch_pll - enable PCH PLL
1572 * @dev_priv: i915 private structure
1573 * @pipe: pipe PLL to enable
1575 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1576 * drives the transcoder clock.
1578 static void ironlake_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1580 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1581 struct intel_pch_pll
*pll
;
1585 /* PCH PLLs only available on ILK, SNB and IVB */
1586 BUG_ON(dev_priv
->info
->gen
< 5);
1587 pll
= intel_crtc
->pch_pll
;
1591 if (WARN_ON(pll
->refcount
== 0))
1594 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1595 pll
->pll_reg
, pll
->active
, pll
->on
,
1596 intel_crtc
->base
.base
.id
);
1598 /* PCH refclock must be enabled first */
1599 assert_pch_refclk_enabled(dev_priv
);
1601 if (pll
->active
++ && pll
->on
) {
1602 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1606 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1609 val
= I915_READ(reg
);
1610 val
|= DPLL_VCO_ENABLE
;
1611 I915_WRITE(reg
, val
);
1618 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1620 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1621 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1625 /* PCH only available on ILK+ */
1626 BUG_ON(dev_priv
->info
->gen
< 5);
1630 if (WARN_ON(pll
->refcount
== 0))
1633 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1634 pll
->pll_reg
, pll
->active
, pll
->on
,
1635 intel_crtc
->base
.base
.id
);
1637 if (WARN_ON(pll
->active
== 0)) {
1638 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1642 if (--pll
->active
) {
1643 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1647 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1649 /* Make sure transcoder isn't still depending on us */
1650 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1653 val
= I915_READ(reg
);
1654 val
&= ~DPLL_VCO_ENABLE
;
1655 I915_WRITE(reg
, val
);
1662 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1665 struct drm_device
*dev
= dev_priv
->dev
;
1666 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1667 uint32_t reg
, val
, pipeconf_val
;
1669 /* PCH only available on ILK+ */
1670 BUG_ON(dev_priv
->info
->gen
< 5);
1672 /* Make sure PCH DPLL is enabled */
1673 assert_pch_pll_enabled(dev_priv
,
1674 to_intel_crtc(crtc
)->pch_pll
,
1675 to_intel_crtc(crtc
));
1677 /* FDI must be feeding us bits for PCH ports */
1678 assert_fdi_tx_enabled(dev_priv
, pipe
);
1679 assert_fdi_rx_enabled(dev_priv
, pipe
);
1681 if (HAS_PCH_CPT(dev
)) {
1682 /* Workaround: Set the timing override bit before enabling the
1683 * pch transcoder. */
1684 reg
= TRANS_CHICKEN2(pipe
);
1685 val
= I915_READ(reg
);
1686 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1687 I915_WRITE(reg
, val
);
1690 reg
= TRANSCONF(pipe
);
1691 val
= I915_READ(reg
);
1692 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1694 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1696 * make the BPC in transcoder be consistent with
1697 * that in pipeconf reg.
1699 val
&= ~PIPE_BPC_MASK
;
1700 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1703 val
&= ~TRANS_INTERLACE_MASK
;
1704 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1705 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1706 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1707 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1709 val
|= TRANS_INTERLACED
;
1711 val
|= TRANS_PROGRESSIVE
;
1713 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1714 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1715 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1718 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1719 enum transcoder cpu_transcoder
)
1721 u32 val
, pipeconf_val
;
1723 /* PCH only available on ILK+ */
1724 BUG_ON(dev_priv
->info
->gen
< 5);
1726 /* FDI must be feeding us bits for PCH ports */
1727 assert_fdi_tx_enabled(dev_priv
, cpu_transcoder
);
1728 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1730 /* Workaround: set timing override bit. */
1731 val
= I915_READ(_TRANSA_CHICKEN2
);
1732 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1733 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1736 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1738 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1739 PIPECONF_INTERLACED_ILK
)
1740 val
|= TRANS_INTERLACED
;
1742 val
|= TRANS_PROGRESSIVE
;
1744 I915_WRITE(TRANSCONF(TRANSCODER_A
), val
);
1745 if (wait_for(I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
, 100))
1746 DRM_ERROR("Failed to enable PCH transcoder\n");
1749 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1752 struct drm_device
*dev
= dev_priv
->dev
;
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv
, pipe
);
1757 assert_fdi_rx_disabled(dev_priv
, pipe
);
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv
, pipe
);
1762 reg
= TRANSCONF(pipe
);
1763 val
= I915_READ(reg
);
1764 val
&= ~TRANS_ENABLE
;
1765 I915_WRITE(reg
, val
);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1768 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1770 if (!HAS_PCH_IBX(dev
)) {
1771 /* Workaround: Clear the timing override chicken bit again. */
1772 reg
= TRANS_CHICKEN2(pipe
);
1773 val
= I915_READ(reg
);
1774 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1775 I915_WRITE(reg
, val
);
1779 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1783 val
= I915_READ(_TRANSACONF
);
1784 val
&= ~TRANS_ENABLE
;
1785 I915_WRITE(_TRANSACONF
, val
);
1786 /* wait for PCH transcoder off, transcoder state */
1787 if (wait_for((I915_READ(_TRANSACONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1788 DRM_ERROR("Failed to disable PCH transcoder\n");
1790 /* Workaround: clear timing override bit. */
1791 val
= I915_READ(_TRANSA_CHICKEN2
);
1792 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1793 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1797 * intel_enable_pipe - enable a pipe, asserting requirements
1798 * @dev_priv: i915 private structure
1799 * @pipe: pipe to enable
1800 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1802 * Enable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1805 * @pipe should be %PIPE_A or %PIPE_B.
1807 * Will wait until the pipe is actually running (i.e. first vblank) before
1810 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1813 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1815 enum transcoder pch_transcoder
;
1819 if (IS_HASWELL(dev_priv
->dev
))
1820 pch_transcoder
= TRANSCODER_A
;
1822 pch_transcoder
= pipe
;
1825 * A pipe without a PLL won't actually be able to drive bits from
1826 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1829 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1830 assert_pll_enabled(dev_priv
, pipe
);
1833 /* if driving the PCH, we need FDI enabled */
1834 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1835 assert_fdi_tx_pll_enabled(dev_priv
, cpu_transcoder
);
1837 /* FIXME: assert CPU port conditions for SNB+ */
1840 reg
= PIPECONF(cpu_transcoder
);
1841 val
= I915_READ(reg
);
1842 if (val
& PIPECONF_ENABLE
)
1845 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1846 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1850 * intel_disable_pipe - disable a pipe, asserting requirements
1851 * @dev_priv: i915 private structure
1852 * @pipe: pipe to disable
1854 * Disable @pipe, making sure that various hardware specific requirements
1855 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1857 * @pipe should be %PIPE_A or %PIPE_B.
1859 * Will wait until the pipe has shut down before returning.
1861 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1864 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1870 * Make sure planes won't keep trying to pump pixels to us,
1871 * or we might hang the display.
1873 assert_planes_disabled(dev_priv
, pipe
);
1875 /* Don't disable pipe A or pipe A PLLs if needed */
1876 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1879 reg
= PIPECONF(cpu_transcoder
);
1880 val
= I915_READ(reg
);
1881 if ((val
& PIPECONF_ENABLE
) == 0)
1884 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1885 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1889 * Plane regs are double buffered, going from enabled->disabled needs a
1890 * trigger in order to latch. The display address reg provides this.
1892 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1895 if (dev_priv
->info
->gen
>= 4)
1896 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1898 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1902 * intel_enable_plane - enable a display plane on a given pipe
1903 * @dev_priv: i915 private structure
1904 * @plane: plane to enable
1905 * @pipe: pipe being fed
1907 * Enable @plane on @pipe, making sure that @pipe is running first.
1909 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1910 enum plane plane
, enum pipe pipe
)
1915 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1916 assert_pipe_enabled(dev_priv
, pipe
);
1918 reg
= DSPCNTR(plane
);
1919 val
= I915_READ(reg
);
1920 if (val
& DISPLAY_PLANE_ENABLE
)
1923 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1924 intel_flush_display_plane(dev_priv
, plane
);
1925 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1929 * intel_disable_plane - disable a display plane
1930 * @dev_priv: i915 private structure
1931 * @plane: plane to disable
1932 * @pipe: pipe consuming the data
1934 * Disable @plane; should be an independent operation.
1936 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1937 enum plane plane
, enum pipe pipe
)
1942 reg
= DSPCNTR(plane
);
1943 val
= I915_READ(reg
);
1944 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1947 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1948 intel_flush_display_plane(dev_priv
, plane
);
1949 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1953 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1954 struct drm_i915_gem_object
*obj
,
1955 struct intel_ring_buffer
*pipelined
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1961 switch (obj
->tiling_mode
) {
1962 case I915_TILING_NONE
:
1963 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1964 alignment
= 128 * 1024;
1965 else if (INTEL_INFO(dev
)->gen
>= 4)
1966 alignment
= 4 * 1024;
1968 alignment
= 64 * 1024;
1971 /* pin() will align the object as required by fence */
1975 /* FIXME: Is this true? */
1976 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1982 dev_priv
->mm
.interruptible
= false;
1983 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1985 goto err_interruptible
;
1987 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1988 * fence, whereas 965+ only requires a fence if using
1989 * framebuffer compression. For simplicity, we always install
1990 * a fence as the cost is not that onerous.
1992 ret
= i915_gem_object_get_fence(obj
);
1996 i915_gem_object_pin_fence(obj
);
1998 dev_priv
->mm
.interruptible
= true;
2002 i915_gem_object_unpin(obj
);
2004 dev_priv
->mm
.interruptible
= true;
2008 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2010 i915_gem_object_unpin_fence(obj
);
2011 i915_gem_object_unpin(obj
);
2014 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2015 * is assumed to be a power-of-two. */
2016 unsigned long intel_gen4_compute_offset_xtiled(int *x
, int *y
,
2020 int tile_rows
, tiles
;
2024 tiles
= *x
/ (512/bpp
);
2027 return tile_rows
* pitch
* 8 + tiles
* 4096;
2030 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2033 struct drm_device
*dev
= crtc
->dev
;
2034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2036 struct intel_framebuffer
*intel_fb
;
2037 struct drm_i915_gem_object
*obj
;
2038 int plane
= intel_crtc
->plane
;
2039 unsigned long linear_offset
;
2048 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2052 intel_fb
= to_intel_framebuffer(fb
);
2053 obj
= intel_fb
->obj
;
2055 reg
= DSPCNTR(plane
);
2056 dspcntr
= I915_READ(reg
);
2057 /* Mask out pixel format bits in case we change it */
2058 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2059 switch (fb
->pixel_format
) {
2061 dspcntr
|= DISPPLANE_8BPP
;
2063 case DRM_FORMAT_XRGB1555
:
2064 case DRM_FORMAT_ARGB1555
:
2065 dspcntr
|= DISPPLANE_BGRX555
;
2067 case DRM_FORMAT_RGB565
:
2068 dspcntr
|= DISPPLANE_BGRX565
;
2070 case DRM_FORMAT_XRGB8888
:
2071 case DRM_FORMAT_ARGB8888
:
2072 dspcntr
|= DISPPLANE_BGRX888
;
2074 case DRM_FORMAT_XBGR8888
:
2075 case DRM_FORMAT_ABGR8888
:
2076 dspcntr
|= DISPPLANE_RGBX888
;
2078 case DRM_FORMAT_XRGB2101010
:
2079 case DRM_FORMAT_ARGB2101010
:
2080 dspcntr
|= DISPPLANE_BGRX101010
;
2082 case DRM_FORMAT_XBGR2101010
:
2083 case DRM_FORMAT_ABGR2101010
:
2084 dspcntr
|= DISPPLANE_RGBX101010
;
2087 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2091 if (INTEL_INFO(dev
)->gen
>= 4) {
2092 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2093 dspcntr
|= DISPPLANE_TILED
;
2095 dspcntr
&= ~DISPPLANE_TILED
;
2098 I915_WRITE(reg
, dspcntr
);
2100 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2102 if (INTEL_INFO(dev
)->gen
>= 4) {
2103 intel_crtc
->dspaddr_offset
=
2104 intel_gen4_compute_offset_xtiled(&x
, &y
,
2105 fb
->bits_per_pixel
/ 8,
2107 linear_offset
-= intel_crtc
->dspaddr_offset
;
2109 intel_crtc
->dspaddr_offset
= linear_offset
;
2112 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2113 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2114 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2115 if (INTEL_INFO(dev
)->gen
>= 4) {
2116 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2117 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2118 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2119 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2121 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2127 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2128 struct drm_framebuffer
*fb
, int x
, int y
)
2130 struct drm_device
*dev
= crtc
->dev
;
2131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2132 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2133 struct intel_framebuffer
*intel_fb
;
2134 struct drm_i915_gem_object
*obj
;
2135 int plane
= intel_crtc
->plane
;
2136 unsigned long linear_offset
;
2146 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2150 intel_fb
= to_intel_framebuffer(fb
);
2151 obj
= intel_fb
->obj
;
2153 reg
= DSPCNTR(plane
);
2154 dspcntr
= I915_READ(reg
);
2155 /* Mask out pixel format bits in case we change it */
2156 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2157 switch (fb
->pixel_format
) {
2159 dspcntr
|= DISPPLANE_8BPP
;
2161 case DRM_FORMAT_RGB565
:
2162 dspcntr
|= DISPPLANE_BGRX565
;
2164 case DRM_FORMAT_XRGB8888
:
2165 case DRM_FORMAT_ARGB8888
:
2166 dspcntr
|= DISPPLANE_BGRX888
;
2168 case DRM_FORMAT_XBGR8888
:
2169 case DRM_FORMAT_ABGR8888
:
2170 dspcntr
|= DISPPLANE_RGBX888
;
2172 case DRM_FORMAT_XRGB2101010
:
2173 case DRM_FORMAT_ARGB2101010
:
2174 dspcntr
|= DISPPLANE_BGRX101010
;
2176 case DRM_FORMAT_XBGR2101010
:
2177 case DRM_FORMAT_ABGR2101010
:
2178 dspcntr
|= DISPPLANE_RGBX101010
;
2181 DRM_ERROR("Unknown pixel format 0x%08x\n", fb
->pixel_format
);
2185 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2186 dspcntr
|= DISPPLANE_TILED
;
2188 dspcntr
&= ~DISPPLANE_TILED
;
2191 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2193 I915_WRITE(reg
, dspcntr
);
2195 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2196 intel_crtc
->dspaddr_offset
=
2197 intel_gen4_compute_offset_xtiled(&x
, &y
,
2198 fb
->bits_per_pixel
/ 8,
2200 linear_offset
-= intel_crtc
->dspaddr_offset
;
2202 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2203 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2204 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2205 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2206 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2207 if (IS_HASWELL(dev
)) {
2208 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2210 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2211 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2218 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2220 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2221 int x
, int y
, enum mode_set_atomic state
)
2223 struct drm_device
*dev
= crtc
->dev
;
2224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2226 if (dev_priv
->display
.disable_fbc
)
2227 dev_priv
->display
.disable_fbc(dev
);
2228 intel_increase_pllclock(crtc
);
2230 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2234 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2236 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2237 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2238 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2241 wait_event(dev_priv
->pending_flip_queue
,
2242 atomic_read(&dev_priv
->mm
.wedged
) ||
2243 atomic_read(&obj
->pending_flip
) == 0);
2245 /* Big Hammer, we also need to ensure that any pending
2246 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2247 * current scanout is retired before unpinning the old
2250 * This should only fail upon a hung GPU, in which case we
2251 * can safely continue.
2253 dev_priv
->mm
.interruptible
= false;
2254 ret
= i915_gem_object_finish_gpu(obj
);
2255 dev_priv
->mm
.interruptible
= was_interruptible
;
2260 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2262 struct drm_device
*dev
= crtc
->dev
;
2263 struct drm_i915_master_private
*master_priv
;
2264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2266 if (!dev
->primary
->master
)
2269 master_priv
= dev
->primary
->master
->driver_priv
;
2270 if (!master_priv
->sarea_priv
)
2273 switch (intel_crtc
->pipe
) {
2275 master_priv
->sarea_priv
->pipeA_x
= x
;
2276 master_priv
->sarea_priv
->pipeA_y
= y
;
2279 master_priv
->sarea_priv
->pipeB_x
= x
;
2280 master_priv
->sarea_priv
->pipeB_y
= y
;
2288 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2289 struct drm_framebuffer
*fb
)
2291 struct drm_device
*dev
= crtc
->dev
;
2292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2293 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2294 struct drm_framebuffer
*old_fb
;
2299 DRM_ERROR("No FB bound\n");
2303 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2304 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2306 dev_priv
->num_pipe
);
2310 mutex_lock(&dev
->struct_mutex
);
2311 ret
= intel_pin_and_fence_fb_obj(dev
,
2312 to_intel_framebuffer(fb
)->obj
,
2315 mutex_unlock(&dev
->struct_mutex
);
2316 DRM_ERROR("pin & fence failed\n");
2321 intel_finish_fb(crtc
->fb
);
2323 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2325 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2326 mutex_unlock(&dev
->struct_mutex
);
2327 DRM_ERROR("failed to update base address\n");
2337 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2338 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2341 intel_update_fbc(dev
);
2342 mutex_unlock(&dev
->struct_mutex
);
2344 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2349 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2351 struct drm_device
*dev
= crtc
->dev
;
2352 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2355 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2356 dpa_ctl
= I915_READ(DP_A
);
2357 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2359 if (clock
< 200000) {
2361 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2362 /* workaround for 160Mhz:
2363 1) program 0x4600c bits 15:0 = 0x8124
2364 2) program 0x46010 bit 0 = 1
2365 3) program 0x46034 bit 24 = 1
2366 4) program 0x64000 bit 14 = 1
2368 temp
= I915_READ(0x4600c);
2370 I915_WRITE(0x4600c, temp
| 0x8124);
2372 temp
= I915_READ(0x46010);
2373 I915_WRITE(0x46010, temp
| 1);
2375 temp
= I915_READ(0x46034);
2376 I915_WRITE(0x46034, temp
| (1 << 24));
2378 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2380 I915_WRITE(DP_A
, dpa_ctl
);
2386 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2388 struct drm_device
*dev
= crtc
->dev
;
2389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2391 int pipe
= intel_crtc
->pipe
;
2394 /* enable normal train */
2395 reg
= FDI_TX_CTL(pipe
);
2396 temp
= I915_READ(reg
);
2397 if (IS_IVYBRIDGE(dev
)) {
2398 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2399 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2401 temp
&= ~FDI_LINK_TRAIN_NONE
;
2402 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2404 I915_WRITE(reg
, temp
);
2406 reg
= FDI_RX_CTL(pipe
);
2407 temp
= I915_READ(reg
);
2408 if (HAS_PCH_CPT(dev
)) {
2409 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2410 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2412 temp
&= ~FDI_LINK_TRAIN_NONE
;
2413 temp
|= FDI_LINK_TRAIN_NONE
;
2415 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2417 /* wait one idle pattern time */
2421 /* IVB wants error correction enabled */
2422 if (IS_IVYBRIDGE(dev
))
2423 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2424 FDI_FE_ERRC_ENABLE
);
2427 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2430 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2432 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2433 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2434 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2435 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2436 POSTING_READ(SOUTH_CHICKEN1
);
2439 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2442 struct intel_crtc
*pipe_B_crtc
=
2443 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2444 struct intel_crtc
*pipe_C_crtc
=
2445 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2448 /* When everything is off disable fdi C so that we could enable fdi B
2449 * with all lanes. XXX: This misses the case where a pipe is not using
2450 * any pch resources and so doesn't need any fdi lanes. */
2451 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2452 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2455 temp
= I915_READ(SOUTH_CHICKEN1
);
2456 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2457 DRM_DEBUG_KMS("disabling fdi C rx\n");
2458 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2462 /* The FDI link training functions for ILK/Ibexpeak. */
2463 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2465 struct drm_device
*dev
= crtc
->dev
;
2466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2467 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2468 int pipe
= intel_crtc
->pipe
;
2469 int plane
= intel_crtc
->plane
;
2470 u32 reg
, temp
, tries
;
2472 /* FDI needs bits from pipe & plane first */
2473 assert_pipe_enabled(dev_priv
, pipe
);
2474 assert_plane_enabled(dev_priv
, plane
);
2476 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2478 reg
= FDI_RX_IMR(pipe
);
2479 temp
= I915_READ(reg
);
2480 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2481 temp
&= ~FDI_RX_BIT_LOCK
;
2482 I915_WRITE(reg
, temp
);
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg
= FDI_TX_CTL(pipe
);
2488 temp
= I915_READ(reg
);
2490 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2491 temp
&= ~FDI_LINK_TRAIN_NONE
;
2492 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2493 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2495 reg
= FDI_RX_CTL(pipe
);
2496 temp
= I915_READ(reg
);
2497 temp
&= ~FDI_LINK_TRAIN_NONE
;
2498 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2499 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2504 /* Ironlake workaround, enable clock pointer after FDI enable*/
2505 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2506 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2507 FDI_RX_PHASE_SYNC_POINTER_EN
);
2509 reg
= FDI_RX_IIR(pipe
);
2510 for (tries
= 0; tries
< 5; tries
++) {
2511 temp
= I915_READ(reg
);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2514 if ((temp
& FDI_RX_BIT_LOCK
)) {
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
2516 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2521 DRM_ERROR("FDI train 1 fail!\n");
2524 reg
= FDI_TX_CTL(pipe
);
2525 temp
= I915_READ(reg
);
2526 temp
&= ~FDI_LINK_TRAIN_NONE
;
2527 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2528 I915_WRITE(reg
, temp
);
2530 reg
= FDI_RX_CTL(pipe
);
2531 temp
= I915_READ(reg
);
2532 temp
&= ~FDI_LINK_TRAIN_NONE
;
2533 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2534 I915_WRITE(reg
, temp
);
2539 reg
= FDI_RX_IIR(pipe
);
2540 for (tries
= 0; tries
< 5; tries
++) {
2541 temp
= I915_READ(reg
);
2542 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2544 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2545 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2546 DRM_DEBUG_KMS("FDI train 2 done.\n");
2551 DRM_ERROR("FDI train 2 fail!\n");
2553 DRM_DEBUG_KMS("FDI train done\n");
2557 static const int snb_b_fdi_train_param
[] = {
2558 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2559 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2560 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2561 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2564 /* The FDI link training functions for SNB/Cougarpoint. */
2565 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2567 struct drm_device
*dev
= crtc
->dev
;
2568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2570 int pipe
= intel_crtc
->pipe
;
2571 u32 reg
, temp
, i
, retry
;
2573 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2575 reg
= FDI_RX_IMR(pipe
);
2576 temp
= I915_READ(reg
);
2577 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2578 temp
&= ~FDI_RX_BIT_LOCK
;
2579 I915_WRITE(reg
, temp
);
2584 /* enable CPU FDI TX and PCH FDI RX */
2585 reg
= FDI_TX_CTL(pipe
);
2586 temp
= I915_READ(reg
);
2588 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2589 temp
&= ~FDI_LINK_TRAIN_NONE
;
2590 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2591 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2593 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2594 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2596 I915_WRITE(FDI_RX_MISC(pipe
),
2597 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2599 reg
= FDI_RX_CTL(pipe
);
2600 temp
= I915_READ(reg
);
2601 if (HAS_PCH_CPT(dev
)) {
2602 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2603 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2605 temp
&= ~FDI_LINK_TRAIN_NONE
;
2606 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2608 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2613 cpt_phase_pointer_enable(dev
, pipe
);
2615 for (i
= 0; i
< 4; i
++) {
2616 reg
= FDI_TX_CTL(pipe
);
2617 temp
= I915_READ(reg
);
2618 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2619 temp
|= snb_b_fdi_train_param
[i
];
2620 I915_WRITE(reg
, temp
);
2625 for (retry
= 0; retry
< 5; retry
++) {
2626 reg
= FDI_RX_IIR(pipe
);
2627 temp
= I915_READ(reg
);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2629 if (temp
& FDI_RX_BIT_LOCK
) {
2630 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2631 DRM_DEBUG_KMS("FDI train 1 done.\n");
2640 DRM_ERROR("FDI train 1 fail!\n");
2643 reg
= FDI_TX_CTL(pipe
);
2644 temp
= I915_READ(reg
);
2645 temp
&= ~FDI_LINK_TRAIN_NONE
;
2646 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2648 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2650 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2652 I915_WRITE(reg
, temp
);
2654 reg
= FDI_RX_CTL(pipe
);
2655 temp
= I915_READ(reg
);
2656 if (HAS_PCH_CPT(dev
)) {
2657 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2658 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2660 temp
&= ~FDI_LINK_TRAIN_NONE
;
2661 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2663 I915_WRITE(reg
, temp
);
2668 for (i
= 0; i
< 4; i
++) {
2669 reg
= FDI_TX_CTL(pipe
);
2670 temp
= I915_READ(reg
);
2671 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2672 temp
|= snb_b_fdi_train_param
[i
];
2673 I915_WRITE(reg
, temp
);
2678 for (retry
= 0; retry
< 5; retry
++) {
2679 reg
= FDI_RX_IIR(pipe
);
2680 temp
= I915_READ(reg
);
2681 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2682 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2683 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2684 DRM_DEBUG_KMS("FDI train 2 done.\n");
2693 DRM_ERROR("FDI train 2 fail!\n");
2695 DRM_DEBUG_KMS("FDI train done.\n");
2698 /* Manual link training for Ivy Bridge A0 parts */
2699 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2701 struct drm_device
*dev
= crtc
->dev
;
2702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2703 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2704 int pipe
= intel_crtc
->pipe
;
2707 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2709 reg
= FDI_RX_IMR(pipe
);
2710 temp
= I915_READ(reg
);
2711 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2712 temp
&= ~FDI_RX_BIT_LOCK
;
2713 I915_WRITE(reg
, temp
);
2718 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2719 I915_READ(FDI_RX_IIR(pipe
)));
2721 /* enable CPU FDI TX and PCH FDI RX */
2722 reg
= FDI_TX_CTL(pipe
);
2723 temp
= I915_READ(reg
);
2725 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2726 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2727 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2728 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2729 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2730 temp
|= FDI_COMPOSITE_SYNC
;
2731 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2733 I915_WRITE(FDI_RX_MISC(pipe
),
2734 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2736 reg
= FDI_RX_CTL(pipe
);
2737 temp
= I915_READ(reg
);
2738 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2739 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2740 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2741 temp
|= FDI_COMPOSITE_SYNC
;
2742 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2747 cpt_phase_pointer_enable(dev
, pipe
);
2749 for (i
= 0; i
< 4; i
++) {
2750 reg
= FDI_TX_CTL(pipe
);
2751 temp
= I915_READ(reg
);
2752 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2753 temp
|= snb_b_fdi_train_param
[i
];
2754 I915_WRITE(reg
, temp
);
2759 reg
= FDI_RX_IIR(pipe
);
2760 temp
= I915_READ(reg
);
2761 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2763 if (temp
& FDI_RX_BIT_LOCK
||
2764 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2765 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2766 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2771 DRM_ERROR("FDI train 1 fail!\n");
2774 reg
= FDI_TX_CTL(pipe
);
2775 temp
= I915_READ(reg
);
2776 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2777 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2778 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2779 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2780 I915_WRITE(reg
, temp
);
2782 reg
= FDI_RX_CTL(pipe
);
2783 temp
= I915_READ(reg
);
2784 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2785 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2786 I915_WRITE(reg
, temp
);
2791 for (i
= 0; i
< 4; i
++) {
2792 reg
= FDI_TX_CTL(pipe
);
2793 temp
= I915_READ(reg
);
2794 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2795 temp
|= snb_b_fdi_train_param
[i
];
2796 I915_WRITE(reg
, temp
);
2801 reg
= FDI_RX_IIR(pipe
);
2802 temp
= I915_READ(reg
);
2803 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2805 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2806 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2807 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2812 DRM_ERROR("FDI train 2 fail!\n");
2814 DRM_DEBUG_KMS("FDI train done.\n");
2817 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2819 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2821 int pipe
= intel_crtc
->pipe
;
2825 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2826 reg
= FDI_RX_CTL(pipe
);
2827 temp
= I915_READ(reg
);
2828 temp
&= ~((0x7 << 19) | (0x7 << 16));
2829 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2830 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2831 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2836 /* Switch from Rawclk to PCDclk */
2837 temp
= I915_READ(reg
);
2838 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2843 /* On Haswell, the PLL configuration for ports and pipes is handled
2844 * separately, as part of DDI setup */
2845 if (!IS_HASWELL(dev
)) {
2846 /* Enable CPU FDI TX PLL, always on for Ironlake */
2847 reg
= FDI_TX_CTL(pipe
);
2848 temp
= I915_READ(reg
);
2849 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2850 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2858 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2860 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2861 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2862 int pipe
= intel_crtc
->pipe
;
2865 /* Switch from PCDclk to Rawclk */
2866 reg
= FDI_RX_CTL(pipe
);
2867 temp
= I915_READ(reg
);
2868 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2870 /* Disable CPU FDI TX PLL */
2871 reg
= FDI_TX_CTL(pipe
);
2872 temp
= I915_READ(reg
);
2873 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2878 reg
= FDI_RX_CTL(pipe
);
2879 temp
= I915_READ(reg
);
2880 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2882 /* Wait for the clocks to turn off. */
2887 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2890 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2892 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2893 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2894 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2895 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2896 POSTING_READ(SOUTH_CHICKEN1
);
2898 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2900 struct drm_device
*dev
= crtc
->dev
;
2901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2902 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2903 int pipe
= intel_crtc
->pipe
;
2906 /* disable CPU FDI tx and PCH FDI rx */
2907 reg
= FDI_TX_CTL(pipe
);
2908 temp
= I915_READ(reg
);
2909 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2912 reg
= FDI_RX_CTL(pipe
);
2913 temp
= I915_READ(reg
);
2914 temp
&= ~(0x7 << 16);
2915 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2916 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2921 /* Ironlake workaround, disable clock pointer after downing FDI */
2922 if (HAS_PCH_IBX(dev
)) {
2923 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2924 } else if (HAS_PCH_CPT(dev
)) {
2925 cpt_phase_pointer_disable(dev
, pipe
);
2928 /* still set train pattern 1 */
2929 reg
= FDI_TX_CTL(pipe
);
2930 temp
= I915_READ(reg
);
2931 temp
&= ~FDI_LINK_TRAIN_NONE
;
2932 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2933 I915_WRITE(reg
, temp
);
2935 reg
= FDI_RX_CTL(pipe
);
2936 temp
= I915_READ(reg
);
2937 if (HAS_PCH_CPT(dev
)) {
2938 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2939 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2941 temp
&= ~FDI_LINK_TRAIN_NONE
;
2942 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2944 /* BPC in FDI rx is consistent with that in PIPECONF */
2945 temp
&= ~(0x07 << 16);
2946 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2947 I915_WRITE(reg
, temp
);
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2955 struct drm_device
*dev
= crtc
->dev
;
2956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2957 unsigned long flags
;
2960 if (atomic_read(&dev_priv
->mm
.wedged
))
2963 spin_lock_irqsave(&dev
->event_lock
, flags
);
2964 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2965 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2972 struct drm_device
*dev
= crtc
->dev
;
2973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2975 if (crtc
->fb
== NULL
)
2978 wait_event(dev_priv
->pending_flip_queue
,
2979 !intel_crtc_has_pending_flip(crtc
));
2981 mutex_lock(&dev
->struct_mutex
);
2982 intel_finish_fb(crtc
->fb
);
2983 mutex_unlock(&dev
->struct_mutex
);
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2988 struct drm_device
*dev
= crtc
->dev
;
2989 struct intel_encoder
*intel_encoder
;
2992 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993 * must be driven by its own crtc; no sharing is possible.
2995 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2996 switch (intel_encoder
->type
) {
2997 case INTEL_OUTPUT_EDP
:
2998 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
3007 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
3009 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3015 struct drm_device
*dev
= crtc
->dev
;
3016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3017 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3020 /* It is necessary to ungate the pixclk gate prior to programming
3021 * the divisors, and gate it back when it is done.
3023 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3025 /* Disable SSCCTL */
3026 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3027 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
3028 SBI_SSCCTL_DISABLE
);
3030 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031 if (crtc
->mode
.clock
== 20000) {
3036 /* The iCLK virtual clock root frequency is in MHz,
3037 * but the crtc->mode.clock in in KHz. To get the divisors,
3038 * it is necessary to divide one by another, so we
3039 * convert the virtual clock precision to KHz here for higher
3042 u32 iclk_virtual_root_freq
= 172800 * 1000;
3043 u32 iclk_pi_range
= 64;
3044 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3046 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
3047 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3048 pi_value
= desired_divisor
% iclk_pi_range
;
3051 divsel
= msb_divisor_value
- 2;
3052 phaseinc
= pi_value
;
3055 /* This should not happen with any sane values */
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3057 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3058 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3059 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3061 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3068 /* Program SSCDIVINTPHASE6 */
3069 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
3070 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3071 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3072 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3073 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3074 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3075 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3077 intel_sbi_write(dev_priv
,
3078 SBI_SSCDIVINTPHASE6
,
3081 /* Program SSCAUXDIV */
3082 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
3083 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3085 intel_sbi_write(dev_priv
,
3090 /* Enable modulator and associated divider */
3091 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
3092 temp
&= ~SBI_SSCCTL_DISABLE
;
3093 intel_sbi_write(dev_priv
,
3097 /* Wait for initialization time */
3100 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3104 * Enable PCH resources required for PCH ports:
3106 * - FDI training & RX/TX
3107 * - update transcoder timings
3108 * - DP transcoding bits
3111 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3113 struct drm_device
*dev
= crtc
->dev
;
3114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3115 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3116 int pipe
= intel_crtc
->pipe
;
3119 assert_transcoder_disabled(dev_priv
, pipe
);
3121 /* Write the TU size bits before fdi link training, so that error
3122 * detection works. */
3123 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3124 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3126 /* For PCH output, training FDI link */
3127 dev_priv
->display
.fdi_link_train(crtc
);
3129 /* XXX: pch pll's can be enabled any time before we enable the PCH
3130 * transcoder, and we actually should do this to not upset any PCH
3131 * transcoder that already use the clock when we share it.
3133 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134 * unconditionally resets the pll - we need that to have the right LVDS
3135 * enable sequence. */
3136 ironlake_enable_pch_pll(intel_crtc
);
3138 if (HAS_PCH_CPT(dev
)) {
3141 temp
= I915_READ(PCH_DPLL_SEL
);
3145 temp
|= TRANSA_DPLL_ENABLE
;
3146 sel
= TRANSA_DPLLB_SEL
;
3149 temp
|= TRANSB_DPLL_ENABLE
;
3150 sel
= TRANSB_DPLLB_SEL
;
3153 temp
|= TRANSC_DPLL_ENABLE
;
3154 sel
= TRANSC_DPLLB_SEL
;
3157 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3161 I915_WRITE(PCH_DPLL_SEL
, temp
);
3164 /* set transcoder timing, panel must allow it */
3165 assert_panel_unlocked(dev_priv
, pipe
);
3166 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3167 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3168 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3170 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3171 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3172 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3173 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3175 intel_fdi_normal_train(crtc
);
3177 /* For PCH DP, enable TRANS_DP_CTL */
3178 if (HAS_PCH_CPT(dev
) &&
3179 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3180 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3181 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3182 reg
= TRANS_DP_CTL(pipe
);
3183 temp
= I915_READ(reg
);
3184 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3185 TRANS_DP_SYNC_MASK
|
3187 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3188 TRANS_DP_ENH_FRAMING
);
3189 temp
|= bpc
<< 9; /* same format but at 11:9 */
3191 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3192 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3193 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3194 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3196 switch (intel_trans_dp_port_sel(crtc
)) {
3198 temp
|= TRANS_DP_PORT_SEL_B
;
3201 temp
|= TRANS_DP_PORT_SEL_C
;
3204 temp
|= TRANS_DP_PORT_SEL_D
;
3210 I915_WRITE(reg
, temp
);
3213 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3216 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3218 struct drm_device
*dev
= crtc
->dev
;
3219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3220 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3221 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3223 assert_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3225 lpt_program_iclkip(crtc
);
3227 /* Set transcoder timing. */
3228 I915_WRITE(_TRANS_HTOTAL_A
, I915_READ(HTOTAL(cpu_transcoder
)));
3229 I915_WRITE(_TRANS_HBLANK_A
, I915_READ(HBLANK(cpu_transcoder
)));
3230 I915_WRITE(_TRANS_HSYNC_A
, I915_READ(HSYNC(cpu_transcoder
)));
3232 I915_WRITE(_TRANS_VTOTAL_A
, I915_READ(VTOTAL(cpu_transcoder
)));
3233 I915_WRITE(_TRANS_VBLANK_A
, I915_READ(VBLANK(cpu_transcoder
)));
3234 I915_WRITE(_TRANS_VSYNC_A
, I915_READ(VSYNC(cpu_transcoder
)));
3235 I915_WRITE(_TRANS_VSYNCSHIFT_A
, I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3237 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3240 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3242 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3247 if (pll
->refcount
== 0) {
3248 WARN(1, "bad PCH PLL refcount\n");
3253 intel_crtc
->pch_pll
= NULL
;
3256 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3258 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3259 struct intel_pch_pll
*pll
;
3262 pll
= intel_crtc
->pch_pll
;
3264 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3265 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3269 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3270 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3271 i
= intel_crtc
->pipe
;
3272 pll
= &dev_priv
->pch_plls
[i
];
3274 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3275 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3280 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3281 pll
= &dev_priv
->pch_plls
[i
];
3283 /* Only want to check enabled timings first */
3284 if (pll
->refcount
== 0)
3287 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3288 fp
== I915_READ(pll
->fp0_reg
)) {
3289 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3290 intel_crtc
->base
.base
.id
,
3291 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3297 /* Ok no matching timings, maybe there's a free one? */
3298 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3299 pll
= &dev_priv
->pch_plls
[i
];
3300 if (pll
->refcount
== 0) {
3301 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3302 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3310 intel_crtc
->pch_pll
= pll
;
3312 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3313 prepare
: /* separate function? */
3314 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3316 /* Wait for the clocks to stabilize before rewriting the regs */
3317 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3318 POSTING_READ(pll
->pll_reg
);
3321 I915_WRITE(pll
->fp0_reg
, fp
);
3322 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3327 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3330 int dslreg
= PIPEDSL(pipe
);
3333 temp
= I915_READ(dslreg
);
3335 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3336 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3337 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3341 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3343 struct drm_device
*dev
= crtc
->dev
;
3344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3346 struct intel_encoder
*encoder
;
3347 int pipe
= intel_crtc
->pipe
;
3348 int plane
= intel_crtc
->plane
;
3352 WARN_ON(!crtc
->enabled
);
3354 if (intel_crtc
->active
)
3357 intel_crtc
->active
= true;
3358 intel_update_watermarks(dev
);
3360 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3361 temp
= I915_READ(PCH_LVDS
);
3362 if ((temp
& LVDS_PORT_EN
) == 0)
3363 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3366 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3369 /* Note: FDI PLL enabling _must_ be done before we enable the
3370 * cpu pipes, hence this is separate from all the other fdi/pch
3372 ironlake_fdi_pll_enable(intel_crtc
);
3374 assert_fdi_tx_disabled(dev_priv
, pipe
);
3375 assert_fdi_rx_disabled(dev_priv
, pipe
);
3378 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3379 if (encoder
->pre_enable
)
3380 encoder
->pre_enable(encoder
);
3382 /* Enable panel fitting for LVDS */
3383 if (dev_priv
->pch_pf_size
&&
3384 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3385 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3386 /* Force use of hard-coded filter coefficients
3387 * as some pre-programmed values are broken,
3390 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3391 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3392 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3396 * On ILK+ LUT must be loaded before the pipe is running but with
3399 intel_crtc_load_lut(crtc
);
3401 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3402 intel_enable_plane(dev_priv
, plane
, pipe
);
3405 ironlake_pch_enable(crtc
);
3407 mutex_lock(&dev
->struct_mutex
);
3408 intel_update_fbc(dev
);
3409 mutex_unlock(&dev
->struct_mutex
);
3411 intel_crtc_update_cursor(crtc
, true);
3413 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3414 encoder
->enable(encoder
);
3416 if (HAS_PCH_CPT(dev
))
3417 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3420 * There seems to be a race in PCH platform hw (at least on some
3421 * outputs) where an enabled pipe still completes any pageflip right
3422 * away (as if the pipe is off) instead of waiting for vblank. As soon
3423 * as the first vblank happend, everything works as expected. Hence just
3424 * wait for one vblank before returning to avoid strange things
3427 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3430 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3432 struct drm_device
*dev
= crtc
->dev
;
3433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3434 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3435 struct intel_encoder
*encoder
;
3436 int pipe
= intel_crtc
->pipe
;
3437 int plane
= intel_crtc
->plane
;
3440 WARN_ON(!crtc
->enabled
);
3442 if (intel_crtc
->active
)
3445 intel_crtc
->active
= true;
3446 intel_update_watermarks(dev
);
3448 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3451 dev_priv
->display
.fdi_link_train(crtc
);
3453 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3454 if (encoder
->pre_enable
)
3455 encoder
->pre_enable(encoder
);
3457 intel_ddi_enable_pipe_clock(intel_crtc
);
3459 /* Enable panel fitting for eDP */
3460 if (dev_priv
->pch_pf_size
&&
3461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3462 /* Force use of hard-coded filter coefficients
3463 * as some pre-programmed values are broken,
3466 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3467 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3468 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3472 * On ILK+ LUT must be loaded before the pipe is running but with
3475 intel_crtc_load_lut(crtc
);
3477 intel_ddi_set_pipe_settings(crtc
);
3478 intel_ddi_enable_pipe_func(crtc
);
3480 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3481 intel_enable_plane(dev_priv
, plane
, pipe
);
3484 lpt_pch_enable(crtc
);
3486 mutex_lock(&dev
->struct_mutex
);
3487 intel_update_fbc(dev
);
3488 mutex_unlock(&dev
->struct_mutex
);
3490 intel_crtc_update_cursor(crtc
, true);
3492 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3493 encoder
->enable(encoder
);
3496 * There seems to be a race in PCH platform hw (at least on some
3497 * outputs) where an enabled pipe still completes any pageflip right
3498 * away (as if the pipe is off) instead of waiting for vblank. As soon
3499 * as the first vblank happend, everything works as expected. Hence just
3500 * wait for one vblank before returning to avoid strange things
3503 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3506 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3508 struct drm_device
*dev
= crtc
->dev
;
3509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3511 struct intel_encoder
*encoder
;
3512 int pipe
= intel_crtc
->pipe
;
3513 int plane
= intel_crtc
->plane
;
3517 if (!intel_crtc
->active
)
3520 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3521 encoder
->disable(encoder
);
3523 intel_crtc_wait_for_pending_flips(crtc
);
3524 drm_vblank_off(dev
, pipe
);
3525 intel_crtc_update_cursor(crtc
, false);
3527 intel_disable_plane(dev_priv
, plane
, pipe
);
3529 if (dev_priv
->cfb_plane
== plane
)
3530 intel_disable_fbc(dev
);
3532 intel_disable_pipe(dev_priv
, pipe
);
3535 I915_WRITE(PF_CTL(pipe
), 0);
3536 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3538 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3539 if (encoder
->post_disable
)
3540 encoder
->post_disable(encoder
);
3542 ironlake_fdi_disable(crtc
);
3544 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3546 if (HAS_PCH_CPT(dev
)) {
3547 /* disable TRANS_DP_CTL */
3548 reg
= TRANS_DP_CTL(pipe
);
3549 temp
= I915_READ(reg
);
3550 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3551 temp
|= TRANS_DP_PORT_SEL_NONE
;
3552 I915_WRITE(reg
, temp
);
3554 /* disable DPLL_SEL */
3555 temp
= I915_READ(PCH_DPLL_SEL
);
3558 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3561 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3564 /* C shares PLL A or B */
3565 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3570 I915_WRITE(PCH_DPLL_SEL
, temp
);
3573 /* disable PCH DPLL */
3574 intel_disable_pch_pll(intel_crtc
);
3576 ironlake_fdi_pll_disable(intel_crtc
);
3578 intel_crtc
->active
= false;
3579 intel_update_watermarks(dev
);
3581 mutex_lock(&dev
->struct_mutex
);
3582 intel_update_fbc(dev
);
3583 mutex_unlock(&dev
->struct_mutex
);
3586 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3588 struct drm_device
*dev
= crtc
->dev
;
3589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3590 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3591 struct intel_encoder
*encoder
;
3592 int pipe
= intel_crtc
->pipe
;
3593 int plane
= intel_crtc
->plane
;
3594 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3597 if (!intel_crtc
->active
)
3600 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3602 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3603 encoder
->disable(encoder
);
3605 intel_crtc_wait_for_pending_flips(crtc
);
3606 drm_vblank_off(dev
, pipe
);
3607 intel_crtc_update_cursor(crtc
, false);
3609 intel_disable_plane(dev_priv
, plane
, pipe
);
3611 if (dev_priv
->cfb_plane
== plane
)
3612 intel_disable_fbc(dev
);
3614 intel_disable_pipe(dev_priv
, pipe
);
3616 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3619 I915_WRITE(PF_CTL(pipe
), 0);
3620 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3622 intel_ddi_disable_pipe_clock(intel_crtc
);
3624 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3625 if (encoder
->post_disable
)
3626 encoder
->post_disable(encoder
);
3629 lpt_disable_pch_transcoder(dev_priv
);
3630 intel_ddi_fdi_disable(crtc
);
3633 intel_crtc
->active
= false;
3634 intel_update_watermarks(dev
);
3636 mutex_lock(&dev
->struct_mutex
);
3637 intel_update_fbc(dev
);
3638 mutex_unlock(&dev
->struct_mutex
);
3641 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3644 intel_put_pch_pll(intel_crtc
);
3647 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3651 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3652 * start using it. */
3653 intel_crtc
->cpu_transcoder
= intel_crtc
->pipe
;
3655 intel_ddi_put_crtc_pll(crtc
);
3658 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3660 if (!enable
&& intel_crtc
->overlay
) {
3661 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3664 mutex_lock(&dev
->struct_mutex
);
3665 dev_priv
->mm
.interruptible
= false;
3666 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3667 dev_priv
->mm
.interruptible
= true;
3668 mutex_unlock(&dev
->struct_mutex
);
3671 /* Let userspace switch the overlay on again. In most cases userspace
3672 * has to recompute where to put it anyway.
3676 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3678 struct drm_device
*dev
= crtc
->dev
;
3679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3680 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3681 struct intel_encoder
*encoder
;
3682 int pipe
= intel_crtc
->pipe
;
3683 int plane
= intel_crtc
->plane
;
3685 WARN_ON(!crtc
->enabled
);
3687 if (intel_crtc
->active
)
3690 intel_crtc
->active
= true;
3691 intel_update_watermarks(dev
);
3693 intel_enable_pll(dev_priv
, pipe
);
3694 intel_enable_pipe(dev_priv
, pipe
, false);
3695 intel_enable_plane(dev_priv
, plane
, pipe
);
3697 intel_crtc_load_lut(crtc
);
3698 intel_update_fbc(dev
);
3700 /* Give the overlay scaler a chance to enable if it's on this pipe */
3701 intel_crtc_dpms_overlay(intel_crtc
, true);
3702 intel_crtc_update_cursor(crtc
, true);
3704 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3705 encoder
->enable(encoder
);
3708 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3710 struct drm_device
*dev
= crtc
->dev
;
3711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3712 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3713 struct intel_encoder
*encoder
;
3714 int pipe
= intel_crtc
->pipe
;
3715 int plane
= intel_crtc
->plane
;
3718 if (!intel_crtc
->active
)
3721 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3722 encoder
->disable(encoder
);
3724 /* Give the overlay scaler a chance to disable if it's on this pipe */
3725 intel_crtc_wait_for_pending_flips(crtc
);
3726 drm_vblank_off(dev
, pipe
);
3727 intel_crtc_dpms_overlay(intel_crtc
, false);
3728 intel_crtc_update_cursor(crtc
, false);
3730 if (dev_priv
->cfb_plane
== plane
)
3731 intel_disable_fbc(dev
);
3733 intel_disable_plane(dev_priv
, plane
, pipe
);
3734 intel_disable_pipe(dev_priv
, pipe
);
3735 intel_disable_pll(dev_priv
, pipe
);
3737 intel_crtc
->active
= false;
3738 intel_update_fbc(dev
);
3739 intel_update_watermarks(dev
);
3742 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3746 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3749 struct drm_device
*dev
= crtc
->dev
;
3750 struct drm_i915_master_private
*master_priv
;
3751 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3752 int pipe
= intel_crtc
->pipe
;
3754 if (!dev
->primary
->master
)
3757 master_priv
= dev
->primary
->master
->driver_priv
;
3758 if (!master_priv
->sarea_priv
)
3763 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3764 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3767 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3768 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3771 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3777 * Sets the power management mode of the pipe and plane.
3779 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3781 struct drm_device
*dev
= crtc
->dev
;
3782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3783 struct intel_encoder
*intel_encoder
;
3784 bool enable
= false;
3786 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3787 enable
|= intel_encoder
->connectors_active
;
3790 dev_priv
->display
.crtc_enable(crtc
);
3792 dev_priv
->display
.crtc_disable(crtc
);
3794 intel_crtc_update_sarea(crtc
, enable
);
3797 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3801 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3803 struct drm_device
*dev
= crtc
->dev
;
3804 struct drm_connector
*connector
;
3805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3807 /* crtc should still be enabled when we disable it. */
3808 WARN_ON(!crtc
->enabled
);
3810 dev_priv
->display
.crtc_disable(crtc
);
3811 intel_crtc_update_sarea(crtc
, false);
3812 dev_priv
->display
.off(crtc
);
3814 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3815 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3818 mutex_lock(&dev
->struct_mutex
);
3819 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3820 mutex_unlock(&dev
->struct_mutex
);
3824 /* Update computed state. */
3825 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3826 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3829 if (connector
->encoder
->crtc
!= crtc
)
3832 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3833 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3837 void intel_modeset_disable(struct drm_device
*dev
)
3839 struct drm_crtc
*crtc
;
3841 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3843 intel_crtc_disable(crtc
);
3847 void intel_encoder_noop(struct drm_encoder
*encoder
)
3851 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3853 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3855 drm_encoder_cleanup(encoder
);
3856 kfree(intel_encoder
);
3859 /* Simple dpms helper for encodres with just one connector, no cloning and only
3860 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3861 * state of the entire output pipe. */
3862 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3864 if (mode
== DRM_MODE_DPMS_ON
) {
3865 encoder
->connectors_active
= true;
3867 intel_crtc_update_dpms(encoder
->base
.crtc
);
3869 encoder
->connectors_active
= false;
3871 intel_crtc_update_dpms(encoder
->base
.crtc
);
3875 /* Cross check the actual hw state with our own modeset state tracking (and it's
3876 * internal consistency). */
3877 static void intel_connector_check_state(struct intel_connector
*connector
)
3879 if (connector
->get_hw_state(connector
)) {
3880 struct intel_encoder
*encoder
= connector
->encoder
;
3881 struct drm_crtc
*crtc
;
3882 bool encoder_enabled
;
3885 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3886 connector
->base
.base
.id
,
3887 drm_get_connector_name(&connector
->base
));
3889 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3890 "wrong connector dpms state\n");
3891 WARN(connector
->base
.encoder
!= &encoder
->base
,
3892 "active connector not linked to encoder\n");
3893 WARN(!encoder
->connectors_active
,
3894 "encoder->connectors_active not set\n");
3896 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3897 WARN(!encoder_enabled
, "encoder not enabled\n");
3898 if (WARN_ON(!encoder
->base
.crtc
))
3901 crtc
= encoder
->base
.crtc
;
3903 WARN(!crtc
->enabled
, "crtc not enabled\n");
3904 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3905 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3906 "encoder active on the wrong pipe\n");
3910 /* Even simpler default implementation, if there's really no special case to
3912 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3914 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3916 /* All the simple cases only support two dpms states. */
3917 if (mode
!= DRM_MODE_DPMS_ON
)
3918 mode
= DRM_MODE_DPMS_OFF
;
3920 if (mode
== connector
->dpms
)
3923 connector
->dpms
= mode
;
3925 /* Only need to change hw state when actually enabled */
3926 if (encoder
->base
.crtc
)
3927 intel_encoder_dpms(encoder
, mode
);
3929 WARN_ON(encoder
->connectors_active
!= false);
3931 intel_modeset_check_state(connector
->dev
);
3934 /* Simple connector->get_hw_state implementation for encoders that support only
3935 * one connector and no cloning and hence the encoder state determines the state
3936 * of the connector. */
3937 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3940 struct intel_encoder
*encoder
= connector
->encoder
;
3942 return encoder
->get_hw_state(encoder
, &pipe
);
3945 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3946 const struct drm_display_mode
*mode
,
3947 struct drm_display_mode
*adjusted_mode
)
3949 struct drm_device
*dev
= crtc
->dev
;
3951 if (HAS_PCH_SPLIT(dev
)) {
3952 /* FDI link clock is fixed at 2.7G */
3953 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3957 /* All interlaced capable intel hw wants timings in frames. Note though
3958 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3959 * timings, so we need to be careful not to clobber these.*/
3960 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3961 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3963 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3964 * with a hsync front porch of 0.
3966 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3967 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3973 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3975 return 400000; /* FIXME */
3978 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3983 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3988 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3993 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3997 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3999 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4002 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4003 case GC_DISPLAY_CLOCK_333_MHZ
:
4006 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4012 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4017 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4020 /* Assume that the hardware is in the high speed state. This
4021 * should be the default.
4023 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4024 case GC_CLOCK_133_200
:
4025 case GC_CLOCK_100_200
:
4027 case GC_CLOCK_166_250
:
4029 case GC_CLOCK_100_133
:
4033 /* Shouldn't happen */
4037 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4051 fdi_reduce_ratio(u32
*num
, u32
*den
)
4053 while (*num
> 0xffffff || *den
> 0xffffff) {
4060 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
4061 int link_clock
, struct fdi_m_n
*m_n
)
4063 m_n
->tu
= 64; /* default size */
4065 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4066 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
4067 m_n
->gmch_n
= link_clock
* nlanes
* 8;
4068 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
4070 m_n
->link_m
= pixel_clock
;
4071 m_n
->link_n
= link_clock
;
4072 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
4075 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4077 if (i915_panel_use_ssc
>= 0)
4078 return i915_panel_use_ssc
!= 0;
4079 return dev_priv
->lvds_use_ssc
4080 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4084 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4085 * @crtc: CRTC structure
4086 * @mode: requested mode
4088 * A pipe may be connected to one or more outputs. Based on the depth of the
4089 * attached framebuffer, choose a good color depth to use on the pipe.
4091 * If possible, match the pipe depth to the fb depth. In some cases, this
4092 * isn't ideal, because the connected output supports a lesser or restricted
4093 * set of depths. Resolve that here:
4094 * LVDS typically supports only 6bpc, so clamp down in that case
4095 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4096 * Displays may support a restricted set as well, check EDID and clamp as
4098 * DP may want to dither down to 6bpc to fit larger modes
4101 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4102 * true if they don't match).
4104 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4105 struct drm_framebuffer
*fb
,
4106 unsigned int *pipe_bpp
,
4107 struct drm_display_mode
*mode
)
4109 struct drm_device
*dev
= crtc
->dev
;
4110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4111 struct drm_connector
*connector
;
4112 struct intel_encoder
*intel_encoder
;
4113 unsigned int display_bpc
= UINT_MAX
, bpc
;
4115 /* Walk the encoders & connectors on this crtc, get min bpc */
4116 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4118 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4119 unsigned int lvds_bpc
;
4121 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4127 if (lvds_bpc
< display_bpc
) {
4128 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4129 display_bpc
= lvds_bpc
;
4134 /* Not one of the known troublemakers, check the EDID */
4135 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4137 if (connector
->encoder
!= &intel_encoder
->base
)
4140 /* Don't use an invalid EDID bpc value */
4141 if (connector
->display_info
.bpc
&&
4142 connector
->display_info
.bpc
< display_bpc
) {
4143 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4144 display_bpc
= connector
->display_info
.bpc
;
4149 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4150 * through, clamp it down. (Note: >12bpc will be caught below.)
4152 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4153 if (display_bpc
> 8 && display_bpc
< 12) {
4154 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4157 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4163 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4164 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4169 * We could just drive the pipe at the highest bpc all the time and
4170 * enable dithering as needed, but that costs bandwidth. So choose
4171 * the minimum value that expresses the full color range of the fb but
4172 * also stays within the max display bpc discovered above.
4175 switch (fb
->depth
) {
4177 bpc
= 8; /* since we go through a colormap */
4181 bpc
= 6; /* min is 18bpp */
4193 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4194 bpc
= min((unsigned int)8, display_bpc
);
4198 display_bpc
= min(display_bpc
, bpc
);
4200 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4203 *pipe_bpp
= display_bpc
* 3;
4205 return display_bpc
!= bpc
;
4208 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4210 struct drm_device
*dev
= crtc
->dev
;
4211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4212 int refclk
= 27000; /* for DP & HDMI */
4214 return 100000; /* only one validated so far */
4216 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4218 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4219 if (intel_panel_use_ssc(dev_priv
))
4223 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4230 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4232 struct drm_device
*dev
= crtc
->dev
;
4233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 if (IS_VALLEYVIEW(dev
)) {
4237 refclk
= vlv_get_refclk(crtc
);
4238 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4239 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4240 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4241 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4243 } else if (!IS_GEN2(dev
)) {
4252 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4253 intel_clock_t
*clock
)
4255 /* SDVO TV has fixed PLL values depend on its clock range,
4256 this mirrors vbios setting. */
4257 if (adjusted_mode
->clock
>= 100000
4258 && adjusted_mode
->clock
< 140500) {
4264 } else if (adjusted_mode
->clock
>= 140500
4265 && adjusted_mode
->clock
<= 200000) {
4274 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4275 intel_clock_t
*clock
,
4276 intel_clock_t
*reduced_clock
)
4278 struct drm_device
*dev
= crtc
->dev
;
4279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4281 int pipe
= intel_crtc
->pipe
;
4284 if (IS_PINEVIEW(dev
)) {
4285 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4287 fp2
= (1 << reduced_clock
->n
) << 16 |
4288 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4290 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4292 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4296 I915_WRITE(FP0(pipe
), fp
);
4298 intel_crtc
->lowfreq_avail
= false;
4299 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4300 reduced_clock
&& i915_powersave
) {
4301 I915_WRITE(FP1(pipe
), fp2
);
4302 intel_crtc
->lowfreq_avail
= true;
4304 I915_WRITE(FP1(pipe
), fp
);
4308 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
4309 struct drm_display_mode
*adjusted_mode
)
4311 struct drm_device
*dev
= crtc
->dev
;
4312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4313 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4314 int pipe
= intel_crtc
->pipe
;
4317 temp
= I915_READ(LVDS
);
4318 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4320 temp
|= LVDS_PIPEB_SELECT
;
4322 temp
&= ~LVDS_PIPEB_SELECT
;
4324 /* set the corresponsding LVDS_BORDER bit */
4325 temp
|= dev_priv
->lvds_border_bits
;
4326 /* Set the B0-B3 data pairs corresponding to whether we're going to
4327 * set the DPLLs for dual-channel mode or not.
4330 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4332 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4334 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4335 * appropriately here, but we need to look more thoroughly into how
4336 * panels behave in the two modes.
4338 /* set the dithering flag on LVDS as needed */
4339 if (INTEL_INFO(dev
)->gen
>= 4) {
4340 if (dev_priv
->lvds_dither
)
4341 temp
|= LVDS_ENABLE_DITHER
;
4343 temp
&= ~LVDS_ENABLE_DITHER
;
4345 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4346 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4347 temp
|= LVDS_HSYNC_POLARITY
;
4348 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4349 temp
|= LVDS_VSYNC_POLARITY
;
4350 I915_WRITE(LVDS
, temp
);
4353 static void vlv_update_pll(struct drm_crtc
*crtc
,
4354 struct drm_display_mode
*mode
,
4355 struct drm_display_mode
*adjusted_mode
,
4356 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4359 struct drm_device
*dev
= crtc
->dev
;
4360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4361 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4362 int pipe
= intel_crtc
->pipe
;
4363 u32 dpll
, mdiv
, pdiv
;
4364 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4368 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4369 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4371 dpll
= DPLL_VGA_MODE_DIS
;
4372 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4373 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4374 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4376 I915_WRITE(DPLL(pipe
), dpll
);
4377 POSTING_READ(DPLL(pipe
));
4386 * In Valleyview PLL and program lane counter registers are exposed
4387 * through DPIO interface
4389 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4390 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4391 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4392 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4393 mdiv
|= (1 << DPIO_K_SHIFT
);
4394 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4395 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4397 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4399 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4400 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4401 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4402 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4403 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4405 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4407 dpll
|= DPLL_VCO_ENABLE
;
4408 I915_WRITE(DPLL(pipe
), dpll
);
4409 POSTING_READ(DPLL(pipe
));
4410 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4411 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4413 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4415 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4416 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4418 I915_WRITE(DPLL(pipe
), dpll
);
4420 /* Wait for the clocks to stabilize. */
4421 POSTING_READ(DPLL(pipe
));
4426 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4428 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4432 I915_WRITE(DPLL_MD(pipe
), temp
);
4433 POSTING_READ(DPLL_MD(pipe
));
4435 /* Now program lane control registers */
4436 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4437 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4442 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4444 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4449 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4453 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4454 struct drm_display_mode
*mode
,
4455 struct drm_display_mode
*adjusted_mode
,
4456 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4459 struct drm_device
*dev
= crtc
->dev
;
4460 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4462 int pipe
= intel_crtc
->pipe
;
4466 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4468 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4469 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4471 dpll
= DPLL_VGA_MODE_DIS
;
4473 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4474 dpll
|= DPLLB_MODE_LVDS
;
4476 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4478 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4479 if (pixel_multiplier
> 1) {
4480 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4481 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4483 dpll
|= DPLL_DVO_HIGH_SPEED
;
4485 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4486 dpll
|= DPLL_DVO_HIGH_SPEED
;
4488 /* compute bitmask from p1 value */
4489 if (IS_PINEVIEW(dev
))
4490 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4492 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4493 if (IS_G4X(dev
) && reduced_clock
)
4494 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4496 switch (clock
->p2
) {
4498 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4501 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4504 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4507 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4510 if (INTEL_INFO(dev
)->gen
>= 4)
4511 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4513 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4514 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4515 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4516 /* XXX: just matching BIOS for now */
4517 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4519 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4520 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4521 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4523 dpll
|= PLL_REF_INPUT_DREFCLK
;
4525 dpll
|= DPLL_VCO_ENABLE
;
4526 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4527 POSTING_READ(DPLL(pipe
));
4530 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4531 * This is an exception to the general rule that mode_set doesn't turn
4534 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4535 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4537 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4538 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4540 I915_WRITE(DPLL(pipe
), dpll
);
4542 /* Wait for the clocks to stabilize. */
4543 POSTING_READ(DPLL(pipe
));
4546 if (INTEL_INFO(dev
)->gen
>= 4) {
4549 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4551 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4555 I915_WRITE(DPLL_MD(pipe
), temp
);
4557 /* The pixel multiplier can only be updated once the
4558 * DPLL is enabled and the clocks are stable.
4560 * So write it again.
4562 I915_WRITE(DPLL(pipe
), dpll
);
4566 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4567 struct drm_display_mode
*adjusted_mode
,
4568 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4571 struct drm_device
*dev
= crtc
->dev
;
4572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4573 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4574 int pipe
= intel_crtc
->pipe
;
4577 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4579 dpll
= DPLL_VGA_MODE_DIS
;
4581 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4582 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4585 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4587 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4589 dpll
|= PLL_P2_DIVIDE_BY_4
;
4592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4593 /* XXX: just matching BIOS for now */
4594 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4596 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4597 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4598 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4600 dpll
|= PLL_REF_INPUT_DREFCLK
;
4602 dpll
|= DPLL_VCO_ENABLE
;
4603 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4604 POSTING_READ(DPLL(pipe
));
4607 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4608 * This is an exception to the general rule that mode_set doesn't turn
4611 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4612 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4614 I915_WRITE(DPLL(pipe
), dpll
);
4616 /* Wait for the clocks to stabilize. */
4617 POSTING_READ(DPLL(pipe
));
4620 /* The pixel multiplier can only be updated once the
4621 * DPLL is enabled and the clocks are stable.
4623 * So write it again.
4625 I915_WRITE(DPLL(pipe
), dpll
);
4628 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4629 struct drm_display_mode
*mode
,
4630 struct drm_display_mode
*adjusted_mode
)
4632 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4634 enum pipe pipe
= intel_crtc
->pipe
;
4635 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4636 uint32_t vsyncshift
;
4638 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4639 /* the chip adds 2 halflines automatically */
4640 adjusted_mode
->crtc_vtotal
-= 1;
4641 adjusted_mode
->crtc_vblank_end
-= 1;
4642 vsyncshift
= adjusted_mode
->crtc_hsync_start
4643 - adjusted_mode
->crtc_htotal
/ 2;
4648 if (INTEL_INFO(dev
)->gen
> 3)
4649 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4651 I915_WRITE(HTOTAL(cpu_transcoder
),
4652 (adjusted_mode
->crtc_hdisplay
- 1) |
4653 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4654 I915_WRITE(HBLANK(cpu_transcoder
),
4655 (adjusted_mode
->crtc_hblank_start
- 1) |
4656 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4657 I915_WRITE(HSYNC(cpu_transcoder
),
4658 (adjusted_mode
->crtc_hsync_start
- 1) |
4659 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4661 I915_WRITE(VTOTAL(cpu_transcoder
),
4662 (adjusted_mode
->crtc_vdisplay
- 1) |
4663 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4664 I915_WRITE(VBLANK(cpu_transcoder
),
4665 (adjusted_mode
->crtc_vblank_start
- 1) |
4666 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4667 I915_WRITE(VSYNC(cpu_transcoder
),
4668 (adjusted_mode
->crtc_vsync_start
- 1) |
4669 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4671 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4672 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4673 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4675 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4676 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4677 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4679 /* pipesrc controls the size that is scaled from, which should
4680 * always be the user's requested size.
4682 I915_WRITE(PIPESRC(pipe
),
4683 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4686 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4687 struct drm_display_mode
*mode
,
4688 struct drm_display_mode
*adjusted_mode
,
4690 struct drm_framebuffer
*fb
)
4692 struct drm_device
*dev
= crtc
->dev
;
4693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4694 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4695 int pipe
= intel_crtc
->pipe
;
4696 int plane
= intel_crtc
->plane
;
4697 int refclk
, num_connectors
= 0;
4698 intel_clock_t clock
, reduced_clock
;
4699 u32 dspcntr
, pipeconf
;
4700 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4701 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4702 struct intel_encoder
*encoder
;
4703 const intel_limit_t
*limit
;
4706 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4707 switch (encoder
->type
) {
4708 case INTEL_OUTPUT_LVDS
:
4711 case INTEL_OUTPUT_SDVO
:
4712 case INTEL_OUTPUT_HDMI
:
4714 if (encoder
->needs_tv_clock
)
4717 case INTEL_OUTPUT_TVOUT
:
4720 case INTEL_OUTPUT_DISPLAYPORT
:
4728 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4731 * Returns a set of divisors for the desired target clock with the given
4732 * refclk, or FALSE. The returned values represent the clock equation:
4733 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4735 limit
= intel_limit(crtc
, refclk
);
4736 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4739 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4743 /* Ensure that the cursor is valid for the new mode before changing... */
4744 intel_crtc_update_cursor(crtc
, true);
4746 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4748 * Ensure we match the reduced clock's P to the target clock.
4749 * If the clocks don't match, we can't switch the display clock
4750 * by using the FP0/FP1. In such case we will disable the LVDS
4751 * downclock feature.
4753 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4754 dev_priv
->lvds_downclock
,
4760 if (is_sdvo
&& is_tv
)
4761 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4764 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4765 has_reduced_clock
? &reduced_clock
: NULL
,
4767 else if (IS_VALLEYVIEW(dev
))
4768 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4769 has_reduced_clock
? &reduced_clock
: NULL
,
4772 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4773 has_reduced_clock
? &reduced_clock
: NULL
,
4776 /* setup pipeconf */
4777 pipeconf
= I915_READ(PIPECONF(pipe
));
4779 /* Set up the display plane register */
4780 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4783 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4785 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4787 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4788 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4791 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4796 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4798 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4801 /* default to 8bpc */
4802 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4804 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4805 pipeconf
|= PIPECONF_BPP_6
|
4806 PIPECONF_DITHER_EN
|
4807 PIPECONF_DITHER_TYPE_SP
;
4811 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4812 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4813 pipeconf
|= PIPECONF_BPP_6
|
4815 I965_PIPECONF_ACTIVE
;
4819 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4820 drm_mode_debug_printmodeline(mode
);
4822 if (HAS_PIPE_CXSR(dev
)) {
4823 if (intel_crtc
->lowfreq_avail
) {
4824 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4825 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4827 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4828 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4832 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4833 if (!IS_GEN2(dev
) &&
4834 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4835 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4837 pipeconf
|= PIPECONF_PROGRESSIVE
;
4839 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4841 /* pipesrc and dspsize control the size that is scaled from,
4842 * which should always be the user's requested size.
4844 I915_WRITE(DSPSIZE(plane
),
4845 ((mode
->vdisplay
- 1) << 16) |
4846 (mode
->hdisplay
- 1));
4847 I915_WRITE(DSPPOS(plane
), 0);
4849 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4850 POSTING_READ(PIPECONF(pipe
));
4851 intel_enable_pipe(dev_priv
, pipe
, false);
4853 intel_wait_for_vblank(dev
, pipe
);
4855 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4856 POSTING_READ(DSPCNTR(plane
));
4858 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4860 intel_update_watermarks(dev
);
4866 * Initialize reference clocks when the driver loads
4868 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4871 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4872 struct intel_encoder
*encoder
;
4874 bool has_lvds
= false;
4875 bool has_cpu_edp
= false;
4876 bool has_pch_edp
= false;
4877 bool has_panel
= false;
4878 bool has_ck505
= false;
4879 bool can_ssc
= false;
4881 /* We need to take the global config into account */
4882 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4884 switch (encoder
->type
) {
4885 case INTEL_OUTPUT_LVDS
:
4889 case INTEL_OUTPUT_EDP
:
4891 if (intel_encoder_is_pch_edp(&encoder
->base
))
4899 if (HAS_PCH_IBX(dev
)) {
4900 has_ck505
= dev_priv
->display_clock_mode
;
4901 can_ssc
= has_ck505
;
4907 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4908 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4911 /* Ironlake: try to setup display ref clock before DPLL
4912 * enabling. This is only under driver's control after
4913 * PCH B stepping, previous chipset stepping should be
4914 * ignoring this setting.
4916 temp
= I915_READ(PCH_DREF_CONTROL
);
4917 /* Always enable nonspread source */
4918 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4921 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4923 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4926 temp
&= ~DREF_SSC_SOURCE_MASK
;
4927 temp
|= DREF_SSC_SOURCE_ENABLE
;
4929 /* SSC must be turned on before enabling the CPU output */
4930 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4931 DRM_DEBUG_KMS("Using SSC on panel\n");
4932 temp
|= DREF_SSC1_ENABLE
;
4934 temp
&= ~DREF_SSC1_ENABLE
;
4936 /* Get SSC going before enabling the outputs */
4937 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4938 POSTING_READ(PCH_DREF_CONTROL
);
4941 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4943 /* Enable CPU source on CPU attached eDP */
4945 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4946 DRM_DEBUG_KMS("Using SSC on eDP\n");
4947 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4950 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4952 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4954 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4955 POSTING_READ(PCH_DREF_CONTROL
);
4958 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4960 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4962 /* Turn off CPU output */
4963 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4965 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4966 POSTING_READ(PCH_DREF_CONTROL
);
4969 /* Turn off the SSC source */
4970 temp
&= ~DREF_SSC_SOURCE_MASK
;
4971 temp
|= DREF_SSC_SOURCE_DISABLE
;
4974 temp
&= ~ DREF_SSC1_ENABLE
;
4976 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4977 POSTING_READ(PCH_DREF_CONTROL
);
4982 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4984 struct drm_device
*dev
= crtc
->dev
;
4985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4986 struct intel_encoder
*encoder
;
4987 struct intel_encoder
*edp_encoder
= NULL
;
4988 int num_connectors
= 0;
4989 bool is_lvds
= false;
4991 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4992 switch (encoder
->type
) {
4993 case INTEL_OUTPUT_LVDS
:
4996 case INTEL_OUTPUT_EDP
:
4997 edp_encoder
= encoder
;
5003 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5004 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5005 dev_priv
->lvds_ssc_freq
);
5006 return dev_priv
->lvds_ssc_freq
* 1000;
5012 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
5013 struct drm_display_mode
*adjusted_mode
,
5016 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5017 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5018 int pipe
= intel_crtc
->pipe
;
5021 val
= I915_READ(PIPECONF(pipe
));
5023 val
&= ~PIPE_BPC_MASK
;
5024 switch (intel_crtc
->bpp
) {
5038 /* Case prevented by intel_choose_pipe_bpp_dither. */
5042 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5044 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5046 val
&= ~PIPECONF_INTERLACE_MASK
;
5047 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5048 val
|= PIPECONF_INTERLACED_ILK
;
5050 val
|= PIPECONF_PROGRESSIVE
;
5052 I915_WRITE(PIPECONF(pipe
), val
);
5053 POSTING_READ(PIPECONF(pipe
));
5056 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
5057 struct drm_display_mode
*adjusted_mode
,
5060 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5061 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5062 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5065 val
= I915_READ(PIPECONF(cpu_transcoder
));
5067 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
5069 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5071 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
5072 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
5073 val
|= PIPECONF_INTERLACED_ILK
;
5075 val
|= PIPECONF_PROGRESSIVE
;
5077 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5078 POSTING_READ(PIPECONF(cpu_transcoder
));
5081 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5082 struct drm_display_mode
*adjusted_mode
,
5083 intel_clock_t
*clock
,
5084 bool *has_reduced_clock
,
5085 intel_clock_t
*reduced_clock
)
5087 struct drm_device
*dev
= crtc
->dev
;
5088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5089 struct intel_encoder
*intel_encoder
;
5091 const intel_limit_t
*limit
;
5092 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
5094 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5095 switch (intel_encoder
->type
) {
5096 case INTEL_OUTPUT_LVDS
:
5099 case INTEL_OUTPUT_SDVO
:
5100 case INTEL_OUTPUT_HDMI
:
5102 if (intel_encoder
->needs_tv_clock
)
5105 case INTEL_OUTPUT_TVOUT
:
5111 refclk
= ironlake_get_refclk(crtc
);
5114 * Returns a set of divisors for the desired target clock with the given
5115 * refclk, or FALSE. The returned values represent the clock equation:
5116 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5118 limit
= intel_limit(crtc
, refclk
);
5119 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5124 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5126 * Ensure we match the reduced clock's P to the target clock.
5127 * If the clocks don't match, we can't switch the display clock
5128 * by using the FP0/FP1. In such case we will disable the LVDS
5129 * downclock feature.
5131 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5132 dev_priv
->lvds_downclock
,
5138 if (is_sdvo
&& is_tv
)
5139 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5144 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5149 temp
= I915_READ(SOUTH_CHICKEN1
);
5150 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5153 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5154 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5156 temp
|= FDI_BC_BIFURCATION_SELECT
;
5157 DRM_DEBUG_KMS("enabling fdi C rx\n");
5158 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5159 POSTING_READ(SOUTH_CHICKEN1
);
5162 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5164 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5166 struct intel_crtc
*pipe_B_crtc
=
5167 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5169 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5170 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5171 if (intel_crtc
->fdi_lanes
> 4) {
5172 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5173 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5174 /* Clamp lanes to avoid programming the hw with bogus values. */
5175 intel_crtc
->fdi_lanes
= 4;
5180 if (dev_priv
->num_pipe
== 2)
5183 switch (intel_crtc
->pipe
) {
5187 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5188 intel_crtc
->fdi_lanes
> 2) {
5189 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5190 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5191 /* Clamp lanes to avoid programming the hw with bogus values. */
5192 intel_crtc
->fdi_lanes
= 2;
5197 if (intel_crtc
->fdi_lanes
> 2)
5198 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5200 cpt_enable_fdi_bc_bifurcation(dev
);
5204 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5205 if (intel_crtc
->fdi_lanes
> 2) {
5206 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5207 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5208 /* Clamp lanes to avoid programming the hw with bogus values. */
5209 intel_crtc
->fdi_lanes
= 2;
5214 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5218 cpt_enable_fdi_bc_bifurcation(dev
);
5226 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5227 struct drm_display_mode
*mode
,
5228 struct drm_display_mode
*adjusted_mode
)
5230 struct drm_device
*dev
= crtc
->dev
;
5231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5232 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5233 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5234 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5235 struct fdi_m_n m_n
= {0};
5236 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5237 bool is_dp
= false, is_cpu_edp
= false;
5239 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5240 switch (intel_encoder
->type
) {
5241 case INTEL_OUTPUT_DISPLAYPORT
:
5244 case INTEL_OUTPUT_EDP
:
5246 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5248 edp_encoder
= intel_encoder
;
5254 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5256 /* CPU eDP doesn't require FDI link, so just set DP M/N
5257 according to current link config */
5259 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5261 /* FDI is a binary signal running at ~2.7GHz, encoding
5262 * each output octet as 10 bits. The actual frequency
5263 * is stored as a divider into a 100MHz clock, and the
5264 * mode pixel clock is stored in units of 1KHz.
5265 * Hence the bw of each lane in terms of the mode signal
5268 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5271 /* [e]DP over FDI requires target mode clock instead of link clock. */
5273 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5275 target_clock
= mode
->clock
;
5277 target_clock
= adjusted_mode
->clock
;
5281 * Account for spread spectrum to avoid
5282 * oversubscribing the link. Max center spread
5283 * is 2.5%; use 5% for safety's sake.
5285 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
5286 lane
= bps
/ (link_bw
* 8) + 1;
5289 intel_crtc
->fdi_lanes
= lane
;
5291 if (pixel_multiplier
> 1)
5292 link_bw
*= pixel_multiplier
;
5293 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
5296 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5297 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5298 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5299 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5302 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5303 struct drm_display_mode
*adjusted_mode
,
5304 intel_clock_t
*clock
, u32 fp
)
5306 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5307 struct drm_device
*dev
= crtc
->dev
;
5308 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5309 struct intel_encoder
*intel_encoder
;
5311 int factor
, pixel_multiplier
, num_connectors
= 0;
5312 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5313 bool is_dp
= false, is_cpu_edp
= false;
5315 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5316 switch (intel_encoder
->type
) {
5317 case INTEL_OUTPUT_LVDS
:
5320 case INTEL_OUTPUT_SDVO
:
5321 case INTEL_OUTPUT_HDMI
:
5323 if (intel_encoder
->needs_tv_clock
)
5326 case INTEL_OUTPUT_TVOUT
:
5329 case INTEL_OUTPUT_DISPLAYPORT
:
5332 case INTEL_OUTPUT_EDP
:
5334 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5342 /* Enable autotuning of the PLL clock (if permissible) */
5345 if ((intel_panel_use_ssc(dev_priv
) &&
5346 dev_priv
->lvds_ssc_freq
== 100) ||
5347 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
5349 } else if (is_sdvo
&& is_tv
)
5352 if (clock
->m
< factor
* clock
->n
)
5358 dpll
|= DPLLB_MODE_LVDS
;
5360 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5362 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5363 if (pixel_multiplier
> 1) {
5364 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5366 dpll
|= DPLL_DVO_HIGH_SPEED
;
5368 if (is_dp
&& !is_cpu_edp
)
5369 dpll
|= DPLL_DVO_HIGH_SPEED
;
5371 /* compute bitmask from p1 value */
5372 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5374 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5376 switch (clock
->p2
) {
5378 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5381 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5384 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5387 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5391 if (is_sdvo
&& is_tv
)
5392 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5394 /* XXX: just matching BIOS for now */
5395 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5397 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5398 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5400 dpll
|= PLL_REF_INPUT_DREFCLK
;
5405 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5406 struct drm_display_mode
*mode
,
5407 struct drm_display_mode
*adjusted_mode
,
5409 struct drm_framebuffer
*fb
)
5411 struct drm_device
*dev
= crtc
->dev
;
5412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5413 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5414 int pipe
= intel_crtc
->pipe
;
5415 int plane
= intel_crtc
->plane
;
5416 int num_connectors
= 0;
5417 intel_clock_t clock
, reduced_clock
;
5418 u32 dpll
, fp
= 0, fp2
= 0;
5419 bool ok
, has_reduced_clock
= false;
5420 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5421 struct intel_encoder
*encoder
;
5424 bool dither
, fdi_config_ok
;
5426 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5427 switch (encoder
->type
) {
5428 case INTEL_OUTPUT_LVDS
:
5431 case INTEL_OUTPUT_DISPLAYPORT
:
5434 case INTEL_OUTPUT_EDP
:
5436 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5444 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5445 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5447 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5448 &has_reduced_clock
, &reduced_clock
);
5450 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5454 /* Ensure that the cursor is valid for the new mode before changing... */
5455 intel_crtc_update_cursor(crtc
, true);
5457 /* determine panel color depth */
5458 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5460 if (is_lvds
&& dev_priv
->lvds_dither
)
5463 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5464 if (has_reduced_clock
)
5465 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5468 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5470 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5471 drm_mode_debug_printmodeline(mode
);
5473 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5475 struct intel_pch_pll
*pll
;
5477 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5479 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5484 intel_put_pch_pll(intel_crtc
);
5486 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5487 * This is an exception to the general rule that mode_set doesn't turn
5491 temp
= I915_READ(PCH_LVDS
);
5492 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5493 if (HAS_PCH_CPT(dev
)) {
5494 temp
&= ~PORT_TRANS_SEL_MASK
;
5495 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5498 temp
|= LVDS_PIPEB_SELECT
;
5500 temp
&= ~LVDS_PIPEB_SELECT
;
5503 /* set the corresponsding LVDS_BORDER bit */
5504 temp
|= dev_priv
->lvds_border_bits
;
5505 /* Set the B0-B3 data pairs corresponding to whether we're going to
5506 * set the DPLLs for dual-channel mode or not.
5509 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5511 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5513 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5514 * appropriately here, but we need to look more thoroughly into how
5515 * panels behave in the two modes.
5517 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5518 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5519 temp
|= LVDS_HSYNC_POLARITY
;
5520 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5521 temp
|= LVDS_VSYNC_POLARITY
;
5522 I915_WRITE(PCH_LVDS
, temp
);
5525 if (is_dp
&& !is_cpu_edp
) {
5526 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5528 /* For non-DP output, clear any trans DP clock recovery setting.*/
5529 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5530 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5531 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5532 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5535 if (intel_crtc
->pch_pll
) {
5536 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5538 /* Wait for the clocks to stabilize. */
5539 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5542 /* The pixel multiplier can only be updated once the
5543 * DPLL is enabled and the clocks are stable.
5545 * So write it again.
5547 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5550 intel_crtc
->lowfreq_avail
= false;
5551 if (intel_crtc
->pch_pll
) {
5552 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5553 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5554 intel_crtc
->lowfreq_avail
= true;
5556 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5560 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5562 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5563 * ironlake_check_fdi_lanes. */
5564 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5566 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5569 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5571 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5573 intel_wait_for_vblank(dev
, pipe
);
5575 /* Set up the display plane register */
5576 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5577 POSTING_READ(DSPCNTR(plane
));
5579 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5581 intel_update_watermarks(dev
);
5583 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5585 return fdi_config_ok
? ret
: -EINVAL
;
5588 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5589 struct drm_display_mode
*mode
,
5590 struct drm_display_mode
*adjusted_mode
,
5592 struct drm_framebuffer
*fb
)
5594 struct drm_device
*dev
= crtc
->dev
;
5595 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5596 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5597 int pipe
= intel_crtc
->pipe
;
5598 int plane
= intel_crtc
->plane
;
5599 int num_connectors
= 0;
5600 intel_clock_t clock
, reduced_clock
;
5601 u32 dpll
= 0, fp
= 0, fp2
= 0;
5602 bool ok
, has_reduced_clock
= false;
5603 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5604 struct intel_encoder
*encoder
;
5609 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5610 switch (encoder
->type
) {
5611 case INTEL_OUTPUT_LVDS
:
5614 case INTEL_OUTPUT_DISPLAYPORT
:
5617 case INTEL_OUTPUT_EDP
:
5619 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5628 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5630 intel_crtc
->cpu_transcoder
= pipe
;
5632 /* We are not sure yet this won't happen. */
5633 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5634 INTEL_PCH_TYPE(dev
));
5636 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5637 num_connectors
, pipe_name(pipe
));
5639 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5640 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5642 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5644 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5647 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5648 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5652 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5657 /* Ensure that the cursor is valid for the new mode before changing... */
5658 intel_crtc_update_cursor(crtc
, true);
5660 /* determine panel color depth */
5661 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5663 if (is_lvds
&& dev_priv
->lvds_dither
)
5666 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5667 drm_mode_debug_printmodeline(mode
);
5669 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5670 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5671 if (has_reduced_clock
)
5672 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5675 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
,
5678 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5679 * own on pre-Haswell/LPT generation */
5681 struct intel_pch_pll
*pll
;
5683 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5685 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5690 intel_put_pch_pll(intel_crtc
);
5692 /* The LVDS pin pair needs to be on before the DPLLs are
5693 * enabled. This is an exception to the general rule that
5694 * mode_set doesn't turn things on.
5697 temp
= I915_READ(PCH_LVDS
);
5698 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5699 if (HAS_PCH_CPT(dev
)) {
5700 temp
&= ~PORT_TRANS_SEL_MASK
;
5701 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5704 temp
|= LVDS_PIPEB_SELECT
;
5706 temp
&= ~LVDS_PIPEB_SELECT
;
5709 /* set the corresponsding LVDS_BORDER bit */
5710 temp
|= dev_priv
->lvds_border_bits
;
5711 /* Set the B0-B3 data pairs corresponding to whether
5712 * we're going to set the DPLLs for dual-channel mode or
5716 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5718 temp
&= ~(LVDS_B0B3_POWER_UP
|
5719 LVDS_CLKB_POWER_UP
);
5721 /* It would be nice to set 24 vs 18-bit mode
5722 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5723 * look more thoroughly into how panels behave in the
5726 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5727 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5728 temp
|= LVDS_HSYNC_POLARITY
;
5729 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5730 temp
|= LVDS_VSYNC_POLARITY
;
5731 I915_WRITE(PCH_LVDS
, temp
);
5735 if (is_dp
&& !is_cpu_edp
) {
5736 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5738 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5739 /* For non-DP output, clear any trans DP clock recovery
5741 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5742 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5743 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5744 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5748 intel_crtc
->lowfreq_avail
= false;
5749 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5750 if (intel_crtc
->pch_pll
) {
5751 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5753 /* Wait for the clocks to stabilize. */
5754 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5757 /* The pixel multiplier can only be updated once the
5758 * DPLL is enabled and the clocks are stable.
5760 * So write it again.
5762 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5765 if (intel_crtc
->pch_pll
) {
5766 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5767 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5768 intel_crtc
->lowfreq_avail
= true;
5770 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5775 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5777 if (!is_dp
|| is_cpu_edp
)
5778 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5780 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5782 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5784 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5786 /* Set up the display plane register */
5787 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5788 POSTING_READ(DSPCNTR(plane
));
5790 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5792 intel_update_watermarks(dev
);
5794 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5799 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5800 struct drm_display_mode
*mode
,
5801 struct drm_display_mode
*adjusted_mode
,
5803 struct drm_framebuffer
*fb
)
5805 struct drm_device
*dev
= crtc
->dev
;
5806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5807 struct drm_encoder_helper_funcs
*encoder_funcs
;
5808 struct intel_encoder
*encoder
;
5809 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5810 int pipe
= intel_crtc
->pipe
;
5813 drm_vblank_pre_modeset(dev
, pipe
);
5815 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5817 drm_vblank_post_modeset(dev
, pipe
);
5822 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5823 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5824 encoder
->base
.base
.id
,
5825 drm_get_encoder_name(&encoder
->base
),
5826 mode
->base
.id
, mode
->name
);
5827 encoder_funcs
= encoder
->base
.helper_private
;
5828 encoder_funcs
->mode_set(&encoder
->base
, mode
, adjusted_mode
);
5834 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5835 int reg_eldv
, uint32_t bits_eldv
,
5836 int reg_elda
, uint32_t bits_elda
,
5839 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5840 uint8_t *eld
= connector
->eld
;
5843 i
= I915_READ(reg_eldv
);
5852 i
= I915_READ(reg_elda
);
5854 I915_WRITE(reg_elda
, i
);
5856 for (i
= 0; i
< eld
[2]; i
++)
5857 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5863 static void g4x_write_eld(struct drm_connector
*connector
,
5864 struct drm_crtc
*crtc
)
5866 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5867 uint8_t *eld
= connector
->eld
;
5872 i
= I915_READ(G4X_AUD_VID_DID
);
5874 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5875 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5877 eldv
= G4X_ELDV_DEVCTG
;
5879 if (intel_eld_uptodate(connector
,
5880 G4X_AUD_CNTL_ST
, eldv
,
5881 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5882 G4X_HDMIW_HDMIEDID
))
5885 i
= I915_READ(G4X_AUD_CNTL_ST
);
5886 i
&= ~(eldv
| G4X_ELD_ADDR
);
5887 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5888 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5893 len
= min_t(uint8_t, eld
[2], len
);
5894 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5895 for (i
= 0; i
< len
; i
++)
5896 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5898 i
= I915_READ(G4X_AUD_CNTL_ST
);
5900 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5903 static void haswell_write_eld(struct drm_connector
*connector
,
5904 struct drm_crtc
*crtc
)
5906 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5907 uint8_t *eld
= connector
->eld
;
5908 struct drm_device
*dev
= crtc
->dev
;
5912 int pipe
= to_intel_crtc(crtc
)->pipe
;
5915 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5916 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5917 int aud_config
= HSW_AUD_CFG(pipe
);
5918 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5921 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5923 /* Audio output enable */
5924 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5925 tmp
= I915_READ(aud_cntrl_st2
);
5926 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5927 I915_WRITE(aud_cntrl_st2
, tmp
);
5929 /* Wait for 1 vertical blank */
5930 intel_wait_for_vblank(dev
, pipe
);
5932 /* Set ELD valid state */
5933 tmp
= I915_READ(aud_cntrl_st2
);
5934 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5935 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5936 I915_WRITE(aud_cntrl_st2
, tmp
);
5937 tmp
= I915_READ(aud_cntrl_st2
);
5938 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5940 /* Enable HDMI mode */
5941 tmp
= I915_READ(aud_config
);
5942 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5943 /* clear N_programing_enable and N_value_index */
5944 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5945 I915_WRITE(aud_config
, tmp
);
5947 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5949 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5951 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5952 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5953 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5954 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5956 I915_WRITE(aud_config
, 0);
5958 if (intel_eld_uptodate(connector
,
5959 aud_cntrl_st2
, eldv
,
5960 aud_cntl_st
, IBX_ELD_ADDRESS
,
5964 i
= I915_READ(aud_cntrl_st2
);
5966 I915_WRITE(aud_cntrl_st2
, i
);
5971 i
= I915_READ(aud_cntl_st
);
5972 i
&= ~IBX_ELD_ADDRESS
;
5973 I915_WRITE(aud_cntl_st
, i
);
5974 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5975 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5977 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5978 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5979 for (i
= 0; i
< len
; i
++)
5980 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5982 i
= I915_READ(aud_cntrl_st2
);
5984 I915_WRITE(aud_cntrl_st2
, i
);
5988 static void ironlake_write_eld(struct drm_connector
*connector
,
5989 struct drm_crtc
*crtc
)
5991 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5992 uint8_t *eld
= connector
->eld
;
6000 int pipe
= to_intel_crtc(crtc
)->pipe
;
6002 if (HAS_PCH_IBX(connector
->dev
)) {
6003 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6004 aud_config
= IBX_AUD_CFG(pipe
);
6005 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6006 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6008 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6009 aud_config
= CPT_AUD_CFG(pipe
);
6010 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6011 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6014 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6016 i
= I915_READ(aud_cntl_st
);
6017 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6019 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6020 /* operate blindly on all ports */
6021 eldv
= IBX_ELD_VALIDB
;
6022 eldv
|= IBX_ELD_VALIDB
<< 4;
6023 eldv
|= IBX_ELD_VALIDB
<< 8;
6025 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6026 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6029 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6030 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6031 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6032 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6034 I915_WRITE(aud_config
, 0);
6036 if (intel_eld_uptodate(connector
,
6037 aud_cntrl_st2
, eldv
,
6038 aud_cntl_st
, IBX_ELD_ADDRESS
,
6042 i
= I915_READ(aud_cntrl_st2
);
6044 I915_WRITE(aud_cntrl_st2
, i
);
6049 i
= I915_READ(aud_cntl_st
);
6050 i
&= ~IBX_ELD_ADDRESS
;
6051 I915_WRITE(aud_cntl_st
, i
);
6053 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6054 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6055 for (i
= 0; i
< len
; i
++)
6056 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6058 i
= I915_READ(aud_cntrl_st2
);
6060 I915_WRITE(aud_cntrl_st2
, i
);
6063 void intel_write_eld(struct drm_encoder
*encoder
,
6064 struct drm_display_mode
*mode
)
6066 struct drm_crtc
*crtc
= encoder
->crtc
;
6067 struct drm_connector
*connector
;
6068 struct drm_device
*dev
= encoder
->dev
;
6069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6071 connector
= drm_select_eld(encoder
, mode
);
6075 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6077 drm_get_connector_name(connector
),
6078 connector
->encoder
->base
.id
,
6079 drm_get_encoder_name(connector
->encoder
));
6081 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6083 if (dev_priv
->display
.write_eld
)
6084 dev_priv
->display
.write_eld(connector
, crtc
);
6087 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6088 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6090 struct drm_device
*dev
= crtc
->dev
;
6091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6092 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6093 int palreg
= PALETTE(intel_crtc
->pipe
);
6096 /* The clocks have to be on to load the palette. */
6097 if (!crtc
->enabled
|| !intel_crtc
->active
)
6100 /* use legacy palette for Ironlake */
6101 if (HAS_PCH_SPLIT(dev
))
6102 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6104 for (i
= 0; i
< 256; i
++) {
6105 I915_WRITE(palreg
+ 4 * i
,
6106 (intel_crtc
->lut_r
[i
] << 16) |
6107 (intel_crtc
->lut_g
[i
] << 8) |
6108 intel_crtc
->lut_b
[i
]);
6112 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6114 struct drm_device
*dev
= crtc
->dev
;
6115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6116 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6117 bool visible
= base
!= 0;
6120 if (intel_crtc
->cursor_visible
== visible
)
6123 cntl
= I915_READ(_CURACNTR
);
6125 /* On these chipsets we can only modify the base whilst
6126 * the cursor is disabled.
6128 I915_WRITE(_CURABASE
, base
);
6130 cntl
&= ~(CURSOR_FORMAT_MASK
);
6131 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6132 cntl
|= CURSOR_ENABLE
|
6133 CURSOR_GAMMA_ENABLE
|
6136 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6137 I915_WRITE(_CURACNTR
, cntl
);
6139 intel_crtc
->cursor_visible
= visible
;
6142 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6144 struct drm_device
*dev
= crtc
->dev
;
6145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6146 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6147 int pipe
= intel_crtc
->pipe
;
6148 bool visible
= base
!= 0;
6150 if (intel_crtc
->cursor_visible
!= visible
) {
6151 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6153 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6154 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6155 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6157 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6158 cntl
|= CURSOR_MODE_DISABLE
;
6160 I915_WRITE(CURCNTR(pipe
), cntl
);
6162 intel_crtc
->cursor_visible
= visible
;
6164 /* and commit changes on next vblank */
6165 I915_WRITE(CURBASE(pipe
), base
);
6168 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6170 struct drm_device
*dev
= crtc
->dev
;
6171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6173 int pipe
= intel_crtc
->pipe
;
6174 bool visible
= base
!= 0;
6176 if (intel_crtc
->cursor_visible
!= visible
) {
6177 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6179 cntl
&= ~CURSOR_MODE
;
6180 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6182 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6183 cntl
|= CURSOR_MODE_DISABLE
;
6185 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6187 intel_crtc
->cursor_visible
= visible
;
6189 /* and commit changes on next vblank */
6190 I915_WRITE(CURBASE_IVB(pipe
), base
);
6193 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6194 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6197 struct drm_device
*dev
= crtc
->dev
;
6198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6199 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6200 int pipe
= intel_crtc
->pipe
;
6201 int x
= intel_crtc
->cursor_x
;
6202 int y
= intel_crtc
->cursor_y
;
6208 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6209 base
= intel_crtc
->cursor_addr
;
6210 if (x
> (int) crtc
->fb
->width
)
6213 if (y
> (int) crtc
->fb
->height
)
6219 if (x
+ intel_crtc
->cursor_width
< 0)
6222 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6225 pos
|= x
<< CURSOR_X_SHIFT
;
6228 if (y
+ intel_crtc
->cursor_height
< 0)
6231 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6234 pos
|= y
<< CURSOR_Y_SHIFT
;
6236 visible
= base
!= 0;
6237 if (!visible
&& !intel_crtc
->cursor_visible
)
6240 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6241 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6242 ivb_update_cursor(crtc
, base
);
6244 I915_WRITE(CURPOS(pipe
), pos
);
6245 if (IS_845G(dev
) || IS_I865G(dev
))
6246 i845_update_cursor(crtc
, base
);
6248 i9xx_update_cursor(crtc
, base
);
6252 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6253 struct drm_file
*file
,
6255 uint32_t width
, uint32_t height
)
6257 struct drm_device
*dev
= crtc
->dev
;
6258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6259 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6260 struct drm_i915_gem_object
*obj
;
6264 /* if we want to turn off the cursor ignore width and height */
6266 DRM_DEBUG_KMS("cursor off\n");
6269 mutex_lock(&dev
->struct_mutex
);
6273 /* Currently we only support 64x64 cursors */
6274 if (width
!= 64 || height
!= 64) {
6275 DRM_ERROR("we currently only support 64x64 cursors\n");
6279 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6280 if (&obj
->base
== NULL
)
6283 if (obj
->base
.size
< width
* height
* 4) {
6284 DRM_ERROR("buffer is to small\n");
6289 /* we only need to pin inside GTT if cursor is non-phy */
6290 mutex_lock(&dev
->struct_mutex
);
6291 if (!dev_priv
->info
->cursor_needs_physical
) {
6292 if (obj
->tiling_mode
) {
6293 DRM_ERROR("cursor cannot be tiled\n");
6298 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6300 DRM_ERROR("failed to move cursor bo into the GTT\n");
6304 ret
= i915_gem_object_put_fence(obj
);
6306 DRM_ERROR("failed to release fence for cursor");
6310 addr
= obj
->gtt_offset
;
6312 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6313 ret
= i915_gem_attach_phys_object(dev
, obj
,
6314 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6317 DRM_ERROR("failed to attach phys object\n");
6320 addr
= obj
->phys_obj
->handle
->busaddr
;
6324 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6327 if (intel_crtc
->cursor_bo
) {
6328 if (dev_priv
->info
->cursor_needs_physical
) {
6329 if (intel_crtc
->cursor_bo
!= obj
)
6330 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6332 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6333 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6336 mutex_unlock(&dev
->struct_mutex
);
6338 intel_crtc
->cursor_addr
= addr
;
6339 intel_crtc
->cursor_bo
= obj
;
6340 intel_crtc
->cursor_width
= width
;
6341 intel_crtc
->cursor_height
= height
;
6343 intel_crtc_update_cursor(crtc
, true);
6347 i915_gem_object_unpin(obj
);
6349 mutex_unlock(&dev
->struct_mutex
);
6351 drm_gem_object_unreference_unlocked(&obj
->base
);
6355 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6357 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6359 intel_crtc
->cursor_x
= x
;
6360 intel_crtc
->cursor_y
= y
;
6362 intel_crtc_update_cursor(crtc
, true);
6367 /** Sets the color ramps on behalf of RandR */
6368 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6369 u16 blue
, int regno
)
6371 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6373 intel_crtc
->lut_r
[regno
] = red
>> 8;
6374 intel_crtc
->lut_g
[regno
] = green
>> 8;
6375 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6378 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6379 u16
*blue
, int regno
)
6381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6383 *red
= intel_crtc
->lut_r
[regno
] << 8;
6384 *green
= intel_crtc
->lut_g
[regno
] << 8;
6385 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6388 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6389 u16
*blue
, uint32_t start
, uint32_t size
)
6391 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6394 for (i
= start
; i
< end
; i
++) {
6395 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6396 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6397 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6400 intel_crtc_load_lut(crtc
);
6404 * Get a pipe with a simple mode set on it for doing load-based monitor
6407 * It will be up to the load-detect code to adjust the pipe as appropriate for
6408 * its requirements. The pipe will be connected to no other encoders.
6410 * Currently this code will only succeed if there is a pipe with no encoders
6411 * configured for it. In the future, it could choose to temporarily disable
6412 * some outputs to free up a pipe for its use.
6414 * \return crtc, or NULL if no pipes are available.
6417 /* VESA 640x480x72Hz mode to set on the pipe */
6418 static struct drm_display_mode load_detect_mode
= {
6419 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6420 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6423 static struct drm_framebuffer
*
6424 intel_framebuffer_create(struct drm_device
*dev
,
6425 struct drm_mode_fb_cmd2
*mode_cmd
,
6426 struct drm_i915_gem_object
*obj
)
6428 struct intel_framebuffer
*intel_fb
;
6431 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6433 drm_gem_object_unreference_unlocked(&obj
->base
);
6434 return ERR_PTR(-ENOMEM
);
6437 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6439 drm_gem_object_unreference_unlocked(&obj
->base
);
6441 return ERR_PTR(ret
);
6444 return &intel_fb
->base
;
6448 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6450 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6451 return ALIGN(pitch
, 64);
6455 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6457 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6458 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6461 static struct drm_framebuffer
*
6462 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6463 struct drm_display_mode
*mode
,
6466 struct drm_i915_gem_object
*obj
;
6467 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
6469 obj
= i915_gem_alloc_object(dev
,
6470 intel_framebuffer_size_for_mode(mode
, bpp
));
6472 return ERR_PTR(-ENOMEM
);
6474 mode_cmd
.width
= mode
->hdisplay
;
6475 mode_cmd
.height
= mode
->vdisplay
;
6476 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6478 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6480 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6483 static struct drm_framebuffer
*
6484 mode_fits_in_fbdev(struct drm_device
*dev
,
6485 struct drm_display_mode
*mode
)
6487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6488 struct drm_i915_gem_object
*obj
;
6489 struct drm_framebuffer
*fb
;
6491 if (dev_priv
->fbdev
== NULL
)
6494 obj
= dev_priv
->fbdev
->ifb
.obj
;
6498 fb
= &dev_priv
->fbdev
->ifb
.base
;
6499 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6500 fb
->bits_per_pixel
))
6503 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6509 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6510 struct drm_display_mode
*mode
,
6511 struct intel_load_detect_pipe
*old
)
6513 struct intel_crtc
*intel_crtc
;
6514 struct intel_encoder
*intel_encoder
=
6515 intel_attached_encoder(connector
);
6516 struct drm_crtc
*possible_crtc
;
6517 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6518 struct drm_crtc
*crtc
= NULL
;
6519 struct drm_device
*dev
= encoder
->dev
;
6520 struct drm_framebuffer
*fb
;
6523 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6524 connector
->base
.id
, drm_get_connector_name(connector
),
6525 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6528 * Algorithm gets a little messy:
6530 * - if the connector already has an assigned crtc, use it (but make
6531 * sure it's on first)
6533 * - try to find the first unused crtc that can drive this connector,
6534 * and use that if we find one
6537 /* See if we already have a CRTC for this connector */
6538 if (encoder
->crtc
) {
6539 crtc
= encoder
->crtc
;
6541 old
->dpms_mode
= connector
->dpms
;
6542 old
->load_detect_temp
= false;
6544 /* Make sure the crtc and connector are running */
6545 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6546 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6551 /* Find an unused one (if possible) */
6552 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6554 if (!(encoder
->possible_crtcs
& (1 << i
)))
6556 if (!possible_crtc
->enabled
) {
6557 crtc
= possible_crtc
;
6563 * If we didn't find an unused CRTC, don't use any.
6566 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6570 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6571 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6573 intel_crtc
= to_intel_crtc(crtc
);
6574 old
->dpms_mode
= connector
->dpms
;
6575 old
->load_detect_temp
= true;
6576 old
->release_fb
= NULL
;
6579 mode
= &load_detect_mode
;
6581 /* We need a framebuffer large enough to accommodate all accesses
6582 * that the plane may generate whilst we perform load detection.
6583 * We can not rely on the fbcon either being present (we get called
6584 * during its initialisation to detect all boot displays, or it may
6585 * not even exist) or that it is large enough to satisfy the
6588 fb
= mode_fits_in_fbdev(dev
, mode
);
6590 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6591 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6592 old
->release_fb
= fb
;
6594 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6596 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6600 if (!intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6601 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6602 if (old
->release_fb
)
6603 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6607 /* let the connector get through one full cycle before testing */
6608 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6612 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6613 struct intel_load_detect_pipe
*old
)
6615 struct intel_encoder
*intel_encoder
=
6616 intel_attached_encoder(connector
);
6617 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6620 connector
->base
.id
, drm_get_connector_name(connector
),
6621 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6623 if (old
->load_detect_temp
) {
6624 struct drm_crtc
*crtc
= encoder
->crtc
;
6626 to_intel_connector(connector
)->new_encoder
= NULL
;
6627 intel_encoder
->new_crtc
= NULL
;
6628 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6630 if (old
->release_fb
)
6631 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6636 /* Switch crtc and encoder back off if necessary */
6637 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6638 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6641 /* Returns the clock of the currently programmed mode of the given pipe. */
6642 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6645 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6646 int pipe
= intel_crtc
->pipe
;
6647 u32 dpll
= I915_READ(DPLL(pipe
));
6649 intel_clock_t clock
;
6651 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6652 fp
= I915_READ(FP0(pipe
));
6654 fp
= I915_READ(FP1(pipe
));
6656 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6657 if (IS_PINEVIEW(dev
)) {
6658 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6659 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6661 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6662 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6665 if (!IS_GEN2(dev
)) {
6666 if (IS_PINEVIEW(dev
))
6667 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6668 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6670 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6671 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6673 switch (dpll
& DPLL_MODE_MASK
) {
6674 case DPLLB_MODE_DAC_SERIAL
:
6675 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6678 case DPLLB_MODE_LVDS
:
6679 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6683 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6684 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6688 /* XXX: Handle the 100Mhz refclk */
6689 intel_clock(dev
, 96000, &clock
);
6691 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6694 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6695 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6698 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6699 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6700 /* XXX: might not be 66MHz */
6701 intel_clock(dev
, 66000, &clock
);
6703 intel_clock(dev
, 48000, &clock
);
6705 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6708 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6709 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6711 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6716 intel_clock(dev
, 48000, &clock
);
6720 /* XXX: It would be nice to validate the clocks, but we can't reuse
6721 * i830PllIsValid() because it relies on the xf86_config connector
6722 * configuration being accurate, which it isn't necessarily.
6728 /** Returns the currently programmed mode of the given pipe. */
6729 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6730 struct drm_crtc
*crtc
)
6732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6734 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6735 struct drm_display_mode
*mode
;
6736 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6737 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6738 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6739 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6741 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6745 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6746 mode
->hdisplay
= (htot
& 0xffff) + 1;
6747 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6748 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6749 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6750 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6751 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6752 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6753 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6755 drm_mode_set_name(mode
);
6760 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6762 struct drm_device
*dev
= crtc
->dev
;
6763 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6764 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6765 int pipe
= intel_crtc
->pipe
;
6766 int dpll_reg
= DPLL(pipe
);
6769 if (HAS_PCH_SPLIT(dev
))
6772 if (!dev_priv
->lvds_downclock_avail
)
6775 dpll
= I915_READ(dpll_reg
);
6776 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6777 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6779 assert_panel_unlocked(dev_priv
, pipe
);
6781 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6782 I915_WRITE(dpll_reg
, dpll
);
6783 intel_wait_for_vblank(dev
, pipe
);
6785 dpll
= I915_READ(dpll_reg
);
6786 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6787 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6791 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6793 struct drm_device
*dev
= crtc
->dev
;
6794 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6795 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6797 if (HAS_PCH_SPLIT(dev
))
6800 if (!dev_priv
->lvds_downclock_avail
)
6804 * Since this is called by a timer, we should never get here in
6807 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6808 int pipe
= intel_crtc
->pipe
;
6809 int dpll_reg
= DPLL(pipe
);
6812 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6814 assert_panel_unlocked(dev_priv
, pipe
);
6816 dpll
= I915_READ(dpll_reg
);
6817 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6818 I915_WRITE(dpll_reg
, dpll
);
6819 intel_wait_for_vblank(dev
, pipe
);
6820 dpll
= I915_READ(dpll_reg
);
6821 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6822 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6827 void intel_mark_busy(struct drm_device
*dev
)
6829 i915_update_gfx_val(dev
->dev_private
);
6832 void intel_mark_idle(struct drm_device
*dev
)
6836 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6838 struct drm_device
*dev
= obj
->base
.dev
;
6839 struct drm_crtc
*crtc
;
6841 if (!i915_powersave
)
6844 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6848 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6849 intel_increase_pllclock(crtc
);
6853 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6855 struct drm_device
*dev
= obj
->base
.dev
;
6856 struct drm_crtc
*crtc
;
6858 if (!i915_powersave
)
6861 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6865 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6866 intel_decrease_pllclock(crtc
);
6870 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6873 struct drm_device
*dev
= crtc
->dev
;
6874 struct intel_unpin_work
*work
;
6875 unsigned long flags
;
6877 spin_lock_irqsave(&dev
->event_lock
, flags
);
6878 work
= intel_crtc
->unpin_work
;
6879 intel_crtc
->unpin_work
= NULL
;
6880 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6883 cancel_work_sync(&work
->work
);
6887 drm_crtc_cleanup(crtc
);
6892 static void intel_unpin_work_fn(struct work_struct
*__work
)
6894 struct intel_unpin_work
*work
=
6895 container_of(__work
, struct intel_unpin_work
, work
);
6896 struct drm_device
*dev
= work
->crtc
->dev
;
6898 mutex_lock(&dev
->struct_mutex
);
6899 intel_unpin_fb_obj(work
->old_fb_obj
);
6900 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6901 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6903 intel_update_fbc(dev
);
6904 mutex_unlock(&dev
->struct_mutex
);
6906 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
6907 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
6912 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6913 struct drm_crtc
*crtc
)
6915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6917 struct intel_unpin_work
*work
;
6918 struct drm_i915_gem_object
*obj
;
6919 struct drm_pending_vblank_event
*e
;
6920 struct timeval tvbl
;
6921 unsigned long flags
;
6923 /* Ignore early vblank irqs */
6924 if (intel_crtc
== NULL
)
6927 spin_lock_irqsave(&dev
->event_lock
, flags
);
6928 work
= intel_crtc
->unpin_work
;
6929 if (work
== NULL
|| !work
->pending
) {
6930 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6934 intel_crtc
->unpin_work
= NULL
;
6938 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6940 e
->event
.tv_sec
= tvbl
.tv_sec
;
6941 e
->event
.tv_usec
= tvbl
.tv_usec
;
6943 list_add_tail(&e
->base
.link
,
6944 &e
->base
.file_priv
->event_list
);
6945 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6948 drm_vblank_put(dev
, intel_crtc
->pipe
);
6950 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6952 obj
= work
->old_fb_obj
;
6954 atomic_clear_mask(1 << intel_crtc
->plane
,
6955 &obj
->pending_flip
.counter
);
6956 wake_up(&dev_priv
->pending_flip_queue
);
6958 queue_work(dev_priv
->wq
, &work
->work
);
6960 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6963 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6965 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6966 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6968 do_intel_finish_page_flip(dev
, crtc
);
6971 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6973 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6974 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6976 do_intel_finish_page_flip(dev
, crtc
);
6979 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6981 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6982 struct intel_crtc
*intel_crtc
=
6983 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6984 unsigned long flags
;
6986 spin_lock_irqsave(&dev
->event_lock
, flags
);
6987 if (intel_crtc
->unpin_work
) {
6988 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6989 DRM_ERROR("Prepared flip multiple times\n");
6991 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6993 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6996 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6997 struct drm_crtc
*crtc
,
6998 struct drm_framebuffer
*fb
,
6999 struct drm_i915_gem_object
*obj
)
7001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7002 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7004 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7007 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7011 ret
= intel_ring_begin(ring
, 6);
7015 /* Can't queue multiple flips, so wait for the previous
7016 * one to finish before executing the next.
7018 if (intel_crtc
->plane
)
7019 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7021 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7022 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7023 intel_ring_emit(ring
, MI_NOOP
);
7024 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7025 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7026 intel_ring_emit(ring
, fb
->pitches
[0]);
7027 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7028 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7029 intel_ring_advance(ring
);
7033 intel_unpin_fb_obj(obj
);
7038 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7039 struct drm_crtc
*crtc
,
7040 struct drm_framebuffer
*fb
,
7041 struct drm_i915_gem_object
*obj
)
7043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7044 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7046 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7049 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7053 ret
= intel_ring_begin(ring
, 6);
7057 if (intel_crtc
->plane
)
7058 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7060 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7061 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7062 intel_ring_emit(ring
, MI_NOOP
);
7063 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7064 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7065 intel_ring_emit(ring
, fb
->pitches
[0]);
7066 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7067 intel_ring_emit(ring
, MI_NOOP
);
7069 intel_ring_advance(ring
);
7073 intel_unpin_fb_obj(obj
);
7078 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7079 struct drm_crtc
*crtc
,
7080 struct drm_framebuffer
*fb
,
7081 struct drm_i915_gem_object
*obj
)
7083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7084 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7085 uint32_t pf
, pipesrc
;
7086 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7089 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7093 ret
= intel_ring_begin(ring
, 4);
7097 /* i965+ uses the linear or tiled offsets from the
7098 * Display Registers (which do not change across a page-flip)
7099 * so we need only reprogram the base address.
7101 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7102 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7103 intel_ring_emit(ring
, fb
->pitches
[0]);
7104 intel_ring_emit(ring
,
7105 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
7108 /* XXX Enabling the panel-fitter across page-flip is so far
7109 * untested on non-native modes, so ignore it for now.
7110 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7113 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7114 intel_ring_emit(ring
, pf
| pipesrc
);
7115 intel_ring_advance(ring
);
7119 intel_unpin_fb_obj(obj
);
7124 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7125 struct drm_crtc
*crtc
,
7126 struct drm_framebuffer
*fb
,
7127 struct drm_i915_gem_object
*obj
)
7129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7130 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7131 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7132 uint32_t pf
, pipesrc
;
7135 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7139 ret
= intel_ring_begin(ring
, 4);
7143 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7144 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7145 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7146 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7148 /* Contrary to the suggestions in the documentation,
7149 * "Enable Panel Fitter" does not seem to be required when page
7150 * flipping with a non-native mode, and worse causes a normal
7152 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7155 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7156 intel_ring_emit(ring
, pf
| pipesrc
);
7157 intel_ring_advance(ring
);
7161 intel_unpin_fb_obj(obj
);
7167 * On gen7 we currently use the blit ring because (in early silicon at least)
7168 * the render ring doesn't give us interrpts for page flip completion, which
7169 * means clients will hang after the first flip is queued. Fortunately the
7170 * blit ring generates interrupts properly, so use it instead.
7172 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7173 struct drm_crtc
*crtc
,
7174 struct drm_framebuffer
*fb
,
7175 struct drm_i915_gem_object
*obj
)
7177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7178 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7179 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7180 uint32_t plane_bit
= 0;
7183 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7187 switch(intel_crtc
->plane
) {
7189 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7192 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7195 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7198 WARN_ONCE(1, "unknown plane in flip command\n");
7203 ret
= intel_ring_begin(ring
, 4);
7207 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7208 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7209 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7210 intel_ring_emit(ring
, (MI_NOOP
));
7211 intel_ring_advance(ring
);
7215 intel_unpin_fb_obj(obj
);
7220 static int intel_default_queue_flip(struct drm_device
*dev
,
7221 struct drm_crtc
*crtc
,
7222 struct drm_framebuffer
*fb
,
7223 struct drm_i915_gem_object
*obj
)
7228 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7229 struct drm_framebuffer
*fb
,
7230 struct drm_pending_vblank_event
*event
)
7232 struct drm_device
*dev
= crtc
->dev
;
7233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7234 struct intel_framebuffer
*intel_fb
;
7235 struct drm_i915_gem_object
*obj
;
7236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7237 struct intel_unpin_work
*work
;
7238 unsigned long flags
;
7241 /* Can't change pixel format via MI display flips. */
7242 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7246 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7247 * Note that pitch changes could also affect these register.
7249 if (INTEL_INFO(dev
)->gen
> 3 &&
7250 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7251 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7254 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7258 work
->event
= event
;
7260 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7261 work
->old_fb_obj
= intel_fb
->obj
;
7262 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7264 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7268 /* We borrow the event spin lock for protecting unpin_work */
7269 spin_lock_irqsave(&dev
->event_lock
, flags
);
7270 if (intel_crtc
->unpin_work
) {
7271 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7273 drm_vblank_put(dev
, intel_crtc
->pipe
);
7275 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7278 intel_crtc
->unpin_work
= work
;
7279 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7281 intel_fb
= to_intel_framebuffer(fb
);
7282 obj
= intel_fb
->obj
;
7284 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
7285 flush_workqueue(dev_priv
->wq
);
7287 ret
= i915_mutex_lock_interruptible(dev
);
7291 /* Reference the objects for the scheduled work. */
7292 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7293 drm_gem_object_reference(&obj
->base
);
7297 work
->pending_flip_obj
= obj
;
7299 work
->enable_stall_check
= true;
7301 /* Block clients from rendering to the new back buffer until
7302 * the flip occurs and the object is no longer visible.
7304 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7305 atomic_inc(&intel_crtc
->unpin_work_count
);
7307 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7309 goto cleanup_pending
;
7311 intel_disable_fbc(dev
);
7312 intel_mark_fb_busy(obj
);
7313 mutex_unlock(&dev
->struct_mutex
);
7315 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7320 atomic_dec(&intel_crtc
->unpin_work_count
);
7321 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7322 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7323 drm_gem_object_unreference(&obj
->base
);
7324 mutex_unlock(&dev
->struct_mutex
);
7327 spin_lock_irqsave(&dev
->event_lock
, flags
);
7328 intel_crtc
->unpin_work
= NULL
;
7329 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7331 drm_vblank_put(dev
, intel_crtc
->pipe
);
7338 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7339 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7340 .load_lut
= intel_crtc_load_lut
,
7341 .disable
= intel_crtc_noop
,
7344 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7346 struct intel_encoder
*other_encoder
;
7347 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7352 list_for_each_entry(other_encoder
,
7353 &crtc
->dev
->mode_config
.encoder_list
,
7356 if (&other_encoder
->new_crtc
->base
!= crtc
||
7357 encoder
== other_encoder
)
7366 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7367 struct drm_crtc
*crtc
)
7369 struct drm_device
*dev
;
7370 struct drm_crtc
*tmp
;
7373 WARN(!crtc
, "checking null crtc?\n");
7377 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7383 if (encoder
->possible_crtcs
& crtc_mask
)
7389 * intel_modeset_update_staged_output_state
7391 * Updates the staged output configuration state, e.g. after we've read out the
7394 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7396 struct intel_encoder
*encoder
;
7397 struct intel_connector
*connector
;
7399 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7401 connector
->new_encoder
=
7402 to_intel_encoder(connector
->base
.encoder
);
7405 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7408 to_intel_crtc(encoder
->base
.crtc
);
7413 * intel_modeset_commit_output_state
7415 * This function copies the stage display pipe configuration to the real one.
7417 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7419 struct intel_encoder
*encoder
;
7420 struct intel_connector
*connector
;
7422 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7424 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7427 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7429 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7433 static struct drm_display_mode
*
7434 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7435 struct drm_display_mode
*mode
)
7437 struct drm_device
*dev
= crtc
->dev
;
7438 struct drm_display_mode
*adjusted_mode
;
7439 struct drm_encoder_helper_funcs
*encoder_funcs
;
7440 struct intel_encoder
*encoder
;
7442 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7444 return ERR_PTR(-ENOMEM
);
7446 /* Pass our mode to the connectors and the CRTC to give them a chance to
7447 * adjust it according to limitations or connector properties, and also
7448 * a chance to reject the mode entirely.
7450 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7453 if (&encoder
->new_crtc
->base
!= crtc
)
7455 encoder_funcs
= encoder
->base
.helper_private
;
7456 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7458 DRM_DEBUG_KMS("Encoder fixup failed\n");
7463 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7464 DRM_DEBUG_KMS("CRTC fixup failed\n");
7467 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7469 return adjusted_mode
;
7471 drm_mode_destroy(dev
, adjusted_mode
);
7472 return ERR_PTR(-EINVAL
);
7475 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7476 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7478 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7479 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7481 struct intel_crtc
*intel_crtc
;
7482 struct drm_device
*dev
= crtc
->dev
;
7483 struct intel_encoder
*encoder
;
7484 struct intel_connector
*connector
;
7485 struct drm_crtc
*tmp_crtc
;
7487 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7489 /* Check which crtcs have changed outputs connected to them, these need
7490 * to be part of the prepare_pipes mask. We don't (yet) support global
7491 * modeset across multiple crtcs, so modeset_pipes will only have one
7492 * bit set at most. */
7493 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7495 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7498 if (connector
->base
.encoder
) {
7499 tmp_crtc
= connector
->base
.encoder
->crtc
;
7501 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7504 if (connector
->new_encoder
)
7506 1 << connector
->new_encoder
->new_crtc
->pipe
;
7509 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7511 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7514 if (encoder
->base
.crtc
) {
7515 tmp_crtc
= encoder
->base
.crtc
;
7517 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7520 if (encoder
->new_crtc
)
7521 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7524 /* Check for any pipes that will be fully disabled ... */
7525 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7529 /* Don't try to disable disabled crtcs. */
7530 if (!intel_crtc
->base
.enabled
)
7533 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7535 if (encoder
->new_crtc
== intel_crtc
)
7540 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7544 /* set_mode is also used to update properties on life display pipes. */
7545 intel_crtc
= to_intel_crtc(crtc
);
7547 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7549 /* We only support modeset on one single crtc, hence we need to do that
7550 * only for the passed in crtc iff we change anything else than just
7553 * This is actually not true, to be fully compatible with the old crtc
7554 * helper we automatically disable _any_ output (i.e. doesn't need to be
7555 * connected to the crtc we're modesetting on) if it's disconnected.
7556 * Which is a rather nutty api (since changed the output configuration
7557 * without userspace's explicit request can lead to confusion), but
7558 * alas. Hence we currently need to modeset on all pipes we prepare. */
7560 *modeset_pipes
= *prepare_pipes
;
7562 /* ... and mask these out. */
7563 *modeset_pipes
&= ~(*disable_pipes
);
7564 *prepare_pipes
&= ~(*disable_pipes
);
7567 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7569 struct drm_encoder
*encoder
;
7570 struct drm_device
*dev
= crtc
->dev
;
7572 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7573 if (encoder
->crtc
== crtc
)
7580 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7582 struct intel_encoder
*intel_encoder
;
7583 struct intel_crtc
*intel_crtc
;
7584 struct drm_connector
*connector
;
7586 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7588 if (!intel_encoder
->base
.crtc
)
7591 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7593 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7594 intel_encoder
->connectors_active
= false;
7597 intel_modeset_commit_output_state(dev
);
7599 /* Update computed state. */
7600 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7602 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7605 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7606 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7609 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7611 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7612 struct drm_property
*dpms_property
=
7613 dev
->mode_config
.dpms_property
;
7615 connector
->dpms
= DRM_MODE_DPMS_ON
;
7616 drm_connector_property_set_value(connector
,
7620 intel_encoder
= to_intel_encoder(connector
->encoder
);
7621 intel_encoder
->connectors_active
= true;
7627 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7628 list_for_each_entry((intel_crtc), \
7629 &(dev)->mode_config.crtc_list, \
7631 if (mask & (1 <<(intel_crtc)->pipe)) \
7634 intel_modeset_check_state(struct drm_device
*dev
)
7636 struct intel_crtc
*crtc
;
7637 struct intel_encoder
*encoder
;
7638 struct intel_connector
*connector
;
7640 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7642 /* This also checks the encoder/connector hw state with the
7643 * ->get_hw_state callbacks. */
7644 intel_connector_check_state(connector
);
7646 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7647 "connector's staged encoder doesn't match current encoder\n");
7650 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7652 bool enabled
= false;
7653 bool active
= false;
7654 enum pipe pipe
, tracked_pipe
;
7656 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7657 encoder
->base
.base
.id
,
7658 drm_get_encoder_name(&encoder
->base
));
7660 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7661 "encoder's stage crtc doesn't match current crtc\n");
7662 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7663 "encoder's active_connectors set, but no crtc\n");
7665 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7667 if (connector
->base
.encoder
!= &encoder
->base
)
7670 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7673 WARN(!!encoder
->base
.crtc
!= enabled
,
7674 "encoder's enabled state mismatch "
7675 "(expected %i, found %i)\n",
7676 !!encoder
->base
.crtc
, enabled
);
7677 WARN(active
&& !encoder
->base
.crtc
,
7678 "active encoder with no crtc\n");
7680 WARN(encoder
->connectors_active
!= active
,
7681 "encoder's computed active state doesn't match tracked active state "
7682 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7684 active
= encoder
->get_hw_state(encoder
, &pipe
);
7685 WARN(active
!= encoder
->connectors_active
,
7686 "encoder's hw state doesn't match sw tracking "
7687 "(expected %i, found %i)\n",
7688 encoder
->connectors_active
, active
);
7690 if (!encoder
->base
.crtc
)
7693 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7694 WARN(active
&& pipe
!= tracked_pipe
,
7695 "active encoder's pipe doesn't match"
7696 "(expected %i, found %i)\n",
7697 tracked_pipe
, pipe
);
7701 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7703 bool enabled
= false;
7704 bool active
= false;
7706 DRM_DEBUG_KMS("[CRTC:%d]\n",
7707 crtc
->base
.base
.id
);
7709 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7710 "active crtc, but not enabled in sw tracking\n");
7712 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7714 if (encoder
->base
.crtc
!= &crtc
->base
)
7717 if (encoder
->connectors_active
)
7720 WARN(active
!= crtc
->active
,
7721 "crtc's computed active state doesn't match tracked active state "
7722 "(expected %i, found %i)\n", active
, crtc
->active
);
7723 WARN(enabled
!= crtc
->base
.enabled
,
7724 "crtc's computed enabled state doesn't match tracked enabled state "
7725 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7727 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7731 bool intel_set_mode(struct drm_crtc
*crtc
,
7732 struct drm_display_mode
*mode
,
7733 int x
, int y
, struct drm_framebuffer
*fb
)
7735 struct drm_device
*dev
= crtc
->dev
;
7736 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7737 struct drm_display_mode
*adjusted_mode
, saved_mode
, saved_hwmode
;
7738 struct intel_crtc
*intel_crtc
;
7739 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7742 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7743 &prepare_pipes
, &disable_pipes
);
7745 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7746 modeset_pipes
, prepare_pipes
, disable_pipes
);
7748 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7749 intel_crtc_disable(&intel_crtc
->base
);
7751 saved_hwmode
= crtc
->hwmode
;
7752 saved_mode
= crtc
->mode
;
7754 /* Hack: Because we don't (yet) support global modeset on multiple
7755 * crtcs, we don't keep track of the new mode for more than one crtc.
7756 * Hence simply check whether any bit is set in modeset_pipes in all the
7757 * pieces of code that are not yet converted to deal with mutliple crtcs
7758 * changing their mode at the same time. */
7759 adjusted_mode
= NULL
;
7760 if (modeset_pipes
) {
7761 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7762 if (IS_ERR(adjusted_mode
)) {
7767 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7768 if (intel_crtc
->base
.enabled
)
7769 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7772 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7773 * to set it here already despite that we pass it down the callchain.
7778 /* Only after disabling all output pipelines that will be changed can we
7779 * update the the output configuration. */
7780 intel_modeset_update_state(dev
, prepare_pipes
);
7782 if (dev_priv
->display
.modeset_global_resources
)
7783 dev_priv
->display
.modeset_global_resources(dev
);
7785 /* Set up the DPLL and any encoders state that needs to adjust or depend
7788 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7789 ret
= !intel_crtc_mode_set(&intel_crtc
->base
,
7790 mode
, adjusted_mode
,
7796 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7797 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7798 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7800 if (modeset_pipes
) {
7801 /* Store real post-adjustment hardware mode. */
7802 crtc
->hwmode
= *adjusted_mode
;
7804 /* Calculate and store various constants which
7805 * are later needed by vblank and swap-completion
7806 * timestamping. They are derived from true hwmode.
7808 drm_calc_timestamping_constants(crtc
);
7811 /* FIXME: add subpixel order */
7813 drm_mode_destroy(dev
, adjusted_mode
);
7814 if (!ret
&& crtc
->enabled
) {
7815 crtc
->hwmode
= saved_hwmode
;
7816 crtc
->mode
= saved_mode
;
7818 intel_modeset_check_state(dev
);
7824 #undef for_each_intel_crtc_masked
7826 static void intel_set_config_free(struct intel_set_config
*config
)
7831 kfree(config
->save_connector_encoders
);
7832 kfree(config
->save_encoder_crtcs
);
7836 static int intel_set_config_save_state(struct drm_device
*dev
,
7837 struct intel_set_config
*config
)
7839 struct drm_encoder
*encoder
;
7840 struct drm_connector
*connector
;
7843 config
->save_encoder_crtcs
=
7844 kcalloc(dev
->mode_config
.num_encoder
,
7845 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7846 if (!config
->save_encoder_crtcs
)
7849 config
->save_connector_encoders
=
7850 kcalloc(dev
->mode_config
.num_connector
,
7851 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7852 if (!config
->save_connector_encoders
)
7855 /* Copy data. Note that driver private data is not affected.
7856 * Should anything bad happen only the expected state is
7857 * restored, not the drivers personal bookkeeping.
7860 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7861 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7865 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7866 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7872 static void intel_set_config_restore_state(struct drm_device
*dev
,
7873 struct intel_set_config
*config
)
7875 struct intel_encoder
*encoder
;
7876 struct intel_connector
*connector
;
7880 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7882 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7886 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7887 connector
->new_encoder
=
7888 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7893 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7894 struct intel_set_config
*config
)
7897 /* We should be able to check here if the fb has the same properties
7898 * and then just flip_or_move it */
7899 if (set
->crtc
->fb
!= set
->fb
) {
7900 /* If we have no fb then treat it as a full mode set */
7901 if (set
->crtc
->fb
== NULL
) {
7902 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7903 config
->mode_changed
= true;
7904 } else if (set
->fb
== NULL
) {
7905 config
->mode_changed
= true;
7906 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7907 config
->mode_changed
= true;
7908 } else if (set
->fb
->bits_per_pixel
!=
7909 set
->crtc
->fb
->bits_per_pixel
) {
7910 config
->mode_changed
= true;
7912 config
->fb_changed
= true;
7915 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7916 config
->fb_changed
= true;
7918 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7919 DRM_DEBUG_KMS("modes are different, full mode set\n");
7920 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7921 drm_mode_debug_printmodeline(set
->mode
);
7922 config
->mode_changed
= true;
7927 intel_modeset_stage_output_state(struct drm_device
*dev
,
7928 struct drm_mode_set
*set
,
7929 struct intel_set_config
*config
)
7931 struct drm_crtc
*new_crtc
;
7932 struct intel_connector
*connector
;
7933 struct intel_encoder
*encoder
;
7936 /* The upper layers ensure that we either disabl a crtc or have a list
7937 * of connectors. For paranoia, double-check this. */
7938 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7939 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7942 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7944 /* Otherwise traverse passed in connector list and get encoders
7946 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7947 if (set
->connectors
[ro
] == &connector
->base
) {
7948 connector
->new_encoder
= connector
->encoder
;
7953 /* If we disable the crtc, disable all its connectors. Also, if
7954 * the connector is on the changing crtc but not on the new
7955 * connector list, disable it. */
7956 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7957 connector
->base
.encoder
&&
7958 connector
->base
.encoder
->crtc
== set
->crtc
) {
7959 connector
->new_encoder
= NULL
;
7961 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7962 connector
->base
.base
.id
,
7963 drm_get_connector_name(&connector
->base
));
7967 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7968 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7969 config
->mode_changed
= true;
7972 /* Disable all disconnected encoders. */
7973 if (connector
->base
.status
== connector_status_disconnected
)
7974 connector
->new_encoder
= NULL
;
7976 /* connector->new_encoder is now updated for all connectors. */
7978 /* Update crtc of enabled connectors. */
7980 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7982 if (!connector
->new_encoder
)
7985 new_crtc
= connector
->new_encoder
->base
.crtc
;
7987 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7988 if (set
->connectors
[ro
] == &connector
->base
)
7989 new_crtc
= set
->crtc
;
7992 /* Make sure the new CRTC will work with the encoder */
7993 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7997 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7999 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8000 connector
->base
.base
.id
,
8001 drm_get_connector_name(&connector
->base
),
8005 /* Check for any encoders that needs to be disabled. */
8006 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8008 list_for_each_entry(connector
,
8009 &dev
->mode_config
.connector_list
,
8011 if (connector
->new_encoder
== encoder
) {
8012 WARN_ON(!connector
->new_encoder
->new_crtc
);
8017 encoder
->new_crtc
= NULL
;
8019 /* Only now check for crtc changes so we don't miss encoders
8020 * that will be disabled. */
8021 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
8022 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8023 config
->mode_changed
= true;
8026 /* Now we've also updated encoder->new_crtc for all encoders. */
8031 static int intel_crtc_set_config(struct drm_mode_set
*set
)
8033 struct drm_device
*dev
;
8034 struct drm_mode_set save_set
;
8035 struct intel_set_config
*config
;
8040 BUG_ON(!set
->crtc
->helper_private
);
8045 /* The fb helper likes to play gross jokes with ->mode_set_config.
8046 * Unfortunately the crtc helper doesn't do much at all for this case,
8047 * so we have to cope with this madness until the fb helper is fixed up. */
8048 if (set
->fb
&& set
->num_connectors
== 0)
8052 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8053 set
->crtc
->base
.id
, set
->fb
->base
.id
,
8054 (int)set
->num_connectors
, set
->x
, set
->y
);
8056 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
8059 dev
= set
->crtc
->dev
;
8062 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
8066 ret
= intel_set_config_save_state(dev
, config
);
8070 save_set
.crtc
= set
->crtc
;
8071 save_set
.mode
= &set
->crtc
->mode
;
8072 save_set
.x
= set
->crtc
->x
;
8073 save_set
.y
= set
->crtc
->y
;
8074 save_set
.fb
= set
->crtc
->fb
;
8076 /* Compute whether we need a full modeset, only an fb base update or no
8077 * change at all. In the future we might also check whether only the
8078 * mode changed, e.g. for LVDS where we only change the panel fitter in
8080 intel_set_config_compute_mode_changes(set
, config
);
8082 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
8086 if (config
->mode_changed
) {
8088 DRM_DEBUG_KMS("attempting to set mode from"
8090 drm_mode_debug_printmodeline(set
->mode
);
8093 if (!intel_set_mode(set
->crtc
, set
->mode
,
8094 set
->x
, set
->y
, set
->fb
)) {
8095 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8096 set
->crtc
->base
.id
);
8100 } else if (config
->fb_changed
) {
8101 ret
= intel_pipe_set_base(set
->crtc
,
8102 set
->x
, set
->y
, set
->fb
);
8105 intel_set_config_free(config
);
8110 intel_set_config_restore_state(dev
, config
);
8112 /* Try to restore the config */
8113 if (config
->mode_changed
&&
8114 !intel_set_mode(save_set
.crtc
, save_set
.mode
,
8115 save_set
.x
, save_set
.y
, save_set
.fb
))
8116 DRM_ERROR("failed to restore config after modeset failure\n");
8119 intel_set_config_free(config
);
8123 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8124 .cursor_set
= intel_crtc_cursor_set
,
8125 .cursor_move
= intel_crtc_cursor_move
,
8126 .gamma_set
= intel_crtc_gamma_set
,
8127 .set_config
= intel_crtc_set_config
,
8128 .destroy
= intel_crtc_destroy
,
8129 .page_flip
= intel_crtc_page_flip
,
8132 static void intel_cpu_pll_init(struct drm_device
*dev
)
8134 if (IS_HASWELL(dev
))
8135 intel_ddi_pll_init(dev
);
8138 static void intel_pch_pll_init(struct drm_device
*dev
)
8140 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8143 if (dev_priv
->num_pch_pll
== 0) {
8144 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8148 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8149 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8150 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8151 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8155 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8158 struct intel_crtc
*intel_crtc
;
8161 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8162 if (intel_crtc
== NULL
)
8165 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8167 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8168 for (i
= 0; i
< 256; i
++) {
8169 intel_crtc
->lut_r
[i
] = i
;
8170 intel_crtc
->lut_g
[i
] = i
;
8171 intel_crtc
->lut_b
[i
] = i
;
8174 /* Swap pipes & planes for FBC on pre-965 */
8175 intel_crtc
->pipe
= pipe
;
8176 intel_crtc
->plane
= pipe
;
8177 intel_crtc
->cpu_transcoder
= pipe
;
8178 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8179 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8180 intel_crtc
->plane
= !pipe
;
8183 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8184 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8185 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8186 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8188 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8190 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8193 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8194 struct drm_file
*file
)
8196 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8197 struct drm_mode_object
*drmmode_obj
;
8198 struct intel_crtc
*crtc
;
8200 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8203 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8204 DRM_MODE_OBJECT_CRTC
);
8207 DRM_ERROR("no such CRTC id\n");
8211 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8212 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8217 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8219 struct drm_device
*dev
= encoder
->base
.dev
;
8220 struct intel_encoder
*source_encoder
;
8224 list_for_each_entry(source_encoder
,
8225 &dev
->mode_config
.encoder_list
, base
.head
) {
8227 if (encoder
== source_encoder
)
8228 index_mask
|= (1 << entry
);
8230 /* Intel hw has only one MUX where enocoders could be cloned. */
8231 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8232 index_mask
|= (1 << entry
);
8240 static bool has_edp_a(struct drm_device
*dev
)
8242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8244 if (!IS_MOBILE(dev
))
8247 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8251 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8257 static void intel_setup_outputs(struct drm_device
*dev
)
8259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8260 struct intel_encoder
*encoder
;
8261 bool dpd_is_edp
= false;
8264 has_lvds
= intel_lvds_init(dev
);
8265 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8266 /* disable the panel fitter on everything but LVDS */
8267 I915_WRITE(PFIT_CONTROL
, 0);
8270 intel_crt_init(dev
);
8272 if (IS_HASWELL(dev
)) {
8275 /* Haswell uses DDI functions to detect digital outputs */
8276 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8277 /* DDI A only supports eDP */
8279 intel_ddi_init(dev
, PORT_A
);
8281 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8283 found
= I915_READ(SFUSE_STRAP
);
8285 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8286 intel_ddi_init(dev
, PORT_B
);
8287 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8288 intel_ddi_init(dev
, PORT_C
);
8289 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8290 intel_ddi_init(dev
, PORT_D
);
8291 } else if (HAS_PCH_SPLIT(dev
)) {
8293 dpd_is_edp
= intel_dpd_is_edp(dev
);
8296 intel_dp_init(dev
, DP_A
, PORT_A
);
8298 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
8299 /* PCH SDVOB multiplex with HDMIB */
8300 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8302 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
8303 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8304 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8307 if (I915_READ(HDMIC
) & PORT_DETECTED
)
8308 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
8310 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
8311 intel_hdmi_init(dev
, HDMID
, PORT_D
);
8313 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8314 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8316 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
8317 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8318 } else if (IS_VALLEYVIEW(dev
)) {
8321 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8322 if (I915_READ(DP_C
) & DP_DETECTED
)
8323 intel_dp_init(dev
, DP_C
, PORT_C
);
8325 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
8326 /* SDVOB multiplex with HDMIB */
8327 found
= intel_sdvo_init(dev
, SDVOB
, true);
8329 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8330 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
8331 intel_dp_init(dev
, DP_B
, PORT_B
);
8334 if (I915_READ(SDVOC
) & PORT_DETECTED
)
8335 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8337 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8340 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8341 DRM_DEBUG_KMS("probing SDVOB\n");
8342 found
= intel_sdvo_init(dev
, SDVOB
, true);
8343 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8344 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8345 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8348 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8349 DRM_DEBUG_KMS("probing DP_B\n");
8350 intel_dp_init(dev
, DP_B
, PORT_B
);
8354 /* Before G4X SDVOC doesn't have its own detect register */
8356 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8357 DRM_DEBUG_KMS("probing SDVOC\n");
8358 found
= intel_sdvo_init(dev
, SDVOC
, false);
8361 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
8363 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8364 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8365 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8367 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8368 DRM_DEBUG_KMS("probing DP_C\n");
8369 intel_dp_init(dev
, DP_C
, PORT_C
);
8373 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8374 (I915_READ(DP_D
) & DP_DETECTED
)) {
8375 DRM_DEBUG_KMS("probing DP_D\n");
8376 intel_dp_init(dev
, DP_D
, PORT_D
);
8378 } else if (IS_GEN2(dev
))
8379 intel_dvo_init(dev
);
8381 if (SUPPORTS_TV(dev
))
8384 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8385 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8386 encoder
->base
.possible_clones
=
8387 intel_encoder_clones(encoder
);
8390 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8391 ironlake_init_pch_refclk(dev
);
8393 drm_helper_move_panel_connectors_to_head(dev
);
8396 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8398 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8400 drm_framebuffer_cleanup(fb
);
8401 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8406 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8407 struct drm_file
*file
,
8408 unsigned int *handle
)
8410 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8411 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8413 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8416 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8417 .destroy
= intel_user_framebuffer_destroy
,
8418 .create_handle
= intel_user_framebuffer_create_handle
,
8421 int intel_framebuffer_init(struct drm_device
*dev
,
8422 struct intel_framebuffer
*intel_fb
,
8423 struct drm_mode_fb_cmd2
*mode_cmd
,
8424 struct drm_i915_gem_object
*obj
)
8428 if (obj
->tiling_mode
== I915_TILING_Y
)
8431 if (mode_cmd
->pitches
[0] & 63)
8434 /* FIXME <= Gen4 stride limits are bit unclear */
8435 if (mode_cmd
->pitches
[0] > 32768)
8438 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
8439 mode_cmd
->pitches
[0] != obj
->stride
)
8442 /* Reject formats not supported by any plane early. */
8443 switch (mode_cmd
->pixel_format
) {
8445 case DRM_FORMAT_RGB565
:
8446 case DRM_FORMAT_XRGB8888
:
8447 case DRM_FORMAT_ARGB8888
:
8449 case DRM_FORMAT_XRGB1555
:
8450 case DRM_FORMAT_ARGB1555
:
8451 if (INTEL_INFO(dev
)->gen
> 3)
8454 case DRM_FORMAT_XBGR8888
:
8455 case DRM_FORMAT_ABGR8888
:
8456 case DRM_FORMAT_XRGB2101010
:
8457 case DRM_FORMAT_ARGB2101010
:
8458 case DRM_FORMAT_XBGR2101010
:
8459 case DRM_FORMAT_ABGR2101010
:
8460 if (INTEL_INFO(dev
)->gen
< 4)
8463 case DRM_FORMAT_YUYV
:
8464 case DRM_FORMAT_UYVY
:
8465 case DRM_FORMAT_YVYU
:
8466 case DRM_FORMAT_VYUY
:
8467 if (INTEL_INFO(dev
)->gen
< 6)
8471 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd
->pixel_format
);
8475 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8476 if (mode_cmd
->offsets
[0] != 0)
8479 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8481 DRM_ERROR("framebuffer init failed %d\n", ret
);
8485 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8486 intel_fb
->obj
= obj
;
8490 static struct drm_framebuffer
*
8491 intel_user_framebuffer_create(struct drm_device
*dev
,
8492 struct drm_file
*filp
,
8493 struct drm_mode_fb_cmd2
*mode_cmd
)
8495 struct drm_i915_gem_object
*obj
;
8497 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8498 mode_cmd
->handles
[0]));
8499 if (&obj
->base
== NULL
)
8500 return ERR_PTR(-ENOENT
);
8502 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8505 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8506 .fb_create
= intel_user_framebuffer_create
,
8507 .output_poll_changed
= intel_fb_output_poll_changed
,
8510 /* Set up chip specific display functions */
8511 static void intel_init_display(struct drm_device
*dev
)
8513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8515 /* We always want a DPMS function */
8516 if (IS_HASWELL(dev
)) {
8517 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8518 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8519 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8520 dev_priv
->display
.off
= haswell_crtc_off
;
8521 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8522 } else if (HAS_PCH_SPLIT(dev
)) {
8523 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8524 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8525 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8526 dev_priv
->display
.off
= ironlake_crtc_off
;
8527 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8529 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8530 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8531 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8532 dev_priv
->display
.off
= i9xx_crtc_off
;
8533 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8536 /* Returns the core display clock speed */
8537 if (IS_VALLEYVIEW(dev
))
8538 dev_priv
->display
.get_display_clock_speed
=
8539 valleyview_get_display_clock_speed
;
8540 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8541 dev_priv
->display
.get_display_clock_speed
=
8542 i945_get_display_clock_speed
;
8543 else if (IS_I915G(dev
))
8544 dev_priv
->display
.get_display_clock_speed
=
8545 i915_get_display_clock_speed
;
8546 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8547 dev_priv
->display
.get_display_clock_speed
=
8548 i9xx_misc_get_display_clock_speed
;
8549 else if (IS_I915GM(dev
))
8550 dev_priv
->display
.get_display_clock_speed
=
8551 i915gm_get_display_clock_speed
;
8552 else if (IS_I865G(dev
))
8553 dev_priv
->display
.get_display_clock_speed
=
8554 i865_get_display_clock_speed
;
8555 else if (IS_I85X(dev
))
8556 dev_priv
->display
.get_display_clock_speed
=
8557 i855_get_display_clock_speed
;
8559 dev_priv
->display
.get_display_clock_speed
=
8560 i830_get_display_clock_speed
;
8562 if (HAS_PCH_SPLIT(dev
)) {
8564 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8565 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8566 } else if (IS_GEN6(dev
)) {
8567 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8568 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8569 } else if (IS_IVYBRIDGE(dev
)) {
8570 /* FIXME: detect B0+ stepping and use auto training */
8571 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8572 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8573 dev_priv
->display
.modeset_global_resources
=
8574 ivb_modeset_global_resources
;
8575 } else if (IS_HASWELL(dev
)) {
8576 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8577 dev_priv
->display
.write_eld
= haswell_write_eld
;
8579 dev_priv
->display
.update_wm
= NULL
;
8580 } else if (IS_G4X(dev
)) {
8581 dev_priv
->display
.write_eld
= g4x_write_eld
;
8584 /* Default just returns -ENODEV to indicate unsupported */
8585 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8587 switch (INTEL_INFO(dev
)->gen
) {
8589 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8593 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8598 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8602 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8605 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8611 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8612 * resume, or other times. This quirk makes sure that's the case for
8615 static void quirk_pipea_force(struct drm_device
*dev
)
8617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8619 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8620 DRM_INFO("applying pipe a force quirk\n");
8624 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8626 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8628 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8629 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8630 DRM_INFO("applying lvds SSC disable quirk\n");
8634 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8637 static void quirk_invert_brightness(struct drm_device
*dev
)
8639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8640 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8641 DRM_INFO("applying inverted panel brightness quirk\n");
8644 struct intel_quirk
{
8646 int subsystem_vendor
;
8647 int subsystem_device
;
8648 void (*hook
)(struct drm_device
*dev
);
8651 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8652 struct intel_dmi_quirk
{
8653 void (*hook
)(struct drm_device
*dev
);
8654 const struct dmi_system_id (*dmi_id_list
)[];
8657 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
8659 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
8663 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
8665 .dmi_id_list
= &(const struct dmi_system_id
[]) {
8667 .callback
= intel_dmi_reverse_brightness
,
8668 .ident
= "NCR Corporation",
8669 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
8670 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
8673 { } /* terminating entry */
8675 .hook
= quirk_invert_brightness
,
8679 static struct intel_quirk intel_quirks
[] = {
8680 /* HP Mini needs pipe A force quirk (LP: #322104) */
8681 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8683 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8684 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8686 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8687 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8689 /* 830/845 need to leave pipe A & dpll A up */
8690 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8691 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8693 /* Lenovo U160 cannot use SSC on LVDS */
8694 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8696 /* Sony Vaio Y cannot use SSC on LVDS */
8697 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8699 /* Acer Aspire 5734Z must invert backlight brightness */
8700 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8703 static void intel_init_quirks(struct drm_device
*dev
)
8705 struct pci_dev
*d
= dev
->pdev
;
8708 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8709 struct intel_quirk
*q
= &intel_quirks
[i
];
8711 if (d
->device
== q
->device
&&
8712 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8713 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8714 (d
->subsystem_device
== q
->subsystem_device
||
8715 q
->subsystem_device
== PCI_ANY_ID
))
8718 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
8719 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
8720 intel_dmi_quirks
[i
].hook(dev
);
8724 /* Disable the VGA plane that we never use */
8725 static void i915_disable_vga(struct drm_device
*dev
)
8727 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8731 if (HAS_PCH_SPLIT(dev
))
8732 vga_reg
= CPU_VGACNTRL
;
8736 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8737 outb(SR01
, VGA_SR_INDEX
);
8738 sr1
= inb(VGA_SR_DATA
);
8739 outb(sr1
| 1<<5, VGA_SR_DATA
);
8740 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8743 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8744 POSTING_READ(vga_reg
);
8747 void intel_modeset_init_hw(struct drm_device
*dev
)
8749 /* We attempt to init the necessary power wells early in the initialization
8750 * time, so the subsystems that expect power to be enabled can work.
8752 intel_init_power_wells(dev
);
8754 intel_prepare_ddi(dev
);
8756 intel_init_clock_gating(dev
);
8758 mutex_lock(&dev
->struct_mutex
);
8759 intel_enable_gt_powersave(dev
);
8760 mutex_unlock(&dev
->struct_mutex
);
8763 void intel_modeset_init(struct drm_device
*dev
)
8765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8768 drm_mode_config_init(dev
);
8770 dev
->mode_config
.min_width
= 0;
8771 dev
->mode_config
.min_height
= 0;
8773 dev
->mode_config
.preferred_depth
= 24;
8774 dev
->mode_config
.prefer_shadow
= 1;
8776 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8778 intel_init_quirks(dev
);
8782 intel_init_display(dev
);
8785 dev
->mode_config
.max_width
= 2048;
8786 dev
->mode_config
.max_height
= 2048;
8787 } else if (IS_GEN3(dev
)) {
8788 dev
->mode_config
.max_width
= 4096;
8789 dev
->mode_config
.max_height
= 4096;
8791 dev
->mode_config
.max_width
= 8192;
8792 dev
->mode_config
.max_height
= 8192;
8794 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8796 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8797 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8799 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8800 intel_crtc_init(dev
, i
);
8801 ret
= intel_plane_init(dev
, i
);
8803 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8806 intel_cpu_pll_init(dev
);
8807 intel_pch_pll_init(dev
);
8809 /* Just disable it once at startup */
8810 i915_disable_vga(dev
);
8811 intel_setup_outputs(dev
);
8815 intel_connector_break_all_links(struct intel_connector
*connector
)
8817 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8818 connector
->base
.encoder
= NULL
;
8819 connector
->encoder
->connectors_active
= false;
8820 connector
->encoder
->base
.crtc
= NULL
;
8823 static void intel_enable_pipe_a(struct drm_device
*dev
)
8825 struct intel_connector
*connector
;
8826 struct drm_connector
*crt
= NULL
;
8827 struct intel_load_detect_pipe load_detect_temp
;
8829 /* We can't just switch on the pipe A, we need to set things up with a
8830 * proper mode and output configuration. As a gross hack, enable pipe A
8831 * by enabling the load detect pipe once. */
8832 list_for_each_entry(connector
,
8833 &dev
->mode_config
.connector_list
,
8835 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8836 crt
= &connector
->base
;
8844 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8845 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8851 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8853 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
8856 if (dev_priv
->num_pipe
== 1)
8859 reg
= DSPCNTR(!crtc
->plane
);
8860 val
= I915_READ(reg
);
8862 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8863 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8869 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8871 struct drm_device
*dev
= crtc
->base
.dev
;
8872 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8875 /* Clear any frame start delays used for debugging left by the BIOS */
8876 reg
= PIPECONF(crtc
->cpu_transcoder
);
8877 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8879 /* We need to sanitize the plane -> pipe mapping first because this will
8880 * disable the crtc (and hence change the state) if it is wrong. Note
8881 * that gen4+ has a fixed plane -> pipe mapping. */
8882 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8883 struct intel_connector
*connector
;
8886 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8887 crtc
->base
.base
.id
);
8889 /* Pipe has the wrong plane attached and the plane is active.
8890 * Temporarily change the plane mapping and disable everything
8892 plane
= crtc
->plane
;
8893 crtc
->plane
= !plane
;
8894 dev_priv
->display
.crtc_disable(&crtc
->base
);
8895 crtc
->plane
= plane
;
8897 /* ... and break all links. */
8898 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8900 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8903 intel_connector_break_all_links(connector
);
8906 WARN_ON(crtc
->active
);
8907 crtc
->base
.enabled
= false;
8910 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8911 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8912 /* BIOS forgot to enable pipe A, this mostly happens after
8913 * resume. Force-enable the pipe to fix this, the update_dpms
8914 * call below we restore the pipe to the right state, but leave
8915 * the required bits on. */
8916 intel_enable_pipe_a(dev
);
8919 /* Adjust the state of the output pipe according to whether we
8920 * have active connectors/encoders. */
8921 intel_crtc_update_dpms(&crtc
->base
);
8923 if (crtc
->active
!= crtc
->base
.enabled
) {
8924 struct intel_encoder
*encoder
;
8926 /* This can happen either due to bugs in the get_hw_state
8927 * functions or because the pipe is force-enabled due to the
8929 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8931 crtc
->base
.enabled
? "enabled" : "disabled",
8932 crtc
->active
? "enabled" : "disabled");
8934 crtc
->base
.enabled
= crtc
->active
;
8936 /* Because we only establish the connector -> encoder ->
8937 * crtc links if something is active, this means the
8938 * crtc is now deactivated. Break the links. connector
8939 * -> encoder links are only establish when things are
8940 * actually up, hence no need to break them. */
8941 WARN_ON(crtc
->active
);
8943 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8944 WARN_ON(encoder
->connectors_active
);
8945 encoder
->base
.crtc
= NULL
;
8950 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8952 struct intel_connector
*connector
;
8953 struct drm_device
*dev
= encoder
->base
.dev
;
8955 /* We need to check both for a crtc link (meaning that the
8956 * encoder is active and trying to read from a pipe) and the
8957 * pipe itself being active. */
8958 bool has_active_crtc
= encoder
->base
.crtc
&&
8959 to_intel_crtc(encoder
->base
.crtc
)->active
;
8961 if (encoder
->connectors_active
&& !has_active_crtc
) {
8962 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8963 encoder
->base
.base
.id
,
8964 drm_get_encoder_name(&encoder
->base
));
8966 /* Connector is active, but has no active pipe. This is
8967 * fallout from our resume register restoring. Disable
8968 * the encoder manually again. */
8969 if (encoder
->base
.crtc
) {
8970 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8971 encoder
->base
.base
.id
,
8972 drm_get_encoder_name(&encoder
->base
));
8973 encoder
->disable(encoder
);
8976 /* Inconsistent output/port/pipe state happens presumably due to
8977 * a bug in one of the get_hw_state functions. Or someplace else
8978 * in our code, like the register restore mess on resume. Clamp
8979 * things to off as a safer default. */
8980 list_for_each_entry(connector
,
8981 &dev
->mode_config
.connector_list
,
8983 if (connector
->encoder
!= encoder
)
8986 intel_connector_break_all_links(connector
);
8989 /* Enabled encoders without active connectors will be fixed in
8990 * the crtc fixup. */
8993 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8994 * and i915 state tracking structures. */
8995 void intel_modeset_setup_hw_state(struct drm_device
*dev
)
8997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9000 struct intel_crtc
*crtc
;
9001 struct intel_encoder
*encoder
;
9002 struct intel_connector
*connector
;
9004 if (IS_HASWELL(dev
)) {
9005 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9007 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9008 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9009 case TRANS_DDI_EDP_INPUT_A_ON
:
9010 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9013 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9016 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9021 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9022 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
9024 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9029 for_each_pipe(pipe
) {
9030 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9032 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
9033 if (tmp
& PIPECONF_ENABLE
)
9034 crtc
->active
= true;
9036 crtc
->active
= false;
9038 crtc
->base
.enabled
= crtc
->active
;
9040 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9042 crtc
->active
? "enabled" : "disabled");
9045 if (IS_HASWELL(dev
))
9046 intel_ddi_setup_hw_pll_state(dev
);
9048 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9052 if (encoder
->get_hw_state(encoder
, &pipe
)) {
9053 encoder
->base
.crtc
=
9054 dev_priv
->pipe_to_crtc_mapping
[pipe
];
9056 encoder
->base
.crtc
= NULL
;
9059 encoder
->connectors_active
= false;
9060 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9061 encoder
->base
.base
.id
,
9062 drm_get_encoder_name(&encoder
->base
),
9063 encoder
->base
.crtc
? "enabled" : "disabled",
9067 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9069 if (connector
->get_hw_state(connector
)) {
9070 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
9071 connector
->encoder
->connectors_active
= true;
9072 connector
->base
.encoder
= &connector
->encoder
->base
;
9074 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
9075 connector
->base
.encoder
= NULL
;
9077 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9078 connector
->base
.base
.id
,
9079 drm_get_connector_name(&connector
->base
),
9080 connector
->base
.encoder
? "enabled" : "disabled");
9083 /* HW state is read out, now we need to sanitize this mess. */
9084 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9086 intel_sanitize_encoder(encoder
);
9089 for_each_pipe(pipe
) {
9090 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
9091 intel_sanitize_crtc(crtc
);
9094 intel_modeset_update_staged_output_state(dev
);
9096 intel_modeset_check_state(dev
);
9098 drm_mode_config_reset(dev
);
9101 void intel_modeset_gem_init(struct drm_device
*dev
)
9103 intel_modeset_init_hw(dev
);
9105 intel_setup_overlay(dev
);
9107 intel_modeset_setup_hw_state(dev
);
9110 void intel_modeset_cleanup(struct drm_device
*dev
)
9112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9113 struct drm_crtc
*crtc
;
9114 struct intel_crtc
*intel_crtc
;
9116 drm_kms_helper_poll_fini(dev
);
9117 mutex_lock(&dev
->struct_mutex
);
9119 intel_unregister_dsm_handler();
9122 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9123 /* Skip inactive CRTCs */
9127 intel_crtc
= to_intel_crtc(crtc
);
9128 intel_increase_pllclock(crtc
);
9131 intel_disable_fbc(dev
);
9133 intel_disable_gt_powersave(dev
);
9135 ironlake_teardown_rc6(dev
);
9137 if (IS_VALLEYVIEW(dev
))
9140 mutex_unlock(&dev
->struct_mutex
);
9142 /* Disable the irq before mode object teardown, for the irq might
9143 * enqueue unpin/hotplug work. */
9144 drm_irq_uninstall(dev
);
9145 cancel_work_sync(&dev_priv
->hotplug_work
);
9146 cancel_work_sync(&dev_priv
->rps
.work
);
9148 /* flush any delayed tasks or pending work */
9149 flush_scheduled_work();
9151 drm_mode_config_cleanup(dev
);
9155 * Return which encoder is currently attached for connector.
9157 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9159 return &intel_attached_encoder(connector
)->base
;
9162 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9163 struct intel_encoder
*encoder
)
9165 connector
->encoder
= encoder
;
9166 drm_mode_connector_attach_encoder(&connector
->base
,
9171 * set vga decode state - true == enable VGA decode
9173 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9178 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9180 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9182 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9183 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9187 #ifdef CONFIG_DEBUG_FS
9188 #include <linux/seq_file.h>
9190 struct intel_display_error_state
{
9191 struct intel_cursor_error_state
{
9196 } cursor
[I915_MAX_PIPES
];
9198 struct intel_pipe_error_state
{
9208 } pipe
[I915_MAX_PIPES
];
9210 struct intel_plane_error_state
{
9218 } plane
[I915_MAX_PIPES
];
9221 struct intel_display_error_state
*
9222 intel_display_capture_error_state(struct drm_device
*dev
)
9224 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9225 struct intel_display_error_state
*error
;
9226 enum transcoder cpu_transcoder
;
9229 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9234 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9236 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9237 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9238 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9240 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9241 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9242 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9243 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9244 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9245 if (INTEL_INFO(dev
)->gen
>= 4) {
9246 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9247 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9250 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9251 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9252 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9253 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9254 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9255 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9256 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9257 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9264 intel_display_print_error_state(struct seq_file
*m
,
9265 struct drm_device
*dev
,
9266 struct intel_display_error_state
*error
)
9268 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9271 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
9273 seq_printf(m
, "Pipe [%d]:\n", i
);
9274 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9275 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9276 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9277 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9278 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9279 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9280 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9281 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9283 seq_printf(m
, "Plane [%d]:\n", i
);
9284 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9285 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9286 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9287 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9288 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9289 if (INTEL_INFO(dev
)->gen
>= 4) {
9290 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9291 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9294 seq_printf(m
, "Cursor [%d]:\n", i
);
9295 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9296 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9297 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);