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drm/i915: Write the FDI RX TU size reg at the right time
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 int
84 intel_pch_rawclk(struct drm_device *dev)
85 {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91 }
92
93 static bool
94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static bool
103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
106 static bool
107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
110
111 static bool
112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static inline u32 /* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device *dev)
118 {
119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
124 }
125
126 static const intel_limit_t intel_limits_i8xx_dvo = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i8xx_lvds = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_sdvo = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_lvds = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182
183 static const intel_limit_t intel_limits_g4x_sdvo = {
184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
195 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_hdmi = {
200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
239 },
240 .find_pll = intel_g4x_find_best_PLL,
241 };
242
243 static const intel_limit_t intel_limits_g4x_display_port = {
244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 10, .p2_fast = 10 },
254 .find_pll = intel_find_pll_g4x_dp,
255 };
256
257 static const intel_limit_t intel_limits_pineview_sdvo = {
258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 static const intel_limit_t intel_limits_pineview_lvds = {
274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 /* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
292 static const intel_limit_t intel_limits_ironlake_dac = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
357 .p1 = { .min = 2, .max = 6 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_display_port = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
373 .p2_slow = 10, .p2_fast = 10 },
374 .find_pll = intel_find_pll_ironlake_dp,
375 };
376
377 static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389 };
390
391 static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
393 .vco = { .min = 4000000, .max = 5994000},
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_dp = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 22, .max = 450 },
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420 {
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439 out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442 }
443
444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446 {
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462 out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464 }
465
466 static void vlv_init_dpio(struct drm_device *dev)
467 {
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475 }
476
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478 {
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481 }
482
483 static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493 };
494
495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497 {
498 unsigned int val;
499
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521 }
522
523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 const intel_limit_t *limit;
529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
532 /* LVDS dual channel */
533 if (refclk == 100000)
534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
538 if (refclk == 100000)
539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
546 else
547 limit = &intel_limits_ironlake_dac;
548
549 return limit;
550 }
551
552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553 {
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
559 if (is_dual_link_lvds(dev_priv, LVDS))
560 /* LVDS with dual channel */
561 limit = &intel_limits_g4x_dual_channel_lvds;
562 else
563 /* LVDS with dual channel */
564 limit = &intel_limits_g4x_single_channel_lvds;
565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
567 limit = &intel_limits_g4x_hdmi;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
569 limit = &intel_limits_g4x_sdvo;
570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
571 limit = &intel_limits_g4x_display_port;
572 } else /* The option is for other outputs */
573 limit = &intel_limits_i9xx_sdvo;
574
575 return limit;
576 }
577
578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
579 {
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
583 if (HAS_PCH_SPLIT(dev))
584 limit = intel_ironlake_limit(crtc, refclk);
585 else if (IS_G4X(dev)) {
586 limit = intel_g4x_limit(crtc);
587 } else if (IS_PINEVIEW(dev)) {
588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
589 limit = &intel_limits_pineview_lvds;
590 else
591 limit = &intel_limits_pineview_sdvo;
592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
606 limit = &intel_limits_i8xx_lvds;
607 else
608 limit = &intel_limits_i8xx_dvo;
609 }
610 return limit;
611 }
612
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk, intel_clock_t *clock)
615 {
616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620 }
621
622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623 {
624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
626 return;
627 }
628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632 }
633
634 /**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
638 {
639 struct drm_device *dev = crtc->dev;
640 struct intel_encoder *encoder;
641
642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
644 return true;
645
646 return false;
647 }
648
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
650 /**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
655 static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
658 {
659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock->p < limit->p.min || limit->p.max < clock->p)
662 INTELPllInvalid("p out of range\n");
663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 if (clock->n < limit->n.min || limit->n.max < clock->n)
672 INTELPllInvalid("n out of range\n");
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static bool
685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
688
689 {
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
693 int err = target;
694
695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
696 (I915_READ(LVDS)) != 0) {
697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
703 if (is_dual_link_lvds(dev_priv, LVDS))
704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
714 memset(best_clock, 0, sizeof(*best_clock));
715
716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
727 int this_err;
728
729 intel_clock(dev, refclk, &clock);
730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
732 continue;
733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748 }
749
750 static bool
751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
754 {
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765 int lvds_reg;
766
767 if (HAS_PCH_SPLIT(dev))
768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
796 intel_clock(dev, refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
815 return found;
816 }
817
818 static bool
819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
822 {
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
825
826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842 }
843
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
845 static bool
846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
849 {
850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
870 }
871 static bool
872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875 {
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
882 flag = 0;
883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938 }
939
940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942 {
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947 }
948
949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958 }
959
960 /**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
969 {
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 int pipestat_reg = PIPESTAT(pipe);
972
973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
998 DRM_DEBUG_KMS("vblank wait timed out\n");
999 }
1000
1001 /*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1016 *
1017 */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
1025 int reg = PIPECONF(cpu_transcoder);
1026
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 } else {
1032 u32 last_line, line_mask;
1033 int reg = PIPEDSL(pipe);
1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
1041 /* Wait for the display line to settle */
1042 do {
1043 last_line = I915_READ(reg) & line_mask;
1044 mdelay(5);
1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
1048 WARN(1, "pipe_off wait timed out\n");
1049 }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054 return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060 {
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
1080 {
1081 u32 val;
1082 bool cur_state;
1083
1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091 return;
1092
1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
1116 }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123 {
1124 int reg;
1125 u32 val;
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149 {
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int reg;
1192 u32 val;
1193
1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
1209 bool locked = true;
1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 int reg;
1236 u32 val;
1237 bool cur_state;
1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
1240
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
1245 reg = PIPECONF(cpu_transcoder);
1246 val = I915_READ(reg);
1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
1255 {
1256 int reg;
1257 u32 val;
1258 bool cur_state;
1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273 {
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
1285 return;
1286 }
1287
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
1297 }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302 u32 val;
1303 bool enabled;
1304
1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351 {
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367 {
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383 {
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, int reg, u32 port_sel)
1398 {
1399 u32 val = I915_READ(reg);
1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg, pipe_name(pipe));
1403
1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
1406 "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411 {
1412 u32 val = I915_READ(reg);
1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg, pipe_name(pipe));
1416
1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
1419 "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424 {
1425 int reg;
1426 u32 val;
1427
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1436 pipe_name(pipe));
1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442 pipe_name(pipe));
1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461 */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545 out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552 unsigned long flags;
1553 u32 value = 0;
1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579 }
1580
1581 /**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592 struct intel_pch_pll *pll;
1593 int reg;
1594 u32 val;
1595
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv->info->gen < 5);
1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
1612 if (pll->active++ && pll->on) {
1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
1625
1626 pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633 int reg;
1634 u32 val;
1635
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1638 if (pll == NULL)
1639 return;
1640
1641 if (WARN_ON(pll->refcount == 0))
1642 return;
1643
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
1647
1648 if (WARN_ON(pll->active == 0)) {
1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650 return;
1651 }
1652
1653 if (--pll->active) {
1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655 return;
1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663 reg = pll->pll_reg;
1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
1669
1670 pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675 {
1676 int reg;
1677 u32 val, pipeconf_val;
1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
1698 pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
1706 val |= pipeconf_val & PIPE_BPC_MASK;
1707 }
1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726 {
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747 * intel_enable_pipe - enable a pipe, asserting requirements
1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
1762 {
1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
1783
1784 reg = PIPECONF(cpu_transcoder);
1785 val = I915_READ(reg);
1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794 * intel_disable_pipe - disable a pipe, asserting requirements
1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807 {
1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
1823 reg = PIPECONF(cpu_transcoder);
1824 val = I915_READ(reg);
1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane)
1838 {
1839 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 }
1842
1843 /**
1844 * intel_enable_plane - enable a display plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1848 *
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1850 */
1851 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane, enum pipe pipe)
1853 {
1854 int reg;
1855 u32 val;
1856
1857 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858 assert_pipe_enabled(dev_priv, pipe);
1859
1860 reg = DSPCNTR(plane);
1861 val = I915_READ(reg);
1862 if (val & DISPLAY_PLANE_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1866 intel_flush_display_plane(dev_priv, plane);
1867 intel_wait_for_vblank(dev_priv->dev, pipe);
1868 }
1869
1870 /**
1871 * intel_disable_plane - disable a display plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1875 *
1876 * Disable @plane; should be an independent operation.
1877 */
1878 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879 enum plane plane, enum pipe pipe)
1880 {
1881 int reg;
1882 u32 val;
1883
1884 reg = DSPCNTR(plane);
1885 val = I915_READ(reg);
1886 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887 return;
1888
1889 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1890 intel_flush_display_plane(dev_priv, plane);
1891 intel_wait_for_vblank(dev_priv->dev, pipe);
1892 }
1893
1894 int
1895 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1896 struct drm_i915_gem_object *obj,
1897 struct intel_ring_buffer *pipelined)
1898 {
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 u32 alignment;
1901 int ret;
1902
1903 switch (obj->tiling_mode) {
1904 case I915_TILING_NONE:
1905 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906 alignment = 128 * 1024;
1907 else if (INTEL_INFO(dev)->gen >= 4)
1908 alignment = 4 * 1024;
1909 else
1910 alignment = 64 * 1024;
1911 break;
1912 case I915_TILING_X:
1913 /* pin() will align the object as required by fence */
1914 alignment = 0;
1915 break;
1916 case I915_TILING_Y:
1917 /* FIXME: Is this true? */
1918 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919 return -EINVAL;
1920 default:
1921 BUG();
1922 }
1923
1924 dev_priv->mm.interruptible = false;
1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926 if (ret)
1927 goto err_interruptible;
1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
1934 ret = i915_gem_object_get_fence(obj);
1935 if (ret)
1936 goto err_unpin;
1937
1938 i915_gem_object_pin_fence(obj);
1939
1940 dev_priv->mm.interruptible = true;
1941 return 0;
1942
1943 err_unpin:
1944 i915_gem_object_unpin(obj);
1945 err_interruptible:
1946 dev_priv->mm.interruptible = true;
1947 return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959 unsigned int bpp,
1960 unsigned int pitch)
1961 {
1962 int tile_rows, tiles;
1963
1964 tile_rows = *y / 8;
1965 *y %= 8;
1966 tiles = *x / (512/bpp);
1967 *x %= 512/bpp;
1968
1969 return tile_rows * pitch * 8 + tiles * 4096;
1970 }
1971
1972 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973 int x, int y)
1974 {
1975 struct drm_device *dev = crtc->dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 struct intel_framebuffer *intel_fb;
1979 struct drm_i915_gem_object *obj;
1980 int plane = intel_crtc->plane;
1981 unsigned long linear_offset;
1982 u32 dspcntr;
1983 u32 reg;
1984
1985 switch (plane) {
1986 case 0:
1987 case 1:
1988 break;
1989 default:
1990 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991 return -EINVAL;
1992 }
1993
1994 intel_fb = to_intel_framebuffer(fb);
1995 obj = intel_fb->obj;
1996
1997 reg = DSPCNTR(plane);
1998 dspcntr = I915_READ(reg);
1999 /* Mask out pixel format bits in case we change it */
2000 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001 switch (fb->bits_per_pixel) {
2002 case 8:
2003 dspcntr |= DISPPLANE_8BPP;
2004 break;
2005 case 16:
2006 if (fb->depth == 15)
2007 dspcntr |= DISPPLANE_15_16BPP;
2008 else
2009 dspcntr |= DISPPLANE_16BPP;
2010 break;
2011 case 24:
2012 case 32:
2013 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014 break;
2015 default:
2016 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2017 return -EINVAL;
2018 }
2019 if (INTEL_INFO(dev)->gen >= 4) {
2020 if (obj->tiling_mode != I915_TILING_NONE)
2021 dspcntr |= DISPPLANE_TILED;
2022 else
2023 dspcntr &= ~DISPPLANE_TILED;
2024 }
2025
2026 I915_WRITE(reg, dspcntr);
2027
2028 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2029
2030 if (INTEL_INFO(dev)->gen >= 4) {
2031 intel_crtc->dspaddr_offset =
2032 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033 fb->bits_per_pixel / 8,
2034 fb->pitches[0]);
2035 linear_offset -= intel_crtc->dspaddr_offset;
2036 } else {
2037 intel_crtc->dspaddr_offset = linear_offset;
2038 }
2039
2040 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2042 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2043 if (INTEL_INFO(dev)->gen >= 4) {
2044 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045 obj->gtt_offset + intel_crtc->dspaddr_offset);
2046 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2047 I915_WRITE(DSPLINOFF(plane), linear_offset);
2048 } else
2049 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2050 POSTING_READ(reg);
2051
2052 return 0;
2053 }
2054
2055 static int ironlake_update_plane(struct drm_crtc *crtc,
2056 struct drm_framebuffer *fb, int x, int y)
2057 {
2058 struct drm_device *dev = crtc->dev;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061 struct intel_framebuffer *intel_fb;
2062 struct drm_i915_gem_object *obj;
2063 int plane = intel_crtc->plane;
2064 unsigned long linear_offset;
2065 u32 dspcntr;
2066 u32 reg;
2067
2068 switch (plane) {
2069 case 0:
2070 case 1:
2071 case 2:
2072 break;
2073 default:
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075 return -EINVAL;
2076 }
2077
2078 intel_fb = to_intel_framebuffer(fb);
2079 obj = intel_fb->obj;
2080
2081 reg = DSPCNTR(plane);
2082 dspcntr = I915_READ(reg);
2083 /* Mask out pixel format bits in case we change it */
2084 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085 switch (fb->bits_per_pixel) {
2086 case 8:
2087 dspcntr |= DISPPLANE_8BPP;
2088 break;
2089 case 16:
2090 if (fb->depth != 16)
2091 return -EINVAL;
2092
2093 dspcntr |= DISPPLANE_16BPP;
2094 break;
2095 case 24:
2096 case 32:
2097 if (fb->depth == 24)
2098 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099 else if (fb->depth == 30)
2100 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101 else
2102 return -EINVAL;
2103 break;
2104 default:
2105 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106 return -EINVAL;
2107 }
2108
2109 if (obj->tiling_mode != I915_TILING_NONE)
2110 dspcntr |= DISPPLANE_TILED;
2111 else
2112 dspcntr &= ~DISPPLANE_TILED;
2113
2114 /* must disable */
2115 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117 I915_WRITE(reg, dspcntr);
2118
2119 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2120 intel_crtc->dspaddr_offset =
2121 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122 fb->bits_per_pixel / 8,
2123 fb->pitches[0]);
2124 linear_offset -= intel_crtc->dspaddr_offset;
2125
2126 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2128 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2129 I915_MODIFY_DISPBASE(DSPSURF(plane),
2130 obj->gtt_offset + intel_crtc->dspaddr_offset);
2131 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2132 I915_WRITE(DSPLINOFF(plane), linear_offset);
2133 POSTING_READ(reg);
2134
2135 return 0;
2136 }
2137
2138 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2139 static int
2140 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141 int x, int y, enum mode_set_atomic state)
2142 {
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146 if (dev_priv->display.disable_fbc)
2147 dev_priv->display.disable_fbc(dev);
2148 intel_increase_pllclock(crtc);
2149
2150 return dev_priv->display.update_plane(crtc, fb, x, y);
2151 }
2152
2153 static int
2154 intel_finish_fb(struct drm_framebuffer *old_fb)
2155 {
2156 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158 bool was_interruptible = dev_priv->mm.interruptible;
2159 int ret;
2160
2161 wait_event(dev_priv->pending_flip_queue,
2162 atomic_read(&dev_priv->mm.wedged) ||
2163 atomic_read(&obj->pending_flip) == 0);
2164
2165 /* Big Hammer, we also need to ensure that any pending
2166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167 * current scanout is retired before unpinning the old
2168 * framebuffer.
2169 *
2170 * This should only fail upon a hung GPU, in which case we
2171 * can safely continue.
2172 */
2173 dev_priv->mm.interruptible = false;
2174 ret = i915_gem_object_finish_gpu(obj);
2175 dev_priv->mm.interruptible = was_interruptible;
2176
2177 return ret;
2178 }
2179
2180 static int
2181 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2182 struct drm_framebuffer *fb)
2183 {
2184 struct drm_device *dev = crtc->dev;
2185 struct drm_i915_private *dev_priv = dev->dev_private;
2186 struct drm_i915_master_private *master_priv;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188 struct drm_framebuffer *old_fb;
2189 int ret;
2190
2191 /* no fb bound */
2192 if (!fb) {
2193 DRM_ERROR("No FB bound\n");
2194 return 0;
2195 }
2196
2197 if(intel_crtc->plane > dev_priv->num_pipe) {
2198 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199 intel_crtc->plane,
2200 dev_priv->num_pipe);
2201 return -EINVAL;
2202 }
2203
2204 mutex_lock(&dev->struct_mutex);
2205 ret = intel_pin_and_fence_fb_obj(dev,
2206 to_intel_framebuffer(fb)->obj,
2207 NULL);
2208 if (ret != 0) {
2209 mutex_unlock(&dev->struct_mutex);
2210 DRM_ERROR("pin & fence failed\n");
2211 return ret;
2212 }
2213
2214 if (crtc->fb)
2215 intel_finish_fb(crtc->fb);
2216
2217 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2218 if (ret) {
2219 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2220 mutex_unlock(&dev->struct_mutex);
2221 DRM_ERROR("failed to update base address\n");
2222 return ret;
2223 }
2224
2225 old_fb = crtc->fb;
2226 crtc->fb = fb;
2227 crtc->x = x;
2228 crtc->y = y;
2229
2230 if (old_fb) {
2231 intel_wait_for_vblank(dev, intel_crtc->pipe);
2232 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2233 }
2234
2235 intel_update_fbc(dev);
2236 mutex_unlock(&dev->struct_mutex);
2237
2238 if (!dev->primary->master)
2239 return 0;
2240
2241 master_priv = dev->primary->master->driver_priv;
2242 if (!master_priv->sarea_priv)
2243 return 0;
2244
2245 if (intel_crtc->pipe) {
2246 master_priv->sarea_priv->pipeB_x = x;
2247 master_priv->sarea_priv->pipeB_y = y;
2248 } else {
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
2251 }
2252
2253 return 0;
2254 }
2255
2256 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2257 {
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 dpa_ctl;
2261
2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2263 dpa_ctl = I915_READ(DP_A);
2264 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266 if (clock < 200000) {
2267 u32 temp;
2268 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2274 */
2275 temp = I915_READ(0x4600c);
2276 temp &= 0xffff0000;
2277 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279 temp = I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp | 1);
2281
2282 temp = I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp | (1 << 24));
2284 } else {
2285 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286 }
2287 I915_WRITE(DP_A, dpa_ctl);
2288
2289 POSTING_READ(DP_A);
2290 udelay(500);
2291 }
2292
2293 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294 {
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 int pipe = intel_crtc->pipe;
2299 u32 reg, temp;
2300
2301 /* enable normal train */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
2304 if (IS_IVYBRIDGE(dev)) {
2305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2310 }
2311 I915_WRITE(reg, temp);
2312
2313 reg = FDI_RX_CTL(pipe);
2314 temp = I915_READ(reg);
2315 if (HAS_PCH_CPT(dev)) {
2316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318 } else {
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_NONE;
2321 }
2322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324 /* wait one idle pattern time */
2325 POSTING_READ(reg);
2326 udelay(1000);
2327
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev))
2330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331 FDI_FE_ERRC_ENABLE);
2332 }
2333
2334 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335 {
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339 flags |= FDI_PHASE_SYNC_OVR(pipe);
2340 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341 flags |= FDI_PHASE_SYNC_EN(pipe);
2342 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1);
2344 }
2345
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348 {
2349 struct drm_device *dev = crtc->dev;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352 int pipe = intel_crtc->pipe;
2353 int plane = intel_crtc->plane;
2354 u32 reg, temp, tries;
2355
2356 /* FDI needs bits from pipe & plane first */
2357 assert_pipe_enabled(dev_priv, pipe);
2358 assert_plane_enabled(dev_priv, plane);
2359
2360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361 for train result */
2362 reg = FDI_RX_IMR(pipe);
2363 temp = I915_READ(reg);
2364 temp &= ~FDI_RX_SYMBOL_LOCK;
2365 temp &= ~FDI_RX_BIT_LOCK;
2366 I915_WRITE(reg, temp);
2367 I915_READ(reg);
2368 udelay(150);
2369
2370 /* enable CPU FDI TX and PCH FDI RX */
2371 reg = FDI_TX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 temp &= ~(7 << 19);
2374 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2375 temp &= ~FDI_LINK_TRAIN_NONE;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1;
2377 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2378
2379 reg = FDI_RX_CTL(pipe);
2380 temp = I915_READ(reg);
2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1;
2383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385 POSTING_READ(reg);
2386 udelay(150);
2387
2388 /* Ironlake workaround, enable clock pointer after FDI enable*/
2389 if (HAS_PCH_IBX(dev)) {
2390 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392 FDI_RX_PHASE_SYNC_POINTER_EN);
2393 }
2394
2395 reg = FDI_RX_IIR(pipe);
2396 for (tries = 0; tries < 5; tries++) {
2397 temp = I915_READ(reg);
2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if ((temp & FDI_RX_BIT_LOCK)) {
2401 DRM_DEBUG_KMS("FDI train 1 done.\n");
2402 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2403 break;
2404 }
2405 }
2406 if (tries == 5)
2407 DRM_ERROR("FDI train 1 fail!\n");
2408
2409 /* Train 2 */
2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_2;
2414 I915_WRITE(reg, temp);
2415
2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_PATTERN_2;
2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
2423 udelay(150);
2424
2425 reg = FDI_RX_IIR(pipe);
2426 for (tries = 0; tries < 5; tries++) {
2427 temp = I915_READ(reg);
2428 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430 if (temp & FDI_RX_SYMBOL_LOCK) {
2431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432 DRM_DEBUG_KMS("FDI train 2 done.\n");
2433 break;
2434 }
2435 }
2436 if (tries == 5)
2437 DRM_ERROR("FDI train 2 fail!\n");
2438
2439 DRM_DEBUG_KMS("FDI train done\n");
2440
2441 }
2442
2443 static const int snb_b_fdi_train_param[] = {
2444 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448 };
2449
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
2457 u32 reg, temp, i, retry;
2458
2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460 for train result */
2461 reg = FDI_RX_IMR(pipe);
2462 temp = I915_READ(reg);
2463 temp &= ~FDI_RX_SYMBOL_LOCK;
2464 temp &= ~FDI_RX_BIT_LOCK;
2465 I915_WRITE(reg, temp);
2466
2467 POSTING_READ(reg);
2468 udelay(150);
2469
2470 /* enable CPU FDI TX and PCH FDI RX */
2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~(7 << 19);
2474 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475 temp &= ~FDI_LINK_TRAIN_NONE;
2476 temp |= FDI_LINK_TRAIN_PATTERN_1;
2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 /* SNB-B */
2479 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2480 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481
2482 reg = FDI_RX_CTL(pipe);
2483 temp = I915_READ(reg);
2484 if (HAS_PCH_CPT(dev)) {
2485 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2486 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2487 } else {
2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 }
2491 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493 POSTING_READ(reg);
2494 udelay(150);
2495
2496 if (HAS_PCH_CPT(dev))
2497 cpt_phase_pointer_enable(dev, pipe);
2498
2499 for (i = 0; i < 4; i++) {
2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 temp |= snb_b_fdi_train_param[i];
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(500);
2508
2509 for (retry = 0; retry < 5; retry++) {
2510 reg = FDI_RX_IIR(pipe);
2511 temp = I915_READ(reg);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513 if (temp & FDI_RX_BIT_LOCK) {
2514 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2515 DRM_DEBUG_KMS("FDI train 1 done.\n");
2516 break;
2517 }
2518 udelay(50);
2519 }
2520 if (retry < 5)
2521 break;
2522 }
2523 if (i == 4)
2524 DRM_ERROR("FDI train 1 fail!\n");
2525
2526 /* Train 2 */
2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
2531 if (IS_GEN6(dev)) {
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535 }
2536 I915_WRITE(reg, temp);
2537
2538 reg = FDI_RX_CTL(pipe);
2539 temp = I915_READ(reg);
2540 if (HAS_PCH_CPT(dev)) {
2541 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2542 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2543 } else {
2544 temp &= ~FDI_LINK_TRAIN_NONE;
2545 temp |= FDI_LINK_TRAIN_PATTERN_2;
2546 }
2547 I915_WRITE(reg, temp);
2548
2549 POSTING_READ(reg);
2550 udelay(150);
2551
2552 for (i = 0; i < 4; i++) {
2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
2555 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2556 temp |= snb_b_fdi_train_param[i];
2557 I915_WRITE(reg, temp);
2558
2559 POSTING_READ(reg);
2560 udelay(500);
2561
2562 for (retry = 0; retry < 5; retry++) {
2563 reg = FDI_RX_IIR(pipe);
2564 temp = I915_READ(reg);
2565 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2566 if (temp & FDI_RX_SYMBOL_LOCK) {
2567 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2568 DRM_DEBUG_KMS("FDI train 2 done.\n");
2569 break;
2570 }
2571 udelay(50);
2572 }
2573 if (retry < 5)
2574 break;
2575 }
2576 if (i == 4)
2577 DRM_ERROR("FDI train 2 fail!\n");
2578
2579 DRM_DEBUG_KMS("FDI train done.\n");
2580 }
2581
2582 /* Manual link training for Ivy Bridge A0 parts */
2583 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2584 {
2585 struct drm_device *dev = crtc->dev;
2586 struct drm_i915_private *dev_priv = dev->dev_private;
2587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2588 int pipe = intel_crtc->pipe;
2589 u32 reg, temp, i;
2590
2591 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2592 for train result */
2593 reg = FDI_RX_IMR(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_RX_SYMBOL_LOCK;
2596 temp &= ~FDI_RX_BIT_LOCK;
2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
2600 udelay(150);
2601
2602 /* enable CPU FDI TX and PCH FDI RX */
2603 reg = FDI_TX_CTL(pipe);
2604 temp = I915_READ(reg);
2605 temp &= ~(7 << 19);
2606 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2607 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2608 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2611 temp |= FDI_COMPOSITE_SYNC;
2612 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2613
2614 reg = FDI_RX_CTL(pipe);
2615 temp = I915_READ(reg);
2616 temp &= ~FDI_LINK_TRAIN_AUTO;
2617 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2619 temp |= FDI_COMPOSITE_SYNC;
2620 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2621
2622 POSTING_READ(reg);
2623 udelay(150);
2624
2625 if (HAS_PCH_CPT(dev))
2626 cpt_phase_pointer_enable(dev, pipe);
2627
2628 for (i = 0; i < 4; i++) {
2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_BIT_LOCK ||
2643 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2644 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2645 DRM_DEBUG_KMS("FDI train 1 done.\n");
2646 break;
2647 }
2648 }
2649 if (i == 4)
2650 DRM_ERROR("FDI train 1 fail!\n");
2651
2652 /* Train 2 */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2656 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2657 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2659 I915_WRITE(reg, temp);
2660
2661 reg = FDI_RX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2664 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 udelay(150);
2669
2670 for (i = 0; i < 4; i++) {
2671 reg = FDI_TX_CTL(pipe);
2672 temp = I915_READ(reg);
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= snb_b_fdi_train_param[i];
2675 I915_WRITE(reg, temp);
2676
2677 POSTING_READ(reg);
2678 udelay(500);
2679
2680 reg = FDI_RX_IIR(pipe);
2681 temp = I915_READ(reg);
2682 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2683
2684 if (temp & FDI_RX_SYMBOL_LOCK) {
2685 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2686 DRM_DEBUG_KMS("FDI train 2 done.\n");
2687 break;
2688 }
2689 }
2690 if (i == 4)
2691 DRM_ERROR("FDI train 2 fail!\n");
2692
2693 DRM_DEBUG_KMS("FDI train done.\n");
2694 }
2695
2696 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2697 {
2698 struct drm_device *dev = intel_crtc->base.dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 int pipe = intel_crtc->pipe;
2701 u32 reg, temp;
2702
2703
2704 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2705 reg = FDI_RX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~((0x7 << 19) | (0x7 << 16));
2708 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2709 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2710 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2711
2712 POSTING_READ(reg);
2713 udelay(200);
2714
2715 /* Switch from Rawclk to PCDclk */
2716 temp = I915_READ(reg);
2717 I915_WRITE(reg, temp | FDI_PCDCLK);
2718
2719 POSTING_READ(reg);
2720 udelay(200);
2721
2722 /* On Haswell, the PLL configuration for ports and pipes is handled
2723 * separately, as part of DDI setup */
2724 if (!IS_HASWELL(dev)) {
2725 /* Enable CPU FDI TX PLL, always on for Ironlake */
2726 reg = FDI_TX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2729 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
2732 udelay(100);
2733 }
2734 }
2735 }
2736
2737 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2738 {
2739 struct drm_device *dev = intel_crtc->base.dev;
2740 struct drm_i915_private *dev_priv = dev->dev_private;
2741 int pipe = intel_crtc->pipe;
2742 u32 reg, temp;
2743
2744 /* Switch from PCDclk to Rawclk */
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2748
2749 /* Disable CPU FDI TX PLL */
2750 reg = FDI_TX_CTL(pipe);
2751 temp = I915_READ(reg);
2752 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2753
2754 POSTING_READ(reg);
2755 udelay(100);
2756
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2760
2761 /* Wait for the clocks to turn off. */
2762 POSTING_READ(reg);
2763 udelay(100);
2764 }
2765
2766 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2767 {
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 u32 flags = I915_READ(SOUTH_CHICKEN1);
2770
2771 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2772 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2773 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2774 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2775 POSTING_READ(SOUTH_CHICKEN1);
2776 }
2777 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2778 {
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 int pipe = intel_crtc->pipe;
2783 u32 reg, temp;
2784
2785 /* disable CPU FDI tx and PCH FDI rx */
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2789 POSTING_READ(reg);
2790
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 temp &= ~(0x7 << 16);
2794 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2795 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2796
2797 POSTING_READ(reg);
2798 udelay(100);
2799
2800 /* Ironlake workaround, disable clock pointer after downing FDI */
2801 if (HAS_PCH_IBX(dev)) {
2802 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2803 I915_WRITE(FDI_RX_CHICKEN(pipe),
2804 I915_READ(FDI_RX_CHICKEN(pipe) &
2805 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2806 } else if (HAS_PCH_CPT(dev)) {
2807 cpt_phase_pointer_disable(dev, pipe);
2808 }
2809
2810 /* still set train pattern 1 */
2811 reg = FDI_TX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 temp &= ~FDI_LINK_TRAIN_NONE;
2814 temp |= FDI_LINK_TRAIN_PATTERN_1;
2815 I915_WRITE(reg, temp);
2816
2817 reg = FDI_RX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 if (HAS_PCH_CPT(dev)) {
2820 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2821 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2822 } else {
2823 temp &= ~FDI_LINK_TRAIN_NONE;
2824 temp |= FDI_LINK_TRAIN_PATTERN_1;
2825 }
2826 /* BPC in FDI rx is consistent with that in PIPECONF */
2827 temp &= ~(0x07 << 16);
2828 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2829 I915_WRITE(reg, temp);
2830
2831 POSTING_READ(reg);
2832 udelay(100);
2833 }
2834
2835 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2836 {
2837 struct drm_device *dev = crtc->dev;
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 unsigned long flags;
2840 bool pending;
2841
2842 if (atomic_read(&dev_priv->mm.wedged))
2843 return false;
2844
2845 spin_lock_irqsave(&dev->event_lock, flags);
2846 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847 spin_unlock_irqrestore(&dev->event_lock, flags);
2848
2849 return pending;
2850 }
2851
2852 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853 {
2854 struct drm_device *dev = crtc->dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857 if (crtc->fb == NULL)
2858 return;
2859
2860 wait_event(dev_priv->pending_flip_queue,
2861 !intel_crtc_has_pending_flip(crtc));
2862
2863 mutex_lock(&dev->struct_mutex);
2864 intel_finish_fb(crtc->fb);
2865 mutex_unlock(&dev->struct_mutex);
2866 }
2867
2868 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2869 {
2870 struct drm_device *dev = crtc->dev;
2871 struct intel_encoder *intel_encoder;
2872
2873 /*
2874 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2875 * must be driven by its own crtc; no sharing is possible.
2876 */
2877 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2878 switch (intel_encoder->type) {
2879 case INTEL_OUTPUT_EDP:
2880 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2881 return false;
2882 continue;
2883 }
2884 }
2885
2886 return true;
2887 }
2888
2889 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2890 {
2891 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2892 }
2893
2894 /* Program iCLKIP clock to the desired frequency */
2895 static void lpt_program_iclkip(struct drm_crtc *crtc)
2896 {
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2900 u32 temp;
2901
2902 /* It is necessary to ungate the pixclk gate prior to programming
2903 * the divisors, and gate it back when it is done.
2904 */
2905 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2906
2907 /* Disable SSCCTL */
2908 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2909 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2910 SBI_SSCCTL_DISABLE);
2911
2912 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913 if (crtc->mode.clock == 20000) {
2914 auxdiv = 1;
2915 divsel = 0x41;
2916 phaseinc = 0x20;
2917 } else {
2918 /* The iCLK virtual clock root frequency is in MHz,
2919 * but the crtc->mode.clock in in KHz. To get the divisors,
2920 * it is necessary to divide one by another, so we
2921 * convert the virtual clock precision to KHz here for higher
2922 * precision.
2923 */
2924 u32 iclk_virtual_root_freq = 172800 * 1000;
2925 u32 iclk_pi_range = 64;
2926 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929 msb_divisor_value = desired_divisor / iclk_pi_range;
2930 pi_value = desired_divisor % iclk_pi_range;
2931
2932 auxdiv = 0;
2933 divsel = msb_divisor_value - 2;
2934 phaseinc = pi_value;
2935 }
2936
2937 /* This should not happen with any sane values */
2938 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944 crtc->mode.clock,
2945 auxdiv,
2946 divsel,
2947 phasedir,
2948 phaseinc);
2949
2950 /* Program SSCDIVINTPHASE6 */
2951 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2952 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2958
2959 intel_sbi_write(dev_priv,
2960 SBI_SSCDIVINTPHASE6,
2961 temp);
2962
2963 /* Program SSCAUXDIV */
2964 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2965 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2966 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2967 intel_sbi_write(dev_priv,
2968 SBI_SSCAUXDIV6,
2969 temp);
2970
2971
2972 /* Enable modulator and associated divider */
2973 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2974 temp &= ~SBI_SSCCTL_DISABLE;
2975 intel_sbi_write(dev_priv,
2976 SBI_SSCCTL6,
2977 temp);
2978
2979 /* Wait for initialization time */
2980 udelay(24);
2981
2982 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2983 }
2984
2985 /*
2986 * Enable PCH resources required for PCH ports:
2987 * - PCH PLLs
2988 * - FDI training & RX/TX
2989 * - update transcoder timings
2990 * - DP transcoding bits
2991 * - transcoder
2992 */
2993 static void ironlake_pch_enable(struct drm_crtc *crtc)
2994 {
2995 struct drm_device *dev = crtc->dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998 int pipe = intel_crtc->pipe;
2999 u32 reg, temp;
3000
3001 assert_transcoder_disabled(dev_priv, pipe);
3002
3003 /* Write the TU size bits before fdi link training, so that error
3004 * detection works. */
3005 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3006 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3007
3008 /* For PCH output, training FDI link */
3009 dev_priv->display.fdi_link_train(crtc);
3010
3011 intel_enable_pch_pll(intel_crtc);
3012
3013 if (HAS_PCH_LPT(dev)) {
3014 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3015 lpt_program_iclkip(crtc);
3016 } else if (HAS_PCH_CPT(dev)) {
3017 u32 sel;
3018
3019 temp = I915_READ(PCH_DPLL_SEL);
3020 switch (pipe) {
3021 default:
3022 case 0:
3023 temp |= TRANSA_DPLL_ENABLE;
3024 sel = TRANSA_DPLLB_SEL;
3025 break;
3026 case 1:
3027 temp |= TRANSB_DPLL_ENABLE;
3028 sel = TRANSB_DPLLB_SEL;
3029 break;
3030 case 2:
3031 temp |= TRANSC_DPLL_ENABLE;
3032 sel = TRANSC_DPLLB_SEL;
3033 break;
3034 }
3035 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3036 temp |= sel;
3037 else
3038 temp &= ~sel;
3039 I915_WRITE(PCH_DPLL_SEL, temp);
3040 }
3041
3042 /* set transcoder timing, panel must allow it */
3043 assert_panel_unlocked(dev_priv, pipe);
3044 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3045 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3046 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3047
3048 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3049 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3050 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3051 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3052
3053 if (!IS_HASWELL(dev))
3054 intel_fdi_normal_train(crtc);
3055
3056 /* For PCH DP, enable TRANS_DP_CTL */
3057 if (HAS_PCH_CPT(dev) &&
3058 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3059 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3060 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3061 reg = TRANS_DP_CTL(pipe);
3062 temp = I915_READ(reg);
3063 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3064 TRANS_DP_SYNC_MASK |
3065 TRANS_DP_BPC_MASK);
3066 temp |= (TRANS_DP_OUTPUT_ENABLE |
3067 TRANS_DP_ENH_FRAMING);
3068 temp |= bpc << 9; /* same format but at 11:9 */
3069
3070 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3071 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3072 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3073 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3074
3075 switch (intel_trans_dp_port_sel(crtc)) {
3076 case PCH_DP_B:
3077 temp |= TRANS_DP_PORT_SEL_B;
3078 break;
3079 case PCH_DP_C:
3080 temp |= TRANS_DP_PORT_SEL_C;
3081 break;
3082 case PCH_DP_D:
3083 temp |= TRANS_DP_PORT_SEL_D;
3084 break;
3085 default:
3086 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3087 temp |= TRANS_DP_PORT_SEL_B;
3088 break;
3089 }
3090
3091 I915_WRITE(reg, temp);
3092 }
3093
3094 intel_enable_transcoder(dev_priv, pipe);
3095 }
3096
3097 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3098 {
3099 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3100
3101 if (pll == NULL)
3102 return;
3103
3104 if (pll->refcount == 0) {
3105 WARN(1, "bad PCH PLL refcount\n");
3106 return;
3107 }
3108
3109 --pll->refcount;
3110 intel_crtc->pch_pll = NULL;
3111 }
3112
3113 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3114 {
3115 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3116 struct intel_pch_pll *pll;
3117 int i;
3118
3119 pll = intel_crtc->pch_pll;
3120 if (pll) {
3121 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3122 intel_crtc->base.base.id, pll->pll_reg);
3123 goto prepare;
3124 }
3125
3126 if (HAS_PCH_IBX(dev_priv->dev)) {
3127 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3128 i = intel_crtc->pipe;
3129 pll = &dev_priv->pch_plls[i];
3130
3131 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3132 intel_crtc->base.base.id, pll->pll_reg);
3133
3134 goto found;
3135 }
3136
3137 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3138 pll = &dev_priv->pch_plls[i];
3139
3140 /* Only want to check enabled timings first */
3141 if (pll->refcount == 0)
3142 continue;
3143
3144 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3145 fp == I915_READ(pll->fp0_reg)) {
3146 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3147 intel_crtc->base.base.id,
3148 pll->pll_reg, pll->refcount, pll->active);
3149
3150 goto found;
3151 }
3152 }
3153
3154 /* Ok no matching timings, maybe there's a free one? */
3155 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3156 pll = &dev_priv->pch_plls[i];
3157 if (pll->refcount == 0) {
3158 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3159 intel_crtc->base.base.id, pll->pll_reg);
3160 goto found;
3161 }
3162 }
3163
3164 return NULL;
3165
3166 found:
3167 intel_crtc->pch_pll = pll;
3168 pll->refcount++;
3169 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3170 prepare: /* separate function? */
3171 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3172
3173 /* Wait for the clocks to stabilize before rewriting the regs */
3174 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3175 POSTING_READ(pll->pll_reg);
3176 udelay(150);
3177
3178 I915_WRITE(pll->fp0_reg, fp);
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180 pll->on = false;
3181 return pll;
3182 }
3183
3184 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3185 {
3186 struct drm_i915_private *dev_priv = dev->dev_private;
3187 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3188 u32 temp;
3189
3190 temp = I915_READ(dslreg);
3191 udelay(500);
3192 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3193 /* Without this, mode sets may fail silently on FDI */
3194 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3195 udelay(250);
3196 I915_WRITE(tc2reg, 0);
3197 if (wait_for(I915_READ(dslreg) != temp, 5))
3198 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3199 }
3200 }
3201
3202 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3203 {
3204 struct drm_device *dev = crtc->dev;
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207 struct intel_encoder *encoder;
3208 int pipe = intel_crtc->pipe;
3209 int plane = intel_crtc->plane;
3210 u32 temp;
3211 bool is_pch_port;
3212
3213 WARN_ON(!crtc->enabled);
3214
3215 if (intel_crtc->active)
3216 return;
3217
3218 intel_crtc->active = true;
3219 intel_update_watermarks(dev);
3220
3221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3222 temp = I915_READ(PCH_LVDS);
3223 if ((temp & LVDS_PORT_EN) == 0)
3224 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3225 }
3226
3227 is_pch_port = ironlake_crtc_driving_pch(crtc);
3228
3229 if (is_pch_port) {
3230 ironlake_fdi_pll_enable(intel_crtc);
3231 } else {
3232 assert_fdi_tx_disabled(dev_priv, pipe);
3233 assert_fdi_rx_disabled(dev_priv, pipe);
3234 }
3235
3236 for_each_encoder_on_crtc(dev, crtc, encoder)
3237 if (encoder->pre_enable)
3238 encoder->pre_enable(encoder);
3239
3240 /* Enable panel fitting for LVDS */
3241 if (dev_priv->pch_pf_size &&
3242 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3243 /* Force use of hard-coded filter coefficients
3244 * as some pre-programmed values are broken,
3245 * e.g. x201.
3246 */
3247 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3248 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3249 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3250 }
3251
3252 /*
3253 * On ILK+ LUT must be loaded before the pipe is running but with
3254 * clocks enabled
3255 */
3256 intel_crtc_load_lut(crtc);
3257
3258 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3259 intel_enable_plane(dev_priv, plane, pipe);
3260
3261 if (is_pch_port)
3262 ironlake_pch_enable(crtc);
3263
3264 mutex_lock(&dev->struct_mutex);
3265 intel_update_fbc(dev);
3266 mutex_unlock(&dev->struct_mutex);
3267
3268 intel_crtc_update_cursor(crtc, true);
3269
3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 encoder->enable(encoder);
3272
3273 if (HAS_PCH_CPT(dev))
3274 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3275
3276 /*
3277 * There seems to be a race in PCH platform hw (at least on some
3278 * outputs) where an enabled pipe still completes any pageflip right
3279 * away (as if the pipe is off) instead of waiting for vblank. As soon
3280 * as the first vblank happend, everything works as expected. Hence just
3281 * wait for one vblank before returning to avoid strange things
3282 * happening.
3283 */
3284 intel_wait_for_vblank(dev, intel_crtc->pipe);
3285 }
3286
3287 static void haswell_crtc_enable(struct drm_crtc *crtc)
3288 {
3289 struct drm_device *dev = crtc->dev;
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292 struct intel_encoder *encoder;
3293 int pipe = intel_crtc->pipe;
3294 int plane = intel_crtc->plane;
3295 bool is_pch_port;
3296
3297 WARN_ON(!crtc->enabled);
3298
3299 if (intel_crtc->active)
3300 return;
3301
3302 intel_crtc->active = true;
3303 intel_update_watermarks(dev);
3304
3305 is_pch_port = haswell_crtc_driving_pch(crtc);
3306
3307 if (is_pch_port)
3308 ironlake_fdi_pll_enable(intel_crtc);
3309
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 if (encoder->pre_enable)
3312 encoder->pre_enable(encoder);
3313
3314 intel_ddi_enable_pipe_clock(intel_crtc);
3315
3316 /* Enable panel fitting for eDP */
3317 if (dev_priv->pch_pf_size && HAS_eDP) {
3318 /* Force use of hard-coded filter coefficients
3319 * as some pre-programmed values are broken,
3320 * e.g. x201.
3321 */
3322 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3323 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3324 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3325 }
3326
3327 /*
3328 * On ILK+ LUT must be loaded before the pipe is running but with
3329 * clocks enabled
3330 */
3331 intel_crtc_load_lut(crtc);
3332
3333 intel_ddi_set_pipe_settings(crtc);
3334 intel_ddi_enable_pipe_func(crtc);
3335
3336 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3337 intel_enable_plane(dev_priv, plane, pipe);
3338
3339 if (is_pch_port)
3340 ironlake_pch_enable(crtc);
3341
3342 mutex_lock(&dev->struct_mutex);
3343 intel_update_fbc(dev);
3344 mutex_unlock(&dev->struct_mutex);
3345
3346 intel_crtc_update_cursor(crtc, true);
3347
3348 for_each_encoder_on_crtc(dev, crtc, encoder)
3349 encoder->enable(encoder);
3350
3351 /*
3352 * There seems to be a race in PCH platform hw (at least on some
3353 * outputs) where an enabled pipe still completes any pageflip right
3354 * away (as if the pipe is off) instead of waiting for vblank. As soon
3355 * as the first vblank happend, everything works as expected. Hence just
3356 * wait for one vblank before returning to avoid strange things
3357 * happening.
3358 */
3359 intel_wait_for_vblank(dev, intel_crtc->pipe);
3360 }
3361
3362 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3363 {
3364 struct drm_device *dev = crtc->dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3367 struct intel_encoder *encoder;
3368 int pipe = intel_crtc->pipe;
3369 int plane = intel_crtc->plane;
3370 u32 reg, temp;
3371
3372
3373 if (!intel_crtc->active)
3374 return;
3375
3376 for_each_encoder_on_crtc(dev, crtc, encoder)
3377 encoder->disable(encoder);
3378
3379 intel_crtc_wait_for_pending_flips(crtc);
3380 drm_vblank_off(dev, pipe);
3381 intel_crtc_update_cursor(crtc, false);
3382
3383 intel_disable_plane(dev_priv, plane, pipe);
3384
3385 if (dev_priv->cfb_plane == plane)
3386 intel_disable_fbc(dev);
3387
3388 intel_disable_pipe(dev_priv, pipe);
3389
3390 /* Disable PF */
3391 I915_WRITE(PF_CTL(pipe), 0);
3392 I915_WRITE(PF_WIN_SZ(pipe), 0);
3393
3394 for_each_encoder_on_crtc(dev, crtc, encoder)
3395 if (encoder->post_disable)
3396 encoder->post_disable(encoder);
3397
3398 ironlake_fdi_disable(crtc);
3399
3400 intel_disable_transcoder(dev_priv, pipe);
3401
3402 if (HAS_PCH_CPT(dev)) {
3403 /* disable TRANS_DP_CTL */
3404 reg = TRANS_DP_CTL(pipe);
3405 temp = I915_READ(reg);
3406 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3407 temp |= TRANS_DP_PORT_SEL_NONE;
3408 I915_WRITE(reg, temp);
3409
3410 /* disable DPLL_SEL */
3411 temp = I915_READ(PCH_DPLL_SEL);
3412 switch (pipe) {
3413 case 0:
3414 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3415 break;
3416 case 1:
3417 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3418 break;
3419 case 2:
3420 /* C shares PLL A or B */
3421 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3422 break;
3423 default:
3424 BUG(); /* wtf */
3425 }
3426 I915_WRITE(PCH_DPLL_SEL, temp);
3427 }
3428
3429 /* disable PCH DPLL */
3430 intel_disable_pch_pll(intel_crtc);
3431
3432 ironlake_fdi_pll_disable(intel_crtc);
3433
3434 intel_crtc->active = false;
3435 intel_update_watermarks(dev);
3436
3437 mutex_lock(&dev->struct_mutex);
3438 intel_update_fbc(dev);
3439 mutex_unlock(&dev->struct_mutex);
3440 }
3441
3442 static void haswell_crtc_disable(struct drm_crtc *crtc)
3443 {
3444 struct drm_device *dev = crtc->dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447 struct intel_encoder *encoder;
3448 int pipe = intel_crtc->pipe;
3449 int plane = intel_crtc->plane;
3450 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3451 bool is_pch_port;
3452
3453 if (!intel_crtc->active)
3454 return;
3455
3456 is_pch_port = haswell_crtc_driving_pch(crtc);
3457
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 encoder->disable(encoder);
3460
3461 intel_crtc_wait_for_pending_flips(crtc);
3462 drm_vblank_off(dev, pipe);
3463 intel_crtc_update_cursor(crtc, false);
3464
3465 intel_disable_plane(dev_priv, plane, pipe);
3466
3467 if (dev_priv->cfb_plane == plane)
3468 intel_disable_fbc(dev);
3469
3470 intel_disable_pipe(dev_priv, pipe);
3471
3472 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3473
3474 /* Disable PF */
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_SZ(pipe), 0);
3477
3478 intel_ddi_disable_pipe_clock(intel_crtc);
3479
3480 for_each_encoder_on_crtc(dev, crtc, encoder)
3481 if (encoder->post_disable)
3482 encoder->post_disable(encoder);
3483
3484 if (is_pch_port) {
3485 ironlake_fdi_disable(crtc);
3486 intel_disable_transcoder(dev_priv, pipe);
3487 intel_disable_pch_pll(intel_crtc);
3488 ironlake_fdi_pll_disable(intel_crtc);
3489 }
3490
3491 intel_crtc->active = false;
3492 intel_update_watermarks(dev);
3493
3494 mutex_lock(&dev->struct_mutex);
3495 intel_update_fbc(dev);
3496 mutex_unlock(&dev->struct_mutex);
3497 }
3498
3499 static void ironlake_crtc_off(struct drm_crtc *crtc)
3500 {
3501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3502 intel_put_pch_pll(intel_crtc);
3503 }
3504
3505 static void haswell_crtc_off(struct drm_crtc *crtc)
3506 {
3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508
3509 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3510 * start using it. */
3511 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3512
3513 intel_ddi_put_crtc_pll(crtc);
3514 }
3515
3516 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3517 {
3518 if (!enable && intel_crtc->overlay) {
3519 struct drm_device *dev = intel_crtc->base.dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521
3522 mutex_lock(&dev->struct_mutex);
3523 dev_priv->mm.interruptible = false;
3524 (void) intel_overlay_switch_off(intel_crtc->overlay);
3525 dev_priv->mm.interruptible = true;
3526 mutex_unlock(&dev->struct_mutex);
3527 }
3528
3529 /* Let userspace switch the overlay on again. In most cases userspace
3530 * has to recompute where to put it anyway.
3531 */
3532 }
3533
3534 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3535 {
3536 struct drm_device *dev = crtc->dev;
3537 struct drm_i915_private *dev_priv = dev->dev_private;
3538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3539 struct intel_encoder *encoder;
3540 int pipe = intel_crtc->pipe;
3541 int plane = intel_crtc->plane;
3542
3543 WARN_ON(!crtc->enabled);
3544
3545 if (intel_crtc->active)
3546 return;
3547
3548 intel_crtc->active = true;
3549 intel_update_watermarks(dev);
3550
3551 intel_enable_pll(dev_priv, pipe);
3552 intel_enable_pipe(dev_priv, pipe, false);
3553 intel_enable_plane(dev_priv, plane, pipe);
3554
3555 intel_crtc_load_lut(crtc);
3556 intel_update_fbc(dev);
3557
3558 /* Give the overlay scaler a chance to enable if it's on this pipe */
3559 intel_crtc_dpms_overlay(intel_crtc, true);
3560 intel_crtc_update_cursor(crtc, true);
3561
3562 for_each_encoder_on_crtc(dev, crtc, encoder)
3563 encoder->enable(encoder);
3564 }
3565
3566 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3567 {
3568 struct drm_device *dev = crtc->dev;
3569 struct drm_i915_private *dev_priv = dev->dev_private;
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571 struct intel_encoder *encoder;
3572 int pipe = intel_crtc->pipe;
3573 int plane = intel_crtc->plane;
3574
3575
3576 if (!intel_crtc->active)
3577 return;
3578
3579 for_each_encoder_on_crtc(dev, crtc, encoder)
3580 encoder->disable(encoder);
3581
3582 /* Give the overlay scaler a chance to disable if it's on this pipe */
3583 intel_crtc_wait_for_pending_flips(crtc);
3584 drm_vblank_off(dev, pipe);
3585 intel_crtc_dpms_overlay(intel_crtc, false);
3586 intel_crtc_update_cursor(crtc, false);
3587
3588 if (dev_priv->cfb_plane == plane)
3589 intel_disable_fbc(dev);
3590
3591 intel_disable_plane(dev_priv, plane, pipe);
3592 intel_disable_pipe(dev_priv, pipe);
3593 intel_disable_pll(dev_priv, pipe);
3594
3595 intel_crtc->active = false;
3596 intel_update_fbc(dev);
3597 intel_update_watermarks(dev);
3598 }
3599
3600 static void i9xx_crtc_off(struct drm_crtc *crtc)
3601 {
3602 }
3603
3604 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3605 bool enabled)
3606 {
3607 struct drm_device *dev = crtc->dev;
3608 struct drm_i915_master_private *master_priv;
3609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3610 int pipe = intel_crtc->pipe;
3611
3612 if (!dev->primary->master)
3613 return;
3614
3615 master_priv = dev->primary->master->driver_priv;
3616 if (!master_priv->sarea_priv)
3617 return;
3618
3619 switch (pipe) {
3620 case 0:
3621 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3622 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3623 break;
3624 case 1:
3625 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3626 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3627 break;
3628 default:
3629 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3630 break;
3631 }
3632 }
3633
3634 /**
3635 * Sets the power management mode of the pipe and plane.
3636 */
3637 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3638 {
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 struct intel_encoder *intel_encoder;
3642 bool enable = false;
3643
3644 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3645 enable |= intel_encoder->connectors_active;
3646
3647 if (enable)
3648 dev_priv->display.crtc_enable(crtc);
3649 else
3650 dev_priv->display.crtc_disable(crtc);
3651
3652 intel_crtc_update_sarea(crtc, enable);
3653 }
3654
3655 static void intel_crtc_noop(struct drm_crtc *crtc)
3656 {
3657 }
3658
3659 static void intel_crtc_disable(struct drm_crtc *crtc)
3660 {
3661 struct drm_device *dev = crtc->dev;
3662 struct drm_connector *connector;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664
3665 /* crtc should still be enabled when we disable it. */
3666 WARN_ON(!crtc->enabled);
3667
3668 dev_priv->display.crtc_disable(crtc);
3669 intel_crtc_update_sarea(crtc, false);
3670 dev_priv->display.off(crtc);
3671
3672 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3673 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3674
3675 if (crtc->fb) {
3676 mutex_lock(&dev->struct_mutex);
3677 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3678 mutex_unlock(&dev->struct_mutex);
3679 crtc->fb = NULL;
3680 }
3681
3682 /* Update computed state. */
3683 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3684 if (!connector->encoder || !connector->encoder->crtc)
3685 continue;
3686
3687 if (connector->encoder->crtc != crtc)
3688 continue;
3689
3690 connector->dpms = DRM_MODE_DPMS_OFF;
3691 to_intel_encoder(connector->encoder)->connectors_active = false;
3692 }
3693 }
3694
3695 void intel_modeset_disable(struct drm_device *dev)
3696 {
3697 struct drm_crtc *crtc;
3698
3699 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3700 if (crtc->enabled)
3701 intel_crtc_disable(crtc);
3702 }
3703 }
3704
3705 void intel_encoder_noop(struct drm_encoder *encoder)
3706 {
3707 }
3708
3709 void intel_encoder_destroy(struct drm_encoder *encoder)
3710 {
3711 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3712
3713 drm_encoder_cleanup(encoder);
3714 kfree(intel_encoder);
3715 }
3716
3717 /* Simple dpms helper for encodres with just one connector, no cloning and only
3718 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3719 * state of the entire output pipe. */
3720 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3721 {
3722 if (mode == DRM_MODE_DPMS_ON) {
3723 encoder->connectors_active = true;
3724
3725 intel_crtc_update_dpms(encoder->base.crtc);
3726 } else {
3727 encoder->connectors_active = false;
3728
3729 intel_crtc_update_dpms(encoder->base.crtc);
3730 }
3731 }
3732
3733 /* Cross check the actual hw state with our own modeset state tracking (and it's
3734 * internal consistency). */
3735 static void intel_connector_check_state(struct intel_connector *connector)
3736 {
3737 if (connector->get_hw_state(connector)) {
3738 struct intel_encoder *encoder = connector->encoder;
3739 struct drm_crtc *crtc;
3740 bool encoder_enabled;
3741 enum pipe pipe;
3742
3743 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3744 connector->base.base.id,
3745 drm_get_connector_name(&connector->base));
3746
3747 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3748 "wrong connector dpms state\n");
3749 WARN(connector->base.encoder != &encoder->base,
3750 "active connector not linked to encoder\n");
3751 WARN(!encoder->connectors_active,
3752 "encoder->connectors_active not set\n");
3753
3754 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3755 WARN(!encoder_enabled, "encoder not enabled\n");
3756 if (WARN_ON(!encoder->base.crtc))
3757 return;
3758
3759 crtc = encoder->base.crtc;
3760
3761 WARN(!crtc->enabled, "crtc not enabled\n");
3762 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3763 WARN(pipe != to_intel_crtc(crtc)->pipe,
3764 "encoder active on the wrong pipe\n");
3765 }
3766 }
3767
3768 /* Even simpler default implementation, if there's really no special case to
3769 * consider. */
3770 void intel_connector_dpms(struct drm_connector *connector, int mode)
3771 {
3772 struct intel_encoder *encoder = intel_attached_encoder(connector);
3773
3774 /* All the simple cases only support two dpms states. */
3775 if (mode != DRM_MODE_DPMS_ON)
3776 mode = DRM_MODE_DPMS_OFF;
3777
3778 if (mode == connector->dpms)
3779 return;
3780
3781 connector->dpms = mode;
3782
3783 /* Only need to change hw state when actually enabled */
3784 if (encoder->base.crtc)
3785 intel_encoder_dpms(encoder, mode);
3786 else
3787 WARN_ON(encoder->connectors_active != false);
3788
3789 intel_modeset_check_state(connector->dev);
3790 }
3791
3792 /* Simple connector->get_hw_state implementation for encoders that support only
3793 * one connector and no cloning and hence the encoder state determines the state
3794 * of the connector. */
3795 bool intel_connector_get_hw_state(struct intel_connector *connector)
3796 {
3797 enum pipe pipe = 0;
3798 struct intel_encoder *encoder = connector->encoder;
3799
3800 return encoder->get_hw_state(encoder, &pipe);
3801 }
3802
3803 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3804 const struct drm_display_mode *mode,
3805 struct drm_display_mode *adjusted_mode)
3806 {
3807 struct drm_device *dev = crtc->dev;
3808
3809 if (HAS_PCH_SPLIT(dev)) {
3810 /* FDI link clock is fixed at 2.7G */
3811 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3812 return false;
3813 }
3814
3815 /* All interlaced capable intel hw wants timings in frames. Note though
3816 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3817 * timings, so we need to be careful not to clobber these.*/
3818 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3819 drm_mode_set_crtcinfo(adjusted_mode, 0);
3820
3821 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3822 * with a hsync front porch of 0.
3823 */
3824 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3825 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3826 return false;
3827
3828 return true;
3829 }
3830
3831 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3832 {
3833 return 400000; /* FIXME */
3834 }
3835
3836 static int i945_get_display_clock_speed(struct drm_device *dev)
3837 {
3838 return 400000;
3839 }
3840
3841 static int i915_get_display_clock_speed(struct drm_device *dev)
3842 {
3843 return 333000;
3844 }
3845
3846 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3847 {
3848 return 200000;
3849 }
3850
3851 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3852 {
3853 u16 gcfgc = 0;
3854
3855 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3856
3857 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3858 return 133000;
3859 else {
3860 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3861 case GC_DISPLAY_CLOCK_333_MHZ:
3862 return 333000;
3863 default:
3864 case GC_DISPLAY_CLOCK_190_200_MHZ:
3865 return 190000;
3866 }
3867 }
3868 }
3869
3870 static int i865_get_display_clock_speed(struct drm_device *dev)
3871 {
3872 return 266000;
3873 }
3874
3875 static int i855_get_display_clock_speed(struct drm_device *dev)
3876 {
3877 u16 hpllcc = 0;
3878 /* Assume that the hardware is in the high speed state. This
3879 * should be the default.
3880 */
3881 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3882 case GC_CLOCK_133_200:
3883 case GC_CLOCK_100_200:
3884 return 200000;
3885 case GC_CLOCK_166_250:
3886 return 250000;
3887 case GC_CLOCK_100_133:
3888 return 133000;
3889 }
3890
3891 /* Shouldn't happen */
3892 return 0;
3893 }
3894
3895 static int i830_get_display_clock_speed(struct drm_device *dev)
3896 {
3897 return 133000;
3898 }
3899
3900 struct fdi_m_n {
3901 u32 tu;
3902 u32 gmch_m;
3903 u32 gmch_n;
3904 u32 link_m;
3905 u32 link_n;
3906 };
3907
3908 static void
3909 fdi_reduce_ratio(u32 *num, u32 *den)
3910 {
3911 while (*num > 0xffffff || *den > 0xffffff) {
3912 *num >>= 1;
3913 *den >>= 1;
3914 }
3915 }
3916
3917 static void
3918 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3919 int link_clock, struct fdi_m_n *m_n)
3920 {
3921 m_n->tu = 64; /* default size */
3922
3923 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3924 m_n->gmch_m = bits_per_pixel * pixel_clock;
3925 m_n->gmch_n = link_clock * nlanes * 8;
3926 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3927
3928 m_n->link_m = pixel_clock;
3929 m_n->link_n = link_clock;
3930 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3931 }
3932
3933 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3934 {
3935 if (i915_panel_use_ssc >= 0)
3936 return i915_panel_use_ssc != 0;
3937 return dev_priv->lvds_use_ssc
3938 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3939 }
3940
3941 /**
3942 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3943 * @crtc: CRTC structure
3944 * @mode: requested mode
3945 *
3946 * A pipe may be connected to one or more outputs. Based on the depth of the
3947 * attached framebuffer, choose a good color depth to use on the pipe.
3948 *
3949 * If possible, match the pipe depth to the fb depth. In some cases, this
3950 * isn't ideal, because the connected output supports a lesser or restricted
3951 * set of depths. Resolve that here:
3952 * LVDS typically supports only 6bpc, so clamp down in that case
3953 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3954 * Displays may support a restricted set as well, check EDID and clamp as
3955 * appropriate.
3956 * DP may want to dither down to 6bpc to fit larger modes
3957 *
3958 * RETURNS:
3959 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3960 * true if they don't match).
3961 */
3962 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3963 struct drm_framebuffer *fb,
3964 unsigned int *pipe_bpp,
3965 struct drm_display_mode *mode)
3966 {
3967 struct drm_device *dev = crtc->dev;
3968 struct drm_i915_private *dev_priv = dev->dev_private;
3969 struct drm_connector *connector;
3970 struct intel_encoder *intel_encoder;
3971 unsigned int display_bpc = UINT_MAX, bpc;
3972
3973 /* Walk the encoders & connectors on this crtc, get min bpc */
3974 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3975
3976 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3977 unsigned int lvds_bpc;
3978
3979 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3980 LVDS_A3_POWER_UP)
3981 lvds_bpc = 8;
3982 else
3983 lvds_bpc = 6;
3984
3985 if (lvds_bpc < display_bpc) {
3986 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3987 display_bpc = lvds_bpc;
3988 }
3989 continue;
3990 }
3991
3992 /* Not one of the known troublemakers, check the EDID */
3993 list_for_each_entry(connector, &dev->mode_config.connector_list,
3994 head) {
3995 if (connector->encoder != &intel_encoder->base)
3996 continue;
3997
3998 /* Don't use an invalid EDID bpc value */
3999 if (connector->display_info.bpc &&
4000 connector->display_info.bpc < display_bpc) {
4001 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4002 display_bpc = connector->display_info.bpc;
4003 }
4004 }
4005
4006 /*
4007 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4008 * through, clamp it down. (Note: >12bpc will be caught below.)
4009 */
4010 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4011 if (display_bpc > 8 && display_bpc < 12) {
4012 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4013 display_bpc = 12;
4014 } else {
4015 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4016 display_bpc = 8;
4017 }
4018 }
4019 }
4020
4021 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4022 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4023 display_bpc = 6;
4024 }
4025
4026 /*
4027 * We could just drive the pipe at the highest bpc all the time and
4028 * enable dithering as needed, but that costs bandwidth. So choose
4029 * the minimum value that expresses the full color range of the fb but
4030 * also stays within the max display bpc discovered above.
4031 */
4032
4033 switch (fb->depth) {
4034 case 8:
4035 bpc = 8; /* since we go through a colormap */
4036 break;
4037 case 15:
4038 case 16:
4039 bpc = 6; /* min is 18bpp */
4040 break;
4041 case 24:
4042 bpc = 8;
4043 break;
4044 case 30:
4045 bpc = 10;
4046 break;
4047 case 48:
4048 bpc = 12;
4049 break;
4050 default:
4051 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4052 bpc = min((unsigned int)8, display_bpc);
4053 break;
4054 }
4055
4056 display_bpc = min(display_bpc, bpc);
4057
4058 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4059 bpc, display_bpc);
4060
4061 *pipe_bpp = display_bpc * 3;
4062
4063 return display_bpc != bpc;
4064 }
4065
4066 static int vlv_get_refclk(struct drm_crtc *crtc)
4067 {
4068 struct drm_device *dev = crtc->dev;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 int refclk = 27000; /* for DP & HDMI */
4071
4072 return 100000; /* only one validated so far */
4073
4074 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4075 refclk = 96000;
4076 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4077 if (intel_panel_use_ssc(dev_priv))
4078 refclk = 100000;
4079 else
4080 refclk = 96000;
4081 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4082 refclk = 100000;
4083 }
4084
4085 return refclk;
4086 }
4087
4088 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4089 {
4090 struct drm_device *dev = crtc->dev;
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 int refclk;
4093
4094 if (IS_VALLEYVIEW(dev)) {
4095 refclk = vlv_get_refclk(crtc);
4096 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4097 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4098 refclk = dev_priv->lvds_ssc_freq * 1000;
4099 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4100 refclk / 1000);
4101 } else if (!IS_GEN2(dev)) {
4102 refclk = 96000;
4103 } else {
4104 refclk = 48000;
4105 }
4106
4107 return refclk;
4108 }
4109
4110 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4111 intel_clock_t *clock)
4112 {
4113 /* SDVO TV has fixed PLL values depend on its clock range,
4114 this mirrors vbios setting. */
4115 if (adjusted_mode->clock >= 100000
4116 && adjusted_mode->clock < 140500) {
4117 clock->p1 = 2;
4118 clock->p2 = 10;
4119 clock->n = 3;
4120 clock->m1 = 16;
4121 clock->m2 = 8;
4122 } else if (adjusted_mode->clock >= 140500
4123 && adjusted_mode->clock <= 200000) {
4124 clock->p1 = 1;
4125 clock->p2 = 10;
4126 clock->n = 6;
4127 clock->m1 = 12;
4128 clock->m2 = 8;
4129 }
4130 }
4131
4132 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4133 intel_clock_t *clock,
4134 intel_clock_t *reduced_clock)
4135 {
4136 struct drm_device *dev = crtc->dev;
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139 int pipe = intel_crtc->pipe;
4140 u32 fp, fp2 = 0;
4141
4142 if (IS_PINEVIEW(dev)) {
4143 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4144 if (reduced_clock)
4145 fp2 = (1 << reduced_clock->n) << 16 |
4146 reduced_clock->m1 << 8 | reduced_clock->m2;
4147 } else {
4148 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4149 if (reduced_clock)
4150 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4151 reduced_clock->m2;
4152 }
4153
4154 I915_WRITE(FP0(pipe), fp);
4155
4156 intel_crtc->lowfreq_avail = false;
4157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4158 reduced_clock && i915_powersave) {
4159 I915_WRITE(FP1(pipe), fp2);
4160 intel_crtc->lowfreq_avail = true;
4161 } else {
4162 I915_WRITE(FP1(pipe), fp);
4163 }
4164 }
4165
4166 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4167 struct drm_display_mode *adjusted_mode)
4168 {
4169 struct drm_device *dev = crtc->dev;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4172 int pipe = intel_crtc->pipe;
4173 u32 temp;
4174
4175 temp = I915_READ(LVDS);
4176 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4177 if (pipe == 1) {
4178 temp |= LVDS_PIPEB_SELECT;
4179 } else {
4180 temp &= ~LVDS_PIPEB_SELECT;
4181 }
4182 /* set the corresponsding LVDS_BORDER bit */
4183 temp |= dev_priv->lvds_border_bits;
4184 /* Set the B0-B3 data pairs corresponding to whether we're going to
4185 * set the DPLLs for dual-channel mode or not.
4186 */
4187 if (clock->p2 == 7)
4188 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4189 else
4190 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4191
4192 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4193 * appropriately here, but we need to look more thoroughly into how
4194 * panels behave in the two modes.
4195 */
4196 /* set the dithering flag on LVDS as needed */
4197 if (INTEL_INFO(dev)->gen >= 4) {
4198 if (dev_priv->lvds_dither)
4199 temp |= LVDS_ENABLE_DITHER;
4200 else
4201 temp &= ~LVDS_ENABLE_DITHER;
4202 }
4203 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4204 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4205 temp |= LVDS_HSYNC_POLARITY;
4206 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4207 temp |= LVDS_VSYNC_POLARITY;
4208 I915_WRITE(LVDS, temp);
4209 }
4210
4211 static void vlv_update_pll(struct drm_crtc *crtc,
4212 struct drm_display_mode *mode,
4213 struct drm_display_mode *adjusted_mode,
4214 intel_clock_t *clock, intel_clock_t *reduced_clock,
4215 int num_connectors)
4216 {
4217 struct drm_device *dev = crtc->dev;
4218 struct drm_i915_private *dev_priv = dev->dev_private;
4219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4220 int pipe = intel_crtc->pipe;
4221 u32 dpll, mdiv, pdiv;
4222 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4223 bool is_sdvo;
4224 u32 temp;
4225
4226 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4227 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4228
4229 dpll = DPLL_VGA_MODE_DIS;
4230 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4231 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4232 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4233
4234 I915_WRITE(DPLL(pipe), dpll);
4235 POSTING_READ(DPLL(pipe));
4236
4237 bestn = clock->n;
4238 bestm1 = clock->m1;
4239 bestm2 = clock->m2;
4240 bestp1 = clock->p1;
4241 bestp2 = clock->p2;
4242
4243 /*
4244 * In Valleyview PLL and program lane counter registers are exposed
4245 * through DPIO interface
4246 */
4247 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4248 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4249 mdiv |= ((bestn << DPIO_N_SHIFT));
4250 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4251 mdiv |= (1 << DPIO_K_SHIFT);
4252 mdiv |= DPIO_ENABLE_CALIBRATION;
4253 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4254
4255 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4256
4257 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4258 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4259 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4260 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4261 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4262
4263 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4264
4265 dpll |= DPLL_VCO_ENABLE;
4266 I915_WRITE(DPLL(pipe), dpll);
4267 POSTING_READ(DPLL(pipe));
4268 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4269 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4270
4271 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4272
4273 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4274 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4275
4276 I915_WRITE(DPLL(pipe), dpll);
4277
4278 /* Wait for the clocks to stabilize. */
4279 POSTING_READ(DPLL(pipe));
4280 udelay(150);
4281
4282 temp = 0;
4283 if (is_sdvo) {
4284 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4285 if (temp > 1)
4286 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4287 else
4288 temp = 0;
4289 }
4290 I915_WRITE(DPLL_MD(pipe), temp);
4291 POSTING_READ(DPLL_MD(pipe));
4292
4293 /* Now program lane control registers */
4294 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4295 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4296 {
4297 temp = 0x1000C4;
4298 if(pipe == 1)
4299 temp |= (1 << 21);
4300 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4301 }
4302 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4303 {
4304 temp = 0x1000C4;
4305 if(pipe == 1)
4306 temp |= (1 << 21);
4307 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4308 }
4309 }
4310
4311 static void i9xx_update_pll(struct drm_crtc *crtc,
4312 struct drm_display_mode *mode,
4313 struct drm_display_mode *adjusted_mode,
4314 intel_clock_t *clock, intel_clock_t *reduced_clock,
4315 int num_connectors)
4316 {
4317 struct drm_device *dev = crtc->dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320 int pipe = intel_crtc->pipe;
4321 u32 dpll;
4322 bool is_sdvo;
4323
4324 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4325
4326 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4327 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4328
4329 dpll = DPLL_VGA_MODE_DIS;
4330
4331 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4332 dpll |= DPLLB_MODE_LVDS;
4333 else
4334 dpll |= DPLLB_MODE_DAC_SERIAL;
4335 if (is_sdvo) {
4336 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4337 if (pixel_multiplier > 1) {
4338 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4339 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4340 }
4341 dpll |= DPLL_DVO_HIGH_SPEED;
4342 }
4343 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4344 dpll |= DPLL_DVO_HIGH_SPEED;
4345
4346 /* compute bitmask from p1 value */
4347 if (IS_PINEVIEW(dev))
4348 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4349 else {
4350 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4351 if (IS_G4X(dev) && reduced_clock)
4352 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4353 }
4354 switch (clock->p2) {
4355 case 5:
4356 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4357 break;
4358 case 7:
4359 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4360 break;
4361 case 10:
4362 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4363 break;
4364 case 14:
4365 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4366 break;
4367 }
4368 if (INTEL_INFO(dev)->gen >= 4)
4369 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4370
4371 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4372 dpll |= PLL_REF_INPUT_TVCLKINBC;
4373 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4374 /* XXX: just matching BIOS for now */
4375 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4376 dpll |= 3;
4377 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4378 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4379 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4380 else
4381 dpll |= PLL_REF_INPUT_DREFCLK;
4382
4383 dpll |= DPLL_VCO_ENABLE;
4384 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4385 POSTING_READ(DPLL(pipe));
4386 udelay(150);
4387
4388 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4389 * This is an exception to the general rule that mode_set doesn't turn
4390 * things on.
4391 */
4392 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4393 intel_update_lvds(crtc, clock, adjusted_mode);
4394
4395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4396 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4397
4398 I915_WRITE(DPLL(pipe), dpll);
4399
4400 /* Wait for the clocks to stabilize. */
4401 POSTING_READ(DPLL(pipe));
4402 udelay(150);
4403
4404 if (INTEL_INFO(dev)->gen >= 4) {
4405 u32 temp = 0;
4406 if (is_sdvo) {
4407 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4408 if (temp > 1)
4409 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4410 else
4411 temp = 0;
4412 }
4413 I915_WRITE(DPLL_MD(pipe), temp);
4414 } else {
4415 /* The pixel multiplier can only be updated once the
4416 * DPLL is enabled and the clocks are stable.
4417 *
4418 * So write it again.
4419 */
4420 I915_WRITE(DPLL(pipe), dpll);
4421 }
4422 }
4423
4424 static void i8xx_update_pll(struct drm_crtc *crtc,
4425 struct drm_display_mode *adjusted_mode,
4426 intel_clock_t *clock, intel_clock_t *reduced_clock,
4427 int num_connectors)
4428 {
4429 struct drm_device *dev = crtc->dev;
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4432 int pipe = intel_crtc->pipe;
4433 u32 dpll;
4434
4435 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4436
4437 dpll = DPLL_VGA_MODE_DIS;
4438
4439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4440 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4441 } else {
4442 if (clock->p1 == 2)
4443 dpll |= PLL_P1_DIVIDE_BY_TWO;
4444 else
4445 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4446 if (clock->p2 == 4)
4447 dpll |= PLL_P2_DIVIDE_BY_4;
4448 }
4449
4450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4451 /* XXX: just matching BIOS for now */
4452 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4453 dpll |= 3;
4454 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4455 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4456 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4457 else
4458 dpll |= PLL_REF_INPUT_DREFCLK;
4459
4460 dpll |= DPLL_VCO_ENABLE;
4461 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4462 POSTING_READ(DPLL(pipe));
4463 udelay(150);
4464
4465 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4466 * This is an exception to the general rule that mode_set doesn't turn
4467 * things on.
4468 */
4469 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4470 intel_update_lvds(crtc, clock, adjusted_mode);
4471
4472 I915_WRITE(DPLL(pipe), dpll);
4473
4474 /* Wait for the clocks to stabilize. */
4475 POSTING_READ(DPLL(pipe));
4476 udelay(150);
4477
4478 /* The pixel multiplier can only be updated once the
4479 * DPLL is enabled and the clocks are stable.
4480 *
4481 * So write it again.
4482 */
4483 I915_WRITE(DPLL(pipe), dpll);
4484 }
4485
4486 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4487 struct drm_display_mode *mode,
4488 struct drm_display_mode *adjusted_mode)
4489 {
4490 struct drm_device *dev = intel_crtc->base.dev;
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492 enum pipe pipe = intel_crtc->pipe;
4493 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4494 uint32_t vsyncshift;
4495
4496 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4497 /* the chip adds 2 halflines automatically */
4498 adjusted_mode->crtc_vtotal -= 1;
4499 adjusted_mode->crtc_vblank_end -= 1;
4500 vsyncshift = adjusted_mode->crtc_hsync_start
4501 - adjusted_mode->crtc_htotal / 2;
4502 } else {
4503 vsyncshift = 0;
4504 }
4505
4506 if (INTEL_INFO(dev)->gen > 3)
4507 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4508
4509 I915_WRITE(HTOTAL(cpu_transcoder),
4510 (adjusted_mode->crtc_hdisplay - 1) |
4511 ((adjusted_mode->crtc_htotal - 1) << 16));
4512 I915_WRITE(HBLANK(cpu_transcoder),
4513 (adjusted_mode->crtc_hblank_start - 1) |
4514 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4515 I915_WRITE(HSYNC(cpu_transcoder),
4516 (adjusted_mode->crtc_hsync_start - 1) |
4517 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4518
4519 I915_WRITE(VTOTAL(cpu_transcoder),
4520 (adjusted_mode->crtc_vdisplay - 1) |
4521 ((adjusted_mode->crtc_vtotal - 1) << 16));
4522 I915_WRITE(VBLANK(cpu_transcoder),
4523 (adjusted_mode->crtc_vblank_start - 1) |
4524 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4525 I915_WRITE(VSYNC(cpu_transcoder),
4526 (adjusted_mode->crtc_vsync_start - 1) |
4527 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4528
4529 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4530 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4531 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4532 * bits. */
4533 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4534 (pipe == PIPE_B || pipe == PIPE_C))
4535 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4536
4537 /* pipesrc controls the size that is scaled from, which should
4538 * always be the user's requested size.
4539 */
4540 I915_WRITE(PIPESRC(pipe),
4541 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4542 }
4543
4544 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4545 struct drm_display_mode *mode,
4546 struct drm_display_mode *adjusted_mode,
4547 int x, int y,
4548 struct drm_framebuffer *fb)
4549 {
4550 struct drm_device *dev = crtc->dev;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4553 int pipe = intel_crtc->pipe;
4554 int plane = intel_crtc->plane;
4555 int refclk, num_connectors = 0;
4556 intel_clock_t clock, reduced_clock;
4557 u32 dspcntr, pipeconf;
4558 bool ok, has_reduced_clock = false, is_sdvo = false;
4559 bool is_lvds = false, is_tv = false, is_dp = false;
4560 struct intel_encoder *encoder;
4561 const intel_limit_t *limit;
4562 int ret;
4563
4564 for_each_encoder_on_crtc(dev, crtc, encoder) {
4565 switch (encoder->type) {
4566 case INTEL_OUTPUT_LVDS:
4567 is_lvds = true;
4568 break;
4569 case INTEL_OUTPUT_SDVO:
4570 case INTEL_OUTPUT_HDMI:
4571 is_sdvo = true;
4572 if (encoder->needs_tv_clock)
4573 is_tv = true;
4574 break;
4575 case INTEL_OUTPUT_TVOUT:
4576 is_tv = true;
4577 break;
4578 case INTEL_OUTPUT_DISPLAYPORT:
4579 is_dp = true;
4580 break;
4581 }
4582
4583 num_connectors++;
4584 }
4585
4586 refclk = i9xx_get_refclk(crtc, num_connectors);
4587
4588 /*
4589 * Returns a set of divisors for the desired target clock with the given
4590 * refclk, or FALSE. The returned values represent the clock equation:
4591 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4592 */
4593 limit = intel_limit(crtc, refclk);
4594 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4595 &clock);
4596 if (!ok) {
4597 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4598 return -EINVAL;
4599 }
4600
4601 /* Ensure that the cursor is valid for the new mode before changing... */
4602 intel_crtc_update_cursor(crtc, true);
4603
4604 if (is_lvds && dev_priv->lvds_downclock_avail) {
4605 /*
4606 * Ensure we match the reduced clock's P to the target clock.
4607 * If the clocks don't match, we can't switch the display clock
4608 * by using the FP0/FP1. In such case we will disable the LVDS
4609 * downclock feature.
4610 */
4611 has_reduced_clock = limit->find_pll(limit, crtc,
4612 dev_priv->lvds_downclock,
4613 refclk,
4614 &clock,
4615 &reduced_clock);
4616 }
4617
4618 if (is_sdvo && is_tv)
4619 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4620
4621 if (IS_GEN2(dev))
4622 i8xx_update_pll(crtc, adjusted_mode, &clock,
4623 has_reduced_clock ? &reduced_clock : NULL,
4624 num_connectors);
4625 else if (IS_VALLEYVIEW(dev))
4626 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4627 has_reduced_clock ? &reduced_clock : NULL,
4628 num_connectors);
4629 else
4630 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4631 has_reduced_clock ? &reduced_clock : NULL,
4632 num_connectors);
4633
4634 /* setup pipeconf */
4635 pipeconf = I915_READ(PIPECONF(pipe));
4636
4637 /* Set up the display plane register */
4638 dspcntr = DISPPLANE_GAMMA_ENABLE;
4639
4640 if (pipe == 0)
4641 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4642 else
4643 dspcntr |= DISPPLANE_SEL_PIPE_B;
4644
4645 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4646 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4647 * core speed.
4648 *
4649 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4650 * pipe == 0 check?
4651 */
4652 if (mode->clock >
4653 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4654 pipeconf |= PIPECONF_DOUBLE_WIDE;
4655 else
4656 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4657 }
4658
4659 /* default to 8bpc */
4660 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4661 if (is_dp) {
4662 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4663 pipeconf |= PIPECONF_BPP_6 |
4664 PIPECONF_DITHER_EN |
4665 PIPECONF_DITHER_TYPE_SP;
4666 }
4667 }
4668
4669 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4670 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4671 pipeconf |= PIPECONF_BPP_6 |
4672 PIPECONF_ENABLE |
4673 I965_PIPECONF_ACTIVE;
4674 }
4675 }
4676
4677 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4678 drm_mode_debug_printmodeline(mode);
4679
4680 if (HAS_PIPE_CXSR(dev)) {
4681 if (intel_crtc->lowfreq_avail) {
4682 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4683 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4684 } else {
4685 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4686 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4687 }
4688 }
4689
4690 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4691 if (!IS_GEN2(dev) &&
4692 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4693 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4694 else
4695 pipeconf |= PIPECONF_PROGRESSIVE;
4696
4697 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4698
4699 /* pipesrc and dspsize control the size that is scaled from,
4700 * which should always be the user's requested size.
4701 */
4702 I915_WRITE(DSPSIZE(plane),
4703 ((mode->vdisplay - 1) << 16) |
4704 (mode->hdisplay - 1));
4705 I915_WRITE(DSPPOS(plane), 0);
4706
4707 I915_WRITE(PIPECONF(pipe), pipeconf);
4708 POSTING_READ(PIPECONF(pipe));
4709 intel_enable_pipe(dev_priv, pipe, false);
4710
4711 intel_wait_for_vblank(dev, pipe);
4712
4713 I915_WRITE(DSPCNTR(plane), dspcntr);
4714 POSTING_READ(DSPCNTR(plane));
4715
4716 ret = intel_pipe_set_base(crtc, x, y, fb);
4717
4718 intel_update_watermarks(dev);
4719
4720 return ret;
4721 }
4722
4723 /*
4724 * Initialize reference clocks when the driver loads
4725 */
4726 void ironlake_init_pch_refclk(struct drm_device *dev)
4727 {
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 struct drm_mode_config *mode_config = &dev->mode_config;
4730 struct intel_encoder *encoder;
4731 u32 temp;
4732 bool has_lvds = false;
4733 bool has_cpu_edp = false;
4734 bool has_pch_edp = false;
4735 bool has_panel = false;
4736 bool has_ck505 = false;
4737 bool can_ssc = false;
4738
4739 /* We need to take the global config into account */
4740 list_for_each_entry(encoder, &mode_config->encoder_list,
4741 base.head) {
4742 switch (encoder->type) {
4743 case INTEL_OUTPUT_LVDS:
4744 has_panel = true;
4745 has_lvds = true;
4746 break;
4747 case INTEL_OUTPUT_EDP:
4748 has_panel = true;
4749 if (intel_encoder_is_pch_edp(&encoder->base))
4750 has_pch_edp = true;
4751 else
4752 has_cpu_edp = true;
4753 break;
4754 }
4755 }
4756
4757 if (HAS_PCH_IBX(dev)) {
4758 has_ck505 = dev_priv->display_clock_mode;
4759 can_ssc = has_ck505;
4760 } else {
4761 has_ck505 = false;
4762 can_ssc = true;
4763 }
4764
4765 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4766 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4767 has_ck505);
4768
4769 /* Ironlake: try to setup display ref clock before DPLL
4770 * enabling. This is only under driver's control after
4771 * PCH B stepping, previous chipset stepping should be
4772 * ignoring this setting.
4773 */
4774 temp = I915_READ(PCH_DREF_CONTROL);
4775 /* Always enable nonspread source */
4776 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4777
4778 if (has_ck505)
4779 temp |= DREF_NONSPREAD_CK505_ENABLE;
4780 else
4781 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4782
4783 if (has_panel) {
4784 temp &= ~DREF_SSC_SOURCE_MASK;
4785 temp |= DREF_SSC_SOURCE_ENABLE;
4786
4787 /* SSC must be turned on before enabling the CPU output */
4788 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4789 DRM_DEBUG_KMS("Using SSC on panel\n");
4790 temp |= DREF_SSC1_ENABLE;
4791 } else
4792 temp &= ~DREF_SSC1_ENABLE;
4793
4794 /* Get SSC going before enabling the outputs */
4795 I915_WRITE(PCH_DREF_CONTROL, temp);
4796 POSTING_READ(PCH_DREF_CONTROL);
4797 udelay(200);
4798
4799 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4800
4801 /* Enable CPU source on CPU attached eDP */
4802 if (has_cpu_edp) {
4803 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4804 DRM_DEBUG_KMS("Using SSC on eDP\n");
4805 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4806 }
4807 else
4808 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4809 } else
4810 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4811
4812 I915_WRITE(PCH_DREF_CONTROL, temp);
4813 POSTING_READ(PCH_DREF_CONTROL);
4814 udelay(200);
4815 } else {
4816 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4817
4818 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4819
4820 /* Turn off CPU output */
4821 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4822
4823 I915_WRITE(PCH_DREF_CONTROL, temp);
4824 POSTING_READ(PCH_DREF_CONTROL);
4825 udelay(200);
4826
4827 /* Turn off the SSC source */
4828 temp &= ~DREF_SSC_SOURCE_MASK;
4829 temp |= DREF_SSC_SOURCE_DISABLE;
4830
4831 /* Turn off SSC1 */
4832 temp &= ~ DREF_SSC1_ENABLE;
4833
4834 I915_WRITE(PCH_DREF_CONTROL, temp);
4835 POSTING_READ(PCH_DREF_CONTROL);
4836 udelay(200);
4837 }
4838 }
4839
4840 static int ironlake_get_refclk(struct drm_crtc *crtc)
4841 {
4842 struct drm_device *dev = crtc->dev;
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 struct intel_encoder *encoder;
4845 struct intel_encoder *edp_encoder = NULL;
4846 int num_connectors = 0;
4847 bool is_lvds = false;
4848
4849 for_each_encoder_on_crtc(dev, crtc, encoder) {
4850 switch (encoder->type) {
4851 case INTEL_OUTPUT_LVDS:
4852 is_lvds = true;
4853 break;
4854 case INTEL_OUTPUT_EDP:
4855 edp_encoder = encoder;
4856 break;
4857 }
4858 num_connectors++;
4859 }
4860
4861 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4862 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4863 dev_priv->lvds_ssc_freq);
4864 return dev_priv->lvds_ssc_freq * 1000;
4865 }
4866
4867 return 120000;
4868 }
4869
4870 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4871 struct drm_display_mode *adjusted_mode,
4872 bool dither)
4873 {
4874 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4876 int pipe = intel_crtc->pipe;
4877 uint32_t val;
4878
4879 val = I915_READ(PIPECONF(pipe));
4880
4881 val &= ~PIPE_BPC_MASK;
4882 switch (intel_crtc->bpp) {
4883 case 18:
4884 val |= PIPE_6BPC;
4885 break;
4886 case 24:
4887 val |= PIPE_8BPC;
4888 break;
4889 case 30:
4890 val |= PIPE_10BPC;
4891 break;
4892 case 36:
4893 val |= PIPE_12BPC;
4894 break;
4895 default:
4896 /* Case prevented by intel_choose_pipe_bpp_dither. */
4897 BUG();
4898 }
4899
4900 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4901 if (dither)
4902 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4903
4904 val &= ~PIPECONF_INTERLACE_MASK;
4905 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4906 val |= PIPECONF_INTERLACED_ILK;
4907 else
4908 val |= PIPECONF_PROGRESSIVE;
4909
4910 I915_WRITE(PIPECONF(pipe), val);
4911 POSTING_READ(PIPECONF(pipe));
4912 }
4913
4914 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4915 struct drm_display_mode *adjusted_mode,
4916 bool dither)
4917 {
4918 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4920 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4921 uint32_t val;
4922
4923 val = I915_READ(PIPECONF(cpu_transcoder));
4924
4925 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4926 if (dither)
4927 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4928
4929 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4930 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4931 val |= PIPECONF_INTERLACED_ILK;
4932 else
4933 val |= PIPECONF_PROGRESSIVE;
4934
4935 I915_WRITE(PIPECONF(cpu_transcoder), val);
4936 POSTING_READ(PIPECONF(cpu_transcoder));
4937 }
4938
4939 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4940 struct drm_display_mode *adjusted_mode,
4941 intel_clock_t *clock,
4942 bool *has_reduced_clock,
4943 intel_clock_t *reduced_clock)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_encoder *intel_encoder;
4948 int refclk;
4949 const intel_limit_t *limit;
4950 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4951
4952 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4953 switch (intel_encoder->type) {
4954 case INTEL_OUTPUT_LVDS:
4955 is_lvds = true;
4956 break;
4957 case INTEL_OUTPUT_SDVO:
4958 case INTEL_OUTPUT_HDMI:
4959 is_sdvo = true;
4960 if (intel_encoder->needs_tv_clock)
4961 is_tv = true;
4962 break;
4963 case INTEL_OUTPUT_TVOUT:
4964 is_tv = true;
4965 break;
4966 }
4967 }
4968
4969 refclk = ironlake_get_refclk(crtc);
4970
4971 /*
4972 * Returns a set of divisors for the desired target clock with the given
4973 * refclk, or FALSE. The returned values represent the clock equation:
4974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4975 */
4976 limit = intel_limit(crtc, refclk);
4977 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4978 clock);
4979 if (!ret)
4980 return false;
4981
4982 if (is_lvds && dev_priv->lvds_downclock_avail) {
4983 /*
4984 * Ensure we match the reduced clock's P to the target clock.
4985 * If the clocks don't match, we can't switch the display clock
4986 * by using the FP0/FP1. In such case we will disable the LVDS
4987 * downclock feature.
4988 */
4989 *has_reduced_clock = limit->find_pll(limit, crtc,
4990 dev_priv->lvds_downclock,
4991 refclk,
4992 clock,
4993 reduced_clock);
4994 }
4995
4996 if (is_sdvo && is_tv)
4997 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4998
4999 return true;
5000 }
5001
5002 static void ironlake_set_m_n(struct drm_crtc *crtc,
5003 struct drm_display_mode *mode,
5004 struct drm_display_mode *adjusted_mode)
5005 {
5006 struct drm_device *dev = crtc->dev;
5007 struct drm_i915_private *dev_priv = dev->dev_private;
5008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5009 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5010 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5011 struct fdi_m_n m_n = {0};
5012 int target_clock, pixel_multiplier, lane, link_bw;
5013 bool is_dp = false, is_cpu_edp = false;
5014
5015 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5016 switch (intel_encoder->type) {
5017 case INTEL_OUTPUT_DISPLAYPORT:
5018 is_dp = true;
5019 break;
5020 case INTEL_OUTPUT_EDP:
5021 is_dp = true;
5022 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5023 is_cpu_edp = true;
5024 edp_encoder = intel_encoder;
5025 break;
5026 }
5027 }
5028
5029 /* FDI link */
5030 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5031 lane = 0;
5032 /* CPU eDP doesn't require FDI link, so just set DP M/N
5033 according to current link config */
5034 if (is_cpu_edp) {
5035 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5036 } else {
5037 /* FDI is a binary signal running at ~2.7GHz, encoding
5038 * each output octet as 10 bits. The actual frequency
5039 * is stored as a divider into a 100MHz clock, and the
5040 * mode pixel clock is stored in units of 1KHz.
5041 * Hence the bw of each lane in terms of the mode signal
5042 * is:
5043 */
5044 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5045 }
5046
5047 /* [e]DP over FDI requires target mode clock instead of link clock. */
5048 if (edp_encoder)
5049 target_clock = intel_edp_target_clock(edp_encoder, mode);
5050 else if (is_dp)
5051 target_clock = mode->clock;
5052 else
5053 target_clock = adjusted_mode->clock;
5054
5055 if (!lane) {
5056 /*
5057 * Account for spread spectrum to avoid
5058 * oversubscribing the link. Max center spread
5059 * is 2.5%; use 5% for safety's sake.
5060 */
5061 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5062 lane = bps / (link_bw * 8) + 1;
5063 }
5064
5065 intel_crtc->fdi_lanes = lane;
5066
5067 if (pixel_multiplier > 1)
5068 link_bw *= pixel_multiplier;
5069 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5070 &m_n);
5071
5072 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5073 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5074 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5075 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5076 }
5077
5078 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5079 struct drm_display_mode *adjusted_mode,
5080 intel_clock_t *clock, u32 fp)
5081 {
5082 struct drm_crtc *crtc = &intel_crtc->base;
5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 struct intel_encoder *intel_encoder;
5086 uint32_t dpll;
5087 int factor, pixel_multiplier, num_connectors = 0;
5088 bool is_lvds = false, is_sdvo = false, is_tv = false;
5089 bool is_dp = false, is_cpu_edp = false;
5090
5091 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5092 switch (intel_encoder->type) {
5093 case INTEL_OUTPUT_LVDS:
5094 is_lvds = true;
5095 break;
5096 case INTEL_OUTPUT_SDVO:
5097 case INTEL_OUTPUT_HDMI:
5098 is_sdvo = true;
5099 if (intel_encoder->needs_tv_clock)
5100 is_tv = true;
5101 break;
5102 case INTEL_OUTPUT_TVOUT:
5103 is_tv = true;
5104 break;
5105 case INTEL_OUTPUT_DISPLAYPORT:
5106 is_dp = true;
5107 break;
5108 case INTEL_OUTPUT_EDP:
5109 is_dp = true;
5110 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5111 is_cpu_edp = true;
5112 break;
5113 }
5114
5115 num_connectors++;
5116 }
5117
5118 /* Enable autotuning of the PLL clock (if permissible) */
5119 factor = 21;
5120 if (is_lvds) {
5121 if ((intel_panel_use_ssc(dev_priv) &&
5122 dev_priv->lvds_ssc_freq == 100) ||
5123 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5124 factor = 25;
5125 } else if (is_sdvo && is_tv)
5126 factor = 20;
5127
5128 if (clock->m < factor * clock->n)
5129 fp |= FP_CB_TUNE;
5130
5131 dpll = 0;
5132
5133 if (is_lvds)
5134 dpll |= DPLLB_MODE_LVDS;
5135 else
5136 dpll |= DPLLB_MODE_DAC_SERIAL;
5137 if (is_sdvo) {
5138 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5139 if (pixel_multiplier > 1) {
5140 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5141 }
5142 dpll |= DPLL_DVO_HIGH_SPEED;
5143 }
5144 if (is_dp && !is_cpu_edp)
5145 dpll |= DPLL_DVO_HIGH_SPEED;
5146
5147 /* compute bitmask from p1 value */
5148 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5149 /* also FPA1 */
5150 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5151
5152 switch (clock->p2) {
5153 case 5:
5154 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5155 break;
5156 case 7:
5157 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5158 break;
5159 case 10:
5160 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5161 break;
5162 case 14:
5163 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5164 break;
5165 }
5166
5167 if (is_sdvo && is_tv)
5168 dpll |= PLL_REF_INPUT_TVCLKINBC;
5169 else if (is_tv)
5170 /* XXX: just matching BIOS for now */
5171 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5172 dpll |= 3;
5173 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5174 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5175 else
5176 dpll |= PLL_REF_INPUT_DREFCLK;
5177
5178 return dpll;
5179 }
5180
5181 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5182 struct drm_display_mode *mode,
5183 struct drm_display_mode *adjusted_mode,
5184 int x, int y,
5185 struct drm_framebuffer *fb)
5186 {
5187 struct drm_device *dev = crtc->dev;
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5190 int pipe = intel_crtc->pipe;
5191 int plane = intel_crtc->plane;
5192 int num_connectors = 0;
5193 intel_clock_t clock, reduced_clock;
5194 u32 dpll, fp = 0, fp2 = 0;
5195 bool ok, has_reduced_clock = false;
5196 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5197 struct intel_encoder *encoder;
5198 u32 temp;
5199 int ret;
5200 bool dither;
5201
5202 for_each_encoder_on_crtc(dev, crtc, encoder) {
5203 switch (encoder->type) {
5204 case INTEL_OUTPUT_LVDS:
5205 is_lvds = true;
5206 break;
5207 case INTEL_OUTPUT_DISPLAYPORT:
5208 is_dp = true;
5209 break;
5210 case INTEL_OUTPUT_EDP:
5211 is_dp = true;
5212 if (!intel_encoder_is_pch_edp(&encoder->base))
5213 is_cpu_edp = true;
5214 break;
5215 }
5216
5217 num_connectors++;
5218 }
5219
5220 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5221 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5222
5223 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5224 &has_reduced_clock, &reduced_clock);
5225 if (!ok) {
5226 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5227 return -EINVAL;
5228 }
5229
5230 /* Ensure that the cursor is valid for the new mode before changing... */
5231 intel_crtc_update_cursor(crtc, true);
5232
5233 /* determine panel color depth */
5234 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5235 adjusted_mode);
5236 if (is_lvds && dev_priv->lvds_dither)
5237 dither = true;
5238
5239 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5240 if (has_reduced_clock)
5241 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5242 reduced_clock.m2;
5243
5244 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5245
5246 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5247 drm_mode_debug_printmodeline(mode);
5248
5249 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5250 if (!is_cpu_edp) {
5251 struct intel_pch_pll *pll;
5252
5253 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5254 if (pll == NULL) {
5255 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5256 pipe);
5257 return -EINVAL;
5258 }
5259 } else
5260 intel_put_pch_pll(intel_crtc);
5261
5262 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5263 * This is an exception to the general rule that mode_set doesn't turn
5264 * things on.
5265 */
5266 if (is_lvds) {
5267 temp = I915_READ(PCH_LVDS);
5268 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5269 if (HAS_PCH_CPT(dev)) {
5270 temp &= ~PORT_TRANS_SEL_MASK;
5271 temp |= PORT_TRANS_SEL_CPT(pipe);
5272 } else {
5273 if (pipe == 1)
5274 temp |= LVDS_PIPEB_SELECT;
5275 else
5276 temp &= ~LVDS_PIPEB_SELECT;
5277 }
5278
5279 /* set the corresponsding LVDS_BORDER bit */
5280 temp |= dev_priv->lvds_border_bits;
5281 /* Set the B0-B3 data pairs corresponding to whether we're going to
5282 * set the DPLLs for dual-channel mode or not.
5283 */
5284 if (clock.p2 == 7)
5285 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5286 else
5287 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5288
5289 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5290 * appropriately here, but we need to look more thoroughly into how
5291 * panels behave in the two modes.
5292 */
5293 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5294 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5295 temp |= LVDS_HSYNC_POLARITY;
5296 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5297 temp |= LVDS_VSYNC_POLARITY;
5298 I915_WRITE(PCH_LVDS, temp);
5299 }
5300
5301 if (is_dp && !is_cpu_edp) {
5302 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5303 } else {
5304 /* For non-DP output, clear any trans DP clock recovery setting.*/
5305 I915_WRITE(TRANSDATA_M1(pipe), 0);
5306 I915_WRITE(TRANSDATA_N1(pipe), 0);
5307 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5308 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5309 }
5310
5311 if (intel_crtc->pch_pll) {
5312 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5313
5314 /* Wait for the clocks to stabilize. */
5315 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5316 udelay(150);
5317
5318 /* The pixel multiplier can only be updated once the
5319 * DPLL is enabled and the clocks are stable.
5320 *
5321 * So write it again.
5322 */
5323 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5324 }
5325
5326 intel_crtc->lowfreq_avail = false;
5327 if (intel_crtc->pch_pll) {
5328 if (is_lvds && has_reduced_clock && i915_powersave) {
5329 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5330 intel_crtc->lowfreq_avail = true;
5331 } else {
5332 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5333 }
5334 }
5335
5336 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5337
5338 ironlake_set_m_n(crtc, mode, adjusted_mode);
5339
5340 if (is_cpu_edp)
5341 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5342
5343 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5344
5345 intel_wait_for_vblank(dev, pipe);
5346
5347 /* Set up the display plane register */
5348 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5349 POSTING_READ(DSPCNTR(plane));
5350
5351 ret = intel_pipe_set_base(crtc, x, y, fb);
5352
5353 intel_update_watermarks(dev);
5354
5355 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5356
5357 return ret;
5358 }
5359
5360 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5361 struct drm_display_mode *mode,
5362 struct drm_display_mode *adjusted_mode,
5363 int x, int y,
5364 struct drm_framebuffer *fb)
5365 {
5366 struct drm_device *dev = crtc->dev;
5367 struct drm_i915_private *dev_priv = dev->dev_private;
5368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5369 int pipe = intel_crtc->pipe;
5370 int plane = intel_crtc->plane;
5371 int num_connectors = 0;
5372 intel_clock_t clock, reduced_clock;
5373 u32 dpll = 0, fp = 0, fp2 = 0;
5374 bool ok, has_reduced_clock = false;
5375 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5376 struct intel_encoder *encoder;
5377 u32 temp;
5378 int ret;
5379 bool dither;
5380
5381 for_each_encoder_on_crtc(dev, crtc, encoder) {
5382 switch (encoder->type) {
5383 case INTEL_OUTPUT_LVDS:
5384 is_lvds = true;
5385 break;
5386 case INTEL_OUTPUT_DISPLAYPORT:
5387 is_dp = true;
5388 break;
5389 case INTEL_OUTPUT_EDP:
5390 is_dp = true;
5391 if (!intel_encoder_is_pch_edp(&encoder->base))
5392 is_cpu_edp = true;
5393 break;
5394 }
5395
5396 num_connectors++;
5397 }
5398
5399 if (is_cpu_edp)
5400 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5401 else
5402 intel_crtc->cpu_transcoder = pipe;
5403
5404 /* We are not sure yet this won't happen. */
5405 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5406 INTEL_PCH_TYPE(dev));
5407
5408 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5409 num_connectors, pipe_name(pipe));
5410
5411 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5412 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5413
5414 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5415
5416 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5417 return -EINVAL;
5418
5419 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5420 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5421 &has_reduced_clock,
5422 &reduced_clock);
5423 if (!ok) {
5424 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5425 return -EINVAL;
5426 }
5427 }
5428
5429 /* Ensure that the cursor is valid for the new mode before changing... */
5430 intel_crtc_update_cursor(crtc, true);
5431
5432 /* determine panel color depth */
5433 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5434 adjusted_mode);
5435 if (is_lvds && dev_priv->lvds_dither)
5436 dither = true;
5437
5438 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5439 drm_mode_debug_printmodeline(mode);
5440
5441 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5442 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5443 if (has_reduced_clock)
5444 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5445 reduced_clock.m2;
5446
5447 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5448 fp);
5449
5450 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5451 * own on pre-Haswell/LPT generation */
5452 if (!is_cpu_edp) {
5453 struct intel_pch_pll *pll;
5454
5455 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5456 if (pll == NULL) {
5457 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5458 pipe);
5459 return -EINVAL;
5460 }
5461 } else
5462 intel_put_pch_pll(intel_crtc);
5463
5464 /* The LVDS pin pair needs to be on before the DPLLs are
5465 * enabled. This is an exception to the general rule that
5466 * mode_set doesn't turn things on.
5467 */
5468 if (is_lvds) {
5469 temp = I915_READ(PCH_LVDS);
5470 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5471 if (HAS_PCH_CPT(dev)) {
5472 temp &= ~PORT_TRANS_SEL_MASK;
5473 temp |= PORT_TRANS_SEL_CPT(pipe);
5474 } else {
5475 if (pipe == 1)
5476 temp |= LVDS_PIPEB_SELECT;
5477 else
5478 temp &= ~LVDS_PIPEB_SELECT;
5479 }
5480
5481 /* set the corresponsding LVDS_BORDER bit */
5482 temp |= dev_priv->lvds_border_bits;
5483 /* Set the B0-B3 data pairs corresponding to whether
5484 * we're going to set the DPLLs for dual-channel mode or
5485 * not.
5486 */
5487 if (clock.p2 == 7)
5488 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5489 else
5490 temp &= ~(LVDS_B0B3_POWER_UP |
5491 LVDS_CLKB_POWER_UP);
5492
5493 /* It would be nice to set 24 vs 18-bit mode
5494 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5495 * look more thoroughly into how panels behave in the
5496 * two modes.
5497 */
5498 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5499 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5500 temp |= LVDS_HSYNC_POLARITY;
5501 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5502 temp |= LVDS_VSYNC_POLARITY;
5503 I915_WRITE(PCH_LVDS, temp);
5504 }
5505 }
5506
5507 if (is_dp && !is_cpu_edp) {
5508 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5509 } else {
5510 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5511 /* For non-DP output, clear any trans DP clock recovery
5512 * setting.*/
5513 I915_WRITE(TRANSDATA_M1(pipe), 0);
5514 I915_WRITE(TRANSDATA_N1(pipe), 0);
5515 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5516 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5517 }
5518 }
5519
5520 intel_crtc->lowfreq_avail = false;
5521 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5522 if (intel_crtc->pch_pll) {
5523 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5524
5525 /* Wait for the clocks to stabilize. */
5526 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5527 udelay(150);
5528
5529 /* The pixel multiplier can only be updated once the
5530 * DPLL is enabled and the clocks are stable.
5531 *
5532 * So write it again.
5533 */
5534 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5535 }
5536
5537 if (intel_crtc->pch_pll) {
5538 if (is_lvds && has_reduced_clock && i915_powersave) {
5539 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5540 intel_crtc->lowfreq_avail = true;
5541 } else {
5542 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5543 }
5544 }
5545 }
5546
5547 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5548
5549 if (!is_dp || is_cpu_edp)
5550 ironlake_set_m_n(crtc, mode, adjusted_mode);
5551
5552 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5553 if (is_cpu_edp)
5554 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5555
5556 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5557
5558 /* Set up the display plane register */
5559 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5560 POSTING_READ(DSPCNTR(plane));
5561
5562 ret = intel_pipe_set_base(crtc, x, y, fb);
5563
5564 intel_update_watermarks(dev);
5565
5566 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5567
5568 return ret;
5569 }
5570
5571 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5572 struct drm_display_mode *mode,
5573 struct drm_display_mode *adjusted_mode,
5574 int x, int y,
5575 struct drm_framebuffer *fb)
5576 {
5577 struct drm_device *dev = crtc->dev;
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5580 int pipe = intel_crtc->pipe;
5581 int ret;
5582
5583 drm_vblank_pre_modeset(dev, pipe);
5584
5585 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5586 x, y, fb);
5587 drm_vblank_post_modeset(dev, pipe);
5588
5589 return ret;
5590 }
5591
5592 static bool intel_eld_uptodate(struct drm_connector *connector,
5593 int reg_eldv, uint32_t bits_eldv,
5594 int reg_elda, uint32_t bits_elda,
5595 int reg_edid)
5596 {
5597 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5598 uint8_t *eld = connector->eld;
5599 uint32_t i;
5600
5601 i = I915_READ(reg_eldv);
5602 i &= bits_eldv;
5603
5604 if (!eld[0])
5605 return !i;
5606
5607 if (!i)
5608 return false;
5609
5610 i = I915_READ(reg_elda);
5611 i &= ~bits_elda;
5612 I915_WRITE(reg_elda, i);
5613
5614 for (i = 0; i < eld[2]; i++)
5615 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5616 return false;
5617
5618 return true;
5619 }
5620
5621 static void g4x_write_eld(struct drm_connector *connector,
5622 struct drm_crtc *crtc)
5623 {
5624 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5625 uint8_t *eld = connector->eld;
5626 uint32_t eldv;
5627 uint32_t len;
5628 uint32_t i;
5629
5630 i = I915_READ(G4X_AUD_VID_DID);
5631
5632 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5633 eldv = G4X_ELDV_DEVCL_DEVBLC;
5634 else
5635 eldv = G4X_ELDV_DEVCTG;
5636
5637 if (intel_eld_uptodate(connector,
5638 G4X_AUD_CNTL_ST, eldv,
5639 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5640 G4X_HDMIW_HDMIEDID))
5641 return;
5642
5643 i = I915_READ(G4X_AUD_CNTL_ST);
5644 i &= ~(eldv | G4X_ELD_ADDR);
5645 len = (i >> 9) & 0x1f; /* ELD buffer size */
5646 I915_WRITE(G4X_AUD_CNTL_ST, i);
5647
5648 if (!eld[0])
5649 return;
5650
5651 len = min_t(uint8_t, eld[2], len);
5652 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5653 for (i = 0; i < len; i++)
5654 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5655
5656 i = I915_READ(G4X_AUD_CNTL_ST);
5657 i |= eldv;
5658 I915_WRITE(G4X_AUD_CNTL_ST, i);
5659 }
5660
5661 static void haswell_write_eld(struct drm_connector *connector,
5662 struct drm_crtc *crtc)
5663 {
5664 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5665 uint8_t *eld = connector->eld;
5666 struct drm_device *dev = crtc->dev;
5667 uint32_t eldv;
5668 uint32_t i;
5669 int len;
5670 int pipe = to_intel_crtc(crtc)->pipe;
5671 int tmp;
5672
5673 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5674 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5675 int aud_config = HSW_AUD_CFG(pipe);
5676 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5677
5678
5679 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5680
5681 /* Audio output enable */
5682 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5683 tmp = I915_READ(aud_cntrl_st2);
5684 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5685 I915_WRITE(aud_cntrl_st2, tmp);
5686
5687 /* Wait for 1 vertical blank */
5688 intel_wait_for_vblank(dev, pipe);
5689
5690 /* Set ELD valid state */
5691 tmp = I915_READ(aud_cntrl_st2);
5692 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5693 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5694 I915_WRITE(aud_cntrl_st2, tmp);
5695 tmp = I915_READ(aud_cntrl_st2);
5696 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5697
5698 /* Enable HDMI mode */
5699 tmp = I915_READ(aud_config);
5700 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5701 /* clear N_programing_enable and N_value_index */
5702 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5703 I915_WRITE(aud_config, tmp);
5704
5705 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5706
5707 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5708
5709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5710 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5711 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5712 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5713 } else
5714 I915_WRITE(aud_config, 0);
5715
5716 if (intel_eld_uptodate(connector,
5717 aud_cntrl_st2, eldv,
5718 aud_cntl_st, IBX_ELD_ADDRESS,
5719 hdmiw_hdmiedid))
5720 return;
5721
5722 i = I915_READ(aud_cntrl_st2);
5723 i &= ~eldv;
5724 I915_WRITE(aud_cntrl_st2, i);
5725
5726 if (!eld[0])
5727 return;
5728
5729 i = I915_READ(aud_cntl_st);
5730 i &= ~IBX_ELD_ADDRESS;
5731 I915_WRITE(aud_cntl_st, i);
5732 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5733 DRM_DEBUG_DRIVER("port num:%d\n", i);
5734
5735 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5736 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5737 for (i = 0; i < len; i++)
5738 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5739
5740 i = I915_READ(aud_cntrl_st2);
5741 i |= eldv;
5742 I915_WRITE(aud_cntrl_st2, i);
5743
5744 }
5745
5746 static void ironlake_write_eld(struct drm_connector *connector,
5747 struct drm_crtc *crtc)
5748 {
5749 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5750 uint8_t *eld = connector->eld;
5751 uint32_t eldv;
5752 uint32_t i;
5753 int len;
5754 int hdmiw_hdmiedid;
5755 int aud_config;
5756 int aud_cntl_st;
5757 int aud_cntrl_st2;
5758 int pipe = to_intel_crtc(crtc)->pipe;
5759
5760 if (HAS_PCH_IBX(connector->dev)) {
5761 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5762 aud_config = IBX_AUD_CFG(pipe);
5763 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5764 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5765 } else {
5766 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5767 aud_config = CPT_AUD_CFG(pipe);
5768 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5769 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5770 }
5771
5772 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5773
5774 i = I915_READ(aud_cntl_st);
5775 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5776 if (!i) {
5777 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5778 /* operate blindly on all ports */
5779 eldv = IBX_ELD_VALIDB;
5780 eldv |= IBX_ELD_VALIDB << 4;
5781 eldv |= IBX_ELD_VALIDB << 8;
5782 } else {
5783 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5784 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5785 }
5786
5787 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5788 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5789 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5790 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5791 } else
5792 I915_WRITE(aud_config, 0);
5793
5794 if (intel_eld_uptodate(connector,
5795 aud_cntrl_st2, eldv,
5796 aud_cntl_st, IBX_ELD_ADDRESS,
5797 hdmiw_hdmiedid))
5798 return;
5799
5800 i = I915_READ(aud_cntrl_st2);
5801 i &= ~eldv;
5802 I915_WRITE(aud_cntrl_st2, i);
5803
5804 if (!eld[0])
5805 return;
5806
5807 i = I915_READ(aud_cntl_st);
5808 i &= ~IBX_ELD_ADDRESS;
5809 I915_WRITE(aud_cntl_st, i);
5810
5811 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5812 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5813 for (i = 0; i < len; i++)
5814 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5815
5816 i = I915_READ(aud_cntrl_st2);
5817 i |= eldv;
5818 I915_WRITE(aud_cntrl_st2, i);
5819 }
5820
5821 void intel_write_eld(struct drm_encoder *encoder,
5822 struct drm_display_mode *mode)
5823 {
5824 struct drm_crtc *crtc = encoder->crtc;
5825 struct drm_connector *connector;
5826 struct drm_device *dev = encoder->dev;
5827 struct drm_i915_private *dev_priv = dev->dev_private;
5828
5829 connector = drm_select_eld(encoder, mode);
5830 if (!connector)
5831 return;
5832
5833 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5834 connector->base.id,
5835 drm_get_connector_name(connector),
5836 connector->encoder->base.id,
5837 drm_get_encoder_name(connector->encoder));
5838
5839 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5840
5841 if (dev_priv->display.write_eld)
5842 dev_priv->display.write_eld(connector, crtc);
5843 }
5844
5845 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5846 void intel_crtc_load_lut(struct drm_crtc *crtc)
5847 {
5848 struct drm_device *dev = crtc->dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5851 int palreg = PALETTE(intel_crtc->pipe);
5852 int i;
5853
5854 /* The clocks have to be on to load the palette. */
5855 if (!crtc->enabled || !intel_crtc->active)
5856 return;
5857
5858 /* use legacy palette for Ironlake */
5859 if (HAS_PCH_SPLIT(dev))
5860 palreg = LGC_PALETTE(intel_crtc->pipe);
5861
5862 for (i = 0; i < 256; i++) {
5863 I915_WRITE(palreg + 4 * i,
5864 (intel_crtc->lut_r[i] << 16) |
5865 (intel_crtc->lut_g[i] << 8) |
5866 intel_crtc->lut_b[i]);
5867 }
5868 }
5869
5870 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5871 {
5872 struct drm_device *dev = crtc->dev;
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5875 bool visible = base != 0;
5876 u32 cntl;
5877
5878 if (intel_crtc->cursor_visible == visible)
5879 return;
5880
5881 cntl = I915_READ(_CURACNTR);
5882 if (visible) {
5883 /* On these chipsets we can only modify the base whilst
5884 * the cursor is disabled.
5885 */
5886 I915_WRITE(_CURABASE, base);
5887
5888 cntl &= ~(CURSOR_FORMAT_MASK);
5889 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5890 cntl |= CURSOR_ENABLE |
5891 CURSOR_GAMMA_ENABLE |
5892 CURSOR_FORMAT_ARGB;
5893 } else
5894 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5895 I915_WRITE(_CURACNTR, cntl);
5896
5897 intel_crtc->cursor_visible = visible;
5898 }
5899
5900 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5901 {
5902 struct drm_device *dev = crtc->dev;
5903 struct drm_i915_private *dev_priv = dev->dev_private;
5904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5905 int pipe = intel_crtc->pipe;
5906 bool visible = base != 0;
5907
5908 if (intel_crtc->cursor_visible != visible) {
5909 uint32_t cntl = I915_READ(CURCNTR(pipe));
5910 if (base) {
5911 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5912 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5913 cntl |= pipe << 28; /* Connect to correct pipe */
5914 } else {
5915 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5916 cntl |= CURSOR_MODE_DISABLE;
5917 }
5918 I915_WRITE(CURCNTR(pipe), cntl);
5919
5920 intel_crtc->cursor_visible = visible;
5921 }
5922 /* and commit changes on next vblank */
5923 I915_WRITE(CURBASE(pipe), base);
5924 }
5925
5926 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5927 {
5928 struct drm_device *dev = crtc->dev;
5929 struct drm_i915_private *dev_priv = dev->dev_private;
5930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5931 int pipe = intel_crtc->pipe;
5932 bool visible = base != 0;
5933
5934 if (intel_crtc->cursor_visible != visible) {
5935 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5936 if (base) {
5937 cntl &= ~CURSOR_MODE;
5938 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5939 } else {
5940 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5941 cntl |= CURSOR_MODE_DISABLE;
5942 }
5943 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5944
5945 intel_crtc->cursor_visible = visible;
5946 }
5947 /* and commit changes on next vblank */
5948 I915_WRITE(CURBASE_IVB(pipe), base);
5949 }
5950
5951 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5952 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5953 bool on)
5954 {
5955 struct drm_device *dev = crtc->dev;
5956 struct drm_i915_private *dev_priv = dev->dev_private;
5957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5958 int pipe = intel_crtc->pipe;
5959 int x = intel_crtc->cursor_x;
5960 int y = intel_crtc->cursor_y;
5961 u32 base, pos;
5962 bool visible;
5963
5964 pos = 0;
5965
5966 if (on && crtc->enabled && crtc->fb) {
5967 base = intel_crtc->cursor_addr;
5968 if (x > (int) crtc->fb->width)
5969 base = 0;
5970
5971 if (y > (int) crtc->fb->height)
5972 base = 0;
5973 } else
5974 base = 0;
5975
5976 if (x < 0) {
5977 if (x + intel_crtc->cursor_width < 0)
5978 base = 0;
5979
5980 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5981 x = -x;
5982 }
5983 pos |= x << CURSOR_X_SHIFT;
5984
5985 if (y < 0) {
5986 if (y + intel_crtc->cursor_height < 0)
5987 base = 0;
5988
5989 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5990 y = -y;
5991 }
5992 pos |= y << CURSOR_Y_SHIFT;
5993
5994 visible = base != 0;
5995 if (!visible && !intel_crtc->cursor_visible)
5996 return;
5997
5998 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5999 I915_WRITE(CURPOS_IVB(pipe), pos);
6000 ivb_update_cursor(crtc, base);
6001 } else {
6002 I915_WRITE(CURPOS(pipe), pos);
6003 if (IS_845G(dev) || IS_I865G(dev))
6004 i845_update_cursor(crtc, base);
6005 else
6006 i9xx_update_cursor(crtc, base);
6007 }
6008 }
6009
6010 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6011 struct drm_file *file,
6012 uint32_t handle,
6013 uint32_t width, uint32_t height)
6014 {
6015 struct drm_device *dev = crtc->dev;
6016 struct drm_i915_private *dev_priv = dev->dev_private;
6017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6018 struct drm_i915_gem_object *obj;
6019 uint32_t addr;
6020 int ret;
6021
6022 /* if we want to turn off the cursor ignore width and height */
6023 if (!handle) {
6024 DRM_DEBUG_KMS("cursor off\n");
6025 addr = 0;
6026 obj = NULL;
6027 mutex_lock(&dev->struct_mutex);
6028 goto finish;
6029 }
6030
6031 /* Currently we only support 64x64 cursors */
6032 if (width != 64 || height != 64) {
6033 DRM_ERROR("we currently only support 64x64 cursors\n");
6034 return -EINVAL;
6035 }
6036
6037 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6038 if (&obj->base == NULL)
6039 return -ENOENT;
6040
6041 if (obj->base.size < width * height * 4) {
6042 DRM_ERROR("buffer is to small\n");
6043 ret = -ENOMEM;
6044 goto fail;
6045 }
6046
6047 /* we only need to pin inside GTT if cursor is non-phy */
6048 mutex_lock(&dev->struct_mutex);
6049 if (!dev_priv->info->cursor_needs_physical) {
6050 if (obj->tiling_mode) {
6051 DRM_ERROR("cursor cannot be tiled\n");
6052 ret = -EINVAL;
6053 goto fail_locked;
6054 }
6055
6056 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6057 if (ret) {
6058 DRM_ERROR("failed to move cursor bo into the GTT\n");
6059 goto fail_locked;
6060 }
6061
6062 ret = i915_gem_object_put_fence(obj);
6063 if (ret) {
6064 DRM_ERROR("failed to release fence for cursor");
6065 goto fail_unpin;
6066 }
6067
6068 addr = obj->gtt_offset;
6069 } else {
6070 int align = IS_I830(dev) ? 16 * 1024 : 256;
6071 ret = i915_gem_attach_phys_object(dev, obj,
6072 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6073 align);
6074 if (ret) {
6075 DRM_ERROR("failed to attach phys object\n");
6076 goto fail_locked;
6077 }
6078 addr = obj->phys_obj->handle->busaddr;
6079 }
6080
6081 if (IS_GEN2(dev))
6082 I915_WRITE(CURSIZE, (height << 12) | width);
6083
6084 finish:
6085 if (intel_crtc->cursor_bo) {
6086 if (dev_priv->info->cursor_needs_physical) {
6087 if (intel_crtc->cursor_bo != obj)
6088 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6089 } else
6090 i915_gem_object_unpin(intel_crtc->cursor_bo);
6091 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6092 }
6093
6094 mutex_unlock(&dev->struct_mutex);
6095
6096 intel_crtc->cursor_addr = addr;
6097 intel_crtc->cursor_bo = obj;
6098 intel_crtc->cursor_width = width;
6099 intel_crtc->cursor_height = height;
6100
6101 intel_crtc_update_cursor(crtc, true);
6102
6103 return 0;
6104 fail_unpin:
6105 i915_gem_object_unpin(obj);
6106 fail_locked:
6107 mutex_unlock(&dev->struct_mutex);
6108 fail:
6109 drm_gem_object_unreference_unlocked(&obj->base);
6110 return ret;
6111 }
6112
6113 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6114 {
6115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6116
6117 intel_crtc->cursor_x = x;
6118 intel_crtc->cursor_y = y;
6119
6120 intel_crtc_update_cursor(crtc, true);
6121
6122 return 0;
6123 }
6124
6125 /** Sets the color ramps on behalf of RandR */
6126 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6127 u16 blue, int regno)
6128 {
6129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6130
6131 intel_crtc->lut_r[regno] = red >> 8;
6132 intel_crtc->lut_g[regno] = green >> 8;
6133 intel_crtc->lut_b[regno] = blue >> 8;
6134 }
6135
6136 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6137 u16 *blue, int regno)
6138 {
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6140
6141 *red = intel_crtc->lut_r[regno] << 8;
6142 *green = intel_crtc->lut_g[regno] << 8;
6143 *blue = intel_crtc->lut_b[regno] << 8;
6144 }
6145
6146 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6147 u16 *blue, uint32_t start, uint32_t size)
6148 {
6149 int end = (start + size > 256) ? 256 : start + size, i;
6150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6151
6152 for (i = start; i < end; i++) {
6153 intel_crtc->lut_r[i] = red[i] >> 8;
6154 intel_crtc->lut_g[i] = green[i] >> 8;
6155 intel_crtc->lut_b[i] = blue[i] >> 8;
6156 }
6157
6158 intel_crtc_load_lut(crtc);
6159 }
6160
6161 /**
6162 * Get a pipe with a simple mode set on it for doing load-based monitor
6163 * detection.
6164 *
6165 * It will be up to the load-detect code to adjust the pipe as appropriate for
6166 * its requirements. The pipe will be connected to no other encoders.
6167 *
6168 * Currently this code will only succeed if there is a pipe with no encoders
6169 * configured for it. In the future, it could choose to temporarily disable
6170 * some outputs to free up a pipe for its use.
6171 *
6172 * \return crtc, or NULL if no pipes are available.
6173 */
6174
6175 /* VESA 640x480x72Hz mode to set on the pipe */
6176 static struct drm_display_mode load_detect_mode = {
6177 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6178 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6179 };
6180
6181 static struct drm_framebuffer *
6182 intel_framebuffer_create(struct drm_device *dev,
6183 struct drm_mode_fb_cmd2 *mode_cmd,
6184 struct drm_i915_gem_object *obj)
6185 {
6186 struct intel_framebuffer *intel_fb;
6187 int ret;
6188
6189 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6190 if (!intel_fb) {
6191 drm_gem_object_unreference_unlocked(&obj->base);
6192 return ERR_PTR(-ENOMEM);
6193 }
6194
6195 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6196 if (ret) {
6197 drm_gem_object_unreference_unlocked(&obj->base);
6198 kfree(intel_fb);
6199 return ERR_PTR(ret);
6200 }
6201
6202 return &intel_fb->base;
6203 }
6204
6205 static u32
6206 intel_framebuffer_pitch_for_width(int width, int bpp)
6207 {
6208 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6209 return ALIGN(pitch, 64);
6210 }
6211
6212 static u32
6213 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6214 {
6215 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6216 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6217 }
6218
6219 static struct drm_framebuffer *
6220 intel_framebuffer_create_for_mode(struct drm_device *dev,
6221 struct drm_display_mode *mode,
6222 int depth, int bpp)
6223 {
6224 struct drm_i915_gem_object *obj;
6225 struct drm_mode_fb_cmd2 mode_cmd;
6226
6227 obj = i915_gem_alloc_object(dev,
6228 intel_framebuffer_size_for_mode(mode, bpp));
6229 if (obj == NULL)
6230 return ERR_PTR(-ENOMEM);
6231
6232 mode_cmd.width = mode->hdisplay;
6233 mode_cmd.height = mode->vdisplay;
6234 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6235 bpp);
6236 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6237
6238 return intel_framebuffer_create(dev, &mode_cmd, obj);
6239 }
6240
6241 static struct drm_framebuffer *
6242 mode_fits_in_fbdev(struct drm_device *dev,
6243 struct drm_display_mode *mode)
6244 {
6245 struct drm_i915_private *dev_priv = dev->dev_private;
6246 struct drm_i915_gem_object *obj;
6247 struct drm_framebuffer *fb;
6248
6249 if (dev_priv->fbdev == NULL)
6250 return NULL;
6251
6252 obj = dev_priv->fbdev->ifb.obj;
6253 if (obj == NULL)
6254 return NULL;
6255
6256 fb = &dev_priv->fbdev->ifb.base;
6257 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6258 fb->bits_per_pixel))
6259 return NULL;
6260
6261 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6262 return NULL;
6263
6264 return fb;
6265 }
6266
6267 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6268 struct drm_display_mode *mode,
6269 struct intel_load_detect_pipe *old)
6270 {
6271 struct intel_crtc *intel_crtc;
6272 struct intel_encoder *intel_encoder =
6273 intel_attached_encoder(connector);
6274 struct drm_crtc *possible_crtc;
6275 struct drm_encoder *encoder = &intel_encoder->base;
6276 struct drm_crtc *crtc = NULL;
6277 struct drm_device *dev = encoder->dev;
6278 struct drm_framebuffer *fb;
6279 int i = -1;
6280
6281 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6282 connector->base.id, drm_get_connector_name(connector),
6283 encoder->base.id, drm_get_encoder_name(encoder));
6284
6285 /*
6286 * Algorithm gets a little messy:
6287 *
6288 * - if the connector already has an assigned crtc, use it (but make
6289 * sure it's on first)
6290 *
6291 * - try to find the first unused crtc that can drive this connector,
6292 * and use that if we find one
6293 */
6294
6295 /* See if we already have a CRTC for this connector */
6296 if (encoder->crtc) {
6297 crtc = encoder->crtc;
6298
6299 old->dpms_mode = connector->dpms;
6300 old->load_detect_temp = false;
6301
6302 /* Make sure the crtc and connector are running */
6303 if (connector->dpms != DRM_MODE_DPMS_ON)
6304 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6305
6306 return true;
6307 }
6308
6309 /* Find an unused one (if possible) */
6310 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6311 i++;
6312 if (!(encoder->possible_crtcs & (1 << i)))
6313 continue;
6314 if (!possible_crtc->enabled) {
6315 crtc = possible_crtc;
6316 break;
6317 }
6318 }
6319
6320 /*
6321 * If we didn't find an unused CRTC, don't use any.
6322 */
6323 if (!crtc) {
6324 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6325 return false;
6326 }
6327
6328 intel_encoder->new_crtc = to_intel_crtc(crtc);
6329 to_intel_connector(connector)->new_encoder = intel_encoder;
6330
6331 intel_crtc = to_intel_crtc(crtc);
6332 old->dpms_mode = connector->dpms;
6333 old->load_detect_temp = true;
6334 old->release_fb = NULL;
6335
6336 if (!mode)
6337 mode = &load_detect_mode;
6338
6339 /* We need a framebuffer large enough to accommodate all accesses
6340 * that the plane may generate whilst we perform load detection.
6341 * We can not rely on the fbcon either being present (we get called
6342 * during its initialisation to detect all boot displays, or it may
6343 * not even exist) or that it is large enough to satisfy the
6344 * requested mode.
6345 */
6346 fb = mode_fits_in_fbdev(dev, mode);
6347 if (fb == NULL) {
6348 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6349 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6350 old->release_fb = fb;
6351 } else
6352 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6353 if (IS_ERR(fb)) {
6354 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6355 goto fail;
6356 }
6357
6358 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6359 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6360 if (old->release_fb)
6361 old->release_fb->funcs->destroy(old->release_fb);
6362 goto fail;
6363 }
6364
6365 /* let the connector get through one full cycle before testing */
6366 intel_wait_for_vblank(dev, intel_crtc->pipe);
6367
6368 return true;
6369 fail:
6370 connector->encoder = NULL;
6371 encoder->crtc = NULL;
6372 return false;
6373 }
6374
6375 void intel_release_load_detect_pipe(struct drm_connector *connector,
6376 struct intel_load_detect_pipe *old)
6377 {
6378 struct intel_encoder *intel_encoder =
6379 intel_attached_encoder(connector);
6380 struct drm_encoder *encoder = &intel_encoder->base;
6381
6382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6383 connector->base.id, drm_get_connector_name(connector),
6384 encoder->base.id, drm_get_encoder_name(encoder));
6385
6386 if (old->load_detect_temp) {
6387 struct drm_crtc *crtc = encoder->crtc;
6388
6389 to_intel_connector(connector)->new_encoder = NULL;
6390 intel_encoder->new_crtc = NULL;
6391 intel_set_mode(crtc, NULL, 0, 0, NULL);
6392
6393 if (old->release_fb)
6394 old->release_fb->funcs->destroy(old->release_fb);
6395
6396 return;
6397 }
6398
6399 /* Switch crtc and encoder back off if necessary */
6400 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6401 connector->funcs->dpms(connector, old->dpms_mode);
6402 }
6403
6404 /* Returns the clock of the currently programmed mode of the given pipe. */
6405 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6406 {
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409 int pipe = intel_crtc->pipe;
6410 u32 dpll = I915_READ(DPLL(pipe));
6411 u32 fp;
6412 intel_clock_t clock;
6413
6414 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6415 fp = I915_READ(FP0(pipe));
6416 else
6417 fp = I915_READ(FP1(pipe));
6418
6419 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6420 if (IS_PINEVIEW(dev)) {
6421 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6422 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6423 } else {
6424 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6425 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6426 }
6427
6428 if (!IS_GEN2(dev)) {
6429 if (IS_PINEVIEW(dev))
6430 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6431 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6432 else
6433 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6434 DPLL_FPA01_P1_POST_DIV_SHIFT);
6435
6436 switch (dpll & DPLL_MODE_MASK) {
6437 case DPLLB_MODE_DAC_SERIAL:
6438 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6439 5 : 10;
6440 break;
6441 case DPLLB_MODE_LVDS:
6442 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6443 7 : 14;
6444 break;
6445 default:
6446 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6447 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6448 return 0;
6449 }
6450
6451 /* XXX: Handle the 100Mhz refclk */
6452 intel_clock(dev, 96000, &clock);
6453 } else {
6454 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6455
6456 if (is_lvds) {
6457 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6458 DPLL_FPA01_P1_POST_DIV_SHIFT);
6459 clock.p2 = 14;
6460
6461 if ((dpll & PLL_REF_INPUT_MASK) ==
6462 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6463 /* XXX: might not be 66MHz */
6464 intel_clock(dev, 66000, &clock);
6465 } else
6466 intel_clock(dev, 48000, &clock);
6467 } else {
6468 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6469 clock.p1 = 2;
6470 else {
6471 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6472 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6473 }
6474 if (dpll & PLL_P2_DIVIDE_BY_4)
6475 clock.p2 = 4;
6476 else
6477 clock.p2 = 2;
6478
6479 intel_clock(dev, 48000, &clock);
6480 }
6481 }
6482
6483 /* XXX: It would be nice to validate the clocks, but we can't reuse
6484 * i830PllIsValid() because it relies on the xf86_config connector
6485 * configuration being accurate, which it isn't necessarily.
6486 */
6487
6488 return clock.dot;
6489 }
6490
6491 /** Returns the currently programmed mode of the given pipe. */
6492 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6493 struct drm_crtc *crtc)
6494 {
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6498 struct drm_display_mode *mode;
6499 int htot = I915_READ(HTOTAL(cpu_transcoder));
6500 int hsync = I915_READ(HSYNC(cpu_transcoder));
6501 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6502 int vsync = I915_READ(VSYNC(cpu_transcoder));
6503
6504 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6505 if (!mode)
6506 return NULL;
6507
6508 mode->clock = intel_crtc_clock_get(dev, crtc);
6509 mode->hdisplay = (htot & 0xffff) + 1;
6510 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6511 mode->hsync_start = (hsync & 0xffff) + 1;
6512 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6513 mode->vdisplay = (vtot & 0xffff) + 1;
6514 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6515 mode->vsync_start = (vsync & 0xffff) + 1;
6516 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6517
6518 drm_mode_set_name(mode);
6519
6520 return mode;
6521 }
6522
6523 static void intel_increase_pllclock(struct drm_crtc *crtc)
6524 {
6525 struct drm_device *dev = crtc->dev;
6526 drm_i915_private_t *dev_priv = dev->dev_private;
6527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6528 int pipe = intel_crtc->pipe;
6529 int dpll_reg = DPLL(pipe);
6530 int dpll;
6531
6532 if (HAS_PCH_SPLIT(dev))
6533 return;
6534
6535 if (!dev_priv->lvds_downclock_avail)
6536 return;
6537
6538 dpll = I915_READ(dpll_reg);
6539 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6540 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6541
6542 assert_panel_unlocked(dev_priv, pipe);
6543
6544 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6545 I915_WRITE(dpll_reg, dpll);
6546 intel_wait_for_vblank(dev, pipe);
6547
6548 dpll = I915_READ(dpll_reg);
6549 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6550 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6551 }
6552 }
6553
6554 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6555 {
6556 struct drm_device *dev = crtc->dev;
6557 drm_i915_private_t *dev_priv = dev->dev_private;
6558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559
6560 if (HAS_PCH_SPLIT(dev))
6561 return;
6562
6563 if (!dev_priv->lvds_downclock_avail)
6564 return;
6565
6566 /*
6567 * Since this is called by a timer, we should never get here in
6568 * the manual case.
6569 */
6570 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6571 int pipe = intel_crtc->pipe;
6572 int dpll_reg = DPLL(pipe);
6573 int dpll;
6574
6575 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6576
6577 assert_panel_unlocked(dev_priv, pipe);
6578
6579 dpll = I915_READ(dpll_reg);
6580 dpll |= DISPLAY_RATE_SELECT_FPA1;
6581 I915_WRITE(dpll_reg, dpll);
6582 intel_wait_for_vblank(dev, pipe);
6583 dpll = I915_READ(dpll_reg);
6584 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6585 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6586 }
6587
6588 }
6589
6590 void intel_mark_busy(struct drm_device *dev)
6591 {
6592 i915_update_gfx_val(dev->dev_private);
6593 }
6594
6595 void intel_mark_idle(struct drm_device *dev)
6596 {
6597 }
6598
6599 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6600 {
6601 struct drm_device *dev = obj->base.dev;
6602 struct drm_crtc *crtc;
6603
6604 if (!i915_powersave)
6605 return;
6606
6607 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6608 if (!crtc->fb)
6609 continue;
6610
6611 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6612 intel_increase_pllclock(crtc);
6613 }
6614 }
6615
6616 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6617 {
6618 struct drm_device *dev = obj->base.dev;
6619 struct drm_crtc *crtc;
6620
6621 if (!i915_powersave)
6622 return;
6623
6624 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6625 if (!crtc->fb)
6626 continue;
6627
6628 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6629 intel_decrease_pllclock(crtc);
6630 }
6631 }
6632
6633 static void intel_crtc_destroy(struct drm_crtc *crtc)
6634 {
6635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6636 struct drm_device *dev = crtc->dev;
6637 struct intel_unpin_work *work;
6638 unsigned long flags;
6639
6640 spin_lock_irqsave(&dev->event_lock, flags);
6641 work = intel_crtc->unpin_work;
6642 intel_crtc->unpin_work = NULL;
6643 spin_unlock_irqrestore(&dev->event_lock, flags);
6644
6645 if (work) {
6646 cancel_work_sync(&work->work);
6647 kfree(work);
6648 }
6649
6650 drm_crtc_cleanup(crtc);
6651
6652 kfree(intel_crtc);
6653 }
6654
6655 static void intel_unpin_work_fn(struct work_struct *__work)
6656 {
6657 struct intel_unpin_work *work =
6658 container_of(__work, struct intel_unpin_work, work);
6659
6660 mutex_lock(&work->dev->struct_mutex);
6661 intel_unpin_fb_obj(work->old_fb_obj);
6662 drm_gem_object_unreference(&work->pending_flip_obj->base);
6663 drm_gem_object_unreference(&work->old_fb_obj->base);
6664
6665 intel_update_fbc(work->dev);
6666 mutex_unlock(&work->dev->struct_mutex);
6667 kfree(work);
6668 }
6669
6670 static void do_intel_finish_page_flip(struct drm_device *dev,
6671 struct drm_crtc *crtc)
6672 {
6673 drm_i915_private_t *dev_priv = dev->dev_private;
6674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6675 struct intel_unpin_work *work;
6676 struct drm_i915_gem_object *obj;
6677 struct drm_pending_vblank_event *e;
6678 struct timeval tvbl;
6679 unsigned long flags;
6680
6681 /* Ignore early vblank irqs */
6682 if (intel_crtc == NULL)
6683 return;
6684
6685 spin_lock_irqsave(&dev->event_lock, flags);
6686 work = intel_crtc->unpin_work;
6687 if (work == NULL || !work->pending) {
6688 spin_unlock_irqrestore(&dev->event_lock, flags);
6689 return;
6690 }
6691
6692 intel_crtc->unpin_work = NULL;
6693
6694 if (work->event) {
6695 e = work->event;
6696 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6697
6698 e->event.tv_sec = tvbl.tv_sec;
6699 e->event.tv_usec = tvbl.tv_usec;
6700
6701 list_add_tail(&e->base.link,
6702 &e->base.file_priv->event_list);
6703 wake_up_interruptible(&e->base.file_priv->event_wait);
6704 }
6705
6706 drm_vblank_put(dev, intel_crtc->pipe);
6707
6708 spin_unlock_irqrestore(&dev->event_lock, flags);
6709
6710 obj = work->old_fb_obj;
6711
6712 atomic_clear_mask(1 << intel_crtc->plane,
6713 &obj->pending_flip.counter);
6714
6715 wake_up(&dev_priv->pending_flip_queue);
6716 schedule_work(&work->work);
6717
6718 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6719 }
6720
6721 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6722 {
6723 drm_i915_private_t *dev_priv = dev->dev_private;
6724 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6725
6726 do_intel_finish_page_flip(dev, crtc);
6727 }
6728
6729 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6730 {
6731 drm_i915_private_t *dev_priv = dev->dev_private;
6732 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6733
6734 do_intel_finish_page_flip(dev, crtc);
6735 }
6736
6737 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6738 {
6739 drm_i915_private_t *dev_priv = dev->dev_private;
6740 struct intel_crtc *intel_crtc =
6741 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6742 unsigned long flags;
6743
6744 spin_lock_irqsave(&dev->event_lock, flags);
6745 if (intel_crtc->unpin_work) {
6746 if ((++intel_crtc->unpin_work->pending) > 1)
6747 DRM_ERROR("Prepared flip multiple times\n");
6748 } else {
6749 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6750 }
6751 spin_unlock_irqrestore(&dev->event_lock, flags);
6752 }
6753
6754 static int intel_gen2_queue_flip(struct drm_device *dev,
6755 struct drm_crtc *crtc,
6756 struct drm_framebuffer *fb,
6757 struct drm_i915_gem_object *obj)
6758 {
6759 struct drm_i915_private *dev_priv = dev->dev_private;
6760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6761 u32 flip_mask;
6762 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6763 int ret;
6764
6765 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6766 if (ret)
6767 goto err;
6768
6769 ret = intel_ring_begin(ring, 6);
6770 if (ret)
6771 goto err_unpin;
6772
6773 /* Can't queue multiple flips, so wait for the previous
6774 * one to finish before executing the next.
6775 */
6776 if (intel_crtc->plane)
6777 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6778 else
6779 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6780 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6781 intel_ring_emit(ring, MI_NOOP);
6782 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6783 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6784 intel_ring_emit(ring, fb->pitches[0]);
6785 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6786 intel_ring_emit(ring, 0); /* aux display base address, unused */
6787 intel_ring_advance(ring);
6788 return 0;
6789
6790 err_unpin:
6791 intel_unpin_fb_obj(obj);
6792 err:
6793 return ret;
6794 }
6795
6796 static int intel_gen3_queue_flip(struct drm_device *dev,
6797 struct drm_crtc *crtc,
6798 struct drm_framebuffer *fb,
6799 struct drm_i915_gem_object *obj)
6800 {
6801 struct drm_i915_private *dev_priv = dev->dev_private;
6802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6803 u32 flip_mask;
6804 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6805 int ret;
6806
6807 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6808 if (ret)
6809 goto err;
6810
6811 ret = intel_ring_begin(ring, 6);
6812 if (ret)
6813 goto err_unpin;
6814
6815 if (intel_crtc->plane)
6816 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6817 else
6818 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6819 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6820 intel_ring_emit(ring, MI_NOOP);
6821 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6822 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6823 intel_ring_emit(ring, fb->pitches[0]);
6824 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6825 intel_ring_emit(ring, MI_NOOP);
6826
6827 intel_ring_advance(ring);
6828 return 0;
6829
6830 err_unpin:
6831 intel_unpin_fb_obj(obj);
6832 err:
6833 return ret;
6834 }
6835
6836 static int intel_gen4_queue_flip(struct drm_device *dev,
6837 struct drm_crtc *crtc,
6838 struct drm_framebuffer *fb,
6839 struct drm_i915_gem_object *obj)
6840 {
6841 struct drm_i915_private *dev_priv = dev->dev_private;
6842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6843 uint32_t pf, pipesrc;
6844 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6845 int ret;
6846
6847 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6848 if (ret)
6849 goto err;
6850
6851 ret = intel_ring_begin(ring, 4);
6852 if (ret)
6853 goto err_unpin;
6854
6855 /* i965+ uses the linear or tiled offsets from the
6856 * Display Registers (which do not change across a page-flip)
6857 * so we need only reprogram the base address.
6858 */
6859 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6860 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6861 intel_ring_emit(ring, fb->pitches[0]);
6862 intel_ring_emit(ring,
6863 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6864 obj->tiling_mode);
6865
6866 /* XXX Enabling the panel-fitter across page-flip is so far
6867 * untested on non-native modes, so ignore it for now.
6868 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6869 */
6870 pf = 0;
6871 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6872 intel_ring_emit(ring, pf | pipesrc);
6873 intel_ring_advance(ring);
6874 return 0;
6875
6876 err_unpin:
6877 intel_unpin_fb_obj(obj);
6878 err:
6879 return ret;
6880 }
6881
6882 static int intel_gen6_queue_flip(struct drm_device *dev,
6883 struct drm_crtc *crtc,
6884 struct drm_framebuffer *fb,
6885 struct drm_i915_gem_object *obj)
6886 {
6887 struct drm_i915_private *dev_priv = dev->dev_private;
6888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6889 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6890 uint32_t pf, pipesrc;
6891 int ret;
6892
6893 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6894 if (ret)
6895 goto err;
6896
6897 ret = intel_ring_begin(ring, 4);
6898 if (ret)
6899 goto err_unpin;
6900
6901 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6902 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6903 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6904 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6905
6906 /* Contrary to the suggestions in the documentation,
6907 * "Enable Panel Fitter" does not seem to be required when page
6908 * flipping with a non-native mode, and worse causes a normal
6909 * modeset to fail.
6910 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6911 */
6912 pf = 0;
6913 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6914 intel_ring_emit(ring, pf | pipesrc);
6915 intel_ring_advance(ring);
6916 return 0;
6917
6918 err_unpin:
6919 intel_unpin_fb_obj(obj);
6920 err:
6921 return ret;
6922 }
6923
6924 /*
6925 * On gen7 we currently use the blit ring because (in early silicon at least)
6926 * the render ring doesn't give us interrpts for page flip completion, which
6927 * means clients will hang after the first flip is queued. Fortunately the
6928 * blit ring generates interrupts properly, so use it instead.
6929 */
6930 static int intel_gen7_queue_flip(struct drm_device *dev,
6931 struct drm_crtc *crtc,
6932 struct drm_framebuffer *fb,
6933 struct drm_i915_gem_object *obj)
6934 {
6935 struct drm_i915_private *dev_priv = dev->dev_private;
6936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6937 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6938 uint32_t plane_bit = 0;
6939 int ret;
6940
6941 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6942 if (ret)
6943 goto err;
6944
6945 switch(intel_crtc->plane) {
6946 case PLANE_A:
6947 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6948 break;
6949 case PLANE_B:
6950 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6951 break;
6952 case PLANE_C:
6953 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6954 break;
6955 default:
6956 WARN_ONCE(1, "unknown plane in flip command\n");
6957 ret = -ENODEV;
6958 goto err_unpin;
6959 }
6960
6961 ret = intel_ring_begin(ring, 4);
6962 if (ret)
6963 goto err_unpin;
6964
6965 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6966 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6967 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6968 intel_ring_emit(ring, (MI_NOOP));
6969 intel_ring_advance(ring);
6970 return 0;
6971
6972 err_unpin:
6973 intel_unpin_fb_obj(obj);
6974 err:
6975 return ret;
6976 }
6977
6978 static int intel_default_queue_flip(struct drm_device *dev,
6979 struct drm_crtc *crtc,
6980 struct drm_framebuffer *fb,
6981 struct drm_i915_gem_object *obj)
6982 {
6983 return -ENODEV;
6984 }
6985
6986 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6987 struct drm_framebuffer *fb,
6988 struct drm_pending_vblank_event *event)
6989 {
6990 struct drm_device *dev = crtc->dev;
6991 struct drm_i915_private *dev_priv = dev->dev_private;
6992 struct intel_framebuffer *intel_fb;
6993 struct drm_i915_gem_object *obj;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 struct intel_unpin_work *work;
6996 unsigned long flags;
6997 int ret;
6998
6999 /* Can't change pixel format via MI display flips. */
7000 if (fb->pixel_format != crtc->fb->pixel_format)
7001 return -EINVAL;
7002
7003 /*
7004 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7005 * Note that pitch changes could also affect these register.
7006 */
7007 if (INTEL_INFO(dev)->gen > 3 &&
7008 (fb->offsets[0] != crtc->fb->offsets[0] ||
7009 fb->pitches[0] != crtc->fb->pitches[0]))
7010 return -EINVAL;
7011
7012 work = kzalloc(sizeof *work, GFP_KERNEL);
7013 if (work == NULL)
7014 return -ENOMEM;
7015
7016 work->event = event;
7017 work->dev = crtc->dev;
7018 intel_fb = to_intel_framebuffer(crtc->fb);
7019 work->old_fb_obj = intel_fb->obj;
7020 INIT_WORK(&work->work, intel_unpin_work_fn);
7021
7022 ret = drm_vblank_get(dev, intel_crtc->pipe);
7023 if (ret)
7024 goto free_work;
7025
7026 /* We borrow the event spin lock for protecting unpin_work */
7027 spin_lock_irqsave(&dev->event_lock, flags);
7028 if (intel_crtc->unpin_work) {
7029 spin_unlock_irqrestore(&dev->event_lock, flags);
7030 kfree(work);
7031 drm_vblank_put(dev, intel_crtc->pipe);
7032
7033 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7034 return -EBUSY;
7035 }
7036 intel_crtc->unpin_work = work;
7037 spin_unlock_irqrestore(&dev->event_lock, flags);
7038
7039 intel_fb = to_intel_framebuffer(fb);
7040 obj = intel_fb->obj;
7041
7042 ret = i915_mutex_lock_interruptible(dev);
7043 if (ret)
7044 goto cleanup;
7045
7046 /* Reference the objects for the scheduled work. */
7047 drm_gem_object_reference(&work->old_fb_obj->base);
7048 drm_gem_object_reference(&obj->base);
7049
7050 crtc->fb = fb;
7051
7052 work->pending_flip_obj = obj;
7053
7054 work->enable_stall_check = true;
7055
7056 /* Block clients from rendering to the new back buffer until
7057 * the flip occurs and the object is no longer visible.
7058 */
7059 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7060
7061 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7062 if (ret)
7063 goto cleanup_pending;
7064
7065 intel_disable_fbc(dev);
7066 intel_mark_fb_busy(obj);
7067 mutex_unlock(&dev->struct_mutex);
7068
7069 trace_i915_flip_request(intel_crtc->plane, obj);
7070
7071 return 0;
7072
7073 cleanup_pending:
7074 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7075 drm_gem_object_unreference(&work->old_fb_obj->base);
7076 drm_gem_object_unreference(&obj->base);
7077 mutex_unlock(&dev->struct_mutex);
7078
7079 cleanup:
7080 spin_lock_irqsave(&dev->event_lock, flags);
7081 intel_crtc->unpin_work = NULL;
7082 spin_unlock_irqrestore(&dev->event_lock, flags);
7083
7084 drm_vblank_put(dev, intel_crtc->pipe);
7085 free_work:
7086 kfree(work);
7087
7088 return ret;
7089 }
7090
7091 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7092 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7093 .load_lut = intel_crtc_load_lut,
7094 .disable = intel_crtc_noop,
7095 };
7096
7097 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7098 {
7099 struct intel_encoder *other_encoder;
7100 struct drm_crtc *crtc = &encoder->new_crtc->base;
7101
7102 if (WARN_ON(!crtc))
7103 return false;
7104
7105 list_for_each_entry(other_encoder,
7106 &crtc->dev->mode_config.encoder_list,
7107 base.head) {
7108
7109 if (&other_encoder->new_crtc->base != crtc ||
7110 encoder == other_encoder)
7111 continue;
7112 else
7113 return true;
7114 }
7115
7116 return false;
7117 }
7118
7119 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7120 struct drm_crtc *crtc)
7121 {
7122 struct drm_device *dev;
7123 struct drm_crtc *tmp;
7124 int crtc_mask = 1;
7125
7126 WARN(!crtc, "checking null crtc?\n");
7127
7128 dev = crtc->dev;
7129
7130 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7131 if (tmp == crtc)
7132 break;
7133 crtc_mask <<= 1;
7134 }
7135
7136 if (encoder->possible_crtcs & crtc_mask)
7137 return true;
7138 return false;
7139 }
7140
7141 /**
7142 * intel_modeset_update_staged_output_state
7143 *
7144 * Updates the staged output configuration state, e.g. after we've read out the
7145 * current hw state.
7146 */
7147 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7148 {
7149 struct intel_encoder *encoder;
7150 struct intel_connector *connector;
7151
7152 list_for_each_entry(connector, &dev->mode_config.connector_list,
7153 base.head) {
7154 connector->new_encoder =
7155 to_intel_encoder(connector->base.encoder);
7156 }
7157
7158 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7159 base.head) {
7160 encoder->new_crtc =
7161 to_intel_crtc(encoder->base.crtc);
7162 }
7163 }
7164
7165 /**
7166 * intel_modeset_commit_output_state
7167 *
7168 * This function copies the stage display pipe configuration to the real one.
7169 */
7170 static void intel_modeset_commit_output_state(struct drm_device *dev)
7171 {
7172 struct intel_encoder *encoder;
7173 struct intel_connector *connector;
7174
7175 list_for_each_entry(connector, &dev->mode_config.connector_list,
7176 base.head) {
7177 connector->base.encoder = &connector->new_encoder->base;
7178 }
7179
7180 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7181 base.head) {
7182 encoder->base.crtc = &encoder->new_crtc->base;
7183 }
7184 }
7185
7186 static struct drm_display_mode *
7187 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7188 struct drm_display_mode *mode)
7189 {
7190 struct drm_device *dev = crtc->dev;
7191 struct drm_display_mode *adjusted_mode;
7192 struct drm_encoder_helper_funcs *encoder_funcs;
7193 struct intel_encoder *encoder;
7194
7195 adjusted_mode = drm_mode_duplicate(dev, mode);
7196 if (!adjusted_mode)
7197 return ERR_PTR(-ENOMEM);
7198
7199 /* Pass our mode to the connectors and the CRTC to give them a chance to
7200 * adjust it according to limitations or connector properties, and also
7201 * a chance to reject the mode entirely.
7202 */
7203 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7204 base.head) {
7205
7206 if (&encoder->new_crtc->base != crtc)
7207 continue;
7208 encoder_funcs = encoder->base.helper_private;
7209 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7210 adjusted_mode))) {
7211 DRM_DEBUG_KMS("Encoder fixup failed\n");
7212 goto fail;
7213 }
7214 }
7215
7216 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7217 DRM_DEBUG_KMS("CRTC fixup failed\n");
7218 goto fail;
7219 }
7220 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7221
7222 return adjusted_mode;
7223 fail:
7224 drm_mode_destroy(dev, adjusted_mode);
7225 return ERR_PTR(-EINVAL);
7226 }
7227
7228 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7229 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7230 static void
7231 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7232 unsigned *prepare_pipes, unsigned *disable_pipes)
7233 {
7234 struct intel_crtc *intel_crtc;
7235 struct drm_device *dev = crtc->dev;
7236 struct intel_encoder *encoder;
7237 struct intel_connector *connector;
7238 struct drm_crtc *tmp_crtc;
7239
7240 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7241
7242 /* Check which crtcs have changed outputs connected to them, these need
7243 * to be part of the prepare_pipes mask. We don't (yet) support global
7244 * modeset across multiple crtcs, so modeset_pipes will only have one
7245 * bit set at most. */
7246 list_for_each_entry(connector, &dev->mode_config.connector_list,
7247 base.head) {
7248 if (connector->base.encoder == &connector->new_encoder->base)
7249 continue;
7250
7251 if (connector->base.encoder) {
7252 tmp_crtc = connector->base.encoder->crtc;
7253
7254 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7255 }
7256
7257 if (connector->new_encoder)
7258 *prepare_pipes |=
7259 1 << connector->new_encoder->new_crtc->pipe;
7260 }
7261
7262 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7263 base.head) {
7264 if (encoder->base.crtc == &encoder->new_crtc->base)
7265 continue;
7266
7267 if (encoder->base.crtc) {
7268 tmp_crtc = encoder->base.crtc;
7269
7270 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7271 }
7272
7273 if (encoder->new_crtc)
7274 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7275 }
7276
7277 /* Check for any pipes that will be fully disabled ... */
7278 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7279 base.head) {
7280 bool used = false;
7281
7282 /* Don't try to disable disabled crtcs. */
7283 if (!intel_crtc->base.enabled)
7284 continue;
7285
7286 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7287 base.head) {
7288 if (encoder->new_crtc == intel_crtc)
7289 used = true;
7290 }
7291
7292 if (!used)
7293 *disable_pipes |= 1 << intel_crtc->pipe;
7294 }
7295
7296
7297 /* set_mode is also used to update properties on life display pipes. */
7298 intel_crtc = to_intel_crtc(crtc);
7299 if (crtc->enabled)
7300 *prepare_pipes |= 1 << intel_crtc->pipe;
7301
7302 /* We only support modeset on one single crtc, hence we need to do that
7303 * only for the passed in crtc iff we change anything else than just
7304 * disable crtcs.
7305 *
7306 * This is actually not true, to be fully compatible with the old crtc
7307 * helper we automatically disable _any_ output (i.e. doesn't need to be
7308 * connected to the crtc we're modesetting on) if it's disconnected.
7309 * Which is a rather nutty api (since changed the output configuration
7310 * without userspace's explicit request can lead to confusion), but
7311 * alas. Hence we currently need to modeset on all pipes we prepare. */
7312 if (*prepare_pipes)
7313 *modeset_pipes = *prepare_pipes;
7314
7315 /* ... and mask these out. */
7316 *modeset_pipes &= ~(*disable_pipes);
7317 *prepare_pipes &= ~(*disable_pipes);
7318 }
7319
7320 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7321 {
7322 struct drm_encoder *encoder;
7323 struct drm_device *dev = crtc->dev;
7324
7325 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7326 if (encoder->crtc == crtc)
7327 return true;
7328
7329 return false;
7330 }
7331
7332 static void
7333 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7334 {
7335 struct intel_encoder *intel_encoder;
7336 struct intel_crtc *intel_crtc;
7337 struct drm_connector *connector;
7338
7339 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7340 base.head) {
7341 if (!intel_encoder->base.crtc)
7342 continue;
7343
7344 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7345
7346 if (prepare_pipes & (1 << intel_crtc->pipe))
7347 intel_encoder->connectors_active = false;
7348 }
7349
7350 intel_modeset_commit_output_state(dev);
7351
7352 /* Update computed state. */
7353 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7354 base.head) {
7355 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7356 }
7357
7358 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7359 if (!connector->encoder || !connector->encoder->crtc)
7360 continue;
7361
7362 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7363
7364 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7365 struct drm_property *dpms_property =
7366 dev->mode_config.dpms_property;
7367
7368 connector->dpms = DRM_MODE_DPMS_ON;
7369 drm_connector_property_set_value(connector,
7370 dpms_property,
7371 DRM_MODE_DPMS_ON);
7372
7373 intel_encoder = to_intel_encoder(connector->encoder);
7374 intel_encoder->connectors_active = true;
7375 }
7376 }
7377
7378 }
7379
7380 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7381 list_for_each_entry((intel_crtc), \
7382 &(dev)->mode_config.crtc_list, \
7383 base.head) \
7384 if (mask & (1 <<(intel_crtc)->pipe)) \
7385
7386 void
7387 intel_modeset_check_state(struct drm_device *dev)
7388 {
7389 struct intel_crtc *crtc;
7390 struct intel_encoder *encoder;
7391 struct intel_connector *connector;
7392
7393 list_for_each_entry(connector, &dev->mode_config.connector_list,
7394 base.head) {
7395 /* This also checks the encoder/connector hw state with the
7396 * ->get_hw_state callbacks. */
7397 intel_connector_check_state(connector);
7398
7399 WARN(&connector->new_encoder->base != connector->base.encoder,
7400 "connector's staged encoder doesn't match current encoder\n");
7401 }
7402
7403 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7404 base.head) {
7405 bool enabled = false;
7406 bool active = false;
7407 enum pipe pipe, tracked_pipe;
7408
7409 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7410 encoder->base.base.id,
7411 drm_get_encoder_name(&encoder->base));
7412
7413 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7414 "encoder's stage crtc doesn't match current crtc\n");
7415 WARN(encoder->connectors_active && !encoder->base.crtc,
7416 "encoder's active_connectors set, but no crtc\n");
7417
7418 list_for_each_entry(connector, &dev->mode_config.connector_list,
7419 base.head) {
7420 if (connector->base.encoder != &encoder->base)
7421 continue;
7422 enabled = true;
7423 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7424 active = true;
7425 }
7426 WARN(!!encoder->base.crtc != enabled,
7427 "encoder's enabled state mismatch "
7428 "(expected %i, found %i)\n",
7429 !!encoder->base.crtc, enabled);
7430 WARN(active && !encoder->base.crtc,
7431 "active encoder with no crtc\n");
7432
7433 WARN(encoder->connectors_active != active,
7434 "encoder's computed active state doesn't match tracked active state "
7435 "(expected %i, found %i)\n", active, encoder->connectors_active);
7436
7437 active = encoder->get_hw_state(encoder, &pipe);
7438 WARN(active != encoder->connectors_active,
7439 "encoder's hw state doesn't match sw tracking "
7440 "(expected %i, found %i)\n",
7441 encoder->connectors_active, active);
7442
7443 if (!encoder->base.crtc)
7444 continue;
7445
7446 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7447 WARN(active && pipe != tracked_pipe,
7448 "active encoder's pipe doesn't match"
7449 "(expected %i, found %i)\n",
7450 tracked_pipe, pipe);
7451
7452 }
7453
7454 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7455 base.head) {
7456 bool enabled = false;
7457 bool active = false;
7458
7459 DRM_DEBUG_KMS("[CRTC:%d]\n",
7460 crtc->base.base.id);
7461
7462 WARN(crtc->active && !crtc->base.enabled,
7463 "active crtc, but not enabled in sw tracking\n");
7464
7465 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7466 base.head) {
7467 if (encoder->base.crtc != &crtc->base)
7468 continue;
7469 enabled = true;
7470 if (encoder->connectors_active)
7471 active = true;
7472 }
7473 WARN(active != crtc->active,
7474 "crtc's computed active state doesn't match tracked active state "
7475 "(expected %i, found %i)\n", active, crtc->active);
7476 WARN(enabled != crtc->base.enabled,
7477 "crtc's computed enabled state doesn't match tracked enabled state "
7478 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7479
7480 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7481 }
7482 }
7483
7484 bool intel_set_mode(struct drm_crtc *crtc,
7485 struct drm_display_mode *mode,
7486 int x, int y, struct drm_framebuffer *fb)
7487 {
7488 struct drm_device *dev = crtc->dev;
7489 drm_i915_private_t *dev_priv = dev->dev_private;
7490 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7491 struct drm_encoder_helper_funcs *encoder_funcs;
7492 struct drm_encoder *encoder;
7493 struct intel_crtc *intel_crtc;
7494 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7495 bool ret = true;
7496
7497 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7498 &prepare_pipes, &disable_pipes);
7499
7500 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7501 modeset_pipes, prepare_pipes, disable_pipes);
7502
7503 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7504 intel_crtc_disable(&intel_crtc->base);
7505
7506 saved_hwmode = crtc->hwmode;
7507 saved_mode = crtc->mode;
7508
7509 /* Hack: Because we don't (yet) support global modeset on multiple
7510 * crtcs, we don't keep track of the new mode for more than one crtc.
7511 * Hence simply check whether any bit is set in modeset_pipes in all the
7512 * pieces of code that are not yet converted to deal with mutliple crtcs
7513 * changing their mode at the same time. */
7514 adjusted_mode = NULL;
7515 if (modeset_pipes) {
7516 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7517 if (IS_ERR(adjusted_mode)) {
7518 return false;
7519 }
7520 }
7521
7522 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7523 if (intel_crtc->base.enabled)
7524 dev_priv->display.crtc_disable(&intel_crtc->base);
7525 }
7526
7527 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7528 * to set it here already despite that we pass it down the callchain.
7529 */
7530 if (modeset_pipes)
7531 crtc->mode = *mode;
7532
7533 /* Only after disabling all output pipelines that will be changed can we
7534 * update the the output configuration. */
7535 intel_modeset_update_state(dev, prepare_pipes);
7536
7537 /* Set up the DPLL and any encoders state that needs to adjust or depend
7538 * on the DPLL.
7539 */
7540 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7541 ret = !intel_crtc_mode_set(&intel_crtc->base,
7542 mode, adjusted_mode,
7543 x, y, fb);
7544 if (!ret)
7545 goto done;
7546
7547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7548
7549 if (encoder->crtc != &intel_crtc->base)
7550 continue;
7551
7552 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7553 encoder->base.id, drm_get_encoder_name(encoder),
7554 mode->base.id, mode->name);
7555 encoder_funcs = encoder->helper_private;
7556 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7557 }
7558 }
7559
7560 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7561 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7562 dev_priv->display.crtc_enable(&intel_crtc->base);
7563
7564 if (modeset_pipes) {
7565 /* Store real post-adjustment hardware mode. */
7566 crtc->hwmode = *adjusted_mode;
7567
7568 /* Calculate and store various constants which
7569 * are later needed by vblank and swap-completion
7570 * timestamping. They are derived from true hwmode.
7571 */
7572 drm_calc_timestamping_constants(crtc);
7573 }
7574
7575 /* FIXME: add subpixel order */
7576 done:
7577 drm_mode_destroy(dev, adjusted_mode);
7578 if (!ret && crtc->enabled) {
7579 crtc->hwmode = saved_hwmode;
7580 crtc->mode = saved_mode;
7581 } else {
7582 intel_modeset_check_state(dev);
7583 }
7584
7585 return ret;
7586 }
7587
7588 #undef for_each_intel_crtc_masked
7589
7590 static void intel_set_config_free(struct intel_set_config *config)
7591 {
7592 if (!config)
7593 return;
7594
7595 kfree(config->save_connector_encoders);
7596 kfree(config->save_encoder_crtcs);
7597 kfree(config);
7598 }
7599
7600 static int intel_set_config_save_state(struct drm_device *dev,
7601 struct intel_set_config *config)
7602 {
7603 struct drm_encoder *encoder;
7604 struct drm_connector *connector;
7605 int count;
7606
7607 config->save_encoder_crtcs =
7608 kcalloc(dev->mode_config.num_encoder,
7609 sizeof(struct drm_crtc *), GFP_KERNEL);
7610 if (!config->save_encoder_crtcs)
7611 return -ENOMEM;
7612
7613 config->save_connector_encoders =
7614 kcalloc(dev->mode_config.num_connector,
7615 sizeof(struct drm_encoder *), GFP_KERNEL);
7616 if (!config->save_connector_encoders)
7617 return -ENOMEM;
7618
7619 /* Copy data. Note that driver private data is not affected.
7620 * Should anything bad happen only the expected state is
7621 * restored, not the drivers personal bookkeeping.
7622 */
7623 count = 0;
7624 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7625 config->save_encoder_crtcs[count++] = encoder->crtc;
7626 }
7627
7628 count = 0;
7629 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7630 config->save_connector_encoders[count++] = connector->encoder;
7631 }
7632
7633 return 0;
7634 }
7635
7636 static void intel_set_config_restore_state(struct drm_device *dev,
7637 struct intel_set_config *config)
7638 {
7639 struct intel_encoder *encoder;
7640 struct intel_connector *connector;
7641 int count;
7642
7643 count = 0;
7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7645 encoder->new_crtc =
7646 to_intel_crtc(config->save_encoder_crtcs[count++]);
7647 }
7648
7649 count = 0;
7650 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7651 connector->new_encoder =
7652 to_intel_encoder(config->save_connector_encoders[count++]);
7653 }
7654 }
7655
7656 static void
7657 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7658 struct intel_set_config *config)
7659 {
7660
7661 /* We should be able to check here if the fb has the same properties
7662 * and then just flip_or_move it */
7663 if (set->crtc->fb != set->fb) {
7664 /* If we have no fb then treat it as a full mode set */
7665 if (set->crtc->fb == NULL) {
7666 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7667 config->mode_changed = true;
7668 } else if (set->fb == NULL) {
7669 config->mode_changed = true;
7670 } else if (set->fb->depth != set->crtc->fb->depth) {
7671 config->mode_changed = true;
7672 } else if (set->fb->bits_per_pixel !=
7673 set->crtc->fb->bits_per_pixel) {
7674 config->mode_changed = true;
7675 } else
7676 config->fb_changed = true;
7677 }
7678
7679 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7680 config->fb_changed = true;
7681
7682 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7683 DRM_DEBUG_KMS("modes are different, full mode set\n");
7684 drm_mode_debug_printmodeline(&set->crtc->mode);
7685 drm_mode_debug_printmodeline(set->mode);
7686 config->mode_changed = true;
7687 }
7688 }
7689
7690 static int
7691 intel_modeset_stage_output_state(struct drm_device *dev,
7692 struct drm_mode_set *set,
7693 struct intel_set_config *config)
7694 {
7695 struct drm_crtc *new_crtc;
7696 struct intel_connector *connector;
7697 struct intel_encoder *encoder;
7698 int count, ro;
7699
7700 /* The upper layers ensure that we either disabl a crtc or have a list
7701 * of connectors. For paranoia, double-check this. */
7702 WARN_ON(!set->fb && (set->num_connectors != 0));
7703 WARN_ON(set->fb && (set->num_connectors == 0));
7704
7705 count = 0;
7706 list_for_each_entry(connector, &dev->mode_config.connector_list,
7707 base.head) {
7708 /* Otherwise traverse passed in connector list and get encoders
7709 * for them. */
7710 for (ro = 0; ro < set->num_connectors; ro++) {
7711 if (set->connectors[ro] == &connector->base) {
7712 connector->new_encoder = connector->encoder;
7713 break;
7714 }
7715 }
7716
7717 /* If we disable the crtc, disable all its connectors. Also, if
7718 * the connector is on the changing crtc but not on the new
7719 * connector list, disable it. */
7720 if ((!set->fb || ro == set->num_connectors) &&
7721 connector->base.encoder &&
7722 connector->base.encoder->crtc == set->crtc) {
7723 connector->new_encoder = NULL;
7724
7725 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7726 connector->base.base.id,
7727 drm_get_connector_name(&connector->base));
7728 }
7729
7730
7731 if (&connector->new_encoder->base != connector->base.encoder) {
7732 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7733 config->mode_changed = true;
7734 }
7735
7736 /* Disable all disconnected encoders. */
7737 if (connector->base.status == connector_status_disconnected)
7738 connector->new_encoder = NULL;
7739 }
7740 /* connector->new_encoder is now updated for all connectors. */
7741
7742 /* Update crtc of enabled connectors. */
7743 count = 0;
7744 list_for_each_entry(connector, &dev->mode_config.connector_list,
7745 base.head) {
7746 if (!connector->new_encoder)
7747 continue;
7748
7749 new_crtc = connector->new_encoder->base.crtc;
7750
7751 for (ro = 0; ro < set->num_connectors; ro++) {
7752 if (set->connectors[ro] == &connector->base)
7753 new_crtc = set->crtc;
7754 }
7755
7756 /* Make sure the new CRTC will work with the encoder */
7757 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7758 new_crtc)) {
7759 return -EINVAL;
7760 }
7761 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7762
7763 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7764 connector->base.base.id,
7765 drm_get_connector_name(&connector->base),
7766 new_crtc->base.id);
7767 }
7768
7769 /* Check for any encoders that needs to be disabled. */
7770 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7771 base.head) {
7772 list_for_each_entry(connector,
7773 &dev->mode_config.connector_list,
7774 base.head) {
7775 if (connector->new_encoder == encoder) {
7776 WARN_ON(!connector->new_encoder->new_crtc);
7777
7778 goto next_encoder;
7779 }
7780 }
7781 encoder->new_crtc = NULL;
7782 next_encoder:
7783 /* Only now check for crtc changes so we don't miss encoders
7784 * that will be disabled. */
7785 if (&encoder->new_crtc->base != encoder->base.crtc) {
7786 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7787 config->mode_changed = true;
7788 }
7789 }
7790 /* Now we've also updated encoder->new_crtc for all encoders. */
7791
7792 return 0;
7793 }
7794
7795 static int intel_crtc_set_config(struct drm_mode_set *set)
7796 {
7797 struct drm_device *dev;
7798 struct drm_mode_set save_set;
7799 struct intel_set_config *config;
7800 int ret;
7801
7802 BUG_ON(!set);
7803 BUG_ON(!set->crtc);
7804 BUG_ON(!set->crtc->helper_private);
7805
7806 if (!set->mode)
7807 set->fb = NULL;
7808
7809 /* The fb helper likes to play gross jokes with ->mode_set_config.
7810 * Unfortunately the crtc helper doesn't do much at all for this case,
7811 * so we have to cope with this madness until the fb helper is fixed up. */
7812 if (set->fb && set->num_connectors == 0)
7813 return 0;
7814
7815 if (set->fb) {
7816 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7817 set->crtc->base.id, set->fb->base.id,
7818 (int)set->num_connectors, set->x, set->y);
7819 } else {
7820 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7821 }
7822
7823 dev = set->crtc->dev;
7824
7825 ret = -ENOMEM;
7826 config = kzalloc(sizeof(*config), GFP_KERNEL);
7827 if (!config)
7828 goto out_config;
7829
7830 ret = intel_set_config_save_state(dev, config);
7831 if (ret)
7832 goto out_config;
7833
7834 save_set.crtc = set->crtc;
7835 save_set.mode = &set->crtc->mode;
7836 save_set.x = set->crtc->x;
7837 save_set.y = set->crtc->y;
7838 save_set.fb = set->crtc->fb;
7839
7840 /* Compute whether we need a full modeset, only an fb base update or no
7841 * change at all. In the future we might also check whether only the
7842 * mode changed, e.g. for LVDS where we only change the panel fitter in
7843 * such cases. */
7844 intel_set_config_compute_mode_changes(set, config);
7845
7846 ret = intel_modeset_stage_output_state(dev, set, config);
7847 if (ret)
7848 goto fail;
7849
7850 if (config->mode_changed) {
7851 if (set->mode) {
7852 DRM_DEBUG_KMS("attempting to set mode from"
7853 " userspace\n");
7854 drm_mode_debug_printmodeline(set->mode);
7855 }
7856
7857 if (!intel_set_mode(set->crtc, set->mode,
7858 set->x, set->y, set->fb)) {
7859 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7860 set->crtc->base.id);
7861 ret = -EINVAL;
7862 goto fail;
7863 }
7864 } else if (config->fb_changed) {
7865 ret = intel_pipe_set_base(set->crtc,
7866 set->x, set->y, set->fb);
7867 }
7868
7869 intel_set_config_free(config);
7870
7871 return 0;
7872
7873 fail:
7874 intel_set_config_restore_state(dev, config);
7875
7876 /* Try to restore the config */
7877 if (config->mode_changed &&
7878 !intel_set_mode(save_set.crtc, save_set.mode,
7879 save_set.x, save_set.y, save_set.fb))
7880 DRM_ERROR("failed to restore config after modeset failure\n");
7881
7882 out_config:
7883 intel_set_config_free(config);
7884 return ret;
7885 }
7886
7887 static const struct drm_crtc_funcs intel_crtc_funcs = {
7888 .cursor_set = intel_crtc_cursor_set,
7889 .cursor_move = intel_crtc_cursor_move,
7890 .gamma_set = intel_crtc_gamma_set,
7891 .set_config = intel_crtc_set_config,
7892 .destroy = intel_crtc_destroy,
7893 .page_flip = intel_crtc_page_flip,
7894 };
7895
7896 static void intel_cpu_pll_init(struct drm_device *dev)
7897 {
7898 if (IS_HASWELL(dev))
7899 intel_ddi_pll_init(dev);
7900 }
7901
7902 static void intel_pch_pll_init(struct drm_device *dev)
7903 {
7904 drm_i915_private_t *dev_priv = dev->dev_private;
7905 int i;
7906
7907 if (dev_priv->num_pch_pll == 0) {
7908 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7909 return;
7910 }
7911
7912 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7913 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7914 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7915 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7916 }
7917 }
7918
7919 static void intel_crtc_init(struct drm_device *dev, int pipe)
7920 {
7921 drm_i915_private_t *dev_priv = dev->dev_private;
7922 struct intel_crtc *intel_crtc;
7923 int i;
7924
7925 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7926 if (intel_crtc == NULL)
7927 return;
7928
7929 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7930
7931 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7932 for (i = 0; i < 256; i++) {
7933 intel_crtc->lut_r[i] = i;
7934 intel_crtc->lut_g[i] = i;
7935 intel_crtc->lut_b[i] = i;
7936 }
7937
7938 /* Swap pipes & planes for FBC on pre-965 */
7939 intel_crtc->pipe = pipe;
7940 intel_crtc->plane = pipe;
7941 intel_crtc->cpu_transcoder = pipe;
7942 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7943 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7944 intel_crtc->plane = !pipe;
7945 }
7946
7947 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7948 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7949 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7950 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7951
7952 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7953
7954 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7955 }
7956
7957 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7958 struct drm_file *file)
7959 {
7960 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7961 struct drm_mode_object *drmmode_obj;
7962 struct intel_crtc *crtc;
7963
7964 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7965 return -ENODEV;
7966
7967 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7968 DRM_MODE_OBJECT_CRTC);
7969
7970 if (!drmmode_obj) {
7971 DRM_ERROR("no such CRTC id\n");
7972 return -EINVAL;
7973 }
7974
7975 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7976 pipe_from_crtc_id->pipe = crtc->pipe;
7977
7978 return 0;
7979 }
7980
7981 static int intel_encoder_clones(struct intel_encoder *encoder)
7982 {
7983 struct drm_device *dev = encoder->base.dev;
7984 struct intel_encoder *source_encoder;
7985 int index_mask = 0;
7986 int entry = 0;
7987
7988 list_for_each_entry(source_encoder,
7989 &dev->mode_config.encoder_list, base.head) {
7990
7991 if (encoder == source_encoder)
7992 index_mask |= (1 << entry);
7993
7994 /* Intel hw has only one MUX where enocoders could be cloned. */
7995 if (encoder->cloneable && source_encoder->cloneable)
7996 index_mask |= (1 << entry);
7997
7998 entry++;
7999 }
8000
8001 return index_mask;
8002 }
8003
8004 static bool has_edp_a(struct drm_device *dev)
8005 {
8006 struct drm_i915_private *dev_priv = dev->dev_private;
8007
8008 if (!IS_MOBILE(dev))
8009 return false;
8010
8011 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8012 return false;
8013
8014 if (IS_GEN5(dev) &&
8015 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8016 return false;
8017
8018 return true;
8019 }
8020
8021 static void intel_setup_outputs(struct drm_device *dev)
8022 {
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 struct intel_encoder *encoder;
8025 bool dpd_is_edp = false;
8026 bool has_lvds;
8027
8028 has_lvds = intel_lvds_init(dev);
8029 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8030 /* disable the panel fitter on everything but LVDS */
8031 I915_WRITE(PFIT_CONTROL, 0);
8032 }
8033
8034 if (HAS_PCH_SPLIT(dev)) {
8035 dpd_is_edp = intel_dpd_is_edp(dev);
8036
8037 if (has_edp_a(dev))
8038 intel_dp_init(dev, DP_A, PORT_A);
8039
8040 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8041 intel_dp_init(dev, PCH_DP_D, PORT_D);
8042 }
8043
8044 intel_crt_init(dev);
8045
8046 if (IS_HASWELL(dev)) {
8047 int found;
8048
8049 /* Haswell uses DDI functions to detect digital outputs */
8050 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8051 /* DDI A only supports eDP */
8052 if (found)
8053 intel_ddi_init(dev, PORT_A);
8054
8055 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8056 * register */
8057 found = I915_READ(SFUSE_STRAP);
8058
8059 if (found & SFUSE_STRAP_DDIB_DETECTED)
8060 intel_ddi_init(dev, PORT_B);
8061 if (found & SFUSE_STRAP_DDIC_DETECTED)
8062 intel_ddi_init(dev, PORT_C);
8063 if (found & SFUSE_STRAP_DDID_DETECTED)
8064 intel_ddi_init(dev, PORT_D);
8065 } else if (HAS_PCH_SPLIT(dev)) {
8066 int found;
8067
8068 if (I915_READ(HDMIB) & PORT_DETECTED) {
8069 /* PCH SDVOB multiplex with HDMIB */
8070 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8071 if (!found)
8072 intel_hdmi_init(dev, HDMIB, PORT_B);
8073 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8074 intel_dp_init(dev, PCH_DP_B, PORT_B);
8075 }
8076
8077 if (I915_READ(HDMIC) & PORT_DETECTED)
8078 intel_hdmi_init(dev, HDMIC, PORT_C);
8079
8080 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8081 intel_hdmi_init(dev, HDMID, PORT_D);
8082
8083 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8084 intel_dp_init(dev, PCH_DP_C, PORT_C);
8085
8086 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8087 intel_dp_init(dev, PCH_DP_D, PORT_D);
8088 } else if (IS_VALLEYVIEW(dev)) {
8089 int found;
8090
8091 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8092 if (I915_READ(DP_C) & DP_DETECTED)
8093 intel_dp_init(dev, DP_C, PORT_C);
8094
8095 if (I915_READ(SDVOB) & PORT_DETECTED) {
8096 /* SDVOB multiplex with HDMIB */
8097 found = intel_sdvo_init(dev, SDVOB, true);
8098 if (!found)
8099 intel_hdmi_init(dev, SDVOB, PORT_B);
8100 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8101 intel_dp_init(dev, DP_B, PORT_B);
8102 }
8103
8104 if (I915_READ(SDVOC) & PORT_DETECTED)
8105 intel_hdmi_init(dev, SDVOC, PORT_C);
8106
8107 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8108 bool found = false;
8109
8110 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8111 DRM_DEBUG_KMS("probing SDVOB\n");
8112 found = intel_sdvo_init(dev, SDVOB, true);
8113 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8114 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8115 intel_hdmi_init(dev, SDVOB, PORT_B);
8116 }
8117
8118 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8119 DRM_DEBUG_KMS("probing DP_B\n");
8120 intel_dp_init(dev, DP_B, PORT_B);
8121 }
8122 }
8123
8124 /* Before G4X SDVOC doesn't have its own detect register */
8125
8126 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8127 DRM_DEBUG_KMS("probing SDVOC\n");
8128 found = intel_sdvo_init(dev, SDVOC, false);
8129 }
8130
8131 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8132
8133 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8134 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8135 intel_hdmi_init(dev, SDVOC, PORT_C);
8136 }
8137 if (SUPPORTS_INTEGRATED_DP(dev)) {
8138 DRM_DEBUG_KMS("probing DP_C\n");
8139 intel_dp_init(dev, DP_C, PORT_C);
8140 }
8141 }
8142
8143 if (SUPPORTS_INTEGRATED_DP(dev) &&
8144 (I915_READ(DP_D) & DP_DETECTED)) {
8145 DRM_DEBUG_KMS("probing DP_D\n");
8146 intel_dp_init(dev, DP_D, PORT_D);
8147 }
8148 } else if (IS_GEN2(dev))
8149 intel_dvo_init(dev);
8150
8151 if (SUPPORTS_TV(dev))
8152 intel_tv_init(dev);
8153
8154 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8155 encoder->base.possible_crtcs = encoder->crtc_mask;
8156 encoder->base.possible_clones =
8157 intel_encoder_clones(encoder);
8158 }
8159
8160 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8161 ironlake_init_pch_refclk(dev);
8162 }
8163
8164 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8165 {
8166 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8167
8168 drm_framebuffer_cleanup(fb);
8169 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8170
8171 kfree(intel_fb);
8172 }
8173
8174 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8175 struct drm_file *file,
8176 unsigned int *handle)
8177 {
8178 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8179 struct drm_i915_gem_object *obj = intel_fb->obj;
8180
8181 return drm_gem_handle_create(file, &obj->base, handle);
8182 }
8183
8184 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8185 .destroy = intel_user_framebuffer_destroy,
8186 .create_handle = intel_user_framebuffer_create_handle,
8187 };
8188
8189 int intel_framebuffer_init(struct drm_device *dev,
8190 struct intel_framebuffer *intel_fb,
8191 struct drm_mode_fb_cmd2 *mode_cmd,
8192 struct drm_i915_gem_object *obj)
8193 {
8194 int ret;
8195
8196 if (obj->tiling_mode == I915_TILING_Y)
8197 return -EINVAL;
8198
8199 if (mode_cmd->pitches[0] & 63)
8200 return -EINVAL;
8201
8202 switch (mode_cmd->pixel_format) {
8203 case DRM_FORMAT_RGB332:
8204 case DRM_FORMAT_RGB565:
8205 case DRM_FORMAT_XRGB8888:
8206 case DRM_FORMAT_XBGR8888:
8207 case DRM_FORMAT_ARGB8888:
8208 case DRM_FORMAT_XRGB2101010:
8209 case DRM_FORMAT_ARGB2101010:
8210 /* RGB formats are common across chipsets */
8211 break;
8212 case DRM_FORMAT_YUYV:
8213 case DRM_FORMAT_UYVY:
8214 case DRM_FORMAT_YVYU:
8215 case DRM_FORMAT_VYUY:
8216 break;
8217 default:
8218 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8219 mode_cmd->pixel_format);
8220 return -EINVAL;
8221 }
8222
8223 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8224 if (ret) {
8225 DRM_ERROR("framebuffer init failed %d\n", ret);
8226 return ret;
8227 }
8228
8229 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8230 intel_fb->obj = obj;
8231 return 0;
8232 }
8233
8234 static struct drm_framebuffer *
8235 intel_user_framebuffer_create(struct drm_device *dev,
8236 struct drm_file *filp,
8237 struct drm_mode_fb_cmd2 *mode_cmd)
8238 {
8239 struct drm_i915_gem_object *obj;
8240
8241 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8242 mode_cmd->handles[0]));
8243 if (&obj->base == NULL)
8244 return ERR_PTR(-ENOENT);
8245
8246 return intel_framebuffer_create(dev, mode_cmd, obj);
8247 }
8248
8249 static const struct drm_mode_config_funcs intel_mode_funcs = {
8250 .fb_create = intel_user_framebuffer_create,
8251 .output_poll_changed = intel_fb_output_poll_changed,
8252 };
8253
8254 /* Set up chip specific display functions */
8255 static void intel_init_display(struct drm_device *dev)
8256 {
8257 struct drm_i915_private *dev_priv = dev->dev_private;
8258
8259 /* We always want a DPMS function */
8260 if (IS_HASWELL(dev)) {
8261 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8262 dev_priv->display.crtc_enable = haswell_crtc_enable;
8263 dev_priv->display.crtc_disable = haswell_crtc_disable;
8264 dev_priv->display.off = haswell_crtc_off;
8265 dev_priv->display.update_plane = ironlake_update_plane;
8266 } else if (HAS_PCH_SPLIT(dev)) {
8267 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8268 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8269 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8270 dev_priv->display.off = ironlake_crtc_off;
8271 dev_priv->display.update_plane = ironlake_update_plane;
8272 } else {
8273 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8274 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8275 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8276 dev_priv->display.off = i9xx_crtc_off;
8277 dev_priv->display.update_plane = i9xx_update_plane;
8278 }
8279
8280 /* Returns the core display clock speed */
8281 if (IS_VALLEYVIEW(dev))
8282 dev_priv->display.get_display_clock_speed =
8283 valleyview_get_display_clock_speed;
8284 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8285 dev_priv->display.get_display_clock_speed =
8286 i945_get_display_clock_speed;
8287 else if (IS_I915G(dev))
8288 dev_priv->display.get_display_clock_speed =
8289 i915_get_display_clock_speed;
8290 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8291 dev_priv->display.get_display_clock_speed =
8292 i9xx_misc_get_display_clock_speed;
8293 else if (IS_I915GM(dev))
8294 dev_priv->display.get_display_clock_speed =
8295 i915gm_get_display_clock_speed;
8296 else if (IS_I865G(dev))
8297 dev_priv->display.get_display_clock_speed =
8298 i865_get_display_clock_speed;
8299 else if (IS_I85X(dev))
8300 dev_priv->display.get_display_clock_speed =
8301 i855_get_display_clock_speed;
8302 else /* 852, 830 */
8303 dev_priv->display.get_display_clock_speed =
8304 i830_get_display_clock_speed;
8305
8306 if (HAS_PCH_SPLIT(dev)) {
8307 if (IS_GEN5(dev)) {
8308 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8309 dev_priv->display.write_eld = ironlake_write_eld;
8310 } else if (IS_GEN6(dev)) {
8311 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8312 dev_priv->display.write_eld = ironlake_write_eld;
8313 } else if (IS_IVYBRIDGE(dev)) {
8314 /* FIXME: detect B0+ stepping and use auto training */
8315 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8316 dev_priv->display.write_eld = ironlake_write_eld;
8317 } else if (IS_HASWELL(dev)) {
8318 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8319 dev_priv->display.write_eld = haswell_write_eld;
8320 } else
8321 dev_priv->display.update_wm = NULL;
8322 } else if (IS_G4X(dev)) {
8323 dev_priv->display.write_eld = g4x_write_eld;
8324 }
8325
8326 /* Default just returns -ENODEV to indicate unsupported */
8327 dev_priv->display.queue_flip = intel_default_queue_flip;
8328
8329 switch (INTEL_INFO(dev)->gen) {
8330 case 2:
8331 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8332 break;
8333
8334 case 3:
8335 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8336 break;
8337
8338 case 4:
8339 case 5:
8340 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8341 break;
8342
8343 case 6:
8344 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8345 break;
8346 case 7:
8347 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8348 break;
8349 }
8350 }
8351
8352 /*
8353 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8354 * resume, or other times. This quirk makes sure that's the case for
8355 * affected systems.
8356 */
8357 static void quirk_pipea_force(struct drm_device *dev)
8358 {
8359 struct drm_i915_private *dev_priv = dev->dev_private;
8360
8361 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8362 DRM_INFO("applying pipe a force quirk\n");
8363 }
8364
8365 /*
8366 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8367 */
8368 static void quirk_ssc_force_disable(struct drm_device *dev)
8369 {
8370 struct drm_i915_private *dev_priv = dev->dev_private;
8371 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8372 DRM_INFO("applying lvds SSC disable quirk\n");
8373 }
8374
8375 /*
8376 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8377 * brightness value
8378 */
8379 static void quirk_invert_brightness(struct drm_device *dev)
8380 {
8381 struct drm_i915_private *dev_priv = dev->dev_private;
8382 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8383 DRM_INFO("applying inverted panel brightness quirk\n");
8384 }
8385
8386 struct intel_quirk {
8387 int device;
8388 int subsystem_vendor;
8389 int subsystem_device;
8390 void (*hook)(struct drm_device *dev);
8391 };
8392
8393 static struct intel_quirk intel_quirks[] = {
8394 /* HP Mini needs pipe A force quirk (LP: #322104) */
8395 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8396
8397 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8398 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8399
8400 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8401 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8402
8403 /* 830/845 need to leave pipe A & dpll A up */
8404 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8405 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8406
8407 /* Lenovo U160 cannot use SSC on LVDS */
8408 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8409
8410 /* Sony Vaio Y cannot use SSC on LVDS */
8411 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8412
8413 /* Acer Aspire 5734Z must invert backlight brightness */
8414 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8415 };
8416
8417 static void intel_init_quirks(struct drm_device *dev)
8418 {
8419 struct pci_dev *d = dev->pdev;
8420 int i;
8421
8422 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8423 struct intel_quirk *q = &intel_quirks[i];
8424
8425 if (d->device == q->device &&
8426 (d->subsystem_vendor == q->subsystem_vendor ||
8427 q->subsystem_vendor == PCI_ANY_ID) &&
8428 (d->subsystem_device == q->subsystem_device ||
8429 q->subsystem_device == PCI_ANY_ID))
8430 q->hook(dev);
8431 }
8432 }
8433
8434 /* Disable the VGA plane that we never use */
8435 static void i915_disable_vga(struct drm_device *dev)
8436 {
8437 struct drm_i915_private *dev_priv = dev->dev_private;
8438 u8 sr1;
8439 u32 vga_reg;
8440
8441 if (HAS_PCH_SPLIT(dev))
8442 vga_reg = CPU_VGACNTRL;
8443 else
8444 vga_reg = VGACNTRL;
8445
8446 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8447 outb(SR01, VGA_SR_INDEX);
8448 sr1 = inb(VGA_SR_DATA);
8449 outb(sr1 | 1<<5, VGA_SR_DATA);
8450 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8451 udelay(300);
8452
8453 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8454 POSTING_READ(vga_reg);
8455 }
8456
8457 void intel_modeset_init_hw(struct drm_device *dev)
8458 {
8459 /* We attempt to init the necessary power wells early in the initialization
8460 * time, so the subsystems that expect power to be enabled can work.
8461 */
8462 intel_init_power_wells(dev);
8463
8464 intel_prepare_ddi(dev);
8465
8466 intel_init_clock_gating(dev);
8467
8468 mutex_lock(&dev->struct_mutex);
8469 intel_enable_gt_powersave(dev);
8470 mutex_unlock(&dev->struct_mutex);
8471 }
8472
8473 void intel_modeset_init(struct drm_device *dev)
8474 {
8475 struct drm_i915_private *dev_priv = dev->dev_private;
8476 int i, ret;
8477
8478 drm_mode_config_init(dev);
8479
8480 dev->mode_config.min_width = 0;
8481 dev->mode_config.min_height = 0;
8482
8483 dev->mode_config.preferred_depth = 24;
8484 dev->mode_config.prefer_shadow = 1;
8485
8486 dev->mode_config.funcs = &intel_mode_funcs;
8487
8488 intel_init_quirks(dev);
8489
8490 intel_init_pm(dev);
8491
8492 intel_init_display(dev);
8493
8494 if (IS_GEN2(dev)) {
8495 dev->mode_config.max_width = 2048;
8496 dev->mode_config.max_height = 2048;
8497 } else if (IS_GEN3(dev)) {
8498 dev->mode_config.max_width = 4096;
8499 dev->mode_config.max_height = 4096;
8500 } else {
8501 dev->mode_config.max_width = 8192;
8502 dev->mode_config.max_height = 8192;
8503 }
8504 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8505
8506 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8507 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8508
8509 for (i = 0; i < dev_priv->num_pipe; i++) {
8510 intel_crtc_init(dev, i);
8511 ret = intel_plane_init(dev, i);
8512 if (ret)
8513 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8514 }
8515
8516 intel_cpu_pll_init(dev);
8517 intel_pch_pll_init(dev);
8518
8519 /* Just disable it once at startup */
8520 i915_disable_vga(dev);
8521 intel_setup_outputs(dev);
8522 }
8523
8524 static void
8525 intel_connector_break_all_links(struct intel_connector *connector)
8526 {
8527 connector->base.dpms = DRM_MODE_DPMS_OFF;
8528 connector->base.encoder = NULL;
8529 connector->encoder->connectors_active = false;
8530 connector->encoder->base.crtc = NULL;
8531 }
8532
8533 static void intel_enable_pipe_a(struct drm_device *dev)
8534 {
8535 struct intel_connector *connector;
8536 struct drm_connector *crt = NULL;
8537 struct intel_load_detect_pipe load_detect_temp;
8538
8539 /* We can't just switch on the pipe A, we need to set things up with a
8540 * proper mode and output configuration. As a gross hack, enable pipe A
8541 * by enabling the load detect pipe once. */
8542 list_for_each_entry(connector,
8543 &dev->mode_config.connector_list,
8544 base.head) {
8545 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8546 crt = &connector->base;
8547 break;
8548 }
8549 }
8550
8551 if (!crt)
8552 return;
8553
8554 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8555 intel_release_load_detect_pipe(crt, &load_detect_temp);
8556
8557
8558 }
8559
8560 static bool
8561 intel_check_plane_mapping(struct intel_crtc *crtc)
8562 {
8563 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8564 u32 reg, val;
8565
8566 if (dev_priv->num_pipe == 1)
8567 return true;
8568
8569 reg = DSPCNTR(!crtc->plane);
8570 val = I915_READ(reg);
8571
8572 if ((val & DISPLAY_PLANE_ENABLE) &&
8573 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8574 return false;
8575
8576 return true;
8577 }
8578
8579 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8580 {
8581 struct drm_device *dev = crtc->base.dev;
8582 struct drm_i915_private *dev_priv = dev->dev_private;
8583 u32 reg;
8584
8585 /* Clear any frame start delays used for debugging left by the BIOS */
8586 reg = PIPECONF(crtc->cpu_transcoder);
8587 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8588
8589 /* We need to sanitize the plane -> pipe mapping first because this will
8590 * disable the crtc (and hence change the state) if it is wrong. Note
8591 * that gen4+ has a fixed plane -> pipe mapping. */
8592 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8593 struct intel_connector *connector;
8594 bool plane;
8595
8596 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8597 crtc->base.base.id);
8598
8599 /* Pipe has the wrong plane attached and the plane is active.
8600 * Temporarily change the plane mapping and disable everything
8601 * ... */
8602 plane = crtc->plane;
8603 crtc->plane = !plane;
8604 dev_priv->display.crtc_disable(&crtc->base);
8605 crtc->plane = plane;
8606
8607 /* ... and break all links. */
8608 list_for_each_entry(connector, &dev->mode_config.connector_list,
8609 base.head) {
8610 if (connector->encoder->base.crtc != &crtc->base)
8611 continue;
8612
8613 intel_connector_break_all_links(connector);
8614 }
8615
8616 WARN_ON(crtc->active);
8617 crtc->base.enabled = false;
8618 }
8619
8620 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8621 crtc->pipe == PIPE_A && !crtc->active) {
8622 /* BIOS forgot to enable pipe A, this mostly happens after
8623 * resume. Force-enable the pipe to fix this, the update_dpms
8624 * call below we restore the pipe to the right state, but leave
8625 * the required bits on. */
8626 intel_enable_pipe_a(dev);
8627 }
8628
8629 /* Adjust the state of the output pipe according to whether we
8630 * have active connectors/encoders. */
8631 intel_crtc_update_dpms(&crtc->base);
8632
8633 if (crtc->active != crtc->base.enabled) {
8634 struct intel_encoder *encoder;
8635
8636 /* This can happen either due to bugs in the get_hw_state
8637 * functions or because the pipe is force-enabled due to the
8638 * pipe A quirk. */
8639 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8640 crtc->base.base.id,
8641 crtc->base.enabled ? "enabled" : "disabled",
8642 crtc->active ? "enabled" : "disabled");
8643
8644 crtc->base.enabled = crtc->active;
8645
8646 /* Because we only establish the connector -> encoder ->
8647 * crtc links if something is active, this means the
8648 * crtc is now deactivated. Break the links. connector
8649 * -> encoder links are only establish when things are
8650 * actually up, hence no need to break them. */
8651 WARN_ON(crtc->active);
8652
8653 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8654 WARN_ON(encoder->connectors_active);
8655 encoder->base.crtc = NULL;
8656 }
8657 }
8658 }
8659
8660 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8661 {
8662 struct intel_connector *connector;
8663 struct drm_device *dev = encoder->base.dev;
8664
8665 /* We need to check both for a crtc link (meaning that the
8666 * encoder is active and trying to read from a pipe) and the
8667 * pipe itself being active. */
8668 bool has_active_crtc = encoder->base.crtc &&
8669 to_intel_crtc(encoder->base.crtc)->active;
8670
8671 if (encoder->connectors_active && !has_active_crtc) {
8672 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8673 encoder->base.base.id,
8674 drm_get_encoder_name(&encoder->base));
8675
8676 /* Connector is active, but has no active pipe. This is
8677 * fallout from our resume register restoring. Disable
8678 * the encoder manually again. */
8679 if (encoder->base.crtc) {
8680 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8681 encoder->base.base.id,
8682 drm_get_encoder_name(&encoder->base));
8683 encoder->disable(encoder);
8684 }
8685
8686 /* Inconsistent output/port/pipe state happens presumably due to
8687 * a bug in one of the get_hw_state functions. Or someplace else
8688 * in our code, like the register restore mess on resume. Clamp
8689 * things to off as a safer default. */
8690 list_for_each_entry(connector,
8691 &dev->mode_config.connector_list,
8692 base.head) {
8693 if (connector->encoder != encoder)
8694 continue;
8695
8696 intel_connector_break_all_links(connector);
8697 }
8698 }
8699 /* Enabled encoders without active connectors will be fixed in
8700 * the crtc fixup. */
8701 }
8702
8703 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8704 * and i915 state tracking structures. */
8705 void intel_modeset_setup_hw_state(struct drm_device *dev)
8706 {
8707 struct drm_i915_private *dev_priv = dev->dev_private;
8708 enum pipe pipe;
8709 u32 tmp;
8710 struct intel_crtc *crtc;
8711 struct intel_encoder *encoder;
8712 struct intel_connector *connector;
8713
8714 if (IS_HASWELL(dev)) {
8715 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8716
8717 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8718 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8719 case TRANS_DDI_EDP_INPUT_A_ON:
8720 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8721 pipe = PIPE_A;
8722 break;
8723 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8724 pipe = PIPE_B;
8725 break;
8726 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8727 pipe = PIPE_C;
8728 break;
8729 }
8730
8731 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8732 crtc->cpu_transcoder = TRANSCODER_EDP;
8733
8734 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8735 pipe_name(pipe));
8736 }
8737 }
8738
8739 for_each_pipe(pipe) {
8740 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8741
8742 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8743 if (tmp & PIPECONF_ENABLE)
8744 crtc->active = true;
8745 else
8746 crtc->active = false;
8747
8748 crtc->base.enabled = crtc->active;
8749
8750 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8751 crtc->base.base.id,
8752 crtc->active ? "enabled" : "disabled");
8753 }
8754
8755 if (IS_HASWELL(dev))
8756 intel_ddi_setup_hw_pll_state(dev);
8757
8758 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8759 base.head) {
8760 pipe = 0;
8761
8762 if (encoder->get_hw_state(encoder, &pipe)) {
8763 encoder->base.crtc =
8764 dev_priv->pipe_to_crtc_mapping[pipe];
8765 } else {
8766 encoder->base.crtc = NULL;
8767 }
8768
8769 encoder->connectors_active = false;
8770 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8771 encoder->base.base.id,
8772 drm_get_encoder_name(&encoder->base),
8773 encoder->base.crtc ? "enabled" : "disabled",
8774 pipe);
8775 }
8776
8777 list_for_each_entry(connector, &dev->mode_config.connector_list,
8778 base.head) {
8779 if (connector->get_hw_state(connector)) {
8780 connector->base.dpms = DRM_MODE_DPMS_ON;
8781 connector->encoder->connectors_active = true;
8782 connector->base.encoder = &connector->encoder->base;
8783 } else {
8784 connector->base.dpms = DRM_MODE_DPMS_OFF;
8785 connector->base.encoder = NULL;
8786 }
8787 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8788 connector->base.base.id,
8789 drm_get_connector_name(&connector->base),
8790 connector->base.encoder ? "enabled" : "disabled");
8791 }
8792
8793 /* HW state is read out, now we need to sanitize this mess. */
8794 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8795 base.head) {
8796 intel_sanitize_encoder(encoder);
8797 }
8798
8799 for_each_pipe(pipe) {
8800 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8801 intel_sanitize_crtc(crtc);
8802 }
8803
8804 intel_modeset_update_staged_output_state(dev);
8805
8806 intel_modeset_check_state(dev);
8807
8808 drm_mode_config_reset(dev);
8809 }
8810
8811 void intel_modeset_gem_init(struct drm_device *dev)
8812 {
8813 intel_modeset_init_hw(dev);
8814
8815 intel_setup_overlay(dev);
8816
8817 intel_modeset_setup_hw_state(dev);
8818 }
8819
8820 void intel_modeset_cleanup(struct drm_device *dev)
8821 {
8822 struct drm_i915_private *dev_priv = dev->dev_private;
8823 struct drm_crtc *crtc;
8824 struct intel_crtc *intel_crtc;
8825
8826 drm_kms_helper_poll_fini(dev);
8827 mutex_lock(&dev->struct_mutex);
8828
8829 intel_unregister_dsm_handler();
8830
8831
8832 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8833 /* Skip inactive CRTCs */
8834 if (!crtc->fb)
8835 continue;
8836
8837 intel_crtc = to_intel_crtc(crtc);
8838 intel_increase_pllclock(crtc);
8839 }
8840
8841 intel_disable_fbc(dev);
8842
8843 intel_disable_gt_powersave(dev);
8844
8845 ironlake_teardown_rc6(dev);
8846
8847 if (IS_VALLEYVIEW(dev))
8848 vlv_init_dpio(dev);
8849
8850 mutex_unlock(&dev->struct_mutex);
8851
8852 /* Disable the irq before mode object teardown, for the irq might
8853 * enqueue unpin/hotplug work. */
8854 drm_irq_uninstall(dev);
8855 cancel_work_sync(&dev_priv->hotplug_work);
8856 cancel_work_sync(&dev_priv->rps.work);
8857
8858 /* flush any delayed tasks or pending work */
8859 flush_scheduled_work();
8860
8861 drm_mode_config_cleanup(dev);
8862 }
8863
8864 /*
8865 * Return which encoder is currently attached for connector.
8866 */
8867 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8868 {
8869 return &intel_attached_encoder(connector)->base;
8870 }
8871
8872 void intel_connector_attach_encoder(struct intel_connector *connector,
8873 struct intel_encoder *encoder)
8874 {
8875 connector->encoder = encoder;
8876 drm_mode_connector_attach_encoder(&connector->base,
8877 &encoder->base);
8878 }
8879
8880 /*
8881 * set vga decode state - true == enable VGA decode
8882 */
8883 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8884 {
8885 struct drm_i915_private *dev_priv = dev->dev_private;
8886 u16 gmch_ctrl;
8887
8888 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8889 if (state)
8890 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8891 else
8892 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8893 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8894 return 0;
8895 }
8896
8897 #ifdef CONFIG_DEBUG_FS
8898 #include <linux/seq_file.h>
8899
8900 struct intel_display_error_state {
8901 struct intel_cursor_error_state {
8902 u32 control;
8903 u32 position;
8904 u32 base;
8905 u32 size;
8906 } cursor[I915_MAX_PIPES];
8907
8908 struct intel_pipe_error_state {
8909 u32 conf;
8910 u32 source;
8911
8912 u32 htotal;
8913 u32 hblank;
8914 u32 hsync;
8915 u32 vtotal;
8916 u32 vblank;
8917 u32 vsync;
8918 } pipe[I915_MAX_PIPES];
8919
8920 struct intel_plane_error_state {
8921 u32 control;
8922 u32 stride;
8923 u32 size;
8924 u32 pos;
8925 u32 addr;
8926 u32 surface;
8927 u32 tile_offset;
8928 } plane[I915_MAX_PIPES];
8929 };
8930
8931 struct intel_display_error_state *
8932 intel_display_capture_error_state(struct drm_device *dev)
8933 {
8934 drm_i915_private_t *dev_priv = dev->dev_private;
8935 struct intel_display_error_state *error;
8936 enum transcoder cpu_transcoder;
8937 int i;
8938
8939 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8940 if (error == NULL)
8941 return NULL;
8942
8943 for_each_pipe(i) {
8944 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8945
8946 error->cursor[i].control = I915_READ(CURCNTR(i));
8947 error->cursor[i].position = I915_READ(CURPOS(i));
8948 error->cursor[i].base = I915_READ(CURBASE(i));
8949
8950 error->plane[i].control = I915_READ(DSPCNTR(i));
8951 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8952 error->plane[i].size = I915_READ(DSPSIZE(i));
8953 error->plane[i].pos = I915_READ(DSPPOS(i));
8954 error->plane[i].addr = I915_READ(DSPADDR(i));
8955 if (INTEL_INFO(dev)->gen >= 4) {
8956 error->plane[i].surface = I915_READ(DSPSURF(i));
8957 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8958 }
8959
8960 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
8961 error->pipe[i].source = I915_READ(PIPESRC(i));
8962 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8963 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8964 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8965 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8966 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8967 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
8968 }
8969
8970 return error;
8971 }
8972
8973 void
8974 intel_display_print_error_state(struct seq_file *m,
8975 struct drm_device *dev,
8976 struct intel_display_error_state *error)
8977 {
8978 drm_i915_private_t *dev_priv = dev->dev_private;
8979 int i;
8980
8981 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8982 for_each_pipe(i) {
8983 seq_printf(m, "Pipe [%d]:\n", i);
8984 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8985 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8986 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8987 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8988 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8989 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8990 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8991 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8992
8993 seq_printf(m, "Plane [%d]:\n", i);
8994 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8995 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8996 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8997 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8998 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8999 if (INTEL_INFO(dev)->gen >= 4) {
9000 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9001 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9002 }
9003
9004 seq_printf(m, "Cursor [%d]:\n", i);
9005 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9006 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9007 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9008 }
9009 }
9010 #endif
Linux kernel - Deliverables
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